Update new repository name

was scanning PCI config space of all valid slot/bus combination when all needed information is already available from the initial scan.

BaS_codewarrior/firebeeV1/cfg/DDRAM.cfg

@@ -0,0 +1,57 @@
+; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture
+;        $RCSfile: M5475EVB.cfg,v $
+;        $Revision: 1.4 $   $Date: 2008/01/09 11:46:41 $
+; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file.
+
+ResetHalt
+
+;Set VBR - debugger must know this in order
+;   to do exception capture
+writecontrolreg 0x0801 0x00000000
+
+; If MBAR changes all following writes must change
+;   and if a memory configuration file is used,
+;   the reserved areas in the register block must
+;   change also.
+;Turn on MBAR at 0xFF00_0000
+writecontrolreg 0x0C0F 0xFF000000
+
+;Turn on RAMBAR0 at address FF10_0000 
+writecontrolreg 0x0C04 0xFF100035
+
+;Turn on RAMBAR1 at address FF10_1000 
+writecontrolreg 0x0C05 0xFF101035
+
+;Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
+writemem.l 0xFF000500 0xE0000000;
+writemem.l 0xFF000508 0x00101980;  16-bit port
+writemem.l 0xFF000504 0x007F0001;
+
+;SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
+writemem.l 0xFF000004 0x000002AA;   SDRAMDS configuration
+writemem.l 0xFF000020 0x0000001A;   SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
+writemem.l 0xFF000024 0x0800001A;   SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
+writemem.l 0xFF000028 0x1000001A;   SDRAM CS2 configuration (128Mbytes 1000_0000 - 07FF_FFFF)
+writemem.l 0xFF00002C 0x1800001A;   SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
+;writemem.l 0xFF000108 0x73611730;   SDCFG1
+writemem.l 0xFF000108 0x53611730;   SDCFG1
+;writemem.l 0xFF00010C 0x46770000;   SDCFG2
+writemem.l 0xFF00010C 0x24730000;   SDCFG2
+
+;writemem.l 0xFF000104 0xE10D0002;   SDCR + IPALL
+writemem.l 0xFF000104 0xE10F0002;   SDCR + IPALL
+writemem.l 0xFF000100 0x40010000;   SDMR (write to LEMR)
+;writemem.l 0xFF000100 0x048D0000;   SDMR (write to LMR)
+writemem.l 0xFF000100 0x04890000;   SDMR (write to LMR)
+;writemem.l 0xFF000104 0xE10D0002;   SDCR + IPALL
+writemem.l 0xFF000104 0xE10F0002;   SDCR + IPALL
+;writemem.l 0xFF000104 0xE10D0004;   SDCR + IREF (first refresh)
+writemem.l 0xFF000104 0xE10F0004;   SDCR + IREF (first refresh)
+;writemem.l 0xFF000104 0xE10D0004;   SDCR + IREF (second refresh)
+writemem.l 0xFF000104 0xE10F0004;   SDCR + IREF (first refresh)
+;writemem.l 0xFF000100 0x008D0000;   SDMR (write to LMR)
+writemem.l 0xFF000100 0x00890000;   SDMR (write to LMR)
+;writemem.l 0xFF000104 0x71100F00;   SDCR (lock SDMR and enable refresh)
+writemem.l 0xFF000104 0x71100F00;   SDCR (lock SDMR and enable refresh)
+
+delay 1000

BaS_codewarrior/firebeeV1/cfg/DDRAM.mem

@@ -0,0 +1,47 @@
+// Memory Configuration File
+//
+// Description:
+//  A memory configuration file contains commands that define the legally accessible
+//  areas of memory for your specific board. Useful for example when the debugger
+//  tries to display the content of a "char *" variable, that has not yet been initialized.
+//  In this case the debugger may try to read from a bogus address, which could cause a
+//  bus error.
+//
+// Board:
+//  LogicPD COLDARI1
+//
+// Reference:
+//  MCF5475RM.pdf
+
+
+// All reserved ranges read back 0xBABA...
+reservedchar 0xBA
+
+address 	MBAR_BASE 		0xFF000000 
+address 	MMUBAR_BASE 	0xFF040000
+
+usederivative "MCF5475"
+
+//         Memory Map:
+//         ----------------------------------------------------------------------
+range		0x00000000 			0x1FFFFFFF 				4 ReadWrite		// 512MB DDR SDRAM
+reserved	0x20000000 			0x5FFFFFFF
+
+range		0x60000000			0x7FFFFFFF				4 ReadWrite
+
+range		0x80000000			0xCFFFFFFF				4 ReadWrite			
+
+range		0xD0000000			0xFBFFFFFF				4 ReadWrite
+			
+reserved	0xFC000000			$MBAR_BASE-1			
+
+ 			$MBAR_BASE 			$MBAR_BASE+0x3FFFF						// Memory Mapped Registers
+range		$MBAR_BASE+0x10000	$MBAR_BASE+0x17FFC		4 ReadWrite		// 32K Internal SRAM
+
+range		$MMUBAR_BASE		$MMUBAR_BASE+0xFFFF
+reserved	$MMUBAR_BASE+1x0000	0xFF0FFFFF	     						// Added to fill gap in MMR
+
+range      	0xFF100000 			0xFF100FFF 				4 ReadWrite		// 4K SRAM0 (RAMBAR0)
+range      	0xFF101000 			0xFFFFFFFF 				4 ReadWrite		// 4K SRAM1 (RAMBAR1)
+
+

BaS_codewarrior/firebeeV1/cfg/flash.cfg

@@ -0,0 +1,11 @@
+; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture
+;        $RCSfile: M5475EVB.cfg,v $
+;        $Revision: 1.4 $   $Date: 2008/01/09 11:46:41 $
+; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file.
+
+
+;Init CS0 (BootFLASH @ FE00_0000 - FE7F_FFFF 8Mbytes)
+writemem.l 0xFF000500 0xFE000000;
+writemem.l 0xFF000508 0x00101980;  16-bit port
+writemem.l 0xFF000504 0x007F0001;
+

BaS_codewarrior/firebeeV1/cfg/mem.cfg

@@ -0,0 +1,48 @@
+; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture
+;        $RCSfile: M5475EVB.cfg,v $
+;        $Revision: 1.4 $   $Date: 2008/01/09 11:46:41 $
+; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file.
+
+ResetHalt
+
+;Set VBR - debugger must know this in order
+;   to do exception capture
+writecontrolreg 0x0801 0x00000000
+
+; If MBAR changes all following writes must change
+;   and if a memory configuration file is used,
+;   the reserved areas in the register block must
+;   change also.
+;Turn on MBAR at 0xFF00_0000
+writecontrolreg 0x0C0F 0xFF000000
+
+;Turn on RAMBAR0 at address FF10_0000 
+writecontrolreg 0x0C04 0xFF100035
+
+;Turn on RAMBAR1 at address FF10_1000 
+writecontrolreg 0x0C05 0xFF101035
+
+;Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
+writemem.l 0xFF000500 0xE0000000;
+writemem.l 0xFF000508 0x00001180;  16-bit port
+writemem.l 0xFF000504 0x007F0001;
+
+;SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
+writemem.l 0xFF000004 0x000002AA;   SDRAMDS configuration
+writemem.l 0xFF000020 0x0000001A;   SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
+writemem.l 0xFF000024 0x0800001A;   SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
+writemem.l 0xFF000028 0x1000001A;   SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
+writemem.l 0xFF00002C 0x1800001A;   SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
+writemem.l 0xFF000108 0x53722938;   SDCFG1
+writemem.l 0xFF00010C 0x24330000;   SDCFG2
+
+writemem.l 0xFF000104 0xE10F0002;   SDCR + IPALL
+writemem.l 0xFF000100 0x40010000;   SDMR (write to LEMR)
+writemem.l 0xFF000100 0x05890000;   SDRM (write to LMR)
+writemem.l 0xFF000104 0xE10F0002;   SDCR + IPALL
+writemem.l 0xFF000104 0xE10F0004;   SDCR + IREF (first refresh)
+writemem.l 0xFF000104 0xE10F0004;   SDCR + IREF (second refresh)
+writemem.l 0xFF000100 0x01890000;   SDMR (write to LMR)
+writemem.l 0xFF000104 0x710F0F00;   SDCR (lock SDMR and enable refresh)
+
+delay 1000

BaS_codewarrior/firebeeV1/cfg/mem.mem

@@ -0,0 +1,38 @@
+// Memory Configuration File
+//
+// Description:
+//  A memory configuration file contains commands that define the legally accessible
+//  areas of memory for your specific board. Useful for example when the debugger
+//  tries to display the content of a "char *" variable, that has not yet been initialized.
+//  In this case the debugger may try to read from a bogus address, which could cause a
+//  bus error.
+//
+// Board:
+//  LogicPD COLDARI1
+//
+// Reference:
+//  MCF5475RM.pdf
+
+
+// All reserved ranges read back 0xBABA...
+reservedchar 0xBA
+
+address 	MBAR_BASE 		0xFF000000 
+address 	MMUBAR_BASE 	0xFF040000
+
+usederivative "MCF5475"
+
+//         Memory Map:
+//         ----------------------------------------------------------------------
+range		0x00000000 			0x1FFFFFFF 				4 ReadWrite		// 512MB DDR SDRAM
+reserved	0x20000000 			$MBAR_BASE-1
+
+  			$MBAR_BASE 			$MBAR_BASE+0x3FFFF		4 ReadWrite		// Memory Mapped Registers
+range		$MBAR_BASE+0x10000	$MBAR_BASE+0x17FFC		4 ReadWrite		// 32K Internal SRAM
+reserved	$MBAR_BASE+0x17FFD	$MBAR_BASE+0x1FFBF
+
+ 			$MMUBAR_BASE		$MMUBAR_BASE+0x001B
+reserved	$MMUBAR_BASE+0x001C 0xFF0FFFFF				
+
+range      	0xFF100000 			0xFF100FFF 				4 ReadWrite		// 4K SRAM0 (RAMBAR0)
+range      	0xFF101000 			0xFF101FFF 				4 ReadWrite		// 4K SRAM1 (RAMBAR1)

BaS_codewarrior/firebeeV1/flash_config.xml

@@ -0,0 +1,47 @@
+<?xml version="1.0" encoding="iso-8859-1" standalone="no" ?>
+<fpconfig>
+
+  <targetconfwindow>
+    <usecustomsettings>true</usecustomsettings>
+    <targetprocessor>5474</targetprocessor>
+    <connection>PEMICRO_USB</connection>
+    <usetargetinit>true</usetargetinit>
+    <targetinitfile>C:\FireBee\codewarrior\firebeeV1\cfg\mem.cfg</targetinitfile>
+    <targetmembuffaddr>0x00000000</targetmembuffaddr>
+    <targetmembuffsize>0x00006000</targetmembuffsize>
+    <enablelogging>true</enablelogging>
+    <verifywrites>false</verifywrites>
+  </targetconfwindow>
+
+  <flashconfwindow>
+    <membaseaddr>0xE0000000</membaseaddr>
+    <device>M29W640DB</device>
+    <organization>4Mx16x1</organization>
+    <flashstart>0xE0000000</flashstart>
+    <flashend>0xE07FFFFF</flashend>
+  </flashconfwindow>
+
+  <programverifywindow>
+    <useselectedfile>true</useselectedfile>
+    <projbuildtargetfile>C:\FireBee\codewarrior\firebeeV1\bin\FLASH.elf.S19</projbuildtargetfile>
+    <fileiotype>Auto Detect</fileiotype>
+    <restrictaddrrange>false</restrictaddrrange>
+    <restrictaddrrangestart>0xFF800000</restrictaddrrangestart>
+    <restrictaddrrangeend>0xFFFFFFFF</restrictaddrrangeend>
+    <applyaddroffset>false</applyaddroffset>
+    <addroffset>0xC0200000</addroffset>
+  </programverifywindow>
+
+  <eraseblankcheckwindow>
+    <eraseallsectors>false</eraseallsectors>
+    <sector/>
+    <processsectorsindividually>false</processsectorsindividually>
+  </eraseblankcheckwindow>
+
+  <checksumwindow>
+    <computechecksumover>FileOnTarg</computechecksumover>
+    <addrstart>0xFF800000</addrstart>
+    <addrsize>0x007FFFFF</addrsize>
+  </checksumwindow>
+
+</fpconfig>

BaS_codewarrior/firebeeV1/hardware_diagnostic.xml

@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="iso-8859-1" standalone="no" ?>
+<configsettings>
+
+  <confwindow>
+    <usecustomsettings>true</usecustomsettings>
+    <targetprocessor>5474</targetprocessor>
+    <connection>PEMICRO_USB</connection>
+    <usetargetinit>true</usetargetinit>
+    <targetinitfile>{CodeWarrior}\ColdFire_Support\Initialization_Files\MCF5475.cfg</targetinitfile>
+  </confwindow>
+
+  <memoryreadwritewindow>
+    <accesstype>read</accesstype>
+    <accesssize>long_word</accesssize>
+    <targetaddress>0x60001000</targetaddress>
+    <valuetowrite>FFFFFFFF</valuetowrite>
+  </memoryreadwritewindow>
+
+  <scopelooptestwindow>
+    <accesstype>read</accesstype>
+    <accesssize>long_word</accesssize>
+    <targetaddress>0x00100000</targetaddress>
+    <valuetowrite>0x67</valuetowrite>
+    <speed>1000</speed>
+  </scopelooptestwindow>
+
+  <memorytestswindow>
+    <runwalking1s>true</runwalking1s>
+    <runbusnoise>true</runbusnoise>
+    <runaddress>true</runaddress>
+    <startaddress>0x00DE1000</startaddress>
+    <endaddress>0x00DE11FF</endaddress>
+    <accesssize>long_word</accesssize>
+    <passes>1</passes>
+    <usetargetcpu>false</usetargetcpu>
+    <targetscratchmemstart>0x00000100</targetscratchmemstart>
+    <targetscratchmemend>0x0000FFFF</targetscratchmemend>
+  </memorytestswindow>
+
+</configsettings>

BaS_codewarrior/firebeeV1/headers/MCF5475.h

@@ -0,0 +1,93 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_H__
+#define __MCF5475_H__
+
+
+/********************************************************************/
+/*
+ * The basic data types
+ */
+
+typedef unsigned char           uint8;   /*  8 bits */
+typedef unsigned short int      uint16;  /* 16 bits */
+typedef unsigned long int       uint32;  /* 32 bits */
+
+typedef signed char             int8;    /*  8 bits */
+typedef signed short int        int16;   /* 16 bits */
+typedef signed long int         int32;   /* 32 bits */
+
+typedef volatile uint8          vuint8;  /*  8 bits */
+typedef volatile uint16         vuint16; /* 16 bits */
+typedef volatile uint32         vuint32; /* 32 bits */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#pragma define_section system ".system" far_absolute RW
+
+/***
+ * MCF5475 Derivative Memory map definitions from linker command files:
+ * __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
+ * linker symbols must be defined in the linker command file.
+ */
+
+extern __declspec(system) uint8 __MBAR[];
+extern __declspec(system) uint8 __MMUBAR[];
+extern __declspec(system) uint8 __RAMBAR0[];
+extern __declspec(system) uint8 __RAMBAR0_SIZE[];
+extern __declspec(system) uint8 __RAMBAR1[];
+extern __declspec(system) uint8 __RAMBAR1_SIZE[];
+
+#define MBAR_ADDRESS    (uint32)__MBAR
+#define MMUBAR_ADDRESS  (uint32)__MMUBAR
+#define RAMBAR0_ADDRESS (uint32)__RAMBAR0
+#define RAMBAR0_SIZE    (uint32)__RAMBAR0_SIZE
+#define RAMBAR1_ADDRESS (uint32)__RAMBAR1
+#define RAMBAR1_SIZE    (uint32)__RAMBAR1_SIZE
+
+
+#include "MCF5475_SIU.h"
+#include "MCF5475_MMU.h"
+#include "MCF5475_SDRAMC.h"
+#include "MCF5475_XLB.h"
+#include "MCF5475_CLOCK.h"
+#include "MCF5475_FBCS.h"
+#include "MCF5475_INTC.h"
+#include "MCF5475_GPT.h"
+#include "MCF5475_SLT.h"
+#include "MCF5475_GPIO.h"
+#include "MCF5475_PAD.h"
+#include "MCF5475_PCI.h"
+#include "MCF5475_PCIARB.h"
+#include "MCF5475_EPORT.h"
+#include "MCF5475_CTM.h"
+#include "MCF5475_DMA.h"
+#include "MCF5475_PSC.h"
+#include "MCF5475_DSPI.h"
+#include "MCF5475_I2C.h"
+#include "MCF5475_FEC.h"
+#include "MCF5475_USB.h"
+#include "MCF5475_SRAM.h"
+#include "MCF5475_SEC.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __MCF5475_H__ */

BaS_codewarrior/firebeeV1/headers/MCF5475_CLOCK.h

@@ -0,0 +1,47 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_CLOCK_H__
+#define __MCF5475_CLOCK_H__
+
+
+/*********************************************************************
+*
+* Clock Module (CLOCK)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CLOCK_SPCR                       (*(vuint32*)(&__MBAR[0x300]))
+
+
+/* Bit definitions and macros for MCF_CLOCK_SPCR */
+#define MCF_CLOCK_SPCR_MEMEN                 (0x1)
+#define MCF_CLOCK_SPCR_PCIEN                 (0x2)
+#define MCF_CLOCK_SPCR_FBEN                  (0x4)
+#define MCF_CLOCK_SPCR_CAN0EN                (0x8)
+#define MCF_CLOCK_SPCR_DMAEN                 (0x10)
+#define MCF_CLOCK_SPCR_FEC0EN                (0x20)
+#define MCF_CLOCK_SPCR_FEC1EN                (0x40)
+#define MCF_CLOCK_SPCR_USBEN                 (0x80)
+#define MCF_CLOCK_SPCR_PSCEN                 (0x200)
+#define MCF_CLOCK_SPCR_CAN1EN                (0x800)
+#define MCF_CLOCK_SPCR_CRYENA                (0x1000)
+#define MCF_CLOCK_SPCR_CRYENB                (0x2000)
+#define MCF_CLOCK_SPCR_COREN                 (0x4000)
+#define MCF_CLOCK_SPCR_PLLK                  (0x80000000)
+
+
+#endif /* __MCF5475_CLOCK_H__ */

BaS_codewarrior/firebeeV1/headers/MCF5475_CTM.h

@@ -0,0 +1,76 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_CTM_H__
+#define __MCF5475_CTM_H__
+
+
+/*********************************************************************
+*
+* Comm Timer Module (CTM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CTM_CTCR0                        (*(vuint32*)(&__MBAR[0x7F00]))
+#define MCF_CTM_CTCR1                        (*(vuint32*)(&__MBAR[0x7F04]))
+#define MCF_CTM_CTCR2                        (*(vuint32*)(&__MBAR[0x7F08]))
+#define MCF_CTM_CTCR3                        (*(vuint32*)(&__MBAR[0x7F0C]))
+#define MCF_CTM_CTCR4                        (*(vuint32*)(&__MBAR[0x7F10]))
+#define MCF_CTM_CTCR5                        (*(vuint32*)(&__MBAR[0x7F14]))
+#define MCF_CTM_CTCR6                        (*(vuint32*)(&__MBAR[0x7F18]))
+#define MCF_CTM_CTCR7                        (*(vuint32*)(&__MBAR[0x7F1C]))
+#define MCF_CTM_CTCRF(x)                     (*(vuint32*)(&__MBAR[0x7F00 + ((x)*0x4)]))
+#define MCF_CTM_CTCRV(x)                     (*(vuint32*)(&__MBAR[0x7F10 + ((x-4)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_CTM_CTCRF */
+#define MCF_CTM_CTCRF_CRV(x)                 (((x)&0xFFFF)<<0)
+#define MCF_CTM_CTCRF_S(x)                   (((x)&0xF)<<0x10)
+#define MCF_CTM_CTCRF_S_CLK_1                (0)
+#define MCF_CTM_CTCRF_S_CLK_2                (0x10000)
+#define MCF_CTM_CTCRF_S_CLK_4                (0x20000)
+#define MCF_CTM_CTCRF_S_CLK_8                (0x30000)
+#define MCF_CTM_CTCRF_S_CLK_16               (0x40000)
+#define MCF_CTM_CTCRF_S_CLK_32               (0x50000)
+#define MCF_CTM_CTCRF_S_CLK_64               (0x60000)
+#define MCF_CTM_CTCRF_S_CLK_128              (0x70000)
+#define MCF_CTM_CTCRF_S_CLK_256              (0x80000)
+#define MCF_CTM_CTCRF_S_CLK_EXT              (0x90000)
+#define MCF_CTM_CTCRF_PCT(x)                 (((x)&0x7)<<0x14)
+#define MCF_CTM_CTCRF_PCT_100                (0)
+#define MCF_CTM_CTCRF_PCT_50                 (0x100000)
+#define MCF_CTM_CTCRF_PCT_25                 (0x200000)
+#define MCF_CTM_CTCRF_PCT_12p5               (0x300000)
+#define MCF_CTM_CTCRF_PCT_6p25               (0x400000)
+#define MCF_CTM_CTCRF_PCT_OFF                (0x500000)
+#define MCF_CTM_CTCRF_M                      (0x800000)
+#define MCF_CTM_CTCRF_IM                     (0x1000000)
+#define MCF_CTM_CTCRF_I                      (0x80000000)
+
+/* Bit definitions and macros for MCF_CTM_CTCRV */
+#define MCF_CTM_CTCRV_CRV(x)                 (((x)&0xFFFFFF)<<0)
+#define MCF_CTM_CTCRV_PCT(x)                 (((x)&0x7)<<0x18)
+#define MCF_CTM_CTCRV_PCT_100                (0)
+#define MCF_CTM_CTCRV_PCT_50                 (0x1000000)
+#define MCF_CTM_CTCRV_PCT_25                 (0x2000000)
+#define MCF_CTM_CTCRV_PCT_12p5               (0x3000000)
+#define MCF_CTM_CTCRV_PCT_6p25               (0x4000000)
+#define MCF_CTM_CTCRV_PCT_OFF                (0x5000000)
+#define MCF_CTM_CTCRV_M                      (0x8000000)
+#define MCF_CTM_CTCRV_S                      (0x10000000)
+
+
+#endif /* __MCF5475_CTM_H__ */

BaS_codewarrior/firebeeV1/headers/MCF5475_DMA.h

@@ -0,0 +1,202 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_DMA_H__
+#define __MCF5475_DMA_H__
+
+
+/*********************************************************************
+*
+* Multichannel DMA (DMA)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_DMA_TASKBAR                      (*(vuint32*)(&__MBAR[0x8000]))
+#define MCF_DMA_CP                           (*(vuint32*)(&__MBAR[0x8004]))
+#define MCF_DMA_EP                           (*(vuint32*)(&__MBAR[0x8008]))
+#define MCF_DMA_VP                           (*(vuint32*)(&__MBAR[0x800C]))
+#define MCF_DMA_PTD                          (*(vuint32*)(&__MBAR[0x8010]))
+#define MCF_DMA_DIPR                         (*(vuint32*)(&__MBAR[0x8014]))
+#define MCF_DMA_DIMR                         (*(vuint32*)(&__MBAR[0x8018]))
+#define MCF_DMA_TCR0                         (*(vuint16*)(&__MBAR[0x801C]))
+#define MCF_DMA_TCR1                         (*(vuint16*)(&__MBAR[0x801E]))
+#define MCF_DMA_TCR2                         (*(vuint16*)(&__MBAR[0x8020]))
+#define MCF_DMA_TCR3                         (*(vuint16*)(&__MBAR[0x8022]))
+#define MCF_DMA_TCR4                         (*(vuint16*)(&__MBAR[0x8024]))
+#define MCF_DMA_TCR5                         (*(vuint16*)(&__MBAR[0x8026]))
+#define MCF_DMA_TCR6                         (*(vuint16*)(&__MBAR[0x8028]))
+#define MCF_DMA_TCR7                         (*(vuint16*)(&__MBAR[0x802A]))
+#define MCF_DMA_TCR8                         (*(vuint16*)(&__MBAR[0x802C]))
+#define MCF_DMA_TCR9                         (*(vuint16*)(&__MBAR[0x802E]))
+#define MCF_DMA_TCR10                        (*(vuint16*)(&__MBAR[0x8030]))
+#define MCF_DMA_TCR11                        (*(vuint16*)(&__MBAR[0x8032]))
+#define MCF_DMA_TCR12                        (*(vuint16*)(&__MBAR[0x8034]))
+#define MCF_DMA_TCR13                        (*(vuint16*)(&__MBAR[0x8036]))
+#define MCF_DMA_TCR14                        (*(vuint16*)(&__MBAR[0x8038]))
+#define MCF_DMA_TCR15                        (*(vuint16*)(&__MBAR[0x803A]))
+#define MCF_DMA_PRIOR0                       (*(vuint8 *)(&__MBAR[0x803C]))
+#define MCF_DMA_PRIOR1                       (*(vuint8 *)(&__MBAR[0x803D]))
+#define MCF_DMA_PRIOR2                       (*(vuint8 *)(&__MBAR[0x803E]))
+#define MCF_DMA_PRIOR3                       (*(vuint8 *)(&__MBAR[0x803F]))
+#define MCF_DMA_PRIOR4                       (*(vuint8 *)(&__MBAR[0x8040]))
+#define MCF_DMA_PRIOR5                       (*(vuint8 *)(&__MBAR[0x8041]))
+#define MCF_DMA_PRIOR6                       (*(vuint8 *)(&__MBAR[0x8042]))
+#define MCF_DMA_PRIOR7                       (*(vuint8 *)(&__MBAR[0x8043]))
+#define MCF_DMA_PRIOR8                       (*(vuint8 *)(&__MBAR[0x8044]))
+#define MCF_DMA_PRIOR9                       (*(vuint8 *)(&__MBAR[0x8045]))
+#define MCF_DMA_PRIOR10                      (*(vuint8 *)(&__MBAR[0x8046]))
+#define MCF_DMA_PRIOR11                      (*(vuint8 *)(&__MBAR[0x8047]))
+#define MCF_DMA_PRIOR12                      (*(vuint8 *)(&__MBAR[0x8048]))
+#define MCF_DMA_PRIOR13                      (*(vuint8 *)(&__MBAR[0x8049]))
+#define MCF_DMA_PRIOR14                      (*(vuint8 *)(&__MBAR[0x804A]))
+#define MCF_DMA_PRIOR15                      (*(vuint8 *)(&__MBAR[0x804B]))
+#define MCF_DMA_PRIOR16                      (*(vuint8 *)(&__MBAR[0x804C]))
+#define MCF_DMA_PRIOR17                      (*(vuint8 *)(&__MBAR[0x804D]))
+#define MCF_DMA_PRIOR18                      (*(vuint8 *)(&__MBAR[0x804E]))
+#define MCF_DMA_PRIOR19                      (*(vuint8 *)(&__MBAR[0x804F]))
+#define MCF_DMA_PRIOR20                      (*(vuint8 *)(&__MBAR[0x8050]))
+#define MCF_DMA_PRIOR21                      (*(vuint8 *)(&__MBAR[0x8051]))
+#define MCF_DMA_PRIOR22                      (*(vuint8 *)(&__MBAR[0x8052]))
+#define MCF_DMA_PRIOR23                      (*(vuint8 *)(&__MBAR[0x8053]))
+#define MCF_DMA_PRIOR24                      (*(vuint8 *)(&__MBAR[0x8054]))
+#define MCF_DMA_PRIOR25                      (*(vuint8 *)(&__MBAR[0x8055]))
+#define MCF_DMA_PRIOR26                      (*(vuint8 *)(&__MBAR[0x8056]))
+#define MCF_DMA_PRIOR27                      (*(vuint8 *)(&__MBAR[0x8057]))
+#define MCF_DMA_PRIOR28                      (*(vuint8 *)(&__MBAR[0x8058]))
+#define MCF_DMA_PRIOR29                      (*(vuint8 *)(&__MBAR[0x8059]))
+#define MCF_DMA_PRIOR30                      (*(vuint8 *)(&__MBAR[0x805A]))
+#define MCF_DMA_PRIOR31                      (*(vuint8 *)(&__MBAR[0x805B]))
+#define MCF_DMA_IMCR                         (*(vuint32*)(&__MBAR[0x805C]))
+#define MCF_DMA_TSKSZ0                       (*(vuint32*)(&__MBAR[0x8060]))
+#define MCF_DMA_TSKSZ1                       (*(vuint32*)(&__MBAR[0x8064]))
+#define MCF_DMA_DBGCOMP0                     (*(vuint32*)(&__MBAR[0x8070]))
+#define MCF_DMA_DBGCOMP2                     (*(vuint32*)(&__MBAR[0x8074]))
+#define MCF_DMA_DBGCTL                       (*(vuint32*)(&__MBAR[0x8078]))
+#define MCF_DMA_TCR(x)                       (*(vuint16*)(&__MBAR[0x801C + ((x)*0x2)]))
+#define MCF_DMA_PRIOR(x)                     (*(vuint8 *)(&__MBAR[0x803C + ((x)*0x1)]))
+
+
+/* Bit definitions and macros for MCF_DMA_TASKBAR */
+#define MCF_DMA_TASKBAR_TASK_BASE_ADDRESS(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_CP */
+#define MCF_DMA_CP_DESCRIPTOR_POINTER(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_EP */
+#define MCF_DMA_EP_DESCRIPTOR_POINTER(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_VP */
+#define MCF_DMA_VP_VARIABLE_POINTER(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_PTD */
+#define MCF_DMA_PTD_PCTL0                    (0x1)
+#define MCF_DMA_PTD_PCTL1                    (0x2)
+#define MCF_DMA_PTD_PCTL13                   (0x2000)
+#define MCF_DMA_PTD_PCTL14                   (0x4000)
+#define MCF_DMA_PTD_PCTL15                   (0x8000)
+
+/* Bit definitions and macros for MCF_DMA_DIPR */
+#define MCF_DMA_DIPR_TASK(x)                 (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DIMR */
+#define MCF_DMA_DIMR_TASK(x)                 (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_TCR */
+#define MCF_DMA_TCR_ASTSKNUM(x)              (((x)&0xF)<<0)
+#define MCF_DMA_TCR_HLDINITNUM               (0x20)
+#define MCF_DMA_TCR_HIPRITSKEN               (0x40)
+#define MCF_DMA_TCR_ASTRT                    (0x80)
+#define MCF_DMA_TCR_INITNUM(x)               (((x)&0x1F)<<0x8)
+#define MCF_DMA_TCR_ALWINIT                  (0x2000)
+#define MCF_DMA_TCR_V                        (0x4000)
+#define MCF_DMA_TCR_EN                       (0x8000)
+
+/* Bit definitions and macros for MCF_DMA_PRIOR */
+#define MCF_DMA_PRIOR_PRI(x)                 (((x)&0x7)<<0)
+#define MCF_DMA_PRIOR_HLD                    (0x80)
+
+/* Bit definitions and macros for MCF_DMA_IMCR */
+#define MCF_DMA_IMCR_IMC0(x)                 (((x)&0x3)<<0)
+#define MCF_DMA_IMCR_IMC1(x)                 (((x)&0x3)<<0x2)
+#define MCF_DMA_IMCR_IMC2(x)                 (((x)&0x3)<<0x4)
+#define MCF_DMA_IMCR_IMC3(x)                 (((x)&0x3)<<0x6)
+#define MCF_DMA_IMCR_IMC4(x)                 (((x)&0x3)<<0x8)
+#define MCF_DMA_IMCR_IMC5(x)                 (((x)&0x3)<<0xA)
+#define MCF_DMA_IMCR_IMC6(x)                 (((x)&0x3)<<0xC)
+#define MCF_DMA_IMCR_IMC7(x)                 (((x)&0x3)<<0xE)
+#define MCF_DMA_IMCR_IMC8(x)                 (((x)&0x3)<<0x10)
+#define MCF_DMA_IMCR_IMC9(x)                 (((x)&0x3)<<0x12)
+#define MCF_DMA_IMCR_IMC10(x)                (((x)&0x3)<<0x14)
+#define MCF_DMA_IMCR_IMC11(x)                (((x)&0x3)<<0x16)
+#define MCF_DMA_IMCR_IMC12(x)                (((x)&0x3)<<0x18)
+#define MCF_DMA_IMCR_IMC13(x)                (((x)&0x3)<<0x1A)
+#define MCF_DMA_IMCR_IMC14(x)                (((x)&0x3)<<0x1C)
+#define MCF_DMA_IMCR_IMC15(x)                (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_DMA_TSKSZ0 */
+#define MCF_DMA_TSKSZ0_DSTSZ7(x)             (((x)&0x3)<<0)
+#define MCF_DMA_TSKSZ0_SRCSZ7(x)             (((x)&0x3)<<0x2)
+#define MCF_DMA_TSKSZ0_DSTSZ6(x)             (((x)&0x3)<<0x4)
+#define MCF_DMA_TSKSZ0_SRCSZ6(x)             (((x)&0x3)<<0x6)
+#define MCF_DMA_TSKSZ0_DSTSZ5(x)             (((x)&0x3)<<0x8)
+#define MCF_DMA_TSKSZ0_SRCSZ5(x)             (((x)&0x3)<<0xA)
+#define MCF_DMA_TSKSZ0_DSTSZ4(x)             (((x)&0x3)<<0xC)
+#define MCF_DMA_TSKSZ0_SRCSZ4(x)             (((x)&0x3)<<0xE)
+#define MCF_DMA_TSKSZ0_DSTSZ3(x)             (((x)&0x3)<<0x10)
+#define MCF_DMA_TSKSZ0_SRCSZ3(x)             (((x)&0x3)<<0x12)
+#define MCF_DMA_TSKSZ0_DSTSZ2(x)             (((x)&0x3)<<0x14)
+#define MCF_DMA_TSKSZ0_SRCSZ2(x)             (((x)&0x3)<<0x16)
+#define MCF_DMA_TSKSZ0_DSTSZ1(x)             (((x)&0x3)<<0x18)
+#define MCF_DMA_TSKSZ0_SRCSZ1(x)             (((x)&0x3)<<0x1A)
+#define MCF_DMA_TSKSZ0_DSTSZ0(x)             (((x)&0x3)<<0x1C)
+#define MCF_DMA_TSKSZ0_SRCSZ0(x)             (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_DMA_TSKSZ1 */
+#define MCF_DMA_TSKSZ1_DSTSZ15(x)            (((x)&0x3)<<0)
+#define MCF_DMA_TSKSZ1_SRCSZ15(x)            (((x)&0x3)<<0x2)
+#define MCF_DMA_TSKSZ1_DSTSZ14(x)            (((x)&0x3)<<0x4)
+#define MCF_DMA_TSKSZ1_SRCSZ14(x)            (((x)&0x3)<<0x6)
+#define MCF_DMA_TSKSZ1_DSTSZ13(x)            (((x)&0x3)<<0x8)
+#define MCF_DMA_TSKSZ1_SRCSZ13(x)            (((x)&0x3)<<0xA)
+#define MCF_DMA_TSKSZ1_DSTSZ12(x)            (((x)&0x3)<<0xC)
+#define MCF_DMA_TSKSZ1_SRCSZ12(x)            (((x)&0x3)<<0xE)
+#define MCF_DMA_TSKSZ1_DSTSZ11(x)            (((x)&0x3)<<0x10)
+#define MCF_DMA_TSKSZ1_SRCSZ11(x)            (((x)&0x3)<<0x12)
+#define MCF_DMA_TSKSZ1_DSTSZ10(x)            (((x)&0x3)<<0x14)
+#define MCF_DMA_TSKSZ1_SRCSZ10(x)            (((x)&0x3)<<0x16)
+#define MCF_DMA_TSKSZ1_DSTSZ9(x)             (((x)&0x3)<<0x18)
+#define MCF_DMA_TSKSZ1_SRCSZ9(x)             (((x)&0x3)<<0x1A)
+#define MCF_DMA_TSKSZ1_DSTSZ8(x)             (((x)&0x3)<<0x1C)
+#define MCF_DMA_TSKSZ1_SRCSZ8(x)             (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_DMA_DBGCOMP0 */
+#define MCF_DMA_DBGCOMP0_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DBGCOMP2 */
+#define MCF_DMA_DBGCOMP2_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DBGCTL */
+#define MCF_DMA_DBGCTL_I                     (0x2)
+#define MCF_DMA_DBGCTL_E                     (0x4)
+#define MCF_DMA_DBGCTL_AND_OR                (0x80)
+#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_2(x)  (((x)&0x7)<<0x8)
+#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_1(x)  (((x)&0x7)<<0xB)
+#define MCF_DMA_DBGCTL_B                     (0x4000)
+#define MCF_DMA_DBGCTL_AA                    (0x8000)
+#define MCF_DMA_DBGCTL_BLOCK_TASKS(x)        (((x)&0xFFFF)<<0x10)
+
+
+#endif /* __MCF5475_DMA_H__ */

BaS_codewarrior/firebeeV1/headers/MCF5475_DSPI.h

@@ -0,0 +1,150 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_DSPI_H__
+#define __MCF5475_DSPI_H__
+
+
+/*********************************************************************
+*
+* DMA Serial Peripheral Interface (DSPI)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_DSPI_DMCR                        (*(vuint32*)(&__MBAR[0x8A00]))
+#define MCF_DSPI_DTCR                        (*(vuint32*)(&__MBAR[0x8A08]))
+#define MCF_DSPI_DCTAR0                      (*(vuint32*)(&__MBAR[0x8A0C]))
+#define MCF_DSPI_DCTAR1                      (*(vuint32*)(&__MBAR[0x8A10]))
+#define MCF_DSPI_DCTAR2                      (*(vuint32*)(&__MBAR[0x8A14]))
+#define MCF_DSPI_DCTAR3                      (*(vuint32*)(&__MBAR[0x8A18]))
+#define MCF_DSPI_DCTAR4                      (*(vuint32*)(&__MBAR[0x8A1C]))
+#define MCF_DSPI_DCTAR5                      (*(vuint32*)(&__MBAR[0x8A20]))
+#define MCF_DSPI_DCTAR6                      (*(vuint32*)(&__MBAR[0x8A24]))
+#define MCF_DSPI_DCTAR7                      (*(vuint32*)(&__MBAR[0x8A28]))
+#define MCF_DSPI_DSR                         (*(vuint32*)(&__MBAR[0x8A2C]))
+#define MCF_DSPI_DIRSR                       (*(vuint32*)(&__MBAR[0x8A30]))
+#define MCF_DSPI_DTFR                        (*(vuint32*)(&__MBAR[0x8A34]))
+#define MCF_DSPI_DRFR                        (*(vuint32*)(&__MBAR[0x8A38]))
+#define MCF_DSPI_DTFDR0                      (*(vuint32*)(&__MBAR[0x8A3C]))
+#define MCF_DSPI_DTFDR1                      (*(vuint32*)(&__MBAR[0x8A40]))
+#define MCF_DSPI_DTFDR2                      (*(vuint32*)(&__MBAR[0x8A44]))
+#define MCF_DSPI_DTFDR3                      (*(vuint32*)(&__MBAR[0x8A48]))
+#define MCF_DSPI_DRFDR0                      (*(vuint32*)(&__MBAR[0x8A7C]))
+#define MCF_DSPI_DRFDR1                      (*(vuint32*)(&__MBAR[0x8A80]))
+#define MCF_DSPI_DRFDR2                      (*(vuint32*)(&__MBAR[0x8A84]))
+#define MCF_DSPI_DRFDR3                      (*(vuint32*)(&__MBAR[0x8A88]))
+#define MCF_DSPI_DCTAR(x)                    (*(vuint32*)(&__MBAR[0x8A0C + ((x)*0x4)]))
+#define MCF_DSPI_DTFDR(x)                    (*(vuint32*)(&__MBAR[0x8A3C + ((x)*0x4)]))
+#define MCF_DSPI_DRFDR(x)                    (*(vuint32*)(&__MBAR[0x8A7C + ((x)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_DSPI_DMCR */
+#define MCF_DSPI_DMCR_HALT                   (0x1)
+#define MCF_DSPI_DMCR_SMPL_PT(x)             (((x)&0x3)<<0x8)
+#define MCF_DSPI_DMCR_SMPL_PT_0CLK           (0)
+#define MCF_DSPI_DMCR_SMPL_PT_1CLK           (0x100)
+#define MCF_DSPI_DMCR_SMPL_PT_2CLK           (0x200)
+#define MCF_DSPI_DMCR_CRXF                   (0x400)
+#define MCF_DSPI_DMCR_CTXF                   (0x800)
+#define MCF_DSPI_DMCR_DRXF                   (0x1000)
+#define MCF_DSPI_DMCR_DTXF                   (0x2000)
+#define MCF_DSPI_DMCR_CSIS0                  (0x10000)
+#define MCF_DSPI_DMCR_CSIS2                  (0x40000)
+#define MCF_DSPI_DMCR_CSIS3                  (0x80000)
+#define MCF_DSPI_DMCR_CSIS5                  (0x200000)
+#define MCF_DSPI_DMCR_ROOE                   (0x1000000)
+#define MCF_DSPI_DMCR_PCSSE                  (0x2000000)
+#define MCF_DSPI_DMCR_MTFE                   (0x4000000)
+#define MCF_DSPI_DMCR_FRZ                    (0x8000000)
+#define MCF_DSPI_DMCR_DCONF(x)               (((x)&0x3)<<0x1C)
+#define MCF_DSPI_DMCR_CSCK                   (0x40000000)
+#define MCF_DSPI_DMCR_MSTR                   (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DTCR */
+#define MCF_DSPI_DTCR_SPI_TCNT(x)            (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_DSPI_DCTAR */
+#define MCF_DSPI_DCTAR_BR(x)                 (((x)&0xF)<<0)
+#define MCF_DSPI_DCTAR_DT(x)                 (((x)&0xF)<<0x4)
+#define MCF_DSPI_DCTAR_ASC(x)                (((x)&0xF)<<0x8)
+#define MCF_DSPI_DCTAR_CSSCK(x)              (((x)&0xF)<<0xC)
+#define MCF_DSPI_DCTAR_PBR(x)                (((x)&0x3)<<0x10)
+#define MCF_DSPI_DCTAR_PBR_1CLK              (0)
+#define MCF_DSPI_DCTAR_PBR_3CLK              (0x10000)
+#define MCF_DSPI_DCTAR_PBR_5CLK              (0x20000)
+#define MCF_DSPI_DCTAR_PBR_7CLK              (0x30000)
+#define MCF_DSPI_DCTAR_PDT(x)                (((x)&0x3)<<0x12)
+#define MCF_DSPI_DCTAR_PDT_1CLK              (0)
+#define MCF_DSPI_DCTAR_PDT_3CLK              (0x40000)
+#define MCF_DSPI_DCTAR_PDT_5CLK              (0x80000)
+#define MCF_DSPI_DCTAR_PDT_7CLK              (0xC0000)
+#define MCF_DSPI_DCTAR_PASC(x)               (((x)&0x3)<<0x14)
+#define MCF_DSPI_DCTAR_PASC_1CLK             (0)
+#define MCF_DSPI_DCTAR_PASC_3CLK             (0x100000)
+#define MCF_DSPI_DCTAR_PASC_5CLK             (0x200000)
+#define MCF_DSPI_DCTAR_PASC_7CLK             (0x300000)
+#define MCF_DSPI_DCTAR_PCSSCK(x)             (((x)&0x3)<<0x16)
+#define MCF_DSPI_DCTAR_LSBFE                 (0x1000000)
+#define MCF_DSPI_DCTAR_CPHA                  (0x2000000)
+#define MCF_DSPI_DCTAR_CPOL                  (0x4000000)
+#define MCF_DSPI_DCTAR_TRSZ(x)               (((x)&0xF)<<0x1B)
+
+/* Bit definitions and macros for MCF_DSPI_DSR */
+#define MCF_DSPI_DSR_RXPTR(x)                (((x)&0xF)<<0)
+#define MCF_DSPI_DSR_RXCTR(x)                (((x)&0xF)<<0x4)
+#define MCF_DSPI_DSR_TXPTR(x)                (((x)&0xF)<<0x8)
+#define MCF_DSPI_DSR_TXCTR(x)                (((x)&0xF)<<0xC)
+#define MCF_DSPI_DSR_RFDF                    (0x20000)
+#define MCF_DSPI_DSR_RFOF                    (0x80000)
+#define MCF_DSPI_DSR_TFFF                    (0x2000000)
+#define MCF_DSPI_DSR_TFUF                    (0x8000000)
+#define MCF_DSPI_DSR_EOQF                    (0x10000000)
+#define MCF_DSPI_DSR_TXRXS                   (0x40000000)
+#define MCF_DSPI_DSR_TCF                     (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DIRSR */
+#define MCF_DSPI_DIRSR_RFDFS                 (0x10000)
+#define MCF_DSPI_DIRSR_RFDFE                 (0x20000)
+#define MCF_DSPI_DIRSR_RFOFE                 (0x80000)
+#define MCF_DSPI_DIRSR_TFFFS                 (0x1000000)
+#define MCF_DSPI_DIRSR_TFFFE                 (0x2000000)
+#define MCF_DSPI_DIRSR_TFUFE                 (0x8000000)
+#define MCF_DSPI_DIRSR_EOQFE                 (0x10000000)
+#define MCF_DSPI_DIRSR_TCFE                  (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DTFR */
+#define MCF_DSPI_DTFR_TXDATA(x)              (((x)&0xFFFF)<<0)
+#define MCF_DSPI_DTFR_CS0                    (0x10000)
+#define MCF_DSPI_DTFR_CS2                    (0x40000)
+#define MCF_DSPI_DTFR_CS3                    (0x80000)
+#define MCF_DSPI_DTFR_CS5                    (0x200000)
+#define MCF_DSPI_DTFR_CTCNT                  (0x4000000)
+#define MCF_DSPI_DTFR_EOQ                    (0x8000000)
+#define MCF_DSPI_DTFR_CTAS(x)                (((x)&0x7)<<0x1C)
+#define MCF_DSPI_DTFR_CONT                   (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DRFR */
+#define MCF_DSPI_DRFR_RXDATA(x)              (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DSPI_DTFDR */
+#define MCF_DSPI_DTFDR_TXDATA(x)             (((x)&0xFFFF)<<0)
+#define MCF_DSPI_DTFDR_TXCMD(x)              (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_DSPI_DRFDR */
+#define MCF_DSPI_DRFDR_RXDATA(x)             (((x)&0xFFFF)<<0)
+
+
+#endif /* __MCF5475_DSPI_H__ */

BaS_codewarrior/firebeeV1/headers/MCF5475_EPORT.h

@@ -0,0 +1,123 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_EPORT_H__
+#define __MCF5475_EPORT_H__
+
+
+/*********************************************************************
+*
+* Edge Port Module (EPORT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_EPORT_EPPAR                      (*(vuint16*)(&__MBAR[0xF00]))
+#define MCF_EPORT_EPDDR                      (*(vuint8 *)(&__MBAR[0xF04]))
+#define MCF_EPORT_EPIER                      (*(vuint8 *)(&__MBAR[0xF05]))
+#define MCF_EPORT_EPDR                       (*(vuint8 *)(&__MBAR[0xF08]))
+#define MCF_EPORT_EPPDR                      (*(vuint8 *)(&__MBAR[0xF09]))
+#define MCF_EPORT_EPFR                       (*(vuint8 *)(&__MBAR[0xF0C]))
+
+
+
+/* Bit definitions and macros for MCF_EPORT_EPPAR */
+#define MCF_EPORT_EPPAR_EPPA1(x)             (((x)&0x3)<<0x2)
+#define MCF_EPORT_EPPAR_EPPA1_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA1_RISING         (0x4)
+#define MCF_EPORT_EPPAR_EPPA1_FALLING        (0x8)
+#define MCF_EPORT_EPPAR_EPPA1_BOTH           (0xC)
+#define MCF_EPORT_EPPAR_EPPA2(x)             (((x)&0x3)<<0x4)
+#define MCF_EPORT_EPPAR_EPPA2_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA2_RISING         (0x10)
+#define MCF_EPORT_EPPAR_EPPA2_FALLING        (0x20)
+#define MCF_EPORT_EPPAR_EPPA2_BOTH           (0x30)
+#define MCF_EPORT_EPPAR_EPPA3(x)             (((x)&0x3)<<0x6)
+#define MCF_EPORT_EPPAR_EPPA3_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA3_RISING         (0x40)
+#define MCF_EPORT_EPPAR_EPPA3_FALLING        (0x80)
+#define MCF_EPORT_EPPAR_EPPA3_BOTH           (0xC0)
+#define MCF_EPORT_EPPAR_EPPA4(x)             (((x)&0x3)<<0x8)
+#define MCF_EPORT_EPPAR_EPPA4_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA4_RISING         (0x100)
+#define MCF_EPORT_EPPAR_EPPA4_FALLING        (0x200)
+#define MCF_EPORT_EPPAR_EPPA4_BOTH           (0x300)
+#define MCF_EPORT_EPPAR_EPPA5(x)             (((x)&0x3)<<0xA)
+#define MCF_EPORT_EPPAR_EPPA5_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA5_RISING         (0x400)
+#define MCF_EPORT_EPPAR_EPPA5_FALLING        (0x800)
+#define MCF_EPORT_EPPAR_EPPA5_BOTH           (0xC00)
+#define MCF_EPORT_EPPAR_EPPA6(x)             (((x)&0x3)<<0xC)
+#define MCF_EPORT_EPPAR_EPPA6_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA6_RISING         (0x1000)
+#define MCF_EPORT_EPPAR_EPPA6_FALLING        (0x2000)
+#define MCF_EPORT_EPPAR_EPPA6_BOTH           (0x3000)
+#define MCF_EPORT_EPPAR_EPPA7(x)             (((x)&0x3)<<0xE)
+#define MCF_EPORT_EPPAR_EPPA7_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA7_RISING         (0x4000)
+#define MCF_EPORT_EPPAR_EPPA7_FALLING        (0x8000)
+#define MCF_EPORT_EPPAR_EPPA7_BOTH           (0xC000)
+#define MCF_EPORT_EPPAR_LEVEL                (0)
+#define MCF_EPORT_EPPAR_RISING               (0x1)
+#define MCF_EPORT_EPPAR_FALLING              (0x2)
+#define MCF_EPORT_EPPAR_BOTH                 (0x3)
+
+/* Bit definitions and macros for MCF_EPORT_EPDDR */
+#define MCF_EPORT_EPDDR_EPDD1                (0x2)
+#define MCF_EPORT_EPDDR_EPDD2                (0x4)
+#define MCF_EPORT_EPDDR_EPDD3                (0x8)
+#define MCF_EPORT_EPDDR_EPDD4                (0x10)
+#define MCF_EPORT_EPDDR_EPDD5                (0x20)
+#define MCF_EPORT_EPDDR_EPDD6                (0x40)
+#define MCF_EPORT_EPDDR_EPDD7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPIER */
+#define MCF_EPORT_EPIER_EPIE1                (0x2)
+#define MCF_EPORT_EPIER_EPIE2                (0x4)
+#define MCF_EPORT_EPIER_EPIE3                (0x8)
+#define MCF_EPORT_EPIER_EPIE4                (0x10)
+#define MCF_EPORT_EPIER_EPIE5                (0x20)
+#define MCF_EPORT_EPIER_EPIE6                (0x40)
+#define MCF_EPORT_EPIER_EPIE7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPDR */
+#define MCF_EPORT_EPDR_EPD1                  (0x2)
+#define MCF_EPORT_EPDR_EPD2                  (0x4)
+#define MCF_EPORT_EPDR_EPD3                  (0x8)
+#define MCF_EPORT_EPDR_EPD4                  (0x10)
+#define MCF_EPORT_EPDR_EPD5                  (0x20)
+#define MCF_EPORT_EPDR_EPD6                  (0x40)
+#define MCF_EPORT_EPDR_EPD7                  (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPPDR */
+#define MCF_EPORT_EPPDR_EPPD1                (0x2)
+#define MCF_EPORT_EPPDR_EPPD2                (0x4)
+#define MCF_EPORT_EPPDR_EPPD3                (0x8)
+#define MCF_EPORT_EPPDR_EPPD4                (0x10)
+#define MCF_EPORT_EPPDR_EPPD5                (0x20)
+#define MCF_EPORT_EPPDR_EPPD6                (0x40)
+#define MCF_EPORT_EPPDR_EPPD7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPFR */
+#define MCF_EPORT_EPFR_EPF1                  (0x2)
+#define MCF_EPORT_EPFR_EPF2                  (0x4)
+#define MCF_EPORT_EPFR_EPF3                  (0x8)
+#define MCF_EPORT_EPFR_EPF4                  (0x10)
+#define MCF_EPORT_EPFR_EPF5                  (0x20)
+#define MCF_EPORT_EPFR_EPF6                  (0x40)
+#define MCF_EPORT_EPFR_EPF7                  (0x80)
+
+
+#endif /* __MCF5475_EPORT_H__ */

BaS_codewarrior/firebeeV1/headers/MCF5475_FBCS.h

@@ -0,0 +1,100 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_FBCS_H__
+#define __MCF5475_FBCS_H__
+
+
+/*********************************************************************
+*
+* FlexBus Chip Select Module (FBCS)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FBCS0_CSAR                       (*(vuint32*)(&__MBAR[0x500]))
+#define MCF_FBCS0_CSMR                       (*(vuint32*)(&__MBAR[0x504]))
+#define MCF_FBCS0_CSCR                       (*(vuint32*)(&__MBAR[0x508]))
+
+#define MCF_FBCS1_CSAR                       (*(vuint32*)(&__MBAR[0x50C]))
+#define MCF_FBCS1_CSMR                       (*(vuint32*)(&__MBAR[0x510]))
+#define MCF_FBCS1_CSCR                       (*(vuint32*)(&__MBAR[0x514]))
+
+#define MCF_FBCS2_CSAR                       (*(vuint32*)(&__MBAR[0x518]))
+#define MCF_FBCS2_CSMR                       (*(vuint32*)(&__MBAR[0x51C]))
+#define MCF_FBCS2_CSCR                       (*(vuint32*)(&__MBAR[0x520]))
+
+#define MCF_FBCS3_CSAR                       (*(vuint32*)(&__MBAR[0x524]))
+#define MCF_FBCS3_CSMR                       (*(vuint32*)(&__MBAR[0x528]))
+#define MCF_FBCS3_CSCR                       (*(vuint32*)(&__MBAR[0x52C]))
+
+#define MCF_FBCS4_CSAR                       (*(vuint32*)(&__MBAR[0x530]))
+#define MCF_FBCS4_CSMR                       (*(vuint32*)(&__MBAR[0x534]))
+#define MCF_FBCS4_CSCR                       (*(vuint32*)(&__MBAR[0x538]))
+
+#define MCF_FBCS5_CSAR                       (*(vuint32*)(&__MBAR[0x53C]))
+#define MCF_FBCS5_CSMR                       (*(vuint32*)(&__MBAR[0x540]))
+#define MCF_FBCS5_CSCR                       (*(vuint32*)(&__MBAR[0x544]))
+
+#define MCF_FBCS_CSAR(x)                     (*(vuint32*)(&__MBAR[0x500 + ((x)*0xC)]))
+#define MCF_FBCS_CSMR(x)                     (*(vuint32*)(&__MBAR[0x504 + ((x)*0xC)]))
+#define MCF_FBCS_CSCR(x)                     (*(vuint32*)(&__MBAR[0x508 + ((x)*0xC)]))
+
+
+/* Bit definitions and macros for MCF_FBCS_CSAR */
+#define MCF_FBCS_CSAR_BA(x)                  ((x)&0xFFFF0000)
+
+/* Bit definitions and macros for MCF_FBCS_CSMR */
+#define MCF_FBCS_CSMR_V                      (0x1)
+#define MCF_FBCS_CSMR_WP                     (0x100)
+#define MCF_FBCS_CSMR_BAM(x)                 (((x)&0xFFFF)<<0x10)
+#define MCF_FBCS_CSMR_BAM_4G                 (0xFFFF0000)
+#define MCF_FBCS_CSMR_BAM_2G                 (0x7FFF0000)
+#define MCF_FBCS_CSMR_BAM_1G                 (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_1024M              (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_512M               (0x1FFF0000)
+#define MCF_FBCS_CSMR_BAM_256M               (0xFFF0000)
+#define MCF_FBCS_CSMR_BAM_128M               (0x7FF0000)
+#define MCF_FBCS_CSMR_BAM_64M                (0x3FF0000)
+#define MCF_FBCS_CSMR_BAM_32M                (0x1FF0000)
+#define MCF_FBCS_CSMR_BAM_16M                (0xFF0000)
+#define MCF_FBCS_CSMR_BAM_8M                 (0x7F0000)
+#define MCF_FBCS_CSMR_BAM_4M                 (0x3F0000)
+#define MCF_FBCS_CSMR_BAM_2M                 (0x1F0000)
+#define MCF_FBCS_CSMR_BAM_1M                 (0xF0000)
+#define MCF_FBCS_CSMR_BAM_1024K              (0xF0000)
+#define MCF_FBCS_CSMR_BAM_512K               (0x70000)
+#define MCF_FBCS_CSMR_BAM_256K               (0x30000)
+#define MCF_FBCS_CSMR_BAM_128K               (0x10000)
+#define MCF_FBCS_CSMR_BAM_64K                (0)
+
+/* Bit definitions and macros for MCF_FBCS_CSCR */
+#define MCF_FBCS_CSCR_BSTW                   (0x8)
+#define MCF_FBCS_CSCR_BSTR                   (0x10)
+#define MCF_FBCS_CSCR_BEM                    (0x20)
+#define MCF_FBCS_CSCR_PS(x)                  (((x)&0x3)<<0x6)
+#define MCF_FBCS_CSCR_PS_32                  (0)
+#define MCF_FBCS_CSCR_PS_8                   (0x40)
+#define MCF_FBCS_CSCR_PS_16                  (0x80)
+#define MCF_FBCS_CSCR_AA                     (0x100)
+#define MCF_FBCS_CSCR_WS(x)                  (((x)&0x3F)<<0xA)
+#define MCF_FBCS_CSCR_WRAH(x)                (((x)&0x3)<<0x10)
+#define MCF_FBCS_CSCR_RDAH(x)                (((x)&0x3)<<0x12)
+#define MCF_FBCS_CSCR_ASET(x)                (((x)&0x3)<<0x14)
+#define MCF_FBCS_CSCR_SWSEN                  (0x800000)
+#define MCF_FBCS_CSCR_SWS(x)                 (((x)&0x3F)<<0x1A)
+
+
+#endif /* __MCF5475_FBCS_H__ */

BaS_codewarrior/firebeeV1/headers/MCF5475_FEC.h

@@ -0,0 +1,680 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_FEC_H__
+#define __MCF5475_FEC_H__
+
+
+/*********************************************************************
+*
+* Fast Ethernet Controller(FEC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FEC0_EIR                         (*(vuint32*)(&__MBAR[0x9004]))
+#define MCF_FEC0_EIMR                        (*(vuint32*)(&__MBAR[0x9008]))
+#define MCF_FEC0_ECR                         (*(vuint32*)(&__MBAR[0x9024]))
+#define MCF_FEC0_MMFR                        (*(vuint32*)(&__MBAR[0x9040]))
+#define MCF_FEC0_MSCR                        (*(vuint32*)(&__MBAR[0x9044]))
+#define MCF_FEC0_MIBC                        (*(vuint32*)(&__MBAR[0x9064]))
+#define MCF_FEC0_RCR                         (*(vuint32*)(&__MBAR[0x9084]))
+#define MCF_FEC0_RHR                         (*(vuint32*)(&__MBAR[0x9088]))
+#define MCF_FEC0_TCR                         (*(vuint32*)(&__MBAR[0x90C4]))
+#define MCF_FEC0_PALR                        (*(vuint32*)(&__MBAR[0x90E4]))
+#define MCF_FEC0_PAHR                        (*(vuint32*)(&__MBAR[0x90E8]))
+#define MCF_FEC0_OPD                         (*(vuint32*)(&__MBAR[0x90EC]))
+#define MCF_FEC0_IAUR                        (*(vuint32*)(&__MBAR[0x9118]))
+#define MCF_FEC0_IALR                        (*(vuint32*)(&__MBAR[0x911C]))
+#define MCF_FEC0_GAUR                        (*(vuint32*)(&__MBAR[0x9120]))
+#define MCF_FEC0_GALR                        (*(vuint32*)(&__MBAR[0x9124]))
+#define MCF_FEC0_FECTFWR                     (*(vuint32*)(&__MBAR[0x9144]))
+#define MCF_FEC0_FECRFDR                     (*(vuint32*)(&__MBAR[0x9184]))
+#define MCF_FEC0_FECRFSR                     (*(vuint32*)(&__MBAR[0x9188]))
+#define MCF_FEC0_FECRFCR                     (*(vuint32*)(&__MBAR[0x918C]))
+#define MCF_FEC0_FECRLRFP                    (*(vuint32*)(&__MBAR[0x9190]))
+#define MCF_FEC0_FECRLWFP                    (*(vuint32*)(&__MBAR[0x9194]))
+#define MCF_FEC0_FECRFAR                     (*(vuint32*)(&__MBAR[0x9198]))
+#define MCF_FEC0_FECRFRP                     (*(vuint32*)(&__MBAR[0x919C]))
+#define MCF_FEC0_FECRFWP                     (*(vuint32*)(&__MBAR[0x91A0]))
+#define MCF_FEC0_FECTFDR                     (*(vuint32*)(&__MBAR[0x91A4]))
+#define MCF_FEC0_FECTFSR                     (*(vuint32*)(&__MBAR[0x91A8]))
+#define MCF_FEC0_FECTFCR                     (*(vuint32*)(&__MBAR[0x91AC]))
+#define MCF_FEC0_FECTLRFP                    (*(vuint32*)(&__MBAR[0x91B0]))
+#define MCF_FEC0_FECTLWFP                    (*(vuint32*)(&__MBAR[0x91B4]))
+#define MCF_FEC0_FECTFAR                     (*(vuint32*)(&__MBAR[0x91B8]))
+#define MCF_FEC0_FECTFRP                     (*(vuint32*)(&__MBAR[0x91BC]))
+#define MCF_FEC0_FECTFWP                     (*(vuint32*)(&__MBAR[0x91C0]))
+#define MCF_FEC0_FECFRST                     (*(vuint32*)(&__MBAR[0x91C4]))
+#define MCF_FEC0_FECCTCWR                    (*(vuint32*)(&__MBAR[0x91C8]))
+#define MCF_FEC0_RMON_T_DROP                 (*(vuint32*)(&__MBAR[0x9200]))
+#define MCF_FEC0_RMON_T_PACKETS              (*(vuint32*)(&__MBAR[0x9204]))
+#define MCF_FEC0_RMON_T_BC_PKT               (*(vuint32*)(&__MBAR[0x9208]))
+#define MCF_FEC0_RMON_T_MC_PKT               (*(vuint32*)(&__MBAR[0x920C]))
+#define MCF_FEC0_RMON_T_CRC_ALIGN            (*(vuint32*)(&__MBAR[0x9210]))
+#define MCF_FEC0_RMON_T_UNDERSIZE            (*(vuint32*)(&__MBAR[0x9214]))
+#define MCF_FEC0_RMON_T_OVERSIZE             (*(vuint32*)(&__MBAR[0x9218]))
+#define MCF_FEC0_RMON_T_FRAG                 (*(vuint32*)(&__MBAR[0x921C]))
+#define MCF_FEC0_RMON_T_JAB                  (*(vuint32*)(&__MBAR[0x9220]))
+#define MCF_FEC0_RMON_T_COL                  (*(vuint32*)(&__MBAR[0x9224]))
+#define MCF_FEC0_RMON_T_P64                  (*(vuint32*)(&__MBAR[0x9228]))
+#define MCF_FEC0_RMON_T_P65TO127             (*(vuint32*)(&__MBAR[0x922C]))
+#define MCF_FEC0_RMON_T_P128TO255            (*(vuint32*)(&__MBAR[0x9230]))
+#define MCF_FEC0_RMON_T_P256TO511            (*(vuint32*)(&__MBAR[0x9234]))
+#define MCF_FEC0_RMON_T_P512TO1023           (*(vuint32*)(&__MBAR[0x9238]))
+#define MCF_FEC0_RMON_T_P1024TO2047          (*(vuint32*)(&__MBAR[0x923C]))
+#define MCF_FEC0_RMON_T_P_GTE2048            (*(vuint32*)(&__MBAR[0x9240]))
+#define MCF_FEC0_RMON_T_OCTETS               (*(vuint32*)(&__MBAR[0x9244]))
+#define MCF_FEC0_IEEE_T_DROP                 (*(vuint32*)(&__MBAR[0x9248]))
+#define MCF_FEC0_IEEE_T_FRAME_OK             (*(vuint32*)(&__MBAR[0x924C]))
+#define MCF_FEC0_IEEE_T_1COL                 (*(vuint32*)(&__MBAR[0x9250]))
+#define MCF_FEC0_IEEE_T_MCOL                 (*(vuint32*)(&__MBAR[0x9254]))
+#define MCF_FEC0_IEEE_T_DEF                  (*(vuint32*)(&__MBAR[0x9258]))
+#define MCF_FEC0_IEEE_T_LCOL                 (*(vuint32*)(&__MBAR[0x925C]))
+#define MCF_FEC0_IEEE_T_EXCOL                (*(vuint32*)(&__MBAR[0x9260]))
+#define MCF_FEC0_IEEE_T_MACERR               (*(vuint32*)(&__MBAR[0x9264]))
+#define MCF_FEC0_IEEE_T_CSERR                (*(vuint32*)(&__MBAR[0x9268]))
+#define MCF_FEC0_IEEE_T_SQE                  (*(vuint32*)(&__MBAR[0x926C]))
+#define MCF_FEC0_IEEE_T_FDXFC                (*(vuint32*)(&__MBAR[0x9270]))
+#define MCF_FEC0_IEEE_T_OCTETS_OK            (*(vuint32*)(&__MBAR[0x9274]))
+#define MCF_FEC0_RMON_R_DROP                 (*(vuint32*)(&__MBAR[0x9280]))
+#define MCF_FEC0_RMON_R_PACKETS              (*(vuint32*)(&__MBAR[0x9284]))
+#define MCF_FEC0_RMON_R_BC_PKT               (*(vuint32*)(&__MBAR[0x9288]))
+#define MCF_FEC0_RMON_R_MC_PKT               (*(vuint32*)(&__MBAR[0x928C]))
+#define MCF_FEC0_RMON_R_CRC_ALIGN            (*(vuint32*)(&__MBAR[0x9290]))
+#define MCF_FEC0_RMON_R_UNDERSIZE            (*(vuint32*)(&__MBAR[0x9294]))
+#define MCF_FEC0_RMON_R_OVERSIZE             (*(vuint32*)(&__MBAR[0x9298]))
+#define MCF_FEC0_RMON_R_FRAG                 (*(vuint32*)(&__MBAR[0x929C]))
+#define MCF_FEC0_RMON_R_JAB                  (*(vuint32*)(&__MBAR[0x92A0]))
+#define MCF_FEC0_RMON_R_RESVD_0              (*(vuint32*)(&__MBAR[0x92A4]))
+#define MCF_FEC0_RMON_R_P64                  (*(vuint32*)(&__MBAR[0x92A8]))
+#define MCF_FEC0_RMON_R_P65TO127             (*(vuint32*)(&__MBAR[0x92AC]))
+#define MCF_FEC0_RMON_R_P128TO255            (*(vuint32*)(&__MBAR[0x92B0]))
+#define MCF_FEC0_RMON_R_P256TO511            (*(vuint32*)(&__MBAR[0x92B4]))
+#define MCF_FEC0_RMON_R_P512TO1023           (*(vuint32*)(&__MBAR[0x92B8]))
+#define MCF_FEC0_RMON_R_P1024TO2047          (*(vuint32*)(&__MBAR[0x92BC]))
+#define MCF_FEC0_RMON_R_P_GTE2048            (*(vuint32*)(&__MBAR[0x92C0]))
+#define MCF_FEC0_RMON_R_OCTETS               (*(vuint32*)(&__MBAR[0x92C4]))
+#define MCF_FEC0_IEEE_R_DROP                 (*(vuint32*)(&__MBAR[0x92C8]))
+#define MCF_FEC0_IEEE_R_FRAME_OK             (*(vuint32*)(&__MBAR[0x92CC]))
+#define MCF_FEC0_IEEE_R_CRC                  (*(vuint32*)(&__MBAR[0x92D0]))
+#define MCF_FEC0_IEEE_R_ALIGN                (*(vuint32*)(&__MBAR[0x92D4]))
+#define MCF_FEC0_IEEE_R_MACERR               (*(vuint32*)(&__MBAR[0x92D8]))
+#define MCF_FEC0_IEEE_R_FDXFC                (*(vuint32*)(&__MBAR[0x92DC]))
+#define MCF_FEC0_IEEE_R_OCTETS_OK            (*(vuint32*)(&__MBAR[0x92E0]))
+
+#define MCF_FEC1_EIR                         (*(vuint32*)(&__MBAR[0x9804]))
+#define MCF_FEC1_EIMR                        (*(vuint32*)(&__MBAR[0x9808]))
+#define MCF_FEC1_ECR                         (*(vuint32*)(&__MBAR[0x9824]))
+#define MCF_FEC1_MMFR                        (*(vuint32*)(&__MBAR[0x9840]))
+#define MCF_FEC1_MSCR                        (*(vuint32*)(&__MBAR[0x9844]))
+#define MCF_FEC1_MIBC                        (*(vuint32*)(&__MBAR[0x9864]))
+#define MCF_FEC1_RCR                         (*(vuint32*)(&__MBAR[0x9884]))
+#define MCF_FEC1_RHR                         (*(vuint32*)(&__MBAR[0x9888]))
+#define MCF_FEC1_TCR                         (*(vuint32*)(&__MBAR[0x98C4]))
+#define MCF_FEC1_PALR                        (*(vuint32*)(&__MBAR[0x98E4]))
+#define MCF_FEC1_PAHR                        (*(vuint32*)(&__MBAR[0x98E8]))
+#define MCF_FEC1_OPD                         (*(vuint32*)(&__MBAR[0x98EC]))
+#define MCF_FEC1_IAUR                        (*(vuint32*)(&__MBAR[0x9918]))
+#define MCF_FEC1_IALR                        (*(vuint32*)(&__MBAR[0x991C]))
+#define MCF_FEC1_GAUR                        (*(vuint32*)(&__MBAR[0x9920]))
+#define MCF_FEC1_GALR                        (*(vuint32*)(&__MBAR[0x9924]))
+#define MCF_FEC1_FECTFWR                     (*(vuint32*)(&__MBAR[0x9944]))
+#define MCF_FEC1_FECRFDR                     (*(vuint32*)(&__MBAR[0x9984]))
+#define MCF_FEC1_FECRFSR                     (*(vuint32*)(&__MBAR[0x9988]))
+#define MCF_FEC1_FECRFCR                     (*(vuint32*)(&__MBAR[0x998C]))
+#define MCF_FEC1_FECRLRFP                    (*(vuint32*)(&__MBAR[0x9990]))
+#define MCF_FEC1_FECRLWFP                    (*(vuint32*)(&__MBAR[0x9994]))
+#define MCF_FEC1_FECRFAR                     (*(vuint32*)(&__MBAR[0x9998]))
+#define MCF_FEC1_FECRFRP                     (*(vuint32*)(&__MBAR[0x999C]))
+#define MCF_FEC1_FECRFWP                     (*(vuint32*)(&__MBAR[0x99A0]))
+#define MCF_FEC1_FECTFDR                     (*(vuint32*)(&__MBAR[0x99A4]))
+#define MCF_FEC1_FECTFSR                     (*(vuint32*)(&__MBAR[0x99A8]))
+#define MCF_FEC1_FECTFCR                     (*(vuint32*)(&__MBAR[0x99AC]))
+#define MCF_FEC1_FECTLRFP                    (*(vuint32*)(&__MBAR[0x99B0]))
+#define MCF_FEC1_FECTLWFP                    (*(vuint32*)(&__MBAR[0x99B4]))
+#define MCF_FEC1_FECTFAR                     (*(vuint32*)(&__MBAR[0x99B8]))
+#define MCF_FEC1_FECTFRP                     (*(vuint32*)(&__MBAR[0x99BC]))
+#define MCF_FEC1_FECTFWP                     (*(vuint32*)(&__MBAR[0x99C0]))
+#define MCF_FEC1_FECFRST                     (*(vuint32*)(&__MBAR[0x99C4]))
+#define MCF_FEC1_FECCTCWR                    (*(vuint32*)(&__MBAR[0x99C8]))
+#define MCF_FEC1_RMON_T_DROP                 (*(vuint32*)(&__MBAR[0x9A00]))
+#define MCF_FEC1_RMON_T_PACKETS              (*(vuint32*)(&__MBAR[0x9A04]))
+#define MCF_FEC1_RMON_T_BC_PKT               (*(vuint32*)(&__MBAR[0x9A08]))
+#define MCF_FEC1_RMON_T_MC_PKT               (*(vuint32*)(&__MBAR[0x9A0C]))
+#define MCF_FEC1_RMON_T_CRC_ALIGN            (*(vuint32*)(&__MBAR[0x9A10]))
+#define MCF_FEC1_RMON_T_UNDERSIZE            (*(vuint32*)(&__MBAR[0x9A14]))
+#define MCF_FEC1_RMON_T_OVERSIZE             (*(vuint32*)(&__MBAR[0x9A18]))
+#define MCF_FEC1_RMON_T_FRAG                 (*(vuint32*)(&__MBAR[0x9A1C]))
+#define MCF_FEC1_RMON_T_JAB                  (*(vuint32*)(&__MBAR[0x9A20]))
+#define MCF_FEC1_RMON_T_COL                  (*(vuint32*)(&__MBAR[0x9A24]))
+#define MCF_FEC1_RMON_T_P64                  (*(vuint32*)(&__MBAR[0x9A28]))
+#define MCF_FEC1_RMON_T_P65TO127             (*(vuint32*)(&__MBAR[0x9A2C]))
+#define MCF_FEC1_RMON_T_P128TO255            (*(vuint32*)(&__MBAR[0x9A30]))
+#define MCF_FEC1_RMON_T_P256TO511            (*(vuint32*)(&__MBAR[0x9A34]))
+#define MCF_FEC1_RMON_T_P512TO1023           (*(vuint32*)(&__MBAR[0x9A38]))
+#define MCF_FEC1_RMON_T_P1024TO2047          (*(vuint32*)(&__MBAR[0x9A3C]))
+#define MCF_FEC1_RMON_T_P_GTE2048            (*(vuint32*)(&__MBAR[0x9A40]))
+#define MCF_FEC1_RMON_T_OCTETS               (*(vuint32*)(&__MBAR[0x9A44]))
+#define MCF_FEC1_IEEE_T_DROP                 (*(vuint32*)(&__MBAR[0x9A48]))
+#define MCF_FEC1_IEEE_T_FRAME_OK             (*(vuint32*)(&__MBAR[0x9A4C]))
+#define MCF_FEC1_IEEE_T_1COL                 (*(vuint32*)(&__MBAR[0x9A50]))
+#define MCF_FEC1_IEEE_T_MCOL                 (*(vuint32*)(&__MBAR[0x9A54]))
+#define MCF_FEC1_IEEE_T_DEF                  (*(vuint32*)(&__MBAR[0x9A58]))
+#define MCF_FEC1_IEEE_T_LCOL                 (*(vuint32*)(&__MBAR[0x9A5C]))
+#define MCF_FEC1_IEEE_T_EXCOL                (*(vuint32*)(&__MBAR[0x9A60]))
+#define MCF_FEC1_IEEE_T_MACERR               (*(vuint32*)(&__MBAR[0x9A64]))
+#define MCF_FEC1_IEEE_T_CSERR                (*(vuint32*)(&__MBAR[0x9A68]))
+#define MCF_FEC1_IEEE_T_SQE                  (*(vuint32*)(&__MBAR[0x9A6C]))
+#define MCF_FEC1_IEEE_T_FDXFC                (*(vuint32*)(&__MBAR[0x9A70]))
+#define MCF_FEC1_IEEE_T_OCTETS_OK            (*(vuint32*)(&__MBAR[0x9A74]))
+#define MCF_FEC1_RMON_R_DROP                 (*(vuint32*)(&__MBAR[0x9A80]))
+#define MCF_FEC1_RMON_R_PACKETS              (*(vuint32*)(&__MBAR[0x9A84]))
+#define MCF_FEC1_RMON_R_BC_PKT               (*(vuint32*)(&__MBAR[0x9A88]))
+#define MCF_FEC1_RMON_R_MC_PKT               (*(vuint32*)(&__MBAR[0x9A8C]))
+#define MCF_FEC1_RMON_R_CRC_ALIGN            (*(vuint32*)(&__MBAR[0x9A90]))
+#define MCF_FEC1_RMON_R_UNDERSIZE            (*(vuint32*)(&__MBAR[0x9A94]))
+#define MCF_FEC1_RMON_R_OVERSIZE             (*(vuint32*)(&__MBAR[0x9A98]))
+#define MCF_FEC1_RMON_R_FRAG                 (*(vuint32*)(&__MBAR[0x9A9C]))
+#define MCF_FEC1_RMON_R_JAB                  (*(vuint32*)(&__MBAR[0x9AA0]))
+#define MCF_FEC1_RMON_R_RESVD_0              (*(vuint32*)(&__MBAR[0x9AA4]))
+#define MCF_FEC1_RMON_R_P64                  (*(vuint32*)(&__MBAR[0x9AA8]))
+#define MCF_FEC1_RMON_R_P65TO127             (*(vuint32*)(&__MBAR[0x9AAC]))
+#define MCF_FEC1_RMON_R_P128TO255            (*(vuint32*)(&__MBAR[0x9AB0]))
+#define MCF_FEC1_RMON_R_P256TO511            (*(vuint32*)(&__MBAR[0x9AB4]))
+#define MCF_FEC1_RMON_R_P512TO1023           (*(vuint32*)(&__MBAR[0x9AB8]))
+#define MCF_FEC1_RMON_R_P1024TO2047          (*(vuint32*)(&__MBAR[0x9ABC]))
+#define MCF_FEC1_RMON_R_P_GTE2048            (*(vuint32*)(&__MBAR[0x9AC0]))
+#define MCF_FEC1_RMON_R_OCTETS               (*(vuint32*)(&__MBAR[0x9AC4]))
+#define MCF_FEC1_IEEE_R_DROP                 (*(vuint32*)(&__MBAR[0x9AC8]))
+#define MCF_FEC1_IEEE_R_FRAME_OK             (*(vuint32*)(&__MBAR[0x9ACC]))
+#define MCF_FEC1_IEEE_R_CRC                  (*(vuint32*)(&__MBAR[0x9AD0]))
+#define MCF_FEC1_IEEE_R_ALIGN                (*(vuint32*)(&__MBAR[0x9AD4]))
+#define MCF_FEC1_IEEE_R_MACERR               (*(vuint32*)(&__MBAR[0x9AD8]))
+#define MCF_FEC1_IEEE_R_FDXFC                (*(vuint32*)(&__MBAR[0x9ADC]))
+#define MCF_FEC1_IEEE_R_OCTETS_OK            (*(vuint32*)(&__MBAR[0x9AE0]))
+
+#define MCF_FEC_EIR(x)                       (*(vuint32*)(&__MBAR[0x9004 + ((x)*0x800)]))
+#define MCF_FEC_EIMR(x)                      (*(vuint32*)(&__MBAR[0x9008 + ((x)*0x800)]))
+#define MCF_FEC_ECR(x)                       (*(vuint32*)(&__MBAR[0x9024 + ((x)*0x800)]))
+#define MCF_FEC_MMFR(x)                      (*(vuint32*)(&__MBAR[0x9040 + ((x)*0x800)]))
+#define MCF_FEC_MSCR(x)                      (*(vuint32*)(&__MBAR[0x9044 + ((x)*0x800)]))
+#define MCF_FEC_MIBC(x)                      (*(vuint32*)(&__MBAR[0x9064 + ((x)*0x800)]))
+#define MCF_FEC_RCR(x)                       (*(vuint32*)(&__MBAR[0x9084 + ((x)*0x800)]))
+#define MCF_FEC_RHR(x)                       (*(vuint32*)(&__MBAR[0x9088 + ((x)*0x800)]))
+#define MCF_FEC_TCR(x)                       (*(vuint32*)(&__MBAR[0x90C4 + ((x)*0x800)]))
+#define MCF_FEC_PALR(x)                      (*(vuint32*)(&__MBAR[0x90E4 + ((x)*0x800)]))
+#define MCF_FEC_PAHR(x)                      (*(vuint32*)(&__MBAR[0x90E8 + ((x)*0x800)]))
+#define MCF_FEC_OPD(x)                       (*(vuint32*)(&__MBAR[0x90EC + ((x)*0x800)]))
+#define MCF_FEC_IAUR(x)                      (*(vuint32*)(&__MBAR[0x9118 + ((x)*0x800)]))
+#define MCF_FEC_IALR(x)                      (*(vuint32*)(&__MBAR[0x911C + ((x)*0x800)]))
+#define MCF_FEC_GAUR(x)                      (*(vuint32*)(&__MBAR[0x9120 + ((x)*0x800)]))
+#define MCF_FEC_GALR(x)                      (*(vuint32*)(&__MBAR[0x9124 + ((x)*0x800)]))
+#define MCF_FEC_FECTFWR(x)                   (*(vuint32*)(&__MBAR[0x9144 + ((x)*0x800)]))
+#define MCF_FEC_FECRFDR(x)                   (*(vuint32*)(&__MBAR[0x9184 + ((x)*0x800)]))
+#define MCF_FEC_FECRFSR(x)                   (*(vuint32*)(&__MBAR[0x9188 + ((x)*0x800)]))
+#define MCF_FEC_FECRFCR(x)                   (*(vuint32*)(&__MBAR[0x918C + ((x)*0x800)]))
+#define MCF_FEC_FECRLRFP(x)                  (*(vuint32*)(&__MBAR[0x9190 + ((x)*0x800)]))
+#define MCF_FEC_FECRLWFP(x)                  (*(vuint32*)(&__MBAR[0x9194 + ((x)*0x800)]))
+#define MCF_FEC_FECRFAR(x)                   (*(vuint32*)(&__MBAR[0x9198 + ((x)*0x800)]))
+#define MCF_FEC_FECRFRP(x)                   (*(vuint32*)(&__MBAR[0x919C + ((x)*0x800)]))
+#define MCF_FEC_FECRFWP(x)                   (*(vuint32*)(&__MBAR[0x91A0 + ((x)*0x800)]))
+#define MCF_FEC_FECTFDR(x)                   (*(vuint32*)(&__MBAR[0x91A4 + ((x)*0x800)]))
+#define MCF_FEC_FECTFSR(x)                   (*(vuint32*)(&__MBAR[0x91A8 + ((x)*0x800)]))
+#define MCF_FEC_FECTFCR(x)                   (*(vuint32*)(&__MBAR[0x91AC + ((x)*0x800)]))
+#define MCF_FEC_FECTLRFP(x)                  (*(vuint32*)(&__MBAR[0x91B0 + ((x)*0x800)]))
+#define MCF_FEC_FECTLWFP(x)                  (*(vuint32*)(&__MBAR[0x91B4 + ((x)*0x800)]))
+#define MCF_FEC_FECTFAR(x)                   (*(vuint32*)(&__MBAR[0x91B8 + ((x)*0x800)]))
+#define MCF_FEC_FECTFRP(x)                   (*(vuint32*)(&__MBAR[0x91BC + ((x)*0x800)]))
+#define MCF_FEC_FECTFWP(x)                   (*(vuint32*)(&__MBAR[0x91C0 + ((x)*0x800)]))
+#define MCF_FEC_FECFRST(x)                   (*(vuint32*)(&__MBAR[0x91C4 + ((x)*0x800)]))
+#define MCF_FEC_FECCTCWR(x)                  (*(vuint32*)(&__MBAR[0x91C8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_DROP(x)               (*(vuint32*)(&__MBAR[0x9200 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_PACKETS(x)            (*(vuint32*)(&__MBAR[0x9204 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_BC_PKT(x)             (*(vuint32*)(&__MBAR[0x9208 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_MC_PKT(x)             (*(vuint32*)(&__MBAR[0x920C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_CRC_ALIGN(x)          (*(vuint32*)(&__MBAR[0x9210 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_UNDERSIZE(x)          (*(vuint32*)(&__MBAR[0x9214 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_OVERSIZE(x)           (*(vuint32*)(&__MBAR[0x9218 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_FRAG(x)               (*(vuint32*)(&__MBAR[0x921C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_JAB(x)                (*(vuint32*)(&__MBAR[0x9220 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_COL(x)                (*(vuint32*)(&__MBAR[0x9224 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P64(x)                (*(vuint32*)(&__MBAR[0x9228 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P65TO127(x)           (*(vuint32*)(&__MBAR[0x922C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P128TO255(x)          (*(vuint32*)(&__MBAR[0x9230 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P256TO511(x)          (*(vuint32*)(&__MBAR[0x9234 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P512TO1023(x)         (*(vuint32*)(&__MBAR[0x9238 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P1024TO2047(x)        (*(vuint32*)(&__MBAR[0x923C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P_GTE2048(x)          (*(vuint32*)(&__MBAR[0x9240 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_OCTETS(x)             (*(vuint32*)(&__MBAR[0x9244 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_DROP(x)               (*(vuint32*)(&__MBAR[0x9248 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_FRAME_OK(x)           (*(vuint32*)(&__MBAR[0x924C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_1COL(x)               (*(vuint32*)(&__MBAR[0x9250 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_MCOL(x)               (*(vuint32*)(&__MBAR[0x9254 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_DEF(x)                (*(vuint32*)(&__MBAR[0x9258 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_LCOL(x)               (*(vuint32*)(&__MBAR[0x925C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_EXCOL(x)              (*(vuint32*)(&__MBAR[0x9260 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_MACERR(x)             (*(vuint32*)(&__MBAR[0x9264 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_CSERR(x)              (*(vuint32*)(&__MBAR[0x9268 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_SQE(x)                (*(vuint32*)(&__MBAR[0x926C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_FDXFC(x)              (*(vuint32*)(&__MBAR[0x9270 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_OCTETS_OK(x)          (*(vuint32*)(&__MBAR[0x9274 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_DROP(x)               (*(vuint32*)(&__MBAR[0x9280 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_PACKETS(x)            (*(vuint32*)(&__MBAR[0x9284 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_BC_PKT(x)             (*(vuint32*)(&__MBAR[0x9288 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_MC_PKT(x)             (*(vuint32*)(&__MBAR[0x928C + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_CRC_ALIGN(x)          (*(vuint32*)(&__MBAR[0x9290 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_UNDERSIZE(x)          (*(vuint32*)(&__MBAR[0x9294 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_OVERSIZE(x)           (*(vuint32*)(&__MBAR[0x9298 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_FRAG(x)               (*(vuint32*)(&__MBAR[0x929C + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_JAB(x)                (*(vuint32*)(&__MBAR[0x92A0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_RESVD_0(x)            (*(vuint32*)(&__MBAR[0x92A4 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P64(x)                (*(vuint32*)(&__MBAR[0x92A8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P65TO127(x)           (*(vuint32*)(&__MBAR[0x92AC + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P128TO255(x)          (*(vuint32*)(&__MBAR[0x92B0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P256TO511(x)          (*(vuint32*)(&__MBAR[0x92B4 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P512TO1023(x)         (*(vuint32*)(&__MBAR[0x92B8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P1024TO2047(x)        (*(vuint32*)(&__MBAR[0x92BC + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P_GTE2048(x)          (*(vuint32*)(&__MBAR[0x92C0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_OCTETS(x)             (*(vuint32*)(&__MBAR[0x92C4 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_DROP(x)               (*(vuint32*)(&__MBAR[0x92C8 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_FRAME_OK(x)           (*(vuint32*)(&__MBAR[0x92CC + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_CRC(x)                (*(vuint32*)(&__MBAR[0x92D0 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_ALIGN(x)              (*(vuint32*)(&__MBAR[0x92D4 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_MACERR(x)             (*(vuint32*)(&__MBAR[0x92D8 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_FDXFC(x)              (*(vuint32*)(&__MBAR[0x92DC + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_OCTETS_OK(x)          (*(vuint32*)(&__MBAR[0x92E0 + ((x)*0x800)]))
+
+
+/* Bit definitions and macros for MCF_FEC_EIR */
+#define MCF_FEC_EIR_RFERR                    (0x20000)
+#define MCF_FEC_EIR_XFERR                    (0x40000)
+#define MCF_FEC_EIR_XFUN                     (0x80000)
+#define MCF_FEC_EIR_RL                       (0x100000)
+#define MCF_FEC_EIR_LC                       (0x200000)
+#define MCF_FEC_EIR_MII                      (0x800000)
+#define MCF_FEC_EIR_TXF                      (0x8000000)
+#define MCF_FEC_EIR_GRA                      (0x10000000)
+#define MCF_FEC_EIR_BABT                     (0x20000000)
+#define MCF_FEC_EIR_BABR                     (0x40000000)
+#define MCF_FEC_EIR_HBERR                    (0x80000000)
+#define MCF_FEC_EIR_CLEAR_ALL                (0xFFFFFFFF)
+
+/* Bit definitions and macros for MCF_FEC_EIMR */
+#define MCF_FEC_EIMR_RFERR                   (0x20000)
+#define MCF_FEC_EIMR_XFERR                   (0x40000)
+#define MCF_FEC_EIMR_XFUN                    (0x80000)
+#define MCF_FEC_EIMR_RL                      (0x100000)
+#define MCF_FEC_EIMR_LC                      (0x200000)
+#define MCF_FEC_EIMR_MII                     (0x800000)
+#define MCF_FEC_EIMR_TXF                     (0x8000000)
+#define MCF_FEC_EIMR_GRA                     (0x10000000)
+#define MCF_FEC_EIMR_BABT                    (0x20000000)
+#define MCF_FEC_EIMR_BABR                    (0x40000000)
+#define MCF_FEC_EIMR_HBERR                   (0x80000000)
+#define MCF_FEC_EIMR_MASK_ALL                (0)
+#define MCF_FEC_EIMR_UNMASK_ALL              (0xFFFFFFFF)
+
+/* Bit definitions and macros for MCF_FEC_ECR */
+#define MCF_FEC_ECR_RESET                    (0x1)
+#define MCF_FEC_ECR_ETHER_EN                 (0x2)
+
+/* Bit definitions and macros for MCF_FEC_MMFR */
+#define MCF_FEC_MMFR_DATA(x)                 (((x)&0xFFFF)<<0)
+#define MCF_FEC_MMFR_TA(x)                   (((x)&0x3)<<0x10)
+#define MCF_FEC_MMFR_TA_10                   (0x20000)
+#define MCF_FEC_MMFR_RA(x)                   (((x)&0x1F)<<0x12)
+#define MCF_FEC_MMFR_PA(x)                   (((x)&0x1F)<<0x17)
+#define MCF_FEC_MMFR_OP(x)                   (((x)&0x3)<<0x1C)
+#define MCF_FEC_MMFR_OP_READ                 (0x20000000)
+#define MCF_FEC_MMFR_OP_WRITE                (0x10000000)
+#define MCF_FEC_MMFR_ST(x)                   (((x)&0x3)<<0x1E)
+#define MCF_FEC_MMFR_ST_01                   (0x40000000)
+
+/* Bit definitions and macros for MCF_FEC_MSCR */
+#define MCF_FEC_MSCR_MII_SPEED(x)            (((x)&0x3F)<<0x1)
+#define MCF_FEC_MSCR_DIS_PREAMBLE            (0x80)
+#define MCF_FEC_MSCR_MII_SPEED_133           (0x1B<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_120           (0x18<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_66            (0xE<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_60            (0xC<<0x1)
+
+/* Bit definitions and macros for MCF_FEC_MIBC */
+#define MCF_FEC_MIBC_MIB_IDLE                (0x40000000)
+#define MCF_FEC_MIBC_MIB_DISABLE             (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_RCR */
+#define MCF_FEC_RCR_LOOP                     (0x1)
+#define MCF_FEC_RCR_DRT                      (0x2)
+#define MCF_FEC_RCR_MII_MODE                 (0x4)
+#define MCF_FEC_RCR_PROM                     (0x8)
+#define MCF_FEC_RCR_BC_REJ                   (0x10)
+#define MCF_FEC_RCR_FCE                      (0x20)
+#define MCF_FEC_RCR_MAX_FL(x)                (((x)&0x7FF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_RHR */
+#define MCF_FEC_RHR_HASH(x)                  (((x)&0x3F)<<0x18)
+#define MCF_FEC_RHR_MULTCAST                 (0x40000000)
+#define MCF_FEC_RHR_FCE                      (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_TCR */
+#define MCF_FEC_TCR_GTS                      (0x1)
+#define MCF_FEC_TCR_HBC                      (0x2)
+#define MCF_FEC_TCR_FDEN                     (0x4)
+#define MCF_FEC_TCR_TFC_PAUSE                (0x8)
+#define MCF_FEC_TCR_RFC_PAUSE                (0x10)
+
+/* Bit definitions and macros for MCF_FEC_PALR */
+#define MCF_FEC_PALR_PADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_PAHR */
+#define MCF_FEC_PAHR_TYPE(x)                 (((x)&0xFFFF)<<0)
+#define MCF_FEC_PAHR_PADDR2(x)               (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_OPD */
+#define MCF_FEC_OPD_PAUSE_DUR(x)             (((x)&0xFFFF)<<0)
+#define MCF_FEC_OPD_OPCODE(x)                (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_IAUR */
+#define MCF_FEC_IAUR_IADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IALR */
+#define MCF_FEC_IALR_IADDR2(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_GAUR */
+#define MCF_FEC_GAUR_GADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_GALR */
+#define MCF_FEC_GALR_GADDR2(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFWR */
+#define MCF_FEC_FECTFWR_X_WMRK(x)            (((x)&0xF)<<0)
+#define MCF_FEC_FECTFWR_X_WMRK_64            (0)
+#define MCF_FEC_FECTFWR_X_WMRK_128           (0x1)
+#define MCF_FEC_FECTFWR_X_WMRK_192           (0x2)
+#define MCF_FEC_FECTFWR_X_WMRK_256           (0x3)
+#define MCF_FEC_FECTFWR_X_WMRK_320           (0x4)
+#define MCF_FEC_FECTFWR_X_WMRK_384           (0x5)
+#define MCF_FEC_FECTFWR_X_WMRK_448           (0x6)
+#define MCF_FEC_FECTFWR_X_WMRK_512           (0x7)
+#define MCF_FEC_FECTFWR_X_WMRK_576           (0x8)
+#define MCF_FEC_FECTFWR_X_WMRK_640           (0x9)
+#define MCF_FEC_FECTFWR_X_WMRK_704           (0xA)
+#define MCF_FEC_FECTFWR_X_WMRK_768           (0xB)
+#define MCF_FEC_FECTFWR_X_WMRK_832           (0xC)
+#define MCF_FEC_FECTFWR_X_WMRK_896           (0xD)
+#define MCF_FEC_FECTFWR_X_WMRK_960           (0xE)
+#define MCF_FEC_FECTFWR_X_WMRK_1024          (0xF)
+
+/* Bit definitions and macros for MCF_FEC_FECRFDR */
+#define MCF_FEC_FECRFDR_FIFO_DATA(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFSR */
+#define MCF_FEC_FECRFSR_EMT                  (0x10000)
+#define MCF_FEC_FECRFSR_ALARM                (0x20000)
+#define MCF_FEC_FECRFSR_FU                   (0x40000)
+#define MCF_FEC_FECRFSR_FRMRDY               (0x80000)
+#define MCF_FEC_FECRFSR_OF                   (0x100000)
+#define MCF_FEC_FECRFSR_UF                   (0x200000)
+#define MCF_FEC_FECRFSR_RXW                  (0x400000)
+#define MCF_FEC_FECRFSR_FAE                  (0x800000)
+#define MCF_FEC_FECRFSR_FRM(x)               (((x)&0xF)<<0x18)
+#define MCF_FEC_FECRFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_FECRFCR */
+#define MCF_FEC_FECRFCR_COUNTER(x)           (((x)&0xFFFF)<<0)
+#define MCF_FEC_FECRFCR_OF_MSK               (0x80000)
+#define MCF_FEC_FECRFCR_UF_MSK               (0x100000)
+#define MCF_FEC_FECRFCR_RXW_MSK              (0x200000)
+#define MCF_FEC_FECRFCR_FAE_MSK              (0x400000)
+#define MCF_FEC_FECRFCR_IP_MSK               (0x800000)
+#define MCF_FEC_FECRFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_FEC_FECRFCR_FRMEN                (0x8000000)
+#define MCF_FEC_FECRFCR_TIMER                (0x10000000)
+
+/* Bit definitions and macros for MCF_FEC_FECRLRFP */
+#define MCF_FEC_FECRLRFP_LRFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRLWFP */
+#define MCF_FEC_FECRLWFP_LWFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFAR */
+#define MCF_FEC_FECRFAR_ALARM(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFRP */
+#define MCF_FEC_FECRFRP_READ(x)              (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFWP */
+#define MCF_FEC_FECRFWP_WRITE(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFDR */
+#define MCF_FEC_FECTFDR_FIFO_DATA(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFSR */
+#define MCF_FEC_FECTFSR_EMT                  (0x10000)
+#define MCF_FEC_FECTFSR_ALARM                (0x20000)
+#define MCF_FEC_FECTFSR_FU                   (0x40000)
+#define MCF_FEC_FECTFSR_FRMRDY               (0x80000)
+#define MCF_FEC_FECTFSR_OF                   (0x100000)
+#define MCF_FEC_FECTFSR_UF                   (0x200000)
+#define MCF_FEC_FECTFSR_FAE                  (0x800000)
+#define MCF_FEC_FECTFSR_FRM(x)               (((x)&0xF)<<0x18)
+#define MCF_FEC_FECTFSR_TXW                  (0x40000000)
+#define MCF_FEC_FECTFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_FECTFCR */
+#define MCF_FEC_FECTFCR_RESERVED             (0x200000)
+#define MCF_FEC_FECTFCR_COUNTER(x)           (((x)&0xFFFF)<<0|0x200000)
+#define MCF_FEC_FECTFCR_TXW_MASK             (0x240000)
+#define MCF_FEC_FECTFCR_OF_MSK               (0x280000)
+#define MCF_FEC_FECTFCR_UF_MSK               (0x300000)
+#define MCF_FEC_FECTFCR_FAE_MSK              (0x600000)
+#define MCF_FEC_FECTFCR_IP_MSK               (0xA00000)
+#define MCF_FEC_FECTFCR_GR(x)                (((x)&0x7)<<0x18|0x200000)
+#define MCF_FEC_FECTFCR_FRMEN                (0x8200000)
+#define MCF_FEC_FECTFCR_TIMER                (0x10200000)
+#define MCF_FEC_FECTFCR_WFR                  (0x20200000)
+#define MCF_FEC_FECTFCR_WCTL                 (0x40200000)
+
+/* Bit definitions and macros for MCF_FEC_FECTLRFP */
+#define MCF_FEC_FECTLRFP_LRFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTLWFP */
+#define MCF_FEC_FECTLWFP_LWFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFAR */
+#define MCF_FEC_FECTFAR_ALARM(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFRP */
+#define MCF_FEC_FECTFRP_READ(x)              (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFWP */
+#define MCF_FEC_FECTFWP_WRITE(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECFRST */
+#define MCF_FEC_FECFRST_RST_CTL              (0x1000000)
+#define MCF_FEC_FECFRST_SW_RST               (0x2000000)
+
+/* Bit definitions and macros for MCF_FEC_FECCTCWR */
+#define MCF_FEC_FECCTCWR_TFCW                (0x1000000)
+#define MCF_FEC_FECCTCWR_CRC                 (0x2000000)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */
+#define MCF_FEC_RMON_T_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */
+#define MCF_FEC_RMON_T_PACKETS_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */
+#define MCF_FEC_RMON_T_BC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */
+#define MCF_FEC_RMON_T_MC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */
+#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */
+#define MCF_FEC_RMON_T_UNDERSIZE_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */
+#define MCF_FEC_RMON_T_OVERSIZE_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */
+#define MCF_FEC_RMON_T_FRAG_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */
+#define MCF_FEC_RMON_T_JAB_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_COL */
+#define MCF_FEC_RMON_T_COL_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */
+#define MCF_FEC_RMON_T_P64_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */
+#define MCF_FEC_RMON_T_P65TO127_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */
+#define MCF_FEC_RMON_T_P128TO255_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */
+#define MCF_FEC_RMON_T_P256TO511_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */
+#define MCF_FEC_RMON_T_P512TO1023_Value(x)   (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */
+#define MCF_FEC_RMON_T_P1024TO2047_Value(x)  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */
+#define MCF_FEC_RMON_T_P_GTE2048_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */
+#define MCF_FEC_RMON_T_OCTETS_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */
+#define MCF_FEC_IEEE_T_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */
+#define MCF_FEC_IEEE_T_FRAME_OK_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */
+#define MCF_FEC_IEEE_T_1COL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */
+#define MCF_FEC_IEEE_T_MCOL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */
+#define MCF_FEC_IEEE_T_DEF_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */
+#define MCF_FEC_IEEE_T_LCOL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */
+#define MCF_FEC_IEEE_T_EXCOL_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */
+#define MCF_FEC_IEEE_T_MACERR_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */
+#define MCF_FEC_IEEE_T_CSERR_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */
+#define MCF_FEC_IEEE_T_SQE_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */
+#define MCF_FEC_IEEE_T_FDXFC_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */
+#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_DROP */
+#define MCF_FEC_RMON_R_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */
+#define MCF_FEC_RMON_R_PACKETS_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */
+#define MCF_FEC_RMON_R_BC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */
+#define MCF_FEC_RMON_R_MC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */
+#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */
+#define MCF_FEC_RMON_R_UNDERSIZE_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */
+#define MCF_FEC_RMON_R_OVERSIZE_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */
+#define MCF_FEC_RMON_R_FRAG_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */
+#define MCF_FEC_RMON_R_JAB_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */
+#define MCF_FEC_RMON_R_RESVD_0_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */
+#define MCF_FEC_RMON_R_P64_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */
+#define MCF_FEC_RMON_R_P65TO127_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */
+#define MCF_FEC_RMON_R_P128TO255_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */
+#define MCF_FEC_RMON_R_P256TO511_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */
+#define MCF_FEC_RMON_R_P512TO1023_Value(x)   (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */
+#define MCF_FEC_RMON_R_P1024TO2047_Value(x)  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */
+#define MCF_FEC_RMON_R_P_GTE2048_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */
+#define MCF_FEC_RMON_R_OCTETS_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */
+#define MCF_FEC_IEEE_R_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */
+#define MCF_FEC_IEEE_R_FRAME_OK_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */
+#define MCF_FEC_IEEE_R_CRC_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */
+#define MCF_FEC_IEEE_R_ALIGN_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */
+#define MCF_FEC_IEEE_R_MACERR_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */
+#define MCF_FEC_IEEE_R_FDXFC_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */
+#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+
+#endif /* __MCF5475_FEC_H__ */

BaS_codewarrior/firebeeV1/headers/MCF5475_GPIO.h

@@ -0,0 +1,543 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_GPIO_H__
+#define __MCF5475_GPIO_H__
+
+
+/*********************************************************************
+*
+* General Purpose I/O (GPIO)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPIO_PODR_FBCTL                  (*(vuint8 *)(&__MBAR[0xA00]))
+#define MCF_GPIO_PDDR_FBCTL                  (*(vuint8 *)(&__MBAR[0xA10]))
+#define MCF_GPIO_PPDSDR_FBCTL                (*(vuint8 *)(&__MBAR[0xA20]))
+#define MCF_GPIO_PCLRR_FBCTL                 (*(vuint8 *)(&__MBAR[0xA30]))
+
+#define MCF_GPIO_PODR_FBCS                   (*(vuint8 *)(&__MBAR[0xA01]))
+#define MCF_GPIO_PDDR_FBCS                   (*(vuint8 *)(&__MBAR[0xA11]))
+#define MCF_GPIO_PPDSDR_FBCS                 (*(vuint8 *)(&__MBAR[0xA21]))
+#define MCF_GPIO_PCLRR_FBCS                  (*(vuint8 *)(&__MBAR[0xA31]))
+
+#define MCF_GPIO_PODR_DMA                    (*(vuint8 *)(&__MBAR[0xA02]))
+#define MCF_GPIO_PDDR_DMA                    (*(vuint8 *)(&__MBAR[0xA12]))
+#define MCF_GPIO_PPDSDR_DMA                  (*(vuint8 *)(&__MBAR[0xA22]))
+#define MCF_GPIO_PCLRR_DMA                   (*(vuint8 *)(&__MBAR[0xA32]))
+
+#define MCF_GPIO_PODR_FEC0H                  (*(vuint8 *)(&__MBAR[0xA04]))
+#define MCF_GPIO_PDDR_FEC0H                  (*(vuint8 *)(&__MBAR[0xA14]))
+#define MCF_GPIO_PPDSDR_FEC0H                (*(vuint8 *)(&__MBAR[0xA24]))
+#define MCF_GPIO_PCLRR_FEC0H                 (*(vuint8 *)(&__MBAR[0xA34]))
+
+#define MCF_GPIO_PODR_FEC0L                  (*(vuint8 *)(&__MBAR[0xA05]))
+#define MCF_GPIO_PDDR_FEC0L                  (*(vuint8 *)(&__MBAR[0xA15]))
+#define MCF_GPIO_PPDSDR_FEC0L                (*(vuint8 *)(&__MBAR[0xA25]))
+#define MCF_GPIO_PCLRR_FEC0L                 (*(vuint8 *)(&__MBAR[0xA35]))
+
+#define MCF_GPIO_PODR_FEC1H                  (*(vuint8 *)(&__MBAR[0xA06]))
+#define MCF_GPIO_PDDR_FEC1H                  (*(vuint8 *)(&__MBAR[0xA16]))
+#define MCF_GPIO_PPDSDR_FEC1H                (*(vuint8 *)(&__MBAR[0xA26]))
+#define MCF_GPIO_PCLRR_FEC1H                 (*(vuint8 *)(&__MBAR[0xA36]))
+
+#define MCF_GPIO_PODR_FEC1L                  (*(vuint8 *)(&__MBAR[0xA07]))
+#define MCF_GPIO_PDDR_FEC1L                  (*(vuint8 *)(&__MBAR[0xA17]))
+#define MCF_GPIO_PPDSDR_FEC1L                (*(vuint8 *)(&__MBAR[0xA27]))
+#define MCF_GPIO_PCLRR_FEC1L                 (*(vuint8 *)(&__MBAR[0xA37]))
+
+#define MCF_GPIO_PODR_FECI2C                 (*(vuint8 *)(&__MBAR[0xA08]))
+#define MCF_GPIO_PDDR_FECI2C                 (*(vuint8 *)(&__MBAR[0xA18]))
+#define MCF_GPIO_PPDSDR_FECI2C               (*(vuint8 *)(&__MBAR[0xA28]))
+#define MCF_GPIO_PCLRR_FECI2C                (*(vuint8 *)(&__MBAR[0xA38]))
+
+#define MCF_GPIO_PODR_PCIBG                  (*(vuint8 *)(&__MBAR[0xA09]))
+#define MCF_GPIO_PDDR_PCIBG                  (*(vuint8 *)(&__MBAR[0xA19]))
+#define MCF_GPIO_PPDSDR_PCIBG                (*(vuint8 *)(&__MBAR[0xA29]))
+#define MCF_GPIO_PCLRR_PCIBG                 (*(vuint8 *)(&__MBAR[0xA39]))
+
+#define MCF_GPIO_PODR_PCIBR                  (*(vuint8 *)(&__MBAR[0xA0A]))
+#define MCF_GPIO_PDDR_PCIBR                  (*(vuint8 *)(&__MBAR[0xA1A]))
+#define MCF_GPIO_PPDSDR_PCIBR                (*(vuint8 *)(&__MBAR[0xA2A]))
+#define MCF_GPIO_PCLRR_PCIBR                 (*(vuint8 *)(&__MBAR[0xA3A]))
+
+#define MCF_GPIO2_PODR_PSC3PSC               (*(vuint8 *)(&__MBAR[0xA0C]))
+#define MCF_GPIO2_PDDR_PSC3PSC               (*(vuint8 *)(&__MBAR[0xA1C]))
+#define MCF_GPIO2_PPDSDR_PSC3PSC             (*(vuint8 *)(&__MBAR[0xA2C]))
+#define MCF_GPIO2_PCLRR_PSC3PSC              (*(vuint8 *)(&__MBAR[0xA3C]))
+
+#define MCF_GPIO0_PODR_PSC1PSC               (*(vuint8 *)(&__MBAR[0xA0D]))
+#define MCF_GPIO0_PDDR_PSC1PSC               (*(vuint8 *)(&__MBAR[0xA1D]))
+#define MCF_GPIO0_PPDSDR_PSC1PSC             (*(vuint8 *)(&__MBAR[0xA2D]))
+#define MCF_GPIO0_PCLRR_PSC1PSC              (*(vuint8 *)(&__MBAR[0xA3D]))
+
+#define MCF_GPIO_PODR_DSPI                   (*(vuint8 *)(&__MBAR[0xA0E]))
+#define MCF_GPIO_PDDR_DSPI                   (*(vuint8 *)(&__MBAR[0xA1E]))
+#define MCF_GPIO_PPDSDR_DSPI                 (*(vuint8 *)(&__MBAR[0xA2E]))
+#define MCF_GPIO_PCLRR_DSPI                  (*(vuint8 *)(&__MBAR[0xA3E]))
+
+
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0      (0x1)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1      (0x2)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2      (0x4)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3      (0x8)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4      (0x10)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5      (0x20)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6      (0x40)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0      (0x1)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1      (0x2)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2      (0x4)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3      (0x8)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4      (0x10)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5      (0x20)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6      (0x40)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0  (0x1)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1  (0x2)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2  (0x4)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3  (0x8)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4  (0x10)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5  (0x20)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6  (0x40)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0    (0x1)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1    (0x2)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2    (0x4)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3    (0x8)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4    (0x10)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5    (0x20)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6    (0x40)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS1        (0x2)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS2        (0x4)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS3        (0x8)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS4        (0x10)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS5        (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1        (0x2)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2        (0x4)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3        (0x8)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4        (0x10)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5        (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1    (0x2)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2    (0x4)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3    (0x8)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4    (0x10)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5    (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1      (0x2)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2      (0x4)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3      (0x8)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4      (0x10)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5      (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_DMA */
+#define MCF_GPIO_PODR_DMA_PODR_DMA0          (0x1)
+#define MCF_GPIO_PODR_DMA_PODR_DMA1          (0x2)
+#define MCF_GPIO_PODR_DMA_PODR_DMA2          (0x4)
+#define MCF_GPIO_PODR_DMA_PODR_DMA3          (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA0          (0x1)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA1          (0x2)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA2          (0x4)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA3          (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0      (0x1)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1      (0x2)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2      (0x4)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3      (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0        (0x1)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1        (0x2)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2        (0x4)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3        (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0      (0x1)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1      (0x2)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2      (0x4)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3      (0x8)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4      (0x10)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5      (0x20)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6      (0x40)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0      (0x1)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1      (0x2)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2      (0x4)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3      (0x8)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4      (0x10)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5      (0x20)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6      (0x40)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0    (0x1)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1    (0x2)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2    (0x4)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3    (0x8)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4    (0x10)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5    (0x20)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6    (0x40)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0      (0x1)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1      (0x2)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2      (0x4)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3      (0x8)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4      (0x10)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5      (0x20)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6      (0x40)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0      (0x1)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1      (0x2)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2      (0x4)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3      (0x8)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4      (0x10)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5      (0x20)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6      (0x40)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0    (0x1)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1    (0x2)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2    (0x4)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3    (0x8)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4    (0x10)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5    (0x20)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6    (0x40)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0      (0x1)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1      (0x2)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2      (0x4)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3      (0x8)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4      (0x10)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5      (0x20)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6      (0x40)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0      (0x1)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1      (0x2)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2      (0x4)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3      (0x8)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4      (0x10)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5      (0x20)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6      (0x40)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0    (0x1)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1    (0x2)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2    (0x4)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3    (0x8)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4    (0x10)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5    (0x20)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6    (0x40)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0      (0x1)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1      (0x2)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2      (0x4)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3      (0x8)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4      (0x10)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5      (0x20)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6      (0x40)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0      (0x1)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1      (0x2)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2      (0x4)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3      (0x8)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4      (0x10)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5      (0x20)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6      (0x40)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0    (0x1)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1    (0x2)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2    (0x4)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3    (0x8)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4    (0x10)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5    (0x20)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6    (0x40)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0    (0x1)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1    (0x2)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2    (0x4)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3    (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0    (0x1)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1    (0x2)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2    (0x4)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3    (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0  (0x1)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1  (0x2)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2  (0x4)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3  (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0      (0x1)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1      (0x2)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2      (0x4)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3      (0x8)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0      (0x1)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1      (0x2)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2      (0x4)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3      (0x8)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0  (0x1)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1  (0x2)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2  (0x4)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3  (0x8)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4  (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0    (0x1)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1    (0x2)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2    (0x4)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3    (0x8)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4    (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0      (0x1)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1      (0x2)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2      (0x4)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3      (0x8)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0      (0x1)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1      (0x2)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2      (0x4)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3      (0x8)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0  (0x1)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1  (0x2)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2  (0x4)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3  (0x8)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4  (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0    (0x1)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1    (0x2)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2    (0x4)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3    (0x8)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4    (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI0        (0x1)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI1        (0x2)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI2        (0x4)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI3        (0x8)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI4        (0x10)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI5        (0x20)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI6        (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0        (0x1)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1        (0x2)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2        (0x4)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3        (0x8)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4        (0x10)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5        (0x20)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6        (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0    (0x1)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1    (0x2)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2    (0x4)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3    (0x8)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4    (0x10)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5    (0x20)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6    (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0      (0x1)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1      (0x2)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2      (0x4)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3      (0x8)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4      (0x10)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5      (0x20)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6      (0x40)
+
+
+#endif /* __MCF5475_GPIO_H__ */

BaS_codewarrior/firebeeV1/headers/MCF5475_GPT.h

@@ -0,0 +1,100 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_GPT_H__
+#define __MCF5475_GPT_H__
+
+
+/*********************************************************************
+*
+* General Purpose Timers (GPT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPT0_GMS                         (*(vuint32*)(&__MBAR[0x800]))
+#define MCF_GPT0_GCIR                        (*(vuint32*)(&__MBAR[0x804]))
+#define MCF_GPT0_GPWM                        (*(vuint32*)(&__MBAR[0x808]))
+#define MCF_GPT0_GSR                         (*(vuint32*)(&__MBAR[0x80C]))
+
+#define MCF_GPT1_GMS                         (*(vuint32*)(&__MBAR[0x810]))
+#define MCF_GPT1_GCIR                        (*(vuint32*)(&__MBAR[0x814]))
+#define MCF_GPT1_GPWM                        (*(vuint32*)(&__MBAR[0x818]))
+#define MCF_GPT1_GSR                         (*(vuint32*)(&__MBAR[0x81C]))
+
+#define MCF_GPT2_GMS                         (*(vuint32*)(&__MBAR[0x820]))
+#define MCF_GPT2_GCIR                        (*(vuint32*)(&__MBAR[0x824]))
+#define MCF_GPT2_GPWM                        (*(vuint32*)(&__MBAR[0x828]))
+#define MCF_GPT2_GSR                         (*(vuint32*)(&__MBAR[0x82C]))
+
+#define MCF_GPT3_GMS                         (*(vuint32*)(&__MBAR[0x830]))
+#define MCF_GPT3_GCIR                        (*(vuint32*)(&__MBAR[0x834]))
+#define MCF_GPT3_GPWM                        (*(vuint32*)(&__MBAR[0x838]))
+#define MCF_GPT3_GSR                         (*(vuint32*)(&__MBAR[0x83C]))
+
+#define MCF_GPT_GMS(x)                       (*(vuint32*)(&__MBAR[0x800 + ((x)*0x10)]))
+#define MCF_GPT_GCIR(x)                      (*(vuint32*)(&__MBAR[0x804 + ((x)*0x10)]))
+#define MCF_GPT_GPWM(x)                      (*(vuint32*)(&__MBAR[0x808 + ((x)*0x10)]))
+#define MCF_GPT_GSR(x)                       (*(vuint32*)(&__MBAR[0x80C + ((x)*0x10)]))
+
+
+/* Bit definitions and macros for MCF_GPT_GMS */
+#define MCF_GPT_GMS_TMS(x)                   (((x)&0x7)<<0)
+#define MCF_GPT_GMS_TMS_DISABLE              (0)
+#define MCF_GPT_GMS_TMS_INCAPT               (0x1)
+#define MCF_GPT_GMS_TMS_OUTCAPT              (0x2)
+#define MCF_GPT_GMS_TMS_PWM                  (0x3)
+#define MCF_GPT_GMS_TMS_GPIO                 (0x4)
+#define MCF_GPT_GMS_GPIO(x)                  (((x)&0x3)<<0x4)
+#define MCF_GPT_GMS_GPIO_INPUT               (0)
+#define MCF_GPT_GMS_GPIO_OUTLO               (0x20)
+#define MCF_GPT_GMS_GPIO_OUTHI               (0x30)
+#define MCF_GPT_GMS_IEN                      (0x100)
+#define MCF_GPT_GMS_OD                       (0x200)
+#define MCF_GPT_GMS_SC                       (0x400)
+#define MCF_GPT_GMS_CE                       (0x1000)
+#define MCF_GPT_GMS_WDEN                     (0x8000)
+#define MCF_GPT_GMS_ICT(x)                   (((x)&0x3)<<0x10)
+#define MCF_GPT_GMS_ICT_ANY                  (0)
+#define MCF_GPT_GMS_ICT_RISE                 (0x10000)
+#define MCF_GPT_GMS_ICT_FALL                 (0x20000)
+#define MCF_GPT_GMS_ICT_PULSE                (0x30000)
+#define MCF_GPT_GMS_OCT(x)                   (((x)&0x3)<<0x14)
+#define MCF_GPT_GMS_OCT_FRCLOW               (0)
+#define MCF_GPT_GMS_OCT_PULSEHI              (0x100000)
+#define MCF_GPT_GMS_OCT_PULSELO              (0x200000)
+#define MCF_GPT_GMS_OCT_TOGGLE               (0x300000)
+#define MCF_GPT_GMS_OCPW(x)                  (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_GPT_GCIR */
+#define MCF_GPT_GCIR_CNT(x)                  (((x)&0xFFFF)<<0)
+#define MCF_GPT_GCIR_PRE(x)                  (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_GPT_GPWM */
+#define MCF_GPT_GPWM_LOAD                    (0x1)
+#define MCF_GPT_GPWM_PWMOP                   (0x100)
+#define MCF_GPT_GPWM_WIDTH(x)                (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_GPT_GSR */
+#define MCF_GPT_GSR_CAPT                     (0x1)
+#define MCF_GPT_GSR_COMP                     (0x2)
+#define MCF_GPT_GSR_PWMP                     (0x4)
+#define MCF_GPT_GSR_TEXP                     (0x8)
+#define MCF_GPT_GSR_PIN                      (0x100)
+#define MCF_GPT_GSR_OVF(x)                   (((x)&0x7)<<0xC)
+#define MCF_GPT_GSR_CAPTURE(x)               (((x)&0xFFFF)<<0x10)
+
+
+#endif /* __MCF5475_GPT_H__ */

BaS_codewarrior/firebeeV1/headers/MCF5475_I2C.h

@@ -0,0 +1,69 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_I2C_H__
+#define __MCF5475_I2C_H__
+
+
+/*********************************************************************
+*
+* I2C Module (I2C)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_I2C_I2ADR                        (*(vuint8 *)(&__MBAR[0x8F00]))
+#define MCF_I2C_I2FDR                        (*(vuint8 *)(&__MBAR[0x8F04]))
+#define MCF_I2C_I2CR                         (*(vuint8 *)(&__MBAR[0x8F08]))
+#define MCF_I2C_I2SR                         (*(vuint8 *)(&__MBAR[0x8F0C]))
+#define MCF_I2C_I2DR                         (*(vuint8 *)(&__MBAR[0x8F10]))
+#define MCF_I2C_I2ICR                        (*(vuint8 *)(&__MBAR[0x8F20]))
+
+
+
+/* Bit definitions and macros for MCF_I2C_I2ADR */
+#define MCF_I2C_I2ADR_ADR(x)                 (((x)&0x7F)<<0x1)
+
+/* Bit definitions and macros for MCF_I2C_I2FDR */
+#define MCF_I2C_I2FDR_IC(x)                  (((x)&0x3F)<<0)
+
+/* Bit definitions and macros for MCF_I2C_I2CR */
+#define MCF_I2C_I2CR_RSTA                    (0x4)
+#define MCF_I2C_I2CR_TXAK                    (0x8)
+#define MCF_I2C_I2CR_MTX                     (0x10)
+#define MCF_I2C_I2CR_MSTA                    (0x20)
+#define MCF_I2C_I2CR_IIEN                    (0x40)
+#define MCF_I2C_I2CR_IEN                     (0x80)
+
+/* Bit definitions and macros for MCF_I2C_I2SR */
+#define MCF_I2C_I2SR_RXAK                    (0x1)
+#define MCF_I2C_I2SR_IIF                     (0x2)
+#define MCF_I2C_I2SR_SRW                     (0x4)
+#define MCF_I2C_I2SR_IAL                     (0x10)
+#define MCF_I2C_I2SR_IBB                     (0x20)
+#define MCF_I2C_I2SR_IAAS                    (0x40)
+#define MCF_I2C_I2SR_ICF                     (0x80)
+
+/* Bit definitions and macros for MCF_I2C_I2DR */
+#define MCF_I2C_I2DR_DATA(x)                 (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_I2C_I2ICR */
+#define MCF_I2C_I2ICR_IE                     (0x1)
+#define MCF_I2C_I2ICR_RE                     (0x2)
+#define MCF_I2C_I2ICR_TE                     (0x4)
+#define MCF_I2C_I2ICR_BNBE                   (0x8)
+
+
+#endif /* __MCF5475_I2C_H__ */

BaS_codewarrior/firebeeV1/headers/MCF5475_INTC.h

@@ -0,0 +1,331 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_INTC_H__
+#define __MCF5475_INTC_H__
+
+
+/*********************************************************************
+*
+* Interrupt Controller (INTC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_INTC_IPRH                        (*(vuint32*)(&__MBAR[0x700]))
+#define MCF_INTC_IPRL                        (*(vuint32*)(&__MBAR[0x704]))
+#define MCF_INTC_IMRH                        (*(vuint32*)(&__MBAR[0x708]))
+#define MCF_INTC_IMRL                        (*(vuint32*)(&__MBAR[0x70C]))
+#define MCF_INTC_INTFRCH                     (*(vuint32*)(&__MBAR[0x710]))
+#define MCF_INTC_INTFRCL                     (*(vuint32*)(&__MBAR[0x714]))
+#define MCF_INTC_IRLR                        (*(vuint8 *)(&__MBAR[0x718]))
+#define MCF_INTC_IACKLPR                     (*(vuint8 *)(&__MBAR[0x719]))
+#define MCF_INTC_ICR01                       (*(vuint8 *)(&__MBAR[0x741]))
+#define MCF_INTC_ICR02                       (*(vuint8 *)(&__MBAR[0x742]))
+#define MCF_INTC_ICR03                       (*(vuint8 *)(&__MBAR[0x743]))
+#define MCF_INTC_ICR04                       (*(vuint8 *)(&__MBAR[0x744]))
+#define MCF_INTC_ICR05                       (*(vuint8 *)(&__MBAR[0x745]))
+#define MCF_INTC_ICR06                       (*(vuint8 *)(&__MBAR[0x746]))
+#define MCF_INTC_ICR07                       (*(vuint8 *)(&__MBAR[0x747]))
+#define MCF_INTC_ICR08                       (*(vuint8 *)(&__MBAR[0x748]))
+#define MCF_INTC_ICR09                       (*(vuint8 *)(&__MBAR[0x749]))
+#define MCF_INTC_ICR10                       (*(vuint8 *)(&__MBAR[0x74A]))
+#define MCF_INTC_ICR11                       (*(vuint8 *)(&__MBAR[0x74B]))
+#define MCF_INTC_ICR12                       (*(vuint8 *)(&__MBAR[0x74C]))
+#define MCF_INTC_ICR13                       (*(vuint8 *)(&__MBAR[0x74D]))
+#define MCF_INTC_ICR14                       (*(vuint8 *)(&__MBAR[0x74E]))
+#define MCF_INTC_ICR15                       (*(vuint8 *)(&__MBAR[0x74F]))
+#define MCF_INTC_ICR16                       (*(vuint8 *)(&__MBAR[0x750]))
+#define MCF_INTC_ICR17                       (*(vuint8 *)(&__MBAR[0x751]))
+#define MCF_INTC_ICR18                       (*(vuint8 *)(&__MBAR[0x752]))
+#define MCF_INTC_ICR19                       (*(vuint8 *)(&__MBAR[0x753]))
+#define MCF_INTC_ICR20                       (*(vuint8 *)(&__MBAR[0x754]))
+#define MCF_INTC_ICR21                       (*(vuint8 *)(&__MBAR[0x755]))
+#define MCF_INTC_ICR22                       (*(vuint8 *)(&__MBAR[0x756]))
+#define MCF_INTC_ICR23                       (*(vuint8 *)(&__MBAR[0x757]))
+#define MCF_INTC_ICR24                       (*(vuint8 *)(&__MBAR[0x758]))
+#define MCF_INTC_ICR25                       (*(vuint8 *)(&__MBAR[0x759]))
+#define MCF_INTC_ICR26                       (*(vuint8 *)(&__MBAR[0x75A]))
+#define MCF_INTC_ICR27                       (*(vuint8 *)(&__MBAR[0x75B]))
+#define MCF_INTC_ICR28                       (*(vuint8 *)(&__MBAR[0x75C]))
+#define MCF_INTC_ICR29                       (*(vuint8 *)(&__MBAR[0x75D]))
+#define MCF_INTC_ICR30                       (*(vuint8 *)(&__MBAR[0x75E]))
+#define MCF_INTC_ICR31                       (*(vuint8 *)(&__MBAR[0x75F]))
+#define MCF_INTC_ICR32                       (*(vuint8 *)(&__MBAR[0x760]))
+#define MCF_INTC_ICR33                       (*(vuint8 *)(&__MBAR[0x761]))
+#define MCF_INTC_ICR34                       (*(vuint8 *)(&__MBAR[0x762]))
+#define MCF_INTC_ICR35                       (*(vuint8 *)(&__MBAR[0x763]))
+#define MCF_INTC_ICR36                       (*(vuint8 *)(&__MBAR[0x764]))
+#define MCF_INTC_ICR37                       (*(vuint8 *)(&__MBAR[0x765]))
+#define MCF_INTC_ICR38                       (*(vuint8 *)(&__MBAR[0x766]))
+#define MCF_INTC_ICR39                       (*(vuint8 *)(&__MBAR[0x767]))
+#define MCF_INTC_ICR40                       (*(vuint8 *)(&__MBAR[0x768]))
+#define MCF_INTC_ICR41                       (*(vuint8 *)(&__MBAR[0x769]))
+#define MCF_INTC_ICR42                       (*(vuint8 *)(&__MBAR[0x76A]))
+#define MCF_INTC_ICR43                       (*(vuint8 *)(&__MBAR[0x76B]))
+#define MCF_INTC_ICR44                       (*(vuint8 *)(&__MBAR[0x76C]))
+#define MCF_INTC_ICR45                       (*(vuint8 *)(&__MBAR[0x76D]))
+#define MCF_INTC_ICR46                       (*(vuint8 *)(&__MBAR[0x76E]))
+#define MCF_INTC_ICR47                       (*(vuint8 *)(&__MBAR[0x76F]))
+#define MCF_INTC_ICR48                       (*(vuint8 *)(&__MBAR[0x770]))
+#define MCF_INTC_ICR49                       (*(vuint8 *)(&__MBAR[0x771]))
+#define MCF_INTC_ICR50                       (*(vuint8 *)(&__MBAR[0x772]))
+#define MCF_INTC_ICR51                       (*(vuint8 *)(&__MBAR[0x773]))
+#define MCF_INTC_ICR52                       (*(vuint8 *)(&__MBAR[0x774]))
+#define MCF_INTC_ICR53                       (*(vuint8 *)(&__MBAR[0x775]))
+#define MCF_INTC_ICR54                       (*(vuint8 *)(&__MBAR[0x776]))
+#define MCF_INTC_ICR55                       (*(vuint8 *)(&__MBAR[0x777]))
+#define MCF_INTC_ICR56                       (*(vuint8 *)(&__MBAR[0x778]))
+#define MCF_INTC_ICR57                       (*(vuint8 *)(&__MBAR[0x779]))
+#define MCF_INTC_ICR58                       (*(vuint8 *)(&__MBAR[0x77A]))
+#define MCF_INTC_ICR59                       (*(vuint8 *)(&__MBAR[0x77B]))
+#define MCF_INTC_ICR60                       (*(vuint8 *)(&__MBAR[0x77C]))
+#define MCF_INTC_ICR61                       (*(vuint8 *)(&__MBAR[0x77D]))
+#define MCF_INTC_ICR62                       (*(vuint8 *)(&__MBAR[0x77E]))
+#define MCF_INTC_ICR63                       (*(vuint8 *)(&__MBAR[0x77F]))
+#define MCF_INTC_SWIACK                      (*(vuint8 *)(&__MBAR[0x7E0]))
+#define MCF_INTC_L1IACK                      (*(vuint8 *)(&__MBAR[0x7E4]))
+#define MCF_INTC_L2IACK                      (*(vuint8 *)(&__MBAR[0x7E8]))
+#define MCF_INTC_L3IACK                      (*(vuint8 *)(&__MBAR[0x7EC]))
+#define MCF_INTC_L4IACK                      (*(vuint8 *)(&__MBAR[0x7F0]))
+#define MCF_INTC_L5IACK                      (*(vuint8 *)(&__MBAR[0x7F4]))
+#define MCF_INTC_L6IACK                      (*(vuint8 *)(&__MBAR[0x7F8]))
+#define MCF_INTC_L7IACK                      (*(vuint8 *)(&__MBAR[0x7FC]))
+#define MCF_INTC_ICR(x)                      (*(vuint8 *)(&__MBAR[0x741 + ((x-1)*0x1)]))
+#define MCF_INTC_LIACK(x)                    (*(vuint8 *)(&__MBAR[0x7E4 + ((x-1)*0x4)]))
+
+
+
+/* Bit definitions and macros for MCF_INTC_IPRH */
+#define MCF_INTC_IPRH_INT32                  (0x1)
+#define MCF_INTC_IPRH_INT33                  (0x2)
+#define MCF_INTC_IPRH_INT34                  (0x4)
+#define MCF_INTC_IPRH_INT35                  (0x8)
+#define MCF_INTC_IPRH_INT36                  (0x10)
+#define MCF_INTC_IPRH_INT37                  (0x20)
+#define MCF_INTC_IPRH_INT38                  (0x40)
+#define MCF_INTC_IPRH_INT39                  (0x80)
+#define MCF_INTC_IPRH_INT40                  (0x100)
+#define MCF_INTC_IPRH_INT41                  (0x200)
+#define MCF_INTC_IPRH_INT42                  (0x400)
+#define MCF_INTC_IPRH_INT43                  (0x800)
+#define MCF_INTC_IPRH_INT44                  (0x1000)
+#define MCF_INTC_IPRH_INT45                  (0x2000)
+#define MCF_INTC_IPRH_INT46                  (0x4000)
+#define MCF_INTC_IPRH_INT47                  (0x8000)
+#define MCF_INTC_IPRH_INT48                  (0x10000)
+#define MCF_INTC_IPRH_INT49                  (0x20000)
+#define MCF_INTC_IPRH_INT50                  (0x40000)
+#define MCF_INTC_IPRH_INT51                  (0x80000)
+#define MCF_INTC_IPRH_INT52                  (0x100000)
+#define MCF_INTC_IPRH_INT53                  (0x200000)
+#define MCF_INTC_IPRH_INT54                  (0x400000)
+#define MCF_INTC_IPRH_INT55                  (0x800000)
+#define MCF_INTC_IPRH_INT56                  (0x1000000)
+#define MCF_INTC_IPRH_INT57                  (0x2000000)
+#define MCF_INTC_IPRH_INT58                  (0x4000000)
+#define MCF_INTC_IPRH_INT59                  (0x8000000)
+#define MCF_INTC_IPRH_INT60                  (0x10000000)
+#define MCF_INTC_IPRH_INT61                  (0x20000000)
+#define MCF_INTC_IPRH_INT62                  (0x40000000)
+#define MCF_INTC_IPRH_INT63                  (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IPRL */
+#define MCF_INTC_IPRL_INT1                   (0x2)
+#define MCF_INTC_IPRL_INT2                   (0x4)
+#define MCF_INTC_IPRL_INT3                   (0x8)
+#define MCF_INTC_IPRL_INT4                   (0x10)
+#define MCF_INTC_IPRL_INT5                   (0x20)
+#define MCF_INTC_IPRL_INT6                   (0x40)
+#define MCF_INTC_IPRL_INT7                   (0x80)
+#define MCF_INTC_IPRL_INT8                   (0x100)
+#define MCF_INTC_IPRL_INT9                   (0x200)
+#define MCF_INTC_IPRL_INT10                  (0x400)
+#define MCF_INTC_IPRL_INT11                  (0x800)
+#define MCF_INTC_IPRL_INT12                  (0x1000)
+#define MCF_INTC_IPRL_INT13                  (0x2000)
+#define MCF_INTC_IPRL_INT14                  (0x4000)
+#define MCF_INTC_IPRL_INT15                  (0x8000)
+#define MCF_INTC_IPRL_INT16                  (0x10000)
+#define MCF_INTC_IPRL_INT17                  (0x20000)
+#define MCF_INTC_IPRL_INT18                  (0x40000)
+#define MCF_INTC_IPRL_INT19                  (0x80000)
+#define MCF_INTC_IPRL_INT20                  (0x100000)
+#define MCF_INTC_IPRL_INT21                  (0x200000)
+#define MCF_INTC_IPRL_INT22                  (0x400000)
+#define MCF_INTC_IPRL_INT23                  (0x800000)
+#define MCF_INTC_IPRL_INT24                  (0x1000000)
+#define MCF_INTC_IPRL_INT25                  (0x2000000)
+#define MCF_INTC_IPRL_INT26                  (0x4000000)
+#define MCF_INTC_IPRL_INT27                  (0x8000000)
+#define MCF_INTC_IPRL_INT28                  (0x10000000)
+#define MCF_INTC_IPRL_INT29                  (0x20000000)
+#define MCF_INTC_IPRL_INT30                  (0x40000000)
+#define MCF_INTC_IPRL_INT31                  (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IMRH */
+#define MCF_INTC_IMRH_INT_MASK32             (0x1)
+#define MCF_INTC_IMRH_INT_MASK33             (0x2)
+#define MCF_INTC_IMRH_INT_MASK34             (0x4)
+#define MCF_INTC_IMRH_INT_MASK35             (0x8)
+#define MCF_INTC_IMRH_INT_MASK36             (0x10)
+#define MCF_INTC_IMRH_INT_MASK37             (0x20)
+#define MCF_INTC_IMRH_INT_MASK38             (0x40)
+#define MCF_INTC_IMRH_INT_MASK39             (0x80)
+#define MCF_INTC_IMRH_INT_MASK40             (0x100)
+#define MCF_INTC_IMRH_INT_MASK41             (0x200)
+#define MCF_INTC_IMRH_INT_MASK42             (0x400)
+#define MCF_INTC_IMRH_INT_MASK43             (0x800)
+#define MCF_INTC_IMRH_INT_MASK44             (0x1000)
+#define MCF_INTC_IMRH_INT_MASK45             (0x2000)
+#define MCF_INTC_IMRH_INT_MASK46             (0x4000)
+#define MCF_INTC_IMRH_INT_MASK47             (0x8000)
+#define MCF_INTC_IMRH_INT_MASK48             (0x10000)
+#define MCF_INTC_IMRH_INT_MASK49             (0x20000)
+#define MCF_INTC_IMRH_INT_MASK50             (0x40000)
+#define MCF_INTC_IMRH_INT_MASK51             (0x80000)
+#define MCF_INTC_IMRH_INT_MASK52             (0x100000)
+#define MCF_INTC_IMRH_INT_MASK53             (0x200000)
+#define MCF_INTC_IMRH_INT_MASK54             (0x400000)
+#define MCF_INTC_IMRH_INT_MASK55             (0x800000)
+#define MCF_INTC_IMRH_INT_MASK56             (0x1000000)
+#define MCF_INTC_IMRH_INT_MASK57             (0x2000000)
+#define MCF_INTC_IMRH_INT_MASK58             (0x4000000)
+#define MCF_INTC_IMRH_INT_MASK59             (0x8000000)
+#define MCF_INTC_IMRH_INT_MASK60             (0x10000000)
+#define MCF_INTC_IMRH_INT_MASK61             (0x20000000)
+#define MCF_INTC_IMRH_INT_MASK62             (0x40000000)
+#define MCF_INTC_IMRH_INT_MASK63             (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IMRL */
+#define MCF_INTC_IMRL_MASKALL                (0x1)
+#define MCF_INTC_IMRL_INT_MASK1              (0x2)
+#define MCF_INTC_IMRL_INT_MASK2              (0x4)
+#define MCF_INTC_IMRL_INT_MASK3              (0x8)
+#define MCF_INTC_IMRL_INT_MASK4              (0x10)
+#define MCF_INTC_IMRL_INT_MASK5              (0x20)
+#define MCF_INTC_IMRL_INT_MASK6              (0x40)
+#define MCF_INTC_IMRL_INT_MASK7              (0x80)
+#define MCF_INTC_IMRL_INT_MASK8              (0x100)
+#define MCF_INTC_IMRL_INT_MASK9              (0x200)
+#define MCF_INTC_IMRL_INT_MASK10             (0x400)
+#define MCF_INTC_IMRL_INT_MASK11             (0x800)
+#define MCF_INTC_IMRL_INT_MASK12             (0x1000)
+#define MCF_INTC_IMRL_INT_MASK13             (0x2000)
+#define MCF_INTC_IMRL_INT_MASK14             (0x4000)
+#define MCF_INTC_IMRL_INT_MASK15             (0x8000)
+#define MCF_INTC_IMRL_INT_MASK16             (0x10000)
+#define MCF_INTC_IMRL_INT_MASK17             (0x20000)
+#define MCF_INTC_IMRL_INT_MASK18             (0x40000)
+#define MCF_INTC_IMRL_INT_MASK19             (0x80000)
+#define MCF_INTC_IMRL_INT_MASK20             (0x100000)
+#define MCF_INTC_IMRL_INT_MASK21             (0x200000)
+#define MCF_INTC_IMRL_INT_MASK22             (0x400000)
+#define MCF_INTC_IMRL_INT_MASK23             (0x800000)
+#define MCF_INTC_IMRL_INT_MASK24             (0x1000000)
+#define MCF_INTC_IMRL_INT_MASK25             (0x2000000)
+#define MCF_INTC_IMRL_INT_MASK26             (0x4000000)
+#define MCF_INTC_IMRL_INT_MASK27             (0x8000000)
+#define MCF_INTC_IMRL_INT_MASK28             (0x10000000)
+#define MCF_INTC_IMRL_INT_MASK29             (0x20000000)
+#define MCF_INTC_IMRL_INT_MASK30             (0x40000000)
+#define MCF_INTC_IMRL_INT_MASK31             (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_INTFRCH */
+#define MCF_INTC_INTFRCH_INTFRC32            (0x1)
+#define MCF_INTC_INTFRCH_INTFRC33            (0x2)
+#define MCF_INTC_INTFRCH_INTFRC34            (0x4)
+#define MCF_INTC_INTFRCH_INTFRC35            (0x8)
+#define MCF_INTC_INTFRCH_INTFRC36            (0x10)
+#define MCF_INTC_INTFRCH_INTFRC37            (0x20)
+#define MCF_INTC_INTFRCH_INTFRC38            (0x40)
+#define MCF_INTC_INTFRCH_INTFRC39            (0x80)
+#define MCF_INTC_INTFRCH_INTFRC40            (0x100)
+#define MCF_INTC_INTFRCH_INTFRC41            (0x200)
+#define MCF_INTC_INTFRCH_INTFRC42            (0x400)
+#define MCF_INTC_INTFRCH_INTFRC43            (0x800)
+#define MCF_INTC_INTFRCH_INTFRC44            (0x1000)
+#define MCF_INTC_INTFRCH_INTFRC45            (0x2000)
+#define MCF_INTC_INTFRCH_INTFRC46            (0x4000)
+#define MCF_INTC_INTFRCH_INTFRC47            (0x8000)
+#define MCF_INTC_INTFRCH_INTFRC48            (0x10000)
+#define MCF_INTC_INTFRCH_INTFRC49            (0x20000)
+#define MCF_INTC_INTFRCH_INTFRC50            (0x40000)
+#define MCF_INTC_INTFRCH_INTFRC51            (0x80000)
+#define MCF_INTC_INTFRCH_INTFRC52            (0x100000)
+#define MCF_INTC_INTFRCH_INTFRC53            (0x200000)
+#define MCF_INTC_INTFRCH_INTFRC54            (0x400000)
+#define MCF_INTC_INTFRCH_INTFRC55            (0x800000)
+#define MCF_INTC_INTFRCH_INTFRC56            (0x1000000)
+#define MCF_INTC_INTFRCH_INTFRC57            (0x2000000)
+#define MCF_INTC_INTFRCH_INTFRC58            (0x4000000)
+#define MCF_INTC_INTFRCH_INTFRC59            (0x8000000)
+#define MCF_INTC_INTFRCH_INTFRC60            (0x10000000)
+#define MCF_INTC_INTFRCH_INTFRC61            (0x20000000)
+#define MCF_INTC_INTFRCH_INTFRC62            (0x40000000)
+#define MCF_INTC_INTFRCH_INTFRC63            (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_INTFRCL */
+#define MCF_INTC_INTFRCL_INTFRC1             (0x2)
+#define MCF_INTC_INTFRCL_INTFRC2             (0x4)
+#define MCF_INTC_INTFRCL_INTFRC3             (0x8)
+#define MCF_INTC_INTFRCL_INTFRC4             (0x10)
+#define MCF_INTC_INTFRCL_INTFRC5             (0x20)
+#define MCF_INTC_INTFRCL_INTFRC6             (0x40)
+#define MCF_INTC_INTFRCL_INTFRC7             (0x80)
+#define MCF_INTC_INTFRCL_INTFRC8             (0x100)
+#define MCF_INTC_INTFRCL_INTFRC9             (0x200)
+#define MCF_INTC_INTFRCL_INTFRC10            (0x400)
+#define MCF_INTC_INTFRCL_INTFRC11            (0x800)
+#define MCF_INTC_INTFRCL_INTFRC12            (0x1000)
+#define MCF_INTC_INTFRCL_INTFRC13            (0x2000)
+#define MCF_INTC_INTFRCL_INTFRC14            (0x4000)
+#define MCF_INTC_INTFRCL_INTFRC15            (0x8000)
+#define MCF_INTC_INTFRCL_INTFRC16            (0x10000)
+#define MCF_INTC_INTFRCL_INTFRC17            (0x20000)
+#define MCF_INTC_INTFRCL_INTFRC18            (0x40000)
+#define MCF_INTC_INTFRCL_INTFRC19            (0x80000)
+#define MCF_INTC_INTFRCL_INTFRC20            (0x100000)
+#define MCF_INTC_INTFRCL_INTFRC21            (0x200000)
+#define MCF_INTC_INTFRCL_INTFRC22            (0x400000)
+#define MCF_INTC_INTFRCL_INTFRC23            (0x800000)
+#define MCF_INTC_INTFRCL_INTFRC24            (0x1000000)
+#define MCF_INTC_INTFRCL_INTFRC25            (0x2000000)
+#define MCF_INTC_INTFRCL_INTFRC26            (0x4000000)
+#define MCF_INTC_INTFRCL_INTFRC27            (0x8000000)
+#define MCF_INTC_INTFRCL_INTFRC28            (0x10000000)
+#define MCF_INTC_INTFRCL_INTFRC29            (0x20000000)
+#define MCF_INTC_INTFRCL_INTFRC30            (0x40000000)
+#define MCF_INTC_INTFRCL_INTFRC31            (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IRLR */
+#define MCF_INTC_IRLR_IRQ(x)                 (((x)&0x7F)<<0x1)
+
+/* Bit definitions and macros for MCF_INTC_IACKLPR */
+#define MCF_INTC_IACKLPR_PRI(x)              (((x)&0xF)<<0)
+#define MCF_INTC_IACKLPR_LEVEL(x)            (((x)&0x7)<<0x4)
+
+/* Bit definitions and macros for MCF_INTC_ICR */
+#define MCF_INTC_ICR_IP(x)                   (((x)&0x7)<<0)
+#define MCF_INTC_ICR_IL(x)                   (((x)&0x7)<<0x3)
+
+/* Bit definitions and macros for MCF_INTC_SWIACK */
+#define MCF_INTC_SWIACK_VECTOR(x)            (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_INTC_LIACK */
+#define MCF_INTC_LIACK_VECTOR(x)             (((x)&0xFF)<<0)
+
+
+#endif /* __MCF5475_INTC_H__ */

BaS_codewarrior/firebeeV1/headers/MCF5475_MMU.h

@@ -0,0 +1,77 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_MMU_H__
+#define __MCF5475_MMU_H__
+
+
+/*********************************************************************
+*
+* Memory Management Unit (MMU)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_MMU_MMUCR                        (*(vuint32*)(&__MMUBAR[0]))
+#define MCF_MMU_MMUOR                        (*(vuint32*)(&__MMUBAR[0x4]))
+#define MCF_MMU_MMUSR                        (*(vuint32*)(&__MMUBAR[0x8]))
+#define MCF_MMU_MMUAR                        (*(vuint32*)(&__MMUBAR[0x10]))
+#define MCF_MMU_MMUTR                        (*(vuint32*)(&__MMUBAR[0x14]))
+#define MCF_MMU_MMUDR                        (*(vuint32*)(&__MMUBAR[0x18]))
+
+
+/* Bit definitions and macros for MCF_MMU_MMUCR */
+#define MCF_MMU_MMUCR_EN                     (0x1)
+#define MCF_MMU_MMUCR_ASM                    (0x2)
+
+/* Bit definitions and macros for MCF_MMU_MMUOR */
+#define MCF_MMU_MMUOR_UAA                    (0x1)
+#define MCF_MMU_MMUOR_ACC                    (0x2)
+#define MCF_MMU_MMUOR_RW                     (0x4)
+#define MCF_MMU_MMUOR_ADR                    (0x8)
+#define MCF_MMU_MMUOR_ITLB                   (0x10)
+#define MCF_MMU_MMUOR_CAS                    (0x20)
+#define MCF_MMU_MMUOR_CNL                    (0x40)
+#define MCF_MMU_MMUOR_CA                     (0x80)
+#define MCF_MMU_MMUOR_STLB                   (0x100)
+#define MCF_MMU_MMUOR_AA(x)                  (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_MMU_MMUSR */
+#define MCF_MMU_MMUSR_HIT                    (0x2)
+#define MCF_MMU_MMUSR_WF                     (0x8)
+#define MCF_MMU_MMUSR_RF                     (0x10)
+#define MCF_MMU_MMUSR_SPF                    (0x20)
+
+/* Bit definitions and macros for MCF_MMU_MMUAR */
+#define MCF_MMU_MMUAR_FA(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_MMU_MMUTR */
+#define MCF_MMU_MMUTR_V                      (0x1)
+#define MCF_MMU_MMUTR_SG                     (0x2)
+#define MCF_MMU_MMUTR_ID(x)                  (((x)&0xFF)<<0x2)
+#define MCF_MMU_MMUTR_VA(x)                  (((x)&0x3FFFFF)<<0xA)
+
+/* Bit definitions and macros for MCF_MMU_MMUDR */
+#define MCF_MMU_MMUDR_LK                     (0x2)
+#define MCF_MMU_MMUDR_X                      (0x4)
+#define MCF_MMU_MMUDR_W                      (0x8)
+#define MCF_MMU_MMUDR_R                      (0x10)
+#define MCF_MMU_MMUDR_SP                     (0x20)
+#define MCF_MMU_MMUDR_CM(x)                  (((x)&0x3)<<0x6)
+#define MCF_MMU_MMUDR_SZ(x)                  (((x)&0x3)<<0x8)
+#define MCF_MMU_MMUDR_PA(x)                  (((x)&0x3FFFFF)<<0xA)
+
+
+#endif /* __MCF5475_MMU_H__ */

BaS_codewarrior/firebeeV1/headers/MCF5475_PAD.h

@@ -0,0 +1,233 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PAD_H__
+#define __MCF5475_PAD_H__
+
+
+/*********************************************************************
+*
+* Common GPIO
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PAD_PAR_FBCTL                    (*(vuint16*)(&__MBAR[0xA40]))
+#define MCF_PAD_PAR_FBCS                     (*(vuint8 *)(&__MBAR[0xA42]))
+#define MCF_PAD_PAR_DMA                      (*(vuint8 *)(&__MBAR[0xA43]))
+#define MCF_PAD_PAR_FECI2CIRQ                (*(vuint16*)(&__MBAR[0xA44]))
+#define MCF_PAD_PAR_PCIBG                    (*(vuint16*)(&__MBAR[0xA48]))
+#define MCF_PAD_PAR_PCIBR                    (*(vuint16*)(&__MBAR[0xA4A]))
+#define MCF_PAD_PAR_PSC3                     (*(vuint8 *)(&__MBAR[0xA4C]))
+#define MCF_PAD_PAR_PSC2                     (*(vuint8 *)(&__MBAR[0xA4D]))
+#define MCF_PAD_PAR_PSC1                     (*(vuint8 *)(&__MBAR[0xA4E]))
+#define MCF_PAD_PAR_PSC0                     (*(vuint8 *)(&__MBAR[0xA4F]))
+#define MCF_PAD_PAR_DSPI                     (*(vuint16*)(&__MBAR[0xA50]))
+#define MCF_PAD_PAR_TIMER                    (*(vuint8 *)(&__MBAR[0xA52]))
+
+
+/* Bit definitions and macros for MCF_PAD_PAR_FBCTL */
+#define MCF_PAD_PAR_FBCTL_PAR_ALE(x)         (((x)&0x3)<<0)
+#define MCF_PAD_PAR_FBCTL_PAR_ALE_GPIO       (0)
+#define MCF_PAD_PAR_FBCTL_PAR_ALE_TBST       (0x2)
+#define MCF_PAD_PAR_FBCTL_PAR_ALE_ALE        (0x3)
+#define MCF_PAD_PAR_FBCTL_PAR_TA             (0x4)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB_GPIO       (0)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB_TBST       (0x20)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB_RW         (0x30)
+#define MCF_PAD_PAR_FBCTL_PAR_OE             (0x40)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE0           (0x100)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE1           (0x400)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE2           (0x1000)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE3           (0x4000)
+
+/* Bit definitions and macros for MCF_PAD_PAR_FBCS */
+#define MCF_PAD_PAR_FBCS_PAR_CS1             (0x2)
+#define MCF_PAD_PAR_FBCS_PAR_CS2             (0x4)
+#define MCF_PAD_PAR_FBCS_PAR_CS3             (0x8)
+#define MCF_PAD_PAR_FBCS_PAR_CS4             (0x10)
+#define MCF_PAD_PAR_FBCS_PAR_CS5             (0x20)
+
+/* Bit definitions and macros for MCF_PAD_PAR_DMA */
+#define MCF_PAD_PAR_DMA_PAR_DREQ0(x)         (((x)&0x3)<<0)
+#define MCF_PAD_PAR_DMA_PAR_DREQ0_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DREQ0_TIN0       (0x2)
+#define MCF_PAD_PAR_DMA_PAR_DREQ0_DREQ0      (0x3)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1(x)         (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_IRQ1       (0x4)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_TIN1       (0x8)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_DREQ1      (0xC)
+#define MCF_PAD_PAR_DMA_PAR_DACK0(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_DMA_PAR_DACK0_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DACK0_TOUT0      (0x20)
+#define MCF_PAD_PAR_DMA_PAR_DACK0_DACK0      (0x30)
+#define MCF_PAD_PAR_DMA_PAR_DACK1(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_DMA_PAR_DACK1_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DACK1_TOUT1      (0x80)
+#define MCF_PAD_PAR_DMA_PAR_DACK1_DACK1      (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_FECI2CIRQ */
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ5       (0x1)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ6       (0x2)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_SCL        (0x4)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_SDA        (0x8)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC(x)   (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_SCL  (0x80)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC (0xC0)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO(x)  (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x200)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO (0x300)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MII      (0x400)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E17        (0x800)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC      (0x1000)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO     (0x2000)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII      (0x4000)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E07        (0x8000)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PCIBG */
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0(x)      (((x)&0x3)<<0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_TOUT0   (0x2)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0  (0x3)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1(x)      (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_TOUT1   (0x8)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1  (0xC)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2(x)      (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_TOUT2   (0x20)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2  (0x30)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3(x)      (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_TOUT3   (0x80)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3  (0xC0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4(x)      (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST    (0x200)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4  (0x300)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PCIBR */
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0(x)      (((x)&0x3)<<0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_TIN0    (0x2)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0  (0x3)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1(x)      (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_TIN1    (0x8)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1  (0xC)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2(x)      (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_TIN2    (0x20)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2  (0x30)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3(x)      (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_TIN3    (0x80)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3  (0xC0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4(x)      (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4    (0x200)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4  (0x300)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC3 */
+#define MCF_PAD_PAR_PSC3_PAR_TXD3            (0x4)
+#define MCF_PAD_PAR_PSC3_PAR_RXD3            (0x8)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3_GPIO       (0)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3_RTS        (0x30)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3_GPIO       (0)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC2 */
+#define MCF_PAD_PAR_PSC2_PAR_TXD2            (0x4)
+#define MCF_PAD_PAR_PSC2_PAR_RXD2            (0x8)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2_GPIO       (0)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2_RTS        (0x30)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2_GPIO       (0)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC1 */
+#define MCF_PAD_PAR_PSC1_PAR_TXD1            (0x4)
+#define MCF_PAD_PAR_PSC1_PAR_RXD1            (0x8)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1_GPIO       (0)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1_RTS        (0x30)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1_GPIO       (0)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC0 */
+#define MCF_PAD_PAR_PSC0_PAR_TXD0            (0x4)
+#define MCF_PAD_PAR_PSC0_PAR_RXD0            (0x8)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0_GPIO       (0)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0_RTS        (0x30)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0_GPIO       (0)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_DSPI */
+#define MCF_PAD_PAR_DSPI_PAR_SOUT(x)         (((x)&0x3)<<0)
+#define MCF_PAD_PAR_DSPI_PAR_SOUT_GPIO       (0)
+#define MCF_PAD_PAR_DSPI_PAR_SOUT_TXD        (0x2)
+#define MCF_PAD_PAR_DSPI_PAR_SOUT_SOUT       (0x3)
+#define MCF_PAD_PAR_DSPI_PAR_SIN(x)          (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_DSPI_PAR_SIN_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_SIN_RXD         (0x8)
+#define MCF_PAD_PAR_DSPI_PAR_SIN_SIN         (0xC)
+#define MCF_PAD_PAR_DSPI_PAR_SCK(x)          (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_BCLK        (0x10)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_CTS         (0x20)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_SCK         (0x30)
+#define MCF_PAD_PAR_DSPI_PAR_CS0(x)          (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_FSYNC       (0x40)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_RTS         (0x80)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_DSPICS0     (0xC0)
+#define MCF_PAD_PAR_DSPI_PAR_CS2(x)          (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_DSPI_PAR_CS2_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_CS2_TOUT2       (0x200)
+#define MCF_PAD_PAR_DSPI_PAR_CS2_DSPICS2     (0x300)
+#define MCF_PAD_PAR_DSPI_PAR_CS3(x)          (((x)&0x3)<<0xA)
+#define MCF_PAD_PAR_DSPI_PAR_CS3_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_CS3_TOUT3       (0x800)
+#define MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3     (0xC00)
+#define MCF_PAD_PAR_DSPI_PAR_CS5             (0x1000)
+
+/* Bit definitions and macros for MCF_PAD_PAR_TIMER */
+#define MCF_PAD_PAR_TIMER_PAR_TOUT2          (0x1)
+#define MCF_PAD_PAR_TIMER_PAR_TIN2(x)        (((x)&0x3)<<0x1)
+#define MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2      (0x4)
+#define MCF_PAD_PAR_TIMER_PAR_TIN2_TIN2      (0x6)
+#define MCF_PAD_PAR_TIMER_PAR_TOUT3          (0x8)
+#define MCF_PAD_PAR_TIMER_PAR_TIN3(x)        (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_TIMER_PAR_TIN3_IRQ3      (0x20)
+#define MCF_PAD_PAR_TIMER_PAR_TIN3_TIN3      (0x30)
+
+
+#endif /* __MCF5475_PAD_H__ */

BaS_codewarrior/firebeeV1/headers/MCF5475_PCI.h

@@ -0,0 +1,376 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PCI_H__
+#define __MCF5475_PCI_H__
+
+
+/*********************************************************************
+*
+* PCI Bus Controller (PCI)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PCI_PCIIDR                       (*(vuint32*)(&__MBAR[0xB00]))
+#define MCF_PCI_PCISCR                       (*(vuint32*)(&__MBAR[0xB04]))
+#define MCF_PCI_PCICCRIR                     (*(vuint32*)(&__MBAR[0xB08]))
+#define MCF_PCI_PCICR1                       (*(vuint32*)(&__MBAR[0xB0C]))
+#define MCF_PCI_PCIBAR0                      (*(vuint32*)(&__MBAR[0xB10]))
+#define MCF_PCI_PCIBAR1                      (*(vuint32*)(&__MBAR[0xB14]))
+#define MCF_PCI_PCICCPR                      (*(vuint32*)(&__MBAR[0xB28]))
+#define MCF_PCI_PCISID                       (*(vuint32*)(&__MBAR[0xB2C]))
+#define MCF_PCI_PCICR2                       (*(vuint32*)(&__MBAR[0xB3C]))
+#define MCF_PCI_PCIGSCR                      (*(vuint32*)(&__MBAR[0xB60]))
+#define MCF_PCI_PCITBATR0                    (*(vuint32*)(&__MBAR[0xB64]))
+#define MCF_PCI_PCITBATR1                    (*(vuint32*)(&__MBAR[0xB68]))
+#define MCF_PCI_PCITCR                       (*(vuint32*)(&__MBAR[0xB6C]))
+#define MCF_PCI_PCIIW0BTAR                   (*(vuint32*)(&__MBAR[0xB70]))
+#define MCF_PCI_PCIIW1BTAR                   (*(vuint32*)(&__MBAR[0xB74]))
+#define MCF_PCI_PCIIW2BTAR                   (*(vuint32*)(&__MBAR[0xB78]))
+#define MCF_PCI_PCIIWCR                      (*(vuint32*)(&__MBAR[0xB80]))
+#define MCF_PCI_PCIICR                       (*(vuint32*)(&__MBAR[0xB84]))
+#define MCF_PCI_PCIISR                       (*(vuint32*)(&__MBAR[0xB88]))
+#define MCF_PCI_PCICAR                       (*(vuint32*)(&__MBAR[0xBF8]))
+#define MCF_PCI_PCITPSR                      (*(vuint32*)(&__MBAR[0x8400]))
+#define MCF_PCI_PCITSAR                      (*(vuint32*)(&__MBAR[0x8404]))
+#define MCF_PCI_PCITTCR                      (*(vuint32*)(&__MBAR[0x8408]))
+#define MCF_PCI_PCITER                       (*(vuint32*)(&__MBAR[0x840C]))
+#define MCF_PCI_PCITNAR                      (*(vuint32*)(&__MBAR[0x8410]))
+#define MCF_PCI_PCITLWR                      (*(vuint32*)(&__MBAR[0x8414]))
+#define MCF_PCI_PCITDCR                      (*(vuint32*)(&__MBAR[0x8418]))
+#define MCF_PCI_PCITSR                       (*(vuint32*)(&__MBAR[0x841C]))
+#define MCF_PCI_PCITFDR                      (*(vuint32*)(&__MBAR[0x8440]))
+#define MCF_PCI_PCITFSR                      (*(vuint32*)(&__MBAR[0x8444]))
+#define MCF_PCI_PCITFCR                      (*(vuint32*)(&__MBAR[0x8448]))
+#define MCF_PCI_PCITFAR                      (*(vuint32*)(&__MBAR[0x844C]))
+#define MCF_PCI_PCITFRPR                     (*(vuint32*)(&__MBAR[0x8450]))
+#define MCF_PCI_PCITFWPR                     (*(vuint32*)(&__MBAR[0x8454]))
+#define MCF_PCI_PCIRPSR                      (*(vuint32*)(&__MBAR[0x8480]))
+#define MCF_PCI_PCIRSAR                      (*(vuint32*)(&__MBAR[0x8484]))
+#define MCF_PCI_PCIRTCR                      (*(vuint32*)(&__MBAR[0x8488]))
+#define MCF_PCI_PCIRER                       (*(vuint32*)(&__MBAR[0x848C]))
+#define MCF_PCI_PCIRNAR                      (*(vuint32*)(&__MBAR[0x8490]))
+#define MCF_PCI_PCIRDCR                      (*(vuint32*)(&__MBAR[0x8498]))
+#define MCF_PCI_PCIRSR                       (*(vuint32*)(&__MBAR[0x849C]))
+#define MCF_PCI_PCIRFDR                      (*(vuint32*)(&__MBAR[0x84C0]))
+#define MCF_PCI_PCIRFSR                      (*(vuint32*)(&__MBAR[0x84C4]))
+#define MCF_PCI_PCIRFCR                      (*(vuint32*)(&__MBAR[0x84C8]))
+#define MCF_PCI_PCIRFAR                      (*(vuint32*)(&__MBAR[0x84CC]))
+#define MCF_PCI_PCIRFRPR                     (*(vuint32*)(&__MBAR[0x84D0]))
+#define MCF_PCI_PCIRFWPR                     (*(vuint32*)(&__MBAR[0x84D4]))
+
+
+/* Bit definitions and macros for MCF_PCI_PCIIDR */
+#define MCF_PCI_PCIIDR_VENDORID(x)           (((x)&0xFFFF)<<0)
+#define MCF_PCI_PCIIDR_DEVICEID(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCISCR */
+#define MCF_PCI_PCISCR_IO                    (0x1)
+#define MCF_PCI_PCISCR_M                     (0x2)
+#define MCF_PCI_PCISCR_B                     (0x4)
+#define MCF_PCI_PCISCR_SP                    (0x8)
+#define MCF_PCI_PCISCR_MW                    (0x10)
+#define MCF_PCI_PCISCR_V                     (0x20)
+#define MCF_PCI_PCISCR_PER                   (0x40)
+#define MCF_PCI_PCISCR_ST                    (0x80)
+#define MCF_PCI_PCISCR_S                     (0x100)
+#define MCF_PCI_PCISCR_F                     (0x200)
+#define MCF_PCI_PCISCR_C                     (0x100000)
+#define MCF_PCI_PCISCR_66M                   (0x200000)
+#define MCF_PCI_PCISCR_R                     (0x400000)
+#define MCF_PCI_PCISCR_FC                    (0x800000)
+#define MCF_PCI_PCISCR_DP                    (0x1000000)
+#define MCF_PCI_PCISCR_DT(x)                 (((x)&0x3)<<0x19)
+#define MCF_PCI_PCISCR_TS                    (0x8000000)
+#define MCF_PCI_PCISCR_TR                    (0x10000000)
+#define MCF_PCI_PCISCR_MA                    (0x20000000)
+#define MCF_PCI_PCISCR_SE                    (0x40000000)
+#define MCF_PCI_PCISCR_PE                    (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCICCRIR */
+#define MCF_PCI_PCICCRIR_REVISIONID(x)       (((x)&0xFF)<<0)
+#define MCF_PCI_PCICCRIR_CLASSCODE(x)        (((x)&0xFFFFFF)<<0x8)
+
+/* Bit definitions and macros for MCF_PCI_PCICR1 */
+#define MCF_PCI_PCICR1_CACHELINESIZE(x)      (((x)&0xFF)<<0)
+#define MCF_PCI_PCICR1_LATTIMER(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCICR1_HEADERTYPE(x)         (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCICR1_BIST(x)               (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIBAR0 */
+#define MCF_PCI_PCIBAR0_IOM                  (0x1)
+#define MCF_PCI_PCIBAR0_RANGE(x)             (((x)&0x3)<<0x1)
+#define MCF_PCI_PCIBAR0_PREF                 (0x8)
+#define MCF_PCI_PCIBAR0_BAR0(x)              (((x)&0x3FFF)<<0x12)
+
+/* Bit definitions and macros for MCF_PCI_PCIBAR1 */
+#define MCF_PCI_PCIBAR1_IOM                  (0x1)
+#define MCF_PCI_PCIBAR1_RANGE(x)             (((x)&0x3)<<0x1)
+#define MCF_PCI_PCIBAR1_PREF                 (0x8)
+#define MCF_PCI_PCIBAR1_BAR1(x)              (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_PCI_PCICCPR */
+#define MCF_PCI_PCICCPR_PCICCP(x)            (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCISID */
+#define MCF_PCI_PCISID_VENDORID(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCICR2 */
+#define MCF_PCI_PCICR2_INTLINE(x)            (((x)&0xFF)<<0)
+#define MCF_PCI_PCICR2_INTPIN(x)             (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCICR2_MINGNT(x)             (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCICR2_MAXLAT(x)             (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIGSCR */
+#define MCF_PCI_PCIGSCR_PR                   (0x1)
+#define MCF_PCI_PCIGSCR_SEE                  (0x1000)
+#define MCF_PCI_PCIGSCR_PEE                  (0x2000)
+#define MCF_PCI_PCIGSCR_CLKINRESERVED(x)     (((x)&0x7)<<0x10)
+#define MCF_PCI_PCIGSCR_XLB2CLKIN(x)         (((x)&0x7)<<0x18)
+#define MCF_PCI_PCIGSCR_SE                   (0x10000000)
+#define MCF_PCI_PCIGSCR_PE                   (0x20000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITBATR0 */
+#define MCF_PCI_PCITBATR0_EN                 (0x1)
+#define MCF_PCI_PCITBATR0_BAT0(x)            (((x)&0x3FFF)<<0x12)
+
+/* Bit definitions and macros for MCF_PCI_PCITBATR1 */
+#define MCF_PCI_PCITBATR1_EN                 (0x1)
+#define MCF_PCI_PCITBATR1_BAT1(x)            (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_PCI_PCITCR */
+#define MCF_PCI_PCITCR_P                     (0x10000)
+#define MCF_PCI_PCITCR_LD                    (0x1000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */
+#define MCF_PCI_PCIIW0BTAR_WTA0(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCIIW0BTAR_WAM0(x)           (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIIW0BTAR_WBA0(x)           (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */
+#define MCF_PCI_PCIIW1BTAR_WTA1(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCIIW1BTAR_WAM1(x)           (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIIW1BTAR_WBA1(x)           (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */
+#define MCF_PCI_PCIIW2BTAR_WTA2(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCIIW2BTAR_WAM2(x)           (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIIW2BTAR_WBA2(x)           (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIIWCR */
+#define MCF_PCI_PCIIWCR_WINCTRL2_E           (0x100)
+#define MCF_PCI_PCIIWCR_WINCTRL2_PRC(x)      (((x)&0x3)<<0x9)
+#define MCF_PCI_PCIIWCR_WINCTRL2_IOM         (0x800)
+#define MCF_PCI_PCIIWCR_WINCTRL1_E           (0x10000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_PRC(x)      (((x)&0x3)<<0x11)
+#define MCF_PCI_PCIIWCR_WINCTRL1_IOM         (0x80000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_E           (0x1000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_PRC(x)      (((x)&0x3)<<0x19)
+#define MCF_PCI_PCIIWCR_WINCTRL0_IOM         (0x8000000)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD     (0x100)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE   (0x300)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL    (0x500)
+#define MCF_PCI_PCIIWCR_WINCTRL2_IO          (0x900)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD     (0x10000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE   (0x30000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL    (0x50000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_IO          (0x90000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD     (0x1000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE   (0x3000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL    (0x5000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_IO          (0x9000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIICR */
+#define MCF_PCI_PCIICR_MAXRETRY(x)           (((x)&0xFF)<<0)
+#define MCF_PCI_PCIICR_TAE                   (0x1000000)
+#define MCF_PCI_PCIICR_IAE                   (0x2000000)
+#define MCF_PCI_PCIICR_REE                   (0x4000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIISR */
+#define MCF_PCI_PCIISR_TA                    (0x1000000)
+#define MCF_PCI_PCIISR_IA                    (0x2000000)
+#define MCF_PCI_PCIISR_RE                    (0x4000000)
+
+/* Bit definitions and macros for MCF_PCI_PCICAR */
+#define MCF_PCI_PCICAR_DWORD(x)              (((x)&0x3F)<<0x2)
+#define MCF_PCI_PCICAR_FUNCNUM(x)            (((x)&0x7)<<0x8)
+#define MCF_PCI_PCICAR_DEVNUM(x)             (((x)&0x1F)<<0xB)
+#define MCF_PCI_PCICAR_BUSNUM(x)             (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCICAR_E                     (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITPSR */
+#define MCF_PCI_PCITPSR_PKTSIZE(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCITSAR */
+#define MCF_PCI_PCITSAR_STARTADD(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITTCR */
+#define MCF_PCI_PCITTCR_DI                   (0x1)
+#define MCF_PCI_PCITTCR_W                    (0x10)
+#define MCF_PCI_PCITTCR_MAXBEATS(x)          (((x)&0x7)<<0x8)
+#define MCF_PCI_PCITTCR_MAXRETRY(x)          (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCITTCR_PCICMD(x)            (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCITER */
+#define MCF_PCI_PCITER_NE                    (0x10000)
+#define MCF_PCI_PCITER_IAE                   (0x20000)
+#define MCF_PCI_PCITER_TAE                   (0x40000)
+#define MCF_PCI_PCITER_RE                    (0x80000)
+#define MCF_PCI_PCITER_SE                    (0x100000)
+#define MCF_PCI_PCITER_FEE                   (0x200000)
+#define MCF_PCI_PCITER_ME                    (0x1000000)
+#define MCF_PCI_PCITER_BE                    (0x8000000)
+#define MCF_PCI_PCITER_CM                    (0x10000000)
+#define MCF_PCI_PCITER_RF                    (0x40000000)
+#define MCF_PCI_PCITER_RC                    (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITNAR */
+#define MCF_PCI_PCITNAR_NEXTADDRESS(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITLWR */
+#define MCF_PCI_PCITLWR_LASTWORD(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITDCR */
+#define MCF_PCI_PCITDCR_PKTSDONE(x)          (((x)&0xFFFF)<<0)
+#define MCF_PCI_PCITDCR_BYTESDONE(x)         (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCITSR */
+#define MCF_PCI_PCITSR_IA                    (0x10000)
+#define MCF_PCI_PCITSR_TA                    (0x20000)
+#define MCF_PCI_PCITSR_RE                    (0x40000)
+#define MCF_PCI_PCITSR_SE                    (0x80000)
+#define MCF_PCI_PCITSR_FE                    (0x100000)
+#define MCF_PCI_PCITSR_BE1                   (0x200000)
+#define MCF_PCI_PCITSR_BE2                   (0x400000)
+#define MCF_PCI_PCITSR_BE3                   (0x800000)
+#define MCF_PCI_PCITSR_NT                    (0x1000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITFDR */
+#define MCF_PCI_PCITFDR_FIFODATAWORD(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITFSR */
+#define MCF_PCI_PCITFSR_EMPTY                (0x10000)
+#define MCF_PCI_PCITFSR_ALARM                (0x20000)
+#define MCF_PCI_PCITFSR_FULL                 (0x40000)
+#define MCF_PCI_PCITFSR_FR                   (0x80000)
+#define MCF_PCI_PCITFSR_OF                   (0x100000)
+#define MCF_PCI_PCITFSR_UF                   (0x200000)
+#define MCF_PCI_PCITFSR_RXW                  (0x400000)
+#define MCF_PCI_PCITFSR_FAE                  (0x800000)
+#define MCF_PCI_PCITFSR_TXW                  (0x40000000)
+#define MCF_PCI_PCITFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITFCR */
+#define MCF_PCI_PCITFCR_TXW_MASK             (0x40000)
+#define MCF_PCI_PCITFCR_OF_MASK              (0x80000)
+#define MCF_PCI_PCITFCR_UF_MASK              (0x100000)
+#define MCF_PCI_PCITFCR_RXW_MASK             (0x200000)
+#define MCF_PCI_PCITFCR_FAE_MASK             (0x400000)
+#define MCF_PCI_PCITFCR_IP_MASK              (0x800000)
+#define MCF_PCI_PCITFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PCI_PCITFCR_WFR                  (0x20000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITFAR */
+#define MCF_PCI_PCITFAR_ALARM(x)             (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITFRPR */
+#define MCF_PCI_PCITFRPR_READPTR(x)          (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITFWPR */
+#define MCF_PCI_PCITFWPR_WRITEPTR(x)         (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRPSR */
+#define MCF_PCI_PCIRPSR_PKTSIZE(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCIRSAR */
+#define MCF_PCI_PCIRSAR_STARTADD(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRTCR */
+#define MCF_PCI_PCIRTCR_DI                   (0x1)
+#define MCF_PCI_PCIRTCR_W                    (0x10)
+#define MCF_PCI_PCIRTCR_MAXBEATS(x)          (((x)&0x7)<<0x8)
+#define MCF_PCI_PCIRTCR_FB                   (0x1000)
+#define MCF_PCI_PCIRTCR_MAXRETRY(x)          (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIRTCR_PCICMD(x)            (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIRER */
+#define MCF_PCI_PCIRER_NE                    (0x10000)
+#define MCF_PCI_PCIRER_IAE                   (0x20000)
+#define MCF_PCI_PCIRER_TAE                   (0x40000)
+#define MCF_PCI_PCIRER_RE                    (0x80000)
+#define MCF_PCI_PCIRER_SE                    (0x100000)
+#define MCF_PCI_PCIRER_FEE                   (0x200000)
+#define MCF_PCI_PCIRER_ME                    (0x1000000)
+#define MCF_PCI_PCIRER_BE                    (0x8000000)
+#define MCF_PCI_PCIRER_CM                    (0x10000000)
+#define MCF_PCI_PCIRER_FE                    (0x20000000)
+#define MCF_PCI_PCIRER_RF                    (0x40000000)
+#define MCF_PCI_PCIRER_RC                    (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRNAR */
+#define MCF_PCI_PCIRNAR_NEXTADDRESS(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRDCR */
+#define MCF_PCI_PCIRDCR_PKTSDONE(x)          (((x)&0xFFFF)<<0)
+#define MCF_PCI_PCIRDCR_BYTESDONE(x)         (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCIRSR */
+#define MCF_PCI_PCIRSR_IA                    (0x10000)
+#define MCF_PCI_PCIRSR_TA                    (0x20000)
+#define MCF_PCI_PCIRSR_RE                    (0x40000)
+#define MCF_PCI_PCIRSR_SE                    (0x80000)
+#define MCF_PCI_PCIRSR_FE                    (0x100000)
+#define MCF_PCI_PCIRSR_BE1                   (0x200000)
+#define MCF_PCI_PCIRSR_BE2                   (0x400000)
+#define MCF_PCI_PCIRSR_BE3                   (0x800000)
+#define MCF_PCI_PCIRSR_NT                    (0x1000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFDR */
+#define MCF_PCI_PCIRFDR_FIFODATAWORD(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFSR */
+#define MCF_PCI_PCIRFSR_EMPTY                (0x10000)
+#define MCF_PCI_PCIRFSR_ALARM                (0x20000)
+#define MCF_PCI_PCIRFSR_FULL                 (0x40000)
+#define MCF_PCI_PCIRFSR_FR                   (0x80000)
+#define MCF_PCI_PCIRFSR_OF                   (0x100000)
+#define MCF_PCI_PCIRFSR_UF                   (0x200000)
+#define MCF_PCI_PCIRFSR_RXW                  (0x400000)
+#define MCF_PCI_PCIRFSR_FAE                  (0x800000)
+#define MCF_PCI_PCIRFSR_TXW                  (0x40000000)
+#define MCF_PCI_PCIRFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFCR */
+#define MCF_PCI_PCIRFCR_TXW_MASK             (0x40000)
+#define MCF_PCI_PCIRFCR_OF_MASK              (0x80000)
+#define MCF_PCI_PCIRFCR_UF_MASK              (0x100000)
+#define MCF_PCI_PCIRFCR_RXW_MASK             (0x200000)
+#define MCF_PCI_PCIRFCR_FAE_MASK             (0x400000)
+#define MCF_PCI_PCIRFCR_IP_MASK              (0x800000)
+#define MCF_PCI_PCIRFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PCI_PCIRFCR_WFR                  (0x20000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFAR */
+#define MCF_PCI_PCIRFAR_ALARM(x)             (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFRPR */
+#define MCF_PCI_PCIRFRPR_READPTR(x)          (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFWPR */
+#define MCF_PCI_PCIRFWPR_WRITEPTR(x)         (((x)&0x7F)<<0)
+
+
+#endif /* __MCF5475_PCI_H__ */

BaS_codewarrior/firebeeV1/headers/MCF5475_PCIARB.h

@@ -0,0 +1,43 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PCIARB_H__
+#define __MCF5475_PCIARB_H__
+
+
+/*********************************************************************
+*
+* PCI Bus Arbiter Module (PCIARB)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PCIARB_PACR                      (*(vuint32*)(&__MBAR[0xC00]))
+#define MCF_PCIARB_PASR                      (*(vuint32*)(&__MBAR[0xC04]))
+
+
+/* Bit definitions and macros for MCF_PCIARB_PACR */
+#define MCF_PCIARB_PACR_INTMPRI              (0x1)
+#define MCF_PCIARB_PACR_EXTMPRI(x)           (((x)&0x1F)<<0x1)
+#define MCF_PCIARB_PACR_INTMINTEN            (0x10000)
+#define MCF_PCIARB_PACR_EXTMINTEN(x)         (((x)&0x1F)<<0x11)
+#define MCF_PCIARB_PACR_DS                   (0x80000000)
+
+/* Bit definitions and macros for MCF_PCIARB_PASR */
+#define MCF_PCIARB_PASR_ITLMBK               (0x10000)
+#define MCF_PCIARB_PASR_EXTMBK(x)            (((x)&0x1F)<<0x11)
+
+
+#endif /* __MCF5475_PCIARB_H__ */

BaS_codewarrior/firebeeV1/headers/MCF5475_PSC.h

@@ -0,0 +1,527 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PSC_H__
+#define __MCF5475_PSC_H__
+
+
+/*********************************************************************
+*
+* Programmable Serial Controller (PSC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PSC0_PSCMR2                      (*(vuint8 *)(&__MBAR[0x8600]))
+#define MCF_PSC0_PSCMR1                      (*(vuint8 *)(&__MBAR[0x8600]))
+#define MCF_PSC0_PSCCSR                      (*(vuint8 *)(&__MBAR[0x8604]))
+#define MCF_PSC0_PSCSR                       (*(vuint16*)(&__MBAR[0x8604]))
+#define MCF_PSC0_PSCCR                       (*(vuint8 *)(&__MBAR[0x8608]))
+#define MCF_PSC0_PSCRB_8BIT                  (*(vuint32*)(&__MBAR[0x860C]))
+#define MCF_PSC0_PSCTB_8BIT                  (*(vuint32*)(&__MBAR[0x860C]))
+#define MCF_PSC0_PSCRB_16BIT                 (*(vuint32*)(&__MBAR[0x860C]))
+#define MCF_PSC0_PSCTB_16BIT                 (*(vuint32*)(&__MBAR[0x860C]))
+#define MCF_PSC0_PSCRB_AC97                  (*(vuint32*)(&__MBAR[0x860C]))
+#define MCF_PSC0_PSCTB_AC97                  (*(vuint32*)(&__MBAR[0x860C]))
+#define MCF_PSC0_PSCIPCR                     (*(vuint8 *)(&__MBAR[0x8610]))
+#define MCF_PSC0_PSCACR                      (*(vuint8 *)(&__MBAR[0x8610]))
+#define MCF_PSC0_PSCIMR                      (*(vuint16*)(&__MBAR[0x8614]))
+#define MCF_PSC0_PSCISR                      (*(vuint16*)(&__MBAR[0x8614]))
+#define MCF_PSC0_PSCCTUR                     (*(vuint8 *)(&__MBAR[0x8618]))
+#define MCF_PSC0_PSCCTLR                     (*(vuint8 *)(&__MBAR[0x861C]))
+#define MCF_PSC0_PSCIP                       (*(vuint8 *)(&__MBAR[0x8634]))
+#define MCF_PSC0_PSCOPSET                    (*(vuint8 *)(&__MBAR[0x8638]))
+#define MCF_PSC0_PSCOPRESET                  (*(vuint8 *)(&__MBAR[0x863C]))
+#define MCF_PSC0_PSCSICR                     (*(vuint8 *)(&__MBAR[0x8640]))
+#define MCF_PSC0_PSCIRCR1                    (*(vuint8 *)(&__MBAR[0x8644]))
+#define MCF_PSC0_PSCIRCR2                    (*(vuint8 *)(&__MBAR[0x8648]))
+#define MCF_PSC0_PSCIRSDR                    (*(vuint8 *)(&__MBAR[0x864C]))
+#define MCF_PSC0_PSCIRMDR                    (*(vuint8 *)(&__MBAR[0x8650]))
+#define MCF_PSC0_PSCIRFDR                    (*(vuint8 *)(&__MBAR[0x8654]))
+#define MCF_PSC0_PSCRFCNT                    (*(vuint16*)(&__MBAR[0x8658]))
+#define MCF_PSC0_PSCTFCNT                    (*(vuint16*)(&__MBAR[0x865C]))
+#define MCF_PSC0_PSCRFDR                     (*(vuint32*)(&__MBAR[0x8660]))
+#define MCF_PSC0_PSCRFSR                     (*(vuint16*)(&__MBAR[0x8664]))
+#define MCF_PSC0_PSCRFCR                     (*(vuint32*)(&__MBAR[0x8668]))
+#define MCF_PSC0_PSCRFAR                     (*(vuint16*)(&__MBAR[0x866E]))
+#define MCF_PSC0_PSCRFRP                     (*(vuint16*)(&__MBAR[0x8672]))
+#define MCF_PSC0_PSCRFWP                     (*(vuint16*)(&__MBAR[0x8676]))
+#define MCF_PSC0_PSCRLRFP                    (*(vuint16*)(&__MBAR[0x867A]))
+#define MCF_PSC0_PSCRLWFP                    (*(vuint16*)(&__MBAR[0x867E]))
+#define MCF_PSC0_PSCTFDR                     (*(vuint32*)(&__MBAR[0x8680]))
+#define MCF_PSC0_PSCTFSR                     (*(vuint16*)(&__MBAR[0x8684]))
+#define MCF_PSC0_PSCTFCR                     (*(vuint32*)(&__MBAR[0x8688]))
+#define MCF_PSC0_PSCTFAR                     (*(vuint16*)(&__MBAR[0x868E]))
+#define MCF_PSC0_PSCTFRP                     (*(vuint16*)(&__MBAR[0x8692]))
+#define MCF_PSC0_PSCTFWP                     (*(vuint16*)(&__MBAR[0x8696]))
+#define MCF_PSC0_PSCTLRFP                    (*(vuint16*)(&__MBAR[0x869A]))
+#define MCF_PSC0_PSCTLWFP                    (*(vuint16*)(&__MBAR[0x869E]))
+
+#define MCF_PSC1_PSCMR2                      (*(vuint8 *)(&__MBAR[0x8700]))
+#define MCF_PSC1_PSCMR1                      (*(vuint8 *)(&__MBAR[0x8700]))
+#define MCF_PSC1_PSCCSR                      (*(vuint8 *)(&__MBAR[0x8704]))
+#define MCF_PSC1_PSCSR                       (*(vuint16*)(&__MBAR[0x8704]))
+#define MCF_PSC1_PSCCR                       (*(vuint8 *)(&__MBAR[0x8708]))
+#define MCF_PSC1_PSCRB_8BIT                  (*(vuint32*)(&__MBAR[0x870C]))
+#define MCF_PSC1_PSCTB_8BIT                  (*(vuint32*)(&__MBAR[0x870C]))
+#define MCF_PSC1_PSCRB_16BIT                 (*(vuint32*)(&__MBAR[0x870C]))
+#define MCF_PSC1_PSCTB_16BIT                 (*(vuint32*)(&__MBAR[0x870C]))
+#define MCF_PSC1_PSCRB_AC97                  (*(vuint32*)(&__MBAR[0x870C]))
+#define MCF_PSC1_PSCTB_AC97                  (*(vuint32*)(&__MBAR[0x870C]))
+#define MCF_PSC1_PSCIPCR                     (*(vuint8 *)(&__MBAR[0x8710]))
+#define MCF_PSC1_PSCACR                      (*(vuint8 *)(&__MBAR[0x8710]))
+#define MCF_PSC1_PSCIMR                      (*(vuint16*)(&__MBAR[0x8714]))
+#define MCF_PSC1_PSCISR                      (*(vuint16*)(&__MBAR[0x8714]))
+#define MCF_PSC1_PSCCTUR                     (*(vuint8 *)(&__MBAR[0x8718]))
+#define MCF_PSC1_PSCCTLR                     (*(vuint8 *)(&__MBAR[0x871C]))
+#define MCF_PSC1_PSCIP                       (*(vuint8 *)(&__MBAR[0x8734]))
+#define MCF_PSC1_PSCOPSET                    (*(vuint8 *)(&__MBAR[0x8738]))
+#define MCF_PSC1_PSCOPRESET                  (*(vuint8 *)(&__MBAR[0x873C]))
+#define MCF_PSC1_PSCSICR                     (*(vuint8 *)(&__MBAR[0x8740]))
+#define MCF_PSC1_PSCIRCR1                    (*(vuint8 *)(&__MBAR[0x8744]))
+#define MCF_PSC1_PSCIRCR2                    (*(vuint8 *)(&__MBAR[0x8748]))
+#define MCF_PSC1_PSCIRSDR                    (*(vuint8 *)(&__MBAR[0x874C]))
+#define MCF_PSC1_PSCIRMDR                    (*(vuint8 *)(&__MBAR[0x8750]))
+#define MCF_PSC1_PSCIRFDR                    (*(vuint8 *)(&__MBAR[0x8754]))
+#define MCF_PSC1_PSCRFCNT                    (*(vuint16*)(&__MBAR[0x8758]))
+#define MCF_PSC1_PSCTFCNT                    (*(vuint16*)(&__MBAR[0x875C]))
+#define MCF_PSC1_PSCRFDR                     (*(vuint32*)(&__MBAR[0x8760]))
+#define MCF_PSC1_PSCRFSR                     (*(vuint16*)(&__MBAR[0x8764]))
+#define MCF_PSC1_PSCRFCR                     (*(vuint32*)(&__MBAR[0x8768]))
+#define MCF_PSC1_PSCRFAR                     (*(vuint16*)(&__MBAR[0x876E]))
+#define MCF_PSC1_PSCRFRP                     (*(vuint16*)(&__MBAR[0x8772]))
+#define MCF_PSC1_PSCRFWP                     (*(vuint16*)(&__MBAR[0x8776]))
+#define MCF_PSC1_PSCRLRFP                    (*(vuint16*)(&__MBAR[0x877A]))
+#define MCF_PSC1_PSCRLWFP                    (*(vuint16*)(&__MBAR[0x877E]))
+#define MCF_PSC1_PSCTFDR                     (*(vuint32*)(&__MBAR[0x8780]))
+#define MCF_PSC1_PSCTFSR                     (*(vuint16*)(&__MBAR[0x8784]))
+#define MCF_PSC1_PSCTFCR                     (*(vuint32*)(&__MBAR[0x8788]))
+#define MCF_PSC1_PSCTFAR                     (*(vuint16*)(&__MBAR[0x878E]))
+#define MCF_PSC1_PSCTFRP                     (*(vuint16*)(&__MBAR[0x8792]))
+#define MCF_PSC1_PSCTFWP                     (*(vuint16*)(&__MBAR[0x8796]))
+#define MCF_PSC1_PSCTLRFP                    (*(vuint16*)(&__MBAR[0x879A]))
+#define MCF_PSC1_PSCTLWFP                    (*(vuint16*)(&__MBAR[0x879E]))
+
+#define MCF_PSC2_PSCMR2                      (*(vuint8 *)(&__MBAR[0x8800]))
+#define MCF_PSC2_PSCMR1                      (*(vuint8 *)(&__MBAR[0x8800]))
+#define MCF_PSC2_PSCCSR                      (*(vuint8 *)(&__MBAR[0x8804]))
+#define MCF_PSC2_PSCSR                       (*(vuint16*)(&__MBAR[0x8804]))
+#define MCF_PSC2_PSCCR                       (*(vuint8 *)(&__MBAR[0x8808]))
+#define MCF_PSC2_PSCRB_8BIT                  (*(vuint32*)(&__MBAR[0x880C]))
+#define MCF_PSC2_PSCTB_8BIT                  (*(vuint32*)(&__MBAR[0x880C]))
+#define MCF_PSC2_PSCRB_16BIT                 (*(vuint32*)(&__MBAR[0x880C]))
+#define MCF_PSC2_PSCTB_16BIT                 (*(vuint32*)(&__MBAR[0x880C]))
+#define MCF_PSC2_PSCRB_AC97                  (*(vuint32*)(&__MBAR[0x880C]))
+#define MCF_PSC2_PSCTB_AC97                  (*(vuint32*)(&__MBAR[0x880C]))
+#define MCF_PSC2_PSCIPCR                     (*(vuint8 *)(&__MBAR[0x8810]))
+#define MCF_PSC2_PSCACR                      (*(vuint8 *)(&__MBAR[0x8810]))
+#define MCF_PSC2_PSCIMR                      (*(vuint16*)(&__MBAR[0x8814]))
+#define MCF_PSC2_PSCISR                      (*(vuint16*)(&__MBAR[0x8814]))
+#define MCF_PSC2_PSCCTUR                     (*(vuint8 *)(&__MBAR[0x8818]))
+#define MCF_PSC2_PSCCTLR                     (*(vuint8 *)(&__MBAR[0x881C]))
+#define MCF_PSC2_PSCIP                       (*(vuint8 *)(&__MBAR[0x8834]))
+#define MCF_PSC2_PSCOPSET                    (*(vuint8 *)(&__MBAR[0x8838]))
+#define MCF_PSC2_PSCOPRESET                  (*(vuint8 *)(&__MBAR[0x883C]))
+#define MCF_PSC2_PSCSICR                     (*(vuint8 *)(&__MBAR[0x8840]))
+#define MCF_PSC2_PSCIRCR1                    (*(vuint8 *)(&__MBAR[0x8844]))
+#define MCF_PSC2_PSCIRCR2                    (*(vuint8 *)(&__MBAR[0x8848]))
+#define MCF_PSC2_PSCIRSDR                    (*(vuint8 *)(&__MBAR[0x884C]))
+#define MCF_PSC2_PSCIRMDR                    (*(vuint8 *)(&__MBAR[0x8850]))
+#define MCF_PSC2_PSCIRFDR                    (*(vuint8 *)(&__MBAR[0x8854]))
+#define MCF_PSC2_PSCRFCNT                    (*(vuint16*)(&__MBAR[0x8858]))
+#define MCF_PSC2_PSCTFCNT                    (*(vuint16*)(&__MBAR[0x885C]))
+#define MCF_PSC2_PSCRFDR                     (*(vuint32*)(&__MBAR[0x8860]))
+#define MCF_PSC2_PSCRFSR                     (*(vuint16*)(&__MBAR[0x8864]))
+#define MCF_PSC2_PSCRFCR                     (*(vuint32*)(&__MBAR[0x8868]))
+#define MCF_PSC2_PSCRFAR                     (*(vuint16*)(&__MBAR[0x886E]))
+#define MCF_PSC2_PSCRFRP                     (*(vuint16*)(&__MBAR[0x8872]))
+#define MCF_PSC2_PSCRFWP                     (*(vuint16*)(&__MBAR[0x8876]))
+#define MCF_PSC2_PSCRLRFP                    (*(vuint16*)(&__MBAR[0x887A]))
+#define MCF_PSC2_PSCRLWFP                    (*(vuint16*)(&__MBAR[0x887E]))
+#define MCF_PSC2_PSCTFDR                     (*(vuint32*)(&__MBAR[0x8880]))
+#define MCF_PSC2_PSCTFSR                     (*(vuint16*)(&__MBAR[0x8884]))
+#define MCF_PSC2_PSCTFCR                     (*(vuint32*)(&__MBAR[0x8888]))
+#define MCF_PSC2_PSCTFAR                     (*(vuint16*)(&__MBAR[0x888E]))
+#define MCF_PSC2_PSCTFRP                     (*(vuint16*)(&__MBAR[0x8892]))
+#define MCF_PSC2_PSCTFWP                     (*(vuint16*)(&__MBAR[0x8896]))
+#define MCF_PSC2_PSCTLRFP                    (*(vuint16*)(&__MBAR[0x889A]))
+#define MCF_PSC2_PSCTLWFP                    (*(vuint16*)(&__MBAR[0x889E]))
+
+#define MCF_PSC3_PSCMR2                      (*(vuint8 *)(&__MBAR[0x8900]))
+#define MCF_PSC3_PSCMR1                      (*(vuint8 *)(&__MBAR[0x8900]))
+#define MCF_PSC3_PSCCSR                      (*(vuint8 *)(&__MBAR[0x8904]))
+#define MCF_PSC3_PSCSR                       (*(vuint16*)(&__MBAR[0x8904]))
+#define MCF_PSC3_PSCCR                       (*(vuint8 *)(&__MBAR[0x8908]))
+#define MCF_PSC3_PSCRB_8BIT                  (*(vuint32*)(&__MBAR[0x890C]))
+#define MCF_PSC3_PSCTB_8BIT                  (*(vuint32*)(&__MBAR[0x890C]))
+#define MCF_PSC3_PSCRB_16BIT                 (*(vuint32*)(&__MBAR[0x890C]))
+#define MCF_PSC3_PSCTB_16BIT                 (*(vuint32*)(&__MBAR[0x890C]))
+#define MCF_PSC3_PSCRB_AC97                  (*(vuint32*)(&__MBAR[0x890C]))
+#define MCF_PSC3_PSCTB_AC97                  (*(vuint32*)(&__MBAR[0x890C]))
+#define MCF_PSC3_PSCIPCR                     (*(vuint8 *)(&__MBAR[0x8910]))
+#define MCF_PSC3_PSCACR                      (*(vuint8 *)(&__MBAR[0x8910]))
+#define MCF_PSC3_PSCIMR                      (*(vuint16*)(&__MBAR[0x8914]))
+#define MCF_PSC3_PSCISR                      (*(vuint16*)(&__MBAR[0x8914]))
+#define MCF_PSC3_PSCCTUR                     (*(vuint8 *)(&__MBAR[0x8918]))
+#define MCF_PSC3_PSCCTLR                     (*(vuint8 *)(&__MBAR[0x891C]))
+#define MCF_PSC3_PSCIP                       (*(vuint8 *)(&__MBAR[0x8934]))
+#define MCF_PSC3_PSCOPSET                    (*(vuint8 *)(&__MBAR[0x8938]))
+#define MCF_PSC3_PSCOPRESET                  (*(vuint8 *)(&__MBAR[0x893C]))
+#define MCF_PSC3_PSCSICR                     (*(vuint8 *)(&__MBAR[0x8940]))
+#define MCF_PSC3_PSCIRCR1                    (*(vuint8 *)(&__MBAR[0x8944]))
+#define MCF_PSC3_PSCIRCR2                    (*(vuint8 *)(&__MBAR[0x8948]))
+#define MCF_PSC3_PSCIRSDR                    (*(vuint8 *)(&__MBAR[0x894C]))
+#define MCF_PSC3_PSCIRMDR                    (*(vuint8 *)(&__MBAR[0x8950]))
+#define MCF_PSC3_PSCIRFDR                    (*(vuint8 *)(&__MBAR[0x8954]))
+#define MCF_PSC3_PSCRFCNT                    (*(vuint16*)(&__MBAR[0x8958]))
+#define MCF_PSC3_PSCTFCNT                    (*(vuint16*)(&__MBAR[0x895C]))
+#define MCF_PSC3_PSCRFDR                     (*(vuint32*)(&__MBAR[0x8960]))
+#define MCF_PSC3_PSCRFSR                     (*(vuint16*)(&__MBAR[0x8964]))
+#define MCF_PSC3_PSCRFCR                     (*(vuint32*)(&__MBAR[0x8968]))
+#define MCF_PSC3_PSCRFAR                     (*(vuint16*)(&__MBAR[0x896E]))
+#define MCF_PSC3_PSCRFRP                     (*(vuint16*)(&__MBAR[0x8972]))
+#define MCF_PSC3_PSCRFWP                     (*(vuint16*)(&__MBAR[0x8976]))
+#define MCF_PSC3_PSCRLRFP                    (*(vuint16*)(&__MBAR[0x897A]))
+#define MCF_PSC3_PSCRLWFP                    (*(vuint16*)(&__MBAR[0x897E]))
+#define MCF_PSC3_PSCTFDR                     (*(vuint32*)(&__MBAR[0x8980]))
+#define MCF_PSC3_PSCTFSR                     (*(vuint16*)(&__MBAR[0x8984]))
+#define MCF_PSC3_PSCTFCR                     (*(vuint32*)(&__MBAR[0x8988]))
+#define MCF_PSC3_PSCTFAR                     (*(vuint16*)(&__MBAR[0x898E]))
+#define MCF_PSC3_PSCTFRP                     (*(vuint16*)(&__MBAR[0x8992]))
+#define MCF_PSC3_PSCTFWP                     (*(vuint16*)(&__MBAR[0x8996]))
+#define MCF_PSC3_PSCTLRFP                    (*(vuint16*)(&__MBAR[0x899A]))
+#define MCF_PSC3_PSCTLWFP                    (*(vuint16*)(&__MBAR[0x899E]))
+
+#define MCF_PSC_PSCMR(x)                     (*(vuint8 *)(&__MBAR[0x8600 + ((x)*0x100)]))
+#define MCF_PSC_PSCCSR(x)                    (*(vuint8 *)(&__MBAR[0x8604 + ((x)*0x100)]))
+#define MCF_PSC_PSCSR(x)                     (*(vuint16*)(&__MBAR[0x8604 + ((x)*0x100)]))
+#define MCF_PSC_PSCCR(x)                     (*(vuint8 *)(&__MBAR[0x8608 + ((x)*0x100)]))
+#define MCF_PSC_PSCRB_8BIT(x)                (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCTB_8BIT(x)                (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCRB_16BIT(x)               (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCTB_16BIT(x)               (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCRB_AC97(x)                (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCTB_AC97(x)                (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCIPCR(x)                   (*(vuint8 *)(&__MBAR[0x8610 + ((x)*0x100)]))
+#define MCF_PSC_PSCACR(x)                    (*(vuint8 *)(&__MBAR[0x8610 + ((x)*0x100)]))
+#define MCF_PSC_PSCIMR(x)                    (*(vuint16*)(&__MBAR[0x8614 + ((x)*0x100)]))
+#define MCF_PSC_PSCISR(x)                    (*(vuint16*)(&__MBAR[0x8614 + ((x)*0x100)]))
+#define MCF_PSC_PSCCTUR(x)                   (*(vuint8 *)(&__MBAR[0x8618 + ((x)*0x100)]))
+#define MCF_PSC_PSCCTLR(x)                   (*(vuint8 *)(&__MBAR[0x861C + ((x)*0x100)]))
+#define MCF_PSC_PSCIP(x)                     (*(vuint8 *)(&__MBAR[0x8634 + ((x)*0x100)]))
+#define MCF_PSC_PSCOPSET(x)                  (*(vuint8 *)(&__MBAR[0x8638 + ((x)*0x100)]))
+#define MCF_PSC_PSCOPRESET(x)                (*(vuint8 *)(&__MBAR[0x863C + ((x)*0x100)]))
+#define MCF_PSC_PSCSICR(x)                   (*(vuint8 *)(&__MBAR[0x8640 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRCR1(x)                  (*(vuint8 *)(&__MBAR[0x8644 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRCR2(x)                  (*(vuint8 *)(&__MBAR[0x8648 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRSDR(x)                  (*(vuint8 *)(&__MBAR[0x864C + ((x)*0x100)]))
+#define MCF_PSC_PSCIRMDR(x)                  (*(vuint8 *)(&__MBAR[0x8650 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRFDR(x)                  (*(vuint8 *)(&__MBAR[0x8654 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFCNT(x)                  (*(vuint16*)(&__MBAR[0x8658 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFCNT(x)                  (*(vuint16*)(&__MBAR[0x865C + ((x)*0x100)]))
+#define MCF_PSC_PSCRFDR(x)                   (*(vuint32*)(&__MBAR[0x8660 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFSR(x)                   (*(vuint16*)(&__MBAR[0x8664 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFCR(x)                   (*(vuint32*)(&__MBAR[0x8668 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFAR(x)                   (*(vuint16*)(&__MBAR[0x866E + ((x)*0x100)]))
+#define MCF_PSC_PSCRFRP(x)                   (*(vuint16*)(&__MBAR[0x8672 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFWP(x)                   (*(vuint16*)(&__MBAR[0x8676 + ((x)*0x100)]))
+#define MCF_PSC_PSCRLRFP(x)                  (*(vuint16*)(&__MBAR[0x867A + ((x)*0x100)]))
+#define MCF_PSC_PSCRLWFP(x)                  (*(vuint16*)(&__MBAR[0x867E + ((x)*0x100)]))
+#define MCF_PSC_PSCTFDR(x)                   (*(vuint32*)(&__MBAR[0x8680 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFSR(x)                   (*(vuint16*)(&__MBAR[0x8684 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFCR(x)                   (*(vuint32*)(&__MBAR[0x8688 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFAR(x)                   (*(vuint16*)(&__MBAR[0x868E + ((x)*0x100)]))
+#define MCF_PSC_PSCTFRP(x)                   (*(vuint16*)(&__MBAR[0x8692 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFWP(x)                   (*(vuint16*)(&__MBAR[0x8696 + ((x)*0x100)]))
+#define MCF_PSC_PSCTLRFP(x)                  (*(vuint16*)(&__MBAR[0x869A + ((x)*0x100)]))
+#define MCF_PSC_PSCTLWFP(x)                  (*(vuint16*)(&__MBAR[0x869E + ((x)*0x100)]))
+
+/* Bit definitions and macros for MCF_PSC_PSCMR */
+#define MCF_PSC_PSCMR_SB(x)                  (((x)&0xF)<<0)
+#define MCF_PSC_PSCMR_TXCTS                  (0x10)
+#define MCF_PSC_PSCMR_TXRTS                  (0x20)
+#define MCF_PSC_PSCMR_CM(x)                  (((x)&0x3)<<0x6)
+#define MCF_PSC_PSCMR_CM_NORMAL              (0)
+#define MCF_PSC_PSCMR_CM_ECHO                (0x40)
+#define MCF_PSC_PSCMR_CM_LOCAL_LOOP          (0x80)
+#define MCF_PSC_PSCMR_CM_REMOTE_LOOP         (0xC0)
+#define MCF_PSC_PSCMR_SB_STOP_BITS_1         (0x7)
+#define MCF_PSC_PSCMR_SB_STOP_BITS_15        (0x8)
+#define MCF_PSC_PSCMR_SB_STOP_BITS_2         (0xF)
+#define MCF_PSC_PSCMR_PM_MULTI_ADDR          (0x1C)
+#define MCF_PSC_PSCMR_PM_MULTI_DATA          (0x18)
+#define MCF_PSC_PSCMR_PM_NONE                (0x10)
+#define MCF_PSC_PSCMR_PM_FORCE_HI            (0xC)
+#define MCF_PSC_PSCMR_PM_FORCE_LO            (0x8)
+#define MCF_PSC_PSCMR_PM_ODD                 (0x4)
+#define MCF_PSC_PSCMR_PM_EVEN                (0)
+#define MCF_PSC_PSCMR_BC(x)                  (((x)&0x3)<<0)
+#define MCF_PSC_PSCMR_BC_5                   (0)
+#define MCF_PSC_PSCMR_BC_6                   (0x1)
+#define MCF_PSC_PSCMR_BC_7                   (0x2)
+#define MCF_PSC_PSCMR_BC_8                   (0x3)
+#define MCF_PSC_PSCMR_PT                     (0x4)
+#define MCF_PSC_PSCMR_PM(x)                  (((x)&0x3)<<0x3)
+#define MCF_PSC_PSCMR_ERR                    (0x20)
+#define MCF_PSC_PSCMR_RXIRQ_FU               (0x40)
+#define MCF_PSC_PSCMR_RXRTS                  (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCCSR */
+#define MCF_PSC_PSCCSR_TCSEL(x)              (((x)&0xF)<<0)
+#define MCF_PSC_PSCCSR_RCSEL(x)              (((x)&0xF)<<0x4)
+#define MCF_PSC_PSCCSR_TCSEL_SYS_CLK         (0x0D)
+#define MCF_PSC_PSCCSR_TCSEL_CTM16           (0x0E)
+#define MCF_PSC_PSCCSR_TCSEL_CTM             (0x0F)
+#define MCF_PSC_PSCCSR_RCSEL_SYS_CLK         (0xD0)
+#define MCF_PSC_PSCCSR_RCSEL_CTM16           (0xE0)
+#define MCF_PSC_PSCCSR_RCSEL_CTM             (0xF0)
+
+/* Bit definitions and macros for MCF_PSC_PSCSR */
+#define MCF_PSC_PSCSR_ERR                    (0x40)
+#define MCF_PSC_PSCSR_CDE_DEOF               (0x80)
+#define MCF_PSC_PSCSR_RXRDY                  (0x100)
+#define MCF_PSC_PSCSR_FU                     (0x200)
+#define MCF_PSC_PSCSR_TXRDY                  (0x400)
+#define MCF_PSC_PSCSR_TXEMP_URERR            (0x800)
+#define MCF_PSC_PSCSR_OE                     (0x1000)
+#define MCF_PSC_PSCSR_PE_CRCERR              (0x2000)
+#define MCF_PSC_PSCSR_FE_PHYERR              (0x4000)
+#define MCF_PSC_PSCSR_RB_NEOF                (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCCR */
+#define MCF_PSC_PSCCR_RXC(x)                 (((x)&0x3)<<0)
+#define MCF_PSC_PSCCR_RX_ENABLED             (0x1)
+#define MCF_PSC_PSCCR_RX_DISABLED            (0x2)
+#define MCF_PSC_PSCCR_TXC(x)                 (((x)&0x3)<<0x2)
+#define MCF_PSC_PSCCR_TX_ENABLED             (0x4)
+#define MCF_PSC_PSCCR_TX_DISABLED            (0x8)
+#define MCF_PSC_PSCCR_MISC(x)                (((x)&0x7)<<0x4)
+#define MCF_PSC_PSCCR_NONE                   (0)
+#define MCF_PSC_PSCCR_RESET_MR               (0x10)
+#define MCF_PSC_PSCCR_RESET_RX               (0x20)
+#define MCF_PSC_PSCCR_RESET_TX               (0x30)
+#define MCF_PSC_PSCCR_RESET_ERROR            (0x40)
+#define MCF_PSC_PSCCR_RESET_BKCHGINT         (0x50)
+#define MCF_PSC_PSCCR_START_BREAK            (0x60)
+#define MCF_PSC_PSCCR_STOP_BREAK             (0x70)
+
+/* Bit definitions and macros for MCF_PSC_PSCRB_8BIT */
+#define MCF_PSC_PSCRB_8BIT_RB3(x)            (((x)&0xFF)<<0)
+#define MCF_PSC_PSCRB_8BIT_RB2(x)            (((x)&0xFF)<<0x8)
+#define MCF_PSC_PSCRB_8BIT_RB1(x)            (((x)&0xFF)<<0x10)
+#define MCF_PSC_PSCRB_8BIT_RB0(x)            (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PSC_PSCTB_8BIT */
+#define MCF_PSC_PSCTB_8BIT_TB3(x)            (((x)&0xFF)<<0)
+#define MCF_PSC_PSCTB_8BIT_TB2(x)            (((x)&0xFF)<<0x8)
+#define MCF_PSC_PSCTB_8BIT_TB1(x)            (((x)&0xFF)<<0x10)
+#define MCF_PSC_PSCTB_8BIT_TB0(x)            (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PSC_PSCRB_16BIT */
+#define MCF_PSC_PSCRB_16BIT_RB1(x)           (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCRB_16BIT_RB0(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PSC_PSCTB_16BIT */
+#define MCF_PSC_PSCTB_16BIT_TB1(x)           (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCTB_16BIT_TB0(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PSC_PSCRB_AC97 */
+#define MCF_PSC_PSCRB_AC97_SOF               (0x800)
+#define MCF_PSC_PSCRB_AC97_RB(x)             (((x)&0xFFFFF)<<0xC)
+
+/* Bit definitions and macros for MCF_PSC_PSCTB_AC97 */
+#define MCF_PSC_PSCTB_AC97_TB(x)             (((x)&0xFFFFF)<<0xC)
+
+/* Bit definitions and macros for MCF_PSC_PSCIPCR */
+#define MCF_PSC_PSCIPCR_RESERVED             (0xC)
+#define MCF_PSC_PSCIPCR_CTS                  (0xD)
+#define MCF_PSC_PSCIPCR_D_CTS                (0x1C)
+#define MCF_PSC_PSCIPCR_SYNC                 (0x8C)
+
+/* Bit definitions and macros for MCF_PSC_PSCACR */
+#define MCF_PSC_PSCACR_IEC0                  (0x1)
+
+/* Bit definitions and macros for MCF_PSC_PSCIMR */
+#define MCF_PSC_PSCIMR_ERR                   (0x40)
+#define MCF_PSC_PSCIMR_DEOF                  (0x80)
+#define MCF_PSC_PSCIMR_TXRDY                 (0x100)
+#define MCF_PSC_PSCIMR_RXRDY_FU              (0x200)
+#define MCF_PSC_PSCIMR_DB                    (0x400)
+#define MCF_PSC_PSCIMR_IPC                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCISR */
+#define MCF_PSC_PSCISR_ERR                   (0x40)
+#define MCF_PSC_PSCISR_DEOF                  (0x80)
+#define MCF_PSC_PSCISR_TXRDY                 (0x100)
+#define MCF_PSC_PSCISR_RXRDY_FU              (0x200)
+#define MCF_PSC_PSCISR_DB                    (0x400)
+#define MCF_PSC_PSCISR_IPC                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCCTUR */
+#define MCF_PSC_PSCCTUR_CT(x)                (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCCTLR */
+#define MCF_PSC_PSCCTLR_CT(x)                (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCIP */
+#define MCF_PSC_PSCIP_CTS                    (0x1)
+#define MCF_PSC_PSCIP_TGL                    (0x40)
+#define MCF_PSC_PSCIP_LPWR_B                 (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCOPSET */
+#define MCF_PSC_PSCOPSET_RTS                 (0x1)
+
+/* Bit definitions and macros for MCF_PSC_PSCOPRESET */
+#define MCF_PSC_PSCOPRESET_RTS               (0x1)
+
+/* Bit definitions and macros for MCF_PSC_PSCSICR */
+#define MCF_PSC_PSCSICR_SIM(x)               (((x)&0x7)<<0)
+#define MCF_PSC_PSCSICR_SIM_UART             (0)
+#define MCF_PSC_PSCSICR_SIM_MODEM8           (0x1)
+#define MCF_PSC_PSCSICR_SIM_MODEM16          (0x2)
+#define MCF_PSC_PSCSICR_SIM_AC97             (0x3)
+#define MCF_PSC_PSCSICR_SIM_SIR              (0x4)
+#define MCF_PSC_PSCSICR_SIM_MIR              (0x5)
+#define MCF_PSC_PSCSICR_SIM_FIR              (0x6)
+#define MCF_PSC_PSCSICR_SHDIR                (0x10)
+#define MCF_PSC_PSCSICR_DTS1                 (0x20)
+#define MCF_PSC_PSCSICR_AWR                  (0x40)
+#define MCF_PSC_PSCSICR_ACRB                 (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRCR1 */
+#define MCF_PSC_PSCIRCR1_SPUL                (0x1)
+#define MCF_PSC_PSCIRCR1_SIPEN               (0x2)
+#define MCF_PSC_PSCIRCR1_FD                  (0x4)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRCR2 */
+#define MCF_PSC_PSCIRCR2_NXTEOF              (0x1)
+#define MCF_PSC_PSCIRCR2_ABORT               (0x2)
+#define MCF_PSC_PSCIRCR2_SIPREQ              (0x4)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRSDR */
+#define MCF_PSC_PSCIRSDR_IRSTIM(x)           (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRMDR */
+#define MCF_PSC_PSCIRMDR_M_FDIV(x)           (((x)&0x7F)<<0)
+#define MCF_PSC_PSCIRMDR_FREQ                (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRFDR */
+#define MCF_PSC_PSCIRFDR_F_FDIV(x)           (((x)&0xF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFCNT */
+#define MCF_PSC_PSCRFCNT_CNT(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFCNT */
+#define MCF_PSC_PSCTFCNT_CNT(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFDR */
+#define MCF_PSC_PSCRFDR_DATA(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFSR */
+#define MCF_PSC_PSCRFSR_EMT                  (0x1)
+#define MCF_PSC_PSCRFSR_ALARM                (0x2)
+#define MCF_PSC_PSCRFSR_FU                   (0x4)
+#define MCF_PSC_PSCRFSR_FRMRDY               (0x8)
+#define MCF_PSC_PSCRFSR_OF                   (0x10)
+#define MCF_PSC_PSCRFSR_UF                   (0x20)
+#define MCF_PSC_PSCRFSR_RXW                  (0x40)
+#define MCF_PSC_PSCRFSR_FAE                  (0x80)
+#define MCF_PSC_PSCRFSR_FRM(x)               (((x)&0xF)<<0x8)
+#define MCF_PSC_PSCRFSR_FRM_BYTE0            (0x800)
+#define MCF_PSC_PSCRFSR_FRM_BYTE1            (0x400)
+#define MCF_PSC_PSCRFSR_FRM_BYTE2            (0x200)
+#define MCF_PSC_PSCRFSR_FRM_BYTE3            (0x100)
+#define MCF_PSC_PSCRFSR_TAG(x)               (((x)&0x3)<<0xC)
+#define MCF_PSC_PSCRFSR_TXW                  (0x4000)
+#define MCF_PSC_PSCRFSR_IP                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFCR */
+#define MCF_PSC_PSCRFCR_CNTR(x)              (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCRFCR_TXW_MSK              (0x40000)
+#define MCF_PSC_PSCRFCR_OF_MSK               (0x80000)
+#define MCF_PSC_PSCRFCR_UF_MSK               (0x100000)
+#define MCF_PSC_PSCRFCR_RXW_MSK              (0x200000)
+#define MCF_PSC_PSCRFCR_FAE_MSK              (0x400000)
+#define MCF_PSC_PSCRFCR_IP_MSK               (0x800000)
+#define MCF_PSC_PSCRFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PSC_PSCRFCR_FRMEN                (0x8000000)
+#define MCF_PSC_PSCRFCR_TIMER                (0x10000000)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFAR */
+#define MCF_PSC_PSCRFAR_ALARM(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFRP */
+#define MCF_PSC_PSCRFRP_READ(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFWP */
+#define MCF_PSC_PSCRFWP_WRITE(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRLRFP */
+#define MCF_PSC_PSCRLRFP_LRFP(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRLWFP */
+#define MCF_PSC_PSCRLWFP_LWFP(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFDR */
+#define MCF_PSC_PSCTFDR_DATA(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFSR */
+#define MCF_PSC_PSCTFSR_EMT                  (0x1)
+#define MCF_PSC_PSCTFSR_ALARM                (0x2)
+#define MCF_PSC_PSCTFSR_FU                   (0x4)
+#define MCF_PSC_PSCTFSR_FRMRDY               (0x8)
+#define MCF_PSC_PSCTFSR_OF                   (0x10)
+#define MCF_PSC_PSCTFSR_UF                   (0x20)
+#define MCF_PSC_PSCTFSR_RXW                  (0x40)
+#define MCF_PSC_PSCTFSR_FAE                  (0x80)
+#define MCF_PSC_PSCTFSR_FRM(x)               (((x)&0xF)<<0x8)
+#define MCF_PSC_PSCTFSR_FRM_BYTE0            (0x800)
+#define MCF_PSC_PSCTFSR_FRM_BYTE1            (0x400)
+#define MCF_PSC_PSCTFSR_FRM_BYTE2            (0x200)
+#define MCF_PSC_PSCTFSR_FRM_BYTE3            (0x100)
+#define MCF_PSC_PSCTFSR_TAG(x)               (((x)&0x3)<<0xC)
+#define MCF_PSC_PSCTFSR_TXW                  (0x4000)
+#define MCF_PSC_PSCTFSR_IP                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFCR */
+#define MCF_PSC_PSCTFCR_CNTR(x)              (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCTFCR_TXW_MSK              (0x40000)
+#define MCF_PSC_PSCTFCR_OF_MSK               (0x80000)
+#define MCF_PSC_PSCTFCR_UF_MSK               (0x100000)
+#define MCF_PSC_PSCTFCR_RXW_MSK              (0x200000)
+#define MCF_PSC_PSCTFCR_FAE_MSK              (0x400000)
+#define MCF_PSC_PSCTFCR_IP_MSK               (0x800000)
+#define MCF_PSC_PSCTFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PSC_PSCTFCR_FRMEN                (0x8000000)
+#define MCF_PSC_PSCTFCR_TIMER                (0x10000000)
+#define MCF_PSC_PSCTFCR_WFR                  (0x20000000)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFAR */
+#define MCF_PSC_PSCTFAR_ALARM(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFRP */
+#define MCF_PSC_PSCTFRP_READ(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFWP */
+#define MCF_PSC_PSCTFWP_WRITE(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTLRFP */
+#define MCF_PSC_PSCTLRFP_LRFP(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTLWFP */
+#define MCF_PSC_PSCTLWFP_LWFP(x)             (((x)&0x1FF)<<0)
+
+
+#endif /* __MCF5475_PSC_H__ */

BaS_codewarrior/firebeeV1/headers/MCF5475_SDRAMC.h

@@ -0,0 +1,106 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SDRAMC_H__
+#define __MCF5475_SDRAMC_H__
+
+
+/*********************************************************************
+*
+* Synchronous DRAM Controller (SDRAMC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SDRAMC_SDRAMDS                   (*(vuint32*)(&__MBAR[0x4]))
+#define MCF_SDRAMC_CS0CFG                    (*(vuint32*)(&__MBAR[0x20]))
+#define MCF_SDRAMC_CS1CFG                    (*(vuint32*)(&__MBAR[0x24]))
+#define MCF_SDRAMC_CS2CFG                    (*(vuint32*)(&__MBAR[0x28]))
+#define MCF_SDRAMC_CS3CFG                    (*(vuint32*)(&__MBAR[0x2C]))
+#define MCF_SDRAMC_SDMR                      (*(vuint32*)(&__MBAR[0x100]))
+#define MCF_SDRAMC_SDCR                      (*(vuint32*)(&__MBAR[0x104]))
+#define MCF_SDRAMC_SDCFG1                    (*(vuint32*)(&__MBAR[0x108]))
+#define MCF_SDRAMC_SDCFG2                    (*(vuint32*)(&__MBAR[0x10C]))
+#define MCF_SDRAMC_CSCFG(x)                  (*(vuint32*)(&__MBAR[0x20 + ((x)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */
+#define MCF_SDRAMC_SDRAMDS_SB_D(x)           (((x)&0x3)<<0)
+#define MCF_SDRAMC_SDRAMDS_SB_S(x)           (((x)&0x3)<<0x2)
+#define MCF_SDRAMC_SDRAMDS_SB_A(x)           (((x)&0x3)<<0x4)
+#define MCF_SDRAMC_SDRAMDS_SB_C(x)           (((x)&0x3)<<0x6)
+#define MCF_SDRAMC_SDRAMDS_SB_E(x)           (((x)&0x3)<<0x8)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA        (0)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA        (0x1)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA         (0x2)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE        (0x3)
+
+/* Bit definitions and macros for MCF_SDRAMC_CSCFG */
+#define MCF_SDRAMC_CSCFG_CSSZ(x)             (((x)&0x1F)<<0)
+#define MCF_SDRAMC_CSCFG_CSSZ_DISABLED       (0)
+#define MCF_SDRAMC_CSCFG_CSSZ_1MBYTE         (0x13)
+#define MCF_SDRAMC_CSCFG_CSSZ_2MBYTE         (0x14)
+#define MCF_SDRAMC_CSCFG_CSSZ_4MBYTE         (0x15)
+#define MCF_SDRAMC_CSCFG_CSSZ_8MBYTE         (0x16)
+#define MCF_SDRAMC_CSCFG_CSSZ_16MBYTE        (0x17)
+#define MCF_SDRAMC_CSCFG_CSSZ_32MBYTE        (0x18)
+#define MCF_SDRAMC_CSCFG_CSSZ_64MBYTE        (0x19)
+#define MCF_SDRAMC_CSCFG_CSSZ_128MBYTE       (0x1A)
+#define MCF_SDRAMC_CSCFG_CSSZ_256MBYTE       (0x1B)
+#define MCF_SDRAMC_CSCFG_CSSZ_512MBYTE       (0x1C)
+#define MCF_SDRAMC_CSCFG_CSSZ_1GBYTE         (0x1D)
+#define MCF_SDRAMC_CSCFG_CSSZ_2GBYTE         (0x1E)
+#define MCF_SDRAMC_CSCFG_CSSZ_4GBYTE         (0x1F)
+#define MCF_SDRAMC_CSCFG_CSBA(x)             (((x)&0xFFF)<<0x14)
+#define MCF_SDRAMC_CSCFG_BA(x)               ((x)&0xFFF00000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDMR */
+#define MCF_SDRAMC_SDMR_CMD                  (0x10000)
+#define MCF_SDRAMC_SDMR_AD(x)                (((x)&0xFFF)<<0x12)
+#define MCF_SDRAMC_SDMR_BNKAD(x)             (((x)&0x3)<<0x1E)
+#define MCF_SDRAMC_SDMR_BK_LMR               (0)
+#define MCF_SDRAMC_SDMR_BK_LEMR              (0x40000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCR */
+#define MCF_SDRAMC_SDCR_IPALL                (0x2)
+#define MCF_SDRAMC_SDCR_IREF                 (0x4)
+#define MCF_SDRAMC_SDCR_BUFF                 (0x10)
+#define MCF_SDRAMC_SDCR_DQS_OE(x)            (((x)&0xF)<<0x8)
+#define MCF_SDRAMC_SDCR_RCNT(x)              (((x)&0x3F)<<0x10)
+#define MCF_SDRAMC_SDCR_DRIVE                (0x400000)
+#define MCF_SDRAMC_SDCR_AP                   (0x800000)
+#define MCF_SDRAMC_SDCR_MUX(x)               (((x)&0x3)<<0x18)
+#define MCF_SDRAMC_SDCR_REF                  (0x10000000)
+#define MCF_SDRAMC_SDCR_DDR                  (0x20000000)
+#define MCF_SDRAMC_SDCR_CKE                  (0x40000000)
+#define MCF_SDRAMC_SDCR_MODE_EN              (0x80000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
+#define MCF_SDRAMC_SDCFG1_WTLAT(x)           (((x)&0x7)<<0x4)
+#define MCF_SDRAMC_SDCFG1_REF2ACT(x)         (((x)&0xF)<<0x8)
+#define MCF_SDRAMC_SDCFG1_PRE2ACT(x)         (((x)&0x7)<<0xC)
+#define MCF_SDRAMC_SDCFG1_ACT2RW(x)          (((x)&0x7)<<0x10)
+#define MCF_SDRAMC_SDCFG1_RDLAT(x)           (((x)&0xF)<<0x14)
+#define MCF_SDRAMC_SDCFG1_SWT2RD(x)          (((x)&0x7)<<0x18)
+#define MCF_SDRAMC_SDCFG1_SRD2RW(x)          (((x)&0xF)<<0x1C)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
+#define MCF_SDRAMC_SDCFG2_BL(x)              (((x)&0xF)<<0x10)
+#define MCF_SDRAMC_SDCFG2_BRD2WT(x)          (((x)&0xF)<<0x14)
+#define MCF_SDRAMC_SDCFG2_BWT2RW(x)          (((x)&0xF)<<0x18)
+#define MCF_SDRAMC_SDCFG2_BRD2PRE(x)         (((x)&0xF)<<0x1C)
+
+
+#endif /* __MCF5475_SDRAMC_H__ */

BaS_codewarrior/firebeeV1/headers/MCF5475_SEC.h

@@ -0,0 +1,398 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SEC_H__
+#define __MCF5475_SEC_H__
+
+
+/*********************************************************************
+*
+* Integrated Security Engine (SEC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SEC_EUACRH                       (*(vuint32*)(&__MBAR[0x21000]))
+#define MCF_SEC_EUACRL                       (*(vuint32*)(&__MBAR[0x21004]))
+#define MCF_SEC_SIMRH                        (*(vuint32*)(&__MBAR[0x21008]))
+#define MCF_SEC_SIMRL                        (*(vuint32*)(&__MBAR[0x2100C]))
+#define MCF_SEC_SISRH                        (*(vuint32*)(&__MBAR[0x21010]))
+#define MCF_SEC_SISRL                        (*(vuint32*)(&__MBAR[0x21014]))
+#define MCF_SEC_SICRH                        (*(vuint32*)(&__MBAR[0x21018]))
+#define MCF_SEC_SICRL                        (*(vuint32*)(&__MBAR[0x2101C]))
+#define MCF_SEC_SIDR                         (*(vuint32*)(&__MBAR[0x21020]))
+#define MCF_SEC_EUASRH                       (*(vuint32*)(&__MBAR[0x21028]))
+#define MCF_SEC_EUASRL                       (*(vuint32*)(&__MBAR[0x2102C]))
+#define MCF_SEC_SMCR                         (*(vuint32*)(&__MBAR[0x21030]))
+#define MCF_SEC_MEAR                         (*(vuint32*)(&__MBAR[0x21038]))
+#define MCF_SEC_CCCR0                        (*(vuint32*)(&__MBAR[0x2200C]))
+#define MCF_SEC_CCPSRH0                      (*(vuint32*)(&__MBAR[0x22010]))
+#define MCF_SEC_CCPSRL0                      (*(vuint32*)(&__MBAR[0x22014]))
+#define MCF_SEC_CDPR0                        (*(vuint32*)(&__MBAR[0x22044]))
+#define MCF_SEC_FR0                          (*(vuint32*)(&__MBAR[0x2204C]))
+#define MCF_SEC_CCCR1                        (*(vuint32*)(&__MBAR[0x2300C]))
+#define MCF_SEC_CCPSRH1                      (*(vuint32*)(&__MBAR[0x23010]))
+#define MCF_SEC_CCPSRL1                      (*(vuint32*)(&__MBAR[0x23014]))
+#define MCF_SEC_CDPR1                        (*(vuint32*)(&__MBAR[0x23044]))
+#define MCF_SEC_FR1                          (*(vuint32*)(&__MBAR[0x2304C]))
+#define MCF_SEC_AFRCR                        (*(vuint32*)(&__MBAR[0x28018]))
+#define MCF_SEC_AFSR                         (*(vuint32*)(&__MBAR[0x28028]))
+#define MCF_SEC_AFISR                        (*(vuint32*)(&__MBAR[0x28030]))
+#define MCF_SEC_AFIMR                        (*(vuint32*)(&__MBAR[0x28038]))
+#define MCF_SEC_DRCR                         (*(vuint32*)(&__MBAR[0x2A018]))
+#define MCF_SEC_DSR                          (*(vuint32*)(&__MBAR[0x2A028]))
+#define MCF_SEC_DISR                         (*(vuint32*)(&__MBAR[0x2A030]))
+#define MCF_SEC_DIMR                         (*(vuint32*)(&__MBAR[0x2A038]))
+#define MCF_SEC_MDRCR                        (*(vuint32*)(&__MBAR[0x2C018]))
+#define MCF_SEC_MDSR                         (*(vuint32*)(&__MBAR[0x2C028]))
+#define MCF_SEC_MDISR                        (*(vuint32*)(&__MBAR[0x2C030]))
+#define MCF_SEC_MDIMR                        (*(vuint32*)(&__MBAR[0x2C038]))
+#define MCF_SEC_RNGRCR                       (*(vuint32*)(&__MBAR[0x2E018]))
+#define MCF_SEC_RNGSR                        (*(vuint32*)(&__MBAR[0x2E028]))
+#define MCF_SEC_RNGISR                       (*(vuint32*)(&__MBAR[0x2E030]))
+#define MCF_SEC_RNGIMR                       (*(vuint32*)(&__MBAR[0x2E038]))
+#define MCF_SEC_AESRCR                       (*(vuint32*)(&__MBAR[0x32018]))
+#define MCF_SEC_AESSR                        (*(vuint32*)(&__MBAR[0x32028]))
+#define MCF_SEC_AESISR                       (*(vuint32*)(&__MBAR[0x32030]))
+#define MCF_SEC_AESIMR                       (*(vuint32*)(&__MBAR[0x32038]))
+#define MCF_SEC_CCCRn(x)                     (*(vuint32*)(&__MBAR[0x2200C + ((x)*0x1000)]))
+#define MCF_SEC_CCPSRHn(x)                   (*(vuint32*)(&__MBAR[0x22010 + ((x)*0x1000)]))
+#define MCF_SEC_CCPSRLn(x)                   (*(vuint32*)(&__MBAR[0x22014 + ((x)*0x1000)]))
+#define MCF_SEC_CDPRn(x)                     (*(vuint32*)(&__MBAR[0x22044 + ((x)*0x1000)]))
+#define MCF_SEC_FRn(x)                       (*(vuint32*)(&__MBAR[0x2204C + ((x)*0x1000)]))
+
+
+/* Bit definitions and macros for MCF_SEC_EUACRH */
+#define MCF_SEC_EUACRH_AFEU(x)               (((x)&0xF)<<0)
+#define MCF_SEC_EUACRH_AFFEU_NOASSIGN        (0)
+#define MCF_SEC_EUACRH_AFFEU_CHA0            (0x1)
+#define MCF_SEC_EUACRH_AFFEU_CHA1            (0x2)
+#define MCF_SEC_EUACRH_MDEU(x)               (((x)&0xF)<<0x8)
+#define MCF_SEC_EUACRH_MDEU_NOASSIGN         (0)
+#define MCF_SEC_EUACRH_MDEU_CHA0             (0x100)
+#define MCF_SEC_EUACRH_MDEU_CHA1             (0x200)
+#define MCF_SEC_EUACRH_RNG(x)                (((x)&0xF)<<0x18)
+#define MCF_SEC_EUACRH_RNG_NOASSIGN          (0)
+#define MCF_SEC_EUACRH_RNG_CHA0              (0x1000000)
+#define MCF_SEC_EUACRH_RNG_CHA1              (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_EUACRL */
+#define MCF_SEC_EUACRL_AESU(x)               (((x)&0xF)<<0x10)
+#define MCF_SEC_EUACRL_AESU_NOASSIGN         (0)
+#define MCF_SEC_EUACRL_AESU_CHA0             (0x10000)
+#define MCF_SEC_EUACRL_AESU_CHA1             (0x20000)
+#define MCF_SEC_EUACRL_DEU(x)                (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SEC_SIMRH */
+#define MCF_SEC_SIMRH_AERR                   (0x8000000)
+#define MCF_SEC_SIMRH_CHA_0_DN               (0x10000000)
+#define MCF_SEC_SIMRH_CHA_0_ERR              (0x20000000)
+#define MCF_SEC_SIMRH_CHA_1_DN               (0x40000000)
+#define MCF_SEC_SIMRH_CHA_1_ERR              (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_SIMRL */
+#define MCF_SEC_SIMRL_TEA                    (0x40)
+#define MCF_SEC_SIMRL_DEU_DN                 (0x100)
+#define MCF_SEC_SIMRL_DEU_ERR                (0x200)
+#define MCF_SEC_SIMRL_AESU_DN                (0x1000)
+#define MCF_SEC_SIMRL_AESU_ERR               (0x2000)
+#define MCF_SEC_SIMRL_MDEU_DN                (0x10000)
+#define MCF_SEC_SIMRL_MDEU_ERR               (0x20000)
+#define MCF_SEC_SIMRL_AFEU_DN                (0x100000)
+#define MCF_SEC_SIMRL_AFEU_ERR               (0x200000)
+#define MCF_SEC_SIMRL_RNG_DN                 (0x1000000)
+#define MCF_SEC_SIMRL_RNG_ERR                (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_SISRH */
+#define MCF_SEC_SISRH_AERR                   (0x8000000)
+#define MCF_SEC_SISRH_CHA_0_DN               (0x10000000)
+#define MCF_SEC_SISRH_CHA_0_ERR              (0x20000000)
+#define MCF_SEC_SISRH_CHA_1_DN               (0x40000000)
+#define MCF_SEC_SISRH_CHA_1_ERR              (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_SISRL */
+#define MCF_SEC_SISRL_TEA                    (0x40)
+#define MCF_SEC_SISRL_DEU_DN                 (0x100)
+#define MCF_SEC_SISRL_DEU_ERR                (0x200)
+#define MCF_SEC_SISRL_AESU_DN                (0x1000)
+#define MCF_SEC_SISRL_AESU_ERR               (0x2000)
+#define MCF_SEC_SISRL_MDEU_DN                (0x10000)
+#define MCF_SEC_SISRL_MDEU_ERR               (0x20000)
+#define MCF_SEC_SISRL_AFEU_DN                (0x100000)
+#define MCF_SEC_SISRL_AFEU_ERR               (0x200000)
+#define MCF_SEC_SISRL_RNG_DN                 (0x1000000)
+#define MCF_SEC_SISRL_RNG_ERR                (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_SICRH */
+#define MCF_SEC_SICRH_AERR                   (0x8000000)
+#define MCF_SEC_SICRH_CHA_0_DN               (0x10000000)
+#define MCF_SEC_SICRH_CHA_0_ERR              (0x20000000)
+#define MCF_SEC_SICRH_CHA_1_DN               (0x40000000)
+#define MCF_SEC_SICRH_CHA_1_ERR              (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_SICRL */
+#define MCF_SEC_SICRL_TEA                    (0x40)
+#define MCF_SEC_SICRL_DEU_DN                 (0x100)
+#define MCF_SEC_SICRL_DEU_ERR                (0x200)
+#define MCF_SEC_SICRL_AESU_DN                (0x1000)
+#define MCF_SEC_SICRL_AESU_ERR               (0x2000)
+#define MCF_SEC_SICRL_MDEU_DN                (0x10000)
+#define MCF_SEC_SICRL_MDEU_ERR               (0x20000)
+#define MCF_SEC_SICRL_AFEU_DN                (0x100000)
+#define MCF_SEC_SICRL_AFEU_ERR               (0x200000)
+#define MCF_SEC_SICRL_RNG_DN                 (0x1000000)
+#define MCF_SEC_SICRL_RNG_ERR                (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_SIDR */
+#define MCF_SEC_SIDR_VERSION(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_EUASRH */
+#define MCF_SEC_EUASRH_AFEU(x)               (((x)&0xF)<<0)
+#define MCF_SEC_EUASRH_MDEU(x)               (((x)&0xF)<<0x8)
+#define MCF_SEC_EUASRH_RNG(x)                (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SEC_EUASRL */
+#define MCF_SEC_EUASRL_AESU(x)               (((x)&0xF)<<0x10)
+#define MCF_SEC_EUASRL_DEU(x)                (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SEC_SMCR */
+#define MCF_SEC_SMCR_CURR_CHAN(x)            (((x)&0xF)<<0x4)
+#define MCF_SEC_SMCR_CURR_CHAN_1             (0x10)
+#define MCF_SEC_SMCR_CURR_CHAN_2             (0x20)
+#define MCF_SEC_SMCR_SWR                     (0x1000000)
+
+/* Bit definitions and macros for MCF_SEC_MEAR */
+#define MCF_SEC_MEAR_ADDRESS(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_CCCRn */
+#define MCF_SEC_CCCRn_RST                    (0x1)
+#define MCF_SEC_CCCRn_CDIE                   (0x2)
+#define MCF_SEC_CCCRn_NT                     (0x4)
+#define MCF_SEC_CCCRn_NE                     (0x8)
+#define MCF_SEC_CCCRn_WE                     (0x10)
+#define MCF_SEC_CCCRn_BURST_SIZE(x)          (((x)&0x7)<<0x8)
+#define MCF_SEC_CCCRn_BURST_SIZE_2           (0)
+#define MCF_SEC_CCCRn_BURST_SIZE_8           (0x100)
+#define MCF_SEC_CCCRn_BURST_SIZE_16          (0x200)
+#define MCF_SEC_CCCRn_BURST_SIZE_24          (0x300)
+#define MCF_SEC_CCCRn_BURST_SIZE_32          (0x400)
+#define MCF_SEC_CCCRn_BURST_SIZE_40          (0x500)
+#define MCF_SEC_CCCRn_BURST_SIZE_48          (0x600)
+#define MCF_SEC_CCCRn_BURST_SIZE_56          (0x700)
+
+/* Bit definitions and macros for MCF_SEC_CCPSRHn */
+#define MCF_SEC_CCPSRHn_STATE(x)             (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_CCPSRLn */
+#define MCF_SEC_CCPSRLn_PAIR_PTR(x)          (((x)&0xFF)<<0)
+#define MCF_SEC_CCPSRLn_EUERR                (0x100)
+#define MCF_SEC_CCPSRLn_SERR                 (0x200)
+#define MCF_SEC_CCPSRLn_DERR                 (0x400)
+#define MCF_SEC_CCPSRLn_PERR                 (0x1000)
+#define MCF_SEC_CCPSRLn_TEA                  (0x2000)
+#define MCF_SEC_CCPSRLn_SD                   (0x10000)
+#define MCF_SEC_CCPSRLn_PD                   (0x20000)
+#define MCF_SEC_CCPSRLn_SRD                  (0x40000)
+#define MCF_SEC_CCPSRLn_PRD                  (0x80000)
+#define MCF_SEC_CCPSRLn_SG                   (0x100000)
+#define MCF_SEC_CCPSRLn_PG                   (0x200000)
+#define MCF_SEC_CCPSRLn_SR                   (0x400000)
+#define MCF_SEC_CCPSRLn_PR                   (0x800000)
+#define MCF_SEC_CCPSRLn_MO                   (0x1000000)
+#define MCF_SEC_CCPSRLn_MI                   (0x2000000)
+#define MCF_SEC_CCPSRLn_STAT                 (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_CDPRn */
+#define MCF_SEC_CDPRn_CDP(x)                 (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_FRn */
+#define MCF_SEC_FRn_FETCH_ADDR(x)            (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_AFRCR */
+#define MCF_SEC_AFRCR_SR                     (0x1000000)
+#define MCF_SEC_AFRCR_MI                     (0x2000000)
+#define MCF_SEC_AFRCR_RI                     (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_AFSR */
+#define MCF_SEC_AFSR_RD                      (0x1000000)
+#define MCF_SEC_AFSR_ID                      (0x2000000)
+#define MCF_SEC_AFSR_IE                      (0x4000000)
+#define MCF_SEC_AFSR_OFR                     (0x8000000)
+#define MCF_SEC_AFSR_IFW                     (0x10000000)
+#define MCF_SEC_AFSR_HALT                    (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_AFISR */
+#define MCF_SEC_AFISR_DSE                    (0x10000)
+#define MCF_SEC_AFISR_KSE                    (0x20000)
+#define MCF_SEC_AFISR_CE                     (0x40000)
+#define MCF_SEC_AFISR_ERE                    (0x80000)
+#define MCF_SEC_AFISR_IE                     (0x100000)
+#define MCF_SEC_AFISR_OFU                    (0x2000000)
+#define MCF_SEC_AFISR_IFO                    (0x4000000)
+#define MCF_SEC_AFISR_IFE                    (0x10000000)
+#define MCF_SEC_AFISR_OFE                    (0x20000000)
+#define MCF_SEC_AFISR_AE                     (0x40000000)
+#define MCF_SEC_AFISR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_AFIMR */
+#define MCF_SEC_AFIMR_DSE                    (0x10000)
+#define MCF_SEC_AFIMR_KSE                    (0x20000)
+#define MCF_SEC_AFIMR_CE                     (0x40000)
+#define MCF_SEC_AFIMR_ERE                    (0x80000)
+#define MCF_SEC_AFIMR_IE                     (0x100000)
+#define MCF_SEC_AFIMR_OFU                    (0x2000000)
+#define MCF_SEC_AFIMR_IFO                    (0x4000000)
+#define MCF_SEC_AFIMR_IFE                    (0x10000000)
+#define MCF_SEC_AFIMR_OFE                    (0x20000000)
+#define MCF_SEC_AFIMR_AE                     (0x40000000)
+#define MCF_SEC_AFIMR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_DRCR */
+#define MCF_SEC_DRCR_SR                      (0x1000000)
+#define MCF_SEC_DRCR_MI                      (0x2000000)
+#define MCF_SEC_DRCR_RI                      (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_DSR */
+#define MCF_SEC_DSR_RD                       (0x1000000)
+#define MCF_SEC_DSR_ID                       (0x2000000)
+#define MCF_SEC_DSR_IE                       (0x4000000)
+#define MCF_SEC_DSR_OFR                      (0x8000000)
+#define MCF_SEC_DSR_IFW                      (0x10000000)
+#define MCF_SEC_DSR_HALT                     (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_DISR */
+#define MCF_SEC_DISR_DSE                     (0x10000)
+#define MCF_SEC_DISR_KSE                     (0x20000)
+#define MCF_SEC_DISR_CE                      (0x40000)
+#define MCF_SEC_DISR_ERE                     (0x80000)
+#define MCF_SEC_DISR_IE                      (0x100000)
+#define MCF_SEC_DISR_KPE                     (0x200000)
+#define MCF_SEC_DISR_OFU                     (0x2000000)
+#define MCF_SEC_DISR_IFO                     (0x4000000)
+#define MCF_SEC_DISR_IFE                     (0x10000000)
+#define MCF_SEC_DISR_OFE                     (0x20000000)
+#define MCF_SEC_DISR_AE                      (0x40000000)
+#define MCF_SEC_DISR_ME                      (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_DIMR */
+#define MCF_SEC_DIMR_DSE                     (0x10000)
+#define MCF_SEC_DIMR_KSE                     (0x20000)
+#define MCF_SEC_DIMR_CE                      (0x40000)
+#define MCF_SEC_DIMR_ERE                     (0x80000)
+#define MCF_SEC_DIMR_IE                      (0x100000)
+#define MCF_SEC_DIMR_KPE                     (0x200000)
+#define MCF_SEC_DIMR_OFU                     (0x2000000)
+#define MCF_SEC_DIMR_IFO                     (0x4000000)
+#define MCF_SEC_DIMR_IFE                     (0x10000000)
+#define MCF_SEC_DIMR_OFE                     (0x20000000)
+#define MCF_SEC_DIMR_AE                      (0x40000000)
+#define MCF_SEC_DIMR_ME                      (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_MDRCR */
+#define MCF_SEC_MDRCR_SR                     (0x1000000)
+#define MCF_SEC_MDRCR_MI                     (0x2000000)
+#define MCF_SEC_MDRCR_RI                     (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_MDSR */
+#define MCF_SEC_MDSR_RD                      (0x1000000)
+#define MCF_SEC_MDSR_ID                      (0x2000000)
+#define MCF_SEC_MDSR_IE                      (0x4000000)
+#define MCF_SEC_MDSR_IFW                     (0x10000000)
+#define MCF_SEC_MDSR_HALT                    (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_MDISR */
+#define MCF_SEC_MDISR_DSE                    (0x10000)
+#define MCF_SEC_MDISR_KSE                    (0x20000)
+#define MCF_SEC_MDISR_CE                     (0x40000)
+#define MCF_SEC_MDISR_ERE                    (0x80000)
+#define MCF_SEC_MDISR_IE                     (0x100000)
+#define MCF_SEC_MDISR_IFO                    (0x4000000)
+#define MCF_SEC_MDISR_AE                     (0x40000000)
+#define MCF_SEC_MDISR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_MDIMR */
+#define MCF_SEC_MDIMR_DSE                    (0x10000)
+#define MCF_SEC_MDIMR_KSE                    (0x20000)
+#define MCF_SEC_MDIMR_CE                     (0x40000)
+#define MCF_SEC_MDIMR_ERE                    (0x80000)
+#define MCF_SEC_MDIMR_IE                     (0x100000)
+#define MCF_SEC_MDIMR_IFO                    (0x4000000)
+#define MCF_SEC_MDIMR_AE                     (0x40000000)
+#define MCF_SEC_MDIMR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGRCR */
+#define MCF_SEC_RNGRCR_SR                    (0x1000000)
+#define MCF_SEC_RNGRCR_MI                    (0x2000000)
+#define MCF_SEC_RNGRCR_RI                    (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGSR */
+#define MCF_SEC_RNGSR_RD                     (0x1000000)
+#define MCF_SEC_RNGSR_IE                     (0x4000000)
+#define MCF_SEC_RNGSR_OFR                    (0x8000000)
+#define MCF_SEC_RNGSR_HALT                   (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGISR */
+#define MCF_SEC_RNGISR_IE                    (0x100000)
+#define MCF_SEC_RNGISR_OFU                   (0x2000000)
+#define MCF_SEC_RNGISR_AE                    (0x40000000)
+#define MCF_SEC_RNGISR_ME                    (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGIMR */
+#define MCF_SEC_RNGIMR_IE                    (0x100000)
+#define MCF_SEC_RNGIMR_OFU                   (0x2000000)
+#define MCF_SEC_RNGIMR_AE                    (0x40000000)
+#define MCF_SEC_RNGIMR_ME                    (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_AESRCR */
+#define MCF_SEC_AESRCR_SR                    (0x1000000)
+#define MCF_SEC_AESRCR_MI                    (0x2000000)
+#define MCF_SEC_AESRCR_RI                    (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_AESSR */
+#define MCF_SEC_AESSR_RD                     (0x1000000)
+#define MCF_SEC_AESSR_ID                     (0x2000000)
+#define MCF_SEC_AESSR_IE                     (0x4000000)
+#define MCF_SEC_AESSR_OFR                    (0x8000000)
+#define MCF_SEC_AESSR_IFW                    (0x10000000)
+#define MCF_SEC_AESSR_HALT                   (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_AESISR */
+#define MCF_SEC_AESISR_DSE                   (0x10000)
+#define MCF_SEC_AESISR_KSE                   (0x20000)
+#define MCF_SEC_AESISR_CE                    (0x40000)
+#define MCF_SEC_AESISR_ERE                   (0x80000)
+#define MCF_SEC_AESISR_IE                    (0x100000)
+#define MCF_SEC_AESISR_OFU                   (0x2000000)
+#define MCF_SEC_AESISR_IFO                   (0x4000000)
+#define MCF_SEC_AESISR_IFE                   (0x10000000)
+#define MCF_SEC_AESISR_OFE                   (0x20000000)
+#define MCF_SEC_AESISR_AE                    (0x40000000)
+#define MCF_SEC_AESISR_ME                    (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_AESIMR */
+#define MCF_SEC_AESIMR_DSE                   (0x10000)
+#define MCF_SEC_AESIMR_KSE                   (0x20000)
+#define MCF_SEC_AESIMR_CE                    (0x40000)
+#define MCF_SEC_AESIMR_ERE                   (0x80000)
+#define MCF_SEC_AESIMR_IE                    (0x100000)
+#define MCF_SEC_AESIMR_OFU                   (0x2000000)
+#define MCF_SEC_AESIMR_IFO                   (0x4000000)
+#define MCF_SEC_AESIMR_IFE                   (0x10000000)
+#define MCF_SEC_AESIMR_OFE                   (0x20000000)
+#define MCF_SEC_AESIMR_AE                    (0x40000000)
+#define MCF_SEC_AESIMR_ME                    (0x80000000)
+
+
+#endif /* __MCF5475_SEC_H__ */

BaS_codewarrior/firebeeV1/headers/MCF5475_SIU.h

@@ -24,10 +24,10 @@
 *********************************************************************/
 
 /* Register read/write macros */
-#define MCF_SIU_SBCR                         (*(volatile uint32_t*)(&_MBAR[0x10]))
-#define MCF_SIU_SECSACR                      (*(volatile uint32_t*)(&_MBAR[0x38]))
-#define MCF_SIU_RSR                          (*(volatile uint32_t*)(&_MBAR[0x44]))
-#define MCF_SIU_JTAGID                       (*(volatile uint32_t*)(&_MBAR[0x50]))
+#define MCF_SIU_SBCR                         (*(vuint32*)(&__MBAR[0x10]))
+#define MCF_SIU_SECSACR                      (*(vuint32*)(&__MBAR[0x38]))
+#define MCF_SIU_RSR                          (*(vuint32*)(&__MBAR[0x44]))
+#define MCF_SIU_JTAGID                       (*(vuint32*)(&__MBAR[0x50]))
 
 
 /* Bit definitions and macros for MCF_SIU_SBCR */

BaS_codewarrior/firebeeV1/headers/MCF5475_SLT.h

@@ -0,0 +1,59 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SLT_H__
+#define __MCF5475_SLT_H__
+
+
+/*********************************************************************
+*
+* Slice Timers (SLT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SLT0_STCNT                       (*(vuint32*)(&__MBAR[0x900]))
+#define MCF_SLT0_SCR                         (*(vuint32*)(&__MBAR[0x904]))
+#define MCF_SLT0_SCNT                        (*(vuint32*)(&__MBAR[0x908]))
+#define MCF_SLT0_SSR                         (*(vuint32*)(&__MBAR[0x90C]))
+
+#define MCF_SLT1_STCNT                       (*(vuint32*)(&__MBAR[0x910]))
+#define MCF_SLT1_SCR                         (*(vuint32*)(&__MBAR[0x914]))
+#define MCF_SLT1_SCNT                        (*(vuint32*)(&__MBAR[0x918]))
+#define MCF_SLT1_SSR                         (*(vuint32*)(&__MBAR[0x91C]))
+
+#define MCF_SLT_STCNT(x)                     (*(vuint32*)(&__MBAR[0x900 + ((x)*0x10)]))
+#define MCF_SLT_SCR(x)                       (*(vuint32*)(&__MBAR[0x904 + ((x)*0x10)]))
+#define MCF_SLT_SCNT(x)                      (*(vuint32*)(&__MBAR[0x908 + ((x)*0x10)]))
+#define MCF_SLT_SSR(x)                       (*(vuint32*)(&__MBAR[0x90C + ((x)*0x10)]))
+
+
+/* Bit definitions and macros for MCF_SLT_STCNT */
+#define MCF_SLT_STCNT_TC(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SLT_SCR */
+#define MCF_SLT_SCR_TEN                      (0x1000000)
+#define MCF_SLT_SCR_IEN                      (0x2000000)
+#define MCF_SLT_SCR_RUN                      (0x4000000)
+
+/* Bit definitions and macros for MCF_SLT_SCNT */
+#define MCF_SLT_SCNT_CNT(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SLT_SSR */
+#define MCF_SLT_SSR_ST                       (0x1000000)
+#define MCF_SLT_SSR_BE                       (0x2000000)
+
+
+#endif /* __MCF5475_SLT_H__ */

BaS_codewarrior/firebeeV1/headers/MCF5475_SRAM.h

@@ -0,0 +1,62 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SRAM_H__
+#define __MCF5475_SRAM_H__
+
+
+/*********************************************************************
+*
+* System SRAM Module (SRAM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SRAM_SSCR                        (*(vuint32*)(&__MBAR[0x1FFC0]))
+#define MCF_SRAM_TCCR                        (*(vuint32*)(&__MBAR[0x1FFC4]))
+#define MCF_SRAM_TCCRDR                      (*(vuint32*)(&__MBAR[0x1FFC8]))
+#define MCF_SRAM_TCCRDW                      (*(vuint32*)(&__MBAR[0x1FFCC]))
+#define MCF_SRAM_TCCRSEC                     (*(vuint32*)(&__MBAR[0x1FFD0]))
+
+
+/* Bit definitions and macros for MCF_SRAM_SSCR */
+#define MCF_SRAM_SSCR_INLV                   (0x10000)
+
+/* Bit definitions and macros for MCF_SRAM_TCCR */
+#define MCF_SRAM_TCCR_BANK0_TC(x)            (((x)&0xF)<<0)
+#define MCF_SRAM_TCCR_BANK1_TC(x)            (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCR_BANK2_TC(x)            (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCR_BANK3_TC(x)            (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SRAM_TCCRDR */
+#define MCF_SRAM_TCCRDR_BANK0_TC(x)          (((x)&0xF)<<0)
+#define MCF_SRAM_TCCRDR_BANK1_TC(x)          (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCRDR_BANK2_TC(x)          (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCRDR_BANK3_TC(x)          (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SRAM_TCCRDW */
+#define MCF_SRAM_TCCRDW_BANK0_TC(x)          (((x)&0xF)<<0)
+#define MCF_SRAM_TCCRDW_BANK1_TC(x)          (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCRDW_BANK2_TC(x)          (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCRDW_BANK3_TC(x)          (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SRAM_TCCRSEC */
+#define MCF_SRAM_TCCRSEC_BANK0_TC(x)         (((x)&0xF)<<0)
+#define MCF_SRAM_TCCRSEC_BANK1_TC(x)         (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCRSEC_BANK2_TC(x)         (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCRSEC_BANK3_TC(x)         (((x)&0xF)<<0x18)
+
+
+#endif /* __MCF5475_SRAM_H__ */

BaS_codewarrior/firebeeV1/headers/MCF5475_USB.h

@@ -0,0 +1,554 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_USB_H__
+#define __MCF5475_USB_H__
+
+
+/*********************************************************************
+*
+* Universal Serial Bus Interface (USB)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_USB_USBAISR                      (*(vuint8 *)(&__MBAR[0xB000]))
+#define MCF_USB_USBAIMR                      (*(vuint8 *)(&__MBAR[0xB001]))
+#define MCF_USB_EPINFO                       (*(vuint8 *)(&__MBAR[0xB003]))
+#define MCF_USB_CFGR                         (*(vuint8 *)(&__MBAR[0xB004]))
+#define MCF_USB_CFGAR                        (*(vuint8 *)(&__MBAR[0xB005]))
+#define MCF_USB_SPEEDR                       (*(vuint8 *)(&__MBAR[0xB006]))
+#define MCF_USB_FRMNUMR                      (*(vuint16*)(&__MBAR[0xB00E]))
+#define MCF_USB_EPTNR                        (*(vuint16*)(&__MBAR[0xB010]))
+#define MCF_USB_IFUR                         (*(vuint16*)(&__MBAR[0xB014]))
+#define MCF_USB_IFR0                         (*(vuint16*)(&__MBAR[0xB040]))
+#define MCF_USB_IFR1                         (*(vuint16*)(&__MBAR[0xB042]))
+#define MCF_USB_IFR2                         (*(vuint16*)(&__MBAR[0xB044]))
+#define MCF_USB_IFR3                         (*(vuint16*)(&__MBAR[0xB046]))
+#define MCF_USB_IFR4                         (*(vuint16*)(&__MBAR[0xB048]))
+#define MCF_USB_IFR5                         (*(vuint16*)(&__MBAR[0xB04A]))
+#define MCF_USB_IFR6                         (*(vuint16*)(&__MBAR[0xB04C]))
+#define MCF_USB_IFR7                         (*(vuint16*)(&__MBAR[0xB04E]))
+#define MCF_USB_IFR8                         (*(vuint16*)(&__MBAR[0xB050]))
+#define MCF_USB_IFR9                         (*(vuint16*)(&__MBAR[0xB052]))
+#define MCF_USB_IFR10                        (*(vuint16*)(&__MBAR[0xB054]))
+#define MCF_USB_IFR11                        (*(vuint16*)(&__MBAR[0xB056]))
+#define MCF_USB_IFR12                        (*(vuint16*)(&__MBAR[0xB058]))
+#define MCF_USB_IFR13                        (*(vuint16*)(&__MBAR[0xB05A]))
+#define MCF_USB_IFR14                        (*(vuint16*)(&__MBAR[0xB05C]))
+#define MCF_USB_IFR15                        (*(vuint16*)(&__MBAR[0xB05E]))
+#define MCF_USB_IFR16                        (*(vuint16*)(&__MBAR[0xB060]))
+#define MCF_USB_IFR17                        (*(vuint16*)(&__MBAR[0xB062]))
+#define MCF_USB_IFR18                        (*(vuint16*)(&__MBAR[0xB064]))
+#define MCF_USB_IFR19                        (*(vuint16*)(&__MBAR[0xB066]))
+#define MCF_USB_IFR20                        (*(vuint16*)(&__MBAR[0xB068]))
+#define MCF_USB_IFR21                        (*(vuint16*)(&__MBAR[0xB06A]))
+#define MCF_USB_IFR22                        (*(vuint16*)(&__MBAR[0xB06C]))
+#define MCF_USB_IFR23                        (*(vuint16*)(&__MBAR[0xB06E]))
+#define MCF_USB_IFR24                        (*(vuint16*)(&__MBAR[0xB070]))
+#define MCF_USB_IFR25                        (*(vuint16*)(&__MBAR[0xB072]))
+#define MCF_USB_IFR26                        (*(vuint16*)(&__MBAR[0xB074]))
+#define MCF_USB_IFR27                        (*(vuint16*)(&__MBAR[0xB076]))
+#define MCF_USB_IFR28                        (*(vuint16*)(&__MBAR[0xB078]))
+#define MCF_USB_IFR29                        (*(vuint16*)(&__MBAR[0xB07A]))
+#define MCF_USB_IFR30                        (*(vuint16*)(&__MBAR[0xB07C]))
+#define MCF_USB_IFR31                        (*(vuint16*)(&__MBAR[0xB07E]))
+#define MCF_USB_PPCNT                        (*(vuint16*)(&__MBAR[0xB080]))
+#define MCF_USB_DPCNT                        (*(vuint16*)(&__MBAR[0xB082]))
+#define MCF_USB_CRCECNT                      (*(vuint16*)(&__MBAR[0xB084]))
+#define MCF_USB_BSECNT                       (*(vuint16*)(&__MBAR[0xB086]))
+#define MCF_USB_PIDECNT                      (*(vuint16*)(&__MBAR[0xB088]))
+#define MCF_USB_FRMECNT                      (*(vuint16*)(&__MBAR[0xB08A]))
+#define MCF_USB_TXPCNT                       (*(vuint16*)(&__MBAR[0xB08C]))
+#define MCF_USB_CNTOVR                       (*(vuint8 *)(&__MBAR[0xB08E]))
+#define MCF_USB_EP0ACR                       (*(vuint8 *)(&__MBAR[0xB101]))
+#define MCF_USB_EP0MPSR                      (*(vuint16*)(&__MBAR[0xB102]))
+#define MCF_USB_EP0IFR                       (*(vuint8 *)(&__MBAR[0xB104]))
+#define MCF_USB_EP0SR                        (*(vuint8 *)(&__MBAR[0xB105]))
+#define MCF_USB_BMRTR                        (*(vuint8 *)(&__MBAR[0xB106]))
+#define MCF_USB_BRTR                         (*(vuint8 *)(&__MBAR[0xB107]))
+#define MCF_USB_WVALUER                      (*(vuint16*)(&__MBAR[0xB108]))
+#define MCF_USB_WINDEXR                      (*(vuint16*)(&__MBAR[0xB10A]))
+#define MCF_USB_WLENGTHR                     (*(vuint16*)(&__MBAR[0xB10C]))
+#define MCF_USB_EP1OUTACR                    (*(vuint8 *)(&__MBAR[0xB131]))
+#define MCF_USB_EP1OUTMPSR                   (*(vuint16*)(&__MBAR[0xB132]))
+#define MCF_USB_EP1OUTIFR                    (*(vuint8 *)(&__MBAR[0xB134]))
+#define MCF_USB_EP1OUTSR                     (*(vuint8 *)(&__MBAR[0xB135]))
+#define MCF_USB_EP1OUTSFR                    (*(vuint16*)(&__MBAR[0xB13E]))
+#define MCF_USB_EP1INACR                     (*(vuint8 *)(&__MBAR[0xB149]))
+#define MCF_USB_EP1INMPSR                    (*(vuint16*)(&__MBAR[0xB14A]))
+#define MCF_USB_EP1INIFR                     (*(vuint8 *)(&__MBAR[0xB14C]))
+#define MCF_USB_EP1INSR                      (*(vuint8 *)(&__MBAR[0xB14D]))
+#define MCF_USB_EP1INSFR                     (*(vuint16*)(&__MBAR[0xB156]))
+#define MCF_USB_EP2OUTACR                    (*(vuint8 *)(&__MBAR[0xB161]))
+#define MCF_USB_EP2OUTMPSR                   (*(vuint16*)(&__MBAR[0xB162]))
+#define MCF_USB_EP2OUTIFR                    (*(vuint8 *)(&__MBAR[0xB164]))
+#define MCF_USB_EP2OUTSR                     (*(vuint8 *)(&__MBAR[0xB165]))
+#define MCF_USB_EP2OUTSFR                    (*(vuint16*)(&__MBAR[0xB16E]))
+#define MCF_USB_EP2INACR                     (*(vuint8 *)(&__MBAR[0xB179]))
+#define MCF_USB_EP2INMPSR                    (*(vuint16*)(&__MBAR[0xB17A]))
+#define MCF_USB_EP2INIFR                     (*(vuint8 *)(&__MBAR[0xB17C]))
+#define MCF_USB_EP2INSR                      (*(vuint8 *)(&__MBAR[0xB17D]))
+#define MCF_USB_EP2INSFR                     (*(vuint16*)(&__MBAR[0xB186]))
+#define MCF_USB_EP3OUTACR                    (*(vuint8 *)(&__MBAR[0xB191]))
+#define MCF_USB_EP3OUTMPSR                   (*(vuint16*)(&__MBAR[0xB192]))
+#define MCF_USB_EP3OUTIFR                    (*(vuint8 *)(&__MBAR[0xB194]))
+#define MCF_USB_EP3OUTSR                     (*(vuint8 *)(&__MBAR[0xB195]))
+#define MCF_USB_EP3OUTSFR                    (*(vuint16*)(&__MBAR[0xB19E]))
+#define MCF_USB_EP3INACR                     (*(vuint8 *)(&__MBAR[0xB1A9]))
+#define MCF_USB_EP3INMPSR                    (*(vuint16*)(&__MBAR[0xB1AA]))
+#define MCF_USB_EP3INIFR                     (*(vuint8 *)(&__MBAR[0xB1AC]))
+#define MCF_USB_EP3INSR                      (*(vuint8 *)(&__MBAR[0xB1AD]))
+#define MCF_USB_EP3INSFR                     (*(vuint16*)(&__MBAR[0xB1B6]))
+#define MCF_USB_EP4OUTACR                    (*(vuint8 *)(&__MBAR[0xB1C1]))
+#define MCF_USB_EP4OUTMPSR                   (*(vuint16*)(&__MBAR[0xB1C2]))
+#define MCF_USB_EP4OUTIFR                    (*(vuint8 *)(&__MBAR[0xB1C4]))
+#define MCF_USB_EP4OUTSR                     (*(vuint8 *)(&__MBAR[0xB1C5]))
+#define MCF_USB_EP4OUTSFR                    (*(vuint16*)(&__MBAR[0xB1CE]))
+#define MCF_USB_EP4INACR                     (*(vuint8 *)(&__MBAR[0xB1D9]))
+#define MCF_USB_EP4INMPSR                    (*(vuint16*)(&__MBAR[0xB1DA]))
+#define MCF_USB_EP4INIFR                     (*(vuint8 *)(&__MBAR[0xB1DC]))
+#define MCF_USB_EP4INSR                      (*(vuint8 *)(&__MBAR[0xB1DD]))
+#define MCF_USB_EP4INSFR                     (*(vuint16*)(&__MBAR[0xB1E6]))
+#define MCF_USB_EP5OUTACR                    (*(vuint8 *)(&__MBAR[0xB1F1]))
+#define MCF_USB_EP5OUTMPSR                   (*(vuint16*)(&__MBAR[0xB1F2]))
+#define MCF_USB_EP5OUTIFR                    (*(vuint8 *)(&__MBAR[0xB1F4]))
+#define MCF_USB_EP5OUTSR                     (*(vuint8 *)(&__MBAR[0xB1F5]))
+#define MCF_USB_EP5OUTSFR                    (*(vuint16*)(&__MBAR[0xB1FE]))
+#define MCF_USB_EP5INACR                     (*(vuint8 *)(&__MBAR[0xB209]))
+#define MCF_USB_EP5INMPSR                    (*(vuint16*)(&__MBAR[0xB20A]))
+#define MCF_USB_EP5INIFR                     (*(vuint8 *)(&__MBAR[0xB20C]))
+#define MCF_USB_EP5INSR                      (*(vuint8 *)(&__MBAR[0xB20D]))
+#define MCF_USB_EP5INSFR                     (*(vuint16*)(&__MBAR[0xB216]))
+#define MCF_USB_EP6OUTACR                    (*(vuint8 *)(&__MBAR[0xB221]))
+#define MCF_USB_EP6OUTMPSR                   (*(vuint16*)(&__MBAR[0xB222]))
+#define MCF_USB_EP6OUTIFR                    (*(vuint8 *)(&__MBAR[0xB224]))
+#define MCF_USB_EP6OUTSR                     (*(vuint8 *)(&__MBAR[0xB225]))
+#define MCF_USB_EP6OUTSFR                    (*(vuint16*)(&__MBAR[0xB22E]))
+#define MCF_USB_EP6INACR                     (*(vuint8 *)(&__MBAR[0xB239]))
+#define MCF_USB_EP6INMPSR                    (*(vuint16*)(&__MBAR[0xB23A]))
+#define MCF_USB_EP6INIFR                     (*(vuint8 *)(&__MBAR[0xB23C]))
+#define MCF_USB_EP6INSR                      (*(vuint8 *)(&__MBAR[0xB23D]))
+#define MCF_USB_EP6INSFR                     (*(vuint16*)(&__MBAR[0xB246]))
+#define MCF_USB_USBSR                        (*(vuint32*)(&__MBAR[0xB400]))
+#define MCF_USB_USBCR                        (*(vuint32*)(&__MBAR[0xB404]))
+#define MCF_USB_DRAMCR                       (*(vuint32*)(&__MBAR[0xB408]))
+#define MCF_USB_DRAMDR                       (*(vuint32*)(&__MBAR[0xB40C]))
+#define MCF_USB_USBISR                       (*(vuint32*)(&__MBAR[0xB410]))
+#define MCF_USB_USBIMR                       (*(vuint32*)(&__MBAR[0xB414]))
+#define MCF_USB_EP0STAT                      (*(vuint32*)(&__MBAR[0xB440]))
+#define MCF_USB_EP0ISR                       (*(vuint32*)(&__MBAR[0xB444]))
+#define MCF_USB_EP0IMR                       (*(vuint32*)(&__MBAR[0xB448]))
+#define MCF_USB_EP0FRCFGR                    (*(vuint32*)(&__MBAR[0xB44C]))
+#define MCF_USB_EP0FDR                       (*(vuint32*)(&__MBAR[0xB450]))
+#define MCF_USB_EP0FSR                       (*(vuint32*)(&__MBAR[0xB454]))
+#define MCF_USB_EP0FCR                       (*(vuint32*)(&__MBAR[0xB458]))
+#define MCF_USB_EP0FAR                       (*(vuint32*)(&__MBAR[0xB45C]))
+#define MCF_USB_EP0FRP                       (*(vuint32*)(&__MBAR[0xB460]))
+#define MCF_USB_EP0FWP                       (*(vuint32*)(&__MBAR[0xB464]))
+#define MCF_USB_EP0LRFP                      (*(vuint32*)(&__MBAR[0xB468]))
+#define MCF_USB_EP0LWFP                      (*(vuint32*)(&__MBAR[0xB46C]))
+#define MCF_USB_EP1STAT                      (*(vuint32*)(&__MBAR[0xB470]))
+#define MCF_USB_EP1ISR                       (*(vuint32*)(&__MBAR[0xB474]))
+#define MCF_USB_EP1IMR                       (*(vuint32*)(&__MBAR[0xB478]))
+#define MCF_USB_EP1FRCFGR                    (*(vuint32*)(&__MBAR[0xB47C]))
+#define MCF_USB_EP1FDR                       (*(vuint32*)(&__MBAR[0xB480]))
+#define MCF_USB_EP1FSR                       (*(vuint32*)(&__MBAR[0xB484]))
+#define MCF_USB_EP1FCR                       (*(vuint32*)(&__MBAR[0xB488]))
+#define MCF_USB_EP1FAR                       (*(vuint32*)(&__MBAR[0xB48C]))
+#define MCF_USB_EP1FRP                       (*(vuint32*)(&__MBAR[0xB490]))
+#define MCF_USB_EP1FWP                       (*(vuint32*)(&__MBAR[0xB494]))
+#define MCF_USB_EP1LRFP                      (*(vuint32*)(&__MBAR[0xB498]))
+#define MCF_USB_EP1LWFP                      (*(vuint32*)(&__MBAR[0xB49C]))
+#define MCF_USB_EP2STAT                      (*(vuint32*)(&__MBAR[0xB4A0]))
+#define MCF_USB_EP2ISR                       (*(vuint32*)(&__MBAR[0xB4A4]))
+#define MCF_USB_EP2IMR                       (*(vuint32*)(&__MBAR[0xB4A8]))
+#define MCF_USB_EP2FRCFGR                    (*(vuint32*)(&__MBAR[0xB4AC]))
+#define MCF_USB_EP2FDR                       (*(vuint32*)(&__MBAR[0xB4B0]))
+#define MCF_USB_EP2FSR                       (*(vuint32*)(&__MBAR[0xB4B4]))
+#define MCF_USB_EP2FCR                       (*(vuint32*)(&__MBAR[0xB4B8]))
+#define MCF_USB_EP2FAR                       (*(vuint32*)(&__MBAR[0xB4BC]))
+#define MCF_USB_EP2FRP                       (*(vuint32*)(&__MBAR[0xB4C0]))
+#define MCF_USB_EP2FWP                       (*(vuint32*)(&__MBAR[0xB4C4]))
+#define MCF_USB_EP2LRFP                      (*(vuint32*)(&__MBAR[0xB4C8]))
+#define MCF_USB_EP2LWFP                      (*(vuint32*)(&__MBAR[0xB4CC]))
+#define MCF_USB_EP3STAT                      (*(vuint32*)(&__MBAR[0xB4D0]))
+#define MCF_USB_EP3ISR                       (*(vuint32*)(&__MBAR[0xB4D4]))
+#define MCF_USB_EP3IMR                       (*(vuint32*)(&__MBAR[0xB4D8]))
+#define MCF_USB_EP3FRCFGR                    (*(vuint32*)(&__MBAR[0xB4DC]))
+#define MCF_USB_EP3FDR                       (*(vuint32*)(&__MBAR[0xB4E0]))
+#define MCF_USB_EP3FSR                       (*(vuint32*)(&__MBAR[0xB4E4]))
+#define MCF_USB_EP3FCR                       (*(vuint32*)(&__MBAR[0xB4E8]))
+#define MCF_USB_EP3FAR                       (*(vuint32*)(&__MBAR[0xB4EC]))
+#define MCF_USB_EP3FRP                       (*(vuint32*)(&__MBAR[0xB4F0]))
+#define MCF_USB_EP3FWP                       (*(vuint32*)(&__MBAR[0xB4F4]))
+#define MCF_USB_EP3LRFP                      (*(vuint32*)(&__MBAR[0xB4F8]))
+#define MCF_USB_EP3LWFP                      (*(vuint32*)(&__MBAR[0xB4FC]))
+#define MCF_USB_EP4STAT                      (*(vuint32*)(&__MBAR[0xB500]))
+#define MCF_USB_EP4ISR                       (*(vuint32*)(&__MBAR[0xB504]))
+#define MCF_USB_EP4IMR                       (*(vuint32*)(&__MBAR[0xB508]))
+#define MCF_USB_EP4FRCFGR                    (*(vuint32*)(&__MBAR[0xB50C]))
+#define MCF_USB_EP4FDR                       (*(vuint32*)(&__MBAR[0xB510]))
+#define MCF_USB_EP4FSR                       (*(vuint32*)(&__MBAR[0xB514]))
+#define MCF_USB_EP4FCR                       (*(vuint32*)(&__MBAR[0xB518]))
+#define MCF_USB_EP4FAR                       (*(vuint32*)(&__MBAR[0xB51C]))
+#define MCF_USB_EP4FRP                       (*(vuint32*)(&__MBAR[0xB520]))
+#define MCF_USB_EP4FWP                       (*(vuint32*)(&__MBAR[0xB524]))
+#define MCF_USB_EP4LRFP                      (*(vuint32*)(&__MBAR[0xB528]))
+#define MCF_USB_EP4LWFP                      (*(vuint32*)(&__MBAR[0xB52C]))
+#define MCF_USB_EP5STAT                      (*(vuint32*)(&__MBAR[0xB530]))
+#define MCF_USB_EP5ISR                       (*(vuint32*)(&__MBAR[0xB534]))
+#define MCF_USB_EP5IMR                       (*(vuint32*)(&__MBAR[0xB538]))
+#define MCF_USB_EP5FRCFGR                    (*(vuint32*)(&__MBAR[0xB53C]))
+#define MCF_USB_EP5FDR                       (*(vuint32*)(&__MBAR[0xB540]))
+#define MCF_USB_EP5FSR                       (*(vuint32*)(&__MBAR[0xB544]))
+#define MCF_USB_EP5FCR                       (*(vuint32*)(&__MBAR[0xB548]))
+#define MCF_USB_EP5FAR                       (*(vuint32*)(&__MBAR[0xB54C]))
+#define MCF_USB_EP5FRP                       (*(vuint32*)(&__MBAR[0xB550]))
+#define MCF_USB_EP5FWP                       (*(vuint32*)(&__MBAR[0xB554]))
+#define MCF_USB_EP5LRFP                      (*(vuint32*)(&__MBAR[0xB558]))
+#define MCF_USB_EP5LWFP                      (*(vuint32*)(&__MBAR[0xB55C]))
+#define MCF_USB_EP6STAT                      (*(vuint32*)(&__MBAR[0xB560]))
+#define MCF_USB_EP6ISR                       (*(vuint32*)(&__MBAR[0xB564]))
+#define MCF_USB_EP6IMR                       (*(vuint32*)(&__MBAR[0xB568]))
+#define MCF_USB_EP6FRCFGR                    (*(vuint32*)(&__MBAR[0xB56C]))
+#define MCF_USB_EP6FDR                       (*(vuint32*)(&__MBAR[0xB570]))
+#define MCF_USB_EP6FSR                       (*(vuint32*)(&__MBAR[0xB574]))
+#define MCF_USB_EP6FCR                       (*(vuint32*)(&__MBAR[0xB578]))
+#define MCF_USB_EP6FAR                       (*(vuint32*)(&__MBAR[0xB57C]))
+#define MCF_USB_EP6FRP                       (*(vuint32*)(&__MBAR[0xB580]))
+#define MCF_USB_EP6FWP                       (*(vuint32*)(&__MBAR[0xB584]))
+#define MCF_USB_EP6LRFP                      (*(vuint32*)(&__MBAR[0xB588]))
+#define MCF_USB_EP6LWFP                      (*(vuint32*)(&__MBAR[0xB58C]))
+#define MCF_USB_IFR(x)                       (*(vuint16*)(&__MBAR[0xB040 + ((x)*0x2)]))
+#define MCF_USB_EPOUTACR(x)                  (*(vuint8 *)(&__MBAR[0xB131 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTMPSR(x)                 (*(vuint16*)(&__MBAR[0xB132 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTIFR(x)                  (*(vuint8 *)(&__MBAR[0xB134 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTSR(x)                   (*(vuint8 *)(&__MBAR[0xB135 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTSFR(x)                  (*(vuint16*)(&__MBAR[0xB13E + ((x-1)*0x30)]))
+#define MCF_USB_EPINACR(x)                   (*(vuint8 *)(&__MBAR[0xB149 + ((x-1)*0x30)]))
+#define MCF_USB_EPINMPSR(x)                  (*(vuint16*)(&__MBAR[0xB14A + ((x-1)*0x30)]))
+#define MCF_USB_EPINIFR(x)                   (*(vuint8 *)(&__MBAR[0xB14C + ((x-1)*0x30)]))
+#define MCF_USB_EPINSR(x)                    (*(vuint8 *)(&__MBAR[0xB14D + ((x-1)*0x30)]))
+#define MCF_USB_EPINSFR(x)                   (*(vuint16*)(&__MBAR[0xB156 + ((x-1)*0x30)]))
+#define MCF_USB_EPSTAT(x)                    (*(vuint32*)(&__MBAR[0xB440 + ((x)*0x30)]))
+#define MCF_USB_EPISR(x)                     (*(vuint32*)(&__MBAR[0xB444 + ((x)*0x30)]))
+#define MCF_USB_EPIMR(x)                     (*(vuint32*)(&__MBAR[0xB448 + ((x)*0x30)]))
+#define MCF_USB_EPFRCFGR(x)                  (*(vuint32*)(&__MBAR[0xB44C + ((x)*0x30)]))
+#define MCF_USB_EPFDR(x)                     (*(vuint32*)(&__MBAR[0xB450 + ((x)*0x30)]))
+#define MCF_USB_EPFSR(x)                     (*(vuint32*)(&__MBAR[0xB454 + ((x)*0x30)]))
+#define MCF_USB_EPFCR(x)                     (*(vuint32*)(&__MBAR[0xB458 + ((x)*0x30)]))
+#define MCF_USB_EPFAR(x)                     (*(vuint32*)(&__MBAR[0xB45C + ((x)*0x30)]))
+#define MCF_USB_EPFRP(x)                     (*(vuint32*)(&__MBAR[0xB460 + ((x)*0x30)]))
+#define MCF_USB_EPFWP(x)                     (*(vuint32*)(&__MBAR[0xB464 + ((x)*0x30)]))
+#define MCF_USB_EPLRFP(x)                    (*(vuint32*)(&__MBAR[0xB468 + ((x)*0x30)]))
+#define MCF_USB_EPLWFP(x)                    (*(vuint32*)(&__MBAR[0xB46C + ((x)*0x30)]))
+
+
+/* Bit definitions and macros for MCF_USB_USBAISR */
+#define MCF_USB_USBAISR_SETUP                (0x1)
+#define MCF_USB_USBAISR_IN                   (0x2)
+#define MCF_USB_USBAISR_OUT                  (0x4)
+#define MCF_USB_USBAISR_EPHALT               (0x8)
+#define MCF_USB_USBAISR_TRANSERR             (0x10)
+#define MCF_USB_USBAISR_ACK                  (0x20)
+#define MCF_USB_USBAISR_CTROVFL              (0x40)
+#define MCF_USB_USBAISR_EPSTALL              (0x80)
+
+/* Bit definitions and macros for MCF_USB_USBAIMR */
+#define MCF_USB_USBAIMR_SETUPEN              (0x1)
+#define MCF_USB_USBAIMR_INEN                 (0x2)
+#define MCF_USB_USBAIMR_OUTEN                (0x4)
+#define MCF_USB_USBAIMR_EPHALTEN             (0x8)
+#define MCF_USB_USBAIMR_TRANSERREN           (0x10)
+#define MCF_USB_USBAIMR_ACKEN                (0x20)
+#define MCF_USB_USBAIMR_CTROVFLEN            (0x40)
+#define MCF_USB_USBAIMR_EPSTALLEN            (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPINFO */
+#define MCF_USB_EPINFO_EPDIR                 (0x1)
+#define MCF_USB_EPINFO_EPNUM(x)              (((x)&0x7)<<0x1)
+
+/* Bit definitions and macros for MCF_USB_CFGR */
+#define MCF_USB_CFGR_Configuration_Value(x)  (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_CFGAR */
+#define MCF_USB_CFGAR_RESERVED               (0xA0)
+#define MCF_USB_CFGAR_RMTWKEUP               (0xE0)
+
+/* Bit definitions and macros for MCF_USB_SPEEDR */
+#define MCF_USB_SPEEDR_SPEED(x)              (((x)&0x3)<<0)
+
+/* Bit definitions and macros for MCF_USB_FRMNUMR */
+#define MCF_USB_FRMNUMR_FRMNUM(x)            (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPTNR */
+#define MCF_USB_EPTNR_EP1T(x)                (((x)&0x3)<<0)
+#define MCF_USB_EPTNR_EP2T(x)                (((x)&0x3)<<0x2)
+#define MCF_USB_EPTNR_EP3T(x)                (((x)&0x3)<<0x4)
+#define MCF_USB_EPTNR_EP4T(x)                (((x)&0x3)<<0x6)
+#define MCF_USB_EPTNR_EP5T(x)                (((x)&0x3)<<0x8)
+#define MCF_USB_EPTNR_EP6T(x)                (((x)&0x3)<<0xA)
+#define MCF_USB_EPTNR_EPnT1                  (0)
+#define MCF_USB_EPTNR_EPnT2                  (0x1)
+#define MCF_USB_EPTNR_EPnT3                  (0x2)
+
+/* Bit definitions and macros for MCF_USB_IFUR */
+#define MCF_USB_IFUR_ALTSET(x)               (((x)&0xFF)<<0)
+#define MCF_USB_IFUR_IFNUM(x)                (((x)&0xFF)<<0x8)
+
+/* Bit definitions and macros for MCF_USB_IFR */
+#define MCF_USB_IFR_ALTSET(x)                (((x)&0xFF)<<0)
+#define MCF_USB_IFR_IFNUM(x)                 (((x)&0xFF)<<0x8)
+
+/* Bit definitions and macros for MCF_USB_PPCNT */
+#define MCF_USB_PPCNT_PPCNT(x)               (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_DPCNT */
+#define MCF_USB_DPCNT_DPCNT(x)               (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_CRCECNT */
+#define MCF_USB_CRCECNT_CRCECNT(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_BSECNT */
+#define MCF_USB_BSECNT_BSECNT(x)             (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_PIDECNT */
+#define MCF_USB_PIDECNT_PIDECNT(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_FRMECNT */
+#define MCF_USB_FRMECNT_FRMECNT(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_TXPCNT */
+#define MCF_USB_TXPCNT_TXPCNT(x)             (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_CNTOVR */
+#define MCF_USB_CNTOVR_PPCNT                 (0x1)
+#define MCF_USB_CNTOVR_DPCNT                 (0x2)
+#define MCF_USB_CNTOVR_CRCECNT               (0x4)
+#define MCF_USB_CNTOVR_BSECNT                (0x8)
+#define MCF_USB_CNTOVR_PIDECNT               (0x10)
+#define MCF_USB_CNTOVR_FRMECNT               (0x20)
+#define MCF_USB_CNTOVR_TXPCNT                (0x40)
+
+/* Bit definitions and macros for MCF_USB_EP0ACR */
+#define MCF_USB_EP0ACR_TTYPE(x)              (((x)&0x3)<<0)
+#define MCF_USB_EP0ACR_TTYPE_CTRL            (0)
+#define MCF_USB_EP0ACR_TTYPE_ISOC            (0x1)
+#define MCF_USB_EP0ACR_TTYPE_BULK            (0x2)
+#define MCF_USB_EP0ACR_TTYPE_INT             (0x3)
+
+/* Bit definitions and macros for MCF_USB_EP0MPSR */
+#define MCF_USB_EP0MPSR_MAXPKTSZ(x)          (((x)&0x7FF)<<0)
+#define MCF_USB_EP0MPSR_ADDTRANS(x)          (((x)&0x3)<<0xB)
+
+/* Bit definitions and macros for MCF_USB_EP0IFR */
+#define MCF_USB_EP0IFR_IFNUM(x)              (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EP0SR */
+#define MCF_USB_EP0SR_HALT                   (0x1)
+#define MCF_USB_EP0SR_ACTIVE                 (0x2)
+#define MCF_USB_EP0SR_PSTALL                 (0x4)
+#define MCF_USB_EP0SR_CCOMP                  (0x8)
+#define MCF_USB_EP0SR_TXZERO                 (0x20)
+#define MCF_USB_EP0SR_INT                    (0x80)
+
+/* Bit definitions and macros for MCF_USB_BMRTR */
+#define MCF_USB_BMRTR_REC(x)                 (((x)&0x1F)<<0)
+#define MCF_USB_BMRTR_REC_DEVICE             (0)
+#define MCF_USB_BMRTR_REC_INTERFACE          (0x1)
+#define MCF_USB_BMRTR_REC_ENDPOINT           (0x2)
+#define MCF_USB_BMRTR_REC_OTHER              (0x3)
+#define MCF_USB_BMRTR_TYPE(x)                (((x)&0x3)<<0x5)
+#define MCF_USB_BMRTR_TYPE_STANDARD          (0)
+#define MCF_USB_BMRTR_TYPE_CLASS             (0x20)
+#define MCF_USB_BMRTR_TYPE_VENDOR            (0x40)
+#define MCF_USB_BMRTR_DIR                    (0x80)
+
+/* Bit definitions and macros for MCF_USB_BRTR */
+#define MCF_USB_BRTR_BREQ(x)                 (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_WVALUER */
+#define MCF_USB_WVALUER_WVALUE(x)            (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_WINDEXR */
+#define MCF_USB_WINDEXR_WINDEX(x)            (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_WLENGTHR */
+#define MCF_USB_WLENGTHR_WLENGTH(x)          (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPOUTACR */
+#define MCF_USB_EPOUTACR_TTYPE(x)            (((x)&0x3)<<0)
+#define MCF_USB_EPOUTACR_TTYPE_ISOC          (0x1)
+#define MCF_USB_EPOUTACR_TTYPE_BULK          (0x2)
+#define MCF_USB_EPOUTACR_TTYPE_INT           (0x3)
+
+/* Bit definitions and macros for MCF_USB_EPOUTMPSR */
+#define MCF_USB_EPOUTMPSR_MAXPKTSZ(x)        (((x)&0x7FF)<<0)
+#define MCF_USB_EPOUTMPSR_ADDTRANS(x)        (((x)&0x3)<<0xB)
+
+/* Bit definitions and macros for MCF_USB_EPOUTIFR */
+#define MCF_USB_EPOUTIFR_IFNUM(x)            (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPOUTSR */
+#define MCF_USB_EPOUTSR_HALT                 (0x1)
+#define MCF_USB_EPOUTSR_ACTIVE               (0x2)
+#define MCF_USB_EPOUTSR_PSTALL               (0x4)
+#define MCF_USB_EPOUTSR_CCOMP                (0x8)
+#define MCF_USB_EPOUTSR_TXZERO               (0x20)
+#define MCF_USB_EPOUTSR_INT                  (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPOUTSFR */
+#define MCF_USB_EPOUTSFR_FRMNUM(x)           (((x)&0x7FF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPINACR */
+#define MCF_USB_EPINACR_TTYPE(x)             (((x)&0x3)<<0)
+#define MCF_USB_EPINACR_TTYPE_ISOC           (0x1)
+#define MCF_USB_EPINACR_TTYPE_BULK           (0x2)
+#define MCF_USB_EPINACR_TTYPE_INT            (0x3)
+
+/* Bit definitions and macros for MCF_USB_EPINMPSR */
+#define MCF_USB_EPINMPSR_MAXPKTSZ(x)         (((x)&0x7FF)<<0)
+#define MCF_USB_EPINMPSR_ADDTRANS(x)         (((x)&0x3)<<0xB)
+
+/* Bit definitions and macros for MCF_USB_EPINIFR */
+#define MCF_USB_EPINIFR_IFNUM(x)             (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPINSR */
+#define MCF_USB_EPINSR_HALT                  (0x1)
+#define MCF_USB_EPINSR_ACTIVE                (0x2)
+#define MCF_USB_EPINSR_PSTALL                (0x4)
+#define MCF_USB_EPINSR_CCOMP                 (0x8)
+#define MCF_USB_EPINSR_TXZERO                (0x20)
+#define MCF_USB_EPINSR_INT                   (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPINSFR */
+#define MCF_USB_EPINSFR_FRMNUM(x)            (((x)&0x7FF)<<0)
+
+/* Bit definitions and macros for MCF_USB_USBSR */
+#define MCF_USB_USBSR_ISOERREP(x)            (((x)&0xF)<<0)
+#define MCF_USB_USBSR_SUSP                   (0x80)
+
+/* Bit definitions and macros for MCF_USB_USBCR */
+#define MCF_USB_USBCR_RESUME                 (0x1)
+#define MCF_USB_USBCR_APPLOCK                (0x2)
+#define MCF_USB_USBCR_RST                    (0x4)
+#define MCF_USB_USBCR_RAMEN                  (0x8)
+#define MCF_USB_USBCR_RAMSPLIT               (0x20)
+
+/* Bit definitions and macros for MCF_USB_DRAMCR */
+#define MCF_USB_DRAMCR_DADR(x)               (((x)&0x3FF)<<0)
+#define MCF_USB_DRAMCR_DSIZE(x)              (((x)&0x7FF)<<0x10)
+#define MCF_USB_DRAMCR_BSY                   (0x40000000)
+#define MCF_USB_DRAMCR_START                 (0x80000000)
+
+/* Bit definitions and macros for MCF_USB_DRAMDR */
+#define MCF_USB_DRAMDR_DDAT(x)               (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_USBISR */
+#define MCF_USB_USBISR_ISOERR                (0x1)
+#define MCF_USB_USBISR_FTUNLCK               (0x2)
+#define MCF_USB_USBISR_SUSP                  (0x4)
+#define MCF_USB_USBISR_RES                   (0x8)
+#define MCF_USB_USBISR_UPDSOF                (0x10)
+#define MCF_USB_USBISR_RSTSTOP               (0x20)
+#define MCF_USB_USBISR_SOF                   (0x40)
+#define MCF_USB_USBISR_MSOF                  (0x80)
+
+/* Bit definitions and macros for MCF_USB_USBIMR */
+#define MCF_USB_USBIMR_ISOERR                (0x1)
+#define MCF_USB_USBIMR_FTUNLCK               (0x2)
+#define MCF_USB_USBIMR_SUSP                  (0x4)
+#define MCF_USB_USBIMR_RES                   (0x8)
+#define MCF_USB_USBIMR_UPDSOF                (0x10)
+#define MCF_USB_USBIMR_RSTSTOP               (0x20)
+#define MCF_USB_USBIMR_SOF                   (0x40)
+#define MCF_USB_USBIMR_MSOF                  (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPSTAT */
+#define MCF_USB_EPSTAT_RST                   (0x1)
+#define MCF_USB_EPSTAT_FLUSH                 (0x2)
+#define MCF_USB_EPSTAT_DIR                   (0x80)
+#define MCF_USB_EPSTAT_BYTECNT(x)            (((x)&0xFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_USB_EPISR */
+#define MCF_USB_EPISR_EOF                    (0x1)
+#define MCF_USB_EPISR_EOT                    (0x4)
+#define MCF_USB_EPISR_FIFOLO                 (0x10)
+#define MCF_USB_EPISR_FIFOHI                 (0x20)
+#define MCF_USB_EPISR_ERR                    (0x40)
+#define MCF_USB_EPISR_EMT                    (0x80)
+#define MCF_USB_EPISR_FU                     (0x100)
+
+/* Bit definitions and macros for MCF_USB_EPIMR */
+#define MCF_USB_EPIMR_EOF                    (0x1)
+#define MCF_USB_EPIMR_EOT                    (0x4)
+#define MCF_USB_EPIMR_FIFOLO                 (0x10)
+#define MCF_USB_EPIMR_FIFOHI                 (0x20)
+#define MCF_USB_EPIMR_ERR                    (0x40)
+#define MCF_USB_EPIMR_EMT                    (0x80)
+#define MCF_USB_EPIMR_FU                     (0x100)
+
+/* Bit definitions and macros for MCF_USB_EPFRCFGR */
+#define MCF_USB_EPFRCFGR_DEPTH(x)            (((x)&0x1FFF)<<0)
+#define MCF_USB_EPFRCFGR_BASE(x)             (((x)&0xFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_USB_EPFDR */
+#define MCF_USB_EPFDR_RX_TXDATA(x)           (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPFSR */
+#define MCF_USB_EPFSR_EMT                    (0x10000)
+#define MCF_USB_EPFSR_ALRM                   (0x20000)
+#define MCF_USB_EPFSR_FU                     (0x40000)
+#define MCF_USB_EPFSR_FR                     (0x80000)
+#define MCF_USB_EPFSR_OF                     (0x100000)
+#define MCF_USB_EPFSR_UF                     (0x200000)
+#define MCF_USB_EPFSR_RXW                    (0x400000)
+#define MCF_USB_EPFSR_FAE                    (0x800000)
+#define MCF_USB_EPFSR_FRM(x)                 (((x)&0xF)<<0x18)
+#define MCF_USB_EPFSR_TXW                    (0x40000000)
+#define MCF_USB_EPFSR_IP                     (0x80000000)
+
+/* Bit definitions and macros for MCF_USB_EPFCR */
+#define MCF_USB_EPFCR_COUNTER(x)             (((x)&0xFFFF)<<0)
+#define MCF_USB_EPFCR_TXWMSK                 (0x40000)
+#define MCF_USB_EPFCR_OFMSK                  (0x80000)
+#define MCF_USB_EPFCR_UFMSK                  (0x100000)
+#define MCF_USB_EPFCR_RXWMSK                 (0x200000)
+#define MCF_USB_EPFCR_FAEMSK                 (0x400000)
+#define MCF_USB_EPFCR_IPMSK                  (0x800000)
+#define MCF_USB_EPFCR_GR(x)                  (((x)&0x7)<<0x18)
+#define MCF_USB_EPFCR_FRM                    (0x8000000)
+#define MCF_USB_EPFCR_TMR                    (0x10000000)
+#define MCF_USB_EPFCR_WFR                    (0x20000000)
+#define MCF_USB_EPFCR_SHAD                   (0x80000000)
+
+/* Bit definitions and macros for MCF_USB_EPFAR */
+#define MCF_USB_EPFAR_ALRMP(x)               (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPFRP */
+#define MCF_USB_EPFRP_RP(x)                  (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPFWP */
+#define MCF_USB_EPFWP_WP(x)                  (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPLRFP */
+#define MCF_USB_EPLRFP_LRFP(x)               (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPLWFP */
+#define MCF_USB_EPLWFP_LWFP(x)               (((x)&0xFFF)<<0)
+
+
+#endif /* __MCF5475_USB_H__ */

BaS_codewarrior/firebeeV1/headers/MCF5475_XLB.h

@@ -0,0 +1,101 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_XLB_H__
+#define __MCF5475_XLB_H__
+
+
+/*********************************************************************
+*
+* XL Bus Arbiter (XLB)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_XLB_XARB_CFG                     (*(vuint32*)(&__MBAR[0x240]))
+#define MCF_XLB_XARB_VER                     (*(vuint32*)(&__MBAR[0x244]))
+#define MCF_XLB_XARB_SR                      (*(vuint32*)(&__MBAR[0x248]))
+#define MCF_XLB_XARB_IMR                     (*(vuint32*)(&__MBAR[0x24C]))
+#define MCF_XLB_XARB_ADRCAP                  (*(vuint32*)(&__MBAR[0x250]))
+#define MCF_XLB_XARB_SIGCAP                  (*(vuint32*)(&__MBAR[0x254]))
+#define MCF_XLB_XARB_ADRTO                   (*(vuint32*)(&__MBAR[0x258]))
+#define MCF_XLB_XARB_DATTO                   (*(vuint32*)(&__MBAR[0x25C]))
+#define MCF_XLB_XARB_BUSTO                   (*(vuint32*)(&__MBAR[0x260]))
+#define MCF_XLB_XARB_PRIEN                   (*(vuint32*)(&__MBAR[0x264]))
+#define MCF_XLB_XARB_PRI                     (*(vuint32*)(&__MBAR[0x268]))
+
+
+/* Bit definitions and macros for MCF_XLB_XARB_CFG */
+#define MCF_XLB_XARB_CFG_AT                  (0x2)
+#define MCF_XLB_XARB_CFG_DT                  (0x4)
+#define MCF_XLB_XARB_CFG_BA                  (0x8)
+#define MCF_XLB_XARB_CFG_PM(x)               (((x)&0x3)<<0x5)
+#define MCF_XLB_XARB_CFG_SP(x)               (((x)&0x7)<<0x8)
+#define MCF_XLB_XARB_CFG_PLDIS               (0x80000000)
+
+/* Bit definitions and macros for MCF_XLB_XARB_VER */
+#define MCF_XLB_XARB_VER_VER(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_SR */
+#define MCF_XLB_XARB_SR_AT                   (0x1)
+#define MCF_XLB_XARB_SR_DT                   (0x2)
+#define MCF_XLB_XARB_SR_BA                   (0x4)
+#define MCF_XLB_XARB_SR_TTM                  (0x8)
+#define MCF_XLB_XARB_SR_ECW                  (0x10)
+#define MCF_XLB_XARB_SR_TTR                  (0x20)
+#define MCF_XLB_XARB_SR_TTA                  (0x40)
+#define MCF_XLB_XARB_SR_MM                   (0x80)
+#define MCF_XLB_XARB_SR_SEA                  (0x100)
+
+/* Bit definitions and macros for MCF_XLB_XARB_IMR */
+#define MCF_XLB_XARB_IMR_ATE                 (0x1)
+#define MCF_XLB_XARB_IMR_DTE                 (0x2)
+#define MCF_XLB_XARB_IMR_BAE                 (0x4)
+#define MCF_XLB_XARB_IMR_TTME                (0x8)
+#define MCF_XLB_XARB_IMR_ECWE                (0x10)
+#define MCF_XLB_XARB_IMR_TTRE                (0x20)
+#define MCF_XLB_XARB_IMR_TTAE                (0x40)
+#define MCF_XLB_XARB_IMR_MME                 (0x80)
+#define MCF_XLB_XARB_IMR_SEAE                (0x100)
+
+/* Bit definitions and macros for MCF_XLB_XARB_ADRCAP */
+#define MCF_XLB_XARB_ADRCAP_ADRCAP(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_SIGCAP */
+#define MCF_XLB_XARB_SIGCAP_TT(x)            (((x)&0x1F)<<0)
+#define MCF_XLB_XARB_SIGCAP_TBST             (0x20)
+#define MCF_XLB_XARB_SIGCAP_TSIZ(x)          (((x)&0x7)<<0x7)
+
+/* Bit definitions and macros for MCF_XLB_XARB_ADRTO */
+#define MCF_XLB_XARB_ADRTO_ADRTO(x)          (((x)&0xFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_DATTO */
+#define MCF_XLB_XARB_DATTO_DATTO(x)          (((x)&0xFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_BUSTO */
+#define MCF_XLB_XARB_BUSTO_BUSTO(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_PRIEN */
+#define MCF_XLB_XARB_PRIEN_M0                (0x1)
+#define MCF_XLB_XARB_PRIEN_M2                (0x4)
+#define MCF_XLB_XARB_PRIEN_M3                (0x8)
+
+/* Bit definitions and macros for MCF_XLB_XARB_PRI */
+#define MCF_XLB_XARB_PRI_M0P(x)              (((x)&0x7)<<0)
+#define MCF_XLB_XARB_PRI_M2P(x)              (((x)&0x7)<<0x8)
+#define MCF_XLB_XARB_PRI_M3P(x)              (((x)&0x7)<<0xC)
+
+
+#endif /* __MCF5475_XLB_H__ */

BaS_codewarrior/firebeeV1/lcf/DDRAM.lcf

@@ -0,0 +1,88 @@
+# Sample Linker Command File for CodeWarrior for ColdFire
+
+KEEP_SECTION {.vectortable}
+
+# Memory ranges	
+
+MEMORY {
+   code	        (RWX) : ORIGIN = 0x00000000, LENGTH = 0x0
+}
+
+SECTIONS {
+ 
+#BaS Basis adresse
+	___Bas_base	= 	0x1FE00000;
+	
+# Board Memory map definitions from linker command files:
+# __SDRAM,__SDRAM_SIZE, __CODE_FLASH, __CODE_FLASH_SIZE 
+# linker symbols must be defined in the linker command file.
+
+#Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
+   ___BOOT_FLASH           = 0xE0000000;
+   ___BOOT_FLASH_SIZE      = 0x00800000;
+#SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes	
+   ___SDRAM                = 0x00000000;
+   ___SDRAM_SIZE           = 0x20000000;
+   
+#VIDEO RAM BASIS
+   ___VRAM                = 0x60000000;
+   
+# MCF5475 Derivative Memory map definitions from linker command files:
+# __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
+# linker symbols must be defined in the linker command file.
+
+# Memory mapped registers
+   ___MBAR                 = 0xFF000000;
+   ___MMUBAR               = 0xFF040000;
+# 4KB on-chip Core SRAM0: -> exception table and exception stack
+   ___RAMBAR0              = 0xFF100000;
+   ___RAMBAR0_SIZE         = 0x00001000;
+
+   ___SUP_SP = ___RAMBAR0 + ___RAMBAR0_SIZE - 4;
+   
+# 4KB on-chip Core SRAM1: -> modified code
+   ___RAMBAR1              = 0xFF101000;
+   ___RAMBAR1_SIZE         = 0x00001000;
+
+# Systemveriablem:******************************************
+# RAMBAR0 0 bis 0x7FF -> exception vectoren
+_rt_mod    = ___RAMBAR0 + 0x800;   
+_rt_ssp    = ___RAMBAR0 + 0x804;   
+_rt_usp    = ___RAMBAR0 + 0x808;   
+_rt_vbr    = ___RAMBAR0 + 0x80C;  	# (8)01 
+_rt_cacr   = ___RAMBAR0 + 0x810;   	# 002
+_rt_asid   = ___RAMBAR0 + 0x814;   	# 003
+_rt_acr0   = ___RAMBAR0 + 0x818;   	# 004
+_rt_acr1   = ___RAMBAR0 + 0x81c;   	# 005
+_rt_acr2   = ___RAMBAR0 + 0x820;   	# 006
+_rt_acr3   = ___RAMBAR0 + 0x824;   	# 007
+_rt_mmubar = ___RAMBAR0 + 0x828;	# 008
+_rt_sr     = ___RAMBAR0 + 0x82c;   
+_d0_save   = ___RAMBAR0 + 0x830;
+_a7_save   = ___RAMBAR0 + 0x834;
+_video_tlb = ___RAMBAR0 + 0x838;
+_video_sbt = ___RAMBAR0 + 0x83C;
+_rt_mbar   = ___RAMBAR0 + 0x844;   	# (c)0f
+#***********************************************************
+
+# 32KB on-chip System SRAM
+   ___SYS_SRAM             = 0xFF010000;
+   ___SYS_SRAM_SIZE        = 0x00008000;
+  
+  
+	.text :
+	{
+		startcf.c(.text)
+		sysinit.c(.text)
+		BaS.c(.text)
+		sd_card.c(.text)
+		mmu.s(.text)
+		exceptions.s(.text)
+		supervisor.s(.text)
+		ewf.s(.text)
+		illegal_instruction.s(.text)
+		last.c(.text)
+		. = ALIGN (0x4);
+	} > code
+
+}

BaS_codewarrior/firebeeV1/lcf/FLASH.lcf

@@ -0,0 +1,88 @@
+# Sample Linker Command File for CodeWarrior for ColdFire
+
+KEEP_SECTION {.vectortable}
+
+# Memory ranges	
+
+MEMORY {
+   code        (RX)  : ORIGIN = 0xE0000000, LENGTH = 0x00200000
+}
+
+SECTIONS {
+ 
+#BaS Basis adresse
+	___Bas_base		  = 0x1FE00000;
+
+# Board Memory map definitions from linker command files:
+# __SDRAM,__SDRAM_SIZE, __CODE_FLASH, __CODE_FLASH_SIZE 
+# linker symbols must be defined in the linker command file.
+
+#Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
+   ___BOOT_FLASH           = 0xE0000000;
+   ___BOOT_FLASH_SIZE      = 0x00800000;
+#SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes	
+   ___SDRAM                = 0x00000000;
+   ___SDRAM_SIZE           = 0x20000000;
+   
+#VIDEO RAM BASIS
+   ___VRAM                = 0x60000000;
+
+# MCF5475 Derivative Memory map definitions from linker command files:
+# __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
+# linker symbols must be defined in the linker command file.
+
+# Memory mapped registers
+   ___MBAR                 = 0xFF000000;
+   ___MMUBAR               = 0xFF040000;
+# 4KB on-chip Core SRAM0: -> exception table and exception stack
+   ___RAMBAR0              = 0xFF100000;
+   ___RAMBAR0_SIZE         = 0x00001000;
+
+   ___SUP_SP = ___RAMBAR0 + ___RAMBAR0_SIZE - 4;
+   
+# 4KB on-chip Core SRAM1: -> modified code
+   ___RAMBAR1              = 0xFF101000;
+   ___RAMBAR1_SIZE         = 0x00001000;
+
+# Systemveriablem:******************************************
+# RAMBAR0 0 bis 0x7FF -> exception vectoren
+_rt_mod    = ___RAMBAR0 + 0x800;   
+_rt_ssp    = ___RAMBAR0 + 0x804;   
+_rt_usp    = ___RAMBAR0 + 0x808;   
+_rt_vbr    = ___RAMBAR0 + 0x80C;  	# (8)01 
+_rt_cacr   = ___RAMBAR0 + 0x810;   	# 002
+_rt_asid   = ___RAMBAR0 + 0x814;   	# 003
+_rt_acr0   = ___RAMBAR0 + 0x818;   	# 004
+_rt_acr1   = ___RAMBAR0 + 0x81c;   	# 005
+_rt_acr2   = ___RAMBAR0 + 0x820;   	# 006
+_rt_acr3   = ___RAMBAR0 + 0x824;   	# 007
+_rt_mmubar = ___RAMBAR0 + 0x828;	# 008
+_rt_sr     = ___RAMBAR0 + 0x82c;   
+_d0_save   = ___RAMBAR0 + 0x830;
+_a7_save   = ___RAMBAR0 + 0x834;
+_video_tlb = ___RAMBAR0 + 0x838;
+_video_sbt = ___RAMBAR0 + 0x83C;
+_rt_mbar   = ___RAMBAR0 + 0x844;   	# (c)0f
+#***********************************************************
+
+# 32KB on-chip System SRAM
+   ___SYS_SRAM             = 0xFF010000;
+   ___SYS_SRAM_SIZE        = 0x00008000;
+
+  .code	    : {} > code		
+
+	.text :
+	{
+		startcf.c(.text)
+		sysinit.c(.text)
+		BaS.c(.text)
+		sd_card.c(.text)
+		mmu.s(.text)
+		exceptions.s(.text)
+		supervisor.s(.text)
+		ewf.s(.text)
+		illegal_instruction.s(.text)
+		last.c(.text)
+	} >> code
+
+}

BaS_codewarrior/firebeeV1/sources/BaS.c

@@ -0,0 +1,304 @@
+/*
+ * BaS
+ *
+ */
+
+
+#include "MCF5475.h"
+#include "startcf.h"
+
+extern unsigned long far __SP_AFTER_RESET[];
+extern unsigned long far __Bas_base[];
+
+	/* imported routines */
+extern int mmu_init();
+extern int mmutr_miss();
+extern int vec_init();
+extern int illegal_table_make();
+extern int cf68k_initialize();
+
+/********************************************************************/
+	/* warte_routinen /*
+********************************************************************/
+
+void warte_10ms(void)
+{
+	asm
+	{
+warte_10ms:
+		move.l		d0,-(sp) 		
+  		move.l		MCF_SLT0_SCNT,d0
+  		sub.l		#1320000,d0
+ warte_d6:
+		cmp.l		MCF_SLT0_SCNT,d0
+		bcs			warte_d6
+		move.l		(sp)+,d0
+	}
+}
+
+void warte_1ms(void)
+{
+	asm
+	{
+warte_1ms:
+		move.l		d0,-(sp) 		
+  		move.l		MCF_SLT0_SCNT,d0
+  		sub.l		#132000,d0
+ warte_d6:
+		cmp.l		MCF_SLT0_SCNT,d0
+		bcs			warte_d6
+		move.l		(sp)+,d0
+	}
+}
+
+void warte_100us(void)
+{
+	asm
+	{
+ warte_100us:
+		move.l		d0,-(sp) 		
+  		move.l		MCF_SLT0_SCNT,d0
+  		sub.l		#13200,d0
+ warte_d6:
+		cmp.l		MCF_SLT0_SCNT,d0
+		bcs			warte_d6
+		move.l		(sp)+,d0
+	}
+}
+
+void warte_50us(void)
+{
+	asm
+	{
+warte_50us:
+		move.l		d0,-(sp) 		
+  		move.l		MCF_SLT0_SCNT,d0
+  		sub.l		#6600,d0
+ warte_d6:
+		cmp.l		MCF_SLT0_SCNT,d0
+		bcs			warte_d6
+		move.l		(sp)+,d0
+	}
+}
+void warte_10us(void)
+{
+	asm
+	{
+warte_10us:
+		move.l		d0,-(sp) 		
+  		move.l		MCF_SLT0_SCNT,d0
+  		sub.l		#1320,d0
+ warte_d6:
+		cmp.l		MCF_SLT0_SCNT,d0
+		bcs			warte_d6
+		move.l		(sp)+,d0
+	}
+}
+
+void warte_1us(void)
+{
+	asm
+	{
+warte_1us:
+		move.l		d0,-(sp) 		
+  		move.l		MCF_SLT0_SCNT,d0
+  		sub.l		#132,d0
+ warte_d6:
+		cmp.l		MCF_SLT0_SCNT,d0
+		bcs			warte_d6
+		move.l		(sp)+,d0
+	}
+}
+
+/********************************************************************/
+void BaS(void)
+{
+		int		az_sectors;
+		int		sd_status,i;
+
+		az_sectors = sd_card_init();
+		
+		if(az_sectors>0)
+		{
+			sd_card_idle();
+		}
+	
+	asm
+{
+		move.b	DIP_SWITCH,d0				// dip schalter adresse
+		btst.b	#6,d0
+		beq		firetos_kopieren
+		lea		MCF_PSC0_PSCTB_8BIT,a6
+		lea		MCF_PSC3_PSCTB_8BIT,a3
+		lea		MCF_PSC3_PSCRB_8BIT,a4
+		lea		MCF_PSC3_PSCRFCNT,a5
+		move.l 	#'ACPF',(a3)					// SEND SYNC MARKE, MCF BEREIT
+		bsr 	warte_10ms
+		move.l 	#'PIC ',(a6)
+		move.b 	(a4),d0
+		move.b	d0,(a6)
+		move.b 	(a4),d1
+		move.b	d1,(a6)
+		move.b 	(a4),d2
+		move.b	d2,(a6)
+		move.l	#0x0a0d,(a6)
+		move.b 	#0x01,(a3)						// RTC DATEN ANFORDERN
+// TOS kopieren
+		lea		0x00e00000,a0
+		lea		0xe0600000,a1					// default tos
+		lea		0xe0700000,a2					// 1MB
+		move.b	DIP_SWITCH,d0					// dip schalter adresse
+		btst.b	#6,d0
+		bne		cptos_loop
+firetos_kopieren:
+		lea		0x00e00000,a0
+		lea		0xe0400000,a1
+		lea		0xe0500000,a2					// 1MB
+cptos_loop:
+		move.l	(a1)+,(a0)+
+		cmp.l	a2,a1
+		blt		cptos_loop
+/***************************************************************/
+/*   div inits       
+/***************************************************************/
+div_inits:
+		move.b	DIP_SWITCH,d0				// dip schalter adresse
+		btst.b	#6,d0
+		beq		video_setup
+// rtc daten, mmu set, etc nur wenn switch 6 = off
+		lea		0xffff8961,a0
+		clr.l	d1	
+		moveq	#64,d2
+		move.b	(a4),d0
+		cmp.b	#0x81,d0
+		bne		not_rtc	
+loop_sr:
+		move.b	(a4),d0
+		move.b  d1,(a0)
+		move.b	d0,2(a0)
+		addq.l	#1,d1
+		cmp.b	d1,d2
+		bne		loop_sr
+/*
+		// Set the NVRAM checksum as invalid
+		move.b	#63,(a0)
+		move.b	2(a0),d0
+		add		#1,d0
+		move.b	d0,2(a0)
+*/
+not_rtc:
+		bsr		mmu_init
+		bsr		vec_init
+		bsr		illegal_table_make
+		
+// interrupts
+		clr.l	0xf0010004					// disable all interrupts
+		lea		MCF_EPORT_EPPAR,a0
+		move.w	#0xaaa8,(a0)				// falling edge all,
+
+// timer 0 on mit int -> video change -------------------------------------------
+		move.l	#MCF_GPT_GMS_ICT(1)|MCF_GPT_GMS_IEN|MCF_GPT_GMS_TMS(1),d0	//caputre mit int on rising edge
+		move.l	d0,MCF_GPT0_GMS
+		moveq.l	#0x3f,d0					// max prority interrutp
+ 		move.b	d0,MCF_INTC_ICR62			// setzen
+// -------------------------------------------------
+		move.b	#0xfe,d0
+		move.b	d0,0xf0010004				// enable int 1-7
+		nop
+		lea		MCF_EPORT_EPIER,a0
+		move.b	#0xfe,(a0)					// int 1-7 on
+		nop
+		lea		MCF_EPORT_EPFR,a0
+		move.b	#0xff,(a0)					// alle pending interrupts l<>schen
+		nop
+		lea		MCF_INTC_IMRL,a0
+		move.l	#0xFFFFFF00,(a0)			// int 1-7 on
+		lea		MCF_INTC_IMRH,a0
+		move.l	#0xBFFFFFFE,(a0)			// psc3 and timer 0 int on
+
+		move.l	#MCF_MMU_MMUCR_EN,d0
+  		move.l	d0,MCF_MMU_MMUCR			// mmu on
+		nop
+		nop
+/********************************************************************/
+/* IDE reset
+/********************************************************************/
+		lea		0xffff8802,a0
+		move.b	#14,-2(a0)
+		move.b	#0x80,(a0)
+		bsr		warte_1ms
+		clr.b	(a0)
+/********************************************************************/
+/* video setup
+/********************************************************************/
+video_setup:
+		lea		0xf0000410,a0
+// 25MHz
+ 		move.l	#0x032002ba,(a0)+			// horizontal 640x480
+		move.l	#0x020c020a,(a0)+			// vertikal 640x480
+		move.l	#0x0190015d,(a0)+			// horizontal 320x240
+		move.l	#0x020C020A,(a0)+			// vertikal 320x240 */
+/*
+//  32MHz
+		move.l	#0x037002ba,(a0)+			// horizontal 640x480
+		move.l	#0x020d020a,(a0)+			// vertikal 640x480
+		move.l	#0x02A001e0,(a0)+			// horizontal 320x240
+		move.l	#0x05a00160,(a0)+			// vertikal 320x240 
+*/
+		lea		-0x20(a0),a0
+		move.l	#0x01070002,(a0)			// fifo on, refresh on, ddrcs und cke on, video dac on,
+/********************************************************************/
+/* memory setup
+/********************************************************************/
+ 		lea		0x400,a0
+		lea		0x800,a1
+mem_clr_loop:
+		clr.l	(a0)+
+		clr.l	(a0)+
+		clr.l	(a0)+
+		clr.l	(a0)+
+		cmp.l	a0,a1
+		bgt		mem_clr_loop
+
+		moveq	#0x48,d0
+		move.b	d0,0xffff8007
+// stram
+		move.l	#0xe00000,d0				// ende stram
+		move.l	d0,0x42e
+		move.l	#0x752019f3,d0				// memvalid
+		move.l	d0,0x420
+		move.l	#0x237698aa,d0				// memval2
+		move.l	d0,0x43a
+		move.l	#0x5555aaaa,d0				// memval3
+		move.l	d0,0x51a
+// ttram
+   		move.l	#__Bas_base,d0				// ende ttram		
+  		move.l	d0,0x5a4
+  		move.l	#0x1357bd13,d0				// ramvalid
+   		move.l	d0,0x5a8
+   		
+// init acia
+		moveq	#3,d0
+		move.b	d0,0xfffffc00
+		nop
+		move.b	d0,0xfffffc04
+		nop
+		moveq	#0x96,d0
+		move.b	d0,0xfffffc00
+		moveq	#-1,d0
+		nop
+		move.b	d0,0xfffffa0f
+		nop
+		move.b	d0,0xfffffa11
+		nop
+		
+// test auf protect mode ---------------------
+		move.b	DIP_SWITCH,d0
+		btst	#7,d0 
+		beq		no_protect					// nein->
+		move.w	#0x0700,sr
+no_protect:
+		jmp		0xe00030
+
+}
+}

BaS_codewarrior/firebeeV1/sources/exceptions.s

@@ -1,59 +1,59 @@
-/*
- * initialize exception vectors
- */
-#include "startcf.h"
+/********************************************************/
+/*   exception vectoren intialisieren
+/********************************************************/
 
-		.extern __Bas_base
-		.extern __SUP_SP
-		.extern _rom_entry
-		.extern __RAMBAR0
-		.extern _rt_cacr
-		.extern _rt_mod
-		.extern _rt_ssp
-		.extern _rt_usp
-		.extern _rt_vbr
-		.extern _illegal_instruction
-		.extern _privileg_violation
-		.extern _mmutr_miss
-		.extern __MBAR
-		.extern __MMUBAR
-		.extern _video_tlb
-		.extern _video_sbt
-		.extern cpusha
-		.extern _xhdi_sd_install	/* trap #0 exception vector for installation of xhdi SD card driver */
+.include "startcf.h"
+
+.extern ___Bas_base
+.extern ___SUP_SP
+.extern ___BOOT_FLASH
+.extern ___RAMBAR0
+.extern _rt_cacr
+.extern _rt_mod
+.extern _rt_ssp
+.extern _rt_usp
+.extern _rt_vbr
+.extern _illegal_instruction
+.extern _privileg_violation
+.extern _mmutr_miss
+.extern ___MBAR
+.extern ___MMUBAR
+.extern _video_tlb
+.extern _video_sbt
+.extern cpusha
 
 /* Register read/write macros */
-#define MCF_MMU_MMUCR            			__MMUBAR
-#define MCF_MMU_MMUOR                       __MMUBAR+0x04
-#define MCF_MMU_MMUSR                       __MMUBAR+0x08
-#define MCF_MMU_MMUAR                       __MMUBAR+0x10
-#define MCF_MMU_MMUTR                       __MMUBAR+0x14
-#define MCF_MMU_MMUDR                       __MMUBAR+0x18
+#define MCF_MMU_MMUCR            			___MMUBAR
+#define MCF_MMU_MMUOR                       ___MMUBAR+0x04
+#define MCF_MMU_MMUSR                       ___MMUBAR+0x08
+#define MCF_MMU_MMUAR                       ___MMUBAR+0x10
+#define MCF_MMU_MMUTR                       ___MMUBAR+0x14
+#define MCF_MMU_MMUDR                       ___MMUBAR+0x18  
 
-#define MCF_EPORT_EPPAR                     __MBAR+0xF00
-#define MCF_EPORT_EPDDR                     __MBAR+0xF04
-#define MCF_EPORT_EPIER                     __MBAR+0xF05
-#define MCF_EPORT_EPDR                      __MBAR+0xF08
-#define MCF_EPORT_EPPDR                     __MBAR+0xF09
-#define MCF_EPORT_EPFR                      __MBAR+0xF0C
+#define MCF_EPORT_EPPAR                     ___MBAR+0xF00
+#define MCF_EPORT_EPDDR                     ___MBAR+0xF04
+#define MCF_EPORT_EPIER                     ___MBAR+0xF05
+#define MCF_EPORT_EPDR                      ___MBAR+0xF08
+#define MCF_EPORT_EPPDR                     ___MBAR+0xF09
+#define MCF_EPORT_EPFR                      ___MBAR+0xF0C
 
-#define MCF_GPIO_PODR_FEC1L                 __MBAR+0xA07
+#define MCF_GPIO_PODR_FEC1L                 ___MBAR+0xA07
 
-#define MCF_PSC0_PSCTB_8BIT                 __MBAR+0x860C
+#define MCF_PSC0_PSCTB_8BIT                 ___MBAR+0x860C
 
-#define MCF_PSC3_PSCRB_8BIT                 __MBAR+0x890C
-#define MCF_PSC3_PSCTB_8BIT                 __MBAR+0x890C
+#define MCF_PSC3_PSCRB_8BIT                 ___MBAR+0x890C
+#define MCF_PSC3_PSCTB_8BIT                 ___MBAR+0x890C
 
-		.global	_vec_init
+.public	_vec_init
 
 //mmu ---------------------------------------------------
 /* Register read/write macros */
-#define MCF_MMU_MMUCR            			__MMUBAR
-#define MCF_MMU_MMUOR                       __MMUBAR+0x04
-#define MCF_MMU_MMUSR                       __MMUBAR+0x08
-#define MCF_MMU_MMUAR                       __MMUBAR+0x10
-#define MCF_MMU_MMUTR                       __MMUBAR+0x14
-#define MCF_MMU_MMUDR                       __MMUBAR+0x18
+#define MCF_MMU_MMUCR            			___MMUBAR
+#define MCF_MMU_MMUOR                       ___MMUBAR+0x04
+#define MCF_MMU_MMUSR                       ___MMUBAR+0x08
+#define MCF_MMU_MMUAR                       ___MMUBAR+0x10
+#define MCF_MMU_MMUTR                       ___MMUBAR+0x14
+#define MCF_MMU_MMUDR                       ___MMUBAR+0x18
 
 
 /* Bit definitions and macros for MCF_MMU_MMUCR */
@@ -111,7 +111,7 @@
 *********************************************************************/
 
 /* Register read/write macros */
-#define MCF_GPT0_GMS                         __MBAR+0x800
+#define MCF_GPT0_GMS                         ___MBAR+0x800
 
 /*********************************************************************
 *
@@ -119,49 +119,44 @@
 *
 *********************************************************************/
 
-#define MCF_SLT0_SCNT                        __MBAR+0x908
+#define MCF_SLT0_SCNT                        ___MBAR+0x908
 
 /**********************************************************/
 // macros
 /**********************************************************/
-		.altmacro
-		.macro	irq	vector,int_mask,clr_int
-		local	irq_protect
-		local 	sev_supint
-		local	irq_end
-
+irq:	.macro	vector,int_mask,clr_int
 		move.w	#0x2700,sr			// disable interrupt
 		subq.l	#8,a7
-		movem.l	d0/a5,(a7)			// save registers
+		movem.l	d0/a5,(a7)			// register sichern
 		lea		MCF_EPORT_EPFR,a5
-		move.b	#\clr_int,(a5)		// clear int pending
+		move.b	#clr_int,(a5)		// clear int pending
 // test auf protect mode ---------------------
 		move.b	DIP_SWITCHa,d0
 		btst	#7,d0 
-		bne		irq_protect			// ja->
+		bne		@irq_protect		// ja->
 // -------------------------------------------		
-		movem.l	(a7),d0/a5			// restore registers
+		movem.l	(a7),d0/a5			// register zurück
 		addq.l	#8,a7
-		move.l	\vector,-(a7)
-		move	#0x2\int_mask\()00,sr
+		move.l	vector,-(a7)
+		move	#0x2\200,sr
 		rts
-irq_protect:
-		move.l	usp,a5				// get usp
-		tst.b	_rt_mod				// supervisor mode active?
-		bne		sev_supint			// yes ->
-		mov3q.l	#-1,_rt_mod			// enable supervisor mode
-		move.l	a5,_rt_usp			// save rt_usp
-		move.l	_rt_ssp,a5			// get rt_ssp
+@irq_protect:
+		move.l	usp,a5				// usp holen  
+		tst.b	_rt_mod				// supervisor? 
+		bne		@sev_supint			// ja -> 
+		mov3q.l	#-1,_rt_mod			// auf supervisor setzen
+		move.l	a5,_rt_usp			// rt_usp speichern 
+		move.l	_rt_ssp,a5			// rt_ssp holen
 #ifdef cf_stack
-		move.l	12(a7),-(a5)		// transfer pc
+		move.l	12(a7),-(a5)		// pc transferieren 
 		move.l	8(a7),-(a5)			// sr,vec
 #else
-		move.w	8(a7),-(a5)			// vector no
+		move.w	8(a7),-(a5)			// vector nr.
 		move.l	12(a7),-(a5)		// pc verschieben
 		move.w	10(a7),-(a5)		// sr verschieben
 #endif
-		bra		irq_end
-sev_supint:
+		bra		@irq_end
+@sev_supint:
 #ifdef cf_stack
 		move.l	12(a7),-(a5)		// pc transferieren 
 		move.l	8(a7),-(a5)			// sr,vec
@@ -172,57 +167,36 @@ sev_supint:
 		move.w	10(a7),-(a5)		// sr verschieben
 		bset	#5,(a5)				// auf super
 #endif
-irq_end:
+@irq_end:
 		move.l	a5,usp				// usp setzen
-		lea		\vector,a5
+		lea		vector,a5
 		adda.l	_rt_vbr,a5
 		move.l	(a5),12(a7)			// vectoradresse eintragen
-		move.b	#\int_mask,10(a7)	// intmaske setzen
-		movem.l	(a7),d0/a5			// register zur<EFBFBD>ck
+		move.b	#int_mask,10(a7)	// intmaske setzen
+		movem.l	(a7),d0/a5			// register zurück
 		addq.l	#8,a7
 		rte							// und weg 
 		.endm
-
-/*
- * FIXME: this is a GNU gas kludge. Ugly, but I just can't come up with any smarter solution
- *
- * GNU as does not support multi-character constants. At least I don't know of any way it would.
- * The following might look more than strange, but I considered the statement
- *
- * mchar	move.l, 'T,'E,'S,'T,-(SP)
- *
- * somewhat more readable than
- *
- * move.l #1413829460,-(SP)
- *
- * If anybody knows of any better way on how to do this - please do!
- *
- */
-    .macro mchar  st,a,b,c,d,tgt
-    \st #\a << 24|\b<<16|\c<<8|\d,\tgt
-    .endm
-
+/*********************************************************/
 .text
 _vec_init:
-		move.l	a2,-(sp)			// Backup registers
-
  		mov3q.l	#-1,_rt_mod			// rt_mod auf super
  		clr.l	_rt_ssp
  		clr.l	_rt_usp
  		clr.l	_rt_vbr
-		move.l	#__RAMBAR0,d0		// exception vectors reside in rambar0
+		move.l	#___RAMBAR0,d0		// sind in rambar0
 		movec	d0,VBR
 		move.l	d0,a0
 		move.l	a0,a2
 init_vec:
 		move.l	#256,d0
-		lea		std_exc_vec(pc),a1	// standard vector
+		lea		std_exc_vec(pc),a1		// standard vector
 init_vec_loop:
-		move.l	a1,(a2)+			// set standard vector for all exceptions
+		move.l	a1,(a2)+			// mal standard vector für alle setzen
 		subq.l	#1,d0
 		bne		init_vec_loop
 
-		move.l	#__SUP_SP,(a0)
+		move.l	#___SUP_SP,(a0)
 		lea		reset_vector(pc),a1
 		move.l	a1,0x04(a0)
 		lea		acess(pc),a1
@@ -266,10 +240,6 @@ init_vec_loop:
   		move.l	a1,0xdc(a0)
 no_protect_vectors:
 		
-		// trap #0 (without any parameters for now) is used to provide BaS' XHDI
-		// routine address to EmuTOS.
-		lea		_xhdi_sd_install,a1
-		move.l	a1,0x80(a0)				// trap #0 exception vector
 
 // int 1-7
 		lea		irq1(pc),a1
@@ -292,12 +262,10 @@ no_protect_vectors:
 //timer 1 vectors
 		lea		timer0(pc),a1
 		move.l	a1,0x1f8(a0)
-
-		move.l	(sp)+,a2			// Restore registers
 		rts
-/*
- * exception vector routines
- */
+/********************************************************/
+/*   exception vector routinen
+/********************************************************/
 vector_table_start:
 std_exc_vec:
 		move.w	#0x2700,sr			// disable interrupt
@@ -313,12 +281,12 @@ std_exc_vec:
 		add.l	_rt_vbr,d0			// + basis
 		move.l	d0,a5
 		move.l	(a5),d0
-		move.l	4(a7),a5			// a5 zur<EFBFBD>ck
+		move.l	4(a7),a5			// a5 zurück
 		move.l	d0,4(a7)
 		move.w	10(a7),d0
 		bset	#13,d0				// super
 		move.w	d0,sr				// orginal sr wert in super setzen
-		move.l	(a7)+,d0			// d0 zur<EFBFBD>ck
+		move.l	(a7)+,d0			// d0 zurück
 		rts
 stv_protect:
 		move.l	usp,a5				// usp holen  
@@ -343,7 +311,7 @@ stv_protect:
 		add.l	_rt_vbr,d0			// + basis
 		move.l	d0,a5
 		move.l	(a5),12(a7)			// hier geht's weiter
-		movem.l	(a7),d0/a5			// register zur<EFBFBD>ck
+		movem.l	(a7),d0/a5			// register zurück
 		addq.l	#8,a7
 		rte							// und weg 
 sev_sup:
@@ -365,16 +333,16 @@ sev_sup:
 		add.l	_rt_vbr,d0			// + basis
 		move.l	d0,a5
 		move.l	(a5),12(a7)			// hier geht's weiter
-		movem.l	(a7),d0/a5			// register zurück
+		movem.l	(a7),d0/a5			// register zurück
 		addq.l	#8,a7
 		rte							// und weg 
 //*******************************************
 reset_vector:
 		move.w	#0x2700,sr			// disable interrupt
 		move.l	#0x31415926,d0
-		cmp.l	0x426,d0			// reset vector gültg?
+		cmp.l	0x426,d0			// reset vector gültg?
 		beq		std_exc_vec			// ja->
-		jmp		_rom_entry	 		// sonst kaltstart
+		jmp		___BOOT_FLASH 		// sonst kaltstart
 acess:
 		move.w	#0x2700,sr			// disable interrupt
 		move.l	d0,-(sp)			// ++ vr
@@ -394,8 +362,8 @@ access_mmu:
 		btst	#1,d0
 		bne		bus_error
 		move.l	MCF_MMU_MMUAR,d0
-		cmp.l	#__FASTRAM_END,d0	// max User RAM Bereich
-		bge		bus_error			// grösser -> bus error
+		cmp.l	#___Bas_base,d0		// max User RAM Bereich
+		bge		bus_error			// grösser -> bus error
 		bra		_mmutr_miss
 bus_error:
 		move.l	(sp)+,d0
@@ -472,7 +440,7 @@ irq6:				// mfp
 // test auf timeout screen adr change -------------------------------------------------------
 		move.l	_video_sbt,d0
   		beq		irq6_non_sca		// wenn 0 nichts zu tun
-  		sub.l	#0x70000000,d0		// 14 sec abzählen
+  		sub.l	#0x70000000,d0		// 14 sec abzählen
 		lea		MCF_SLT0_SCNT,a5
   		cmp.l	(a5),d0				// aktuelle zeit weg
   		ble		irq6_non_sca		// noch nicht abgelaufen
@@ -492,13 +460,13 @@ irq6:				// mfp
  		swap	d4
  		move.l	d4,MCF_MMU_MMUAR
 		mvz.w	#0x10e,d4
- 		move.l	d4,MCF_MMU_MMUOR	// einträge holen aus mmu
+ 		move.l	d4,MCF_MMU_MMUOR	// einträge holen aus mmu
  		nop
  		move.l	MCF_MMU_MMUTR,d4	// ID holen
  		lsr.l	#2,d4				// bit 9 bis 2
  		cmp.w	#sca_page_ID,d4		// ist screen change ID?
  		bne		irq6_sca_pn			// nein -> page keine screen area next
-// eintrag <EFBFBD>ndern
+// eintrag ändern 		
 		add.l	#std_mmutr,d0
 		move.l	d3,d1				// page 0?
 		beq		irq6_sca_pn0		// ja ->
@@ -532,9 +500,9 @@ irq6_sca_pn:
 
 		move.l	#0x2000,d0
 		move.l	d0,_video_tlb		// anfangszustand wieder herstellen
-  		clr.l	_video_sbt			// zeit löschen
+  		clr.l	_video_sbt			// zeit löschen
 
-  		movem.l	(a7),d0-d4/a0-a1	// register zurück
+  		movem.l	(a7),d0-d4/a0-a1	// register zurück
   		lea		28(a7),a7
 irq6_non_sca:
 // test auf acsi dma -----------------------------------------------------------------
@@ -555,7 +523,7 @@ non_acsi_dma:
 irq6_1:
 		lea		MCF_GPIO_PODR_FEC1L,a5
 		bclr.b	#4,(a5)					// led on
-		lea		blinker,a5
+		lea		blinker(pc),a5
 		addq.l	#1,(a5)					// +1
 		move.l	(a5),d0
 		and.l	#0x80,d0
@@ -571,9 +539,9 @@ irq6_2:
 		move.l	0xF0020000,a5		// vector holen
 		add.l	_rt_vbr,a5			// basis
 		move.l	(a5),d0				// vector holen
-		move.l	4(a7),a5			// a5 zurück
+		move.l	4(a7),a5			// a5 zurück
 		move.l	d0,4(a7)			// vector eintragen
-		move.l	(a7)+,d0			// d0 zurück
+		move.l	(a7)+,d0			// d0 zurück
 		move	#0x2600,sr
 		rts
 irq6_3:
@@ -595,7 +563,7 @@ irq6_3:
 		move.l  0xF0020000,a5		// vector holen: intack routine
 		add.l	_rt_vbr,a5			// virtuelle VBR des Systems
 		move.l	(a5),12(a7)			// hier gehts weiter
-		movem.l	(a7),d0/a5			// register zurück
+		movem.l	(a7),d0/a5			// register zurück
 		addq.l	#8,a7
 		move.b	#6,2(a7)			// intmaske setzen
 		rte 						// und weg 
@@ -614,27 +582,19 @@ sev_sup6:
 		move.l  0xF0020000,a5		// vector holen: intack routine
 		add.l	_rt_vbr,a5			// virtuelle VBR des Systems
 		move.l	(a5),12(a7)			// hier gehts weiter
-		movem.l	(a7),d0/a5			// register zurück
+		movem.l	(a7),d0/a5			// register zurück
 		rts
-
-		.data
 blinker:.long	0
-
-
-		.text
-
-/*
- * pseudo dma
- */
-acsi_dma:							// atari dma
+/**************************************************/
+/* pseudo dma */
+/**************************************************/
+acsi_dma:				// atari dma
 		move.l  a1,-(a7)
 		move.l  d1,-(a7)
 		
-		lea	MCF_PSC0_PSCTB_8BIT,a1	// ++ vr
-                mchar move.l, 'D','M','A','\'' ,(a1)
-		//move.l	#"DMA ",(a1)
-                mchar	move.l,'I','N','T','!',(a1)
-		// move.l	#'INT!',(a1)
+	lea	MCF_PSC0_PSCTB_8BIT,a1		// ++ vr
+	move.l	#'DMA ',(a1)
+	move.l	#'INT!',(a1)
 
 		lea 	0xf0020110,a5		// fifo daten
 acsi_dma_start:
@@ -671,8 +631,8 @@ acsi_dma_wl:
 		sub.l	#16,d0				// byt counter -16
 		bpl		acsi_dma_wl
 acsi_dma_fertig:
-		move.l	a1,-12(a5)			// adresse zur<EFBFBD>ck
-		move.l	d0,-8(a5)			// byt counter zur<EFBFBD>ck
+		move.l	a1,-12(a5)			// adresse zurück
+		move.l	d0,-8(a5)			// byt counter zurück
 acsi_dma_end:
 		tst.b	-4(a5) 				// dma req?
  		bmi		acsi_dma_start		// ja->
@@ -686,14 +646,14 @@ acsi_dma_end:
 		move.l	(a7)+,d1
 		move.l	(a7)+,a1
 		rts
-/*
- * irq 7 = pseudo bus error
- */
+/**************************************************/
+/* irq 7 = pseudo bus error */
+/**************************************************/
 irq7:
 		lea			-12(sp),sp
 		movem.l		d0/a0,(sp)
 
-		move.l		__RAMBAR0+0x008,a0	// Real Access Error handler
+		move.l		___RAMBAR0+0x008,a0	// Real Access Error handler
 		move.l		a0,8(sp)			// This will be the return address for rts
 
 		move.w		12(sp),d0			// Format/Vector word
@@ -710,9 +670,9 @@ irq7:
 		move.l		(sp)+,a0
 		rts								// Forward to the Access Error handler
 
-/*
- * psc3 com PIC MCF
- */
+/**************************************************/
+/* psc3 com PIC MCF */
+/**************************************************/
 psc3:
 		move.w	#0x2700,sr			// disable interrupt
 		lea		-20(a7),a7
@@ -722,15 +682,11 @@ psc3:
 		cmp.b	#2,d1				// anforderung rtc daten?
 		bne		psc3_fertig
 
-		lea	MCF_PSC0_PSCTB_8BIT,a0		// ++ vr
-		mchar	move.l,'\P,'\I,'C,' ,(a0)
-		// move.l	#'PIC ',(a0)
-		mchar	move.l,'I,'N,'T,'\ ,(a0)
-		// move.l	#'INT ',(a0)
-		mchar	move.l,'R,'T,'C,'!,(a0)
-		// move.l	#'RTC!',(a0)
-		mchar 	move.l,0x0d,0x0a,0,0,(a0)
-		//move.l	#0x0d0a,(a0)
+	lea	MCF_PSC0_PSCTB_8BIT,a0		// ++ vr
+	move.l	#'PIC ',(a0)
+	move.l	#'INT ',(a0)
+	move.l	#'RTC!',(a0)
+	move.l	#0x0d0a,(a0)
 
 		lea		0xffff8961,a0
 		lea		MCF_PSC3_PSCTB_8BIT,a3
@@ -745,19 +701,18 @@ loop_sr2:
 		cmp.b	d1,d2
 		bne		loop_sr2
 psc3_fertig:
-		movem.l	(a7),d0-d2/a0/a3	// register zur<EFBFBD>ck
+		movem.l	(a7),d0-d2/a0/a3	// register zurück
 		lea		20(a7),a7
 		RTE
-
-/*
- * timer 0: video change later also others
- */
+/**************************************************/
+/* timer 0: video change later also others
+/**************************************************/
 timer0:
 		move	#0x2700,sr
 //		halt
 		lea		-28(a7),a7
 		movem.l	d0-d4/a0-a1,(a7)
-		mvz.b	0xffff8201,d0		// l<EFBFBD>schen und high byt
+		mvz.b	0xffff8201,d0		// löschen und high byt
 		cmp.w	#2,d0
 		blt		video_chg_end
 		cmp.w	#0xd0,d0			// normale addresse
@@ -777,7 +732,7 @@ video_chg_1page:
 		move.l	d0,d2
 		lsr.l	d4,d2				// neue page
 		move.l	_video_tlb,d4
-		bset.l	d2,d4				// setzen als ge<EFBFBD>ndert
+		bset.l	d2,d4				// setzen als geändert
 		bne		video_chg_2page		// schon gesetzt gewesen? ja->weg
 		move.l	d4,_video_tlb
 		bsr		cpusha				// cache leeren
@@ -799,7 +754,7 @@ video_copy_data_loop:
 // eintrag suchen
 		move.l	d0,MCF_MMU_MMUAR	// addresse
  		move.l	#0x106,d4
- 		move.l	d4,MCF_MMU_MMUOR	// suchen -> schl<EFBFBD>gt neuen vor wenn keiner
+ 		move.l	d4,MCF_MMU_MMUOR	// suchen -> schlägt neuen vor wenn keiner
  		nop
  		move.l	MCF_MMU_MMUOR,d4
  		clr.w	d4
@@ -821,17 +776,17 @@ video_chg_2page:
 		mvz.w	0xffff82a8,d1		// zeilenstart
 		sub.l	d1,d2				// differenz = anzahl zeilen
 		mulu	d2,d4				// maximal 480 zeilen
-		add.l	d4,d0				// video gr<EFBFBD>sse
-		cmp.l	#__STRAM_END,d0		// maximale addresse
-		bge		video_chg_end		// wenn gleich oder gr<EFBFBD>sser -> fertig
+		add.l	d4,d0				// video grösse
+		cmp.l	#0xe00000,d0		// maximale addresse
+		bge		video_chg_end		// wenn gleich oder grösser -> fertig
 		moveq	#20,d4
 		move.l	d0,d2
 		lsr.l	d4,d2				// neue page
 		move.l	_video_tlb,d4
-		bset.l	d2,d4				// setzen als ge<EFBFBD>ndert
+		bset.l	d2,d4				// setzen als geändert
 		beq		video_copy_data		// nein nochmal
 video_chg_end:
-// int pending l<EFBFBD>schen
+// int pending löschen
 		lea		MCF_GPT0_GMS,a0
 		bclr.b	#0,3(a0)
 		nop

BaS_codewarrior/firebeeV1/sources/ii_add.h

@@ -0,0 +1,581 @@
+//--------------------------------------------------------------------
+// add
+//--------------------------------------------------------------------
+/*****************************************************************************************/
+//--------------------------------------------------------------------
+// byt
+//--------------------------------------------------------------------
+//--------------------------------------------------------------------
+// add.b	#im,dx
+//--------------------------------------------------------------------
+addbir_macro:.macro
+	move.w		(a0)+,d0
+	extb.l		d0
+	mvs.b		\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.b		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	ea,dx
+//--------------------------------------------------------------------
+adddd:.macro
+#ifdef	halten_add
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	ea,dx (first ea->a1 z.B. f<>r a0,a1,USP)
+//--------------------------------------------------------------------
+addddd:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		a1,d0
+	mvs.\3		\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	(ea),dx (first ea->a1 z.B. f<>r a0,a1,USP)
+//--------------------------------------------------------------------
+adddda:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	(ay)+,dx (first ea->a1 z.B. f<>r a0,a1,USP)
+//--------------------------------------------------------------------
+addddai:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		(a1)+,d0
+	move.l		a1,\1
+	mvs.\3		\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	-(ay),dx (first ea->a1 z.B. f<>r a0,a1,USP)
+//--------------------------------------------------------------------
+addddad:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		-(a1),d0
+	move.l		a1,\1
+	mvs.\3		\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	d16(ay),dx
+//--------------------------------------------------------------------
+addd16ad:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		\1,a1
+	mvs.w		(a0)+,d0
+	add.l		d0,a1
+	mvs.\3		(a1),d0		
+	mvs.\3		\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	d8(ay,dy),dx
+//--------------------------------------------------------------------
+addd8ad:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		\1,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d0
+	move.l		\2,d1
+.else
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+.endif
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	xxx.w,dx
+//--------------------------------------------------------------------
+addxwd:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.w		(a0)+,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	xxx.l,dx
+//--------------------------------------------------------------------
+addxld:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		(a0)+,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	d16(pc),dx
+//--------------------------------------------------------------------
+addd16pcd:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		a0,a1
+	mvs.w		(a0)+,d0
+	add.l		d0,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	d8(pc,dy),dx
+//--------------------------------------------------------------------
+addd8pcd:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		a0,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d0
+	move.l		\2,d1
+.else
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+.endif
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+//  add dy,ea
+//--------------------------------------------------------------------
+//--------------------------------------------------------------------
+// // add	dx,(ay)  (first ea->a1 z.B. f<>r a0,a1,USP)
+//--------------------------------------------------------------------
+addeda:.macro
+#ifdef	halten_add
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		(a1),d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	dx,(ay)+  (first ea->a1 z.B. f<>r a0,a1,USP)
+//--------------------------------------------------------------------
+addedai:.macro
+#ifdef	halten_add
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		(a1),d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)+
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	dx,(ay)+  
+//--------------------------------------------------------------------
+addedaid:.macro
+#ifdef	halten_add
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2+
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	dx,-(ay)
+//--------------------------------------------------------------------
+addedad:.macro
+#ifdef	halten_add
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		-(a1),d1
+	move.l		a1,\2
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	dx,-(ay)
+//--------------------------------------------------------------------
+addedadd:.macro
+#ifdef	halten_add
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		-\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	dx,d16(ay)
+//--------------------------------------------------------------------
+adde16ad:.macro
+#ifdef	halten_add
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.w		(a0)+,d1
+	add.l		d1,a1
+	mvs.\3		(a1),d1		
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add.w	d8(ay,dy),dx
+//--------------------------------------------------------------------
+adde8ad:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		\2,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d1
+	move.l		\1,d0
+.else
+	mvs.\3		(a1),d1
+	mvs.\3		\1,d0
+.endif
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	dx,xxx.w
+//--------------------------------------------------------------------
+addxwe:.macro
+#ifdef	halten_add
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.w		(a0)+,a1
+	mvs.\3		(a1),d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	dx,xxx.l
+//--------------------------------------------------------------------
+addxle:.macro
+#ifdef	halten_add
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		(a0)+,a1
+	mvs.\3		(a1),d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+/******************************************************/
+// adress register
+/******************************************************/
+//--------------------------------------------------------------------
+// // adda.w	ea,ax (ea = dx;ax;(ax);(ax)+,-(ax)
+//--------------------------------------------------------------------
+addaw:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		a0,pc_off(a7)			// pc auf next
+	movem.l		(a7),d0/d1/a0/a1		// register zurp<72>ck
+	mvs.w		\1,d0
+	adda.l		d0,\2
+	move.l		d0_off(a7),d0
+	lea			ii_ss(a7),a7			// stack erh<72>hen
+	rte
+	.endm;
+//--------------------------------------------------------------------
+// add.w ea,usp
+//--------------------------------------------------------------------
+addawa7:.macro
+#ifdef	halten_add
+	halt
+#endif
+	mvs.w		\1,d0
+	move.l		usp,a1
+	add.l		d0,a1
+	move.l		a1,usp
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // adda.w	ea,usp (ea = dx;ax;(ax);(ax)+,-(ax)
+//--------------------------------------------------------------------
+addawu:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		a0,pc_off(a7)			// pc auf next
+	movem.l		(a7),d0/d1/a0/a1		// register zurp<72>ck
+	move.l		a7,_a7_save
+	move.l		usp,a7
+	move.l		\1,d0
+	adda.l		d0,\2
+	move.l		a7,usp
+	move.l		_a7_save,a7
+	move.l		d0_off(a7),d0
+	lea			ii_ss(a7),a7			// stack erh<72>hen
+	rte
+	.endm;
+//--------------------------------------------------------------------
+// // adda.w	ea,usp (ea = a7 => dx;ax;(ax);(ax)+,-(ax)
+//--------------------------------------------------------------------
+addawua7:.macro
+	addawu		\1,\2
+	.endm;
+//--------------------------------------------------------------------
+// // adda.w	d16(ay),ax
+//--------------------------------------------------------------------
+addawd16a:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		\1,a1
+	mvs.w		(a0)+,d0
+	adda.l		d0,a1
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	add.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // adda.w	d8(ay,dy),ax
+//--------------------------------------------------------------------
+addawd8a:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		\1,a1
+	jsr			ewf
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	add.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // adda.w	xxx.w,ax
+//--------------------------------------------------------------------
+addawxwax:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.w		\1,a1
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	adda.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // adda.w	xxx.l,ax
+//--------------------------------------------------------------------
+addawxlax:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		\1,a1
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	adda.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // adda.w	d16(pc),ax
+//--------------------------------------------------------------------
+addawd16pcax:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.w		\1,a1
+	adda.l		a0,a1
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	adda.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // adda.w	d8(pc,dy),ax
+//--------------------------------------------------------------------
+addawd8pcax:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		a0,a1
+	jsr			ewf
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	adda.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // adda.w	#im,ax
+//--------------------------------------------------------------------
+addawim:.macro
+#ifdef	halten_add
+	halt
+#endif
+	mvs.w		\1,d0
+	move.l		\2,a1
+	adda.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // adda.l	d8(ay,dy),ax
+//--------------------------------------------------------------------
+addald8a:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		\1,a1
+	jsr			ewf
+	move.l		(a1),d0
+	move.l		\2,a1
+	adda.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // adda.l	d8(pc,dy),ax
+//--------------------------------------------------------------------
+addakd8pcax:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		a0,a1
+	jsr			ewf
+	move.l		(a1),d0
+	move.l		\2,a1
+	adda.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//*****************************************************************************************
+// addx 
+//*****************************************************************************************
+//--------------------------------------------------------------------
+// // addx	dy,dx
+//--------------------------------------------------------------------
+adddx:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.b		sr_off+1(a7),d0			//ccr holen
+	move		d0,ccr					//setzen		
+	mvs.\3		\2,d0
+	mvs.\3		\1,d1
+	addx.l		d0,d1
+	set_cc0
+	move.\3		d1,\1
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // addx	-(ay),-(ax)
+//--------------------------------------------------------------------
+adddax:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.b		sr_off+1(a7),d0			//ccr holen
+	move		d0,ccr					//setzen		
+	move.l		\1,a1
+.ifc	\3,l
+	move.l		-(a1),d0
+.else
+	mvs.\3		-(a1),d0
+.endif
+	move.l		\2,a1
+.ifc	\3,l
+	move.l		-(a1),d0
+.else
+	mvs.\3		-(a1),d1
+.endif
+	addx.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------

BaS_codewarrior/firebeeV1/sources/ii_and.h

@@ -0,0 +1,441 @@
+//--------------------------------------------------------------------
+// and
+//--------------------------------------------------------------------
+/*****************************************************************************************/
+//--------------------------------------------------------------------
+// byt
+//--------------------------------------------------------------------
+//--------------------------------------------------------------------
+// and.b	#im,dx
+//--------------------------------------------------------------------
+andbir_macro:.macro
+	move.w		(a0)+,d0
+	extb.l		d0
+	mvs.b		\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.b		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	ea,dx
+//--------------------------------------------------------------------
+anddd:.macro
+#ifdef	halten_and
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	ea(l)->dy(w),dx z.B. f<>r USP
+//--------------------------------------------------------------------
+andddd:.macro
+#ifdef	halten_and
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		a1,d0
+	mvs.\3		\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	(ea)->dy,dx
+//--------------------------------------------------------------------
+anddda:.macro
+#ifdef	halten_and
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	ea->ay,(ay)+,dx
+//--------------------------------------------------------------------
+andddai:.macro
+#ifdef	halten_and
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		(a1)+,d0
+	move.l		a1,\1
+	mvs.\3		\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	ea->ay,-(ay),dx
+//--------------------------------------------------------------------
+andddad:.macro
+#ifdef	halten_and
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		-(a1),d0
+	move.l		a1,\1
+	mvs.\3		\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	d16(ay),dx
+//--------------------------------------------------------------------
+andd16ad:.macro
+#ifdef	halten_and
+	halt
+#endif
+	move.l		\1,a1
+	mvs.w		(a0)+,d0
+	add.l		d0,a1
+	mvs.\3		(a1),d0		
+	mvs.\3		\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	d8(ay,dy),dx
+//--------------------------------------------------------------------
+andd8ad:.macro
+#ifdef	halten_and
+	halt
+#endif
+	move.l		\1,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d0
+	move.l		\2,d1
+.else
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+.endif
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	xxx.w,dx
+//--------------------------------------------------------------------
+andxwd:.macro
+#ifdef	halten_and
+	halt
+#endif
+	move.w		(a0)+,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	xxx.l,dx
+//--------------------------------------------------------------------
+andxld:.macro
+#ifdef	halten_and
+	halt
+#endif
+	move.l		(a0)+,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	d16(pc),dx
+//--------------------------------------------------------------------
+andd16pcd:.macro
+#ifdef	halten_and
+	halt
+#endif
+	move.l		a0,a1
+	mvs.w		(a0)+,d0
+	add.l		d0,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	d8(pc,dy),dx
+//--------------------------------------------------------------------
+andd8pcd:.macro
+#ifdef	halten_and
+	halt
+#endif
+	move.l		a0,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d0
+	move.l		\2,d1
+.else
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+.endif
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+//  and dx,ea
+//--------------------------------------------------------------------
+//--------------------------------------------------------------------
+// // and	dx,(ea)->dy
+//--------------------------------------------------------------------
+andeda:.macro
+#ifdef	halten_and
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		(a1),d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	dx,ea->ay,(ay)+
+//--------------------------------------------------------------------
+andedai:.macro
+#ifdef	halten_and
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		(a1),d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)+
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	dx,ea->ay,(ay)+
+//--------------------------------------------------------------------
+andedaid:.macro
+#ifdef	halten_and
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2+
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	dx,ea->ay,-(ay)
+//--------------------------------------------------------------------
+andedad:.macro
+#ifdef	halten_and
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		-(a1),d1
+	move.l		a1,\2
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	dx,ea->ay,-(ay)
+//--------------------------------------------------------------------
+andedadd:.macro
+#ifdef	halten_and
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		-\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	dx,d16(ay)
+//--------------------------------------------------------------------
+ande16ad:.macro
+#ifdef	halten_and
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.w		(a0)+,d1
+	add.l		d1,a1
+	mvs.\3		(a1),d1		
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and.w	dx,d8(ay,dy)
+//--------------------------------------------------------------------
+ande8ad:.macro
+#ifdef	halten_and
+	halt
+#endif
+	move.l		\2,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d1
+	move.l		\1,d0
+.else
+	mvs.\3		(a1),d1
+	mvs.\3		\1,d0
+.endif
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	dx,xxx.w
+//--------------------------------------------------------------------
+andxwe:.macro
+#ifdef	halten_and
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.w		(a0)+,a1
+	mvs.\3		(a1),d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	dx,xxx.l
+//--------------------------------------------------------------------
+andxle:.macro
+#ifdef	halten_and
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		(a0)+,a1
+	mvs.\3		(a1),d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // anda.w	ea,ax
+//--------------------------------------------------------------------
+andaw:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// and.w ea,usp
+//--------------------------------------------------------------------
+andawa7:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // anda.w	usp?,ax
+//--------------------------------------------------------------------
+andawu:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // anda.w	usp?,usp
+//--------------------------------------------------------------------
+andawua7:.macro
+	andawu		\1,\2
+	.endm;
+//--------------------------------------------------------------------
+// // anda.w	d16(ay),ax
+//--------------------------------------------------------------------
+andawd16a:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // anda.w	d8(ay,dy),ax
+//--------------------------------------------------------------------
+andawd8a:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // anda.w	xxx.w,ax
+//--------------------------------------------------------------------
+andawxwax:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // anda.w	xxx.l,ax
+//--------------------------------------------------------------------
+andawxlax:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // anda.w	d16(pc),ax
+//--------------------------------------------------------------------
+andawd16pcax:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // anda.w	d8(pc,dy),ax
+//--------------------------------------------------------------------
+andawd8pcax:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // anda.w	#im,ax
+//--------------------------------------------------------------------
+andawim:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // anda.l	d8(ay,dy),ax
+//--------------------------------------------------------------------
+andald8a:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // anda.l	d8(pc,dy),ax
+//--------------------------------------------------------------------
+andald8pcax:.macro
+	jmp			ii_error
+	.endm;
+//*****************************************************************************************
+// spezial addx subx etc.
+//--------------------------------------------------------------------
+//--------------------------------------------------------------------
+// // addx	dy,dx
+//--------------------------------------------------------------------
+anddx:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // addx	-(ay),-(ax)
+//--------------------------------------------------------------------
+anddax:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------

BaS_codewarrior/firebeeV1/sources/ii_dbcc.h

@@ -0,0 +1,117 @@
+//--------------------------------------------------------------------
+// dbcc,trapcc
+//--------------------------------------------------------------------
+.text
+ii_lset_dbcc:.macro 
+// dbra
+	ii_lset_opeau	51,c
+	ii_lset_opeau	52,c
+	ii_lset_opeau	53,c
+	ii_lset_opeau	54,c
+	ii_lset_opeau	55,c
+	ii_lset_opeau	56,c
+	ii_lset_opeau	57,c
+	ii_lset_opeau	58,c
+	ii_lset_opeau	59,c
+	ii_lset_opeau	5a,c
+	ii_lset_opeau	5b,c
+	ii_lset_opeau	5c,c
+	ii_lset_opeau	5d,c
+	ii_lset_opeau	5e,c
+	ii_lset_opeau	5f,c
+.endm
+
+ii_dbcc_func:.macro
+ii_0x51c8:
+		dbra_macro	d0_off+2(a7)
+ii_0x51c9:
+		dbra_macro	d1_off+2(a7)
+ii_0x51ca:
+		dbra_macro	d2
+ii_0x51cb:
+		dbra_macro	d3
+ii_0x51cc:
+		dbra_macro	d4
+ii_0x51cd:
+		dbra_macro	d5
+ii_0x51ce:
+		dbra_macro	d6
+ii_0x51cf:
+		dbra_macro	d7
+//---------------------------------------------------------------------------------------------
+// dbcc dx
+//---------------------------------------------------------------------------------------------
+		ii_dbcc	2,hi
+		ii_dbcc 3,ls
+		ii_dbcc	4,cc
+		ii_dbcc 5,cs
+		ii_dbcc	6,ne
+		ii_dbcc	7,eq
+		ii_dbcc	8,vc
+		ii_dbcc 9,vs
+		ii_dbcc a,pl
+		ii_dbcc b,mi
+		ii_dbcc c,ge
+		ii_dbcc	d,lt
+		ii_dbcc	e,gt
+		ii_dbcc	f,le
+.endm		
+//---------------------------------------------------------------------------------------------
+// dbra dx
+//---------------------------------------------------------------------------------------------
+dbra_macro:.macro
+#ifdef	halten_dbcc
+	halt
+#endif
+		mvz.w	\1,d1				// dx holen
+		subq.l	#1,d1				// dx-1
+		bcc		dbra\@				// bra if plus?
+		addq.l	#2,a0				// offset <20>berspringen		
+		move.w	d1,\1				// dx sichern
+ 		ii_end
+dbra\@:
+		move.w	(a0),a1				// offset (wird auf long erweitert)
+		add.l	a1,a0				// dazuadieren
+		move.w	d1,\1				// dx sichern
+ 		ii_end
+.endm
+//---------------------------------------------------------------------------------------------
+// dbcc dx
+//---------------------------------------------------------------------------------------------
+dbcc_macro:.macro
+#ifdef	halten_dbcc
+	halt
+#endif
+		b\2		dbncc\@		
+		mvz.w	\1,d1				// dx holen
+		subq.l	#1,d1				// dx-1
+		bcc		dbcc\@				// bra if plus?
+dbncc\@:
+		addq.l	#2,a0				// offset <20>berspringen		
+		move.w	d1,\1				// dx sichern
+ 		ii_end
+dbcc\@:
+		move.w	(a0),a1				// offset (wird auf long erweitert)
+		add.l	a1,a0				// dazuadieren
+		move.w	d1,\1				// dx sichern
+ 		ii_end
+.endm
+//db
+ii_dbcc:.macro
+ii_0x5\1c8:
+		dbcc_macro	d0_off+2(a7),\2
+ii_0x5\1c9:
+		dbcc_macro	d1_off+2(a7),\2
+ii_0x5\1ca:
+		dbcc_macro	d2,\2
+ii_0x5\1cb:
+		dbcc_macro	d3,\2
+ii_0x5\1cc:
+		dbcc_macro	d4,\2
+ii_0x5\1cd:
+		dbcc_macro	d5,\2
+ii_0x5\1ce:
+		dbcc_macro	d6,\2
+ii_0x5\1cf:
+		dbcc_macro	d7,\2
+.endm

BaS_codewarrior/firebeeV1/sources/ii_ewf.h

@@ -0,0 +1,181 @@
+//--------------------------------------------------------------------
+// extension word format missing
+//--------------------------------------------------------------------
+.text
+ii_ewf_lset:.macro
+// pea
+	ii_lset_opeag	48,7
+	ii_lset	0x487b 
+// jmp
+	ii_lset_opeag	4e,f
+	ii_lset	0x4efb 
+// jsr
+	ii_lset_opeag	4e,b
+	ii_lset	0x4ebb 
+// tas
+	ii_lset_opeag	4a,f
+	ii_lset	0x4ebb 
+// tst.b
+	ii_lset_opeag	4a,3
+	ii_lset	0x4ebb 
+// tst.w
+	ii_lset_opeag	4a,7
+	ii_lset	0x4ebb 
+// tst.l
+	ii_lset_opeag	4a,b
+	ii_lset	0x4ebb 
+// clr.b
+	ii_lset_opeag	42,3
+	ii_lset	0x423b 
+// clr.w
+	ii_lset_opeag	42,7
+	ii_lset	0x423b 
+// clr.l
+	ii_lset_opeag	42,b
+	ii_lset	0x423b 
+.endm
+//---------------------------------------------------------------------------------------------
+ii_ewf_func:.macro
+	ewf_func_macro	pea,487
+	ewf_func_macro	jmp,4ef
+	ewf_func_macro	jsr,4eb
+	ewf_func_macro	tas,4af
+	ewf_func_macro	tstb,4a3
+	ewf_func_macro	tstw,4a7
+	ewf_func_macro	tstl,4ab
+	ewf_func_macro	clrb,423
+	ewf_func_macro	clrw,427
+	ewf_func_macro	clrl,42b
+.endm
+//---------------------------------------------------------------------------------------------
+pea_macro:.macro
+	jsr		ewf
+	move.l	(a1),d0
+	move.l	usp,a1
+	move.l	d0,-(a1)
+	move.l	a1,usp
+	ii_end
+.endm
+
+jmp_macro:.macro
+	jsr		ewf
+	move.l	a1,a0
+	ii_end
+.endm
+
+jsr_macro:.macro
+	jsr		ewf
+	move.l	a1,d0
+	move.l	usp,a1
+	move.l	a0,-(a1)
+	move.l	a1,usp
+	move.l	d0,a0
+	ii_end
+.endm
+	
+tas_macro:.macro
+	jsr		ewf
+	tas		(a1)
+	set_cc0
+	ii_end
+.endm
+	
+tstb_macro:.macro
+	jsr		ewf
+	tst.b	(a1)
+	set_cc0
+	ii_end
+.endm
+	
+tstw_macro:.macro
+	jsr		ewf
+	tst.w	(a1)
+	set_cc0
+	ii_end
+.endm
+	
+tstl_macro:.macro
+	jsr		ewf
+	tst.l	(a1)
+	set_cc0
+	ii_end
+.endm
+	
+clrb_macro:.macro
+	jsr		ewf
+	clr.b	(a1)
+	set_cc0
+	ii_end
+.endm
+	
+clrw_macro:.macro
+	jsr		ewf
+	clr.w	(a1)
+	set_cc0
+	ii_end
+.endm
+	
+clrl_macro:.macro
+	jsr		ewf
+	clr.l	(a1)
+	set_cc0
+	ii_end
+.endm
+//--------------------------------------------------------------------
+ewf_func_macro:.macro	//1=art 2=code
+ii_0x\20:
+#ifdef	halten_ewf
+	halt
+#endif
+	move.l	a0_off(a7),a1
+	\1_macro
+ii_0x\21:
+#ifdef	halten_ewf
+	halt
+#endif
+	move.l	a1_off(a7),a1
+	\1_macro
+ii_0x\22:
+#ifdef	halten_ewf
+	halt
+#endif
+	move.l	a2,a1
+	\1_macro
+ii_0x\23:
+#ifdef	halten_ewf
+	halt
+#endif
+	move.l	a3,a1
+	\1_macro
+ii_0x\24:
+#ifdef	halten_ewf
+	halt
+#endif
+	move.l	a4,a1
+	\1_macro
+ii_0x\25:
+#ifdef	halten_ewf
+	halt
+#endif
+	move.l	a5,a1
+	\1_macro
+ii_0x\26:
+#ifdef	halten_ewf
+	halt
+#endif
+	move.l	a6,a1
+	\1_macro
+ii_0x\27:
+#ifdef	halten_ewf
+	halt
+#endif
+	move.l	usp,a1
+	\1_macro
+ii_0x\2b:
+#ifdef	halten_ewf
+	halt
+#endif
+	move.l	a0,a1
+	\1_macro
+.endm		
+

BaS_codewarrior/firebeeV1/sources/ii_exg.h

@@ -0,0 +1,120 @@
+//--------------------------------------------------------------------
+// exg
+//--------------------------------------------------------------------
+.text
+ii_exg_lset:.macro 
+/*	ii_lset_dxu	c,40	//dx,d0
+	ii_lset_dxu	c,41	//dx,d1
+	ii_lset_dxu	c,42	//dx,d2
+	ii_lset_dxu	c,43	//dx,d3
+	ii_lset_dxu	c,44	//dx,d4
+	ii_lset_dxu	c,45	//dx,d5
+	ii_lset_dxu	c,46	//dx,d6
+	ii_lset_dxu	c,47	//dx,d7
+ 	ii_lset_dxu	c,48	//ax,a0
+	ii_lset_dxu	c,49	//ax,a1
+	ii_lset_dxu	c,4a	//ax,a2
+	ii_lset_dxu	c,4b	//ax,a3
+	ii_lset_dxu	c,4c	//ax,a4
+	ii_lset_dxu	c,4d	//ax,a5
+	ii_lset_dxu	c,4e	//ax,a6
+	ii_lset_dxu	c,4f	//ax,a7 */ -->setting by "and"
+ 	ii_lset_dxu	c,88	//dx,a0
+	ii_lset_dxu	c,89	//dx,a1
+	ii_lset_dxu	c,8a	//dx,a2
+	ii_lset_dxu	c,8b	//dx,a3
+	ii_lset_dxu	c,8c	//dx,a4
+	ii_lset_dxu	c,8d	//dx,a5
+	ii_lset_dxu	c,8e	//dx,a6
+	ii_lset_dxu	c,8f	//dx,a7  
+.endm
+//---------------------------------------------------------------------------------------------
+ii_exg_func:.macro
+// exg dx,dy
+	ii_exg_dx_dx 14,d0_off(a7)
+	ii_exg_dx_dx 34,d1_off(a7)
+	ii_exg_dx_dx 54,d2
+	ii_exg_dx_dx 74,d3
+	ii_exg_dx_dx 94,d4
+	ii_exg_dx_dx b4,d5
+	ii_exg_dx_dx d4,d6
+	ii_exg_dx_dx f4,d7
+// exg ax,ay
+	ii_exg_to_ax 14,a0_off(a7)
+	ii_exg_to_ax 34,a1_off(a7)
+	ii_exg_to_ax 54,a2
+	ii_exg_to_ax 74,a3
+	ii_exg_to_ax 94,a4
+	ii_exg_to_ax b4,a5
+	ii_exg_to_ax d4,a6
+	ii_exg_to_ax f4,usp
+// exg dx,ay
+	ii_exg_to_ax 18,d0_off(a7)
+	ii_exg_to_ax 38,d1_off(a7)
+	ii_exg_to_ax 58,d2
+	ii_exg_to_ax 78,d3
+	ii_exg_to_ax 98,d4
+	ii_exg_to_ax b8,d5
+	ii_exg_to_ax d8,d6
+	ii_exg_to_ax f8,d7
+.endm		
+//---------------------------------------------------------------------------------------------
+exg_macro:.macro
+#ifdef	halten_exg
+	halt
+#endif
+	move.l	\1,a1
+.ifc	\2,usp
+	move.l	a1,d0
+	move.l	\2,a1
+	move.l	a1,\1	
+	move.l	d0,a1
+.else
+	.ifc	\1,usp
+		move.l	a1,d0
+		move.l	\2,a1
+		move.l	a1,\1	
+		move.l	d0,a1
+	.else
+		move.l	\2,\1
+	.endif
+.endif
+	move.l	a1,\2
+	ii_end
+.endm
+ii_exg_dx_dx:.macro
+ii_0xc\10:
+	exg_macro	\2,d0_off(a7)
+ii_0xc\11:
+	exg_macro	\2,d1_off(a7)
+ii_0xc\12:
+	exg_macro	\2,d2
+ii_0xc\13:
+	exg_macro	\2,d3
+ii_0xc\14:
+	exg_macro	\2,d4
+ii_0xc\15:
+	exg_macro	\2,d5
+ii_0xc\16:
+	exg_macro	\2,d6
+ii_0xc\17:
+	exg_macro	\2,d7
+.endm
+ii_exg_to_ax:.macro
+ii_0xc\18:
+	exg_macro	\2,a0_off(a7)
+ii_0xc\19:
+	exg_macro	\2,a1_off(a7)
+ii_0xc\1a:
+	exg_macro	\2,a2
+ii_0xc\1b:
+	exg_macro	\2,a3
+ii_0xc\1c:
+	exg_macro	\2,a4
+ii_0xc\1d:
+	exg_macro	\2,a5
+ii_0xc\1e:
+	exg_macro	\2,a6
+ii_0xc\1f:
+	exg_macro	\2,usp
+.endm

BaS_codewarrior/firebeeV1/sources/ii_func.h

@@ -0,0 +1,945 @@
+//--------------------------------------------------------------------
+// functionen macros
+//--------------------------------------------------------------------
+ii_lset_func:.macro
+/******************************************************/
+// byt
+/******************************************************/
+// func.b dy,dx
+	ii_lset_dx	\1,00						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c			
+	ii_lset_dx	\1,01			
+	ii_lset_dx	\1,02			
+	ii_lset_dx	\1,03			
+	ii_lset_dx	\1,04			
+	ii_lset_dx	\1,05			
+	ii_lset_dx	\1,06			
+	ii_lset_dx	\1,07			
+// func.b ax,dx
+	ii_lset_dxu	\1,08			
+	ii_lset_dxu	\1,09			
+	ii_lset_dxu	\1,0a			
+	ii_lset_dxu	\1,0b			
+	ii_lset_dxu	\1,0c			
+	ii_lset_dxu	\1,0d			
+	ii_lset_dxu	\1,0e			
+	ii_lset_dxu	\1,0f			
+// func.b (ax),dx
+	ii_lset_dx	\1,10			
+	ii_lset_dx	\1,11			
+	ii_lset_dx	\1,12			
+	ii_lset_dx	\1,13			
+	ii_lset_dx	\1,14			
+	ii_lset_dx	\1,15			
+	ii_lset_dx	\1,16			
+	ii_lset_dx	\1,17			
+// func.b (ax)+,dx
+	ii_lset_dx	\1,18			
+	ii_lset_dx	\1,19			
+	ii_lset_dx	\1,1a			
+	ii_lset_dx	\1,1b			
+	ii_lset_dx	\1,1c			
+	ii_lset_dx	\1,1d			
+	ii_lset_dx	\1,1e			
+	ii_lset_dx	\1,1f			
+// func.b -(ax),dx
+	ii_lset_dx	\1,20			
+	ii_lset_dx	\1,21			
+	ii_lset_dx	\1,22			
+	ii_lset_dx	\1,23			
+	ii_lset_dx	\1,24			
+	ii_lset_dx	\1,25			
+	ii_lset_dx	\1,26			
+	ii_lset_dx	\1,27			
+// func.b d16(ax),dx
+	ii_lset_dx	\1,28			
+	ii_lset_dx	\1,29			
+	ii_lset_dx	\1,2a			
+	ii_lset_dx	\1,2b			
+	ii_lset_dx	\1,2c			
+	ii_lset_dx	\1,2d			
+	ii_lset_dx	\1,2e			
+	ii_lset_dx	\1,2f			
+// func.b dd8(ax,dy),dx
+	ii_lset_dx	\1,30			
+	ii_lset_dx	\1,31			
+	ii_lset_dx	\1,32			
+	ii_lset_dx	\1,33			
+	ii_lset_dx	\1,34			
+	ii_lset_dx	\1,35			
+	ii_lset_dx	\1,36			
+	ii_lset_dx	\1,37			
+// func.b xxx.w,dx
+	ii_lset_dx	\1,38						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
+// func.b xxx.l,dx
+	ii_lset_dx	\1,39						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
+// func.b d16(pc),dx
+	ii_lset_dxg	\1,7a						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
+// func.b d8(pc,dy),dx
+	ii_lset_dxg	\1,3b						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
+// func.b #im,dx
+	ii_lset_dxg	\1,3c						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
+/******************************************************/
+// word
+/******************************************************/
+// func.w dy,dx
+	ii_lset_dx	\1,40						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c			
+	ii_lset_dx	\1,41			
+	ii_lset_dx	\1,42			
+	ii_lset_dx	\1,43			
+	ii_lset_dx	\1,44			
+	ii_lset_dx	\1,45			
+	ii_lset_dx	\1,46			
+	ii_lset_dx	\1,47			
+// func.w ax,dx
+	ii_lset_dx	\1,48			
+	ii_lset_dx	\1,49			
+	ii_lset_dx	\1,4a			
+	ii_lset_dx	\1,4b			
+	ii_lset_dx	\1,4c			
+	ii_lset_dx	\1,4d			
+	ii_lset_dx	\1,4e			
+	ii_lset_dx	\1,4f			
+// func.w (ax),dx
+	ii_lset_dx	\1,50			
+	ii_lset_dx	\1,51			
+	ii_lset_dx	\1,52			
+	ii_lset_dx	\1,53			
+	ii_lset_dx	\1,54			
+	ii_lset_dx	\1,55			
+	ii_lset_dx	\1,56			
+	ii_lset_dx	\1,57			
+// func.w (ax)+,dx
+	ii_lset_dx	\1,58			
+	ii_lset_dx	\1,59			
+	ii_lset_dx	\1,5a			
+	ii_lset_dx	\1,5b			
+	ii_lset_dx	\1,5c			
+	ii_lset_dx	\1,5d			
+	ii_lset_dx	\1,5e			
+	ii_lset_dx	\1,5f			
+// func.w -(ax),dx
+	ii_lset_dx	\1,60			
+	ii_lset_dx	\1,61			
+	ii_lset_dx	\1,62			
+	ii_lset_dx	\1,63			
+	ii_lset_dx	\1,64			
+	ii_lset_dx	\1,65			
+	ii_lset_dx	\1,66			
+	ii_lset_dx	\1,67			
+// func.w d16(ax),dx
+	ii_lset_dx	\1,68			
+	ii_lset_dx	\1,69			
+	ii_lset_dx	\1,6a			
+	ii_lset_dx	\1,6b			
+	ii_lset_dx	\1,6c			
+	ii_lset_dx	\1,6d			
+	ii_lset_dx	\1,6e			
+	ii_lset_dx	\1,6f			
+// func.w d8(ax,dy),dx
+	ii_lset_dx	\1,70			
+	ii_lset_dx	\1,71			
+	ii_lset_dx	\1,72			
+	ii_lset_dx	\1,73			
+	ii_lset_dx	\1,74			
+	ii_lset_dx	\1,75			
+	ii_lset_dx	\1,76			
+	ii_lset_dx	\1,77			
+// func.w xxx.w,dx
+	ii_lset_dx	\1,78						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
+// func.w xxx.l,dx
+	ii_lset_dx	\1,79						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
+// func.w d16(pc),dx
+	ii_lset_dxg	\1,7a						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
+// func.w d8(pc,dy),dx
+	ii_lset_dxg	\1,7b						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
+// func.w #im,dx
+	ii_lset_dxg	\1,7c						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
+/******************************************************/
+// long
+/******************************************************/
+// func.l ax,dx		-> -(ay),-(ax)
+	ii_lset_dxu	\1,c8			
+	ii_lset_dxu	\1,c9			
+	ii_lset_dxu	\1,ca			
+	ii_lset_dxu	\1,cb			
+	ii_lset_dxu	\1,cc			
+	ii_lset_dxu	\1,cd			
+	ii_lset_dxu	\1,ce			
+	ii_lset_dxu	\1,cf			
+// func.w d8(ax,dy),dx
+	ii_lset_dx	\1,b0			
+	ii_lset_dx	\1,b1			
+	ii_lset_dx	\1,b2			
+	ii_lset_dx	\1,b3			
+	ii_lset_dx	\1,b4			
+	ii_lset_dx	\1,b5			
+	ii_lset_dx	\1,b6			
+	ii_lset_dx	\1,b7			
+// func.l d8(pc,dy),dx
+	ii_lset_dxg	\1,bb						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
+/******************************************************/
+// adress register
+/******************************************************/
+//func.w dy,ax
+	ii_lset_dxg	\1,c0			
+	ii_lset_dxg	\1,c1			
+	ii_lset_dxg	\1,c2			
+	ii_lset_dxg	\1,c3			
+	ii_lset_dxg	\1,c4			
+	ii_lset_dxg	\1,c5			
+	ii_lset_dxg	\1,c6			
+	ii_lset_dxg	\1,c7			
+//func.w ay,ax
+	ii_lset_dxg	\1,c8			
+	ii_lset_dxg	\1,c9			
+	ii_lset_dxg	\1,ca			
+	ii_lset_dxg	\1,cb			
+	ii_lset_dxg	\1,cc			
+	ii_lset_dxg	\1,cd			
+	ii_lset_dxg	\1,ce			
+	ii_lset_dxg	\1,cf			
+//func.w (ay),ax
+	ii_lset_dxg	\1,d0			
+	ii_lset_dxg	\1,d1			
+	ii_lset_dxg	\1,d2			
+	ii_lset_dxg	\1,d3			
+	ii_lset_dxg	\1,d4			
+	ii_lset_dxg	\1,d5			
+	ii_lset_dxg	\1,d6			
+	ii_lset_dxg	\1,d7			
+//func.w (ay)+,ax
+	ii_lset_dxg	\1,d8			
+	ii_lset_dxg	\1,d9			
+	ii_lset_dxg	\1,da			
+	ii_lset_dxg	\1,db			
+	ii_lset_dxg	\1,dc			
+	ii_lset_dxg	\1,dd			
+	ii_lset_dxg	\1,de			
+	ii_lset_dxg	\1,df			
+//func.w -(ay),ax
+	ii_lset_dxg	\1,e0			
+	ii_lset_dxg	\1,e1			
+	ii_lset_dxg	\1,e2			
+	ii_lset_dxg	\1,e3			
+	ii_lset_dxg	\1,e4			
+	ii_lset_dxg	\1,e5			
+	ii_lset_dxg	\1,e6			
+	ii_lset_dxg	\1,e7			
+//func.w d16(ay),ax
+	ii_lset_dxg	\1,e8			
+	ii_lset_dxg	\1,e9			
+	ii_lset_dxg	\1,ea			
+	ii_lset_dxg	\1,eb			
+	ii_lset_dxg	\1,ec			
+	ii_lset_dxg	\1,ed			
+	ii_lset_dxg	\1,ee			
+	ii_lset_dxg	\1,ef			
+//func.w d8(ay,dy),ax
+	ii_lset_dxg	\1,f0			
+	ii_lset_dxg	\1,f1			
+	ii_lset_dxg	\1,f2			
+	ii_lset_dxg	\1,f3			
+	ii_lset_dxg	\1,f4			
+	ii_lset_dxg	\1,f5			
+	ii_lset_dxg	\1,f6			
+	ii_lset_dxg	\1,f7			
+// func.w xxx.w,ax
+	ii_lset_dxg	\1,f8
+// func.w xxx.l,ax
+	ii_lset_dxg	\1,f9
+// func.w d16(pc),ax
+	ii_lset_dxg	\1,fa
+// func.w d8(pc,dy),ax
+	ii_lset_dxg	\1,fb
+// func.w #im,ax
+	ii_lset_dxg	\1,fc
+//--------------------------------------------------------------------
+// ende
+	.endm;	
+/*****************************************************************************************/
+ii_func:.macro
+//--------------------------------------------------------------------
+// byt
+//--------------------------------------------------------------------
+///--------------------------------------------------------------------
+//  func.b	ds,dx
+//--------------------------------------------------------------------
+	funcbeadx	\1,00,\2dd,d0_off+3(a7)		
+	funcbeadx	\1,01,\2dd,d1_off+3(a7)		
+	funcbeadx	\1,02,\2dd,d2		
+	funcbeadx	\1,03,\2dd,d3		
+	funcbeadx	\1,04,\2dd,d4		
+	funcbeadx	\1,05,\2dd,d5		
+	funcbeadx	\1,06,\2dd,d6		
+	funcbeadx	\1,07,\2dd,d7
+//--------------------------------------------------------------------
+//  func.b	(ax),dx
+//--------------------------------------------------------------------
+	funcbeadx	\1,10,\2dda,a0_off(a7)		
+	funcbeadx	\1,11,\2dda,a1_off(a7)		
+	funcbeadx	\1,12,\2dd,(a2)		
+	funcbeadx	\1,13,\2dd,(a3)		
+	funcbeadx	\1,14,\2dd,(a4)		
+	funcbeadx	\1,15,\2dd,(a5)		
+	funcbeadx	\1,16,\2dd,(a6)		
+	funcbeadx	\1,17,\2dda,usp
+//--------------------------------------------------------------------
+//  func.b	(ax)+,dx
+//--------------------------------------------------------------------
+	funcbeadx	\1,18,\2ddai,a0_off(a7)		
+	funcbeadx	\1,19,\2ddai,a1_off(a7)		
+	funcbeadx	\1,1a,\2dd,(a2)+		
+	funcbeadx	\1,1b,\2dd,(a3)+		
+	funcbeadx	\1,1c,\2dd,(a4)+		
+	funcbeadx	\1,1d,\2dd,(a5)+		
+	funcbeadx	\1,1e,\2dd,(a6)+		
+	funcbeadx	\1,1f,\2ddai,usp
+//--------------------------------------------------------------------
+//  func.b	-(ax),dx
+//--------------------------------------------------------------------
+	funcbeadx	\1,20,\2ddad,a0_off(a7)		
+	funcbeadx	\1,21,\2ddad,a1_off(a7)		
+	funcbeadx	\1,22,\2dd,-(a2)		
+	funcbeadx	\1,23,\2dd,-(a3)		
+	funcbeadx	\1,24,\2dd,-(a4)		
+	funcbeadx	\1,25,\2dd,-(a5)		
+	funcbeadx	\1,26,\2dd,-(a6)		
+	funcbeadx	\1,27,\2ddad,usp
+//--------------------------------------------------------------------
+//  func.b	d16(ax),dx
+//--------------------------------------------------------------------
+	funcbeadx	\1,28,\2d16ad,a0_off(a7)		
+	funcbeadx	\1,29,\2d16ad,a1_off(a7)		
+	funcbeadx	\1,2a,\2d16ad,a2		
+	funcbeadx	\1,2b,\2d16ad,a3		
+	funcbeadx	\1,2c,\2d16ad,a4		
+	funcbeadx	\1,2d,\2d16ad,a5		
+	funcbeadx	\1,2e,\2d16ad,a6		
+	funcbeadx	\1,2f,\2d16ad,usp
+//--------------------------------------------------------------------
+//  func.b	d8(ax,dy),dx
+//--------------------------------------------------------------------
+	funcbeadx	\1,30,\2d8ad,a0_off(a7)		
+	funcbeadx	\1,31,\2d8ad,a1_off(a7)		
+	funcbeadx	\1,32,\2d8ad,a2		
+	funcbeadx	\1,33,\2d8ad,a3		
+	funcbeadx	\1,34,\2d8ad,a4		
+	funcbeadx	\1,35,\2d8ad,a5		
+	funcbeadx	\1,36,\2d8ad,a6		
+	funcbeadx	\1,37,\2d8ad,usp
+//--------------------------------------------------------------------
+// func.b xxx.w,dx
+//--------------------------------------------------------------------
+	funcbeadx	\1,38,\2xwd,(a0)+
+//--------------------------------------------------------------------
+// func.b xxx.w,dx
+//--------------------------------------------------------------------
+	funcbeadx	\1,39,\2xld,(a0)+
+//--------------------------------------------------------------------
+// func.b d16(pc),dx
+//--------------------------------------------------------------------
+	funcbeadx	\1,3a,\2d16pcd,(a0)+
+//--------------------------------------------------------------------
+// func.b d8(pc,dy),dx
+//--------------------------------------------------------------------
+	funcbeadx	\1,3b,\2d8pcd,(a0)+	(a0 wird nicht verwendet)
+//--------------------------------------------------------------------
+// func.b	#im,dx
+//--------------------------------------------------------------------
+	funcbeadx	\1,3c,\2bir_macro,(a0)+
+//--------------------------------------------------------------------
+//  func.b	dy,ea
+//--------------------------------------------------------------------
+///--------------------------------------------------------------------
+//  func.b	dx,dd -> addx subx etc. src und dest vertauscht!
+//--------------------------------------------------------------------
+	funcbdxea	\1,00,\2dx,d0_off+3(a7)		
+	funcbdxea	\1,01,\2dx,d1_off+3(a7)		
+	funcbdxea	\1,02,\2dx,d2		
+	funcbdxea	\1,03,\2dx,d3		
+	funcbdxea	\1,04,\2dx,d4		
+	funcbdxea	\1,05,\2dx,d5		
+	funcbdxea	\1,06,\2dx,d6		
+	funcbdxea	\1,07,\2dx,d7
+//--------------------------------------------------------------------
+//  func.b	-(ax),-(ay) addx subx etc. src und dest vertauscht!
+//--------------------------------------------------------------------
+	funcaxay	\1,08,\2dax,a0_off(a7),b		
+	funcaxay	\1,09,\2dax,a1_off(a7).b		
+	funcaxay	\1,0a,\2dax,a2,b		
+	funcaxay	\1,0b,\2dax,a3,b		
+	funcaxay	\1,0c,\2dax,a4,b		
+	funcaxay	\1,0d,\2dax,a5,b		
+	funcaxay	\1,0e,\2dax,a6,b		
+	funcaxay	\1,0f,\2dax,usp,b
+//--------------------------------------------------------------------
+//  func.b	dy,(ax)
+//--------------------------------------------------------------------
+	funcbdxea	\1,10,\2eda,a0_off(a7)		
+	funcbdxea	\1,11,\2eda,a1_off(a7)		
+	funcbdxea	\1,12,\2dd,(a2)		
+	funcbdxea	\1,13,\2dd,(a3)		
+	funcbdxea	\1,14,\2dd,(a4)		
+	funcbdxea	\1,15,\2dd,(a5)		
+	funcbdxea	\1,16,\2dd,(a6)		
+	funcbdxea	\1,17,\2eda,usp
+//--------------------------------------------------------------------
+//  func.b	dy,(ax)+
+//--------------------------------------------------------------------
+	funcbdxea	\1,18,\2edai,a0_off(a7)		
+	funcbdxea	\1,19,\2edai,a1_off(a7)		
+	funcbdxea	\1,1a,\2edaid,(a2)		
+	funcbdxea	\1,1b,\2edaid,(a3)	
+	funcbdxea	\1,1c,\2edaid,(a4)	
+	funcbdxea	\1,1d,\2edaid,(a5)	
+	funcbdxea	\1,1e,\2edaid,(a6)		
+	funcbdxea	\1,1f,\2edai,usp
+//--------------------------------------------------------------------
+//  func.b	dy,-(ax)
+//--------------------------------------------------------------------
+	funcbdxea	\1,20,\2edad,a0_off(a7)		
+	funcbdxea	\1,21,\2edad,a1_off(a7)		
+	funcbdxea	\1,22,\2edadd,(a2)		
+	funcbdxea	\1,23,\2edadd,(a3)		
+	funcbdxea	\1,24,\2edadd,(a4)		
+	funcbdxea	\1,25,\2edadd,(a5)		
+	funcbdxea	\1,26,\2edadd,(a6)		
+	funcbdxea	\1,27,\2edad,usp
+//--------------------------------------------------------------------
+//  func.b	dy,d16(ax)
+//--------------------------------------------------------------------
+	funcbdxea	\1,28,\2e16ad,a0_off(a7)		
+	funcbdxea	\1,29,\2e16ad,a1_off(a7)		
+	funcbdxea	\1,2a,\2e16ad,a2		
+	funcbdxea	\1,2b,\2e16ad,a3		
+	funcbdxea	\1,2c,\2e16ad,a4		
+	funcbdxea	\1,2d,\2e16ad,a5		
+	funcbdxea	\1,2e,\2e16ad,a6		
+	funcbdxea	\1,2f,\2e16ad,usp
+//--------------------------------------------------------------------
+//  func.b	dy,d8(ax,dy)
+//--------------------------------------------------------------------
+	funcbdxea	\1,30,\2e8ad,a0_off(a7)		
+	funcbdxea	\1,31,\2e8ad,a1_off(a7)		
+	funcbdxea	\1,32,\2e8ad,a2		
+	funcbdxea	\1,33,\2e8ad,a3		
+	funcbdxea	\1,34,\2e8ad,a4		
+	funcbdxea	\1,35,\2e8ad,a5		
+	funcbdxea	\1,36,\2e8ad,a6		
+	funcbdxea	\1,37,\2e8ad,usp
+//--------------------------------------------------------------------
+// func.w dy,xxx.w
+//--------------------------------------------------------------------
+	funcwdxea	\1,38,\2xwe,(a0)+
+//--------------------------------------------------------------------
+// func.w dy,xxx.w
+//--------------------------------------------------------------------
+	funcwdxea	\1,39,\2xld,(a0)+
+/*****************************************************************************************/
+// word
+/*****************************************************************************************/
+//  func.w	ds,dx
+//--------------------------------------------------------------------
+	funcweadx	\1,40,\2dd,d0_off+2(a7)		
+	funcweadx	\1,41,\2dd,d1_off+2(a7)		
+	funcweadx	\1,42,\2dd,d2		
+	funcweadx	\1,43,\2dd,d3		
+	funcweadx	\1,44,\2dd,d4		
+	funcweadx	\1,45,\2dd,d5		
+	funcweadx	\1,46,\2dd,d6		
+	funcweadx	\1,47,\2dd,d7
+//--------------------------------------------------------------------
+//  func.w	ax,dx
+//--------------------------------------------------------------------
+	funcweadx	\1,48,\2dd,a0_off+2(a7)		
+	funcweadx	\1,49,\2dd,a1_off+2(a7)		
+	funcweadx	\1,4a,\2dd,a2		
+	funcweadx	\1,4b,\2dd,a3		
+	funcweadx	\1,4c,\2dd,a4		
+	funcweadx	\1,4d,\2dd,a5		
+	funcweadx	\1,4e,\2dd,a6		
+	funcweadx	\1,4f,\2ddd,usp
+//--------------------------------------------------------------------
+//  func.w	(ax),dx
+//--------------------------------------------------------------------
+	funcweadx	\1,50,\2dda,a0_off(a7)		
+	funcweadx	\1,51,\2dda,a1_off(a7)		
+	funcweadx	\1,52,\2dd,(a2)		
+	funcweadx	\1,53,\2dd,(a3)		
+	funcweadx	\1,54,\2dd,(a4)		
+	funcweadx	\1,55,\2dd,(a5)		
+	funcweadx	\1,56,\2dd,(a6)		
+	funcweadx	\1,57,\2dda,usp
+//--------------------------------------------------------------------
+//  func.w	(ax)+,dx
+//--------------------------------------------------------------------
+	funcweadx	\1,58,\2ddai,a0_off(a7)		
+	funcweadx	\1,59,\2ddai,a1_off(a7)		
+	funcweadx	\1,5a,\2dd,(a2)+		
+	funcweadx	\1,5b,\2dd,(a3)+		
+	funcweadx	\1,5c,\2dd,(a4)+		
+	funcweadx	\1,5d,\2dd,(a5)+		
+	funcweadx	\1,5e,\2dd,(a6)+		
+	funcweadx	\1,5f,\2ddai,usp
+//--------------------------------------------------------------------
+//  func.w	-(ax),dx
+//--------------------------------------------------------------------
+	funcweadx	\1,60,\2ddad,a0_off(a7)		
+	funcweadx	\1,61,\2ddad,a1_off(a7)		
+	funcweadx	\1,62,\2dd,-(a2)		
+	funcweadx	\1,63,\2dd,-(a3)		
+	funcweadx	\1,64,\2dd,-(a4)		
+	funcweadx	\1,65,\2dd,-(a5)		
+	funcweadx	\1,66,\2dd,-(a6)		
+	funcweadx	\1,67,\2ddad,usp
+//--------------------------------------------------------------------
+//  func.w	d16(ax),dx
+//--------------------------------------------------------------------
+	funcweadx	\1,68,\2d16ad,a0_off(a7)		
+	funcweadx	\1,69,\2d16ad,a1_off(a7)		
+	funcweadx	\1,6a,\2d16ad,a2		
+	funcweadx	\1,6b,\2d16ad,a3		
+	funcweadx	\1,6c,\2d16ad,a4		
+	funcweadx	\1,6d,\2d16ad,a5		
+	funcweadx	\1,6e,\2d16ad,a6		
+	funcweadx	\1,6f,\2d16ad,usp
+//--------------------------------------------------------------------
+//  func.w	d8(ax,dy),dx
+//--------------------------------------------------------------------
+	funcweadx	\1,70,\2d8ad,a0_off(a7)		
+	funcweadx	\1,71,\2d8ad,a1_off(a7)		
+	funcweadx	\1,72,\2d8ad,a2		
+	funcweadx	\1,73,\2d8ad,a3		
+	funcweadx	\1,74,\2d8ad,a4		
+	funcweadx	\1,75,\2d8ad,a5		
+	funcweadx	\1,76,\2d8ad,a6		
+	funcweadx	\1,77,\2d8ad,usp
+//--------------------------------------------------------------------
+// func.w xxx.w,dx
+//--------------------------------------------------------------------
+	funcweadx	\1,78,\2xwd,(a0)+
+//--------------------------------------------------------------------
+// func.w xxx.w,dx
+//--------------------------------------------------------------------
+	funcweadx	\1,79,\2xld,(a0)+
+//--------------------------------------------------------------------
+// func.w d16(pc),dx
+//--------------------------------------------------------------------
+	funcweadx	\1,7a,\2d16pcd,(a0)+
+//--------------------------------------------------------------------
+// func.w d8(pc,dy),dx
+//--------------------------------------------------------------------
+	funcweadx	\1,7b,\2d8pcd,(a0)+	(a0 wird nicht verwendet)
+//--------------------------------------------------------------------
+// func.w #im,dx
+//--------------------------------------------------------------------
+	funcweadx	\1,7c,\2dd,(a0)+
+//--------------------------------------------------------------------
+//  func.w	dy,ea
+//--------------------------------------------------------------------
+///--------------------------------------------------------------------
+//  func.w	dx,dd -> addx subx etc.
+//--------------------------------------------------------------------
+.ifnc	\2,and			//platz f<>r exg
+	funcwdxea	\1,40,\2dx,d0_off+2(a7)		
+	funcwdxea	\1,41,\2dx,d1_off+2(a7)		
+	funcwdxea	\1,42,\2dx,d2		
+	funcwdxea	\1,43,\2dx,d3		
+	funcwdxea	\1,44,\2dx,d4		
+	funcwdxea	\1,45,\2dx,d5		
+	funcwdxea	\1,46,\2dx,d6		
+	funcwdxea	\1,47,\2dx,d7
+//--------------------------------------------------------------------
+//  func.w	-(ax),-(ay) -> addx,subx
+//--------------------------------------------------------------------
+	funcaxay	\1,48,\2dax,a0_off(a7),w		
+	funcaxay	\1,49,\2dax,a1_off(a7).w		
+	funcaxay	\1,4a,\2dax,a2,w		
+	funcaxay	\1,4b,\2dax,a3,w		
+	funcaxay	\1,4c,\2dax,a4,w		
+	funcaxay	\1,4d,\2dax,a5,w		
+	funcaxay	\1,4e,\2dax,a6,w		
+	funcaxay	\1,4f,\2dax,usp,w
+.endif
+//--------------------------------------------------------------------
+//  func.w	dy,(ax)
+//--------------------------------------------------------------------
+	funcwdxea	\1,50,\2eda,a0_off(a7)		
+	funcwdxea	\1,51,\2eda,a1_off(a7)		
+	funcwdxea	\1,52,\2dd,(a2)		
+	funcwdxea	\1,53,\2dd,(a3)		
+	funcwdxea	\1,54,\2dd,(a4)		
+	funcwdxea	\1,55,\2dd,(a5)		
+	funcwdxea	\1,56,\2dd,(a6)		
+	funcwdxea	\1,57,\2eda,usp
+//--------------------------------------------------------------------
+//  func.w	dy,(ax)+
+//--------------------------------------------------------------------
+	funcwdxea	\1,58,\2edai,a0_off(a7)		
+	funcwdxea	\1,59,\2edai,a1_off(a7)		
+	funcwdxea	\1,5a,\2edaid,(a2)		
+	funcwdxea	\1,5b,\2edaid,(a3)		
+	funcwdxea	\1,5c,\2edaid,(a4)		
+	funcwdxea	\1,5d,\2edaid,(a5)		
+	funcwdxea	\1,5e,\2edaid,(a6)		
+	funcwdxea	\1,5f,\2edai,usp
+//--------------------------------------------------------------------
+//  func.w	dy,-(ax)
+//--------------------------------------------------------------------
+	funcwdxea	\1,60,\2edad,a0_off(a7)		
+	funcwdxea	\1,61,\2edad,a1_off(a7)		
+	funcwdxea	\1,62,\2edadd,(a2)		
+	funcwdxea	\1,63,\2edadd,(a3)		
+	funcwdxea	\1,64,\2edadd,(a4)		
+	funcwdxea	\1,65,\2edadd,(a5)		
+	funcwdxea	\1,66,\2edadd,(a6)		
+	funcwdxea	\1,67,\2edad,usp
+//--------------------------------------------------------------------
+//  func.w	dy,d16(ax)
+//--------------------------------------------------------------------
+	funcwdxea	\1,68,\2e16ad,a0_off(a7)		
+	funcwdxea	\1,69,\2e16ad,a1_off(a7)		
+	funcwdxea	\1,6a,\2e16ad,a2		
+	funcwdxea	\1,6b,\2e16ad,a3		
+	funcwdxea	\1,6c,\2e16ad,a4		
+	funcwdxea	\1,6d,\2e16ad,a5		
+	funcwdxea	\1,6e,\2e16ad,a6		
+	funcwdxea	\1,6f,\2e16ad,usp
+//--------------------------------------------------------------------
+//  func.w	dy,d8(ax,dy)
+//--------------------------------------------------------------------
+	funcwdxea	\1,70,\2e8ad,a0_off(a7)		
+	funcwdxea	\1,71,\2e8ad,a1_off(a7)		
+	funcwdxea	\1,72,\2e8ad,a2		
+	funcwdxea	\1,73,\2e8ad,a3		
+	funcwdxea	\1,74,\2e8ad,a4		
+	funcwdxea	\1,75,\2e8ad,a5		
+	funcwdxea	\1,76,\2e8ad,a6		
+	funcwdxea	\1,77,\2e8ad,usp
+//--------------------------------------------------------------------
+// func.w dy,xxx.w
+//--------------------------------------------------------------------
+	funcwdxea	\1,78,\2xwe,(a0)+
+//--------------------------------------------------------------------
+// func.w dy,xxx.w
+//--------------------------------------------------------------------
+	funcwdxea	\1,79,\2xld,(a0)+
+/*****************************************************************************************/
+// long
+/*****************************************************************************************/
+//--------------------------------------------------------------------
+//  func.l	-(ax),-(ay)
+//--------------------------------------------------------------------
+	funcaxay	\1,c8,\2dax,a0_off(a7),l		
+	funcaxay	\1,c9,\2dax,a1_off(a7).l		
+	funcaxay	\1,ca,\2dax,a2,l		
+	funcaxay	\1,cb,\2dax,a3,l		
+	funcaxay	\1,cc,\2dax,a4,l		
+	funcaxay	\1,cd,\2dax,a5,l		
+	funcaxay	\1,ce,\2dax,a6,l		
+	funcaxay	\1,cf,\2dax,usp,l
+//--------------------------------------------------------------------
+//  func.l	d8(ax,dy),dx
+//--------------------------------------------------------------------
+	funcleadx	\1,b0,\2d8ad,a0_off(a7)		
+	funcleadx	\1,b1,\2d8ad,a1_off(a7)		
+	funcleadx	\1,b2,\2d8ad,a2		
+	funcleadx	\1,b3,\2d8ad,a3		
+	funcleadx	\1,b4,\2d8ad,a4		
+	funcleadx	\1,b5,\2d8ad,a5		
+	funcleadx	\1,b6,\2d8ad,a6		
+	funcleadx	\1,b7,\2d8ad,usp
+//--------------------------------------------------------------------
+// func.l d8(pc,dy),dx
+//--------------------------------------------------------------------
+	funcleadx	\1,bb,\2d8pcd,(a0)+	(a0 wird nicht verwendet)
+//--------------------------------------------------------------------
+//  func.l	dy,d8(ax,dy)
+//--------------------------------------------------------------------
+	funcldxea	\1,b0,\2e8ad,a0_off(a7)		
+	funcldxea	\1,b1,\2e8ad,a1_off(a7)		
+	funcldxea	\1,b2,\2e8ad,a2		
+	funcldxea	\1,b3,\2e8ad,a3		
+	funcldxea	\1,b4,\2e8ad,a4		
+	funcldxea	\1,b5,\2e8ad,a5		
+	funcldxea	\1,b6,\2e8ad,a6		
+	funcldxea	\1,b7,\2e8ad,usp
+/******************************************************/
+// adress register
+/******************************************************/
+//--------------------------------------------------------------------
+// func.w ea,ax
+//--------------------------------------------------------------------
+//--------------------------------------------------------------------
+// func.w	dx,ax
+//--------------------------------------------------------------------
+	funcweaax	\1,c0,\2aw,d0		
+	funcweaax	\1,c1,\2aw,d1		
+	funcweaax	\1,c2,\2aw,d2		
+	funcweaax	\1,c3,\2aw,d3		
+	funcweaax	\1,c4,\2aw,d4		
+	funcweaax	\1,c5,\2aw,d5		
+	funcweaax	\1,c6,\2aw,d6		
+	funcweaax	\1,c7,\2aw,d7		
+//--------------------------------------------------------------------
+// func.w	ay,ax
+//--------------------------------------------------------------------
+	funcweaax	\1,c8,\2aw,a0		
+	funcweaax	\1,c9,\2aw,a1		
+	funcweaax	\1,ca,\2aw,a2		
+	funcweaax	\1,cb,\2aw,a3		
+	funcweaax	\1,cc,\2aw,a4		
+	funcweaax	\1,cd,\2aw,a5		
+	funcweaax	\1,ce,\2aw,a6		
+	funcweaax	\1,cf,\2awu,a7	
+//--------------------------------------------------------------------
+// func.w	(ay),ax
+//--------------------------------------------------------------------
+	funcweaax	\1,d0,\2aw,(a0)		
+	funcweaax	\1,d1,\2aw,(a1)	
+	funcweaax	\1,d2,\2aw,(a2)		
+	funcweaax	\1,d3,\2aw,(a3)		
+	funcweaax	\1,d4,\2aw,(a4)		
+	funcweaax	\1,d5,\2aw,(a5)		
+	funcweaax	\1,d6,\2aw,(a6)		
+	funcweaax	\1,d7,\2awu,(a7)	
+//--------------------------------------------------------------------
+// func.w	(ay)+,ax
+//--------------------------------------------------------------------
+	funcweaax	\1,d8,\2aw,(a0)+		
+	funcweaax	\1,d9,\2aw,(a1)+
+	funcweaax	\1,da,\2aw,(a2)+	
+	funcweaax	\1,db,\2aw,(a3)+		
+	funcweaax	\1,dc,\2aw,(a4)+	
+	funcweaax	\1,dd,\2aw,(a5)+	
+	funcweaax	\1,de,\2aw,(a6)+	
+	funcweaax	\1,df,\2awu,(a7)+	
+//--------------------------------------------------------------------
+// func.w	-(ay),ax
+//--------------------------------------------------------------------
+	funcweaax	\1,e0,\2aw,-(a0)		
+	funcweaax	\1,e1,\2aw,-(a1)
+	funcweaax	\1,e2,\2aw,-(a2)	
+	funcweaax	\1,e3,\2aw,-(a3)		
+	funcweaax	\1,e4,\2aw,-(a4)	
+	funcweaax	\1,e5,\2aw,-(a5)	
+	funcweaax	\1,e6,\2aw,-(a6)	
+	funcweaax	\1,e7,\2awu,-(a7)	
+//--------------------------------------------------------------------
+// func.w	d16(ay),ax
+//--------------------------------------------------------------------
+	funcweaaxn	\1,e8,\2awd16a,a0_off(a7)		
+	funcweaaxn	\1,e9,\2awd16a,a1_off(a7)
+	funcweaaxn	\1,ea,\2awd16a,a2	
+	funcweaaxn	\1,eb,\2awd16a,a3		
+	funcweaaxn	\1,ec,\2awd16a,a4	
+	funcweaaxn	\1,ed,\2awd16a,a5	
+	funcweaaxn	\1,ee,\2awd16a,a6	
+	funcweaaxn	\1,ef,\2awd16a,usp	
+//--------------------------------------------------------------------
+// func.w	d8(ay,dy),ax
+//--------------------------------------------------------------------
+	funcweaaxn	\1,f0,\2awd8a,a0_off(a7)		
+	funcweaaxn	\1,f1,\2awd8a,a1_off(a7)
+	funcweaaxn	\1,f2,\2awd8a,a2	
+	funcweaaxn	\1,f3,\2awd8a,a3		
+	funcweaaxn	\1,f4,\2awd8a,a4	
+	funcweaaxn	\1,f5,\2awd8a,a5	
+	funcweaaxn	\1,f6,\2awd8a,a6	
+	funcweaaxn	\1,f7,\2awd8a,usp	
+//--------------------------------------------------------------------
+// func.w xxx.w,ax
+//--------------------------------------------------------------------
+	funcweaaxn	\1,f8,\2awxwax,(a0)+
+//--------------------------------------------------------------------
+// func.w xxxlw,ax
+//--------------------------------------------------------------------
+	funcweaaxn	\1,f9,\2awxlax,(a0)+
+//--------------------------------------------------------------------
+// func.w d16(pc),ax
+//--------------------------------------------------------------------
+	funcweaaxn	\1,fa,\2awd16pcax,(a0)+
+//--------------------------------------------------------------------
+// func.w d8(pc,dy),ax
+//--------------------------------------------------------------------
+	funcweaaxn	\1,fb,\2awd8pcax,(a0)+	//(a0 wird nicht verwendet)
+//--------------------------------------------------------------------
+// func.w #im,ax
+//--------------------------------------------------------------------
+	funcweaaxn	\1,fc,\2awim,(a0)+	
+//--------------------------------------------------------------------
+// ende
+	.endm;	
+//--------------------------------------------------------------------
+// byt
+funcbeadx:.macro					// function byt: im,dx 
+ii_0x\10\2:			 
+	\3		\4,d0_off+3(a7),b
+ii_0x\12\2:				 
+	\3		\4,d1_off+3(a7),b
+ii_0x\14\2:			 
+	\3		\4,d2,b
+ii_0x\16\2:			 
+	\3		\4,d3,b 
+ii_0x\18\2:			 
+	\3		\4,d4,b 
+ii_0x\1a\2:				 
+	\3		\4,d5,b
+ii_0x\1c\2:			 
+	\3		\4,d6,b
+ii_0x\1e\2:			 
+	\3		\4,d7,b
+	.endm;
+funcbdxea:.macro	// ea(\4) function(\3) dx -> ea
+ii_0x\11\2:
+	\3	d0_off+3(a7),\4,b
+ii_0x\13\2:
+	\3	d1_off+3(a7),\4,b
+ii_0x\15\2:
+	\3	d2,\4,b
+ii_0x\17\2:
+	\3	d3,\4,b
+ii_0x\19\2:
+	\3	d4,\4,b
+ii_0x\1b\2:
+	\3	d5,\4,b
+ii_0x\1d\2:
+	\3	d6,\4,b
+ii_0x\1f\2:
+	\3	d7,\4,b
+	.endm;
+//--------------------------------------------------------------------
+// word
+funcweadx:.macro	// dx function(\3) ea(\4) -> dx 
+ii_0x\10\2:
+	\3	\4,d0_off+2(a7),w
+ii_0x\12\2:
+	\3	\4,d1_off+2(a7),w
+ii_0x\14\2:
+	\3	\4,d2,w
+ii_0x\16\2:
+	\3	\4,d3,w
+ii_0x\18\2:
+	\3	\4,d4,w
+ii_0x\1a\2:
+	\3	\4,d5,w
+ii_0x\1c\2:
+	\3	\4,d6,w
+ii_0x\1e\2:
+	\3	\4,d7,w
+	.endm;
+funcwdxea:.macro	// ea(\4) function(\3) dx -> ea 
+ii_0x\11\2:
+	\3	d0_off+2(a7),\4,w
+ii_0x\13\2:
+	\3	d1_off+2(a7),\4,w
+ii_0x\15\2:
+	\3	d2,\4,w
+ii_0x\17\2:
+	\3	d3,\4,w
+ii_0x\19\2:
+	\3	d4,\4,w
+ii_0x\1b\2:
+	\3	d5,\4,w
+ii_0x\1d\2:
+	\3	d6,\4,w
+ii_0x\1f\2:
+	\3	d7,\4,w
+	.endm;
+//--------------------------------------------------------------------
+// long
+funcleadx:.macro	// dx function(\3) ea(\4) -> dx 
+ii_0x\10\2:
+	\3	\4,d0_off(a7),w
+ii_0x\12\2:
+	\3	\4,d1_off(a7),w
+ii_0x\14\2:
+	\3	\4,d2,w
+ii_0x\16\2:
+	\3	\4,d3,w
+ii_0x\18\2:
+	\3	\4,d4,w
+ii_0x\1a\2:
+	\3	\4,d5,w
+ii_0x\1c\2:
+	\3	\4,d6,w
+ii_0x\1e\2:
+	\3	\4,d7,w
+	.endm;
+funcldxea:.macro	// ea(\4) function(\3) dx -> ea 
+ii_0x\11\2:
+	\3	d0_off(a7),\4,w
+ii_0x\13\2:
+	\3	d1_off(a7),\4,w
+ii_0x\15\2:
+	\3	d2,\4,w
+ii_0x\17\2:
+	\3	d3,\4,w
+ii_0x\19\2:
+	\3	d4,\4,w
+ii_0x\1b\2:
+	\3	d5,\4,w
+ii_0x\1d\2:
+	\3	d6,\4,w
+ii_0x\1f\2:
+	\3	d7,\4,w
+	.endm;
+//--------------------------------------------------------------
+// address
+funcweaax:.macro	// ax function(\3) ea(\4)(ext long!) -> ax 
+ii_0x\10\2:
+	\3	\4,a0
+ii_0x\12\2:
+	\3	\4,a1
+ii_0x\14\2:
+	\3	\4,a2 
+ii_0x\16\2:
+	\3	\4,a3 
+ii_0x\18\2:
+	\3	\4,a4 
+ii_0x\1a\2:
+	\3	\4,a5 
+ii_0x\1c\2:
+	\3	\4,a6 
+ii_0x\1e\2:
+	\3a7 \4,a7 		// "a7" beachten wegen usp
+	.endm;
+funcweaaxn:.macro	// ax function(\3) ea(\4)(ext long!) -> ax 
+ii_0x\10\2:
+	\3	\4,a0_off(a7) 
+ii_0x\12\2:
+	\3	\4,a1_off(a7) 
+ii_0x\14\2:
+	\3	\4,a2 
+ii_0x\16\2:
+	\3	\4,a3 
+ii_0x\18\2:
+	\3	\4,a4 
+ii_0x\1a\2:
+	\3	\4,a5 
+ii_0x\1c\2:
+	\3	\4,a6 
+ii_0x\1e\2:
+	\3	\4,usp 
+	.endm;
+//--------------------------------------------------------------
+// byt, word, long
+//--------------------------------------------------------------
+funcaxay:.macro	// ea(\4) function(\3) dx -> ea,\5 = size
+ii_0x\11\2:
+	\3	a0_off(a7),\4,\5
+ii_0x\13\2:
+	\3	a1_off(a7),\4,\5
+ii_0x\15\2:
+	\3	a2,\4,\5
+ii_0x\17\2:
+	\3	a3,\4,\5
+ii_0x\19\2:
+	\3	a4,\4,\5
+ii_0x\1b\2:
+	\3	a5,\4,\5
+ii_0x\1d\2:
+	\3	a6,\4,\5
+ii_0x\1f\2:
+	\3	usp,\4,\5
+	.endm;

BaS_codewarrior/firebeeV1/sources/ii_jmp.h

@@ -0,0 +1,59 @@
+//--------------------------------------------------------------------
+// extension word format missing
+//--------------------------------------------------------------------
+ii_\1_func:.macro
+ii_0x\20:
+#ifdef	halten_\1
+	halt
+#endif
+	move.l	a0_off(a7),a1
+	\1_macro
+ii_0x\21:
+#ifdef	halten_\1
+	halt
+#endif
+	move.l	a1_off(a7),a1
+	\1_macro
+ii_0x\22:
+#ifdef	halten_\1
+	halt
+#endif
+	move.l	a2,a1
+	\1_macro
+ii_0x\23:
+#ifdef	halten_\1
+	halt
+#endif
+	move.l	a3,a1
+	\1_macro
+ii_0x\24:
+#ifdef	halten_\1
+	halt
+#endif
+	move.l	a4,a1
+	\1_macro
+ii_0x\25:
+#ifdef	halten_\1
+	halt
+#endif
+	move.l	a5,a1
+	\1_macro
+ii_0x\26:
+#ifdef	halten_\1
+	halt
+#endif
+	move.l	a6,a1
+	\1_macro
+ii_0x\27:
+#ifdef	halten_\1
+	halt
+#endif
+	move.l	usp,a1
+	\1_macro
+ii_0x\2b:
+#ifdef	halten_\1
+	halt
+#endif
+	move.l	a0,a1
+	\1_macro
+.endm		

BaS_codewarrior/firebeeV1/sources/ii_lea.h

@@ -0,0 +1,105 @@
+//-------------------------------------------------------------------
+// lea
+//-------------------------------------------------------------------
+.text
+ii_lea_lset:.macro
+	ii_lset_dxu 4,f0			// lea d8(a0,dy.w),a0-a7
+	ii_lset_dxu 4,f1			// lea d8(a1,dy.w),a0-a7
+	ii_lset_dxu 4,f2			// lea d8(a2,dy.w),a0-a7
+	ii_lset_dxu 4,f3			// lea d8(a3,dy.w),a0-a7
+	ii_lset_dxu 4,f4			// lea d8(a4,dy.w),a0-a7
+	ii_lset_dxu 4,f5			// lea d8(a5,dy.w),a0-a7
+	ii_lset_dxu 4,f6			// lea d8(a6,dy.w),a0-a7
+	ii_lset_dxu 4,f7			// lea d8(a7,dy.w),a0-a7
+	ii_lset_dxu 4,fb			// lea d8(pc,dy.w),a0-a7
+.endm
+
+//---------------------------------------------------------------------------------------------
+// function
+//---------------------------------------------------------------------------------------------
+ii_lea_sub:.macro
+ii_0x4\1\2:
+#ifdef	halten_lea
+	halt
+#endif
+	move.l	\4,a1
+	jsr		ewf
+	move.l	a1,\3
+	ii_end
+.endm
+ii_lea_func:.macro
+//lea d8(ax,dy.w),a0-a7
+	ii_lea_sub	1,f0,a0_off(a7),a0_off(a7)
+	ii_lea_sub	1,f1,a0_off(a7),a1_off(a7)
+	ii_lea_sub	1,f2,a0_off(a7),a2
+	ii_lea_sub	1,f3,a0_off(a7),a3
+	ii_lea_sub	1,f4,a0_off(a7),a4
+	ii_lea_sub	1,f5,a0_off(a7),a5
+	ii_lea_sub	1,f6,a0_off(a7),a6
+	ii_lea_sub	1,f7,a0_off(a7),usp
+	ii_lea_sub	3,f0,a1_off(a7),a0_off(a7)
+	ii_lea_sub	3,f1,a1_off(a7),a1_off(a7)
+	ii_lea_sub	3,f2,a1_off(a7),a2
+	ii_lea_sub	3,f3,a1_off(a7),a3
+	ii_lea_sub	3,f4,a1_off(a7),a4
+	ii_lea_sub	3,f5,a1_off(a7),a5
+	ii_lea_sub	3,f6,a1_off(a7),a6
+	ii_lea_sub	3,f7,a1_off(a7),usp
+	ii_lea_sub	5,f0,a2,a0_off(a7)
+	ii_lea_sub	5,f1,a2,a1_off(a7)
+	ii_lea_sub	5,f2,a2,a2
+	ii_lea_sub	5,f3,a2,a3
+	ii_lea_sub	5,f4,a2,a4
+	ii_lea_sub	5,f5,a2,a5
+	ii_lea_sub	5,f6,a2,a6
+	ii_lea_sub	5,f7,a2,usp
+	ii_lea_sub	7,f0,a3,a0_off(a7)
+	ii_lea_sub	7,f1,a3,a1_off(a7)
+	ii_lea_sub	7,f2,a3,a2
+	ii_lea_sub	7,f3,a3,a3
+	ii_lea_sub	7,f4,a3,a4
+	ii_lea_sub	7,f5,a3,a5
+	ii_lea_sub	7,f6,a3,a6
+	ii_lea_sub	7,f7,a3,usp
+	ii_lea_sub	9,f0,a4,a0_off(a7)
+	ii_lea_sub	9,f1,a4,a1_off(a7)
+	ii_lea_sub	9,f2,a4,a2
+	ii_lea_sub	9,f3,a4,a3
+	ii_lea_sub	9,f4,a4,a4
+	ii_lea_sub	9,f5,a4,a5
+	ii_lea_sub	9,f6,a4,a6
+	ii_lea_sub	9,f7,a4,usp
+	ii_lea_sub	b,f0,a5,a0_off(a7)
+	ii_lea_sub	b,f1,a5,a1_off(a7)
+	ii_lea_sub	b,f2,a5,a2
+	ii_lea_sub	b,f3,a5,a3
+	ii_lea_sub	b,f4,a5,a4
+	ii_lea_sub	b,f5,a5,a5
+	ii_lea_sub	b,f6,a5,a6
+	ii_lea_sub	b,f7,a6,usp
+	ii_lea_sub	d,f0,a6,a0_off(a7)
+	ii_lea_sub	d,f1,a6,a1_off(a7)
+	ii_lea_sub	d,f2,a6,a2
+	ii_lea_sub	d,f3,a6,a3
+	ii_lea_sub	d,f4,a6,a4
+	ii_lea_sub	d,f5,a6,a5
+	ii_lea_sub	d,f6,a6,a6
+	ii_lea_sub	d,f7,a6,usp
+	ii_lea_sub	f,f0,usp,a0_off(a7)
+	ii_lea_sub	f,f1,usp,a1_off(a7)
+	ii_lea_sub	f,f2,usp,a2
+	ii_lea_sub	f,f3,usp,a3
+	ii_lea_sub	f,f4,usp,a4
+	ii_lea_sub	f,f5,usp,a5
+	ii_lea_sub	f,f6,usp,a6
+	ii_lea_sub	f,f7,usp,usp
+// lea d8(pc,dy.w),az
+	ii_lea_sub	1,fb,a0_off(a7),a0
+	ii_lea_sub	3,fb,a1_off(a7),a0
+	ii_lea_sub	5,fb,a2,a0
+	ii_lea_sub	7,fb,a3,a0
+	ii_lea_sub	9,fb,a4,a0
+	ii_lea_sub	b,fb,a5,a0
+	ii_lea_sub	d,fb,a6,a0
+	ii_lea_sub	f,fb,usp,a0
+.endm

BaS_codewarrior/firebeeV1/sources/ii_macro.h

@@ -0,0 +1,144 @@
+/*******************************************************/
+// constanten
+/*******************************************************/
+.extern ___RAMBAR1
+.extern _rt_cacr
+.extern _rt_mod
+.extern _rt_ssp
+.extern _rt_usp
+.extern _rt_vbr
+.extern _d0_save
+.extern _a7_save
+
+ii_ss	=		16
+d0_off	=		0
+d1_off	=		4
+a0_off	=		8
+a1_off	=		12
+format_off =	16
+sr_off	=		18
+ccr_off =		19
+pc_off	=		20
+
+#define 	table 	0x20000000-0x8000-0xF000*4 // Adresse Sprungtabelle 	-> 8000=Sprungbereich mod cod, 61k(ohne 0xFxxx!)x4= tabelle
+
+/*******************************************************/
+// allgemeine macros
+/*******************************************************/
+ii_end:	.macro
+		move.l a0,pc_off(a7)
+		movem.l (a7),d0/d1/a0/a1
+		lea ii_ss(a7),a7
+		rte
+		.endm;
+
+set_cc0:.macro
+		move.w	ccr,d0 
+		move.b	d0,ccr_off(a7)
+		.endm;
+
+ii_esr:	.macro					// geht nicht!!??
+		movem.l		(a7),d0/d1/a0/a1
+		lea			ii_ss+8(a7),a7		// stack erh<72>hen
+		move.w		d0,_d0_save			// d0.w sicheren
+		move.w		-6(a7),d0			// sr holen
+		move.w		d0,sr				// sr setzen
+		nop
+		move.w		_d0_save,d0			// d0.w zur<75>ck
+		.endm;
+
+ii_end_mvm:.macro
+		move.l	a0_off(a7),a0
+		lea		16(a7),a7
+		rte
+		.endm;
+
+ii_endj:.macro
+		movem.l	(a7),d0/d1/a0/a1		// register zur<75>ck
+		lea		ii_ss(a7),a7			// korr
+		rte								// ende
+		.endm;
+		
+set_nzvc:.macro							// set ccr bits nzvc
+		move.w	ccr,d1
+		bclr	#4,d1
+		btst	#4,ccr_off(a7)
+		beq		snzvc2\@
+		bset	#4,d1
+snzvc2\@:
+		move.b	d1,ccr_off(a7)
+		.endm;
+		
+set_cc1:.macro
+		move.w	ccr,d1
+		move.b	d1,ccr_off(a7)
+		.endm;
+
+set_cc_b:.macro
+		move.w	ccr,d1
+		btst	#7,d0					// byt negativ?
+		beq		set_cc_b2\@
+		bset	#3,d1					// make negativ
+set_cc_b2\@:
+		move.b	d1,ccr_off(a7)
+		.endm;
+		
+set_cc_w:.macro
+		move.w	ccr,d1
+		btst	#15,d0					// byt negativ?
+		beq		set_cc_w2\@
+		bset	#3,d1					// make negativ
+set_cc_w2\@:
+		move.b	d1,ccr_off(a7)
+		.endm;
+		
+get_pc:	.macro
+		lea.l		(a0),a1
+		.endm;
+
+//--------------------------------------------------------------------
+ii_lset:.macro
+		lea	table+\1*4,a0
+		move.l #ii_\1,(a0)
+		.endm;
+ii_lset_dx:.macro				// 0x1.22 -> z.B. 1=d,2=4 ->0xd040 -> 0xde40
+		ii_lset_dxg	\1,\2
+		ii_lset_dxu	\1,\2
+		.endm;
+ii_lset_dxg:.macro				// gerade: 0x1.22 -> z.B. 1=d,2=4 ->0xd040 -> 0xde40
+		lea 	table+0x\10\2*4,a0
+		move.l	#ii_0x\10\2,(a0)
+		lea		0x800(a0),a0	// 4 * 0x200
+		move.l	#ii_0x\12\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\14\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\16\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\18\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\1a\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\1c\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\1e\2,(a0)
+		.endm;
+ii_lset_dxu:.macro				// ungerade: 0x1.22 -> z.B. 1=d,2=4 ->0xd140 -> 0xdf40
+		lea	table+0x\11\2*4,a0
+		move.l	#ii_0x\11\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\13\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\15\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\17\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\19\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\1b\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\1d\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\1f\2,(a0)
+		.endm;
+

BaS_codewarrior/firebeeV1/sources/ii_movem.h

@@ -0,0 +1,374 @@
+//***********************************************************************************/
+// movem
+//***********************************************************************************/
+ii_movem_lset: .macro
+// movem.l rx,xxx.L
+	ii_lset		0x48f9
+// movem.l xxx.L,rx
+	ii_lset		0x4cf9
+// movem.w rx,xxx.L
+	ii_lset		0x48b9
+// movem.w xxx.L,rx
+	ii_lset		0x4cb9
+// movem.l rx,-(ax)
+	ii_lset		0x48e0
+	ii_lset		0x48e1
+	ii_lset		0x48e2
+	ii_lset		0x48e3
+	ii_lset		0x48e4
+	ii_lset		0x48e5
+	ii_lset		0x48e6
+	ii_lset		0x48e7
+// movem.l (ax)+,rx
+	ii_lset		0x4cd8
+	ii_lset		0x4cd9
+	ii_lset		0x4cda
+	ii_lset		0x4cdb
+	ii_lset		0x4cdc
+	ii_lset		0x4cdd
+	ii_lset		0x4cde
+	ii_lset		0x4cdf
+.endm
+//***********************************************************************************/
+ii_movem_func: .macro
+//-------------------------------------------------------------------
+// movem.l
+//--------------------------------------------------------------------
+// movem.l (ax)+,reg
+//--------------------------------------------------------------------
+	.long		0
+az_reg_table:
+	.byte		0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4		// 0-f
+	.byte		1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5		// 10-1f
+	.byte		1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5		// 20-2f
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// 30-3f
+	.byte		1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5		// 40-4f
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// 50
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// 60
+	.byte		3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7		// 70
+	.byte		1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5		// 80-8f
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// 90
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// a0
+	.byte		3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7		// b0
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// c0
+	.byte		3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7		// d0
+	.byte		3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7		// e0
+	.byte		4,5,5,6,5,6,6,7,5,6,6,7,6,7,7,8		// f0
+//-------------------------------------------------------------------------------
+ii_0x48e0:		// movem.l reglist,-(a0)
+	mvm_mem_macro	0x48d0,a0_off(a7),2
+ii_0x48e1:		// movem.l reglist,-(a1)
+	mvm_mem_macro	0x48d1,a1_off(a7),2
+ii_0x48e2:		// movem.l reglist,-(a2)
+	mvm_mem_macro	0x48d2,a2,2
+ii_0x48e3:		// movem.l reglist,-(a3)
+	mvm_mem_macro	0x48d3,a3,2
+ii_0x48e4:		// movem.l reglist,-(a4)
+	mvm_mem_macro	0x48d4,a4,2
+ii_0x48e5:		// movem.l reglist,-(a5)
+	mvm_mem_macro	0x48d5,a5,2
+ii_0x48e6:		// movem.l reglist,-(a6)
+	mvm_mem_macro	0x48d6,a6,2
+ii_0x48e7:		// movem.l reglist,-(a7)
+	mvm_mem_macro	0x48d7,usp,2
+//-------------------------------------------------------------------------------
+ii_0x4cd8:		// movem.l (a0)+,reglist
+	mvm_reg_macro	0x4cd0,0x41e8,2
+ii_0x4cd9:		// movem.l (a1)+,reglist
+	mvm_reg_macro	0x4cd1,0x43e9,2
+ii_0x4cda:		// movem.l (a2)+,reglist
+	mvm_reg_macro	0x4cd2,0x45ea,2
+ii_0x4cdb:		// movem.l (a3)+,reglist
+	mvm_reg_macro	0x4cd3,0x47eb,2
+ii_0x4cdc:		// movem.l (a4)+,reglist
+	mvm_reg_macro	0x4cd4,0x49ec,2
+ii_0x4cdd:		// movem.l (a5)+,reglist
+	mvm_reg_macro	0x4cd5,0x4bed,2
+ii_0x4cde:		// movem.l (a6)+,reglist
+	mvm_reg_macro	0x4cd6,0x4dee,2
+ii_0x4cdf:		// movem.l (a7)+,reglist
+	mvm_reg_macro	0x4cd7,0x4fef,2
+//----------------------------------------------------------------------------
+ii_0x48f9:		// movem.l reg,xxx.L
+#ifdef	halten_movem
+	halt
+#endif
+		move.w		(a0)+,d0
+		move.l		(a0)+,a1
+		movemrm_macro	l
+//---------------------------------------------------------------------------------------------
+ii_0x4cf9:		// movem.l xxx.L,reg
+#ifdef	halten_movem
+	halt
+#endif
+		move.w		(a0)+,d0
+		move.l		(a0)+,a1
+		movemmr_macro	l
+//----------------------------------------------------------------------------
+ii_0x48b9:		// movem.w reg,xxx.L
+#ifdef	halten_movem
+	halt
+#endif
+		move.w		(a0)+,d0
+		move.l		(a0)+,a1
+		movemrm_macro	w
+//---------------------------------------------------------------------------------------------
+ii_0x4cb9:		// movem.w xxx.L,reg
+#ifdef	halten_movem
+	halt
+#endif
+		move.w		(a0)+,d0
+		move.l		(a0)+,a1
+		movemmr_macro	w
+.endm
+//==============================================================
+mvm_mem_macro:.macro
+#ifdef	halten_movem
+	halt
+#endif
+	lea			az_reg_table,a1
+	mvz.b		(a0),d1
+	mvz.b		0(a1,d1)+,d0
+	mvz.b		1(a0),d1
+	mvz.b		0(a1,d1)+,d1
+	add.l		d0,d1
+	lsl.l		#\3,d1				// * anzahl byts pro wert
+	move.l		\2,a1
+	sub.l		d1,a1				// ax-anzahl byts
+	move.l		a1,\2
+	lea			___RAMBAR1,a1
+	move.l		a1,pc_off(a7)
+	move.l		a1,d0
+	addq.l		#1,d0
+   	movec      	d0,RAMBAR1
+	move.w		#\1,(a1)+			// movem.x reg_list,-(a7)
+	move.w		(a0)+,(a1)+			// register list
+	move.w		#0x4ef9,(a1)+		// jmp.l
+	move.l		a0,(a1)				// r<>cksprungadresse
+   	move.l 		#___RAMBAR1 + 0x81,d0	// instruction
+   	movec      	d0,RAMBAR1
+	movem.l		(a7),d0/d1/a0/a1
+	lea			ii_ss(a7),a7		// stack erh<72>hen
+	rte
+.endm
+//---------------------------------------------------------------------------------
+mvm_reg_macro:.macro
+#ifdef	halten_movem
+	halt
+#endif
+	lea			az_reg_table,a1
+	mvz.b		(a0),d1
+	mvz.b		0(a1,d1)+,d0
+	mvz.b		1(a0),d1
+	mvz.b		0(a1,d1)+,d1
+	add.l		d0,d1
+	lea			___RAMBAR1,a1
+	move.l		a1,pc_off(a7)
+	move.l		a1,d0
+	addq.l		#1,d0
+   	movec      	d0,RAMBAR1
+	move.w		#\1,(a1)+			// movem.x (ax),reg_list
+	move.w		(a0)+,(a1)+			// register list
+	move.w		#\2,(a1)+			// lea 0(ax),ax
+	lsl.l		#\3,d1				// * anzahl byts pro wert
+	move.w		d1,(a1)+			// offset von lea
+	move.w		#0x4ef9,(a1)+		// jmp.l
+	move.l		a0,(a1)				// r<>cksprungadresse
+   	move.l 		#___RAMBAR1 + 0x81,d0	// instruction
+   	movec      	d0,RAMBAR1
+	movem.l		(a7),d0/d1/a0/a1
+	lea			ii_ss(a7),a7		// stack erh<72>hen
+	rte
+.endm
+//---------------------------------------------------------------------------------
+movemrm_macro:.macro				// in d0 register liste, in a1 zieladresse
+#ifdef	halten_movem
+	halt
+#endif
+		tst.b	d0					// datenregister zu verschieben?
+		bne		mrm_dx\@				// ja->
+		lsr.l	#8,d0				// sonst zu addressregister
+		jmp		mmrm_nd7\@			// ->
+mrm_dx\@:
+		lsr.l	#1,d0
+		bcc		mmrm_nd0\@
+.ifc	1,l
+		move.l	d0_off(a7),(a1)+
+.else
+		move.w	d0_off+2(a7),(a1)+
+.endif
+mmrm_nd0\@:
+		lsr.l	#1,d0
+		bcc		mmrm_nd1\@
+.ifc	1,l
+		move.l	d1_off(a7),(a1)+
+.else
+		move.w	d1_off+2(a7),(a1)+
+.endif
+mmrm_nd1\@:
+		lsr.l	#1,d0
+		bcc		mmrm_nd2\@
+		move.\1	d2,(a1)+
+mmrm_nd2\@:
+		lsr.l	#1,d0
+		bcc		mmrm_nd3\@
+		move.\1	d3,(a1)+
+mmrm_nd3\@:
+		lsr.l	#1,d0
+		bcc		mmrm_nd4\@
+		move.\1	d4,(a1)+
+mmrm_nd4\@:
+		lsr.l	#1,d0
+		bcc		mmrm_nd5\@
+		move.\1	d5,(a1)+
+mmrm_nd5\@:
+		lsr.l	#1,d0
+		bcc		mmrm_nd6\@
+		move.l	d6,(a1)+
+mmrm_nd6\@:
+		lsr.l	#1,d0
+		bcc		mmrm_nd7\@
+		move.\1	d7,(a1)+
+mmrm_nd7\@:
+		tst.b	d0					// addressregister zu verschieben?
+		beq		mmrm_na7\@
+		lsr.l	#1,d0
+		bcc		mmrm_na0\@
+.ifc	1,l
+		move.l	a0_off(a7),(a1)+
+.else
+		move.w	a0_off+2(a7),(a1)+
+.endif
+mmrm_na0\@:
+		lsr.l	#1,d0
+		bcc		mmrm_na1\@
+.ifc	1,l
+		move.l	a1_off(a7),(a1)+
+.else
+		move.w	a1_off+2(a7),(a1)+
+.endif
+mmrm_na1\@:
+		lsr.l	#1,d0
+		bcc		mmrm_na2\@
+		move.\1	a2,(a1)+
+mmrm_na2\@:
+		lsr.l	#1,d0
+		bcc		mmrm_na3\@
+		move.\1	a3,(a1)+
+mmrm_na3\@:
+		lsr.l	#1,d0
+		bcc		mmrm_na4\@
+		move.\1	a4,(a1)+
+mmrm_na4\@:
+		lsr.l	#1,d0
+		bcc		mmrm_na5\@
+		move.\1	a5,(a1)+
+mmrm_na5\@:
+		lsr.l	#1,d0
+		bcc		mmrm_na6\@
+		move.\1	a6,(a1)+
+mmrm_na6\@:
+		lsr.l	#1,d0
+		bcc		mmrm_na7\@
+		move.l	a0,d1		// sichern
+		move.l	usp,a0		// ist ja usp
+		move.\1	a0,(a1)+	// nach a0
+		move.l	d1,a0		// pc zur<75>ck
+mmrm_na7\@:
+		ii_end
+		.endm
+//---------------------------------------------------------------------------------------------
+movemmr_macro:.macro				// in d0 register liste, in a1 source adr
+#ifdef	halten_movem
+	halt
+#endif
+		tst.b	d0					// datenregister zu verschieben?
+		bne		mmr_dx\@				// ja->
+		lsr.l	#8,d0				// sonst zu addressregister
+		bra		mmmr_nd7\@			// ->
+mmr_dx\@:
+		lsr.l	#1,d0
+		bcc		mmmr_nd0\@
+.ifc	1,l
+		move.l	(a1)+,d0_off(a7)
+.else
+		move.w	(a1)+,d0_off+2(a7)
+.endif
+mmmr_nd0\@:
+		lsr.l	#1,d0
+		bcc		mmmr_nd1\@
+.ifc	1,l
+		move.l	(a1)+,d1_off(a7)
+.else
+		move.w	(a1)+,d1_off+2(a7)
+.endif
+mmmr_nd1\@:
+		lsr.l	#1,d0
+		bcc		mmmr_nd2\@
+		move.\1	(a1)+,d2
+mmmr_nd2\@:
+		lsr.l	#1,d0
+		bcc		mmmr_nd3\@
+		move.\1	(a1)+,d3
+mmmr_nd3\@:
+		lsr.l	#1,d0
+		bcc		mmmr_nd4\@
+		move.\1	(a1)+,d4
+mmmr_nd4\@:
+		lsr.l	#1,d0
+		bcc		mmmr_nd5\@
+		move.\1	(a1)+,d5
+mmmr_nd5\@:
+		lsr.l	#1,d0
+		bcc		mmmr_nd6\@
+		move.\1	(a1)+,d6
+mmmr_nd6\@:
+		lsr.l	#1,d0
+		bcc		mmmr_nd7\@
+		move.\1	(a1)+,d7
+mmmr_nd7\@:
+		tst.b	d0					// addressregister zu verschieben?
+		beq		mmmr_na7\@			// nein->
+		lsr.l	#1,d0
+		bcc		mmmr_na0\@
+.ifc	1,l
+		move.l	(a1)+,a0_off(a7)
+.else
+		move.w	(a1)+,a0_off+2(a7)
+.endif
+mmmr_na0\@:
+		lsr.l	#1,d0
+		bcc		mmmr_na1\@
+.ifc	1,l
+		move.l	(a1)+,a1_off(a7)
+.else
+		move.w	(a1)+,a1_off+2(a7)
+.endif
+mmmr_na1\@:
+		lsr.l	#1,d0
+		bcc		mmmr_na2\@
+		move.\1	(a1)+,a2
+mmmr_na2\@:
+		lsr.l	#1,d0
+		bcc		mmmr_na3\@
+		move.\1	(a1)+,a3
+mmmr_na3\@:
+		lsr.l	#1,d0
+		bcc		mmmr_na4\@
+		move.\1	(a1)+,a4
+mmmr_na4\@:
+		lsr.l	#1,d0
+		bcc		mmmr_na5\@
+		move.\1	(a1)+,a5
+mmmr_na5\@:
+		lsr.l	#1,d0
+		bcc		mmmr_na6\@
+		move.\1	(a1)+,a6
+mmmr_na6\@:
+		lsr.l	#1,d0
+		bcc		mmmr_na7\@
+		move.\1	(a1)+,a1	// nach a0
+		move.l	a1,usp		// war ja usp
+mmmr_na7\@:
+		ii_end
+		.endm		

BaS_codewarrior/firebeeV1/sources/ii_movep.h

@@ -0,0 +1,179 @@
+//--------------------------------------------------------------------
+// movep
+//--------------------------------------------------------------------
+.text
+ii_movep_lset:.macro 
+	ii_lset_opeau	01,0	//movep.w d(a0-7),d0
+	ii_lset_opeau	03,0	//movep.w d(a0-7),d1
+	ii_lset_opeau	05,0	//movep.w d(a0-7),d2
+	ii_lset_opeau	07,0	//movep.w d(a0-7),d3
+	ii_lset_opeau	09,0	//movep.w d(a0-7),d4
+	ii_lset_opeau	0b,0	//movep.w d(a0-7),d5
+	ii_lset_opeau	0d,0	//movep.w d(a0-7),d6
+	ii_lset_opeau	0f,0	//movep.w d(a0-7),d7
+
+	ii_lset_opeau	01,4	//movep.w d0,d(a0-7)
+	ii_lset_opeau	03,4	//movep.w d1,d(a0-7)
+	ii_lset_opeau	05,4	//movep.w d2,d(a0-7)
+	ii_lset_opeau	07,4	//movep.w d3,d(a0-7)
+	ii_lset_opeau	09,4	//movep.w d4,d(a0-7)
+	ii_lset_opeau	0b,4	//movep.w d5,d(a0-7)
+	ii_lset_opeau	0d,4	//movep.w d6,d(a0-7)
+	ii_lset_opeau	0f,4	//movep.w d7,d(a0-7)
+
+	ii_lset_opeau	01,8	//movep.l d(a0-7),d0
+	ii_lset_opeau	03,8	//movep.l d(a0-7),d1
+	ii_lset_opeau	05,8	//movep.l d(a0-7),d2
+	ii_lset_opeau	07,8	//movep.l d(a0-7),d3
+	ii_lset_opeau	09,8	//movep.l d(a0-7),d4
+	ii_lset_opeau	0b,8	//movep.l d(a0-7),d5
+	ii_lset_opeau	0d,8	//movep.l d(a0-7),d6
+	ii_lset_opeau	0f,8	//movep.l d(a0-7),d7
+
+	ii_lset_opeau	01,c	//movep.l d0,d(a0-7)
+	ii_lset_opeau	03,c	//movep.l d1,d(a0-7)
+	ii_lset_opeau	05,c	//movep.l d2,d(a0-7)
+	ii_lset_opeau	07,c	//movep.l d3,d(a0-7)
+	ii_lset_opeau	09,c	//movep.l d4,d(a0-7)
+	ii_lset_opeau	0b,c	//movep.l d5,d(a0-7)
+	ii_lset_opeau	0d,c	//movep.l d6,d(a0-7)
+	ii_lset_opeau	0f,c	//movep.l d7,d(a0-7)
+.endm
+//---------------------------------------------------------------------------------------------
+ii_movep_func:.macro
+//movep.w d(a0-7),d0-7
+	ii_movep		010,d0_off(a7),wad
+	ii_movep		030,d1_off(a7),wad
+	ii_movep		050,d2,wad
+	ii_movep		070,d3,wad
+	ii_movep		090,d4,wad
+	ii_movep		0b0,d5,wad
+	ii_movep		0d0,d6,wad
+	ii_movep		0f0,d7,wad
+//movep.w d0-7,d(a0-7)
+	ii_movep		014,d0_off(a7),wda
+	ii_movep		034,d1_off(a7),wda
+	ii_movep		054,d2,wda
+	ii_movep		074,d3,wda
+	ii_movep		094,d4,wda
+	ii_movep		0b4,d5,wda
+	ii_movep		0d4,d6,wda
+	ii_movep		0f4,d7,wda
+//movep.l d(a0-7),d0-7
+	ii_movep		018,d0_off(a7),lad
+	ii_movep		038,d1_off(a7),lad
+	ii_movep		058,d2,lad
+	ii_movep		078,d3,lad
+	ii_movep		098,d4,lad
+	ii_movep		0b8,d5,lad
+	ii_movep		0d8,d6,lad
+	ii_movep		0f8,d7,lad
+//movep.l d0-7,d(a0-7)
+	ii_movep		01c,d0_off(a7),lda
+	ii_movep		03c,d1_off(a7),lda
+	ii_movep		05c,d2,lda
+	ii_movep		07c,d3,lda
+	ii_movep		09c,d4,lda
+	ii_movep		0bc,d5,lda
+	ii_movep		0dc,d6,lda
+	ii_movep		0fc,d7,lda
+.endm		
+//---------------------------------------------------------------------------------------------
+ii_movep:.macro	//1=code ziffer 1-3 2=register 3=art
+ii_0x\18:
+#ifdef	halten_movep
+	halt
+#endif
+	move.l			a0_off(a7),a1
+	ii_movep\3_up1	\2
+ii_0x\19:
+#ifdef	halten_movep
+	halt
+#endif
+	move.l			a1_off(a7),a1
+	ii_movep\3_up1	\2
+ii_0x\1a:
+#ifdef	halten_movep
+	halt
+#endif
+	move.l			a2,a1
+	ii_movep\3_up1	\2
+ii_0x\1b:
+#ifdef	halten_movep
+	halt
+#endif
+	move.l			a3,a1
+	ii_movep\3_up1	\2
+ii_0x\1c:
+#ifdef	halten_movep
+	halt
+#endif
+	move.l			a4,a1
+	ii_movep\3_up1	\2
+ii_0x\1d:
+#ifdef	halten_movep
+	halt
+#endif
+	move.l			a5,a1
+	ii_movep\3_up1	\2
+ii_0x\1e:
+#ifdef	halten_movep
+	halt
+#endif
+	move.l			a6,a1
+	ii_movep\3_up1	\2
+ii_0x\1f:
+#ifdef	halten_movep
+	halt
+#endif
+	move.l			usp,a1
+	ii_movep\3_up1	\2
+.endm	
+	
+ii_movepwad_up1:.macro
+	mvs.w			(a0)+,d1
+	add.l			d1,a1
+	move.b			(a1),d0
+	lsl.l			#8,d0
+	move.b			2(a1,d1.l),d0
+	move.w			d0,\1
+	ii_end
+.endm
+
+ii_movepwda_up1:.macro
+	mvs.w			(a0)+,d1
+	add.l			d1,a1
+	move.w			\1,d0
+	move.b			d0,2(a1)
+	lsr.l			#8,d0
+	move.b			d0,(a1)
+	ii_end
+.endm
+	
+ii_moveplad_up1:.macro
+	mvs.w			(a0)+,d1
+	add.l			d1,a1
+	move.b			(a1),d0
+	lsl.l			#8,d0
+	move.b			2(a1),d0
+	lsl.l			#8,d0
+	move.b			4(a1),d0
+	lsl.l			#8,d0
+	move.b			6(a1),d0
+	move.l			d0,\1
+	ii_end
+.endm
+
+ii_moveplda_up1:.macro
+	mvs.w			(a0)+,d1
+	add.l			d1,a1
+	move.l			\1,d0
+	move.b			d0,6(a1)
+	lsr.l			#8,d0
+	move.b			d0,4(a1)
+	lsr.l			#8,d0
+	move.b			d0,2(a1)
+	lsr.l			#8,d0
+	move.b			d0,(a1)
+	ii_end
+.endm

BaS_codewarrior/firebeeV1/sources/ii_op.h

@@ -0,0 +1,661 @@
+/*****************************************************************************************/
+// opertionen
+/*****************************************************************************************/
+ii_lset_op:.macro
+//byt
+	ii_lset_opea	\1,0			// dx,ax
+	ii_lset_opea	\1,1			// (ax), (ax)+
+	ii_lset_opea	\1,2			// -(ax),d16(ax)
+	ii_lset_opeag	\1,3			// d8(ax,dy)
+	lea	table+0x\1\238*4,a0
+	move.l	#ii_0x\138,(a0)+		// xxx.w
+	move.l	#ii_0x\139,(a0)+		// xxx.l
+//word
+	ii_lset_opea	\1,4			// dx,ax
+	ii_lset_opea	\1,5			// (ax), (ax)+
+	ii_lset_opea	\1,6			// -(ax),d16(ax)
+	ii_lset_opeag	\1,7			// d8(ax,dy)
+	lea	table+0x\178*4,a0
+	move.l	#ii_0x\178,(a0)+		// xxx.w
+	move.l	#ii_0x\179,(a0)+		// xxx.l
+//long
+	ii_lset_opea	\1,8			// dx,ax
+	ii_lset_opea	\1,9			// (ax), (ax)+
+	ii_lset_opea	\1,a			// -(ax),d16(ax)
+	ii_lset_opeag	\1,b			// d8(ax,dy)
+	lea	table+0x\1b8*4,a0
+	move.l	#ii_0x\1b8,(a0)+		// xxx.w
+	move.l	#ii_0x\1b9,(a0)+		// xxx.l
+	.endm
+
+ii_lset_opeag:.macro				// 0x1120-0x1127 
+	lea	table+0x\1\20*4,a0
+	move.l	#ii_0x\1\20,(a0)+
+	move.l	#ii_0x\1\21,(a0)+
+	move.l	#ii_0x\1\22,(a0)+
+	move.l	#ii_0x\1\23,(a0)+
+	move.l	#ii_0x\1\24,(a0)+
+	move.l	#ii_0x\1\25,(a0)+
+	move.l	#ii_0x\1\26,(a0)+
+	move.l	#ii_0x\1\27,(a0)+
+	.endm;
+	
+ii_lset_opeau:.macro				// 0x1128-0x112f 
+	lea	table+0x\1\28*4,a0
+	move.l	#ii_0x\1\28,(a0)+
+	move.l	#ii_0x\1\29,(a0)+
+	move.l	#ii_0x\1\2a,(a0)+
+	move.l	#ii_0x\1\2b,(a0)+
+	move.l	#ii_0x\1\2c,(a0)+
+	move.l	#ii_0x\1\2d,(a0)+
+	move.l	#ii_0x\1\2e,(a0)+
+	move.l	#ii_0x\1\2f,(a0)+
+	.endm;
+
+ii_lset_opea:.macro
+	ii_lset_opeag	\1,\2
+	ii_lset_opeau	\1,\2
+	.endm
+/******************************************************/
+ii_op:.macro	// 1=code 2=operation 3 = normal oder immediat/quick
+// byt
+	opdx	\1,\2,b,0,\3		// dx,ax
+	opia	\1,\2,b,1,\3		// (ax),(ax)+
+	opdia	\1,\2,b,2,\3		// -(ax),d16(ax)
+	opd8a	\1,\2,b,3,\3		// d8(ax),xxx
+// word
+	opdx	\1,\2,w,4,\3		// dx,ax
+	opia	\1,\2,w,5,\3		// (ax),(ax)+
+	opdia	\1,\2,w,6,\3		// -(ax),d16(ax)
+	opd8a	\1,\2,w,7,\3		// d8(ax),xxx
+// long
+	opdx	\1,\2,l,8,\3		// dx,ax
+	opia	\1,\2,l,9,\3		// (ax),(ax)+
+	opdia	\1,\2,l,a,\3		// -(ax),d16(ax)
+	opd8a	\1,\2,l,b,\3		// d8(ax),xxx
+	.endm
+/******************************************************/
+// byt word long
+/******************************************************/
+opdx:	.macro	//register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
+ii_0x\1\40:
+	.ifc	\3,b
+		op\5smd	\2,d0_off+3(a7),d0_off+3(a7),\3
+	.else
+		.ifc		\3,w
+			op\5smd	\2,d0_off+2(a7),d0_off+2(a7),\3
+		.else
+			op\5smd	\2,d0_off(a7),d0_off(a7),\3
+		.endif
+	.endif
+ii_0x\1\41:
+	.ifc	\3,b
+		op\5smd	\2,d1_off+3(a7),d1_off+3(a7),\3
+	.else
+		.ifc		\3,w
+			op\5smd	\2,d1_off+2(a7),d1_off+2(a7),\3
+		.else
+			op\5smd	\2,d1_off(a7),d1_off(a7),\3
+		.endif
+.endif
+ii_0x\1\42:
+	op\5smd	\2,d2,d2,\3
+ii_0x\1\43:
+	op\5smd	\2,d3,d3,\3
+ii_0x\1\44:
+	op\5smd	\2,d4,d4,\3
+ii_0x\1\45:
+	op\5smd	\2,d5,d5,\3
+ii_0x\1\46:
+	op\5smd	\2,d6,d6,\3
+ii_0x\1\47:
+	op\5smd	\2,d7,d7,\3
+//ax
+ii_0x\1\48:
+	opa\5smd	\2,a0_off(a7),a0_off(a7),\3
+ii_0x\1\49:
+	opa\5smd	\2,a1_off(a7),a1_off(a7),\3
+ii_0x\1\4a:
+	opa\5smd	\2,a2,a2,\3
+ii_0x\1\4b:
+	opa\5smd	\2,a3,a3,\3
+ii_0x\1\4c:
+	opa\5smd	\2,a4,a4,\3
+ii_0x\1\4d:
+	opa\5smd	\2,a5,a5,\3
+ii_0x\1\4e:
+	opa\5smd	\2,a6,a6,\3
+ii_0x\1\4f:
+	opa\5smd	\2,usp,usp,\3
+.endm;
+//-----------------------------------------------
+opia:	.macro	// (ax) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
+//(ax)
+ii_0x\1\40:
+	op\5sia	\2,a0_off(a7),(a1),(a1),\3
+ii_0x\1\41:
+	op\5sia	\2,a1_off(a7),(a1),(a1),\3
+ii_0x\1\42:
+	op\5smd	\2,(a2),(a2),\3
+ii_0x\1\43:
+	op\5smd	\2,(a3),(a3),\3
+ii_0x\1\44:
+	op\5smd	\2,(a4),(a4),\3
+ii_0x\1\45:
+	op\5smd	\2,(a5),(a5),\3
+ii_0x\1\46:
+	op\5smd	\2,(a6),(a6),\3
+ii_0x\1\47:
+	op\5sia	\2,usp,(a1),(a1),\3
+//(ax)+
+ii_0x\1\48:
+	op\5sia	\2,a0_off(a7),(a1),(a1)+,\3
+ii_0x\1\49:
+	op\5sia	\2,a1_off(a7),(a1),(a1)+,\3
+ii_0x\1\4a:
+	op\5smd	\2,(a2),(a2)+,\3
+ii_0x\1\4b:
+	op\5smd	\2,(a3),(a3)+,\3
+ii_0x\1\4c:
+	op\5smd	\2,(a4),(a4)+,\3
+ii_0x\1\4d:
+	op\5smd	\2,(a5),(a5)+,\3
+ii_0x\1\4e:
+	op\5smd	\2,(a6),(a6)+,\3
+ii_0x\1\4f:
+	op\5sia	\2,usp,(a1),(a1)+,\3
+.endm;
+//-----------------------------------------------
+opdia:	.macro	// -(ax) \1=code \2 = operation \3 = size \4 size and adressierungsart 5 = immediate oder normal
+ii_0x\1\40:
+	op\5sia	\2,a0_off(a7),-(a1),(a1),\3
+ii_0x\1\41:
+	op\5sia	\2,a1_off(a7),-(a1),(a1),\3
+ii_0x\1\42:
+	op\5smd	\2,-(a2),(a2),\3
+ii_0x\1\43:
+	op\5smd	\2,-(a3),(a3),\3
+ii_0x\1\44:
+	op\5smd	\2,-(a4),(a4),\3
+ii_0x\1\45:
+	op\5smd	\2,-(a5),(a5),\3
+ii_0x\1\46:
+	op\5smd	\2,-(a6),(a6),\3
+ii_0x\1\47:
+	op\5sia	\2,usp,-(a1),(a1),\3
+
+ii_0x\1\48:
+	op\5sd16a	\2,a0_off(a7),\3
+ii_0x\1\49:
+	op\5sd16a	\2,a1_off(a7),\3
+ii_0x\1\4a:
+	op\5sd16a	\2,a2,\3
+ii_0x\1\4b:
+	op\5sd16a	\2,a3,\3
+ii_0x\1\4c:
+	op\5sd16a	\2,a4,\3
+ii_0x\1\4d:
+	op\5sd16a	\2,a5,\3
+ii_0x\1\4e:
+	op\5sd16a	\2,a6,\3
+ii_0x\1\4f:
+	op\5sd16a	\2,usp,\3
+.endm;
+//-----------------------------------------------
+opd8a:	.macro	// d8(ax,dy) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
+ii_0x\1\40:
+	op\5sd8a	\2,a0_off(a7),\3
+ii_0x\1\41:
+	op\5sd8a	\2,a1_off(a7),\3
+ii_0x\1\42:
+	op\5sd8a	\2,a2,\3
+ii_0x\1\43:
+	op\5sd8a	\2,a3,\3
+ii_0x\1\44:
+	op\5sd8a	\2,a4,\3
+ii_0x\1\45:
+	op\5sd8a	\2,a5,\3
+ii_0x\1\46:
+	op\5sd8a	\2,a6,\3
+ii_0x\1\47:
+	op\5sd8a	\2,usp,\3
+
+ii_0x\1\48:
+	op\5sxx		\2,\3,w
+ii_0x\1\49:
+	op\5sxx		\2,\3,l
+.endm;
+//-----------------------------------------------
+opnsmd:.macro		// direct dx: 1=operation	2=ea src 3=ea dest 4=size
+#ifdef	halten_op
+	halt
+#endif
+.ifc	\4,l
+	move.l	\2,d1
+.else
+	mvs.\4	\2,d1
+.endif
+	.ifc	\1,negx
+		move.b		sr_off+1(a7),d1			//ccr holen
+		move		d1,ccr					//setzen
+	.endif		
+	\1	d1
+	set_cc0
+	move.\4		d1,\3
+	ii_end
+	.endm;
+
+opansmd:.macro		// direct ax: 1=operation	2=ea src 3=ea dest 4=size
+#ifdef	halten_op
+	halt
+#endif
+
+.ifc	\2,usp
+		move.l	usp,a1
+		move.l	a1,d1
+.else
+		move.l		\2,d1
+.endif
+	\1	d1
+.ifc	\3,usp
+	move.l		d1,a1
+	move.l		a1,usp
+.else
+	move.l		d1,\3
+.endif
+	ii_end
+.endm;
+
+opnsia:.macro		// indirect: 1=operation 2=adress register 3= src 4=dest 5=size
+#ifdef	halten_op
+	halt
+#endif
+	move.l	\2,a1
+.ifc	\5,l
+	move.l	\3,d1
+.else
+	mvs.\5	\3,d1
+.endif
+	.ifc	\1,negx
+		move.b		sr_off+1(a7),d1			//ccr holen
+		move		d1,ccr					//setzen
+	.endif		
+	\1	d1
+	set_cc0
+	move.\5	d1,\4
+	ii_end
+	.endm;
+
+opnsd16a:.macro		// indirect: 1=operation 2=adress register 3=size
+#ifdef	halten_op
+	halt
+#endif
+	move.l	\2,a1
+	mvs.w	(a0)+,d1
+	add.l	d1,a1
+.ifc	\3,l
+	move.l	(a1),d1
+.else
+	mvs.\3	(a1),d1
+.endif
+	.ifc	\1,negx
+		move.b		sr_off+1(a7),d1			//ccr holen
+		move		d1,ccr					//setzen
+	.endif		
+	\1	d1
+	set_cc0
+	move.\3	d1,(a1)
+	ii_end
+	.endm;
+
+opnsd8a:.macro		// indirect: 1=operation 2=adress register 3=size
+#ifdef	halten_op
+	halt
+#endif
+	move.l	\2,a1
+	jsr		ewf
+.ifc	\3,l
+	move.l	(a1),d1
+.else
+	mvs.\3	(a1),d1
+.endif
+	.ifc	\1,negx
+		move.b		sr_off+1(a7),d1			//ccr holen
+		move		d1,ccr					//setzen
+	.endif		
+	\1	d1
+	set_cc0
+	move.\3	d1,(a1)
+	ii_end
+	.endm;
+
+opnsxx:.macro		// indirect: 1=operation 2=size 3=size adresse
+#ifdef	halten_op
+	halt
+#endif
+
+.ifc	\2,l
+	move.l	(a1),d1
+.else
+	mvs.\2	(a1),d1
+.endif
+	move.\3	(a0)+,a1
+	.ifc	\1,negx
+		move.b		sr_off+1(a7),d1			//ccr holen
+		move		d1,ccr					//setzen
+	.endif		
+	\1	d1
+	set_cc0
+	move.\2	d1,(a1)
+	ii_end
+	.endm;
+//*******************************************************************************3
+opismd:.macro		// immediate dx: 1=opieration	2=ea src 3=ea dest 4=size
+#ifdef	halten_op
+	halt
+#endif
+
+.ifc	\4,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\4,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+.ifc	\4,l
+	move.l	\2,d1
+.else
+	mvs.\4	\2,d1
+.endif
+	\1	d0,d1
+	set_cc0
+.ifnc	\1,cmp.l
+	move.\4		d1,\3
+.endif
+	ii_end
+.endm;
+
+opaismd:.macro		// immediate ax: 1=opieration	2=ea src 3=ea dest 4=size
+#ifdef	halten_op
+	halt
+#endif
+
+.ifc	\4,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\4,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+.ifc	\2,usp
+		move.l	usp,a1
+		move.l	a1,d1
+.else
+		move.l		\2,d1
+.endif
+	\1	d0,d1
+.ifnc	\1,cmp.l
+.ifc	\3,usp
+	move.l		d1,a1
+	move.l		a1,usp
+.else
+	move.l		d1,\3
+.endif
+.endif
+	ii_end
+.endm;
+
+opisia:.macro		// indirect: 1=opieration 2=adress register 3= src 4=dest 5=size
+#ifdef	halten_op
+	halt
+#endif
+
+.ifc	\5,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\5,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+	move.l	\2,a1
+.ifc	\5,l
+	move.l	\3,d1
+.else
+	mvs.\5	\3,d1
+.endif
+	\1	d0,d1
+	set_cc0
+.ifnc	\1,cmp.l
+	move.\5	d1,\4
+.endif
+	ii_end
+.endm;
+
+opisd16a:.macro		// indirect: 1=opieration 2=adress register 3=size
+#ifdef	halten_op
+	halt
+#endif
+
+.ifc	\3,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\3,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+	move.l	\2,a1
+	mvs.w	(a0)+,d1
+	add.l	d1,a1
+.ifc	\3,l
+	move.l	(a1),d1
+.else
+	mvs.\3	(a1),d1
+.endif
+	\1	d0,d1
+	set_cc0
+.ifnc	\1,cmp.l
+	move.\3	d1,(a1)
+.endif
+	ii_end
+	.endm;
+
+opisd8a:.macro		// indirect: 1=opieration 2=adress register 3=size
+#ifdef	halten_op
+	halt
+#endif
+
+.ifc	\3,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\3,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+	move.l	d0,_d0_save
+	move.l	\2,a1
+	jsr		ewf
+	move.l	_d0_save,d0
+.ifc	\3,l
+	move.l	(a1),d1
+.else
+	mvs.\3	(a1),d1
+.endif
+	\1	d0,d1
+	set_cc0
+.ifnc	\1,cmp.l
+	move.\3	d1,(a1)
+.endif
+	ii_end
+	.endm;
+
+opisxx:.macro		// immediate: 1=opieration 2=size 3=size adresse
+.ifc	\2,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\2,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+	move.\3	(a0)+,a1
+.ifc	\2,l
+	move.l	(a1),d1
+.else
+	mvs.\2	(a1),d1
+.endif
+	\1	d0,d1
+	set_cc0
+.ifnc	\1,cmp.l
+	move.\2	d1,(a1)
+.endif
+	ii_end
+	.endm;
+//*******************************************************************************3
+opqsmd:.macro		// quick: 1=opieration	2=ea src 3=ea dest 4=size
+.ifc	\4,l
+	move.l	\2,d1
+.else
+	mvs.\4	\2,d1
+.endif
+.ifc	\1,eor.l d0
+	move.l	d0_off(a7),d0
+.endif
+.ifc	\1,eor.l d1
+	move.l	d1_off(a7),d1
+.endif
+	\1	,d1
+	set_cc0
+	move.\4		d1,\3
+	ii_end
+	.endm;
+
+opaqsmd:.macro		// quick: 1=opieration	2=ea src 3=ea dest 4=size
+.ifc	\2,usp
+		move.l	usp,a1
+		move.l	a1,d1
+.else
+		move.l		\2,d1
+.endif
+	\1	,d1
+.ifc	\3,usp
+	move.l		d1,a1
+	move.l		a1,usp
+.else
+	move.l		d1,\3
+.endif
+	ii_end
+	.endm;
+
+opqsia:.macro		// indirect: 1=opieration 2=adress register 3= src 4=dest 5=size
+#ifdef	halten_op
+	halt
+#endif
+
+	move.l	\2,a1
+.ifc	\5,l
+	move.l	\3,d1
+.else
+	mvs.\5	\3,d1
+.endif
+.ifc	\1,eor.l d0
+	move.l	d0_off(a7),d0
+.endif
+.ifc	\1,eor.l d1
+	move.l	d1_off(a7),d1
+.endif
+	\1	,d1
+	set_cc0
+	move.\5	d1,\4
+	ii_end
+	.endm;
+
+opqsd16a:.macro		// indirect: 1=opieration 2=adress register 3=size
+#ifdef	halten_op
+	halt
+#endif
+
+	move.l	\2,a1
+	mvs.w	(a0)+,d1
+	add.l	d1,a1
+.ifc	\3,l
+	move.l	(a1),d1
+.else
+	mvs.\3	(a1),d1
+.endif
+.ifc	\1,eor.l d0
+	move.l	d0_off(a7),d0
+.endif
+.ifc	\1,eor.l d1
+	move.l	d1_off(a7),d1
+.endif
+	\1	,d1
+	set_cc0
+	move.\3	d1,(a1)
+	ii_end
+	.endm;
+
+opqsd8a:.macro		// indirect: 1=opieration 2=adress register 3=size
+#ifdef	halten_op
+	halt
+#endif
+
+	move.l	d0,_d0_save
+	move.l	\2,a1
+	jsr		ewf
+	move.l	_d0_save,d0
+.ifc	\3,l
+	move.l	(a1),d1
+.else
+	mvs.\3	(a1),d1
+.endif
+.ifc	\1,eor.l d0
+	move.l	d0_off(a7),d0
+.endif
+.ifc	\1,eor.l d1
+	move.l	d1_off(a7),d1
+.endif
+	\1	,d1
+	set_cc0
+	move.\3	d1,(a1)
+	ii_end
+	.endm;
+
+opqsxx:.macro		// quick: 1=opieration 2=size 3=size adresse
+#ifdef	halten_op
+	halt
+#endif
+
+	move.\3	(a0)+,a1
+.ifc	\2,l
+	move.l	(a1),d1
+.else
+	mvs.\2	(a1),d1
+.endif
+.ifc	\1,eor.l d0
+	move.l	d0_off(a7),d0
+.endif
+.ifc	\1,eor.l d1
+	move.l	d1_off(a7),d1
+.endif
+	\1	,d1
+	set_cc0
+	move.\2	d1,(a1)
+	ii_end
+	.endm;

BaS_codewarrior/firebeeV1/sources/ii_opc.h

@@ -0,0 +1,263 @@
+/*****************************************************************************************/
+// functionen macros: fehlende adressierungsarte (MCF nur Dx support) ohne ax
+// zusammen mit op.h
+/*****************************************************************************************/
+ii_lset_opc:.macro
+	ii_lset_opeag	\1,c			// dx,ax
+	ii_lset_opea	\1,d			// (ax), (ax)+
+	ii_lset_opea	\1,e			// -(ax),d16(ax)
+	ii_lset_opeag	\1,f			// d8(ax,dy)
+	lea	table+0x\1b8*4,a0
+	move.l	#ii_0x\1b8,(a0)+		// xxx.w
+	move.l	#ii_0x\1b9,(a0)+		// xxx.l
+	.endm
+
+/******************************************************/
+ii_opc:.macro	// 1=code 2=operation 3 = normal oder immediat
+	opcdx	\1,\2,l,c,\3		// dx,ax
+	opia	\1,\2,l,d,\3		// (ax),(ax)+
+	opdia	\1,\2,l,e,\3		// -(ax),d16(ax)
+	opd8a	\1,\2,l,f,\3		// d8(ax),xxx
+	.endm
+//*******************************************************************************3
+/******************************************************/
+// byt word long
+/******************************************************/
+opcdx:	.macro	//register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
+ii_0x\1\40:
+#ifdef	halten_opc
+	halt
+#endif
+	.ifc	\3,b
+		op\5smd	\2,d0_off+3(a7),d0_off+3(a7),\3
+	.else
+		.ifc		\3,w
+			op\5smd	\2,d0_off+2(a7),d0_off+2(a7),\3
+		.else
+			op\5smd	\2,d0_off(a7),d0_off(a7),\3
+		.endif
+	.endif
+ii_0x\1\41:
+	.ifc	\3,b
+		op\5smd	\2,d1_off+3(a7),d1_off+3(a7),\3
+	.else
+		.ifc		\3,w
+			op\5smd	\2,d1_off+2(a7),d1_off+2(a7),\3
+		.else
+			op\5smd	\2,d1_off(a7),d1_off(a7),\3
+		.endif
+.endif
+ii_0x\1\42:
+	op\5smd	\2,d2,d2,\3
+ii_0x\1\43:
+	op\5smd	\2,d3,d3,\3
+ii_0x\1\44:
+	op\5smd	\2,d4,d4,\3
+ii_0x\1\45:
+	op\5smd	\2,d5,d5,\3
+ii_0x\1\46:
+	op\5smd	\2,d6,d6,\3
+ii_0x\1\47:
+	op\5smd	\2,d7,d7,\3
+.endm
+//-----------------------------------------------------
+opcsmd:.macro		// dx: 1=opieration	2=ea src 3=ea dest 4=size
+#ifdef	halten_opc
+	halt
+#endif
+
+.ifc	\4,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\4,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+.ifc	\4,l
+	move.l	\2,d1
+.else
+	mvs.\4	\2,d1
+.endif
+.ifc	\1,eor.l d0
+	move.l	d0_off(a7),d1
+.endif
+.ifc	\1,eor.l d1
+	move.l	d1_off(a7),d1
+.endif
+	\1	d1
+	set_cc0
+	move.\4		d1,\3
+	ii_end
+	.endm;
+
+opacsmd:.macro		// ax: 1=opieration	2=ea src 3=ea dest 4=size
+#ifdef	halten_opc
+	halt
+#endif
+
+.ifc	\4,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\4,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+.ifc	\2,usp
+		move.l	usp,a1
+		move.l	a1,d1
+.else
+		move.l		\2,d1
+.endif
+	\1	d1
+	set_cc0
+.ifc	\3,usp
+	move.l		d1,a1
+	move.l		a1,usp
+.else
+	move.l		d1,\3
+.endif
+	ii_end
+	.endm;
+
+opcsia:.macro		// (ax) (ax)+ -(ax): 1=opieration 2=adress register 3= src 4=dest 5=size
+#ifdef	halten_opc
+	halt
+#endif
+
+.ifc	\4,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\4,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+	move.l	\2,a1
+.ifc	\5,l
+	move.l	\3,d1
+.else
+	mvs.\5	\3,d1
+.endif
+.ifc	\1,eor.l d0
+	move.l	d0_off(a7),d1
+.endif
+.ifc	\1,eor.l d1
+	move.l	d1_off(a7),d1
+.endif
+	\1	d1
+	set_cc0
+	move.\5	d1,\4
+	ii_end
+	.endm;
+
+opcsd16a:.macro		// d16(ax): 1=opieration 2=adress register 3=size
+#ifdef	halten_opc
+	halt
+#endif
+
+.ifc	\4,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\4,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+	move.l	\2,a1
+	mvs.w	(a0)+,d1
+	add.l	d1,a1
+.ifc	\3,l
+	move.l	(a1),d1
+.else
+	mvs.\3	(a1),d1
+.endif
+.ifc	\1,eor.l d0
+	move.l	d0_off(a7),d1
+.endif
+.ifc	\1,eor.l d1
+	move.l	d1_off(a7),d1
+.endif
+	\1	d1
+	set_cc0
+	move.\3	d1,(a1)
+	ii_end
+	.endm;
+
+opcsd8a:.macro		// indirect: 1=opieration 2=adress register 3=size
+#ifdef	halten_opc
+	halt
+#endif
+
+.ifc	\4,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\4,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+	move.l	d0,_d0_save
+	move.l	\2,a1
+	jsr		ewf
+	move.l	_d0_save,d0
+.ifc	\3,l
+	move.l	(a1),d1
+.else
+	mvs.\3	(a1),d1
+.endif
+.ifc	\1,eor.l d0
+	move.l	d0_off(a7),d1
+.endif
+.ifc	\1,eor.l d1
+	move.l	d1_off(a7),d1
+.endif
+	\1	d1
+	set_cc0
+	move.\3	d1,(a1)
+	ii_end
+	.endm;
+
+opcsxx:.macro		// indirect: 1=opieration 2=size 3=size adresse
+#ifdef	halten_opc
+	halt
+#endif
+
+.ifc	\2,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\2,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+	move.\3	(a0)+,a1
+.ifc	\2,l
+	move.l	(a1),d1
+.else
+	mvs.\2	(a1),d1
+.endif
+.ifc	\1,eor.l d0
+	move.l	d0_off(a7),d1
+.endif
+.ifc	\1,eor.l d1
+	move.l	d1_off(a7),d1
+.endif
+	\1	d1
+	set_cc0
+	move.\2	d1,(a1)
+	ii_end
+	.endm;

BaS_codewarrior/firebeeV1/sources/ii_or.h

@@ -0,0 +1,442 @@
+//--------------------------------------------------------------------
+// or
+//--------------------------------------------------------------------
+/*****************************************************************************************/
+//--------------------------------------------------------------------
+// byt
+//--------------------------------------------------------------------
+//--------------------------------------------------------------------
+// or.b	#im,dx
+//--------------------------------------------------------------------
+orbir_macro:.macro
+#ifdef	halten_or
+	halt
+#endif
+	move.w		(a0)+,d0
+	extb.l		d0
+	mvs.b		\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.b		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	ea,dx
+//--------------------------------------------------------------------
+ordd:.macro
+#ifdef	halten_or
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	ea(l)->dy(w),dx z.B. f<>r USP
+//--------------------------------------------------------------------
+orddd:.macro
+#ifdef	halten_or
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		a1,d0
+	mvs.\3		\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	(ea)->dy,dx
+//--------------------------------------------------------------------
+ordda:.macro
+#ifdef	halten_or
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	ea->ay,(ay)+,dx
+//--------------------------------------------------------------------
+orddai:.macro
+#ifdef	halten_or
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		(a1)+,d0
+	move.l		a1,\1
+	mvs.\3		\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	ea->ay,-(ay),dx
+//--------------------------------------------------------------------
+orddad:.macro
+#ifdef	halten_or
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		-(a1),d0
+	move.l		a1,\1
+	mvs.\3		\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	d16(ay),dx
+//--------------------------------------------------------------------
+ord16ad:.macro
+#ifdef	halten_or
+	halt
+#endif
+	move.l		\1,a1
+	mvs.w		(a0)+,d0
+	add.l		d0,a1
+	mvs.\3		(a1),d0		
+	mvs.\3		\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	d8(ay,dy),dx
+//--------------------------------------------------------------------
+ord8ad:.macro
+#ifdef	halten_or
+	halt
+#endif
+	move.l		\1,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d0
+	move.l		\2,d1
+.else
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+.endif
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	xxx.w,dx
+//--------------------------------------------------------------------
+orxwd:.macro
+#ifdef	halten_or
+	halt
+#endif
+	move.w		(a0)+,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	xxx.l,dx
+//--------------------------------------------------------------------
+orxld:.macro
+#ifdef	halten_or
+	halt
+#endif
+	move.l		(a0)+,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	d16(pc),dx
+//--------------------------------------------------------------------
+ord16pcd:.macro
+	halt
+	move.l		a0,a1
+	mvs.w		(a0)+,d0
+	add.l		d0,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	d8(pc,dy),dx
+//--------------------------------------------------------------------
+ord8pcd:.macro
+#ifdef	halten_or
+	halt
+#endif
+	move.l		a0,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d0
+	move.l		\2,d1
+.else
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+.endif
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+//  or dy,ea
+//--------------------------------------------------------------------
+//--------------------------------------------------------------------
+// // or	(ea)->dy,dx
+//--------------------------------------------------------------------
+oreda:.macro
+#ifdef	halten_or
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		(a1),d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	dx,ea->ay,(ay)+
+//--------------------------------------------------------------------
+oredai:.macro
+#ifdef	halten_or
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		(a1),d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)+
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	dx,ea->ay,(ay)+
+//--------------------------------------------------------------------
+oredaid:.macro
+#ifdef	halten_or
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2+
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	dx,ea->ay,-(ay)
+//--------------------------------------------------------------------
+oredad:.macro
+#ifdef	halten_or
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		-(a1),d1
+	move.l		a1,\2
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	dx,ea->ay,-(ay)
+//--------------------------------------------------------------------
+oredadd:.macro
+#ifdef	halten_or
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		-\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	dx,d16(ay)
+//--------------------------------------------------------------------
+ore16ad:.macro
+#ifdef	halten_or
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.w		(a0)+,d1
+	add.l		d1,a1
+	mvs.\3		(a1),d1		
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or.w	dx,d8(ay,dy)
+//--------------------------------------------------------------------
+ore8ad:.macro
+#ifdef	halten_or
+	halt
+#endif
+	move.l		\2,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d1
+	move.l		\1,d0
+.else
+	mvs.\3		(a1),d1
+	mvs.\3		\1,d0
+.endif
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	dx,xxx.w
+//--------------------------------------------------------------------
+orxwe:.macro
+#ifdef	halten_or
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.w		(a0)+,a1
+	mvs.\3		(a1),d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	dx,xxx.l
+//--------------------------------------------------------------------
+orxle:.macro
+#ifdef	halten_or
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		(a0)+,a1
+	mvs.\3		(a1),d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // ora.w	ea,ax
+//--------------------------------------------------------------------
+oraw:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// or.w ea,usp
+//--------------------------------------------------------------------
+orawa7:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // ora.w	usp?,ax
+//--------------------------------------------------------------------
+orawu:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // ora.w	usp?,usp
+//--------------------------------------------------------------------
+orawua7:.macro
+	orawu		\1,\2
+	.endm;
+//--------------------------------------------------------------------
+// // ora.w	d16(ay),ax
+//--------------------------------------------------------------------
+orawd16a:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // ora.w	d8(ay,dy),ax
+//--------------------------------------------------------------------
+orawd8a:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // ora.w	xxx.w,ax
+//--------------------------------------------------------------------
+orawxwax:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // ora.w	xxx.l,ax
+//--------------------------------------------------------------------
+orawxlax:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // ora.w	d16(pc),ax
+//--------------------------------------------------------------------
+orawd16pcax:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // ora.w	d8(pc,dy),ax
+//--------------------------------------------------------------------
+orawd8pcax:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // ora.w	#im,ax
+//--------------------------------------------------------------------
+orawim:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // ora.l	d8(ay,dy),ax
+//--------------------------------------------------------------------
+orald8a:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // ora.l	d8(pc,dy),ax
+//--------------------------------------------------------------------
+orald8pcax:.macro
+	jmp			ii_error
+	.endm;
+//*****************************************************************************************
+// spezial addx subx etc.
+//--------------------------------------------------------------------
+//--------------------------------------------------------------------
+// // addx	dy,dx
+//--------------------------------------------------------------------
+ordx:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // addx	-(ay),-(ax)
+//--------------------------------------------------------------------
+ordax:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------

BaS_codewarrior/firebeeV1/sources/ii_pea.h

@@ -0,0 +1,74 @@
+//--------------------------------------------------------------------
+// pea
+//--------------------------------------------------------------------
+.text
+ii_pea_lset:.macro
+	ii_lset_opeag	48,7
+	ii_lset	0x487b 
+.endm
+//---------------------------------------------------------------------------------------------
+ii_pea_func:.macro
+ii_0x4870:
+#ifdef	halten_pea
+	halt
+#endif
+	move.l	a0_off(a7),a1
+	pea_macro
+ii_0x4871:
+#ifdef	halten_pea
+	halt
+#endif
+	move.l	a1_off(a7),a1
+	pea_macro
+ii_0x4872:
+#ifdef	halten_pea
+	halt
+#endif
+	move.l	a2,a1
+	pea_macro
+ii_0x4873:
+#ifdef	halten_pea
+	halt
+#endif
+	move.l	a3,a1
+	pea_macro
+ii_0x4874:
+#ifdef	halten_pea
+	halt
+#endif
+	move.l	a4,a1
+	pea_macro
+ii_0x4875:
+#ifdef	halten_pea
+	halt
+#endif
+	move.l	a5,a1
+	pea_macro
+ii_0x4876:
+#ifdef	halten_pea
+	halt
+#endif
+	move.l	a6,a1
+	pea_macro
+ii_0x4877:
+#ifdef	halten_pea
+	halt
+#endif
+	move.l	usp,a1
+	pea_macro
+ii_0x487b:
+#ifdef	halten_pea
+	halt
+#endif
+	move.l	a0,a1
+	pea_macro
+.endm		
+//---------------------------------------------------------------------------------------------
+pea_macro:.macro
+	jsr		ewf
+	move.l	(a1),d0
+	move.l	usp,a1
+	move.l	d0,-(a1)
+	move.l	a1,usp
+	ii_end
+.endm

BaS_codewarrior/firebeeV1/sources/ii_shd.h

@@ -0,0 +1,247 @@
+/*****************************************************************************************/
+// opertionen
+/*****************************************************************************************/
+ii_lset_shd:.macro
+	ii_lset_shdx	e0			//r d0
+	ii_lset_shdx	e2			//r d1
+	ii_lset_shdx	e4			//r d2
+	ii_lset_shdx	e6			//r d3
+	ii_lset_shdx	e8			//r d4
+	ii_lset_shdx	ea			//r d5
+	ii_lset_shdx	ec			//r d6
+	ii_lset_shdx	ee			//r d7
+	
+	ii_lset_shdx	e1			//l d0
+	ii_lset_shdx	e3			//l d1
+	ii_lset_shdx	e4			//l d2
+	ii_lset_shdx	e5			//l d3
+	ii_lset_shdx	e9			//l d4
+	ii_lset_shdx	eb			//l d5
+	ii_lset_shdx	ed			//l d6
+	ii_lset_shdx	ef			//l d7
+	.endm
+	
+ii_lset_shdx:.macro
+//byt
+	ii_lset_opea	\1,0			// as,ls #im,dx
+	ii_lset_opea	\1,1			// rox,ro #im,dx
+	ii_lset_opea	\1,2			// as,ls dy,dx
+	ii_lset_opea	\1,3			// rox,ro dy,dx
+//word
+	ii_lset_opea	\1,4			// as,ls #im,dx
+	ii_lset_opea	\1,5			// rox,ro #im,dx
+	ii_lset_opea	\1,6			// as,ls dy,dx
+	ii_lset_opea	\1,7			// rox,ro dy,dx
+//long
+//	ii_lset_opea	\1,8			// as,ls #im,dx -> vorhanden
+	ii_lset_opea	\1,9			// rox,ro #im,dx
+//	ii_lset_opea	\1,a			// as,ls dy,dx	-> vorhanden
+	ii_lset_opea	\1,b			// rox,ro dy,dx
+	.endm
+/******************************************************/
+ii_shd:.macro	// 1=code 2=operation 3 = normal, direct oder immediat
+// byt
+	opdx	\1,\2,b,0,\3		// dx
+// word
+	opdx	\1,\2,w,4,\3		// dx
+// long
+	opdx	\1,\2,l,8,\3		// dx
+	.endm
+/******************************************************/
+// byt word long routinen
+/******************************************************/
+sh_asr:	.macro		// asr -> 1=operation 2 = dx 3 = dy/im 4 = size b/w
+	mvs.\4		\2,d1
+	sh_shal		\1,\2,\3,\4
+	.endm	
+
+sh_lsr:	.macro		// asl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w
+	mvz.\4		\2,d1
+	sh_shal		\1,\2,\3,\4
+	.endm
+	
+sh_shal:.macro
+	move.w		\3,d0
+	\1.l		d0,d1
+	set_cc0
+	move.\4		d1,\2
+	.endm	
+	
+sh_all:	.macro		// asl/lsl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w
+	mvz.\4		\2,d1
+.ifc	\4,b
+	byterev.l	d1
+.else
+	swap.w		d1
+.endif
+	sh_asr		\1,\2,\3,\4
+	.endm	
+	
+sh_ror:	.macro		// ror -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l
+	move.\4	\2,d1	/
+	move.w	\3,d0
+.ifc	\4,b
+	lsl.l	#8,d1
+	move.b	\2,d1
+	and.l	#0x7,d0
+	lsr.l	d0,d1
+.else
+	.ifc	\4,w
+		swap.w	d1
+		move.w	\2,d1
+		and.l	#0xf,d0
+		lsr.l	d0,d1
+	.else
+		and.l	#0x1f,d0
+		lsr.l	d0,d1
+		move.l	d1,a1
+		move.l	\2,d1
+		sub.l	#32,d0
+		neg.l	d0
+		lsl.l	d0,d1
+		add.l	a1,d1
+	.endif
+.endif
+	move.\4	d1,\2
+	move.w	ccr,d0
+	and.l	#1,d1	// ist auch carry bit
+	or.l	d1,d0	
+	move.b	d0,ccr_off(a7)
+	.endm
+	
+sh_rol:	.macro		// rol -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l
+	move.\4	\2,d1	
+	move.w	\3,d0
+.ifc	\4,b
+	lsl.l	#8,d1
+	move.b	\2,d1
+	and.l	#0x7,d0
+	lsl.l	d0,d1
+	lsr.l	#8,d1
+	moveq	#7,d0
+.else
+	.ifc	\4,w
+		swap.w	d1
+		move.w	\2,d1
+		and.l	#0xf,d0
+		lsr.l	d0,d1
+		swap.w	d1
+		moveq	#15,d0
+	.else
+		and.l	#0x1f,d0
+		lsl.l	d0,d1
+		move.l	d1,a1
+		move.l	\2,d1
+		sub.l	#32,d0
+		neg.l	d0
+		lsr.l	d0,d1
+		add.l	a1,d1
+		moveq	#31,d0
+	.endif
+.endif
+	move.\4	d1,\2
+	lsr.l	d0,d1		// carry bit schieben
+	move.w	ccr,d0
+	and.l	#1,d1
+	or.l	d1,d0	
+	move.b	d0,ccr_off(a7)
+	.endm
+	
+sh_roxr:	.macro		// roxr -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l
+	clr.l	d0
+	addx.l	d0,d0
+ifc	\4,b
+	mvz.b	\2,d1
+	lsl.l	#1,d1
+	add.l	d0,d1
+	lsl.l	#8,d1
+	move.b	\2,d1
+	move.w	\3,d0
+	and.l	#0x7,d0
+	lsr.l	d0,d1
+	set_cc0
+else
+	.ifc	\4,w
+		mvz.b	\2,d1
+		lsl.l	#1,d1
+		add.l	d0,d1
+		lsl.l	#8,d1
+		lsl.l	#8,d1
+		move.w	\2,d1
+		move.w	\3,d0
+		and.l	#0xf,d0
+		lsr.l	d0,d1
+		set_cc0
+	.else
+		bitrev.l d0
+		move.l	\2,d1
+		lsr.l	#1,d1
+		add.l	d0,d1
+		move.w	\3,d0
+		subq.l	#1,d0
+		and.l	#0x1f,d0
+		lsr.l	d0,d1
+		move.l	d1,a1
+		set_cc1
+		move.l	\2,d1
+		sub.l	#32,d0
+		neg.l	d0
+		lsl.l	d0,d1
+		add.l	a1,d1
+	.endif
+.endif
+	move.\4	d1,\2
+	.endm
+	
+sh_roxl:	.macro		// roxl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l
+	clr.l	d0
+	addx.l	d0,d0
+ifc	\4,b
+	mvz.b	\2,d1
+	lsl.l	#1,d1
+	add.l	d0,d1
+	lsl.l	#8,d1
+	move.b	\2,d1
+	lsl.l	#8,d1
+	lsl.l	#7,d1
+	move.w	\3,d0
+	and.l	#0x7,d0
+	lsl.l	d0,d1
+	set_cc0
+	byterev.l d1
+else
+	.ifc	\4,w
+		mvz.b	\2,d1
+		lsl.l	#1,d1
+		add.l	d0,d1
+		lsl.l	#8,d1
+		lsl.l	#7,d1
+		mvz.w	\2,d0
+		lsr.l	#1,d0
+		add.l	d0,d1
+		move.w	\3,d0
+		and.l	#0xf,d0
+		lsl.l	d0,d1
+		set_cc0
+		swap.w	d1
+	.else
+		move.l	\2,d1
+		lsl.l	#1,d1
+		add.l	d0,d1
+		move.w	\3,d0
+		subq.l	#1,d0
+		and.l	#0x1f,d0
+		lsl.l	d0,d1
+		move.l	d1,a1
+		set_cc1
+		move.l	\2,d1
+		sub.l	#32,d0
+		neg.l	d0
+		lsr.l	d0,d1
+		add.l	a1,d1
+	.endif
+.endif
+	move.\4	d1,\2
+	.endm
+	
+	

BaS_codewarrior/firebeeV1/sources/ii_shift.h

@@ -0,0 +1,687 @@
+/*****************************************************************************************/
+// opertionen
+/*****************************************************************************************/
+ii_shift_lset:.macro
+/******************************************************/
+// byt
+/******************************************************/
+//  asx.b #,dx
+	ii_lset_dx	\1,00						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c			
+	ii_lset_dx	\1,01			
+	ii_lset_dx	\1,02			
+	ii_lset_dx	\1,03			
+	ii_lset_dx	\1,04			
+	ii_lset_dx	\1,05			
+	ii_lset_dx	\1,06			
+	ii_lset_dx	\1,07			
+// lsx.b #,dx
+	ii_lset_dxu	\1,08			
+	ii_lset_dxu	\1,09			
+	ii_lset_dxu	\1,0a			
+	ii_lset_dxu	\1,0b			
+	ii_lset_dxu	\1,0c			
+	ii_lset_dxu	\1,0d			
+	ii_lset_dxu	\1,0e			
+	ii_lset_dxu	\1,0f			
+// roxx.b #,dx
+	ii_lset_dx	\1,10			
+	ii_lset_dx	\1,11			
+	ii_lset_dx	\1,12			
+	ii_lset_dx	\1,13			
+	ii_lset_dx	\1,14			
+	ii_lset_dx	\1,15			
+	ii_lset_dx	\1,16			
+	ii_lset_dx	\1,17			
+// rox.b #,dx
+	ii_lset_dx	\1,18			
+	ii_lset_dx	\1,19			
+	ii_lset_dx	\1,1a			
+	ii_lset_dx	\1,1b			
+	ii_lset_dx	\1,1c			
+	ii_lset_dx	\1,1d			
+	ii_lset_dx	\1,1e			
+	ii_lset_dx	\1,1f			
+// asx.b dy,dx
+	ii_lset_dx	\1,20			
+	ii_lset_dx	\1,21			
+	ii_lset_dx	\1,22			
+	ii_lset_dx	\1,23			
+	ii_lset_dx	\1,24			
+	ii_lset_dx	\1,25			
+	ii_lset_dx	\1,26			
+	ii_lset_dx	\1,27			
+// lsx.b dy,dx
+	ii_lset_dx	\1,28			
+	ii_lset_dx	\1,29			
+	ii_lset_dx	\1,2a			
+	ii_lset_dx	\1,2b			
+	ii_lset_dx	\1,2c			
+	ii_lset_dx	\1,2d			
+	ii_lset_dx	\1,2e			
+	ii_lset_dx	\1,2f			
+// roxx.dy,dx
+	ii_lset_dx	\1,30			
+	ii_lset_dx	\1,31			
+	ii_lset_dx	\1,32			
+	ii_lset_dx	\1,33			
+	ii_lset_dx	\1,34			
+	ii_lset_dx	\1,35			
+	ii_lset_dx	\1,36			
+	ii_lset_dx	\1,37			
+// rox.b dy,dx
+	ii_lset_dx	\1,38			
+	ii_lset_dx	\1,39			
+	ii_lset_dx	\1,3a			
+	ii_lset_dx	\1,3b			
+	ii_lset_dx	\1,3c			
+	ii_lset_dx	\1,3d			
+	ii_lset_dx	\1,3e			
+	ii_lset_dx	\1,3f			
+/******************************************************/
+// word
+/******************************************************/
+// asx.w #x,dx
+	ii_lset_dx	\1,40						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c			
+	ii_lset_dx	\1,41			
+	ii_lset_dx	\1,42			
+	ii_lset_dx	\1,43			
+	ii_lset_dx	\1,44			
+	ii_lset_dx	\1,45			
+	ii_lset_dx	\1,46			
+	ii_lset_dx	\1,47			
+// lsx.w #,dx
+	ii_lset_dx	\1,48			
+	ii_lset_dx	\1,49			
+	ii_lset_dx	\1,4a			
+	ii_lset_dx	\1,4b			
+	ii_lset_dx	\1,4c			
+	ii_lset_dx	\1,4d			
+	ii_lset_dx	\1,4e			
+	ii_lset_dx	\1,4f			
+// roxx.w #,dx
+	ii_lset_dx	\1,50			
+	ii_lset_dx	\1,51			
+	ii_lset_dx	\1,52			
+	ii_lset_dx	\1,53			
+	ii_lset_dx	\1,54			
+	ii_lset_dx	\1,55			
+	ii_lset_dx	\1,56			
+	ii_lset_dx	\1,57			
+// rox.w #xdx
+	ii_lset_dx	\1,58			
+	ii_lset_dx	\1,59			
+	ii_lset_dx	\1,5a			
+	ii_lset_dx	\1,5b			
+	ii_lset_dx	\1,5c			
+	ii_lset_dx	\1,5d			
+	ii_lset_dx	\1,5e			
+	ii_lset_dx	\1,5f			
+// asx.w dy,dx
+	ii_lset_dx	\1,60			
+	ii_lset_dx	\1,61			
+	ii_lset_dx	\1,62			
+	ii_lset_dx	\1,63			
+	ii_lset_dx	\1,64			
+	ii_lset_dx	\1,65			
+	ii_lset_dx	\1,66			
+	ii_lset_dx	\1,67			
+// lsx.w dy,dx
+	ii_lset_dx	\1,68			
+	ii_lset_dx	\1,69			
+	ii_lset_dx	\1,6a			
+	ii_lset_dx	\1,6b			
+	ii_lset_dx	\1,6c			
+	ii_lset_dx	\1,6d			
+	ii_lset_dx	\1,6e			
+	ii_lset_dx	\1,6f			
+// roxx.w dy,dx
+	ii_lset_dx	\1,70			
+	ii_lset_dx	\1,71			
+	ii_lset_dx	\1,72			
+	ii_lset_dx	\1,73			
+	ii_lset_dx	\1,74			
+	ii_lset_dx	\1,75			
+	ii_lset_dx	\1,76			
+	ii_lset_dx	\1,77			
+// rox.w dy,dx
+	ii_lset_dx	\1,78			
+	ii_lset_dx	\1,79			
+	ii_lset_dx	\1,7a			
+	ii_lset_dx	\1,7b			
+	ii_lset_dx	\1,7c			
+	ii_lset_dx	\1,7d			
+	ii_lset_dx	\1,7e			
+	ii_lset_dx	\1,7f			
+/******************************************************/
+// long
+/******************************************************/
+// roxx.l #,dx
+	ii_lset_dx	\1,90			
+	ii_lset_dx	\1,91			
+	ii_lset_dx	\1,92			
+	ii_lset_dx	\1,93			
+	ii_lset_dx	\1,94			
+	ii_lset_dx	\1,95			
+	ii_lset_dx	\1,96			
+	ii_lset_dx	\1,97			
+// rox.l #xdx
+	ii_lset_dx	\1,98			
+	ii_lset_dx	\1,99			
+	ii_lset_dx	\1,9a			
+	ii_lset_dx	\1,9b			
+	ii_lset_dx	\1,9c			
+	ii_lset_dx	\1,9d			
+	ii_lset_dx	\1,9e			
+	ii_lset_dx	\1,9f			
+// roxx.l dy,dx
+	ii_lset_dx	\1,b0			
+	ii_lset_dx	\1,b1			
+	ii_lset_dx	\1,b2			
+	ii_lset_dx	\1,b3			
+	ii_lset_dx	\1,b4			
+	ii_lset_dx	\1,b5			
+	ii_lset_dx	\1,b6			
+	ii_lset_dx	\1,b7			
+// rox.l dy,dx
+	ii_lset_dx	\1,b8			
+	ii_lset_dx	\1,b9			
+	ii_lset_dx	\1,ba			
+	ii_lset_dx	\1,bb			
+	ii_lset_dx	\1,bc			
+	ii_lset_dx	\1,bd			
+	ii_lset_dx	\1,be			
+	ii_lset_dx	\1,bf
+//--------------------------------------------------------------------
+// asr.w ea
+	ii_lset_opea	\10,d			// (ax), (ax)+
+	ii_lset_opea	\10,e			// -(ax),d16(ax)
+	ii_lset_opeag	\10,f			// d8(ax,dy)
+	lea	table+0x\10\2f8*4,a0
+	move.l	#ii_0x\10f8,(a0)+		// xxx.w
+	move.l	#ii_0x\10f9,(a0)+		// xxx.l
+// asl.w ea
+	ii_lset_opea	\11,d			// (ax), (ax)+
+	ii_lset_opea	\11,e			// -(ax),d16(ax)
+	ii_lset_opeag	\11,f			// d8(ax,dy)
+	lea	table+0x\11\2f8*4,a0
+	move.l	#ii_0x\11f8,(a0)+		// xxx.w
+	move.l	#ii_0x\11f9,(a0)+		// xxx.l
+// lsr.w ea
+	ii_lset_opea	\12,d			// (ax), (ax)+
+	ii_lset_opea	\12,e			// -(ax),d16(ax)
+	ii_lset_opeag	\12,f			// d8(ax,dy)
+	lea	table+0x\12\2f8*4,a0
+	move.l	#ii_0x\12f8,(a0)+		// xxx.w
+	move.l	#ii_0x\12f9,(a0)+		// xxx.l
+// lsr.w ea
+	ii_lset_opea	\13,d			// (ax), (ax)+
+	ii_lset_opea	\13,e			// -(ax),d16(ax)
+	ii_lset_opeag	\13,f			// d8(ax,dy)
+	lea	table+0x\13\2f8*4,a0
+	move.l	#ii_0x\13f8,(a0)+		// xxx.w
+	move.l	#ii_0x\13f9,(a0)+		// xxx.l
+// roxr.w ea
+	ii_lset_opea	\14,d			// (ax), (ax)+
+	ii_lset_opea	\14,e			// -(ax),d16(ax)
+	ii_lset_opeag	\14,f			// d8(ax,dy)
+	lea	table+0x\14\2f8*4,a0
+	move.l	#ii_0x\14f8,(a0)+		// xxx.w
+	move.l	#ii_0x\14f9,(a0)+		// xxx.l
+// roxl.w ea
+	ii_lset_opea	\15,e			// (ax), (ax)+
+	ii_lset_opea	\15,e			// -(ax),d16(ax)
+	ii_lset_opeag	\15,f			// d8(ax,dy)
+	lea	table+0x\15\2f8*4,a0
+	move.l	#ii_0x\15f8,(a0)+		// xxx.w
+	move.l	#ii_0x\15f9,(a0)+		// xxx.l
+// ror.w ea
+	ii_lset_opea	\16,d			// (ax), (ax)+
+	ii_lset_opea	\16,e			// -(ax),d16(ax)
+	ii_lset_opeag	\16,f			// d8(ax,dy)
+	lea	table+0x\16\2f8*4,a0
+	move.l	#ii_0x\16f8,(a0)+		// xxx.w
+	move.l	#ii_0x\16f9,(a0)+		// xxx.l
+// rol.w ea
+	ii_lset_opea	\17,d			// (ax), (ax)+
+	ii_lset_opea	\17,e			// -(ax),d16(ax)
+	ii_lset_opeag	\17,f			// d8(ax,dy)
+	lea	table+0x\17\2f8*4,a0
+	move.l	#ii_0x\17f8,(a0)+		// xxx.w
+	move.l	#ii_0x\17f9,(a0)+		// xxx.l
+// ende
+.endm;	
+/******************************************************/
+ii_shift_op:.macro	// 1=code 
+//byt-------------------------------
+//asx.b	#x,dx
+	ii_shift_op2agb	0,as,a
+//lsx.b	#x,dx
+	ii_shift_op2aub	0,ls,a
+//roxx.b	#x,dx
+	ii_shift_op2agb	1,rox,a
+//rox.b	#x,dx
+	ii_shift_op2aub	1,ro,a
+//asx.b	dy,dx
+	ii_shift_op2agb	2,as,b
+//lsx.b	dy,dx
+	ii_shift_op2aub	2,ls,b
+//roxx.b dy,dx
+	ii_shift_op2agb	3,rox,b
+//rox.b	dy,dx
+	ii_shift_op2aub	3,ro,b
+// word ---------------------------------------
+//asx.w	#x,dx
+	ii_shift_op2agw	4,as,a
+//lsx.w	#x,dx
+	ii_shift_op2auw	4,ls,a
+//roxx.w	#x,dx
+	ii_shift_op2agw	5,rox,a
+//rox.w	#x,dx
+	ii_shift_op2auw	5,ro,a
+//asx.w	dy,dx
+	ii_shift_op2agw	6,as,b
+//lsx.w	dy,dx
+	ii_shift_op2auw	6,ls,b
+//roxx.w dy,dx
+	ii_shift_op2agw	7,rox,b
+//rox.w	dy,dx
+	ii_shift_op2auw	7,ro,b
+// long ---------------------------------------
+//roxx.l #x,dx
+	ii_shift_op2agw	9,rox,a
+//rox.l	#x,dx
+	ii_shift_op2auw	9,ro,a
+//roxx.l dy,dx
+	ii_shift_op2agw	b,rox,b
+//rox.l	dy,dx
+	ii_shift_op2auw	b,ro,b
+// ea ---------------------------------------
+//asr.w	#1,ea
+	ii_shift_op2ea	0,asr
+//asl.w	#1,ea
+	ii_shift_op2ea	1,asl
+//lsr.w	#1,ea
+	ii_shift_op2ea	2,lsr,
+//lsl.w	#1,ea
+	ii_shift_op2ea	3,lsl
+//roxr.w #1,ea
+	ii_shift_op2ea	4,roxr
+//roxl.w #1,ea
+	ii_shift_op2ea	5,roxl
+//ror.w	#1,ea
+	ii_shift_op2ea	6,ror
+//rol.w	#1,ea
+	ii_shift_op2ea	7,rol
+.endm
+//byt ============================================
+ii_shift_op2agb:.macro	//byt: 1=code 2=operation 3=quick(a) oder register(b)
+	ii_shift_op1\3b	\1,0,\2,d0_off+3(a7)
+	ii_shift_op1\3b	\1,1,\2,d1_off+3(a7)
+	ii_shift_op1\3b	\1,2,\2,d2
+	ii_shift_op1\3b	\1,3,\2,d3
+	ii_shift_op1\3b	\1,4,\2,d4
+	ii_shift_op1\3b	\1,5,\2,d5
+	ii_shift_op1\3b	\1,6,\2,d6
+	ii_shift_op1\3b	\1,7,\2,d7
+.endm
+
+ii_shift_op2aub:.macro	//byt: 1=code 2=operation
+	ii_shift_op1\3b	\1,8,\2,d0_off+3(a7)
+	ii_shift_op1\3b	\1,9,\2,d1_off+3(a7)
+	ii_shift_op1\3b	\1,a,\2,d2
+	ii_shift_op1\3b	\1,b,\2,d3
+	ii_shift_op1\3b	\1,c,\2,d4
+	ii_shift_op1\3b	\1,d,\2,d5
+	ii_shift_op1\3b	\1,e,\2,d6
+	ii_shift_op1\3b	\1,f,\2,d7
+.endm
+
+ii_shift_op1ab:.macro	// z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
+	ii_shift_op0	0\1\2,b,\3r,#8,\4
+	ii_shift_op0	2\1\2,b,\3r,#1,\4
+	ii_shift_op0	4\1\2,b,\3r,#2,\4
+	ii_shift_op0	6\1\2,b,\3r,#3,\4
+	ii_shift_op0	8\1\2,b,\3r,#4,\4
+	ii_shift_op0	a\1\2,b,\3r,#5,\4
+	ii_shift_op0	c\1\2,b,\3r,#6,\4
+	ii_shift_op0	e\1\2,b,\3r,#7,\4
+	ii_shift_op0	1\1\2,b,\3l,#8,\4
+	ii_shift_op0	3\1\2,b,\3l,#1,\4
+	ii_shift_op0	5\1\2,b,\3l,#2,\4
+	ii_shift_op0	7\1\2,b,\3l,#3,\4
+	ii_shift_op0	9\1\2,b,\3l,#4,\4
+	ii_shift_op0	b\1\2,b,\3l,#5,\4
+	ii_shift_op0	d\1\2,b,\3l,#6,\4
+	ii_shift_op0	f\1\2,b,\3l,#7,\4
+.endm
+	
+ii_shift_op1bb:.macro	// z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
+	ii_shift_op0b	0\1\2,b,\3r,d0_off(a7),\4
+	ii_shift_op0b	2\1\2,b,\3r,d1_off(a7),\4
+	ii_shift_op0	4\1\2,b,\3r,d2,\4
+	ii_shift_op0	6\1\2,b,\3r,d3,\4
+	ii_shift_op0	8\1\2,b,\3r,d4,\4
+	ii_shift_op0	a\1\2,b,\3r,d5,\4
+	ii_shift_op0	c\1\2,b,\3r,d6,\4
+	ii_shift_op0	e\1\2,b,\3r,d7,\4
+	ii_shift_op0b	1\1\2,b,\3l,d0_off(a7),\4
+	ii_shift_op0b	3\1\2,b,\3l,d1_off(a7),\4
+	ii_shift_op0	5\1\2,b,\3l,d2,\4
+	ii_shift_op0	7\1\2,b,\3l,d3,\4
+	ii_shift_op0	9\1\2,b,\3l,d4,\4
+	ii_shift_op0	b\1\2,b,\3l,d5,\4
+	ii_shift_op0	d\1\2,b,\3l,d6,\4
+	ii_shift_op0	f\1\2,b,\3l,d7,\4
+.endm
+// word ---------------------------------------
+ii_shift_op2agw:.macro	//byt: 1=code 2=operation 3=quick(a) oder register(b)
+	ii_shift_op1\3w	\1,0,\2,d0_off+2(a7)
+	ii_shift_op1\3w	\1,1,\2,d1_off+2(a7)
+	ii_shift_op1\3w	\1,2,\2,d2
+	ii_shift_op1\3w	\1,3,\2,d3
+	ii_shift_op1\3w	\1,4,\2,d4
+	ii_shift_op1\3w	\1,5,\2,d5
+	ii_shift_op1\3w	\1,6,\2,d6
+	ii_shift_op1\3w	\1,7,\2,d7
+.endm
+
+ii_shift_op2auw:.macro	//byt: 1=code 2=operation
+	ii_shift_op1\3w	\1,8,\2,d0_off+2(a7)
+	ii_shift_op1\3w	\1,9,\2,d1_off+2(a7)
+	ii_shift_op1\3w	\1,a,\2,d2
+	ii_shift_op1\3w	\1,b,\2,d3
+	ii_shift_op1\3w	\1,c,\2,d4
+	ii_shift_op1\3w	\1,d,\2,d5
+	ii_shift_op1\3w	\1,e,\2,d6
+	ii_shift_op1\3w	\1,f,\2,d7
+.endm
+
+ii_shift_op1aw:.macro	// z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
+	ii_shift_op0	0\1\2,w,\3r,#8,\4
+	ii_shift_op0	2\1\2,w,\3r,#1,\4
+	ii_shift_op0	4\1\2,w,\3r,#2,\4
+	ii_shift_op0	6\1\2,w,\3r,#3,\4
+	ii_shift_op0	8\1\2,w,\3r,#4,\4
+	ii_shift_op0	a\1\2,w,\3r,#5,\4
+	ii_shift_op0	c\1\2,w,\3r,#6,\4
+	ii_shift_op0	e\1\2,w,\3r,#7,\4
+	ii_shift_op0	1\1\2,w,\3l,#8,\4
+	ii_shift_op0	3\1\2,w,\3l,#1,\4
+	ii_shift_op0	5\1\2,w,\3l,#2,\4
+	ii_shift_op0	7\1\2,w,\3l,#3,\4
+	ii_shift_op0	9\1\2,w,\3l,#4,\4
+	ii_shift_op0	b\1\2,w,\3l,#5,\4
+	ii_shift_op0	d\1\2,w,\3l,#6,\4
+	ii_shift_op0	f\1\2,w,\3l,#7,\4
+.endm
+	
+ii_shift_op1bw:.macro	// z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
+	ii_shift_op0b	0\1\2,w,\3r,d0_off(a7),\4
+	ii_shift_op0b	2\1\2,w,\3r,d1_off(a7),\4
+	ii_shift_op0	4\1\2,w,\3r,d2,\4
+	ii_shift_op0	6\1\2,w,\3r,d3,\4
+	ii_shift_op0	8\1\2,w,\3r,d4,\4
+	ii_shift_op0	a\1\2,w,\3r,d5,\4
+	ii_shift_op0	c\1\2,w,\3r,d6,\4
+	ii_shift_op0	e\1\2,w,\3r,d7,\4
+	ii_shift_op0b	1\1\2,w,\3l,d0_off(a7),\4
+	ii_shift_op0b	3\1\2,w,\3l,d1_off(a7),\4
+	ii_shift_op0	5\1\2,w,\3l,d2,\4
+	ii_shift_op0	7\1\2,w,\3l,d3,\4
+	ii_shift_op0	9\1\2,w,\3l,d4,\4
+	ii_shift_op0	b\1\2,w,\3l,d5,\4
+	ii_shift_op0	d\1\2,w,\3l,d6,\4
+	ii_shift_op0	f\1\2,w,\3l,d7,\4
+.endm
+// long ---------------------------------------
+ii_shift_op2agl:.macro	//byt: 1=code 2=operation 3=quick(a) oder register(b)
+	ii_shift_op1\3l	\1,0,\2,d0_off(a7)
+	ii_shift_op1\3l	\1,1,\2,d1_off(a7)
+	ii_shift_op1\3l	\1,2,\2,d2
+	ii_shift_op1\3l	\1,3,\2,d3
+	ii_shift_op1\3l	\1,4,\2,d4
+	ii_shift_op1\3l	\1,5,\2,d5
+	ii_shift_op1\3l	\1,6,\2,d6
+	ii_shift_op1\3l	\1,7,\2,d7
+.endm
+
+ii_shift_op2aul:.macro	//byt: 1=code 2=operation
+	ii_shift_op1\3l	\1,8,\2,d0_off(a7)
+	ii_shift_op1\3l	\1,9,\2,d1_off(a7)
+	ii_shift_op1\3l	\1,a,\2,d2
+	ii_shift_op1\3l	\1,b,\2,d3
+	ii_shift_op1\3l	\1,c,\2,d4
+	ii_shift_op1\3l	\1,d,\2,d5
+	ii_shift_op1\3l	\1,e,\2,d6
+	ii_shift_op1\3l	\1,f,\2,d7
+.endm
+
+ii_shift_op1al:.macro	// z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
+	ii_shift_op0	0\1\2,l,\3r,#8,\4
+	ii_shift_op0	2\1\2,l,\3r,#1,\4
+	ii_shift_op0	4\1\2,l,\3r,#2,\4
+	ii_shift_op0	6\1\2,l,\3r,#3,\4
+	ii_shift_op0	8\1\2,l,\3r,#4,\4
+	ii_shift_op0	a\1\2,l,\3r,#5,\4
+	ii_shift_op0	c\1\2,l,\3r,#6,\4
+	ii_shift_op0	e\1\2,l,\3r,#7,\4
+	ii_shift_op0	1\1\2,l,\3l,#8,\4
+	ii_shift_op0	3\1\2,l,\3l,#1,\4
+	ii_shift_op0	5\1\2,l,\3l,#2,\4
+	ii_shift_op0	7\1\2,l,\3l,#3,\4
+	ii_shift_op0	9\1\2,l,\3l,#4,\4
+	ii_shift_op0	b\1\2,l,\3l,#5,\4
+	ii_shift_op0	d\1\2,l,\3l,#6,\4
+	ii_shift_op0	f\1\2,l,\3l,#7,\4
+.endm
+	
+ii_shift_op1bl:.macro	// z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
+	ii_shift_op0b	0\1\2,l,\3r,d0_off(a7),\4
+	ii_shift_op0b	2\1\2,l,\3r,d1_off(a7),\4
+	ii_shift_op0	4\1\2,l,\3r,d2,\4
+	ii_shift_op0	6\1\2,l,\3r,d3,\4
+	ii_shift_op0	8\1\2,l,\3r,d4,\4
+	ii_shift_op0	a\1\2,l,\3r,d5,\4
+	ii_shift_op0	c\1\2,l,\3r,d6,\4
+	ii_shift_op0	e\1\2,l,\3r,d7,\4
+	ii_shift_op0b	1\1\2,l,\3l,d0_off(a7),\4
+	ii_shift_op0b	3\1\2,l,\3l,d1_off(a7),\4
+	ii_shift_op0	5\1\2,l,\3l,d2,\4
+	ii_shift_op0	7\1\2,l,\3l,d3,\4
+	ii_shift_op0	9\1\2,l,\3l,d4,\4
+	ii_shift_op0	b\1\2,l,\3l,d5,\4
+	ii_shift_op0	d\1\2,l,\3l,d6,\4
+	ii_shift_op0	f\1\2,l,\3l,d7,\4
+.endm
+// .word ea ============================================
+ii_shift_op2ea:.macro		//1=code 2.ziffer 2=shiftart
+// (a0) bis (a7) ----------------------------
+ii_0xe\1d0:				 
+	move.l	a0_off(a7),a1
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1d1:				 
+	move.l	a1_off(a7),a1
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1d2:	
+	ii_shift_typ	w,\2,#1,(a2),(a2).
+ii_0xe\1d3:	
+	ii_shift_typ	w,\2,#1,(a3),(a3).
+ii_0xe\1d4:	
+	ii_shift_typ	w,\2,#1,(a4),(a4).
+ii_0xe\1d5:	
+	ii_shift_typ	w,\2,#1,(a5),(a5).
+ii_0xe\1d6:	
+	ii_shift_typ	w,\2,#1,(a6),(a6).
+ii_0xe\1d7:	
+	move.l	usp,a1
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+// (a0)+ bis (a7)+ -----------------------------
+ii_0xe\1d8:				 
+	move.l	a0_off(a7),a1
+	addq.l	#2,a0_off(a7)
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1d9:				 
+	move.l	a1_off(a7),a1
+	addq.l	#2,a0_off(a7)
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1da:	
+	ii_shift_typ	w,\2,#1,(a2),(a2)+.
+ii_0xe\1db:	
+	ii_shift_typ	w,\2,#1,(a3),(a3)+
+ii_0xe\1dc:	
+	ii_shift_typ	w,\2,#1,(a4),(a4)+
+ii_0xe\1dd:	
+	ii_shift_typ	w,\2,#1,(a5),(a5)+
+ii_0xe\1de:	
+	ii_shift_typ	w,\2,#1,(a6),(a6)+
+ii_0xe\1df:	
+	move.l	usp,a1
+	addq.l	#2,a1
+	move.l	a1,usp
+	subq.l	#2,a1
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+// -(a0) bis -(a7) -----------------------------
+ii_0xe\1e0:				 
+	move.l	a0_off(a7),a1
+	subq.l	#2,a1
+	move.l	a1,a0_off(a7)
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1e1:				 
+	move.l	a1_off(a7),a1
+	subq.l	#2,a1
+	move.l	a1,a1_off(a7)
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1e2:	
+	ii_shift_typ	w,\2,#1,-(a2),(a2).
+ii_0xe\1e3:	
+	ii_shift_typ	w,\2,#1,-(a3),(a3)
+ii_0xe\1e4:	
+	ii_shift_typ	w,\2,#1,-(a4),(a4)
+ii_0xe\1e5:	
+	ii_shift_typ	w,\2,#1,-(a5),(a5)
+ii_0xe\1e6:	
+	ii_shift_typ	w,\2,#1,-(a6),(a6)
+ii_0xe\1e7:	
+	move.l	usp,a1
+	subq.l	#2,a1
+	move.l	a1,usp
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+// d16(a0) bis d16(a7) -----------------------------
+ii_0xe\1e8:	
+	move.w	(a0)+,a1			 
+	add.l	a0_off(a7),a1
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1e9:				 
+	move.w	(a0)+,a1			 
+	add.l	a1_off(a7),a1
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1ea:	
+	move.w	(a0)+,a1			 
+	add.l	a2,a1
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1eb:	
+	move.w	(a0)+,a1			 
+	add.l	a3,a1
+	ii_shift_typ	w,\2,#1,(a1),(a1)
+ii_0xe\1ec:	
+	move.w	(a0)+,a1			 
+	add.l	a4,a1
+	ii_shift_typ	w,\2,#1,(a1),(a1)
+ii_0xe\1ed:	
+	move.w	(a0)+,a1			 
+	add.l	a5,a1
+	ii_shift_typ	w,\2,#1,(a1),(a1)
+ii_0xe\1ee:	
+	move.w	(a0)+,a1			 
+	add.l	a6,a1
+	ii_shift_typ	w,\2,#1,(a1),(a1)
+ii_0xe\1ef:	
+	mvs.w	(a0)+,d0
+	move.l	usp,a1			 
+	add.l	d0,a1
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+// d8(a0,dy) bis d8(a7,dy) -----------------------------
+ii_0xe\1f0:	
+	move.l	a0_off(a0),a1			 
+	jsr	ewf
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1f1:				 
+	move.l	a1_off(a0),a1			 
+	jsr	ewf
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1f2:	
+	move.l	a2,a1			 
+	jsr	ewf
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1f3:	
+	move.l	a3,a1			 
+	jsr	ewf
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1f4:	
+	move.l	a4,a1			 
+	jsr	ewf
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1f5:	
+	move.l	a5,a1			 
+	jsr	ewf
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1f6:	
+	move.l	a6,a1			 
+	jsr	ewf
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1f7:	
+	move.l	usp,a1			 
+	jsr	ewf
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+// xxx.w xxx.l
+ii_0xe\1f8:	
+	move.w	(a0)+,a1			 
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1f9:				 
+	move.l	(a0)+,a1			 
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+.endm
+//============================================================================
+//subroutine
+//------------------------------
+ii_shift_op0:.macro	// shift: 1=code 2=size 3=shift art 4=shift wert 5=ea
+ii_0xe\1:
+	ii_shift_typ	\2,\3,\4,\5,\5
+.endm	
+
+ii_shift_op0b:.macro	// shift wert nach d0 holen: 1=code 2=size 3=shift art 4=shift wert 5=ea
+ii_0xe\1:
+	move.l	\4,d0
+	ii_shift_typ	\2,\3,d0,\5,\5
+.endm	
+
+ii_shift_typ:.macro	//1=size 2=shift art 3=shift wert 4=source 5=dest
+#ifdef	halten
+	halt
+#endif
+.ifc	asr,\2
+	mvs.\1	\4,d1
+.else
+	mvz.\1	\4,d1
+.endif
+.ifc	roxr,\2
+	nop
+.else
+	.ifc	roxl,\2
+		nop
+	.else
+		.ifc	ror,\2
+			nop
+		.else
+			.ifc	rol,\2
+				nop
+			.else
+				\2.l	\3,d1
+			.endif
+		.endif
+	.endif
+.endif
+	set_cc0
+	move.\1	d1,\5
+	ii_end
+.endm

BaS_codewarrior/firebeeV1/sources/ii_sub.h

@@ -0,0 +1,584 @@
+//--------------------------------------------------------------------
+// sub
+//--------------------------------------------------------------------
+/*****************************************************************************************/
+//--------------------------------------------------------------------
+// byt
+//--------------------------------------------------------------------
+//--------------------------------------------------------------------
+// sub.b	#im,dx
+//--------------------------------------------------------------------
+subbir_macro:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.w		(a0)+,d0
+	extb.l		d0
+	mvs.b		\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.b		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	ea,dx
+//--------------------------------------------------------------------
+subdd:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	ea(l)->dy(w),dx z.B. f<>r USP
+//--------------------------------------------------------------------
+subddd:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		a1,d0
+	mvs.\3		\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	(ea)->dy,dx
+//--------------------------------------------------------------------
+subdda:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	ea->ay,(ay)+,dx
+//--------------------------------------------------------------------
+subddai:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		(a1)+,d0
+	move.l		a1,\1
+	mvs.\3		\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	ea->ay,-(ay),dx
+//--------------------------------------------------------------------
+subddad:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		-(a1),d0
+	move.l		a1,\1
+	mvs.\3		\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	d16(ay),dx
+//--------------------------------------------------------------------
+subd16ad:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		\1,a1
+	mvs.w		(a0)+,d0
+	add.l		d0,a1
+	mvs.\3		(a1),d0		
+	mvs.\3		\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	d8(ay,dy),dx
+//--------------------------------------------------------------------
+subd8ad:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		\1,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d0
+	move.l		\2,d1
+.else
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+.endif
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	xxx.w,dx
+//--------------------------------------------------------------------
+subxwd:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.w		(a0)+,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	xxx.l,dx
+//--------------------------------------------------------------------
+subxld:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		(a0)+,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	d16(pc),dx
+//--------------------------------------------------------------------
+subd16pcd:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		a0,a1
+	mvs.w		(a0)+,d0
+	add.l		d0,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	d8(pc,dy),dx
+//--------------------------------------------------------------------
+subd8pcd:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		a0,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d0
+	move.l		\2,d1
+.else
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+.endif
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+//  sub dy,ea
+//--------------------------------------------------------------------
+//--------------------------------------------------------------------
+// // sub	(ea)->dy,dx
+//--------------------------------------------------------------------
+subeda:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		(a1),d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	dx,ea->ay,(ay)+
+//--------------------------------------------------------------------
+subedai:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		(a1),d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)+
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	dx,ea->ay,(ay)+
+//--------------------------------------------------------------------
+subedaid:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2+
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	dx,ea->ay,-(ay)
+//--------------------------------------------------------------------
+subedad:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		-(a1),d1
+	move.l		a1,\2
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	dx,ea->ay,-(ay)
+//--------------------------------------------------------------------
+subedadd:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		-\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	dx,d16(ay)
+//--------------------------------------------------------------------
+sube16ad:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.w		(a0)+,d1
+	add.l		d1,a1
+	mvs.\3		(a1),d1		
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	dx,d8(ay,dy)
+//--------------------------------------------------------------------
+sube8ad:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		\2,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d1
+	move.l		\1,d0
+.else
+	mvs.\3		(a1),d1
+	mvs.\3		\1,d0
+.endif
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	dx,xxx.w
+//--------------------------------------------------------------------
+subxwe:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.w		(a0)+,a1
+	mvs.\3		(a1),d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	dx,xxx.l
+//--------------------------------------------------------------------
+subxle:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		(a0)+,a1
+	mvs.\3		(a1),d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+/******************************************************/
+// adress register
+/******************************************************/
+//--------------------------------------------------------------------
+// // suba.w	ea,ax
+//--------------------------------------------------------------------
+subaw:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		a0,pc_off(a7)			// pc auf next
+	movem.l		(a7),d0/d1/a0/a1		// register zurp<72>ck
+	mvs.w		\1,d0
+	suba.l		d0,\2
+	move.l		d0_off(a7),d0
+	lea			ii_ss(a7),a7			// stack erh<72>hen
+	rte
+	.endm;
+//--------------------------------------------------------------------
+// sub.w ea,usp
+//--------------------------------------------------------------------
+subawa7:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	mvs.w		\1,d0
+	move.l		usp,a1
+	sub.l		d0,a1
+	move.l		a1,usp
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // suba.w	usp?,ax
+//--------------------------------------------------------------------
+subawu:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		a0,pc_off(a7)			// pc auf next
+	movem.l		(a7),d0/d1/a0/a1		// register zurp<72>ck
+	move.l		a7,_a7_save
+	move.l		usp,a7
+	move.l		\1,d0
+	suba.l		d0,\2
+	move.l		a7,usp
+	move.l		_a7_save,a7
+	move.l		d0_off(a7),d0
+	lea			ii_ss(a7),a7			// stack erh<72>hen
+	rte
+	.endm;
+//--------------------------------------------------------------------
+// // suba.w	usp?,usp
+//--------------------------------------------------------------------
+subawua7:.macro
+	subawu		\1,\2
+	.endm;
+//--------------------------------------------------------------------
+// // suba.w	d16(ay),ax
+//--------------------------------------------------------------------
+subawd16a:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		\1,a1
+	mvs.w		(a0)+,d0
+	adda.l		d0,a1
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	sub.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // suba.w	d8(ay,dy),ax
+//--------------------------------------------------------------------
+subawd8a:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		\1,a1
+	jsr			ewf
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	sub.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // suba.w	xxx.w,ax
+//--------------------------------------------------------------------
+subawxwax:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.w		(a0)+,a1
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	suba.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // suba.w	xxx.l,ax
+//--------------------------------------------------------------------
+subawxlax:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		(a0)+,a1
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	suba.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // suba.w	d16(pc),ax
+//--------------------------------------------------------------------
+subawd16pcax:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.w		(a0)+,a1
+	adda.l		a0,a1
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	suba.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // suba.w	d8(pc,dy),ax
+//--------------------------------------------------------------------
+subawd8pcax:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		a0,a1
+	jsr			ewf
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	sub.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // suba.w	#im,ax
+//--------------------------------------------------------------------
+subawim:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	mvs.w		\1,d0
+	move.l		\2,a1
+	sub.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // suba.l	d8(ay,dy),ax
+//--------------------------------------------------------------------
+subald8a:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		\1,a1
+	jsr			ewf
+	move.l		(a1),d0
+	move.l		\2,a1
+	sub.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // suba.l	d8(pc,dy),ax
+//--------------------------------------------------------------------
+subakd8pcax:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		a0,a1
+	jsr			ewf
+	move.l		(a1),d0
+	move.l		\2,a1
+	sub.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//*****************************************************************************************
+// subx 
+//*****************************************************************************************
+//--------------------------------------------------------------------
+// // subx	dy,dx
+//--------------------------------------------------------------------
+subdx:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.b		sr_off+1(a7),d0			//ccr holen
+	move		d0,ccr					//setzen		
+	mvs.\3		\2,d0
+	mvs.\3		\1,d1
+	subx.l		d0,d1
+	set_cc0
+	move.\3		d1,\1
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // subx	-(ay),-(ax)
+//--------------------------------------------------------------------
+subdax:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.b		sr_off+1(a7),d0			//ccr holen
+	move		d0,ccr					//setzen		
+	move.l		\1,a1
+.ifc	\3,l
+	move.l		-(a1),d0
+.else
+	mvs.\3		-(a1),d0
+.endif
+	move.l		\2,a1
+.ifc	\3,l
+	move.l		-(a1),d0
+.else
+	mvs.\3		-(a1),d1
+.endif
+	subx.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------

BaS_codewarrior/firebeeV1/sources/illegal_instruction.s

@@ -0,0 +1,328 @@
+.public 	_illegal_instruction
+.public 	_illegal_table_make
+
+.include 	"startcf.h"
+.include	"ii_macro.h"
+.include	"ii_func.h"
+.include	"ii_op.h"
+.include	"ii_opc.h"
+.include	"ii_add.h"
+.include	"ii_sub.h"
+.include	"ii_or.h"
+.include	"ii_and.h"
+.include	"ii_dbcc.h"
+.include	"ii_shd.h"
+.include	"ii_movem.h"
+.include	"ii_lea.h"
+.include	"ii_shift.h"
+.include	"ii_exg.h"
+.include	"ii_movep.h"
+.include	"ii_ewf.h"
+.include	"ii_move.h"
+
+.extern		_ii_shift_vec
+.extern		ewf
+
+/*******************************************************/
+.text
+ii_error:
+	nop
+	halt
+	nop
+	nop
+	
+_illegal_instruction:
+#ifdef	ii_on
+	move.w		#0x2700,sr
+	lea			-ii_ss(a7),a7
+	movem.l		d0/d1/a0/a1,(a7)
+	move.l		pc_off(a7),a0			// pc
+	mvz.w		(a0)+,d0				// code
+	lea			table,a1
+	move.l		0(a1,d0*4),a1
+	jmp			(a1)
+/*************************************************************************************************/
+#endif
+_illegal_table_make:
+#ifdef	ii_on
+	lea			table,a0
+	moveq		#0,d0
+_itm_loop:
+	move.l		#ii_error,(a0)+
+	addq.l		#1,d0
+	cmp.l		#0xF000,d0
+	bne			_itm_loop
+//-------------------------------------------------------------------------
+	ii_ewf_lset		// diverse fehlende adressierungn
+//-------------------------------------------------------------------------
+// 0x0000 
+// ori
+	ii_lset_op	00
+// andi
+	ii_lset_op	02
+// subi
+	ii_lset_op	04
+// addi
+	ii_lset_op	06
+// eori
+	ii_lset_op	0a
+// cmpi
+	ii_lset_op	0c
+// movep
+	ii_movep_lset	
+//-------------------------------------------------------------------------
+// 0x1000 move.b
+// 0x2000 move.l
+// 0x3000 move.w
+	ii_move_lset
+//-------------------------------------------------------------------------
+// 0x4000 
+//-------------------------------------------------------------------------
+// negx
+	ii_lset_op	40
+// neg
+	ii_lset_op	44
+// not
+	ii_lset_op	46
+//---------------------------------------------------------------------------------------------
+// lea	d8(ax,dy.w),az; d8(pc,dy.w),az
+//-------------------------------------------------------------------
+	ii_lea_lset
+//-------------------------------------------------------------------
+// movem 
+//-------------------------------------------------------------------
+	ii_movem_lset
+//-------------------------------------------------------------------------
+// 0x5000
+//-------------------------------------------------------------------------
+// addq, subq
+	ii_lset_op	50
+	ii_lset_op	51
+	ii_lset_op	52
+	ii_lset_op	53
+	ii_lset_op	54
+	ii_lset_op	55
+	ii_lset_op	56
+	ii_lset_op	57
+	ii_lset_op	58
+	ii_lset_op	59
+	ii_lset_op	5a
+	ii_lset_op	5b
+	ii_lset_op	5c
+	ii_lset_op	5d
+	ii_lset_op	5e
+	ii_lset_op	5f
+// dbcc
+	ii_lset_dbcc
+// scc
+	ii_lset_opc	50
+	ii_lset_opc	51
+	ii_lset_opc	52
+	ii_lset_opc	53
+	ii_lset_opc	54
+	ii_lset_opc	55
+	ii_lset_opc	56
+	ii_lset_opc	57
+	ii_lset_opc	58
+	ii_lset_opc	59
+	ii_lset_opc	5a
+	ii_lset_opc	5b
+	ii_lset_opc	5c
+	ii_lset_opc	5d
+	ii_lset_opc	5e
+	ii_lset_opc	5f
+//-------------------------------------------------------------------------
+// 0x8000		or
+//-------------------------------------------------------------------------
+	ii_lset_func	8
+//-------------------------------------------------------------------------
+// 0x9000		sub
+//-------------------------------------------------------------------------
+	ii_lset_func	9
+//-------------------------------------------------------------------------
+// 0xb000		
+//-------------------------------------------------------------------------
+// eor
+	ii_lset_op	b1
+	ii_lset_op	b3
+	ii_lset_op	b5
+	ii_lset_op	b7
+	ii_lset_op	b9
+	ii_lset_op	bb
+	ii_lset_op	bd
+	ii_lset_op	bf
+//-------------------------------------------------------------------------
+// 0xc000		
+//-------------------------------------------------------------------------
+// and
+	ii_lset_func	c
+// exg
+	ii_exg_lset
+//-------------------------------------------------------------------------
+// 0xd000		add
+//-------------------------------------------------------------------------
+	ii_lset_func	d
+//-------------------------------------------------------------------------
+// 0xe000
+//-------------------------------------------------------------------------
+// shift register
+	ii_shift_lset	e	
+//-------------------------------------------------
+// differenz zwischen orginal und gemoved korrigieren
+	lea			ii_error(pc),a1
+	move.l		a1,d1
+	sub.l		#ii_error,d1
+	lea			table,a0
+	moveq		#0,d0
+_itkorr_loop:
+	add.l		d1,(a0)+
+	addq.l		#1,d0
+	cmp.l		#0xF000,d0
+	bne			_itkorr_loop
+#endif
+	rts
+#ifdef	ii_on
+//***********************************************************************************/
+//-------------------------------------------------------------------------
+		ii_ewf_func		// diverse fehlende adressierungn
+//-------------------------------------------------------------------------
+//---------------------------------------------------------------------------------------------
+// 0x0000
+//--------------------------------------------------------------------
+// ori 00
+		ii_op		00,or.l,i
+//--------------------------------------------------------------------
+// andi 02
+		ii_op		02,and.l,i
+//--------------------------------------------------------------------
+// subi 04
+		ii_op		04,and.l,i
+//--------------------------------------------------------------------
+// addi 06
+		ii_op		06,add.l,i
+//--------------------------------------------------------------------
+// eori 0a
+		ii_op		0a,eor.l,i
+//--------------------------------------------------------------------
+// cmpi 0c
+		ii_op		0c,cmp.l,i
+//--------------------------------------------------------------------
+// movep
+	ii_movep_func	
+///---------------------------------------------------------------------------------------------
+// 0x1000 move.b
+// 0x2000 move.l	
+// 0x3000 move.w
+		ii_move_op
+//---------------------------------------------------------------------------------------------
+// 0x4000
+//---------------------------------------------------------------------------------------------
+// neg 0x40..
+		ii_op		40,negx.l,n
+//---------------------------------------------------------------------------------------------
+// neg 0x44..
+		ii_op		44,neg.l,n
+//---------------------------------------------------------------------------------------------
+// not 0x46..
+		ii_op		46,not.l,n
+//---------------------------------------------------------------------------------------------
+// lea	d8(ax,dy.w),az; d8(pc,dy.w),az
+//-------------------------------------------------------------------
+		ii_lea_func
+//-------------------------------------------------------------------
+// movem
+//--------------------------------------------------------------------
+ii_movem_func
+//---------------------------------------------------------------------------------------------
+// 0x5000
+//---------------------------------------------------------------------------------------------
+//dbcc
+		ii_dbcc_func
+// addq 0x5...
+		ii_op		50,addq.l #8,q
+		ii_op		52,addq.l #1,q
+		ii_op		54,addq.l #2,q
+		ii_op		56,addq.l #3,q
+		ii_op		58,addq.l #4,q
+		ii_op		5a,addq.l #5,q
+		ii_op		5c,addq.l #6,q
+		ii_op		5e,addq.l #7,q
+//---------------------------------------------------------------------------------------------
+// subq 0x5...
+		ii_op		51,subq.l #8,q
+		ii_op		53,subq.l #1,q
+		ii_op		55,subq.l #2,q
+		ii_op		57,subq.l #3,q
+		ii_op		59,subq.l #4,q
+		ii_op		5b,subq.l #5,q
+		ii_op		5d,subq.l #6,q
+		ii_op		5f,subq.l #7,q
+//---------------------------------------------------------------------------------------------
+// 0x5... scc
+		ii_opc		50,st,c
+		ii_opc		51,sf,c
+		ii_opc		52,shi,c
+		ii_opc		53,sls,c
+		ii_opc		54,scc,c
+		ii_opc		55,scs,c
+		ii_opc		56,sne,c
+		ii_opc		57,seq,c
+		ii_opc		58,svc,c
+		ii_opc		59,svs,c
+		ii_opc		5a,spl,c
+		ii_opc		5b,smi,c
+		ii_opc		5c,sge,c
+		ii_opc		5d,slt,c
+		ii_opc		5e,sgt,c
+		ii_opc		5f,sle,c
+//---------------------------------------------------------------------------------------------
+// 0x6000
+//--------------------------------------------------------------------
+//---------------------------------------------------------------------------------------------
+// 0x7000
+//--------------------------------------------------------------------
+//---------------------------------------------------------------------------------------------
+// 0x8000
+//---------------------------------------------------------------------------------------------
+// or
+		ii_func		8,or
+//---------------------------------------------------------------------------------------------
+// 0x9000
+//---------------------------------------------------------------------------------------------
+// sub
+		ii_func		9,sub
+//---------------------------------------------------------------------------------------------
+// 0xa000
+//--------------------------------------------------------------------
+//---------------------------------------------------------------------------------------------
+// 0xb000
+//---------------------------------------------------------------------------------------------
+// eor
+		ii_op		b1,eor.l d0,q
+		ii_op		b3,eor.l d1,q
+		ii_op		b5,eor.l d2,q
+		ii_op		b7,eor.l d3,q
+		ii_op		b9,eor.l d4,q
+		ii_op		bb,eor.l d5,q
+		ii_op		bd,eor.l d6,q
+		ii_op		bf,eor.l d7,q
+//---------------------------------------------------------------------------------------------
+// 0xc000
+//---------------------------------------------------------------------------------------------
+// and
+		ii_func		c,and
+// exg
+		ii_exg_func
+//---------------------------------------------------------------------------------------------
+// 0xd000
+//---------------------------------------------------------------------------------------------
+// add
+		ii_func		d,add
+//---------------------------------------------------------------------------------------------
+// 0xe000 shift
+//--------------------------------------------------------------------
+		ii_shift_op
+//--------------------------------------------------------------------
+// 0xf000
+//--------------------------------------------------------------------
+#endif

BaS_codewarrior/firebeeV1/sources/last.c

@@ -0,0 +1,11 @@
+// letztes file der liste
+// wichtig als endpunkt des kopierens
+
+void copy_end(void)
+{
+	asm
+	{
+copy_end:
+		nop
+	}
+}

BaS_codewarrior/firebeeV1/sources/last.s

@@ -0,0 +1,10 @@
+// letztes file der liste
+// wichtig als endpunkt des kopierens
+
+.global	copy_end
+
+.text
+	nop
+copy_end:
+	nop
+.asciz	'ende copy';

BaS_codewarrior/firebeeV1/sources/macro.h

@@ -0,0 +1,10 @@
+/*******************************************************/
+// allgemeine macros
+/*******************************************************/
+.text
+wait_pll: .macro
+wait1_pll\@:
+		tst.w	(a1)
+		bmi		wait1_pll\@
+		rts
+.endm

BaS_codewarrior/firebeeV1/sources/mmu.s

@@ -1,30 +1,29 @@
-/*
- * INIT ACR and MMU
- */
+/********************************************************************/
+	/* INIT ACR und MMU /*
+/********************************************************************/
 
-#include "startcf.h"
+.include "startcf.h"
 
-	.extern _rt_vbr
-	.extern _rt_cacr
-	.extern _rt_asid
-	.extern _rt_acr0
-	.extern _rt_acr1
-	.extern _rt_acr2
-	.extern _rt_acr3
-	.extern _rt_mmubar
-	.extern ___MMUBAR
-	.extern cpusha
-	.extern _video_tlb
-	.extern _video_sbt
-	.extern __TOS
+.extern _rt_vbr
+.extern _rt_cacr
+.extern _rt_asid
+.extern _rt_acr0
+.extern _rt_acr1
+.extern _rt_acr2
+.extern _rt_acr3
+.extern _rt_mmubar
+.extern ___MMUBAR
+.extern cpusha
+.extern _video_tlb
+.extern _video_sbt
 
 /* Register read/write macros */
-#define MCF_MMU_MMUCR	__MMUBAR
-#define MCF_MMU_MMUOR	__MMUBAR+0x04
-#define MCF_MMU_MMUSR	__MMUBAR+0x08
-#define MCF_MMU_MMUAR	__MMUBAR+0x10
-#define MCF_MMU_MMUTR	__MMUBAR+0x14
-#define MCF_MMU_MMUDR	__MMUBAR+0x18
+#define MCF_MMU_MMUCR            			___MMUBAR
+#define MCF_MMU_MMUOR                       ___MMUBAR+0x04
+#define MCF_MMU_MMUSR                       ___MMUBAR+0x08
+#define MCF_MMU_MMUAR                       ___MMUBAR+0x10
+#define MCF_MMU_MMUTR                       ___MMUBAR+0x14
+#define MCF_MMU_MMUDR                       ___MMUBAR+0x18
 
 
 /* Bit definitions and macros for MCF_MMU_MMUCR */
@@ -75,17 +74,17 @@
 #define	 cb_mmudr	(MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(01)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X)
 #define	 nc_mmudr	(MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(10)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X)
 
-		.global _mmu_init
-		.global _mmutr_miss
+.public _mmu_init
+.public _mmutr_miss
 
 .text
 _mmu_init:
-		move.l	d3,-(sp)			// Backup registers
-		move.l	d2,-(sp)
-
  		clr.l	d0
 		movec	d0,ASID				// ASID allways 0
 		move.l	d0,_rt_asid			// sichern
+		movec	d0,cacr				// cache aus
+		move.l	d0,_rt_cacr			// sichern
+		nop
 		
 		move.l	#0xC03FC040,d0		// data r/w precise  c000'0000-ffff'ffff
 		movec	d0,ACR0
@@ -103,7 +102,7 @@ _mmu_init:
 		movec	d0,ACR3
 		move.l	d0,_rt_acr3			// sichern
 
-		move.l	#__MMUBAR+1,d0
+		move.l	#___MMUBAR+1,d0	
 		movec	d0,MMUBAR			//mmubar setzen
 		move.l	d0,_rt_mmubar		// sichern
 		
@@ -134,12 +133,12 @@ _mmu_init:
 		move.l	d3,MCF_MMU_MMUOR						// MMU update instruction  
 		
 		move.l	#0x2000,d0
-		move.l	d0,_video_tlb							// set page as video page
-  		clr.l	_video_sbt								// clear time
+		move.l	d0,_video_tlb							// setze page als video page
+  		clr.l	_video_sbt			// zeit löschen
 //-------------------------------------------------------------------------------------
-// Make the TOS (in SDRAM) read-only
- 		move.l	#__TOS+std_mmutr,d0
-		move.l	#__TOS+cb_mmudr+MCF_MMU_MMUDR_LK,d1
+// 00e0'0000 locked		
+ 		move.l	#0x00e00000|std_mmutr,d0
+		move.l	#0x00e00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1						 
 		move.l	d0,MCF_MMU_MMUTR		
 		move.l	d1,MCF_MMU_MMUDR
  		move.l	d2,MCF_MMU_MMUOR						// setzen read only ?????? noch nicht
@@ -172,13 +171,15 @@ _mmu_init:
 		move.l	d1,MCF_MMU_MMUDR
 		move.l	d3,MCF_MMU_MMUOR						// setzen instr
 */
-		move.l	(sp)+,d2			// Restore registers
-		move.l	(sp)+,d3
+		move.l	#0xa10ca120,d0
+		move.l	d0,_rt_cacr								// sichern
+ 		movec	d0,cacr
+		nop
 		rts
 
-/*
- * MMU table search
- */
+/********************************************************************/
+	/* MMU table search /*
+/********************************************************************/
 _mmutr_miss:
 		bsr		cpusha
 		and.l	#0xFFF00000,d0

BaS_codewarrior/firebeeV1/sources/movem.h

@@ -0,0 +1,256 @@
+// movem
+_ii_movem_lset: .macro
+// movem rx,xxx.L
+	ii_lset		0x48f9
+// movem rx,-(ax)
+	
+// movem (ax)+,rx
+	ii_lset		0x4cd8
+	ii_lset		0x4cd9
+	ii_lset		0x4cda
+	ii_lset		0x4cdb
+	ii_lset		0x4cdc
+	ii_lset		0x4cdd
+	ii_lset		0x4cde
+	ii_lset		0x4cdf
+// movem xxx.L,rx
+	ii_lset		0x4cf9
+.endm
+//***********************************************************************************/
+_ii_movem_func: .macro
+//-------------------------------------------------------------------
+// movem.l
+//--------------------------------------------------------------------
+// movem.l (ax)+,reg
+//--------------------------------------------------------------------
+//-------------------------------------------------------------------------------
+ii_0x4cd8:		// movem.l (a0)+,reglist
+	mvm_macro	0x4cd0,0x41e8,2
+ii_0x4cd9:		// movem.l (a1)+,reglist
+	mvm_macro	0x4cd1,0x43e9,2
+ii_0x4cda:		// movem.l (a2)+,reglist
+	mvm_macro	0x4cd2,0x45ea,2
+ii_0x4cdb:		// movem.l (a3)+,reglist
+	mvm_macro	0x4cd3,0x47eb,2
+ii_0x4cdc:		// movem.l (a4)+,reglist
+	mvm_macro	0x4cd4,0x49ec,2
+ii_0x4cdd:		// movem.l (a5)+,reglist
+	mvm_macro	0x4cd5,0x4bed,2
+ii_0x4cde:		// movem.l (a6)+,reglist
+	mvm_macro	0x4cd6,0x4dee,2
+ii_0x4cdf:		// movem.l (a7)+,reglist
+	mvm_macro	0x4cd7,0x4fef,2
+//----------------------------------------------------------------------------
+ii_0x48f9:		// movem.l reg,xxx.L
+		move.w		(a0)+,d0
+		move.l		(a0)+,a1
+		movemrm_macro
+		ii_end
+//---------------------------------------------------------------------------------------------
+ii_0x4cf9:		// movem.l xxx.L,reg
+		move.w		(a0)+,d0
+		move.l		(a0)+,a1
+		movemmr_macro
+		ii_end
+.endm
+//==============================================================
+mvm_macro:.macro
+halt
+	lea			az_reg_table,a1
+	mvz.b		(a0),d1
+	mvz.b		0(a1,d1)+,d0
+	mvz.b		1(a0),d1
+	mvz.b		0(a1,d1)+,d1
+	add.l		d0,d1
+	lea			___RAMBAR1,a1
+	move.l		a1,pc_off(a7)
+	move.l		a1,d0
+	addq.l		#1,d0
+   	movec      	d0,RAMBAR1
+	move.w		#\1,(a1)+			// movem.x (ax),reg_list
+	move.w		(a0)+,(a1)+			// register list
+	move.w		#\2,(a1)+			// lea 0(ax),ax
+	lsl.l		#\3,d1				// * anzahl byts pro wert
+	move.w		d1,(a1)+			// offset von lea
+	move.w		#0x4ef9,(a1)+		// jmp.l
+	move.l		a0,(a1)				// r<>cksprungadresse
+   	move.l 		#___RAMBAR1 + 0x81,d0	// instruction
+   	movec      	d0,RAMBAR1
+	movem.l		(a7),d0/d1/a0/a1
+	lea			ii_ss(a7),a7		// stack erh<72>hen
+	rte
+	.endm
+	.long		0
+az_reg_table:
+	.byte		0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4		// 0-f
+	.byte		1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5		// 10-1f
+	.byte		1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5		// 20-2f
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// 30-3f
+	.byte		1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5		// 40-4f
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// 50
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// 60
+	.byte		3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7		// 70
+	.byte		1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5		// 80-8f
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// 90
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// a0
+	.byte		3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7		// b0
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// c0
+	.byte		3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7		// d0
+	.byte		3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7		// e0
+	.byte		4,5,5,6,5,6,6,7,5,6,6,7,6,7,7,8		// f0
+//---------------------------------------------------------------------------------
+movemrm_macro:.macro				// in d0 register liste, in a1 zieladresse
+halt
+		tst.b	d0					// datenregister zu verschieben?
+		bne		mrm_dx				// ja->
+		lsr.l	#8,d0				// sonst zu addressregister
+		jmp		mmrm_nd7			// ->
+mrm_dx:
+		lsr.l	#1,d0
+		bcc		mmrm_nd0
+		move.l	d0_off(a7),(a1)+
+mmrm_nd0:
+		lsr.l	#1,d0
+		bcc		mmrm_nd1
+		move.l	d1_off(a7),(a1)+
+mmrm_nd1:
+		lsr.l	#1,d0
+		bcc		mmrm_nd2
+		move.l	d2,(a1)+
+mmrm_nd2:
+		lsr.l	#1,d0
+		bcc		mmrm_nd3
+		move.l	d3,(a1)+
+mmrm_nd3:
+		lsr.l	#1,d0
+		bcc		mmrm_nd4
+		move.l	d4,(a1)+
+mmrm_nd4:
+		lsr.l	#1,d0
+		bcc		mmrm_nd5
+		move.l	d5,(a1)+
+mmrm_nd5:
+		lsr.l	#1,d0
+		bcc		mmrm_nd6
+		move.l	d6,(a1)+
+mmrm_nd6:
+		lsr.l	#1,d0
+		bcc		mmrm_nd7
+		move.l	d7,(a1)+
+mmrm_nd7:
+		tst.b	d0					// addressregister zu verschieben?
+		beq		mmrm_na7
+		lsr.l	#1,d0
+		bcc		mmrm_na0
+		move.l	a0_off(a7),(a1)+
+mmrm_na0:
+		lsr.l	#1,d0
+		bcc		mmrm_na1
+		move.l	a1_off(a7),(a1)+
+mmrm_na1:
+		lsr.l	#1,d0
+		bcc		mmrm_na2
+		move.l	a2,(a1)+
+mmrm_na2:
+		lsr.l	#1,d0
+		bcc		mmrm_na3
+		move.l	a3,(a1)+
+mmrm_na3:
+		lsr.l	#1,d0
+		bcc		mmrm_na4
+		move.l	a4,(a1)+
+mmrm_na4:
+		lsr.l	#1,d0
+		bcc		mmrm_na5
+		move.l	a5,(a1)+
+mmrm_na5:
+		lsr.l	#1,d0
+		bcc		mmrm_na6
+		move.l	a6,(a1)+
+mmrm_na6:
+		lsr.l	#1,d0
+		bcc		mmrm_na7
+		move.l	a0,d1		// sichern
+		move.l	usp,a0		// ist ja usp
+		move.l	a0,(a1)+	// nach a0
+		move.l	d1,a0		// pc zur<75>ck
+mmrm_na7:
+		.endm
+//---------------------------------------------------------------------------------------------
+movemmr_macro:.macro				// in d0 register liste, in a1 source adr
+halt
+		tst.b	d0					// datenregister zu verschieben?
+		bne		mmr_dx				// ja->
+		lsr.l	#8,d0				// sonst zu addressregister
+		bra		mmmr_nd7			// ->
+mmr_dx:
+		lsr.l	#1,d0
+		bcc		mmmr_nd0
+		move.l	(a1)+,d0_off(a7)
+mmmr_nd0:
+		lsr.l	#1,d0
+		bcc		mmmr_nd1
+		move.l	(a1)+,d1_off(a7)
+mmmr_nd1:
+		lsr.l	#1,d0
+		bcc		mmmr_nd2
+		move.l	(a1)+,d2
+mmmr_nd2:
+		lsr.l	#1,d0
+		bcc		mmmr_nd3
+		move.l	(a1)+,d3
+mmmr_nd3:
+		lsr.l	#1,d0
+		bcc		mmmr_nd4
+		move.l	(a1)+,d4
+mmmr_nd4:
+		lsr.l	#1,d0
+		bcc		mmmr_nd5
+		move.l	(a1)+,d5
+mmmr_nd5:
+		lsr.l	#1,d0
+		bcc		mmmr_nd6
+		move.l	(a1)+,d6
+mmmr_nd6:
+		lsr.l	#1,d0
+		bcc		mmmr_nd7
+		move.l	(a1)+,d7
+mmmr_nd7:
+		tst.b	d0					// addressregister zu verschieben?
+		beq		mmmr_na7			// nein->
+		lsr.l	#1,d0
+		bcc		mmmr_na0
+		move.l	(a1)+,a0_off(a7)
+mmmr_na0:
+		lsr.l	#1,d0
+		bcc		mmmr_na1
+		move.l	(a1)+,a1_off(a7)
+mmmr_na1:
+		lsr.l	#1,d0
+		bcc		mmmr_na2
+		move.l	(a1)+,a2
+mmmr_na2:
+		lsr.l	#1,d0
+		bcc		mmmr_na3
+		move.l	(a1)+,a3
+mmmr_na3:
+		lsr.l	#1,d0
+		bcc		mmmr_na4
+		move.l	(a1)+,a4
+mmmr_na4:
+		lsr.l	#1,d0
+		bcc		mmmr_na5
+		move.l	(a1)+,a5
+mmmr_na5:
+		lsr.l	#1,d0
+		bcc		mmmr_na6
+		move.l	(a1)+,a6
+mmmr_na6:
+		lsr.l	#1,d0
+		bcc		mmmr_na7
+		move.l	a0,d1		// sichern
+		move.l	(a1)+,a0	// nach a0
+		move.l	a0,usp		// war ja usp
+		move.l	d1,a0		// pc zur<75>ck
+mmmr_na7:
+		.endm		

BaS_codewarrior/firebeeV1/sources/sd_card.c

@@ -0,0 +1,605 @@
+/********************************************************************/
+// sd card
+/********************************************************************/
+
+#define __MBAR  				0xff000000
+#define MCF_SLT0_SCNT           __MBAR + 0x908
+#define MCF_PSC0_PSCTB_8BIT		__MBAR + 0x860C
+#define MCF_PAD_PAR_DSPI        __MBAR + 0xA50
+#define MCF_DSPI_DMCR		    __MBAR + 0x8A00		//dspi control
+
+#define	dspi_dtar0	0x0c
+#define	dspi_dsr	0x2c	
+#define	dspi_dtfr	0x34	
+#define	dspi_drfr	0x38
+#define	time1us		1320
+
+
+void wait_10ms(void)
+{
+	asm
+	{
+warte_10ms:
+		move.l		d0,-(sp) 		
+  		move.l		MCF_SLT0_SCNT,d0
+  		sub.l		#1320000,d0
+ warte_d6:
+		cmp.l		MCF_SLT0_SCNT,d0
+		bcs			warte_d6
+		move.l		(sp)+,d0
+	}
+}
+
+void sd_com(void)		// byt senden und holen ---------------------
+{
+
+	asm
+	{
+
+		move.l		d4,dspi_dtfr(a0)
+wait_auf_complett:
+		btst.b		#7,dspi_dsr(a0)
+		beq			wait_auf_complett
+		move.l		dspi_drfr(a0),d5
+		mov3q.l		#-1,dspi_dsr(a0)		// clr status register
+	}
+}
+
+void sd_get_status(void)	// status holen -------------------------------
+{
+	asm
+	{
+sd_get_status:
+		move.b		#0xff,d4
+		bsr			sd_com
+		cmp.b		#0xff,d5
+		beq			sd_get_status
+	}
+}
+
+void sd_rcv_info(void)	 // daten holen ----------------------------
+{
+	asm
+	{
+		moveq		#18,d3						// 16 byts + 2 byts crc
+		move.b		#0xff,d4
+sd_rcv_rb_w:		
+		bsr			sd_get_status 
+		cmp.b		#0xfe,d5				// daten bereit?
+		bne			sd_rcv_rb_w				// nein->
+sd_rcv_rd_rb:
+		bsr			sd_com
+		move.b		d5,(a2)+
+		subq.l		#1,d3
+		bne			sd_rcv_rd_rb
+	}
+}
+
+void sd_card_idle(void)
+{
+
+	asm
+	{
+// sd idle
+// speed =400kHz
+		move.l		#0x082000ff,d4			// tx vorbesetzen
+		lea			MCF_DSPI_DMCR,a0
+		move.l		#0x38558897,d0				
+		move.l		d0,dspi_dtar0(a0)		// 400kHz 
+
+		move.b		#0xff,d4
+		bsr			sd_com					// clocks 
+		move.b		#0x40,d4				// cmd idle
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x95,d4
+		bsr			sd_com
+	}
+}
+
+int sd_card_init(void)
+{
+
+		long		az_sectors;
+
+	asm
+	{
+		lea			MCF_PSC0_PSCTB_8BIT,a1
+		move.l  	#'SD-C',(a1)
+		move.l  	#'ard ',(a1)
+
+		move.l		buffer,a5					// basis addresse (diesen bereich brauchen wir nicht mehr!)
+		move.l		#0x1fffffff,d0				// normal dspi
+		move.l		d0,MCF_PAD_PAR_DSPI
+		lea			MCF_DSPI_DMCR,a0
+		move.l		#0x802d3c00,(a0)			// 8 bit cs off clear fifo
+		move.l		#0x38558897,d0				
+		move.l		d0,dspi_dtar0(a0)			// 400kHz 
+		move.l		#0x082000ff,d4				// tx vorbesetzen
+		move.l		d4,dspi_dtfr				// und setzen
+		mov3q.l		#-1,dspi_dsr(a0)			// status register l<>schen
+		
+		move.l		#0xc00d3c00,(a0)			// clock on cs ist on
+		bsr			wait_10ms
+		move.l		#0x802d3c00,(a0)			// clock off cs off
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		move.l		#0x800d3c00,(a0)			// cs on
+		bsr			sd_com						
+		bsr			sd_com
+		move.l		#0x802d3c00,(a0)			// cs off
+		bsr			sd_com
+		bsr			sd_com
+		bsr			wait_10ms
+
+// sd idle
+		move.l		#100,d6						// 100 versuche
+		move.l		#10,d3						// 10 versuche
+sd_idle:
+		bsr			sd_card_idle
+
+		move.l		#10,d7
+		move.b		#0xff,d4
+sd_idle_leeren:
+		bsr			sd_com
+		cmp.b		#0x01,d5
+		beq			idle_end
+		subq.l		#1,d7
+		bne			sd_idle_leeren
+		subq.l		#1,d6
+		beq			sd_not
+		bra			sd_idle
+idle_end:
+
+// cdm 8
+read_ic:
+		move.b		#0xff,d4			// clocks 
+		bsr			sd_com
+		move.b		#0x48,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+		move.b		#0xaa,d4
+		bsr			sd_com
+		move.b		#0x87,d4
+		bsr			sd_com
+		
+		bsr			sd_get_status
+		cmp.b		#5,d5
+		beq			sd_v1
+		cmp.b		#1,d5
+		bne			read_ic
+		
+		bsr			sd_com			// 4byts zum wegwerfen
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		cmp.b		#0xaa,d5		// pattern zur<75>ckgekommen?
+		bne			sd_testd3		// nein ->
+
+		move.l		#'SDHC',(a1)
+		move.b		#' ',(a1)
+sd_v1:
+		
+// cdm 58
+read_ocr:
+		move.b		#0xff,d4			// clocks 
+		bsr			sd_com
+		move.b		#0x7a,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_get_status
+		move.l		#'Ver1',d6
+		cmp.b		#5,d5
+		beq			read_ocr
+		cmp.b		#1,d5
+		bne			read_ocr
+		
+		bsr			sd_com				// 4 byts zum wegwerfen
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+
+// acdm 41
+		move.l		#20000,d6			// 20000 versuche ready can bis 1 sec gehen
+wait_of_aktiv:
+		move.b		#0xff,d4			// clocks 
+		bsr			sd_com
+		move.b		#0x77,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x95,d4
+		bsr			sd_com
+
+		bsr			sd_get_status
+		cmp.b		#0x05,d5
+		beq			wait_of_aktiv
+
+wait_of_aktiv2:
+		move.b		#0xff,d4			// clocks 
+		bsr			sd_com
+		move.b		#0x69,d4
+		bsr			sd_com
+		move.b		#0x40,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x95,d4
+		bsr			sd_com
+
+		bsr			sd_get_status
+		tst.b		d5
+		beq			sd_init_ok
+		cmp.b		#0x05,d5
+		beq			wait_of_aktiv2	
+		subq.l		#1,d6
+		bne			wait_of_aktiv
+sd_testd3:
+		subq.l		#1,d3
+		bne			sd_idle
+		bra			sd_error
+
+sd_init_ok:
+// fullspeed 
+		move.l		#0x38551120,d0				// 22Mbit/sec
+		move.l		d0,dspi_dtar0(a0)			// setzen 
+
+// cdm 10
+read_cid:
+		move.b		#0xff,d4			// clocks 
+		bsr			sd_com
+		move.b		#0x4a,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x95,d4
+		bsr			sd_com
+		
+		move.l		a5,a2				// adresse setzen
+		bsr			sd_rcv_info
+
+// name ausgeben
+		lea			1(a5),a2
+		moveq		#7,d7
+sd_nam_loop:
+		move.b		(a2)+,(a1)
+		subq.l		#1,d7
+		bne			sd_nam_loop
+		move.b		#' ',(a1)
+
+// cdm 9
+read_csd:
+		move.b		#0xff,d4			// clocks 
+		bsr			sd_com
+		move.b		#0x49,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+		
+		move.l		a5,a2				// adresse setzen
+		bsr			sd_rcv_info
+
+		mvz.b		(a5),d0
+		lsr.l		#6,d0
+		
+		bne			sd_csd2				// format v2
+		move.l		6(a5),d1
+		moveq		#14,d0				// bit 73..62 c_size
+		lsr.l		d0,d1				// bits extrahieren
+		and.l		#0xfff,d1			// 12 bits
+		addq.l		#1,d1
+		mvz.w		9(a5),d0
+		lsr.l		#7,d0				// bits 49..47
+		and.l		#0x7,d0				// 3 bits
+		moveq.l		#8,d2				// x256 (dif v1 v2)
+		sub.l		d0,d2		
+		lsr.l		d2,d1
+		bra			sd_print_size
+sd_csd2:
+		mvz.w		8(a5),d1
+		addq.l		#1,d1
+sd_print_size:
+		swap		d1
+		move.l		d1,d3
+		lsr.l		#6,d3				//x65636 /64 -> anzahl sectors
+		move.l		d3,az_sectors
+		lsl.l		#1,d1
+		bcc			sd_16G
+		move.l		#'32GB',(a1)
+		bra			sd_ok
+sd_16G:
+		lsl.l		#1,d1
+		bcc			sd_8G
+		move.l		#'16GB',(a1)
+		bra			sd_ok
+sd_8G:
+		lsl.l		#1,d1
+		bcc			sd_4G
+		move.l		#' 8GB',(a1)
+		bra			sd_ok
+sd_4G:
+		lsl.l		#1,d1
+		bcc			sd_2G
+		move.l		#' 4GB',(a1)
+		bra			sd_ok
+sd_2G:
+		lsl.l		#1,d1
+		bcc			sd_1G
+		move.l		#' 2GB',(a1)
+		bra			sd_ok
+sd_1G:
+		lsl.l		#1,d1
+		bcc			sd_512M
+		move.l		#' 1GB',(a1)
+		bra			sd_ok
+sd_512M:
+		lsl.l		#1,d1
+		bcc			sd_256M
+		move.b		#'5',(a1)
+		move.l		#'12MB',(a1)
+		bra			sd_ok
+sd_256M:
+		lsl.l		#1,d1
+		bcc			sd_128M
+		move.b		#'2',(a1)
+		move.l		#'56MB',(a1)
+		bra			sd_ok
+sd_128M:
+		lsl.l		#1,d1
+		bcc			sd_64M
+		move.b		#'1',(a1)
+		move.l		#'28MB',(a1)
+		bra			sd_ok
+sd_64M:
+		lsl.l		#1,d1
+		bcc			sd_32M
+		move.l		#'64MB',(a1)
+		bra			sd_ok
+sd_32M:
+		lsl.l		#1,d1
+		bcc			sd_16M
+		move.l		#'32MB',(a1)
+		bra			sd_ok
+sd_16M:
+		lsl.l		#1,d1
+		bcc			sd_8M
+		move.l		#'16MB',(a1)
+		bra			sd_ok
+sd_8M:
+		move.l		#'<9MB',(a1)
+sd_ok:		
+		move.l  	#' OK!',(a1)
+		move.l		#0x0a0d,(a1)
+		bra			sd_c_ok
+// subs ende -------------------------------
+sd_error:
+		move.l  	#'Erro',(a1)
+		move.l  	#'r!',(a1)
+		move.l		#0x0a0d,(a1)
+		bra			sd_c_error
+sd_not:
+		move.l  	#'non!',(a1)
+		move.l		#0x0a0d,(a1)
+		bra			sd_c_not
+buffer:	dc.l		0,0,0,0,0,0,0,0
+	}
+sd_c_ok:
+		return		az_sectors;
+sd_c_not:
+		return		-2;
+sd_c_error:
+		return		-1;
+}
+
+void sd_rcv_sector(void)	 // 1 sector daten holen ----------------------------
+{
+	asm
+	{
+		bsr			sd_get_status 
+		cmp.b		#0xfe,d5				// daten bereit?
+		bne			sd_rs_end				// nein-> error
+		move.l		#512,d3					// sonst 512 byts abholen
+sd_rs_loop:
+		bsr			sd_com
+		move.b		d5,(a2)+
+		subq.l		#1,d3
+		bne			sd_rs_loop
+// crc holen
+		bsr			sd_com
+		bsr			sd_com
+		clr.l		d5						// alles ok
+sd_rs_end:
+	}
+}
+
+int sd_card_sector_read(long sec_nr,long buf_adr)
+{
+		int			status ;
+	asm
+	{
+		lea			MCF_DSPI_DMCR,a0
+		move.l		#0x082000ff,d4				// tx vorbesetzen
+
+		move.l		sec_nr,d0
+		move.l		buf_adr,a2
+
+		lsl.l		#8,d0
+		add.l		d0,d0						// x 512 !
+		move.l		d0,d1						// byts kehren
+		swap		d1
+		move.l		d1,d2
+		lsr.l		#8,d1
+		
+		move.b		#0xff,d4			// clocks 
+		bsr			sd_com
+		
+		move.b		#0x51,d4
+		bsr			sd_com
+		move.b		d1,d4
+		bsr			sd_com
+		move.b		d2,d4
+		bsr			sd_com
+		move.l		d0,d2
+		lsr.l		#8,d2
+		move.b		d2,d4
+		bsr			sd_com
+		move.b		d0,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+
+		clr.l		d5					// alles auf no error
+		clr.l		status
+		
+		bsr			sd_get_status		// status holen
+		tst.b		d5
+		bne			sd_csr_end			// wenn nicht ok -> weg
+// sector holen
+		bsr			sd_rcv_sector
+sd_csr_end:
+		tst.b		d5
+		beq			sd_csr_ok
+		neg.l		d5					// wenn nicht ok status auf negativ
+		move.l		d5,status
+sd_csr_ok:
+	}
+	return	status;
+}
+
+void sd_send_sector(void)	 // 1 sector daten senden ----------------------------
+{
+	asm
+	{
+		move.l		#512,d3		
+		move.b		#0xfe,d4			// start token
+		bsr			sd_com				// senden
+sd_send_wr_wb:
+		move.b		(a2)+,d4			// data
+		bsr			sd_com				// senden
+		subq.l		#1,d3
+		bne			sd_send_wr_wb	
+// send crc
+		move.b		#1,d4			
+		bsr			sd_com				// crc 1.byt
+		move.b		#1,d4			
+		bsr			sd_com				// crc 2.byt
+sd_send_wr_ww:
+		bsr			sd_get_status
+		and.l		#0x1f,d5
+		clr.l		d6					//status auf OK
+		cmp.b		#5,d5				//data accepted?
+		beq			sd_send_end			//ja ->
+		move.l		d5,d6				//sonst status sichern
+sd_send_end:
+		bsr			sd_com
+		tst.b		d5					// warte auf geschrieben
+		beq			sd_send_end
+		move.l		d6,d5				// status zur<75>ck
+	}
+}
+
+int sd_card_sector_write(long sec_nr,long buf_adr)
+{
+		int			status;
+	asm
+	{
+		lea			MCF_DSPI_DMCR,a0
+		move.l		#0x082000ff,d4				// tx vorbesetzen
+
+		move.l		sec_nr,d0
+		move.l		buf_adr,a2
+
+		lsl.l		#8,d0
+		add.l		d0,d0						// x 512 !
+		move.l		d0,d1						// byts kehren
+		swap		d1
+		move.l		d1,d2
+		lsr.l		#8,d1
+		
+		move.b		#0xff,d4			// clocks 
+		bsr			sd_com
+		move.b		#0x58,d4
+		bsr			sd_com
+		move.b		d1,d4
+		bsr			sd_com
+		move.b		d2,d4
+		bsr			sd_com
+		move.l		d0,d2
+		lsr.l		#8,d2
+		move.b		d2,d4
+		bsr			sd_com
+		move.b		d0,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+
+		clr.l		d5					// alles auf no error
+		clr.l		status
+		bsr			sd_get_status		// status holen
+		tst.b		d5
+		bne			sd_csw_end			// wenn nicht ok -> weg
+// sector schreiben
+		bsr			sd_send_sector
+sd_csw_end:
+		tst.b		d5
+		beq			sd_csw_ok
+		neg.l		d5					// wenn nicht ok status auf negativ
+		move.l		d5,status
+sd_csw_ok:
+	}
+	return	status;
+}

BaS_codewarrior/firebeeV1/sources/sd_card.s

@@ -0,0 +1,406 @@
+/********************************************************************/
+// sd card
+/********************************************************************/
+#define	dspi_dtar0	0x0c
+#define	dspi_dsr	0x2c	
+#define	dspi_dtfr	0x34	
+#define	dspi_drfr	0x38
+
+.text	
+sd_test:
+		lea			MCF_PSC0_PSCTB_8BIT,a6
+		move.l  	#'SD-C',(a6)
+		move.l  	#'ard ',(a6)
+
+		move.l		#__Bas_base,a5					// basis addresse (diesen bereich brauchen wir nicht mehr!)
+		move.l		#0x1fffffff,d0				// normal dspi
+		move.l		d0,MCF_PAD_PAR_DSPI
+		lea			MCF_DSPI_DMCR,a0
+		move.l		#0x800d3c00,(a0)			// 8 bit cs5 on
+		move.l		#0x38558897,d0				
+		move.l		d0,dspi_dtar0(a0)			// 400kHz 
+		move.l		#0x082000ff,d4				// tx vorbesetzen
+		mov3q.l		#-1,dspi_dsr(a0)
+		
+		bsr			warte_1ms
+		move.l		#0xc00d3c00,(a0)			// 8 bit 4MHz clocken cs off
+		bsr			warte_10ms
+		move.l		#0x800d3c00,(a0)			// 8 bit 4MHz normal cs on
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		move.l		#0x802d3c00,(a0)			// 8 bit 4MHz normal cs off
+		clr.b		d4
+		bsr			sd_com
+		bsr			sd_com
+		move.l		#0x800d3c00,(a0)			// 8 bit 4MHz normal cs on
+		move.b		#0xff,d4
+		bsr			sd_com
+		bsr			sd_com
+		move.l		#0x802d3c00,(a0)			// 8 bit 4MHz normal cs off
+		bsr			warte_10ms
+
+// sd idle
+		move.l		#100,d6				// 100 versuche
+		move.l		#10,d3				// 10 versuche
+sd_idle:
+		move.b		#0xff,d4			// receive byt
+		bsr			sd_com
+		move.b		#0x40,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x95,d4
+		bsr			sd_com
+		
+		move.b		#0xff,d4			// receive byt
+		bsr			sd_com
+		cmp.b		#0x01,d5
+		beq			idle_end
+		bsr			sd_com
+		cmp.b		#0x01,d5
+		beq			idle_end
+		bsr			sd_com
+		cmp.b		#0x01,d5
+		beq			idle_end
+		bsr			sd_com
+		cmp.b		#0x01,d5
+		beq			idle_end
+		bsr			sd_com
+		cmp.b		#0x01,d5
+		beq			idle_end
+		bsr			sd_com
+		cmp.b		#0x01,d5
+		beq			idle_end
+		subq.l		#1,d6
+		beq			sd_not
+		bra			sd_idle
+idle_end:
+// cdm 8
+read_ic:
+		move.b		#0xff,d4			// receive byt
+		bsr			sd_com
+		move.b		#0x48,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+		move.b		#0xaa,d4
+		bsr			sd_com
+		move.b		#0x87,d4
+		bsr			sd_com
+		
+		bsr			sd_get_status
+		cmp.b		#5,d5
+		beq			sd_v1
+		cmp.b		#1,d5
+		bne			read_ic
+		
+		move.b		#0xff,d4
+		bsr			sd_com
+		move.b		d5,d0
+		bsr			sd_com
+		move.b		d5,d1
+		bsr			sd_com
+		move.b		d5,d2
+		bsr			sd_com
+		cmp.b		#0xaa,d5
+		bne			sd_testd3
+
+		move.l		#'SDHC',(a6)
+		move.b		#' ',(a6)
+sd_v1:
+		
+// cdm 58
+read_ocr:
+		move.b		#0xff,d4			// receive byt
+		bsr			sd_com
+		move.b		#0x7a,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_get_status
+		move.l		#'Ver1',d6
+		cmp.b		#5,d5
+		beq			read_ocr
+		cmp.b		#1,d5
+		bne			read_ocr
+		
+		move.b		#0xff,d4
+		bsr			sd_com
+		move.b		d5,d0
+		bsr			sd_com
+		move.b		d5,d1
+		bsr			sd_com
+		move.b		d5,d2
+		bsr			sd_com
+
+// acdm 41
+		move.l		#20000,d6			// 20000 versuche ready can bis 1 sec gehen
+wait_of_aktiv:
+		move.b		#0xff,d4			// receive byt
+		bsr			sd_com
+		move.b		#0x77,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x95,d4
+		bsr			sd_com
+
+		bsr			sd_get_status
+		cmp.b		#0x05,d5
+		beq			wait_of_aktiv
+
+wait_of_aktiv2:
+		move.b		#0xff,d4			// receive byt
+		bsr			sd_com
+		move.b		#0x69,d4
+		bsr			sd_com
+		move.b		#0x40,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x95,d4
+		bsr			sd_com
+
+		bsr			sd_get_status
+		tst.b		d5
+		beq			sd_init_ok
+		cmp.b		#0x05,d5
+		beq			wait_of_aktiv2	
+		subq.l		#1,d6
+		bne			wait_of_aktiv
+sd_testd3:
+		subq.l		#1,d3
+		bne			sd_idle
+		bra			sd_error
+
+sd_init_ok:
+// cdm 10
+read_cid:
+		move.b		#0xff,d4			// receive byt
+		bsr			sd_com
+		move.b		#0x4a,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x95,d4
+		bsr			sd_com
+		
+		move.l		a5,a4				// adresse setzen
+		bsr			sd_rcv_info
+
+// name ausgeben
+		lea			1(a5),a4
+		moveq		#7,d7
+sd_nam_loop:
+		move.b		(a4)+,(a6)
+		subq.l		#1,d7
+		bne			sd_nam_loop
+		move.b		#' ',(a6)
+
+// cdm 9
+read_csd:
+		move.b		#0xff,d4			// receive byt
+		bsr			sd_com
+		move.b		#0x49,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+		
+		move.l		a5,a4				// adresse setzen
+		bsr			sd_rcv_info
+
+		mvz.b		(a5),d0
+		lsr.l		#6,d0
+		
+		bne			sd_csd2				// format v2
+		move.l		6(a5),d1
+		moveq		#14,d0				// bit 73..62 c_size
+		lsr.l		d0,d1				// bits extrahieren
+		and.l		#0xfff,d1			// 12 bits
+		addq.l		#1,d1
+		mvz.w		9(a5),d0
+		lsr.l		#7,d0				// bits 49..47
+		and.l		#0x7,d0				// 3 bits
+		moveq.l		#8,d2				// x256 (dif v1 v2)
+		sub.l		d0,d2		
+		lsr.l		d2,d1
+		bra			sd_print_size
+sd_csd2:
+		mvz.w		8(a5),d1
+		addq.l		#1,d1
+sd_print_size:		
+		swap		d1
+		lsl.l		#1,d1
+		bcc			sd_16G
+		move.l		#'32GB',(a6)
+		bra			sd_ok
+sd_16G:
+		lsl.l		#1,d1
+		bcc			sd_8G
+		move.l		#'16GB',(a6)
+		bra			sd_ok
+sd_8G:
+		lsl.l		#1,d1
+		bcc			sd_4G
+		move.l		#' 8GB',(a6)
+		bra			sd_ok
+sd_4G:
+		lsl.l		#1,d1
+		bcc			sd_2G
+		move.l		#' 4GB',(a6)
+		bra			sd_ok
+sd_2G:
+		lsl.l		#1,d1
+		bcc			sd_1G
+		move.l		#' 2GB',(a6)
+		bra			sd_ok
+sd_1G:
+		lsl.l		#1,d1
+		bcc			sd_512M
+		move.l		#' 1GB',(a6)
+		bra			sd_ok
+sd_512M:
+		lsl.l		#1,d1
+		bcc			sd_256M
+		move.b		#'5',(a6)
+		move.l		#'12MB',(a6)
+		bra			sd_ok
+sd_256M:
+		lsl.l		#1,d1
+		bcc			sd_128M
+		move.b		#'2',(a6)
+		move.l		#'56MB',(a6)
+		bra			sd_ok
+sd_128M:
+		lsl.l		#1,d1
+		bcc			sd_64M
+		move.b		#'1',(a6)
+		move.l		#'28MB',(a6)
+		bra			sd_ok
+sd_64M:
+		lsl.l		#1,d1
+		bcc			sd_32M
+		move.l		#'64MB',(a6)
+		bra			sd_ok
+sd_32M:
+		lsl.l		#1,d1
+		bcc			sd_16M
+		move.l		#'32MB',(a6)
+		bra			sd_ok
+sd_16M:
+		lsl.l		#1,d1
+		bcc			sd_8M
+		move.l		#'16MB',(a6)
+		bra			sd_ok
+sd_8M:
+		move.l		#'<9MB',(a6)
+sd_ok:		
+		move.l  	#' OK!',(a6)
+		move.l		#0x0a0d,(a6)
+		halt
+		halt
+		rts
+// subs ende -------------------------------
+sd_V1:
+		move.l  #'non!',(a6)
+		move.l	#0x0a0d,(a6)
+		halt
+		halt
+		rts
+sd_error:
+		move.l  #'Erro',(a6)
+		move.l  #'r!',(a6)
+		move.l	#0x0a0d,(a6)
+		halt
+		halt
+		rts
+sd_not:
+		move.l  #'non!',(a6)
+		move.l	#0x0a0d,(a6)
+		halt
+		halt
+		rts
+
+// status holen -------------------------------
+sd_get_status:
+		move.b		#0xff,d4
+		bsr			sd_com
+		cmp.b		#0xff,d5
+		beq			sd_get_status
+		rts
+// byt senden und holen ---------------------		
+sd_com:
+		move.l		d4,dspi_dtfr(a0)
+wait_auf_complett:
+		btst.b		#7,dspi_dsr(a0)
+		beq			wait_auf_complett
+		move.l		dspi_drfr(a0),d5
+		mov3q.l		#-1,dspi_dsr(a0)		// clr status register
+		rts
+
+// daten holen ----------------------------
+sd_rcv_info:		
+		moveq		#18,d3						// 16 byts + 2 byts crc
+		move.b		#0xff,d4
+sd_rcv_rb_w:		
+		bsr			sd_get_status 
+		cmp.b		#0xfe,d5				// daten bereit?
+		bne			sd_rcv_rb_w				// nein->
+sd_rcv_rd_rb:
+		bsr			sd_com
+		move.b		d5,(a4)+
+		subq.l		#1,d3
+		bne			sd_rcv_rd_rb
+		rts
+/******************************************/

BaS_codewarrior/firebeeV1/sources/sd_ide.c

@@ -0,0 +1,543 @@
+
+
+#include "MCF5475.h"
+#include "startcf.h"
+
+extern unsigned long far __SP_AFTER_RESET[];
+extern unsigned long far __Bas_base[];
+
+	/* imported routines */
+//extern int warten_20ms();
+//extern int warten_200us();
+//extern int warten_10us();
+ 
+/********************************************************************/
+void asm sd_test(void)
+{
+		clr.w		MCF_PAD_PAR_DSPI
+		lea			MCF_GPIO_PPDSDR_DSPI,a2		// data in
+		lea			MCF_GPIO_PODR_DSPI,a1		// data out
+		move.b		#0x00,(a1)					// alle auf 0
+		lea			MCF_GPIO_PDDR_DSPI,a0
+		move.b		#0x7d,(a0)					// din = input rest output
+		
+		bsr			warten_20ms
+		
+		move.b		#0x7f,(a1)					// alle auf 1
+
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+// sd idle
+sd_idle:
+		bsr			sd_16clk
+		moveq		#0x40,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x95,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x05,d5
+		beq			sd_test
+		cmp.b		#0x01,d5
+		beq			wait_of_aktiv
+		cmp.b		#0x04,d5
+		beq			sd_init_ok
+		cmp.b		#0x00,d5
+		beq			sd_init_ok
+		bra			sd_idle
+				
+// acdm 41
+wait_of_aktiv:
+		bsr			sd_16clk
+
+		moveq		#0x77,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+
+		bsr			sd_receive
+
+		bsr			sd_16clk
+
+		move.l		#0xff,d6
+		moveq		#0x69,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#00,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#00,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#0x02,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#00,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#0x01,d4
+		bsr			sd_com
+		and			d5,d6
+
+		bsr			sd_receive
+				
+		cmp.b		#0x00,d5
+		beq			sd_init_ok
+		cmp.b		#0x05,d5
+		beq			sd_test	
+		bra			wait_of_aktiv
+
+sd_init_ok:
+
+// blockgr<67>sse 512byt
+sd_bg:
+		bsr			sd_16clk
+		moveq		#0x50,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#02,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_bg
+
+// read block
+sd_rb:
+		bsr			sd_16clk
+		moveq		#0x51,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x08,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_rb
+		
+		lea			0xc00000,a4
+		move.l		#513,d7
+rd_rb:
+		bsr			sd_receive
+		move.b		d5,(a4)+
+		subq.l		#1,d7
+		bne			rd_rb	
+
+// write block
+sd_wb:
+		bsr			sd_16clk
+		moveq		#0x58,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x08,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_wb
+		
+		lea			0xc00000,a4
+		move.l		#513,d7
+		moveq.l		#0x66,d4
+wr_wb:
+		bsr			sd_com
+//		subq.l		#1,d4
+		moveq		#0x66,d4
+		subq.l		#1,d7
+		bne			wr_wb	
+
+		bsr			sd_receive
+		
+wr_wb_el:	
+		moveq		#0xff,d4
+		bsr			sd_com
+		cmp.b		#0xff,d5
+		bne			wr_wb_el
+		
+
+// read block 2
+sd_rb2:
+		bsr			sd_16clk
+		moveq		#0x51,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x08,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_rb2
+		
+		lea			0xc00400,a4
+		move.l		#513,d7
+rd_rb2:
+		bsr			sd_receive
+		move.b		d5,(a4)+
+		subq.l		#1,d7
+		bne			rd_rb2	
+
+
+		nop
+		nop
+
+		rts
+		
+sd_receive:
+		moveq		#0xff,d4
+		bsr			sd_com
+		cmp.b		#0xff,d5
+		beq			sd_receive
+		rts
+		
+sd_com:
+		bclr.b		#6,(a1)
+sd_comb:
+		bsr			warten_10us
+		moveq		#7,d2
+		clr.l		d5
+sd_com_loop:
+		btst		d2,d4
+		beq			sd_com2
+		bset.b		#0,(a1)
+		bra			sd_com2_1
+sd_com2:
+		bclr.b		#0,(a1)
+sd_com2_1:
+		bsr			sd_clk
+		and.l		#0x02,d3
+		beq			sd_com3
+		bset.b		d2,d5
+sd_com3:
+		subq.l		#1,d2
+		bge			sd_com_loop
+		bsr			warten_10us
+		bset.b		#6,(a1)
+		bset.b		#0,(a1)
+		bsr			warten_200us
+		rts
+sd_clk:
+		tst.b		0xfffff700
+		tst.b		0xfffff700
+		bset.b		#2,(a1)
+		tst.b		0xfffff700
+		tst.b		0xfffff700
+		move.b		(a2),d3
+		tst.b		0xfffff700
+		bclr.b		#2,(a1)
+		rts
+
+sd_15clk:
+		move		#15,d0
+		bra			sd_16clk
+sd_16clk:
+		moveq		#16,d0
+sd_16clk1:
+		bsr			sd_clk
+		subq.l		#1,d0
+		bne			sd_16clk1
+		bsr			warten_10us
+		rts
+// warteschleife ca. 20ms  
+warten_20ms:  		
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#700000,d6
+  		bra			warten_loop
+// warteschleife ca. 200us  
+warten_200us: 
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#7000,d6
+  		bra			warten_loop
+// warteschleife ca. 10us  
+warten_10us:  		
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#333,d6
+warten_loop:
+		move.l		(a0),d1
+		sub.l		d0,d1
+		add.l		d6,d1
+		bpl			warten_loop
+		move.l		(sp)+,d0
+		move.l		(sp)+,d1
+		move.l		(sp)+,d6
+		move.l		(sp)+,a0
+		rts;
+}
+
+
+/**************************************************/
+void asm ide_test(void)
+{
+		lea			MCF_PAD_PAR_DSPI,a0
+		move.w		#0x1fff,(a0)
+		lea			MCF_DSPI_DCTAR0,a0
+		move.l		#0x38a644e4,(a0)
+		lea			MCF_DSPI_DMCR,a0
+		move.l		#0x802d3c00,(a0)
+		clr.l		MCF_DSPI_DTCR
+		bsr			warten_20ms
+		lea			MCF_DSPI_DTFR,a0
+		lea			MCF_DSPI_DRFR,a1
+
+		moveq		#10,d0		
+sd_reset:
+		move.l		#0x000100ff,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		subq.l		#1,d0
+		bne			sd_reset
+		
+		moveq		#10,d1
+sd_loop1:
+		bsr			warten_20ms
+		moveq		#-1,d0		
+// cmd 0 set to idle
+		move.l		#0x00200040,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200095,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		cmp.w		#0x0001,d0
+		beq			sd_loop2
+		subq.l		#1,d1
+		bne			sd_loop1
+		moveq		#10,d1
+		bra			sd_test
+sd_loop2:
+		moveq		#-1,d0		
+// cmd 41		
+		move.l		#0x00200069,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200001,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		tst.w		d0
+		bne			sd_loop2
+
+		nop
+		nop
+/********************************************************************/
+#define		cmd_reg		(0x1d)
+#define		status_reg	(0x1d)
+#define		seccnt		(0x09)
+
+ide_test:
+		lea			0xfff00040,a0
+		lea			0xc00000,a1
+		move.b		#0xec,cmd_reg(a0)		//identify devcie cmd
+		bsr			wait_int
+		bsr			ds_rx
+// read sector normal		
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x20,cmd_reg(a0)		// read cmd
+		bsr			wait_int
+		bsr			ds_rx
+
+// write testpattern sector
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x30,cmd_reg(a0)		// write cmd
+		bsr			drq_wait
+// write pattern
+		move.l		#256,d0
+ide_test_loop3:		
+		move.w		#0xa55a,(a0)
+		subq.l		#1,d0
+		bne			ide_test_loop3
+		bsr			wait_int
+// read testpattern sector
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x20,cmd_reg(a0)		// read
+		bsr			wait_int
+		bsr			ds_rx
+// sector restauriern
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x30,cmd_reg(a0)		// write
+		lea			-0x400(a1),a1			// vorletzer
+		bsr			drq_wait
+		bsr			ds_tx
+		bsr			wait_int
+// fertig und zur<75>ck		
+		nop
+		rts
+// wait auf int
+wait_int:
+		move.b		0xfffffa01,d0
+		btst.b		#5,d0
+		bne			wait_int
+		move.b		status_reg(a0),d0
+		rts
+// wait auf drq
+drq_wait:
+		move.b		status_reg(a0),d0
+		btst		#3,d0
+		beq			drq_wait
+		rts
+
+// 1 sector lesen word
+ds_rx:
+		move.l		#256,d0
+ds_rx_loop:		
+		move.w		(a0),(a1)+
+		subq.l		#1,d0
+		bne			ds_rx_loop
+		rts
+// 1 sector lesen long
+ds_rxl:
+		move.l		#128,d0
+ds_rxl_loop:		
+		move.l		(a0),(a1)+
+		subq.l		#1,d0
+		bne			ds_rxl_loop
+		rts
+// 1 sector schreiben word
+ds_tx:
+		move.l		#256,d0
+ds_tx_loop:		
+		move.w		(a1)+,(a0)
+		subq.l		#1,d0
+		bne			ds_tx_loop
+		rts
+// 1 sector schreiben word
+ds_txl:
+		move.l		#128,d0
+ds_txl_loop:		
+		move.l		(a1)+,(a0)
+		subq.l		#1,d0
+		bne			ds_txl_loop
+		rts
+// warteschleife ca. 20ms  
+warten_20ms:  		
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#700000,d6
+  		bra			warten_loop
+// warteschleife ca. 200us  
+warten_200us: 
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#7000,d6
+  		bra			warten_loop
+// warteschleife ca. 10us  
+warten_10us:  		
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#333,d6
+warten_loop:
+		move.l		(a0),d1
+		sub.l		d0,d1
+		add.l		d6,d1
+		bpl			warten_loop
+		move.l		(sp)+,d0
+		move.l		(sp)+,d1
+		move.l		(sp)+,d6
+		move.l		(sp)+,a0
+		rts;
+}
+/********************************************************************/

BaS_codewarrior/firebeeV1/sources/sd_ide.s

@@ -0,0 +1,458 @@
+
+
+//.include "startcf.h"
+
+//.extern ___MBAR
+//#define MCF_SLT0_SCNT	___MBAR+0x908
+
+//.global ide_test
+
+.text
+/*
+sd_test:
+		clr.w		MCF_PAD_PAR_DSPI
+		lea			MCF_GPIO_PPDSDR_DSPI,a2		// data in
+		lea			MCF_GPIO_PODR_DSPI,a1		// data out
+		move.b		#0x00,(a1)					// alle auf 0
+		lea			MCF_GPIO_PDDR_DSPI,a0
+		move.b		#0x7d,(a0)					// din = input rest output
+		
+		bsr			warten_20ms
+		
+		move.b		#0x7f,(a1)					// alle auf 1
+
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+// sd idle
+sd_idle:
+		bsr			sd_16clk
+		moveq		#0x40,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x95,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x05,d5
+		beq			sd_test
+		cmp.b		#0x01,d5
+		beq			wait_of_aktiv
+		cmp.b		#0x04,d5
+		beq			sd_init_ok
+		cmp.b		#0x00,d5
+		beq			sd_init_ok
+		bra			sd_idle
+				
+// acdm 41
+wait_of_aktiv:
+		bsr			sd_16clk
+
+		moveq		#0x77,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+
+		bsr			sd_receive
+
+		bsr			sd_16clk
+
+		move.l		#0xff,d6
+		moveq		#0x69,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#00,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#00,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#0x02,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#00,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#0x01,d4
+		bsr			sd_com
+		and			d5,d6
+
+		bsr			sd_receive
+				
+		cmp.b		#0x00,d5
+		beq			sd_init_ok
+		cmp.b		#0x05,d5
+		beq			sd_test	
+		bra			wait_of_aktiv
+
+sd_init_ok:
+
+// blockgr<EFBFBD>sse 512byt
+sd_bg:
+		bsr			sd_16clk
+		moveq		#0x50,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#02,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_bg
+
+// read block
+sd_rb:
+		bsr			sd_16clk
+		moveq		#0x51,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x08,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_rb
+		
+		lea			0xc00000,a4
+		move.l		#513,d7
+rd_rb:
+		bsr			sd_receive
+		move.b		d5,(a4)+
+		subq.l		#1,d7
+		bne			rd_rb	
+
+// write block
+sd_wb:
+		bsr			sd_16clk
+		moveq		#0x58,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x08,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_wb
+		
+		lea			0xc00000,a4
+		move.l		#513,d7
+		moveq.l		#0x66,d4
+wr_wb:
+		bsr			sd_com
+//		subq.l		#1,d4
+		moveq		#0x66,d4
+		subq.l		#1,d7
+		bne			wr_wb	
+
+		bsr			sd_receive
+		
+wr_wb_el:	
+		moveq		#0xff,d4
+		bsr			sd_com
+		cmp.b		#0xff,d5
+		bne			wr_wb_el
+		
+
+// read block 2
+sd_rb2:
+		bsr			sd_16clk
+		moveq		#0x51,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x08,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_rb2
+		
+		lea			0xc00400,a4
+		move.l		#513,d7
+rd_rb2:
+		bsr			sd_receive
+		move.b		d5,(a4)+
+		subq.l		#1,d7
+		bne			rd_rb2	
+
+
+		nop
+		nop
+
+		rts
+		
+sd_receive:
+		moveq		#0xff,d4
+		bsr			sd_com
+		cmp.b		#0xff,d5
+		beq			sd_receive
+		rts
+		
+sd_com:
+		bclr.b		#6,(a1)
+sd_comb:
+		bsr			warten_10us
+		moveq		#7,d2
+		clr.l		d5
+sd_com_loop:
+		btst		d2,d4
+		beq			sd_com2
+		bset.b		#0,(a1)
+		bra			sd_com2_1
+sd_com2:
+		bclr.b		#0,(a1)
+sd_com2_1:
+		bsr			sd_clk
+		and.l		#0x02,d3
+		beq			sd_com3
+		bset.b		d2,d5
+sd_com3:
+		subq.l		#1,d2
+		bge			sd_com_loop
+		bsr			warten_10us
+		bset.b		#6,(a1)
+		bset.b		#0,(a1)
+		bsr			warten_200us
+		rts
+sd_clk:
+		tst.b		0xfffff700
+		tst.b		0xfffff700
+		bset.b		#2,(a1)
+		tst.b		0xfffff700
+		tst.b		0xfffff700
+		move.b		(a2),d3
+		tst.b		0xfffff700
+		bclr.b		#2,(a1)
+		rts
+
+sd_15clk:
+		move		#15,d0
+		bra			sd_16clk
+sd_16clk:
+		moveq		#16,d0
+sd_16clk1:
+		bsr			sd_clk
+		subq.l		#1,d0
+		bne			sd_16clk1
+		bsr			warten_10us
+		rts
+// warteschleife ca. 20ms  
+warten_20ms:  		
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#700000,d6
+  		bra			warten_loop
+// warteschleife ca. 200us  
+warten_200us: 
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#7000,d6
+  		bra			warten_loop
+// warteschleife ca. 10us  
+warten_10us:  		
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#333,d6
+warten_loop:
+		move.l		(a0),d1
+		sub.l		d0,d1
+		add.l		d6,d1
+		bpl			warten_loop
+		move.l		(sp)+,d0
+		move.l		(sp)+,d1
+		move.l		(sp)+,d6
+		move.l		(sp)+,a0
+		rts;
+/********************************************************************/
+#define		cmd_reg		(0x1d)
+#define		status_reg	(0x1d)
+#define		seccnt		(0x09)
+
+ide_test:
+		lea			0xfff00040,a0
+		lea			0xc00000,a1
+		move.b		#0xec,cmd_reg(a0)		//identify devcie cmd
+		bsr			wait_int
+		bsr			ds_rx
+// read sector normal		
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x20,cmd_reg(a0)		// read cmd
+		bsr			wait_int
+		bsr			ds_rx
+
+// write testpattern sector
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x30,cmd_reg(a0)		// write cmd
+		bsr			drq_wait
+// write pattern
+		move.l		#256,d0
+ide_test_loop3:		
+		move.w		#0xa55a,(a0)
+		subq.l		#1,d0
+		bne			ide_test_loop3
+		bsr			wait_int
+// read testpattern sector
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x20,cmd_reg(a0)		// read
+		bsr			wait_int
+		bsr			ds_rx
+// sector restauriern
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x30,cmd_reg(a0)		// write
+		lea			-0x400(a1),a1			// vorletzer
+		bsr			drq_wait
+		bsr			ds_tx
+		bsr			wait_int
+// fertig und zur<EFBFBD>ck		
+		nop
+		rts
+// wait auf int
+wait_int:
+		move.b		0xfffffa01,d0
+		btst		#5,d0
+		bne			wait_int
+		move.b		status_reg(a0),d0
+		rts
+// wait auf drq
+drq_wait:
+		move.b		status_reg(a0),d0
+		btst		#3,d0
+		beq			drq_wait
+		rts
+
+// 1 sector lesen word
+ds_rx:
+		move.l		#256,d0
+ds_rx_loop:		
+		move.w		(a0),(a1)+
+		subq.l		#1,d0
+		bne			ds_rx_loop
+		rts
+// 1 sector lesen long
+ds_rxl:
+		move.l		#128,d0
+ds_rxl_loop:		
+		move.l		(a0),(a1)+
+		subq.l		#1,d0
+		bne			ds_rxl_loop
+		rts
+// 1 sector schreiben word
+ds_tx:
+		move.l		#256,d0
+ds_tx_loop:		
+		move.w		(a1)+,(a0)
+		subq.l		#1,d0
+		bne			ds_tx_loop
+		rts
+// 1 sector schreiben word
+ds_txl:
+		move.l		#128,d0
+ds_txl_loop:		
+		move.l		(a1)+,(a0)
+		subq.l		#1,d0
+		bne			ds_txl_loop
+		rts
+// warteschleife ca. 20ms  
+warten_20ms:  		
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#700000,d6
+  		bra			warten_loop
+// warteschleife ca. 200us  
+warten_200us: 
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#7000,d6
+  		bra			warten_loop
+// warteschleife ca. 10us  
+warten_10us:  		
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#333,d6
+warten_loop:
+		move.l		(a0),d1
+		sub.l		d0,d1
+		add.l		d6,d1
+		bpl			warten_loop
+		move.l		(sp)+,d0
+		move.l		(sp)+,d1
+		move.l		(sp)+,d6
+		move.l		(sp)+,a0
+		rts;
+/********************************************************************/

BaS_codewarrior/firebeeV1/sources/startcf.c

@@ -0,0 +1,83 @@
+/*
+ *    CF_Startup.c - Default init/startup/termination routines for
+ *                     Embedded Metrowerks C++
+ *
+ *    Copyright <20> 1993-1998 Metrowerks, Inc. All Rights Reserved.
+ *    Copyright <20> 2005 Freescale semiConductor Inc. All Rights Reserved.
+ *
+ *
+ *    THEORY OF OPERATION
+ *
+ *    This version of thestartup code is intended for linker relocated
+ *    executables.  The startup code will assign the stack pointer to
+ *    __SP_INIT, assign the address of the data relative base address
+ *    to a5, initialize the .bss/.sbss sections to zero, call any
+ *    static C++ initializers and then call main.  Upon returning from
+ *    main it will call C++ destructors and call exit to terminate.
+ */
+
+#ifdef __cplusplus
+#pragma cplusplus off
+#endif
+#pragma PID off
+#pragma PIC off
+
+#include "MCF5475.h"
+
+
+	/* imported data */
+
+extern unsigned long far _SP_INIT, _SDA_BASE;
+extern unsigned long far _START_BSS, _END_BSS;
+extern unsigned long far _START_SBSS, _END_SBSS;
+extern unsigned long far __DATA_RAM, __DATA_ROM, __DATA_END;
+extern unsigned long far __Bas_base;
+
+extern unsigned long far __SUP_SP,__BOOT_FLASH;
+extern unsigned long far rt_mbar;
+
+	/* imported routines */
+
+extern int BaS(int, char **);
+
+	/* exported routines */
+extern void __initialize_hardware(void);
+extern void init_slt(void);
+
+
+void _startup(void)
+{
+	asm
+{
+	bra			warmstart
+	jmp			__BOOT_FLASH + 8					// ist zugleich reset vector 
+	/* disable interrupts */
+warmstart:	
+// disable interrupts 
+	move.w     	#0x2700,sr
+// Initialize MBAR
+	MOVE.L		#__MBAR,D0
+	MOVEC		D0,MBAR
+	move.l		d0,rt_mbar
+// mmu off   	
+	move.l		#__MMUBAR+1,d0	
+	movec		d0,MMUBAR				//mmubar setzen
+	clr.l		d0
+	move.l		d0,MCF_MMU_MMUCR		// mmu off
+        /* Initialize RAMBARs: locate SRAM and validate it */ \
+   	move.l 		#__RAMBAR0 + 0x7,d0		// supervisor only
+   	movec      	d0,RAMBAR0
+   	move.l 		#__RAMBAR1 + 0x1,d0		// on for all
+   	movec      	d0,RAMBAR1
+   	
+// STACKPOINTER AUF ENDE SRAM1
+	lea 			__SUP_SP,a7
+	
+// instruction cache on
+	move.l		#0x000C8100,d0
+ 	movec		d0,cacr
+ 	nop
+// initialize any hardware specific issues 
+	bra          __initialize_hardware   
+}
+}

BaS_codewarrior/firebeeV1/sources/startcf.h

@@ -0,0 +1,47 @@
+/******************************************************************************
+  FILE    : startcf.h
+  PURPOSE : startup code for ColdFire
+  LANGUAGE: C
+
+
+  Notes:
+        1) Default entry point is _startup. 
+           . disable interrupts
+           . the SP is set to __SP_AFTER_RESET
+           . SP must be initialized to valid memory 
+             in case the memory it points to is not valid using MEMORY_INIT macro
+        2) __initialize_hardware is called. Here you can initialize memory and some peripherics
+           at this point global variables are not initialized yet
+        3) After __initialize_hardware memory is setup; initialize SP to _SP_INIT and perform 
+           needed initialisations for the language (clear memory, data rom copy).
+        4) void __initialize_system(void); is called
+           to allow additional hardware initialization (UART, GPIOs, etc...)
+        5) Jump to main 
+
+*/
+/********************************************************************************/
+
+#define cf_stack
+
+//#define ii_on
+#define halten
+#define halten_dbcc
+#define halten_and
+#define halten_add
+#define halten_sub
+#define halten_or
+#define halten_op
+#define halten_opc
+#define halten_movem
+#define halten_lea
+#define halten_shift
+#define halten_move
+#define halten_exg
+#define halten_movep
+#define halten_ewf
+
+#define DIP_SWITCH		(*(vuint8 *)(&__MBAR[0xA2C]))
+#define DIP_SWITCHa		___MBAR + 0xA2C
+
+#define sca_page_ID 	6
+

BaS_codewarrior/firebeeV1/sources/supervisor.s

@@ -1,27 +1,25 @@
-/*
- *   user/supervisor handler
- */
+/********************************************************/
+/*   user/supervisor handler
+/********************************************************/
 
-#include "startcf.h"
-#define cf_stack
+.include "startcf.h"
 
 .extern _rt_cacr;
 .extern _rt_mod;
 .extern _rt_ssp;
 .extern _rt_usp;
 .extern ___MMUBAR
-.extern _flush_and_invalidate_caches
 
 /* Register read/write macros */
-#define MCF_MMU_MMUCR	__MMUBAR
-#define MCF_MMU_MMUOR	__MMUBAR+0x04
-#define MCF_MMU_MMUSR	__MMUBAR+0x08
-#define MCF_MMU_MMUAR	__MMUBAR+0x10
-#define MCF_MMU_MMUTR	__MMUBAR+0x14
-#define MCF_MMU_MMUDR	__MMUBAR+0x18
+#define MCF_MMU_MMUCR            			___MMUBAR
+#define MCF_MMU_MMUOR                       ___MMUBAR+0x04
+#define MCF_MMU_MMUSR                       ___MMUBAR+0x08
+#define MCF_MMU_MMUAR                       ___MMUBAR+0x10
+#define MCF_MMU_MMUTR                       ___MMUBAR+0x14
+#define MCF_MMU_MMUDR                       ___MMUBAR+0x18
 
-.global _privileg_violation
-.global cpusha
+.public _privileg_violation
+.public cpusha
 
 .text
 _privileg_violation:
@@ -35,7 +33,7 @@ _privileg_violation:
 	lea			_rt_mod,a0		// zugriff setzen
 	tst.b		(a0)			// vom rt_supervisormodus?
 	bne			pv_work			// ja->
-// tats<EFBFBD>chlich privileg violation
+// tatsächlich privileg violation
 	mov3q.l		#-1,(a0)		// sr_mod setzen
 	move.l		usp,a5			// usp holen
 	move.l		a5,8(a0)		// sichern
@@ -54,7 +52,7 @@ _privileg_violation:
 	move.l		12(a0),a5		// rt_vbr
 	lea			0x18(a5),a5		// vector
 	move.l		(a5),16(a7)		// vector privileg violation
-	movem.l		(a7),d0/a0/a5	// register zur<EFBFBD>ck
+	movem.l		(a7),d0/a0/a5	// register zurück
 	lea			12(a7),a7
 	rte
 // privileg violation
@@ -151,7 +149,7 @@ pv_a7_usp:		move.l 4(a0),a5		// rt_ssp -> a5
 pv_ax_usp:
 	move.l		a5,8(a0)			// usp -> rt_usp
 	addq.l		#2,16(a7)			// next
-	movem.l		(a7),d0/a0/a5		// register zur<EFBFBD>ck
+	movem.l		(a7),d0/a0/a5		// register zurück
 	lea			12(a7),a7
 	rte
 // usp->a0
@@ -177,7 +175,7 @@ pv_usp_a6:
 	move.l		a5,a6
 pv_usp_ax:
 	addq.l		#2,16(a7)		// next
-	movem.l		(a7),d0/a0/a5	// register zur<EFBFBD>ck
+	movem.l		(a7),d0/a0/a5	// register zurück
 	lea			12(a7),a7
 	rte
 // rte
@@ -198,7 +196,7 @@ pv_rte:
 	move.l		8(a0),a5		// rt_usp holen
 pv_rte_sup:
 	move.l		a5,usp			// usp setzen
-	movem.l		(a7),d0/a0/a5	// register zur<EFBFBD>ck
+	movem.l		(a7),d0/a0/a5	// register zurück
 	lea			12(a7),a7
 	rte
 // stop
@@ -243,7 +241,7 @@ stop7:
 	stop		#0x2700
 stop_weiter:
 	addq.l		#4,16(a7)		// next 
-	movem.l		(a7),d0/a0/a5	// register zur<EFBFBD>ck
+	movem.l		(a7),d0/a0/a5	// register zurück
 	lea			12(a7),a7
 	rte
 // movec ???????
@@ -337,7 +335,7 @@ pv_46:
 	move.b		1(a5),d0	
 	cmp.b		#0xfc,d0		//#d16->sr
 	beq			im_sr			//ja->
-//move dx->sr (sr und rt_mod ist supervisor sonst w<EFBFBD>re es privileg violation
+//move dx->sr (sr und rt_mod ist supervisor sonst wäre es privileg violation
 	cmp.b		#0xc0,d0		//d0->sr?
 	bne			d1_sr			//nein->
 	move.w		2(a7),d0		//hier ist d0 gesichert
@@ -391,7 +389,7 @@ pv_set_sr_end:
 	move.l		a5,usp			// setzen
 pv_sre2:
 	move.w		d0,14(a7)		// sr setzen
-	movem.l		(a7),d0/a0/a5	// register zur<EFBFBD>ck
+	movem.l		(a7),d0/a0/a5	// register zurück
 	lea			12(a7),a7
 	rte
 // code 0x40xx  *****************************************
@@ -444,7 +442,7 @@ nsr_d7:
 	halt
 sr_dx_end:
 	addq.l		#2,16(a7)		// next 
-	movem.l		(a7),d0/a0/a5	// register zur<EFBFBD>ck
+	movem.l		(a7),d0/a0/a5	// register zurück
 	lea			12(a7),a7
 	rte
 // strldsr
@@ -466,7 +464,7 @@ pv_f4:
 	lea			12(a7),a7
 	rte
 pv_intouch:
-	intouch		a0
+	intouch		(a0)
 	movem.l		(a7),d0/a0/a5
 	lea			12(a7),a7
 	rte
@@ -556,10 +554,32 @@ pv_f_d16pc:
 //*****************************************************
 cpusha:	 
  	lea			-16(a7),a7
-	movem.l		d0-d1/a0-a1,(a7)	// backup C trash registers
-	jsr			_flush_and_invalidate_caches
-	movem.l		(a7),d0-d1/a0-a1	// restore C trash registers
- 	lea			16(a7),a7
+	movem.l		d0-d2/a0,(a7)		// register sichern
+	move		sr,d2
+	nop
+	move		#0x2700,sr			// no interrupts
+
+	clr.l		d0
+	clr.l		d1
+	move.l		d0,a0
+cfa_setloop:
+	cpushl		bc,(a0)				// flush
+	lea			0x10(a0),a0			// index+1
+	addq.l		#1,d1				// index+1
+	cmpi.w		#512,d1				// alle sets?
+	bne			cfa_setloop			// nein->
+	clr.l		d1
+	addq.l		#1,d0
+	move.l		d0,a0
+	cmpi.w		#4,d0				// all ways?
+	bne			cfa_setloop			// nein->
+	nop
+	move.l		_rt_cacr,d0			// holen
+	movec		d0,cacr				// setzen
+	move.w		d2,sr				// alte interrupt maske
+	movem.l		(a7),d0-d2/a0		// register zurück
+	lea			16(a7),a7
+
 	rts	
 //*******************************************************33
 

BaS_codewarrior/firebeeV1/sources/sysinit.c

@@ -0,0 +1,836 @@
+/*
+ * File:		sysinit.c
+ * Purpose:		Power-on Reset configuration of the COLDARI board.
+ *
+ * Notes: 
+ *
+ */
+#include "MCF5475.h"
+#include "startcf.h"
+
+extern unsigned long far __VRAM;
+extern unsigned long far __Bas_base;
+extern unsigned long far BaS;
+extern unsigned long far __BOOT_FLASH[]; 
+extern int copy_end();
+extern int warte_10us();
+extern int warte_1ms();
+extern int warte_10ms();
+extern int warte_50us();
+
+extern unsigned long far rt_cacr;
+
+/********************************************************************/
+// init SLICE TIMER 0 
+// all  = 32.538 sec = 30.736mHz
+// BYT0 = 127.1ms/tick = 7.876Hz   offset 0
+// BYT1 = 496.5us/tick = 2.014kHz  offset 1
+// BYT2 = 1.939us/tick = 515.6kHz  offset 2
+// BYT3 = 7.576ns/tick = 132.00MHz offset 3
+// count down!!! 132MHz!!!
+/********************************************************************/
+
+void init_slt(void)
+{
+	asm
+	{
+		lea 		MCF_SLT0_STCNT,a0
+		move.l		#0xffffffff,(a0)
+		lea 		MCF_SLT0_SCR,a0
+		move.b		#0x05,(a0)
+			
+	}
+		MCF_PSC0_PSCTB_8BIT = 'SLT ';
+		MCF_PSC0_PSCTB_8BIT = 'OK! ';
+		MCF_PSC0_PSCTB_8BIT = 0x0a0d;
+}
+
+/********************************************************************/
+// init GPIO ETC.
+/********************************************************************/
+
+void init_gpio(void)
+{
+
+
+// PAD REGISTER P.S.:FBCTL UND FBCS WERDEN RICHTIG GESETZT BEIM RESET 
+	MCF_PAD_PAR_DMA 		= 0b11111111;			// NORMAL ALS DREQ DACK
+	MCF_PAD_PAR_FECI2CIRQ 	= 0b1111001111001111;	// FEC0 NORMAL, FEC1 ALS I/O, I2C, #INT5..6
+	MCF_PAD_PAR_PCIBG 		= 0b0000001000111111;	// #PCI_BG4=#TBST,#PIC_BG3=I/O,#PCI_BG2..0=NORMAL
+	MCF_PAD_PAR_PCIBR 		= 0b0000001000111111;	// #PCI_BR4=#INT4,#PIC_BR3=INPUT,#PCI_BR2..0=NORMAL
+	MCF_PAD_PAR_PSC3		= 0b00001100;			// PSC3=TX,RX CTS+RTS=I/O
+	MCF_PAD_PAR_PSC1		= 0b11111100;			// PSC1 NORMAL SERIELL
+	MCF_PAD_PAR_PSC0		= 0b11111100;			// PSC0 NORMAL SERIELL
+	MCF_PAD_PAR_DSPI		= 0b0001111111111111;	// DSPI NORMAL
+	MCF_PAD_PAR_TIMER		= 0b00101101;			// TIN3..2=#IRQ3..2;TOUT3..2=NORMAL
+// ALLE OUTPUTS NORMAL LOW
+
+// ALLE DIR NORMAL INPUT = 0
+	MCF_GPIO_PDDR_FEC1L		= 0b00011110;			// OUT: 4=LED,3=PRG_DQ0,2=#FPGA_CONFIG,1=PRG_CLK(FPGA)	
+
+}
+
+/********************************************************************/
+// init seriel
+/********************************************************************/
+
+void init_seriel(void)
+{
+		
+// PSC0: SER1 ----------
+ 		MCF_PSC0_PSCSICR = 0;		// UART
+		MCF_PSC0_PSCCSR = 0xDD;
+		MCF_PSC0_PSCCTUR = 0x00;	 
+		MCF_PSC0_PSCCTLR = 36;		// BAUD RATE = 115200
+		MCF_PSC0_PSCCR = 0x20;
+		MCF_PSC0_PSCCR = 0x30;
+		MCF_PSC0_PSCCR = 0x40;
+		MCF_PSC0_PSCCR = 0x50;
+		MCF_PSC0_PSCCR = 0x10;
+		MCF_PSC0_PSCIMR = 0x8700;
+		MCF_PSC0_PSCACR = 0x03;
+		MCF_PSC0_PSCMR1= 0xb3;
+		MCF_PSC0_PSCMR2= 0x07;
+		MCF_PSC0_PSCRFCR = 0x0F;
+		MCF_PSC0_PSCTFCR = 0x0F;
+		MCF_PSC0_PSCRFAR = 0x00F0;
+		MCF_PSC0_PSCTFAR = 0x00F0;
+		MCF_PSC0_PSCOPSET = 0x01;
+		MCF_PSC0_PSCCR = 0x05;
+// PSC3: PIC ----------
+ 		MCF_PSC3_PSCSICR = 0;		// UART
+		MCF_PSC3_PSCCSR = 0xDD;
+		MCF_PSC3_PSCCTUR = 0x00;	 
+		MCF_PSC3_PSCCTLR = 36;		// BAUD RATE = 115200
+		MCF_PSC3_PSCCR = 0x20;
+		MCF_PSC3_PSCCR = 0x30;
+		MCF_PSC3_PSCCR = 0x40;
+		MCF_PSC3_PSCCR = 0x50;
+		MCF_PSC3_PSCCR = 0x10;
+		MCF_PSC3_PSCIMR = 0x0200;	// receiver interrupt enable
+		MCF_PSC3_PSCACR = 0x03;
+		MCF_PSC3_PSCMR1= 0xb3;
+		MCF_PSC3_PSCMR2= 0x07;
+		MCF_PSC3_PSCRFCR = 0x0F;
+		MCF_PSC3_PSCTFCR = 0x0F;
+		MCF_PSC3_PSCRFAR = 0x00F0;
+		MCF_PSC3_PSCTFAR = 0x00F0;
+		MCF_PSC3_PSCOPSET = 0x01;
+		MCF_PSC3_PSCCR = 0x05;
+		MCF_INTC_ICR32 = 0x3F;		//MAXIMALE PRIORITY/**********/
+
+		MCF_PSC0_PSCTB_8BIT = 0x0a0d;
+		MCF_PSC0_PSCTB_8BIT = 'SERI';
+		MCF_PSC0_PSCTB_8BIT = 'AL O';
+		MCF_PSC0_PSCTB_8BIT = 'K!  ';
+		MCF_PSC0_PSCTB_8BIT = 0x0a0d;	
+}
+/********************************************************************/
+   /* Initialize DDR DIMMs on the EVB board */
+/********************************************************************/
+   /*
+    * Check to see if the SDRAM has already been initialized
+    * by a run control tool
+    */
+
+
+void init_ddram(void)
+{
+ 		MCF_PSC0_PSCTB_8BIT = 'DDRA';
+  if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF))
+   {
+
+	/* Basic configuration and initialization */
+	MCF_SDRAMC_SDRAMDS 	= 0x000002AA;	// SDRAMDS configuration
+	MCF_SDRAMC_CS0CFG 	= 0x0000001A;   // SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
+	MCF_SDRAMC_CS1CFG 	= 0x0800001A;   // SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
+	MCF_SDRAMC_CS2CFG 	= 0x1000001A;   // SDRAM CS2 configuration (128Mbytes 1000_0000 - 07FF_FFFF)
+	MCF_SDRAMC_CS3CFG 	= 0x1800001A;   // SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
+//  	MCF_SDRAMC_SDCFG1 	= 0x53722938;   // SDCFG1
+	MCF_SDRAMC_SDCFG1 	= 0x73622830;   // SDCFG1
+//  	MCF_SDRAMC_SDCFG2 	= 0x24330000;   // SDCFG2
+	MCF_SDRAMC_SDCFG2 	= 0x46770000;   // SDCFG2
+//   	MCF_SDRAMC_SDCR 	= 0xE10F0002;   // SDCR + IPALL
+   	MCF_SDRAMC_SDCR 	= 0xE10D0002;   // SDCR + IPALL
+   	MCF_SDRAMC_SDMR 	= 0x40010000;   // SDMR (write to LEMR)
+//   	MCF_SDRAMC_SDMR 	= 0x05890000;   // SDRM (write to LMR)
+   	MCF_SDRAMC_SDMR 	= 0x048D0000;   // SDRM (write to LMR)
+//   	MCF_SDRAMC_SDCR 	= 0xE10F0002;   // SDCR + IPALL
+   	MCF_SDRAMC_SDCR 	= 0xE10D0002;   // SDCR + IPALL
+//   	MCF_SDRAMC_SDCR 	= 0xE10F0004;   // SDCR + IREF (first refresh)
+   	MCF_SDRAMC_SDCR 	= 0xE10D0004;   // SDCR + IREF (first refresh)
+//   	MCF_SDRAMC_SDCR 	= 0xE10F0004;   // SDCR + IREF (second refresh)
+  	MCF_SDRAMC_SDCR 	= 0xE10D0004;   // SDCR + IREF (second refresh)
+///   	MCF_SDRAMC_SDMR 	= 0x01890000;   // SDMR (write to LMR)
+   	MCF_SDRAMC_SDMR 	= 0x008D0000;   // SDMR (write to LMR)
+//   	MCF_SDRAMC_SDCR 	= 0x710F0F00;   // SDCR (lock SDMR and enable refresh)
+   	MCF_SDRAMC_SDCR 	= 0x710D0F00;   // SDCR (lock SDMR and enable refresh)
+   }
+		MCF_PSC0_PSCTB_8BIT = 'M OK';
+		MCF_PSC0_PSCTB_8BIT = '!   ';
+		MCF_PSC0_PSCTB_8BIT = 0x0a0d;
+}
+/********************************************************************/
+	/* init FB_CSx /*
+/********************************************************************/
+void init_fbcs()
+{
+		MCF_PSC0_PSCTB_8BIT = 'FBCS';
+		/* Flash */
+ 	MCF_FBCS0_CSAR 	= 0xE0000000;						// FLASH ADRESS
+ 	MCF_FBCS0_CSCR 	= 0x00001180;						// 16 bit 4ws aa
+ 	MCF_FBCS0_CSMR 	= 0x007F0001;					 	// 8MB on 
+		
+	MCF_FBCS1_CSAR	= 0xFFF00000;						// ATARI I/O ADRESS
+	MCF_FBCS1_CSCR 	= MCF_FBCS_CSCR_PS_16 				// 16BIT PORT 
+					| MCF_FBCS_CSCR_WS(8)				// DEFAULT 8WS
+ 					| MCF_FBCS_CSCR_AA;					// AA 
+	MCF_FBCS1_CSMR 	= (MCF_FBCS_CSMR_BAM_1M 
+					| MCF_FBCS_CSMR_V);
+
+	MCF_FBCS2_CSAR	= 0xF0000000;						// NEUER I/O ADRESS-BEREICH
+	MCF_FBCS2_CSCR 	= MCF_FBCS_CSCR_PS_32				// 32BIT PORT
+					| MCF_FBCS_CSCR_WS(8)				// DEFAULT 4WS
+					| MCF_FBCS_CSCR_AA;					// AA 
+	MCF_FBCS2_CSMR 	= (MCF_FBCS_CSMR_BAM_128M 			// F000'0000-F7FF'FFFF
+					| MCF_FBCS_CSMR_V);
+ 	
+	MCF_FBCS3_CSAR	= 0xF8000000;						// NEUER I/O ADRESS-BEREICH
+	MCF_FBCS3_CSCR 	= MCF_FBCS_CSCR_PS_16				// 16BIT PORT
+					| MCF_FBCS_CSCR_AA;					// AA 
+	MCF_FBCS3_CSMR 	= (MCF_FBCS_CSMR_BAM_64M 			// F800'0000-FBFF'FFFF
+					| MCF_FBCS_CSMR_V);
+ 
+	MCF_FBCS4_CSAR	= 0x40000000;						// VIDEO RAM BEREICH, #FB_CS3 WIRD NICHT BEN<45>TZT, DECODE DIREKT AUF DEM FPGA
+	MCF_FBCS4_CSCR 	= MCF_FBCS_CSCR_PS_32				// 32BIT PORT
+					| MCF_FBCS_CSCR_BSTR				// BURST READ ENABLE
+					| MCF_FBCS_CSCR_BSTW;				// BURST WRITE ENABLE
+	MCF_FBCS4_CSMR 	= (MCF_FBCS_CSMR_BAM_1G 			// 4000'0000-7FFF'FFFF
+					| MCF_FBCS_CSMR_V);
+
+		MCF_PSC0_PSCTB_8BIT = ' OK!';
+		MCF_PSC0_PSCTB_8BIT = 0x0a0d;
+}
+
+/********************************************************************/
+	/* FPGA LADEN /*
+/********************************************************************/
+
+
+void init_fpga(void)
+{
+
+		MCF_PSC0_PSCTB_8BIT = 'FPGA';
+asm
+	{
+  		lea			MCF_GPIO_PODR_FEC1L,a1				// register adresse:write
+  		lea			MCF_GPIO_PPDSDR_FEC1L,a2			// reads
+  		bclr		#1,(a1)								// clk auf low
+		bclr		#2,(a1)								// #config=low 
+test_nSTATUS:
+		btst		#0,(a2)								// nSTATUS==0
+		bne			test_nSTATUS						// nein->
+		btst		#5,(a2)								// conf done==0
+		bne			test_nSTATUS						// nein->
+		jsr			warte_10us							// warten
+		bset		#2,(a1)								// #config=high
+		jsr			warte_10us							// warten
+test_STATUS:
+		btst		#0,(a2)								// status high?
+		beq			test_STATUS							// nein->
+		jsr			warte_10us							// warten
+
+  		lea			0xE0700000,a0						// startadresse fpga daten
+word_send_loop:
+		cmp.l		#0xE0800000,a0
+		bgt			fpga_error
+		move.b		(a0)+,d0							// 32 bit holen
+		moveq		#8,d1								// 32 bit ausgeben
+bit_send_loop:
+		lsr.l		#1,d0								// bit rausschieben
+		bcs			bit_is_1							
+		bclr		#3,(a1)
+		bra			bit_send
+bit_is_1:
+		bset		#3,(a1)
+bit_send:
+		bset		#1,(a1)								// clock=high
+		bclr		#1,(a1)								// clock=low
+		subq.l		#1,d1
+		bne			bit_send_loop						// wiederholen bis fertig
+		btst		#5,(a2)								// fpga fertig, conf_done=high?
+		beq			word_send_loop						// nein, next word->
+		move.l		#4000,d1
+overclk:
+		bset		#1,(a1)								// clock=high
+		nop
+		bclr		#1,(a1)								// clock=low
+		subq.l		#1,d1
+		bne			overclk								// weiter bis fertig
+  		bra			init_fpga_end
+
+//---------------------------------------------------------
+wait_pll:
+  		lea			MCF_SLT0_SCNT,a3
+  		move.l		(a3),d0
+  		move.l		#100000,d6			// ca 1ms
+wait_pll_loop:
+		tst.w		(a1)
+		bpl			wait_pll_ok
+		move.l		(a3),d1
+		sub.l		d0,d1
+		add.l		d6,d1
+		bpl			wait_pll_loop
+wait_pll_ok:
+		rts
+// fertig
+fpga_error:
+ 	}
+		MCF_PSC0_PSCTB_8BIT = ' NOT';
+init_fpga_end:
+		MCF_PSC0_PSCTB_8BIT = ' OK!';
+		MCF_PSC0_PSCTB_8BIT = 0x0a0d;
+
+// init pll		
+		MCF_PSC0_PSCTB_8BIT = 'PLL ';
+asm
+{
+		lea		0xf0000600,a0
+		lea		0xf0000800,a1
+		bsr		wait_pll
+		move.w	#27,0x48(a0)		// loopfilter r
+		bsr		wait_pll
+		move.w	#1,0x08(a0)			// charge pump I
+		bsr		wait_pll
+		move.w	#12,0x0(a0)			// N counter high = 12
+		bsr		wait_pll
+		move.w	#12,0x40(a0)		// N counter low = 12
+		bsr		wait_pll
+		move.w	#1,0x114(a0)		// ck1 bypass
+		bsr		wait_pll
+		move.w	#1,0x118(a0)		// ck2 bypass
+		bsr		wait_pll
+		move.w	#1,0x11c(a0)		// ck3 bypass
+		bsr		wait_pll
+		move.w	#1,0x10(a0)			// ck0 high = 1
+		bsr		wait_pll
+		move.w	#1,0x50(a0)			// ck0 low	= 1
+		
+		bsr		wait_pll
+		move.w	#1,0x144(a0)		// M odd division
+		bsr		wait_pll
+		move.w	#1,0x44(a0)			// M low = 1
+
+		bsr		wait_pll
+		move.w	#145,0x04(a0)		// M high = 145 = 146MHz
+
+		bsr		wait_pll
+		clr.b	(a1)				// set
+}
+		MCF_PSC0_PSCTB_8BIT = 'SET!';
+		MCF_PSC0_PSCTB_8BIT = 0x0a0d;
+}		
+
+/********************************************************************/
+	/* INIT VIDEO DDR RAM /*
+/********************************************************************/
+
+void init_video_ddr(void)
+{
+	asm
+	{
+
+// init video ram
+		moveq.l	#0xB,d0
+		move.w	d0,0xF0000400				//set cke=1, cs=1 config=1
+		nop
+		lea		__VRAM,a0					//zeiger auf video ram
+		nop
+		move.l	#0x00050400,(a0)			//IPALL
+		nop
+		move.l	#0x00072000,(a0)			//load EMR pll on
+		nop
+		move.l	#0x00070122,(a0)			//load MR: reset pll, cl=2 BURST=4lw
+		nop
+		move.l	#0x00050400,(a0)			//IPALL
+		nop
+		move.l	#0x00060000,(a0)			//auto refresh
+		nop
+		move.l	#0x00060000,(a0)			//auto refresh
+		nop
+		move.l	#0000070022,(a0)			//load MR dll on
+		nop
+		move.l	#0x01070002,d0				// fifo on, refresh on, ddrcs und cke on, video dac on,
+		move.l	d0,0xf0000400
+	}
+}
+
+/********************************************************************/
+	/* video mit aufl<66>sung 1280x1000 137MHz /*
+/********************************************************************/
+
+void video_1280_1024(void)
+{
+extern int wait_pll;
+
+	asm
+	{
+
+
+// SPEICHER F<>LLEM
+
+//testmuster 1
+		lea		__VRAM,a2
+		lea		__VRAM+0x600000,a3
+		clr.l	d0
+		move.l	#0x1000102,d1
+loop5:	move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		add.l	d1,d0
+flo6:	cmp.l	a2,a3
+		bgt		loop5
+
+// screen setzen
+//horizontal 1280
+		lea		0xffff8282,a0
+		move.w	#1800,(a0)+
+		move.w	#1380,(a0)+
+		move.w	#99,(a0)+
+		move.w	#100,(a0)+
+		move.w	#1379,(a0)+
+		move.w	#1500,(a0)
+//vertical 1024
+		lea		0xffff82a2,a0
+		move.w	#1150,(a0)+
+		move.w	#1074,(a0)+
+		move.w	#49,(a0)+
+		move.w	#50,(a0)+
+		move.w	#1073,(a0)+
+		move.w	#1100,(a0)+
+// acp video on		
+		move.l	#0x01070207,d0
+		move.l	d0,0xf0000400
+		
+		
+// clut setzen
+		lea		0xf0000000,a0
+		move.l	#0xffffffff,(a0)+
+		move.l	#0xff,(a0)+
+		move.l	#0xff00,(a0)+
+		move.l	#0xff0000,(a0) 
+		
+//		halt
+		
+	}
+
+}
+/********************************************************************/
+	/* INIT PCI /*
+/********************************************************************/
+
+#define	 PCI_MEMORY_OFFSET	(0x80000000)
+#define	 PCI_MEMORY_SIZE	(0x40000000)
+#define	 PCI_IO_OFFSET		(0xD0000000)
+#define	 PCI_IO_SIZE		(0x10000000)
+
+
+void init_PCI(void)
+{
+
+		MCF_PSC0_PSCTB_8BIT = 'PCI ';
+asm
+	{
+ 	// Setup the arbiter
+		move.l #MCF_PCIARB_PACR_INTMPRI \
+		 + MCF_PCIARB_PACR_EXTMPRI(0x1F) \
+		 + MCF_PCIARB_PACR_INTMINTEN \
+		 + MCF_PCIARB_PACR_EXTMINTEN(0x1F),D0
+		move.l D0,MCF_PCIARB_PACR
+	// Setup burst parameters
+		move.l #MCF_PCI_PCICR1_CACHELINESIZE(4) + MCF_PCI_PCICR1_LATTIMER(32),D0
+		move.l D0,MCF_PCI_PCICR1
+		move.l #MCF_PCI_PCICR2_MINGNT(16) + MCF_PCI_PCICR2_MAXLAT(16),D0
+		move.l D0,MCF_PCI_PCICR2
+	// Turn on error signaling
+		move.l #MCF_PCI_PCIICR_TAE + MCF_PCI_PCIICR_IAE + MCF_PCI_PCIICR_REE + 32,D0
+		move.l D0,MCF_PCI_PCIICR
+		move.l #MCF_PCI_PCIGSCR_SEE,D0
+		or.l D0,MCF_PCI_PCIGSCR
+	// Configure Initiator Windows */
+		move.l #PCI_MEMORY_OFFSET + ((PCI_MEMORY_SIZE - 1) >> 8),D0
+		clr.w D0
+		move.l D0,MCF_PCI_PCIIW0BTAR // Initiator Window 0 Base / Translation Address Register
+	
+		move.l #PCI_IO_OFFSET+((PCI_IO_SIZE-1)>>8),D0
+		clr.w D0
+		move.l D0,MCF_PCI_PCIIW1BTAR // Initiator Window 1 Base / Translation Address Register
+
+		clr.l MCF_PCI_PCIIW2BTAR     // not used
+		
+		move.l #MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE + MCF_PCI_PCIIWCR_WINCTRL1_IO,D0
+		move.l D0,MCF_PCI_PCIIWCR	   // Initiator Window Configuration Register
+
+	/* Clear PCI Reset and wait for devices to reset */
+		move.l #~MCF_PCI_PCIGSCR_PR,D0
+		and.l D0,MCF_PCI_PCIGSCR
+	}
+
+		MCF_PSC0_PSCTB_8BIT = 'OK! ';
+		MCF_PSC0_PSCTB_8BIT = 0x0a0d;
+}
+/********************************************************************/
+	/* test UPC720101 (USB) /*
+/********************************************************************/
+
+void test_upd720101(void)
+{
+
+		MCF_PSC0_PSCTB_8BIT = 'NEC ';
+asm
+	{
+	// SELECT UPD720101 AD17
+		MOVE.L	#MCF_PCI_PCICAR_E+MCF_PCI_PCICAR_DEVNUM(17)+MCF_PCI_PCICAR_FUNCNUM(0)+MCF_PCI_PCICAR_DWORD(0),D0
+		MOVE.L	D0,MCF_PCI_PCICAR
+		LEA		PCI_IO_OFFSET,A0
+		MOVE.L	(A0),D1	
+		move.l	#0x33103500,d0
+		cmp.l	d0,d1
+		beq		nec_ok
+	}
+		MCF_PSC0_PSCTB_8BIT = 'NOT ';
+		goto	nec_not_ok;
+nec_ok:
+	asm 
+	{
+		MOVE.L	#MCF_PCI_PCICAR_E+MCF_PCI_PCICAR_DEVNUM(17)+MCF_PCI_PCICAR_FUNCNUM(0)+MCF_PCI_PCICAR_DWORD(57),D0
+		MOVE.L	D0,MCF_PCI_PCICAR
+		move.b	#0x20,(a0)
+	}
+nec_not_ok:
+	asm 
+	{
+		MOVE.L	#MCF_PCI_PCICAR_DEVNUM(17)+MCF_PCI_PCICAR_FUNCNUM(0)+MCF_PCI_PCICAR_DWORD(57),D0
+		MOVE.L	D0,MCF_PCI_PCICAR
+	}
+		MCF_PSC0_PSCTB_8BIT = 'OK! ';
+		MCF_PSC0_PSCTB_8BIT = 0x0a0d;
+}
+
+/********************************************************************/
+	/* TFP410 (vdi) einschalten /*
+/********************************************************************/
+
+void vdi_on(void)
+{
+ 		uint8  RBYT, DBYT;
+ 		int versuche, startzeit;
+
+ 		 
+		MCF_PSC0_PSCTB_8BIT = 'DVI ';
+		MCF_I2C_I2FDR = 0x3c;			// 100kHz standard
+		versuche = 0;
+loop_i2c:
+		if (versuche++>10) goto next;
+		MCF_I2C_I2ICR = 0x0;
+		MCF_I2C_I2CR = 0x0;
+		MCF_I2C_I2CR = 0xA;
+		RBYT = MCF_I2C_I2DR;
+		MCF_I2C_I2SR = 0x0;
+		MCF_I2C_I2CR = 0x0;
+		MCF_I2C_I2ICR = 0x01;
+ 
+		MCF_I2C_I2CR = 0xb0;
+		
+		MCF_I2C_I2DR = 0x7a;								// ADRESSE TFP410
+		while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;			// warten auf fertig
+		MCF_I2C_I2SR &= 0xfd;								// clear bit
+
+		if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) goto loop_i2c; // ack erhalten? -> nein
+
+tpf_410_ACK_OK:
+		MCF_I2C_I2DR = 0x00;								// SUB ADRESS 0
+		while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
+		MCF_I2C_I2SR &= 0xfd;
+
+		MCF_I2C_I2CR |= 0x4;								// repeat start
+	
+		MCF_I2C_I2DR = 0x7b;								// beginn read
+		while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;			// warten auf fertig
+		MCF_I2C_I2SR &= 0xfd;								// clear bit
+
+		if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) goto loop_i2c; // ack erhalten? -> nein
+
+
+		MCF_I2C_I2CR &= 0xef;								// switch to rx	
+		DBYT = MCF_I2C_I2DR;								// dummy read
+
+		while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
+		MCF_I2C_I2SR &= 0xfd;
+		
+		MCF_I2C_I2CR |= 0x08;								// txak=1
+
+		RBYT = MCF_I2C_I2DR;
+
+		while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
+		MCF_I2C_I2SR &= 0xfd;
+
+		MCF_I2C_I2CR = 0x80;								// stop
+		DBYT = MCF_I2C_I2DR;								// dummy read
+
+		if (RBYT!=0x4c) goto loop_i2c;
+		
+
+i2c_ok:
+		MCF_I2C_I2CR = 0x0;									// stop
+		MCF_I2C_I2SR = 0x0;									// clear sr
+		while((MCF_I2C_I2SR & MCF_I2C_I2SR_IBB)) ; 			// wait auf bus free
+		
+		MCF_I2C_I2CR = 0xb0;								// on tx master	
+		MCF_I2C_I2DR = 0x7A;
+		while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;			// warten auf fertig
+		MCF_I2C_I2SR &= 0xfd;								// clear bit
+
+		if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) goto loop_i2c; // ack erhalten? -> nein
+
+		MCF_I2C_I2DR = 0x08;								// SUB ADRESS 8
+		while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
+		MCF_I2C_I2SR &= 0xfd;
+
+		MCF_I2C_I2DR = 0xbf;								// ctl1: power on, T:M:D:S: enable
+		while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;			// warten auf fertig
+		MCF_I2C_I2SR &= 0xfd;								// clear bit
+
+		MCF_I2C_I2CR = 0x80;								// stop
+		DBYT = MCF_I2C_I2DR;								// dummy read
+		MCF_I2C_I2SR = 0x0;									// clear sr
+
+		while((MCF_I2C_I2SR & MCF_I2C_I2SR_IBB)) ; 			// wait auf bus free
+
+		MCF_I2C_I2CR = 0xb0;
+		MCF_I2C_I2DR = 0x7A;
+		while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;			// warten auf fertig
+		MCF_I2C_I2SR &= 0xfd;								// clear bit
+
+		if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) goto loop_i2c; // ack erhalten? -> nein
+
+		MCF_I2C_I2DR = 0x08;								// SUB ADRESS 8
+		while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
+		MCF_I2C_I2SR &= 0xfd;
+
+		MCF_I2C_I2CR |= 0x4;								// repeat start
+		MCF_I2C_I2DR = 0x7b;								// beginn read
+		while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;			// warten auf fertig
+		MCF_I2C_I2SR &= 0xfd;								// clear bit
+
+		if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) goto loop_i2c; // ack erhalten? -> nein
+
+		MCF_I2C_I2CR &= 0xef;								// switch to rx	
+
+		DBYT = MCF_I2C_I2DR;								// dummy read
+
+		while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
+		MCF_I2C_I2SR &= 0xfd;
+		
+		MCF_I2C_I2CR |= 0x08;								// txak=1
+
+		warte_50us();
+		RBYT = MCF_I2C_I2DR;
+
+		while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
+		MCF_I2C_I2SR &= 0xfd;
+
+		MCF_I2C_I2CR = 0x80;								// stop
+		DBYT = MCF_I2C_I2DR;								// dummy read
+
+		if (RBYT!=0xbf) goto loop_i2c;
+		
+		goto	dvi_ok;
+next:
+		MCF_PSC0_PSCTB_8BIT = 'NOT ';
+dvi_ok:
+		MCF_PSC0_PSCTB_8BIT = 'OK! ';
+		MCF_PSC0_PSCTB_8BIT = 0x0a0d;
+		MCF_I2C_I2CR = 0x0;									// i2c off
+}
+
+/********************************************************************/
+	/* AC97 /*
+/********************************************************************/
+void init_ac97(void)
+{
+// PSC2: AC97 ----------
+		int i,k,zm,x,va,vb,vc;
+
+		MCF_PSC0_PSCTB_8BIT = 'AC97';
+		MCF_PAD_PAR_PSC2 = MCF_PAD_PAR_PSC2_PAR_RTS2_RTS	// PSC2=TX,RX BCLK,CTS->AC'97
+						 | MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK
+						 | MCF_PAD_PAR_PSC2_PAR_TXD2
+ 						 | MCF_PAD_PAR_PSC2_PAR_RXD2;  
+ 		MCF_PSC2_PSCMR1 = 0x0;		 	 
+		MCF_PSC2_PSCMR2 = 0x0;	
+		MCF_PSC2_PSCIMR = 0x0300;	 	 
+		MCF_PSC2_PSCSICR = 0x03;		//AC97		 
+		MCF_PSC2_PSCRFCR = 0x0f000000;
+		MCF_PSC2_PSCTFCR = 0x0f000000;
+		MCF_PSC2_PSCRFAR = 0x00F0;
+		MCF_PSC2_PSCTFAR = 0x00F0;
+
+	for ( zm = 0; zm<100000; zm++)		// wiederholen bis synchron
+	{
+		MCF_PSC2_PSCCR = 0x20;
+		MCF_PSC2_PSCCR = 0x30;
+		MCF_PSC2_PSCCR = 0x40;
+		MCF_PSC2_PSCCR = 0x05;
+// MASTER VOLUME -0dB
+		MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
+		MCF_PSC2_PSCTB_AC97 = 0x02000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
+		for ( i = 2; i<13; i++ )
+		{
+			MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
+		}
+ //	 read register
+ 		MCF_PSC2_PSCTB_AC97 = 0xc0000000; //START SLOT1 + SLOT2, FIRST FRAME
+ 		MCF_PSC2_PSCTB_AC97 = 0x82000000; //SLOT1:master volume
+		for ( i = 2; i<13; i++ )
+		{
+			MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT2-12:RD REG ALLES 0
+		}
+		warte_50us();    
+		va = MCF_PSC2_PSCTB_AC97;
+		if ((va & 0x80000fff)==0x80000800)
+		{
+			vb = MCF_PSC2_PSCTB_AC97;
+ 			vc = MCF_PSC2_PSCTB_AC97;
+			if ((va & 0xE0000fff)==0xE0000800 & vb==0x02000000 & vc==0x00000000)
+			{
+				goto livo;
+			}
+		}
+	}
+	MCF_PSC0_PSCTB_8BIT = ' NOT';
+livo: 
+// AUX VOLUME ->-0dB 
+	MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
+	MCF_PSC2_PSCTB_AC97 = 0x16000000; //SLOT1:WR REG AUX VOLUME adr 0x16
+	MCF_PSC2_PSCTB_AC97 = 0x06060000; //SLOT1:VOLUME 
+	for ( i = 3; i<13; i++ )
+	{
+		MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
+	}
+ 
+// line in VOLUME +12dB
+	MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
+	MCF_PSC2_PSCTB_AC97 = 0x10000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
+	for ( i = 2; i<13; i++ )
+	{
+		MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
+	}
+// cd in VOLUME 0dB
+	MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
+	MCF_PSC2_PSCTB_AC97 = 0x12000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
+	for ( i = 2; i<13; i++ )
+	{
+		MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
+	}
+// mono out VOLUME 0dB
+	MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
+	MCF_PSC2_PSCTB_AC97 = 0x06000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
+	MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
+	for ( i = 3; i<13; i++ )
+	{
+		MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
+	}
+	MCF_PSC2_PSCTFCR |= MCF_PSC_PSCTFCR_WFR; //set EOF
+	MCF_PSC2_PSCTB_AC97 = 0x00000000; //last data
+
+ac97_end:
+	MCF_PSC0_PSCTB_8BIT = ' OK!';
+	MCF_PSC0_PSCTB_8BIT = 0x0a0d;
+
+}
+/********************************************************************/
+
+void __initialize_hardware(void)
+{
+_init_hardware:
+asm
+{
+	// instruction cache on
+	 	move.l		#0x000C8120,d0
+	 	move.l		d0,rt_cacr
+ 		movec		d0,cacr
+ 		nop
+}
+		init_gpio();
+   		init_seriel();
+		init_slt();
+		init_fbcs();
+		init_ddram();
+// Ports nicht initialisieren wenn DIP Switch 5 = on
+asm
+{
+		move.b	DIP_SWITCH,d0					// dip schalter adresse
+		btst.b	#6,d0
+		beq		not_init_ports
+}
+ 		init_PCI();		//pci braucht zeit
+ not_init_ports:
+		init_fpga();
+		init_video_ddr();
+ 		vdi_on();
+// Ports nicht initialisieren wenn DIP Switch 5 = on
+asm
+{
+		move.b	DIP_SWITCH,d0					// dip schalter adresse
+		btst.b	#6,d0
+		beq		not_init_ports2
+}
+  		test_upd720101();
+//  		video_1280_1024(); 
+  		init_ac97();
+not_init_ports2:
+
+asm
+{
+/*****************************************************/
+/* BaS kopieren 
+/*****************************************************/
+ 		lea		copy_start,a0
+ 		lea		BaS,a1
+ 		sub.l	a0,a1
+		move.l	#__Bas_base,a2
+ 		move.l	a2,a3
+ 		add.l	a1,a3
+		lea		copy_end,a4
+BaS_kopieren_loop:					// immer 16 bytes
+		move.l	(a0)+,(a2)+
+		move.l	(a0)+,(a2)+
+		move.l	(a0)+,(a2)+
+		move.l	(a0)+,(a2)+
+		cmp.l	a4,a0
+		blt		BaS_kopieren_loop
+/*****************************************************/
+		jmp		(a3)
+ copy_start:
+/********************************************************************/
+}
+}
+

BaS_codewarrior/firebeeV1/sources/sysinit.h

@@ -0,0 +1,87 @@
+/*
+ * File:		sysinit.h
+ * Purpose:		COLDARI Power-on Reset configuration
+ *
+ * Notes:
+ *
+ */
+
+#ifndef __SYSINIT_H__
+#define __SYSINIT_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if ENABLE_UART_SUPPORT==1 
+
+/*
+ * System Bus Clock Info
+ */
+// 5475EVB has 133Mhz system clock
+#define SYSTEM_CLOCK_KHZ    133000     /* system bus frequency in kHz */
+
+
+/*** 
+ * Serial Port Info
+ * The baud rate to be : 19200
+ * Data bits : 8
+ * Parity : None
+ * Stop Bits : 1
+ * Flow Control : None
+ */
+#define TERMINAL_PORT       (0)          /* PSC channel used as terminal */
+#define TERMINAL_BAUD       kBaud19200   /* 115200 */
+#undef  HARDWARE_FLOW_CONTROL       /* Flow control ON or OFF */
+#endif
+
+/*** 
+ * Board Memory map definitions from linker command files:
+ * __SDRAM,__SDRAM_SIZE, __FLASH, __FLASH_SIZE linker 
+ * symbols must be defined in the linker command file.
+ */
+extern __declspec(system) uint8 __BOOT_FLASH[];
+extern __declspec(system) uint8 __BOOT_FLASH_SIZE[];
+
+extern __declspec(system) uint8 __SDRAM[];
+extern __declspec(system) uint8 __SDRAM_SIZE[];
+
+
+#define BOOT_FLASH_ADDRESS		(uint32)__BOOT_FLASH
+#define BOOT_FLASH_SIZE			(uint32)__BOOT_FLASH_SIZE
+
+#define SDRAM_ADDRESS		    (uint32)__SDRAM
+#define SDRAM_SIZE			   	(uint32)__SDRAM_SIZE
+
+
+
+
+/********************************************************************/
+/* __initialize_hardware Startup code routine
+ * 
+ * __initialize_hardware is called by the startup code right after reset, 
+ * with interrupt disabled and SP pre-set to a valid memory area.
+ * Here you should initialize memory and some peripherics;
+ * at this point global variables are not initialized yet.
+ * The startup code will initialize SP on return of this function.
+ */
+void __initialize_hardware(void);
+
+/********************************************************************/
+/* __initialize_system Startup code routine
+ * 
+ * __initialize_system is called by the startup code when all languages 
+ * specific initialization are done to allow additional hardware setup.
+ */ 
+void __initialize_system(void);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSINIT_H__ */
+
+

BaS_codewarrior/workspace.cww

@@ -0,0 +1,413 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<?codewarrior exportversion="1.0" ideversion="5.9.0" success="y" ?>
+
+<!DOCTYPE MWIDEWORKSPACE [
+<!ELEMENT MWIDEWORKSPACE (WINDOW*, COMWINDOW*)>
+<!ELEMENT WINDOW (SESSION, EDOCTYPE, PATH, FRAMELOC, FRAMESIZE, DOCKINFO)>
+<!ELEMENT COMWINDOW (SESSION, CLSID, OWNERPROJECT, DATA, FRAMELOC, FRAMESIZE, DOCKINFO)>
+<!ELEMENT SESSION (#PCDATA)>
+<!ELEMENT EDOCTYPE (#PCDATA)>
+<!ELEMENT DEFAULT (#PCDATA)>
+<!ELEMENT MAXIMIZED (#PCDATA)>
+<!ELEMENT PATH (#PCDATA)>
+<!ATTLIST PATH USERELATIVEPATHS (true | false) "true">
+<!ELEMENT FRAMELOC (X, Y)>
+<!ELEMENT X (#PCDATA)>
+<!ELEMENT Y (#PCDATA)>
+<!ELEMENT FRAMESIZE (W, H)>
+<!ELEMENT W (#PCDATA)>
+<!ELEMENT H (#PCDATA)>
+<!ELEMENT DOCKINFO (STATUS, ROW, COLUMN, DOCKBARID, PCTWIDTH, HGT, GROUPID)>
+<!ELEMENT STATUS (#PCDATA)>
+<!ELEMENT ROW (#PCDATA)>
+<!ELEMENT COLUMN (#PCDATA)>
+<!ELEMENT DOCKBARID (#PCDATA)>
+<!ELEMENT PCTWIDTH (#PCDATA)>
+<!ELEMENT HGT (#PCDATA)>
+<!ELEMENT GROUPID (GIDHIGHPART, GIDLOWPART)>
+<!ELEMENT GIDHIGHPART (#PCDATA)>
+<!ELEMENT GIDLOWPART (#PCDATA)>
+<!ELEMENT CLSID (#PCDATA)>
+<!ELEMENT OWNERPROJECT (#PCDATA)>
+<!ATTLIST OWNERPROJECT USERELATIVEPATHS (true | false) "true">
+<!ELEMENT DATA (#PCDATA)>
+<!ATTLIST DATA BINARYFORMAT (true | false) "true">
+]>
+
+<MWIDEWORKSPACE>
+    <WINDOW>
+        <SESSION>-1</SESSION>
+        <EDOCTYPE>0</EDOCTYPE>
+        <DEFAULT>true</DEFAULT>
+        <PATH USERELATIVEPATHS = "true">firebeeV1\firebeeV1.mcp</PATH>
+        <FRAMELOC>
+            <X>938</X>
+            <Y>306</Y>
+        </FRAMELOC>
+        <FRAMESIZE>
+            <W>392</W>
+            <H>338</H>
+        </FRAMESIZE>
+        <DOCKINFO>
+            <STATUS>1</STATUS>
+            <ROW>0</ROW>
+            <COLUMN>0</COLUMN>
+            <DOCKBARID>59420</DOCKBARID>
+            <PCTWIDTH>1.000000</PCTWIDTH>
+            <HGT>378</HGT>
+            <GROUPID>
+                <GIDHIGHPART>0</GIDHIGHPART>
+                <GIDLOWPART>0</GIDLOWPART>
+            </GROUPID>
+        </DOCKINFO>
+    </WINDOW>
+    <WINDOW>
+        <SESSION>-1</SESSION>
+        <EDOCTYPE>1</EDOCTYPE>
+        <PATH USERELATIVEPATHS = "true">firebeeV1\sources\exceptions.s</PATH>
+        <FRAMELOC>
+            <X>8</X>
+            <Y>34</Y>
+        </FRAMELOC>
+        <FRAMESIZE>
+            <W>549</W>
+            <H>895</H>
+        </FRAMESIZE>
+        <DOCKINFO>
+            <STATUS>0</STATUS>
+            <ROW></ROW>
+            <COLUMN></COLUMN>
+            <DOCKBARID></DOCKBARID>
+            <PCTWIDTH></PCTWIDTH>
+            <HGT></HGT>
+            <GROUPID>
+                <GIDHIGHPART></GIDHIGHPART>
+                <GIDLOWPART></GIDLOWPART>
+            </GROUPID>
+        </DOCKINFO>
+    </WINDOW>
+    <WINDOW>
+        <SESSION>1073741824</SESSION>
+        <EDOCTYPE>35</EDOCTYPE>
+        <FRAMELOC>
+            <X>60</X>
+            <Y>205</Y>
+        </FRAMELOC>
+        <FRAMESIZE>
+            <W>582</W>
+            <H>392</H>
+        </FRAMESIZE>
+        <DOCKINFO>
+            <STATUS>0</STATUS>
+            <ROW></ROW>
+            <COLUMN></COLUMN>
+            <DOCKBARID></DOCKBARID>
+            <PCTWIDTH></PCTWIDTH>
+            <HGT></HGT>
+            <GROUPID>
+                <GIDHIGHPART></GIDHIGHPART>
+                <GIDLOWPART></GIDLOWPART>
+            </GROUPID>
+        </DOCKINFO>
+        <DEBUGCONTEXT>GlobalSession, cpu68K, osCWDS</DEBUGCONTEXT>
+        <DEBUGTARGETNAME>C:\FireBee\codewarrior\firebeeV1\bin\DDRAM.elf</DEBUGTARGETNAME>
+            <MEMORYWININDEX>2</MEMORYWININDEX>
+            <MEMORYWINSETTINGS EXPRSTRING = "0xf0000600" SPACEINDEX = "1" VIEWINDEX = "1" WORDSIZE = "1" SNAP16 = "0" SWAPENDIAN = "0" ASCIISHOWN = "1"/>
+    </WINDOW>
+    <WINDOW>
+        <SESSION>1073741824</SESSION>
+        <EDOCTYPE>35</EDOCTYPE>
+        <FRAMELOC>
+            <X>1586</X>
+            <Y>31</Y>
+        </FRAMELOC>
+        <FRAMESIZE>
+            <W>484</W>
+            <H>907</H>
+        </FRAMESIZE>
+        <DOCKINFO>
+            <STATUS>0</STATUS>
+            <ROW></ROW>
+            <COLUMN></COLUMN>
+            <DOCKBARID></DOCKBARID>
+            <PCTWIDTH></PCTWIDTH>
+            <HGT></HGT>
+            <GROUPID>
+                <GIDHIGHPART></GIDHIGHPART>
+                <GIDLOWPART></GIDLOWPART>
+            </GROUPID>
+        </DOCKINFO>
+        <DEBUGCONTEXT>GlobalSession, cpu68K, osCWDS</DEBUGCONTEXT>
+        <DEBUGTARGETNAME>C:\firebee\codewarrior\firebeeV1\bin\DDRAM.elf</DEBUGTARGETNAME>
+            <MEMORYWININDEX>4</MEMORYWININDEX>
+            <MEMORYWINSETTINGS EXPRSTRING = "0x1009626" SPACEINDEX = "1" VIEWINDEX = "4" WORDSIZE = "2" SNAP16 = "0" SWAPENDIAN = "0" ASCIISHOWN = "1"/>
+    </WINDOW>
+    <WINDOW>
+        <SESSION>1073741824</SESSION>
+        <EDOCTYPE>35</EDOCTYPE>
+        <FRAMELOC>
+            <X>1185</X>
+            <Y>39</Y>
+        </FRAMELOC>
+        <FRAMESIZE>
+            <W>481</W>
+            <H>225</H>
+        </FRAMESIZE>
+        <DOCKINFO>
+            <STATUS>0</STATUS>
+            <ROW></ROW>
+            <COLUMN></COLUMN>
+            <DOCKBARID></DOCKBARID>
+            <PCTWIDTH></PCTWIDTH>
+            <HGT></HGT>
+            <GROUPID>
+                <GIDHIGHPART></GIDHIGHPART>
+                <GIDLOWPART></GIDLOWPART>
+            </GROUPID>
+        </DOCKINFO>
+        <DEBUGCONTEXT>GlobalSession, cpu68K, osCWDS</DEBUGCONTEXT>
+        <DEBUGTARGETNAME>C:\firebee\codewarrior\firebeeV1\bin\DDRAM.elf</DEBUGTARGETNAME>
+            <MEMORYWININDEX>5</MEMORYWININDEX>
+            <MEMORYWINSETTINGS EXPRSTRING = "0xF" SPACEINDEX = "1" VIEWINDEX = "1" WORDSIZE = "3" SNAP16 = "0" SWAPENDIAN = "0" ASCIISHOWN = "1"/>
+    </WINDOW>
+    <WINDOW>
+        <SESSION>1073741824</SESSION>
+        <EDOCTYPE>35</EDOCTYPE>
+        <FRAMELOC>
+            <X>1100</X>
+            <Y>691</Y>
+        </FRAMELOC>
+        <FRAMESIZE>
+            <W>481</W>
+            <H>225</H>
+        </FRAMESIZE>
+        <DOCKINFO>
+            <STATUS>0</STATUS>
+            <ROW></ROW>
+            <COLUMN></COLUMN>
+            <DOCKBARID></DOCKBARID>
+            <PCTWIDTH></PCTWIDTH>
+            <HGT></HGT>
+            <GROUPID>
+                <GIDHIGHPART></GIDHIGHPART>
+                <GIDLOWPART></GIDLOWPART>
+            </GROUPID>
+        </DOCKINFO>
+        <DEBUGCONTEXT>GlobalSession, cpu68K, osCWDS</DEBUGCONTEXT>
+        <DEBUGTARGETNAME>C:\firebee\codewarrior\firebeeV1\bin\DDRAM.elf</DEBUGTARGETNAME>
+            <MEMORYWININDEX>3</MEMORYWININDEX>
+            <MEMORYWINSETTINGS EXPRSTRING = "0x010077e2" SPACEINDEX = "1" VIEWINDEX = "1" WORDSIZE = "3" SNAP16 = "0" SWAPENDIAN = "0" ASCIISHOWN = "1"/>
+    </WINDOW>
+    <WINDOW>
+        <SESSION>1073741824</SESSION>
+        <EDOCTYPE>35</EDOCTYPE>
+        <FRAMELOC>
+            <X>645</X>
+            <Y>600</Y>
+        </FRAMELOC>
+        <FRAMESIZE>
+            <W>481</W>
+            <H>225</H>
+        </FRAMESIZE>
+        <DOCKINFO>
+            <STATUS>0</STATUS>
+            <ROW></ROW>
+            <COLUMN></COLUMN>
+            <DOCKBARID></DOCKBARID>
+            <PCTWIDTH></PCTWIDTH>
+            <HGT></HGT>
+            <GROUPID>
+                <GIDHIGHPART></GIDHIGHPART>
+                <GIDLOWPART></GIDLOWPART>
+            </GROUPID>
+        </DOCKINFO>
+        <DEBUGCONTEXT>GlobalSession, cpu68K, osCWDS</DEBUGCONTEXT>
+        <DEBUGTARGETNAME>C:\FireBee\codewarrior\firebeeV1\bin\DDRAM.elf</DEBUGTARGETNAME>
+            <MEMORYWININDEX>1</MEMORYWININDEX>
+            <MEMORYWINSETTINGS EXPRSTRING = "0xfffffa" SPACEINDEX = "1" VIEWINDEX = "1" WORDSIZE = "1" SNAP16 = "0" SWAPENDIAN = "0" ASCIISHOWN = "1"/>
+    </WINDOW>
+    <WINDOW>
+        <SESSION>-2147483648</SESSION>
+        <EDOCTYPE>24</EDOCTYPE>
+        <FRAMELOC>
+            <X>13</X>
+            <Y>33</Y>
+        </FRAMELOC>
+        <FRAMESIZE>
+            <W>591</W>
+            <H>742</H>
+        </FRAMESIZE>
+        <DOCKINFO>
+            <STATUS>0</STATUS>
+            <ROW></ROW>
+            <COLUMN></COLUMN>
+            <DOCKBARID></DOCKBARID>
+            <PCTWIDTH></PCTWIDTH>
+            <HGT></HGT>
+            <GROUPID>
+                <GIDHIGHPART></GIDHIGHPART>
+                <GIDLOWPART></GIDLOWPART>
+            </GROUPID>
+        </DOCKINFO>
+    </WINDOW>
+    <WINDOW>
+        <SESSION>-2147483648</SESSION>
+        <EDOCTYPE>28</EDOCTYPE>
+        <FRAMELOC>
+            <X>652</X>
+            <Y>33</Y>
+        </FRAMELOC>
+        <FRAMESIZE>
+            <W>518</W>
+            <H>519</H>
+        </FRAMESIZE>
+        <DOCKINFO>
+            <STATUS>0</STATUS>
+            <ROW></ROW>
+            <COLUMN></COLUMN>
+            <DOCKBARID></DOCKBARID>
+            <PCTWIDTH></PCTWIDTH>
+            <HGT></HGT>
+            <GROUPID>
+                <GIDHIGHPART></GIDHIGHPART>
+                <GIDLOWPART></GIDLOWPART>
+            </GROUPID>
+        </DOCKINFO>
+        <DEBUGCONTEXT>GlobalSession, cpu68K, osCWDS</DEBUGCONTEXT>
+        <DEBUGTARGETNAME>C:\FireBee\codewarrior\firebeeV1\bin\DDRAM.elf</DEBUGTARGETNAME>
+            <REGISTERWINDOW><WINDOWINDEX>0</WINDOWINDEX>
+            <DIVIDERPOS>373</DIVIDERPOS>
+            <REGDISCLOSE NAME = "" TYPE = "334368068" DISCLOSED = "0">
+                <REGDISCLOSE NAME = "PEMICRO_USB" TYPE = "3" DISCLOSED = "1">
+                    <REGDISCLOSE NAME = "DDRAM.elf" TYPE = "4" DISCLOSED = "1">
+                        <REGDISCLOSE NAME = "Thread 0x0" TYPE = "5" DISCLOSED = "1">
+                            <REGDISCLOSE NAME = "General Purpose Registers" TYPE = "1" DISCLOSED = "1">
+                            </REGDISCLOSE>
+                            <REGDISCLOSE NAME = "FPU Registers" TYPE = "1" DISCLOSED = "0">
+                            </REGDISCLOSE>
+                            <REGDISCLOSE NAME = "EMAC Registers" TYPE = "1" DISCLOSED = "0">
+                            </REGDISCLOSE>
+                        </REGDISCLOSE>
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Supervisor Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Memory Management Unit Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "System Integration Unit Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "SDRAM Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "XL Bus Arbiter Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Clock Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Chip Select Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Interrupt Controller Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "GPT Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "GPT Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "GPT Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "GPT Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "SLT0 Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "SLT1 Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port FBCTL Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port FBCS Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port DMA Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port FEC0H Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port FEC0L Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port FEC1H Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port FEC1L Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port FECI2C Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port PCIBG Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port PCIBR Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port PSC3PSC2 Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port PSC1PSC0 Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port DSPI Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Common GPIO Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "PCI Bus Controller Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "PCI Bus Arbiter Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Edge Port Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Comm Timer Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Multichannel DMA Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Programmable Serial Controller 0 Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Programmable Serial Controller 1 Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Programmable Serial Controller 2 Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Programmable Serial Controller 3 Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "DMA Serial Peripheral Interface Registers" TYPE = "1" DISCLOSED = "1">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "I2C Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "FEC0 Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "FEC1 Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "USB Interface Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "SRAM Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                </REGDISCLOSE>
+            </REGDISCLOSE>
+            </REGISTERWINDOW>
+    </WINDOW>
+    <WINDOW>
+        <SESSION>1073741824</SESSION>
+        <EDOCTYPE>28</EDOCTYPE>
+        <FRAMELOC>
+            <X>652</X>
+            <Y>33</Y>
+        </FRAMELOC>
+        <FRAMESIZE>
+            <W>518</W>
+            <H>519</H>
+        </FRAMESIZE>
+        <DOCKINFO>
+            <STATUS>0</STATUS>
+            <ROW></ROW>
+            <COLUMN></COLUMN>
+            <DOCKBARID></DOCKBARID>
+            <PCTWIDTH></PCTWIDTH>
+            <HGT></HGT>
+            <GROUPID>
+                <GIDHIGHPART></GIDHIGHPART>
+                <GIDLOWPART></GIDLOWPART>
+            </GROUPID>
+        </DOCKINFO>
+        <DEBUGCONTEXT>GlobalSession, cpu68K, osCWDS</DEBUGCONTEXT>
+        <DEBUGTARGETNAME>C:\FireBee\codewarrior\firebeeV1\bin\DDRAM.elf</DEBUGTARGETNAME>
+            <REGISTERWINDOW><WINDOWINDEX>0</WINDOWINDEX>
+            <DIVIDERPOS>373</DIVIDERPOS>
+            <REGDISCLOSE NAME = "" TYPE = "334367732" DISCLOSED = "0">
+            </REGDISCLOSE>
+            </REGISTERWINDOW>
+    </WINDOW>
+</MWIDEWORKSPACE>

BaS_gcc/.gdbinit

@@ -3,12 +3,12 @@ define tr
 	#!killall m68k-bdm-gdbserver
 	target remote | m68k-bdm-gdbserver pipe /dev/bdmcf3
 	#target remote localhost:1234
-	#target remote | m68k-bdm-gdbserver pipe /dev/tblcf3
+	#target remote | m68k-bdm-gdbserver pipe /dev/tblcf2
 	#target dbug /dev/ttyS0
 	#monitor bdm-reset
 end
 define tbtr
-	target remote | m68k-bdm-gdbserver pipe /dev/tblcf3
+	target remote | m68k-bdm-gdbserver pipe /dev/tblcf2
 end
 source mcf5474.gdb
 set breakpoint auto-hw

BaS_gcc/BaS_gcc.config

@@ -0,0 +1,3 @@
+// Add predefined macros for your project here. For example:
+// #define THE_ANSWER 42
+#define MACHINE_FIREBEE

BaS_gcc/BaS_gcc.files

@@ -0,0 +1,397 @@
+dma/dma.c
+dma/MCD_dmaApi.c
+dma/MCD_tasks.c
+dma/MCD_tasksInit.c
+exe/basflash.c
+exe/basflash_start.c
+firebee/bas.elf
+firebee/bas.lk
+firebee/bas.map
+firebee/bas.s19
+firebee/basflash.elf
+firebee/basflash.lk
+firebee/basflash.map
+firebee/basflash.s19
+firebee/depend
+firebee/libbas.a
+firebee/ram.elf
+firebee/ram.lk
+firebee/ram.map
+firebee/ram.s19
+flash/flash.c
+flash/s19reader.c
+flash_scripts/flash_firebee_bas.bdm
+flash_scripts/flash_firebee_etos.bdm
+flash_scripts/flash_firebee_firetos.bdm
+flash_scripts/flash_firebee_fpga.bdm
+flash_scripts/flash_m548x_bas.bdm
+flash_scripts/flash_m548x_dbug.bdm
+flash_scripts/flash_m548x_etos.bdm
+flash_scripts/m548xlite_dbug_ram.elf
+flash_scripts/m548xlite_dbug_ram.s19
+flash_scripts/run_m548x_dbug.bdm
+fs/cc932.c
+fs/cc936.c
+fs/cc949.c
+fs/cc950.c
+fs/ccsbcs.c
+fs/ff.c
+fs/unicode.c
+i2c/i2c.c
+if/driver_vec.c
+include/acia.h
+include/am79c874.h
+include/arp.h
+include/ati_ids.h
+include/bas_printf.h
+include/bas_string.h
+include/bas_types.h
+include/bas_utils.h
+include/bcm5222.h
+include/bootp.h
+include/cache.h
+include/conout.h
+include/debug.h
+include/diskio.h
+include/dma.h
+include/driver_mem.h
+include/driver_vec.h
+include/edid.h
+include/ehci.h
+include/eth.h
+include/exceptions.h
+include/fb.h
+include/fec.h
+include/fecbd.h
+include/ff.h
+include/ffconf.h
+include/firebee.h
+include/font.h
+include/i2c-algo-bit.h
+include/i2c.h
+include/icmp.h
+include/ikbd.h
+include/interrupts.h
+include/ip.h
+include/m54455.h
+include/m5484l.h
+include/MCD_dma.h
+include/mcd_initiators.h
+include/MCD_progCheck.h
+include/MCD_tasksInit.h
+include/MCF5475.h
+include/MCF5475_CLOCK.h
+include/MCF5475_CTM.h
+include/MCF5475_DMA.h
+include/MCF5475_DSPI.h
+include/MCF5475_EPORT.h
+include/MCF5475_FBCS.h
+include/MCF5475_FEC.h
+include/MCF5475_GPIO.h
+include/MCF5475_GPT.h
+include/MCF5475_I2C.h
+include/MCF5475_INTC.h
+include/MCF5475_MMU.h
+include/MCF5475_PAD.h
+include/MCF5475_PCI.h
+include/MCF5475_PCIARB.h
+include/MCF5475_PSC.h
+include/MCF5475_SDRAMC.h
+include/MCF5475_SEC.h
+include/MCF5475_SIU.h
+include/MCF5475_SLT.h
+include/MCF5475_SRAM.h
+include/MCF5475_USB.h
+include/MCF5475_XLB.h
+include/mmu.h
+include/mod_devicetable.h
+include/nbuf.h
+include/net.h
+include/net_timer.h
+include/nif.h
+include/ohci.h
+include/part.h
+include/pci.h
+include/pci_errata.h
+include/pci_ids.h
+include/queue.h
+include/radeon_reg.h
+include/radeonfb.h
+include/s19reader.h
+include/screen.h
+include/sd_card.h
+include/setjmp.h
+include/startcf.h
+include/sysinit.h
+include/tftp.h
+include/udp.h
+include/usb.h
+include/usb_defs.h
+include/usb_hub.h
+include/user_io.h
+include/util.h
+include/version.h
+include/videl.h
+include/video.h
+include/wait.h
+include/x86emu.h
+include/x86emu_regs.h
+include/x86pcibios.h
+include/xhdi_sd.h
+kbd/ikbd.c
+m54455/bas.elf
+m54455/bas.lk
+m54455/bas.map
+m54455/bas.s19
+m54455/basflash.elf
+m54455/basflash.lk
+m54455/basflash.map
+m54455/basflash.s19
+m54455/depend
+m54455/libbas.a
+m54455/ram.elf
+m54455/ram.lk
+m54455/ram.map
+m54455/ram.s19
+m5484lite/bas.elf
+m5484lite/bas.lk
+m5484lite/bas.map
+m5484lite/bas.s19
+m5484lite/basflash.elf
+m5484lite/basflash.lk
+m5484lite/basflash.map
+m5484lite/basflash.s19
+m5484lite/depend
+m5484lite/libbas.a
+m5484lite/ram.elf
+m5484lite/ram.lk
+m5484lite/ram.map
+m5484lite/ram.s19
+net/am79c874.c
+net/arp.c
+net/bcm5222.c
+net/bootp.c
+net/fec.c
+net/fecbd.c
+net/ip.c
+net/nbuf.c
+net/net_timer.c
+net/nif.c
+net/queue.c
+net/tftp.c
+net/udp.c
+nutil/s19header.c
+pci/ehci-hcd.c
+pci/ohci-hcd.c
+pci/pci.c
+pci/pci_errata.c
+pci/pci_wrappers.S
+radeon/i2c-algo-bit.c
+radeon/radeon_accel.c
+radeon/radeon_base.c
+radeon/radeon_cursor.c
+radeon/radeon_i2c.c
+radeon/radeon_monitor.c
+release/firebee/bas.s19
+release/m5484lite/bas.s19
+release/bascook.prg
+release/readme.txt
+spi/dspi.c
+spi/mmc.c
+spi/sd_card.c
+sys/BaS.c
+sys/cache.c
+sys/driver_mem.c
+sys/exceptions.S
+sys/fault_vectors.c
+sys/init_fpga.c
+sys/interrupts.c
+sys/mmu.c
+sys/startcf.S
+sys/sysinit.c
+tos/bascook/sources/bascook.c
+tos/bascook/bascook.prg
+tos/bascook/depend
+tos/bascook/mapfile
+tos/fpga_test/m5475/mshort/fpga_test.prg
+tos/fpga_test/m5475/fpga_test.prg
+tos/fpga_test/sources/fpga_test.c
+tos/fpga_test/sources/ser_printf.c
+tos/fpga_test/sources/vmem_test.c
+tos/fpga_test/depend
+tos/fpga_test/mapfile
+tos/jtagwait/include/bas_printf.h
+tos/jtagwait/include/bas_string.h
+tos/jtagwait/include/driver_vec.h
+tos/jtagwait/include/MCF5475.h
+tos/jtagwait/include/MCF5475_CLOCK.h
+tos/jtagwait/include/MCF5475_CTM.h
+tos/jtagwait/include/MCF5475_DMA.h
+tos/jtagwait/include/MCF5475_DSPI.h
+tos/jtagwait/include/MCF5475_EPORT.h
+tos/jtagwait/include/MCF5475_FBCS.h
+tos/jtagwait/include/MCF5475_FEC.h
+tos/jtagwait/include/MCF5475_GPIO.h
+tos/jtagwait/include/MCF5475_GPT.h
+tos/jtagwait/include/MCF5475_I2C.h
+tos/jtagwait/include/MCF5475_INTC.h
+tos/jtagwait/include/MCF5475_MMU.h
+tos/jtagwait/include/MCF5475_PAD.h
+tos/jtagwait/include/MCF5475_PCI.h
+tos/jtagwait/include/MCF5475_PCIARB.h
+tos/jtagwait/include/MCF5475_PSC.h
+tos/jtagwait/include/MCF5475_SDRAMC.h
+tos/jtagwait/include/MCF5475_SEC.h
+tos/jtagwait/include/MCF5475_SIU.h
+tos/jtagwait/include/MCF5475_SLT.h
+tos/jtagwait/include/MCF5475_SRAM.h
+tos/jtagwait/include/MCF5475_USB.h
+tos/jtagwait/include/MCF5475_XLB.h
+tos/jtagwait/m5475/mshort/jtagwait.prg
+tos/jtagwait/m5475/jtagwait.prg
+tos/jtagwait/sources/bas_printf.c
+tos/jtagwait/sources/bas_string.c
+tos/jtagwait/sources/jtagwait.c
+tos/jtagwait/sources/printf_helper.S
+tos/jtagwait/depend
+tos/jtagwait/mapfile
+tos/pci_mem/include/bas_string.h
+tos/pci_mem/include/bas_types.h
+tos/pci_mem/include/driver_vec.h
+tos/pci_mem/include/MCF5475.h
+tos/pci_mem/include/MCF5475_CLOCK.h
+tos/pci_mem/include/MCF5475_CTM.h
+tos/pci_mem/include/MCF5475_DMA.h
+tos/pci_mem/include/MCF5475_DSPI.h
+tos/pci_mem/include/MCF5475_EPORT.h
+tos/pci_mem/include/MCF5475_FBCS.h
+tos/pci_mem/include/MCF5475_FEC.h
+tos/pci_mem/include/MCF5475_GPIO.h
+tos/pci_mem/include/MCF5475_GPT.h
+tos/pci_mem/include/MCF5475_I2C.h
+tos/pci_mem/include/MCF5475_INTC.h
+tos/pci_mem/include/MCF5475_MMU.h
+tos/pci_mem/include/MCF5475_PAD.h
+tos/pci_mem/include/MCF5475_PCI.h
+tos/pci_mem/include/MCF5475_PCIARB.h
+tos/pci_mem/include/MCF5475_PSC.h
+tos/pci_mem/include/MCF5475_SDRAMC.h
+tos/pci_mem/include/MCF5475_SEC.h
+tos/pci_mem/include/MCF5475_SIU.h
+tos/pci_mem/include/MCF5475_SLT.h
+tos/pci_mem/include/MCF5475_SRAM.h
+tos/pci_mem/include/MCF5475_USB.h
+tos/pci_mem/include/MCF5475_XLB.h
+tos/pci_mem/include/pci.h
+tos/pci_mem/include/util.h
+tos/pci_mem/m5475/mshort/pci_mem.prg
+tos/pci_mem/m5475/pci_mem.prg
+tos/pci_mem/sources/pci_mem.c
+tos/pci_mem/depend
+tos/pci_mem/mapfile
+tos/pci_test/include/bas_string.h
+tos/pci_test/include/bas_types.h
+tos/pci_test/include/driver_vec.h
+tos/pci_test/include/MCF5475.h
+tos/pci_test/include/MCF5475_CLOCK.h
+tos/pci_test/include/MCF5475_CTM.h
+tos/pci_test/include/MCF5475_DMA.h
+tos/pci_test/include/MCF5475_DSPI.h
+tos/pci_test/include/MCF5475_EPORT.h
+tos/pci_test/include/MCF5475_FBCS.h
+tos/pci_test/include/MCF5475_FEC.h
+tos/pci_test/include/MCF5475_GPIO.h
+tos/pci_test/include/MCF5475_GPT.h
+tos/pci_test/include/MCF5475_I2C.h
+tos/pci_test/include/MCF5475_INTC.h
+tos/pci_test/include/MCF5475_MMU.h
+tos/pci_test/include/MCF5475_PAD.h
+tos/pci_test/include/MCF5475_PCI.h
+tos/pci_test/include/MCF5475_PCIARB.h
+tos/pci_test/include/MCF5475_PSC.h
+tos/pci_test/include/MCF5475_SDRAMC.h
+tos/pci_test/include/MCF5475_SEC.h
+tos/pci_test/include/MCF5475_SIU.h
+tos/pci_test/include/MCF5475_SLT.h
+tos/pci_test/include/MCF5475_SRAM.h
+tos/pci_test/include/MCF5475_USB.h
+tos/pci_test/include/MCF5475_XLB.h
+tos/pci_test/include/pci.h
+tos/pci_test/include/util.h
+tos/pci_test/m5475/mshort/pci_test.prg
+tos/pci_test/m5475/pci_test.prg
+tos/pci_test/sources/pci_test.c
+tos/pci_test/sources/printf_helper.S
+tos/pci_test/depend
+tos/pci_test/mapfile
+tos/vmem_test/include/bas_printf.h
+tos/vmem_test/include/bas_string.h
+tos/vmem_test/include/driver_vec.h
+tos/vmem_test/include/MCF5475.h
+tos/vmem_test/include/MCF5475_CLOCK.h
+tos/vmem_test/include/MCF5475_CTM.h
+tos/vmem_test/include/MCF5475_DMA.h
+tos/vmem_test/include/MCF5475_DSPI.h
+tos/vmem_test/include/MCF5475_EPORT.h
+tos/vmem_test/include/MCF5475_FBCS.h
+tos/vmem_test/include/MCF5475_FEC.h
+tos/vmem_test/include/MCF5475_GPIO.h
+tos/vmem_test/include/MCF5475_GPT.h
+tos/vmem_test/include/MCF5475_I2C.h
+tos/vmem_test/include/MCF5475_INTC.h
+tos/vmem_test/include/MCF5475_MMU.h
+tos/vmem_test/include/MCF5475_PAD.h
+tos/vmem_test/include/MCF5475_PCI.h
+tos/vmem_test/include/MCF5475_PCIARB.h
+tos/vmem_test/include/MCF5475_PSC.h
+tos/vmem_test/include/MCF5475_SDRAMC.h
+tos/vmem_test/include/MCF5475_SEC.h
+tos/vmem_test/include/MCF5475_SIU.h
+tos/vmem_test/include/MCF5475_SLT.h
+tos/vmem_test/include/MCF5475_SRAM.h
+tos/vmem_test/include/MCF5475_USB.h
+tos/vmem_test/include/MCF5475_XLB.h
+tos/vmem_test/m5475/mshort/vmem_test.prg
+tos/vmem_test/m5475/vmem_test.prg
+tos/vmem_test/sources/bas_printf.c
+tos/vmem_test/sources/bas_string.c
+tos/vmem_test/sources/printf_helper.S
+tos/vmem_test/sources/vmem_test.c
+tos/vmem_test/depend
+tos/vmem_test/mapfile
+usb/usb.c
+usb/usb_hub.c
+usb/usb_kbd.c
+usb/usb_mouse.c
+util/bas_printf.c
+util/bas_string.c
+util/conout.c
+util/libgcc_helper.S
+util/setjmp.S
+util/wait.c
+video/fbmem.c
+video/fbmodedb.c
+video/fbmon.c
+video/fnt_st_8x16.c
+video/offscreen.c
+video/vdi_fill.c
+video/videl.c
+video/video.c
+x86emu/x86biosemu.c
+x86emu/x86emu.c
+x86emu/x86emu_util.c
+x86emu/x86pcibios.c
+xhdi/xhdi_interface.c
+xhdi/xhdi_sd.c
+xhdi/xhdi_vec.S
+bas.lk.in
+bas_firebee.bdm
+bas_m5484.bdm
+basflash.lk.in
+check.bdm
+COPYING
+COPYING.LESSER
+Doxyfile
+dump.bdm
+mcf5474.gdb
+memory_map.txt

BaS_gcc/BaS_gcc.includes

@@ -0,0 +1,5 @@
+include
+tos/jtagwait/include
+tos/pci_mem/include
+tos/pci_test/include
+tos/vmem_test/include

BaS_gcc/Makefile

@@ -1,12 +1,20 @@
-# # Makefile for Firebee BaS
+# Makefile for Firebee BaS
 #
 # This Makefile is meant for cross compiling the BaS with Vincent Riviere's cross compilers.
 # If you want to compile native on an Atari (you will need at least GCC 4.6.3), set
 # TCPREFIX to be empty.
+#
 # If you want to compile with the m68k-elf- toolchain, set TCPREFIX accordingly. Requires an extra
 # installation, but allows source level debugging over BDM with a recent gdb (tested with 7.5),
 # the m68k BDM tools from sourceforge (http://bdm.sourceforge.net) and a BDM pod (TBLCF and P&E tested).
 
+
+ifneq (yes,$(VERBOSE))
+Q=@
+else
+Q=
+endif
+
 # can be either "Y" or "N" (without quotes). "Y" for using the m68k-elf-, "N" for using the m68k-atari-mint
 # toolchain
 COMPILE_ELF=Y
@@ -29,35 +37,43 @@ AR=$(TCPREFIX)ar
 RANLIB=$(TCPREFIX)ranlib
 NATIVECC=gcc
 
+ifeq (Y,$(COMPILE_ELF))
+LDLIBS=-lgcc
+else
+LDLIBS=-lgcc
+endif
+
 INCLUDE=-Iinclude
-CFLAGS=-mcpu=5474 \
-		-Wall \
-		-g3 \
-		-fomit-frame-pointer \
-		-ffreestanding \
-		-fleading-underscore \
-		-Wa,--register-prefix-optional
+CFLAGS=	-Wall \
+	-O2 \
+	-fomit-frame-pointer \
+	-ffreestanding \
+	-fno-strict-aliasing \
+	-fleading-underscore \
+	-Winline \
+	-Wa,--register-prefix-optional
+
 CFLAGS_OPTIMIZED = -mcpu=5474 \
 		-Wall \
-		-g3 \
 		-O2 \
 		-fomit-frame-pointer \
 		-ffreestanding \
 		-fleading-underscore \
 		-Wa,--register-prefix-optional
+LDFLAGS=
 
-TRGTDIRS= ./firebee ./m5484lite ./m54455
+TRGTDIRS= ./firebee ./m54455 ./m5484lite
 OBJDIRS=$(patsubst %, %/objs,$(TRGTDIRS))
 TOOLDIR=util
 
-VPATH=dma exe flash fs if kbd pci spi sys usb net util video radeon x86emu xhdi
+VPATH=dma exe flash fs i2c if kbd pci spi sys usb net util video radeon x86emu xhdi
 
 # Linker control file. The final $(LDCFILE) is intermediate only (preprocessed version of $(LDCSRC)
 LDCFILE=bas.lk
 LDRFILE=ram.lk
 LDCSRC=bas.lk.in
 LDCBSRC=basflash.lk.in
-LDCBFS=bashflash.lk
+LDCBFS=basflash.lk
 
 # this Makefile can create the BaS to flash or an arbitrary ram address (for BDM debugging). See
 # below for the definition of TARGET_ADDRESS
@@ -70,8 +86,11 @@ CSRCS= \
 	init_fpga.c \
 	fault_vectors.c \
 	interrupts.c \
+	\
 	bas_printf.c \
 	bas_string.c \
+	conout.c \
+	\
 	BaS.c \
 	cache.c \
 	mmu.c \
@@ -83,20 +102,25 @@ CSRCS= \
 	s19reader.c \
 	flash.c \
 	dma.c \
+	i2c.c \
 	xhdi_sd.c \
 	xhdi_interface.c \
 	pci.c \
+	pci_errata.c \
 	dspi.c \
 	driver_vec.c \
 	driver_mem.c \
+	\
 	MCD_dmaApi.c \
 	MCD_tasks.c \
 	MCD_tasksInit.c \
+	\
 	usb.c \
 	ohci-hcd.c \
 	ehci-hcd.c \
 	usb_hub.c \
 	usb_mouse.c \
+	usb_kbd.c \
 	ikbd.c \
 	\
 	nbuf.c \
@@ -121,21 +145,19 @@ CSRCS= \
 	videl.c \
 	video.c \
 	\
+	i2c-algo-bit.c \
+	\
 	radeon_base.c \
 	radeon_accel.c \
 	radeon_cursor.c \
 	radeon_monitor.c \
+	radeon_i2c.c \
 	fnt_st_8x16.c \
 	\
-	x86decode.c \
-	x86sys.c \
-	x86debug.c \
-	x86prim_ops.c \
-	x86ops.c \
-	x86ops2.c \
-	x86fpu.c \
-	x86biosemu.c \
+	x86emu.c \
 	x86pcibios.c \
+	x86biosemu.c \
+	x86emu_util.c \
 	\
 	basflash.c \
 	basflash_start.c
@@ -144,9 +166,14 @@ CSRCS= \
 ASRCS= \
 	startcf.S \
 	exceptions.S \
+	setjmp.S \
 	xhdi_vec.S \
 	pci_wrappers.S
 
+ifeq (Y,$(COMPILE_ELF))			# needed for __ vs ___ kludge
+	ASRCS += libgcc_helper.S
+endif
+
 SRCS=$(ASRCS) $(CSRCS)
 COBJS=$(patsubst %.c,%.o,$(CSRCS))
 AOBJS=$(patsubst %.S,%.o,$(ASRCS))
@@ -165,55 +192,57 @@ lib: $(LIBS)
 .PHONY: ver
 ver:
 	touch include/version.h
+
 .PHONY: tos
 tos:
-	(cd tos; make)
+	$(Q)(cd tos; $(MAKE) -s)
 
 .PHONY: clean
 clean:
-	for d in $(TRGTDIRS);\
+	$(Q)for d in $(TRGTDIRS);\
 		do rm -f $$d/*.map $$d/*.s19 $$d/*.elf $$d/*.lk $$d/*.a $$d/objs/* $$d/depend;\
 	done
-	rm -f tags
+	$(Q)rm -f tags
+	$(Q)(cd tos; make -s clean)
+
 
 
 # flags for targets
 m5484lite/bas.$(EXE): MACHINE=MACHINE_M5484LITE
 m54455/bas.$(EXE): MACHINE=MACHINE_M54455
 firebee/bas.$(EXE): MACHINE=MACHINE_FIREBEE
+
 m5484lite/ram.$(EXE): MACHINE=MACHINE_M5484LITE
 m54455/ram.$(EXE): MACHINE=MACHINE_M54455
 firebee/ram.$(EXE): MACHINE=MACHINE_FIREBEE
+
 m5484lite/basflash.$(EXE): MACHINE=MACHINE_M5484LITE
 m54455/basflash.$(EXE): MACHINE=MACHINE_M54455
 firebee/basflash.$(EXE): MACHINE=MACHINE_FIREBEE
 
+m5484lite/bas.$(EXE): CFLAGS += -mcpu=5484
+m54455/bas.$(EXE): CFLAGS += -mcpu=54455 -msoft-float
+firebee/bas.$(EXE): CFLAGS += -mcpu=5474
+
+m5484lite/ram.$(EXE): CFLAGS += -mcpu=5484
+m54455/ram.$(EXE): CFLAGS += -mcpu=54455 -msoft-float
+firebee/ram.$(EXE): CFLAGS += -mcpu=5474
+
+m5484lite/basflash.$(EXE): CFLAGS += -mcpu=5484
+m54455/basflash.$(EXE): CFLAGS += -mcpu=54455 -msoft-float
+firebee/basflash.$(EXE): CFLAGS += -mcpu=5474
+
 #
 # generate pattern rules for different object files
 #
 define CC_TEMPLATE
-#ifeq (firebee,$(1))
-	#MACHINE=MACHINE_FIREBEE
-#else
-	#MACHINE=MACHINE_M5484LITE
-#endif
-
-# always optimize x86 emulator objects
-#$(1)/objs/x86decode.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
-#$(1)/objs/x86sys.o:		CFLAGS=$(CFLAGS_OPTIMIZED)
-#$(1)/objs/x86debug.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
-#$(1)/objs/x86prim_ops.o:CFLAGS=$(CFLAGS_OPTIMIZED)
-#$(1)/objs/x86ops.o:		CFLAGS=$(CFLAGS_OPTIMIZED)
-#$(1)/objs/x86ops2.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
-#$(1)/objs/x86fpu.o:		CFLAGS=$(CFLAGS_OPTIMIZED)
-#$(1)/objs/x86biosemu.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
-#$(1)/objs/x86pcibios.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
-
 $(1)/objs/%.o:%.c
-	$(CC) $$(CFLAGS) -D$$(MACHINE) $(INCLUDE) -c $$< -o $$@
+	$(Q)echo CC $$<
+	$(Q)$(CC) $$(CFLAGS) -D$$(MACHINE) $(INCLUDE) -c $$< -o $$@
 
 $(1)/objs/%.o:%.S
-	$(CC) $$(CFLAGS) -Wa,--bitwise-or -D$$(MACHINE) $(INCLUDE) -c $$< -o $$@
+	$(Q)echo CC $$<
+	$(Q)$(CC) $$(CFLAGS) -Wa,--bitwise-or -D$$(MACHINE) $(INCLUDE) -c $$< -o $$@
 endef
 $(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
 
@@ -229,7 +258,8 @@ else
 	MACHINE=MACHINE_M5484LITE
 endif
 $(1)/depend:$(SRCS)
-	$(CC) $$(CFLAGS) -D$$(MACHINE) $(INCLUDE) -M $$^ | sed -e "s#^\(.*\).o:#"$(1)"/objs/\1.o:#" > $$@
+	$(Q)echo DEPEND
+	$(Q)$(CC) $$(CFLAGS) -D$$(MACHINE) $(INCLUDE) -M $$^ | sed -e "s#^\(.*\).o:#"$(1)"/objs/\1.o:#" > $$@
 endef
 $(foreach DIR,$(TRGTDIRS),$(eval $(call DEP_TEMPLATE,$(DIR))))
 
@@ -240,8 +270,9 @@ $(foreach DIR,$(TRGTDIRS),$(eval $(call DEP_TEMPLATE,$(DIR))))
 define AR_TEMPLATE
 $(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
 $(1)/$(LIBBAS): $$($(1)_OBJS)
-	$(AR) rv $$@ $$?
-	$(RANLIB) $$@
+	$(Q)echo AR $$@
+	$(Q)$(AR) r $$@ $$?
+	$(Q)$(RANLIB) $$@
 endef
 $(foreach DIR,$(TRGTDIRS),$(eval $(call AR_TEMPLATE,$(DIR))))
 
@@ -250,41 +281,59 @@ ifeq ($(COMPILE_ELF),Y)
 else
 	FORMAT_ELF=0
 endif
+
+define LK_TEMPLATE
+$(1)/$$(LDCFILE): $(LDCSRC)
+	$(Q)echo CPP $$<
+	$(Q)$(CPP) $(INCLUDE) -DOBJDIR=$(1)/objs -P -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $$< -o $$@
+endef
+$(foreach DIR,$(TRGTDIRS),$(eval $(call LK_TEMPLATE,$(DIR))))
+
 #
 # define pattern rules for binaries
 #
 define EX_TEMPLATE
 # pattern rule for flash
 $(1)_MAPFILE=$(1)/$$(basename $$(FLASH_EXEC)).map
-$(1)/$$(FLASH_EXEC): $(1)/$(LIBBAS) $(LDCSRC)
-	$(CPP) $(INCLUDE) -DOBJDIR=$(1)/objs -P -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCSRC) -o $(1)/$$(LDCFILE)
-	$(LD) --oformat $$(FORMAT) -Map $$($(1)_MAPFILE) --cref -T $(1)/$$(LDCFILE) -o $$@
+$(1)/$$(FLASH_EXEC): $(1)/$(LIBBAS) $(1)/$$(LDCFILE)
+	$(Q)echo CC $$@
+	$(Q)$(CC) $$(CFLAGS) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDCFILE) $(LDLIBS) -o $$@
 ifeq ($(COMPILE_ELF),Y)
-	$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
+	$(Q)echo OBJCOPY $$@
+	$(Q)$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
 else
-	objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf
+	$(Q)echo OBJCOPY $$@
+	$(Q)objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf
 endif
 
 # pattern rule for RAM
 $(1)_MAPFILE_RAM=$(1)/$$(basename $$(RAM_EXEC)).map
-$(1)/$$(RAM_EXEC): $(1)/$(LIBBAS) $(LDCSRC)
-	$(CPP) $(INCLUDE) -DCOMPILE_RAM -DOBJDIR=$(1)/objs -P -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCSRC) -o $(1)/$$(LDRFILE)
-	$(LD) -g --oformat $$(FORMAT) -Map $$($(1)_MAPFILE_RAM) --cref -T $(1)/$$(LDRFILE) -o $$@
+$(1)/$$(RAM_EXEC): $(1)/$(LIBBAS) $(1)/$$(LDCFILE)
+	$(Q)echo CPP $$@
+	$(Q)$(CPP) $(INCLUDE) -DCOMPILE_RAM -DOBJDIR=$(1)/objs -P -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCSRC) -o $(1)/$$(LDRFILE)
+	$(Q)echo CC $$@
+	$(Q)$(CC) $$(CFLAGS) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE_RAM) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDRFILE) $(LDLIBS) -o $$@
 ifeq ($(COMPILE_ELF),Y)
-	$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
+	$(Q)echo OBJCOPY $$@
+	$(Q)$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
 else
-	objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf
+	$(Q)echo OBJCOPY $$<
+	$(Q)objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf
 endif
 
 # pattern rule for basflash
 $(1)_MAPFILE_BFL=$(1)/$$(basename $$(BASFLASH_EXEC)).map
 $(1)/$$(BASFLASH_EXEC): $(1)/objs/basflash.o $(1)/objs/basflash_start.o $(1)/$(LIBBAS) $(LDCBFL)
+	$(Q)echo CPP $$<
 	$(CPP) $(INCLUDE) -P -DOBJDIR=$(1)/objs -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCBSRC) -o $(1)/$$(LDCBFS)
-	$(LD) --oformat $$(FORMAT) -Map $$($(1)_MAPFILE_BFL) --cref -T $(1)/$$(LDCFILE) -L$(1) -lbas -o $$@
+	$(Q)echo CC $$<
+	$(Q)$(CC) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE_BFL) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDCBFS) -L$(1) -lbas $(LDLIBS) -o $$@
 ifeq ($(COMPILE_ELF),Y)
-	$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
+	$(Q)echo OBJCOPY $$<
+	$(Q)$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
 else
-	objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf
+	$(Q)echo OBJCOPY $$<
+	$(Q)objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf
 endif
 endef
 $(foreach DIR,$(TRGTDIRS),$(eval $(call EX_TEMPLATE,$(DIR))))
@@ -299,7 +348,7 @@ tags:
 
 .PHONY: printvars
 printvars:
-	@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
+	$(Q)$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
 ifeq (MACHINE_M5484LITE,$$(MACHINE))
 	MNAME=m5484lite
 else ifeq (MACHINE_FIREBEE,$(MACHINE))

BaS_gcc/bas.lk.in

@@ -0,0 +1,282 @@
+#if defined(MACHINE_FIREBEE)
+#include "firebee.h"
+#elif defined(MACHINE_M5484LITE)
+#    include "m5484l.h"
+#elif defined(MACHINE_M54455)
+#include "m54455.h"
+#else
+#error "unknown machine!"
+#endif /* MACHINE_M5484LITE */
+
+/* make bas_rom access flags rx if compiling to RAM */
+#ifdef COMPILE_RAM
+#define ROMFLAGS    WX
+#else
+#define ROMFLAGS    RX
+#endif /* COMPILE_RAM */
+
+MEMORY
+{
+   bas_rom (ROMFLAGS) : ORIGIN = TARGET_ADDRESS, LENGTH = 0x00100000
+   /*
+    * target to copy BaS data segment to. 1M should be enough for now
+    */
+   bas_ram (WX) : ORIGIN = SDRAM_START + SDRAM_SIZE - 0x00200000, LENGTH = 0x00100000
+   /*
+    * driver_ram is an uncached, reserved memory area for drivers (e.g. USB) that need this type of memory
+    */
+   driver_ram (WX) : ORIGIN = SDRAM_START + SDRAM_SIZE - 0x00100000, LENGTH = 0x00100000
+}
+
+SECTIONS
+{
+        /* BaS in ROM */
+        .text :
+        {
+                OBJDIR/startcf.o(.text) /* this one is the entry point so it must be the first */
+
+                OBJDIR/sysinit.o(.text)
+                OBJDIR/fault_vectors.o(.text)
+#ifdef MACHINE_FIREBEE
+                OBJDIR/init_fpga.o(.text)
+#endif /* MACHINE_FIREBEE */
+                OBJDIR/wait.o(.text)
+                OBJDIR/exceptions.o(.text)
+                OBJDIR/setjmp.o(.text)
+                OBJDIR/driver_vec.o(.text)
+                OBJDIR/interrupts.o(.text)
+                OBJDIR/mmu.o(.text)
+
+                OBJDIR/BaS.o(.text)
+                OBJDIR/pci.o(.text)
+                . = ALIGN(16);
+                OBJDIR/pci_errata.o(.text)
+                OBJDIR/pci_wrappers.o(.text)
+                OBJDIR/usb.o(.text)
+                OBJDIR/driver_mem.o(.text)
+                OBJDIR/usb_hub.o(.text)
+                OBJDIR/usb_mouse.o(.text)
+                OBJDIR/usb_kbd.o(.text)
+                OBJDIR/ohci-hcd.o(.text)
+                OBJDIR/ehci-hcd.o(.text)
+                OBJDIR/wait.o(.text)
+
+                OBJDIR/nbuf.o(.text)
+                OBJDIR/net_timer.o(.text)
+                OBJDIR/queue.o(.text)
+                OBJDIR/nif.o(.text)
+                OBJDIR/fecbd.o(.text)
+                OBJDIR/fec.o(.text)
+                OBJDIR/am79c874.o(.text)
+                OBJDIR/bcm5222.o(.text)
+                OBJDIR/ip.o(.text)
+                OBJDIR/udp.o(text)
+                OBJDIR/bootp.o(text)
+                OBJDIR/tftp.o(text)
+                OBJDIR/arp.o(text)
+
+                OBJDIR/unicode.o(.text)
+                OBJDIR/mmc.o(.text)
+                OBJDIR/ff.o(.text)
+                OBJDIR/sd_card.o(.text)
+                OBJDIR/s19reader.o(.text)
+                OBJDIR/bas_printf.o(.text)
+                OBJDIR/bas_string.o(.text)
+		OBJDIR/conout.o(.text)
+#if (FORMAT_ELF == 1)
+                OBJDIR/libgcc_helper.o(.text)
+#endif
+                OBJDIR/cache.o(.text)
+                OBJDIR/dma.o(.text)
+                OBJDIR/MCD_dmaApi.o(.text)
+                OBJDIR/MCD_tasks.o(.text)
+                OBJDIR/MCD_tasksInit.o(.text)
+
+                OBJDIR/video.o(.text)
+                OBJDIR/videl.o(.text)
+                OBJDIR/fbmem.o(.text)
+                OBJDIR/fbmon.o(.text)
+                OBJDIR/fbmodedb.o(.text)
+		OBJDIR/fnt_st_8x16.o(.text)
+                OBJDIR/offscreen.o(.text)
+
+                OBJDIR/x86emu.o(.text)
+                OBJDIR/x86emu_util.o(.text)
+                OBJDIR/x86pcibios.o(.text)
+                OBJDIR/x86biosemu.o(.text)
+
+		OBJDIR/i2c-algo-bit.o(.text)
+
+                OBJDIR/radeon_base.o(.text)
+                OBJDIR/radeon_accel.o(.text)
+                OBJDIR/radeon_cursor.o(.text)
+                OBJDIR/radeon_monitor.o(.text)
+		OBJDIR/radeon_i2c.o(.text)
+
+                OBJDIR/xhdi_sd.o(.text)
+                OBJDIR/xhdi_interface.o(.text)
+                OBJDIR/xhdi_vec.o(.text)
+
+#ifdef COMPILE_RAM
+                /*
+                 * if we compile to RAM anyway, there is no need to copy anything
+                 */
+                . = ALIGN(4);
+                __BAS_DATA_START = .;
+                *(.data)
+                __BAS_DATA_END = .;
+                __BAS_BSS_START = .;
+                *(.bss)
+                __BAS_BSS_END = .;
+#endif /* COMPILE_RAM */
+
+#if (FORMAT_ELF == 1)
+                *(.eh_frame)
+                *(.rodata)
+                *(.rodata.*)
+#endif
+        } > bas_rom
+
+
+#if (TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS)
+        /*
+         * put BaS .data and .bss segments to flash, but relocate it to RAM after initialize_hardware() ran
+         */
+        .bas :
+        AT (ALIGN(ADDR(.text) + SIZEOF(.text), 4))
+        {
+                . = ALIGN(4);       /* same alignment than AT() statement! */
+                __BAS_DATA_START = .;
+                *(.data)
+                __BAS_DATA_END = .;
+                __BAS_BSS_START = .;
+                *(.bss)
+                __BAS_BSS_END = .;
+
+                . = ALIGN(16);
+        } > bas_ram
+#endif
+
+        .driver_memory :
+        {
+                . = ALIGN(4);
+                _driver_mem_buffer = .;
+                //. = . + DRIVER_MEM_BUFFER_SIZE;
+        } > driver_ram
+
+        /*
+         * Global memory map
+         */
+
+        /* SDRAM Initialization */
+        ___SDRAM                = SDRAM_START;
+        ___SDRAM_SIZE           = SDRAM_SIZE;
+        _SDRAM_VECTOR_TABLE     = ___SDRAM;
+
+        /* ST-RAM */
+        __STRAM                 = ___SDRAM;
+        __STRAM_END             = __TOS;
+
+        /* TOS */
+        __TOS                   = 0x00e00000;
+
+        /* FastRAM */
+        __FASTRAM               = 0x10000000;
+        __TARGET_ADDRESS        = TARGET_ADDRESS;
+
+#if TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS
+        __FASTRAM_END           = __BAS_IN_RAM;
+#else
+        __FASTRAM_END           = TARGET_ADDRESS;
+#endif
+        __FASTRAM_SIZE          = __FASTRAM_END - __FASTRAM;
+
+        /* Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) */
+        ___BOOT_FLASH           = BOOTFLASH_BASE_ADDRESS;
+        ___BOOT_FLASH_SIZE      = BOOTFLASH_SIZE;
+
+#if TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS
+        /* BaS */
+        __BAS_LMA               = LOADADDR(.bas);
+        __BAS_IN_RAM            = ADDR(.bas);
+        __BAS_SIZE              = SIZEOF(.bas);
+#else
+        /* BaS is already in RAM - no need to copy anything */
+        __BAS_IN_RAM            = __FASTRAM_END;
+        __BAS_SIZE              = 0;
+        __BAS_LMA               = __BAS_IN_RAM;
+#endif
+
+        /* Other flash components */
+        __FIRETOS               = 0xe0400000;
+        __EMUTOS                = EMUTOS_BASE_ADDRESS;
+        __EMUTOS_SIZE           = 0x00100000;
+
+        /* where FPGA data lives in flash */
+        __FPGA_CONFIG       = 0xe0700000;
+        __FPGA_CONFIG_SIZE  = 0x100000;
+
+        /* VIDEO RAM BASIS */
+        __VRAM                  = 0x60000000;
+
+        /* Memory mapped registers */
+        __MBAR                  = 0xFF000000;
+
+        /* 32KB on-chip System SRAM */
+        __SYS_SRAM              = __MBAR + 0x10000;
+        __SYS_SRAM_SIZE         = 0x00008000;
+
+        /* MMU memory mapped registers */
+        __MMUBAR                = 0xFF040000;
+
+#if !defined(MACHINE_M54455)        /* MCF54455 does not have RAMBAR0 and RAMBAR1 registers */
+        /*
+         * 4KB on-chip Core SRAM0: -> exception table
+         */
+        __RAMBAR0               = 0xFF100000;
+        __RAMBAR0_SIZE          = 0x00001000;
+
+        /* 4KB on-chip Core SRAM1 */
+        __RAMBAR1               = 0xFF101000;
+        __RAMBAR1_SIZE          = 0x00001000;
+        __SUP_SP                = __RAMBAR1 + __RAMBAR1_SIZE - 4;
+#else
+        __RAMBAR0               = 0x80000000;   /* RAMBAR must be between 0x80000000 on MCF54455 */
+        __RAMBAR0_SIZE          = 0x1000;
+        __SUP_SP                = __RAMBAR0 + __RAMBAR0_SIZE + 0x1000 - 4;
+#endif
+
+    /*
+     * FPGA_JTAG_LOADED (if 1) indicates that FPGA configuration has been loaded through JTAG
+     * and shouldn't be overwritten on boot. For this to work (and not let us be faked
+     * by a random uninitialised value), __FPGA_JTAG_VALID is used as a "magic value" and must be
+     * 0xaffeaffe to make this work.
+     */
+#if !defined(MACHINE_M54455)        /* MCF54455 does not have RAMBAR0 and RAMBAR1 */
+    __FPGA_JTAG_LOADED      = __RAMBAR1;
+    __FPGA_JTAG_VALID       = __RAMBAR1 + 4;
+#else
+    __FPGA_JTAG_LOADED      = __RAMBAR0 + 0x1000;
+    __FPGA_JTAG_VALID       = __RAMBAR0 + 0x1000 + 4;
+#endif
+
+    /* system variables */
+    /* RAMBAR0 0 to 0x7FF -> exception vectors */
+    _rt_mod    = __RAMBAR0 + 0x800;
+    _rt_ssp    = __RAMBAR0 + 0x804;
+    _rt_usp    = __RAMBAR0 + 0x808;
+    _rt_vbr    = __RAMBAR0 + 0x80C;     /* (8)01 */
+    _rt_cacr   = __RAMBAR0 + 0x810;     /* 002 */
+    _rt_asid   = __RAMBAR0 + 0x814;     /* 003 */
+    _rt_acr0   = __RAMBAR0 + 0x818;     /* 004 */
+    _rt_acr1   = __RAMBAR0 + 0x81c;     /* 005 */
+    _rt_acr2   = __RAMBAR0 + 0x820;     /* 006 */
+    _rt_acr3   = __RAMBAR0 + 0x824;     /* 007 */
+    _rt_mmubar = __RAMBAR0 + 0x828;     /* 008 */
+    _rt_sr     = __RAMBAR0 + 0x82c;
+    _d0_save   = __RAMBAR0 + 0x830;
+    _a7_save   = __RAMBAR0 + 0x834;
+    _video_tlb = __RAMBAR0 + 0x838;
+    _video_sbt = __RAMBAR0 + 0x83C;
+    _rt_mbar   = __RAMBAR0 + 0x844;     /* (c)0f */
+}

BaS_gcc/bas_firebee.bdm

@@ -63,10 +63,6 @@ write 0xFF000104 0x710D0F00 4	# SDCR (lock SDMR and enable refresh)
 sleep 100
 
 load -v firebee/ram.elf
-write-ctrl 0x80e	0x2700
-write-ctrl 0x2	0xa50c8120
-dump-register SR
-dump-register CACR
-dump-register MBAR
+
 execute
 wait

BaS_gcc/basflash.lk.in

@@ -1,14 +1,16 @@
-#ifdef MACHINE_FIREBEE
+#if defined(MACHINE_FIREBEE)
 #include "firebee.h"
-#endif /* MACHINE_FIREBEE */
-
-#ifdef MACHINE_M5484LITE
+#elif defined(MACHINE_M5484LITE)
 #include "m5484l.h"
-#endif /* MACHINE_M5484LITE */
+#elif defined(MACHINE_M54455)
+#include "m54455.h"
+#else
+#error unknown machine
+#endif
 
 MEMORY
 {
-   flasher (WX) : ORIGIN = TARGET_ADDRESS, LENGTH = 0x00100000		/* target to load basflash */
+   flasher (WX) : ORIGIN = BFL_TARGET_ADDRESS, LENGTH = 0x00100000		/* target to load basflash */
 }
 
 SECTIONS

BaS_gcc/dma/MCD_dmaApi.c

@@ -0,0 +1,932 @@
+/*
+ * File:        MCD_dmaApi.c
+ * Purpose:     Main C file for multi-channel DMA API.
+ *
+ * Notes:
+ */
+
+#include "MCD_dma.h"
+#include "MCD_tasksInit.h"
+#include "MCD_progCheck.h"
+
+/********************************************************************/
+/*
+ * This is an API-internal pointer to the DMA's registers
+ */
+dmaRegs *MCD_dmaBar;
+
+/*
+ * These are the real and model task tables as generated by the
+ * build process
+ */
+extern TaskTableEntry MCD_realTaskTableSrc[NCHANNELS];
+extern TaskTableEntry MCD_modelTaskTableSrc[NUMOFVARIANTS];
+
+/*
+ * However, this (usually) gets relocated to on-chip SRAM, at which
+ * point we access them as these tables
+ */
+volatile TaskTableEntry *MCD_taskTable;
+TaskTableEntry *MCD_modelTaskTable;
+
+
+/*
+ * MCD_chStatus[] is an array of status indicators for remembering
+ * whether a DMA has ever been attempted on each channel, pausing
+ * status, etc.
+ */
+static int MCD_chStatus[NCHANNELS] =
+{
+    MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
+    MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
+    MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
+    MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA
+};
+
+/*
+ * Prototypes for local functions
+ */
+static void MCD_memcpy (int *dest, int *src, u32 size);
+static void MCD_resmActions (int channel);
+
+/*
+ * Buffer descriptors used for storage of progress info for single Dmas
+ * Also used as storage for the DMA for CRCs for single DMAs
+ * Otherwise, the DMA does not parse these buffer descriptors
+ */
+#ifdef MCD_INCLUDE_EU
+extern MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
+#else
+MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
+#endif
+MCD_bufDesc *MCD_relocBuffDesc;
+
+
+/*
+ * Defines for the debug control register's functions
+ */
+#define DBG_CTL_COMP1_TASK  (0x00002000) /* have comparator 1 look for a task # */
+#define DBG_CTL_ENABLE      (DBG_CTL_AUTO_ARM    | \
+                             DBG_CTL_BREAK       | \
+                             DBG_CTL_INT_BREAK   | \
+                             DBG_CTL_COMP1_TASK)
+#define DBG_CTL_DISABLE     (DBG_CTL_AUTO_ARM    | \
+                             DBG_CTL_INT_BREAK   | \
+                             DBG_CTL_COMP1_TASK)
+#define DBG_KILL_ALL_STAT   (0xFFFFFFFF)
+
+/*
+ * Offset to context save area where progress info is stored
+ */
+#define CSAVE_OFFSET        10
+
+/*
+ * Defines for Byte Swapping
+ */
+#define MCD_BYTE_SWAP_KILLER    0xFFF8888F
+#define MCD_NO_BYTE_SWAP_ATALL  0x00040000
+
+/*
+ * Execution Unit Identifiers
+ */
+#define MAC  0  /* legacy - not used */
+#define LUAC 1  /* legacy - not used */
+#define CRC  2  /* legacy - not used */
+#define LURC 3  /* Logic Unit with CRC */
+
+/*
+ * Task Identifiers
+ */
+#define TASK_CHAINNOEU  0
+#define TASK_SINGLENOEU 1
+#ifdef MCD_INCLUDE_EU
+#define TASK_CHAINEU    2
+#define TASK_SINGLEEU   3
+#define TASK_FECRX      4
+#define TASK_FECTX      5
+#else
+#define TASK_CHAINEU    0
+#define TASK_SINGLEEU   1
+#define TASK_FECRX      2
+#define TASK_FECTX      3
+#endif
+
+/*
+ * Structure to remember which variant is on which channel
+ * TBD- need this?
+ */
+typedef struct MCD_remVariants_struct MCD_remVariant;
+struct MCD_remVariants_struct
+{
+   int remDestRsdIncr[NCHANNELS];  /* -1,0,1 */
+   int remSrcRsdIncr[NCHANNELS];   /* -1,0,1 */
+   s16 remDestIncr[NCHANNELS];     /* DestIncr */
+   s16 remSrcIncr[NCHANNELS];      /* srcIncr */
+   u32 remXferSize[NCHANNELS];     /* xferSize */
+};
+
+/*
+ * Structure to remember the startDma parameters for each channel
+ */
+MCD_remVariant MCD_remVariants;
+/********************************************************************/
+/*
+ * Function: MCD_initDma
+ * Purpose:  Initializes the DMA API by setting up a pointer to the DMA
+ *           registers, relocating and creating the appropriate task
+ *           structures, and setting up some global settings
+ * Arguments:
+ *  dmaBarAddr    - pointer to the multichannel DMA registers
+ *  taskTableDest - location to move DMA task code and structs to
+ *  flags         - operational parameters
+ * Return Value:
+ *  MCD_TABLE_UNALIGNED if taskTableDest is not 512-byte aligned
+ *  MCD_OK otherwise
+ */
+extern u32 MCD_funcDescTab0[];
+
+int MCD_initDma (dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags)
+{
+    int i;
+    TaskTableEntry *entryPtr;
+
+    /* setup the local pointer to register set */
+    MCD_dmaBar = dmaBarAddr;
+
+    /* do we need to move/create a task table */
+    if ((flags & MCD_RELOC_TASKS) != 0)
+    {
+        int fixedSize;
+        u32 *fixedPtr;
+        /*int *tablePtr = taskTableDest;TBD*/
+        int varTabsOffset, funcDescTabsOffset, contextSavesOffset;
+        int taskDescTabsOffset;
+        int taskTableSize, varTabsSize, funcDescTabsSize, contextSavesSize;
+        int taskDescTabSize;
+
+
+        /* check if physical address is aligned on 512 byte boundary */
+        if (((u32) taskTableDest & 0x000001ff) != 0)
+            return MCD_TABLE_UNALIGNED;
+
+        MCD_taskTable = taskTableDest; /* set up local pointer to task Table */
+
+        /*
+         * Create a task table:
+         * - compute aligned base offsets for variable tables and
+         *   function descriptor tables, then
+         * - loop through the task table and setup the pointers
+         * - copy over model task table with the the actual task descriptor
+         *   tables
+         */
+
+        taskTableSize = NCHANNELS * sizeof(TaskTableEntry);
+        /* align variable tables to size */
+        varTabsOffset = taskTableSize + (u32)taskTableDest;
+        if ((varTabsOffset & (VAR_TAB_SIZE - 1)) != 0)
+            varTabsOffset = (varTabsOffset + VAR_TAB_SIZE) & (~VAR_TAB_SIZE);
+        /* align function descriptor tables */
+        varTabsSize = NCHANNELS * VAR_TAB_SIZE;
+        funcDescTabsOffset = varTabsOffset + varTabsSize;
+
+        if ((funcDescTabsOffset & (FUNCDESC_TAB_SIZE - 1)) != 0)
+            funcDescTabsOffset = (funcDescTabsOffset + FUNCDESC_TAB_SIZE) &
+            (~FUNCDESC_TAB_SIZE);
+
+        funcDescTabsSize = FUNCDESC_TAB_NUM * FUNCDESC_TAB_SIZE;
+        contextSavesOffset = funcDescTabsOffset + funcDescTabsSize;
+        contextSavesSize = (NCHANNELS * CONTEXT_SAVE_SIZE);
+        fixedSize = taskTableSize + varTabsSize + funcDescTabsSize +
+                    contextSavesSize;
+
+        /* zero the thing out */
+        fixedPtr = (u32 *)taskTableDest;
+        for (i = 0;i<(fixedSize/4);i++)
+            fixedPtr[i] = 0;
+
+        entryPtr = (TaskTableEntry*)MCD_taskTable;
+        /* set up fixed pointers */
+        for (i = 0; i < NCHANNELS; i++)
+        {
+            entryPtr[i].varTab = (u32)varTabsOffset; /* update ptr to local value */
+            entryPtr[i].FDTandFlags = (u32)funcDescTabsOffset | MCD_TT_FLAGS_DEF;
+            entryPtr[i].contextSaveSpace = (u32)contextSavesOffset;
+            varTabsOffset += VAR_TAB_SIZE;
+#ifdef MCD_INCLUDE_EU /* if not there is only one, just point to the same one */
+            funcDescTabsOffset += FUNCDESC_TAB_SIZE;
+#endif
+            contextSavesOffset += CONTEXT_SAVE_SIZE;
+        }
+        /* copy over the function descriptor table */
+        for ( i = 0; i < FUNCDESC_TAB_NUM; i++)
+        {
+            MCD_memcpy((void*)(entryPtr[i].FDTandFlags & ~MCD_TT_FLAGS_MASK),
+                       (void*)MCD_funcDescTab0, FUNCDESC_TAB_SIZE);
+        }
+
+        /* copy model task table to where the context saves stuff leaves off*/
+        MCD_modelTaskTable = (TaskTableEntry*)contextSavesOffset;
+
+        MCD_memcpy ((void*)MCD_modelTaskTable, (void*)MCD_modelTaskTableSrc,
+                    NUMOFVARIANTS * sizeof(TaskTableEntry));
+
+        entryPtr = MCD_modelTaskTable; /* point to local version of
+                                                            model task table */
+        taskDescTabsOffset = (u32)MCD_modelTaskTable +
+                            (NUMOFVARIANTS * sizeof(TaskTableEntry));
+
+        /* copy actual task code and update TDT ptrs in local model task table */
+        for (i = 0; i < NUMOFVARIANTS; i++)
+        {
+            taskDescTabSize = entryPtr[i].TDTend - entryPtr[i].TDTstart + 4;
+            MCD_memcpy ((void*)taskDescTabsOffset, (void*)entryPtr[i].TDTstart, taskDescTabSize);
+            entryPtr[i].TDTstart = (u32)taskDescTabsOffset;
+            taskDescTabsOffset += taskDescTabSize;
+            entryPtr[i].TDTend = (u32)taskDescTabsOffset - 4;
+        }
+#ifdef MCD_INCLUDE_EU /* Tack single DMA BDs onto end of code so API controls
+                         where they are since DMA might write to them */
+        MCD_relocBuffDesc = (MCD_bufDesc*)(entryPtr[NUMOFVARIANTS - 1].TDTend + 4);
+#else /* DMA does not touch them so they can be wherever and we don't need to
+         waste SRAM on them */
+        MCD_relocBuffDesc = MCD_singleBufDescs;
+#endif
+    }
+    else
+    {
+        /* point the would-be relocated task tables and the
+        buffer descriptors to the ones the linker generated */
+
+        if (((u32)MCD_realTaskTableSrc & 0x000001ff) != 0)
+            return(MCD_TABLE_UNALIGNED);
+
+        /* need to add code to make sure that every thing else is aligned properly TBD*/
+        /* this is problematic if we init more than once or after running tasks,
+            need to add variable to see if we have aleady init'd */
+        entryPtr = MCD_realTaskTableSrc;
+        for (i = 0; i < NCHANNELS; i++)
+        {
+            if (((entryPtr[i].varTab & (VAR_TAB_SIZE - 1)) != 0) ||
+                ((entryPtr[i].FDTandFlags & (FUNCDESC_TAB_SIZE - 1)) != 0))
+                return(MCD_TABLE_UNALIGNED);
+        }
+
+        MCD_taskTable = MCD_realTaskTableSrc;
+        MCD_modelTaskTable = MCD_modelTaskTableSrc;
+        MCD_relocBuffDesc = MCD_singleBufDescs;
+    }
+
+
+    /* Make all channels as totally inactive, and remember them as such: */
+
+    MCD_dmaBar->taskbar = (u32) MCD_taskTable;
+    for (i = 0;  i < NCHANNELS;  i++)
+    {
+        MCD_dmaBar->taskControl[i] = 0x0;
+        MCD_chStatus[i] = MCD_NO_DMA;
+    }
+
+   /* Set up pausing mechanism to inactive state: */
+    MCD_dmaBar->debugComp1 = 0;  /* no particular values yet for either comparator registers */
+    MCD_dmaBar->debugComp2 = 0;
+    MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
+    MCD_dmaBar->debugStatus = DBG_KILL_ALL_STAT;
+
+    /* enable or disable commbus prefetch, really need an ifdef or
+       something to keep from trying to set this in the 8220 */
+    if ((flags & MCD_COMM_PREFETCH_EN) != 0)
+        MCD_dmaBar->ptdControl &= ~PTD_CTL_COMM_PREFETCH;
+    else
+        MCD_dmaBar->ptdControl |= PTD_CTL_COMM_PREFETCH;
+
+    return MCD_OK;
+}
+/*********************** End of MCD_initDma() ***********************/
+
+/********************************************************************/
+/* Function:   MCD_dmaStatus
+ * Purpose:    Returns the status of the DMA on the requested channel
+ * Arguments:  channel - channel number
+ * Returns:    Predefined status indicators
+ */
+int MCD_dmaStatus (int channel)
+{
+    u16 tcrValue;
+
+    if((channel < 0) || (channel >= NCHANNELS))
+        return(MCD_CHANNEL_INVALID);
+
+    tcrValue = MCD_dmaBar->taskControl[channel];
+    if ((tcrValue & TASK_CTL_EN) == 0)
+    {  /* nothing running */
+        /* if last reported with task enabled */
+        if (   MCD_chStatus[channel] == MCD_RUNNING
+            || MCD_chStatus[channel] == MCD_IDLE)
+            MCD_chStatus[channel] = MCD_DONE;
+    }
+    else /* something is running */
+    {
+        /* There are three possibilities: paused, running or idle. */
+        if (   MCD_chStatus[channel] == MCD_RUNNING
+            || MCD_chStatus[channel] == MCD_IDLE)
+        {
+            MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT;
+            /* This register is selected to know which initiator is
+            actually asserted. */
+            if ((MCD_dmaBar->ptdDebug >> channel ) & 0x1 )
+                MCD_chStatus[channel] = MCD_RUNNING;
+            else
+                MCD_chStatus[channel] = MCD_IDLE;
+        /* do not change the status if it is already paused. */
+        }
+    }
+    return MCD_chStatus[channel];
+}
+/******************** End of MCD_dmaStatus() ************************/
+
+/********************************************************************/
+/* Function:    MCD_startDma
+ * Ppurpose:    Starts a particular kind of DMA
+ * Arguments:   see below
+ * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
+ */
+
+int MCD_startDma (
+    int  channel,   /* the channel on which to run the DMA */
+    s8   *srcAddr,  /* the address to move data from, or physical buffer-descriptor address */
+    s16  srcIncr,   /* the amount to increment the source address per transfer */
+    s8   *destAddr, /* the address to move data to */
+    s16  destIncr,  /* the amount to increment the destination address per transfer */
+    u32  dmaSize,   /* the number of bytes to transfer independent of the transfer size */
+    u32  xferSize,  /* the number bytes in of each data movement (1, 2, or 4) */
+    u32  initiator, /* what device initiates the DMA */
+    int  priority,  /* priority of the DMA */
+    u32  flags,     /* flags describing the DMA */
+    u32  funcDesc   /* a description of byte swapping, bit swapping, and CRC actions */
+#ifdef MCD_NEED_ADDR_TRANS
+    s8   *srcAddrVirt /* virtual buffer descriptor address TBD*/
+#endif
+)
+{
+    int srcRsdIncr, destRsdIncr;
+    int *cSave;
+    short xferSizeIncr;
+    int tcrCount = 0;
+#ifdef MCD_INCLUDE_EU
+    u32 *realFuncArray;
+#endif
+
+    if((channel < 0) || (channel >= NCHANNELS))
+        return(MCD_CHANNEL_INVALID);
+
+    /* tbd - need to determine the proper response to a bad funcDesc when not
+       including EU functions, for now, assign a benign funcDesc, but maybe
+       should return an error */
+#ifndef MCD_INCLUDE_EU
+    funcDesc = MCD_FUNC_NOEU1;
+#endif
+
+#ifdef MCD_DEBUG
+printf("startDma:Setting up params\n");
+#endif
+   /* Set us up for task-wise priority.  We don't technically need to do this on every start, but
+      since the register involved is in the same longword as other registers that users are in control
+      of, setting it more than once is probably preferable.  That since the documentation doesn't seem
+      to be completely consistent about the nature of the PTD control register. */
+    MCD_dmaBar->ptdControl |= (u16) 0x8000;
+#if 1 /* Not sure what we need to keep here rtm TBD */
+    /* Calculate additional parameters to the regular DMA calls. */
+    srcRsdIncr = srcIncr < 0 ? -1 : (srcIncr > 0 ? 1 : 0);
+    destRsdIncr = destIncr < 0 ? -1 : (destIncr > 0 ? 1 : 0);
+
+    xferSizeIncr = (xferSize & 0xffff) | 0x20000000;
+
+    /* Remember for each channel which variant is running. */
+    MCD_remVariants.remSrcRsdIncr[channel] = srcRsdIncr;
+    MCD_remVariants.remDestRsdIncr[channel] = destRsdIncr;
+    MCD_remVariants.remDestIncr[channel] = destIncr;
+    MCD_remVariants.remSrcIncr[channel] = srcIncr;
+    MCD_remVariants.remXferSize[channel] = xferSize;
+#endif
+
+    cSave = (int*)(MCD_taskTable[channel].contextSaveSpace) + CSAVE_OFFSET + CURRBD;
+
+#ifdef MCD_INCLUDE_EU /* may move this to EU specific calls */
+    realFuncArray = (u32 *) (MCD_taskTable[channel].FDTandFlags & 0xffffff00);
+    /* Modify the LURC's normal and byte-residue-loop functions according to parameter. */
+    realFuncArray[(LURC*16)] = xferSize == 4 ?
+                                 funcDesc : xferSize == 2 ?
+                                     funcDesc & 0xfffff00f : funcDesc & 0xffff000f;
+    realFuncArray[(LURC*16+1)] = (funcDesc & MCD_BYTE_SWAP_KILLER) | MCD_NO_BYTE_SWAP_ATALL;
+#endif
+   /* Write the initiator field in the TCR, and also set the initiator-hold
+      bit.  Note that,due to a hardware quirk, this could collide with an
+      MDE access to the initiator-register file, so we have to verify that the write
+      reads back correctly. */
+
+    MCD_dmaBar->taskControl[channel] =
+        (initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM;
+
+    while(((MCD_dmaBar->taskControl[channel] & 0x1fff) !=
+          ((initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM)) &&
+            (tcrCount < 1000))
+    {
+        tcrCount++;
+        /*MCD_dmaBar->ptd_tcr[channel] = (initiator << 8) | 0x0020;*/
+        MCD_dmaBar->taskControl[channel] =
+            (initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM;
+    }
+
+    MCD_dmaBar->priority[channel] = (u8)priority & PRIORITY_PRI_MASK;
+    /* should be albe to handle this stuff with only one write to ts reg - tbd */
+    if (channel < 8 && channel >= 0)
+    {
+        MCD_dmaBar->taskSize0 &= ~(0xf << (7-channel)*4);
+        MCD_dmaBar->taskSize0 |= (xferSize & 3) << (((7 - channel)*4) + 2);
+        MCD_dmaBar->taskSize0 |= (xferSize & 3) << ((7 - channel)*4);
+    }
+    else
+    {
+        MCD_dmaBar->taskSize1 &= ~(0xf << (15-channel)*4);
+        MCD_dmaBar->taskSize1 |= (xferSize & 3) << (((15 - channel)*4) + 2);
+        MCD_dmaBar->taskSize1 |= (xferSize & 3) << ((15 - channel)*4);
+    }
+
+    /* setup task table flags/options which mostly control the line buffers */
+    MCD_taskTable[channel].FDTandFlags &= ~MCD_TT_FLAGS_MASK;
+    MCD_taskTable[channel].FDTandFlags |= (MCD_TT_FLAGS_MASK & flags);
+
+    if (flags & MCD_FECTX_DMA)
+    {
+        /* TDTStart and TDTEnd */
+        MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_FECTX].TDTstart;
+        MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_FECTX].TDTend;
+        MCD_startDmaENetXmit(srcAddr, srcAddr, destAddr, MCD_taskTable, channel);
+    }
+    else if (flags & MCD_FECRX_DMA)
+    {
+        /* TDTStart and TDTEnd */
+        MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_FECRX].TDTstart;
+        MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_FECRX].TDTend;
+        MCD_startDmaENetRcv(srcAddr, srcAddr, destAddr, MCD_taskTable, channel);
+    }
+    else if(flags & MCD_SINGLE_DMA)
+    {
+        /* this buffer descriptor is used for storing off initial parameters for later
+           progress query calculation and for the DMA to write the resulting checksum
+           The DMA does not use this to determine how to operate, that info is passed
+           with the init routine*/
+        MCD_relocBuffDesc[channel].srcAddr = srcAddr;
+        MCD_relocBuffDesc[channel].destAddr = destAddr;
+        MCD_relocBuffDesc[channel].lastDestAddr = destAddr;  /* definitely not its final value */
+        MCD_relocBuffDesc[channel].dmaSize = dmaSize;
+        MCD_relocBuffDesc[channel].flags = 0;       /* not used */
+        MCD_relocBuffDesc[channel].csumResult = 0;  /* not used */
+        MCD_relocBuffDesc[channel].next = 0;        /* not used */
+
+        /* Initialize the progress-querying stuff to show no progress:*/
+        ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET] = (int)srcAddr;
+        ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET] = (int)destAddr;
+        ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0;
+        ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET] =
+                                             (u32) &(MCD_relocBuffDesc[channel]);
+        /* tbd - need to keep the user from trying to call the EU routine
+           when MCD_INCLUDE_EU is not defined */
+        if( funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2)
+        {
+           /* TDTStart and TDTEnd */
+           MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_SINGLENOEU].TDTstart;
+           MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_SINGLENOEU].TDTend;
+           MCD_startDmaSingleNoEu(srcAddr, srcIncr, destAddr, destIncr, dmaSize,
+                                xferSizeIncr, flags, (int *)&(MCD_relocBuffDesc[channel]), cSave,
+                                MCD_taskTable, channel);
+        }
+        else
+        {
+           /* TDTStart and TDTEnd */
+           MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_SINGLEEU].TDTstart;
+           MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_SINGLEEU].TDTend;
+           MCD_startDmaSingleEu(srcAddr, srcIncr, destAddr, destIncr, dmaSize,
+                              xferSizeIncr, flags, (int *)&(MCD_relocBuffDesc[channel]), cSave,
+                              MCD_taskTable, channel);
+        }
+    }
+    else
+    { /* chained DMAS */
+        /* Initialize the progress-querying stuff to show no progress:*/
+#if 1 /* (!defined(MCD_NEED_ADDR_TRANS)) */
+        ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
+          = (int)((MCD_bufDesc*) srcAddr)->srcAddr;
+        ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
+          = (int)((MCD_bufDesc*) srcAddr)->destAddr;
+#else /* if using address translation, need the virtual addr of the first buffdesc */
+        ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
+          = (int)((MCD_bufDesc*) srcAddrVirt)->srcAddr;
+        ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
+          = (int)((MCD_bufDesc*) srcAddrVirt)->destAddr;
+#endif
+        ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0;
+        ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET] = (u32) srcAddr;
+
+        if( funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2)
+        {
+          /*TDTStart and TDTEnd*/
+          MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_CHAINNOEU].TDTstart;
+          MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_CHAINNOEU].TDTend;
+          MCD_startDmaChainNoEu((int *)srcAddr, srcIncr, destIncr, xferSize,
+                                    xferSizeIncr, cSave, MCD_taskTable, channel);
+        }
+        else
+        {
+          /*TDTStart and TDTEnd*/
+          MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_CHAINEU].TDTstart;
+          MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_CHAINEU].TDTend;
+          MCD_startDmaChainEu((int *)srcAddr, srcIncr, destIncr, xferSize,
+                                 xferSizeIncr, cSave, MCD_taskTable, channel);
+        }
+    }
+    MCD_chStatus[channel] = MCD_IDLE;
+    return MCD_OK;
+}
+
+/************************ End of MCD_startDma() *********************/
+
+/********************************************************************/
+/* Function:    MCD_XferProgrQuery
+ * Purpose:     Returns progress of DMA on requested channel
+ * Arguments:   channel - channel to retrieve progress for
+ *              progRep - pointer to user supplied MCD_XferProg struct
+ * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
+ *
+ * Notes:
+ *  MCD_XferProgrQuery() upon completing or after aborting a DMA, or
+ *  while the DMA is in progress, this function returns the first
+ *  DMA-destination address not (or not yet) used in the DMA. When
+ *  encountering a non-ready buffer descriptor, the information for
+ *  the last completed descriptor is returned.
+ *
+ *  MCD_XferProgQuery() has to avoid the possibility of getting
+ *  partially-updated information in the event that we should happen
+ *  to query DMA progress just as the DMA is updating it. It does that
+ *  by taking advantage of the fact context is not saved frequently for
+ *  the most part. We therefore read it at least twice until we get the
+ *  same information twice in a row.
+ *
+ *  Because a small, but not insignificant, amount of time is required
+ *  to write out the progress-query information, especially upon
+ *  completion of the DMA, it would be wise to guarantee some time lag
+ *  between successive readings of the progress-query information.
+ */
+
+/*
+ * How many iterations of the loop below to execute to stabilize values
+ */
+#define STABTIME 0
+
+int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep)
+{
+    MCD_XferProg prevRep;
+    int again;  /* true if we are to try again to get consistent results */
+    int i;  /* used as a time-waste counter */
+    int destDiffBytes; /* Total number of bytes that we think actually got xfered. */
+    int numIterations; /* number of iterations */
+    int bytesNotXfered; /* bytes that did not get xfered. */
+    s8 *LWAlignedInitDestAddr, *LWAlignedCurrDestAddr;
+    int subModVal, addModVal; /* Mode values to added and subtracted from the
+                                final destAddr */
+
+    if((channel < 0) || (channel >= NCHANNELS))
+        return(MCD_CHANNEL_INVALID);
+
+    /* Read a trial value for the progress-reporting values*/
+    prevRep.lastSrcAddr =
+          (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET];
+    prevRep.lastDestAddr =
+          (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET];
+    prevRep.dmaSize = ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET];
+    prevRep.currBufDesc =
+          (MCD_bufDesc*) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET];
+    /* Repeatedly reread those values until they match previous values: */
+    do {
+        /* Waste a little bit of time to ensure stability: */
+        for (i = 0;  i < STABTIME;  i++)
+            i += i >> 2;  /* make sure this loop does something so that it doesn't get optimized out */
+        /* Check them again: */
+        progRep->lastSrcAddr =
+            (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET];
+        progRep->lastDestAddr =
+            (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET];
+        progRep->dmaSize = ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET];
+        progRep->currBufDesc =
+            (MCD_bufDesc*) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET];
+       /* See if they match: */
+       if (   prevRep.lastSrcAddr != progRep->lastSrcAddr
+           || prevRep.lastDestAddr != progRep->lastDestAddr
+           || prevRep.dmaSize != progRep->dmaSize
+           || prevRep.currBufDesc != progRep->currBufDesc)
+       {
+          /* If they don't match, remember previous values and try again:*/
+          prevRep.lastSrcAddr = progRep->lastSrcAddr;
+          prevRep.lastDestAddr = progRep->lastDestAddr;
+          prevRep.dmaSize = progRep->dmaSize;
+          prevRep.currBufDesc = progRep->currBufDesc;
+          again = MCD_TRUE;
+       }
+       else
+          again = MCD_FALSE;
+    } while (again == MCD_TRUE);
+
+
+    /* Update the dCount, srcAddr and destAddr */
+    /* To calculate dmaCount, we consider destination address. C
+       overs M1,P1,Z for destination */
+    switch(MCD_remVariants.remDestRsdIncr[channel]) {
+        case MINUS1:
+           subModVal = ((int)progRep->lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
+           addModVal = ((int)progRep->currBufDesc->destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
+           LWAlignedInitDestAddr = (progRep->currBufDesc->destAddr) - addModVal;
+           LWAlignedCurrDestAddr = (progRep->lastDestAddr) - subModVal;
+           destDiffBytes = LWAlignedInitDestAddr - LWAlignedCurrDestAddr;
+           bytesNotXfered = (destDiffBytes/MCD_remVariants.remDestIncr[channel]) *
+                            ( MCD_remVariants.remDestIncr[channel]
+                            + MCD_remVariants.remXferSize[channel]);
+           progRep->dmaSize = destDiffBytes - bytesNotXfered + addModVal - subModVal;
+           break;
+        case ZERO:
+           progRep->lastDestAddr = progRep->currBufDesc->destAddr;
+           break;
+        case PLUS1:
+           /* This value has to be subtracted from the final calculated dCount. */
+           subModVal = ((int)progRep->currBufDesc->destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
+           /* These bytes are already in lastDestAddr. */
+            addModVal = ((int)progRep->lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
+            LWAlignedInitDestAddr = (progRep->currBufDesc->destAddr) - subModVal;
+            LWAlignedCurrDestAddr = (progRep->lastDestAddr) - addModVal;
+            destDiffBytes = (progRep->lastDestAddr - LWAlignedInitDestAddr);
+            numIterations = ( LWAlignedCurrDestAddr - LWAlignedInitDestAddr)/MCD_remVariants.remDestIncr[channel];
+            bytesNotXfered =  numIterations *
+                ( MCD_remVariants.remDestIncr[channel]
+                  - MCD_remVariants.remXferSize[channel]);
+           progRep->dmaSize = destDiffBytes - bytesNotXfered - subModVal;
+           break;
+        default:
+           break;
+    }
+
+    /* This covers M1,P1,Z for source */
+    switch(MCD_remVariants.remSrcRsdIncr[channel]) {
+        case MINUS1:
+            progRep->lastSrcAddr =
+                progRep->currBufDesc->srcAddr +
+                 ( MCD_remVariants.remSrcIncr[channel] *
+                   (progRep->dmaSize/MCD_remVariants.remXferSize[channel]));
+            break;
+        case ZERO:
+            progRep->lastSrcAddr = progRep->currBufDesc->srcAddr;
+            break;
+       case PLUS1:
+            progRep->lastSrcAddr =
+                progRep->currBufDesc->srcAddr +
+                 ( MCD_remVariants.remSrcIncr[channel] *
+                   (progRep->dmaSize/MCD_remVariants.remXferSize[channel]));
+          break;
+       default: break;
+    }
+
+    return MCD_OK;
+}
+/******************* End of MCD_XferProgrQuery() ********************/
+
+/********************************************************************/
+/* MCD_resmActions() does the majority of the actions of a DMA resume.
+ * It is called from MCD_killDma() and MCD_resumeDma().  It has to be
+ * a separate function because the kill function has to negate the task
+ * enable before resuming it, but the resume function has to do nothing
+ * if there is no DMA on that channel (i.e., if the enable bit is 0).
+ */
+static void MCD_resmActions (int channel)
+{
+   MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
+   MCD_dmaBar->debugStatus = MCD_dmaBar->debugStatus;
+   MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT; /* This register is selected to know
+                                        which initiator is actually asserted. */
+   if((MCD_dmaBar->ptdDebug >> channel ) & 0x1)
+       MCD_chStatus[channel] = MCD_RUNNING;
+   else
+       MCD_chStatus[channel] = MCD_IDLE;
+}
+/********************* End of MCD_resmActions() *********************/
+
+/********************************************************************/
+/* Function:    MCD_killDma
+ * Purpose:     Halt the DMA on the requested channel, without any
+ *              intention of resuming the DMA.
+ * Arguments:   channel - requested channel
+ * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
+ *
+ * Notes:
+ *  A DMA may be killed from any state, including paused state, and it
+ *  always goes to the MCD_HALTED state even if it is killed while in
+ *  the MCD_NO_DMA or MCD_IDLE states.
+ */
+int MCD_killDma (int channel)
+{
+   /* MCD_XferProg progRep; */
+
+    if((channel < 0) || (channel >= NCHANNELS))
+        return(MCD_CHANNEL_INVALID);
+
+    MCD_dmaBar->taskControl[channel] = 0x0;
+    MCD_resumeDma (channel);
+    /*
+     * This must be after the write to the TCR so that the task doesn't
+     * start up again momentarily, and before the status assignment so
+     * as to override whatever MCD_resumeDma() may do to the channel
+     * status.
+     */
+    MCD_chStatus[channel] = MCD_HALTED;
+
+    /*
+     * Update the current buffer descriptor's lastDestAddr field
+     *
+     * MCD_XferProgrQuery (channel, &progRep);
+     * progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
+     */
+    return MCD_OK;
+}
+/************************ End of MCD_killDma() **********************/
+
+/********************************************************************/
+/* Function:    MCD_continDma
+ * Purpose:     Continue a DMA which as stopped due to encountering an
+ *              unready buffer descriptor.
+ * Arguments:   channel - channel to continue the DMA on
+ * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
+ *
+ * Notes:
+ *  This routine does not check to see if there is a task which can
+ *  be continued. Also this routine should not be used with single DMAs.
+ */
+int MCD_continDma (int channel)
+{
+    if((channel < 0) || (channel >= NCHANNELS))
+        return(MCD_CHANNEL_INVALID);
+
+    MCD_dmaBar->taskControl[channel] |= TASK_CTL_EN;
+    MCD_chStatus[channel] = MCD_RUNNING;
+
+    return MCD_OK;
+}
+/********************** End of MCD_continDma() **********************/
+
+/*********************************************************************
+ * MCD_pauseDma() and MCD_resumeDma() below use the DMA's debug unit
+ * to freeze a task and resume it.  We freeze a task by breakpointing
+ * on the stated task.  That is, not any specific place in the task,
+ * but any time that task executes.  In particular, when that task
+ * executes, we want to freeze that task and only that task.
+ *
+ * The bits of the debug control register influence interrupts vs.
+ * breakpoints as follows:
+ * - Bits 14 and 0 enable or disable debug functions.  If enabled, you
+ *   will get the interrupt but you may or may not get a breakpoint.
+ * - Bits 2 and 1 decide whether you also get a breakpoint in addition
+ *   to an interrupt.
+ *
+ * The debug unit can do these actions in response to either internally
+ * detected breakpoint conditions from the comparators, or in response
+ * to the external breakpoint pin, or both.
+ * - Bits 14 and 1 perform the above-described functions for
+ *   internally-generated conditions, i.e., the debug comparators.
+ * - Bits 0 and 2 perform the above-described functions for external
+ *   conditions, i.e., the breakpoint external pin.
+ *
+ * Note that, although you "always" get the interrupt when you turn
+ * the debug functions, the interrupt can nevertheless, if desired, be
+ * masked by the corresponding bit in the PTD's IMR. Note also that
+ * this means that bits 14 and 0 must enable debug functions before
+ * bits 1 and 2, respectively, have any effect.
+ *
+ * NOTE: It's extremely important to not pause more than one DMA channel
+ *  at a time.
+ ********************************************************************/
+
+/********************************************************************/
+/* Function:    MCD_pauseDma
+ * Purpose:     Pauses the DMA on a given channel (if any DMA is running
+ *              on that channel).
+ * Arguments:   channel
+ * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
+ */
+int MCD_pauseDma (int channel)
+{
+    /* MCD_XferProg progRep; */
+
+    if((channel < 0) || (channel >= NCHANNELS))
+        return(MCD_CHANNEL_INVALID);
+
+    if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN)
+    {
+        MCD_dmaBar->debugComp1 = channel;
+        MCD_dmaBar->debugControl = DBG_CTL_ENABLE | (1 << (channel + 16));
+        MCD_chStatus[channel] = MCD_PAUSED;
+
+        /*
+         * Update the current buffer descriptor's lastDestAddr field
+         *
+         * MCD_XferProgrQuery (channel, &progRep);
+         * progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
+         */
+    }
+    return MCD_OK;
+}
+/************************* End of MCD_pauseDma() ********************/
+
+/********************************************************************/
+/* Function:    MCD_resumeDma
+ * Purpose:     Resumes the DMA on a given channel (if any DMA is
+ *              running on that channel).
+ * Arguments:   channel - channel on which to resume DMA
+ * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
+ */
+int MCD_resumeDma (int channel)
+{
+    if((channel < 0) || (channel >= NCHANNELS))
+        return(MCD_CHANNEL_INVALID);
+
+    if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN)
+        MCD_resmActions (channel);
+
+    return MCD_OK;
+}
+/************************ End of MCD_resumeDma() ********************/
+
+/********************************************************************/
+/* Function:    MCD_csumQuery
+ * Purpose:     Provide the checksum after performing a non-chained DMA
+ * Arguments:   channel - channel to report on
+ *              csum - pointer to where to write the checksum/CRC
+ * Returns:     MCD_ERROR if the channel is invalid, else MCD_OK
+ *
+ * Notes:
+ *
+ */
+int MCD_csumQuery (int channel, u32 *csum)
+{
+#ifdef MCD_INCLUDE_EU
+    if((channel < 0) || (channel >= NCHANNELS))
+        return(MCD_CHANNEL_INVALID);
+
+    *csum = MCD_relocBuffDesc[channel].csumResult;
+    return(MCD_OK);
+#else
+    return MCD_ERROR;
+#endif
+}
+/*********************** End of MCD_resumeDma() *********************/
+
+/********************************************************************/
+/* Function:    MCD_getCodeSize
+ * Purpose:     Provide the size requirements of the microcoded tasks
+ * Returns:     Size in bytes
+ */
+int MCD_getCodeSize(void)
+{
+#ifdef MCD_INCLUDE_EU
+    return(0x2b5c);
+#else
+    return(0x173c);
+#endif
+}
+/********************** End of MCD_getCodeSize() ********************/
+
+/********************************************************************/
+/* Function:    MCD_getVersion
+ * Purpose:     Provide the version string and number
+ * Arguments:   longVersion - user supplied pointer to a pointer to a char
+ *                    which points to the version string
+ * Returns:     Version number and version string (by reference)
+ */
+char MCD_versionString[] = "Multi-channel DMA API Alpha v0.3 (2004-04-26)";
+#define MCD_REV_MAJOR   0x00
+#define MCD_REV_MINOR   0x03
+
+int MCD_getVersion(char **longVersion)
+{
+    *longVersion = MCD_versionString;
+    return((MCD_REV_MAJOR << 8) | MCD_REV_MINOR);
+}
+/********************** End of MCD_getVersion() *********************/
+
+/********************************************************************/
+/* Private version of memcpy()
+ * Note that everything this is used for is longword-aligned.
+ */
+static void MCD_memcpy (int *dest, int *src, u32 size)
+{
+    u32 i;
+
+    for (i = 0;  i < size;  i += sizeof(int), dest++, src++)
+        *dest = *src;
+}
+/********************************************************************/

BaS_gcc/dma/MCD_tasks.c

@@ -7,253 +7,253 @@
 
 #include "MCD_dma.h"
 
-uint32_t MCD_varTab0[];
-uint32_t MCD_varTab1[];
-uint32_t MCD_varTab2[];
-uint32_t MCD_varTab3[];
-uint32_t MCD_varTab4[];
-uint32_t MCD_varTab5[];
-uint32_t MCD_varTab6[];
-uint32_t MCD_varTab7[];
-uint32_t MCD_varTab8[];
-uint32_t MCD_varTab9[];
-uint32_t MCD_varTab10[];
-uint32_t MCD_varTab11[];
-uint32_t MCD_varTab12[];
-uint32_t MCD_varTab13[];
-uint32_t MCD_varTab14[];
-uint32_t MCD_varTab15[];
+u32 MCD_varTab0[];
+u32 MCD_varTab1[];
+u32 MCD_varTab2[];
+u32 MCD_varTab3[];
+u32 MCD_varTab4[];
+u32 MCD_varTab5[];
+u32 MCD_varTab6[];
+u32 MCD_varTab7[];
+u32 MCD_varTab8[];
+u32 MCD_varTab9[];
+u32 MCD_varTab10[];
+u32 MCD_varTab11[];
+u32 MCD_varTab12[];
+u32 MCD_varTab13[];
+u32 MCD_varTab14[];
+u32 MCD_varTab15[];
 
-uint32_t MCD_funcDescTab0[];
+u32 MCD_funcDescTab0[];
 #ifdef MCD_INCLUDE_EU
-uint32_t MCD_funcDescTab1[];
-uint32_t MCD_funcDescTab2[];
-uint32_t MCD_funcDescTab3[];
-uint32_t MCD_funcDescTab4[];
-uint32_t MCD_funcDescTab5[];
-uint32_t MCD_funcDescTab6[];
-uint32_t MCD_funcDescTab7[];
-uint32_t MCD_funcDescTab8[];
-uint32_t MCD_funcDescTab9[];
-uint32_t MCD_funcDescTab10[];
-uint32_t MCD_funcDescTab11[];
-uint32_t MCD_funcDescTab12[];
-uint32_t MCD_funcDescTab13[];
-uint32_t MCD_funcDescTab14[];
-uint32_t MCD_funcDescTab15[];
+u32 MCD_funcDescTab1[];
+u32 MCD_funcDescTab2[];
+u32 MCD_funcDescTab3[];
+u32 MCD_funcDescTab4[];
+u32 MCD_funcDescTab5[];
+u32 MCD_funcDescTab6[];
+u32 MCD_funcDescTab7[];
+u32 MCD_funcDescTab8[];
+u32 MCD_funcDescTab9[];
+u32 MCD_funcDescTab10[];
+u32 MCD_funcDescTab11[];
+u32 MCD_funcDescTab12[];
+u32 MCD_funcDescTab13[];
+u32 MCD_funcDescTab14[];
+u32 MCD_funcDescTab15[];
 #endif
 
-uint32_t MCD_contextSave0[];
-uint32_t MCD_contextSave1[];
-uint32_t MCD_contextSave2[];
-uint32_t MCD_contextSave3[];
-uint32_t MCD_contextSave4[];
-uint32_t MCD_contextSave5[];
-uint32_t MCD_contextSave6[];
-uint32_t MCD_contextSave7[];
-uint32_t MCD_contextSave8[];
-uint32_t MCD_contextSave9[];
-uint32_t MCD_contextSave10[];
-uint32_t MCD_contextSave11[];
-uint32_t MCD_contextSave12[];
-uint32_t MCD_contextSave13[];
-uint32_t MCD_contextSave14[];
-uint32_t MCD_contextSave15[];
+u32 MCD_contextSave0[];
+u32 MCD_contextSave1[];
+u32 MCD_contextSave2[];
+u32 MCD_contextSave3[];
+u32 MCD_contextSave4[];
+u32 MCD_contextSave5[];
+u32 MCD_contextSave6[];
+u32 MCD_contextSave7[];
+u32 MCD_contextSave8[];
+u32 MCD_contextSave9[];
+u32 MCD_contextSave10[];
+u32 MCD_contextSave11[];
+u32 MCD_contextSave12[];
+u32 MCD_contextSave13[];
+u32 MCD_contextSave14[];
+u32 MCD_contextSave15[];
 
-uint32_t MCD_realTaskTableSrc[] =
+u32 MCD_realTaskTableSrc[] =
 {
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab0,   /* Task 0 Variable Table */
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_varTab0,   /* Task 0 Variable Table */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave0,  /* Task 0 context save space */
+    (u32)MCD_contextSave0,  /* Task 0 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab1,   /* Task 1 Variable Table */
+    (u32)MCD_varTab1,   /* Task 1 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab1,  /* Task 1 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab1,  /* Task 1 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave1,  /* Task 1 context save space */
+    (u32)MCD_contextSave1,  /* Task 1 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab2,   /* Task 2 Variable Table */
+    (u32)MCD_varTab2,   /* Task 2 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab2,  /* Task 2 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab2,  /* Task 2 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave2,  /* Task 2 context save space */
+    (u32)MCD_contextSave2,  /* Task 2 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab3,   /* Task 3 Variable Table */
+    (u32)MCD_varTab3,   /* Task 3 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab3,  /* Task 3 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab3,  /* Task 3 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave3,  /* Task 3 context save space */
+    (u32)MCD_contextSave3,  /* Task 3 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab4,   /* Task 4 Variable Table */
+    (u32)MCD_varTab4,   /* Task 4 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab4,  /* Task 4 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab4,  /* Task 4 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave4,  /* Task 4 context save space */
+    (u32)MCD_contextSave4,  /* Task 4 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab5,   /* Task 5 Variable Table */
+    (u32)MCD_varTab5,   /* Task 5 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab5,  /* Task 5 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab5,  /* Task 5 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave5,  /* Task 5 context save space */
+    (u32)MCD_contextSave5,  /* Task 5 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab6,   /* Task 6 Variable Table */
+    (u32)MCD_varTab6,   /* Task 6 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab6,  /* Task 6 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab6,  /* Task 6 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave6,  /* Task 6 context save space */
+    (u32)MCD_contextSave6,  /* Task 6 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab7,   /* Task 7 Variable Table */
+    (u32)MCD_varTab7,   /* Task 7 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab7,  /* Task 7 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab7,  /* Task 7 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave7,  /* Task 7 context save space */
+    (u32)MCD_contextSave7,  /* Task 7 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab8,   /* Task 8 Variable Table */
+    (u32)MCD_varTab8,   /* Task 8 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab8,  /* Task 8 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab8,  /* Task 8 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave8,  /* Task 8 context save space */
+    (u32)MCD_contextSave8,  /* Task 8 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab9,   /* Task 9 Variable Table */
+    (u32)MCD_varTab9,   /* Task 9 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab9,  /* Task 9 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab9,  /* Task 9 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave9,  /* Task 9 context save space */
+    (u32)MCD_contextSave9,  /* Task 9 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab10,  /* Task 10 Variable Table */
+    (u32)MCD_varTab10,  /* Task 10 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab10, /* Task 10 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab10, /* Task 10 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave10, /* Task 10 context save space */
+    (u32)MCD_contextSave10, /* Task 10 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab11,  /* Task 11 Variable Table */
+    (u32)MCD_varTab11,  /* Task 11 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab11, /* Task 11 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab11, /* Task 11 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave11, /* Task 11 context save space */
+    (u32)MCD_contextSave11, /* Task 11 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab12,  /* Task 12 Variable Table */
+    (u32)MCD_varTab12,  /* Task 12 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab12, /* Task 12 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab12, /* Task 12 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave12, /* Task 12 context save space */
+    (u32)MCD_contextSave12, /* Task 12 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab13,  /* Task 13 Variable Table */
+    (u32)MCD_varTab13,  /* Task 13 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab13, /* Task 13 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab13, /* Task 13 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave13, /* Task 13 context save space */
+    (u32)MCD_contextSave13, /* Task 13 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab14,  /* Task 14 Variable Table */
+    (u32)MCD_varTab14,  /* Task 14 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab14, /* Task 14 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab14, /* Task 14 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave14, /* Task 14 context save space */
+    (u32)MCD_contextSave14, /* Task 14 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab15,  /* Task 15 Variable Table */
+    (u32)MCD_varTab15,  /* Task 15 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab15, /* Task 15 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab15, /* Task 15 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave15, /* Task 15 context save space */
+    (u32)MCD_contextSave15, /* Task 15 context save space */
     0x00000000,
 };
 
 
-uint32_t MCD_varTab0[] =
+u32 MCD_varTab0[] =
 {   /* Task 0 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -290,7 +290,7 @@ uint32_t MCD_varTab0[] =
 };
 
 
-uint32_t MCD_varTab1[] =
+u32 MCD_varTab1[] =
 {   /* Task 1 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -326,7 +326,7 @@ uint32_t MCD_varTab1[] =
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab2[]=
+u32 MCD_varTab2[]=
 {   /* Task 2 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -362,7 +362,7 @@ uint32_t MCD_varTab2[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab3[]=
+u32 MCD_varTab3[]=
 {   /* Task 3 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -398,7 +398,7 @@ uint32_t MCD_varTab3[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab4[]=
+u32 MCD_varTab4[]=
 {   /* Task 4 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -434,7 +434,7 @@ uint32_t MCD_varTab4[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab5[]=
+u32 MCD_varTab5[]=
 {   /* Task 5 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -470,7 +470,7 @@ uint32_t MCD_varTab5[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab6[]=
+u32 MCD_varTab6[]=
 {   /* Task 6 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -506,7 +506,7 @@ uint32_t MCD_varTab6[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab7[]=
+u32 MCD_varTab7[]=
 {   /* Task 7 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -542,7 +542,7 @@ uint32_t MCD_varTab7[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab8[]=
+u32 MCD_varTab8[]=
 {   /* Task 8 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -578,7 +578,7 @@ uint32_t MCD_varTab8[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab9[]=
+u32 MCD_varTab9[]=
 {   /* Task 9 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -614,7 +614,7 @@ uint32_t MCD_varTab9[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab10[]=
+u32 MCD_varTab10[]=
 {   /* Task 10 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -650,7 +650,7 @@ uint32_t MCD_varTab10[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab11[]=
+u32 MCD_varTab11[]=
 {   /* Task 11 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -686,7 +686,7 @@ uint32_t MCD_varTab11[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab12[]=
+u32 MCD_varTab12[]=
 {   /* Task 12 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -722,7 +722,7 @@ uint32_t MCD_varTab12[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab13[]=
+u32 MCD_varTab13[]=
 {   /* Task 13 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -758,7 +758,7 @@ uint32_t MCD_varTab13[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab14[]=
+u32 MCD_varTab14[]=
 {   /* Task 14 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -794,7 +794,7 @@ uint32_t MCD_varTab14[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab15[]=
+u32 MCD_varTab15[]=
 {   /* Task 15 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -830,7 +830,7 @@ uint32_t MCD_varTab15[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_funcDescTab0[]=
+u32 MCD_funcDescTab0[]=
 {   /* Task 0 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -899,7 +899,7 @@ uint32_t MCD_funcDescTab0[]=
 };
 
 #ifdef MCD_INCLUDE_EU
-uint32_t MCD_funcDescTab1[]=
+u32 MCD_funcDescTab1[]=
 {   /* Task 1 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -967,7 +967,7 @@ uint32_t MCD_funcDescTab1[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab2[]=
+u32 MCD_funcDescTab2[]=
 {   /* Task 2 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1035,7 +1035,7 @@ uint32_t MCD_funcDescTab2[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab3[]=
+u32 MCD_funcDescTab3[]=
 {   /* Task 3 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1103,7 +1103,7 @@ uint32_t MCD_funcDescTab3[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab4[]=
+u32 MCD_funcDescTab4[]=
 {   /* Task 4 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1171,7 +1171,7 @@ uint32_t MCD_funcDescTab4[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab5[]=
+u32 MCD_funcDescTab5[]=
 {   /* Task 5 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1239,7 +1239,7 @@ uint32_t MCD_funcDescTab5[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab6[]=
+u32 MCD_funcDescTab6[]=
 {   /* Task 6 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1307,7 +1307,7 @@ uint32_t MCD_funcDescTab6[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab7[]=
+u32 MCD_funcDescTab7[]=
 {   /* Task 7 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1375,7 +1375,7 @@ uint32_t MCD_funcDescTab7[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab8[]=
+u32 MCD_funcDescTab8[]=
 {   /* Task 8 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1443,7 +1443,7 @@ uint32_t MCD_funcDescTab8[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab9[]=
+u32 MCD_funcDescTab9[]=
 {   /* Task 9 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1511,7 +1511,7 @@ uint32_t MCD_funcDescTab9[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab10[]=
+u32 MCD_funcDescTab10[]=
 {   /* Task 10 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1579,7 +1579,7 @@ uint32_t MCD_funcDescTab10[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab11[]=
+u32 MCD_funcDescTab11[]=
 {   /* Task 11 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1647,7 +1647,7 @@ uint32_t MCD_funcDescTab11[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab12[]=
+u32 MCD_funcDescTab12[]=
 {   /* Task 12 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1715,7 +1715,7 @@ uint32_t MCD_funcDescTab12[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab13[]=
+u32 MCD_funcDescTab13[]=
 {   /* Task 13 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1783,7 +1783,7 @@ uint32_t MCD_funcDescTab13[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab14[]=
+u32 MCD_funcDescTab14[]=
 {   /* Task 14 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1851,7 +1851,7 @@ uint32_t MCD_funcDescTab14[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab15[]=
+u32 MCD_funcDescTab15[]=
 {   /* Task 15 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1920,45 +1920,45 @@ uint32_t MCD_funcDescTab15[]=
 };
 #endif /*MCD_INCLUDE_EU*/
 
-uint32_t MCD_contextSave0[128];  /* Task 0 context save space */
-uint32_t MCD_contextSave1[128];  /* Task 1 context save space */
-uint32_t MCD_contextSave2[128];  /* Task 2 context save space */
-uint32_t MCD_contextSave3[128];  /* Task 3 context save space */
-uint32_t MCD_contextSave4[128];  /* Task 4 context save space */
-uint32_t MCD_contextSave5[128];  /* Task 5 context save space */
-uint32_t MCD_contextSave6[128];  /* Task 6 context save space */
-uint32_t MCD_contextSave7[128];  /* Task 7 context save space */
-uint32_t MCD_contextSave8[128];  /* Task 8 context save space */
-uint32_t MCD_contextSave9[128];  /* Task 9 context save space */
-uint32_t MCD_contextSave10[128]; /* Task 10 context save space */
-uint32_t MCD_contextSave11[128]; /* Task 11 context save space */
-uint32_t MCD_contextSave12[128]; /* Task 12 context save space */
-uint32_t MCD_contextSave13[128]; /* Task 13 context save space */
-uint32_t MCD_contextSave14[128]; /* Task 14 context save space */
-uint32_t MCD_contextSave15[128]; /* Task 15 context save space */
+u32 MCD_contextSave0[128];  /* Task 0 context save space */
+u32 MCD_contextSave1[128];  /* Task 1 context save space */
+u32 MCD_contextSave2[128];  /* Task 2 context save space */
+u32 MCD_contextSave3[128];  /* Task 3 context save space */
+u32 MCD_contextSave4[128];  /* Task 4 context save space */
+u32 MCD_contextSave5[128];  /* Task 5 context save space */
+u32 MCD_contextSave6[128];  /* Task 6 context save space */
+u32 MCD_contextSave7[128];  /* Task 7 context save space */
+u32 MCD_contextSave8[128];  /* Task 8 context save space */
+u32 MCD_contextSave9[128];  /* Task 9 context save space */
+u32 MCD_contextSave10[128]; /* Task 10 context save space */
+u32 MCD_contextSave11[128]; /* Task 11 context save space */
+u32 MCD_contextSave12[128]; /* Task 12 context save space */
+u32 MCD_contextSave13[128]; /* Task 13 context save space */
+u32 MCD_contextSave14[128]; /* Task 14 context save space */
+u32 MCD_contextSave15[128]; /* Task 15 context save space */
 
 
-uint32_t MCD_ChainNoEu_TDT[];
-uint32_t MCD_SingleNoEu_TDT[];
+u32 MCD_ChainNoEu_TDT[];
+u32 MCD_SingleNoEu_TDT[];
 #ifdef MCD_INCLUDE_EU
-uint32_t MCD_ChainEu_TDT[];
-uint32_t MCD_SingleEu_TDT[];
+u32 MCD_ChainEu_TDT[];
+u32 MCD_SingleEu_TDT[];
 #endif
-uint32_t MCD_ENetRcv_TDT[];
-uint32_t MCD_ENetXmit_TDT[];
+u32 MCD_ENetRcv_TDT[];
+u32 MCD_ENetXmit_TDT[];
 
-uint32_t MCD_modelTaskTableSrc[]=
+u32 MCD_modelTaskTableSrc[]=
 {
-    (uint32_t)MCD_ChainNoEu_TDT,
-    (uint32_t)&((uint8_t*)MCD_ChainNoEu_TDT)[0x0000016c],
+    (u32)MCD_ChainNoEu_TDT,
+    (u32)&((u8*)MCD_ChainNoEu_TDT)[0x0000016c],
     0x00000000,
     0x00000000,
     0x00000000,
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_SingleNoEu_TDT,
-    (uint32_t)&((uint8_t*)MCD_SingleNoEu_TDT)[0x000000d4],
+    (u32)MCD_SingleNoEu_TDT,
+    (u32)&((u8*)MCD_SingleNoEu_TDT)[0x000000d4],
     0x00000000,
     0x00000000,
     0x00000000,
@@ -1966,16 +1966,16 @@ uint32_t MCD_modelTaskTableSrc[]=
     0x00000000,
     0x00000000,
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_ChainEu_TDT,
-    (uint32_t)&((uint8_t*)MCD_ChainEu_TDT)[0x000001b4],
+    (u32)MCD_ChainEu_TDT,
+    (u32)&((u8*)MCD_ChainEu_TDT)[0x000001b4],
     0x00000000,
     0x00000000,
     0x00000000,
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_SingleEu_TDT,
-    (uint32_t)&((uint8_t*)MCD_SingleEu_TDT)[0x00000124],
+    (u32)MCD_SingleEu_TDT,
+    (u32)&((u8*)MCD_SingleEu_TDT)[0x00000124],
     0x00000000,
     0x00000000,
     0x00000000,
@@ -1983,16 +1983,16 @@ uint32_t MCD_modelTaskTableSrc[]=
     0x00000000,
     0x00000000,
 #endif    
-    (uint32_t)MCD_ENetRcv_TDT,
-    (uint32_t)&((uint8_t*)MCD_ENetRcv_TDT)[0x0000009c],
+    (u32)MCD_ENetRcv_TDT,
+    (u32)&((u8*)MCD_ENetRcv_TDT)[0x0000009c],
     0x00000000,
     0x00000000,
     0x00000000,
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_ENetXmit_TDT,
-    (uint32_t)&((uint8_t*)MCD_ENetXmit_TDT)[0x000000d0],
+    (u32)MCD_ENetXmit_TDT,
+    (u32)&((u8*)MCD_ENetXmit_TDT)[0x000000d0],
     0x00000000,
     0x00000000,
     0x00000000,
@@ -2000,7 +2000,7 @@ uint32_t MCD_modelTaskTableSrc[]=
     0x00000000,
     0x00000000,
 };
-uint32_t MCD_ChainNoEu_TDT[]=
+u32 MCD_ChainNoEu_TDT[]=
 {
     0x80004000, /* 0000(:370):  LCDEXT: idx0 = 0x00000000; ; */
     0x8118801b, /* 0004(:370):  LCD: idx1 = var2; idx1 once var0; idx1 += inc3 */
@@ -2095,7 +2095,7 @@ uint32_t MCD_ChainNoEu_TDT[]=
     0x000001f8, /* 0168(:0):      NOP */
     0x000001f8, /* 016C(:0):    NOP */
 };
-uint32_t MCD_SingleNoEu_TDT[]=
+u32 MCD_SingleNoEu_TDT[]=
 {
     0x8198001b, /* 0000(:657):  LCD: idx0 = var3; idx0 once var0; idx0 += inc3 */
     0x7000000d, /* 0004(:658):    DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */
@@ -2153,7 +2153,7 @@ uint32_t MCD_SingleNoEu_TDT[]=
     0x040001f8, /* 00D4(:713):    DRD1A: FN=0 INT init=0 WS=0 RS=0 */
 };
 #ifdef MCD_INCLUDE_EU
-uint32_t MCD_ChainEu_TDT[]=
+u32 MCD_ChainEu_TDT[]=
 {
     0x80004000, /* 0000(:947):  LCDEXT: idx0 = 0x00000000; ; */
     0x8198801b, /* 0004(:947):  LCD: idx1 = var3; idx1 once var0; idx1 += inc3 */
@@ -2266,7 +2266,7 @@ uint32_t MCD_ChainEu_TDT[]=
     0x000001f8, /* 01B0(:0):      NOP */
     0x000001f8, /* 01B4(:0):    NOP */
 };
-uint32_t MCD_SingleEu_TDT[]=
+u32 MCD_SingleEu_TDT[]=
 {
     0x8218001b, /* 0000(:1248):  LCD: idx0 = var4; idx0 once var0; idx0 += inc3 */
     0x7000000d, /* 0004(:1249):    DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */
@@ -2344,7 +2344,7 @@ uint32_t MCD_SingleEu_TDT[]=
     0x040001f8, /* 0124(:1316):    DRD1A: FN=0 INT init=0 WS=0 RS=0 */
 };
 #endif
-uint32_t MCD_ENetRcv_TDT[]=
+u32 MCD_ENetRcv_TDT[]=
 {
     0x80004000, /* 0000(:1389):  LCDEXT: idx0 = 0x00000000; ; */
     0x81988000, /* 0004(:1389):  LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
@@ -2387,7 +2387,7 @@ uint32_t MCD_ENetRcv_TDT[]=
     0x040001f8, /* 0098(:1441):      DRD1A: FN=0 INT init=0 WS=0 RS=0 */
     0x000001f8, /* 009C(:0):    NOP */
 };
-uint32_t MCD_ENetXmit_TDT[]=
+u32 MCD_ENetXmit_TDT[]=
 {
     0x80004000, /* 0000(:1516):  LCDEXT: idx0 = 0x00000000; ; */
     0x81988000, /* 0004(:1516):  LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */

BaS_gcc/dma/MCD_tasksInit.c

@@ -0,0 +1,224 @@
+/*
+ * File:        MCD_tasksInit.c
+ * Purpose:     Functions for initializing variable tables of different
+ *              types of tasks.
+ *
+ * Notes:
+ */
+
+/*
+ * Do not edit!
+ */
+
+#include "MCD_dma.h"
+
+extern dmaRegs *MCD_dmaBar;
+
+
+/*
+ * Task 0
+ */
+ 
+void  MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
+{
+
+    MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */
+    MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr));   /* inc[1] */
+    MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr));  /* inc[0] */
+    MCD_SET_VAR(taskTable+channel, 11, (u32)xferSize);  /* var[11] */
+    MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr));  /* inc[2] */
+    MCD_SET_VAR(taskTable+channel, 0, (u32)cSave);  /* var[0] */
+    MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
+    MCD_SET_VAR(taskTable+channel, 3, (u32)0x00000000); /* var[3] */
+    MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
+    MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
+    MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
+    MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
+    MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
+    MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
+    MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000);    /* var[10] */
+    MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000);    /* var[12] */
+    MCD_SET_VAR(taskTable+channel, 13, (u32)0x80000000);    /* var[13] */
+    MCD_SET_VAR(taskTable+channel, 14, (u32)0x00000010);    /* var[14] */
+    MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004);    /* var[15] */
+    MCD_SET_VAR(taskTable+channel, 16, (u32)0x08000000);    /* var[16] */
+    MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000);    /* inc[3] */
+    MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000);    /* inc[4] */
+    MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000001);    /* inc[5] */
+    MCD_SET_VAR(taskTable+channel, 30, (u32)0x40000000);    /* inc[6] */
+
+    /* Set the task's Enable bit in its Task Control Register */
+    MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
+}
+
+
+/*
+ * Task 1
+ */
+ 
+void  MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
+{
+
+    MCD_SET_VAR(taskTable+channel, 7, (u32)srcAddr);    /* var[7] */
+    MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr));   /* inc[1] */
+    MCD_SET_VAR(taskTable+channel, 2, (u32)destAddr);   /* var[2] */
+    MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr));  /* inc[0] */
+    MCD_SET_VAR(taskTable+channel, 3, (u32)dmaSize);    /* var[3] */
+    MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr));  /* inc[2] */
+    MCD_SET_VAR(taskTable+channel, 5, (u32)flags);  /* var[5] */
+    MCD_SET_VAR(taskTable+channel, 1, (u32)currBD); /* var[1] */
+    MCD_SET_VAR(taskTable+channel, 0, (u32)cSave);  /* var[0] */
+    MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
+    MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
+    MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
+    MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000004); /* var[9] */
+    MCD_SET_VAR(taskTable+channel, 10, (u32)0x08000000);    /* var[10] */
+    MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000);    /* inc[3] */
+    MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000001);    /* inc[4] */
+    MCD_SET_VAR(taskTable+channel, 29, (u32)0x40000000);    /* inc[5] */
+
+    /* Set the task's Enable bit in its Task Control Register */
+    MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
+}
+
+
+/*
+ * Task 2
+ */
+ 
+void  MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
+{
+
+    MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
+    MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr));   /* inc[1] */
+    MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr));  /* inc[0] */
+    MCD_SET_VAR(taskTable+channel, 12, (u32)xferSize);  /* var[12] */
+    MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr));  /* inc[2] */
+    MCD_SET_VAR(taskTable+channel, 0, (u32)cSave);  /* var[0] */
+    MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
+    MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
+    MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
+    MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
+    MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
+    MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
+    MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
+    MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
+    MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000);    /* var[10] */
+    MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000000);    /* var[11] */
+    MCD_SET_VAR(taskTable+channel, 13, (u32)0x00000000);    /* var[13] */
+    MCD_SET_VAR(taskTable+channel, 14, (u32)0x80000000);    /* var[14] */
+    MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000010);    /* var[15] */
+    MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000001);    /* var[16] */
+    MCD_SET_VAR(taskTable+channel, 17, (u32)0x00000004);    /* var[17] */
+    MCD_SET_VAR(taskTable+channel, 18, (u32)0x08000000);    /* var[18] */
+    MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000);    /* inc[3] */
+    MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000);    /* inc[4] */
+    MCD_SET_VAR(taskTable+channel, 29, (u32)0xc0000000);    /* inc[5] */
+    MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001);    /* inc[6] */
+    MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000);    /* inc[7] */
+
+    /* Set the task's Enable bit in its Task Control Register */
+    MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
+}
+
+
+/*
+ * Task 3
+ */
+ 
+void  MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
+{
+
+    MCD_SET_VAR(taskTable+channel, 8, (u32)srcAddr);    /* var[8] */
+    MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr));   /* inc[1] */
+    MCD_SET_VAR(taskTable+channel, 3, (u32)destAddr);   /* var[3] */
+    MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr));  /* inc[0] */
+    MCD_SET_VAR(taskTable+channel, 4, (u32)dmaSize);    /* var[4] */
+    MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr));  /* inc[2] */
+    MCD_SET_VAR(taskTable+channel, 6, (u32)flags);  /* var[6] */
+    MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */
+    MCD_SET_VAR(taskTable+channel, 0, (u32)cSave);  /* var[0] */
+    MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
+    MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
+    MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
+    MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
+    MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000001);    /* var[10] */
+    MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000004);    /* var[11] */
+    MCD_SET_VAR(taskTable+channel, 12, (u32)0x08000000);    /* var[12] */
+    MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000);    /* inc[3] */
+    MCD_SET_VAR(taskTable+channel, 28, (u32)0xc0000000);    /* inc[4] */
+    MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000);    /* inc[5] */
+    MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001);    /* inc[6] */
+    MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000);    /* inc[7] */
+
+    /* Set the task's Enable bit in its Task Control Register */
+    MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
+}
+
+
+/*
+ * Task 4
+ */
+ 
+void  MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel)
+{
+
+    MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */
+    MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
+    MCD_SET_VAR(taskTable+channel, 6, (u32)rcvFifoPtr); /* var[6] */
+    MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
+    MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
+    MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
+    MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
+    MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
+    MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
+    MCD_SET_VAR(taskTable+channel, 9, (u32)0x0000ffff); /* var[9] */
+    MCD_SET_VAR(taskTable+channel, 10, (u32)0x30000000);    /* var[10] */
+    MCD_SET_VAR(taskTable+channel, 11, (u32)0x0fffffff);    /* var[11] */
+    MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000008);    /* var[12] */
+    MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000);    /* inc[0] */
+    MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000);    /* inc[1] */
+    MCD_SET_VAR(taskTable+channel, 26, (u32)0x20000004);    /* inc[2] */
+    MCD_SET_VAR(taskTable+channel, 27, (u32)0x40000000);    /* inc[3] */
+
+    /* Set the task's Enable bit in its Task Control Register */
+    MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
+}
+
+
+/*
+ * Task 5
+ */
+ 
+void  MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel)
+{
+
+    MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */
+    MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
+    MCD_SET_VAR(taskTable+channel, 11, (u32)xmitFifoPtr);   /* var[11] */
+    MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
+    MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
+    MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
+    MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
+    MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
+    MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
+    MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
+    MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
+    MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000);    /* var[10] */
+    MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000);    /* var[12] */
+    MCD_SET_VAR(taskTable+channel, 13, (u32)0x0000ffff);    /* var[13] */
+    MCD_SET_VAR(taskTable+channel, 14, (u32)0xffffffff);    /* var[14] */
+    MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004);    /* var[15] */
+    MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000008);    /* var[16] */
+    MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000);    /* inc[0] */
+    MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000);    /* inc[1] */
+    MCD_SET_VAR(taskTable+channel, 26, (u32)0x40000000);    /* inc[2] */
+    MCD_SET_VAR(taskTable+channel, 27, (u32)0xc000fffc);    /* inc[3] */
+    MCD_SET_VAR(taskTable+channel, 28, (u32)0xe0000004);    /* inc[4] */
+    MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000);    /* inc[5] */
+    MCD_SET_VAR(taskTable+channel, 30, (u32)0x4000ffff);    /* inc[6] */
+    MCD_SET_VAR(taskTable+channel, 31, (u32)0xe0000001);    /* inc[7] */
+
+    /* Set the task's Enable bit in its Task Control Register */
+    MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
+}

BaS_gcc/dma/dma.c

@@ -0,0 +1,674 @@
+/*
+ * dma.c
+ *
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  Created on: 26.02.2013
+ *      Author: Markus Fröschle
+ */
+
+#include "dma.h"
+#include <MCD_dma.h>
+#include "mcd_initiators.h"
+#include "bas_printf.h"
+#include "bas_string.h"
+#include "cache.h"
+#include "exceptions.h"
+
+#if defined(MACHINE_FIREBEE)
+#include "firebee.h"
+#elif defined(MACHINE_M5484LITE)
+#include "m5484l.h"
+#elif defined(MACHINE_M54455)
+#include "m54455.h"
+#else
+#error "unknown machine!"
+#endif /* MACHINE_FIREBEE */
+
+// #define DEBUG
+#include "debug.h"
+
+extern char _SYS_SRAM[];
+#define SYS_SRAM &_SYS_SRAM[0]
+
+struct dma_channel
+{
+    int req;
+    void (*handler)(void);
+};
+
+static char used_reqs[32] =
+{
+    DMA_ALWAYS,  DMA_DSPI_RXFIFO, DMA_DSPI_TXFIFO, DMA_DREQ0,
+    DMA_PSC0_RX, DMA_PSC0_TX, DMA_USB_EP0,  DMA_USB_EP1,
+    DMA_USB_EP2,  DMA_USB_EP3,  DMA_PCI_TX,  DMA_PCI_RX,
+    DMA_PSC1_RX, DMA_PSC1_TX, DMA_I2C_RX,  DMA_I2C_TX,
+    0,           0,           0,           0,
+    0,           0,           0,           0,
+    0,           0,           0,           0,
+    0,           0,           0,           0
+};
+
+static struct dma_channel dma_channel[NCHANNELS] =
+{
+    {-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL},
+    {-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL},
+    {-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL},
+    {-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL},
+};
+
+/*
+ * Enable all DMA interrupts
+ *
+ */
+void dma_irq_enable(void)
+{
+    /* Unmask all task interrupts */
+    MCF_DMA_DIMR = 0;
+
+    /* Clear the interrupt pending register */
+    MCF_DMA_DIPR = 0;
+
+    dbg("DMA task interrupts unmasked.\r\n");
+}
+
+/*
+ * Disable all DMA interrupts
+ */
+void dma_irq_disable(void)
+{
+    /* Mask all task interrupts */
+    MCF_DMA_DIMR = (uint32_t) ~0;
+
+    /* Clear any pending task interrupts */
+    MCF_DMA_DIPR = (uint32_t) ~0;
+
+    /* Mask the DMA interrupt in the interrupt controller */
+    MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK48;
+
+    dbg("DMA interrupts masked and disabled\r\n");
+}
+
+int dma_set_initiator(int initiator)
+{
+    switch (initiator)
+    {
+        /* these initiators are always active */
+        case DMA_ALWAYS:
+        case DMA_DSPI_RXFIFO:
+        case DMA_DSPI_TXFIFO:
+        case DMA_DREQ0:
+        case DMA_PSC0_RX:
+        case DMA_PSC0_TX:
+        case DMA_USB_EP0:
+        case DMA_USB_EP1:
+        case DMA_USB_EP2:
+        case DMA_USB_EP3:
+        case DMA_PCI_TX:
+        case DMA_PCI_RX:
+        case DMA_PSC1_RX:
+        case DMA_I2C_RX:
+        case DMA_I2C_TX:
+            break;
+
+        case DMA_FEC0_RX:
+            MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC16(3)) | MCF_DMA_IMCR_IMC16_FEC0RX;
+            used_reqs[16] = DMA_FEC0_RX;
+            break;
+
+        case DMA_FEC0_TX:
+            MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC17(3)) | MCF_DMA_IMCR_IMC17_FEC0TX;
+            used_reqs[17] = DMA_FEC0_TX;
+            break;
+
+        case DMA_FEC1_RX:
+            MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC20(3)) | MCF_DMA_IMCR_IMC20_FEC1RX;
+            used_reqs[20] = DMA_FEC1_RX;
+            break;
+
+        case DMA_FEC1_TX:
+            if (used_reqs[21] == 0)
+            {
+                MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC21(3)) | MCF_DMA_IMCR_IMC21_FEC1TX;
+                used_reqs[21] = DMA_FEC1_TX;
+            }
+            else if (used_reqs[25] == 0)
+            {
+                MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC25(3)) | MCF_DMA_IMCR_IMC25_FEC1TX;
+                used_reqs[25] = DMA_FEC1_TX;
+            }
+            else if (used_reqs[31] == 0)
+            {
+                MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC31(3)) | MCF_DMA_IMCR_IMC31_FEC1TX;
+                used_reqs[31] = DMA_FEC1_TX;
+            }
+            else /* No empty slots */
+            {
+                err("no free slot found\r\n");
+
+                return 1;
+            }
+            break;
+
+        case DMA_DREQ1:
+            if (used_reqs[29] == 0)
+            {
+                MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC29(3)) | MCF_DMA_IMCR_IMC29_DREQ1;
+                used_reqs[29] = DMA_DREQ1;
+            }
+            else if (used_reqs[21] == 0)
+            {
+                MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC21(3)) | MCF_DMA_IMCR_IMC21_DREQ1;
+                used_reqs[21] = DMA_DREQ1;
+            }
+            else /* No empty slots */
+            {
+                err("no free slot\r\n");
+
+                return 1;
+            }
+            break;
+
+        case DMA_CTM0:
+            if (used_reqs[24] == 0)
+            {
+                MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC24(3)) | MCF_DMA_IMCR_IMC24_CTM0;
+                used_reqs[24] = DMA_CTM0;
+            }
+            else /* No empty slots */
+            {
+                err("no free slot\r\n");
+
+                return 1;
+            }
+            break;
+
+        case DMA_CTM1:
+            if (used_reqs[25] == 0)
+            {
+                MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC25(3)) | MCF_DMA_IMCR_IMC25_CTM1;
+                used_reqs[25] = DMA_CTM1;
+            }
+            else /* No empty slots */
+            {
+                err("no free slot\r\n");
+
+                return 1;
+            }
+            break;
+
+        case DMA_CTM2:
+            if (used_reqs[26] == 0)
+            {
+                MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC26(3)) | MCF_DMA_IMCR_IMC26_CTM2;
+                used_reqs[26] = DMA_CTM2;
+            }
+            else /* No empty slots */
+            {
+                err("no free slot\r\n");
+
+                return 1;
+            }
+            break;
+
+        case DMA_CTM3:
+            if (used_reqs[27] == 0)
+            {
+                MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC27(3)) | MCF_DMA_IMCR_IMC27_CTM3;
+                used_reqs[27] = DMA_CTM3;
+            }
+            else /* No empty slots */
+            {
+                err("no free slot\r\n");
+
+                return 1;
+            }
+            break;
+
+        case DMA_CTM4:
+            if (used_reqs[28] == 0)
+            {
+                MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC28(3)) | MCF_DMA_IMCR_IMC28_CTM4;
+                used_reqs[28] = DMA_CTM4;
+            }
+            else /* No empty slots */
+            {
+                err("no free slot\r\n");
+
+                return 1;
+            }
+            break;
+
+        case DMA_CTM5:
+            if (used_reqs[29] == 0)
+            {
+                MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC29(3)) | MCF_DMA_IMCR_IMC29_CTM5;
+                used_reqs[29] = DMA_CTM5;
+            }
+            else /* No empty slots */
+            {
+                err("no free slot\r\n");
+
+                return 1;
+            }
+            break;
+
+        case DMA_CTM6:
+            if (used_reqs[30] == 0)
+            {
+                MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC30(3)) | MCF_DMA_IMCR_IMC30_CTM6;
+                used_reqs[30] = DMA_CTM6;
+            }
+            else /* No empty slots */
+            {
+                err("no free slot\r\n");
+
+                return 1;
+            }
+            break;
+
+        case DMA_CTM7:
+            if (used_reqs[31] == 0)
+            {
+                MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC31(3)) | MCF_DMA_IMCR_IMC31_CTM7;
+                used_reqs[31] = DMA_CTM7;
+            }
+            else /* No empty slots */
+            {
+                err("no free slot\r\n");
+
+                return 1;
+            }
+            break;
+
+        case DMA_USBEP4:
+            if (used_reqs[26] == 0)
+            {
+                MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC26(3)) | MCF_DMA_IMCR_IMC26_USBEP4;
+                used_reqs[26] = DMA_USBEP4;
+            }
+            else /* No empty slots */
+            {
+                err("no free slot\r\n");
+
+                return 1;
+            }
+            break;
+
+        case DMA_USBEP5:
+            if (used_reqs[27] == 0)
+            {
+                MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC27(3)) | MCF_DMA_IMCR_IMC27_USBEP5;
+                used_reqs[27] = DMA_USBEP5;
+            }
+            else /* No empty slots */
+            {
+                err("no free slot\r\n");
+
+                return 1;
+            }
+            break;
+
+        case DMA_USBEP6:
+            if (used_reqs[28] == 0)
+            {
+                MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC28(3)) | MCF_DMA_IMCR_IMC28_USBEP6;
+                used_reqs[28] = DMA_USBEP6;
+            }
+            else /* No empty slots */
+            {
+                err("no free slot\r\n");
+                return 1;
+            }
+            break;
+
+        case DMA_PSC2_RX:
+            if (used_reqs[28] == 0)
+            {
+                MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC28(3)) | MCF_DMA_IMCR_IMC28_PSC2RX;
+                used_reqs[28] = DMA_PSC2_RX;            }
+            else /* No empty slots */
+            {
+                err("no free slot\r\n");
+
+                return 1;
+            }
+            break;
+
+        case DMA_PSC2_TX:
+            if (used_reqs[29] == 0)
+            {
+                MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC29(3)) | MCF_DMA_IMCR_IMC29_PSC2TX;
+                used_reqs[29] = DMA_PSC2_TX;
+            }
+            else /* No empty slots */
+            {
+                err("no free slot\r\n");
+
+                return 1;
+            }
+            break;
+
+        case DMA_PSC3_RX:
+            if (used_reqs[30] == 0)
+            {
+                MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC30(3)) | MCF_DMA_IMCR_IMC30_PSC3RX;
+                used_reqs[30] = DMA_PSC3_RX;
+            }
+            else /* No empty slots */
+            {
+                err("no free slot\r\n");
+
+                return 1;
+            }
+            break;
+
+        case DMA_PSC3_TX:
+            if (used_reqs[31] == 0)
+            {
+                MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC31(3)) | MCF_DMA_IMCR_IMC31_PSC3TX;
+                used_reqs[31] = DMA_PSC3_TX;
+            }
+            else /* No empty slots */
+            {
+                err("no free slot\r\n");
+
+                return 1;
+            }
+            break;
+
+        default:
+            {
+                err("don't know what to do\r\n");
+
+                return 1;
+            }
+    }
+    return 0;
+}
+
+/*
+ * Return the initiator number for the given requestor
+ *
+ * Parameters:
+ *  requestor   Initiator/Requestor identifier
+ *
+ * Return Value:
+ *  The initiator number (0-31) if initiator has been assigned
+ *  0 (always initiator) otherwise
+ */
+uint32_t dma_get_initiator(int requestor)
+{
+    uint32_t i;
+
+    for (i = 0; i < sizeof(used_reqs); ++i)
+    {
+        if (used_reqs[i] == requestor)
+            return i;
+    }
+    err("no initiator found for requestor %d\r\n", requestor);
+
+    return 0;
+}
+
+/*
+ * Remove the given initiator from the active list
+ *
+ * Parameters:
+ *  requestor   Initiator/Requestor identifier
+ */
+void dma_free_initiator(int requestor)
+{
+    uint32_t i;
+
+    for (i = 16; i < sizeof(used_reqs); ++i)
+    {
+        if (used_reqs[i] == requestor)
+        {
+            used_reqs[i] = 0;
+            break;
+        }
+    }
+    dbg("DMA requestor %d freed\r\n", requestor);
+}
+
+/*
+ * Attempt to find an available channel and mark it as used
+ *
+ * Parameters:
+ *  requestor   Initiator/Requestor identifier
+ *
+ * Return Value:
+ *  First available channel or -1 if they are all occupied
+ */
+int dma_set_channel(int requestor, void (*handler)(void))
+{
+    int i;
+
+    /* Check to see if this requestor is already assigned to a channel */
+    dbg("check if requestor %d is already assigned to a channel\r\n", requestor);
+    if ((i = dma_get_channel(requestor)) != -1)
+    {
+        return i;
+    }
+
+    for (i = 0; i < NCHANNELS; ++i)
+    {
+        if (dma_channel[i].req == -1)
+        {
+            dma_channel[i].req = requestor;
+            dma_channel[i].handler = handler;
+            dbg("assigned channel %d to requestor %d\r\n", i, requestor);
+            return i;
+        }
+    }
+    err("no free DMA channel found for requestor %d\r\n", requestor);
+
+    /* All channels taken */
+    return -1;
+}
+
+void dma_clear_channel(int channel)
+{
+    if(channel >= 0 && channel < NCHANNELS)
+    {
+        dma_channel[channel].req = -1;
+        dma_channel[channel].handler = NULL;
+        dbg("cleared DMA channel %d\r\n", channel);
+    }
+}
+
+/*
+ * Return the channel being initiated by the given requestor
+ *
+ * Parameters:
+ *  requestor   Initiator/Requestor identifier
+ *
+ * Return Value:
+ *  Channel that the requestor is controlling or -1 if hasn't been
+ *  activated
+ */
+int dma_get_channel(int requestor)
+{
+    uint32_t i;
+
+    for (i = 0; i < NCHANNELS; ++i)
+    {
+        if (dma_channel[i].req == requestor)
+            return i;
+    }
+    dbg("no channel occupied by requestor %d\r\n", requestor);
+    return -1;
+}
+
+/*
+ * Remove the channel being initiated by the given requestor from
+ * the active list
+ *
+ * Parameters:
+ *  requestor   Initiator/Requestor identifier
+ */
+void dma_free_channel(int requestor)
+{
+    uint32_t i;
+
+    for (i = 0; i < NCHANNELS; ++i)
+    {
+        if (dma_channel[i].req == requestor)
+        {
+            dma_channel[i].req = -1;
+            dma_channel[i].handler = NULL;
+            break;
+        }
+    }
+}
+
+/*
+ * This is the catch-all interrupt handler for the mult-channel DMA
+ */
+bool dma_interrupt_handler(void *arg1, void *arg2)
+{
+    int i, interrupts;
+    uint32_t ipl;
+
+    ipl = set_ipl(7);       /* do not disturb */
+
+    /*
+     * Determine which interrupt(s) triggered by AND'ing the
+     * pending interrupts with those that aren't masked.
+     */
+    interrupts = MCF_DMA_DIPR & ~MCF_DMA_DIMR;
+
+    /* Make sure we are here for a reason */
+    if (interrupts == 0)
+    {
+        err("not DMA interrupt!\r\n");
+        return 0;
+    }
+
+    dbg("");
+    /* Clear the interrupt in the pending register */
+    MCF_DMA_DIPR = interrupts;
+
+    for (i = 0; i < 16; ++i, interrupts >>= 1)
+    {
+        if (interrupts & 0x1)
+        {
+            /* If there is a handler, call it */
+            if (dma_channel[i].handler != NULL)
+            {
+                dbg("call handler for DMA channel %d (%p)\r\n", i, dma_channel[i].handler);
+                dma_channel[i].handler();
+            }
+        }
+    }
+
+    set_ipl(ipl);
+
+    return true;   /* handled */
+}
+/********************************************************************/
+
+void *dma_memcpy(void *dst, void *src, size_t n)
+{
+    int ret;
+
+#ifdef DBG_DMA
+    int32_t time;
+    int32_t start;
+    int32_t end;
+
+    start = MCF_SLT0_SCNT;
+#endif /* DBG_DMA */
+
+    ret = MCD_startDma(1, src, 4, dst, 4, n, 4, DMA_ALWAYS, 0, MCD_SINGLE_DMA, 0);
+    if (ret == MCD_OK)
+    {
+        dbg("DMA on channel 1 successfully started\r\n");
+    }
+
+    do
+    {
+        ret = MCD_dmaStatus(1);
+#ifdef _NOT_USED_ /* suppress annoying printout for now */
+        switch (ret)
+        {
+            case MCD_NO_DMA:
+                xprintf("MCD_NO_DMA: no DMA active on this channel\r\n");
+                return NULL;
+                break;
+            case MCD_IDLE:
+                xprintf("MCD_IDLE: DMA defined but not active (initiator not ready)\r\n");
+                break;
+            case MCD_RUNNING:
+                xprintf("MCD_RUNNING: DMA active and working on this channel\r\n");
+                break;
+            case MCD_PAUSED:
+                xprintf("MCD_PAUSED: DMA defined and enabled, but currently paused\r\n");
+                break;
+            case MCD_HALTED:
+                xprintf("MCD_HALTED: DMA killed\r\n");
+                return NULL;
+                break;
+            case MCD_DONE:
+                xprintf("MCD_DONE: DMA finished\r\n");
+                break;
+            case MCD_CHANNEL_INVALID:
+                xprintf("MCD_CHANNEL_INVALID: invalid DMA channel\r\n");
+                return NULL;
+                break;
+            default:
+                xprintf("unknown DMA status %d\r\n", ret);
+                break;
+        }
+#endif
+    } while (ret != MCD_DONE);
+
+#ifdef DBG_DMA
+    end = MCF_SLT0_SCNT;
+    time = (start - end) / (SYSCLK / 1000) / 1000;
+    dbg("took %d ms (%f Mbytes/second)\r\n", time, n / (float) time / 1000.0);
+#endif /* DBG_DMA */
+
+    return dst;
+}
+
+int dma_init(void)
+{
+    int i;
+    int res;
+
+    dbg("MCD DMA API initialization: ");
+    res = MCD_initDma((dmaRegs *) &_MBAR[0x8000], SYS_SRAM, MCD_RELOC_TASKS | MCD_COMM_PREFETCH_EN);
+    if (res != MCD_OK)
+    {
+        err("DMA API initialization failed (0x%x)\r\n", res);
+        return 0;
+    }
+
+    /*
+     * make sure dma_channel array is properly initialized
+     */
+    for (i = 0; i < NCHANNELS; i++)
+    {
+        dma_channel[i].req = -1;
+        dma_channel[i].handler = NULL;
+    }
+
+    return 0;
+}
+

BaS_gcc/exe/basflash.c

@@ -0,0 +1,679 @@
+/*
+ * basflash.c
+ *
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  Created on: 26.02.2013
+ *      Author: Markus Fröschle
+ */
+
+#include <bas_types.h>
+#include "bas_printf.h"
+#include "bas_string.h"
+#include "diskio.h"
+#include "ff.h"
+#include "s19reader.h"
+
+#if defined(MACHINE_FIREBEE)
+#include "firebee.h"
+#elif defined(MACHINE_M5484LITE)
+#include "m5484l.h"
+#elif defined(MACHINE_M54455)
+#include "m54455.h"
+#else
+error unknown machine!
+#endif /* MACHINE_M5484LITE */
+
+#define AMD_FLASH_BUS_SHIFT     1
+#define AMD_FLASH_CELL          volatile uint16_t
+#define AMD_FLASH_CELL_BYTES    2
+#define AMD_FLASH_CELL_MASK     0x1
+#define AMD_FLASH_CMD_DATA(x)   ((uint16_t) x)
+
+struct amd_flash_sector_info
+{
+    uint32_t size; /* sector size in bytes */
+    uint32_t offset; /* offset from base of device */
+};
+
+/*
+ * AM29LV640D flash layout (bottom boot as used in the Firebee)
+ */
+static struct amd_flash_sector_info sector[] =
+{
+{  8 * 1024, 0x00000000 }, /* SA0 */
+{  8 * 1024, 0x00008000 }, /* SA1 */
+{  8 * 1024, 0x00010000 }, /* SA2 */
+{  8 * 1024, 0x00018000 }, /* SA3 */
+{  8 * 1024, 0x00020000 }, /* SA4 */
+{  8 * 1024, 0x00028000 }, /* SA5 */
+{  8 * 1024, 0x00030000 }, /* SA6 */
+{  8 * 1024, 0x00038000 }, /* SA7 */
+{  8 * 1024, 0x00040000 }, /* SA8 */
+{ 64 * 1024, 0x00048000 }, /* SA9 */
+{ 64 * 1024, 0x00050000 }, /* SA10 */
+{ 64 * 1024, 0x00058000 }, /* SA11 */
+{ 64 * 1024, 0x00060000 }, /* SA12 */
+{ 64 * 1024, 0x00068000 }, /* SA13 */
+{ 64 * 1024, 0x00070000 }, /* SA14 */
+{ 64 * 1024, 0x00078000 }, /* SA15 */
+{ 64 * 1024, 0x00080000 }, /* SA16 */
+{ 64 * 1024, 0x00088000 }, /* SA17 */
+{ 64 * 1024, 0x00090000 }, /* SA18 */
+{ 64 * 1024, 0x00098000 }, /* SA19 */
+{ 64 * 1024, 0x000a0000 }, /* SA20 */
+{ 64 * 1024, 0x000a8000 }, /* SA21 */
+{ 64 * 1024, 0x000b0000 }, /* SA22 */
+{ 64 * 1024, 0x000b8000 }, /* SA23 */
+{ 64 * 1024, 0x000c0000 }, /* SA24 */
+{ 64 * 1024, 0x000c8000 }, /* SA25 */
+{ 64 * 1024, 0x000d0000 }, /* SA26 */
+{ 64 * 1024, 0x000d8000 }, /* SA27 */
+{ 64 * 1024, 0x000e0000 }, /* SA28 */
+{ 64 * 1024, 0x000e8000 }, /* SA29 */
+{ 64 * 1024, 0x000f0000 }, /* SA30 */
+{ 64 * 1024, 0x000f8000 }, /* SA31 */
+{ 64 * 1024, 0x00100000 }, /* SA32 */
+{ 64 * 1024, 0x00108000 }, /* SA32 */
+{ 64 * 1024, 0x00110000 }, /* SA34 */
+{ 64 * 1024, 0x00118000 }, /* SA35 */
+{ 64 * 1024, 0x00120000 }, /* SA36 */
+{ 64 * 1024, 0x00128000 }, /* SA37 */
+{ 64 * 1024, 0x00130000 }, /* SA38 */
+{ 64 * 1024, 0x00138000 }, /* SA39 */
+{ 64 * 1024, 0x00140000 }, /* SA40 */
+{ 64 * 1024, 0x00148000 }, /* SA41 */
+{ 64 * 1024, 0x00150000 }, /* SA42 */
+{ 64 * 1024, 0x00158000 }, /* SA43 */
+{ 64 * 1024, 0x00160000 }, /* SA44 */
+{ 64 * 1024, 0x00168000 }, /* SA45 */
+{ 64 * 1024, 0x00170000 }, /* SA46 */
+{ 64 * 1024, 0x00178000 }, /* SA47 */
+{ 64 * 1024, 0x00180000 }, /* SA48 */
+{ 64 * 1024, 0x00188000 }, /* SA49 */
+{ 64 * 1024, 0x00190000 }, /* SA50 */
+{ 64 * 1024, 0x00198000 }, /* SA51 */
+{ 64 * 1024, 0x001a0000 }, /* SA52 */
+{ 64 * 1024, 0x001a8000 }, /* SA53 */
+{ 64 * 1024, 0x001b0000 }, /* SA54 */
+{ 64 * 1024, 0x001b8000 }, /* SA55 */
+{ 64 * 1024, 0x001c0000 }, /* SA56 */
+{ 64 * 1024, 0x001c8000 }, /* SA57 */
+{ 64 * 1024, 0x001d0000 }, /* SA58 */
+{ 64 * 1024, 0x001d8000 }, /* SA59 */
+{ 64 * 1024, 0x001e0000 }, /* SA60 */
+{ 64 * 1024, 0x001e8000 }, /* SA61 */
+{ 64 * 1024, 0x001f0000 }, /* SA62 */
+{ 64 * 1024, 0x001f8000 }, /* SA63 */
+{ 64 * 1024, 0x00200000 }, /* SA64 */
+{ 64 * 1024, 0x00208000 }, /* SA65 */
+{ 64 * 1024, 0x00210000 }, /* SA66 */
+{ 64 * 1024, 0x00218000 }, /* SA67 */
+{ 64 * 1024, 0x00220000 }, /* SA68 */
+{ 64 * 1024, 0x00228000 }, /* SA69 */
+{ 64 * 1024, 0x00230000 }, /* SA70 */
+{ 64 * 1024, 0x00238000 }, /* SA71 */
+{ 64 * 1024, 0x00240000 }, /* SA72 */
+{ 64 * 1024, 0x00248000 }, /* SA73 */
+{ 64 * 1024, 0x00250000 }, /* SA74 */
+{ 64 * 1024, 0x00258000 }, /* SA75 */
+{ 64 * 1024, 0x00260000 }, /* SA76 */
+{ 64 * 1024, 0x00268000 }, /* SA77 */
+{ 64 * 1024, 0x00270000 }, /* SA78 */
+{ 64 * 1024, 0x00278000 }, /* SA79 */
+{ 64 * 1024, 0x00280000 }, /* SA80 */
+{ 64 * 1024, 0x00288000 }, /* SA81 */
+{ 64 * 1024, 0x00290000 }, /* SA82 */
+{ 64 * 1024, 0x00298000 }, /* SA83 */
+{ 64 * 1024, 0x002a0000 }, /* SA84 */
+{ 64 * 1024, 0x002a8000 }, /* SA85 */
+{ 64 * 1024, 0x002b0000 }, /* SA86 */
+{ 64 * 1024, 0x002b8000 }, /* SA87 */
+{ 64 * 1024, 0x002c0000 }, /* SA88 */
+{ 64 * 1024, 0x002c8000 }, /* SA89 */
+{ 64 * 1024, 0x002d0000 }, /* SA90 */
+{ 64 * 1024, 0x002d8000 }, /* SA91 */
+{ 64 * 1024, 0x002e0000 }, /* SA92 */
+{ 64 * 1024, 0x002e8000 }, /* SA93 */
+{ 64 * 1024, 0x002f0000 }, /* SA94 */
+{ 64 * 1024, 0x002f8000 }, /* SA95 */
+{ 64 * 1024, 0x00300000 }, /* SA96 */
+{ 64 * 1024, 0x00308000 }, /* SA97 */
+{ 64 * 1024, 0x00310000 }, /* SA98 */
+{ 64 * 1024, 0x00318000 }, /* SA99 */
+{ 64 * 1024, 0x00320000 }, /* SA100 */
+{ 64 * 1024, 0x00328000 }, /* SA101 */
+{ 64 * 1024, 0x00330000 }, /* SA102 */
+{ 64 * 1024, 0x00338000 }, /* SA103 */
+{ 64 * 1024, 0x00340000 }, /* SA104 */
+{ 64 * 1024, 0x00348000 }, /* SA105 */
+{ 64 * 1024, 0x00350000 }, /* SA106 */
+{ 64 * 1024, 0x00358000 }, /* SA107 */
+{ 64 * 1024, 0x00360000 }, /* SA108 */
+{ 64 * 1024, 0x00368000 }, /* SA109 */
+{ 64 * 1024, 0x00370000 }, /* SA110 */
+{ 64 * 1024, 0x00378000 }, /* SA111 */
+{ 64 * 1024, 0x00380000 }, /* SA112 */
+{ 64 * 1024, 0x00388000 }, /* SA113 */
+{ 64 * 1024, 0x00390000 }, /* SA114 */
+{ 64 * 1024, 0x00398000 }, /* SA115 */
+{ 64 * 1024, 0x003a0000 }, /* SA116 */
+{ 64 * 1024, 0x003a8000 }, /* SA117 */
+{ 64 * 1024, 0x003b0000 }, /* SA118 */
+{ 64 * 1024, 0x003b8000 }, /* SA119 */
+{ 64 * 1024, 0x003c0000 }, /* SA120 */
+{ 64 * 1024, 0x003c8000 }, /* SA121 */
+{ 64 * 1024, 0x003d0000 }, /* SA122 */
+{ 64 * 1024, 0x003d8000 }, /* SA123 */
+{ 64 * 1024, 0x003e0000 }, /* SA124 */
+{ 64 * 1024, 0x003e8000 }, /* SA125 */
+{ 64 * 1024, 0x003f0000 }, /* SA126 */
+{ 64 * 1024, 0x003f8000 }, /* SA127 */
+};
+
+static const int AMD_FLASH_SECTORS = sizeof(sector)	/ sizeof(struct amd_flash_sector_info);
+
+#define SOFFSET(n)  (sector[n].offset)
+#define SADDR(n)    (SOFFSET(n) >> AMD_FLASH_BUS_SHIFT)
+#define SSIZE(n)	(sector[n].size)
+
+#define AMD_FLASH_DEVICES	1
+
+static AMD_FLASH_CELL *pFlash;
+
+typedef struct romram
+{
+    uint32_t flash_address;
+    uint32_t ram_address;
+    char *name;
+} ROMRAM;
+
+#if defined(MACHINE_FIREBEE)
+static const struct romram flash_areas[] =
+{
+{ 0xe0600000, 0x00e00000, "EmuTOS" }, /* EmuTOS */
+{ 0xe0400000, 0x00e00000, "FireTOS" }, /* FireTOS */
+{ 0xe0700000, 0x00e00000, "FPGA" }, /* FPGA config */
+};
+static const int num_flash_areas = sizeof(flash_areas) / sizeof(struct romram);
+#endif
+
+#define FLASH_ADDRESS 0xe0000000
+
+/*
+ * erase a flash sector
+ *
+ * sector_num is the index into the sector table above.
+ *
+ * FIXME: need to disable data cache to ensure proper operation
+ */
+void amd_flash_sector_erase(int n)
+{
+    volatile AMD_FLASH_CELL status;
+
+    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+    pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+    pFlash[0x555] = AMD_FLASH_CMD_DATA(0x80);
+    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+    pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+    pFlash[SADDR(n)] = AMD_FLASH_CMD_DATA(0x30);
+
+    do
+        status = pFlash[SADDR(n)];
+    while ((status & AMD_FLASH_CMD_DATA(0x80)) != AMD_FLASH_CMD_DATA(0x80));
+
+    /*
+     * Place device in read mode
+     */
+    pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+    pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+    pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+}
+
+int amd_flash_erase(void *start, int bytes, void (*putchar)(int))
+{
+    int i, ebytes = 0;
+
+    if (bytes == 0)
+        return 0;
+
+    for (i = 0; i < AMD_FLASH_SECTORS; i++)
+    {
+        if (start >= (void *)((void *) pFlash + SOFFSET(i)) &&
+                start <= (void *)((void *) pFlash + SOFFSET(i) + (SSIZE(i) - 1)))
+        {
+            break;
+        }
+    }
+
+    while (ebytes < bytes)
+    {
+        if (putchar != NULL)
+        {
+            putchar('.');
+        }
+        amd_flash_sector_erase(i);
+        ebytes += SSIZE(i);
+        i++;
+    }
+
+    if (putchar != NULL)
+    {
+        putchar(10);    /* LF */
+        putchar(13);    /* CR */
+    }
+
+    return ebytes;
+}
+
+void amd_flash_program_cell(AMD_FLASH_CELL *dst, AMD_FLASH_CELL data)
+{
+    volatile AMD_FLASH_CELL status;
+    int retry;
+
+    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+    pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xA0);
+    *dst = data;
+
+    /*
+     * Wait for program operation to finish
+     *  (Data# Polling Algorithm)
+     */
+    retry = 0;
+    while (1)
+    {
+        status = *dst;
+        if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
+                (data & AMD_FLASH_CMD_DATA(0x80)))
+        {
+            break;
+        }
+        if (status & AMD_FLASH_CMD_DATA(0x20))
+        {
+            status = *dst;
+            if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
+                    (data & AMD_FLASH_CMD_DATA(0x80)))
+            {
+                break;
+            }
+            if (++retry > 1024)
+            {
+                break;
+            }
+        }
+    }
+}
+
+
+int amd_flash_program(void *dest, void *source, int bytes, int erase, void (*func)(void), void (*putchar)(int))
+{
+    AMD_FLASH_CELL *src, *dst;
+    int hashi=1,hashj=0;
+    char hash[5];
+
+    hash[0]=8;  /* Backspace */
+    hash[1]=124;/* "|" */
+    hash[2]=47; /* "/" */
+    hash[3]=45; /* "-" */
+    hash[4]=92; /* "\" */
+
+    src = (AMD_FLASH_CELL *)source;
+    dst = (AMD_FLASH_CELL *)dest;
+
+    /*
+     * Place device in read mode
+     */
+    pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+    pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+    pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+
+    /*
+     * Erase device if necessary
+     */
+    if (erase)
+    {
+        amd_flash_erase(dest, bytes, putchar);
+    }
+
+    /*
+     * Program device
+     */
+    while (bytes > 0)
+    {
+        amd_flash_program_cell(dst,*src);
+
+        /* Verify Write */
+        if (*dst == *src)
+        {
+            bytes -= AMD_FLASH_CELL_BYTES;
+            *dst++, *src++;
+
+            if ((putchar != NULL))
+            {
+                /* Hash marks to indicate progress */
+                if (hashj == 0x1000)
+                {
+                    hashj = -1;
+                    putchar(hash[0]);
+                    putchar(hash[hashi]);
+
+                    hashi++;
+                    if (hashi == 5)
+                    {
+                        hashi=1;
+                    }
+
+                }
+                hashj++;
+            }
+        }
+        else
+            break;
+    }
+
+    /*
+     * Place device in read mode
+     */
+    pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+    pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+    pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+
+    if (putchar != NULL)
+    {
+        putchar(hash[0]);
+    }
+
+    /*
+     * If a function was passed in, call it now
+     */
+    if ((func != NULL))
+    {
+        func();
+    }
+
+    return ((int)src - (int)source);
+}
+
+/*
+ * this callback just does nothing besides returning OK. Meant to do a dry run over the file to check its integrity
+ */
+static err_t simulate()
+{
+    err_t ret = OK;
+
+    return ret;
+}
+
+static err_t flash(uint8_t *dst, uint8_t *src, uint32_t length)
+{
+    err_t ret = OK;
+
+    /* TODO: do the actual flash */
+    amd_flash_program(dst, src, length, 1, NULL, xputchar);
+    return ret;
+}
+
+/*
+ * this callback verifies the data against the S-record file contents after a write to destination
+ */
+static err_t verify(uint8_t *dst, uint8_t *src, size_t length)
+{
+    uint8_t *end = src + length;
+
+    do
+    {
+        if (*src++ != *dst++)
+            return FAIL;
+    } while (src < end);
+
+    return OK;
+}
+
+void srec_flash(char *flash_filename)
+{
+    DRESULT res;
+    FRESULT fres;
+    FATFS fs;
+    FIL file;
+    err_t err;
+    void *start_address;
+    uint32_t length;
+
+    res = disk_status(0);
+    if (res == RES_OK)
+    {
+        fres = f_mount(0, &fs);
+        if (fres == FR_OK)
+        {
+            if ((fres = f_open(&file, flash_filename, FA_READ) != FR_OK))
+            {
+                xprintf("flasher file %s not present on disk\r\n",
+                        flash_filename);
+            }
+            else
+            {
+                f_close(&file);
+
+                /* first pass: parse and check for inconsistencies */
+                xprintf("check file integrity: ");
+                err = read_srecords(flash_filename, &start_address, &length,
+                                    simulate);
+                if (err == OK)
+                {
+                    xprintf("OK.\r\nerase flash area (from %p, length 0x%lx): ",
+                            start_address, length);
+                    err = amd_flash_erase(start_address, length, xputchar);
+
+                    /* next pass: copy data to destination */
+                    xprintf("OK.\r\flash data: ");
+                    err = read_srecords(flash_filename, &start_address, &length, flash);
+                    if (err == OK)
+                    {
+                        /* next pass: verify data */
+                        xprintf("OK.\r\nverify data: ");
+                        err = read_srecords(flash_filename, &start_address,
+                                            &length, verify);
+                        if (err == OK)
+                        {
+                            typedef void void_func(void);
+                            void_func *func;
+
+                            xprintf("OK.\r\n");
+
+                            xprintf(
+                                        "target successfully written and verified. Start address: %p\r\n",
+                                        start_address);
+
+                            func = (void_func *) start_address;
+                            (*func)();
+                        }
+                        else
+                        {
+                            xprintf("failed\r\n");
+                        }
+                    }
+                    else
+                    {
+                        xprintf("failed\r\n");
+                    }
+                }
+                else
+                {
+                    xprintf("failed\r\n");
+                }
+            }
+        }
+        else
+        {
+            // xprintf("could not mount FAT FS\r\n");
+        }
+        f_mount(0, 0L);
+    }
+    else
+    {
+        // xprintf("could not initialize SD card\r\n");
+    }
+}
+
+err_t srec_load(char *flash_filename)
+{
+    FRESULT fres;
+    FIL file;
+    err_t err;
+    void *start_address;
+    uint32_t length;
+
+    if ((fres = f_open(&file, flash_filename, FA_READ) != FR_OK))
+    {
+        xprintf("flasher file %s not present on disk\r\n", flash_filename);
+    }
+    else
+    {
+        f_close(&file);
+
+        /* first pass: parse and check for inconsistencies */
+        xprintf("check file integrity: ");
+        err = read_srecords(flash_filename, &start_address, &length, simulate);
+        if (err == OK)
+        {
+            /* next pass: copy data to destination */
+            xprintf("OK (start address = %p).\r\ncopy/flash data: ", start_address);
+            err = read_srecords(flash_filename, &start_address, &length, srec_memcpy);
+            if (err == OK)
+            {
+                /* next pass: verify data */
+                xprintf("OK (start address = %p).\r\nverify data: ", start_address);
+                err = read_srecords(flash_filename, &start_address, &length, verify);
+                if (err == OK)
+                {
+                    typedef void void_func(void);
+                    void_func *func;
+
+                    xprintf("OK.\r\n");
+                    xprintf(
+                                "target successfully written and verified. Start address: %p\r\n",
+                                start_address);
+
+                    func = (void_func *) start_address;
+                    (*func)();
+                }
+                else
+                {
+                    xprintf("failed\r\n");
+                }
+            }
+            else
+            {
+                xprintf("failed\r\n");
+            }
+        }
+        else
+        {
+            xprintf("failed\r\n");
+        }
+    }
+    return OK;
+}
+
+void basflash(void)
+{
+    // const char *basflash_str = "\\BASFLASH";
+    const char *bastest_str = "\\BASTEST";
+    DRESULT res;
+    FRESULT fres;
+    FATFS fs;
+
+    xprintf("\r\nHello from BASFLASH.S19!\r\n\r\n");
+
+    /*
+     * read \BASTEST\ folder contents (search for .S19-files). If found load them to their final destination
+     * (after BaS has copied them, not their flash location) and return.
+     *
+     * Files located in the BASTEST-folder thus override those in flash. Useful for testing before flashing
+     */
+    res = disk_status(0);
+    xprintf("disk_status(0) = %d\r\n", res);
+    if (res == RES_OK)
+    {
+        fres = f_mount(0, &fs);
+        xprintf("f_mount() = %d\r\n", fres);
+        if (fres == FR_OK)
+        {
+            DIR directory;
+
+            fres = f_opendir(&directory, bastest_str);
+            xprintf("f_opendir() = %d\r\n", fres);
+            if (fres == FR_OK)
+            {
+                FILINFO fileinfo;
+
+                fres = f_readdir(&directory, &fileinfo);
+                xprintf("f_readdir() = %d\r\n", fres);
+                while (fres == FR_OK)
+                {
+                    const char *srec_ext = ".S19";
+                    char path[30];
+
+                    if (fileinfo.fname[0] != '\0') /* found a file */
+                    {
+                        xprintf("check file %s (%s == %s ?)\r\n",
+                                fileinfo.fname,
+                                &fileinfo.fname[strlen(fileinfo.fname) - 4],
+                                srec_ext);
+                        if (strlen(fileinfo.fname) >= 4
+                                && strncmp(
+                                    &fileinfo.fname[strlen(fileinfo.fname)
+                                    - 4], srec_ext, 4) == 0) /* we have a .S19 file */
+                        {
+                            /*
+                             * build path + filename
+                             */
+                            strcpy(path, bastest_str);
+                            strcat(path, "\\");
+                            strncat(path, fileinfo.fname, 13);
+
+                            xprintf("loading file %s\r\n", path);
+                            /*
+                             * load file
+                             */
+                            srec_load(path);
+//                            {
+//                                xprintf("failed to load file %s\r\n", path);
+                                // error handling
+//                            }
+                        }
+                    }
+                    else
+                        break; /* exit if no file found */
+                    fres = f_readdir(&directory, &fileinfo);
+                    xprintf("f_readdir() = %d\r\n", fres);
+                }
+            }
+            else
+            {
+                xprintf("f_opendir %s failed with error code %d\r\n",
+                        bastest_str, fres);
+            }
+        }
+        else
+        {
+            // xprintf("could not mount FAT FS\r\n");
+        }
+        f_mount(0, 0L); /* unmount SD card */
+    }
+}

BaS_gcc/exe/basflash_start.c

@@ -23,20 +23,21 @@
 
 #include <bas_types.h>
 
-static uint32_t ownstack[4096];
-static uint32_t *stackptr = &ownstack[4095];
+#define STACKSIZE   16384
+static uint32_t ownstack[STACKSIZE];
+static uint32_t *stackptr = &ownstack[STACKSIZE - 1];
 
 /*
  * setup our own stack in SDRAM to prevent clashing BaS's in SRAM (size limited).
  */
 void startup(void)
 {
-	static uint32_t oldstack;
+    static uint32_t oldstack;
 
-	void basflash(void);
-	__asm__ __volatile__("move.l	sp,%0\n\t" : "=g"(oldstack) : :);
-	__asm__ __volatile__("move.l	%0,sp\n\t" : : "g"(stackptr) : );
-	basflash();
-	__asm__ __volatile__("move.l	%0,sp\n\t" : : "g"(oldstack) : "sp");
-	(void) stackptr; /* make compiler happy about unused variables */
+    void basflash(void);
+    __asm__ __volatile__("move.l	sp,%0\n\t" : "=g"(oldstack) : :);
+    __asm__ __volatile__("move.l	%0,sp\n\t" : : "g"(stackptr) : );
+    basflash();
+    __asm__ __volatile__("move.l	%0,sp\n\t" : : "g"(oldstack) : "sp");
+    (void) stackptr; /* make compiler happy about unused variables */
 }

BaS_gcc/flash/flash.c

@@ -0,0 +1,383 @@
+#include <stddef.h>
+#include "bas_types.h"
+
+#if defined(MACHINE_FIREBEE)
+#include "firebee.h"
+#elif defined(MACHINE_M5484LITE)
+#include "m5484l.h"
+#endif /* MACHINE_FIREBEE */
+
+#define AMD_FLASH_BUS_SHIFT     1
+#define AMD_FLASH_CELL          volatile uint16_t
+#define AMD_FLASH_CELL_BYTES    2
+#define AMD_FLASH_CELL_MASK     0x1
+#define AMD_FLASH_CMD_DATA(x)   ((uint16_t) x)
+
+struct amd_flash_sector_info
+{
+    uint32_t size; /* sector size in bytes */
+    uint32_t offset; /* offset from base of device */
+};
+
+/*
+ * AM29LV640D flash layout (bottom boot as used in the Firebee )
+ */
+static struct amd_flash_sector_info sector[] =
+{
+{  8 * 1024, 0x00000000 }, /* SA0 */
+{  8 * 1024, 0x00008000 }, /* SA1 */
+{  8 * 1024, 0x00010000 }, /* SA2 */
+{  8 * 1024, 0x00018000 }, /* SA3 */
+{  8 * 1024, 0x00020000 }, /* SA4 */
+{  8 * 1024, 0x00028000 }, /* SA5 */
+{  8 * 1024, 0x00030000 }, /* SA6 */
+{  8 * 1024, 0x00038000 }, /* SA7 */
+{  8 * 1024, 0x00040000 }, /* SA8 */
+{ 64 * 1024, 0x00048000 }, /* SA9 */
+{ 64 * 1024, 0x00050000 }, /* SA10 */
+{ 64 * 1024, 0x00058000 }, /* SA11 */
+{ 64 * 1024, 0x00060000 }, /* SA12 */
+{ 64 * 1024, 0x00068000 }, /* SA13 */
+{ 64 * 1024, 0x00070000 }, /* SA14 */
+{ 64 * 1024, 0x00078000 }, /* SA15 */
+{ 64 * 1024, 0x00080000 }, /* SA16 */
+{ 64 * 1024, 0x00088000 }, /* SA17 */
+{ 64 * 1024, 0x00090000 }, /* SA18 */
+{ 64 * 1024, 0x00098000 }, /* SA19 */
+{ 64 * 1024, 0x000a0000 }, /* SA20 */
+{ 64 * 1024, 0x000a8000 }, /* SA21 */
+{ 64 * 1024, 0x000b0000 }, /* SA22 */
+{ 64 * 1024, 0x000b8000 }, /* SA23 */
+{ 64 * 1024, 0x000c0000 }, /* SA24 */
+{ 64 * 1024, 0x000c8000 }, /* SA25 */
+{ 64 * 1024, 0x000d0000 }, /* SA26 */
+{ 64 * 1024, 0x000d8000 }, /* SA27 */
+{ 64 * 1024, 0x000e0000 }, /* SA28 */
+{ 64 * 1024, 0x000e8000 }, /* SA29 */
+{ 64 * 1024, 0x000f0000 }, /* SA30 */
+{ 64 * 1024, 0x000f8000 }, /* SA31 */
+{ 64 * 1024, 0x00100000 }, /* SA32 */
+{ 64 * 1024, 0x00108000 }, /* SA32 */
+{ 64 * 1024, 0x00110000 }, /* SA34 */
+{ 64 * 1024, 0x00118000 }, /* SA35 */
+{ 64 * 1024, 0x00120000 }, /* SA36 */
+{ 64 * 1024, 0x00128000 }, /* SA37 */
+{ 64 * 1024, 0x00130000 }, /* SA38 */
+{ 64 * 1024, 0x00138000 }, /* SA39 */
+{ 64 * 1024, 0x00140000 }, /* SA40 */
+{ 64 * 1024, 0x00148000 }, /* SA41 */
+{ 64 * 1024, 0x00150000 }, /* SA42 */
+{ 64 * 1024, 0x00158000 }, /* SA43 */
+{ 64 * 1024, 0x00160000 }, /* SA44 */
+{ 64 * 1024, 0x00168000 }, /* SA45 */
+{ 64 * 1024, 0x00170000 }, /* SA46 */
+{ 64 * 1024, 0x00178000 }, /* SA47 */
+{ 64 * 1024, 0x00180000 }, /* SA48 */
+{ 64 * 1024, 0x00188000 }, /* SA49 */
+{ 64 * 1024, 0x00190000 }, /* SA50 */
+{ 64 * 1024, 0x00198000 }, /* SA51 */
+{ 64 * 1024, 0x001a0000 }, /* SA52 */
+{ 64 * 1024, 0x001a8000 }, /* SA53 */
+{ 64 * 1024, 0x001b0000 }, /* SA54 */
+{ 64 * 1024, 0x001b8000 }, /* SA55 */
+{ 64 * 1024, 0x001c0000 }, /* SA56 */
+{ 64 * 1024, 0x001c8000 }, /* SA57 */
+{ 64 * 1024, 0x001d0000 }, /* SA58 */
+{ 64 * 1024, 0x001d8000 }, /* SA59 */
+{ 64 * 1024, 0x001e0000 }, /* SA60 */
+{ 64 * 1024, 0x001e8000 }, /* SA61 */
+{ 64 * 1024, 0x001f0000 }, /* SA62 */
+{ 64 * 1024, 0x001f8000 }, /* SA63 */
+{ 64 * 1024, 0x00200000 }, /* SA64 */
+{ 64 * 1024, 0x00208000 }, /* SA65 */
+{ 64 * 1024, 0x00210000 }, /* SA66 */
+{ 64 * 1024, 0x00218000 }, /* SA67 */
+{ 64 * 1024, 0x00220000 }, /* SA68 */
+{ 64 * 1024, 0x00228000 }, /* SA69 */
+{ 64 * 1024, 0x00230000 }, /* SA70 */
+{ 64 * 1024, 0x00238000 }, /* SA71 */
+{ 64 * 1024, 0x00240000 }, /* SA72 */
+{ 64 * 1024, 0x00248000 }, /* SA73 */
+{ 64 * 1024, 0x00250000 }, /* SA74 */
+{ 64 * 1024, 0x00258000 }, /* SA75 */
+{ 64 * 1024, 0x00260000 }, /* SA76 */
+{ 64 * 1024, 0x00268000 }, /* SA77 */
+{ 64 * 1024, 0x00270000 }, /* SA78 */
+{ 64 * 1024, 0x00278000 }, /* SA79 */
+{ 64 * 1024, 0x00280000 }, /* SA80 */
+{ 64 * 1024, 0x00288000 }, /* SA81 */
+{ 64 * 1024, 0x00290000 }, /* SA82 */
+{ 64 * 1024, 0x00298000 }, /* SA83 */
+{ 64 * 1024, 0x002a0000 }, /* SA84 */
+{ 64 * 1024, 0x002a8000 }, /* SA85 */
+{ 64 * 1024, 0x002b0000 }, /* SA86 */
+{ 64 * 1024, 0x002b8000 }, /* SA87 */
+{ 64 * 1024, 0x002c0000 }, /* SA88 */
+{ 64 * 1024, 0x002c8000 }, /* SA89 */
+{ 64 * 1024, 0x002d0000 }, /* SA90 */
+{ 64 * 1024, 0x002d8000 }, /* SA91 */
+{ 64 * 1024, 0x002e0000 }, /* SA92 */
+{ 64 * 1024, 0x002e8000 }, /* SA93 */
+{ 64 * 1024, 0x002f0000 }, /* SA94 */
+{ 64 * 1024, 0x002f8000 }, /* SA95 */
+{ 64 * 1024, 0x00300000 }, /* SA96 */
+{ 64 * 1024, 0x00308000 }, /* SA97 */
+{ 64 * 1024, 0x00310000 }, /* SA98 */
+{ 64 * 1024, 0x00318000 }, /* SA99 */
+{ 64 * 1024, 0x00320000 }, /* SA100 */
+{ 64 * 1024, 0x00328000 }, /* SA101 */
+{ 64 * 1024, 0x00330000 }, /* SA102 */
+{ 64 * 1024, 0x00338000 }, /* SA103 */
+{ 64 * 1024, 0x00340000 }, /* SA104 */
+{ 64 * 1024, 0x00348000 }, /* SA105 */
+{ 64 * 1024, 0x00350000 }, /* SA106 */
+{ 64 * 1024, 0x00358000 }, /* SA107 */
+{ 64 * 1024, 0x00360000 }, /* SA108 */
+{ 64 * 1024, 0x00368000 }, /* SA109 */
+{ 64 * 1024, 0x00370000 }, /* SA110 */
+{ 64 * 1024, 0x00378000 }, /* SA111 */
+{ 64 * 1024, 0x00380000 }, /* SA112 */
+{ 64 * 1024, 0x00388000 }, /* SA113 */
+{ 64 * 1024, 0x00390000 }, /* SA114 */
+{ 64 * 1024, 0x00398000 }, /* SA115 */
+{ 64 * 1024, 0x003a0000 }, /* SA116 */
+{ 64 * 1024, 0x003a8000 }, /* SA117 */
+{ 64 * 1024, 0x003b0000 }, /* SA118 */
+{ 64 * 1024, 0x003b8000 }, /* SA119 */
+{ 64 * 1024, 0x003c0000 }, /* SA120 */
+{ 64 * 1024, 0x003c8000 }, /* SA121 */
+{ 64 * 1024, 0x003d0000 }, /* SA122 */
+{ 64 * 1024, 0x003d8000 }, /* SA123 */
+{ 64 * 1024, 0x003e0000 }, /* SA124 */
+{ 64 * 1024, 0x003e8000 }, /* SA125 */
+{ 64 * 1024, 0x003f0000 }, /* SA126 */
+{ 64 * 1024, 0x003f8000 }, /* SA127 */
+};
+
+static const int AMD_FLASH_SECTORS = sizeof(sector)	/ sizeof(struct amd_flash_sector_info);
+
+#define SOFFSET(n)  (sector[n].offset)
+#define SADDR(n)    (SOFFSET(n) >> AMD_FLASH_BUS_SHIFT)
+#define SSIZE(n)	(sector[n].size)
+
+#define AMD_FLASH_DEVICES	1
+
+static AMD_FLASH_CELL *pFlash;
+
+typedef struct romram
+{
+    uint32_t flash_address;
+    uint32_t ram_address;
+    char *name;
+} ROMRAM;
+
+static const struct romram flash_areas[] =
+{
+{ 0xe0000000, 0x00e00000, "BaS" },		/* BaS */
+{ 0xe0600000, 0x00e00000, "EmuTOS" }, 	/* EmuTOS */
+{ 0xe0400000, 0x00e00000, "FireTOS" }, 	/* FireTOS */
+{ 0xe0700000, 0x00e00000, "FPGA" },		/* FPGA config */
+};
+static const int num_flash_areas = sizeof(flash_areas) / sizeof(struct romram);
+
+#define FLASH_ADDRESS BOOTFLASH_BASE_ADDRESS
+
+/*
+ * erase a flash sector
+ *
+ * sector_num is the index into the sector table above.
+ *
+ * FIXME: need to disable data cache to ensure proper operation
+ */
+void amd_flash_sector_erase(int n)
+{
+    volatile AMD_FLASH_CELL status;
+
+    (void) num_flash_areas;     /* to make compiler happy */
+
+    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+    pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+    pFlash[0x555] = AMD_FLASH_CMD_DATA(0x80);
+    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+    pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+    pFlash[SADDR(n)] = AMD_FLASH_CMD_DATA(0x30);
+
+    do
+        status = pFlash[SADDR(n)];
+    while ((status & AMD_FLASH_CMD_DATA(0x80)) != AMD_FLASH_CMD_DATA(0x80));
+
+    /*
+     * Place device in read mode
+     */
+    pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+    pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+    pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+}
+
+int amd_flash_erase(void *start, int bytes, void (*putchar)(int))
+{
+    int i, ebytes = 0;
+
+    if (bytes == 0)
+        return 0;
+
+    for (i = 0; i < AMD_FLASH_SECTORS; i++)
+    {
+        if (start >= (void *)((void *) pFlash + SOFFSET(i)) &&
+                start <= (void *)((void *) pFlash + SOFFSET(i) + (SSIZE(i) - 1)))
+        {
+            break;
+        }
+    }
+
+    while (ebytes < bytes)
+    {
+        if (putchar != NULL)
+        {
+            putchar('.');
+        }
+        amd_flash_sector_erase(i);
+        ebytes += SSIZE(i);
+        i++;
+    }
+
+    if (putchar != NULL)
+    {
+        putchar(10);    /* LF */
+        putchar(13);    /* CR */
+    }
+
+    return ebytes;
+}
+
+void amd_flash_program_cell(AMD_FLASH_CELL *dst, AMD_FLASH_CELL data)
+{
+    volatile AMD_FLASH_CELL status;
+    int retry;
+
+    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+    pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xA0);
+    *dst = data;
+
+    /*
+     * Wait for program operation to finish
+     *  (Data# Polling Algorithm)
+     */
+    retry = 0;
+    while (1)
+    {
+        status = *dst;
+        if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
+                (data & AMD_FLASH_CMD_DATA(0x80)))
+        {
+            break;
+        }
+        if (status & AMD_FLASH_CMD_DATA(0x20))
+        {
+            status = *dst;
+            if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
+                    (data & AMD_FLASH_CMD_DATA(0x80)))
+            {
+                break;
+            }
+            if (++retry > 1024)
+            {
+                break;
+            }
+        }
+    }
+}
+
+
+int amd_flash_program(void *dest, void *source, int bytes, int erase, void (*func)(void), void (*putchar)(int))
+{
+    AMD_FLASH_CELL *src;
+    AMD_FLASH_CELL *dst;
+    int hashi = 1;
+    int hashj = 0;
+    char hash[5];
+
+    hash[0] = 8;  /* Backspace */
+    hash[1] = 124;/* "|" */
+    hash[2] = 47; /* "/" */
+    hash[3] = 45; /* "-" */
+    hash[4] = 92; /* "\" */
+
+    src = (AMD_FLASH_CELL *)source;
+    dst = (AMD_FLASH_CELL *)dest;
+
+    /*
+     * Place device in read mode
+     */
+    pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+    pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+    pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+
+    /*
+     * Erase device if necessary
+     */
+    if (erase)
+    {
+        amd_flash_erase(dest, bytes, putchar);
+    }
+
+    /*
+     * Program device
+     */
+    while (bytes > 0)
+    {
+        amd_flash_program_cell(dst, *src);
+
+        /* Verify Write */
+        if (*dst == *src)
+        {
+            bytes -= AMD_FLASH_CELL_BYTES;
+            *dst++, *src++;
+
+            if ((putchar != NULL))
+            {
+                /* Hash marks to indicate progress */
+                if (hashj == 0x1000)
+                {
+                    hashj = -1;
+                    putchar(hash[0]);
+                    putchar(hash[hashi]);
+
+                    hashi++;
+                    if (hashi == 5)
+                    {
+                        hashi = 1;
+                    }
+
+                }
+                hashj++;
+            }
+        }
+        else
+            break;
+    }
+
+    /*
+     * Place device in read mode
+     */
+    pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+    pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+    pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+
+    if (putchar != NULL)
+    {
+        putchar(hash[0]);
+    }
+
+    /*
+     * If a function was passed in, call it now
+     */
+    if ((func != NULL))
+    {
+        func();
+    }
+
+    return ((int)src - (int)source);
+}
+

BaS_gcc/flash/s19reader.c

@@ -0,0 +1,449 @@
+/*
+ * s19reader.c
+ *
+ *  Created on: 17.12.2012
+ *      Author: mfro
+ *      The ACP Firebee project
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Copyright 2012        M. Froeschle
+ */
+
+#include <bas_types.h>
+
+#include "bas_printf.h"
+#include "bas_string.h"
+#include "sd_card.h"
+#include "diskio.h"
+#include "ff.h"
+#include "s19reader.h"
+#include "dma.h"
+#include "cache.h"
+
+// #define DEBUG
+#include "debug.h"
+
+/*
+ * Yes, I know. The following doesn't really look like code should look like...
+ *
+ * I did try to map structures over the S-records with (packed) which didn't work reliably due to gcc _not_ packing them appropiate
+ * and finally ended up with this. Not nice, put paid (and working).
+ *
+ */
+#define SREC_TYPE(a)        (a)[0]                          /* type of record */
+#define SREC_COUNT(a)       (a)[1]                          /* length of valid bytes to follow */
+#define SREC_ADDR16(a)      (256 * (a)[2] + (a)[3])         /* 2 byte address field */
+#define SREC_ADDR24(a)      (0x10000 * (a)[2] + 0x100 *  \
+    (a)[3] + (a)[4])                                        /* 3 byte address field */
+#define SREC_ADDR32(a) 		(0x1000000 * a[2] + 0x10000 * \
+    (a)[3] + 0x100 * (a)[4] + (a)[5])   /* 4 byte address field */
+#define SREC_DATA16(a)      ((uint8_t *)&((a)[4]))          /* address of first byte of data in a record */
+#define SREC_DATA24(a)      ((uint8_t *)&((a)[5]))          /* address of first data byte in 24 bit record */
+#define SREC_DATA32(a)      ((uint8_t *)&((a)[6]))          /* adress of first byte of a record with 32 bit address field */
+#define SREC_DATA16_SIZE(a)	(SREC_COUNT((a)) - 3)           /* length of the data[] array without the checksum field */
+#define SREC_DATA24_SIZE(a)	(SREC_COUNT((a)) - 4)           /* length of the data[] array without the checksum field */
+#define SREC_DATA32_SIZE(a)	(SREC_COUNT((a)) - 5)           /* length of the data[] array without the checksum field */
+#define SREC_CHECKSUM(a)    (a)[SREC_COUNT(a) + 2 - 1]      /* record's checksum (two's complement of the sum of all bytes) */
+
+/*
+ * convert a single hex character into byte
+ */
+static uint8_t nibble_to_byte(uint8_t nibble)
+{
+    if ((nibble >= '0') && (nibble <= '9'))
+        return nibble - '0';
+    else if ((nibble >= 'A' && nibble <= 'F'))
+        return 10 + nibble - 'A';
+    else if ((nibble >= 'a' && nibble <= 'f'))
+        return 10 + nibble - 'a';
+    return 0;
+}
+
+/*
+ * convert two hex characters into byte
+ */
+static uint8_t hex_to_byte(uint8_t hex[2])
+{
+    return 16 * (nibble_to_byte(hex[0])) + (nibble_to_byte(hex[1]));
+}
+
+#ifdef _NOT_USED_
+/*
+ * convert four hex characters into a 16 bit word
+ */
+static uint16_t hex_to_word(uint8_t hex[4])
+{
+    return 256 * hex_to_byte(&hex[0]) + hex_to_byte(&hex[2]);
+}
+
+/*
+ * convert eight hex characters into a 32 bit word
+ */
+static uint32_t hex_to_long(uint8_t hex[8])
+{
+    return 65536 * hex_to_word(&hex[0]) + hex_to_word(&hex[4]);
+}
+#endif /* _NOT_USED_ */
+
+/*
+ * compute the record checksum
+ *
+ * it consists of the one's complement of the byte sum of the data from the count field until the end
+ */
+static uint8_t checksum(uint8_t arr[])
+{
+    int i;
+    uint8_t cs = SREC_COUNT(arr);
+
+    for (i = 0; i < SREC_COUNT(arr) - 1; i++)
+    {
+        cs += arr[i + 2];
+    }
+    return ~cs;
+}
+
+#ifdef _NOT_USED_
+void print_record(uint8_t *arr)
+{
+    switch (SREC_TYPE(arr))
+    {
+        case 0:
+            {
+                xprintf("type 0x%x ", SREC_TYPE(arr));
+                xprintf("count 0x%x ", SREC_COUNT(arr));
+                xprintf("addr 0x%x ", SREC_ADDR16(arr));
+                xprintf("module %11.11s ", SREC_DATA16(arr));
+                xprintf("chk 0x%x 0x%x\r\n", SREC_CHECKSUM(arr), checksum(arr));
+            }
+            break;
+
+        case 3:
+        case 7:
+            {
+                xprintf("type 0x%x ", SREC_TYPE(arr));
+                xprintf("count 0x%x ", SREC_COUNT(arr));
+                xprintf("addr 0x%x ", SREC_ADDR32(arr));
+                xprintf("data %02x,%02x,%02x,%02x,... ",
+                        SREC_DATA32(arr)[0], SREC_DATA32(arr)[1], SREC_DATA32(arr)[3], SREC_DATA32(arr)[4]);
+                xprintf("chk 0x%x 0x%x\r\n", SREC_CHECKSUM(arr), checksum(arr));
+            }
+            break;
+
+        default:
+            xprintf("unsupported report type %d in print_record\r\n", arr[0]);
+            break;
+    }
+}
+#endif /* _NOT_USED_ */
+
+/*
+ * convert an S-record line into its corresponding byte vector (ASCII->binary)
+ */
+static void line_to_vector(uint8_t *buff, uint8_t *vector)
+{
+    int i;
+    int length;
+    uint8_t *vp = vector;
+
+    length = hex_to_byte(buff + 2);
+
+    buff++;
+    *vp++ = nibble_to_byte(*buff); /* record type. Only one single nibble */
+    buff++;
+
+    for (i = 0; i <= length; i++)
+    {
+        *vp++ = hex_to_byte(buff);
+        buff += 2;
+    }
+}
+
+/*
+ * read and parse a Motorola S-record file and copy contents to dst. The theory of operation is to read and parse the S-record file
+ * and to use the supplied callback routine to copy the buffer to the destination once the S-record line is converted.
+ * The memcpy callback can be anything (as long as it conforms parameter-wise) - a basically empty function to just let
+ * read_srecords validate the file, a standard memcpy() to copy file contents to destination RAM or a more sophisticated
+ * routine that does write/erase flash
+ *
+ * FIXME: Currently only records that the gcc toolchain emits are supported.
+ *
+ * Parameters:
+ *   IN
+ *   	filename - the filename that contains the S-records
+ *   	callback - the memcpy() routine discussed above
+ *   OUT
+ *   	start_address - the execution address of the code as read from the file. Can be used to jump into and execute it
+ *   	actual_length - the overall length of the binary code read from the file
+ *   returns
+ *   	OK or an err_t error code if anything failed
+ */
+err_t read_srecords(char *filename, void **start_address, uint32_t *actual_length, memcpy_callback_t callback)
+{
+    FRESULT fres;
+    FIL file;
+    err_t ret = OK;
+    uint32_t length = 0;
+
+    if ((fres = f_open(&file, filename, FA_READ) == FR_OK))
+    {
+        uint8_t line[255];
+        int lineno = 0;
+        int data_records = 0;
+        bool found_block_header = false;
+        bool found_block_end = false;
+        bool found_block_data = false;
+
+        *actual_length = 0;
+
+        while (ret == OK && (uint8_t *) f_gets((char *) line, sizeof(line), &file) != NULL)
+        {
+            lineno++;
+            uint8_t vector[80];
+
+            memset(vector, 0, sizeof(vector));
+            line_to_vector(line, vector);	/* vector now contains the decoded contents of line, from line[1] on */
+
+            if (line[0] == 'S')
+            {
+                if (SREC_CHECKSUM(vector) != checksum(vector))
+                {
+                    xprintf("invalid checksum 0x%x (should be 0x%x) in line %d\r\n",
+                            SREC_CHECKSUM(vector), checksum(vector), lineno);
+                    ret = FAIL;
+                }
+
+                switch (vector[0])
+                {
+                    case 0:	/* block header */
+                        found_block_header = true;
+                        if (found_block_data || found_block_end)
+                        {
+                            xprintf("S7 or S3 record found before S0: S-records corrupt?\r\n");
+                            ret = FAIL;
+                        }
+
+                        break;
+
+                    case 2: /* three byte address field data record */
+                        if (!found_block_header || found_block_end)
+                        {
+                            xprintf("S2 record found before S0 or after S7: S-records corrupt?\r\n");
+                            ret = FAIL;
+                        }
+                        ret = callback((uint8_t *) SREC_ADDR24(vector), SREC_DATA24(vector), SREC_DATA24_SIZE(vector));
+                        length += SREC_DATA24_SIZE(vector);
+                        data_records++;
+                        break;
+
+                    case 3: /* four byte address field data record */
+                        if (!found_block_header || found_block_end)
+                        {
+                            xprintf("S3 record found before S0 or after S7: S-records corrupt?\r\n");
+                            ret = FAIL;
+                        }
+                        length += SREC_DATA32_SIZE(vector);
+                        ret = callback((uint8_t *) SREC_ADDR32(vector), SREC_DATA32(vector), SREC_DATA32_SIZE(vector));
+                        data_records++;
+                        break;
+
+                    case 7: /* four byte address field end record */
+                        if (!found_block_header || found_block_end)
+                        {
+                            xprintf("S7 record found before S0 or after S7: S-records corrupt?\r\n");
+                        }
+                        else
+                        {
+                            // xprintf("S7 record (end) found after %d valid data blocks\r\n", data_records);
+                            *start_address = (void *) SREC_ADDR32(vector);
+                            xprintf("%d blocks read. Found start address %p\r\n", data_records, *start_address);
+                        }
+                        break;
+
+                    case 8: /* three byte address field end record */
+                        if (!found_block_header || found_block_end)
+                        {
+                            xprintf("S8 record found before S0 or after S8: S-records corrupt?\r\n");
+                        }
+                        else
+                        {
+                            // xprintf("S8 record (end) found after %d valid data blocks\r\n", data_records);
+                            *start_address = (void *) SREC_ADDR24(vector);
+                        }
+                        break;
+
+                    default:
+                        xprintf("unsupported record type (%d) found in line %d\r\n", vector[0], lineno);
+                        xprintf("offending line: \r\n");
+                        xprintf("%s\r\n", line);
+                        ret = FAIL;
+                        break;
+                }
+            }
+            else
+            {
+                xprintf("illegal character ('%c') found on line %d: S-records corrupt?\r\n", line[0], lineno);
+                ret = FAIL;
+                break;
+            }
+        }
+        f_close(&file);
+    }
+    else
+    {
+        xprintf("could not open file %s\r\n", filename);
+        ret = FILE_OPEN;
+    }
+    *actual_length = length;
+    return ret;
+}
+
+/*
+ * this callback just does nothing besides returning OK. Meant to do a dry run over the file to check its integrity
+ */
+static err_t simulate()
+{
+    err_t ret = OK;
+
+    return ret;
+}
+
+
+#ifdef _NOT_USED_
+static err_t flash(uint8_t *dst, uint8_t *src, uint32_t length)
+{
+    err_t ret = OK;
+
+    /* TODO: do the actual flash */
+    amd_flash_program(dst, src, length, false, NULL, xputchar);
+
+    return ret;
+}
+#endif /* _NOT_USED_ */
+
+
+/*
+ * this callback verifies the data against the S-record file contents after a write to destination
+ */
+static err_t verify(uint8_t *dst, uint8_t *src, size_t length)
+{
+    uint8_t *end = src + length;
+
+    do
+    {
+        if (*src++ != *dst++)
+        {
+            xprintf("data differs at %p (expected 0x%02x, got 0x%02x)\r\n",
+                    *(src - 1), *(dst - 1));
+            return FAIL;
+        }
+    } while (src < end);
+
+    return OK;
+}
+
+/*
+ * needed to avoid missing type cast warning below
+ */
+err_t srec_memcpy(uint8_t *dst, uint8_t *src, size_t n)
+{
+    err_t e = OK;
+
+    xprintf(".");
+    dbg("\r\ncopy from %p to %p, length %d", src, dst, n);
+    // dma_memcpy((void *) dst, (void *) src, n);
+    memcpy((void *) dst, (void *) src, n);
+    return e;
+}
+
+void srec_execute(char *flasher_filename)
+{
+    DRESULT res;
+    FRESULT fres;
+    FATFS fs;
+    FIL file;
+    err_t err;
+    void *start_address;
+    uint32_t length;
+
+    disk_initialize(0);
+    res = disk_status(0);
+    if (res == RES_OK)
+    {
+        fres = f_mount(0, &fs);
+        if (fres == FR_OK)
+        {
+            if ((fres = f_open(&file, flasher_filename, FA_READ) != FR_OK))
+            {
+                xprintf("flasher file %s not present on disk\r\n", flasher_filename);
+            }
+            else
+            {
+                f_close(&file);
+
+                /* first pass: parse and check for inconsistencies */
+                xprintf("check file integrity: ");
+                err = read_srecords(flasher_filename, &start_address, &length, simulate);
+                if (err == OK)
+                {
+                    /* next pass: copy data to destination */
+                    xprintf("OK (start address=%p, length = %ld).\r\ncopy data: ", start_address, length);
+                    err = read_srecords(flasher_filename, &start_address, &length, srec_memcpy);
+                    if (err == OK)
+                    {
+                        /* next pass: verify data */
+                        xprintf("OK.\r\nverify data: ");
+                        err = read_srecords(flasher_filename, &start_address, &length, verify);
+                        if (err == OK)
+                        {
+                            xprintf("OK.\r\n");
+
+                            typedef void void_func(void);
+                            void_func *func;
+                            xprintf("target successfully written and verified. Start address: %p\r\n", start_address);
+
+                            func = start_address;
+                            flush_and_invalidate_caches();
+                            (*func)();
+                        }
+                        else
+                        {
+                            xprintf("failed\r\n");
+                        }
+                    }
+                    else
+                    {
+                        xprintf("failed\r\n");
+                    }
+                }
+                else
+                {
+                    xprintf("failed\r\n");
+                }
+            }
+        }
+        else
+        {
+            // xprintf("could not mount FAT FS\r\n");
+        }
+        f_mount(0, NULL);
+    }
+    else
+    {
+        // xprintf("could not initialize SD card\r\n");
+    }
+}
+

BaS_gcc/flash_scripts/flash_firebee_bas.bdm

@@ -11,7 +11,7 @@ wait
 # use system sdram as flashlib scratch area.
 # TODO: plugin flashing seems to work o.k. now for smaller binaries, while it doesn't for larger ones (EmuTOS) yet.
 # This seems to be related to large flash buffers and PC-relative adressing of the plugin
-#flash-plugin 0x1000 0xf000 flash29-5475.plugin
+flash-plugin 0x1000 0xf000 flash29.plugin
 # notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
 flash 0xe0000000