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IP migration and cleanup

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This commit is contained in:
torlus
2014-03-07 20:36:26 +00:00
parent f66ded818d
commit 335660823b
10 changed files with 136 additions and 156 deletions
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8
FPGA_quartus_GE/Interrupt_Handler/interrupt_handler.v
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@@ -222,7 +222,7 @@ module interrupt_handler(MAIN_CLK, nFB_WR, nFB_CS1, nFB_CS2, FB_SIZE0,
// Sub Module Section
lpm_bustri_BYT u0 (.data(u0_data), .enabledt(u0_enabledt),
/*lpm_bustri_BYT u0 (.data(u0_data), .enabledt(u0_enabledt),
.tridata(u0_tridata));
lpm_bustri_BYT u1 (.data(u1_data), .enabledt(u1_enabledt),
@@ -232,7 +232,11 @@ module interrupt_handler(MAIN_CLK, nFB_WR, nFB_CS1, nFB_CS2, FB_SIZE0,
.tridata(u2_tridata));
lpm_bustri_BYT u3 (.data(u3_data), .enabledt(u3_enabledt),
.tridata(u3_tridata));
.tridata(u3_tridata));*/
assign u0_tridata = (u0_enabledt) ? u0_data : 8'hzz;
assign u1_tridata = (u1_enabledt) ? u1_data : 8'hzz;
assign u2_tridata = (u2_enabledt) ? u2_data : 8'hzz;
assign u3_tridata = (u3_enabledt) ? u3_data : 8'hzz;
assign ACP_CONF[31:24] = ACP_CONF_q[31:24];

2
FPGA_quartus_GE/PLLJ_PLLSPE_INFO.txt
View File

@@ -13,7 +13,7 @@ PLLJITTER NA
PLLSPEmax 84
PLLSPEmin -53
PLL_Name altpll4:b2v_inst22|altpll:altpll_component|altpll_r4n2:auto_generated|pll1
PLL_Name altpll4:b2v_inst22|altpll:altpll_component|altpll_qfk2:auto_generated|pll1
PLLJITTER 31
PLLSPEmax 84
PLLSPEmin -53

6
FPGA_quartus_GE/Video/DDR_CTR.v
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@@ -161,11 +161,13 @@ module DDR_CTR(FB_ADR, nFB_CS1, nFB_CS2, nFB_CS3, nFB_OE, FB_SIZE0, FB_SIZE1,
// Sub Module Section
lpm_bustri_BYT u0 (.data(u0_data), .enabledt(u0_enabledt),
/*lpm_bustri_BYT u0 (.data(u0_data), .enabledt(u0_enabledt),
.tridata(u0_tridata));
lpm_bustri_BYT u1 (.data(u1_data), .enabledt(u1_enabledt),
.tridata(u1_tridata));
.tridata(u1_tridata));*/
assign u0_tridata = (u0_enabledt) ? u0_data : 8'hzz;
assign u1_tridata = (u1_enabledt) ? u1_data : 8'hzz;
assign SR_FIFO_WRE = SR_FIFO_WRE_q;

79
FPGA_quartus_GE/Video/video.v
View File

@@ -510,18 +510,20 @@ assign CLUT_ADR[2] = CLUT_ADR2A & SYNTHESIZED_WIRE_61;
assign SYNTHESIZED_WIRE_16 = COLOR4 | COLOR8 | COLOR2;
lpm_bustri_LONG b2v_inst108(
/*lpm_bustri_LONG b2v_inst108(
.enabledt(FB_VDOE[0]),
.data(VDR),
.tridata(FB_AD)
);
);*/
assign FB_AD = (FB_VDOE[0]) ? VDR : 32'hzzzzzzzz;
lpm_bustri_LONG b2v_inst109(
/*lpm_bustri_LONG b2v_inst109(
.enabledt(FB_VDOE[1]),
.data(SYNTHESIZED_WIRE_11),
.tridata(FB_AD)
);
);*/
assign FB_AD = (FB_VDOE[1]) ? SYNTHESIZED_WIRE_11 : 32'hzzzzzzzz;
lpm_ff5 b2v_inst11(
@@ -530,18 +532,20 @@ lpm_ff5 b2v_inst11(
.q(ZR_C8));
lpm_bustri_LONG b2v_inst110(
/*lpm_bustri_LONG b2v_inst110(
.enabledt(FB_VDOE[2]),
.data(SYNTHESIZED_WIRE_13),
.tridata(FB_AD)
);
);*/
assign FB_AD = (FB_VDOE[2]) ? SYNTHESIZED_WIRE_13 : 32'hzzzzzzzz;
lpm_bustri_LONG b2v_inst119(
/*lpm_bustri_LONG b2v_inst119(
.enabledt(FB_VDOE[3]),
.data(SYNTHESIZED_WIRE_14),
.tridata(FB_AD)
);
);*/
assign FB_AD = (FB_VDOE[3]) ? SYNTHESIZED_WIRE_14 : 32'hzzzzzzzz;
lpm_ff1 b2v_inst12(
@@ -677,10 +681,19 @@ lpm_shiftreg4 b2v_inst26(
.shiftout(FIFO_WRE));
lpm_latch0 b2v_inst27(
/*lpm_latch0 b2v_inst27(
.gate(DDR_SYNC_66M),
.data(SYNTHESIZED_WIRE_15),
.q(VDR));
.q(VDR));*/
reg [31:0] VDR_q = 32'd0;
assign VDR = VDR_q;
always @(DDR_SYNC_66M or SYNTHESIZED_WIRE_15) begin
if (DDR_SYNC_66M) begin
VDR_q <= SYNTHESIZED_WIRE_15;
end else begin
VDR_q <= VDR_q;
end
end
assign CLUT_ADR[1] = CLUT_ADR1A & SYNTHESIZED_WIRE_16;
@@ -815,11 +828,12 @@ altddio_out2 b2v_inst5(
lpm_bustri1 b2v_inst51(
/*lpm_bustri1 b2v_inst51(
.enabledt(ST_CLUT_RD),
.data(SYNTHESIZED_WIRE_29),
.tridata(FB_AD[26:24])
);
);*/
assign FB_AD[26:24] = (ST_CLUT_RD) ? SYNTHESIZED_WIRE_29 : 3'bzzz;
lpm_ff3 b2v_inst52(
@@ -828,11 +842,12 @@ lpm_ff3 b2v_inst52(
.q(SYNTHESIZED_WIRE_26));
lpm_bustri_BYT b2v_inst53(
/*lpm_bustri_BYT b2v_inst53(
.enabledt(ACP_CLUT_RD),
.data(SYNTHESIZED_WIRE_30),
.tridata(FB_AD[7:0])
);
);*/
assign FB_AD[7:0] = (ACP_CLUT_RD) ? SYNTHESIZED_WIRE_30 : 8'hzz;
lpm_constant0 b2v_inst54(
@@ -840,25 +855,27 @@ lpm_constant0 b2v_inst54(
lpm_bustri1 b2v_inst56(
/*lpm_bustri1 b2v_inst56(
.enabledt(ST_CLUT_RD),
.data(SYNTHESIZED_WIRE_31),
.tridata(FB_AD[22:20])
);
);*/
assign FB_AD[22:20] = (ST_CLUT_RD) ? SYNTHESIZED_WIRE_31 : 3'bzzz;
lpm_bustri_BYT b2v_inst57(
/*lpm_bustri_BYT b2v_inst57(
.enabledt(ACP_CLUT_RD),
.data(SYNTHESIZED_WIRE_32),
.tridata(FB_AD[15:8])
);
);*/
assign FB_AD[15:8] = (ACP_CLUT_RD) ? SYNTHESIZED_WIRE_32 : 8'hzz;
lpm_bustri_BYT b2v_inst58(
/*lpm_bustri_BYT b2v_inst58(
.enabledt(ACP_CLUT_RD),
.data(SYNTHESIZED_WIRE_33),
.tridata(FB_AD[23:16])
);
);*/
assign FB_AD[23:16] = (ACP_CLUT_RD) ? SYNTHESIZED_WIRE_33 : 8'hzz;
lpm_constant0 b2v_inst59(
@@ -867,11 +884,12 @@ lpm_constant0 b2v_inst59(
lpm_bustri1 b2v_inst61(
/*lpm_bustri1 b2v_inst61(
.enabledt(ST_CLUT_RD),
.data(SYNTHESIZED_WIRE_34),
.tridata(FB_AD[18:16])
);
);*/
assign FB_AD[18:16] = (ST_CLUT_RD) ? SYNTHESIZED_WIRE_34 : 3'bzzz;
lpm_muxDZ b2v_inst62(
@@ -898,11 +916,12 @@ lpm_constant0 b2v_inst64(
assign SYNTHESIZED_WIRE_60 = FIFO_RDE & SYNTHESIZED_WIRE_40;
lpm_bustri3 b2v_inst66(
/*lpm_bustri3 b2v_inst66(
.enabledt(FALCON_CLUT_RDH),
.data(SYNTHESIZED_WIRE_41),
.tridata(FB_AD[31:26])
);
);*/
assign FB_AD[31:26] = (FALCON_CLUT_RDH) ? SYNTHESIZED_WIRE_41 : 6'bzzzzzz;
assign SYNTHESIZED_WIRE_38 = FIFO_RDE & INTER_ZEI;
@@ -924,11 +943,12 @@ lpm_mux6 b2v_inst7(
.result(SYNTHESIZED_WIRE_62));
lpm_bustri3 b2v_inst70(
/*lpm_bustri3 b2v_inst70(
.enabledt(FALCON_CLUT_RDH),
.data(SYNTHESIZED_WIRE_44),
.tridata(FB_AD[23:18])
);
);*/
assign FB_AD[23:18] = (FALCON_CLUT_RDH) ? SYNTHESIZED_WIRE_44 : 6'bzzzzzz;
lpm_ff6 b2v_inst71(
@@ -940,11 +960,12 @@ lpm_ff6 b2v_inst71(
lpm_bustri3 b2v_inst74(
/*lpm_bustri3 b2v_inst74(
.enabledt(FALCON_CLUT_RDL),
.data(SYNTHESIZED_WIRE_45),
.tridata(FB_AD[23:18])
);
);*/
assign FB_AD[23:18] = (FALCON_CLUT_RDL) ? SYNTHESIZED_WIRE_45 : 6'bzzzzzz;

2
FPGA_quartus_GE/firebee1.done
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@@ -1 +1 @@
Mon Mar 03 21:48:22 2014
Fri Mar 07 20:10:16 2014

124
FPGA_quartus_GE/firebee1.qsf
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@@ -736,24 +736,21 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name VERILOG_FILE Video/DDR_CTR.v
set_global_assignment -name VERILOG_FILE Video/VIDEO_MOD_MUX_CLUTCTR.v
set_global_assignment -name VERILOG_FILE Interrupt_Handler/interrupt_handler.v
set_global_assignment -name VERILOG_FILE mux41.v
set_global_assignment -name VERILOG_FILE Video/video.v
set_global_assignment -name VERILOG_FILE firebee1.v
set_global_assignment -name SDC_FILE firebee1.sdc
set_global_assignment -name VERILOG_FILE Video/video.v
set_global_assignment -name VERILOG_FILE Video/DDR_CTR.v
set_global_assignment -name VERILOG_FILE Video/VIDEO_MOD_MUX_CLUTCTR.v
set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd
set_global_assignment -name VERILOG_FILE Interrupt_Handler/interrupt_handler.v
set_global_assignment -name VHDL_FILE DSP/DSP.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd
set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
@@ -762,9 +759,7 @@ set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf177
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd
set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
@@ -783,70 +778,49 @@ set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf214
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
set_global_assignment -name VHDL_FILE lpm_latch0.vhd
set_global_assignment -name QIP_FILE altpll1.qip
set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd
set_global_assignment -name QIP_FILE altpll2.qip
set_global_assignment -name QIP_FILE altpll3.qip
set_global_assignment -name VHDL_FILE Video/altdpram0.vhd
set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd
set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd
set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd
set_global_assignment -name VHDL_FILE altpll2.vhd
set_global_assignment -name VHDL_FILE altpll3.vhd
set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd
set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd
set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd
set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd
set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd
set_global_assignment -name VHDL_FILE altpll1.vhd
set_global_assignment -name QIP_FILE altpll0.qip
set_global_assignment -name QIP_FILE lpm_counter0.qip
set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip
set_global_assignment -name QIP_FILE Video/altdpram0.qip
set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip
set_global_assignment -name QIP_FILE Video/altdpram1.qip
set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip
set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip
set_global_assignment -name QIP_FILE Video/lpm_constant0.qip
set_global_assignment -name QIP_FILE Video/lpm_constant1.qip
set_global_assignment -name QIP_FILE Video/lpm_mux0.qip
set_global_assignment -name QIP_FILE Video/lpm_mux1.qip
set_global_assignment -name QIP_FILE Video/lpm_mux2.qip
set_global_assignment -name QIP_FILE Video/lpm_constant2.qip
set_global_assignment -name QIP_FILE Video/altdpram2.qip
set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip
set_global_assignment -name QIP_FILE Video/lpm_mux3.qip
set_global_assignment -name QIP_FILE Video/lpm_mux4.qip
set_global_assignment -name QIP_FILE Video/lpm_constant3.qip
set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip
set_global_assignment -name QIP_FILE Video/lpm_latch1.qip
set_global_assignment -name QIP_FILE Video/lpm_constant4.qip
set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip
set_global_assignment -name QIP_FILE Video/lpm_compare1.qip
set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip
set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
set_global_assignment -name QIP_FILE Video/lpm_ff4.qip
set_global_assignment -name QIP_FILE Video/lpm_ff5.qip
set_global_assignment -name QIP_FILE Video/lpm_ff6.qip
set_global_assignment -name VECTOR_WAVEFORM_FILE firebee1.vwf
set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip
set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip
set_global_assignment -name QIP_FILE Video/altddio_out0.qip
set_global_assignment -name QIP_FILE Video/lpm_mux5.qip
set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip
set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip
set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip
set_global_assignment -name QIP_FILE Video/altddio_out1.qip
set_global_assignment -name QIP_FILE Video/altddio_out2.qip
set_global_assignment -name QIP_FILE altddio_out3.qip
set_global_assignment -name QIP_FILE Video/lpm_mux6.qip
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd
set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip
set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip
set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip
set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip
set_global_assignment -name QIP_FILE altpll_reconfig1.qip
set_global_assignment -name QIP_FILE altpll4.qip
set_global_assignment -name VERILOG_FILE lpm_ffs.v
set_global_assignment -name VERILOG_FILE mux41.v
set_global_assignment -name QIP_FILE altip/altddio_bidir0.qip
set_global_assignment -name QIP_FILE altip/altddio_out0.qip
set_global_assignment -name QIP_FILE altip/altddio_out1.qip
set_global_assignment -name QIP_FILE altip/altddio_out2.qip
set_global_assignment -name QIP_FILE altip/lpm_compare1.qip
set_global_assignment -name QIP_FILE altip/lpm_constant0.qip
set_global_assignment -name QIP_FILE altip/lpm_constant1.qip
set_global_assignment -name QIP_FILE altip/lpm_constant2.qip
set_global_assignment -name QIP_FILE altip/lpm_constant3.qip
set_global_assignment -name QIP_FILE altip/lpm_constant4.qip
set_global_assignment -name QIP_FILE altip/lpm_mux0.qip
set_global_assignment -name QIP_FILE altip/lpm_mux1.qip
set_global_assignment -name QIP_FILE altip/lpm_mux2.qip
set_global_assignment -name QIP_FILE altip/lpm_mux3.qip
set_global_assignment -name QIP_FILE altip/lpm_mux4.qip
set_global_assignment -name QIP_FILE altip/lpm_mux5.qip
set_global_assignment -name QIP_FILE altip/lpm_mux6.qip
set_global_assignment -name QIP_FILE altip/lpm_muxDZ.qip
set_global_assignment -name QIP_FILE altip/lpm_muxDZ2.qip
set_global_assignment -name QIP_FILE altip/lpm_muxVDM.qip
set_global_assignment -name QIP_FILE altip/lpm_shiftreg0.qip
set_global_assignment -name QIP_FILE altip/lpm_shiftreg1.qip
set_global_assignment -name QIP_FILE altip/lpm_shiftreg2.qip
set_global_assignment -name QIP_FILE altip/lpm_shiftreg3.qip
set_global_assignment -name QIP_FILE altip/lpm_shiftreg4.qip
set_global_assignment -name QIP_FILE altip/lpm_shiftreg5.qip
set_global_assignment -name QIP_FILE altip/lpm_shiftreg6.qip
set_global_assignment -name QIP_FILE altip/altddio_out3.qip
set_global_assignment -name QIP_FILE altip/altpll_reconfig1.qip
set_global_assignment -name QIP_FILE altip/altpll0.qip
set_global_assignment -name QIP_FILE altip/altpll1.qip
set_global_assignment -name QIP_FILE altip/altpll2.qip
set_global_assignment -name QIP_FILE altip/altpll3.qip
set_global_assignment -name QIP_FILE altip/altpll4.qip
set_global_assignment -name QIP_FILE altip/lpm_counter0.qip
set_global_assignment -name QIP_FILE altip/altdpram0.qip
set_global_assignment -name QIP_FILE altip/altdpram1.qip
set_global_assignment -name QIP_FILE altip/altdpram2.qip
set_global_assignment -name QIP_FILE altip/lpm_fifo_dc0.qip
set_global_assignment -name QIP_FILE altip/lpm_fifoDZ.qip
set_global_assignment -name QIP_FILE altip/dcfifo0.qip
set_global_assignment -name QIP_FILE altip/dcfifo1.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

BIN
FPGA_quartus_GE/firebee1.qws
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BIN
FPGA_quartus_GE/firebee1.rbf
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56
FPGA_quartus_GE/firebee1.sdc
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@@ -81,7 +81,7 @@ set_false_path -from [get_registers {*dcfifo*delayed_wrptr_g[*]}] -to [get_regis
set_false_path -from [get_registers {*dcfifo*rdptr_g[*]}] -to [get_registers {*dcfifo*ws_dgrp*}]
set_clock_groups -asynchronous -group { \
altpll4:b2v_inst22|altpll:altpll_component|altpll_r4n2:auto_generated|clk[0] \
altpll4:b2v_inst22|altpll:altpll_component|altpll_qfk2:auto_generated|clk[0] \
} \
-group { \
altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|clk[3] \
@@ -112,53 +112,23 @@ altpll1:b2v_inst|altpll:altpll_component|altpll_8tp2:auto_generated|clk[0] \
} \
#set_multicycle_path -from [get_clocks {altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|clk[2]}] -to [get_clocks {altpll4:b2v_inst22|altpll:altpll_component|altpll_r4n2:auto_generated|clk[0]}] -setup -end 2
#set_multicycle_path -from [get_clocks {altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|clk[2]}] -to [get_clocks {altpll4:b2v_inst22|altpll:altpll_component|altpll_r4n2:auto_generated|clk[0]}] -hold -end 1
set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[4]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[0]}] -setup -end 2
set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[4]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[0]}] -hold -end 1
#set_multicycle_path -from [get_clocks {altpll4:b2v_inst22|altpll:altpll_component|altpll_r4n2:auto_generated|clk[0]}] -to [get_clocks {altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|clk[2]}] -setup -end 2
#set_multicycle_path -from [get_clocks {altpll4:b2v_inst22|altpll:altpll_component|altpll_r4n2:auto_generated|clk[0]}] -to [get_clocks {altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|clk[2]}] -hold -end 1
set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[4]}] -to [get_clocks {CLK33M}] -setup -end 2
set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[4]}] -to [get_clocks {CLK33M}] -hold -end 1
set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[0]}] -to [get_clocks {CLK33M}] -setup -end 2
set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[0]}] -to [get_clocks {CLK33M}] -hold -end 1
set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[3]}] -to [get_clocks {CLK33M}] -setup -end 2
set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[3]}] -to [get_clocks {CLK33M}] -hold -end 1
#set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[2]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -setup -end 2
#set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[2]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -hold -end 1
set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[4]}] -setup -end 2
set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[4]}] -hold -end 1
#set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[3]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -setup -end 2
#set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[3]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -hold -end 1
#set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[1]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -setup -end 2
#set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[1]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -hold -end 1
set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0]}] -setup -end 2
set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0]}] -hold -end 1
#set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[2]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0]}] -setup -end 2
#set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[2]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0]}] -hold -end 1
#set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[3]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0]}] -setup -end 2
#set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[3]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0]}] -hold -end 1
set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -to [get_clocks {CLK33M}] -setup -end 2
set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -to [get_clocks {CLK33M}] -hold -end 1
set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0]}] -to [get_clocks {CLK33M}] -setup -end 2
set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0]}] -to [get_clocks {CLK33M}] -hold -end 1
set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[3]}] -to [get_clocks {CLK33M}] -setup -end 2
set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[3]}] -to [get_clocks {CLK33M}] -hold -end 1
set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -setup -end 2
set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -hold -end 1
set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[1]}] -setup -end 2
set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[1]}] -hold -end 1
#set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0]}] -setup -end 2
#set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0]}] -hold -end 1
#set_false_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll4:b2v_inst22|altpll:altpll_component|altpll_r4n2:auto_generated|clk[0]}]
#set_false_path -to [get_clocks {CLK33M}] -from [get_clocks {altpll4:b2v_inst22|altpll:altpll_component|altpll_r4n2:auto_generated|clk[0]}]
set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[1]}] -setup -end 2
set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[1]}] -hold -end 1
# ---------------------------------------------

15
FPGA_quartus_GE/firebee1.v
View File

@@ -304,7 +304,10 @@ wire DMA_DRQ;
wire DSP_INT;
wire DSP_TA;
wire FALCON_IO_TA;
wire [31:0] FB_ADR;
//GE wire [31:0] FB_ADR;
reg [31:0] FB_ADR;
wire FDC_CLK;
wire HSYNC;
wire INT_HANDLER_TA;
@@ -403,11 +406,17 @@ altpll1 b2v_inst(
.locked(SYNTHESIZED_WIRE_5));
lpm_ff0 b2v_inst1(
/*lpm_ff0 b2v_inst1(
.clock(DDR_SYNC_66M),
.enable(FB_ALE),
.data(FB_AD),
.q(FB_ADR));
.q(FB_ADR));*/
always @(posedge DDR_SYNC_66M)
begin
if (FB_ALE)
FB_ADR <= FB_AD;
end