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fifo_mw never got a value assigned - fixed for testbench, but still open for toplevel

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This commit is contained in:
Markus Fröschle
2014-12-22 08:31:07 +00:00
parent 89f75bd4e8
commit 4bb0527539
7 changed files with 85 additions and 51 deletions
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4
vhdl/backend/Altera/Firebee/firebee.qsf
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@@ -680,7 +680,6 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SYNC_n
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to CLK_DDR_OUT_n
set_instance_assignment -name IO_STANDARD "2.5 V" -to CLK_DDR_OUT_n
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to CLK_DDR_OUT_n
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_location_assignment PIN_F21 -to IRQ_n[2]
set_location_assignment PIN_H20 -to IRQ_n[3]
set_location_assignment PIN_F20 -to IRQ_n[4]
@@ -689,4 +688,5 @@ set_location_assignment PIN_P7 -to IRQ_n[6]
set_location_assignment PIN_N7 -to IRQ_n[7]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQ_n[2]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQ_n[3]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQ_n[4]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQ_n[4]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

66
vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd
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@@ -65,7 +65,7 @@ ENTITY DDR_CTRL IS
ddrclk0 : IN STD_LOGIC;
clk_33m : IN STD_LOGIC;
fifo_mw : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
fifo_mw : IN UNSIGNED (8 DOWNTO 0);
va : OUT STD_LOGIC_VECTOR (12 DOWNTO 0); -- video Adress bus at the DDR chips
vwe_n : OUT STD_LOGIC; -- video memory write enable
@@ -96,19 +96,19 @@ ENTITY DDR_CTRL IS
END ENTITY DDR_CTRL;
ARCHITECTURE BEHAVIOUR of DDR_CTRL IS
-- ddr_access_fifo WATER MARK:
CONSTANT fifo_lwm : INTEGER := 0; -- low water mark
CONSTANT fifo_mwM : INTEGER := 200; -- medium water mark
CONSTANT fifo_hwm : INTEGER := 500; -- high water mark
-- fifo watermark:
CONSTANT FIFO_LWM : INTEGER := 0; -- low water mark
CONSTANT FIFO_MWM : INTEGER := 200; -- medium water mark
CONSTANT FIFO_HWM : INTEGER := 500; -- high water mark
-- constants for bits in video_control_register
CONSTANT vrcr_vcke : INTEGER := 0;
CONSTANT vrcr_refresh_on : INTEGER := 2;
CONSTANT vrcr_config_on : INTEGER := 3;
CONSTANT vrcr_vcs : INTEGER := 1;
CONSTANT VRCR_VCKE : INTEGER := 0;
CONSTANT VRCR_REFRESH_ON : INTEGER := 2;
CONSTANT VRCR_CONFIG_ON : INTEGER := 3;
CONSTANT VRCR_VCS : INTEGER := 1;
--
CONSTANT vrcr_fifo_on : INTEGER := 24;
CONSTANT vrcr_border_on : INTEGER := 25;
CONSTANT VRCR_FIFO_ON : INTEGER := 24;
CONSTANT VRCR_BORDER_ON : INTEGER := 25;
TYPE access_width_t IS (long_access, word_access, byte_access);
TYPE ddr_access_t IS (ddr_access_cpu, ddr_access_fifo, ddr_access_blitter, ddr_access_none);
@@ -160,7 +160,7 @@ ARCHITECTURE BEHAVIOUR of DDR_CTRL IS
SIGNAL ddr_refresh_cnt : UNSIGNED(10 DOWNTO 0) := "00000000000";
SIGNAL ddr_refresh_req : STD_LOGIC;
SIGNAL ddr_refresh_sig : UNSIGNED(3 DOWNTO 0);
SIGNAL refresh_time : STD_LOGIC;
SIGNAL need_refresh : STD_LOGIC;
SIGNAL video_base_l_d : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL video_base_l : STD_LOGIC;
SIGNAL video_base_m_d : STD_LOGIC_VECTOR (7 DOWNTO 0);
@@ -372,7 +372,7 @@ BEGIN
ddr_next_state <= ds_t7f;
WHEN ds_t7f =>
IF cpu_req = '1' AND fifo_mw > STD_LOGIC_VECTOR (TO_UNSIGNED(fifo_lwm, fifo_mw'LENGTH)) THEN
IF cpu_req = '1' AND fifo_mw > FIFO_LWM THEN
ddr_next_state <= ds_cb8; -- Close bank.
ELSIF fifo_req = '1' AND video_adr_cnt(7 DOWNTO 0) = x"FF" THEN -- New page?
ddr_next_state <= ds_cb8; -- Close bank.
@@ -383,7 +383,7 @@ BEGIN
END IF;
WHEN ds_t8f =>
IF fifo_mw < STD_LOGIC_VECTOR (TO_UNSIGNED(fifo_lwm, fifo_mw'LENGTH)) THEN -- Emergency?
IF fifo_mw < FIFO_LWM THEN -- Emergency?
ddr_next_state <= ds_t5f; -- Yes!
ELSE
ddr_next_state <= ds_t9f;
@@ -484,24 +484,24 @@ BEGIN
mcs <= mcs(0) & clk_33m; -- sync on clk_33m
blitter_req <= blitter_sig AND NOT
video_control_register(vrcr_config_on) AND
video_control_register(vrcr_vcke) AND
video_control_register(vrcr_vcs);
video_control_register(VRCR_CONFIG_ON) AND
video_control_register(VRCR_VCKE) AND
video_control_register(VRCR_VCS);
fifo_clr_sync <= fifo_clr;
clear_fifo_cnt <= fifo_clr_sync OR NOT fifo_active;
stop <= fifo_clr_sync OR clear_fifo_cnt;
IF fifo_mw < STD_LOGIC_VECTOR (TO_UNSIGNED(fifo_mwm, fifo_mw'LENGTH)) THEN
IF fifo_mw < fifo_mwm THEN
fifo_req <= '1';
ELSIF fifo_mw < STD_LOGIC_VECTOR (TO_UNSIGNED(fifo_hwm, fifo_mw'LENGTH)) AND fifo_req = '1' THEN
ELSIF fifo_mw < FIFO_HWM AND fifo_req = '1' THEN
fifo_req <= '1';
ELSIF fifo_active = '1' AND
clear_fifo_cnt = '0' AND
stop = '0' AND
ddr_config = '0' AND
video_control_register(vrcr_vcke) = '1' AND
video_control_register(vrcr_vcs) = '1' THEN
video_control_register(VRCR_VCKE) = '1' AND
video_control_register(VRCR_VCS) = '1' THEN
fifo_req <= '1';
ELSE
fifo_req <= '1';
@@ -513,27 +513,27 @@ BEGIN
video_adr_cnt <= video_adr_cnt + 1;
END IF;
IF mcs = "10" AND video_control_register(vrcr_vcke) = '1' AND video_control_register(vrcr_vcs) = '1' THEN
IF mcs = "10" AND video_control_register(VRCR_VCKE) = '1' AND video_control_register(VRCR_VCS) = '1' THEN
cpu_ddr_sync <= '1';
ELSE
cpu_ddr_sync <= '0';
END IF;
IF ddr_refresh_sig /= x"0" AND video_control_register(vrcr_refresh_on) = '1' AND ddr_config = '0' AND refresh_time = '1' THEN
IF ddr_refresh_sig /= x"0" AND video_control_register(VRCR_REFRESH_ON) = '1' AND ddr_config = '0' AND need_refresh = '1' THEN
ddr_refresh_req <= '1';
ELSE
ddr_refresh_req <= '0';
END IF;
IF ddr_refresh_cnt = 0 AND clk_33m = '0' THEN
refresh_time <= '1';
need_refresh <= '1';
ELSE
refresh_time <= '0';
need_refresh <= '0';
END IF;
IF refresh_time = '1' AND video_control_register(vrcr_refresh_on) = '1' AND ddr_config = '0' THEN
IF need_refresh = '1' AND video_control_register(VRCR_REFRESH_ON) = '1' AND ddr_config = '0' THEN
ddr_refresh_sig <= x"9";
ELSIF ddr_state = ds_r6 AND video_control_register(vrcr_refresh_on) = '1' AND ddr_config = '0' THEN
ELSIF ddr_state = ds_r6 AND video_control_register(VRCR_REFRESH_ON) = '1' AND ddr_config = '0' THEN
ddr_refresh_sig <= ddr_refresh_sig - 1;
ELSE
ddr_refresh_sig <= x"0";
@@ -662,7 +662,7 @@ BEGIN
va_s(10) <= '0';
ELSIF ddr_state = ds_t6f THEN
sr_fifo_wre_i <= '1';
ELSIF ddr_state = ds_t7f AND cpu_req = '1' AND fifo_mw > STD_LOGIC_VECTOR (TO_UNSIGNED(fifo_lwm, fifo_mw'LENGTH)) THEN
ELSIF ddr_state = ds_t7f AND cpu_req = '1' AND fifo_mw > FIFO_LWM THEN
va_s(10) <= '1';
ELSIF ddr_state = ds_t7f AND fifo_req = '1' AND video_adr_cnt(7 DOWNTO 0) = x"FF" THEN
va_s(10) <= '1';
@@ -717,13 +717,13 @@ BEGIN
IF ddr_sel = '1' AND fb_wr_n = '1' AND ddr_config = '0' THEN
cpu_req <= '1';
ELSIF ddr_sel = '1' AND access_width /= long_access AND ddr_config = '0' THEN -- Start WHEN NOT config AND NOT long_access word_access access.
ELSIF ddr_sel = '1' AND access_width /= long_access AND ddr_config = '0' THEN -- Start when not config and not longword access.
cpu_req <= '1';
ELSIF ddr_sel = '1' AND ddr_config = '1' THEN -- Config, start immediately.
cpu_req <= '1';
ELSIF fb_regddr = fr_s1 AND fb_wr_n = '0' THEN -- Long word_access write later.
ELSIF fb_regddr = fr_s1 AND fb_wr_n = '0' THEN -- Longword write later.
cpu_req <= '1';
ELSIF fb_regddr /= fr_s1 AND fb_regddr /= fr_s3 AND bus_cyc_end = '0' AND bus_cyc = '0' THEN -- Halt, bus cycle IN progress OR ready.
ELSIF fb_regddr /= fr_s1 AND fb_regddr /= fr_s3 AND bus_cyc_end = '0' AND bus_cyc = '0' THEN -- Halt, bus cycle in progress or ready.
cpu_req <= '0';
END IF;
END PROCESS p_cpu_req;
@@ -784,7 +784,7 @@ BEGIN
-- VIDEO RAM CONTROL REGISTER (IS IN VIDEO_MUX_CTR)
-- $F0000400: BIT 0: vcke; 1: NOT nVCS ;2:REFRESH ON , (0=ddr_access_fifo AND CNT CLEAR);
-- 3: CONFIG; 8: fifo_active;
vcs_n <= NOT(video_control_register(vrcr_refresh_on));
vcs_n <= NOT(video_control_register(VRCR_REFRESH_ON));
ddr_config <= video_control_register(3);
fifo_active <= video_control_register(8);
@@ -814,7 +814,7 @@ BEGIN
vdm_sel_i <= video_base_l_d(3 DOWNTO 0);
-- Current video address:
video_act_adr(26 DOWNTO 4) <= STD_LOGIC_VECTOR (video_adr_cnt - UNSIGNED(fifo_mw));
video_act_adr(26 DOWNTO 4) <= STD_LOGIC_VECTOR (video_adr_cnt - fifo_mw);
video_act_adr(3 DOWNTO 0) <= vdm_sel_i;
p_video_regs : PROCESS

2
vhdl/rtl/vhdl/Firebee/Firebee.vhd
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@@ -407,7 +407,7 @@ ARCHITECTURE Structure of firebee is
SIGNAL fdc_cs_n : STD_LOGIC;
SIGNAL fdc_wr_n : STD_LOGIC;
SIGNAL fifo_clr : STD_LOGIC;
SIGNAL fifo_mw : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL fifo_mw : UNSIGNED (8 DOWNTO 0);
SIGNAL hd_dd_out : STD_LOGIC;
SIGNAL hsync_i : STD_LOGIC;
SIGNAL ide_cf_ta : STD_LOGIC;

5
vhdl/rtl/vhdl/Firebee/Firebee_pkg.vhd
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@@ -43,6 +43,7 @@
-- Initial Release of the second edition.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
PACKAGE firebee_pkg IS
COMPONENT VIDEO_SYSTEM
@@ -91,7 +92,7 @@ PACKAGE firebee_pkg IS
VD_VZ : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
SR_FIFO_WRE : IN STD_LOGIC;
SR_VDMP : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
FIFO_MW : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
FIFO_MW : OUT UNSIGNED (8 DOWNTO 0);
VDM_SEL : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
VIDEO_RAM_CTR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
FIFO_CLR : OUT STD_LOGIC;
@@ -173,7 +174,7 @@ PACKAGE firebee_pkg IS
BLITTER_WR : IN STD_LOGIC;
DDRCLK0 : IN STD_LOGIC;
CLK_33M : IN STD_LOGIC;
FIFO_MW : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
FIFO_MW : IN UNSIGNED (8 DOWNTO 0);
VA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
vwe_n : OUT STD_LOGIC;
vras_n : OUT STD_LOGIC;

12
vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_timers.vhd
View File

@@ -306,7 +306,7 @@ begin
when "010" => PRESCALE := x"09"; -- Prescaler = 10.
when "001" => PRESCALE := x"03"; -- Prescaler = 4.
when "000" => PRESCALE := x"00"; -- Timer stopped or event count mode.
when others => PRESCALE := x"00";
when others => NULL;
end case;
A_CNTSTRB <= '1';
end if;
@@ -330,7 +330,7 @@ begin
when "010" => PRESCALE := x"09"; -- Prescaler = 10.
when "001" => PRESCALE := x"03"; -- Prescaler = 4.
when "000" => PRESCALE := x"00"; -- Timer stopped or event count mode.
when others => PRESCALE := x"00";
when others => NULL;
end case;
B_CNTSTRB <= '1';
end if;
@@ -354,7 +354,7 @@ begin
when "010" => PRESCALE := x"09"; -- Prescaler = 10.
when "001" => PRESCALE := x"03"; -- Prescaler = 4.
when "000" => PRESCALE := x"00"; -- Timer stopped.
when others => PRESCALE := x"00";
when others => NULL;
end case;
C_CNTSTRB <= '1';
end if;
@@ -378,7 +378,7 @@ begin
when "010" => PRESCALE := x"09"; -- Prescaler = 10.
when "001" => PRESCALE := x"03"; -- Prescaler = 4.
when "000" => PRESCALE := x"00"; -- Timer stopped.
when others => PRESCALE := x"00";
when others => NULL;
end case;
D_CNTSTRB <= '1';
end if;
@@ -424,7 +424,7 @@ begin
TAO_I <= not TAO_I; -- Toggle the timer A output pin.
TIMER_A_INT <= '1';
end if;
when others => TAO_I <= '0';
when others => NULL;
end case;
end if;
end if;
@@ -470,7 +470,7 @@ begin
TBO_I <= not TBO_I; -- Toggle the timer B output pin.
TIMER_B_INT <= '1';
end if;
when others => TBO_I <= '0';
when others => NULL;
end case;
end if;
end if;

9
vhdl/testbenches/ddr2_ram_model.vhd
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@@ -674,7 +674,7 @@ BEGIN
END IF;
WHEN "0" & cmd_type_encoding(REFRESH) & cmd_type_encoding(PWR_DOWN) =>
-- 1 tCK_avg
NULL; -- 1 tCK_avg
WHEN "0" & cmd_type_encoding(REFRESH) & cmd_type_encoding(SELF_REF) =>
IF NOW - tm_refresh < TRFC_MIN THEN
@@ -745,10 +745,10 @@ BEGIN
END IF;
WHEN "1" & cmd_type_encoding(ACTIVATE) & "010-" =>
-- tRCD is checked outside this task
NULL; -- tRCD is checked outside this task
WHEN "1" & cmd_type_encoding(ACTIVATE) & cmd_type_encoding(PWR_DOWN) =>
-- 1 tCK
NULL; -- 1 tCK
WHEN "1" & cmd_type_encoding(WRITE_CMD) & cmd_type_encoding(PRECHARGE) =>
IF ck_cntr - ck_bank_write(TO_INTEGER(UNSIGNED(bank)))
@@ -773,7 +773,8 @@ BEGIN
WHEN "0" & cmd_type_encoding(WRITE_CMD) & cmd_type_encoding(PWR_DOWN) =>
WHEN OTHERS => -- do nothing
WHEN OTHERS =>
NULL; -- do nothing
END CASE?;
END;

38
vhdl/testbenches/ddr_ctlr_tb.vhd
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@@ -32,7 +32,7 @@ ARCHITECTURE beh OF ddr_ctlr_tb IS
SIGNAL blitter_wr : STD_LOGIC;
SIGNAL ddrclk0 : STD_LOGIC;
SIGNAL clk_33m : STD_LOGIC := '0';
SIGNAL fifo_mw : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL fifo_mw : UNSIGNED (8 DOWNTO 0) := TO_UNSIGNED(300, 9);
SIGNAL va : STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL vwe_n : STD_LOGIC;
SIGNAL vras_n : STD_LOGIC;
@@ -60,7 +60,7 @@ ARCHITECTURE beh OF ddr_ctlr_tb IS
SIGNAL bus_state : bus_state_t := S0;
BEGIN
t : DDR_CTRL
i_ddr_ctrl : DDR_CTRL
PORT map
(
clk_main => clock,
@@ -104,7 +104,39 @@ BEGIN
data_en_l => data_en_l
);
d1 : ddr2_ram_model
i_ddr2_ram_1 : ddr2_ram_model
GENERIC MAP
(
VERBOSE => TRUE, -- define if you want additional debug output
CLOCK_TICK => (1000000 / 132000) * 1 ps, -- time for one clock tick
BA_BITS => 2, -- number of banks
ADDR_BITS => 13, -- number of address bits
DM_BITS => 2, -- number of data mask bits
DQ_BITS => 8, -- number of data bits
DQS_BITS => 2 -- number of data strobes
)
PORT map
(
ck => ddrclk0,
ck_n => NOT ddrclk0,
cke => vcke,
cs_n => vcs_n,
ras_n => vras_n,
cas_n => vcas_n,
we_n => vwe_n,
dm_rdqs(0) => data_en_l,
dm_rdqs(1) => data_en_h,
ba => ba,
addr => va,
dq => sr_vdmp,
dqs(0) => data_en_l,
dqs(1) => data_en_h,
odt => '0'
);
i_ddr2_ram_2 : ddr2_ram_model
GENERIC MAP
(
VERBOSE => TRUE, -- define if you want additional debug output