started implementing SAMSUNG's Verilog DDR model in VHDL
This commit is contained in:
Markus Fröschle
@@ -4,22 +4,7 @@ LIBRARY IEEE;
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LIBRARY work;
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PACKAGE ddr_ram_model_pkg IS
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-- DDR RAM timing constants
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CONSTANT TRFC_MIN : TIME := 105000 ps; -- refresh to refresh command minimum value
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CONSTANT TRFC_MAX : TIME := 70000000 ps; -- refresh to refresh command maximum value
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CONSTANT TRP : TIME := 13125 ps; -- precharge period
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CONSTANT TRPA : TIME := 13125 ps; -- precharge all period
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CONSTANT TRC : TIME := 54000 ps; -- activate to activate/auto refresh command time
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CONSTANT TRAS_MIN : TIME := 40000 ps; -- minimum active to precharge command time
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CONSTANT TRAS_MAX : TIME := 70000000 ps; -- maximum active to precharge command time
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CONSTANT TRRD : TIME := 10000 ps; -- tRRD: active bank to active bank command time
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CONSTANT TFAW : TIME := 45000 ps; -- four bank activate window
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CONSTANT TWR : TIME := 15000 ps; -- write recovery time
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CONSTANT RANDOM_SEED : INTEGER := 711689044; -- seed value for random generator
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PACKAGE ddr_ram_model_pkg IS
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COMPONENT ddr_ram_model IS
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GENERIC
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(
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@@ -27,31 +12,33 @@ PACKAGE ddr_ram_model_pkg IS
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CLOCK_TICK : TIME := (1000000 / 132000) * 1 ps; -- time for one clock tick
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BA_BITS : INTEGER := 2; -- number of banks
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ADDR_BITS : INTEGER := 13; -- number of address bits
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DM_BITS : INTEGER := 2; -- number of data mask bits
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DQ_BITS : INTEGER := 16; -- number of data bits
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DQS_BITS : INTEGER := 2 -- number of data strobes
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NBANK : INTEGER := 4;
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ADDRTOP : INTEGER := 12;
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A10_LESS : BOOLEAN := TRUE; -- top column address is less than A10
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B : INTEGER := 16; -- number of bit (x16)
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NCOL : INTEGER := 10; -- top column address is CA9 (NCOL- 1)
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PAGEDEPTH : INTEGER := 1024;
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NDM : INTEGER := 2;
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NDQS : INTEGER := 2
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);
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PORT
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(
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ck : IN STD_LOGIC;
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ck_n : IN STD_LOGIC;
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dqi : INOUT STD_LOGIC_VECTOR (B - 1 DOWNTO 0);
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ba : IN UNSIGNED (NBANK / 2 - 1 DOWNTO 0);
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ad : IN STD_LOGIC_VECTOR (ADDRTOP DOWNTO 0);
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rasb : IN STD_LOGIC;
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casb : IN STD_LOGIC;
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web : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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clkb : IN STD_LOGIC;
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cke : IN STD_LOGIC;
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cs_n : IN STD_LOGIC;
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ras_n : IN STD_LOGIC;
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cas_n : IN STD_LOGIC;
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we_n : IN STD_LOGIC;
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dm_rdqs : INOUT UNSIGNED (DM_BITS - 1 DOWNTO 0);
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ba : IN UNSIGNED (BA_BITS - 1 DOWNTO 0);
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addr : IN UNSIGNED (ADDR_BITS - 1 DOWNTO 0);
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dq : INOUT UNSIGNED (DQ_BITS - 1 DOWNTO 0);
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dqs : INOUT UNSIGNED (DQS_BITS - 1 DOWNTO 0);
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dqs_n : INOUT UNSIGNED (DQS_BITS - 1 DOWNTO 0);
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rdqs_n : OUT UNSIGNED (DQS_BITS - 1 DOWNTO 0);
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odt : IN STD_LOGIC
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csb : IN STD_LOGIC;
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dm : IN UNSIGNED (NDM - 1 DOWNTO 0);
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dqs : INOUT STD_LOGIC_VECTOR (NDQS - 1 DOWNTO 0);
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qfc : OUT STD_LOGIC
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);
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END COMPONENT;
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END PACKAGE;
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PACKAGE BODY ddr_ram_model_pkg IS
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@@ -69,716 +56,90 @@ LIBRARY work;
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ENTITY ddr_ram_model IS
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GENERIC
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(
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VERBOSE : BOOLEAN := TRUE; -- define if you want additional debug output
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VERBOSE : BOOLEAN := TRUE; -- define if you want additional debug output
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CLOCK_TICK : TIME := (1000000 / 132000) * 1 ps; -- time for one clock tick
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BA_BITS : INTEGER := 2; -- number of banks
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ADDR_BITS : INTEGER := 13; -- number of address bits
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DM_BITS : INTEGER := 2; -- number of data mask bits
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DQ_BITS : INTEGER := 8; -- number of data bits
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DQS_BITS : INTEGER := 2 -- number of data strobes
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NBANK : INTEGER := 4;
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ADDRTOP : INTEGER := 12;
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A10_LESS : BOOLEAN := TRUE; -- top column address is less than A10
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B : INTEGER := 16; -- number of bit (x16)
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NCOL : INTEGER := 10; -- top column address is CA9 (NCOL- 1)
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PAGEDEPTH : INTEGER := 1024;
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NDM : INTEGER := 2;
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NDQS : INTEGER := 2
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);
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PORT
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(
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ck : IN STD_LOGIC;
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ck_n : IN STD_LOGIC;
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cke : IN STD_LOGIC;
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cs_n : IN STD_LOGIC;
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ras_n : IN STD_LOGIC;
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cas_n : IN STD_LOGIC;
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we_n : IN STD_LOGIC;
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dm_rdqs : INOUT UNSIGNED (DM_BITS - 1 DOWNTO 0);
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ba : IN UNSIGNED (BA_BITS - 1 DOWNTO 0);
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addr : IN UNSIGNED (ADDR_BITS - 1 DOWNTO 0);
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dq : INOUT UNSIGNED (DQ_BITS - 1 DOWNTO 0);
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dqs : INOUT UNSIGNED (DQS_BITS - 1 DOWNTO 0);
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dqs_n : INOUT UNSIGNED (DQS_BITS - 1 DOWNTO 0);
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rdqs_n : OUT UNSIGNED (DQS_BITS - 1 DOWNTO 0);
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odt : IN STD_LOGIC
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);
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dqi : INOUT STD_LOGIC_VECTOR (B - 1 DOWNTO 0);
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ba : IN UNSIGNED (NBANK / 2 - 1 DOWNTO 0);
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ad : IN STD_LOGIC_VECTOR (ADDRTOP DOWNTO 0);
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rasb : IN STD_LOGIC;
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casb : IN STD_LOGIC;
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web : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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clkb : IN STD_LOGIC;
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cke : IN STD_LOGIC;
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csb : IN STD_LOGIC;
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dm : IN UNSIGNED (NDM - 1 DOWNTO 0);
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dqs : INOUT STD_LOGIC_VECTOR (NDQS - 1 DOWNTO 0);
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qfc : OUT STD_LOGIC
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);
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END ENTITY ddr_ram_model;
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ARCHITECTURE rtl OF ddr_ram_model IS
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-- DDR RAM size constants
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CONSTANT MEM_BITS : INTEGER := 10; -- number of write data bursts can be stored in memory. The default is 2 ** 10 = 1024
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CONSTANT AP : INTEGER := 10; -- the address bit that controls auto-precharge and precharge-all
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CONSTANT TDLLK : INTEGER := 200;
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CONSTANT BANKS : INTEGER := TO_INTEGER(SHIFT_LEFT(TO_UNSIGNED(1, 32), BA_BITS));
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CONSTANT ROW_BITS : INTEGER := 13;
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CONSTANT COL_BITS : INTEGER := 10;
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CONSTANT BL_BITS : INTEGER := 3; -- the number of bits required to count to MAX_BL
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CONSTANT BL_MAX : INTEGER := 8;
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CONSTANT BO_BITS : INTEGER := 2; -- the number of burst order bits
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CONSTANT MAX_BITS : INTEGER := BA_BITS + ROW_BITS + COL_BITS - BL_BITS;
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-- DDR RAM timing constants
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CONSTANT TRC : TIME := 65 ps; -- row cycle time (min)
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CONSTANT TRFC : TIME := 115 ps; -- Refresh Row cycle time (min)
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CONSTANT TRASMIN : TIME := 45 ps; -- Row active minimum time
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CONSTANT TRASMAX : TIME := 120000 ps; -- Row active maximum time
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CONSTANT TRCD : TIME := 20 ps; -- Ras to cas delay (min)
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CONSTANT TRP : TIME := 20 ps; -- Row precharge time (min)
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CONSTANT TRRD : TIME := 15 ps; -- Row to row delay (min)
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CONSTANT TCCD : TIME := CLOCK_TICK; -- Col. address to col. address delay: 1 clk
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CONSTANT TCKMIN : TIME := 7.5 ps; -- Clock minimum cycle time
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CONSTANT TCKMAX : TIME := 12 ps; -- Clock maximum cycle time
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CONSTANT TCK15 : TIME := 10 ps; -- Clock minimum cycle time at cas latency=1.5
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CONSTANT TCK2 : TIME := 10 ps; -- Clock minimum cycle time at cas latency=2
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CONSTANT TCK25 : TIME := 7.5 ps; -- Clock minimum cycle time at cas latency=2.5
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CONSTANT TCK3 : TIME := 7.5 ps; -- Clock minimum cycle time at cas latency=3
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CONSTANT TCHMIN : TIME := 0.45 ps; -- Clock high pulse width (min. 0.45 tCK, max: 0.55 tCK)
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CONSTANT TCHMAX : TIME := 0.55 ps;
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CONSTANT TCLMIN : TIME := 0.45 ps; -- Clock low pulse width (min. 0.45 tCK, max: 0.55 tCK)
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CONSTANT TCLMAX : TIME := 0.55 ps;
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CONSTANT TIS : TIME := 0.9 ps; -- input setup time (old Tss)
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CONSTANT TIH : TIME := 0.9 ps; -- input hold time (old Tsh)
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CONSTANT TWR : TIME := 15 ps; -- write recovery time
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CONSTANT TDS : TIME := 0.5 ps; -- Data in & DQM setup time
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CONSTANT TDH : TIME := 0.5 ps; -- Data in & DQM hold time
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CONSTANT TDQSH : TIME := 0.6 ps; -- DQS-in high level width (min. 0.4 tCK, max. 0.6 tCK)
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CONSTANT TDQSL : TIME := 0.6 ps; --
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CONSTANT TDSC : TIME := 1 ps; -- DQS-in cycle time tCIC changed following tDSC
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CONSTANT TPDEX : TIME := 7.5 ps; -- Power down exit time
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CONSTANT TSREX : TIME := 200 ps; -- Self refresh exit time : 200 clk
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CONSTANT THZQ : TIME := 0.75 ps; -- Data out active to High-Z (min:-0.75, max: +0.75)
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CONSTANT TDQSCK : TIME := 0.75 ps; -- DQS out edge to clock edge
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CONSTANT TAC : TIME := 0.75 ps; -- Output data access time from CK/CKB (min: -0.75, max: +0.75)
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CONSTANT TQCSW : TIME := 3.5 ps; -- Delay from the clock edge of write command to QFC out on writes (max: 4ns)
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CONSTANT TQCHW : TIME := 0.5 ps; -- QFC hold time on writes (min 1.25 ns, max: 0.5 tCK)
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CONSTANT TQCH : TIME := 0.4 ps; -- QFC hold time on reads (min 0.4 tCK, max 0.6 tCK)
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CONSTANT TQCS : TIME := 0.9 ps; -- QFC setup time on reads (min: 0.9 tCK, max 1.1 tCK)
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-- time constants
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CONSTANT BUS_DELAY : TIME := 0 ps;
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CONSTANT K1 : INTEGER := 1024;
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CONSTANT M1 : INTEGER := 1048576;
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CONSTANT BYTE : INTEGER := 8;
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-- time constants (in tCK's)
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CONSTANT TMRD : INTEGER := 2; -- load mode register command cycle time
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CONSTANT TCCD : INTEGER := 2; -- CAS to CAS command delay
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CONSTANT TBITS : INTEGER := 512 * M1;
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CONSTANT DQ_PER_DQS : INTEGER := DQ_BITS / DQS_BITS;
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CONSTANT MAX_SIZE : INTEGER := TO_INTEGER(SHIFT_LEFT(TO_UNSIGNED(1, 32), BA_BITS + ROW_BITS + COL_BITS - BL_BITS));
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CONSTANT MEM_SIZE : INTEGER := TO_INTEGER(SHIFT_LEFT(TO_UNSIGNED(1, 32), MEM_BITS));
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CONSTANT AL_MAX : INTEGER := 6;
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CONSTANT CL_MAX : INTEGER := 7;
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CONSTANT MAX_PIPE : INTEGER := 2 * (AL_MAX + CL_MAX);
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TYPE time_array_t IS ARRAY (NATURAL RANGE <>) OF TIME;
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-- clock jitter
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SIGNAL tck_avg : REAL;
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SIGNAL tck_sample : time_array_t (TDLLK - 1 DOWNTO 0);
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SIGNAL tch_sample : time_array_t (TDLLK - 1 DOWNTO 0);
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SIGNAL tcl_sample : time_array_t (TDLLK - 1 DOWNTO 0);
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SIGNAL tck_i : TIME;
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SIGNAL tch_i : TIME;
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SIGNAL tcl_i : TIME;
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SIGNAL tch_avg : REAL;
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SIGNAL tcl_avg : REAL;
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SIGNAL tm_ck_pos : TIME;
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SIGNAL tm_ck_neg : TIME;
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SIGNAL tjit_per_rtime : REAL;
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SIGNAL tjit_cc_time : INTEGER;
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SIGNAL terr_nper_rtime : REAL;
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-- clock skew
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SIGNAL out_delay : REAL;
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SIGNAL dqsck : UNSIGNED (DQS_BITS - 1 DOWNTO 0);
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SIGNAL dqsck_min : INTEGER;
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SIGNAL dqsck_max : INTEGER;
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SIGNAL dqsq_min : INTEGER;
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SIGNAL dqsq_max : INTEGER;
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SIGNAL seed : INTEGER;
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-- mode registers
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SIGNAL burst_order : STD_LOGIC;
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SIGNAL burst_length : UNSIGNED (BL_BITS DOWNTO 0);
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SIGNAL cas_latency : INTEGER;
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SIGNAL additive_latency : INTEGER;
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SIGNAL dll_reset : STD_LOGIC;
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SIGNAL dll_locked : STD_LOGIC;
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SIGNAL dll_en : STD_LOGIC;
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SIGNAL write_recovery : INTEGER;
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SIGNAL low_power : STD_LOGIC;
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SIGNAL odt_rtt : UNSIGNED (1 DOWNTO 0);
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SIGNAL odt_en : STD_LOGIC;
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SIGNAL ocd : UNSIGNED (2 DOWNTO 0);
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SIGNAL dqs_n_en : STD_LOGIC;
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SIGNAL rdqs_en : STD_LOGIC;
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SIGNAL out_en : STD_LOGIC;
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SIGNAL read_latency : INTEGER;
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SIGNAL write_latency : INTEGER;
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TYPE cmd_type_t IS (LOAD_MODE, REFRESH, PRECHARGE, ACTIVATE, WRITE_CMD, READ_CMD, NOP, PWR_DOWN, SELF_REF);
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TYPE cmd_type_encoding_array_t IS ARRAY(cmd_type_t) OF UNSIGNED(3 DOWNTO 0);
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CONSTANT cmd_type_encoding : cmd_type_encoding_array_t :=
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(
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"0000", "0001", "0010", "0011",
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"0100", "0101", "0111", "1000",
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"1001"
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);
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TYPE cmd_string_array_t IS ARRAY (INTEGER RANGE <>) OF STRING(1 TO 9);
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CONSTANT cmd_string : cmd_string_array_t(1 TO 9) :=
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( "Load Mode",
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"Refresh ",
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"Precharge",
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"Activate ",
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"Write ",
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"Read ",
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"No OP ",
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"Pwr Down ",
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"Self Ref "
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);
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-- command state
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SIGNAL active_bank : UNSIGNED (BANKS - 1 DOWNTO 0);
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SIGNAL auto_precharge_bank : UNSIGNED (BANKS - 1 DOWNTO 0);
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SIGNAL write_precharge_bank : UNSIGNED (BANKS - 1 DOWNTO 0);
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SIGNAL read_precharge_bank : UNSIGNED (BANKS - 1 DOWNTO 0);
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TYPE row_array_t IS ARRAY (INTEGER RANGE <>) OF UNSIGNED (BANKS - 1 DOWNTO 0);
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SIGNAL active_row : row_array_t (ROW_BITS - 1 DOWNTO 0);
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SIGNAL in_power_down : STD_LOGIC;
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SIGNAL in_self_refresh : STD_LOGIC;
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SIGNAL init_mode_reg : UNSIGNED (3 DOWNTO 0);
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SIGNAL init_done : STD_LOGIC;
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SIGNAL init_step : INTEGER;
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SIGNAL er_trfc_max : STD_LOGIC;
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SIGNAL odt_state : STD_LOGIC;
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SIGNAL pref_odt : STD_LOGIC;
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-- cmd timers/counters
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SIGNAL ref_cntr : INTEGER;
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SIGNAL ck_cntr : INTEGER;
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SIGNAL ck_load_mode : INTEGER;
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SIGNAL ck_write : INTEGER;
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SIGNAL ck_read : INTEGER;
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SIGNAL ck_write_ap : INTEGER;
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SIGNAL ck_power_down : INTEGER;
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SIGNAL ck_slow_exit_pd : INTEGER;
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SIGNAL ck_self_refresh : INTEGER;
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SIGNAL ck_cke : INTEGER;
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SIGNAL ck_odt : INTEGER;
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SIGNAL ck_dll_reset : INTEGER;
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TYPE ck_bank_array_t IS ARRAY (NATURAL RANGE <>) OF INTEGER;
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SIGNAL ck_bank_write : ck_bank_array_t (BANKS - 1 DOWNTO 0);
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SIGNAL ck_bank_read : ck_bank_array_t (BANKS - 1 DOWNTO 0);
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SIGNAL tm_refresh : TIME;
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SIGNAL tm_precharge : TIME;
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SIGNAL tm_precharge_all : TIME;
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SIGNAL tm_activate : TIME;
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SIGNAL tm_write_end : TIME;
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SIGNAL tm_self_refresh : TIME;
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SIGNAL tm_odt_en : TIME;
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SIGNAL tm_bank_precharge : time_array_t (BANKS - 1 DOWNTO 0);
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SIGNAL tm_bank_activate : time_array_t (BANKS - 1 DOWNTO 0);
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SIGNAL tm_bank_write_end : time_array_t (BANKS - 1 DOWNTO 0);
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SIGNAL tm_bank_read_end : time_array_t (BANKS - 1 DOWNTO 0);
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-- pipelines
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SIGNAL al_pipeline : UNSIGNED (MAX_PIPE DOWNTO 0);
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SIGNAL wr_pipeline : UNSIGNED (MAX_PIPE DOWNTO 0);
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SIGNAL rd_pipeline : UNSIGNED (MAX_PIPE DOWNTO 0);
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SIGNAL odt_pipeline : UNSIGNED (MAX_PIPE DOWNTO 0);
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TYPE ba_pipeline_t IS ARRAY (NATURAL RANGE <>) OF UNSIGNED (BA_BITS - 1 DOWNTO 0);
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SIGNAL ba_pipeline : ba_pipeline_t (MAX_PIPE DOWNTO 0);
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TYPE row_pipeline_t IS ARRAY (NATURAL RANGE <>) OF UNSIGNED (ROW_BITS - 1 DOWNTO 0);
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SIGNAL row_pipeline : row_pipeline_t (MAX_PIPE DOWNTO 0);
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TYPE col_pipeline_t IS ARRAY (NATURAL RANGE <>) OF UNSIGNED (COL_BITS - 1 DOWNTO 0);
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SIGNAL col_pipeline : col_pipeline_t (MAX_PIPE DOWNTO 0);
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SIGNAL prev_cke : STD_LOGIC;
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-- data state
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SIGNAL memory_data : UNSIGNED (BL_MAX * DQ_BITS - 1 DOWNTO 0);
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SIGNAL bit_mask : UNSIGNED (BL_MAX * DQ_BITS - 1 DOWNTO 0);
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SIGNAL burst_position : UNSIGNED (BL_BITS - 1 DOWNTO 0);
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SIGNAL burst_cntr : UNSIGNED (BL_BITS DOWNTO 0);
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SIGNAL dq_temp : UNSIGNED (DQ_BITS - 1 DOWNTO 0);
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SIGNAL check_write_postamble: UNSIGNED (35 DOWNTO 0);
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SIGNAL check_write_preamble : UNSIGNED (35 DOWNTO 0);
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SIGNAL check_write_dqs_high : UNSIGNED (35 DOWNTO 0);
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SIGNAL check_write_dqs_low : UNSIGNED (35 DOWNTO 0);
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SIGNAL check_dm_tdipw : UNSIGNED (17 DOWNTO 0);
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SIGNAL check_dq_tdipw : UNSIGNED (17 DOWNTO 0);
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-- data timers/counters
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SIGNAL tm_cke : TIME;
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SIGNAL tm_odt : TIME;
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SIGNAL tm_tdqss : TIME;
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SIGNAL tm_dm : time_array_t (17 DOWNTO 0);
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SIGNAL tm_dqs : time_array_t (17 DOWNTO 0);
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SIGNAL tm_dqs_pos : time_array_t (35 DOWNTO 0);
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SIGNAL tm_dqss_pos : time_array_t (35 DOWNTO 0);
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SIGNAL tm_dqss_neg : time_array_t (35 DOWNTO 0);
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SIGNAL tm_dq : time_array_t (71 DOWNTO 0);
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SIGNAL tm_cmd_addr : time_array_t (22 DOWNTO 0);
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TYPE cmd_addr_array_t IS ARRAY (INTEGER RANGE <>) OF STRING(1 TO 8);
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CONSTANT cmd_addr_string : cmd_addr_array_t(22 DOWNTO 0) :=
|
||||
(
|
||||
"CS_N ",
|
||||
"RAS_N ",
|
||||
"CAS_N ",
|
||||
"WE_N ",
|
||||
"BA 0 ",
|
||||
"BA 1 ",
|
||||
"BA 2 ",
|
||||
"ADDR 0",
|
||||
"ADDR 1",
|
||||
"ADDR 2",
|
||||
"ADDR 3",
|
||||
"ADDR 4",
|
||||
"ADDR 5",
|
||||
"ADDR 6",
|
||||
"ADDR 7",
|
||||
"ADDR 8",
|
||||
"ADDR 9",
|
||||
"ADDR 10",
|
||||
"ADDR 11",
|
||||
"ADDR 12",
|
||||
"ADDR 13",
|
||||
"ADDR 14",
|
||||
"ADDR 15"
|
||||
);
|
||||
|
||||
TYPE dqs_string_t IS ARRAY (INTEGER RANGE <>) OF STRING (1 TO 5);
|
||||
CONSTANT dqs_string : dqs_string_t (1 DOWNTO 0) :=
|
||||
(
|
||||
"DQS ",
|
||||
"DQS_N"
|
||||
);
|
||||
--SIGNAL BITs : UNSIGNED (B - 1 DOWNTO 0);
|
||||
SIGNAL BIT_C : UNSIGNED (NCOL - 1 DOWNTO 0);
|
||||
CONSTANT NWORD : INTEGER := TBITS / B / NBANK;
|
||||
SIGNAL BIT_T : UNSIGNED (NCOL + ADDRTOP DOWNTO 0);
|
||||
SIGNAL WORD : UNSIGNED (NWORD - 1 DOWNTO 0);
|
||||
|
||||
-- memory storage
|
||||
TYPE mem_t IS ARRAY (INTEGER RANGE <>) OF UNSIGNED (BL_MAX * DQ_BITS - 1 DOWNTO 0);
|
||||
SIGNAL memory : mem_t(0 TO MEM_SIZE - 1);
|
||||
TYPE adr_t IS ARRAY (INTEGER RANGE <>) OF UNSIGNED (MAX_BITS - 1 DOWNTO 0);
|
||||
SIGNAL address : adr_t(0 TO MEM_SIZE - 1);
|
||||
SIGNAL memory_index : UNSIGNED(MEM_BITS DOWNTO 0);
|
||||
SIGNAL memory_used : UNSIGNED(MEM_BITS DOWNTO 0);
|
||||
|
||||
SIGNAL ck_in : STD_LOGIC;
|
||||
SIGNAL ck_n_in : STD_LOGIC;
|
||||
SIGNAL cke_in : STD_LOGIC;
|
||||
SIGNAL cs_n_in : STD_LOGIC;
|
||||
SIGNAL ras_n_in : STD_LOGIC;
|
||||
SIGNAL cas_n_in : STD_LOGIC;
|
||||
SIGNAL we_n_in : STD_LOGIC;
|
||||
SIGNAL dm_in : UNSIGNED (17 DOWNTO 0);
|
||||
SIGNAL ba_in : UNSIGNED (2 DOWNTO 0);
|
||||
SIGNAL addr_in : UNSIGNED (15 DOWNTO 0);
|
||||
SIGNAL dq_in : UNSIGNED (71 DOWNTO 0);
|
||||
SIGNAL dqs_in : UNSIGNED (35 DOWNTO 0);
|
||||
SIGNAL odt_in : STD_LOGIC;
|
||||
|
||||
SIGNAL dm_in_pos : UNSIGNED (17 DOWNTO 0);
|
||||
SIGNAL dm_in_neg : UNSIGNED (17 DOWNTO 0);
|
||||
SIGNAL dq_in_pos : UNSIGNED (71 DOWNTO 0);
|
||||
SIGNAL dq_in_neg : UNSIGNED (71 DOWNTO 0);
|
||||
SIGNAL dq_in_valid : STD_LOGIC;
|
||||
SIGNAL dqs_in_valid : STD_LOGIC;
|
||||
SIGNAL wdqs_cntr : INTEGER;
|
||||
SIGNAL wdq_cntr : INTEGER;
|
||||
|
||||
TYPE integer_array_t IS ARRAY (NATURAL RANGE <>) OF INTEGER;
|
||||
SIGNAL wdqs_pos_cntr : integer_array_t(35 DOWNTO 0);
|
||||
|
||||
SIGNAL b2b_write : STD_LOGIC;
|
||||
SIGNAL prev_dqs_in : UNSIGNED (35 DOWNTO 0);
|
||||
SIGNAL diff_ck : STD_LOGIC;
|
||||
|
||||
SIGNAL dqs_even : UNSIGNED (17 DOWNTO 0);
|
||||
SIGNAL dqs_odd : UNSIGNED (17 DOWNTO 0);
|
||||
SIGNAL cmd_n_in : UNSIGNED (3 DOWNTO 0);
|
||||
|
||||
-- transmit
|
||||
SIGNAL dqs_out_en : STD_LOGIC;
|
||||
SIGNAL dqs_out_en_dly : UNSIGNED (DQS_BITS - 1 DOWNTO 0);
|
||||
SIGNAL dqs_out : STD_LOGIC;
|
||||
SIGNAL dqs_out_dly : UNSIGNED (DQS_BITS - 1 DOWNTO 0);
|
||||
SIGNAL dq_out_en : STD_LOGIC;
|
||||
SIGNAL dq_out_en_dly : UNSIGNED (DQ_BITS - 1 DOWNTO 0);
|
||||
SIGNAL dq_out : UNSIGNED (DQ_BITS - 1 DOWNTO 0);
|
||||
SIGNAL dq_out_dly : UNSIGNED (DQ_BITS - 1 DOWNTO 0);
|
||||
SIGNAL rdqsen_cntr : INTEGER;
|
||||
SIGNAL rdqs_cntr : INTEGER;
|
||||
SIGNAL rdqen_cntr : INTEGER;
|
||||
SIGNAL rdq_cntr : INTEGER;
|
||||
|
||||
SIGNAL r : STD_LOGIC := '0';
|
||||
|
||||
PROCEDURE memory_write(
|
||||
SIGNAL bank : IN UNSIGNED (BA_BITS - 1 DOWNTO 0);
|
||||
SIGNAL row : IN UNSIGNED (ROW_BITS - 1 DOWNTO 0);
|
||||
SIGNAL col : IN UNSIGNED (COL_BITS - 1 DOWNTO 0);
|
||||
SIGNAL data : IN UNSIGNED (BL_MAX * DQ_BITS - 1 DOWNTO 0);
|
||||
SIGNAL addr : INOUT UNSIGNED (MAX_BITS - 1 DOWNTO 0)) IS
|
||||
BEGIN
|
||||
addr <= (bank & row & col) / BL_MAX;
|
||||
-- TODO: only the MAX_MEM defined functionality available here
|
||||
-- memory(addr) <= data;
|
||||
END memory_write;
|
||||
|
||||
PROCEDURE memory_read(
|
||||
SIGNAL bank : IN UNSIGNED (BA_BITS - 1 DOWNTO 0);
|
||||
SIGNAL row : IN UNSIGNED (ROW_BITS - 1 DOWNTO 0);
|
||||
SIGNAL col : IN UNSIGNED (COL_BITS - 1 DOWNTO 0);
|
||||
SIGNAL data : OUT UNSIGNED (BL_MAX * DQ_BITS - 1 DOWNTO 0);
|
||||
SIGNAL addr : INOUT UNSIGNED (MAX_BITS - 1 DOWNTO 0)) IS
|
||||
BEGIN
|
||||
-- chop off the lowest address bits
|
||||
addr <= (bank & row & col) / BL_MAX;
|
||||
-- TODO: only the MAX_MEM defined functionality defined yet
|
||||
-- data <= memory(addr);
|
||||
END memory_read;
|
||||
|
||||
PROCEDURE cmd_task(
|
||||
cke : IN STD_LOGIC;
|
||||
cmd : IN UNSIGNED (3 DOWNTO 0);
|
||||
bank : IN UNSIGNED (BA_BITS - 1 DOWNTO 0);
|
||||
addr : IN UNSIGNED (ADDR_BITS - 1 DOWNTO 0)) IS
|
||||
|
||||
VARIABLE i : UNSIGNED (BANKS DOWNTO 0);
|
||||
VARIABLE j : INTEGER;
|
||||
VARIABLE tfaw_cntr : UNSIGNED (BANKS DOWNTO 0);
|
||||
VARIABLE col : UNSIGNED (COL_BITS - 1 DOWNTO 0);
|
||||
BEGIN
|
||||
END cmd_task;
|
||||
|
||||
|
||||
PROCEDURE initialize(
|
||||
SIGNAL mode_reg0 : IN UNSIGNED (ADDR_BITS - 1 DOWNTO 0);
|
||||
SIGNAL mode_reg1 : IN UNSIGNED (ADDR_BITS - 1 DOWNTO 0);
|
||||
SIGNAL mode_reg2 : IN UNSIGNED (ADDR_BITS - 1 DOWNTO 0);
|
||||
SIGNAL mode_reg3 : IN UNSIGNED (ADDR_BITS - 1 DOWNTO 0)) IS
|
||||
|
||||
CONSTANT AP_BIT : UNSIGNED (ADDR_BITS - 1 DOWNTO 0) := TO_UNSIGNED(2 ** AP, ADDR_BITS);
|
||||
BEGIN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & "INFO: performing initialization sequence");
|
||||
|
||||
cmd_task('1', cmd_type_encoding(NOP), (OTHERS => 'X'), (OTHERS => 'X'));
|
||||
cmd_task('1', cmd_type_encoding(PRECHARGE), (OTHERS => 'X'), AP_BIT);
|
||||
cmd_task('1', cmd_type_encoding(LOAD_MODE), RESIZE(2D"3", BA_BITS), mode_reg3);
|
||||
cmd_task('1', cmd_type_encoding(LOAD_MODE), RESIZE(2D"2", BA_BITS), mode_reg2);
|
||||
cmd_task('1', cmd_type_encoding(LOAD_MODE), RESIZE(2D"1", BA_BITS), mode_reg1);
|
||||
cmd_task('1', cmd_type_encoding(LOAD_MODE), (OTHERS => '0'), mode_reg0 OR "100"); -- DLL reset
|
||||
cmd_task('1', cmd_type_encoding(PRECHARGE), (OTHERS => 'X'), AP_BIT); -- Precharge all
|
||||
cmd_task('1', cmd_type_encoding(REFRESH), (OTHERS => 'X'), (OTHERS => 'X'));
|
||||
cmd_task('1', cmd_type_encoding(REFRESH), (OTHERS => 'X'), (OTHERS => 'X'));
|
||||
cmd_task('1', cmd_type_encoding(LOAD_MODE), (OTHERS => '0'), mode_reg0);
|
||||
cmd_task('1', cmd_type_encoding(LOAD_MODE), RESIZE(2D"1", BA_BITS), mode_reg1 OR x"380"); -- OCD default
|
||||
cmd_task('1', cmd_type_encoding(LOAD_MODE), RESIZE(2D"1", BA_BITS), mode_reg1);
|
||||
cmd_task('1', cmd_type_encoding(NOP), (OTHERS => 'X'), (OTHERS => 'X'));
|
||||
END initialize;
|
||||
|
||||
FUNCTION abs_value(SIGNAL arg : IN REAL) RETURN REAL IS
|
||||
BEGIN
|
||||
IF arg < 0.0 THEN
|
||||
RETURN -1.0 * arg;
|
||||
END IF;
|
||||
|
||||
RETURN arg;
|
||||
END abs_value;
|
||||
|
||||
BEGIN
|
||||
PROCESS (ck)
|
||||
BEGIN
|
||||
ck_in <= ck AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (ck_n)
|
||||
BEGIN
|
||||
ck_n_in <= ck_n AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (cke)
|
||||
BEGIN
|
||||
cke_in <= cke AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (cs_n)
|
||||
BEGIN
|
||||
cs_n_in <= cs_n AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (ras_n)
|
||||
BEGIN
|
||||
ras_n_in <= ras_n AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (cas_n)
|
||||
BEGIN
|
||||
cas_n_in <= cas_n AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (we_n)
|
||||
BEGIN
|
||||
we_n_in <= we_n AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (dm_rdqs)
|
||||
BEGIN
|
||||
dm_in <= RESIZE(dm_rdqs, dm_in'LENGTH) AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (ba)
|
||||
BEGIN
|
||||
ba_in <= RESIZE(ba, ba_in'LENGTH) AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (addr)
|
||||
BEGIN
|
||||
addr_in <= RESIZE(addr, addr_in'LENGTH) AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (dq)
|
||||
BEGIN
|
||||
dq_in <= RESIZE(dq, dq_in'LENGTH) AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (dqs, dqs_n)
|
||||
BEGIN
|
||||
dqs_in <= SHIFT_LEFT(RESIZE(dqs_n, dqs_in'LENGTH), 18) OR RESIZE(dqs, dqs_in'LENGTH);
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (odt)
|
||||
BEGIN
|
||||
odt_in <= odt AFTER BUS_DELAY;
|
||||
END PROCESS;
|
||||
|
||||
-- create internal clock
|
||||
PROCESS
|
||||
BEGIN
|
||||
WAIT UNTIL RISING_EDGE(ck_in);
|
||||
diff_ck <= ck_in;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS
|
||||
BEGIN
|
||||
WAIT UNTIL RISING_EDGE(ck_n_in);
|
||||
diff_ck <= NOT ck_n_in;
|
||||
END PROCESS;
|
||||
|
||||
dqs_even <= dqs_in (17 DOWNTO 0);
|
||||
dqs_odd <= dqs_in (35 DOWNTO 18) WHEN dqs_n_en = '1' ELSE NOT(dqs_in (17 DOWNTO 0));
|
||||
cmd_n_in <= '0' & ras_n_in & cas_n_in & we_n_in WHEN NOT(cs_n_in) ELSE cmd_type_encoding(NOP);
|
||||
|
||||
-- bufif1 buf_dqs
|
||||
dqs <= dqs_out_dly WHEN (dqs_out_en_dly AND UNSIGNED'(0 TO DQS_BITS - 1 => out_en)) /= x"0" ELSE (OTHERS => 'Z');
|
||||
|
||||
-- bufif1 buf_dm
|
||||
dm_rdqs <= dqs_out_dly WHEN (dqs_out_en_dly AND
|
||||
UNSIGNED'(0 TO DM_BITS - 1 => out_en) AND
|
||||
UNSIGNED'(0 TO DM_BITS - 1 => rdqs_en)) /= x"0" ELSE (OTHERS => 'Z');
|
||||
-- bufif1 buf_dqs_n
|
||||
dqs_n <= NOT dqs_out_dly WHEN (dqs_out_en_dly AND
|
||||
UNSIGNED'(0 TO DQS_BITS - 1 => out_en) AND
|
||||
UNSIGNED'(0 TO DQS_BITS - 1 => dqs_n_en)) /= x"0" ELSE (OTHERS => 'Z');
|
||||
-- bufif1 buf_rdqs_n
|
||||
rdqs_n <= NOT dqs_out_dly WHEN (dqs_out_en_dly AND
|
||||
UNSIGNED'(0 TO DQS_BITS - 1 => out_en) AND
|
||||
UNSIGNED'(0 to DQS_BITS - 1 => dqs_n_en) AND
|
||||
UNSIGNED'(0 TO DQS_BITS - 1 => rdqs_en)) /= x"0" ELSE (OTHERS => 'Z');
|
||||
|
||||
-- bufif1 buf_dq
|
||||
dq <= dq_out_dly WHEN (dq_out_en_dly AND
|
||||
UNSIGNED'(0 TO DQ_BITS - 1 => out_en)) /= x"0" ELSE (OTHERS => 'Z');
|
||||
|
||||
-- initial block
|
||||
init : PROCESS
|
||||
BEGIN
|
||||
IF BL_MAX < 2 THEN
|
||||
REPORT("ERROR: BL_MAX parameter must be >= 2. BL_MAX=" & INTEGER'IMAGE(BL_MAX));
|
||||
END IF;
|
||||
|
||||
IF 2 ** BO_BITS > BL_MAX THEN
|
||||
REPORT("ERROR: 2**BO_BITS cannot be greater than BL_MAX parameter");
|
||||
END IF;
|
||||
seed <= RANDOM_SEED;
|
||||
ck_cntr <= 0;
|
||||
|
||||
WAIT;
|
||||
END PROCESS;
|
||||
|
||||
-- ugly kludge: encapsulate reset_task PROCEDURE into a process to make ModelSim happy
|
||||
reset : PROCESS
|
||||
PROCEDURE reset_task IS
|
||||
-- VARIABLE i : INTEGER;
|
||||
BEGIN
|
||||
-- disable inputs
|
||||
dq_in_valid <= '0';
|
||||
dqs_in_valid <= '0';
|
||||
wdqs_cntr <= 0;
|
||||
wdq_cntr <= 0;
|
||||
|
||||
FOR i IN 0 TO 35 LOOP
|
||||
wdqs_pos_cntr(i) <= 0;
|
||||
END LOOP;
|
||||
|
||||
b2b_write <= '0';
|
||||
|
||||
-- disable outputs
|
||||
out_en <= '0';
|
||||
dqs_n_en <= '0';
|
||||
rdqs_en <= '0';
|
||||
dq_out_en <= '0';
|
||||
rdq_cntr <= 0;
|
||||
dqs_out_en <= '0';
|
||||
rdqs_cntr <= 0;
|
||||
|
||||
-- disable ODT
|
||||
odt_en <= '0';
|
||||
odt_state <= '0';
|
||||
|
||||
-- reset bank state
|
||||
active_bank <= (OTHERS => '1');
|
||||
auto_precharge_bank <= (OTHERS =>'0');
|
||||
read_precharge_bank <= (OTHERS => '0');
|
||||
write_precharge_bank <= (OTHERS =>'0');
|
||||
|
||||
-- require initialization sequence
|
||||
init_done <= '0';
|
||||
init_step <= 0;
|
||||
init_mode_reg <= (OTHERS => '0');
|
||||
|
||||
-- reset DLL
|
||||
dll_en <= '0';
|
||||
dll_reset <= '0';
|
||||
dll_locked <= '0';
|
||||
ocd <= (OTHERS => '0');
|
||||
|
||||
-- exit power down and self refresh
|
||||
in_power_down <= '0';
|
||||
in_self_refresh <= '0';
|
||||
|
||||
-- clear pipelines
|
||||
al_pipeline <= (OTHERS => '0');
|
||||
wr_pipeline <= (OTHERS => '0');
|
||||
rd_pipeline <= (OTHERS => '0');
|
||||
odt_pipeline <= (OTHERS => '0');
|
||||
|
||||
-- clear memory
|
||||
FOR i IN 0 TO MAX_SIZE LOOP
|
||||
memory(i) <= (OTHERS => 'X');
|
||||
END LOOP;
|
||||
|
||||
-- clear maximum timing checks
|
||||
tm_refresh <= 0 ns;
|
||||
FOR i IN 0 TO BANKS - 1 LOOP
|
||||
tm_bank_activate(i) <= 0 ns;
|
||||
END LOOP;
|
||||
END reset_task;
|
||||
BEGIN
|
||||
WAIT UNTIL rising_edge(ck);
|
||||
IF r /= '0' THEN
|
||||
reset_task;
|
||||
r <= '0';
|
||||
END IF;
|
||||
END PROCESS; -- reset
|
||||
|
||||
err : PROCESS
|
||||
PROCEDURE chk_err(
|
||||
samebank : IN UNSIGNED (0 DOWNTO 0);
|
||||
bank : IN UNSIGNED (BA_BITS - 1 DOWNTO 0);
|
||||
fromcmd : IN UNSIGNED (3 DOWNTO 0);
|
||||
cmd : IN UNSIGNED (3 DOWNTO 0)
|
||||
) IS
|
||||
|
||||
VARIABLE err : STD_LOGIC;
|
||||
BEGIN
|
||||
-- all matching case expression will be evaluated
|
||||
|
||||
CASE? (samebank & fromcmd & cmd) IS
|
||||
WHEN "0" & cmd_type_encoding(LOAD_MODE) & "0---" =>
|
||||
IF ck_cntr - ck_load_mode < TMRD THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tMRD violation during " & cmd_string(TO_INTEGER(cmd)));
|
||||
END IF;
|
||||
|
||||
WHEN "0" & cmd_type_encoding(LOAD_MODE) & "100-" =>
|
||||
IF ck_cntr - ck_load_mode < TMRD THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " INFO: Load Mode to Reset Condition");
|
||||
END IF;
|
||||
|
||||
WHEN "0" & cmd_type_encoding(REFRESH) & "0---" =>
|
||||
IF NOW - tm_refresh < TRFC_MIN THEN
|
||||
REPORT("tRFC violation during " & cmd_string(TO_INTEGER(cmd)));
|
||||
END IF;
|
||||
|
||||
WHEN "0" & cmd_type_encoding(REFRESH) & cmd_type_encoding(PWR_DOWN) =>
|
||||
NULL; -- 1 tCK_avg
|
||||
|
||||
WHEN "0" & cmd_type_encoding(REFRESH) & cmd_type_encoding(SELF_REF) =>
|
||||
IF NOW - tm_refresh < TRFC_MIN THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & "INFO: Refresh to Reset condition");
|
||||
END IF;
|
||||
init_done <= '0';
|
||||
|
||||
WHEN "0" & cmd_type_encoding(PRECHARGE) & "000-" =>
|
||||
IF NOW - tm_precharge_all < TRPA THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRPA violation during " & cmd_string(TO_INTEGER(cmd)));
|
||||
END IF;
|
||||
IF NOW - tm_precharge < TRP THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRP violation during " & cmd_string(TO_INTEGER(cmd)));
|
||||
END IF;
|
||||
|
||||
WHEN "1" & cmd_type_encoding(PRECHARGE) & cmd_type_encoding(PRECHARGE) =>
|
||||
IF VERBOSE = TRUE AND NOW - tm_precharge_all < TRPA THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " INFO: Precharge All interruption during " & cmd_string(TO_INTEGER(cmd)));
|
||||
END IF;
|
||||
IF VERBOSE = TRUE AND NOW - tm_bank_precharge(TO_INTEGER(bank)) < TRP THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " INFO: Precharge Bank " & INTEGER'IMAGE(TO_INTEGER(bank)) & " interruption during "
|
||||
& cmd_string(TO_INTEGER(cmd)));
|
||||
END IF;
|
||||
|
||||
WHEN "1" & cmd_type_encoding(PRECHARGE) & cmd_type_encoding(ACTIVATE) =>
|
||||
IF NOW - tm_precharge_all < TRPA THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRPA violation during " & cmd_string(TO_INTEGER(cmd)));
|
||||
END IF;
|
||||
IF NOW - tm_bank_precharge(TO_INTEGER(bank)) < TRP THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " tRP violation during " & cmd_string(TO_INTEGER(cmd)) & " to bank "
|
||||
& INTEGER'IMAGE(TO_INTEGER(bank)));
|
||||
END IF;
|
||||
|
||||
WHEN "0" & cmd_type_encoding(PRECHARGE) & cmd_type_encoding(PWR_DOWN) =>
|
||||
-- 1 tCK, can be concurrent with auto precharge
|
||||
|
||||
WHEN "0" & cmd_type_encoding(PRECHARGE) & cmd_type_encoding(SELF_REF) =>
|
||||
IF NOW - tm_precharge_all < TRPA OR NOW - tm_precharge < TRP THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " INFO: Precharge to reset condition");
|
||||
init_done <= '0';
|
||||
END IF;
|
||||
|
||||
WHEN "0" & cmd_type_encoding(ACTIVATE) & cmd_type_encoding(REFRESH) =>
|
||||
IF NOW - tm_activate < TRC THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRC violation during " & cmd_string(TO_INTEGER(cmd)));
|
||||
END IF;
|
||||
|
||||
WHEN "1" & cmd_type_encoding(ACTIVATE) & cmd_type_encoding(PRECHARGE) =>
|
||||
IF NOW - tm_bank_activate(TO_INTEGER(bank)) > TRAS_MAX AND active_bank(TO_INTEGER(bank)) = '1' THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRAS maximum violation during " & cmd_string(TO_INTEGER(cmd)) &
|
||||
" to bank " & INTEGER'IMAGE(TO_INTEGER(bank)));
|
||||
END IF;
|
||||
IF NOW - tm_bank_activate(TO_INTEGER(bank)) < TRAS_MIN THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRAS minimum violation during " & cmd_string(TO_INTEGER(cmd)) &
|
||||
" to bank " & INTEGER'IMAGE(TO_INTEGER(bank)));
|
||||
END IF;
|
||||
|
||||
WHEN "0" & cmd_type_encoding(ACTIVATE) & cmd_type_encoding(ACTIVATE) =>
|
||||
IF NOW - tm_activate < TRRD THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRRD violation during " & cmd_string(TO_INTEGER(cmd)) &
|
||||
" to bank " & INTEGER'IMAGE(TO_INTEGER(bank)));
|
||||
END IF;
|
||||
|
||||
WHEN "1" & cmd_type_encoding(ACTIVATE) & cmd_type_encoding(ACTIVATE) =>
|
||||
IF NOW - tm_bank_activate(TO_INTEGER(bank)) < TRC THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRC violation during " & cmd_string(TO_INTEGER(cmd)) & " to bank " &
|
||||
INTEGER'IMAGE(TO_INTEGER(bank)));
|
||||
END IF;
|
||||
|
||||
WHEN "1" & cmd_type_encoding(ACTIVATE) & "010-" =>
|
||||
NULL; -- tRCD is checked outside this task
|
||||
|
||||
WHEN "1" & cmd_type_encoding(ACTIVATE) & cmd_type_encoding(PWR_DOWN) =>
|
||||
NULL; -- 1 tCK
|
||||
|
||||
WHEN "1" & cmd_type_encoding(WRITE_CMD) & cmd_type_encoding(PRECHARGE) =>
|
||||
IF ck_cntr - ck_bank_write(TO_INTEGER(bank))
|
||||
<= write_latency + TO_INTEGER(burst_length) + 2 OR
|
||||
NOW - tm_bank_write_end(TO_INTEGER(bank)) < TWR THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tWR violation during " & cmd_string(TO_INTEGER(cmd)) &
|
||||
" to bank " & INTEGER'IMAGE(TO_INTEGER(bank)));
|
||||
END IF;
|
||||
|
||||
WHEN "0" & cmd_type_encoding(WRITE_CMD) & cmd_type_encoding(WRITE_CMD) =>
|
||||
IF ck_cntr - ck_write < TCCD THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tCCD violation during " & cmd_string(TO_INTEGER(cmd)) &
|
||||
" to bank " & INTEGER'IMAGE(TO_INTEGER(bank)));
|
||||
END IF;
|
||||
|
||||
WHEN "0" & cmd_type_encoding(WRITE_CMD) & cmd_type_encoding(READ_CMD) =>
|
||||
IF ck_load_mode < ck_write AND ck_cntr - ck_write < write_latency + TO_INTEGER(burst_length) / 2 + 2 - additive_latency THEN
|
||||
REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tWTR violation during " & cmd_string(TO_INTEGER(cmd)) &
|
||||
" to bank " & INTEGER'IMAGE(TO_INTEGER(bank)));
|
||||
END IF;
|
||||
|
||||
WHEN "0" & cmd_type_encoding(WRITE_CMD) & cmd_type_encoding(PWR_DOWN) =>
|
||||
|
||||
|
||||
WHEN OTHERS =>
|
||||
NULL; -- do nothing
|
||||
|
||||
END CASE?;
|
||||
END;
|
||||
BEGIN
|
||||
WAIT UNTIL RISING_EDGE(ck);
|
||||
END PROCESS; -- err
|
||||
CONSTANT HB : INTEGER := B / 2;
|
||||
BEGIN
|
||||
END rtl;
|
||||
|
||||
@@ -469,15 +469,17 @@ BEGIN
|
||||
I_DDR_1 : ddr_ram_model
|
||||
PORT MAP
|
||||
(
|
||||
ck => clk_ddr_out,
|
||||
ck_n => clk_ddr_out_n,
|
||||
clk => clk_ddr_out,
|
||||
clkb => clk_ddr_out_n,
|
||||
cke => vcke,
|
||||
cs_n => vcs_n,
|
||||
ras_n => vras_n,
|
||||
cas_n => vcas_n,
|
||||
we_n => vwe_n,
|
||||
csb => vcs_n,
|
||||
rasb => vras_n,
|
||||
casb => vcas_n,
|
||||
web => vwe_n,
|
||||
ba => UNSIGNED(ba),
|
||||
addr => UNSIGNED(va),
|
||||
odt => '1'
|
||||
ad => va (12 DOWNTO 0),
|
||||
dqi => vd (30 DOWNTO 15),
|
||||
dm => UNSIGNED(vdm (3 DOWNTO 2)),
|
||||
dqs => vd_qs (3 DOWNTO 2)
|
||||
);
|
||||
END beh;
|
||||
Reference in New Issue
Block a user