FPGA_Config

Author	SHA1	Message	Date
Markus Fröschle	87a7353ee8	remove unneeded tristate bus driver	2016-07-28 12:46:05 +00:00
Markus Fröschle	00511897bf	fix capitalisation	2016-07-28 12:33:14 +00:00
Markus Fröschle	f1a038e3a5	finally fixed multiple drivers problem	2016-07-28 11:48:10 +00:00
Markus Fröschle	c6f8a7d4e8	compiles again, but needs reconnecting the split FlexBus signal at top level	2016-07-28 07:11:19 +00:00
Markus Fröschle	cf0c449258	remove inout buffers	2016-07-28 06:08:31 +00:00
Markus Fröschle	8199db400a	removed (most) stuck buffers	2016-07-28 05:33:31 +00:00
Markus Fröschle	43c8e5e149	add firebee_utils_pkg	2016-06-04 06:36:00 +00:00
Markus Fröschle	26125ea4a8	formatting	2016-06-03 07:43:07 +00:00
Markus Fröschle	a40b7175e5	replace translator output with more clear VHDL	2016-06-02 16:28:02 +00:00
Markus Fröschle	f03a1eb525	more fixes	2016-06-02 15:57:06 +00:00
Markus Fröschle	ba5713a154	multiple driver problem	2016-04-28 04:34:30 +00:00
Markus Fröschle	761b807e92	reenable nFB_TA	2016-04-27 15:08:14 +00:00
Markus Fröschle	790663a7cf	remove unneeded component declarations	2016-04-27 11:32:14 +00:00
Markus Fröschle	777e7a4b1c	remove strange constant assignment	2016-04-27 05:59:07 +00:00
Markus Fröschle	36f41e4fb7	fix assignment vector length	2016-04-27 05:24:49 +00:00
Markus Fröschle	195025b4be	fix hold time violations	2016-04-27 05:10:46 +00:00
Markus Fröschle	6cf7000199	fix number of bits to compare	2016-04-26 19:58:21 +00:00
Markus Fröschle	1a972f2c64	reformatting	2016-04-26 19:34:39 +00:00
Markus Fröschle	fa4a3f686c	simplify and fix errors	2016-04-26 16:39:22 +00:00
Markus Fröschle	a7f6d4191e	add function f_addr_cmp()	2016-04-26 06:14:03 +00:00
Markus Fröschle	6a0eebf068	change formatting	2016-04-25 19:09:52 +00:00
Markus Fröschle	fb71e53c7e	fix timing violation at border color assignment	2016-04-14 18:11:14 +00:00
Markus Fröschle	8114dcadf3	fix hsync len calculation for Firebee mode	2016-04-14 05:56:39 +00:00
Markus Fröschle	accc7e85f0	make it compile again	2016-02-10 17:06:57 +00:00
Markus Fröschle	5f55a6738a	cast to std_logic_vector	2016-01-19 17:36:29 +00:00
Markus Fröschle	752b4cd0ad	modify to use WHEN statements instead of binary logic	2016-01-19 15:50:36 +00:00
Markus Fröschle	1846f7eff2	remove specialised clocks	2016-01-19 07:27:27 +00:00
Markus Fröschle	2724be31d1	removed more "indirect" clocks	2016-01-19 07:07:31 +00:00
Markus Fröschle	9f01c704dc	saved	2016-01-18 18:45:17 +00:00
Markus Fröschle	e2ab4af020	get rid of BUFFER parameters	2016-01-18 18:32:50 +00:00
Markus Fröschle	652dd1c124	hold time fix test	2016-01-18 18:15:02 +00:00
Markus Fröschle	e623e668c2	more flexbus_register work	2016-01-18 07:40:08 +00:00
Markus Fröschle	47f6884bbe	add more functionality	2016-01-17 21:45:53 +00:00
Markus Fröschle	b9c3ec9366	modify indent	2016-01-17 20:39:25 +00:00
Markus Fröschle	21a4a80fb7	start of flexbus_register implementation to simplify that	2016-01-17 20:28:18 +00:00
Markus Fröschle	ddad975d6f	fix 13MHz clock sdc	2016-01-17 08:43:20 +00:00
Markus Fröschle	91791dfb5d	do not automatically insert delay chains	2016-01-16 22:11:51 +00:00
Markus Fröschle	58a69ffc5f	reformat	2016-01-16 22:04:05 +00:00
Markus Fröschle	7bf4d912a0	fix timing	2016-01-16 21:38:17 +00:00
Markus Fröschle	0fe61bedef	fix output delay	2016-01-15 17:38:29 +00:00
Markus Fröschle	11bd410c15	simplify processes	2016-01-15 08:37:40 +00:00
Markus Fröschle	f11629ac29	fix video base address and video counter register	2016-01-14 22:02:44 +00:00
Markus Fröschle	c4d56bb652	reformat	2016-01-14 16:49:11 +00:00
Markus Fröschle	b7a34c8abf	reformat	2016-01-14 07:17:08 +00:00
Markus Fröschle	69c107ef32	remove unused connections	2016-01-14 06:45:15 +00:00
Markus Fröschle	52e1b53192	formatting	2016-01-14 06:44:52 +00:00
Markus Fröschle	4ed4616156	remove unused generated signals	2016-01-13 16:43:54 +00:00
Markus Fröschle	97a48bf636	reactivated delay chain	2016-01-13 15:04:24 +00:00
Markus Fröschle	fd5abf8b4a	reformat	2016-01-13 13:23:46 +00:00
Markus Fröschle	90c0f7758d	remove AHDL files	2016-01-13 12:54:00 +00:00

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156 Commits