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FPGA_Config
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1846f7eff25f1c103822f8118248b159f7d6ac4a
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Markus Fröschle
1846f7eff2
remove specialised clocks
2016-01-19 07:27:27 +00:00
FPGA_Quartus_13.1
remove specialised clocks
2016-01-19 07:27:27 +00:00
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10
MiB
Languages
VHDL
83.4%
Verilog
13.1%
PHP
2.1%
Tcl
0.6%
Assembly
0.4%
Other
0.4%