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add more functionality

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This commit is contained in:
Markus Fröschle
2016-01-17 21:45:53 +00:00
parent b9c3ec9366
commit 47f6884bbe
2 changed files with 10 additions and 5 deletions
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4
FPGA_Quartus_13.1/Video/DDR_CTR.vhd
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@@ -278,6 +278,7 @@ ARCHITECTURE rtl OF ddr_ctr IS
SIGNAL LINE : std_logic;
SIGNAL v_bash : std_logic_vector(7 DOWNTO 0);
SIGNAL v_bash_cs : std_logic;
SIGNAL reg_ta : std_logic;
-- Sub Module Interface Section
@@ -588,8 +589,9 @@ BEGIN
fb_addr => fb_adr,
fb_data => fb_ad,
fb_cs => ('0', '0', nfb_cs3, nfb_cs2, nfb_cs1),
fb_ta_n => reg_ta,
fb_wr_n => nfb_wr,
data => v_bash,
reg_value => v_bash,
cs => v_bash_cs
);

11
FPGA_Quartus_13.1/flexbus_register.vhd
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@@ -14,10 +14,11 @@ ENTITY flexbus_register IS
(
clk : IN std_logic;
fb_addr : IN std_logic_vector(31 DOWNTO 0);
fb_data : IN std_logic_vector(31 DOWNTO 0);
fb_data : INOUT std_logic_vector(31 DOWNTO 0);
fb_cs : IN std_logic_vector(5 DOWNTO 1);
fb_wr_n : IN std_logic;
data : OUT std_logic_vector(reg_width - 1 DOWNTO 0);
fb_ta_n : OUT std_logic;
reg_value : INOUT std_logic_vector(reg_width - 1 DOWNTO 0);
cs : OUT std_logic := '0'
);
END ENTITY flexbus_register;
@@ -25,7 +26,6 @@ END ENTITY flexbus_register;
ARCHITECTURE rtl OF flexbus_register IS
SIGNAL fbcs_match : std_logic;
SIGNAL address_match : std_logic;
SIGNAL reg_value : std_logic_vector(reg_width - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
fbcs_match <= '1' WHEN fb_cs(match_fbcs) = '1' ELSE '0';
address_match <= '1' WHEN (fb_addr and match_mask) = (match_address and match_mask) ELSE '0';
@@ -38,9 +38,12 @@ BEGIN
IF fb_wr_n = '0' THEN -- write access
reg_value <= fb_data(reg_width - 1 DOWNTO 0);
ELSE -- read access
data <= reg_value;
fb_data(reg_width - 1 DOWNTO 0) <= reg_value;
fb_ta_n <= '0';
END IF;
ELSE
fb_data <= (OTHERS => 'Z');
fb_ta_n <= 'Z';
cs <= '0';
END IF;
END IF;