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Sync with Fredi's source tree 13/06/2015

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Parallel port fix.
This commit is contained in:
David Gálvez
2018-04-09 17:19:13 +02:00
parent 3fb6e3bd8a
commit 68129dbe57
107 changed files with 12435 additions and 27384 deletions
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314
FPGA_by_Fredi/BLITTER.tdf Normal file
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-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2010 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
-- Created on Sat Jan 15 11:06:17 2011
INCLUDE "lpm_bustri_WORD.inc";
INCLUDE "VIDEO/BLITTER/lpm_clshift0.INC";
INCLUDE "VIDEO/BLITTER/altsyncram0.INC";
CONSTANT BL_SKEW_LF = 255;
-- Title Statement (optional)
TITLE "Blitter";
-- Parameters Statement (optional)
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-- Subdesign Section
SUBDESIGN BLITTER
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
nRSTO : INPUT;
MAIN_CLK : INPUT;
FB_ALE : INPUT;
nFB_WR : INPUT;
nFB_OE : INPUT;
FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT;
VIDEO_RAM_CTR[15..0] : INPUT;
BLITTER_ON : INPUT;
FB_ADR[31..0] : INPUT;
nFB_CS1 : INPUT;
nFB_CS2 : INPUT;
nFB_CS3 : INPUT;
DDRCLK0 : INPUT;
BLITTER_DIN[127..0] : INPUT;
BLITTER_DACK[4..0] : INPUT;
SR_BLITTER_DACK : INPUT;
BLITTER_RUN : OUTPUT;
BLITTER_DOUT[127..0] : OUTPUT;
BLITTER_ADR[31..0] : OUTPUT;
BLITTER_SIG : OUTPUT;
BLITTER_WR : OUTPUT;
BLITTER_TA : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
VARIABLE
FB_B[3..0] :NODE;
FB_16B[1..0] :NODE;
BLITTER_CS :NODE;
BL_BUSY :NODE;
BL_HRAM_CS :NODE;
BL_HRAM_ADR[3..0] :NODE;
BL_HRAM_OUT[15..0] :NODE;
BL_HRAM_BE[1..0] :NODE;
BL_SRC_X_INC_CS :NODE;
BL_SRC_X_INC[15..0] :DFFE;
BL_SRC_Y_INC_CS :NODE;
BL_SRC_Y_INC[15..0] :DFFE;
BL_ENDMASK1_CS :NODE;
BL_ENDMASK1[15..0] :DFFE;
BL_ENDMASK2_CS :NODE;
BL_ENDMASK2[15..0] :DFFE;
BL_ENDMASK3_CS :NODE;
BL_ENDMASK3[15..0] :DFFE;
BL_SRC_ADRH_CS :NODE;
BL_SRC_ADRL_CS :NODE;
BL_SRC_ADR[31..0] :DFFE;
BL_DST_X_INC_CS :NODE;
BL_DST_X_INC[15..0] :DFFE;
BL_DST_Y_INC_CS :NODE;
BL_DST_Y_INC[15..0] :DFFE;
BL_DST_ADRH_CS :NODE;
BL_DST_ADRL_CS :NODE;
BL_DST_ADR[31..0] :DFFE;
BL_X_CNT_CS :NODE;
BL_X_CNT[15..0] :DFFE;
BL_Y_CNT_CS :NODE;
BL_Y_CNT[15..0] :DFFE;
BL_HT_OP_CS :NODE;
BL_HT_OP[7..0] :DFFE;
BL_LC_OP[7..0] :DFFE;
BL_LN_CS :NODE;
BL_LN[7..0] :DFFE;
BL_SKEW[7..0] :DFFE;
BL_SKEW_EXT[6..0] :NODE;
BL_SKEW_IN[255..0] :DFFE;
BL_SKEW_OUT[255..0] :NODE;
BL_DATA_DDR_READY :DFF; -- 1 WENN DATEN GESCHRIEBEN ODER LESBAR
BL_READ_SRC :DFFE;
BL_DST_BUFFER[127..0] :DFFE;
BL_READ_DST :DFFE;
HOP_OUT[127..0] :NODE;
COUNT[18..0] :DFF;
BEGIN
-- BYT SELECT 32 BIT
FB_B0 = FB_ADR[1..0]==0; -- ADR==0
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- BYT SELECT 16 BIT
FB_16B0 = FB_ADR[0]==0; -- ADR==0
FB_16B1 = FB_ADR[0]==1 -- ADR==1
# !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT
-- BLITTER CS
BLITTER_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..6]==H"3E28"; -- FFFF8A00-3F/40
BLITTER_TA = BLITTER_CS;
-- REGISTER
-- HALFTON RAM
BL_HRAM_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..5]==H"7C50"; -- $F8A00/20
BL_HRAM_BE1 = BL_HRAM_CS & FB_16B0 # !BL_HRAM_CS;
BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1 # !BL_HRAM_CS;
BL_HRAM_ADR[] = BL_HRAM_CS & FB_ADR[4..1]
# !BL_HRAM_CS & BL_LN[3..0];
BL_HRAM_OUT[] = altsyncram0(BL_HRAM_ADR[],BL_HRAM_BE[],DDRCLK0,FB_AD[31..16],BL_HRAM_CS & !nFB_WR);
-- SRC X INC
BL_SRC_X_INC[].CLK = MAIN_CLK;
BL_SRC_X_INC[] = !BL_BUSY & FB_AD[31..16];
BL_SRC_X_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C510"; -- $F8A20/2
BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_X_INC[7..0].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
-- SRC Y INC
BL_SRC_Y_INC[].CLK = MAIN_CLK;
BL_SRC_Y_INC[] = !BL_BUSY & FB_AD[31..16];
BL_SRC_Y_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C511"; -- $F8A22/2
BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_Y_INC[7..0].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
-- SRC ADR HIGH
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[31..16] = !BL_BUSY & FB_AD[31..16];
BL_SRC_ADRH_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C512"; -- $F8A24/2
BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
-- SRC ADR LOW
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[15..0] = !BL_BUSY & FB_AD[31..16];
BL_SRC_ADRL_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C513"; -- $F8A26/2
BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[7..0].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
-- ENDMASK 1
BL_ENDMASK1[].CLK = MAIN_CLK;
BL_ENDMASK1[] = FB_AD[31..16];
BL_ENDMASK1_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C514"; -- $F8A28/2
BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
BL_ENDMASK1[7..0].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
-- ENDMASK 2
BL_ENDMASK2[].CLK = MAIN_CLK;
BL_ENDMASK2[] = FB_AD[31..16];
BL_ENDMASK2_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C515"; -- $F8A2A/2
BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
BL_ENDMASK2[7..0].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
-- ENDMASK 3
BL_ENDMASK3[].CLK = MAIN_CLK;
BL_ENDMASK3[] = FB_AD[31..16];
BL_ENDMASK3_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C516"; -- $F8A2C/2
BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
BL_ENDMASK3[7..0].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
-- DST X INC
BL_DST_X_INC[].CLK = MAIN_CLK;
BL_DST_X_INC[] = !BL_BUSY & FB_AD[31..16];
BL_DST_X_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C517"; -- $F8A2E/2
BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
BL_DST_X_INC[7..0].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
-- DST Y INC
BL_DST_Y_INC[].CLK = MAIN_CLK;
BL_DST_Y_INC[] = !BL_BUSY & FB_AD[31..16];
BL_DST_Y_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C518"; -- $F8A30/2
BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
BL_DST_Y_INC[7..0].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
-- DST ADR HIGH
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[31..16] = !BL_BUSY & FB_AD[31..16];
BL_DST_ADRH_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C512"; -- $F8A24/2
BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
-- DST ADR LOW
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[15..0] = !BL_BUSY & FB_AD[31..16];
BL_DST_ADRL_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C513"; -- $F8A26/2
BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[7..0].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
-- X COUNT
BL_X_CNT[].CLK = MAIN_CLK;
BL_X_CNT[] = !BL_BUSY & FB_AD[31..16];
BL_X_CNT_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51B"; -- $F8A36/2
BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
BL_X_CNT[7..0].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B1;
-- Y COUNT
BL_Y_CNT[].CLK = MAIN_CLK;
BL_Y_CNT[] = !BL_BUSY & FB_AD[31..16];
BL_Y_CNT_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51C"; -- $F8A38/2
BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
BL_Y_CNT[7..0].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
-- HALFTONE OP BYT
BL_HT_OP[].CLK = MAIN_CLK;
BL_HT_OP[] = FB_AD[31..24];
BL_HT_OP_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51D"; -- $F8A3A/2
BL_HT_OP[7..0].ENA = BL_HT_OP_CS & !nFB_WR & FB_16B0;
-- LOGIC OP BYT
BL_LC_OP[].CLK = MAIN_CLK;
BL_LC_OP[] = FB_AD[23..16];
BL_LC_OP[7..0].ENA = BL_HT_OP_CS & !nFB_WR & FB_16B1; -- $F8A3B
-- LINE NUMBER BYT
BL_LN[].CLK = MAIN_CLK;
BL_LN[] = !BL_BUSY & FB_AD[31..24];
BL_LN_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51E"; -- $F8A3C/2
BL_LN[7..0].ENA = BL_LN_CS & !nFB_WR & FB_16B0;
-- SKEW BYT
BL_SKEW[].CLK = MAIN_CLK;
BL_SKEW[] = FB_AD[31..24];
BL_SKEW[7..0].ENA = BL_LN_CS & !nFB_WR & FB_16B1; -- $F8A3D
--- REGISTER OUT
FB_AD[31..16] = lpm_bustri_WORD(
BL_HRAM_CS & BL_HRAM_OUT[]
# BL_SRC_X_INC_CS & BL_SRC_X_INC[]
# BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
# BL_SRC_ADRH_CS & BL_SRC_ADR[31..16]
# BL_SRC_ADRL_CS & BL_SRC_ADR[15..0]
# BL_ENDMASK1_CS & BL_ENDMASK1[]
# BL_ENDMASK2_CS & BL_ENDMASK2[]
# BL_ENDMASK3_CS & BL_ENDMASK3[]
# BL_DST_X_INC_CS & BL_DST_X_INC[]
# BL_DST_Y_INC_CS & BL_DST_Y_INC[]
# BL_DST_ADRH_CS & BL_DST_ADR[31..16]
# BL_DST_ADRL_CS & BL_DST_ADR[15..0]
# BL_X_CNT_CS & BL_X_CNT[]
# BL_Y_CNT_CS & BL_Y_CNT[]
# BL_HT_OP_CS & (BL_HT_OP[],BL_LC_OP[])
# BL_LN_CS & (BL_LN[],BL_SKEW[])
,BLITTER_CS & !nFB_OE); -- FFFF8A00-3F/40
-----------------------------------------
--
BL_READ_SRC.CLK = DDRCLK0;
BL_READ_DST.CLK = DDRCLK0;
-- READY SIGNAL 1 CLOCK SP<53>TER
BL_DATA_DDR_READY.CLK = DDRCLK0;
BL_DATA_DDR_READY = BL_DATA_DDR_READY & BLITTER_DACK0;
-- SRC BUFFER LADEN
BL_SKEW_IN[].CLK = DDRCLK0;
BL_SKEW_IN[].ENA = BL_DATA_DDR_READY & BL_READ_SRC;
BL_SKEW_IN[255..128] = BLITTER_DIN[];
BL_SKEW_IN[127..0] = BL_SKEW_IN[255..128];
-- DST BUFFER LADEN
BL_DST_BUFFER[].CLK = DDRCLK0;
BL_DST_BUFFER[].ENA = BL_DATA_DDR_READY & BL_READ_DST;
BL_DST_BUFFER[] = BLITTER_DIN[];
-- SKEW EXTENDET
BL_SKEW_EXT[6..4] = BL_SRC_ADR[3..1];
BL_SKEW_EXT[3..0] = BL_SKEW[3..0];
-- SKEW EXT MUX
BL_SKEW_OUT[] = lpm_clshift0(BL_SKEW_IN[],BL_SKEW_EXT[]); -- BIT 127..0 SIND RELEVANT
-- HOP
IF BL_HT_OP[1..0]==B"00" THEN
HOP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
ELSE
IF BL_HT_OP[1..0]==B"01" THEN
HOP_OUT[] = (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]);
ELSE
IF BL_HT_OP[1..0]==B"10" THEN
HOP_OUT[] = BL_SKEW_OUT[127..0];
ELSE
HOP_OUT[] = BL_SKEW_OUT[127..0] & (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]);
END IF;
END IF;
END IF;
BLITTER_RUN = GND; --VCC;
BLITTER_SIG = GND; --VCC;
BLITTER_WR = GND; --VCC;
BL_BUSY = GND;
COUNT[] = COUNT[] + 16;
COUNT[].CLK = BLITTER_DACK0;
BLITTER_DOUT[] = H"112233445566778899AABBCCDDEEFF00";
BLITTER_ADR[] = (0, COUNT[]) + 400000;
END;

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-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2010 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
-- Created on Sat Jan 15 11:06:17 2011
INCLUDE "lpm_bustri_WORD.inc";
INCLUDE "VIDEO/BLITTER/lpm_clshift0.INC";
INCLUDE "VIDEO/BLITTER/altsyncram0.INC";
CONSTANT BL_SKEW_LF = 255;
-- Title Statement (optional)
TITLE "Blitter";
-- Parameters Statement (optional)
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-- Subdesign Section
SUBDESIGN BLITTER
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
nRSTO : INPUT;
MAIN_CLK : INPUT;
FB_ALE : INPUT;
nFB_WR : INPUT;
nFB_OE : INPUT;
FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT;
VIDEO_RAM_CTR[15..0] : INPUT;
BLITTER_ON : INPUT;
FB_ADR[31..0] : INPUT;
nFB_CS1 : INPUT;
nFB_CS2 : INPUT;
nFB_CS3 : INPUT;
DDRCLK0 : INPUT;
BLITTER_DIN[127..0] : INPUT;
BLITTER_DACK[4..0] : INPUT;
SR_BLITTER_DACK : INPUT;
BLITTER_RUN : OUTPUT;
BLITTER_DOUT[127..0] : OUTPUT;
BLITTER_ADR[31..0] : OUTPUT;
BLITTER_SIG : OUTPUT;
BLITTER_WR : OUTPUT;
BLITTER_TA : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
VARIABLE
FB_B[3..0] :NODE;
FB_16B[1..0] :NODE;
BLITTER_CS :NODE;
BL_BUSY :NODE;
BL_HRAM_CS :NODE;
BL_HRAM_ADR[3..0] :NODE;
BL_HRAM_OUT[15..0] :NODE;
BL_HRAM_BE[1..0] :NODE;
BL_SRC_X_INC_CS :NODE;
BL_SRC_X_INC[15..0] :DFFE;
BL_SRC_Y_INC_CS :NODE;
BL_SRC_Y_INC[15..0] :DFFE;
BL_ENDMASK1_CS :NODE;
BL_ENDMASK1[15..0] :DFFE;
BL_ENDMASK2_CS :NODE;
BL_ENDMASK2[15..0] :DFFE;
BL_ENDMASK3_CS :NODE;
BL_ENDMASK3[15..0] :DFFE;
BL_SRC_ADRH_CS :NODE;
BL_SRC_ADRL_CS :NODE;
BL_SRC_ADR[31..0] :DFFE;
BL_DST_X_INC_CS :NODE;
BL_DST_X_INC[15..0] :DFFE;
BL_DST_Y_INC_CS :NODE;
BL_DST_Y_INC[15..0] :DFFE;
BL_DST_ADRH_CS :NODE;
BL_DST_ADRL_CS :NODE;
BL_DST_ADR[31..0] :DFFE;
BL_X_CNT_CS :NODE;
BL_X_CNT[15..0] :DFFE;
BL_Y_CNT_CS :NODE;
BL_Y_CNT[15..0] :DFFE;
BL_HT_OP_CS :NODE;
BL_HT_OP[7..0] :DFFE;
BL_LC_OP[7..0] :DFFE;
BL_LN_CS :NODE;
BL_LN[7..0] :DFFE;
BL_SKEW[7..0] :DFFE;
BL_SKEW_EXT[6..0] :NODE;
BL_SKEW_IN[255..0] :DFFE;
BL_SKEW_OUT[255..0] :NODE;
BL_DATA_DDR_READY :DFF; -- 1 WENN DATEN GESCHRIEBEN ODER LESBAR
BL_READ_SRC :DFFE;
BL_DST_BUFFER[127..0] :DFFE;
BL_READ_DST :DFFE;
HOP_OUT[127..0] :NODE;
COUNT[18..0] :DFF;
BEGIN
-- BYT SELECT 32 BIT
FB_B0 = FB_ADR[1..0]==0; -- ADR==0
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- BYT SELECT 16 BIT
FB_16B0 = FB_ADR[0]==0; -- ADR==0
FB_16B1 = FB_ADR[0]==1 -- ADR==1
# !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT
-- BLITTER CS
BLITTER_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..6]==H"3E28"; -- FFFF8A00-3F/40
BLITTER_TA = BLITTER_CS;
-- REGISTER
-- HALFTON RAM
BL_HRAM_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..5]==H"7C50"; -- $F8A00/20
BL_HRAM_BE1 = BL_HRAM_CS & FB_16B0 # !BL_HRAM_CS;
BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1 # !BL_HRAM_CS;
BL_HRAM_ADR[] = BL_HRAM_CS & FB_ADR[4..1]
# !BL_HRAM_CS & BL_LN[3..0];
BL_HRAM_OUT[] = altsyncram0(BL_HRAM_ADR[],BL_HRAM_BE[],DDRCLK0,FB_AD[31..16],BL_HRAM_CS & !nFB_WR);
-- SRC X INC
BL_SRC_X_INC[].CLK = MAIN_CLK;
BL_SRC_X_INC[] = !BL_BUSY & FB_AD[31..16];
BL_SRC_X_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C510"; -- $F8A20/2
BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_X_INC[7..0].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
-- SRC Y INC
BL_SRC_Y_INC[].CLK = MAIN_CLK;
BL_SRC_Y_INC[] = !BL_BUSY & FB_AD[31..16];
BL_SRC_Y_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C511"; -- $F8A22/2
BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_Y_INC[7..0].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
-- SRC ADR HIGH
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[31..16] = !BL_BUSY & FB_AD[31..16];
BL_SRC_ADRH_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C512"; -- $F8A24/2
BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
-- SRC ADR LOW
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[15..0] = !BL_BUSY & FB_AD[31..16];
BL_SRC_ADRL_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C513"; -- $F8A26/2
BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[7..0].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
-- ENDMASK 1
BL_ENDMASK1[].CLK = MAIN_CLK;
BL_ENDMASK1[] = FB_AD[31..16];
BL_ENDMASK1_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C514"; -- $F8A28/2
BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
BL_ENDMASK1[7..0].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
-- ENDMASK 2
BL_ENDMASK2[].CLK = MAIN_CLK;
BL_ENDMASK2[] = FB_AD[31..16];
BL_ENDMASK2_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C515"; -- $F8A2A/2
BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
BL_ENDMASK2[7..0].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
-- ENDMASK 3
BL_ENDMASK3[].CLK = MAIN_CLK;
BL_ENDMASK3[] = FB_AD[31..16];
BL_ENDMASK3_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C516"; -- $F8A2C/2
BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
BL_ENDMASK3[7..0].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
-- DST X INC
BL_DST_X_INC[].CLK = MAIN_CLK;
BL_DST_X_INC[] = !BL_BUSY & FB_AD[31..16];
BL_DST_X_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C517"; -- $F8A2E/2
BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
BL_DST_X_INC[7..0].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
-- DST Y INC
BL_DST_Y_INC[].CLK = MAIN_CLK;
BL_DST_Y_INC[] = !BL_BUSY & FB_AD[31..16];
BL_DST_Y_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C518"; -- $F8A30/2
BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
BL_DST_Y_INC[7..0].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
-- DST ADR HIGH
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[31..16] = !BL_BUSY & FB_AD[31..16];
BL_DST_ADRH_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C512"; -- $F8A24/2
BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
-- DST ADR LOW
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[15..0] = !BL_BUSY & FB_AD[31..16];
BL_DST_ADRL_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C513"; -- $F8A26/2
BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[7..0].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
-- X COUNT
BL_X_CNT[].CLK = MAIN_CLK;
BL_X_CNT[] = !BL_BUSY & FB_AD[31..16];
BL_X_CNT_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51B"; -- $F8A36/2
BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
BL_X_CNT[7..0].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B1;
-- Y COUNT
BL_Y_CNT[].CLK = MAIN_CLK;
BL_Y_CNT[] = !BL_BUSY & FB_AD[31..16];
BL_Y_CNT_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51C"; -- $F8A38/2
BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
BL_Y_CNT[7..0].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
-- HALFTONE OP BYT
BL_HT_OP[].CLK = MAIN_CLK;
BL_HT_OP[] = FB_AD[31..24];
BL_HT_OP_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51D"; -- $F8A3A/2
BL_HT_OP[7..0].ENA = BL_HT_OP_CS & !nFB_WR & FB_16B0;
-- LOGIC OP BYT
BL_LC_OP[].CLK = MAIN_CLK;
BL_LC_OP[] = FB_AD[23..16];
BL_LC_OP[7..0].ENA = BL_HT_OP_CS & !nFB_WR & FB_16B1; -- $F8A3B
-- LINE NUMBER BYT
BL_LN[].CLK = MAIN_CLK;
BL_LN[] = !BL_BUSY & FB_AD[31..24];
BL_LN_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51E"; -- $F8A3C/2
BL_LN[7..0].ENA = BL_LN_CS & !nFB_WR & FB_16B0;
-- SKEW BYT
BL_SKEW[].CLK = MAIN_CLK;
BL_SKEW[] = FB_AD[31..24];
BL_SKEW[7..0].ENA = BL_LN_CS & !nFB_WR & FB_16B1; -- $F8A3D
--- REGISTER OUT
FB_AD[31..16] = lpm_bustri_WORD(
BL_HRAM_CS & BL_HRAM_OUT[]
# BL_SRC_X_INC_CS & BL_SRC_X_INC[]
# BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
# BL_SRC_ADRH_CS & BL_SRC_ADR[31..16]
# BL_SRC_ADRL_CS & BL_SRC_ADR[15..0]
# BL_ENDMASK1_CS & BL_ENDMASK1[]
# BL_ENDMASK2_CS & BL_ENDMASK2[]
# BL_ENDMASK3_CS & BL_ENDMASK3[]
# BL_DST_X_INC_CS & BL_DST_X_INC[]
# BL_DST_Y_INC_CS & BL_DST_Y_INC[]
# BL_DST_ADRH_CS & BL_DST_ADR[31..16]
# BL_DST_ADRL_CS & BL_DST_ADR[15..0]
# BL_X_CNT_CS & BL_X_CNT[]
# BL_Y_CNT_CS & BL_Y_CNT[]
# BL_HT_OP_CS & (BL_HT_OP[],BL_LC_OP[])
# BL_LN_CS & (BL_LN[],BL_SKEW[])
,BLITTER_CS & !nFB_OE); -- FFFF8A00-3F/40
-----------------------------------------
--
BL_READ_SRC.CLK = DDRCLK0;
BL_READ_DST.CLK = DDRCLK0;
-- READY SIGNAL 1 CLOCK SP<53>TER
BL_DATA_DDR_READY.CLK = DDRCLK0;
BL_DATA_DDR_READY = BL_DATA_DDR_READY & BLITTER_DACK0;
-- SRC BUFFER LADEN
BL_SKEW_IN[].CLK = DDRCLK0;
BL_SKEW_IN[].ENA = BL_DATA_DDR_READY & BL_READ_SRC;
BL_SKEW_IN[255..128] = BLITTER_DIN[];
BL_SKEW_IN[127..0] = BL_SKEW_IN[255..128];
-- DST BUFFER LADEN
BL_DST_BUFFER[].CLK = DDRCLK0;
BL_DST_BUFFER[].ENA = BL_DATA_DDR_READY & BL_READ_DST;
BL_DST_BUFFER[] = BLITTER_DIN[];
-- SKEW EXTENDET
BL_SKEW_EXT[6..4] = BL_SRC_ADR[3..1];
BL_SKEW_EXT[3..0] = BL_SKEW[3..0];
-- SKEW EXT MUX
BL_SKEW_OUT[] = lpm_clshift0(BL_SKEW_IN[],BL_SKEW_EXT[]); -- BIT 127..0 SIND RELEVANT
-- HOP
IF BL_HT_OP[1..0]==B"00" THEN
HOP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
ELSE
IF BL_HT_OP[1..0]==B"01" THEN
HOP_OUT[] = (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]);
ELSE
IF BL_HT_OP[1..0]==B"10" THEN
HOP_OUT[] = BL_SKEW_OUT[127..0];
ELSE
HOP_OUT[] = BL_SKEW_OUT[127..0] & (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]);
END IF;
END IF;
END IF;
BLITTER_RUN = gnd; --VCC;
BLITTER_SIG = gnd; --VCC;
BLITTER_WR = gnd; --VCC;
COUNT[] = COUNT[] + 16;
COUNT[].CLK = BLITTER_DACK0;
BLITTER_DOUT[] = H"112233445566778899AABBCCDDEEFF00";
BLITTER_ADR[] = (0, COUNT[]) + 400000;
END;

BIN
FPGA_by_Fredi/DSP/dsp56k.zip
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319
FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
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@@ -115,7 +115,7 @@ ENTITY FalconIO_SDCard_IDE_CF IS
nCF_CS0 : OUT STD_LOGIC;
nIDE_RD : INOUT STD_LOGIC;
nIDE_WR : INOUT STD_LOGIC;
AMKB_TX : OUT STD_LOGIC;
AMKB_TX : buffer STD_LOGIC;
IDE_RES : OUT STD_LOGIC;
DTR : OUT STD_LOGIC;
RTS : OUT STD_LOGIC;
@@ -132,6 +132,7 @@ ENTITY FalconIO_SDCard_IDE_CF IS
DMA_DRQ : OUT STD_LOGIC;
FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
SND_A : INOUT STD_LOGIC_VECTOR(7 downto 0);
ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
SCSI_PAR : INOUT STD_LOGIC;
@@ -156,12 +157,15 @@ signal FB_B0 : STD_LOGIC; -- UPPER BYT BEI 16BIT BUS
signal FB_B1 : STD_LOGIC; -- LOWER BYT BEI 16BIT BUS
signal BYT : STD_LOGIC; -- WENN BYT -> 1
signal LONG : STD_LOGIC; -- WENN -> 1
signal FB_ADI : STD_LOGIC_VECTOR(15 downto 0); -- gespeicherte writedaten
signal nResetatio : STD_LOGIC; -- reset atari bausteine
-- KEYBOARD MIDI
signal ACIA_CS_I : STD_LOGIC;
signal IRQ_KEYBDn : STD_LOGIC;
signal IRQ_MIDIn : STD_LOGIC;
signal KEYB_RxD : STD_LOGIC;
signal AMKB_REG : STD_LOGIC_VECTOR(4 downto 0);
signal AMKB_REG : STD_LOGIC_VECTOR(3 downto 0);
signal AMKB_TX_sync : std_logic;
signal MIDI_OUT : STD_LOGIC;
signal DATA_OUT_ACIA_I : STD_LOGIC_VECTOR(7 downto 0);
signal DATA_OUT_ACIA_II : STD_LOGIC_VECTOR(7 downto 0);
@@ -169,8 +173,8 @@ signal DATA_OUT_ACIA_II : STD_LOGIC_VECTOR(7 downto 0);
signal MFP_CS : STD_LOGIC;
signal MFP_INTACK : STD_LOGIC;
signal LDS : STD_LOGIC;
signal acia_irq : STD_LOGIC;
signal DTACK_OUT_MFPn : STD_LOGIC;
signal IRQ_ACIAn : STD_LOGIC;
signal DINTn : STD_LOGIC;
signal DATA_OUT_MFP : STD_LOGIC_VECTOR(7 downto 0);
signal TDO : STD_LOGIC;
@@ -180,7 +184,22 @@ signal SNDCS_I : STD_LOGIC;
signal SNDIR_I : STD_LOGIC;
signal LP_DIR_X : STD_LOGIC;
signal DA_OUT_X : STD_LOGIC_VECTOR(7 downto 0);
signal SND_A_X : STD_LOGIC_VECTOR(7 downto 0);
signal LP_D_X : STD_LOGIC_VECTOR(7 downto 0);
signal nLP_STR : STD_LOGIC;
-- DMA SOUND
signal dma_snd_cs : STD_LOGIC;
signal sndmactl : STD_LOGIC_VECTOR(7 downto 0);
signal sndbashi : STD_LOGIC_VECTOR(7 downto 0);
signal sndbasmi : STD_LOGIC_VECTOR(7 downto 0);
signal sndbaslo : STD_LOGIC_VECTOR(7 downto 0);
signal sndadrhi : STD_LOGIC_VECTOR(7 downto 0);
signal sndadrmi : STD_LOGIC_VECTOR(7 downto 0);
signal sndadrlo : STD_LOGIC_VECTOR(7 downto 0);
signal sndendhi : STD_LOGIC_VECTOR(7 downto 0);
signal sndendmi : STD_LOGIC_VECTOR(7 downto 0);
signal sndendlo : STD_LOGIC_VECTOR(7 downto 0);
signal sndmode : STD_LOGIC_VECTOR(7 downto 0);
-- DIV
signal SUB_BUS : STD_LOGIC; -- SUB BUS MIT ROM-PORT, CF UND IDE
signal ROM_CS : STD_LOGIC;
@@ -265,22 +284,36 @@ signal NEXT_nIDE_WR : STD_LOGIC;
type CMD_STATES is( IDLE, T1, T6, T7);
signal CMD_STATE : CMD_STATES;
signal NEXT_CMD_STATE : CMD_STATES;
-- Paddle
signal paddle_cs : STD_LOGIC;
BEGIN
LONG <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else '0';
BYT <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0';
FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0';
FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0';
FALCON_IO_TA <= '1' when SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1'
or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';
SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE
FALCON_IO_TA <= '1' when ACIA_CS_I = '1' or DTACK_OUT_MFPn = '0' or DMA_MODUS_CS ='1' or dma_snd_cs = '1' or paddle_cs = '1'
or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';--SNDCS = '1' or
SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE
'1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE
'1' when nFB_WR = '0' and nIDE_WR = '0' ELSE '0';
nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1';
nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1';
nRP_UDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B0 = '1' else '1';
nRP_LDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B1 = '1' else '1';
nDREQ0 <= '0';
-- input daten halten
process(MAIN_CLK, nFB_WR, FB_AD(31 downto 16), FB_ADI(15 downto 0))
begin
if rising_edge(MAIN_CLK) then
IF nFB_WR = '0' THEN
FB_ADI <= FB_AD(31 downto 16);
ELSE
FB_ADI <= FB_ADI;
end if;
ELSE
FB_ADI <= FB_ADI;
end if;
END PROCESS;
----------------------------------------------------------------------------
-- SD
----------------------------------------------------------------------------
@@ -386,7 +419,7 @@ RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT;
q => WRF_DOUT,
rdusedw => WRF_AZ
);
CD_IN_FDC <= WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_AD(23 downto 16); -- BEI DMA WRITE <-FIFO SONST <-FB
CD_IN_FDC <= WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_ADI(7 downto 0); -- BEI DMA WRITE <-FIFO SONST <-FB
DMA_AZ_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"002010C" else '0'; -- F002'010C LONG
FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ when DMA_AZ_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
DMA_DRQ_Q <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0';
@@ -513,7 +546,7 @@ SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_
I_FDC: WF1772IP_TOP_SOC
port map(
CLK => FDC_CLK,
RESETn => nRSTO,
RESETn => nResetatio,
CSn => FDCS_In,
RWn => nFDC_WR,
A1 => CA2,
@@ -695,13 +728,13 @@ CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD;
I_SCSI: WF5380_TOP_SOC
port map(
CLK => FDC_CLK,
RESETn => nRSTO,
RESETn => nResetatio,
ADR => CA2 & CA1 & CA0,
DATA_IN => CD_IN_FDC,
DATA_OUT => SCSI_DOUT,
--DATA_EN : out bit;
-- Bus and DMA controls:
CSn => '1', --SCSI_CSn, ABGESCHALTET
CSn => SCSI_CSn,
RDn => (not nFDC_WR) or (not SCSI_CS),
WRn => nFDC_WR or (not SCSI_CS),
EOPn => '1',
@@ -745,18 +778,19 @@ CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD;
-- MSG_EN => MSG_EN
);
-- SCSI ACSI ---------------------------------------------------------------
SCSI_D <= DB_OUTn when DB_EN = '1' else "ZZZZZZZZ";
SCSI_DIR <= '1'; --'0' when DB_EN = '1' else '1'; --ABGESCHALTET
SCSI_D <= "ZZZZZZZZ";--DB_OUTn when DB_EN = '1' else "ZZZZZZZZ";
SCSI_DIR <= '1';-- when DB_EN = '1' else '1';
SCSI_PAR <= DBP_OUTn when DBP_EN = '1' else 'Z';
nSCSI_RST <= RST_OUTn when RST_EN = '1' else 'Z';
nSCSI_BUSY <= BSY_OUTn when BSY_EN = '1' else 'Z';
nSCSI_SEL <= SEL_OUTn when SEL_EN = '1' else 'Z';
nSCSI_RST <= 'Z';--RST_OUTn when RST_EN = '1' else 'Z';
nSCSI_BUSY <= 'Z';--BSY_OUTn when BSY_EN = '1' else 'Z';
nSCSI_SEL <= 'Z';--SEL_OUTn when SEL_EN = '1' else 'Z';
ACSI_DIR <= '0';
ACSI_D <= "ZZZZZZZZ";
nACSI_CS <= '1';
ACSI_A1 <= CA1;
nACSI_RESET <= nRSTO;
nACSI_ACK <= '1';
nResetatio <= '0' when nRSTO = '0' or ACP_CONF(24) = '1' else '1';
----------------------------------------------------------------------------
-- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns
----------------------------------------------------------------------------
@@ -769,16 +803,16 @@ nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1';
I_ACIA_KEYBOARD: WF6850IP_TOP_SOC
port map(
CLK => MAIN_CLK,
RESETn => nRSTO,
RESETn => nResetatio,
CS2n => FB_ADR(2),
CS1 => '1',
CS0 => ACIA_CS_I,
E => ACIA_CS_I,
E => ACIA_CS_I,
RWn => nFB_WR,
RS => FB_ADR(1),
DATA_IN => FB_AD(31 downto 24),
DATA_IN => FB_ADI(15 downto 8),
DATA_OUT => DATA_OUT_ACIA_I,
-- DATA_EN => DATA_EN_ACIA_I,
@@ -790,40 +824,45 @@ nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1';
DCDn => '0',
IRQn => IRQ_KEYBDn,
TXDATA => AMKB_TX
TXDATA => AMKB_TX_sync
--RTSn => -- Not used.
);
ACIA_CS_I <= '1' when nFB_CS1 = '0'and FB_ADR(19 downto 3) = x"1FF80" else '0'; -- FFC00-FFC07 FFC00/8
KEYB_RxD <= '1' when AMKB_REG(3) = '1' or PIC_AMKB_RX = '0' else '0'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL
FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else "ZZZZZZZZ";
-- AMKB_TX: SPIKES AUSFILTERN ------------------------------------------
KEYB_RxD <= '0' when AMKB_REG(3) = '0' or PIC_AMKB_RX = '0' else '1'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL //
FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else
DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
-- AMKB_TX: SPIKES AUSFILTERN und sychronisieren ------------------------------------------
process(CLK2M, AMKB_RX, AMKB_REG)
begin
if rising_edge(CLK2M) then
if rising_edge(CLK500k) then
AMKB_TX <= AMKB_TX_sync;
IF AMKB_RX = '0' THEN
IF AMKB_REG < 16 THEN
AMKB_REG <= "00000";
IF AMKB_REG < 8 THEN
AMKB_REG <= "0000";
ELSE
AMKB_REG <= AMKB_REG - 1;
END IF;
ELSE
IF AMKB_REG > 15 THEN
AMKB_REG <= "11111";
IF AMKB_REG > 7 THEN
AMKB_REG <= "1111";
ELSE
AMKB_REG <= AMKB_REG + 1;
END IF;
END IF;
ELSE
AMKB_TX <= AMKB_TX;
AMKB_REG <= AMKB_REG;
end if;
END PROCESS;
-- acia interrupt ------------------------------------------
acia_irq <= '0' when IRQ_KEYBDn = '0' or IRQ_MIDIn = '0' else '1';
----------------------------------------------------------------------------
-- ACIA MIDI
----------------------------------------------------------------------------
I_ACIA_MIDI: WF6850IP_TOP_SOC
port map(
CLK => MAIN_CLK,
RESETn => nRSTO,
RESETn => nResetatio,
CS2n => '0',
CS1 => FB_ADR(2),
@@ -832,7 +871,7 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0'
RWn => nFB_WR,
RS => FB_ADR(1),
DATA_IN => FB_AD(31 downto 24),
DATA_IN => FB_ADI(15 downto 8),
DATA_OUT => DATA_OUT_ACIA_II,
-- DATA_EN => DATA_EN_ACIA_II,
@@ -845,18 +884,17 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0'
IRQn => IRQ_MIDIn,
TXDATA => MIDI_OUT
--RTSn => -- Not used.
);
MIDI_TLR <= MIDI_OUT;
);
MIDI_TLR <= MIDI_IN;
MIDI_OLR <= MIDI_OUT;
FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
----------------------------------------------------------------------------
-- MFP
----------------------------------------------------------------------------
I_MFP: WF68901IP_TOP_SOC
port map(
-- System control:
CLK => MAIN_CLK,
RESETn => nRSTO,
CLK => not MAIN_CLK,
RESETn => nResetatio,
-- Asynchronous bus control:
DSn => not LDS,
CSn => not MFP_CS,
@@ -867,14 +905,14 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1'
DATA_IN => FB_AD(23 downto 16),
DATA_OUT => DATA_OUT_MFP,
-- DATA_EN => DATA_EN_MFP,
GPIP_IN(7) => not DMA_DRQ_Q,
GPIP_IN(6) => not RI,
GPIP_IN(7) => not DMA_DRQ_Q,
GPIP_IN(6) => not RI,
GPIP_IN(5) => DINTn,
GPIP_IN(4) => IRQ_ACIAn,
GPIP_IN(4) => acia_irq,
GPIP_IN(3) => DSP_INT,
GPIP_IN(2) => not CTS,
GPIP_IN(1) => not DCD,
GPIP_IN(0) => LP_BUSY,
GPIP_IN(2) => not CTS,
GPIP_IN(1) => not DCD,
GPIP_IN(0) => LP_BUSY,
-- GPIP_OUT =>, -- Not used; all GPIPs are direction input.
-- GPIP_EN =>, -- Not used; all GPIPs are direction input.
-- Interrupt control:
@@ -885,7 +923,7 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1'
-- Timers and timer control:
XTAL1 => CLK2M4576,
TAI => '0',
TBI => nBLANK,
TBI => nBLANK,
-- TAO =>,
-- TBO =>,
-- TCO =>,
@@ -911,24 +949,13 @@ FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ";
DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else
'0' when FDINT = '1' else
'0' when SCSI_INT = '1' AND ACP_CONF(28) = '1' else '1';
-- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN ------------------------------------------
process(MAIN_CLK,nRSTO,IRQ_ACIAn,IRQ_KEYBDn,IRQ_MIDIn)
begin
if nRSTO = '0' THEN
IRQ_ACIAn <= '1';
elsif rising_edge(MAIN_CLK) then
IRQ_ACIAn <= IRQ_KEYBDn and IRQ_MIDIn;
else
IRQ_ACIAn <= IRQ_ACIAn;
end if;
END PROCESS;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Sound
----------------------------------------------------------------------------
I_SOUND: WF2149IP_TOP_SOC
port map(
SYS_CLK => MAIN_CLK,
RESETn => nRSTO,
SYS_CLK => not MAIN_CLK,
RESETn => nResetatio,
WAV_CLK => CLK2M,
SELn => '1',
@@ -939,18 +966,11 @@ DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else
A9n => '0',
A8 => '1',
DA_IN => FB_AD(31 downto 24),
DA_IN => FB_ADI(15 downto 8),
DA_OUT => DA_OUT_X,
IO_A_IN => x"00", -- All port pins are dedicated outputs.
IO_A_OUT(7) => nnIDE_RES,
IO_A_OUT(6) => LP_DIR_X,
IO_A_OUT(5) => LP_STR,
IO_A_OUT(4) => DTR,
IO_A_OUT(3) => RTS,
-- IO_A_OUT(2) => FDD_D1SEL,
IO_A_OUT(1) => DSA_D,
IO_A_OUT(0) => nSDSEL,
IO_A_IN => SND_A,
IO_A_OUT => SND_A_X,
-- IO_A_EN =>, -- Not required.
IO_B_IN => LP_D,
IO_B_OUT => LP_D_X,
@@ -965,7 +985,170 @@ SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0'; --
SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0';
SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0';
FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ";
nnIDE_RES <= SND_A_X(7);
LP_DIR_X <= SND_A_X(6);
LP_STR <= SND_A_X(5);
DTR <= SND_A_X(4);
RTS <= SND_A_X(3);
-- FDD_D1SEL <= SND_A_X(2)
DSA_D <= SND_A_X(1);
nSDSEL <= SND_A_X(0);
SND_A <= SND_A_X;
LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ";
LP_DIR <= LP_DIR_X;
----------------------------------------------------------------------------
-- DMA Sound register
----------------------------------------------------------------------------
dma_snd_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3E24" else '0'; -- F8900-F893F
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
begin
if nRSTO = '0' THEN
sndmactl <= x"00";
elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_WR = '0' and FB_B1 ='1' then
sndmactl <= FB_AD(23 downto 16);
else
sndmactl <= sndmactl;
end if;
END PROCESS;
FB_AD(23 downto 16) <= sndmactl when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_OE = '0' else "ZZZZZZZZ";
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
begin
if nRSTO = '0' THEN
sndbashi <= x"00";
elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"1" and nFB_WR = '0' and FB_B1 ='1' then
sndbashi <= FB_AD(23 downto 16);
else
sndbashi <= sndbashi;
end if;
END PROCESS;
FB_AD(23 downto 16) <= sndbashi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"1" and nFB_OE = '0' else "ZZZZZZZZ";
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
begin
if nRSTO = '0' THEN
sndbasmi <= x"00";
elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"2" and nFB_WR = '0' and FB_B1 ='1' then
sndbasmi <= FB_AD(23downto 16);
else
sndbasmi <= sndbasmi;
end if;
END PROCESS;
FB_AD(23 downto 16) <= sndbasmi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"2" and nFB_OE = '0' else "ZZZZZZZZ";
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
begin
if nRSTO = '0' THEN
sndbaslo <= x"00";
elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"3" and nFB_WR = '0' and FB_B1 ='1' then
sndbaslo <= FB_AD(23 downto 16);
else
sndbaslo <= sndbaslo;
end if;
END PROCESS;
FB_AD(23 downto 16) <= sndbaslo when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"3" and nFB_OE = '0' else "ZZZZZZZZ";
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
begin
if nRSTO = '0' THEN
sndadrhi <= x"00";
elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"4" and nFB_WR = '0' and FB_B1 ='1' then
sndadrhi <= FB_AD(23 downto 16);
else
sndadrhi <= sndadrhi;
end if;
END PROCESS;
FB_AD(23 downto 16) <= sndadrhi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"4" and nFB_OE = '0' else "ZZZZZZZZ";
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
begin
if nRSTO = '0' THEN
sndadrmi <= x"00";
elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"5" and nFB_WR = '0' and FB_B1 ='1' then
sndadrmi <= FB_AD(23 downto 16);
else
sndadrmi <= sndadrmi;
end if;
END PROCESS;
FB_AD(23 downto 16) <= sndadrmi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"5" and nFB_OE = '0' else "ZZZZZZZZ";
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
begin
if nRSTO = '0' THEN
sndadrlo <= x"00";
elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"6" and nFB_WR = '0' and FB_B1 ='1' then
sndadrlo <= FB_AD(23 downto 16);
else
sndadrlo <= sndadrlo;
end if;
END PROCESS;
FB_AD(23 downto 16) <= sndadrlo when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"6" and nFB_OE = '0' else "ZZZZZZZZ";
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
begin
if nRSTO = '0' THEN
sndendhi <= x"00";
elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"7" and nFB_WR = '0' and FB_B1 ='1' then
sndendhi <= FB_AD(23 downto 16);
else
sndendhi <= sndendhi;
end if;
END PROCESS;
FB_AD(23 downto 16) <= sndendhi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"7" and nFB_OE = '0' else "ZZZZZZZZ";
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
begin
if nRSTO = '0' THEN
sndendmi <= x"00";
elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"8" and nFB_WR = '0' and FB_B1 ='1' then
sndendmi <= FB_AD(23 downto 16);
else
sndendmi <= sndendmi;
end if;
END PROCESS;
FB_AD(23 downto 16) <= sndendmi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"8" and nFB_OE = '0' else "ZZZZZZZZ";
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
begin
if nRSTO = '0' THEN
sndendlo <= x"00";
elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"9" and nFB_WR = '0' and FB_B1 ='1' then
sndendlo <= FB_AD(23 downto 16);
else
sndendlo <= sndendlo;
end if;
END PROCESS;
FB_AD(23 downto 16) <= sndendlo when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"9" and nFB_OE = '0' else "ZZZZZZZZ";
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
begin
if nRSTO = '0' THEN
sndmode <= x"00";
elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"10" and nFB_WR = '0' and FB_B1 ='1' then
sndmode <= FB_AD(23 downto 16);
else
sndmode <= sndmode;
end if;
END PROCESS;
FB_AD(23 downto 16) <= sndmode when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"10" and nFB_OE = '0' else "ZZZZZZZZ";
----------------------------------------------------------------------------
-- Paddle
----------------------------------------------------------------------------
paddle_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3E48" else '0'; -- F9200-F923F
FB_AD(31 downto 16) <= x"bfff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"1" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"8" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"9" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"A" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"B" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= x"0000" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"10" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= x"0000" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"11" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
END FalconIO_SDCard_IDE_CF_architecture;

322
FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak
View File

@@ -115,7 +115,7 @@ ENTITY FalconIO_SDCard_IDE_CF IS
nCF_CS0 : OUT STD_LOGIC;
nIDE_RD : INOUT STD_LOGIC;
nIDE_WR : INOUT STD_LOGIC;
AMKB_TX : OUT STD_LOGIC;
AMKB_TX : buffer STD_LOGIC;
IDE_RES : OUT STD_LOGIC;
DTR : OUT STD_LOGIC;
RTS : OUT STD_LOGIC;
@@ -132,6 +132,7 @@ ENTITY FalconIO_SDCard_IDE_CF IS
DMA_DRQ : OUT STD_LOGIC;
FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
SND_A : INOUT STD_LOGIC_VECTOR(7 downto 0);
ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
SCSI_PAR : INOUT STD_LOGIC;
@@ -156,12 +157,15 @@ signal FB_B0 : STD_LOGIC; -- UPPER BYT BEI 16BIT BUS
signal FB_B1 : STD_LOGIC; -- LOWER BYT BEI 16BIT BUS
signal BYT : STD_LOGIC; -- WENN BYT -> 1
signal LONG : STD_LOGIC; -- WENN -> 1
signal FB_ADI : STD_LOGIC_VECTOR(15 downto 0); -- gespeicherte writedaten
signal nResetatio : STD_LOGIC; -- reset atari bausteine
-- KEYBOARD MIDI
signal ACIA_CS_I : STD_LOGIC;
signal IRQ_KEYBDn : STD_LOGIC;
signal IRQ_MIDIn : STD_LOGIC;
signal KEYB_RxD : STD_LOGIC;
signal AMKB_REG : STD_LOGIC_VECTOR(4 downto 0);
signal AMKB_REG : STD_LOGIC_VECTOR(3 downto 0);
signal AMKB_TX_sync : std_logic;
signal MIDI_OUT : STD_LOGIC;
signal DATA_OUT_ACIA_I : STD_LOGIC_VECTOR(7 downto 0);
signal DATA_OUT_ACIA_II : STD_LOGIC_VECTOR(7 downto 0);
@@ -169,8 +173,8 @@ signal DATA_OUT_ACIA_II : STD_LOGIC_VECTOR(7 downto 0);
signal MFP_CS : STD_LOGIC;
signal MFP_INTACK : STD_LOGIC;
signal LDS : STD_LOGIC;
signal acia_irq : STD_LOGIC;
signal DTACK_OUT_MFPn : STD_LOGIC;
signal IRQ_ACIAn : STD_LOGIC;
signal DINTn : STD_LOGIC;
signal DATA_OUT_MFP : STD_LOGIC_VECTOR(7 downto 0);
signal TDO : STD_LOGIC;
@@ -180,7 +184,22 @@ signal SNDCS_I : STD_LOGIC;
signal SNDIR_I : STD_LOGIC;
signal LP_DIR_X : STD_LOGIC;
signal DA_OUT_X : STD_LOGIC_VECTOR(7 downto 0);
signal SND_A_X : STD_LOGIC_VECTOR(7 downto 0);
signal LP_D_X : STD_LOGIC_VECTOR(7 downto 0);
signal nLP_STR : STD_LOGIC;
-- DMA SOUND
signal dma_snd_cs : STD_LOGIC;
signal sndmactl : STD_LOGIC_VECTOR(7 downto 0);
signal sndbashi : STD_LOGIC_VECTOR(7 downto 0);
signal sndbasmi : STD_LOGIC_VECTOR(7 downto 0);
signal sndbaslo : STD_LOGIC_VECTOR(7 downto 0);
signal sndadrhi : STD_LOGIC_VECTOR(7 downto 0);
signal sndadrmi : STD_LOGIC_VECTOR(7 downto 0);
signal sndadrlo : STD_LOGIC_VECTOR(7 downto 0);
signal sndendhi : STD_LOGIC_VECTOR(7 downto 0);
signal sndendmi : STD_LOGIC_VECTOR(7 downto 0);
signal sndendlo : STD_LOGIC_VECTOR(7 downto 0);
signal sndmode : STD_LOGIC_VECTOR(7 downto 0);
-- DIV
signal SUB_BUS : STD_LOGIC; -- SUB BUS MIT ROM-PORT, CF UND IDE
signal ROM_CS : STD_LOGIC;
@@ -265,22 +284,36 @@ signal NEXT_nIDE_WR : STD_LOGIC;
type CMD_STATES is( IDLE, T1, T6, T7);
signal CMD_STATE : CMD_STATES;
signal NEXT_CMD_STATE : CMD_STATES;
-- Paddle
signal paddle_cs : STD_LOGIC;
BEGIN
LONG <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else '0';
BYT <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0';
FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0';
FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0';
FALCON_IO_TA <= '1' when SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1'
or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';
SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE
FALCON_IO_TA <= '1' when ACIA_CS_I = '1' or DTACK_OUT_MFPn = '0' or DMA_MODUS_CS ='1' or dma_snd_cs = '1' or paddle_cs = '1'
or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';--SNDCS = '1' or
SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE
'1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE
'1' when nFB_WR = '0' and nIDE_WR = '0' ELSE '0';
nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1';
nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1';
nRP_UDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B0 = '1' else '1';
nRP_LDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B1 = '1' else '1';
nDREQ0 <= '0';
-- input daten halten
process(MAIN_CLK, nFB_WR, FB_AD(31 downto 16), FB_ADI(15 downto 0))
begin
if rising_edge(MAIN_CLK) then
IF nFB_WR = '0' THEN
FB_ADI <= FB_AD(31 downto 16);
ELSE
FB_ADI <= FB_ADI;
end if;
ELSE
FB_ADI <= FB_ADI;
end if;
END PROCESS;
----------------------------------------------------------------------------
-- SD
----------------------------------------------------------------------------
@@ -386,7 +419,7 @@ RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT;
q => WRF_DOUT,
rdusedw => WRF_AZ
);
CD_IN_FDC <= WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_AD(23 downto 16); -- BEI DMA WRITE <-FIFO SONST <-FB
CD_IN_FDC <= WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_ADI(7 downto 0); -- BEI DMA WRITE <-FIFO SONST <-FB
DMA_AZ_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"002010C" else '0'; -- F002'010C LONG
FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ when DMA_AZ_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
DMA_DRQ_Q <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0';
@@ -513,7 +546,7 @@ SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_
I_FDC: WF1772IP_TOP_SOC
port map(
CLK => FDC_CLK,
RESETn => nRSTO,
RESETn => nResetatio,
CSn => FDCS_In,
RWn => nFDC_WR,
A1 => CA2,
@@ -695,13 +728,13 @@ CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD;
I_SCSI: WF5380_TOP_SOC
port map(
CLK => FDC_CLK,
RESETn => nRSTO,
RESETn => nResetatio,
ADR => CA2 & CA1 & CA0,
DATA_IN => CD_IN_FDC,
DATA_OUT => SCSI_DOUT,
--DATA_EN : out bit;
-- Bus and DMA controls:
CSn => '1', --SCSI_CSn, ABGESCHALTET
CSn => SCSI_CSn,
RDn => (not nFDC_WR) or (not SCSI_CS),
WRn => nFDC_WR or (not SCSI_CS),
EOPn => '1',
@@ -745,18 +778,19 @@ CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD;
-- MSG_EN => MSG_EN
);
-- SCSI ACSI ---------------------------------------------------------------
SCSI_D <= DB_OUTn when DB_EN = '1' else "ZZZZZZZZ";
SCSI_DIR <= '1'; --'0' when DB_EN = '1' else '1'; --ABGESCHALTET
SCSI_D <= "ZZZZZZZZ";--DB_OUTn when DB_EN = '1' else "ZZZZZZZZ";
SCSI_DIR <= '1';-- when DB_EN = '1' else '1';
SCSI_PAR <= DBP_OUTn when DBP_EN = '1' else 'Z';
nSCSI_RST <= RST_OUTn when RST_EN = '1' else 'Z';
nSCSI_BUSY <= BSY_OUTn when BSY_EN = '1' else 'Z';
nSCSI_SEL <= SEL_OUTn when SEL_EN = '1' else 'Z';
nSCSI_RST <= 'Z';--RST_OUTn when RST_EN = '1' else 'Z';
nSCSI_BUSY <= 'Z';--BSY_OUTn when BSY_EN = '1' else 'Z';
nSCSI_SEL <= 'Z';--SEL_OUTn when SEL_EN = '1' else 'Z';
ACSI_DIR <= '0';
ACSI_D <= "ZZZZZZZZ";
nACSI_CS <= '1';
ACSI_A1 <= CA1;
nACSI_RESET <= nRSTO;
nACSI_ACK <= '1';
nResetatio <= '0' when nRSTO = '0' or ACP_CONF(24) = '1' else '1';
----------------------------------------------------------------------------
-- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns
----------------------------------------------------------------------------
@@ -769,16 +803,16 @@ nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1';
I_ACIA_KEYBOARD: WF6850IP_TOP_SOC
port map(
CLK => MAIN_CLK,
RESETn => nRSTO,
RESETn => nResetatio,
CS2n => FB_ADR(2),
CS1 => '1',
CS0 => ACIA_CS_I,
E => ACIA_CS_I,
E => ACIA_CS_I,
RWn => nFB_WR,
RS => FB_ADR(1),
DATA_IN => FB_AD(31 downto 24),
DATA_IN => FB_ADI(15 downto 8),
DATA_OUT => DATA_OUT_ACIA_I,
-- DATA_EN => DATA_EN_ACIA_I,
@@ -790,40 +824,45 @@ nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1';
DCDn => '0',
IRQn => IRQ_KEYBDn,
TXDATA => AMKB_TX
TXDATA => AMKB_TX_sync
--RTSn => -- Not used.
);
ACIA_CS_I <= '1' when nFB_CS1 = '0'and FB_ADR(19 downto 3) = x"1FF80" else '0'; -- FFC00-FFC07 FFC00/8
KEYB_RxD <= '1' when AMKB_REG(3) = '1' or PIC_AMKB_RX = '0' else '0'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL
FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else "ZZZZZZZZ";
-- AMKB_TX: SPIKES AUSFILTERN ------------------------------------------
KEYB_RxD <= '0' when AMKB_REG(3) = '0' or PIC_AMKB_RX = '0' else '1'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL //
FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else
DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
-- AMKB_TX: SPIKES AUSFILTERN und sychronisieren ------------------------------------------
process(CLK2M, AMKB_RX, AMKB_REG)
begin
if rising_edge(CLK2M) then
if rising_edge(CLK500k) then
AMKB_TX <= AMKB_TX_sync;
IF AMKB_RX = '0' THEN
IF AMKB_REG < 16 THEN
AMKB_REG <= "00000";
IF AMKB_REG < 8 THEN
AMKB_REG <= "0000";
ELSE
AMKB_REG <= AMKB_REG - 1;
END IF;
ELSE
IF AMKB_REG > 15 THEN
AMKB_REG <= "11111";
IF AMKB_REG > 7 THEN
AMKB_REG <= "1111";
ELSE
AMKB_REG <= AMKB_REG + 1;
END IF;
END IF;
ELSE
AMKB_TX <= AMKB_TX;
AMKB_REG <= AMKB_REG;
end if;
END PROCESS;
-- acia interrupt ------------------------------------------
acia_irq <= '0' when IRQ_KEYBDn = '0' or IRQ_MIDIn = '0' else '1';
----------------------------------------------------------------------------
-- ACIA MIDI
----------------------------------------------------------------------------
I_ACIA_MIDI: WF6850IP_TOP_SOC
port map(
CLK => MAIN_CLK,
RESETn => nRSTO,
RESETn => nResetatio,
CS2n => '0',
CS1 => FB_ADR(2),
@@ -832,7 +871,7 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0'
RWn => nFB_WR,
RS => FB_ADR(1),
DATA_IN => FB_AD(31 downto 24),
DATA_IN => FB_ADI(15 downto 8),
DATA_OUT => DATA_OUT_ACIA_II,
-- DATA_EN => DATA_EN_ACIA_II,
@@ -845,18 +884,17 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0'
IRQn => IRQ_MIDIn,
TXDATA => MIDI_OUT
--RTSn => -- Not used.
);
MIDI_TLR <= MIDI_OUT;
);
MIDI_TLR <= MIDI_IN;
MIDI_OLR <= MIDI_OUT;
FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
----------------------------------------------------------------------------
-- MFP
----------------------------------------------------------------------------
I_MFP: WF68901IP_TOP_SOC
port map(
-- System control:
CLK => MAIN_CLK,
RESETn => nRSTO,
CLK => not MAIN_CLK,
RESETn => nResetatio,
-- Asynchronous bus control:
DSn => not LDS,
CSn => not MFP_CS,
@@ -867,14 +905,14 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1'
DATA_IN => FB_AD(23 downto 16),
DATA_OUT => DATA_OUT_MFP,
-- DATA_EN => DATA_EN_MFP,
GPIP_IN(7) => not DMA_DRQ_Q,
GPIP_IN(6) => not RI,
GPIP_IN(7) => not DMA_DRQ_Q,
GPIP_IN(6) => not RI,
GPIP_IN(5) => DINTn,
GPIP_IN(4) => IRQ_ACIAn,
GPIP_IN(4) => acia_irq,
GPIP_IN(3) => DSP_INT,
GPIP_IN(2) => not CTS,
GPIP_IN(1) => not DCD,
GPIP_IN(0) => LP_BUSY,
GPIP_IN(2) => not CTS,
GPIP_IN(1) => not DCD,
GPIP_IN(0) => LP_BUSY,
-- GPIP_OUT =>, -- Not used; all GPIPs are direction input.
-- GPIP_EN =>, -- Not used; all GPIPs are direction input.
-- Interrupt control:
@@ -885,7 +923,7 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1'
-- Timers and timer control:
XTAL1 => CLK2M4576,
TAI => '0',
TBI => nBLANK,
TBI => nBLANK,
-- TAO =>,
-- TBO =>,
-- TCO =>,
@@ -908,27 +946,16 @@ FB_AD(23 downto 16) <= DATA_OUT_MFP when MFP_CS = '1' and nFB_OE = '0' else "ZZZ
FB_AD(31 downto 10) <= "0000000000000000000000" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZ";
FB_AD(9 downto 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZ";
FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ";
DINTn <= '0' when IDE_INT = '1' AND ACP_CONFIG[28] = '1' else
DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else
'0' when FDINT = '1' else
'0' when SCSI_INT = '1' AND ACP_CONFIG[28] = '1' else '1';
-- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN ------------------------------------------
process(MAIN_CLK,nRSTO,IRQ_ACIAn,IRQ_KEYBDn,IRQ_MIDIn)
begin
if nRSTO = '0' THEN
IRQ_ACIAn <= '1';
elsif rising_edge(MAIN_CLK) then
IRQ_ACIAn <= IRQ_KEYBDn and IRQ_MIDIn;
else
IRQ_ACIAn <= IRQ_ACIAn;
end if;
END PROCESS;
----------------------------------------------------------------------------
'0' when SCSI_INT = '1' AND ACP_CONF(28) = '1' else '1';
----------------------------------------------------------------------------
-- Sound
----------------------------------------------------------------------------
I_SOUND: WF2149IP_TOP_SOC
port map(
SYS_CLK => MAIN_CLK,
RESETn => nRSTO,
SYS_CLK => not MAIN_CLK,
RESETn => nResetatio,
WAV_CLK => CLK2M,
SELn => '1',
@@ -939,18 +966,11 @@ DINTn <= '0' when IDE_INT = '1' AND ACP_CONFIG[28] = '1' else
A9n => '0',
A8 => '1',
DA_IN => FB_AD(31 downto 24),
DA_IN => FB_ADI(15 downto 8),
DA_OUT => DA_OUT_X,
IO_A_IN => x"00", -- All port pins are dedicated outputs.
IO_A_OUT(7) => nnIDE_RES,
IO_A_OUT(6) => LP_DIR_X,
IO_A_OUT(5) => LP_STR,
IO_A_OUT(4) => DTR,
IO_A_OUT(3) => RTS,
-- IO_A_OUT(2) => FDD_D1SEL,
IO_A_OUT(1) => DSA_D,
IO_A_OUT(0) => nSDSEL,
IO_A_IN => SND_A,
IO_A_OUT => SND_A_X,
-- IO_A_EN =>, -- Not required.
IO_B_IN => LP_D,
IO_B_OUT => LP_D_X,
@@ -965,7 +985,169 @@ SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0'; --
SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0';
SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0';
FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ";
nnIDE_RES <= SND_A_X(7);
LP_DIR_X <= SND_A_X(6);
LP_STR <= SND_A_X(5);
DTR <= SND_A_X(4);
RTS <= SND_A_X(3);
-- FDD_D1SEL <= SND_A_X(2)
DSA_D <= SND_A_X(1);
nSDSEL <= SND_A_X(0);
LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ";
LP_DIR <= LP_DIR_X;
----------------------------------------------------------------------------
-- DMA Sound register
----------------------------------------------------------------------------
dma_snd_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3E24" else '0'; -- F8900-F893F
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
begin
if nRSTO = '0' THEN
sndmactl <= x"00";
elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_WR = '0' and FB_B1 ='1' then
sndmactl <= FB_AD(23 downto 16);
else
sndmactl <= sndmactl;
end if;
END PROCESS;
FB_AD(23 downto 16) <= sndmactl when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_OE = '0' else "ZZZZZZZZ";
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
begin
if nRSTO = '0' THEN
sndbashi <= x"00";
elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"1" and nFB_WR = '0' and FB_B1 ='1' then
sndbashi <= FB_AD(23 downto 16);
else
sndbashi <= sndbashi;
end if;
END PROCESS;
FB_AD(23 downto 16) <= sndbashi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"1" and nFB_OE = '0' else "ZZZZZZZZ";
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
begin
if nRSTO = '0' THEN
sndbasmi <= x"00";
elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"2" and nFB_WR = '0' and FB_B1 ='1' then
sndbasmi <= FB_AD(23downto 16);
else
sndbasmi <= sndbasmi;
end if;
END PROCESS;
FB_AD(23 downto 16) <= sndbasmi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"2" and nFB_OE = '0' else "ZZZZZZZZ";
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
begin
if nRSTO = '0' THEN
sndbaslo <= x"00";
elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"3" and nFB_WR = '0' and FB_B1 ='1' then
sndbaslo <= FB_AD(23 downto 16);
else
sndbaslo <= sndbaslo;
end if;
END PROCESS;
FB_AD(23 downto 16) <= sndbaslo when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"3" and nFB_OE = '0' else "ZZZZZZZZ";
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
begin
if nRSTO = '0' THEN
sndadrhi <= x"00";
elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"4" and nFB_WR = '0' and FB_B1 ='1' then
sndadrhi <= FB_AD(23 downto 16);
else
sndadrhi <= sndadrhi;
end if;
END PROCESS;
FB_AD(23 downto 16) <= sndadrhi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"4" and nFB_OE = '0' else "ZZZZZZZZ";
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
begin
if nRSTO = '0' THEN
sndadrmi <= x"00";
elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"5" and nFB_WR = '0' and FB_B1 ='1' then
sndadrmi <= FB_AD(23 downto 16);
else
sndadrmi <= sndadrmi;
end if;
END PROCESS;
FB_AD(23 downto 16) <= sndadrmi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"5" and nFB_OE = '0' else "ZZZZZZZZ";
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
begin
if nRSTO = '0' THEN
sndadrlo <= x"00";
elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"6" and nFB_WR = '0' and FB_B1 ='1' then
sndadrlo <= FB_AD(23 downto 16);
else
sndadrlo <= sndadrlo;
end if;
END PROCESS;
FB_AD(23 downto 16) <= sndadrlo when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"6" and nFB_OE = '0' else "ZZZZZZZZ";
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
begin
if nRSTO = '0' THEN
sndendhi <= x"00";
elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"7" and nFB_WR = '0' and FB_B1 ='1' then
sndendhi <= FB_AD(23 downto 16);
else
sndendhi <= sndendhi;
end if;
END PROCESS;
FB_AD(23 downto 16) <= sndendhi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"7" and nFB_OE = '0' else "ZZZZZZZZ";
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
begin
if nRSTO = '0' THEN
sndendmi <= x"00";
elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"8" and nFB_WR = '0' and FB_B1 ='1' then
sndendmi <= FB_AD(23 downto 16);
else
sndendmi <= sndendmi;
end if;
END PROCESS;
FB_AD(23 downto 16) <= sndendmi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"8" and nFB_OE = '0' else "ZZZZZZZZ";
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
begin
if nRSTO = '0' THEN
sndendlo <= x"00";
elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"9" and nFB_WR = '0' and FB_B1 ='1' then
sndendlo <= FB_AD(23 downto 16);
else
sndendlo <= sndendlo;
end if;
END PROCESS;
FB_AD(23 downto 16) <= sndendlo when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"9" and nFB_OE = '0' else "ZZZZZZZZ";
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
begin
if nRSTO = '0' THEN
sndmode <= x"00";
elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"10" and nFB_WR = '0' and FB_B1 ='1' then
sndmode <= FB_AD(23 downto 16);
else
sndmode <= sndmode;
end if;
END PROCESS;
FB_AD(23 downto 16) <= sndmode when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"10" and nFB_OE = '0' else "ZZZZZZZZ";
----------------------------------------------------------------------------
-- Paddle
----------------------------------------------------------------------------
paddle_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3E48" else '0'; -- F9200-F923F
FB_AD(31 downto 16) <= x"bfff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"1" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"8" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"9" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"A" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"B" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= x"0000" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"10" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= x"0000" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"11" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
END FalconIO_SDCard_IDE_CF_architecture;

391
FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd.bak Normal file
View File

@@ -0,0 +1,391 @@
----------------------------------------------------------------------
---- ----
---- ATARI MFP compatible IP Core ----
---- ----
---- This file is part of the SUSKA ATARI clone project. ----
---- http://www.experiment-s.de ----
---- ----
---- Description: ----
---- MC68901 compatible multi function port core. ----
---- ----
---- This is the SUSKA MFP IP core interrupt logic file. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2006 - 2008 Wolfgang Foerster ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.gnu.org/licenses/lgpl.html ----
---- ----
----------------------------------------------------------------------
--
-- Revision History
--
-- Revision 2K6A 2006/06/03 WF
-- Initial Release.
-- Revision 2K6B 2006/11/07 WF
-- Modified Source to compile with the Xilinx ISE.
-- Revision 2K8A 2008/06/03 WF
-- Fixed Pending register logic.
-- Revision 2K9A 2009/06/20 WF
-- Fixed interrupt polarity for TA_I and TB_I.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity WF68901IP_INTERRUPTS is
port ( -- System control:
CLK : in bit;
RESETn : in bit;
-- Asynchronous bus control:
DSn : in bit;
CSn : in bit;
RWn : in bit;
-- Data and Adresses:
RS : in bit_vector(5 downto 1);
DATA_IN : in bit_vector(7 downto 0);
DATA_OUT : out bit_vector(7 downto 0);
DATA_OUT_EN : out bit;
-- Interrupt control:
IACKn : in bit;
IEIn : in bit;
IEOn : out bit;
IRQn : out bit;
-- Interrupt sources:
GP_INT : in bit_vector(7 downto 0);
AER_4 : in bit;
AER_3 : in bit;
TAI : in bit;
TBI : in bit;
TA_PWM : in bit;
TB_PWM : in bit;
TIMER_A_INT : in bit;
TIMER_B_INT : in bit;
TIMER_C_INT : in bit;
TIMER_D_INT : in bit;
RCV_ERR : in bit;
TRM_ERR : in bit;
RCV_BUF_F : in bit;
TRM_BUF_E : in bit
);
end entity WF68901IP_INTERRUPTS;
architecture BEHAVIOR of WF68901IP_INTERRUPTS is
-- Interrupt state machine:
type INT_STATES is (SCAN, REQUEST, VECTOR_OUT);
signal INT_STATE : INT_STATES;
-- The registers:
signal IERA : bit_vector(7 downto 0);
signal IERB : bit_vector(7 downto 0);
signal IPRA : bit_vector(7 downto 0);
signal IPRB : bit_vector(7 downto 0);
signal ISRA : bit_vector(7 downto 0);
signal ISRB : bit_vector(7 downto 0);
signal IMRA : bit_vector(7 downto 0);
signal IMRB : bit_vector(7 downto 0);
signal VR : bit_vector(7 downto 3);
-- Interconnect:
signal VECT_NUMBER : bit_vector(7 downto 0);
signal INT_SRC : bit_vector(15 downto 0);
signal INT_SRC_EDGE : bit_vector(15 downto 0);
signal INT_ENA : bit_vector(15 downto 0);
signal INT_MASK : bit_vector(15 downto 0);
signal INT_PENDING : bit_vector(15 downto 0);
signal INT_SERVICE : bit_vector(15 downto 0);
signal INT_PASS : bit_vector(15 downto 0);
signal INT_OUT : bit_vector(15 downto 0);
signal GP_INT_4 : bit;
signal GP_INT_3 : bit;
begin
-- Interrupt source for the GPI_4 and GPI_3 is normally the respective port pin.
-- But when the timers operate in their PWM modes, the GPI_4 and GPI_3 are associated
-- to timer A and timer B.
-- The xor logic provides polarity control for the interrupt transition. Be aware,
-- that the PWM signals cause an interrupt on the opposite transition like the
-- respective GPIP port pins (with the same AER settings).
--GP_INT_4 <= GP_INT(4) when TA_PWM = '0' else TAI xor AER_4;
--GP_INT_3 <= GP_INT(3) when TB_PWM = '0' else TBI xor AER_3;
GP_INT_4 <= GP_INT(4) when TA_PWM = '0' else TAI xnor AER_4; -- This should be correct.
GP_INT_3 <= GP_INT(3) when TB_PWM = '0' else TBI xnor AER_3;
-- Interrupt source priority sorted (15 = highest):
INT_SRC <= GP_INT(7 downto 6) & TIMER_A_INT & RCV_BUF_F & RCV_ERR & TRM_BUF_E & TRM_ERR & TIMER_B_INT &
GP_INT(5) & GP_INT_4 & TIMER_C_INT & TIMER_D_INT & GP_INT_3 & GP_INT(2 downto 0);
INT_ENA <= IERA & IERB;
INT_MASK <= IMRA & IMRB;
INT_PENDING <= IPRA & IPRB;
INT_SERVICE <= ISRA & ISRB;
INT_OUT <= INT_PENDING and INT_MASK; -- Masking:
-- Enable the daisy chain, if there is no pending interrupt and
-- the interrupt state machine is not in service.
IEOn <= '0' when INT_OUT = x"0000" and INT_STATE = SCAN else '1';
-- Interrupt request:
IRQn <= '0' when INT_OUT /= x"0000" and INT_STATE = REQUEST else '1';
EDGE_ENA: process(RESETn, CLK)
-- These are the 16 edge detectors of the 16 interrupt input sources. This
-- process also provides the disabling or enabling via the IERA and IERB registers.
variable LOCK : bit_vector(15 downto 0);
begin
if RESETn = '0' then
INT_SRC_EDGE <= x"0000";
LOCK := x"0000";
elsif CLK = '0' and CLK' event then
for i in 15 downto 0 loop
if INT_SRC(i) = '1' and INT_ENA(i) = '1' and LOCK(i) = '0' then
LOCK(i) := '1';
INT_SRC_EDGE(i) <= '1';
elsif INT_SRC(i) = '0' then
LOCK(i) := '0';
INT_SRC_EDGE(i) <= '0';
else
INT_SRC_EDGE(i) <= '0';
end if;
end loop;
end if;
end process EDGE_ENA;
INT_REGISTERS: process(RESETn, CLK)
begin
if RESETn = '0' then
IERA <= (others => '0');
IERB <= (others => '0');
IPRA <= (others => '0');
IPRB <= (others => '0');
ISRA <= (others => '0');
ISRB <= (others => '0');
IMRA <= (others => '0');
IMRB <= (others => '0');
elsif CLK = '1' and CLK' event then
if CSn = '0' and DSn = '0' and RWn = '0' then
case RS is
when "00011" => IERA <= DATA_IN; -- Enable A.
when "00100" => IERB <= DATA_IN; -- Enable B.
when "00101" =>
-- Only a '0' can be written to the pending register.
for i in 7 downto 0 loop
if DATA_IN(i) = '0' then
IPRA(i) <= '0'; -- Pending A.
end if;
end loop;
when "00110" =>
-- Only a '0' can be written to the pending register.
for i in 7 downto 0 loop
if DATA_IN(i) = '0' then
IPRB(i) <= '0'; -- Pending B.
end if;
end loop;
when "00111" =>
-- Only a '0' can be written to the in service register.
for i in 7 downto 0 loop
if DATA_IN(i) = '0' then
ISRA(i) <= '0'; -- In Service A.
end if;
end loop;
when "01000" =>
-- Only a '0' can be written to the in service register.
for i in 7 downto 0 loop
if DATA_IN(i) = '0' then
ISRB(i) <= '0'; -- In Service B.
end if;
end loop;
when "01001" => IMRA <= DATA_IN; -- Mask A.
when "01010" => IMRB <= DATA_IN; -- Mask B.
when "01011" => VR <= DATA_IN(7 downto 3); -- Vector register.
when others => null;
end case;
end if;
-- Pending register:
-- set and clear bit logic.
for i in 15 downto 8 loop
if INT_SRC_EDGE(i) = '1' then
IPRA(i-8) <= '1';
elsif INT_ENA(i) = '0' then
IPRA(i-8) <= '0'; -- Clear by disabling the channel.
elsif INT_PASS(i) = '1' then
IPRA(i-8) <= '0'; -- Clear by passing the interrupt.
end if;
end loop;
for i in 7 downto 0 loop
if INT_SRC_EDGE(i) = '1' then
IPRB(i) <= '1';
elsif INT_ENA(i) = '0' then
IPRB(i) <= '0'; -- Clear by disabling the channel.
elsif INT_PASS(i) = '1' then
IPRB(i) <= '0'; -- Clear by passing the interrupt.
end if;
end loop;
-- In-Service register:
-- Set bit logic, VR(3) is the service register enable.
for i in 15 downto 8 loop
if INT_OUT(i) = '1' and INT_PASS(i) = '1' and VR(3) = '1' then
ISRA(i-8) <= '1';
end if;
end loop;
for i in 7 downto 0 loop
if INT_OUT(i) = '1' and INT_PASS(i) = '1' and VR(3) = '1' then
ISRB(i) <= '1';
end if;
end loop;
end if;
end process INT_REGISTERS;
DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS > "00010" and RS <= "01011" else '1' when INT_STATE = VECTOR_OUT else '0';
DATA_OUT <= IERA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00011" else
IERB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00100" else
IPRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00101" else
IPRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00110" else
ISRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00111" else
ISRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01000" else
IMRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01001" else
IMRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01010" else
VR & "000" when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01011" else
VECT_NUMBER when INT_STATE = VECTOR_OUT else x"00";
P_INT_STATE : process(RESETn, CLK)
begin
if RESETn = '0' then
INT_STATE <= SCAN;
elsif CLK = '1' and CLK' event then
case INT_STATE is
when SCAN =>
INT_PASS <= x"0000";
-- Automatic End of Interrupt mode. Service register disabled.
-- The MFP does not respond for an interrupt acknowledge cycle for an uninitialized
-- vector number (VR(7 downto 4) = x"0").
if INT_OUT /= x"0000" and VR(7 downto 4) /= x"0" and VR(3) = '0' and IEIn = '0' then
INT_STATE <= REQUEST; -- Non masked interrupt is pending.
-- The following 16 are the Software end of interrupt mode. Service register enabled.
-- The MFP does not respond for an interrupt acknowledge cycle for an uninitialized
-- vector number (VR(7 downto 4) = x"0"). The interrupts are prioritized.
elsif INT_OUT /= x"0000" and VR(7 downto 4) /= x"0" and VR(3) = '1' and IEIn = '0' then
if INT_OUT (15) = '1' and INT_SERVICE(15) = '0' then
INT_STATE <= REQUEST;
elsif INT_OUT (14) = '1' and INT_SERVICE(15 downto 14) = "00" then
INT_STATE <= REQUEST;
elsif INT_OUT (13) = '1' and INT_SERVICE(15 downto 13) = "000" then
INT_STATE <= REQUEST;
elsif INT_OUT (12) = '1' and INT_SERVICE(15 downto 12) = x"0" then
INT_STATE <= REQUEST;
elsif INT_OUT (11) = '1' and INT_SERVICE(15 downto 11) = x"0" & '0' then
INT_STATE <= REQUEST;
elsif INT_OUT (10) = '1' and INT_SERVICE(15 downto 10) = x"0" & "00" then
INT_STATE <= REQUEST;
elsif INT_OUT (9) = '1' and INT_SERVICE(15 downto 9) = x"0" & "000" then
INT_STATE <= REQUEST;
elsif INT_OUT (8) = '1' and INT_SERVICE(15 downto 8) = x"00" then
INT_STATE <= REQUEST;
elsif INT_OUT (7) = '1' and INT_SERVICE(15 downto 7) = x"00" & '0' then
INT_STATE <= REQUEST;
elsif INT_OUT (6) = '1' and INT_SERVICE(15 downto 6) = x"00" & "00" then
INT_STATE <= REQUEST;
elsif INT_OUT (5) = '1' and INT_SERVICE(15 downto 5) = x"00" & "000" then
INT_STATE <= REQUEST;
elsif INT_OUT (4) = '1' and INT_SERVICE(15 downto 4) = x"000" then
INT_STATE <= REQUEST;
elsif INT_OUT (3) = '1' and INT_SERVICE(15 downto 3) = x"000" & '0' then
INT_STATE <= REQUEST;
elsif INT_OUT (2) = '1' and INT_SERVICE(15 downto 2) = x"000" & "00" then
INT_STATE <= REQUEST;
elsif INT_OUT (1) = '1' and INT_SERVICE(15 downto 1) = x"000" & "000" then
INT_STATE <= REQUEST;
elsif INT_OUT (0) = '1' and INT_SERVICE(15 downto 0) = x"0000" then
INT_STATE <= REQUEST;
else
INT_STATE <= SCAN; -- Wait for interrupt.
end if;
else
INT_STATE <= SCAN;
end if;
when REQUEST =>
if IACKn = '0' and DSn = '0' then -- Vectored interrupt mode.
INT_STATE <= VECTOR_OUT; -- Non masked interrupt is pending.
if INT_OUT(15) = '1' then
INT_PASS(15) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"F"; -- GPI 7.
elsif INT_OUT(14) = '1' then
INT_PASS(14) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"E"; -- GPI 6.
elsif INT_OUT(13) = '1' then
INT_PASS(13) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"D"; -- TIMER A.
elsif INT_OUT(12) = '1' then
INT_PASS(12) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"C"; -- Receive buffer full.
elsif INT_OUT(11) = '1' then
INT_PASS(11) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"B"; -- Receiver error.
elsif INT_OUT(10) = '1' then
INT_PASS(10) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"A"; -- Transmit buffer empty.
elsif INT_OUT(9) = '1' then
INT_PASS(9) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"9"; -- Transmit error.
elsif INT_OUT(8) = '1' then
INT_PASS(8) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"8"; -- Timer B.
elsif INT_OUT(7) = '1' then
INT_PASS(7) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"7"; -- GPI 5.
elsif INT_OUT(6) = '1' then
INT_PASS(6) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"6"; -- GPI 4.
elsif INT_OUT(5) = '1' then
INT_PASS(5) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"5"; -- Timer C.
elsif INT_OUT(4) = '1' then
INT_PASS(4) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"4"; -- Timer D.
elsif INT_OUT(3) = '1' then
INT_PASS(3) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"3"; -- GPI 3.
elsif INT_OUT(2) = '1' then
INT_PASS(2) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"2"; -- GPI 2.
elsif INT_OUT(1) = '1' then
INT_PASS(1) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"1"; -- GPI 1.
elsif INT_OUT(0) = '1' then
INT_PASS(0) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"0"; -- GPI 0.
end if;
-- Polled interrupt mode: End of interrupt by writing to the pending registers.
elsif CSn = '0' and DSn = '0' and RWn = '0' and (RS = "00101" or RS = "00110") then
INT_STATE <= SCAN;
else
INT_STATE <= REQUEST; -- Wait.
end if;
when VECTOR_OUT =>
INT_PASS <= x"0000";
if DSn = '1' or IACKn = '1' then
INT_STATE <= SCAN; -- Finished.
else
INT_STATE <= VECTOR_OUT; -- Wait for processor to read the vector.
end if;
end case;
end if;
end process P_INT_STATE;
end architecture BEHAVIOR;

4
FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
View File

@@ -190,8 +190,8 @@ begin
end if;
end process DIG_PORTS;
-- Set port direction to input or to output:
IO_A_EN <= '1' when CTRL_REG(6) = '1' else '0';
IO_B_EN <= '1' when CTRL_REG(7) = '1' else '0';
IO_A_EN <= '1' when CTRL_REG(6) = '1' else '0';
IO_B_EN <= '1' when CTRL_REG(7) = '1' else '0';
IO_A_OUT <= PORT_A;
IO_B_OUT <= PORT_B;

229
FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd.bak Normal file
View File

@@ -0,0 +1,229 @@
----------------------------------------------------------------------
---- ----
---- YM2149 compatible sound generator. ----
---- ----
---- This file is part of the SUSKA ATARI clone project. ----
---- http://www.experiment-s.de ----
---- ----
---- Description: ----
---- Model of the ST or STE's YM2149 sound generator. ----
---- This IP core of the sound generator differs slightly from ----
---- the original. Firstly it is a synchronous design without any ----
---- latches (like assumed in the original chip). This required ----
---- the introduction of a system adequate clock. In detail this ----
---- SYS_CLK should on the one hand be fast enough to meet the ----
---- timing requirements of the system's bus cycle and should one ----
---- the other hand drive the PWM modules correctly. To meet both ----
---- a SYS_CLK of 16MHz or above is recommended. ----
---- Secondly, the original chip has an implemented DA converter. ----
---- This feature is not possible in today's FPGAs. Therefore the ----
---- converter is replaced by pulse width modulators. This solu- ----
---- tion is very simple in comparison to other approaches like ----
---- external DA converters with wave tables etc. The soltution ----
---- with the pulse width modulators is probably not as accurate ----
---- DAs with wavetables. For a detailed descrition of the hard- ----
---- ware PWM filter look at the end of the wave file, where the ----
---- pulse width modulators can be found. ----
---- For a proper operation it is required, that the wave clock ----
---- is lower than the system clock. A good choice is for example ----
---- 2MHz for the wave clock and 16MHz for the system clock. ----
---- ----
---- Main module file. ----
---- Top level file for use in systems on programmable chips. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2006 - 2008 Wolfgang Foerster ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.gnu.org/licenses/lgpl.html ----
---- ----
----------------------------------------------------------------------
--
-- Revision History
--
-- Revision 2K6A 2006/06/03 WF
-- Initial Release.
-- Revision 2K6B 2006/11/07 WF
-- Modified Source to compile with the Xilinx ISE.
-- Top level file provided for SOC (systems on programmable chips).
-- Revision 2K8A 2008/07/14 WF
-- Minor changes.
--
library ieee;
use ieee.std_logic_1164.all;
use work.wf2149ip_pkg.all;
entity WF2149IP_TOP_SOC is
port(
SYS_CLK : in bit; -- Read the inforation in the header!
RESETn : in bit;
WAV_CLK : in bit; -- Read the inforation in the header!
SELn : in bit;
BDIR : in bit;
BC2, BC1 : in bit;
A9n, A8 : in bit;
DA_IN : in std_logic_vector(7 downto 0);
DA_OUT : out std_logic_vector(7 downto 0);
DA_EN : out bit;
IO_A_IN : in bit_vector(7 downto 0);
IO_A_OUT : out bit_vector(7 downto 0);
IO_A_EN : out bit;
IO_B_IN : in bit_vector(7 downto 0);
IO_B_OUT : out bit_vector(7 downto 0);
IO_B_EN : out bit;
OUT_A : out bit; -- Analog (PWM) outputs.
OUT_B : out bit;
OUT_C : out bit
);
end WF2149IP_TOP_SOC;
architecture STRUCTURE of WF2149IP_TOP_SOC is
signal BUSCYCLE : BUSCYCLES;
signal DATA_OUT_I : std_logic_vector(7 downto 0);
signal DATA_EN_I : bit;
signal WAV_STRB : bit;
signal ADR_I : bit_vector(3 downto 0);
signal CTRL_REG : bit_vector(7 downto 0);
signal PORT_A : bit_vector(7 downto 0);
signal PORT_B : bit_vector(7 downto 0);
begin
P_WAVSTRB: process(RESETn, SYS_CLK)
variable LOCK : boolean;
variable TMP : bit;
begin
if RESETn = '0' then
LOCK := false;
TMP := '0';
elsif SYS_CLK = '1' and SYS_CLK' event then
if WAV_CLK = '1' and LOCK = false then
LOCK := true;
TMP := not TMP; -- Divider by 2.
case SELn is
when '1' => WAV_STRB <= '1';
when others => WAV_STRB <= TMP;
end case;
elsif WAV_CLK = '0' then
LOCK := false;
WAV_STRB <= '0';
else
WAV_STRB <= '0';
end if;
end if;
end process P_WAVSTRB;
with BDIR & BC2 & BC1 select
BUSCYCLE <= INACTIVE when "000" | "010" | "101",
ADDRESS when "001" | "100" | "111",
R_READ when "011",
R_WRITE when "110";
ADDRESSLATCH: process(RESETn, SYS_CLK)
-- This process is responsible to store the desired register
-- address. The default (after reset) is channel A fine tone
-- adjustment.
begin
if RESETn = '0' then
ADR_I <= (others => '0');
elsif SYS_CLK = '1' and SYS_CLK' event then
if BUSCYCLE = ADDRESS and A9n = '0' and A8 = '1' and DA_IN(7 downto 4) = x"0" then
ADR_I <= To_BitVector(DA_IN(3 downto 0));
end if;
end if;
end process ADDRESSLATCH;
P_CTRL_REG: process(RESETn, SYS_CLK)
-- THIS is the Control register for the mixer and for the I/O ports.
begin
if RESETn = '0' then
CTRL_REG <= x"00";
elsif SYS_CLK = '1' and SYS_CLK' event then
if BUSCYCLE = R_WRITE and ADR_I = x"7" then
CTRL_REG <= To_BitVector(DA_IN);
end if;
end if;
end process P_CTRL_REG;
DIG_PORTS: process(RESETn, SYS_CLK)
begin
if RESETn = '0' then
PORT_A <= x"00";
PORT_B <= x"00";
elsif SYS_CLK = '1' and SYS_CLK' event then
if BUSCYCLE = R_WRITE and ADR_I = x"E" then
PORT_A <= To_BitVector(DA_IN);
elsif BUSCYCLE = R_WRITE and ADR_I = x"F" then
PORT_B <= To_BitVector(DA_IN);
end if;
end if;
end process DIG_PORTS;
-- Set port direction to input or to output:
IO_A_EN <= '1' when CTRL_REG(6) = '1' else '1'; --0
IO_B_EN <= '1' when CTRL_REG(7) = '1' else '1'; --0
IO_A_OUT <= PORT_A;
IO_B_OUT <= PORT_B;
I_PSG_WAVE: WF2149IP_WAVE
port map(
RESETn => RESETn,
SYS_CLK => SYS_CLK,
WAV_STRB => WAV_STRB,
ADR => ADR_I,
DATA_IN => DA_IN,
DATA_OUT => DATA_OUT_I,
DATA_EN => DATA_EN_I,
BUSCYCLE => BUSCYCLE,
CTRL_REG => CTRL_REG(5 downto 0),
OUT_A => OUT_A,
OUT_B => OUT_B,
OUT_C => OUT_C
);
-- Read the ports and registers:
DA_EN <= '1' when DATA_EN_I = '1' else
'1' when BUSCYCLE = R_READ and ADR_I = x"7" else
'1' when BUSCYCLE = R_READ and ADR_I = x"E" else
'1' when BUSCYCLE = R_READ and ADR_I = x"F" else '0';
DA_OUT <= DATA_OUT_I when DATA_EN_I = '1' else -- WAV stuff.
To_StdLogicVector(IO_A_IN) when BUSCYCLE = R_READ and ADR_I = x"E" else
To_StdLogicVector(IO_B_IN) when BUSCYCLE = R_READ and ADR_I = x"F" else
To_StdLogicVector(CTRL_REG) when BUSCYCLE = R_READ and ADR_I = x"7" else (others => '0');
end STRUCTURE;

166
FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
View File

@@ -67,7 +67,7 @@ use ieee.std_logic_unsigned.all;
entity WF6850IP_CTRL_STATUS is
port (
CLK : in bit;
CLK : in std_logic;
RESETn : in bit;
CS : in bit_vector(2 downto 0); -- Active if "011".
@@ -94,7 +94,7 @@ entity WF6850IP_CTRL_STATUS is
CDS : out bit_vector(1 downto 0); -- Clock control.
WS : out bit_vector(2 downto 0); -- Word select.
TC : out bit_vector(1 downto 0); -- Transmit control.
IRQn : out bit -- Interrupt request.
IRQn : buffer bit -- Interrupt request.
);
end entity WF6850IP_CTRL_STATUS;
@@ -102,19 +102,14 @@ architecture BEHAVIOR of WF6850IP_CTRL_STATUS is
signal CTRL_REG : bit_vector(7 downto 0);
signal STATUS_REG : bit_vector(7 downto 0);
signal RIE : bit;
signal IRQ_I : bit;
signal CTS_In : bit;
signal DCD_In : bit;
signal DCD_FLAGn : bit;
begin
P_SAMPLE: process
begin
wait until CLK = '0' and CLK' event;
CTS_In <= CTSn; -- Sample CTSn on the negative clock edge.
DCD_In <= DCDn; -- Sample DCDn on the negative clock edge.
end process P_SAMPLE;
CTS_In <= CTSn;
DCD_In <= DCDn; -- immer 0
STATUS_REG(7) <= IRQ_I;
STATUS_REG(7) <= not IRQn;
STATUS_REG(6) <= PE;
STATUS_REG(5) <= OVR;
STATUS_REG(4) <= FE;
@@ -123,8 +118,8 @@ begin
STATUS_REG(1) <= TDRE and not CTS_In; -- No TDRE for CTSn = '1'.
STATUS_REG(0) <= RDRF and not DCD_In; -- DCDn = '1' indicates empty.
DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' and E = '1' else (others => '0');
DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' and E = '1' else '0';
DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' else (others => '0');
DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' else '0';
MCLR <= '1' when CTRL_REG(1 downto 0) = "11" else '0';
RTSn <= '0' when CTRL_REG(6 downto 5) /= "10" else '1';
@@ -134,110 +129,73 @@ begin
TC <= CTRL_REG(6 downto 5);
RIE <= CTRL_REG(7);
P_IRQ: process
variable DCD_OVR_LOCK : boolean;
variable DCD_LOCK : boolean;
variable DCD_TRANS : boolean;
begin
wait until CLK = '1' and CLK' event;
if RESETn = '0' then
DCD_OVR_LOCK := false;
IRQn <= '1';
IRQ_I <= '0';
elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then
DCD_OVR_LOCK := false; -- Enable reset by reading the status.
P_IRQ: process(CLK)
begin
if rising_edge(CLK) then
if RESETn = '0' or MCLR = '1' then
IRQn <= '1';
else
-- Transmitter interrupt:
if TDRE = '1' and CTRL_REG(6 downto 5) = "01" then
IRQn <= '0';
end if;
-- Receiver interrupts:
if RDRF = '1' and RIE = '1' then
IRQn <= '0';
end if;
-- Overrun
if OVR = '1' and RIE = '1' then
IRQn <= '0';
end if;
-- The reset of the IRQ status flag:
-- Clear by writing to the transmit data register.
-- Clear by reading the receive data register.
if CS = "011" and RS = '1' then
IRQn <= '1';
end if;
end if;
end if;
-- Clear interrupts when disabled.
if CTRL_REG(7) = '0' then
IRQn <= '1';
IRQ_I <= '0';
elsif CTRL_REG(6 downto 5) /= "01" then
IRQn <= '1';
IRQ_I <= '0';
end if;
-- Transmitter interrupt:
if TDRE = '1' and CTRL_REG(6 downto 5) = "01" and CTS_In = '0' then
IRQn <= '0';
IRQ_I <= '1';
elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' then
IRQn <= '1'; -- Clear by writing to the transmit data register.
end if;
-- Receiver interrupts:
if RDRF = '1' and RIE = '1' and DCD_In = '0' then
IRQn <= '0';
IRQ_I <= '1';
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
IRQn <= '1'; -- Clear by reading the receive data register.
end if;
if OVR = '1' and RIE = '1' then
IRQn <= '0';
IRQ_I <= '1';
DCD_OVR_LOCK := true;
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then
IRQn <= '1'; -- Clear by reading the receive data register after the status.
end if;
if DCD_In = '1' and RIE = '1' and DCD_TRANS = false then
IRQn <= '0';
IRQ_I <= '1';
-- DCD_TRANS is used to detect a low to high transition of DCDn.
DCD_TRANS := true;
DCD_OVR_LOCK := true;
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then
IRQn <= '1'; -- Clear by reading the receive data register after the status.
elsif DCD_In = '0' then
DCD_TRANS := false;
end if;
-- The reset of the IRQ status flag:
-- Clear by writing to the transmit data register.
-- Clear by reading the receive data register.
if CS = "011" and RS = '1' and E = '1' then
IRQ_I <= '0';
end if;
end process P_IRQ;
CONTROL: process
CONTROL: process(CLK)
begin
wait until CLK = '1' and CLK' event;
if RESETn = '0' then
CTRL_REG <= "01000000";
elsif CS = "011" and RWn = '0' and RS = '0' and E = '1' then
CTRL_REG <= DATA_IN;
if rising_edge(CLK) then
if RESETn = '0' then
CTRL_REG <= "01000000";
elsif CS = "011" and RWn = '0' and RS = '0' then
CTRL_REG <= DATA_IN;
end if;
end if;
end process CONTROL;
P_DCD: process
P_DCD: process(CLK)
-- This process is some kind of tricky. Refer to the MC6850 data
-- sheet for more information.
variable READ_LOCK : boolean;
variable DCD_RELEASE : boolean;
begin
wait until CLK = '1' and CLK' event;
if RESETn = '0' then
DCD_FLAGn <= '0'; -- This interrupt source must initialise low.
READ_LOCK := true;
DCD_RELEASE := false;
elsif MCLR = '1' then
DCD_FLAGn <= DCD_In;
READ_LOCK := true;
elsif DCD_In = '1' then
DCD_FLAGn <= '1';
elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then
READ_LOCK := false; -- Un-READ_LOCK if receiver data register is read.
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and READ_LOCK = false then
-- Clear if receiver status register read access.
-- After data register has ben read and READ_LOCK again.
DCD_RELEASE := true;
READ_LOCK := true;
DCD_FLAGn <= DCD_In;
elsif DCD_In = '0' and DCD_RELEASE = true then
DCD_FLAGn <= '0';
DCD_RELEASE := false;
if rising_edge(CLK) then
if RESETn = '0' then
DCD_FLAGn <= '0'; -- This interrupt source must initialise low.
READ_LOCK := true;
DCD_RELEASE := false;
elsif MCLR = '1' then
DCD_FLAGn <= DCD_In;
READ_LOCK := true;
elsif DCD_In = '1' then
DCD_FLAGn <= '1';
elsif CS = "011" and RWn = '1' and RS = '0' then
READ_LOCK := false; -- Un-READ_LOCK if receiver data register is read.
elsif CS = "011" and RWn = '1' and RS = '1' and READ_LOCK = false then
-- Clear if receiver status register read access.
-- After data register has ben read and READ_LOCK again.
DCD_RELEASE := true;
READ_LOCK := true;
DCD_FLAGn <= DCD_In;
elsif DCD_In = '0' and DCD_RELEASE = true then
DCD_FLAGn <= '0';
DCD_RELEASE := false;
end if;
end if;
end process P_DCD;
end architecture BEHAVIOR;

178
FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak
View File

@@ -67,7 +67,7 @@ use ieee.std_logic_unsigned.all;
entity WF6850IP_CTRL_STATUS is
port (
CLK : in bit;
CLK : in std_logic;
RESETn : in bit;
CS : in bit_vector(2 downto 0); -- Active if "011".
@@ -94,7 +94,7 @@ entity WF6850IP_CTRL_STATUS is
CDS : out bit_vector(1 downto 0); -- Clock control.
WS : out bit_vector(2 downto 0); -- Word select.
TC : out bit_vector(1 downto 0); -- Transmit control.
IRQn : out bit -- Interrupt request.
IRQn : buffer bit -- Interrupt request.
);
end entity WF6850IP_CTRL_STATUS;
@@ -102,19 +102,14 @@ architecture BEHAVIOR of WF6850IP_CTRL_STATUS is
signal CTRL_REG : bit_vector(7 downto 0);
signal STATUS_REG : bit_vector(7 downto 0);
signal RIE : bit;
signal IRQ_I : bit;
signal CTS_In : bit;
signal DCD_In : bit;
signal DCD_FLAGn : bit;
begin
P_SAMPLE: process
begin
wait until CLK = '0' and CLK' event;
CTS_In <= CTSn; -- Sample CTSn on the negative clock edge.
DCD_In <= DCDn; -- Sample DCDn on the negative clock edge.
end process P_SAMPLE;
CTS_In <= CTSn;
DCD_In <= DCDn; -- immer 0
STATUS_REG(7) <= IRQ_I;
STATUS_REG(7) <= not IRQn;
STATUS_REG(6) <= PE;
STATUS_REG(5) <= OVR;
STATUS_REG(4) <= FE;
@@ -123,8 +118,8 @@ begin
STATUS_REG(1) <= TDRE and not CTS_In; -- No TDRE for CTSn = '1'.
STATUS_REG(0) <= RDRF and not DCD_In; -- DCDn = '1' indicates empty.
DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' and E = '1' else (others => '0');
DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' and E = '1' else '0';
DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' else (others => '0');
DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' else '0';
MCLR <= '1' when CTRL_REG(1 downto 0) = "11" else '0';
RTSn <= '0' when CTRL_REG(6 downto 5) /= "10" else '1';
@@ -134,110 +129,85 @@ begin
TC <= CTRL_REG(6 downto 5);
RIE <= CTRL_REG(7);
P_IRQ: process
variable DCD_OVR_LOCK : boolean;
variable DCD_LOCK : boolean;
variable DCD_TRANS : boolean;
begin
wait until CLK = '1' and CLK' event;
if RESETn = '0' then
DCD_OVR_LOCK := false;
IRQn <= '1';
IRQ_I <= '0';
elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then
DCD_OVR_LOCK := false; -- Enable reset by reading the status.
P_IRQ: process(CLK)
variable irq_v : std_logic_vector(3 downto 0);
begin
if rising_edge(CLK) then
if RESETn = '0' or MCLR = '1' then
irq_v := x"0";
IRQn <= '1';
else
-- Transmitter interrupt:
if TDRE = '1' and CTRL_REG(6 downto 5) = "01" then
if irq_v = x"F" then
irq_v := irq_v + 1;
end if;
-- Receiver interrupts:
elsif RDRF = '1' and RIE = '1' then
if irq_v < 15 then
irq_v := irq_v + 1;
end if;
-- Overrun
elsif OVR = '1' and RIE = '1' then
if irq_v < 15 then
irq_v := irq_v + 1;
end if;
else
if irq_v > 0 then
irq_v := irq_v - 1;
end if;
end if;
if irq_v < 8 then
IRQn <= '1';
else
IRQn <= '0';
end if;
-- The reset of the IRQ status flag:
-- Clear by writing to the transmit data register.
-- Clear by reading the receive data register.
end if;
end if;
-- Clear interrupts when disabled.
if CTRL_REG(7) = '0' then
IRQn <= '1';
IRQ_I <= '0';
elsif CTRL_REG(6 downto 5) /= "01" then
IRQn <= '1';
IRQ_I <= '0';
end if;
-- Transmitter interrupt:
if TDRE = '1' and CTRL_REG(6 downto 5) = "01" and CTS_In = '0' then
IRQn <= '0';
IRQ_I <= '1';
elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' then
IRQn <= '1'; -- Clear by writing to the transmit data register.
end if;
-- Receiver interrupts:
if RDRF = '1' and RIE = '1' and DCD_In = '0' then
IRQn <= '0';
IRQ_I <= '1';
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
IRQn <= '1'; -- Clear by reading the receive data register.
end if;
if OVR = '1' and RIE = '1' then
IRQn <= '0';
IRQ_I <= '1';
DCD_OVR_LOCK := true;
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then
IRQn <= '1'; -- Clear by reading the receive data register after the status.
end if;
if DCD_In = '1' and RIE = '1' and DCD_TRANS = false then
IRQn <= '0';
IRQ_I <= '1';
-- DCD_TRANS is used to detect a low to high transition of DCDn.
DCD_TRANS := true;
DCD_OVR_LOCK := true;
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then
IRQn <= '1'; -- Clear by reading the receive data register after the status.
elsif DCD_In = '0' then
DCD_TRANS := false;
end if;
-- The reset of the IRQ status flag:
-- Clear by writing to the transmit data register.
-- Clear by reading the receive data register.
if CS = "011" and RS = '1' and E = '1' then
IRQ_I <= '0';
end if;
end process P_IRQ;
CONTROL: process
CONTROL: process(CLK)
begin
wait until CLK = '1' and CLK' event;
if RESETn = '0' then
CTRL_REG <= "01000000";
elsif CS = "011" and RWn = '0' and RS = '0' and E = '1' then
CTRL_REG <= DATA_IN;
if rising_edge(CLK) then
if RESETn = '0' then
CTRL_REG <= "01000000";
elsif CS = "011" and RWn = '0' and RS = '0' then
CTRL_REG <= DATA_IN;
end if;
end if;
end process CONTROL;
P_DCD: process
P_DCD: process(CLK)
-- This process is some kind of tricky. Refer to the MC6850 data
-- sheet for more information.
variable READ_LOCK : boolean;
variable DCD_RELEASE : boolean;
begin
wait until CLK = '1' and CLK' event;
if RESETn = '0' then
DCD_FLAGn <= '0'; -- This interrupt source must initialise low.
READ_LOCK := true;
DCD_RELEASE := false;
elsif MCLR = '1' then
DCD_FLAGn <= DCD_In;
READ_LOCK := true;
elsif DCD_In = '1' then
DCD_FLAGn <= '1';
elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then
READ_LOCK := false; -- Un-READ_LOCK if receiver data register is read.
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and READ_LOCK = false then
-- Clear if receiver status register read access.
-- After data register has ben read and READ_LOCK again.
DCD_RELEASE := true;
READ_LOCK := true;
DCD_FLAGn <= DCD_In;
elsif DCD_In = '0' and DCD_RELEASE = true then
DCD_FLAGn <= '0';
DCD_RELEASE := false;
if rising_edge(CLK) then
if RESETn = '0' then
DCD_FLAGn <= '0'; -- This interrupt source must initialise low.
READ_LOCK := true;
DCD_RELEASE := false;
elsif MCLR = '1' then
DCD_FLAGn <= DCD_In;
READ_LOCK := true;
elsif DCD_In = '1' then
DCD_FLAGn <= '1';
elsif CS = "011" and RWn = '1' and RS = '0' then
READ_LOCK := false; -- Un-READ_LOCK if receiver data register is read.
elsif CS = "011" and RWn = '1' and RS = '1' and READ_LOCK = false then
-- Clear if receiver status register read access.
-- After data register has ben read and READ_LOCK again.
DCD_RELEASE := true;
READ_LOCK := true;
DCD_FLAGn <= DCD_In;
elsif DCD_In = '0' and DCD_RELEASE = true then
DCD_FLAGn <= '0';
DCD_RELEASE := false;
end if;
end if;
end process P_DCD;
end architecture BEHAVIOR;

419
FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive - Kopie.vhd Normal file
View File

@@ -0,0 +1,419 @@
----------------------------------------------------------------------
---- ----
---- 6850 compatible IP Core ----
---- ----
---- This file is part of the SUSKA ATARI clone project. ----
---- http://www.experiment-s.de ----
---- ----
---- Description: ----
---- UART 6850 compatible IP core ----
---- ----
---- 6850's receiver unit. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2006 - 2008 Wolfgang Foerster ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.gnu.org/licenses/lgpl.html ----
---- ----
----------------------------------------------------------------------
--
-- Revision History
--
-- Revision 2K6A 2006/06/03 WF
-- Initial Release.
-- Revision 2K6B 2006/11/07 WF
-- Modified Source to compile with the Xilinx ISE.
-- Revision 2K8A 2008/07/14 WF
-- Minor changes.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity WF6850IP_RECEIVE is
port (
CLK : in bit;
RESETn : in bit;
MCLR : in bit;
CS : in bit_vector(2 downto 0);
E : in bit;
RWn : in bit;
RS : in bit;
DATA_OUT : out bit_vector(7 downto 0);
DATA_EN : out bit;
WS : in bit_vector(2 downto 0);
CDS : in bit_vector(1 downto 0);
RXCLK : in bit;
RXDATA : in bit;
RDRF : buffer bit;
OVR : out bit;
PE : out bit;
FE : out bit
);
end entity WF6850IP_RECEIVE;
architecture BEHAVIOR of WF6850IP_RECEIVE is
type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC);
signal RCV_STATE, RCV_NEXT_STATE : RCV_STATES;
signal RXDATA_I : bit;
signal RXDATA_S : bit;
signal DATA_REG : bit_vector(7 downto 0);
signal SHIFT_REG : bit_vector(7 downto 0);
signal CLK_STRB : bit;
signal BITCNT : std_logic_vector(2 downto 0);
begin
P_SAMPLE: process
-- This filter provides a synchronisation to the system
-- clock, even for random baud rates of the received data
-- stream.
variable FLT_TMP : integer range 0 to 2;
begin
wait until CLK = '1' and CLK' event;
--
RXDATA_I <= RXDATA;
--
if RXDATA_I = '1' and FLT_TMP < 2 then
FLT_TMP := FLT_TMP + 1;
elsif RXDATA_I = '1' then
RXDATA_S <= '1';
elsif RXDATA_I = '0' and FLT_TMP > 0 then
FLT_TMP := FLT_TMP - 1;
elsif RXDATA_I = '0' then
RXDATA_S <= '0';
end if;
end process P_SAMPLE;
CLKDIV: process
variable CLK_LOCK : boolean;
variable STRB_LOCK : boolean;
variable CLK_DIVCNT : std_logic_vector(6 downto 0);
begin
wait until CLK = '1' and CLK' event;
if CDS = "00" then -- Divider off.
if RXCLK = '1' and STRB_LOCK = false then
CLK_STRB <= '1';
STRB_LOCK := true;
elsif RXCLK = '0' then
CLK_STRB <= '0';
STRB_LOCK := false;
else
CLK_STRB <= '0';
end if;
elsif RCV_STATE = IDLE then
-- Preset the CLKDIV with the start delays.
if CDS = "01" then
CLK_DIVCNT := "0001000"; -- Half of div by 16 mode.
elsif CDS = "10" then
CLK_DIVCNT := "0100000"; -- Half of div by 64 mode.
end if;
CLK_STRB <= '0';
else
if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then
CLK_DIVCNT := CLK_DIVCNT - '1';
CLK_STRB <= '0';
CLK_LOCK := true;
elsif CDS = "01" and CLK_DIVCNT = "0000000" then
CLK_DIVCNT := "0010000"; -- Div by 16 mode.
--
if STRB_LOCK = false then
STRB_LOCK := true;
CLK_STRB <= '1';
else
CLK_STRB <= '0';
end if;
elsif CDS = "10" and CLK_DIVCNT = "0000000" then
CLK_DIVCNT := "1000000"; -- Div by 64 mode.
if STRB_LOCK = false then
STRB_LOCK := true;
CLK_STRB <= '1';
else
CLK_STRB <= '0';
end if;
elsif RXCLK = '0' then
CLK_LOCK := false;
STRB_LOCK := false;
CLK_STRB <= '0';
else
CLK_STRB <= '0';
end if;
end if;
end process CLKDIV;
DATAREG: process(RESETn, CLK)
begin
if RESETn = '0' then
DATA_REG <= x"00";
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
DATA_REG <= x"00";
elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data.
-- Transfer from shift- to data register only if
-- data register is empty (RDRF = '0').
DATA_REG <= '0' & SHIFT_REG(7 downto 1);
elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data.
-- Transfer from shift- to data register only if
-- data register is empty (RDRF = '0').
DATA_REG <= SHIFT_REG;
end if;
end if;
end process DATAREG;
DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' and E = '1' else (others => '0');
DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' and E = '1' else '0';
SHIFTREG: process(RESETn, CLK)
begin
if RESETn = '0' then
SHIFT_REG <= x"00";
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
SHIFT_REG <= x"00";
elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then
SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right.
end if;
end if;
end process SHIFTREG;
P_BITCNT: process
begin
wait until CLK = '1' and CLK' event;
if RCV_STATE = SAMPLE and CLK_STRB = '1' then
BITCNT <= BITCNT + '1';
elsif RCV_STATE /= SAMPLE then
BITCNT <= (others => '0');
end if;
end process P_BITCNT;
FRAME_ERR: process(RESETn, CLK)
-- This module detects a framing error
-- during stop bit 1 and stop bit 2.
variable FE_I: bit;
begin
if RESETn = '0' then
FE_I := '0';
FE <= '0';
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
FE_I := '0';
FE <= '0';
elsif CLK_STRB = '1' then
if RCV_STATE = STOP1 and RXDATA_S = '0' then
FE_I := '1';
elsif RCV_STATE = STOP2 and RXDATA_S = '0' then
FE_I := '1';
elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then
FE_I := '0'; -- Error resets when correct data appears.
end if;
end if;
if RCV_STATE = SYNC then
FE <= FE_I; -- Update the FE every SYNC time.
end if;
end if;
end process FRAME_ERR;
OVERRUN: process(RESETn, CLK)
variable OVR_I : bit;
variable FIRST_READ : boolean;
begin
if RESETn = '0' then
OVR_I := '0';
OVR <= '0';
FIRST_READ := false;
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
OVR_I := '0';
OVR <= '0';
FIRST_READ := false;
elsif CLK_STRB = '1' and RCV_STATE = STOP1 then
-- Overrun appears if RDRF is '1' in this state.
OVR_I := RDRF;
end if;
if CS = "011" and RWn = '1' and RS = '1' then
-- If an overrun was detected, the concerning flag is
-- set when the valid data word in the receiver data
-- register is read. Thereafter the RDRF flag is reset
-- and the overrun disappears (OVR_I goes low) after
-- a second read (in time) of the receiver data register.
if FIRST_READ = false then
if OVR_I = '1' then
OVR <= '1';
OVR_I := '0';
FIRST_READ := true;
else
OVR <= '0';
end if;
end if;
else
FIRST_READ := false;
end if;
end if;
end process OVERRUN;
PARITY_TEST: process(RESETn, CLK)
variable PAR_TMP : bit;
variable PE_I : bit;
begin
if RESETn = '0' then
PE <= '0';
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
PE <= '0';
elsif CLK_STRB = '1' then -- Sample parity on clock strobe.
PE_I := '0'; -- Initialise.
if RCV_STATE = PARITY then
for i in 1 to 7 loop
if i = 1 then
PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
else
PAR_TMP := PAR_TMP xor SHIFT_REG(i);
end if;
end loop;
if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
PE_I := PAR_TMP xor RXDATA_S;
elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
PE_I := not PAR_TMP xor RXDATA_S;
else -- No parity for WS = "100" and WS = "101".
PE_I := '0';
end if;
end if;
end if;
-- Transmit the parity flag together with the data
-- In other words: no parity to the status register
-- when RDRF inhibits the data transfer to the
-- receiver data register.
if RCV_STATE = SYNC and RDRF = '0' then
PE <= PE_I;
elsif CS = "011" and RWn = '1' and RS = '1' then
PE <= '0'; -- Clear when reading the data register.
end if;
end if;
end process PARITY_TEST;
P_RDRF: process(RESETn, CLK)
-- Receive data register full flag.
begin
if RESETn = '0' then
RDRF <= '0';
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
RDRF <= '0';
elsif RCV_STATE = SYNC then
RDRF <= '1'; -- Data register is full until now!
elsif CS = "011" and RWn = '1' and RS = '1' then
RDRF <= '0'; -- After reading the data register ...
end if;
end if;
end process P_RDRF;
RCV_STATEREG: process(RESETn, CLK)
begin
if RESETn = '0' then
RCV_STATE <= IDLE;
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
RCV_STATE <= IDLE;
else
RCV_STATE <= RCV_NEXT_STATE;
end if;
end if;
end process RCV_STATEREG;
RCV_STATEDEC: process(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB)
begin
case RCV_STATE is
when IDLE =>
if RXDATA_S = '0' and CDS = "00" then
RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode.
elsif RXDATA_S = '0' and CDS = "01" then
RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode.
elsif RXDATA_S = '0' and CDS = "10" then
RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 64 mode.
else
RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-)
end if;
when WAIT_START =>
if CLK_STRB = '1' then
if RXDATA_S = '0' then
RCV_NEXT_STATE <= SAMPLE; -- Start condition in no div by 1 modes.
else
RCV_NEXT_STATE <= IDLE; -- No valid start condition, go back.
end if;
else
RCV_NEXT_STATE <= WAIT_START; -- Stay.
end if;
when SAMPLE =>
if CLK_STRB = '1' then
if BITCNT < "110" and WS(2) = '0' then
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits.
elsif BITCNT < "111" and WS(2) = '1' then
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits.
elsif WS = "100" or WS = "101" then
RCV_NEXT_STATE <= STOP1; -- No parity check enabled.
else
RCV_NEXT_STATE <= PARITY; -- Parity enabled.
end if;
else
RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode.
end if;
when PARITY =>
if CLK_STRB = '1' then
RCV_NEXT_STATE <= STOP1;
else
RCV_NEXT_STATE <= PARITY;
end if;
when STOP1 =>
if CLK_STRB = '1' then
if RXDATA_S = '0' then
RCV_NEXT_STATE <= SYNC; -- Framing error detected.
elsif WS = "000" or WS = "001" or WS = "100" then
RCV_NEXT_STATE <= STOP2; -- Two stop bits selected.
else
RCV_NEXT_STATE <= SYNC; -- One stop bit selected.
end if;
else
RCV_NEXT_STATE <= STOP1;
end if;
when STOP2 =>
if CLK_STRB = '1' then
RCV_NEXT_STATE <= SYNC;
else
RCV_NEXT_STATE <= STOP2;
end if;
when SYNC =>
RCV_NEXT_STATE <= IDLE;
end case;
end process RCV_STATEDEC;
end architecture BEHAVIOR;

316
FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
View File

@@ -60,7 +60,7 @@ use ieee.std_logic_unsigned.all;
entity WF6850IP_RECEIVE is
port (
CLK : in bit;
CLK : in std_logic;
RESETn : in bit;
MCLR : in bit;
@@ -95,124 +95,127 @@ signal SHIFT_REG : bit_vector(7 downto 0);
signal CLK_STRB : bit;
signal BITCNT : std_logic_vector(2 downto 0);
begin
P_SAMPLE: process
P_SAMPLE: process(CLK)
-- This filter provides a synchronisation to the system
-- clock, even for random baud rates of the received data
-- stream.
variable FLT_TMP : integer range 0 to 2;
begin
wait until CLK = '1' and CLK' event;
--
RXDATA_I <= RXDATA;
--
if RXDATA_I = '1' and FLT_TMP < 2 then
FLT_TMP := FLT_TMP + 1;
elsif RXDATA_I = '1' then
RXDATA_S <= '1';
elsif RXDATA_I = '0' and FLT_TMP > 0 then
FLT_TMP := FLT_TMP - 1;
elsif RXDATA_I = '0' then
RXDATA_S <= '0';
if rising_edge(CLK) then
--
RXDATA_I <= RXDATA;
--
if RXDATA_I = '1' and FLT_TMP < 2 then
FLT_TMP := FLT_TMP + 1;
elsif RXDATA_I = '1' then
RXDATA_S <= '1';
elsif RXDATA_I = '0' and FLT_TMP > 0 then
FLT_TMP := FLT_TMP - 1;
elsif RXDATA_I = '0' then
RXDATA_S <= '0';
end if;
end if;
end process P_SAMPLE;
CLKDIV: process
CLKDIV: process(CLK)
variable CLK_LOCK : boolean;
variable STRB_LOCK : boolean;
variable CLK_DIVCNT : std_logic_vector(6 downto 0);
begin
wait until CLK = '1' and CLK' event;
if CDS = "00" then -- Divider off.
if RXCLK = '1' and STRB_LOCK = false then
CLK_STRB <= '1';
STRB_LOCK := true;
elsif RXCLK = '0' then
CLK_STRB <= '0';
STRB_LOCK := false;
else
CLK_STRB <= '0';
end if;
elsif RCV_STATE = IDLE then
-- Preset the CLKDIV with the start delays.
if CDS = "01" then
CLK_DIVCNT := "0001000"; -- Half of div by 16 mode.
elsif CDS = "10" then
CLK_DIVCNT := "0100000"; -- Half of div by 64 mode.
end if;
CLK_STRB <= '0';
else
if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then
CLK_DIVCNT := CLK_DIVCNT - '1';
CLK_STRB <= '0';
CLK_LOCK := true;
elsif CDS = "01" and CLK_DIVCNT = "0000000" then
CLK_DIVCNT := "0010000"; -- Div by 16 mode.
--
if STRB_LOCK = false then
STRB_LOCK := true;
if rising_edge(CLK) then
if CDS = "00" then -- Divider off.
if RXCLK = '1' and STRB_LOCK = false then
CLK_STRB <= '1';
STRB_LOCK := true;
elsif RXCLK = '0' then
CLK_STRB <= '0';
STRB_LOCK := false;
else
CLK_STRB <= '0';
end if;
elsif CDS = "10" and CLK_DIVCNT = "0000000" then
CLK_DIVCNT := "1000000"; -- Div by 64 mode.
if STRB_LOCK = false then
STRB_LOCK := true;
CLK_STRB <= '1';
else
CLK_STRB <= '0';
elsif RCV_STATE = IDLE then
-- Preset the CLKDIV with the start delays.
if CDS = "01" then
CLK_DIVCNT := "0001000"; -- Half of div by 16 mode.
elsif CDS = "10" then
CLK_DIVCNT := "0100000"; -- Half of div by 64 mode.
end if;
elsif RXCLK = '0' then
CLK_LOCK := false;
STRB_LOCK := false;
CLK_STRB <= '0';
else
CLK_STRB <= '0';
if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then
CLK_DIVCNT := CLK_DIVCNT - '1';
CLK_STRB <= '0';
CLK_LOCK := true;
elsif CDS = "01" and CLK_DIVCNT = "0000000" then
CLK_DIVCNT := "0010000"; -- Div by 16 mode.
--
if STRB_LOCK = false then
STRB_LOCK := true;
CLK_STRB <= '1';
else
CLK_STRB <= '0';
end if;
elsif CDS = "10" and CLK_DIVCNT = "0000000" then
CLK_DIVCNT := "1000000"; -- Div by 64 mode.
if STRB_LOCK = false then
STRB_LOCK := true;
CLK_STRB <= '1';
else
CLK_STRB <= '0';
end if;
elsif RXCLK = '0' then
CLK_LOCK := false;
STRB_LOCK := false;
CLK_STRB <= '0';
else
CLK_STRB <= '0';
end if;
end if;
end if;
end process CLKDIV;
DATAREG: process(RESETn, CLK)
begin
if RESETn = '0' then
if RESETn = '0' or MCLR = '1' then
DATA_REG <= x"00";
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
DATA_REG <= x"00";
elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data.
-- Transfer from shift- to data register only if
-- data register is empty (RDRF = '0').
DATA_REG <= '0' & SHIFT_REG(7 downto 1);
elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data.
-- Transfer from shift- to data register only if
-- data register is empty (RDRF = '0').
DATA_REG <= SHIFT_REG;
else
if rising_edge(CLK) then
if RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data.
-- Transfer from shift- to data register only if
-- data register is empty (RDRF = '0').
DATA_REG <= '0' & SHIFT_REG(7 downto 1);
elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data.
-- Transfer from shift- to data register only if
-- data register is empty (RDRF = '0').
DATA_REG <= SHIFT_REG;
end if;
end if;
end if;
end process DATAREG;
DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' and E = '1' else (others => '0');
DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' and E = '1' else '0';
DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' else (others => '0');
DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' else '0';
SHIFTREG: process(RESETn, CLK)
begin
if RESETn = '0' then
SHIFT_REG <= x"00";
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
SHIFT_REG <= x"00";
elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then
SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right.
if RESETn = '0' or MCLR = '1' then
SHIFT_REG <= x"00";
else
if rising_edge(CLK) then
if RCV_STATE = SAMPLE and CLK_STRB = '1' then
SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right.
end if;
end if;
end if;
end process SHIFTREG;
P_BITCNT: process
P_BITCNT: process(CLK)
begin
wait until CLK = '1' and CLK' event;
if RCV_STATE = SAMPLE and CLK_STRB = '1' then
BITCNT <= BITCNT + '1';
elsif RCV_STATE /= SAMPLE then
BITCNT <= (others => '0');
if rising_edge(CLK) then
if RCV_STATE = SAMPLE and CLK_STRB = '1' then
BITCNT <= BITCNT + '1';
elsif RCV_STATE /= SAMPLE then
BITCNT <= (others => '0');
end if;
end if;
end process P_BITCNT;
@@ -224,84 +227,88 @@ begin
if RESETn = '0' then
FE_I := '0';
FE <= '0';
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
FE_I := '0';
FE <= '0';
elsif CLK_STRB = '1' then
if RCV_STATE = STOP1 and RXDATA_S = '0' then
FE_I := '1';
elsif RCV_STATE = STOP2 and RXDATA_S = '0' then
FE_I := '1';
elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then
FE_I := '0'; -- Error resets when correct data appears.
else
if rising_edge(CLK) then
if MCLR = '1' then
FE_I := '0';
FE <= '0';
elsif CLK_STRB = '1' then
if RCV_STATE = STOP1 and RXDATA_S = '0' then
FE_I := '1';
elsif RCV_STATE = STOP2 and RXDATA_S = '0' then
FE_I := '1';
elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then
FE_I := '0'; -- Error resets when correct data appears.
end if;
end if;
if RCV_STATE = SYNC then
FE <= FE_I; -- Update the FE every SYNC time.
end if;
end if;
if RCV_STATE = SYNC then
FE <= FE_I; -- Update the FE every SYNC time.
end if;
end if;
end process FRAME_ERR;
OVERRUN: process(RESETn, CLK)
variable OVR_I : bit;
variable OVR_I : bit;
variable FIRST_READ : boolean;
begin
if RESETn = '0' then
OVR_I := '0';
OVR <= '0';
FIRST_READ := false;
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
if rising_edge(CLK) then
if RESETn = '0' or MCLR = '1' then
OVR_I := '0';
OVR <= '0';
FIRST_READ := false;
elsif CLK_STRB = '1' and RCV_STATE = STOP1 then
-- Overrun appears if RDRF is '1' in this state.
OVR_I := RDRF;
end if;
if CS = "011" and RWn = '1' and RS = '1' and E = '1' and OVR_I = '1' then
else
if CLK_STRB = '1' and RCV_STATE = STOP1 then
-- Overrun appears if RDRF is '1' in this state.
OVR_I := RDRF;
end if;
if CS = "011" and RWn = '1' and RS = '1' then
-- If an overrun was detected, the concerning flag is
-- set when the valid data word in the receiver data
-- register is read. Thereafter the RDRF flag is reset
-- and the overrun disappears (OVR_I goes low) after
-- a second read (in time) of the receiver data register.
if FIRST_READ = false then
OVR <= '1';
FIRST_READ := true;
else
OVR <= '0';
FIRST_READ := false;
end if;
if FIRST_READ = false then
if OVR_I = '1' then
OVR <= '1';
OVR_I := '0';
FIRST_READ := true;
else
OVR <= '0';
end if;
end if;
else
FIRST_READ := false;
end if;
end if;
end if;
end process OVERRUN;
PARITY_TEST: process(RESETn, CLK)
PARITY_TEST: process(RESETn,MCLR,CLK)
variable PAR_TMP : bit;
variable PE_I : bit;
begin
if RESETn = '0' then
if RESETn = '0' or MCLR = '1' then
PE <= '0';
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
PE <= '0';
elsif CLK_STRB = '1' then -- Sample parity on clock strobe.
PE_I := '0'; -- Initialise.
if RCV_STATE = PARITY then
for i in 1 to 7 loop
if i = 1 then
PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
else
PAR_TMP := PAR_TMP xor SHIFT_REG(i);
end if;
end loop;
if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
PE_I := PAR_TMP xor RXDATA_S;
elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
PE_I := not PAR_TMP xor RXDATA_S;
else -- No parity for WS = "100" and WS = "101".
PE_I := '0';
else
if rising_edge(CLK) then
if CLK_STRB = '1' then -- Sample parity on clock strobe.
PE_I := '0'; -- Initialise.
if RCV_STATE = PARITY then
for i in 1 to 7 loop
if i = 1 then
PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
else
PAR_TMP := PAR_TMP xor SHIFT_REG(i);
end if;
end loop;
if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
PE_I := PAR_TMP xor RXDATA_S;
elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
PE_I := not PAR_TMP xor RXDATA_S;
else -- No parity for WS = "100" and WS = "101".
PE_I := '0';
end if;
end if;
end if;
end if;
@@ -311,7 +318,7 @@ begin
-- receiver data register.
if RCV_STATE = SYNC and RDRF = '0' then
PE <= PE_I;
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
elsif CS = "011" and RWn = '1' and RS = '1' then
PE <= '0'; -- Clear when reading the data register.
end if;
end if;
@@ -320,28 +327,31 @@ begin
P_RDRF: process(RESETn, CLK)
-- Receive data register full flag.
begin
if RESETn = '0' then
RDRF <= '0';
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
RDRF <= '0';
elsif RCV_STATE = SYNC then
RDRF <= '1'; -- Data register is full until now!
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
RDRF <= '0'; -- After reading the data register ...
end if;
end if;
if rising_edge(CLK) then
if RESETn = '0' or MCLR = '1' then
RDRF <= '0';
else
if RCV_STATE = SYNC then
RDRF <= '1'; -- Data register is full until now!
end if;
if CS = "011" and RWn = '1' and RS = '1' then
RDRF <= '0'; -- when reading the data register ...
end if;
end if;
end if;
end process P_RDRF;
RCV_STATEREG: process(RESETn, CLK)
begin
if RESETn = '0' then
RCV_STATE <= IDLE;
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
RCV_STATE <= IDLE;
else
RCV_STATE <= RCV_NEXT_STATE;
else
if rising_edge(CLK) then
if MCLR = '1' then
RCV_STATE <= IDLE;
else
RCV_STATE <= RCV_NEXT_STATE;
end if;
end if;
end if;
end process RCV_STATEREG;

324
FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak
View File

@@ -19,7 +19,7 @@
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2006 Wolfgang Foerster ----
---- Copyright (C) 2006 - 2008 Wolfgang Foerster ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
@@ -48,8 +48,10 @@
--
-- Revision 2K6A 2006/06/03 WF
-- Initial Release.
-- Revision 2K6B 2006/11/07 WF
-- Revision 2K6B 2006/11/07 WF
-- Modified Source to compile with the Xilinx ISE.
-- Revision 2K8A 2008/07/14 WF
-- Minor changes.
--
library ieee;
@@ -58,7 +60,7 @@ use ieee.std_logic_unsigned.all;
entity WF6850IP_RECEIVE is
port (
CLK : in bit;
CLK : in std_logic;
RESETn : in bit;
MCLR : in bit;
@@ -93,126 +95,127 @@ signal SHIFT_REG : bit_vector(7 downto 0);
signal CLK_STRB : bit;
signal BITCNT : std_logic_vector(2 downto 0);
begin
P_SAMPLE: process
P_SAMPLE: process(CLK)
-- This filter provides a synchronisation to the system
-- clock, even for random baud rates of the received data
-- stream.
variable FLT_TMP : integer range 0 to 2;
begin
wait until CLK = '1' and CLK' event;
--
RXDATA_I <= RXDATA;
--
if RXDATA_I = '1' and FLT_TMP < 2 then
FLT_TMP := FLT_TMP + 1;
elsif RXDATA_I = '1' then
RXDATA_S <= '1';
elsif RXDATA_I = '0' and FLT_TMP > 0 then
FLT_TMP := FLT_TMP - 1;
elsif RXDATA_I = '0' then
RXDATA_S <= '0';
if rising_edge(CLK) then
--
RXDATA_I <= RXDATA;
--
if RXDATA_I = '1' and FLT_TMP < 2 then
FLT_TMP := FLT_TMP + 1;
elsif RXDATA_I = '1' then
RXDATA_S <= '1';
elsif RXDATA_I = '0' and FLT_TMP > 0 then
FLT_TMP := FLT_TMP - 1;
elsif RXDATA_I = '0' then
RXDATA_S <= '0';
end if;
end if;
end process P_SAMPLE;
CLKDIV: process
CLKDIV: process(CLK)
variable CLK_LOCK : boolean;
variable STRB_LOCK : boolean;
variable CLK_DIVCNT : std_logic_vector(6 downto 0);
begin
wait until CLK = '1' and CLK' event;
if CDS = "00" then -- Divider off.
if RXCLK = '1' and STRB_LOCK = false then
CLK_STRB <= '1';
STRB_LOCK := true;
elsif RXCLK = '0' then
CLK_STRB <= '0';
STRB_LOCK := false;
else
CLK_STRB <= '0';
end if;
elsif RCV_STATE = IDLE then
-- Preset the CLKDIV with the start delays.
if CDS = "01" then
CLK_DIVCNT := "0001000"; -- Half of div by 16 mode.
elsif CDS = "10" then
CLK_DIVCNT := "0100000"; -- Half of div by 64 mode.
end if;
CLK_STRB <= '0';
else
if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then
CLK_DIVCNT := CLK_DIVCNT - '1';
CLK_STRB <= '0';
CLK_LOCK := true;
elsif CDS = "01" and CLK_DIVCNT = "0000000" then
CLK_DIVCNT := "0010000"; -- Div by 16 mode.
--
if STRB_LOCK = false then
STRB_LOCK := true;
if rising_edge(CLK) then
if CDS = "00" then -- Divider off.
if RXCLK = '1' and STRB_LOCK = false then
CLK_STRB <= '1';
STRB_LOCK := true;
elsif RXCLK = '0' then
CLK_STRB <= '0';
STRB_LOCK := false;
else
CLK_STRB <= '0';
end if;
elsif CDS = "10" and CLK_DIVCNT = "0000000" then
CLK_DIVCNT := "1000000"; -- Div by 64 mode.
if STRB_LOCK = false then
STRB_LOCK := true;
CLK_STRB <= '1';
else
CLK_STRB <= '0';
elsif RCV_STATE = IDLE then
-- Preset the CLKDIV with the start delays.
if CDS = "01" then
CLK_DIVCNT := "0001000"; -- Half of div by 16 mode.
elsif CDS = "10" then
CLK_DIVCNT := "0100000"; -- Half of div by 64 mode.
end if;
elsif RXCLK = '0' then
CLK_LOCK := false;
STRB_LOCK := false;
CLK_STRB <= '0';
else
CLK_STRB <= '0';
if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then
CLK_DIVCNT := CLK_DIVCNT - '1';
CLK_STRB <= '0';
CLK_LOCK := true;
elsif CDS = "01" and CLK_DIVCNT = "0000000" then
CLK_DIVCNT := "0010000"; -- Div by 16 mode.
--
if STRB_LOCK = false then
STRB_LOCK := true;
CLK_STRB <= '1';
else
CLK_STRB <= '0';
end if;
elsif CDS = "10" and CLK_DIVCNT = "0000000" then
CLK_DIVCNT := "1000000"; -- Div by 64 mode.
if STRB_LOCK = false then
STRB_LOCK := true;
CLK_STRB <= '1';
else
CLK_STRB <= '0';
end if;
elsif RXCLK = '0' then
CLK_LOCK := false;
STRB_LOCK := false;
CLK_STRB <= '0';
else
CLK_STRB <= '0';
end if;
end if;
end if;
end process CLKDIV;
DATAREG: process(RESETn, CLK)
begin
if RESETn = '0' then
if RESETn = '0' or MCLR = '1' then
DATA_REG <= x"00";
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
DATA_REG <= x"00";
elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data.
-- Transfer from shift- to data register only if
-- data register is empty (RDRF = '0').
DATA_REG <= '0' & SHIFT_REG(7 downto 1);
elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data.
-- Transfer from shift- to data register only if
-- data register is empty (RDRF = '0').
DATA_REG <= SHIFT_REG;
else
if rising_edge(CLK) then
if RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data.
-- Transfer from shift- to data register only if
-- data register is empty (RDRF = '0').
DATA_REG <= '0' & SHIFT_REG(7 downto 1);
elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data.
-- Transfer from shift- to data register only if
-- data register is empty (RDRF = '0').
DATA_REG <= SHIFT_REG;
end if;
end if;
end if;
end process DATAREG;
--DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' and E = '1' else (others => '0');
--DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' and E = '1' else '0';
DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' else (others => '0');
DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' else '0';
DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' else (others => '0');
DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' else '0';
SHIFTREG: process(RESETn, CLK)
begin
if RESETn = '0' then
SHIFT_REG <= x"00";
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
SHIFT_REG <= x"00";
elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then
SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right.
if RESETn = '0' or MCLR = '1' then
SHIFT_REG <= x"00";
else
if rising_edge(CLK) then
if RCV_STATE = SAMPLE and CLK_STRB = '1' then
SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right.
end if;
end if;
end if;
end process SHIFTREG;
P_BITCNT: process
P_BITCNT: process(CLK)
begin
wait until CLK = '1' and CLK' event;
if RCV_STATE = SAMPLE and CLK_STRB = '1' then
BITCNT <= BITCNT + '1';
elsif RCV_STATE /= SAMPLE then
BITCNT <= (others => '0');
if rising_edge(CLK) then
if RCV_STATE = SAMPLE and CLK_STRB = '1' then
BITCNT <= BITCNT + '1';
elsif RCV_STATE /= SAMPLE then
BITCNT <= (others => '0');
end if;
end if;
end process P_BITCNT;
@@ -224,84 +227,88 @@ DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' else '0';
if RESETn = '0' then
FE_I := '0';
FE <= '0';
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
FE_I := '0';
FE <= '0';
elsif CLK_STRB = '1' then
if RCV_STATE = STOP1 and RXDATA_S = '0' then
FE_I := '1';
elsif RCV_STATE = STOP2 and RXDATA_S = '0' then
FE_I := '1';
elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then
FE_I := '0'; -- Error resets when correct data appears.
else
if rising_edge(CLK) then
if MCLR = '1' then
FE_I := '0';
FE <= '0';
elsif CLK_STRB = '1' then
if RCV_STATE = STOP1 and RXDATA_S = '0' then
FE_I := '1';
elsif RCV_STATE = STOP2 and RXDATA_S = '0' then
FE_I := '1';
elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then
FE_I := '0'; -- Error resets when correct data appears.
end if;
end if;
if RCV_STATE = SYNC then
FE <= FE_I; -- Update the FE every SYNC time.
end if;
end if;
if RCV_STATE = SYNC then
FE <= FE_I; -- Update the FE every SYNC time.
end if;
end if;
end process FRAME_ERR;
OVERRUN: process(RESETn, CLK)
variable OVR_I : bit;
variable OVR_I : bit;
variable FIRST_READ : boolean;
begin
if RESETn = '0' then
OVR_I := '0';
OVR <= '0';
FIRST_READ := false;
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
if rising_edge(CLK) then
if RESETn = '0' or MCLR = '1' then
OVR_I := '0';
OVR <= '0';
FIRST_READ := false;
elsif CLK_STRB = '1' and RCV_STATE = STOP1 then
-- Overrun appears if RDRF is '1' in this state.
OVR_I := RDRF;
end if;
if CS = "011" and RWn = '1' and RS = '1' and E = '1' and OVR_I = '1' then
else
if CLK_STRB = '1' and RCV_STATE = STOP1 then
-- Overrun appears if RDRF is '1' in this state.
OVR_I := RDRF;
end if;
if CS = "011" and RWn = '1' and RS = '1' then
-- If an overrun was detected, the concerning flag is
-- set when the valid data word in the receiver data
-- register is read. Thereafter the RDRF flag is reset
-- and the overrun disappears (OVR_I goes low) after
-- a second read (in time) of the receiver data register.
if FIRST_READ = false then
OVR <= '1';
FIRST_READ := true;
else
OVR <= '0';
FIRST_READ := false;
end if;
if FIRST_READ = false then
if OVR_I = '1' then
OVR <= '1';
OVR_I := '0';
FIRST_READ := true;
else
OVR <= '0';
end if;
end if;
else
FIRST_READ := false;
end if;
end if;
end if;
end process OVERRUN;
PARITY_TEST: process(RESETn, CLK)
PARITY_TEST: process(RESETn,MCLR,CLK)
variable PAR_TMP : bit;
variable PE_I : bit;
begin
if RESETn = '0' then
if RESETn = '0' or MCRL = '1' then
PE <= '0';
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
PE <= '0';
elsif CLK_STRB = '1' then -- Sample parity on clock strobe.
PE_I := '0'; -- Initialise.
if RCV_STATE = PARITY then
for i in 1 to 7 loop
if i = 1 then
PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
else
PAR_TMP := PAR_TMP xor SHIFT_REG(i);
end if;
end loop;
if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
PE_I := PAR_TMP xor RXDATA_S;
elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
PE_I := not PAR_TMP xor RXDATA_S;
else -- No parity for WS = "100" and WS = "101".
PE_I := '0';
else
if rising_edge(CLK) then
if CLK_STRB = '1' then -- Sample parity on clock strobe.
PE_I := '0'; -- Initialise.
if RCV_STATE = PARITY then
for i in 1 to 7 loop
if i = 1 then
PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
else
PAR_TMP := PAR_TMP xor SHIFT_REG(i);
end if;
end loop;
if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
PE_I := PAR_TMP xor RXDATA_S;
elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
PE_I := not PAR_TMP xor RXDATA_S;
else -- No parity for WS = "100" and WS = "101".
PE_I := '0';
end if;
end if;
end if;
end if;
@@ -311,7 +318,7 @@ DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' else '0';
-- receiver data register.
if RCV_STATE = SYNC and RDRF = '0' then
PE <= PE_I;
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
elsif CS = "011" and RWn = '1' and RS = '1' then
PE <= '0'; -- Clear when reading the data register.
end if;
end if;
@@ -320,28 +327,31 @@ DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' else '0';
P_RDRF: process(RESETn, CLK)
-- Receive data register full flag.
begin
if RESETn = '0' then
RDRF <= '0';
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
RDRF <= '0';
elsif RCV_STATE = SYNC then
RDRF <= '1'; -- Data register is full until now!
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
RDRF <= '0'; -- After reading the data register ...
end if;
end if;
if rising_edge(CLK) then
if RESETn = '0' or MCLR = '1' then
RDRF <= '0';
else
if RCV_STATE = SYNC then
RDRF <= '1'; -- Data register is full until now!
end if;
if CS = "011" and RWn = '1' and RS = '1' then
RDRF <= '0'; -- when reading the data register ...
end if;
end if;
end if;
end process P_RDRF;
RCV_STATEREG: process(RESETn, CLK)
begin
if RESETn = '0' then
RCV_STATE <= IDLE;
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
RCV_STATE <= IDLE;
else
RCV_STATE <= RCV_NEXT_STATE;
else
if rising_edge(CLK) then
if MCLR = '1' then
RCV_STATE <= IDLE;
else
RCV_STATE <= RCV_NEXT_STATE;
end if;
end if;
end if;
end process RCV_STATEREG;

147
FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
View File

@@ -63,7 +63,7 @@ use ieee.std_logic_unsigned.all;
entity WF6850IP_TRANSMIT is
port (
CLK : in bit;
CLK : in std_logic;
RESETn : in bit;
MCLR : in bit;
@@ -108,58 +108,59 @@ begin
'1' when TR_STATE = STOP1 else
'1' when TR_STATE = STOP2 else '1';
CLKDIV: process
CLKDIV: process(CLK)
variable CLK_LOCK : boolean;
variable STRB_LOCK : boolean;
variable CLK_DIVCNT : std_logic_vector(6 downto 0);
begin
wait until CLK = '1' and CLK' event;
if CDS = "00" then -- divider off
if TXCLK = '0' and STRB_LOCK = false then -- Works on negative TXCLK edge.
CLK_STRB <= '1';
STRB_LOCK := true;
elsif TXCLK = '1' then
CLK_STRB <= '0';
STRB_LOCK := false;
else
CLK_STRB <= '0';
end if;
elsif TR_STATE = IDLE then
-- preset the CLKDIV with the start delays
if CDS = "01" then
CLK_DIVCNT := "0010000"; -- div by 16 mode
elsif CDS = "10" then
CLK_DIVCNT := "1000000"; -- div by 64 mode
end if;
CLK_STRB <= '0';
else
-- Works on negative TXCLK edge:
if CLK_DIVCNT > "0000000" and TXCLK = '0' and CLK_LOCK = false then
CLK_DIVCNT := CLK_DIVCNT - '1';
CLK_STRB <= '0';
CLK_LOCK := true;
elsif CDS = "01" and CLK_DIVCNT = "0000000" then
CLK_DIVCNT := "0010000"; -- Div by 16 mode.
if STRB_LOCK = false then
STRB_LOCK := true;
if rising_edge(CLK) then
if CDS = "00" then -- divider off
if TXCLK = '0' and STRB_LOCK = false then -- Works on negative TXCLK edge.
CLK_STRB <= '1';
STRB_LOCK := true;
elsif TXCLK = '1' then
CLK_STRB <= '0';
STRB_LOCK := false;
else
CLK_STRB <= '0';
end if;
elsif CDS = "10" and CLK_DIVCNT = "0000000" then
CLK_DIVCNT := "1000000"; -- Div by 64 mode.
if STRB_LOCK = false then
STRB_LOCK := true;
CLK_STRB <= '1';
else
CLK_STRB <= '0';
elsif TR_STATE = IDLE then
-- preset the CLKDIV with the start delays
if CDS = "01" then
CLK_DIVCNT := "0010000"; -- div by 16 mode
elsif CDS = "10" then
CLK_DIVCNT := "1000000"; -- div by 64 mode
end if;
elsif TXCLK = '1' then
CLK_LOCK := false;
STRB_LOCK := false;
CLK_STRB <= '0';
else
CLK_STRB <= '0';
-- Works on negative TXCLK edge:
if CLK_DIVCNT > "0000000" and TXCLK = '0' and CLK_LOCK = false then
CLK_DIVCNT := CLK_DIVCNT - '1';
CLK_STRB <= '0';
CLK_LOCK := true;
elsif CDS = "01" and CLK_DIVCNT = "0000000" then
CLK_DIVCNT := "0010000"; -- Div by 16 mode.
if STRB_LOCK = false then
STRB_LOCK := true;
CLK_STRB <= '1';
else
CLK_STRB <= '0';
end if;
elsif CDS = "10" and CLK_DIVCNT = "0000000" then
CLK_DIVCNT := "1000000"; -- Div by 64 mode.
if STRB_LOCK = false then
STRB_LOCK := true;
CLK_STRB <= '1';
else
CLK_STRB <= '0';
end if;
elsif TXCLK = '1' then
CLK_LOCK := false;
STRB_LOCK := false;
CLK_STRB <= '0';
else
CLK_STRB <= '0';
end if;
end if;
end if;
end process CLKDIV;
@@ -168,7 +169,7 @@ begin
begin
if RESETn = '0' then
DATA_REG <= x"00";
elsif CLK = '1' and CLK' event then
elsif rising_edge(CLK) then
if MCLR = '1' then
DATA_REG <= x"00";
elsif WS(2) = '0' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then
@@ -183,7 +184,7 @@ begin
begin
if RESETn = '0' then
SHIFT_REG <= x"00";
elsif CLK = '1' and CLK' event then
elsif rising_edge(CLK) then
if MCLR = '1' then
SHIFT_REG <= x"00";
elsif TR_STATE = LOAD_SHFT and TDRE = '0' then
@@ -198,47 +199,42 @@ begin
end if;
end process SHIFTREG;
P_BITCNT: process
P_BITCNT: process(CLK)
-- Counter for the data bits transmitted.
begin
wait until CLK = '1' and CLK' event;
if TR_STATE = SHIFTOUT and CLK_STRB = '1' then
BITCNT <= BITCNT + '1';
elsif TR_STATE /= SHIFTOUT then
BITCNT <= "000";
if rising_edge(CLK) then
if TR_STATE = SHIFTOUT and CLK_STRB = '1' then
BITCNT <= BITCNT + '1';
elsif TR_STATE /= SHIFTOUT then
BITCNT <= "000";
end if;
end if;
end process P_BITCNT;
P_TDRE: process(RESETn, CLK)
-- Transmit data register empty flag.
variable LOCK : boolean;
begin
if RESETn = '0' then
TDRE <= '1';
LOCK := false;
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
TDRE <= '1';
elsif TR_NEXT_STATE = START and TR_STATE /= START then
if rising_edge(CLK) then
if RESETn = '0' or MCLR = '1' then
TDRE <= '1';
else
if TR_NEXT_STATE = START and TR_STATE /= START then
-- Data has been loaded to shift register, thus data register is free again.
-- Thanks to Lyndon Amsdon for finding a bug here. The TDRE is set to one once
-- entering the state now.
TDRE <= '1';
elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' and LOCK = false then
LOCK := true;
elsif E = '0' and LOCK = true then
-- This construction clears TDRE after the falling edge of E
-- and after the transmit data register has been written to.
TDRE <= '0';
LOCK := false;
-- entering the state now.
TDRE <= '1';
end if;
if CS = "011" and RWn = '0' and RS = '1' then
TDRE <= '0';
end if;
end if;
end if;
end process P_TDRE;
PARITY_GEN: process
PARITY_GEN: process(CLK)
variable PAR_TMP : bit;
begin
wait until CLK = '1' and CLK' event;
if rising_edge(CLK) then
if TR_STATE = START then -- Calculate the parity during the start phase.
for i in 1 to 7 loop
if i = 1 then
@@ -254,6 +250,7 @@ begin
else -- No parity for WS = "100" and WS = "101".
PARITY_I <= '0';
end if;
end if;
end if;
end process PARITY_GEN;
@@ -261,11 +258,13 @@ begin
begin
if RESETn = '0' then
TR_STATE <= IDLE;
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
TR_STATE <= IDLE;
else
TR_STATE <= TR_NEXT_STATE;
else
if rising_edge(CLK) then
if MCLR = '1' then
TR_STATE <= IDLE;
else
TR_STATE <= TR_NEXT_STATE;
end if;
end if;
end if;
end process TR_STATEREG;

145
FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak
View File

@@ -63,7 +63,7 @@ use ieee.std_logic_unsigned.all;
entity WF6850IP_TRANSMIT is
port (
CLK : in bit;
CLK : in std_logic;
RESETn : in bit;
MCLR : in bit;
@@ -113,53 +113,54 @@ begin
variable STRB_LOCK : boolean;
variable CLK_DIVCNT : std_logic_vector(6 downto 0);
begin
wait until CLK = '1' and CLK' event;
if CDS = "00" then -- divider off
if TXCLK = '0' and STRB_LOCK = false then -- Works on negative TXCLK edge.
CLK_STRB <= '1';
STRB_LOCK := true;
elsif TXCLK = '1' then
CLK_STRB <= '0';
STRB_LOCK := false;
else
CLK_STRB <= '0';
end if;
elsif TR_STATE = IDLE then
-- preset the CLKDIV with the start delays
if CDS = "01" then
CLK_DIVCNT := "0010000"; -- div by 16 mode
elsif CDS = "10" then
CLK_DIVCNT := "1000000"; -- div by 64 mode
end if;
CLK_STRB <= '0';
else
-- Works on negative TXCLK edge:
if CLK_DIVCNT > "0000000" and TXCLK = '0' and CLK_LOCK = false then
CLK_DIVCNT := CLK_DIVCNT - '1';
CLK_STRB <= '0';
CLK_LOCK := true;
elsif CDS = "01" and CLK_DIVCNT = "0000000" then
CLK_DIVCNT := "0010000"; -- Div by 16 mode.
if STRB_LOCK = false then
STRB_LOCK := true;
if rising_edge(CLK) then
if CDS = "00" then -- divider off
if TXCLK = '0' and STRB_LOCK = false then -- Works on negative TXCLK edge.
CLK_STRB <= '1';
STRB_LOCK := true;
elsif TXCLK = '1' then
CLK_STRB <= '0';
STRB_LOCK := false;
else
CLK_STRB <= '0';
end if;
elsif CDS = "10" and CLK_DIVCNT = "0000000" then
CLK_DIVCNT := "1000000"; -- Div by 64 mode.
if STRB_LOCK = false then
STRB_LOCK := true;
CLK_STRB <= '1';
else
CLK_STRB <= '0';
elsif TR_STATE = IDLE then
-- preset the CLKDIV with the start delays
if CDS = "01" then
CLK_DIVCNT := "0010000"; -- div by 16 mode
elsif CDS = "10" then
CLK_DIVCNT := "1000000"; -- div by 64 mode
end if;
elsif TXCLK = '1' then
CLK_LOCK := false;
STRB_LOCK := false;
CLK_STRB <= '0';
else
CLK_STRB <= '0';
-- Works on negative TXCLK edge:
if CLK_DIVCNT > "0000000" and TXCLK = '0' and CLK_LOCK = false then
CLK_DIVCNT := CLK_DIVCNT - '1';
CLK_STRB <= '0';
CLK_LOCK := true;
elsif CDS = "01" and CLK_DIVCNT = "0000000" then
CLK_DIVCNT := "0010000"; -- Div by 16 mode.
if STRB_LOCK = false then
STRB_LOCK := true;
CLK_STRB <= '1';
else
CLK_STRB <= '0';
end if;
elsif CDS = "10" and CLK_DIVCNT = "0000000" then
CLK_DIVCNT := "1000000"; -- Div by 64 mode.
if STRB_LOCK = false then
STRB_LOCK := true;
CLK_STRB <= '1';
else
CLK_STRB <= '0';
end if;
elsif TXCLK = '1' then
CLK_LOCK := false;
STRB_LOCK := false;
CLK_STRB <= '0';
else
CLK_STRB <= '0';
end if;
end if;
end if;
end process CLKDIV;
@@ -168,7 +169,7 @@ begin
begin
if RESETn = '0' then
DATA_REG <= x"00";
elsif CLK = '1' and CLK' event then
elsif rising_edge(CLK) then
if MCLR = '1' then
DATA_REG <= x"00";
elsif WS(2) = '0' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then
@@ -183,7 +184,7 @@ begin
begin
if RESETn = '0' then
SHIFT_REG <= x"00";
elsif CLK = '1' and CLK' event then
elsif rising_edge(CLK) then
if MCLR = '1' then
SHIFT_REG <= x"00";
elsif TR_STATE = LOAD_SHFT and TDRE = '0' then
@@ -198,47 +199,42 @@ begin
end if;
end process SHIFTREG;
P_BITCNT: process
P_BITCNT: process(CLK)
-- Counter for the data bits transmitted.
begin
wait until CLK = '1' and CLK' event;
if TR_STATE = SHIFTOUT and CLK_STRB = '1' then
BITCNT <= BITCNT + '1';
elsif TR_STATE /= SHIFTOUT then
BITCNT <= "000";
if rising_edge(CLK) then
if TR_STATE = SHIFTOUT and CLK_STRB = '1' then
BITCNT <= BITCNT + '1';
elsif TR_STATE /= SHIFTOUT then
BITCNT <= "000";
end if;
end if;
end process P_BITCNT;
P_TDRE: process(RESETn, CLK)
-- Transmit data register empty flag.
variable LOCK : boolean;
begin
if RESETn = '0' then
TDRE <= '1';
LOCK := false;
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
TDRE <= '1';
elsif TR_NEXT_STATE = START and TR_STATE /= START then
if rising_edge(CLK) then
if RESETn = '0' or MCLR = '1' then
TDRE <= '1';
else
if TR_NEXT_STATE = START and TR_STATE /= START then
-- Data has been loaded to shift register, thus data register is free again.
-- Thanks to Lyndon Amsdon for finding a bug here. The TDRE is set to one once
-- entering the state now.
TDRE <= '1';
elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' and LOCK = false then
LOCK := true;
elsif E = '0' and LOCK = true and CS /= "011" then
-- This construction clears TDRE after the falling edge of E
-- and after the transmit data register has been written to.
TDRE <= '0';
LOCK := false;
-- entering the state now.
TDRE <= '1';
end if;
if CS = "011" and RWn = '0' and RS = '1' then
TDRE <= '0';
end if;
end if;
end if;
end process P_TDRE;
PARITY_GEN: process
PARITY_GEN: process(CLK)
variable PAR_TMP : bit;
begin
wait until CLK = '1' and CLK' event;
if rising_edge(CLK) then
if TR_STATE = START then -- Calculate the parity during the start phase.
for i in 1 to 7 loop
if i = 1 then
@@ -254,6 +250,7 @@ begin
else -- No parity for WS = "100" and WS = "101".
PARITY_I <= '0';
end if;
end if;
end if;
end process PARITY_GEN;
@@ -261,11 +258,13 @@ begin
begin
if RESETn = '0' then
TR_STATE <= IDLE;
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
TR_STATE <= IDLE;
else
TR_STATE <= TR_NEXT_STATE;
else
if rising_edge(CLK) then
if MCLR = '1' then
TR_STATE <= IDLE;
else
TR_STATE <= TR_NEXT_STATE;
end if;
end if;
end if;
end process TR_STATEREG;

182
FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf
View File

@@ -37,6 +37,7 @@ SUBDESIGN interrupt_handler
VSYNC : INPUT;
HSYNC : INPUT;
DMA_DRQ : INPUT;
nRSTO : INPUT;
nIRQ[7..2] : OUTPUT;
INT_HANDLER_TA : OUTPUT;
ACP_CONF[31..0] : OUTPUT;
@@ -56,6 +57,8 @@ VARIABLE
INT_IN[31..0] :NODE;
INT_ENA[31..0] :DFFE;
INT_ENA_CS :NODE;
INT_L[9..0] :DFF;
INT_LA[9..0][3..0] :DFF;
ACP_CONF[31..0] :DFFE;
ACP_CONF_CS :NODE;
PSEUDO_BUS_ERROR :NODE;
@@ -101,6 +104,7 @@ BEGIN
INT_CTR[7..0].ENA = INT_CTR_CS & FB_B3 & !nFB_WR;
-- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
INT_ENA[].CLK = MAIN_CLK;
INT_ENA[].CLRN = nRSTO;
INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001"; -- $10004/4
INT_ENA[] = FB_AD[];
INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR;
@@ -120,15 +124,15 @@ BEGIN
!nIRQ2 = HSYNC & INT_ENA[26];
!nIRQ3 = INT_CTR0 & INT_ENA[27];
!nIRQ4 = VSYNC & INT_ENA[28];
nIRQ5 = INT_LATCH[]==H"00000000" & INT_ENA[29];
!nIRQ5 = INT_LATCH[]!=H"00000000" & INT_ENA[29];
!nIRQ6 = !nMFP_INT & INT_ENA[30];
!nIRQ7 = PSEUDO_BUS_ERROR & INT_ENA[31];
PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC
# FB_ADR[19..4]==H"F8E0" -- VME
# FB_ADR[19..4]==H"F920" -- PADDLE
# FB_ADR[19..4]==H"F921" -- PADDLE
# FB_ADR[19..4]==H"F922" -- PADDLE
-- # FB_ADR[19..4]==H"F920" -- PADDLE
-- # FB_ADR[19..4]==H"F921" -- PADDLE
-- # FB_ADR[19..4]==H"F922" -- PADDLE
# FB_ADR[19..4]==H"FFA8" -- MFP2
# FB_ADR[19..4]==H"FFA9" -- MFP2
# FB_ADR[19..4]==H"FFAA" -- MFP2
@@ -136,27 +140,38 @@ PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC
# FB_ADR[19..8]==H"F87" -- TT SCSI
# FB_ADR[19..4]==H"FFC2" -- ST UHR
# FB_ADR[19..4]==H"FFC3" -- ST UHR
# FB_ADR[19..4]==H"F890" -- DMA SOUND
# FB_ADR[19..4]==H"F891" -- DMA SOUND
# FB_ADR[19..4]==H"F892"); -- DMA SOUND
-- # FB_ADR[19..4]==H"F890" -- DMA SOUND
-- # FB_ADR[19..4]==H"F891" -- DMA SOUND
-- # FB_ADR[19..4]==H"F892" -- DMA SOUND
);
-- IF VIDEO ADR CHANGE
TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2
-- INTERRUPT LATCH
INT_LATCH[] = H"FFFFFFFF";
INT_LATCH0.CLK = PIC_INT & INT_ENA[0];
INT_LATCH1.CLK = E0_INT & INT_ENA[1];
INT_LATCH2.CLK = DVI_INT & INT_ENA[2];
INT_LATCH3.CLK = !nPCI_INTA & INT_ENA[3];
INT_LATCH4.CLK = !nPCI_INTB & INT_ENA[4];
INT_LATCH5.CLK = !nPCI_INTC & INT_ENA[5];
INT_LATCH6.CLK = !nPCI_INTD & INT_ENA[6];
INT_LATCH7.CLK = DSP_INT & INT_ENA[7];
INT_LATCH8.CLK = VSYNC & INT_ENA[8];
INT_LATCH9.CLK = HSYNC & INT_ENA[9];
INT_L[].CLK = MAIN_CLK;
INT_L[].CLRN = nRSTO;
INT_L0 = PIC_INT & INT_ENA[0];
INT_L1 = E0_INT & INT_ENA[1];
INT_L2 = DVI_INT & INT_ENA[2];
INT_L3 = !nPCI_INTA & INT_ENA[3];
INT_L4 = !nPCI_INTB & INT_ENA[4];
INT_L5 = !nPCI_INTC & INT_ENA[5];
INT_L6 = !nPCI_INTD & INT_ENA[6];
INT_L7 = DSP_INT & INT_ENA[7];
INT_L8 = VSYNC & INT_ENA[8];
INT_L9 = HSYNC & INT_ENA[9];
-- INTERRUPT CLEAR
INT_LATCH[].CLRN = !INT_CLEAR[];
INT_LA[][].CLK = MAIN_CLK;
INT_LATCH[] = H"FFFFFFFF";
INT_LATCH[].CLRN = !INT_CLEAR[] & nRSTO;
FOR I IN 0 TO 9 GENERATE
INT_LA[I][].CLRN = INT_ENA[I] & nRSTO;
INT_LA[I][] = INT_LA[I][]+1 & INT_L[I] & INT_LA[I][]<7
# INT_LA[I][]-1 & !INT_L[I] & INT_LA[I][]>8
# 15 & INT_L[I] & INT_LA[I][]>6
# 0 & !INT_L[I] & INT_LA[I][]<9;
INT_LATCH[I].CLK = INT_LA[I][3];
END GENERATE;
-- INT_IN
INT_IN0 = PIC_INT;
@@ -206,125 +221,14 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H
WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR;
WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR;
WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR;
WERTE[7..0][10] = FB_AD[23..16];
WERTE[7..0][11] = FB_AD[23..16];
WERTE[7..0][12] = FB_AD[23..16];
WERTE[7..0][13] = FB_AD[23..16];
WERTE[7..0][14] = FB_AD[23..16];
WERTE[7..0][15] = FB_AD[23..16];
WERTE[7..0][16] = FB_AD[23..16];
WERTE[7..0][17] = FB_AD[23..16];
WERTE[7..0][18] = FB_AD[23..16];
WERTE[7..0][19] = FB_AD[23..16];
WERTE[7..0][20] = FB_AD[23..16];
WERTE[7..0][21] = FB_AD[23..16];
WERTE[7..0][22] = FB_AD[23..16];
WERTE[7..0][23] = FB_AD[23..16];
WERTE[7..0][24] = FB_AD[23..16];
WERTE[7..0][25] = FB_AD[23..16];
WERTE[7..0][26] = FB_AD[23..16];
WERTE[7..0][27] = FB_AD[23..16];
WERTE[7..0][28] = FB_AD[23..16];
WERTE[7..0][29] = FB_AD[23..16];
WERTE[7..0][30] = FB_AD[23..16];
WERTE[7..0][31] = FB_AD[23..16];
WERTE[7..0][32] = FB_AD[23..16];
WERTE[7..0][33] = FB_AD[23..16];
WERTE[7..0][34] = FB_AD[23..16];
WERTE[7..0][35] = FB_AD[23..16];
WERTE[7..0][36] = FB_AD[23..16];
WERTE[7..0][37] = FB_AD[23..16];
WERTE[7..0][38] = FB_AD[23..16];
WERTE[7..0][39] = FB_AD[23..16];
WERTE[7..0][40] = FB_AD[23..16];
WERTE[7..0][41] = FB_AD[23..16];
WERTE[7..0][42] = FB_AD[23..16];
WERTE[7..0][43] = FB_AD[23..16];
WERTE[7..0][44] = FB_AD[23..16];
WERTE[7..0][45] = FB_AD[23..16];
WERTE[7..0][46] = FB_AD[23..16];
WERTE[7..0][47] = FB_AD[23..16];
WERTE[7..0][48] = FB_AD[23..16];
WERTE[7..0][49] = FB_AD[23..16];
WERTE[7..0][50] = FB_AD[23..16];
WERTE[7..0][51] = FB_AD[23..16];
WERTE[7..0][52] = FB_AD[23..16];
WERTE[7..0][53] = FB_AD[23..16];
WERTE[7..0][54] = FB_AD[23..16];
WERTE[7..0][55] = FB_AD[23..16];
WERTE[7..0][56] = FB_AD[23..16];
WERTE[7..0][57] = FB_AD[23..16];
WERTE[7..0][58] = FB_AD[23..16];
WERTE[7..0][59] = FB_AD[23..16];
WERTE[7..0][60] = FB_AD[23..16];
WERTE[7..0][61] = FB_AD[23..16];
WERTE[7..0][62] = FB_AD[23..16];
WERTE[7..0][63] = FB_AD[23..16];
WERTE[][0].ENA = RTC_ADR[]==0 & UHR_DS & !nFB_WR;
WERTE[][1].ENA = RTC_ADR[]==1 & UHR_DS & !nFB_WR;
WERTE[][2].ENA = RTC_ADR[]==2 & UHR_DS & !nFB_WR;
WERTE[][3].ENA = RTC_ADR[]==3 & UHR_DS & !nFB_WR;
WERTE[][4].ENA = RTC_ADR[]==4 & UHR_DS & !nFB_WR;
WERTE[][5].ENA = RTC_ADR[]==5 & UHR_DS & !nFB_WR;
WERTE[][6].ENA = RTC_ADR[]==6 & UHR_DS & !nFB_WR;
WERTE[][7].ENA = RTC_ADR[]==7 & UHR_DS & !nFB_WR;
WERTE[][8].ENA = RTC_ADR[]==8 & UHR_DS & !nFB_WR;
WERTE[][9].ENA = RTC_ADR[]==9 & UHR_DS & !nFB_WR;
WERTE[][10].ENA = RTC_ADR[]==10 & UHR_DS & !nFB_WR;
WERTE[][11].ENA = RTC_ADR[]==11 & UHR_DS & !nFB_WR;
WERTE[][12].ENA = RTC_ADR[]==12 & UHR_DS & !nFB_WR;
WERTE[][13].ENA = RTC_ADR[]==13 & UHR_DS & !nFB_WR;
WERTE[][14].ENA = RTC_ADR[]==14 & UHR_DS & !nFB_WR;
WERTE[][15].ENA = RTC_ADR[]==15 & UHR_DS & !nFB_WR;
WERTE[][16].ENA = RTC_ADR[]==16 & UHR_DS & !nFB_WR;
WERTE[][17].ENA = RTC_ADR[]==17 & UHR_DS & !nFB_WR;
WERTE[][18].ENA = RTC_ADR[]==18 & UHR_DS & !nFB_WR;
WERTE[][19].ENA = RTC_ADR[]==19 & UHR_DS & !nFB_WR;
WERTE[][20].ENA = RTC_ADR[]==20 & UHR_DS & !nFB_WR;
WERTE[][21].ENA = RTC_ADR[]==21 & UHR_DS & !nFB_WR;
WERTE[][22].ENA = RTC_ADR[]==22 & UHR_DS & !nFB_WR;
WERTE[][23].ENA = RTC_ADR[]==23 & UHR_DS & !nFB_WR;
WERTE[][24].ENA = RTC_ADR[]==24 & UHR_DS & !nFB_WR;
WERTE[][25].ENA = RTC_ADR[]==25 & UHR_DS & !nFB_WR;
WERTE[][26].ENA = RTC_ADR[]==26 & UHR_DS & !nFB_WR;
WERTE[][27].ENA = RTC_ADR[]==27 & UHR_DS & !nFB_WR;
WERTE[][28].ENA = RTC_ADR[]==28 & UHR_DS & !nFB_WR;
WERTE[][29].ENA = RTC_ADR[]==29 & UHR_DS & !nFB_WR;
WERTE[][30].ENA = RTC_ADR[]==30 & UHR_DS & !nFB_WR;
WERTE[][31].ENA = RTC_ADR[]==31 & UHR_DS & !nFB_WR;
WERTE[][32].ENA = RTC_ADR[]==32 & UHR_DS & !nFB_WR;
WERTE[][33].ENA = RTC_ADR[]==33 & UHR_DS & !nFB_WR;
WERTE[][34].ENA = RTC_ADR[]==34 & UHR_DS & !nFB_WR;
WERTE[][35].ENA = RTC_ADR[]==35 & UHR_DS & !nFB_WR;
WERTE[][36].ENA = RTC_ADR[]==36 & UHR_DS & !nFB_WR;
WERTE[][37].ENA = RTC_ADR[]==37 & UHR_DS & !nFB_WR;
WERTE[][38].ENA = RTC_ADR[]==38 & UHR_DS & !nFB_WR;
WERTE[][39].ENA = RTC_ADR[]==39 & UHR_DS & !nFB_WR;
WERTE[][40].ENA = RTC_ADR[]==40 & UHR_DS & !nFB_WR;
WERTE[][41].ENA = RTC_ADR[]==41 & UHR_DS & !nFB_WR;
WERTE[][42].ENA = RTC_ADR[]==42 & UHR_DS & !nFB_WR;
WERTE[][43].ENA = RTC_ADR[]==43 & UHR_DS & !nFB_WR;
WERTE[][44].ENA = RTC_ADR[]==44 & UHR_DS & !nFB_WR;
WERTE[][45].ENA = RTC_ADR[]==45 & UHR_DS & !nFB_WR;
WERTE[][46].ENA = RTC_ADR[]==46 & UHR_DS & !nFB_WR;
WERTE[][47].ENA = RTC_ADR[]==47 & UHR_DS & !nFB_WR;
WERTE[][48].ENA = RTC_ADR[]==48 & UHR_DS & !nFB_WR;
WERTE[][49].ENA = RTC_ADR[]==49 & UHR_DS & !nFB_WR;
WERTE[][50].ENA = RTC_ADR[]==50 & UHR_DS & !nFB_WR;
WERTE[][51].ENA = RTC_ADR[]==51 & UHR_DS & !nFB_WR;
WERTE[][52].ENA = RTC_ADR[]==52 & UHR_DS & !nFB_WR;
WERTE[][53].ENA = RTC_ADR[]==53 & UHR_DS & !nFB_WR;
WERTE[][54].ENA = RTC_ADR[]==54 & UHR_DS & !nFB_WR;
WERTE[][55].ENA = RTC_ADR[]==55 & UHR_DS & !nFB_WR;
WERTE[][56].ENA = RTC_ADR[]==56 & UHR_DS & !nFB_WR;
WERTE[][57].ENA = RTC_ADR[]==57 & UHR_DS & !nFB_WR;
WERTE[][58].ENA = RTC_ADR[]==58 & UHR_DS & !nFB_WR;
WERTE[][59].ENA = RTC_ADR[]==59 & UHR_DS & !nFB_WR;
WERTE[][60].ENA = RTC_ADR[]==60 & UHR_DS & !nFB_WR;
WERTE[][61].ENA = RTC_ADR[]==61 & UHR_DS & !nFB_WR;
WERTE[][62].ENA = RTC_ADR[]==62 & UHR_DS & !nFB_WR;
WERTE[][63].ENA = RTC_ADR[]==63 & UHR_DS & !nFB_WR;
PIC_INT_SYNC[].CLK = MAIN_CLK; PIC_INT_SYNC[0] = PIC_INT;
FOR I IN 10 TO 63 GENERATE
WERTE[7..0][I] = FB_AD[23..16];
END GENERATE;
FOR I IN 0 TO 63 GENERATE
WERTE[][I].ENA = RTC_ADR[]==I & UHR_DS & !nFB_WR;
END GENERATE;
PIC_INT_SYNC[].CLK = MAIN_CLK;
PIC_INT_SYNC[0] = PIC_INT;
PIC_INT_SYNC[1] = PIC_INT_SYNC[0];
PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0];
UPDATE_ON = !WERTE[7][11];

182
FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak
View File

@@ -37,6 +37,7 @@ SUBDESIGN interrupt_handler
VSYNC : INPUT;
HSYNC : INPUT;
DMA_DRQ : INPUT;
nRSTO : INPUT;
nIRQ[7..2] : OUTPUT;
INT_HANDLER_TA : OUTPUT;
ACP_CONF[31..0] : OUTPUT;
@@ -56,6 +57,8 @@ VARIABLE
INT_IN[31..0] :NODE;
INT_ENA[31..0] :DFFE;
INT_ENA_CS :NODE;
INT_L[9..0] :DFF;
INT_LA[9..0][3..0] :DFF;
ACP_CONF[31..0] :DFFE;
ACP_CONF_CS :NODE;
PSEUDO_BUS_ERROR :NODE;
@@ -101,6 +104,7 @@ BEGIN
INT_CTR[7..0].ENA = INT_CTR_CS & FB_B3 & !nFB_WR;
-- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
INT_ENA[].CLK = MAIN_CLK;
INT_ENA[].CLRN = nRSTO;
INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001"; -- $10004/4
INT_ENA[] = FB_AD[];
INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR;
@@ -126,9 +130,9 @@ BEGIN
PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC
# FB_ADR[19..4]==H"F8E0" -- VME
# FB_ADR[19..4]==H"F920" -- PADDLE
# FB_ADR[19..4]==H"F921" -- PADDLE
# FB_ADR[19..4]==H"F922" -- PADDLE
-- # FB_ADR[19..4]==H"F920" -- PADDLE
-- # FB_ADR[19..4]==H"F921" -- PADDLE
-- # FB_ADR[19..4]==H"F922" -- PADDLE
# FB_ADR[19..4]==H"FFA8" -- MFP2
# FB_ADR[19..4]==H"FFA9" -- MFP2
# FB_ADR[19..4]==H"FFAA" -- MFP2
@@ -136,27 +140,38 @@ PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC
# FB_ADR[19..8]==H"F87" -- TT SCSI
# FB_ADR[19..4]==H"FFC2" -- ST UHR
# FB_ADR[19..4]==H"FFC3" -- ST UHR
# FB_ADR[19..4]==H"F890" -- DMA SOUND
# FB_ADR[19..4]==H"F891" -- DMA SOUND
# FB_ADR[19..4]==H"F892"); -- DMA SOUND
-- # FB_ADR[19..4]==H"F890" -- DMA SOUND
-- # FB_ADR[19..4]==H"F891" -- DMA SOUND
-- # FB_ADR[19..4]==H"F892" -- DMA SOUND
);
-- IF VIDEO ADR CHANGE
TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100"; -- VIDEO BASE ADR HIGH 0xFFFF8201/2
TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2
-- INTERRUPT LATCH
INT_LATCH[] = H"FFFFFFFF";
INT_LATCH0.CLK = PIC_INT & INT_ENA[0];
INT_LATCH1.CLK = E0_INT & INT_ENA[1];
INT_LATCH2.CLK = DVI_INT & INT_ENA[2];
INT_LATCH3.CLK = !nPCI_INTA & INT_ENA[3];
INT_LATCH4.CLK = !nPCI_INTB & INT_ENA[4];
INT_LATCH5.CLK = !nPCI_INTC & INT_ENA[5];
INT_LATCH6.CLK = !nPCI_INTD & INT_ENA[6];
INT_LATCH7.CLK = DSP_INT & INT_ENA[7];
INT_LATCH8.CLK = VSYNC & INT_ENA[8];
INT_LATCH9.CLK = HSYNC & INT_ENA[9];
INT_L[].CLK = MAIN_CLK;
INT_L[].CLRN = nRSTO;
INT_L0 = PIC_INT & INT_ENA[0];
INT_L1 = E0_INT & INT_ENA[1];
INT_L2 = DVI_INT & INT_ENA[2];
INT_L3 = !nPCI_INTA & INT_ENA[3];
INT_L4 = !nPCI_INTB & INT_ENA[4];
INT_L5 = !nPCI_INTC & INT_ENA[5];
INT_L6 = !nPCI_INTD & INT_ENA[6];
INT_L7 = DSP_INT & INT_ENA[7];
INT_L8 = VSYNC & INT_ENA[8];
INT_L9 = HSYNC & INT_ENA[9];
-- INTERRUPT CLEAR
INT_LATCH[].CLRN = !INT_CLEAR[];
INT_LA[][].CLK = MAIN_CLK;
INT_LATCH[] = H"FFFFFFFF";
INT_LATCH[].CLRN = !INT_CLEAR[] & nRSTO;
FOR I IN 0 TO 9 GENERATE
INT_LA[I][].CLRN = INT_ENA[I] & nRSTO;
INT_LA[I][] = INT_LA[I][]+1 & INT_L[I] & INT_LA[I][]<7
# INT_LA[I][]-1 & !INT_L[I] & INT_LA[I][]>8
# 15 & INT_L[I] & INT_LA[I][]>6
# 0 & !INT_L[I] & INT_LA[I][]<9;
INT_LATCH[I].CLK = INT_LA[I][3];
END GENERATE;
-- INT_IN
INT_IN0 = PIC_INT;
@@ -206,125 +221,14 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100"; -- VIDEO BASE ADR HIGH 0xFFFF8201/2
WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR;
WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR;
WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR;
WERTE[7..0][10] = FB_AD[23..16];
WERTE[7..0][11] = FB_AD[23..16];
WERTE[7..0][12] = FB_AD[23..16];
WERTE[7..0][13] = FB_AD[23..16];
WERTE[7..0][14] = FB_AD[23..16];
WERTE[7..0][15] = FB_AD[23..16];
WERTE[7..0][16] = FB_AD[23..16];
WERTE[7..0][17] = FB_AD[23..16];
WERTE[7..0][18] = FB_AD[23..16];
WERTE[7..0][19] = FB_AD[23..16];
WERTE[7..0][20] = FB_AD[23..16];
WERTE[7..0][21] = FB_AD[23..16];
WERTE[7..0][22] = FB_AD[23..16];
WERTE[7..0][23] = FB_AD[23..16];
WERTE[7..0][24] = FB_AD[23..16];
WERTE[7..0][25] = FB_AD[23..16];
WERTE[7..0][26] = FB_AD[23..16];
WERTE[7..0][27] = FB_AD[23..16];
WERTE[7..0][28] = FB_AD[23..16];
WERTE[7..0][29] = FB_AD[23..16];
WERTE[7..0][30] = FB_AD[23..16];
WERTE[7..0][31] = FB_AD[23..16];
WERTE[7..0][32] = FB_AD[23..16];
WERTE[7..0][33] = FB_AD[23..16];
WERTE[7..0][34] = FB_AD[23..16];
WERTE[7..0][35] = FB_AD[23..16];
WERTE[7..0][36] = FB_AD[23..16];
WERTE[7..0][37] = FB_AD[23..16];
WERTE[7..0][38] = FB_AD[23..16];
WERTE[7..0][39] = FB_AD[23..16];
WERTE[7..0][40] = FB_AD[23..16];
WERTE[7..0][41] = FB_AD[23..16];
WERTE[7..0][42] = FB_AD[23..16];
WERTE[7..0][43] = FB_AD[23..16];
WERTE[7..0][44] = FB_AD[23..16];
WERTE[7..0][45] = FB_AD[23..16];
WERTE[7..0][46] = FB_AD[23..16];
WERTE[7..0][47] = FB_AD[23..16];
WERTE[7..0][48] = FB_AD[23..16];
WERTE[7..0][49] = FB_AD[23..16];
WERTE[7..0][50] = FB_AD[23..16];
WERTE[7..0][51] = FB_AD[23..16];
WERTE[7..0][52] = FB_AD[23..16];
WERTE[7..0][53] = FB_AD[23..16];
WERTE[7..0][54] = FB_AD[23..16];
WERTE[7..0][55] = FB_AD[23..16];
WERTE[7..0][56] = FB_AD[23..16];
WERTE[7..0][57] = FB_AD[23..16];
WERTE[7..0][58] = FB_AD[23..16];
WERTE[7..0][59] = FB_AD[23..16];
WERTE[7..0][60] = FB_AD[23..16];
WERTE[7..0][61] = FB_AD[23..16];
WERTE[7..0][62] = FB_AD[23..16];
WERTE[7..0][63] = FB_AD[23..16];
WERTE[][0].ENA = RTC_ADR[]==0 & UHR_DS & !nFB_WR;
WERTE[][1].ENA = RTC_ADR[]==1 & UHR_DS & !nFB_WR;
WERTE[][2].ENA = RTC_ADR[]==2 & UHR_DS & !nFB_WR;
WERTE[][3].ENA = RTC_ADR[]==3 & UHR_DS & !nFB_WR;
WERTE[][4].ENA = RTC_ADR[]==4 & UHR_DS & !nFB_WR;
WERTE[][5].ENA = RTC_ADR[]==5 & UHR_DS & !nFB_WR;
WERTE[][6].ENA = RTC_ADR[]==6 & UHR_DS & !nFB_WR;
WERTE[][7].ENA = RTC_ADR[]==7 & UHR_DS & !nFB_WR;
WERTE[][8].ENA = RTC_ADR[]==8 & UHR_DS & !nFB_WR;
WERTE[][9].ENA = RTC_ADR[]==9 & UHR_DS & !nFB_WR;
WERTE[][10].ENA = RTC_ADR[]==10 & UHR_DS & !nFB_WR;
WERTE[][11].ENA = RTC_ADR[]==11 & UHR_DS & !nFB_WR;
WERTE[][12].ENA = RTC_ADR[]==12 & UHR_DS & !nFB_WR;
WERTE[][13].ENA = RTC_ADR[]==13 & UHR_DS & !nFB_WR;
WERTE[][14].ENA = RTC_ADR[]==14 & UHR_DS & !nFB_WR;
WERTE[][15].ENA = RTC_ADR[]==15 & UHR_DS & !nFB_WR;
WERTE[][16].ENA = RTC_ADR[]==16 & UHR_DS & !nFB_WR;
WERTE[][17].ENA = RTC_ADR[]==17 & UHR_DS & !nFB_WR;
WERTE[][18].ENA = RTC_ADR[]==18 & UHR_DS & !nFB_WR;
WERTE[][19].ENA = RTC_ADR[]==19 & UHR_DS & !nFB_WR;
WERTE[][20].ENA = RTC_ADR[]==20 & UHR_DS & !nFB_WR;
WERTE[][21].ENA = RTC_ADR[]==21 & UHR_DS & !nFB_WR;
WERTE[][22].ENA = RTC_ADR[]==22 & UHR_DS & !nFB_WR;
WERTE[][23].ENA = RTC_ADR[]==23 & UHR_DS & !nFB_WR;
WERTE[][24].ENA = RTC_ADR[]==24 & UHR_DS & !nFB_WR;
WERTE[][25].ENA = RTC_ADR[]==25 & UHR_DS & !nFB_WR;
WERTE[][26].ENA = RTC_ADR[]==26 & UHR_DS & !nFB_WR;
WERTE[][27].ENA = RTC_ADR[]==27 & UHR_DS & !nFB_WR;
WERTE[][28].ENA = RTC_ADR[]==28 & UHR_DS & !nFB_WR;
WERTE[][29].ENA = RTC_ADR[]==29 & UHR_DS & !nFB_WR;
WERTE[][30].ENA = RTC_ADR[]==30 & UHR_DS & !nFB_WR;
WERTE[][31].ENA = RTC_ADR[]==31 & UHR_DS & !nFB_WR;
WERTE[][32].ENA = RTC_ADR[]==32 & UHR_DS & !nFB_WR;
WERTE[][33].ENA = RTC_ADR[]==33 & UHR_DS & !nFB_WR;
WERTE[][34].ENA = RTC_ADR[]==34 & UHR_DS & !nFB_WR;
WERTE[][35].ENA = RTC_ADR[]==35 & UHR_DS & !nFB_WR;
WERTE[][36].ENA = RTC_ADR[]==36 & UHR_DS & !nFB_WR;
WERTE[][37].ENA = RTC_ADR[]==37 & UHR_DS & !nFB_WR;
WERTE[][38].ENA = RTC_ADR[]==38 & UHR_DS & !nFB_WR;
WERTE[][39].ENA = RTC_ADR[]==39 & UHR_DS & !nFB_WR;
WERTE[][40].ENA = RTC_ADR[]==40 & UHR_DS & !nFB_WR;
WERTE[][41].ENA = RTC_ADR[]==41 & UHR_DS & !nFB_WR;
WERTE[][42].ENA = RTC_ADR[]==42 & UHR_DS & !nFB_WR;
WERTE[][43].ENA = RTC_ADR[]==43 & UHR_DS & !nFB_WR;
WERTE[][44].ENA = RTC_ADR[]==44 & UHR_DS & !nFB_WR;
WERTE[][45].ENA = RTC_ADR[]==45 & UHR_DS & !nFB_WR;
WERTE[][46].ENA = RTC_ADR[]==46 & UHR_DS & !nFB_WR;
WERTE[][47].ENA = RTC_ADR[]==47 & UHR_DS & !nFB_WR;
WERTE[][48].ENA = RTC_ADR[]==48 & UHR_DS & !nFB_WR;
WERTE[][49].ENA = RTC_ADR[]==49 & UHR_DS & !nFB_WR;
WERTE[][50].ENA = RTC_ADR[]==50 & UHR_DS & !nFB_WR;
WERTE[][51].ENA = RTC_ADR[]==51 & UHR_DS & !nFB_WR;
WERTE[][52].ENA = RTC_ADR[]==52 & UHR_DS & !nFB_WR;
WERTE[][53].ENA = RTC_ADR[]==53 & UHR_DS & !nFB_WR;
WERTE[][54].ENA = RTC_ADR[]==54 & UHR_DS & !nFB_WR;
WERTE[][55].ENA = RTC_ADR[]==55 & UHR_DS & !nFB_WR;
WERTE[][56].ENA = RTC_ADR[]==56 & UHR_DS & !nFB_WR;
WERTE[][57].ENA = RTC_ADR[]==57 & UHR_DS & !nFB_WR;
WERTE[][58].ENA = RTC_ADR[]==58 & UHR_DS & !nFB_WR;
WERTE[][59].ENA = RTC_ADR[]==59 & UHR_DS & !nFB_WR;
WERTE[][60].ENA = RTC_ADR[]==60 & UHR_DS & !nFB_WR;
WERTE[][61].ENA = RTC_ADR[]==61 & UHR_DS & !nFB_WR;
WERTE[][62].ENA = RTC_ADR[]==62 & UHR_DS & !nFB_WR;
WERTE[][63].ENA = RTC_ADR[]==63 & UHR_DS & !nFB_WR;
PIC_INT_SYNC[].CLK = MAIN_CLK; PIC_INT_SYNC[0] = PIC_INT;
FOR I IN 10 TO 63 GENERATE
WERTE[7..0][I] = FB_AD[23..16];
END GENERATE;
FOR I IN 0 TO 63 GENERATE
WERTE[][I].ENA = RTC_ADR[]==I & UHR_DS & !nFB_WR;
END GENERATE;
PIC_INT_SYNC[].CLK = MAIN_CLK;
PIC_INT_SYNC[0] = PIC_INT;
PIC_INT_SYNC[1] = PIC_INT_SYNC[0];
PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0];
UPDATE_ON = !WERTE[7][11];

20
FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt Normal file
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@@ -0,0 +1,20 @@
PLL_Name altpll1:inst|altpll:altpll_component|altpll_3vp2:auto_generated|pll1
PLLJITTER 36
PLLSPEmax 84
PLLSPEmin -53
PLL_Name altpll2:inst12|altpll:altpll_component|altpll_1r33:auto_generated|pll1
PLLJITTER 43
PLLSPEmax 84
PLLSPEmin -53
PLL_Name altpll3:inst13|altpll:altpll_component|altpll_aus2:auto_generated|pll1
PLLJITTER NA
PLLSPEmax 84
PLLSPEmin -53
PLL_Name altpll4:inst22|altpll:altpll_component|altpll_r4n2:auto_generated|pll1
PLLJITTER 31
PLLSPEmax 84
PLLSPEmin -53

75
FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd
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@@ -1,75 +0,0 @@
-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
-- Created on Fri Oct 16 15:40:59 2009
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY BLITTER IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
nRSTO : IN STD_LOGIC;
MAIN_CLK : IN STD_LOGIC;
FB_ALE : IN STD_LOGIC;
nFB_WR : IN STD_LOGIC;
nFB_OE : IN STD_LOGIC;
FB_SIZE0 : IN STD_LOGIC;
FB_SIZE1 : IN STD_LOGIC;
VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0);
BLITTER_ON : IN STD_LOGIC;
FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
nFB_CS1 : IN STD_LOGIC;
nFB_CS2 : IN STD_LOGIC;
nFB_CS3 : IN STD_LOGIC;
DDRCLK0 : IN STD_LOGIC;
BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0);
BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0);
BLITTER_RUN : OUT STD_LOGIC;
BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0);
BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0);
BLITTER_SIG : OUT STD_LOGIC;
BLITTER_WR : OUT STD_LOGIC;
BLITTER_TA : OUT STD_LOGIC;
FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0)
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END BLITTER;
-- Architecture Body
ARCHITECTURE BLITTER_architecture OF BLITTER IS
BEGIN
BLITTER_RUN <= '0';
BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0";
BLITTER_ADR <= x"76543210";
BLITTER_SIG <= '0';
BLITTER_WR <= '0';
BLITTER_TA <= '0';
END BLITTER_architecture;

75
FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd.bak
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@@ -1,75 +0,0 @@
-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
-- Created on Fri Oct 16 15:40:59 2009
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY BLITTER IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
nRSTO : IN STD_LOGIC;
MAIN_CLK : IN STD_LOGIC;
FB_ALE : IN STD_LOGIC;
nFB_WR : IN STD_LOGIC;
nFB_OE : IN STD_LOGIC;
FB_SIZE0 : IN STD_LOGIC;
FB_SIZE1 : IN STD_LOGIC;
VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0);
BLITTER_ON : IN STD_LOGIC;
FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
nFB_CS1 : IN STD_LOGIC;
nFB_CS2 : IN STD_LOGIC;
nFB_CS3 : IN STD_LOGIC;
DDRCLK0 : IN STD_LOGIC;
BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0);
BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0);
BLITTER_RUN : OUT STD_LOGIC;
BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0);
BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0);
BLITTER_SIG : OUT STD_LOGIC;
BLITTER_WR : OUT STD_LOGIC;
BLITTER_TA : OUT STD_LOGIC;
FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0)
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END BLITTER;
-- Architecture Body
ARCHITECTURE BLITTER_architecture OF BLITTER IS
BEGIN
BLITTER_RUN <= '0';
BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0";
BLITTER_ADR <= x"FEDCBA9876543210";
BLITTER_SIG <= '0';
BLITTER_WR <= '0';
BLITTER_TA <= '0';
END BLITTER_architecture;

110
FPGA_by_Fredi/Video/BLITTER/altsyncram0.bsf Normal file
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@@ -0,0 +1,110 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 256 128)
(text "altsyncram0" (rect 84 2 187 21)(font "Arial" (font_size 10)))
(text "inst" (rect 8 109 31 124)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "data[15..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
(text "data[15..0]" (rect 4 16 66 32)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 112 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "address[3..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
(text "address[3..0]" (rect 4 32 80 48)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 112 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "wren" (rect 0 0 31 16)(font "Arial" (font_size 8)))
(text "wren" (rect 4 48 31 64)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 112 64)(line_width 1))
)
(port
(pt 0 88)
(input)
(text "byteena_a[1..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
(text "byteena_a[1..0]" (rect 4 72 94 88)(font "Arial" (font_size 8)))
(line (pt 0 88)(pt 112 88)(line_width 3))
)
(port
(pt 0 104)
(input)
(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
(text "clock" (rect 4 88 35 104)(font "Arial" (font_size 8)))
(line (pt 0 104)(pt 104 104)(line_width 1))
)
(port
(pt 256 32)
(output)
(text "q[15..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
(text "q[15..0]" (rect 209 16 253 32)(font "Arial" (font_size 8)))
(line (pt 256 32)(pt 168 32)(line_width 3))
)
(drawing
(text "16 Word(s)" (rect 133 35 147 90)(font "Arial" )(vertical))
(text "RAM" (rect 149 49 163 72)(font "Arial" )(vertical))
(text "Block Type: AUTO" (rect 41 106 129 120)(font "Arial" ))
(line (pt 128 24)(pt 168 24)(line_width 1))
(line (pt 168 24)(pt 168 96)(line_width 1))
(line (pt 168 96)(pt 128 96)(line_width 1))
(line (pt 128 96)(pt 128 24)(line_width 1))
(line (pt 112 27)(pt 120 27)(line_width 1))
(line (pt 120 27)(pt 120 39)(line_width 1))
(line (pt 120 39)(pt 112 39)(line_width 1))
(line (pt 112 39)(pt 112 27)(line_width 1))
(line (pt 112 34)(pt 114 36)(line_width 1))
(line (pt 114 36)(pt 112 38)(line_width 1))
(line (pt 104 36)(pt 112 36)(line_width 1))
(line (pt 120 32)(pt 128 32)(line_width 3))
(line (pt 112 43)(pt 120 43)(line_width 1))
(line (pt 120 43)(pt 120 55)(line_width 1))
(line (pt 120 55)(pt 112 55)(line_width 1))
(line (pt 112 55)(pt 112 43)(line_width 1))
(line (pt 112 50)(pt 114 52)(line_width 1))
(line (pt 114 52)(pt 112 54)(line_width 1))
(line (pt 104 52)(pt 112 52)(line_width 1))
(line (pt 120 48)(pt 128 48)(line_width 3))
(line (pt 112 59)(pt 120 59)(line_width 1))
(line (pt 120 59)(pt 120 71)(line_width 1))
(line (pt 120 71)(pt 112 71)(line_width 1))
(line (pt 112 71)(pt 112 59)(line_width 1))
(line (pt 112 66)(pt 114 68)(line_width 1))
(line (pt 114 68)(pt 112 70)(line_width 1))
(line (pt 104 68)(pt 112 68)(line_width 1))
(line (pt 120 64)(pt 128 64)(line_width 1))
(line (pt 112 83)(pt 120 83)(line_width 1))
(line (pt 120 83)(pt 120 95)(line_width 1))
(line (pt 120 95)(pt 112 95)(line_width 1))
(line (pt 112 95)(pt 112 83)(line_width 1))
(line (pt 112 90)(pt 114 92)(line_width 1))
(line (pt 114 92)(pt 112 94)(line_width 1))
(line (pt 104 92)(pt 112 92)(line_width 1))
(line (pt 120 88)(pt 128 88)(line_width 3))
(line (pt 104 36)(pt 104 105)(line_width 1))
)
)

26
FPGA_by_Fredi/Video/BLITTER/altsyncram0.cmp Normal file
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@@ -0,0 +1,26 @@
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component altsyncram0
PORT
(
address : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '1');
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component;

27
FPGA_by_Fredi/Video/BLITTER/altsyncram0.inc Normal file
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@@ -0,0 +1,27 @@
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION altsyncram0
(
address[3..0],
byteena_a[1..0],
clock,
data[15..0],
wren
)
RETURNS (
q[15..0]
);

6
FPGA_by_Fredi/Video/BLITTER/altsyncram0.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTSYNCRAM"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.cmp"]

181
FPGA_by_Fredi/Video/BLITTER/altsyncram0.tdf Normal file
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-- megafunction wizard: %ALTSYNCRAM%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: altsyncram0.tdf
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
INCLUDE "altsyncram.inc";
SUBDESIGN altsyncram0
(
address[3..0] : INPUT;
byteena_a[1..0] : INPUT = VCC;
clock : INPUT = VCC;
data[15..0] : INPUT;
wren : INPUT = GND;
q[15..0] : OUTPUT;
)
VARIABLE
altsyncram_component : altsyncram WITH (
BYTE_SIZE = 8,
CLOCK_ENABLE_INPUT_A = "BYPASS",
CLOCK_ENABLE_OUTPUT_A = "BYPASS",
INTENDED_DEVICE_FAMILY = "Cyclone III",
LPM_HINT = "ENABLE_RUNTIME_MOD=NO",
LPM_TYPE = "altsyncram",
NUMWORDS_A = 16,
OPERATION_MODE = "SINGLE_PORT",
OUTDATA_ACLR_A = "NONE",
OUTDATA_REG_A = "UNREGISTERED",
POWER_UP_UNINITIALIZED = "FALSE",
READ_DURING_WRITE_MODE_PORT_A = "NEW_DATA_WITH_NBE_READ",
READ_DURING_WRITE_MODE_PORT_B = "NEW_DATA_WITH_NBE_READ",
WIDTHAD_A = 4,
WIDTH_A = 16,
WIDTH_BYTEENA_A = 2
);
BEGIN
q[15..0] = altsyncram_component.q_a[15..0];
altsyncram_component.wren_a = wren;
altsyncram_component.clock0 = clock;
altsyncram_component.byteena_a[1..0] = byteena_a[1..0];
altsyncram_component.address_a[3..0] = address[3..0];
altsyncram_component.data_a[15..0] = data[15..0];
END;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "256"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "1"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_WITH_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_WITH_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
-- Retrieval info: USED_PORT: address 0 0 4 0 INPUT NODEFVAL address[3..0]
-- Retrieval info: USED_PORT: byteena_a 0 0 2 0 INPUT VCC byteena_a[1..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND wren
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: CONNECT: @address_a 0 0 4 0 address 0 0 4 0
-- Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena_a 0 0 2 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.tdf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_inst.tdf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf

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<html>
<head>
<title>Sample Waveforms for "altsyncram0.tdf" </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file "altsyncram0.tdf" </CENTER></h2>
<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design "altsyncram0.tdf". For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( FFF0, FFF1, FFF2, FFF3, ...). The design "altsyncram0.tdf" has </P>
<CENTER><img src=altsyncram0_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. </P>
<P></P>
</body>
</html>

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-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2010 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
-- Created on Sat Jan 15 11:06:17 2011
INCLUDE "lpm_bustri_WORD.inc";
INCLUDE "VIDEO/BLITTER/lpm_clshift0.INC";
CONSTANT BL_SKEW_LF = 255;
-- Title Statement (optional)
TITLE "Blitter";
-- Parameters Statement (optional)
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-- Subdesign Section
SUBDESIGN BLITTER
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
nRSTO : INPUT;
MAIN_CLK : INPUT;
FB_ALE : INPUT;
nFB_WR : INPUT;
nFB_OE : INPUT;
FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT;
VIDEO_RAM_CTR[15..0] : INPUT;
BLITTER_ON : INPUT;
FB_ADR[31..0] : INPUT;
nFB_CS1 : INPUT;
nFB_CS2 : INPUT;
nFB_CS3 : INPUT;
DDRCLK0 : INPUT;
BLITTER_DIN[127..0] : INPUT;
BLITTER_DACK[4..0] : INPUT;
SR_BLITTER_DACK : INPUT;
BLITTER_RUN : OUTPUT;
BLITTER_DOUT[127..0] : OUTPUT;
BLITTER_ADR[31..0] : OUTPUT;
BLITTER_SIG : OUTPUT;
BLITTER_WR : OUTPUT;
BLITTER_TA : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
VARIABLE
FB_B[3..0] :NODE;
FB_16B[1..0] :NODE;
BLITTER_CS :NODE;
BL_HRAM0_CS :NODE;
BL_HRAM0[15..0] :DFFE;
BL_HRAM1_CS :NODE;
BL_HRAM1[15..0] :DFFE;
BL_HRAM2_CS :NODE;
BL_HRAM2[15..0] :DFFE;
BL_HRAM3_CS :NODE;
BL_HRAM3[15..0] :DFFE;
BL_HRAM4_CS :NODE;
BL_HRAM4[15..0] :DFFE;
BL_HRAM5_CS :NODE;
BL_HRAM5[15..0] :DFFE;
BL_HRAM6_CS :NODE;
BL_HRAM6[15..0] :DFFE;
BL_HRAM7_CS :NODE;
BL_HRAM7[15..0] :DFFE;
BL_HRAM8_CS :NODE;
BL_HRAM8[15..0] :DFFE;
BL_HRAM9_CS :NODE;
BL_HRAM9[15..0] :DFFE;
BL_HRAMA_CS :NODE;
BL_HRAMA[15..0] :DFFE;
BL_HRAMB_CS :NODE;
BL_HRAMB[15..0] :DFFE;
BL_HRAMC_CS :NODE;
BL_HRAMC[15..0] :DFFE;
BL_HRAMD_CS :NODE;
BL_HRAMD[15..0] :DFFE;
BL_HRAME_CS :NODE;
BL_HRAME[15..0] :DFFE;
BL_HRAMF_CS :NODE;
BL_HRAMF[15..0] :DFFE;
BL_SRC_X_INC_CS :NODE;
BL_SRC_X_INC[15..0] :DFFE;
BL_SRC_Y_INC_CS :NODE;
BL_SRC_Y_INC[15..0] :DFFE;
BL_ENDMASK1_CS :NODE;
BL_ENDMASK1[15..0] :DFFE;
BL_ENDMASK2_CS :NODE;
BL_ENDMASK2[15..0] :DFFE;
BL_ENDMASK3_CS :NODE;
BL_ENDMASK3[15..0] :DFFE;
BL_SRC_ADRH_CS :NODE;
BL_SRC_ADRL_CS :NODE;
BL_SRC_ADR[31..0] :DFFE;
BL_DST_X_INC_CS :NODE;
BL_DST_X_INC[15..0] :DFFE;
BL_DST_Y_INC_CS :NODE;
BL_DST_Y_INC[15..0] :DFFE;
BL_DST_ADRH_CS :NODE;
BL_DST_ADRL_CS :NODE;
BL_DST_ADR[31..0] :DFFE;
BL_X_CNT_CS :NODE;
BL_X_CNT[15..0] :DFFE;
BL_Y_CNT_CS :NODE;
BL_Y_CNT[15..0] :DFFE;
BL_HT_OP_CS :NODE;
BL_HT_OP[7..0] :DFFE;
BL_LC_OP[7..0] :DFFE;
BL_LN_CS :NODE;
BL_LN[7..0] :DFFE;
BL_SKEW[7..0] :DFFE;
BL_SKEW_EXT[6..0] :NODE;
BL_SKEW_IN[255..0] :DFFE;
BL_SKEW_OUT[255..0] :DFFE;
BL_DATA_DDR_READY :DFF; -- 1 WENN DATEN GESCHRIEBEN ODER LESBAR
BL_READ_SRC :DFFE;
BL_DST_BUFFER[127..0] :DFFE;
BL_READ_DST :DFFE;
COUNT[18..0] :DFF;
BEGIN
-- BYT SELECT 32 BIT
FB_B0 = FB_ADR[1..0]==0; -- ADR==0
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- BYT SELECT 16 BIT
FB_16B0 = FB_ADR[0]==0; -- ADR==0
FB_16B1 = FB_ADR[0]==1 -- ADR==1
# !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT
-- BLITTER CS
BLITTER_CS = !nFB_CS1 & FB_ADR[19..6]==H"3E28"; -- FFFF8A00-3F/40
BLITTER_TA = BLITTER_CS;
-- REGISTER
-- HALFTON RAM 0
BL_HRAM0[].CLK = MAIN_CLK;
BL_HRAM0[15..0] = FB_AD[31..16];
BL_HRAM0_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C500"; -- $F8A00/2
BL_HRAM0[15..8].ENA = BL_HRAM0_CS & !nFB_WR & FB_16B0;
BL_HRAM0[7..0].ENA = BL_HRAM0_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 1
BL_HRAM1[].CLK = MAIN_CLK;
BL_HRAM1[15..0] = FB_AD[31..16];
BL_HRAM1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C501"; -- $F8A02/2
BL_HRAM1[15..8].ENA = BL_HRAM1_CS & !nFB_WR & FB_16B0;
BL_HRAM1[7..0].ENA = BL_HRAM1_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 2
BL_HRAM2[].CLK = MAIN_CLK;
BL_HRAM2[15..0] = FB_AD[31..16];
BL_HRAM2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C502"; -- $F8A04/2
BL_HRAM2[15..8].ENA = BL_HRAM2_CS & !nFB_WR & FB_16B0;
BL_HRAM2[7..0].ENA = BL_HRAM2_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 3
BL_HRAM3[].CLK = MAIN_CLK;
BL_HRAM3[15..0] = FB_AD[31..16];
BL_HRAM3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C503"; -- $F8A06/2
BL_HRAM3[15..8].ENA = BL_HRAM3_CS & !nFB_WR & FB_16B0;
BL_HRAM3[7..0].ENA = BL_HRAM3_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 4
BL_HRAM4[].CLK = MAIN_CLK;
BL_HRAM4[15..0] = FB_AD[31..16];
BL_HRAM4_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C504"; -- $F8A08/2
BL_HRAM4[15..8].ENA = BL_HRAM4_CS & !nFB_WR & FB_16B0;
BL_HRAM4[7..0].ENA = BL_HRAM4_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 5
BL_HRAM5[].CLK = MAIN_CLK;
BL_HRAM5[15..0] = FB_AD[31..16];
BL_HRAM5_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C505"; -- $F8A08/2
BL_HRAM5[15..8].ENA = BL_HRAM5_CS & !nFB_WR & FB_16B0;
BL_HRAM5[7..0].ENA = BL_HRAM5_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 6
BL_HRAM6[].CLK = MAIN_CLK;
BL_HRAM6[15..0] = FB_AD[31..16];
BL_HRAM6_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C506"; -- $F8A08/2
BL_HRAM6[15..8].ENA = BL_HRAM6_CS & !nFB_WR & FB_16B0;
BL_HRAM6[7..0].ENA = BL_HRAM6_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 7
BL_HRAM7[].CLK = MAIN_CLK;
BL_HRAM7[15..0] = FB_AD[31..16];
BL_HRAM7_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C507"; -- $F8A08/2
BL_HRAM7[15..8].ENA = BL_HRAM7_CS & !nFB_WR & FB_16B0;
BL_HRAM7[7..0].ENA = BL_HRAM7_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 8
BL_HRAM8[].CLK = MAIN_CLK;
BL_HRAM8[15..0] = FB_AD[31..16];
BL_HRAM8_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C508"; -- $F8A10/2
BL_HRAM8[15..8].ENA = BL_HRAM8_CS & !nFB_WR & FB_16B0;
BL_HRAM8[7..0].ENA = BL_HRAM8_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 9
BL_HRAM9[].CLK = MAIN_CLK;
BL_HRAM9[15..0] = FB_AD[31..16];
BL_HRAM9_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C509"; -- $F8A12/2
BL_HRAM9[15..8].ENA = BL_HRAM9_CS & !nFB_WR & FB_16B0;
BL_HRAM9[7..0].ENA = BL_HRAM9_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 10
BL_HRAMA[].CLK = MAIN_CLK;
BL_HRAMA[15..0] = FB_AD[31..16];
BL_HRAMA_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50A"; -- $F8A4/2
BL_HRAMA[15..8].ENA = BL_HRAMA_CS & !nFB_WR & FB_16B0;
BL_HRAMA[7..0].ENA = BL_HRAMA_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 11
BL_HRAMB[].CLK = MAIN_CLK;
BL_HRAMB[15..0] = FB_AD[31..16];
BL_HRAMB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50B"; -- $F8A16/2
BL_HRAMB[15..8].ENA = BL_HRAMB_CS & !nFB_WR & FB_16B0;
BL_HRAMB[7..0].ENA = BL_HRAMB_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 12
BL_HRAMC[].CLK = MAIN_CLK;
BL_HRAMC[15..0] = FB_AD[31..16];
BL_HRAMC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50C"; -- $F8A18/2
BL_HRAMC[15..8].ENA = BL_HRAMC_CS & !nFB_WR & FB_16B0;
BL_HRAMC[7..0].ENA = BL_HRAMC_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 13
BL_HRAMD[].CLK = MAIN_CLK;
BL_HRAMD[15..0] = FB_AD[31..16];
BL_HRAMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50D"; -- $F8A1A/2
BL_HRAMD[15..8].ENA = BL_HRAMD_CS & !nFB_WR & FB_16B0;
BL_HRAMD[7..0].ENA = BL_HRAMD_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 14
BL_HRAME[].CLK = MAIN_CLK;
BL_HRAME[15..0] = FB_AD[31..16];
BL_HRAME_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50E"; -- $F8A1C/2
BL_HRAME[15..8].ENA = BL_HRAME_CS & !nFB_WR & FB_16B0;
BL_HRAME[7..0].ENA = BL_HRAME_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 15
BL_HRAMF[].CLK = MAIN_CLK;
BL_HRAMF[15..0] = FB_AD[31..16];
BL_HRAMF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50F"; -- $F8A1E/2
BL_HRAMF[15..8].ENA = BL_HRAMF_CS & !nFB_WR & FB_16B0;
BL_HRAMF[7..0].ENA = BL_HRAMF_CS & !nFB_WR & FB_16B1;
-- SRC X INC
BL_SRC_X_INC[].CLK = MAIN_CLK;
BL_SRC_X_INC[] = FB_AD[31..16];
BL_SRC_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C510"; -- $F8A20/2
BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_X_INC[7..0].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
-- SRC Y INC
BL_SRC_Y_INC[].CLK = MAIN_CLK;
BL_SRC_Y_INC[] = FB_AD[31..16];
BL_SRC_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C511"; -- $F8A22/2
BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_Y_INC[7..0].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
-- SRC ADR HIGH
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[31..16] = FB_AD[31..16];
BL_SRC_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512"; -- $F8A24/2
BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
-- SRC ADR LOW
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[15..0] = FB_AD[31..16];
BL_SRC_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513"; -- $F8A26/2
BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[7..0].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
-- ENDMASK 1
BL_ENDMASK1[].CLK = MAIN_CLK;
BL_ENDMASK1[] = FB_AD[31..16];
BL_ENDMASK1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C514"; -- $F8A28/2
BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
BL_ENDMASK1[7..0].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
-- ENDMASK 2
BL_ENDMASK2[].CLK = MAIN_CLK;
BL_ENDMASK2[] = FB_AD[31..16];
BL_ENDMASK2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C515"; -- $F8A2A/2
BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
BL_ENDMASK2[7..0].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
-- ENDMASK 3
BL_ENDMASK3[].CLK = MAIN_CLK;
BL_ENDMASK3[] = FB_AD[31..16];
BL_ENDMASK3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C516"; -- $F8A2C/2
BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
BL_ENDMASK3[7..0].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
-- DST X INC
BL_DST_X_INC[].CLK = MAIN_CLK;
BL_DST_X_INC[] = FB_AD[31..16];
BL_DST_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C517"; -- $F8A2E/2
BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
BL_DST_X_INC[7..0].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
-- DST Y INC
BL_DST_Y_INC[].CLK = MAIN_CLK;
BL_DST_Y_INC[] = FB_AD[31..16];
BL_DST_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C518"; -- $F8A30/2
BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
BL_DST_Y_INC[7..0].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
-- DST ADR HIGH
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[31..16] = FB_AD[31..16];
BL_DST_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512"; -- $F8A24/2
BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
-- DST ADR LOW
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[15..0] = FB_AD[31..16];
BL_DST_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513"; -- $F8A26/2
BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[7..0].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
-- X COUNT
BL_X_CNT[].CLK = MAIN_CLK;
BL_X_CNT[] = FB_AD[31..16];
BL_X_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51B"; -- $F8A36/2
BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
BL_X_CNT[7..0].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B1;
-- Y COUNT
BL_Y_CNT[].CLK = MAIN_CLK;
BL_Y_CNT[] = FB_AD[31..16];
BL_Y_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51C"; -- $F8A38/2
BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
BL_Y_CNT[7..0].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
-- HALFTONE OP BYT
BL_HT_OP[].CLK = MAIN_CLK;
BL_HT_OP[] = FB_AD[31..24];
BL_HT_OP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51D"; -- $F8A3A/2
BL_HT_OP[7..0].ENA = BL_HT_OP_CS & !nFB_WR & FB_16B0;
-- LOGIC OP BYT
BL_LC_OP[].CLK = MAIN_CLK;
BL_LC_OP[] = FB_AD[23..16];
BL_LC_OP[7..0].ENA = BL_HT_OP_CS & !nFB_WR & FB_16B1; -- $F8A3B
-- LINE NUMBER BYT
BL_LN[].CLK = MAIN_CLK;
BL_LN[] = FB_AD[31..24];
BL_LN_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51E"; -- $F8A3C/2
BL_LN[7..0].ENA = BL_LN_CS & !nFB_WR & FB_16B0;
-- SKEW BYT
BL_SKEW[].CLK = MAIN_CLK;
BL_SKEW[] = FB_AD[31..24];
BL_SKEW[7..0].ENA = BL_LN_CS & !nFB_WR & FB_16B1; -- $F8A3D
--- REGISTER OUT
FB_AD[31..16] = lpm_bustri_WORD(
BL_HRAM0_CS & BL_HRAM0[15..0]
# BL_HRAM1_CS & BL_HRAM1[15..0]
# BL_HRAM2_CS & BL_HRAM2[15..0]
# BL_HRAM3_CS & BL_HRAM3[15..0]
# BL_HRAM4_CS & BL_HRAM4[15..0]
# BL_HRAM5_CS & BL_HRAM5[15..0]
# BL_HRAM6_CS & BL_HRAM6[15..0]
# BL_HRAM7_CS & BL_HRAM7[15..0]
# BL_HRAM8_CS & BL_HRAM8[15..0]
# BL_HRAM9_CS & BL_HRAM9[15..0]
# BL_HRAMA_CS & BL_HRAMA[15..0]
# BL_HRAMB_CS & BL_HRAMB[15..0]
# BL_HRAMC_CS & BL_HRAMC[15..0]
# BL_HRAMD_CS & BL_HRAMD[15..0]
# BL_HRAME_CS & BL_HRAME[15..0]
# BL_HRAMF_CS & BL_HRAMF[15..0]
# BL_SRC_X_INC_CS & BL_SRC_X_INC[]
# BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
# BL_SRC_ADRH_CS & BL_SRC_ADR[31..16]
# BL_SRC_ADRL_CS & BL_SRC_ADR[15..0]
# BL_ENDMASK1_CS & BL_ENDMASK1[]
# BL_ENDMASK2_CS & BL_ENDMASK2[]
# BL_ENDMASK3_CS & BL_ENDMASK3[]
# BL_DST_X_INC_CS & BL_DST_X_INC[]
# BL_DST_Y_INC_CS & BL_DST_Y_INC[]
# BL_DST_ADRH_CS & BL_DST_ADR[31..16]
# BL_DST_ADRL_CS & BL_DST_ADR[15..0]
# BL_X_CNT_CS & BL_X_CNT[]
# BL_Y_CNT_CS & BL_Y_CNT[]
# BL_HT_OP_CS & (BL_HT_OP[],BL_LC_OP[])
# BL_LN_CS & (BL_LN[],BL_SKEW[])
,!nFB_CS1 & FB_ADR[19..6]==H"3E28" & !nFB_OE); -- FFFF8A00-3F/40
-----------------------------------------
--
BL_READ_SRC.CLK = DDRCLK0;
BL_READ_DST.CLK = DDRCLK0;
BLITTER_RUN = VCC;
BLITTER_SIG = VCC;
BLITTER_WR = VCC;
-- READY SIGNAL 1 CLOCK SP<53>TER
BL_DATA_DDR_READY.CLK = DDRCLK0;
BL_DATA_DDR_READY = BL_DATA_DDR_READY & BLITTER_DACK0;
-- SRC BUFFER LADEN
BL_SKEW_IN[].CLK = DDRCLK0;
BL_SKEW_IN[].ENA = BL_DATA_DDR_READY & BL_READ_SRC;
BL_SKEW_IN[255..128] = BLITTER_DIN[];
BL_SKEW_IN[127..0] = BL_SKEW_IN[255..128];
-- DST BUFFER LADEN
BL_DST_BUFFER[].CLK = DDRCLK0;
BL_DST_BUFFER[].ENA = BL_DATA_DDR_READY & BL_READ_DST;
BL_DST_BUFFER[] = BLITTER_DIN[];
-- SKEW EXTENDET
BL_SKEW_EXT[6..4] = BL_SRC_ADR[3..1];
BL_SKEW_EXT[3..0] = BL_SKEW[3..0];
-- SKEW EXT MUX
BL_SKEW_OUT[].CLK = DDRCLK0;
BL_SKEW_OUT[].ENA = BL_DATA_DDR_READY & BL_READ_DST;
BL_SKEW_OUT[] = lpm_clshift0(BL_SKEW_IN[],BL_SKEW_EXT[]); -- BIT 127..0 SIND RELEVANT
COUNT[] = COUNT[] + 16;
COUNT[].CLK = BLITTER_DACK0;
BLITTER_DOUT[] = H"112233445566778899AABBCCDDEEFF00";
BLITTER_ADR[] = (0, COUNT[]) + 400000;
END;

54
FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.bsf Normal file
View File

@@ -0,0 +1,54 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 208 80)
(text "lpm_clshift0" (rect 62 3 162 22)(font "Arial" (font_size 10)))
(text "inst" (rect 8 61 31 76)(font "Arial" ))
(port
(pt 0 24)
(input)
(text "data[255..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
(text "data[255..0]" (rect 20 16 89 32)(font "Arial" (font_size 8)))
(line (pt 0 24)(pt 16 24)(line_width 3))
)
(port
(pt 0 40)
(input)
(text "distance[6..0]" (rect 0 0 93 16)(font "Arial" (font_size 8)))
(text "distance[6..0]" (rect 20 32 99 48)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 16 40)(line_width 3))
)
(port
(pt 208 24)
(output)
(text "result[255..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
(text "result[255..0]" (rect 113 16 189 32)(font "Arial" (font_size 8)))
(line (pt 208 24)(pt 192 24)(line_width 3))
)
(drawing
(text "LOGICAL right shift" (rect 21 50 114 64)(font "Arial" ))
(line (pt 16 16)(pt 16 64)(line_width 1))
(line (pt 192 16)(pt 192 64)(line_width 1))
(line (pt 16 16)(pt 192 16)(line_width 1))
(line (pt 16 64)(pt 192 64)(line_width 1))
)
)

23
FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.cmp Normal file
View File

@@ -0,0 +1,23 @@
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_clshift0
PORT
(
data : IN STD_LOGIC_VECTOR (255 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (255 DOWNTO 0)
);
end component;

24
FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.inc Normal file
View File

@@ -0,0 +1,24 @@
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION lpm_clshift0
(
data[255..0],
distance[6..0]
)
RETURNS (
result[255..0]
);

6
FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.qip Normal file
View File

@@ -0,0 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "LPM_CLSHIFT"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.cmp"]

92
FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.tdf Normal file
View File

@@ -0,0 +1,92 @@
-- megafunction wizard: %LPM_CLSHIFT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_clshift
-- ============================================================
-- File Name: lpm_clshift0.tdf
-- Megafunction Name(s):
-- lpm_clshift
--
-- Simulation Library Files(s):
--
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
INCLUDE "lpm_clshift.inc";
SUBDESIGN lpm_clshift0
(
data[255..0] : INPUT;
distance[6..0] : INPUT;
result[255..0] : OUTPUT;
)
VARIABLE
lpm_clshift_component : lpm_clshift WITH (
LPM_SHIFTTYPE = "LOGICAL",
LPM_TYPE = "LPM_CLSHIFT",
LPM_WIDTH = 256,
LPM_WIDTHDIST = 7
);
BEGIN
result[255..0] = lpm_clshift_component.result[255..0];
lpm_clshift_component.distance[6..0] = distance[6..0];
lpm_clshift_component.direction = VCC;
lpm_clshift_component.data[255..0] = data[255..0];
END;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_SHIFTTYPE NUMERIC "0"
-- Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "256"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: lpm_width_varies NUMERIC "0"
-- Retrieval info: PRIVATE: lpm_widthdist NUMERIC "7"
-- Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "1"
-- Retrieval info: PRIVATE: port_direction NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_SHIFTTYPE STRING "LOGICAL"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CLSHIFT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "256"
-- Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "7"
-- Retrieval info: USED_PORT: data 0 0 256 0 INPUT NODEFVAL data[255..0]
-- Retrieval info: USED_PORT: distance 0 0 7 0 INPUT NODEFVAL distance[6..0]
-- Retrieval info: USED_PORT: result 0 0 256 0 OUTPUT NODEFVAL result[255..0]
-- Retrieval info: CONNECT: @distance 0 0 7 0 distance 0 0 7 0
-- Retrieval info: CONNECT: @data 0 0 256 0 data 0 0 256 0
-- Retrieval info: CONNECT: result 0 0 256 0 @result 0 0 256 0
-- Retrieval info: CONNECT: @direction 0 0 0 0 VCC 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.tdf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0_inst.tdf FALSE

6
FPGA_by_Fredi/Video/DDR_CTR.tdf
View File

@@ -373,8 +373,8 @@ BEGIN
VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
BA_S[] = CPU_AC & CPU_BA[]
# BLITTER_AC & BLITTER_BA[];
SR_VDMP[7..4] = FB_B[]; -- BYTE ENABLE WRITE
SR_VDMP[3..0] = LINE & B"1111"; -- LINE ENABLE WRITE
SR_VDMP[7..4] = FB_B[] # BLITTER_AC & B"1111"; -- BYTE ENABLE WRITE, BEI BLITTER IMMER LINE
SR_VDMP[3..0] = (LINE # BLITTER_AC) & B"1111"; -- LINE ENABLE WRITE, BEI BLITTER IMMER LINE
DDR_SM = DS_T6W;
WHEN DS_T6W =>
@@ -384,7 +384,7 @@ BEGIN
VWE = VCC;
SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV
SR_VDMP[] = (LINE # BLITTER_AC) & B"11111111"; -- WENN LINE DANN ACTIV
DDR_SM = DS_T7W;
WHEN DS_T7W =>

1
FPGA_by_Fredi/Video/DDR_CTR.tdf.bak
View File

@@ -43,7 +43,6 @@ SUBDESIGN DDR_CTR
nVCAS : OUTPUT;
FB_LE[3..0] : OUTPUT;
FB_VDOE[3..0] : OUTPUT;
CLEAR_FIFO_CNT : OUTPUT;
SR_FIFO_WRE : OUTPUT;
SR_DDR_FB : OUTPUT;
SR_DDR_WR : OUTPUT;

2
FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
View File

@@ -620,7 +620,7 @@ BEGIN
VERZ[][8] = VERZ[][7];
VERZ[][9] = VERZ[][8];
VERZ[0][0] = DISP_ON;
VERZ[1][0] = HSYNC_I[]!=0;
-- VERZ[1][0] = HSYNC_I[]!=0;
VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
# ACP_VCTR15 & VDL_VCT6 & HSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE
VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0

6
FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
View File

@@ -650,11 +650,11 @@ BEGIN
START_ZEILE.ENA = LAST;
START_ZEILE = VVCNT[]==0; -- ZEILE 1
SYNC_PIX.CLK = PIXEL_CLK;
SYNC_PIX = VHCNT[]==1 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX = VHCNT[]==3 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX1.CLK = PIXEL_CLK;
SYNC_PIX1 = VHCNT[]==3 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX1 = VHCNT[]==5 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX2.CLK = PIXEL_CLK;
SYNC_PIX2 = VHCNT[]==5 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX2 = VHCNT[]==7 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX; --count up if display on sonst clear bei sync pix

380
FPGA_by_Fredi/Video/Video.bdf
View File

@@ -6758,124 +6758,6 @@ applicable agreement for further details.
(line (pt 22 96)(pt 16 102)(line_width 1))
)
)
(block
(rect 296 2552 568 3000)
(text "BLITTER" (rect 5 5 65 21)(font "Arial" (font_size 8))) (text "BLITTER" (rect 5 434 62 449)(font "Arial" )) (block_io "nRSTO" (input))
(block_io "MAIN_CLK" (input))
(block_io "FB_ALE" (input))
(block_io "nFB_WR" (input))
(block_io "nFB_OE" (input))
(block_io "FB_SIZE0" (input))
(block_io "FB_SIZE1" (input))
(block_io "VIDEO_RAM_CTR[15..0]" (input))
(block_io "BLITTER_ON" (input))
(block_io "FB_ADR[31..0]" (input))
(block_io "nFB_CS1" (input))
(block_io "nFB_CS2" (input))
(block_io "nFB_CS3" (input))
(block_io "DDRCLK0" (input))
(block_io "BLITTER_DIN[127..0]" (input))
(block_io "BLITTER_DACK[4..0]" (input))
(block_io "BLITTER_RUN" (output))
(block_io "BLITTER_DOUT[127..0]" (output))
(block_io "BLITTER_ADR[31..0]" (output))
(block_io "BLITTER_SIG" (output))
(block_io "BLITTER_WR" (output))
(block_io "BLITTER_TA" (output))
(block_io "FB_AD[31..0]" (bidir))
(mapper
(pt 272 176)
(bidir)
)
(mapper
(pt 272 208)
(bidir)
)
(mapper
(pt 272 240)
(bidir)
)
(mapper
(pt 272 264)
(bidir)
)
(mapper
(pt 272 288)
(bidir)
)
(mapper
(pt 0 384)
(bidir)
)
(mapper
(pt 272 72)
(bidir)
)
(mapper
(pt 0 56)
(bidir)
)
(mapper
(pt 0 32)
(bidir)
)
(mapper
(pt 0 296)
(bidir)
)
(mapper
(pt 0 272)
(bidir)
)
(mapper
(pt 0 104)
(bidir)
)
(mapper
(pt 0 128)
(bidir)
)
(mapper
(pt 0 80)
(bidir)
)
(mapper
(pt 0 248)
(bidir)
)
(mapper
(pt 0 224)
(bidir)
)
(mapper
(pt 0 200)
(bidir)
)
(mapper
(pt 0 176)
(bidir)
)
(mapper
(pt 0 152)
(bidir)
)
(mapper
(pt 0 360)
(bidir)
)
(mapper
(pt 0 328)
(bidir)
)
(mapper
(pt 272 424)
(bidir)
)
(mapper
(pt 0 408)
(bidir)
)
)
(block
(rect 1664 1664 2016 2600)
(text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 5 211 21)(font "Arial" (font_size 8))) (text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 922 200 937)(font "Arial" )) (block_io "nRSTO" (input))
@@ -7322,6 +7204,129 @@ applicable agreement for further details.
(bidir)
)
)
(block
(rect 296 2552 568 3040)
(text "BLITTER" (rect 5 5 65 21)(font "Arial" (font_size 8))) (text "BLITTER" (rect 5 474 62 489)(font "Arial" )) (block_io "nRSTO" (input))
(block_io "MAIN_CLK" (input))
(block_io "FB_ALE" (input))
(block_io "nFB_WR" (input))
(block_io "nFB_OE" (input))
(block_io "FB_SIZE0" (input))
(block_io "FB_SIZE1" (input))
(block_io "VIDEO_RAM_CTR[15..0]" (input))
(block_io "BLITTER_ON" (input))
(block_io "FB_ADR[31..0]" (input))
(block_io "nFB_CS1" (input))
(block_io "nFB_CS2" (input))
(block_io "nFB_CS3" (input))
(block_io "DDRCLK0" (input))
(block_io "BLITTER_DIN[127..0]" (input))
(block_io "BLITTER_DACK[4..0]" (input))
(block_io "SR_BLITTER_DACK" (input))
(block_io "BLITTER_RUN" (output))
(block_io "BLITTER_DOUT[127..0]" (output))
(block_io "BLITTER_ADR[31..0]" (output))
(block_io "BLITTER_SIG" (output))
(block_io "BLITTER_WR" (output))
(block_io "BLITTER_TA" (output))
(block_io "FB_AD[31..0]" (bidir))
(mapper
(pt 272 176)
(bidir)
)
(mapper
(pt 272 208)
(bidir)
)
(mapper
(pt 272 240)
(bidir)
)
(mapper
(pt 272 264)
(bidir)
)
(mapper
(pt 272 288)
(bidir)
)
(mapper
(pt 0 384)
(bidir)
)
(mapper
(pt 272 72)
(bidir)
)
(mapper
(pt 0 56)
(bidir)
)
(mapper
(pt 0 32)
(bidir)
)
(mapper
(pt 0 296)
(bidir)
)
(mapper
(pt 0 272)
(bidir)
)
(mapper
(pt 0 104)
(bidir)
)
(mapper
(pt 0 128)
(bidir)
)
(mapper
(pt 0 80)
(bidir)
)
(mapper
(pt 0 248)
(bidir)
)
(mapper
(pt 0 224)
(bidir)
)
(mapper
(pt 0 200)
(bidir)
)
(mapper
(pt 0 176)
(bidir)
)
(mapper
(pt 0 152)
(bidir)
)
(mapper
(pt 0 360)
(bidir)
)
(mapper
(pt 0 328)
(bidir)
)
(mapper
(pt 272 424)
(bidir)
)
(mapper
(pt 0 408)
(bidir)
)
(mapper
(pt 0 440)
(bidir)
)
)
(connector
(text "CLUT_ADR0" (rect 2786 1272 2869 1287)(font "Arial" ))
(pt 2776 1288)
@@ -8363,34 +8368,12 @@ applicable agreement for further details.
(pt 560 2376)
(pt 664 2376)
)
(connector
(text "BLITTER_ON" (rect 226 2920 313 2935)(font "Arial" ))
(pt 296 2936)
(pt 216 2936)
)
(connector
(text "BLITTER_RUN" (rect 578 2712 675 2727)(font "Arial" ))
(pt 568 2728)
(pt 648 2728)
)
(connector
(text "VDVZ[127..0]" (rect 810 2920 892 2935)(font "Arial" ))
(pt 800 2936)
(pt 888 2936)
(bus)
)
(connector
(text "BLITTER_DOUT[127..0]" (rect 578 2744 731 2759)(font "Arial" ))
(pt 680 2760)
(pt 568 2760)
(bus)
)
(connector
(text "BLITTER_ADR[31..0]" (rect 578 2776 712 2791)(font "Arial" ))
(pt 568 2792)
(pt 680 2792)
(bus)
)
(connector
(text "BLITTER_SIG" (rect 578 2800 667 2815)(font "Arial" ))
(pt 568 2816)
@@ -8457,12 +8440,6 @@ applicable agreement for further details.
(pt 192 2584)
(pt 296 2584)
)
(connector
(text "VIDEO_RAM_CTR[15..0]" (rect 178 2896 334 2911)(font "Arial" ))
(pt 296 2912)
(pt 168 2912)
(bus)
)
(connector
(text "FB_AD[31..0]" (rect 578 2608 661 2623)(font "Arial" ))
(pt 688 2624)
@@ -8613,23 +8590,6 @@ applicable agreement for further details.
(pt 1192 1288)
(bus)
)
(connector
(text "BLITTER_DACK[0]" (rect 802 2952 922 2967)(font "Arial" ))
(pt 888 2968)
(pt 808 2968)
)
(connector
(text "BLITTER_DIN[127..0]" (rect 1042 2944 1180 2959)(font "Arial" ))
(pt 1144 2960)
(pt 1032 2960)
(bus)
)
(connector
(text "BLITTER_DIN[127..0]" (rect 194 2944 332 2959)(font "Arial" ))
(pt 296 2960)
(pt 184 2960)
(bus)
)
(connector
(text "SR_BLITTER_DACK" (rect 570 2464 703 2479)(font "Arial" ))
(pt 664 2480)
@@ -8671,12 +8631,6 @@ applicable agreement for further details.
(pt 1168 2192)
(bus)
)
(connector
(text "BLITTER_DACK[4..0]" (rect 202 2864 337 2879)(font "Arial" ))
(pt 192 2880)
(pt 296 2880)
(bus)
)
(connector
(text "CLK33M" (rect 218 2432 273 2447)(font "Arial" ))
(pt 208 2448)
@@ -8971,22 +8925,6 @@ applicable agreement for further details.
(pt 1032 2400)
(pt 1096 2400)
)
(connector
(text "SR_BLITTER_DACK" (rect 810 2560 943 2575)(font "Arial" ))
(pt 904 2576)
(pt 800 2576)
)
(connector
(text "DDRCLK0" (rect 826 2544 894 2559)(font "Arial" ))
(pt 816 2560)
(pt 904 2560)
)
(connector
(text "BLITTER_DACK[4..0]" (rect 1058 2560 1193 2575)(font "Arial" ))
(pt 1048 2576)
(pt 1152 2576)
(bus)
)
(connector
(text "DDRCLK2" (rect 1018 2672 1086 2687)(font "Arial" ))
(pt 1008 2688)
@@ -10625,6 +10563,78 @@ applicable agreement for further details.
(pt 1712 1472)
(pt 1632 1472)
)
(connector
(text "BLITTER_DACK[4..0]" (rect 178 2864 313 2879)(font "Arial" ))
(pt 296 2880)
(pt 184 2880)
(bus)
)
(connector
(text "VIDEO_RAM_CTR[15..0]" (rect 154 2896 310 2911)(font "Arial" ))
(pt 296 2912)
(pt 144 2912)
(bus)
)
(connector
(text "BLITTER_ON" (rect 202 2920 289 2935)(font "Arial" ))
(pt 296 2936)
(pt 192 2936)
)
(connector
(text "BLITTER_DIN[127..0]" (rect 162 2944 300 2959)(font "Arial" ))
(pt 296 2960)
(pt 152 2960)
(bus)
)
(connector
(text "SR_BLITTER_DACK" (rect 778 2560 911 2575)(font "Arial" ))
(pt 904 2576)
(pt 768 2576)
)
(connector
(text "DDRCLK0" (rect 794 2544 862 2559)(font "Arial" ))
(pt 904 2560)
(pt 784 2560)
)
(connector
(text "BLITTER_DACK[4..0]" (rect 1058 2560 1193 2575)(font "Arial" ))
(pt 1176 2576)
(pt 1048 2576)
(bus)
)
(connector
(text "BLITTER_DOUT[127..0]" (rect 578 2744 731 2759)(font "Arial" ))
(pt 712 2760)
(pt 568 2760)
(bus)
)
(connector
(text "BLITTER_ADR[31..0]" (rect 578 2776 712 2791)(font "Arial" ))
(pt 704 2792)
(pt 568 2792)
(bus)
)
(connector
(text "BLITTER_RUN" (rect 578 2712 675 2727)(font "Arial" ))
(pt 672 2728)
(pt 568 2728)
)
(connector
(text "BLITTER_DACK[0]" (rect 778 2952 898 2967)(font "Arial" ))
(pt 776 2968)
(pt 888 2968)
)
(connector
(text "SR_BLITTER_DACK" (rect 170 2976 303 2991)(font "Arial" ))
(pt 296 2992)
(pt 160 2992)
)
(connector
(text "BLITTER_DIN[127..0]" (rect 1042 2944 1180 2959)(font "Arial" ))
(pt 1160 2960)
(pt 1032 2960)
(bus)
)
(junction (pt 2984 1688))
(junction (pt 792 1192))
(junction (pt 792 1312))

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71
FPGA_by_Fredi/altiobuf_bidir0.bsf Normal file
View File

@@ -0,0 +1,71 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 232 216)
(text "altiobuf_bidir0" (rect 65 1 185 20)(font "Arial" (font_size 10)))
(text "inst" (rect 8 197 31 212)(font "Arial" ))
(port
(pt 0 176)
(input)
(text "datain[0]" (rect 0 0 59 16)(font "Arial" (font_size 8)))
(text "datain[0]" (rect 4 160 54 176)(font "Arial" (font_size 8)))
(line (pt 0 176)(pt 100 176)(line_width 3))
)
(port
(pt 0 144)
(input)
(text "oe[0]" (rect 0 0 34 16)(font "Arial" (font_size 8)))
(text "oe[0]" (rect 4 128 33 144)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 105 144)(line_width 3))
)
(port
(pt 232 56)
(output)
(text "dataout[0]" (rect 0 0 68 16)(font "Arial" (font_size 8)))
(text "dataout[0]" (rect 171 40 229 56)(font "Arial" (font_size 8)))
(line (pt 232 56)(pt 80 56)(line_width 3))
)
(port
(pt 232 176)
(bidir)
(text "dataio[0]" (rect 0 0 59 16)(font "Arial" (font_size 8)))
(text "dataio[0]" (rect 179 160 229 176)(font "Arial" (font_size 8)))
(line (pt 232 176)(pt 131 176)(line_width 3))
)
(drawing
(line (pt 100 160)(pt 100 192)(line_width 1))
(line (pt 100 160)(pt 132 176)(line_width 1))
(line (pt 100 192)(pt 132 176)(line_width 1))
(line (pt 156 176)(pt 156 80)(line_width 3))
(line (pt 132 80)(pt 156 80)(line_width 3))
(line (pt 105 144)(pt 105 161)(line_width 3))
(line (pt 132 64)(pt 132 96)(line_width 1))
(line (pt 132 64)(pt 100 80)(line_width 1))
(line (pt 132 96)(pt 100 80)(line_width 1))
(line (pt 80 56)(pt 80 80)(line_width 3))
(line (pt 80 80)(pt 100 80)(line_width 3))
(line (pt 0 0)(pt 233 0)(line_width 1))
(line (pt 233 0)(pt 233 217)(line_width 1))
(line (pt 0 217)(pt 233 217)(line_width 1))
(line (pt 0 0)(pt 0 217)(line_width 1))
)
)

24
FPGA_by_Fredi/altiobuf_bidir0.cmp Normal file
View File

@@ -0,0 +1,24 @@
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component altiobuf_bidir0
PORT
(
datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
oe : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataio : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
end component;

25
FPGA_by_Fredi/altiobuf_bidir0.inc Normal file
View File

@@ -0,0 +1,25 @@
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION altiobuf_bidir0
(
datain[0..0],
oe[0..0]
)
RETURNS (
dataio[0..0],
dataout[0..0]
);

6
FPGA_by_Fredi/altiobuf_bidir0.qip Normal file
View File

@@ -0,0 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "ALTIOBUF"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altiobuf_bidir0.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altiobuf_bidir0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altiobuf_bidir0.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altiobuf_bidir0.cmp"]

90
FPGA_by_Fredi/altiobuf_bidir0.tdf Normal file
View File

@@ -0,0 +1,90 @@
-- megafunction wizard: %ALTIOBUF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altiobuf_bidir
-- ============================================================
-- File Name: altiobuf_bidir0.tdf
-- Megafunction Name(s):
-- altiobuf_bidir
--
-- Simulation Library Files(s):
-- cycloneiii
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
-- Clearbox generated function header
FUNCTION altiobuf_bidir0_iobuf_bidir_quo (datain[0..0], oe[0..0])
RETURNS ( dataio[0..0], dataout[0..0]);
SUBDESIGN altiobuf_bidir0
(
datain[0..0] : INPUT;
oe[0..0] : INPUT;
dataio[0..0] : BIDIR;
dataout[0..0] : OUTPUT;
)
VARIABLE
altiobuf_bidir0_iobuf_bidir_quo_component : altiobuf_bidir0_iobuf_bidir_quo;
BEGIN
dataout[0..0] = altiobuf_bidir0_iobuf_bidir_quo_component.dataout[0..0];
dataio[0..0] = altiobuf_bidir0_iobuf_bidir_quo_component.dataio[0..0];
altiobuf_bidir0_iobuf_bidir_quo_component.datain[0..0] = datain[0..0];
altiobuf_bidir0_iobuf_bidir_quo_component.oe[0..0] = oe[0..0];
END;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"
-- Retrieval info: CONSTANT: number_of_channels NUMERIC "1"
-- Retrieval info: CONSTANT: open_drain_output STRING "FALSE"
-- Retrieval info: CONSTANT: use_differential_mode STRING "FALSE"
-- Retrieval info: CONSTANT: use_dynamic_termination_control STRING "FALSE"
-- Retrieval info: CONSTANT: use_termination_control STRING "FALSE"
-- Retrieval info: USED_PORT: datain 0 0 1 0 INPUT NODEFVAL "datain[0..0]"
-- Retrieval info: USED_PORT: dataio 0 0 1 0 BIDIR NODEFVAL "dataio[0..0]"
-- Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
-- Retrieval info: USED_PORT: oe 0 0 1 0 INPUT NODEFVAL "oe[0..0]"
-- Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 1 0
-- Retrieval info: CONNECT: @oe 0 0 1 0 oe 0 0 1 0
-- Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
-- Retrieval info: CONNECT: dataio 0 0 1 0 @dataio 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf_bidir0.tdf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf_bidir0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf_bidir0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf_bidir0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf_bidir0_inst.tdf FALSE
-- Retrieval info: LIB_FILE: cycloneiii

53
FPGA_by_Fredi/altiobuf_bidir0_iobuf_bidir_quo.tdf Normal file
View File

@@ -0,0 +1,53 @@
--altiobuf_bidir CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone III" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" USE_DIFFERENTIAL_MODE="FALSE" USE_DYNAMIC_TERMINATION_CONTROL="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataio dataout oe
--VERSION_BEGIN 9.1SP2 cbx_altiobuf_bidir 2010:03:24:20:43:42:SJ cbx_mgl 2010:03:24:21:01:05:SJ cbx_stratixiii 2010:03:24:20:43:43:SJ VERSION_END
-- Copyright (C) 1991-2010 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION cycloneiii_io_ibuf (i, ibar)
WITH ( bus_hold, differential_mode, simulate_z_as)
RETURNS ( o);
FUNCTION cycloneiii_io_obuf (i, oe, seriesterminationcontrol[TERM_CTRL_WIDTH-1..0])
WITH ( bus_hold, open_drain_output, TERM_CTRL_WIDTH = 16)
RETURNS ( o, obar);
--synthesis_resources = cycloneiii_io_ibuf 1 cycloneiii_io_obuf 1
SUBDESIGN altiobuf_bidir0_iobuf_bidir_quo
(
datain[0..0] : input;
dataio[0..0] : bidir;
dataout[0..0] : output;
oe[0..0] : input;
)
VARIABLE
ibufa[0..0] : cycloneiii_io_ibuf
WITH (
bus_hold = "false"
);
obufa[0..0] : cycloneiii_io_obuf
WITH (
bus_hold = "false",
open_drain_output = "false"
);
BEGIN
ibufa[].i = dataio[];
obufa[].i = datain[];
obufa[].oe = oe[];
dataio[] = obufa[].o;
dataout[] = ibufa[].o;
END;
--VALID FILE

120
FPGA_by_Fredi/altpll1.bsf
View File

@@ -20,81 +20,81 @@ applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 328 216)
(text "altpll1" (rect 144 1 191 20)(font "Arial" (font_size 10)))
(text "inst" (rect 8 197 31 212)(font "Arial" ))
(rect 0 0 272 184)
(text "altpll1" (rect 119 0 159 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 168 25 180)(font "Arial" ))
(port
(pt 0 72)
(pt 0 64)
(input)
(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 48 72)(line_width 1))
(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 40 64)(line_width 1))
)
(port
(pt 328 72)
(pt 272 64)
(output)
(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
(text "c0" (rect 311 56 325 72)(font "Arial" (font_size 8)))
(line (pt 328 72)(pt 272 72)(line_width 1))
(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c0" (rect 257 51 268 64)(font "Arial" (font_size 8)))
(line (pt 272 64)(pt 224 64)(line_width 1))
)
(port
(pt 328 96)
(pt 272 80)
(output)
(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
(text "c1" (rect 311 80 325 96)(font "Arial" (font_size 8)))
(line (pt 328 96)(pt 272 96)(line_width 1))
(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c1" (rect 257 67 268 80)(font "Arial" (font_size 8)))
(line (pt 272 80)(pt 224 80)(line_width 1))
)
(port
(pt 328 120)
(pt 272 96)
(output)
(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
(text "c2" (rect 311 104 325 120)(font "Arial" (font_size 8)))
(line (pt 328 120)(pt 272 120)(line_width 1))
(text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c2" (rect 257 83 268 96)(font "Arial" (font_size 8)))
(line (pt 272 96)(pt 224 96)(line_width 1))
)
(port
(pt 328 144)
(pt 272 112)
(output)
(text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8)))
(text "locked" (rect 287 128 325 144)(font "Arial" (font_size 8)))
(line (pt 328 144)(pt 272 144)(line_width 1))
(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "locked" (rect 238 99 268 112)(font "Arial" (font_size 8)))
(line (pt 272 112)(pt 224 112)(line_width 1))
)
(drawing
(text "Cyclone III" (rect 253 198 301 212)(font "Arial" ))
(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
(text "Clk " (rect 59 111 76 125)(font "Arial" ))
(text "Ratio" (rect 90 111 114 125)(font "Arial" ))
(text "Ph (dg)" (rect 128 111 163 125)(font "Arial" ))
(text "DC (%)" (rect 173 111 208 125)(font "Arial" ))
(text "c0" (rect 63 129 75 143)(font "Arial" ))
(text "1/66" (rect 92 129 113 143)(font "Arial" ))
(text "0.00" (rect 136 129 157 143)(font "Arial" ))
(text "50.00" (rect 178 129 205 143)(font "Arial" ))
(text "c1" (rect 63 147 75 161)(font "Arial" ))
(text "67/900" (rect 85 147 118 161)(font "Arial" ))
(text "0.00" (rect 136 147 157 161)(font "Arial" ))
(text "50.00" (rect 178 147 205 161)(font "Arial" ))
(text "c2" (rect 63 165 75 179)(font "Arial" ))
(text "67/90" (rect 89 165 116 179)(font "Arial" ))
(text "0.00" (rect 136 165 157 179)(font "Arial" ))
(text "50.00" (rect 178 165 205 179)(font "Arial" ))
(line (pt 0 0)(pt 329 0)(line_width 1))
(line (pt 329 0)(pt 329 217)(line_width 1))
(line (pt 0 217)(pt 329 217)(line_width 1))
(line (pt 0 0)(pt 0 217)(line_width 1))
(line (pt 56 108)(pt 215 108)(line_width 1))
(line (pt 56 125)(pt 215 125)(line_width 1))
(line (pt 56 143)(pt 215 143)(line_width 1))
(line (pt 56 161)(pt 215 161)(line_width 1))
(line (pt 56 179)(pt 215 179)(line_width 1))
(line (pt 56 108)(pt 56 179)(line_width 1))
(line (pt 82 108)(pt 82 179)(line_width 3))
(line (pt 125 108)(pt 125 179)(line_width 3))
(line (pt 170 108)(pt 170 179)(line_width 3))
(line (pt 214 108)(pt 214 179)(line_width 1))
(line (pt 48 56)(pt 272 56)(line_width 1))
(line (pt 272 56)(pt 272 200)(line_width 1))
(line (pt 48 200)(pt 272 200)(line_width 1))
(line (pt 48 56)(pt 48 200)(line_width 1))
(text "Cyclone III" (rect 211 169 258 181)(font "Arial" ))
(text "inclk0 frequency: 33.000 MHz" (rect 50 59 175 71)(font "Arial" ))
(text "Operation Mode: Src Sync Comp" (rect 50 73 188 85)(font "Arial" ))
(text "Clk " (rect 51 96 68 108)(font "Arial" ))
(text "Ratio" (rect 83 96 105 108)(font "Arial" ))
(text "Ph (dg)" (rect 121 96 151 108)(font "Arial" ))
(text "DC (%)" (rect 156 96 187 108)(font "Arial" ))
(text "c0" (rect 54 111 64 123)(font "Arial" ))
(text "16/11" (rect 83 111 106 123)(font "Arial" ))
(text "0.00" (rect 127 111 145 123)(font "Arial" ))
(text "50.00" (rect 160 111 183 123)(font "Arial" ))
(text "c1" (rect 54 126 64 138)(font "Arial" ))
(text "16/33" (rect 83 126 106 138)(font "Arial" ))
(text "0.00" (rect 127 126 145 138)(font "Arial" ))
(text "50.00" (rect 160 126 183 138)(font "Arial" ))
(text "c2" (rect 54 141 64 153)(font "Arial" ))
(text "1024/1375" (rect 73 141 116 153)(font "Arial" ))
(text "0.00" (rect 127 141 145 153)(font "Arial" ))
(text "50.00" (rect 160 141 183 153)(font "Arial" ))
(line (pt 0 0)(pt 273 0)(line_width 1))
(line (pt 273 0)(pt 273 185)(line_width 1))
(line (pt 0 185)(pt 273 185)(line_width 1))
(line (pt 0 0)(pt 0 185)(line_width 1))
(line (pt 48 94)(pt 189 94)(line_width 1))
(line (pt 48 108)(pt 189 108)(line_width 1))
(line (pt 48 123)(pt 189 123)(line_width 1))
(line (pt 48 138)(pt 189 138)(line_width 1))
(line (pt 48 153)(pt 189 153)(line_width 1))
(line (pt 48 94)(pt 48 153)(line_width 1))
(line (pt 70 94)(pt 70 153)(line_width 3))
(line (pt 118 94)(pt 118 153)(line_width 3))
(line (pt 153 94)(pt 153 153)(line_width 3))
(line (pt 188 94)(pt 188 153)(line_width 1))
(line (pt 40 48)(pt 224 48)(line_width 1))
(line (pt 224 48)(pt 224 168)(line_width 1))
(line (pt 40 168)(pt 224 168)(line_width 1))
(line (pt 40 48)(pt 40 168)(line_width 1))
)
)

46
FPGA_by_Fredi/altpll1.vhd
View File

@@ -153,17 +153,17 @@ BEGIN
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 66,
clk0_divide_by => 11,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_multiply_by => 16,
clk0_phase_shift => "0",
clk1_divide_by => 900,
clk1_divide_by => 33,
clk1_duty_cycle => 50,
clk1_multiply_by => 67,
clk1_multiply_by => 16,
clk1_phase_shift => "0",
clk2_divide_by => 90,
clk2_divide_by => 1375,
clk2_duty_cycle => 50,
clk2_multiply_by => 67,
clk2_multiply_by => 1024,
clk2_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 30303,
@@ -244,15 +244,15 @@ END SYN;
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "90"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "90"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.500000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.456667"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.566668"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.576000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -272,23 +272,23 @@ END SYN;
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "67"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "67"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.50000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.45760000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
@@ -298,7 +298,7 @@ END SYN;
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
@@ -338,17 +338,17 @@ END SYN;
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "66"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "900"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "67"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "90"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1375"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "67"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1024"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"

137
FPGA_by_Fredi/altpll3.bsf
View File

@@ -20,86 +20,93 @@ applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 304 232)
(text "altpll3" (rect 132 1 179 20)(font "Arial" (font_size 10)))
(text "inst" (rect 8 213 31 228)(font "Arial" ))
(rect 0 0 272 200)
(text "altpll3" (rect 119 0 159 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 184 25 196)(font "Arial" ))
(port
(pt 0 72)
(pt 0 64)
(input)
(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 48 72)(line_width 1))
(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 40 64)(line_width 1))
)
(port
(pt 304 72)
(pt 272 64)
(output)
(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
(text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8)))
(line (pt 304 72)(pt 272 72)(line_width 1))
(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c0" (rect 257 51 268 64)(font "Arial" (font_size 8)))
(line (pt 272 64)(pt 224 64)(line_width 1))
)
(port
(pt 304 96)
(pt 272 80)
(output)
(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
(text "c1" (rect 287 80 301 96)(font "Arial" (font_size 8)))
(line (pt 304 96)(pt 272 96)(line_width 1))
(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c1" (rect 257 67 268 80)(font "Arial" (font_size 8)))
(line (pt 272 80)(pt 224 80)(line_width 1))
)
(port
(pt 304 120)
(pt 272 96)
(output)
(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
(text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8)))
(line (pt 304 120)(pt 272 120)(line_width 1))
(text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c2" (rect 257 83 268 96)(font "Arial" (font_size 8)))
(line (pt 272 96)(pt 224 96)(line_width 1))
)
(port
(pt 304 144)
(pt 272 112)
(output)
(text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8)))
(text "c3" (rect 287 128 301 144)(font "Arial" (font_size 8)))
(line (pt 304 144)(pt 272 144)(line_width 1))
(text "c3" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c3" (rect 257 99 268 112)(font "Arial" (font_size 8)))
(line (pt 272 112)(pt 224 112)(line_width 1))
)
(port
(pt 272 128)
(output)
(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "locked" (rect 238 115 268 128)(font "Arial" (font_size 8)))
(line (pt 272 128)(pt 224 128)(line_width 1))
)
(drawing
(text "Cyclone III" (rect 229 214 277 228)(font "Arial" ))
(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
(text "Clk " (rect 59 111 76 125)(font "Arial" ))
(text "Ratio" (rect 86 111 110 125)(font "Arial" ))
(text "Ph (dg)" (rect 121 111 156 125)(font "Arial" ))
(text "DC (%)" (rect 166 111 201 125)(font "Arial" ))
(text "c0" (rect 63 129 75 143)(font "Arial" ))
(text "2/33" (rect 88 129 109 143)(font "Arial" ))
(text "0.00" (rect 129 129 150 143)(font "Arial" ))
(text "50.00" (rect 171 129 198 143)(font "Arial" ))
(text "c1" (rect 63 147 75 161)(font "Arial" ))
(text "16/33" (rect 85 147 112 161)(font "Arial" ))
(text "0.00" (rect 129 147 150 161)(font "Arial" ))
(text "50.00" (rect 171 147 198 161)(font "Arial" ))
(text "c2" (rect 63 165 75 179)(font "Arial" ))
(text "25/33" (rect 85 165 112 179)(font "Arial" ))
(text "0.00" (rect 129 165 150 179)(font "Arial" ))
(text "50.00" (rect 171 165 198 179)(font "Arial" ))
(text "c3" (rect 63 183 75 197)(font "Arial" ))
(text "16/11" (rect 85 183 112 197)(font "Arial" ))
(text "0.00" (rect 129 183 150 197)(font "Arial" ))
(text "50.00" (rect 171 183 198 197)(font "Arial" ))
(line (pt 0 0)(pt 305 0)(line_width 1))
(line (pt 305 0)(pt 305 233)(line_width 1))
(line (pt 0 233)(pt 305 233)(line_width 1))
(line (pt 0 0)(pt 0 233)(line_width 1))
(line (pt 56 108)(pt 208 108)(line_width 1))
(line (pt 56 125)(pt 208 125)(line_width 1))
(line (pt 56 143)(pt 208 143)(line_width 1))
(line (pt 56 161)(pt 208 161)(line_width 1))
(line (pt 56 179)(pt 208 179)(line_width 1))
(line (pt 56 197)(pt 208 197)(line_width 1))
(line (pt 56 108)(pt 56 197)(line_width 1))
(line (pt 82 108)(pt 82 197)(line_width 3))
(line (pt 118 108)(pt 118 197)(line_width 3))
(line (pt 163 108)(pt 163 197)(line_width 3))
(line (pt 207 108)(pt 207 197)(line_width 1))
(line (pt 48 56)(pt 272 56)(line_width 1))
(line (pt 272 56)(pt 272 216)(line_width 1))
(line (pt 48 216)(pt 272 216)(line_width 1))
(line (pt 48 56)(pt 48 216)(line_width 1))
(text "Cyclone III" (rect 211 185 258 197)(font "Arial" ))
(text "inclk0 frequency: 33.000 MHz" (rect 50 59 175 71)(font "Arial" ))
(text "Operation Mode: Src Sync Comp" (rect 50 73 188 85)(font "Arial" ))
(text "Clk " (rect 51 96 68 108)(font "Arial" ))
(text "Ratio" (rect 81 96 103 108)(font "Arial" ))
(text "Ph (dg)" (rect 116 96 146 108)(font "Arial" ))
(text "DC (%)" (rect 151 96 182 108)(font "Arial" ))
(text "c0" (rect 54 111 64 123)(font "Arial" ))
(text "25/33" (rect 81 111 104 123)(font "Arial" ))
(text "0.00" (rect 122 111 140 123)(font "Arial" ))
(text "50.00" (rect 155 111 178 123)(font "Arial" ))
(text "c1" (rect 54 126 64 138)(font "Arial" ))
(text "2/33" (rect 83 126 101 138)(font "Arial" ))
(text "0.00" (rect 122 126 140 138)(font "Arial" ))
(text "50.00" (rect 155 126 178 138)(font "Arial" ))
(text "c2" (rect 54 141 64 153)(font "Arial" ))
(text "1/66" (rect 83 141 101 153)(font "Arial" ))
(text "0.00" (rect 122 141 140 153)(font "Arial" ))
(text "50.00" (rect 155 141 178 153)(font "Arial" ))
(text "c3" (rect 54 156 64 168)(font "Arial" ))
(text "512/6875" (rect 73 156 111 168)(font "Arial" ))
(text "0.00" (rect 122 156 140 168)(font "Arial" ))
(text "50.00" (rect 155 156 178 168)(font "Arial" ))
(line (pt 0 0)(pt 273 0)(line_width 1))
(line (pt 273 0)(pt 273 201)(line_width 1))
(line (pt 0 201)(pt 273 201)(line_width 1))
(line (pt 0 0)(pt 0 201)(line_width 1))
(line (pt 48 94)(pt 184 94)(line_width 1))
(line (pt 48 108)(pt 184 108)(line_width 1))
(line (pt 48 123)(pt 184 123)(line_width 1))
(line (pt 48 138)(pt 184 138)(line_width 1))
(line (pt 48 153)(pt 184 153)(line_width 1))
(line (pt 48 168)(pt 184 168)(line_width 1))
(line (pt 48 94)(pt 48 168)(line_width 1))
(line (pt 70 94)(pt 70 168)(line_width 3))
(line (pt 113 94)(pt 113 168)(line_width 3))
(line (pt 148 94)(pt 148 168)(line_width 3))
(line (pt 183 94)(pt 183 168)(line_width 1))
(line (pt 40 48)(pt 224 48)(line_width 1))
(line (pt 224 48)(pt 224 184)(line_width 1))
(line (pt 40 184)(pt 224 184)(line_width 1))
(line (pt 40 48)(pt 40 184)(line_width 1))
)
)

3
FPGA_by_Fredi/altpll3.cmp
View File

@@ -20,6 +20,7 @@ component altpll3
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC
c3 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;

3
FPGA_by_Fredi/altpll3.inc
View File

@@ -22,5 +22,6 @@ RETURNS (
c0,
c1,
c2,
c3
c3,
locked
);

1
FPGA_by_Fredi/altpll3.ppf
View File

@@ -7,6 +7,7 @@
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="c2" direction="output" scope="external" source="clock" />
<pin name="c3" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>

108
FPGA_by_Fredi/altpll3.vhd
View File

@@ -46,7 +46,8 @@ ENTITY altpll3 IS
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC
c3 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END altpll3;
@@ -59,9 +60,10 @@ ARCHITECTURE SYN OF altpll3 IS
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
@@ -131,17 +133,19 @@ ARCHITECTURE SYN OF altpll3 IS
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire8_bv(0 DOWNTO 0) <= "0";
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
sub_wire4 <= sub_wire0(3);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
@@ -150,29 +154,30 @@ BEGIN
c1 <= sub_wire2;
c2 <= sub_wire3;
c3 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
locked <= sub_wire5;
sub_wire6 <= inclk0;
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 33,
clk0_duty_cycle => 50,
clk0_multiply_by => 2,
clk0_multiply_by => 25,
clk0_phase_shift => "0",
clk1_divide_by => 33,
clk1_duty_cycle => 50,
clk1_multiply_by => 16,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
clk2_divide_by => 33,
clk2_divide_by => 66,
clk2_duty_cycle => 50,
clk2_multiply_by => 25,
clk2_multiply_by => 1,
clk2_phase_shift => "0",
clk3_divide_by => 11,
clk3_divide_by => 6875,
clk3_duty_cycle => 50,
clk3_multiply_by => 16,
clk3_multiply_by => 512,
clk3_phase_shift => "0",
compensate_clock => "CLK1",
compensate_clock => "CLK0",
inclk0_input_frequency => 30303,
intended_device_family => "Cyclone III",
lpm_type => "altpll",
@@ -188,7 +193,7 @@ BEGIN
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
@@ -219,11 +224,13 @@ BEGIN
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire6,
clk => sub_wire0
inclk => sub_wire7,
clk => sub_wire0,
locked => sub_wire5
);
@@ -246,21 +253,21 @@ END SYN;
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "33"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "33"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "33"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "72"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "906"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "3072"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "738"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "0.500000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "2.457600"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -276,7 +283,7 @@ END SYN;
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
@@ -289,19 +296,19 @@ END SYN;
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "25"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "48"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "55"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "55"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "55"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "55"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "160.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "0.50000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "2.45760000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
@@ -316,7 +323,7 @@ END SYN;
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ns"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -359,21 +366,21 @@ END SYN;
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "33"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "66"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "11"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6875"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "512"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
@@ -389,7 +396,7 @@ END SYN;
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
@@ -420,6 +427,7 @@ END SYN;
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
@@ -428,6 +436,8 @@ END SYN;
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1

128
FPGA_by_Fredi/firebee1.asm.rpt
View File

@@ -1,128 +0,0 @@
Assembler report for firebee1
Wed Dec 15 02:25:13 2010
Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: C:/FireBee/FPGA/firebee1.sof
6. Assembler Device Options: C:/FireBee/FPGA/firebee1.rbf
7. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Wed Dec 15 02:25:13 2010 ;
; Revision Name ; firebee1 ;
; Top-level Entity Name ; firebee1 ;
; Family ; Cyclone III ;
; Device ; EP3C40F484C6 ;
+-----------------------+---------------------------------------+
+----------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+-----------------------------------------------------------------------------+------------+---------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------------+------------+---------------+
; Generate Raw Binary File (.rbf) For Target Device ; On ; Off ;
; Hexadecimal Output File start address ; 0XE0700000 ; 0 ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Generate compressed bitstreams ; On ; On ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; Auto user code ; Off ; Off ;
; Use configuration device ; Off ; Off ;
; Configuration device ; Auto ; Auto ;
; Configuration device auto user code ; Off ; Off ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Release clears before tri-states ; Off ; Off ;
; Auto-restart configuration after error ; On ; On ;
; Enable OCT_DONE ; Off ; Off ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
+-----------------------------------------------------------------------------+------------+---------------+
+------------------------------+
; Assembler Generated Files ;
+------------------------------+
; File Name ;
+------------------------------+
; C:/FireBee/FPGA/firebee1.sof ;
; C:/FireBee/FPGA/firebee1.rbf ;
+------------------------------+
+--------------------------------------------------------+
; Assembler Device Options: C:/FireBee/FPGA/firebee1.sof ;
+----------------+---------------------------------------+
; Option ; Setting ;
+----------------+---------------------------------------+
; Device ; EP3C40F484C6 ;
; JTAG usercode ; 0xFFFFFFFF ;
; Checksum ; 0x0085E8C6 ;
+----------------+---------------------------------------+
+--------------------------------------------------------+
; Assembler Device Options: C:/FireBee/FPGA/firebee1.rbf ;
+---------------------+----------------------------------+
; Option ; Setting ;
+---------------------+----------------------------------+
; Raw Binary File ; ;
; Compression Ratio ; 2 ;
+---------------------+----------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
Info: Processing started: Wed Dec 15 02:25:08 2010
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 291 megabytes
Info: Processing ended: Wed Dec 15 02:25:13 2010
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:05

5016
FPGA_by_Fredi/firebee1.bdf
View File

File diff suppressed because it is too large Load Diff

2
FPGA_by_Fredi/firebee1.done
View File

@@ -1 +1 @@
Wed Dec 15 02:25:24 2010
Fri Aug 28 13:39:52 2015

6866
FPGA_by_Fredi/firebee1.fit.rpt
View File

File diff suppressed because it is too large Load Diff

12
FPGA_by_Fredi/firebee1.fit.summary
View File

@@ -1,16 +1,16 @@
Fitter Status : Successful - Wed Dec 15 02:25:02 2010
Fitter Status : Successful - Fri Aug 28 13:39:32 2015
Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
Revision Name : firebee1
Top-level Entity Name : firebee1
Family : Cyclone III
Device : EP3C40F484C6
Timing Models : Final
Total logic elements : 9,526 / 39,600 ( 24 % )
Total combinational functions : 8,061 / 39,600 ( 20 % )
Dedicated logic registers : 4,563 / 39,600 ( 12 % )
Total registers : 4749
Total logic elements : 10,207 / 39,600 ( 26 % )
Total combinational functions : 8,661 / 39,600 ( 22 % )
Dedicated logic registers : 5,025 / 39,600 ( 13 % )
Total registers : 5162
Total pins : 295 / 332 ( 89 % )
Total virtual pins : 0
Total memory bits : 109,344 / 1,161,216 ( 9 % )
Total memory bits : 109,600 / 1,161,216 ( 9 % )
Embedded Multiplier 9-bit elements : 6 / 252 ( 2 % )
Total PLLs : 4 / 4 ( 100 % )

380
FPGA_by_Fredi/firebee1.flow.rpt
View File

@@ -1,380 +0,0 @@
Flow report for firebee1
Wed Dec 15 02:25:22 2010
Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+----------------------------------------------+
; Flow Status ; Successful - Wed Dec 15 02:25:21 2010 ;
; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
; Revision Name ; firebee1 ;
; Top-level Entity Name ; firebee1 ;
; Family ; Cyclone III ;
; Device ; EP3C40F484C6 ;
; Timing Models ; Final ;
; Met timing requirements ; No ;
; Total logic elements ; 9,526 / 39,600 ( 24 % ) ;
; Total combinational functions ; 8,061 / 39,600 ( 20 % ) ;
; Dedicated logic registers ; 4,563 / 39,600 ( 12 % ) ;
; Total registers ; 4749 ;
; Total pins ; 295 / 332 ( 89 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 109,344 / 1,161,216 ( 9 % ) ;
; Embedded Multiplier 9-bit elements ; 6 / 252 ( 2 % ) ;
; Total PLLs ; 4 / 4 ( 100 % ) ;
+------------------------------------+----------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 12/15/2010 02:20:37 ;
; Main task ; Compilation ;
; Revision Name ; firebee1 ;
+-------------------+---------------------+
+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-----------------------------------------+------------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-----------------------------------------+------------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 150661768621.129237603704664 ; -- ; -- ; -- ;
; CYCLONEII_OPTIMIZATION_TECHNIQUE ; Speed ; Balanced ; -- ; -- ;
; FMAX_REQUIREMENT ; 30 ns ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_COUNTER ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_RAM_DP+ ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_RAM_DP+ ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_RAM_DP+ ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_LATCH ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_COMPARE ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_FF ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_FF ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_FF ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTDDIO_BIDIR ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_FIFO+ ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_FIFO+ ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTPLL_RECONFIG ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; MISC_FILE ; C:/firebee/FPGA/firebee1.dpf ; -- ; -- ; -- ;
; MISC_FILE ; altpll1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; altpll1.inc ; -- ; -- ; -- ;
; MISC_FILE ; altpll1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; altpll1.ppf ; -- ; -- ; -- ;
; MISC_FILE ; altpll2.bsf ; -- ; -- ; -- ;
; MISC_FILE ; altpll2.inc ; -- ; -- ; -- ;
; MISC_FILE ; altpll2.cmp ; -- ; -- ; -- ;
; MISC_FILE ; altpll2.ppf ; -- ; -- ; -- ;
; MISC_FILE ; altpll3.bsf ; -- ; -- ; -- ;
; MISC_FILE ; altpll3.inc ; -- ; -- ; -- ;
; MISC_FILE ; altpll3.cmp ; -- ; -- ; -- ;
; MISC_FILE ; altpll3.ppf ; -- ; -- ; -- ;
; MISC_FILE ; altpll0.bsf ; -- ; -- ; -- ;
; MISC_FILE ; altpll0.inc ; -- ; -- ; -- ;
; MISC_FILE ; altpll0.cmp ; -- ; -- ; -- ;
; MISC_FILE ; altpll0.ppf ; -- ; -- ; -- ;
; MISC_FILE ; lpm_counter0.bsf ; -- ; -- ; -- ;
; MISC_FILE ; lpm_counter0.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg0.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg0.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg0.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/altdpram0.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/altdpram0.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/altdpram0.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_bustri1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_bustri1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/altdpram1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/altdpram1.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/altdpram1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_bustri2.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_bustri2.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_bustri4.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_bustri4.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant0.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant0.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant1.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux0.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux0.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux0.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux1.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux2.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux2.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux2.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant2.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant2.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/altdpram2.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/altdpram2.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/altdpram2.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_bustri6.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_bustri6.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux3.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux3.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux4.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux4.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant3.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant3.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_latch1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_latch1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant4.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant4.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant4.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg2.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg2.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_compare1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_compare1.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_compare1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; lpm_bustri_LONG.bsf ; -- ; -- ; -- ;
; MISC_FILE ; lpm_bustri_LONG.inc ; -- ; -- ; -- ;
; MISC_FILE ; lpm_bustri_LONG.cmp ; -- ; -- ; -- ;
; MISC_FILE ; lpm_bustri_BYT.bsf ; -- ; -- ; -- ;
; MISC_FILE ; lpm_bustri_BYT.inc ; -- ; -- ; -- ;
; MISC_FILE ; lpm_bustri_BYT.cmp ; -- ; -- ; -- ;
; MISC_FILE ; lpm_bustri_WORD.bsf ; -- ; -- ; -- ;
; MISC_FILE ; lpm_bustri_WORD.inc ; -- ; -- ; -- ;
; MISC_FILE ; lpm_bustri_WORD.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_ff4.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_ff4.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_ff4.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_ff5.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_ff5.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_ff5.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_ff6.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_ff6.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_ff6.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg3.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg3.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg3.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_bidir0.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_bidir0.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_bidir0.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_bidir0.ppf ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out0.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out0.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out0.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out0.ppf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux5.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux5.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux5.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg5.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg5.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg5.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg6.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg6.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg6.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg4.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg4.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg4.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out1.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out1.ppf ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out2.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out2.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out2.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out2.ppf ; -- ; -- ; -- ;
; MISC_FILE ; altddio_out3.bsf ; -- ; -- ; -- ;
; MISC_FILE ; altddio_out3.inc ; -- ; -- ; -- ;
; MISC_FILE ; altddio_out3.cmp ; -- ; -- ; -- ;
; MISC_FILE ; altddio_out3.ppf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux6.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux6.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux6.cmp ; -- ; -- ; -- ;
; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo0.bsf ; -- ; -- ; -- ;
; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo0.cmp ; -- ; -- ; -- ;
; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_muxDZ.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_muxDZ.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_muxVDM.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_muxVDM.cmp ; -- ; -- ; -- ;
; MISC_FILE ; C:/FireBee/FPGA/firebee1.dpf ; -- ; -- ; -- ;
; MISC_FILE ; altpll_reconfig1.tdf ; -- ; -- ; -- ;
; MISC_FILE ; altpll_reconfig1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; altpll_reconfig1.inc ; -- ; -- ; -- ;
; MISC_FILE ; altpll_reconfig1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; altpll4.tdf ; -- ; -- ; -- ;
; MISC_FILE ; altpll4.bsf ; -- ; -- ; -- ;
; MISC_FILE ; altpll4.inc ; -- ; -- ; -- ;
; MISC_FILE ; altpll4.cmp ; -- ; -- ; -- ;
; MISC_FILE ; altpll4.ppf ; -- ; -- ; -- ;
; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; PHYSICAL_SYNTHESIS_COMBO_LOGIC ; On ; Off ; -- ; -- ;
; PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ; On ; Off ; -- ; -- ;
; PHYSICAL_SYNTHESIS_EFFORT ; Fast ; Normal ; -- ; -- ;
; PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ; On ; Off ; -- ; -- ;
; STATE_MACHINE_PROCESSING ; One-Hot ; Auto ; -- ; -- ;
; TCO_REQUIREMENT ; 1 ns ; -- ; -- ; -- ;
; TH_REQUIREMENT ; 1 ns ; -- ; -- ; -- ;
; TPD_REQUIREMENT ; 1 ns ; -- ; -- ; -- ;
; TSU_REQUIREMENT ; 1 ns ; -- ; -- ; -- ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
; USE_TIMEQUEST_TIMING_ANALYZER ; Off ; On ; -- ; -- ;
+-----------------------------------------+------------------------------------+---------------+-------------+----------------+
+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:01:16 ; 1.0 ; 347 MB ; 00:01:17 ;
; Fitter ; 00:03:05 ; 1.0 ; 334 MB ; 00:03:07 ;
; Assembler ; 00:00:05 ; 1.0 ; 291 MB ; 00:00:04 ;
; Classic Timing Analyzer ; 00:00:07 ; 1.0 ; 227 MB ; 00:00:09 ;
; Total ; 00:04:33 ; -- ; -- ; 00:04:37 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+------------------------------------------------------------------------------------------+
; Flow OS Summary ;
+-------------------------+------------------+---------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+-------------------------+------------------+---------------+------------+----------------+
; Analysis & Synthesis ; envy15 ; Windows Vista ; 6.1 ; x86_64 ;
; Fitter ; envy15 ; Windows Vista ; 6.1 ; x86_64 ;
; Assembler ; envy15 ; Windows Vista ; 6.1 ; x86_64 ;
; Classic Timing Analyzer ; envy15 ; Windows Vista ; 6.1 ; x86_64 ;
+-------------------------+------------------+---------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off firebeei1 -c firebee1
quartus_fit --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1
quartus_asm --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1
quartus_tan --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 --timing_analysis_only

8590
FPGA_by_Fredi/firebee1.map.rpt
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File diff suppressed because it is too large Load Diff

12
FPGA_by_Fredi/firebee1.map.summary
View File

@@ -1,14 +1,14 @@
Analysis & Synthesis Status : Successful - Wed Dec 15 02:21:55 2010
Analysis & Synthesis Status : Successful - Fri Aug 28 13:35:56 2015
Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
Revision Name : firebee1
Top-level Entity Name : firebee1
Family : Cyclone III
Total logic elements : 10,706
Total combinational functions : 8,060
Dedicated logic registers : 4,612
Total registers : 4740
Total logic elements : 11,642
Total combinational functions : 8,656
Dedicated logic registers : 5,028
Total registers : 5156
Total pins : 295
Total virtual pins : 0
Total memory bits : 109,344
Total memory bits : 109,600
Embedded Multiplier 9-bit elements : 6
Total PLLs : 4

96
FPGA_by_Fredi/firebee1.pin
View File

@@ -33,7 +33,7 @@
-- Bank 5: 2.5V
-- Bank 6: 3.0V
-- Bank 7: 3.3V
-- Bank 8: 3.3V
-- Bank 8: 3.0V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
@@ -72,15 +72,15 @@ CHIP "firebee1" ASSIGNED TO AN: EP3C40F484C6
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
GND : A1 : gnd : : : :
VCCIO8 : A2 : power : : 3.3V : 8 :
LP_D[6] : A3 : bidir : 3.3-V LVTTL : : 8 : Y
nSRBLE : A4 : output : 3.3-V LVTTL : : 8 : Y
SRD[1] : A5 : bidir : 3.3-V LVTTL : : 8 : Y
IO[3] : A6 : bidir : 3.3-V LVTTL : : 8 : Y
IO[1] : A7 : bidir : 3.3-V LVTTL : : 8 : Y
IO[0] : A8 : bidir : 3.3-V LVTTL : : 8 : Y
SRD[10] : A9 : bidir : 3.3-V LVTTL : : 8 : Y
SRD[9] : A10 : bidir : 3.3-V LVTTL : : 8 : Y
VCCIO8 : A2 : power : : 3.0V : 8 :
LP_D[6] : A3 : bidir : 3.0-V LVCMOS : : 8 : Y
nSRBLE : A4 : output : 3.0-V LVCMOS : : 8 : Y
SRD[1] : A5 : bidir : 3.0-V LVCMOS : : 8 : Y
IO[3] : A6 : bidir : 3.0-V LVCMOS : : 8 : Y
IO[1] : A7 : bidir : 3.0-V LVCMOS : : 8 : Y
IO[0] : A8 : bidir : 3.0-V LVCMOS : : 8 : Y
SRD[10] : A9 : bidir : 3.0-V LVCMOS : : 8 : Y
SRD[9] : A10 : bidir : 3.0-V LVCMOS : : 8 : Y
DVI_INT : A11 : input : 3.3-V LVTTL : : 8 : Y
nDACK1 : A12 : input : 3.3-V LVTTL : : 7 : Y
IO[16] : A13 : bidir : 3.3-V LVTTL : : 7 : Y
@@ -126,7 +126,7 @@ FB_AD[23] : AB8 : bidir : 3.3-V LVTTL :
FB_AD[26] : AB9 : bidir : 3.3-V LVTTL : : 3 : Y
CLK24M576 : AB10 : output : 3.3-V LVTTL : : 3 : Y
GND+ : AB11 : : : : 3 :
CLK33M : AB12 : input : 3.3-V LVTTL : : 4 : Y
CLK33MDIR : AB12 : input : 3.3-V LVTTL : : 4 : Y
VD[29] : AB13 : bidir : 2.5 V : : 4 : Y
VD[26] : AB14 : bidir : 2.5 V : : 4 : Y
VD[24] : AB15 : bidir : 2.5 V : : 4 : Y
@@ -139,14 +139,14 @@ VCCIO4 : AB21 : power : : 2.5V
GND : AB22 : gnd : : : :
ACSI_D[0] : B1 : bidir : 3.3-V LVTTL : : 1 : Y
MIDI_TLR : B2 : output : 3.3-V LVTTL : : 1 : Y
LP_D[5] : B3 : bidir : 3.3-V LVTTL : : 8 : Y
nSRBHE : B4 : output : 3.3-V LVTTL : : 8 : Y
SRD[0] : B5 : bidir : 3.3-V LVTTL : : 8 : Y
IO[4] : B6 : bidir : 3.3-V LVTTL : : 8 : Y
IO[2] : B7 : bidir : 3.3-V LVTTL : : 8 : Y
nSRCS : B8 : output : 3.3-V LVTTL : : 8 : Y
SRD[8] : B9 : bidir : 3.3-V LVTTL : : 8 : Y
SRD[11] : B10 : bidir : 3.3-V LVTTL : : 8 : Y
LP_D[5] : B3 : bidir : 3.0-V LVCMOS : : 8 : Y
nSRBHE : B4 : output : 3.0-V LVCMOS : : 8 : Y
SRD[0] : B5 : bidir : 3.0-V LVCMOS : : 8 : Y
IO[4] : B6 : bidir : 3.0-V LVCMOS : : 8 : Y
IO[2] : B7 : bidir : 3.0-V LVCMOS : : 8 : Y
nSRCS : B8 : output : 3.0-V LVCMOS : : 8 : Y
SRD[8] : B9 : bidir : 3.0-V LVCMOS : : 8 : Y
SRD[11] : B10 : bidir : 3.0-V LVCMOS : : 8 : Y
nRSTO_MCF : B11 : input : 3.3-V LVTTL : : 8 : Y
nDACK0 : B12 : input : 3.3-V LVTTL : : 7 : Y
IO[17] : B13 : bidir : 3.3-V LVTTL : : 7 : Y
@@ -161,14 +161,14 @@ VB[5] : B21 : output : 3.0-V LVTTL :
VB[4] : B22 : output : 3.0-V LVTTL : : 6 : Y
ACSI_D[4] : C1 : bidir : 3.3-V LVTTL : : 1 : Y
ACSI_D[3] : C2 : bidir : 3.3-V LVTTL : : 1 : Y
LP_D[2] : C3 : bidir : 3.3-V LVTTL : : 8 : Y
LP_D[1] : C4 : bidir : 3.3-V LVTTL : : 8 : Y
LP_D[2] : C3 : bidir : 3.0-V LVCMOS : : 8 : Y
LP_D[1] : C4 : bidir : 3.0-V LVCMOS : : 8 : Y
GND : C5 : gnd : : : :
SRD[2] : C6 : bidir : 3.3-V LVTTL : : 8 : Y
IO[7] : C7 : bidir : 3.3-V LVTTL : : 8 : Y
IO[6] : C8 : bidir : 3.3-V LVTTL : : 8 : Y
SRD[2] : C6 : bidir : 3.0-V LVCMOS : : 8 : Y
IO[7] : C7 : bidir : 3.0-V LVCMOS : : 8 : Y
IO[6] : C8 : bidir : 3.0-V LVCMOS : : 8 : Y
GND : C9 : gnd : : : :
SRD[4] : C10 : bidir : 3.3-V LVTTL : : 8 : Y
SRD[4] : C10 : bidir : 3.0-V LVCMOS : : 8 : Y
GND : C11 : gnd : : : :
GND : C12 : gnd : : : :
IO[11] : C13 : bidir : 3.3-V LVTTL : : 7 : Y
@@ -185,13 +185,13 @@ VB[2] : C22 : output : 3.0-V LVTTL :
ACSI_D[5] : D2 : bidir : 3.3-V LVTTL : : 1 : Y
GND : D3 : gnd : : : :
VCCIO1 : D4 : power : : 3.3V : 1 :
VCCIO8 : D5 : power : : 3.3V : 8 :
LP_D[4] : D6 : bidir : 3.3-V LVTTL : : 8 : Y
VCCIO8 : D5 : power : : 3.0V : 8 :
LP_D[4] : D6 : bidir : 3.0-V LVCMOS : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 :
GND : D8 : gnd : : : :
VCCIO8 : D9 : power : : 3.3V : 8 :
SRD[12] : D10 : bidir : 3.3-V LVTTL : : 8 : Y
VCCIO8 : D11 : power : : 3.3V : 8 :
VCCIO8 : D9 : power : : 3.0V : 8 :
SRD[12] : D10 : bidir : 3.0-V LVCMOS : : 8 : Y
VCCIO8 : D11 : power : : 3.0V : 8 :
VCCIO7 : D12 : power : : 3.3V : 7 :
IO[12] : D13 : bidir : 3.3-V LVTTL : : 7 : Y
VCCIO7 : D14 : power : : 3.3V : 7 :
@@ -207,14 +207,14 @@ SCSI_D[1] : E1 : bidir : 3.3-V LVTTL :
~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT : E2 : input : 3.3-V LVTTL : : 1 : N
ACSI_D[2] : E3 : bidir : 3.3-V LVTTL : : 1 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 1 :
LPDIR : E5 : output : 3.3-V LVTTL : : 8 : Y
LP_STR : E6 : output : 3.3-V LVTTL : : 8 : Y
LP_D[3] : E7 : bidir : 3.3-V LVTTL : : 8 : Y
VCCIO8 : E8 : power : : 3.3V : 8 :
IO[5] : E9 : bidir : 3.3-V LVTTL : : 8 : Y
SRD[6] : E10 : bidir : 3.3-V LVTTL : : 8 : Y
LPDIR : E5 : output : 3.0-V LVCMOS : : 8 : Y
LP_STR : E6 : output : 3.0-V LVCMOS : : 8 : Y
LP_D[3] : E7 : bidir : 3.0-V LVCMOS : : 8 : Y
VCCIO8 : E8 : power : : 3.0V : 8 :
IO[5] : E9 : bidir : 3.0-V LVCMOS : : 8 : Y
SRD[6] : E10 : bidir : 3.0-V LVCMOS : : 8 : Y
nDREQ1 : E11 : output : 3.3-V LVTTL : : 7 : Y
MIDI_IN : E12 : input : 3.3-V LVTTL : : 7 : Y
MIDI_IN_PIN : E12 : bidir : 3.3-V LVTTL : : 7 : Y
IO[13] : E13 : bidir : 3.3-V LVTTL : : 7 : Y
SD_CMD_D1 : E14 : bidir : 3.3-V LVTTL : : 7 : Y
YM_QC : E15 : output : 3.3-V LVTTL : : 7 : Y
@@ -231,10 +231,10 @@ GND : F3 : gnd : :
VCCIO1 : F4 : power : : 3.3V : 1 :
GNDA3 : F5 : gnd : : : :
VCCD_PLL3 : F6 : power : : 1.2V : :
LP_D[0] : F7 : bidir : 3.3-V LVTTL : : 8 : Y
nSRWE : F8 : output : 3.3-V LVTTL : : 8 : Y
SRD[5] : F9 : bidir : 3.3-V LVTTL : : 8 : Y
SRD[13] : F10 : bidir : 3.3-V LVTTL : : 8 : Y
LP_D[0] : F7 : bidir : 3.0-V LVCMOS : : 8 : Y
nSRWE : F8 : output : 3.0-V LVCMOS : : 8 : Y
SRD[5] : F9 : bidir : 3.0-V LVCMOS : : 8 : Y
SRD[13] : F10 : bidir : 3.0-V LVCMOS : : 8 : Y
nSROE : F11 : output : 3.3-V LVTTL : : 7 : Y
GND : F12 : gnd : : : :
SD_CD_DATA3 : F13 : bidir : 3.3-V LVTTL : : 7 : Y
@@ -254,10 +254,10 @@ SCSI_D[4] : G4 : bidir : 3.3-V LVTTL :
ACSI_D[1] : G5 : bidir : 3.3-V LVTTL : : 1 : Y
VCCA3 : G6 : power : : 2.5V : :
LP_BUSY : G7 : input : 3.3-V LVTTL : : 8 : Y
LP_D[7] : G8 : bidir : 3.3-V LVTTL : : 8 : Y
SRD[14] : G9 : bidir : 3.3-V LVTTL : : 8 : Y
IO[8] : G10 : bidir : 3.3-V LVTTL : : 8 : Y
SRD[3] : G11 : bidir : 3.3-V LVTTL : : 8 : Y
LP_D[7] : G8 : bidir : 3.0-V LVCMOS : : 8 : Y
SRD[14] : G9 : bidir : 3.0-V LVCMOS : : 8 : Y
IO[8] : G10 : bidir : 3.0-V LVCMOS : : 8 : Y
SRD[3] : G11 : bidir : 3.0-V LVCMOS : : 8 : Y
VCCINT : G12 : power : : 1.2V : :
YM_QB : G13 : output : 3.3-V LVTTL : : 7 : Y
nWR : G14 : output : 3.3-V LVTTL : : 7 : Y
@@ -278,8 +278,8 @@ ACSI_D[7] : H6 : bidir : 3.3-V LVTTL :
ACSI_D[6] : H7 : bidir : 3.3-V LVTTL : : 1 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 1 :
VCCINT : H9 : power : : 1.2V : :
SRD[15] : H10 : bidir : 3.3-V LVTTL : : 8 : Y
SRD[7] : H11 : bidir : 3.3-V LVTTL : : 8 : Y
SRD[15] : H10 : bidir : 3.0-V LVCMOS : : 8 : Y
SRD[7] : H11 : bidir : 3.0-V LVCMOS : : 8 : Y
GND : H12 : gnd : : : :
GND : H13 : gnd : : : :
CTS : H14 : input : 3.3-V LVTTL : : 7 : Y
@@ -534,7 +534,7 @@ VA[0] : W20 : output : 2.5 V :
VA[2] : W21 : output : 2.5 V : : 5 : Y
VA[1] : W22 : output : 2.5 V : : 5 : Y
IDE_RDY : Y1 : input : 3.3-V LVTTL : : 2 : Y
AMKB_RX : Y2 : input : 3.3-V LVTTL : : 2 : Y
AMKB_RX : Y2 : input : 3.3-V LVCMOS : : 2 : Y
FB_AD[0] : Y3 : bidir : 3.3-V LVTTL : : 3 : Y
FB_SIZE1 : Y4 : input : 3.3-V LVTTL : : 3 : Y
GND : Y5 : gnd : : : :

448
FPGA_by_Fredi/firebee1.qsf
View File

@@ -43,175 +43,9 @@ set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2"
set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf"
set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd
set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd
set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd
set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd
set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd
set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp
set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp
set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf
set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp
set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp
set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp
set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp
set_global_assignment -name VHDL_FILE lpm_latch0.vhd
set_global_assignment -name SOURCE_FILE lpm_latch0.cmp
set_global_assignment -name QIP_FILE altpll1.qip
set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp
set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp
set_global_assignment -name QIP_FILE altpll2.qip
set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp
set_global_assignment -name QIP_FILE altpll3.qip
set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp
set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp
set_global_assignment -name VHDL_FILE Video/altdpram0.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp
set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp
set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp
set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd
set_global_assignment -name SOURCE_FILE altpll0.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp
set_global_assignment -name SOURCE_FILE altpll2.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp
set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp
set_global_assignment -name VHDL_FILE altpll2.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp
set_global_assignment -name SOURCE_FILE altpll3.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp
set_global_assignment -name VHDL_FILE altpll3.vhd
set_global_assignment -name SOURCE_FILE lpm_counter0.cmp
set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp
set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp
set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd
set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf
set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp
set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd
set_global_assignment -name BDF_FILE Video/Video.bdf
set_global_assignment -name VHDL_FILE altpll1.vhd
set_global_assignment -name SOURCE_FILE altpll1.cmp
set_global_assignment -name BDF_FILE firebee1.bdf
set_global_assignment -name QIP_FILE altpll0.qip
set_global_assignment -name QIP_FILE lpm_counter0.qip
set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\FalconIO_SDCard_IDE_CF\\FalconIO_SDCard_IDE_CF.vhd"
set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\DSP\\DSP.vhd"
set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip
set_global_assignment -name QIP_FILE Video/altdpram0.qip
set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip
set_global_assignment -name QIP_FILE Video/altdpram1.qip
set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip
set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip
set_global_assignment -name QIP_FILE Video/lpm_constant0.qip
set_global_assignment -name QIP_FILE Video/lpm_constant1.qip
set_global_assignment -name QIP_FILE Video/lpm_mux0.qip
set_global_assignment -name QIP_FILE Video/lpm_mux1.qip
set_global_assignment -name QIP_FILE Video/lpm_mux2.qip
set_global_assignment -name QIP_FILE Video/lpm_constant2.qip
set_global_assignment -name QIP_FILE Video/altdpram2.qip
set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip
set_global_assignment -name QIP_FILE Video/lpm_mux3.qip
set_global_assignment -name QIP_FILE Video/lpm_mux4.qip
set_global_assignment -name QIP_FILE Video/lpm_constant3.qip
set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip
set_global_assignment -name QIP_FILE Video/lpm_latch1.qip
set_global_assignment -name QIP_FILE Video/lpm_constant4.qip
set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip
set_global_assignment -name QIP_FILE Video/lpm_compare1.qip
set_global_assignment -name AHDL_FILE "C:\\firebee\\FPGA\\Interrupt_Handler\\interrupt_handler.tdf"
set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip
set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
set_global_assignment -name QIP_FILE Video/lpm_ff4.qip
set_global_assignment -name QIP_FILE Video/lpm_ff5.qip
set_global_assignment -name QIP_FILE Video/lpm_ff6.qip
set_global_assignment -name VECTOR_WAVEFORM_FILE firebee1.vwf
set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip
set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip
set_global_assignment -name QIP_FILE Video/altddio_out0.qip
set_global_assignment -name QIP_FILE Video/lpm_mux5.qip
set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\Video\\BLITTER\\BLITTER.vhd"
set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip
set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip
set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip
set_global_assignment -name QIP_FILE Video/altddio_out1.qip
set_global_assignment -name QIP_FILE Video/altddio_out2.qip
set_global_assignment -name QIP_FILE altddio_out3.qip
set_global_assignment -name QIP_FILE Video/lpm_mux6.qip
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd
set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip
set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip
set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip
set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip
set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_AB12 -to CLK33M
set_location_assignment PIN_G2 -to MAIN_CLK
set_location_assignment PIN_Y3 -to FB_AD[0]
set_location_assignment PIN_Y6 -to FB_AD[1]
@@ -485,7 +319,6 @@ set_location_assignment PIN_A20 -to nRD_DATA
set_location_assignment PIN_C17 -to nDCHG
set_location_assignment PIN_J4 -to nACSI_INT
set_location_assignment PIN_K7 -to nACSI_DRQ
set_location_assignment PIN_E12 -to MIDI_IN
set_location_assignment PIN_G7 -to LP_BUSY
set_location_assignment PIN_Y1 -to IDE_RDY
set_location_assignment PIN_G22 -to IDE_INT
@@ -662,7 +495,7 @@ set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to FB_AD
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA
@@ -680,15 +513,14 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG
set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR
set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD
set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nPD_VGA
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SRD
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to IO
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRWE
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSROE
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRCS
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBLE
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBHE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M
@@ -733,8 +565,268 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end ENTITY(firebee1)
# --------------------
set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf"
set_global_assignment -name QIP_FILE altpll_reconfig1.qip
set_global_assignment -name QIP_FILE altpll4.qip
set_location_assignment PIN_E5 -to LPDIR
set_location_assignment PIN_B11 -to nRSTO_MCF
set_global_assignment -name SOURCE_FILE Video/BLITTER/lpm_clshift0.cmp
set_global_assignment -name AHDL_FILE Video/BLITTER/lpm_clshift0.tdf
set_global_assignment -name SOURCE_FILE Video/BLITTER/altsyncram0.cmp
set_global_assignment -name AHDL_FILE Video/BLITTER/altsyncram0.tdf
set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd
set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd
set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd
set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd
set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd
set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp
set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp
set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf
set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp
set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp
set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp
set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp
set_global_assignment -name VHDL_FILE lpm_latch0.vhd
set_global_assignment -name SOURCE_FILE lpm_latch0.cmp
set_global_assignment -name QIP_FILE altpll1.qip
set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp
set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp
set_global_assignment -name QIP_FILE altpll2.qip
set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp
set_global_assignment -name QIP_FILE altpll3.qip
set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp
set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp
set_global_assignment -name VHDL_FILE Video/altdpram0.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp
set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp
set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp
set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd
set_global_assignment -name SOURCE_FILE altpll0.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp
set_global_assignment -name SOURCE_FILE altpll2.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp
set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp
set_global_assignment -name VHDL_FILE altpll2.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp
set_global_assignment -name SOURCE_FILE altpll3.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp
set_global_assignment -name VHDL_FILE altpll3.vhd
set_global_assignment -name SOURCE_FILE lpm_counter0.cmp
set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp
set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp
set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd
set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf
set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp
set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd
set_global_assignment -name BDF_FILE Video/Video.bdf
set_global_assignment -name VHDL_FILE altpll1.vhd
set_global_assignment -name SOURCE_FILE altpll1.cmp
set_global_assignment -name BDF_FILE firebee1.bdf
set_global_assignment -name QIP_FILE altpll0.qip
set_global_assignment -name QIP_FILE lpm_counter0.qip
set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\FalconIO_SDCard_IDE_CF\\FalconIO_SDCard_IDE_CF.vhd"
set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\DSP\\DSP.vhd"
set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip
set_global_assignment -name QIP_FILE Video/altdpram0.qip
set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip
set_global_assignment -name QIP_FILE Video/altdpram1.qip
set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip
set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip
set_global_assignment -name QIP_FILE Video/lpm_constant0.qip
set_global_assignment -name QIP_FILE Video/lpm_constant1.qip
set_global_assignment -name QIP_FILE Video/lpm_mux0.qip
set_global_assignment -name QIP_FILE Video/lpm_mux1.qip
set_global_assignment -name QIP_FILE Video/lpm_mux2.qip
set_global_assignment -name QIP_FILE Video/lpm_constant2.qip
set_global_assignment -name QIP_FILE Video/altdpram2.qip
set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip
set_global_assignment -name QIP_FILE Video/lpm_mux3.qip
set_global_assignment -name QIP_FILE Video/lpm_mux4.qip
set_global_assignment -name QIP_FILE Video/lpm_constant3.qip
set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip
set_global_assignment -name QIP_FILE Video/lpm_latch1.qip
set_global_assignment -name QIP_FILE Video/lpm_constant4.qip
set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip
set_global_assignment -name QIP_FILE Video/lpm_compare1.qip
set_global_assignment -name AHDL_FILE "C:\\firebee\\FPGA\\Interrupt_Handler\\interrupt_handler.tdf"
set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip
set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
set_global_assignment -name QIP_FILE Video/lpm_ff4.qip
set_global_assignment -name QIP_FILE Video/lpm_ff5.qip
set_global_assignment -name QIP_FILE Video/lpm_ff6.qip
set_global_assignment -name VECTOR_WAVEFORM_FILE firebee1.vwf
set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip
set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip
set_global_assignment -name QIP_FILE Video/altddio_out0.qip
set_global_assignment -name QIP_FILE Video/lpm_mux5.qip
set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip
set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip
set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip
set_global_assignment -name QIP_FILE Video/altddio_out1.qip
set_global_assignment -name QIP_FILE Video/altddio_out2.qip
set_global_assignment -name QIP_FILE altddio_out3.qip
set_global_assignment -name QIP_FILE Video/lpm_mux6.qip
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd
set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip
set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip
set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip
set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip
set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt
set_global_assignment -name QIP_FILE altpll_reconfig1.qip
set_global_assignment -name QIP_FILE altpll4.qip
set_global_assignment -name QIP_FILE lpm_mux0.qip
set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip
set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT
set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD
set_location_assignment PIN_AB12 -to CLK33MDIR
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name QIP_FILE lpm_shiftreg0.qip
set_global_assignment -name QIP_FILE lpm_counter1.qip
set_global_assignment -name QIP_FILE altiobuf_bidir0.qip
set_location_assignment PIN_E12 -to MIDI_IN_PIN
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN
set_instance_assignment -name PCI_IO ON -to nPCI_INTA
set_instance_assignment -name PCI_IO ON -to nPCI_INTB
set_instance_assignment -name PCI_IO ON -to nPCI_INTC
set_instance_assignment -name PCI_IO ON -to nPCI_INTD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2]
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4]
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4]
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5]
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3]
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2]
set_global_assignment -name POWER_USE_TA_VALUE 35
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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FPGA_by_Fredi/firebee1.rbf
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FPGA_by_Fredi/firebee1.sof
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857
FPGA_by_Fredi/firebee1.sta.summary Normal file
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@@ -0,0 +1,857 @@
------------------------------------------------------------
TimeQuest Timing Analyzer Summary
------------------------------------------------------------
Type : Slow 1200mV 85C Model Setup 'inst22|altpll_component|auto_generated|pll1|clk[0]'
Slack : -17.450
TNS : -16147.437
Type : Slow 1200mV 85C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[2]'
Slack : -7.331
TNS : -4287.365
Type : Slow 1200mV 85C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[0]'
Slack : -4.994
TNS : -47.649
Type : Slow 1200mV 85C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[1]'
Slack : -4.588
TNS : -478.150
Type : Slow 1200mV 85C Model Setup 'MAIN_CLK'
Slack : -4.230
TNS : -5479.268
Type : Slow 1200mV 85C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[3]'
Slack : 2.377
TNS : 0.000
Type : Slow 1200mV 85C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[1]'
Slack : 2.892
TNS : 0.000
Type : Slow 1200mV 85C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[4]'
Slack : 3.750
TNS : 0.000
Type : Slow 1200mV 85C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[2]'
Slack : 5.312
TNS : 0.000
Type : Slow 1200mV 85C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[0]'
Slack : 497.531
TNS : 0.000
Type : Slow 1200mV 85C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[3]'
Slack : 1997.881
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[2]'
Slack : -11.047
TNS : -9871.573
Type : Slow 1200mV 85C Model Hold 'MAIN_CLK'
Slack : -10.882
TNS : -9731.628
Type : Slow 1200mV 85C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[0]'
Slack : -5.940
TNS : -5.940
Type : Slow 1200mV 85C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.283
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'inst22|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.342
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.376
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[3]'
Slack : 0.389
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[2]'
Slack : 1.541
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[3]'
Slack : 2.366
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[4]'
Slack : 3.005
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[1]'
Slack : 4.128
TNS : 0.000
Type : Slow 1200mV 85C Model Recovery 'inst22|altpll_component|auto_generated|pll1|clk[0]'
Slack : -15.674
TNS : -2798.000
Type : Slow 1200mV 85C Model Recovery 'inst12|altpll_component|auto_generated|pll1|clk[0]'
Slack : -8.406
TNS : -16.812
Type : Slow 1200mV 85C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[2]'
Slack : -4.536
TNS : -782.022
Type : Slow 1200mV 85C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[1]'
Slack : -4.460
TNS : -652.825
Type : Slow 1200mV 85C Model Recovery 'MAIN_CLK'
Slack : -3.788
TNS : -646.634
Type : Slow 1200mV 85C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
Slack : -2.802
TNS : -2.802
Type : Slow 1200mV 85C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
Slack : -1.533
TNS : -1.533
Type : Slow 1200mV 85C Model Recovery 'DVI_INT'
Slack : -0.826
TNS : -0.826
Type : Slow 1200mV 85C Model Recovery 'E0_INT'
Slack : -0.766
TNS : -0.766
Type : Slow 1200mV 85C Model Recovery 'nPCI_INTA'
Slack : -0.281
TNS : -0.281
Type : Slow 1200mV 85C Model Recovery 'nPCI_INTD'
Slack : -0.267
TNS : -0.267
Type : Slow 1200mV 85C Model Recovery 'nPCI_INTC'
Slack : -0.249
TNS : -0.249
Type : Slow 1200mV 85C Model Recovery 'nPCI_INTB'
Slack : -0.188
TNS : -0.188
Type : Slow 1200mV 85C Model Recovery 'PIC_INT'
Slack : -0.038
TNS : -0.038
Type : Slow 1200mV 85C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[2]'
Slack : -10.353
TNS : -1430.734
Type : Slow 1200mV 85C Model Removal 'MAIN_CLK'
Slack : -10.188
TNS : -1400.869
Type : Slow 1200mV 85C Model Removal 'inst12|altpll_component|auto_generated|pll1|clk[0]'
Slack : -2.755
TNS : -5.510
Type : Slow 1200mV 85C Model Removal 'PIC_INT'
Slack : -0.526
TNS : -0.526
Type : Slow 1200mV 85C Model Removal 'nPCI_INTB'
Slack : -0.361
TNS : -0.361
Type : Slow 1200mV 85C Model Removal 'nPCI_INTC'
Slack : -0.295
TNS : -0.295
Type : Slow 1200mV 85C Model Removal 'nPCI_INTD'
Slack : -0.274
TNS : -0.274
Type : Slow 1200mV 85C Model Removal 'nPCI_INTA'
Slack : -0.256
TNS : -0.256
Type : Slow 1200mV 85C Model Removal 'E0_INT'
Slack : 0.237
TNS : 0.000
Type : Slow 1200mV 85C Model Removal 'DVI_INT'
Slack : 0.299
TNS : 0.000
Type : Slow 1200mV 85C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
Slack : 1.026
TNS : 0.000
Type : Slow 1200mV 85C Model Removal 'inst22|altpll_component|auto_generated|pll1|clk[0]'
Slack : 1.036
TNS : 0.000
Type : Slow 1200mV 85C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
Slack : 2.350
TNS : 0.000
Type : Slow 1200mV 85C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[1]'
Slack : 3.015
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'PIC_INT'
Slack : -3.000
TNS : -4.134
Type : Slow 1200mV 85C Model Minimum Pulse Width 'nPCI_INTB'
Slack : -3.000
TNS : -4.079
Type : Slow 1200mV 85C Model Minimum Pulse Width 'nPCI_INTD'
Slack : -3.000
TNS : -4.070
Type : Slow 1200mV 85C Model Minimum Pulse Width 'nPCI_INTC'
Slack : -3.000
TNS : -4.050
Type : Slow 1200mV 85C Model Minimum Pulse Width 'nPCI_INTA'
Slack : -3.000
TNS : -4.038
Type : Slow 1200mV 85C Model Minimum Pulse Width 'DVI_INT'
Slack : -3.000
TNS : -4.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'E0_INT'
Slack : -3.000
TNS : -4.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
Slack : -1.000
TNS : -1.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
Slack : -1.000
TNS : -1.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[0]'
Slack : 3.527
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[1]'
Slack : 3.533
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[2]'
Slack : 3.533
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[3]'
Slack : 3.533
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst22|altpll_component|auto_generated|pll1|clk[0]'
Slack : 4.811
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[4]'
Slack : 7.320
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst|altpll_component|auto_generated|pll1|clk[3]'
Slack : 10.398
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'MAIN_CLK'
Slack : 13.528
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[2]'
Slack : 18.585
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[1]'
Slack : 30.973
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[0]'
Slack : 249.617
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[3]'
Slack : 999.882
TNS : 0.000
Type : Slow 1200mV 0C Model Setup 'inst22|altpll_component|auto_generated|pll1|clk[0]'
Slack : -15.403
TNS : -14377.209
Type : Slow 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[2]'
Slack : -6.421
TNS : -3676.693
Type : Slow 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[0]'
Slack : -4.520
TNS : -37.132
Type : Slow 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[1]'
Slack : -4.094
TNS : -426.105
Type : Slow 1200mV 0C Model Setup 'MAIN_CLK'
Slack : -3.696
TNS : -4132.088
Type : Slow 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[3]'
Slack : 2.718
TNS : 0.000
Type : Slow 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[1]'
Slack : 2.995
TNS : 0.000
Type : Slow 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[4]'
Slack : 3.994
TNS : 0.000
Type : Slow 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[2]'
Slack : 5.426
TNS : 0.000
Type : Slow 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[0]'
Slack : 497.772
TNS : 0.000
Type : Slow 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[3]'
Slack : 1998.168
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[2]'
Slack : -9.832
TNS : -8727.393
Type : Slow 1200mV 0C Model Hold 'MAIN_CLK'
Slack : -9.617
TNS : -8529.400
Type : Slow 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[0]'
Slack : -5.065
TNS : -5.065
Type : Slow 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.254
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'inst22|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.297
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.335
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[3]'
Slack : 0.346
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[2]'
Slack : 1.517
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[3]'
Slack : 2.163
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[4]'
Slack : 2.766
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[1]'
Slack : 4.082
TNS : 0.000
Type : Slow 1200mV 0C Model Recovery 'inst22|altpll_component|auto_generated|pll1|clk[0]'
Slack : -13.902
TNS : -2482.848
Type : Slow 1200mV 0C Model Recovery 'inst12|altpll_component|auto_generated|pll1|clk[0]'
Slack : -7.532
TNS : -15.064
Type : Slow 1200mV 0C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[1]'
Slack : -3.927
TNS : -573.408
Type : Slow 1200mV 0C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[2]'
Slack : -3.851
TNS : -663.617
Type : Slow 1200mV 0C Model Recovery 'MAIN_CLK'
Slack : -3.223
TNS : -549.949
Type : Slow 1200mV 0C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
Slack : -2.555
TNS : -2.555
Type : Slow 1200mV 0C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
Slack : -1.377
TNS : -1.377
Type : Slow 1200mV 0C Model Recovery 'DVI_INT'
Slack : -0.706
TNS : -0.706
Type : Slow 1200mV 0C Model Recovery 'E0_INT'
Slack : -0.653
TNS : -0.653
Type : Slow 1200mV 0C Model Recovery 'nPCI_INTA'
Slack : -0.192
TNS : -0.192
Type : Slow 1200mV 0C Model Recovery 'nPCI_INTD'
Slack : -0.190
TNS : -0.190
Type : Slow 1200mV 0C Model Recovery 'nPCI_INTC'
Slack : -0.180
TNS : -0.180
Type : Slow 1200mV 0C Model Recovery 'nPCI_INTB'
Slack : -0.104
TNS : -0.104
Type : Slow 1200mV 0C Model Recovery 'PIC_INT'
Slack : 0.013
TNS : 0.000
Type : Slow 1200mV 0C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[2]'
Slack : -9.193
TNS : -1262.369
Type : Slow 1200mV 0C Model Removal 'MAIN_CLK'
Slack : -8.978
TNS : -1223.454
Type : Slow 1200mV 0C Model Removal 'inst12|altpll_component|auto_generated|pll1|clk[0]'
Slack : -2.195
TNS : -4.390
Type : Slow 1200mV 0C Model Removal 'PIC_INT'
Slack : -0.527
TNS : -0.527
Type : Slow 1200mV 0C Model Removal 'nPCI_INTB'
Slack : -0.384
TNS : -0.384
Type : Slow 1200mV 0C Model Removal 'nPCI_INTC'
Slack : -0.316
TNS : -0.316
Type : Slow 1200mV 0C Model Removal 'nPCI_INTD'
Slack : -0.288
TNS : -0.288
Type : Slow 1200mV 0C Model Removal 'nPCI_INTA'
Slack : -0.283
TNS : -0.283
Type : Slow 1200mV 0C Model Removal 'E0_INT'
Slack : 0.170
TNS : 0.000
Type : Slow 1200mV 0C Model Removal 'DVI_INT'
Slack : 0.223
TNS : 0.000
Type : Slow 1200mV 0C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
Slack : 0.914
TNS : 0.000
Type : Slow 1200mV 0C Model Removal 'inst22|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.936
TNS : 0.000
Type : Slow 1200mV 0C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
Slack : 2.150
TNS : 0.000
Type : Slow 1200mV 0C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[1]'
Slack : 2.663
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'PIC_INT'
Slack : -3.000
TNS : -4.036
Type : Slow 1200mV 0C Model Minimum Pulse Width 'nPCI_INTB'
Slack : -3.000
TNS : -4.036
Type : Slow 1200mV 0C Model Minimum Pulse Width 'nPCI_INTD'
Slack : -3.000
TNS : -4.012
Type : Slow 1200mV 0C Model Minimum Pulse Width 'nPCI_INTA'
Slack : -3.000
TNS : -4.002
Type : Slow 1200mV 0C Model Minimum Pulse Width 'DVI_INT'
Slack : -3.000
TNS : -4.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'E0_INT'
Slack : -3.000
TNS : -4.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'nPCI_INTC'
Slack : -3.000
TNS : -4.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
Slack : -1.000
TNS : -1.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
Slack : -1.000
TNS : -1.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[0]'
Slack : 3.517
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[2]'
Slack : 3.528
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[1]'
Slack : 3.529
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[3]'
Slack : 3.529
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst22|altpll_component|auto_generated|pll1|clk[0]'
Slack : 4.909
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[4]'
Slack : 7.316
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst|altpll_component|auto_generated|pll1|clk[3]'
Slack : 10.392
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'MAIN_CLK'
Slack : 13.634
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[2]'
Slack : 18.774
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[1]'
Slack : 30.967
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[0]'
Slack : 249.612
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[3]'
Slack : 999.877
TNS : 0.000
Type : Fast 1200mV 0C Model Setup 'inst22|altpll_component|auto_generated|pll1|clk[0]'
Slack : -9.748
TNS : -9757.013
Type : Fast 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[2]'
Slack : -3.484
TNS : -1911.267
Type : Fast 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[0]'
Slack : -2.773
TNS : -9.357
Type : Fast 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[1]'
Slack : -2.483
TNS : -260.497
Type : Fast 1200mV 0C Model Setup 'MAIN_CLK'
Slack : -1.767
TNS : -1399.694
Type : Fast 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[1]'
Slack : 3.283
TNS : 0.000
Type : Fast 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[3]'
Slack : 3.689
TNS : 0.000
Type : Fast 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[4]'
Slack : 4.868
TNS : 0.000
Type : Fast 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[2]'
Slack : 5.744
TNS : 0.000
Type : Fast 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[0]'
Slack : 498.517
TNS : 0.000
Type : Fast 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[3]'
Slack : 1998.908
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[2]'
Slack : -6.775
TNS : -6188.069
Type : Fast 1200mV 0C Model Hold 'MAIN_CLK'
Slack : -6.521
TNS : -5940.597
Type : Fast 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[0]'
Slack : -3.440
TNS : -3.440
Type : Fast 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.136
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'inst22|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.178
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.197
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[3]'
Slack : 0.204
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[3]'
Slack : 1.296
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[2]'
Slack : 1.392
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[4]'
Slack : 1.655
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[1]'
Slack : 3.971
TNS : 0.000
Type : Fast 1200mV 0C Model Recovery 'inst22|altpll_component|auto_generated|pll1|clk[0]'
Slack : -9.449
TNS : -1688.035
Type : Fast 1200mV 0C Model Recovery 'inst12|altpll_component|auto_generated|pll1|clk[0]'
Slack : -4.842
TNS : -9.684
Type : Fast 1200mV 0C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[1]'
Slack : -2.521
TNS : -370.829
Type : Fast 1200mV 0C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[2]'
Slack : -2.077
TNS : -353.703
Type : Fast 1200mV 0C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
Slack : -1.593
TNS : -1.593
Type : Fast 1200mV 0C Model Recovery 'MAIN_CLK'
Slack : -1.560
TNS : -261.778
Type : Fast 1200mV 0C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
Slack : -0.866
TNS : -0.866
Type : Fast 1200mV 0C Model Recovery 'DVI_INT'
Slack : -0.475
TNS : -0.475
Type : Fast 1200mV 0C Model Recovery 'E0_INT'
Slack : -0.438
TNS : -0.438
Type : Fast 1200mV 0C Model Recovery 'PIC_INT'
Slack : -0.086
TNS : -0.086
Type : Fast 1200mV 0C Model Recovery 'nPCI_INTA'
Slack : 0.253
TNS : 0.000
Type : Fast 1200mV 0C Model Recovery 'nPCI_INTC'
Slack : 0.262
TNS : 0.000
Type : Fast 1200mV 0C Model Recovery 'nPCI_INTD'
Slack : 0.263
TNS : 0.000
Type : Fast 1200mV 0C Model Recovery 'nPCI_INTB'
Slack : 0.294
TNS : 0.000
Type : Fast 1200mV 0C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[2]'
Slack : -6.385
TNS : -890.317
Type : Fast 1200mV 0C Model Removal 'MAIN_CLK'
Slack : -6.131
TNS : -844.343
Type : Fast 1200mV 0C Model Removal 'inst12|altpll_component|auto_generated|pll1|clk[0]'
Slack : -1.544
TNS : -3.088
Type : Fast 1200mV 0C Model Removal 'nPCI_INTB'
Slack : -0.648
TNS : -0.648
Type : Fast 1200mV 0C Model Removal 'nPCI_INTD'
Slack : -0.607
TNS : -0.607
Type : Fast 1200mV 0C Model Removal 'nPCI_INTA'
Slack : -0.603
TNS : -0.603
Type : Fast 1200mV 0C Model Removal 'nPCI_INTC'
Slack : -0.601
TNS : -0.601
Type : Fast 1200mV 0C Model Removal 'PIC_INT'
Slack : -0.261
TNS : -0.261
Type : Fast 1200mV 0C Model Removal 'E0_INT'
Slack : 0.109
TNS : 0.000
Type : Fast 1200mV 0C Model Removal 'DVI_INT'
Slack : 0.148
TNS : 0.000
Type : Fast 1200mV 0C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
Slack : 0.560
TNS : 0.000
Type : Fast 1200mV 0C Model Removal 'inst22|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.568
TNS : 0.000
Type : Fast 1200mV 0C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
Slack : 1.306
TNS : 0.000
Type : Fast 1200mV 0C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[1]'
Slack : 1.739
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'PIC_INT'
Slack : -3.000
TNS : -5.254
Type : Fast 1200mV 0C Model Minimum Pulse Width 'nPCI_INTD'
Slack : -3.000
TNS : -5.059
Type : Fast 1200mV 0C Model Minimum Pulse Width 'nPCI_INTB'
Slack : -3.000
TNS : -5.025
Type : Fast 1200mV 0C Model Minimum Pulse Width 'nPCI_INTC'
Slack : -3.000
TNS : -5.003
Type : Fast 1200mV 0C Model Minimum Pulse Width 'nPCI_INTA'
Slack : -3.000
TNS : -4.993
Type : Fast 1200mV 0C Model Minimum Pulse Width 'E0_INT'
Slack : -3.000
TNS : -4.216
Type : Fast 1200mV 0C Model Minimum Pulse Width 'DVI_INT'
Slack : -3.000
TNS : -4.207
Type : Fast 1200mV 0C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
Slack : -1.000
TNS : -1.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
Slack : -1.000
TNS : -1.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[0]'
Slack : 3.538
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[1]'
Slack : 3.563
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[2]'
Slack : 3.567
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[3]'
Slack : 3.568
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst22|altpll_component|auto_generated|pll1|clk[0]'
Slack : 4.773
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[4]'
Slack : 7.355
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst|altpll_component|auto_generated|pll1|clk[3]'
Slack : 10.398
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'MAIN_CLK'
Slack : 13.572
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[2]'
Slack : 18.964
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[1]'
Slack : 30.983
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[0]'
Slack : 249.649
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[3]'
Slack : 999.914
TNS : 0.000
------------------------------------------------------------

6936
FPGA_by_Fredi/firebee1.tan.rpt
View File

File diff suppressed because it is too large Load Diff

278
FPGA_by_Fredi/firebee1.tan.summary
View File

@@ -3,203 +3,183 @@ Timing Analyzer Summary
--------------------------------------------------------------------------------------
Type : Worst-case tsu
Slack : -4.528 ns
Slack : -10.339 ns
Required Time : 1.000 ns
Actual Time : 5.528 ns
From : MAIN_CLK
To : altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state
Actual Time : 11.339 ns
From : FB_SIZE1
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[2]
From Clock : --
To Clock : MAIN_CLK
Failed Paths : 6867
Failed Paths : 10192
Type : Worst-case tco
Slack : -14.840 ns
Slack : -14.371 ns
Required Time : 1.000 ns
Actual Time : 15.840 ns
From : interrupt_handler:nobody|INT_LATCH[8]
To : nIRQ[5]
Actual Time : 15.371 ns
From : interrupt_handler:nobody|RTC_ADR[0]
To : FB_AD[18]
From Clock : MAIN_CLK
To Clock : --
Failed Paths : 4976
Failed Paths : 5354
Type : Worst-case tpd
Slack : -11.944 ns
Slack : -13.264 ns
Required Time : 1.000 ns
Actual Time : 12.944 ns
Actual Time : 14.264 ns
From : nFB_CS1
To : FB_AD[18]
From Clock : --
To Clock : --
Failed Paths : 514
Failed Paths : 538
Type : Worst-case th
Slack : -0.401 ns
Slack : -0.110 ns
Required Time : 1.000 ns
Actual Time : 1.401 ns
From : FB_AD[25]
To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]
Actual Time : 1.110 ns
From : VD[31]
To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31]
From Clock : --
To Clock : MAIN_CLK
Failed Paths : 117
Failed Paths : 2
Type : Clock Setup: 'CLK33M'
Slack : -5.966 ns
Required Time : 33.00 MHz ( period = 30.303 ns )
Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]'
Slack : -7.918 ns
Required Time : 25.00 MHz ( period = 39.999 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0
To : Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]
From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]
To Clock : CLK33M
Failed Paths : 3741
Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'
Slack : -4.615 ns
Required Time : 24.98 MHz ( period = 40.033 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0
To : Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]
From Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]
Failed Paths : 3741
From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]
To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF
From Clock : MAIN_CLK
To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
Failed Paths : 4748
Type : Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
Slack : -4.294 ns
Required Time : 95.92 MHz ( period = 10.425 ns )
Slack : -6.799 ns
Required Time : 96.01 MHz ( period = 10.416 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0
To : Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]
From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]
From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]
To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF
From Clock : MAIN_CLK
To Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
Failed Paths : 3741
Failed Paths : 4694
Type : Clock Setup: 'MAIN_CLK'
Slack : -4.261 ns
Slack : -5.955 ns
Required Time : 33.00 MHz ( period = 30.303 ns )
Actual Time : N/A
From : FB_ALE
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|nBLANK
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[3]
From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
To Clock : MAIN_CLK
Failed Paths : 27347
Failed Paths : 41276
Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
Slack : -2.673 ns
Slack : -5.567 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A
From : FB_ALE
To : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO
To : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLR_FIFO_SYNC
From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
Failed Paths : 86
Failed Paths : 129
Type : Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]'
Slack : -4.614 ns
Required Time : 16.00 MHz ( period = 62.499 ns )
Actual Time : N/A
From : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19]
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[4]
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
To Clock : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
Failed Paths : 2882
Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
Slack : -1.712 ns
Slack : -3.520 ns
Required Time : 66.00 MHz ( period = 15.151 ns )
Actual Time : N/A
From : FB_ALE
To : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
To : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]
From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
Failed Paths : 29
Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
Slack : 1.672 ns
Slack : 2.410 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]
To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR
To : Video:Fredi_Aschwanden|inst90~_Duplicate_2
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
Failed Paths : 0
Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
Slack : 2.965 ns
Slack : 2.966 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : Restricted to 500.00 MHz ( period = 2.000 ns )
From : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]
To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]
From : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29]
To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29]
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
Failed Paths : 0
Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
Slack : 5.299 ns
Slack : 5.144 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]
To : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]
From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4]
To : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4]
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
Failed Paths : 0
Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'
Slack : 28.590 ns
Required Time : 15.99 MHz ( period = 62.552 ns )
Actual Time : 186.15 MHz ( period = 5.372 ns )
From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK
From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]
To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]
Failed Paths : 0
Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'
Slack : 498.663 ns
Required Time : 2.00 MHz ( period = 500.416 ns )
Actual Time : Restricted to 500.00 MHz ( period = 2.000 ns )
From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]
From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]
To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]
Failed Paths : 0
Type : Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'
Slack : 1997.239 ns
Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]'
Slack : 26.171 ns
Required Time : 0.50 MHz ( period = 1999.998 ns )
Actual Time : 362.45 MHz ( period = 2.759 ns )
From : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]
To : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]
From Clock : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]
To Clock : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]
Actual Time : N/A
From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[0]
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_TX
From Clock : MAIN_CLK
To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]
Failed Paths : 0
Type : Clock Hold: 'MAIN_CLK'
Slack : -3.786 ns
Slack : -3.299 ns
Required Time : 33.00 MHz ( period = 30.303 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]
To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]
From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]
To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[2]
From Clock : MAIN_CLK
To Clock : MAIN_CLK
Failed Paths : 108
Failed Paths : 529
Type : Clock Hold: 'CLK33M'
Slack : -0.687 ns
Required Time : 33.00 MHz ( period = 30.303 ns )
Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]'
Slack : -0.640 ns
Required Time : 25.00 MHz ( period = 39.999 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
To : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
From Clock : CLK33M
To Clock : CLK33M
Failed Paths : 26
From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
Failed Paths : 33
Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'
Slack : -0.454 ns
Required Time : 24.98 MHz ( period = 40.033 ns )
Type : Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]'
Slack : 0.453 ns
Required Time : 16.00 MHz ( period = 62.499 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
To : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]
To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]
Failed Paths : 26
From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[6]
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_address_reg0
From Clock : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
To Clock : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
Failed Paths : 0
Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'
Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]'
Slack : 0.502 ns
Required Time : 15.99 MHz ( period = 62.552 ns )
Required Time : 0.50 MHz ( period = 1999.998 ns )
Actual Time : N/A
From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1
From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]
To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]
From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]
From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]
To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]
Failed Paths : 0
Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
@@ -214,7 +194,7 @@ Failed Paths : 0
Type : Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
Slack : 0.502 ns
Required Time : 95.92 MHz ( period = 10.425 ns )
Required Time : 96.01 MHz ( period = 10.416 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
To : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
@@ -222,62 +202,42 @@ From Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generat
To Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
Failed Paths : 0
Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'
Slack : 0.564 ns
Required Time : 2.00 MHz ( period = 500.416 ns )
Actual Time : N/A
From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]
From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]
To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]
Failed Paths : 0
Type : Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'
Slack : 0.825 ns
Required Time : 0.50 MHz ( period = 1999.998 ns )
Actual Time : N/A
From : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]
To : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]
From Clock : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]
To Clock : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]
Failed Paths : 0
Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
Slack : 1.825 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]
To : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
Failed Paths : 0
Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
Slack : 2.664 ns
Slack : 1.775 ns
Required Time : 66.00 MHz ( period = 15.151 ns )
Actual Time : N/A
From : FB_ALE
To : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]
From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ
To : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
Failed Paths : 0
Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
Slack : 3.263 ns
Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
Slack : 1.829 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]
To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7]
To : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7]
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
Failed Paths : 0
Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
Slack : 2.585 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|inst90~_Duplicate_4
To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
Failed Paths : 0
Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
Slack : 4.336 ns
Slack : 4.335 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]
To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]
From : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12]
To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12]
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
Failed Paths : 0
@@ -290,7 +250,7 @@ From :
To :
From Clock :
To Clock :
Failed Paths : 51319
Failed Paths : 70406
--------------------------------------------------------------------------------------

27
FPGA_by_Fredi/firebeei1.qws
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@@ -1,27 +0,0 @@
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
ptn_Child3=Document-2
ptn_Child4=Document-3
[ProjectWorkspace.Frames.ChildFrames.Document-0]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
DocPathName=firebee1.bdf
DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
IsChildFrameDetached=False
IsActiveChildFrame=False
ptn_Child1=StateMap
[ProjectWorkspace.Frames.ChildFrames.Document-1]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0]
DocPathName=FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2}
IsChildFrameDetached=False
IsActiveChildFrame=False
ptn_Child1=StateMap
[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0.StateMap]
AFC_IN_REPORT=False

11
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@@ -0,0 +1,11 @@
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.

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FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.cdb Normal file
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FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.hdb Normal file
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FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.logdb Normal file
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@@ -0,0 +1,5 @@
v1
DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12|mult_aat:auto_generated|mac_out2,
DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6|mult_aat:auto_generated|mac_out2,
DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated|mac_out2,
PORT_SWAPPING,PORT_SWAPPING_FINISHED,Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated|mac_mult1,

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FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.map.cdb Normal file
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FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.merge_hb.atm Normal file
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56
FPGA_by_Fredi/lpm_counter1.bsf Normal file
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@@ -0,0 +1,56 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 144 80)
(text "lpm_counter1" (rect 23 2 138 21)(font "Arial" (font_size 10)))
(text "inst" (rect 8 61 31 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
(text "clock" (rect 26 24 57 40)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 144 40)
(output)
(text "q[11..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
(text "q[11..0]" (rect 81 32 125 48)(font "Arial" (font_size 8)))
(line (pt 144 40)(pt 128 40)(line_width 3))
)
(port
(pt 144 56)
(output)
(text "cout" (rect 0 0 29 16)(font "Arial" (font_size 8)))
(text "cout" (rect 100 48 125 64)(font "Arial" (font_size 8)))
(line (pt 144 56)(pt 128 56)(line_width 1))
)
(drawing
(text "up counter" (rect 70 18 122 32)(font "Arial" ))
(line (pt 16 16)(pt 128 16)(line_width 1))
(line (pt 128 16)(pt 128 64)(line_width 1))
(line (pt 128 64)(pt 16 64)(line_width 1))
(line (pt 16 64)(pt 16 16)(line_width 1))
(line (pt 16 26)(pt 22 32)(line_width 1))
(line (pt 22 32)(pt 16 38)(line_width 1))
)
)

23
FPGA_by_Fredi/lpm_counter1.cmp Normal file
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@@ -0,0 +1,23 @@
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_counter1
PORT
(
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
end component;

24
FPGA_by_Fredi/lpm_counter1.inc Normal file
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@@ -0,0 +1,24 @@
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION lpm_counter1
(
clock
)
RETURNS (
cout,
q[11..0]
);

6
FPGA_by_Fredi/lpm_counter1.qip Normal file
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@@ -0,0 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "LPM_COUNTER"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter1.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter1.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter1.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter1.cmp"]

103
FPGA_by_Fredi/lpm_counter1.tdf Normal file
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@@ -0,0 +1,103 @@
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: lpm_counter1.tdf
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
INCLUDE "lpm_counter.inc";
SUBDESIGN lpm_counter1
(
clock : INPUT;
cout : OUTPUT;
q[11..0] : OUTPUT;
)
VARIABLE
lpm_counter_component : lpm_counter WITH (
LPM_DIRECTION = "UP",
LPM_PORT_UPDOWN = "PORT_UNUSED",
LPM_TYPE = "LPM_COUNTER",
LPM_WIDTH = 12
);
BEGIN
cout = lpm_counter_component.cout;
q[11..0] = lpm_counter_component.q[11..0];
lpm_counter_component.clock = clock;
END;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "1"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "12"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL q[11..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.tdf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1_inst.tdf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm

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11
FPGA_by_Fredi/lpm_counter1_waveforms.html
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@@ -1,16 +1,13 @@
<html>
<head>
<title>Sample Waveforms for lpm_counter1.vhd </title>
<title>Sample Waveforms for "lpm_counter1.tdf" </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file lpm_counter1.vhd </CENTER></h2>
<P>The following waveforms show the behavior of lpm_counter megafunction for the chosen set of parameters in design lpm_counter1.vhd. The design lpm_counter1.vhd is a 4 bit up modulus 8 counter. </P>
<h2><CENTER>Sample behavioral waveforms for design file "lpm_counter1.tdf" </CENTER></h2>
<P>The following waveforms show the behavior of lpm_counter megafunction for the chosen set of parameters in design "lpm_counter1.tdf". The design "lpm_counter1.tdf" is a 12 bit up counter. </P>
<CENTER><img src=lpm_counter1_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing counter operation. </CENTER></P>
<P><FONT size=3></P>
<CENTER><img src=lpm_counter1_wave1.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 2 : Wave showing counter cout and/or modulus operation. </CENTER></P>
<P><FONT size=3>The counter counts till the modulus value 7. </P>
<P><FONT size=3>The output port cout will be asserted at the completion of count sequence. The ports cin and cout are used to chain multiple counters together. </P>
<P></P>
</body>
</html>

1838
FPGA_by_Fredi/lpm_mux0.bsf Normal file
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278
FPGA_by_Fredi/lpm_mux0.cmp Normal file
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@@ -0,0 +1,278 @@
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_mux0
PORT
(
data0x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data100x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data101x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data102x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data103x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data104x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data105x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data106x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data107x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data108x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data109x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data10x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data110x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data111x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data112x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data113x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data114x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data115x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data116x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data117x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data118x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data119x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data11x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data120x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data121x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data122x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data123x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data124x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data125x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data126x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data127x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data128x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data129x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data12x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data130x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data131x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data132x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data133x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data134x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data135x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data136x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data137x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data138x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data139x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data13x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data140x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data141x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data142x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data143x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data144x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data145x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data146x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data147x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data148x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data149x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data14x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data150x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data151x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data152x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data153x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data154x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data155x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data156x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data157x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data158x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data159x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data15x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data160x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data161x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data162x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data163x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data164x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data165x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data166x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data167x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data168x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data169x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data16x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data170x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data171x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data172x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data173x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data174x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data175x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data176x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data177x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data178x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data179x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data17x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data180x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data181x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data182x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data183x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data184x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data185x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data186x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data187x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data188x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data189x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data18x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data190x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data191x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data192x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data193x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data194x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data195x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data196x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data197x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data198x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data199x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data19x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data200x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data201x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data202x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data203x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data204x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data205x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data206x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data207x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data208x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data209x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data20x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data210x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data211x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data212x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data213x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data214x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data215x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data216x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data217x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data218x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data219x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data21x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data220x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data221x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data222x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data223x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data224x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data225x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data226x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data227x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data228x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data229x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data22x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data230x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data231x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data232x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data233x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data234x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data235x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data236x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data237x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data238x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data239x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data23x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data240x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data241x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data242x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data243x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data244x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data245x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data246x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data247x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data248x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data249x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data24x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data250x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data251x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data252x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data253x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data254x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data255x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data25x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data26x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data27x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data28x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data29x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data2x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data30x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data31x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data32x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data33x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data34x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data35x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data36x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data37x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data38x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data39x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data3x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data40x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data41x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data42x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data43x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data44x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data45x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data46x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data47x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data48x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data49x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data4x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data50x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data51x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data52x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data53x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data54x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data55x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data56x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data57x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data58x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data59x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data5x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data60x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data61x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data62x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data63x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data64x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data65x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data66x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data67x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data68x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data69x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data6x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data70x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data71x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data72x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data73x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data74x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data75x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data76x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data77x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data78x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data79x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data7x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data80x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data81x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data82x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data83x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data84x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data85x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data86x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data87x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data88x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data89x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data8x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data90x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data91x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data92x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data93x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data94x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data95x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data96x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data97x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data98x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data99x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data9x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
);
end component;

279
FPGA_by_Fredi/lpm_mux0.inc Normal file
View File

@@ -0,0 +1,279 @@
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION lpm_mux0
(
data0x[127..0],
data100x[127..0],
data101x[127..0],
data102x[127..0],
data103x[127..0],
data104x[127..0],
data105x[127..0],
data106x[127..0],
data107x[127..0],
data108x[127..0],
data109x[127..0],
data10x[127..0],
data110x[127..0],
data111x[127..0],
data112x[127..0],
data113x[127..0],
data114x[127..0],
data115x[127..0],
data116x[127..0],
data117x[127..0],
data118x[127..0],
data119x[127..0],
data11x[127..0],
data120x[127..0],
data121x[127..0],
data122x[127..0],
data123x[127..0],
data124x[127..0],
data125x[127..0],
data126x[127..0],
data127x[127..0],
data128x[127..0],
data129x[127..0],
data12x[127..0],
data130x[127..0],
data131x[127..0],
data132x[127..0],
data133x[127..0],
data134x[127..0],
data135x[127..0],
data136x[127..0],
data137x[127..0],
data138x[127..0],
data139x[127..0],
data13x[127..0],
data140x[127..0],
data141x[127..0],
data142x[127..0],
data143x[127..0],
data144x[127..0],
data145x[127..0],
data146x[127..0],
data147x[127..0],
data148x[127..0],
data149x[127..0],
data14x[127..0],
data150x[127..0],
data151x[127..0],
data152x[127..0],
data153x[127..0],
data154x[127..0],
data155x[127..0],
data156x[127..0],
data157x[127..0],
data158x[127..0],
data159x[127..0],
data15x[127..0],
data160x[127..0],
data161x[127..0],
data162x[127..0],
data163x[127..0],
data164x[127..0],
data165x[127..0],
data166x[127..0],
data167x[127..0],
data168x[127..0],
data169x[127..0],
data16x[127..0],
data170x[127..0],
data171x[127..0],
data172x[127..0],
data173x[127..0],
data174x[127..0],
data175x[127..0],
data176x[127..0],
data177x[127..0],
data178x[127..0],
data179x[127..0],
data17x[127..0],
data180x[127..0],
data181x[127..0],
data182x[127..0],
data183x[127..0],
data184x[127..0],
data185x[127..0],
data186x[127..0],
data187x[127..0],
data188x[127..0],
data189x[127..0],
data18x[127..0],
data190x[127..0],
data191x[127..0],
data192x[127..0],
data193x[127..0],
data194x[127..0],
data195x[127..0],
data196x[127..0],
data197x[127..0],
data198x[127..0],
data199x[127..0],
data19x[127..0],
data1x[127..0],
data200x[127..0],
data201x[127..0],
data202x[127..0],
data203x[127..0],
data204x[127..0],
data205x[127..0],
data206x[127..0],
data207x[127..0],
data208x[127..0],
data209x[127..0],
data20x[127..0],
data210x[127..0],
data211x[127..0],
data212x[127..0],
data213x[127..0],
data214x[127..0],
data215x[127..0],
data216x[127..0],
data217x[127..0],
data218x[127..0],
data219x[127..0],
data21x[127..0],
data220x[127..0],
data221x[127..0],
data222x[127..0],
data223x[127..0],
data224x[127..0],
data225x[127..0],
data226x[127..0],
data227x[127..0],
data228x[127..0],
data229x[127..0],
data22x[127..0],
data230x[127..0],
data231x[127..0],
data232x[127..0],
data233x[127..0],
data234x[127..0],
data235x[127..0],
data236x[127..0],
data237x[127..0],
data238x[127..0],
data239x[127..0],
data23x[127..0],
data240x[127..0],
data241x[127..0],
data242x[127..0],
data243x[127..0],
data244x[127..0],
data245x[127..0],
data246x[127..0],
data247x[127..0],
data248x[127..0],
data249x[127..0],
data24x[127..0],
data250x[127..0],
data251x[127..0],
data252x[127..0],
data253x[127..0],
data254x[127..0],
data255x[127..0],
data25x[127..0],
data26x[127..0],
data27x[127..0],
data28x[127..0],
data29x[127..0],
data2x[127..0],
data30x[127..0],
data31x[127..0],
data32x[127..0],
data33x[127..0],
data34x[127..0],
data35x[127..0],
data36x[127..0],
data37x[127..0],
data38x[127..0],
data39x[127..0],
data3x[127..0],
data40x[127..0],
data41x[127..0],
data42x[127..0],
data43x[127..0],
data44x[127..0],
data45x[127..0],
data46x[127..0],
data47x[127..0],
data48x[127..0],
data49x[127..0],
data4x[127..0],
data50x[127..0],
data51x[127..0],
data52x[127..0],
data53x[127..0],
data54x[127..0],
data55x[127..0],
data56x[127..0],
data57x[127..0],
data58x[127..0],
data59x[127..0],
data5x[127..0],
data60x[127..0],
data61x[127..0],
data62x[127..0],
data63x[127..0],
data64x[127..0],
data65x[127..0],
data66x[127..0],
data67x[127..0],
data68x[127..0],
data69x[127..0],
data6x[127..0],
data70x[127..0],
data71x[127..0],
data72x[127..0],
data73x[127..0],
data74x[127..0],
data75x[127..0],
data76x[127..0],
data77x[127..0],
data78x[127..0],
data79x[127..0],
data7x[127..0],
data80x[127..0],
data81x[127..0],
data82x[127..0],
data83x[127..0],
data84x[127..0],
data85x[127..0],
data86x[127..0],
data87x[127..0],
data88x[127..0],
data89x[127..0],
data8x[127..0],
data90x[127..0],
data91x[127..0],
data92x[127..0],
data93x[127..0],
data94x[127..0],
data95x[127..0],
data96x[127..0],
data97x[127..0],
data98x[127..0],
data99x[127..0],
data9x[127..0],
sel[7..0]
)
RETURNS (
result[127..0]
);

6
FPGA_by_Fredi/lpm_mux0.qip Normal file
View File

@@ -0,0 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.cmp"]

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