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FPGA_Config/FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt
David Gálvez 68129dbe57 Sync with Fredi's source tree 13/06/2015
Parallel port fix.
2018-04-09 17:19:13 +02:00

21 lines
502 B
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PLL_Name altpll1:inst|altpll:altpll_component|altpll_3vp2:auto_generated|pll1
PLLJITTER 36
PLLSPEmax 84
PLLSPEmin -53
PLL_Name altpll2:inst12|altpll:altpll_component|altpll_1r33:auto_generated|pll1
PLLJITTER 43
PLLSPEmax 84
PLLSPEmin -53
PLL_Name altpll3:inst13|altpll:altpll_component|altpll_aus2:auto_generated|pll1
PLLJITTER NA
PLLSPEmax 84
PLLSPEmin -53
PLL_Name altpll4:inst22|altpll:altpll_component|altpll_r4n2:auto_generated|pll1
PLLJITTER 31
PLLSPEmax 84
PLLSPEmin -53