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  • 44bdd93e74 Not tested. Hopefully fixed interrupts. Markus Fröschle 2015-01-08 16:36:55 +00:00
  • 922be63d2a fixed formatting Markus Fröschle 2015-01-07 13:54:35 +00:00
  • 19c8636eae fixed formatting Markus Fröschle 2015-01-07 13:54:35 +00:00
  • 2eb79b156a reformatted Markus Fröschle 2014-12-30 22:25:36 +00:00
  • 1ca15ed48b reformatted Markus Fröschle 2014-12-30 22:25:36 +00:00
  • dd2814477b added DQS_FREQUENCY to assignment editor (with no apparent result) Markus Fröschle 2014-12-30 15:46:32 +00:00
  • b22e83e8b7 more constraints Markus Fröschle 2014-12-30 15:26:27 +00:00
  • 3daaa49e79 reduced wait times Markus Fröschle 2014-12-30 14:21:05 +00:00
  • 7a4037eb24 reduced wait times Markus Fröschle 2014-12-30 14:21:05 +00:00
  • 17b17a2263 further constrained Markus Fröschle 2014-12-30 14:05:49 +00:00
  • 7ef61bd397 added sdc file and upgraded IP components Markus Fröschle 2014-12-30 12:57:22 +00:00
  • 7f5ab992fc is a generated file Markus Fröschle 2014-12-30 08:15:54 +00:00
  • f511b1e324 removed more generated files Markus Fröschle 2014-12-30 08:15:10 +00:00
  • 978a642ce7 removed more generated files Markus Fröschle 2014-12-30 08:12:59 +00:00
  • 6e4e180e96 removed generated files Markus Fröschle 2014-12-30 07:37:08 +00:00
  • 320230ce31 merged latest fixes from R_0_8_6 branch Markus Fröschle 2014-12-29 14:44:55 +00:00
  • c90a6e58f9 merged latest fixes from R_0_8_6 branch Markus Fröschle 2014-12-29 14:44:55 +00:00
  • 8cb34bfe15 vmem_ctrl cannot be read on the current FPGA version Markus Fröschle 2014-12-29 14:37:39 +00:00
  • 550572d2d3 vmem_ctrl cannot be read on the current FPGA version Markus Fröschle 2014-12-29 14:37:39 +00:00
  • 40162047d8 (hopefully) fixed a problem with hang when i2c communication to TFP410 fails R_0_8_6 Markus Fröschle 2014-12-28 22:47:43 +00:00
  • 51d9e1f5f6 modified DDR_CTRL state machine as exact copy of Fredi's HDL original Markus Fröschle 2014-12-28 10:01:08 +00:00
  • c90e9e1b8c reverted DDR_CTR to original version Markus Fröschle 2014-12-28 06:48:41 +00:00
  • 825eb66023 added more tests Markus Fröschle 2014-12-27 20:22:09 +00:00
  • acaafef944 added more tests Markus Fröschle 2014-12-27 20:22:09 +00:00
  • 2adda3f946 various changes Markus Fröschle 2014-12-27 20:21:33 +00:00
  • b3f899a1fb disabled caches for tests to work reliably Markus Fröschle 2014-12-27 16:49:57 +00:00
  • 6fcd8c2cf2 disabled caches for tests to work reliably Markus Fröschle 2014-12-27 16:49:57 +00:00
  • 5cb3becb63 reformatted Markus Fröschle 2014-12-27 07:07:46 +00:00
  • a628e686cc compile ELF by default Markus Fröschle 2014-12-26 22:15:38 +00:00
  • 525253f70a compile ELF by default Markus Fröschle 2014-12-26 22:15:38 +00:00
  • eb47f0ae06 reformatted Markus Fröschle 2014-12-26 22:14:57 +00:00
  • 09b8c3acb7 reformatted Markus Fröschle 2014-12-26 22:14:57 +00:00
  • 851e2a455f DDR RAM read and write both seem to work but writing is eeeextreeeeeeemly slow for now... Markus Fröschle 2014-12-26 20:01:53 +00:00
  • a68d0dbc60 more FPGA tests Markus Fröschle 2014-12-26 20:01:03 +00:00
  • 0cc08d4bed more FPGA tests Markus Fröschle 2014-12-26 20:01:03 +00:00
  • 0c26287af7 moved logic into process Markus Fröschle 2014-12-26 19:47:22 +00:00
  • df5164157d fixed earlier misunderstandings, but still doesn't work Markus Fröschle 2014-12-26 16:29:40 +00:00
  • a522fccc80 added more FPGA tests Markus Fröschle 2014-12-26 15:35:01 +00:00
  • 22f39a7414 added more FPGA tests Markus Fröschle 2014-12-26 15:35:01 +00:00
  • 31cd70c66d do first tests with FPGA config. SDRAM doesn't seem to work, reading and writing of Firebee CLUT does work, hovever. Markus Fröschle 2014-12-26 12:31:44 +00:00
  • aea1a66956 do first tests with FPGA config. SDRAM doesn't seem to work, reading and writing of Firebee CLUT does work, hovever. Markus Fröschle 2014-12-26 12:31:44 +00:00
  • 0bd0b02c3c added test program for FPGA Markus Fröschle 2014-12-26 11:38:27 +00:00
  • 6ecdcbb3d1 added test program for FPGA Markus Fröschle 2014-12-26 11:38:27 +00:00
  • 5fe664c290 fixed to support bugfix from 0.8.6 Markus Fröschle 2014-12-26 10:33:53 +00:00
  • 551375c12e fixed to support bugfix from 0.8.6 Markus Fröschle 2014-12-26 10:33:53 +00:00
  • 645aca7228 merged fixes from 0.8.6.1 (errornous skip of FPGA load) Markus Fröschle 2014-12-26 09:36:45 +00:00
  • 8081df42a6 merged fixes from 0.8.6.1 (errornous skip of FPGA load) Markus Fröschle 2014-12-26 09:36:45 +00:00
  • 732956830f start merging R_0.8.6.1 (jtag load bug fix) Markus Fröschle 2014-12-26 09:07:22 +00:00
  • b1c7851f34 start merging R_0.8.6.1 (jtag load bug fix) Markus Fröschle 2014-12-26 09:07:22 +00:00
  • f871794760 fixed bug that prevented proper detection of FPGA load skip request Markus Fröschle 2014-12-26 08:56:30 +00:00
  • 88c1bd2373 fixed errornous deactivation of FPGA load Markus Fröschle 2014-12-26 07:26:10 +00:00
  • 8706322f96 added to the DDR RAM model reformatted (converted tabs to spaces) Markus Fröschle 2014-12-25 15:20:14 +00:00
  • a7eb46e158 used design assistant to force the fitter to put more effort into getting the timing right which removed negative slack Markus Fröschle 2014-12-25 10:08:53 +00:00
  • 674406e4d3 formatting Markus Fröschle 2014-12-24 17:54:51 +00:00
  • 06688a9a02 got rid of BIT signal types Markus Fröschle 2014-12-24 17:07:51 +00:00
  • 5a923ddada fixed formatting Markus Fröschle 2014-12-24 16:24:21 +00:00
  • ef1807665e removed UNSIGNED() conversions that are not needed anymore Markus Fröschle 2014-12-24 16:17:17 +00:00
  • 517599bc33 reenabled all modules Markus Fröschle 2014-12-24 16:11:12 +00:00
  • e7e4fa4e75 added a little bus toggling to the test bench Markus Fröschle 2014-12-24 09:42:57 +00:00
  • 766d75a5d3 fixed pin assignments for renamed pins fb_cs_n[..] Markus Fröschle 2014-12-23 22:35:03 +00:00
  • 71db27849b started implementing SAMSUNG's Verilog DDR model in VHDL Markus Fröschle 2014-12-23 22:30:23 +00:00
  • 63c0a2f167 added testbench files Markus Fröschle 2014-12-23 18:25:15 +00:00
  • 5eac75430e renamed files, fixed testbench Markus Fröschle 2014-12-23 18:20:11 +00:00
  • 5cc8c3bbbf fixed type inconistencies Markus Fröschle 2014-12-23 16:44:21 +00:00
  • c197609be6 started "full fledged" testbench to analyze where fb_ta_n gets lost Markus Fröschle 2014-12-23 14:56:53 +00:00
  • 5c9253c6a9 implemented video_control_register as ALIAS fb_ta_n stuck at GND? Markus Fröschle 2014-12-23 11:21:56 +00:00
  • a4835a305c experimental Markus Fröschle 2014-12-23 08:59:40 +00:00
  • 1f50d16cfc got rid of several unnecessary UNSIGNED() type conversions Markus Fröschle 2014-12-23 08:33:59 +00:00
  • 85ec4c726c added io_register.vhd Markus Fröschle 2014-12-22 22:14:33 +00:00
  • 1612d52010 more formatting Markus Fröschle 2014-12-22 21:09:46 +00:00
  • 0f55615b45 converted more STD_LOGIC_VECTORs to UNSIGNED Markus Fröschle 2014-12-22 19:58:01 +00:00
  • 822f5a64d2 finished fixing formatting Markus Fröschle 2014-12-22 12:36:35 +00:00
  • e2c69a75f6 changed all STD_LOGIC_VECTOR signals to UNSIGNED to ease calculations Markus Fröschle 2014-12-22 12:09:53 +00:00
  • e0a1dfedcf enabled flow analysis Markus Fröschle 2014-12-22 10:05:59 +00:00
  • 7963f9c8ae fixed formatting Markus Fröschle 2014-12-22 08:50:22 +00:00
  • 7d98e35c50 fixed fifo_mw initialization Markus Fröschle 2014-12-22 08:40:35 +00:00
  • 4bb0527539 fifo_mw never got a value assigned - fixed for testbench, but still open for toplevel Markus Fröschle 2014-12-22 08:31:07 +00:00
  • 89f75bd4e8 fixed IRQn[x] to IRQ_n[x] Markus Fröschle 2014-12-22 06:42:16 +00:00
  • 2de4cceb00 fixed assignment to the new postfixed names Markus Fröschle 2014-12-22 06:37:25 +00:00
  • 5b64c3d6cf fixed CLOCK_TICK generic Markus Fröschle 2014-12-22 06:09:10 +00:00
  • 3e769ceeb4 DDR2 simulation compiles in ModelSim Markus Fröschle 2014-12-22 05:57:17 +00:00
  • 1aab3c25d2 further extended testbench. Need to fix difference between clock ticks and TIME in original code Markus Fröschle 2014-12-21 20:40:51 +00:00
  • 9d7858a144 fixed missing data_in Markus Fröschle 2014-12-21 11:13:58 +00:00
  • ff7faf4395 more formatting and corrections of testbench code Markus Fröschle 2014-12-21 10:55:49 +00:00
  • 04c32593cf renamed RAM model Markus Fröschle 2014-12-21 08:33:17 +00:00
  • db93ec6026 updated testbench (not functional yet) Markus Fröschle 2014-12-21 08:32:20 +00:00
  • 132f136d3a relaxed timing and uncommented unneeded components in toplevel until timing issues are solved added lots of set_false_path statements to sort out timing problems Markus Fröschle 2014-12-20 12:26:32 +00:00
  • 9f288fc3d0 fixed formatting Markus Fröschle 2014-12-20 10:13:32 +00:00
  • 0c95b41b15 commented everything which is not needed to debug video system/DDR controller for now Markus Fröschle 2014-12-20 09:12:56 +00:00
  • 6d3b09f87b fixed formatting Markus Fröschle 2014-12-20 09:05:03 +00:00
  • fe27ee2e22 fixed formatting errors Markus Fröschle 2014-12-20 08:48:21 +00:00
  • 599b23bdcf renamed directory hierarchy and toplevel entity Markus Fröschle 2014-12-20 08:34:53 +00:00
  • e5f37977e1 renamed files Markus Fröschle 2014-12-20 08:26:37 +00:00
  • c51e6c6098 reformatted Markus Fröschle 2014-12-20 08:25:53 +00:00
  • cbff11f5d8 renamed files Markus Fröschle 2014-12-20 08:22:10 +00:00
  • 91ea8fc622 reformatted Markus Fröschle 2014-12-20 01:21:36 +00:00
  • dce24ff7c7 fixed comments Markus Fröschle 2014-12-16 20:33:51 +00:00
  • c81fc7e7e9 fixed comments Markus Fröschle 2014-12-16 20:33:51 +00:00
  • a40831e6b7 Delete USB directories and the sorce code from the repository. Here is not the place for this source code, it's not related directly with the project. They were my firsts experiments with USB, it's very outdated too. David Gálvez 2014-11-28 10:25:52 +00:00
  • 764e089806 improved error handling Markus Fröschle 2014-11-24 16:12:35 +00:00