bump version number

was scanning PCI config space of all valid slot/bus combination when all needed information is already available from the initial scan.

.gdbinit

@@ -3,12 +3,12 @@ define tr
 	#!killall m68k-bdm-gdbserver
 	target remote | m68k-bdm-gdbserver pipe /dev/bdmcf3
 	#target remote localhost:1234
-	#target remote | m68k-bdm-gdbserver pipe /dev/tblcf1
+	#target remote | m68k-bdm-gdbserver pipe /dev/tblcf2
 	#target dbug /dev/ttyS0
 	#monitor bdm-reset
 end
 define tbtr
-	target remote | m68k-bdm-gdbserver pipe /dev/tblcf3
+	target remote | m68k-bdm-gdbserver pipe /dev/tblcf2
 end
 source mcf5474.gdb
 set breakpoint auto-hw

BaS_gcc.config

@@ -1,2 +1,3 @@
 // ADD PREDEFINED MACROS HERE!
-#define MACHINE_FIREBEE
+//#define MACHINE_FIREBEE
+#define MACHINE_M5484LITE

BaS_gcc.includes

@@ -1,44 +1,55 @@
-include
-tos/jtagwait/include
-tos/pci_test/include
-/usr/m68k-atari-mint/include
-dma
-m54455
-sys
-pci
-tos/pci_test
-tos/jtagwait/m5475/mshort
-m5484lite
-tos/pci_test/include
-tos/bascook
-tos/vmem_test/m5475/mshort
-i2c
-fs
-tos/vmem_test/m5475
-tos/pci_test/m5475
-spi
-if
-tos/jtagwait/m5475
-util
-kbd
-flash_scripts
-video
-usb
-exe
-tos/vmem_test/sources
-tos
-nutil
-tos/jtagwait/sources
-x86emu
-flash
-tos/vmem_test/include
-tos/bascook/sources
-tos/pci_test/m5475/mshort
-.
-radeon
-net
-xhdi
-tos/vmem_test
-tos/pci_test/sources
-firebee
-tos/jtagwait
+include
+tos/jtagwait/include
+tos/pci_test/include
+/usr/m68k-atari-mint/include
+/opt/cross-mint/m68k-atari-mint/include
+/opt/gygwin/opt/cross-mint/m68k-atari-mint/include
+/opt/m68k-elf/include
+/opt/cygwin/opt/m68k-elf/include
+/opt/cygwin/opt/m68k-elf/lib/gcc/m68k-elf/4.6.4/include
+dma
+m54455
+sys
+pci
+tos/pci_test
+tos/jtagwait/m5475/mshort
+m5484lite
+tos/pci_test/include
+tos/bascook
+tos/vmem_test/m5475/mshort
+i2c
+fs
+tos/vmem_test/m5475
+tos/pci_test/m5475
+spi
+if
+tos/jtagwait/m5475
+util
+kbd
+flash_scripts
+video
+usb
+exe
+tos/vmem_test/sources
+tos
+nutil
+tos/jtagwait/sources
+x86emu
+flash
+tos/vmem_test/include
+tos/bascook/sources
+tos/pci_test/m5475/mshort
+.
+radeon
+net
+xhdi
+tos/vmem_test
+tos/pci_test/sources
+firebee
+tos/jtagwait
+tos/fpga_test/include
+tos/fpga_test
+tos/fpga_test/sources
+tos/pci_mem
+tos/pci_mem/include
+tos/pci_mem/sources

Makefile

@@ -8,6 +8,14 @@
 # installation, but allows source level debugging over BDM with a recent gdb (tested with 7.5),
 # the m68k BDM tools from sourceforge (http://bdm.sourceforge.net) and a BDM pod (TBLCF and P&E tested).
 
+VERBOSE=N
+
+ifneq (Y,$(VERBOSE))
+Q=@
+else
+Q=
+endif
+
 # can be either "Y" or "N" (without quotes). "Y" for using the m68k-elf-, "N" for using the m68k-atari-mint
 # toolchain
 COMPILE_ELF=Y
@@ -38,10 +46,14 @@ endif
 
 INCLUDE=-Iinclude
 CFLAGS=	-Wall \
+	-O2 \
 	-fomit-frame-pointer \
 	-ffreestanding \
+	-fno-strict-aliasing \
 	-fleading-underscore \
+	-Winline \
 	-Wa,--register-prefix-optional
+
 CFLAGS_OPTIMIZED = -mcpu=5474 \
 		-Wall \
 		-O2 \
@@ -51,7 +63,7 @@ CFLAGS_OPTIMIZED = -mcpu=5474 \
 		-Wa,--register-prefix-optional
 LDFLAGS=
 
-TRGTDIRS= ./firebee ./m5484lite
+TRGTDIRS= ./firebee ./m54455 ./m5484lite
 OBJDIRS=$(patsubst %, %/objs,$(TRGTDIRS))
 TOOLDIR=util
 
@@ -62,7 +74,7 @@ LDCFILE=bas.lk
 LDRFILE=ram.lk
 LDCSRC=bas.lk.in
 LDCBSRC=basflash.lk.in
-LDCBFS=bashflash.lk
+LDCBFS=basflash.lk
 
 # this Makefile can create the BaS to flash or an arbitrary ram address (for BDM debugging). See
 # below for the definition of TARGET_ADDRESS
@@ -75,8 +87,11 @@ CSRCS= \
 	init_fpga.c \
 	fault_vectors.c \
 	interrupts.c \
+	\
 	bas_printf.c \
 	bas_string.c \
+	conout.c \
+	\
 	BaS.c \
 	cache.c \
 	mmu.c \
@@ -92,6 +107,7 @@ CSRCS= \
 	xhdi_sd.c \
 	xhdi_interface.c \
 	pci.c \
+	pci_errata.c \
 	dspi.c \
 	driver_vec.c \
 	driver_mem.c \
@@ -130,10 +146,13 @@ CSRCS= \
 	videl.c \
 	video.c \
 	\
+	i2c-algo-bit.c \
+	\
 	radeon_base.c \
 	radeon_accel.c \
 	radeon_cursor.c \
 	radeon_monitor.c \
+	radeon_i2c.c \
 	fnt_st_8x16.c \
 	\
 	x86emu.c \
@@ -147,7 +166,6 @@ CSRCS= \
 
 ASRCS= \
 	startcf.S \
-	printf_helper.S \
 	exceptions.S \
 	setjmp.S \
 	xhdi_vec.S \
@@ -175,16 +193,19 @@ lib: $(LIBS)
 .PHONY: ver
 ver:
 	touch include/version.h
+
 .PHONY: tos
 tos:
-	(cd tos; $(MAKE))
+	$(Q)(cd tos; $(MAKE) -s)
 
 .PHONY: clean
 clean:
-	for d in $(TRGTDIRS);\
+	$(Q)for d in $(TRGTDIRS);\
 		do rm -f $$d/*.map $$d/*.s19 $$d/*.elf $$d/*.lk $$d/*.a $$d/objs/* $$d/depend;\
 	done
-	rm -f tags
+	$(Q)rm -f tags
+	$(Q)(cd tos; make -s clean)
+
 
 
 # flags for targets
@@ -217,10 +238,12 @@ firebee/basflash.$(EXE): CFLAGS += -mcpu=5474
 #
 define CC_TEMPLATE
 $(1)/objs/%.o:%.c
-	$(CC) $$(CFLAGS) -D$$(MACHINE) $(INCLUDE) -c $$< -o $$@
+	$(Q)echo CC $$<
+	$(Q)$(CC) $$(CFLAGS) -D$$(MACHINE) $(INCLUDE) -c $$< -o $$@
 
 $(1)/objs/%.o:%.S
-	$(CC) $$(CFLAGS) -Wa,--bitwise-or -D$$(MACHINE) $(INCLUDE) -c $$< -o $$@
+	$(Q)echo CC $$<
+	$(Q)$(CC) $$(CFLAGS) -Wa,--bitwise-or -D$$(MACHINE) $(INCLUDE) -c $$< -o $$@
 endef
 $(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
 
@@ -236,7 +259,8 @@ else
 	MACHINE=MACHINE_M5484LITE
 endif
 $(1)/depend:$(SRCS)
-	$(CC) $$(CFLAGS) -D$$(MACHINE) $(INCLUDE) -M $$^ | sed -e "s#^\(.*\).o:#"$(1)"/objs/\1.o:#" > $$@
+	$(Q)echo DEPEND
+	$(Q)$(CC) $$(CFLAGS) -D$$(MACHINE) $(INCLUDE) -M $$^ | sed -e "s#^\(.*\).o:#"$(1)"/objs/\1.o:#" > $$@
 endef
 $(foreach DIR,$(TRGTDIRS),$(eval $(call DEP_TEMPLATE,$(DIR))))
 
@@ -247,8 +271,9 @@ $(foreach DIR,$(TRGTDIRS),$(eval $(call DEP_TEMPLATE,$(DIR))))
 define AR_TEMPLATE
 $(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
 $(1)/$(LIBBAS): $$($(1)_OBJS)
-	$(AR) rv $$@ $$?
-	$(RANLIB) $$@
+	$(Q)echo AR $$@
+	$(Q)$(AR) r $$@ $$?
+	$(Q)$(RANLIB) $$@
 endef
 $(foreach DIR,$(TRGTDIRS),$(eval $(call AR_TEMPLATE,$(DIR))))
 
@@ -257,44 +282,59 @@ ifeq ($(COMPILE_ELF),Y)
 else
 	FORMAT_ELF=0
 endif
+
+define LK_TEMPLATE
+$(1)/$$(LDCFILE): $(LDCSRC)
+	$(Q)echo CPP $$<
+	$(Q)$(CPP) $(INCLUDE) -DOBJDIR=$(1)/objs -P -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $$< -o $$@
+endef
+$(foreach DIR,$(TRGTDIRS),$(eval $(call LK_TEMPLATE,$(DIR))))
+
 #
 # define pattern rules for binaries
 #
 define EX_TEMPLATE
 # pattern rule for flash
 $(1)_MAPFILE=$(1)/$$(basename $$(FLASH_EXEC)).map
-$(1)/$$(FLASH_EXEC): $(1)/$(LIBBAS) $(LDCSRC)
-	$(CPP) $(INCLUDE) -DOBJDIR=$(1)/objs -P -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCSRC) -o $(1)/$$(LDCFILE)
-	#$(LD) --oformat $$(FORMAT) -Map $$($(1)_MAPFILE) --cref -T $(1)/$$(LDCFILE) $(LDLIBS) -o $$@
-	$(CC) $$(CFLAGS) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDCFILE) $(LDLIBS) -o $$@
+$(1)/$$(FLASH_EXEC): $(1)/$(LIBBAS) $(1)/$$(LDCFILE)
+	$(Q)echo CC $$@
+	$(Q)$(CC) $$(CFLAGS) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDCFILE) $(LDLIBS) -o $$@
 ifeq ($(COMPILE_ELF),Y)
-	$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
+	$(Q)echo OBJCOPY $$@
+	$(Q)$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
 else
-	objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf
+	$(Q)echo OBJCOPY $$@
+	$(Q)objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf
 endif
 
 # pattern rule for RAM
 $(1)_MAPFILE_RAM=$(1)/$$(basename $$(RAM_EXEC)).map
-$(1)/$$(RAM_EXEC): $(1)/$(LIBBAS) $(LDCSRC)
-	$(CPP) $(INCLUDE) -DCOMPILE_RAM -DOBJDIR=$(1)/objs -P -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCSRC) -o $(1)/$$(LDRFILE)
-	#$(LD) $(LDFLAGS) --oformat $$(FORMAT) -Map $$($(1)_MAPFILE_RAM) --cref -T $(1)/$$(LDRFILE) $(LDLIBS) -o $$@
-	$(CC) $$(CFLAGS) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDRFILE) $(LDLIBS) -o $$@
+$(1)/$$(RAM_EXEC): $(1)/$(LIBBAS) $(1)/$$(LDCFILE)
+	$(Q)echo CPP $$@
+	$(Q)$(CPP) $(INCLUDE) -DCOMPILE_RAM -DOBJDIR=$(1)/objs -P -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCSRC) -o $(1)/$$(LDRFILE)
+	$(Q)echo CC $$@
+	$(Q)$(CC) $$(CFLAGS) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE_RAM) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDRFILE) $(LDLIBS) -o $$@
 ifeq ($(COMPILE_ELF),Y)
-	$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
+	$(Q)echo OBJCOPY $$@
+	$(Q)$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
 else
-	objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf
+	$(Q)echo OBJCOPY $$<
+	$(Q)objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf
 endif
 
 # pattern rule for basflash
 $(1)_MAPFILE_BFL=$(1)/$$(basename $$(BASFLASH_EXEC)).map
 $(1)/$$(BASFLASH_EXEC): $(1)/objs/basflash.o $(1)/objs/basflash_start.o $(1)/$(LIBBAS) $(LDCBFL)
+	$(Q)echo CPP $$<
 	$(CPP) $(INCLUDE) -P -DOBJDIR=$(1)/objs -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCBSRC) -o $(1)/$$(LDCBFS)
-	#$(LD) --oformat $$(FORMAT) -Map $$($(1)_MAPFILE_BFL) --cref -T $(1)/$$(LDCFILE) -L$(1) -lbas $(LDLIBS) -o $$@
-	$(CC) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE_BFL) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDCFILE) -L$(1) -lbas $(LDLIBS) -o $$@
+	$(Q)echo CC $$<
+	$(Q)$(CC) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE_BFL) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDCBFS) -L$(1) -lbas $(LDLIBS) -o $$@
 ifeq ($(COMPILE_ELF),Y)
-	$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
+	$(Q)echo OBJCOPY $$<
+	$(Q)$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
 else
-	objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf
+	$(Q)echo OBJCOPY $$<
+	$(Q)objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf
 endif
 endef
 $(foreach DIR,$(TRGTDIRS),$(eval $(call EX_TEMPLATE,$(DIR))))
@@ -309,7 +349,7 @@ tags:
 
 .PHONY: printvars
 printvars:
-	@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
+	$(Q)$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
 ifeq (MACHINE_M5484LITE,$$(MACHINE))
 	MNAME=m5484lite
 else ifeq (MACHINE_FIREBEE,$(MACHINE))

bas.lk.in

@@ -1,7 +1,7 @@
 #if defined(MACHINE_FIREBEE)
 #include "firebee.h"
 #elif defined(MACHINE_M5484LITE)
-#include "m5484l.h"
+#    include "m5484l.h"
 #elif defined(MACHINE_M54455)
 #include "m54455.h"
 #else
@@ -49,6 +49,8 @@ SECTIONS
 
                 OBJDIR/BaS.o(.text)
                 OBJDIR/pci.o(.text)
+                . = ALIGN(16);
+                OBJDIR/pci_errata.o(.text)
                 OBJDIR/pci_wrappers.o(.text)
                 OBJDIR/usb.o(.text)
                 OBJDIR/driver_mem.o(.text)
@@ -80,10 +82,10 @@ SECTIONS
                 OBJDIR/s19reader.o(.text)
                 OBJDIR/bas_printf.o(.text)
                 OBJDIR/bas_string.o(.text)
+		OBJDIR/conout.o(.text)
 #if (FORMAT_ELF == 1)
                 OBJDIR/libgcc_helper.o(.text)
 #endif
-                OBJDIR/printf_helper.o(.text)
                 OBJDIR/cache.o(.text)
                 OBJDIR/dma.o(.text)
                 OBJDIR/MCD_dmaApi.o(.text)
@@ -95,6 +97,7 @@ SECTIONS
                 OBJDIR/fbmem.o(.text)
                 OBJDIR/fbmon.o(.text)
                 OBJDIR/fbmodedb.o(.text)
+		OBJDIR/fnt_st_8x16.o(.text)
                 OBJDIR/offscreen.o(.text)
 
                 OBJDIR/x86emu.o(.text)
@@ -102,10 +105,13 @@ SECTIONS
                 OBJDIR/x86pcibios.o(.text)
                 OBJDIR/x86biosemu.o(.text)
 
+		OBJDIR/i2c-algo-bit.o(.text)
+
                 OBJDIR/radeon_base.o(.text)
                 OBJDIR/radeon_accel.o(.text)
                 OBJDIR/radeon_cursor.o(.text)
                 OBJDIR/radeon_monitor.o(.text)
+		OBJDIR/radeon_i2c.o(.text)
 
                 OBJDIR/xhdi_sd.o(.text)
                 OBJDIR/xhdi_interface.o(.text)

basflash.lk.in

@@ -1,14 +1,16 @@
-#ifdef MACHINE_FIREBEE
+#if defined(MACHINE_FIREBEE)
 #include "firebee.h"
-#endif /* MACHINE_FIREBEE */
-
-#ifdef MACHINE_M5484LITE
+#elif defined(MACHINE_M5484LITE)
 #include "m5484l.h"
-#endif /* MACHINE_M5484LITE */
+#elif defined(MACHINE_M54455)
+#include "m54455.h"
+#else
+#error unknown machine
+#endif
 
 MEMORY
 {
-   flasher (WX) : ORIGIN = TARGET_ADDRESS, LENGTH = 0x00100000		/* target to load basflash */
+   flasher (WX) : ORIGIN = BFL_TARGET_ADDRESS, LENGTH = 0x00100000		/* target to load basflash */
 }
 
 SECTIONS

dma/MCD_dmaApi.c

@@ -164,11 +164,10 @@ int MCD_initDma (dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags)
         int taskTableSize, varTabsSize, funcDescTabsSize, contextSavesSize;
         int taskDescTabSize;
 
-        int i;
 
         /* check if physical address is aligned on 512 byte boundary */
-        if (((u32)taskTableDest & 0x000001ff) != 0)
-            return(MCD_TABLE_UNALIGNED);
+        if (((u32) taskTableDest & 0x000001ff) != 0)
+            return MCD_TABLE_UNALIGNED;
 
         MCD_taskTable = taskTableDest; /* set up local pointer to task Table */
 
@@ -246,9 +245,9 @@ int MCD_initDma (dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags)
             entryPtr[i].TDTend = (u32)taskDescTabsOffset - 4;
         }
 #ifdef MCD_INCLUDE_EU /* Tack single DMA BDs onto end of code so API controls
-                         where they are since DMA might write to them */        
+                         where they are since DMA might write to them */
         MCD_relocBuffDesc = (MCD_bufDesc*)(entryPtr[NUMOFVARIANTS - 1].TDTend + 4);
-#else /* DMA does not touch them so they can be wherever and we don't need to 
+#else /* DMA does not touch them so they can be wherever and we don't need to
          waste SRAM on them */
         MCD_relocBuffDesc = MCD_singleBufDescs;
 #endif
@@ -300,7 +299,7 @@ int MCD_initDma (dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags)
     else
         MCD_dmaBar->ptdControl |= PTD_CTL_COMM_PREFETCH;
 
-    return(MCD_OK);
+    return MCD_OK;
 }
 /*********************** End of MCD_initDma() ***********************/
 
@@ -379,14 +378,14 @@ int MCD_startDma (
 
     if((channel < 0) || (channel >= NCHANNELS))
         return(MCD_CHANNEL_INVALID);
-        
-    /* tbd - need to determine the proper response to a bad funcDesc when not 
+
+    /* tbd - need to determine the proper response to a bad funcDesc when not
        including EU functions, for now, assign a benign funcDesc, but maybe
        should return an error */
 #ifndef MCD_INCLUDE_EU
     funcDesc = MCD_FUNC_NOEU1;
 #endif
-        
+
 #ifdef MCD_DEBUG
 printf("startDma:Setting up params\n");
 #endif
@@ -547,7 +546,7 @@ printf("startDma:Setting up params\n");
         }
     }
     MCD_chStatus[channel] = MCD_IDLE;
-    return(MCD_OK);
+    return MCD_OK;
 }
 
 /************************ End of MCD_startDma() *********************/
@@ -562,7 +561,7 @@ printf("startDma:Setting up params\n");
  * Notes:
  *  MCD_XferProgrQuery() upon completing or after aborting a DMA, or
  *  while the DMA is in progress, this function returns the first
- *  DMA-destination address not (or not yet) used in the DMA. When 
+ *  DMA-destination address not (or not yet) used in the DMA. When
  *  encountering a non-ready buffer descriptor, the information for
  *  the last completed descriptor is returned.
  *
@@ -694,7 +693,7 @@ int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep)
        default: break;
     }
 
-    return(MCD_OK);
+    return MCD_OK;
 }
 /******************* End of MCD_XferProgrQuery() ********************/
 
@@ -753,7 +752,7 @@ int MCD_killDma (int channel)
      * MCD_XferProgrQuery (channel, &progRep);
      * progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
      */
-    return(MCD_OK);
+    return MCD_OK;
 }
 /************************ End of MCD_killDma() **********************/
 
@@ -776,7 +775,7 @@ int MCD_continDma (int channel)
     MCD_dmaBar->taskControl[channel] |= TASK_CTL_EN;
     MCD_chStatus[channel] = MCD_RUNNING;
 
-    return(MCD_OK);
+    return MCD_OK;
 }
 /********************** End of MCD_continDma() **********************/
 
@@ -808,7 +807,7 @@ int MCD_continDma (int channel)
  * this means that bits 14 and 0 must enable debug functions before
  * bits 1 and 2, respectively, have any effect.
  *
- * NOTE: It's extremely important to not pause more than one DMA channel 
+ * NOTE: It's extremely important to not pause more than one DMA channel
  *  at a time.
  ********************************************************************/
 
@@ -839,7 +838,7 @@ int MCD_pauseDma (int channel)
          * progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
          */
     }
-    return(MCD_OK);
+    return MCD_OK;
 }
 /************************* End of MCD_pauseDma() ********************/
 
@@ -858,7 +857,7 @@ int MCD_resumeDma (int channel)
     if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN)
         MCD_resmActions (channel);
 
-    return(MCD_OK);
+    return MCD_OK;
 }
 /************************ End of MCD_resumeDma() ********************/
 
@@ -881,7 +880,7 @@ int MCD_csumQuery (int channel, u32 *csum)
     *csum = MCD_relocBuffDesc[channel].csumResult;
     return(MCD_OK);
 #else
-    return(MCD_ERROR);
+    return MCD_ERROR;
 #endif
 }
 /*********************** End of MCD_resumeDma() *********************/

dma/dma.c

@@ -39,13 +39,8 @@
 #error "unknown machine!"
 #endif /* MACHINE_FIREBEE */
 
-// #define DBG_DMA
-#ifdef DBG_DMA
-#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
-#else
-#define dbg(format, arg...) do { ; } while (0)
-#endif /* DBG_DMA */
-#define err(format, arg...) do { xprintf("ERROR: %s(): " format, __FUNCTION__, ##arg); } while (0)
+//// #define DEBUG
+#include "debug.h"
 
 extern char _SYS_SRAM[];
 #define SYS_SRAM &_SYS_SRAM[0]
@@ -674,9 +669,6 @@ int dma_init(void)
         dma_channel[i].handler = NULL;
     }
 
-    // test
-    dma_memcpy((void *) 0x10000, (void *) 0x03e00000, 0x00100000);  /* copy one megabyte of flash to RAM */
-
     return 0;
 }
 

exe/basflash_start.c

@@ -23,20 +23,21 @@
 
 #include <bas_types.h>
 
-static uint32_t ownstack[4096];
-static uint32_t *stackptr = &ownstack[4095];
+#define STACKSIZE   16384
+static uint32_t ownstack[STACKSIZE];
+static uint32_t *stackptr = &ownstack[STACKSIZE - 1];
 
 /*
  * setup our own stack in SDRAM to prevent clashing BaS's in SRAM (size limited).
  */
 void startup(void)
 {
-	static uint32_t oldstack;
+    static uint32_t oldstack;
 
-	void basflash(void);
-	__asm__ __volatile__("move.l	sp,%0\n\t" : "=g"(oldstack) : :);
-	__asm__ __volatile__("move.l	%0,sp\n\t" : : "g"(stackptr) : );
-	basflash();
-	__asm__ __volatile__("move.l	%0,sp\n\t" : : "g"(oldstack) : "sp");
-	(void) stackptr; /* make compiler happy about unused variables */
+    void basflash(void);
+    __asm__ __volatile__("move.l	sp,%0\n\t" : "=g"(oldstack) : :);
+    __asm__ __volatile__("move.l	%0,sp\n\t" : : "g"(stackptr) : );
+    basflash();
+    __asm__ __volatile__("move.l	%0,sp\n\t" : : "g"(oldstack) : "sp");
+    (void) stackptr; /* make compiler happy about unused variables */
 }

flash/flash.c

@@ -193,6 +193,8 @@ void amd_flash_sector_erase(int n)
 {
     volatile AMD_FLASH_CELL status;
 
+    (void) num_flash_areas;     /* to make compiler happy */
+
     pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
     pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
     pFlash[0x555] = AMD_FLASH_CMD_DATA(0x80);

flash/s19reader.c

@@ -31,8 +31,12 @@
 #include "diskio.h"
 #include "ff.h"
 #include "s19reader.h"
+#include "dma.h"
 #include "cache.h"
 
+// #define DEBUG
+#include "debug.h"
+
 /*
  * Yes, I know. The following doesn't really look like code should look like...
  *
@@ -103,13 +107,13 @@ static uint32_t hex_to_long(uint8_t hex[8])
 static uint8_t checksum(uint8_t arr[])
 {
     int i;
-    uint8_t checksum = SREC_COUNT(arr);
+    uint8_t cs = SREC_COUNT(arr);
 
     for (i = 0; i < SREC_COUNT(arr) - 1; i++)
     {
-        checksum += arr[i + 2];
+        cs += arr[i + 2];
     }
-    return ~checksum;
+    return ~cs;
 }
 
 #ifdef _NOT_USED_
@@ -192,21 +196,25 @@ err_t read_srecords(char *filename, void **start_address, uint32_t *actual_lengt
     FRESULT fres;
     FIL file;
     err_t ret = OK;
+    uint32_t length = 0;
 
     if ((fres = f_open(&file, filename, FA_READ) == FR_OK))
     {
-        uint8_t line[80];
+        uint8_t line[255];
         int lineno = 0;
         int data_records = 0;
         bool found_block_header = false;
         bool found_block_end = false;
         bool found_block_data = false;
 
+        *actual_length = 0;
+
         while (ret == OK && (uint8_t *) f_gets((char *) line, sizeof(line), &file) != NULL)
         {
             lineno++;
             uint8_t vector[80];
 
+            memset(vector, 0, sizeof(vector));
             line_to_vector(line, vector);	/* vector now contains the decoded contents of line, from line[1] on */
 
             if (line[0] == 'S')
@@ -233,10 +241,11 @@ err_t read_srecords(char *filename, void **start_address, uint32_t *actual_lengt
                     case 2: /* three byte address field data record */
                         if (!found_block_header || found_block_end)
                         {
-                            xprintf("S3 record found before S0 or after S7: S-records corrupt?\r\n");
+                            xprintf("S2 record found before S0 or after S7: S-records corrupt?\r\n");
                             ret = FAIL;
                         }
                         ret = callback((uint8_t *) SREC_ADDR24(vector), SREC_DATA24(vector), SREC_DATA24_SIZE(vector));
+                        length += SREC_DATA24_SIZE(vector);
                         data_records++;
                         break;
 
@@ -246,6 +255,7 @@ err_t read_srecords(char *filename, void **start_address, uint32_t *actual_lengt
                             xprintf("S3 record found before S0 or after S7: S-records corrupt?\r\n");
                             ret = FAIL;
                         }
+                        length += SREC_DATA32_SIZE(vector);
                         ret = callback((uint8_t *) SREC_ADDR32(vector), SREC_DATA32(vector), SREC_DATA32_SIZE(vector));
                         data_records++;
                         break;
@@ -259,6 +269,7 @@ err_t read_srecords(char *filename, void **start_address, uint32_t *actual_lengt
                         {
                             // xprintf("S7 record (end) found after %d valid data blocks\r\n", data_records);
                             *start_address = (void *) SREC_ADDR32(vector);
+                            xprintf("%d blocks read. Found start address %p\r\n", data_records, *start_address);
                         }
                         break;
 
@@ -269,7 +280,7 @@ err_t read_srecords(char *filename, void **start_address, uint32_t *actual_lengt
                         }
                         else
                         {
-                            // xprintf("S7 record (end) found after %d valid data blocks\r\n", data_records);
+                            // xprintf("S8 record (end) found after %d valid data blocks\r\n", data_records);
                             *start_address = (void *) SREC_ADDR24(vector);
                         }
                         break;
@@ -296,6 +307,7 @@ err_t read_srecords(char *filename, void **start_address, uint32_t *actual_lengt
         xprintf("could not open file %s\r\n", filename);
         ret = FILE_OPEN;
     }
+    *actual_length = length;
     return ret;
 }
 
@@ -333,7 +345,11 @@ static err_t verify(uint8_t *dst, uint8_t *src, size_t length)
     do
     {
         if (*src++ != *dst++)
+        {
+            xprintf("data differs at %p (expected 0x%02x, got 0x%02x)\r\n",
+                    *(src - 1), *(dst - 1));
             return FAIL;
+        }
     } while (src < end);
 
     return OK;
@@ -342,10 +358,13 @@ static err_t verify(uint8_t *dst, uint8_t *src, size_t length)
 /*
  * needed to avoid missing type cast warning below
  */
-static inline err_t srec_memcpy(uint8_t *dst, uint8_t *src, size_t n)
+err_t srec_memcpy(uint8_t *dst, uint8_t *src, size_t n)
 {
     err_t e = OK;
 
+    xprintf(".");
+    dbg("\r\ncopy from %p to %p, length %d", src, dst, n);
+    // dma_memcpy((void *) dst, (void *) src, n);
     memcpy((void *) dst, (void *) src, n);
     return e;
 }
@@ -381,7 +400,7 @@ void srec_execute(char *flasher_filename)
                 if (err == OK)
                 {
                     /* next pass: copy data to destination */
-                    xprintf("OK.\r\ncopy/flash data: ");
+                    xprintf("OK (start address=%p, length = %ld).\r\ncopy data: ", start_address, length);
                     err = read_srecords(flasher_filename, &start_address, &length, srec_memcpy);
                     if (err == OK)
                     {
@@ -391,6 +410,7 @@ void srec_execute(char *flasher_filename)
                         if (err == OK)
                         {
                             xprintf("OK.\r\n");
+
                             typedef void void_func(void);
                             void_func *func;
                             xprintf("target successfully written and verified. Start address: %p\r\n", start_address);

flash_scripts/flash_firebee_bas.bdm

@@ -11,7 +11,7 @@ wait
 # use system sdram as flashlib scratch area.
 # TODO: plugin flashing seems to work o.k. now for smaller binaries, while it doesn't for larger ones (EmuTOS) yet.
 # This seems to be related to large flash buffers and PC-relative adressing of the plugin
-#flash-plugin 0x1000 0xf000 flash29-5475.plugin
+flash-plugin 0x1000 0xf000 flash29.plugin
 # notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
 flash 0xe0000000
 

flash_scripts/flash_m548x_etos.bdm

@@ -63,4 +63,4 @@ erase 0xe0000000 37
 erase 0xe0000000 38
 erase 0xe0000000 39
 
-load ../../emutos/emutos-m548xbas.elf
+load ../../emutos/emutos-m548x-bas.elf

flash_scripts/run_m548x_dbug.bdm

@@ -0,0 +1,55 @@
+#!/usr/local/bin/bdmctrl -D2 -v9 -d9
+#
+# firebee board initialization for bdmctrl 
+#
+open $1
+reset
+sleep 1
+
+wait
+
+# set VBR
+write-ctrl 0x0801 0x00000000
+dump-register VBR
+
+# Turn on MBAR at 0x1000_0000
+write-ctrl 0x0C0F 0x10000000
+dump-register MBAR
+
+# Turn on RAMBAR0 at address 20000000 
+write-ctrl 0x0C04 0x20000021
+
+# Turn on RAMBAR1 at address 20001000
+write-ctrl 0x0C05 0x20001021
+
+# Init CS0 (BootFLASH @ ff80_0000 - ff8F_FFFF 8Mbytes)
+write 0x10000500 0xff800000 4
+write 0x10000508 0x00041180 4
+write 0x10000504 0x003F0001 4
+wait
+
+# SDRAM Initialization @ 0000_0000 - 03FF_FFFF 64 MBytes
+write 0x10000004 0x000002AA 4	# SDRAMDS configuration
+write 0x10000020 0x00000019 4	# SDRAM CS0 configuration (64Mbytes 0000_0000 - 03FF_FFFF)
+write 0x10000024 0x00000000 4	# SDRAM CS1 configuration
+write 0x10000028 0x00000000 4	# SDRAM CS2 configuration
+write 0x1000002C 0x00000000 4	# SDRAM CS3 configuration
+
+write 0x10000108 0x73711630 4	# SDCFG1
+write 0x1000010C 0x46370000 4	# SDCFG2
+
+write 0x10000104 0xE10B0002 4	# SDCR + IPALL
+write 0x10000100 0x40010000 4	# SDMR (write to LEMR)
+write 0x10000100 0x058D0000 4	# SDMR (write to LMR)
+sleep 100
+write 0x10000104 0xE10D0002 4	# SDCR + IPALL
+write 0x10000104 0xE10D0004 4	# SDCR + IREF (first refresh)
+write 0x10000104 0xE10D0004 4	# SDCR + IREF (first refresh)
+write 0x10000100 0x018D0000 4	# SDMR (write to LMR)
+write 0x10000104 0x710D0F00 4	# SDCR (lock SDMR and enable refresh)
+sleep 100
+
+load m548xlite_dbug_ram.elf
+
+execute
+wait

include/bas_printf.h

@@ -21,15 +21,24 @@
 #define _BAS_PRINTF_H_
 #include <stdarg.h>
 #include <stddef.h>
+#include "MCF5475.h"
 
 extern void xvsnprintf(char *str, size_t size, const char *fmt, va_list va);
 extern void xvprintf(const char *fmt, va_list va);
 extern void xprintf(const char *fmt, ...);
 extern void xsnprintf(char *str, size_t size, const char *fmt, ...);
-extern void xputchar(int c);
 extern int sprintf(char *str, const char *format, ...);
 
 
 extern void display_progress(void);
 extern void hexdump(uint8_t buffer[], int size);
+
+static inline void xputchar(int c)
+{
+    while (!(MCF_PSC0_PSCSR & MCF_PSC_PSCSR_TXRDY))
+        ;
+
+    MCF_PSC0_PSCTB_8BIT = (uint8_t) c;
+}
+
 #endif /* _BAS_PRINTF_H_ */

include/bas_string.h

@@ -34,6 +34,7 @@ extern char *strcat(char *dst, const char *src);
 extern char *strncat(char *dst, const char *src, size_t max);
 extern int atoi(const char *c);
 extern void *memcpy(void *dst, const void *src, size_t n);
+extern void *memmove(void *dst, const void *src, size_t n);
 extern void *memset(void *s, int c, size_t n);
 extern int memcmp(const void *s1, const void *s2, size_t max);
 extern void bzero(void *s, size_t n);

include/bas_utils.h

@@ -26,4 +26,7 @@
 #define CLEAR_BIT(p,bit)        p &= ~(bit)
 #define CLEAR_BIT_NO(p,nr)      CLEAR_BIT(p, (1 << (nr)))
 
+extern void write_pic_byte(uint8_t value);
+extern uint8_t read_pic_byte(void);
+
 #endif /* _BAS_UTILS_H_ */

include/conout.h

@@ -0,0 +1,63 @@
+#ifndef __CONOUT_H__
+#define __CONOUT_H__
+
+#include "bas_types.h"
+
+/*
+ * conout.h - lowlevel color model dependent screen handling routines
+ *
+ *
+ * Copyright (C) 2004-2016 by Authors:
+ *
+ * Authors:
+ *  MAD     Martin Doering
+ *
+ * This file is distributed under the GPL, version 2 or at your
+ * option any later version.  See doc/license.txt for details.
+ */
+
+
+
+/* Defines for cursor */
+#define  M_CFLASH       0x0001  /* cursor flash         0:disabled 1:enabled */
+#define  M_CSTATE       0x0002  /* cursor flash state   0:off 1:on */
+#define  M_CVIS         0x0004  /* cursor visibility    0:invisible 1:visible */
+
+/*
+ * The visibility flag is also used as a semaphore to prevent
+ * the interrupt-driven cursor blink logic from colliding with
+ * escape function/sequence cursor drawing activity.
+ */
+
+#define  M_CEOL         0x0008  /* end of line handling 0:overwrite 1:wrap */
+#define  M_REVID        0x0010  /* reverse video        0:on        1:off */
+#define  M_SVPOS        0x0020  /* position saved flag. 0:false,    1:true */
+#define  M_CRIT         0x0040  /* reverse video        0:on        1:off */
+
+/* Color related linea variables */
+
+extern int16_t v_col_bg;           /* current background color */
+extern int16_t v_col_fg;           /* current foreground color */
+
+/* Cursor related linea variables */
+
+extern uint8_t *v_cur_ad;         /* current cursor address */
+extern int16_t v_cur_of;           /* cursor offset */
+extern int8_t v_cur_tim;          /* cursor blink timer */
+
+extern int8_t v_period;
+extern int16_t disab_cnt;          /* disable depth count. (>0 means disabled) */
+extern int8_t v_stat_0;           /* video cell system status */
+extern int16_t sav_cur_x;          /* saved cursor cell x */
+extern int16_t sav_cur_y;          /* saved cursor cell y */
+
+/* Prototypes */
+
+extern void ascii_out(int);
+extern void move_cursor(int, int);
+extern void blank_out (int, int, int, int);
+extern void invert_cell(int, int);
+extern void scroll_up(int);
+extern void scroll_down(int);
+
+#endif /* __CONOUT_H__ */

include/debug.h

@@ -0,0 +1,16 @@
+#ifndef DEBUG_H
+// #define DEBUG_H
+
+#ifdef DEBUG
+#include "bas_types.h"
+#include "bas_printf.h"
+
+#define dbg(format, arg...) do { xprintf("DEBUG (%s()): " format, __FUNCTION__, ##arg);} while(0)
+#else
+#define dbg(format, arg...) do {;} while (0)
+#endif /* DEBUG */
+#define err(format, arg...) do { xprintf("ERROR (%s()): " format, __FUNCTION__, ##arg); } while(0)
+#define inf(format, arg...) do { xprintf("" format, ##arg); } while(0)
+
+#endif // DEBUG_H
+

include/driver_vec.h

@@ -81,128 +81,7 @@ struct xhdi_driver_interface
     uint32_t (*xhdivec)();
 };
 
-/*
- * Interpretation of offset for color fields: All offsets are from the right,
- * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you
- * can use the offset as right argument to <<). A pixel afterwards is a bit
- * stream and is written to video memory as that unmodified. This implies
- * big-endian byte order if bits_per_pixel is greater than 8.
- */
-struct fb_bitfield
-{
-    unsigned long offset;           /* beginning of bitfield    */
-    unsigned long length;           /* length of bitfield       */
-    unsigned long msb_right;        /* != 0 : Most significant bit is */
-    /* right */
-};
-
-/*
- * the following structures define the interface to the BaS-builtin-framebuffer video driver
- */
-struct fb_var_screeninfo
-{
-    unsigned long xres;             /* visible resolution       */
-    unsigned long yres;
-    unsigned long xres_virtual;     /* virtual resolution       */
-    unsigned long yres_virtual;
-    unsigned long xoffset;          /* offset from virtual to visible */
-    unsigned long yoffset;          /* resolution           */
-
-    unsigned long bits_per_pixel;   /* guess what           */
-    unsigned long grayscale;        /* != 0 Graylevels instead of colors */
-
-    struct fb_bitfield red;         /* bitfield in fb mem if true color, */
-    struct fb_bitfield green;       /* else only length is significant */
-    struct fb_bitfield blue;
-    struct fb_bitfield transp;      /* transparency         */
-
-    unsigned long nonstd;           /* != 0 Non standard pixel format */
-
-    unsigned long activate;         /* see FB_ACTIVATE_*        */
-
-    unsigned long height;           /* height of picture in mm    */
-    unsigned long width;            /* width of picture in mm     */
-
-    unsigned long accel_flags;      /* (OBSOLETE) see fb_info.flags */
-
-    /* Timing: All values in pixclocks, except pixclock (of course) */
-    unsigned long pixclock;         /* pixel clock in ps (pico seconds) */
-    unsigned long left_margin;      /* time from sync to picture    */
-    unsigned long right_margin;     /* time from picture to sync    */
-    unsigned long upper_margin;     /* time from sync to picture    */
-    unsigned long lower_margin;
-    unsigned long hsync_len;        /* length of horizontal sync    */
-    unsigned long vsync_len;        /* length of vertical sync  */
-    unsigned long sync;             /* see FB_SYNC_*        */
-    unsigned long vmode;            /* see FB_VMODE_*       */
-    unsigned long rotate;           /* angle we rotate counter clockwise */
-    unsigned long refresh;
-    unsigned long reserved[4];      /* Reserved for future compatibility */
-};
-
-struct fb_fix_screeninfo
-{
-    char id[16];                    /* identification string eg "TT Builtin" */
-    unsigned long smem_start;       /* Start of frame buffer mem */
-    /* (physical address) */
-    unsigned long smem_len;         /* Length of frame buffer mem */
-    unsigned long type;             /* see FB_TYPE_*        */
-    unsigned long type_aux;         /* Interleave for interleaved Planes */
-    unsigned long visual;           /* see FB_VISUAL_*      */
-    unsigned short xpanstep;        /* zero if no hardware panning  */
-    unsigned short ypanstep;        /* zero if no hardware panning  */
-    unsigned short ywrapstep;       /* zero if no hardware ywrap    */
-    unsigned long line_length;      /* length of a line in bytes    */
-    unsigned long mmio_start;       /* Start of Memory Mapped I/O   */
-    /* (physical address) */
-    unsigned long mmio_len;         /* Length of Memory Mapped I/O  */
-    unsigned long accel;            /* Indicate to driver which */
-    /*  specific chip/card we have  */
-    unsigned short reserved[3];     /* Reserved for future compatibility */
-};
-
-struct fb_chroma
-{
-    unsigned long redx;             /* in fraction of 1024 */
-    unsigned long greenx;
-    unsigned long bluex;
-    unsigned long whitex;
-    unsigned long redy;
-    unsigned long greeny;
-    unsigned long bluey;
-    unsigned long whitey;
-};
-
-struct fb_monspecs
-{
-    struct fb_chroma chroma;
-    struct fb_videomode *modedb;    /* mode database */
-    unsigned char  manufacturer[4]; /* Manufacturer */
-    unsigned char  monitor[14];     /* Monitor String */
-    unsigned char  serial_no[14];   /* Serial Number */
-    unsigned char  ascii[14];       /* ? */
-    unsigned long modedb_len;       /* mode database length */
-    unsigned long model;            /* Monitor Model */
-    unsigned long serial;           /* Serial Number - Integer */
-    unsigned long year;             /* Year manufactured */
-    unsigned long week;             /* Week Manufactured */
-    unsigned long hfmin;            /* hfreq lower limit (Hz) */
-    unsigned long hfmax;            /* hfreq upper limit (Hz) */
-    unsigned long dclkmin;          /* pixelclock lower limit (Hz) */
-    unsigned long dclkmax;          /* pixelclock upper limit (Hz) */
-    unsigned short input;           /* display type - see FB_DISP_* */
-    unsigned short dpms;            /* DPMS support - see FB_DPMS_ */
-    unsigned short signal;          /* Signal Type - see FB_SIGNAL_* */
-    unsigned short vfmin;           /* vfreq lower limit (Hz) */
-    unsigned short vfmax;           /* vfreq upper limit (Hz) */
-    unsigned short gamma;           /* Gamma - in fractions of 100 */
-    unsigned short gtf  : 1;        /* supports GTF */
-    unsigned short misc;            /* Misc flags - see FB_MISC_* */
-    unsigned char  version;         /* EDID version... */
-    unsigned char  revision;        /* ...and revision */
-    unsigned char  max_x;           /* Maximum horizontal size (cm) */
-    unsigned char  max_y;           /* Maximum vertical size (cm) */
-};
+#include "fb.h"
 
 struct framebuffer_driver_interface
 {
@@ -265,9 +144,9 @@ struct pci_bios_interface
 
 struct mmu_driver_interface
 {
-    int32_t (*map_page_locked)(uint32_t address, uint32_t length, int asid);
-    int32_t (*unlock_page)(uint32_t address, uint32_t length, int asid);
-    int32_t (*report_locked_pages)(uint32_t *num_itlb, uint32_t *num_dtlb);
+    uint32_t (*map_page_locked)(uint32_t address, uint32_t length, int asid);
+    uint32_t (*unlock_page)(uint32_t address, uint32_t length, int asid);
+    uint32_t (*report_locked_pages)(uint32_t *num_itlb, uint32_t *num_dtlb);
     uint32_t (*report_pagesize)(void);
 };
 

include/exceptions.h

@@ -3,26 +3,6 @@
 
 #include <bas_types.h>
 
-static inline uint32_t set_ipl(uint32_t ipl)
-{
-	uint32_t ret;
-
-	__asm__ __volatile__(
-		"		move.w	sr,%[ret]\r\n"			/* retrieve status register */
-		"		andi.l	#0x07,%[ipl]\n\t"		/* mask out ipl bits on new value */
-		"		lsl.l	#8,%[ipl]\n\t"			/* shift them to position */
-		"		move.l	%[ret],d0\n\t"			/* retrieve original value */
-		"		andi.l	#0x0000f8ff,d0\n\t"		/* clear ipl part */
-		"		or.l	%[ipl],d0\n\t"			/* or in new value */
-		"		move.w	d0,sr\n\t"				/* put it in place */
-		"		andi.l	#0x0700,%[ret]\r\n"		/* mask out ipl bits */
-		"		lsr.l	#8,%[ret]\r\n"			/* shift them to position */
-		: [ret] "=&d" (ret)		/* output */
-		: [ipl] "d" (ipl)		/* input */
-		: "cc", "d0"	/* clobber */
-	);
-
-	return ret;
-}
+extern uint32_t set_ipl(uint32_t ipl);
 
 #endif /* _EXCEPTIONS_H_ */

include/fb.h

@@ -1,196 +1,206 @@
 #ifndef _FB_H
 #define _FB_H
 
-/* Definitions of frame buffers						*/
+#include "bas_types.h"
 
-#define FB_MAJOR		29
-#define FB_MAX			32	/* sufficient for now */
+/* Definitions of frame buffers	*/
 
-/* ioctls
-   0x46 is 'F'								*/
-#define FBIOGET_VSCREENINFO	0x4600
-#define FBIOPUT_VSCREENINFO	0x4601
-#define FBIOGET_FSCREENINFO	0x4602
-#define FBIOPAN_DISPLAY     0x4606
-#define FBIOBLANK		        0x4611		/* arg: 0 or vesa level + 1 */
-#define FBIO_ALLOC          0x4613
-#define FBIO_FREE           0x4614
+#define FB_MAJOR                29
+#define FB_MAX                  32	/* sufficient for now */
+
+/* ioctls 0x46 is 'F' */
+#define FBIOGET_VSCREENINFO     0x4600
+#define FBIOPUT_VSCREENINFO     0x4601
+#define FBIOGET_FSCREENINFO     0x4602
+#define FBIOPAN_DISPLAY         0x4606
+#define FBIOBLANK               0x4611      /* arg: 0 or vesa level + 1 */
+#define FBIO_ALLOC              0x4613
+#define FBIO_FREE               0x4614
 
 /* picture format */
-#define PICT_FORMAT(bpp,type,a,r,g,b)	(((bpp) << 24) | ((type) << 16) | ((a) << 12) | ((r) << 8) | ((g) << 4) | ((b)))
+#define PICT_FORMAT(bpp, type, a, r, g, b)  (((bpp) << 24) | ((type) << 16) | ((a) << 12) | ((r) << 8) | ((g) << 4) | ((b)))
+
 /* gray/color formats use a visual index instead of argb */
-#define PICT_VISFORMAT(bpp,type,vi)	(((bpp) << 24) | ((type) << 16) | ((vi)))
-#define PICT_FORMAT_BPP(f)	(((f) >> 24)       )
-#define PICT_FORMAT_TYPE(f)	(((f) >> 16) & 0xff)
-#define PICT_FORMAT_A(f)	(((f) >> 12) & 0x0f)
-#define PICT_FORMAT_R(f)	(((f) >>  8) & 0x0f)
-#define PICT_FORMAT_G(f)	(((f) >>  4) & 0x0f)
-#define PICT_FORMAT_B(f)	(((f)      ) & 0x0f)
-#define PICT_FORMAT_RGB(f)	(((f)      ) & 0xfff)
-#define PICT_FORMAT_VIS(f)	(((f)      ) & 0xffff)
-#define PICT_TYPE_OTHER	0
-#define PICT_TYPE_A	1
-#define PICT_TYPE_ARGB	2
-#define PICT_TYPE_ABGR	3
-#define PICT_TYPE_COLOR	4
-#define PICT_TYPE_GRAY	5
-#define PICT_FORMAT_COLOR(f)	(PICT_FORMAT_TYPE(f) & 2)
+#define PICT_VISFORMAT(bpp, type, vi)   (((bpp) << 24) | ((type) << 16) | ((vi)))
+#define PICT_FORMAT_BPP(f)              (((f) >> 24)       )
+#define PICT_FORMAT_TYPE(f)             (((f) >> 16) & 0xff)
+#define PICT_FORMAT_A(f)                (((f) >> 12) & 0x0f)
+#define PICT_FORMAT_R(f)                (((f) >>  8) & 0x0f)
+#define PICT_FORMAT_G(f)                (((f) >>  4) & 0x0f)
+#define PICT_FORMAT_B(f)                (((f)      ) & 0x0f)
+#define PICT_FORMAT_RGB(f)              (((f)      ) & 0xfff)
+#define PICT_FORMAT_VIS(f)              (((f)      ) & 0xffff)
+
+#define PICT_TYPE_OTHER         0
+#define PICT_TYPE_A             1
+#define PICT_TYPE_ARGB          2
+#define PICT_TYPE_ABGR          3
+#define PICT_TYPE_COLOR         4
+#define PICT_TYPE_GRAY          5
+#define PICT_FORMAT_COLOR(f)    (PICT_FORMAT_TYPE(f) & 2)
+
 /* 32bpp formats */
-#define PICT_a8r8g8b8	PICT_FORMAT(32,PICT_TYPE_ARGB,8,8,8,8)
-#define PICT_x8r8g8b8	PICT_FORMAT(32,PICT_TYPE_ARGB,0,8,8,8)
-#define PICT_a8b8g8r8	PICT_FORMAT(32,PICT_TYPE_ABGR,8,8,8,8)
-#define PICT_x8b8g8r8	PICT_FORMAT(32,PICT_TYPE_ABGR,0,8,8,8)
+#define PICT_a8r8g8b8           PICT_FORMAT(32, PICT_TYPE_ARGB, 8, 8, 8, 8)
+#define PICT_x8r8g8b8           PICT_FORMAT(32, PICT_TYPE_ARGB, 0, 8, 8, 8)
+#define PICT_a8b8g8r8           PICT_FORMAT(32, PICT_TYPE_ABGR, 8, 8, 8, 8)
+#define PICT_x8b8g8r8           PICT_FORMAT(32, PICT_TYPE_ABGR, 0, 8, 8, 8)
+
 /* 24bpp formats */
-#define PICT_r8g8b8	PICT_FORMAT(24,PICT_TYPE_ARGB,0,8,8,8)
-#define PICT_b8g8r8	PICT_FORMAT(24,PICT_TYPE_ABGR,0,8,8,8)
+#define PICT_r8g8b8             PICT_FORMAT(24, PICT_TYPE_ARGB, 0, 8, 8, 8)
+#define PICT_b8g8r8             PICT_FORMAT(24, PICT_TYPE_ABGR, 0, 8, 8, 8)
+
 /* 16bpp formats */
-#define PICT_r5g6b5	PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,6,5)
-#define PICT_b5g6r5	PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,6,5)
-#define PICT_a1r5g5b5	PICT_FORMAT(16,PICT_TYPE_ARGB,1,5,5,5)
-#define PICT_x1r5g5b5	PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,5,5)
-#define PICT_a1b5g5r5	PICT_FORMAT(16,PICT_TYPE_ABGR,1,5,5,5)
-#define PICT_x1b5g5r5	PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,5,5)
-#define PICT_a4r4g4b4	PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4)
-#define PICT_x4r4g4b4	PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4)
-#define PICT_a4b4g4r4	PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4)
-#define PICT_x4b4g4r4	PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4)
+#define PICT_r5g6b5             PICT_FORMAT(16, PICT_TYPE_ARGB, 0, 5, 6, 5)
+#define PICT_b5g6r5             PICT_FORMAT(16, PICT_TYPE_ABGR, 0, 5, 6, 5)
+#define PICT_a1r5g5b5           PICT_FORMAT(16, PICT_TYPE_ARGB, 1, 5, 5, 5)
+#define PICT_x1r5g5b5           PICT_FORMAT(16, PICT_TYPE_ARGB, 0, 5, 5, 5)
+#define PICT_a1b5g5r5           PICT_FORMAT(16, PICT_TYPE_ABGR, 1, 5, 5, 5)
+#define PICT_x1b5g5r5           PICT_FORMAT(16, PICT_TYPE_ABGR, 0, 5, 5, 5)
+#define PICT_a4r4g4b4           PICT_FORMAT(16, PICT_TYPE_ARGB, 4, 4, 4, 4)
+#define PICT_x4r4g4b4           PICT_FORMAT(16, PICT_TYPE_ARGB, 4, 4, 4, 4)
+#define PICT_a4b4g4r4           PICT_FORMAT(16, PICT_TYPE_ARGB, 4, 4, 4, 4)
+#define PICT_x4b4g4r4           PICT_FORMAT(16, PICT_TYPE_ARGB, 4, 4, 4, 4)
+
 /* 8bpp formats */
-#define PICT_a8 PICT_FORMAT(8,PICT_TYPE_A,8,0,0,0)
-#define PICT_r3g3b2	PICT_FORMAT(8,PICT_TYPE_ARGB,0,3,3,2)
-#define PICT_b2g3r3	PICT_FORMAT(8,PICT_TYPE_ABGR,0,3,3,2)
-#define PICT_a2r2g2b2 PICT_FORMAT(8,PICT_TYPE_ARGB,2,2,2,2)
-#define PICT_a2b2g2r2 PICT_FORMAT(8,PICT_TYPE_ABGR,2,2,2,2)
-#define PICT_c8 PICT_FORMAT(8,PICT_TYPE_COLOR,0,0,0,0)
-#define PICT_g8 PICT_FORMAT(8,PICT_TYPE_GRAY,0,0,0,0)
+#define PICT_a8                 PICT_FORMAT(8, PICT_TYPE_A, 8, 0, 0, 0)
+#define PICT_r3g3b2             PICT_FORMAT(8, PICT_TYPE_ARGB, 0, 3, 3, 2)
+#define PICT_b2g3r3             PICT_FORMAT(8, PICT_TYPE_ABGR, 0, 3, 3, 2)
+#define PICT_a2r2g2b2           PICT_FORMAT(8, PICT_TYPE_ARGB, 2, 2, 2, 2)
+#define PICT_a2b2g2r2           PICT_FORMAT(8, PICT_TYPE_ABGR, 2, 2, 2, 2)
+#define PICT_c8                 PICT_FORMAT(8, PICT_TYPE_COLOR, 0, 0, 0, 0)
+#define PICT_g8                 PICT_FORMAT(8, PICT_TYPE_GRAY, 0, 0, 0, 0)
 
 /* fVDI */
-#define MODE_EMUL_MONO_FLAG 1
-#define MODE_VESA_FLAG 2 /* for modedb.c */
-struct mode_option {
-	short used; /* Whether the mode option was used or not. */
-	short width;
-	short height;
-	short bpp;
-	short freq;
-	short flags;
+#define MODE_EMUL_MONO_FLAG     1
+#define MODE_VESA_FLAG          2   /* for modedb.c */
+
+struct mode_option
+{
+    short used; /* Whether the mode option was used or not. */
+    short width;
+    short height;
+    short bpp;
+    short freq;
+    short flags;
 };
 
 extern struct mode_option resolution; /* fVDI */
 
-#define FB_TYPE_PACKED_PIXELS		0	/* Packed Pixels	*/
-#define FB_TYPE_PLANES			1	/* Non interleaved planes */
-#define FB_TYPE_INTERLEAVED_PLANES	2	/* Interleaved planes	*/
-#define FB_TYPE_TEXT			3	/* Text/attributes	*/
-#define FB_TYPE_VGA_PLANES		4	/* EGA/VGA planes	*/
+#define FB_TYPE_PACKED_PIXELS       0	/* Packed Pixels	*/
+#define FB_TYPE_PLANES              1	/* Non interleaved planes */
+#define FB_TYPE_INTERLEAVED_PLANES  2	/* Interleaved planes	*/
+#define FB_TYPE_TEXT                3	/* Text/attributes	*/
+#define FB_TYPE_VGA_PLANES          4	/* EGA/VGA planes	*/
 
-#define FB_AUX_TEXT_MDA		0	/* Monochrome text */
-#define FB_AUX_TEXT_CGA		1	/* CGA/EGA/VGA Color text */
-#define FB_AUX_TEXT_S3_MMIO	2	/* S3 MMIO fasttext */
-#define FB_AUX_TEXT_MGA_STEP16	3	/* MGA Millenium I: text, attr, 14 reserved bytes */
-#define FB_AUX_TEXT_MGA_STEP8	4	/* other MGAs:      text, attr,  6 reserved bytes */
+#define FB_AUX_TEXT_MDA             0	/* Monochrome text */
+#define FB_AUX_TEXT_CGA             1	/* CGA/EGA/VGA Color text */
+#define FB_AUX_TEXT_S3_MMIO         2	/* S3 MMIO fasttext */
+#define FB_AUX_TEXT_MGA_STEP16      3	/* MGA Millenium I: text, attr, 14 reserved bytes */
+#define FB_AUX_TEXT_MGA_STEP8       4	/* other MGAs:      text, attr,  6 reserved bytes */
 
-#define FB_AUX_VGA_PLANES_VGA4		0	/* 16 color planes (EGA/VGA) */
-#define FB_AUX_VGA_PLANES_CFB4		1	/* CFB4 in planes (VGA) */
-#define FB_AUX_VGA_PLANES_CFB8		2	/* CFB8 in planes (VGA) */
+#define FB_AUX_VGA_PLANES_VGA4      0	/* 16 color planes (EGA/VGA) */
+#define FB_AUX_VGA_PLANES_CFB4      1	/* CFB4 in planes (VGA) */
+#define FB_AUX_VGA_PLANES_CFB8      2	/* CFB8 in planes (VGA) */
 
-#define FB_VISUAL_MONO01		0	/* Monochr. 1=Black 0=White */
-#define FB_VISUAL_MONO10		1	/* Monochr. 1=White 0=Black */
-#define FB_VISUAL_TRUECOLOR		2	/* True color	*/
-#define FB_VISUAL_PSEUDOCOLOR		3	/* Pseudo color (like atari) */
-#define FB_VISUAL_DIRECTCOLOR		4	/* Direct color */
-#define FB_VISUAL_STATIC_PSEUDOCOLOR	5	/* Pseudo color readonly */
+#define FB_VISUAL_MONO01            0	/* Monochr. 1=Black 0=White */
+#define FB_VISUAL_MONO10            1	/* Monochr. 1=White 0=Black */
+#define FB_VISUAL_TRUECOLOR         2	/* True color	*/
+#define FB_VISUAL_PSEUDOCOLOR       3	/* Pseudo color (like atari) */
+#define FB_VISUAL_DIRECTCOLOR       4	/* Direct color */
+#define FB_VISUAL_STATIC_PSEUDOCOLOR    5	/* Pseudo color readonly */
 
-#define FB_ACCEL_NONE		0	/* no hardware accelerator	*/
-#define FB_ACCEL_ATARIBLITT	1	/* Atari Blitter		*/
-#define FB_ACCEL_AMIGABLITT	2	/* Amiga Blitter                */
-#define FB_ACCEL_S3_TRIO64	3	/* Cybervision64 (S3 Trio64)    */
-#define FB_ACCEL_NCR_77C32BLT	4	/* RetinaZ3 (NCR 77C32BLT)      */
-#define FB_ACCEL_S3_VIRGE	5	/* Cybervision64/3D (S3 ViRGE)	*/
-#define FB_ACCEL_ATI_MACH64GX	6	/* ATI Mach 64GX family		*/
-#define FB_ACCEL_DEC_TGA	7	/* DEC 21030 TGA		*/
-#define FB_ACCEL_ATI_MACH64CT	8	/* ATI Mach 64CT family		*/
-#define FB_ACCEL_ATI_MACH64VT	9	/* ATI Mach 64CT family VT class */
-#define FB_ACCEL_ATI_MACH64GT	10	/* ATI Mach 64CT family GT class */
-#define FB_ACCEL_SUN_CREATOR	11	/* Sun Creator/Creator3D	*/
-#define FB_ACCEL_SUN_CGSIX	12	/* Sun cg6			*/
-#define FB_ACCEL_SUN_LEO	13	/* Sun leo/zx			*/
-#define FB_ACCEL_IMS_TWINTURBO	14	/* IMS Twin Turbo		*/
-#define FB_ACCEL_3DLABS_PERMEDIA2 15	/* 3Dlabs Permedia 2		*/
-#define FB_ACCEL_MATROX_MGA2064W 16	/* Matrox MGA2064W (Millenium)	*/
-#define FB_ACCEL_MATROX_MGA1064SG 17	/* Matrox MGA1064SG (Mystique)	*/
-#define FB_ACCEL_MATROX_MGA2164W 18	/* Matrox MGA2164W (Millenium II) */
-#define FB_ACCEL_MATROX_MGA2164W_AGP 19	/* Matrox MGA2164W (Millenium II) */
-#define FB_ACCEL_MATROX_MGAG100	20	/* Matrox G100 (Productiva G100) */
-#define FB_ACCEL_MATROX_MGAG200	21	/* Matrox G200 (Myst, Mill, ...) */
-#define FB_ACCEL_SUN_CG14	22	/* Sun cgfourteen		 */
-#define FB_ACCEL_SUN_BWTWO	23	/* Sun bwtwo			*/
-#define FB_ACCEL_SUN_CGTHREE	24	/* Sun cgthree			*/
-#define FB_ACCEL_SUN_TCX	25	/* Sun tcx			*/
-#define FB_ACCEL_MATROX_MGAG400	26	/* Matrox G400			*/
-#define FB_ACCEL_NV3		27	/* nVidia RIVA 128              */
-#define FB_ACCEL_NV4		28	/* nVidia RIVA TNT		*/
-#define FB_ACCEL_NV5		29	/* nVidia RIVA TNT2		*/
-#define FB_ACCEL_CT_6555x	30	/* C&T 6555x			*/
-#define FB_ACCEL_3DFX_BANSHEE	31	/* 3Dfx Banshee			*/
-#define FB_ACCEL_ATI_RAGE128	32	/* ATI Rage128 family		*/
-#define FB_ACCEL_IGS_CYBER2000	33	/* CyberPro 2000		*/
-#define FB_ACCEL_IGS_CYBER2010	34	/* CyberPro 2010		*/
-#define FB_ACCEL_IGS_CYBER5000	35	/* CyberPro 5000		*/
-#define FB_ACCEL_SIS_GLAMOUR    36	/* SiS 300/630/540              */
-#define FB_ACCEL_3DLABS_PERMEDIA3 37	/* 3Dlabs Permedia 3		*/
-#define FB_ACCEL_ATI_RADEON	38	/* ATI Radeon family		*/
-#define FB_ACCEL_I810           39      /* Intel 810/815                */
-#define FB_ACCEL_SIS_GLAMOUR_2  40	/* SiS 315, 650, 740		*/
-#define FB_ACCEL_SIS_XABRE      41	/* SiS 330 ("Xabre")		*/
-#define FB_ACCEL_I830           42      /* Intel 830M/845G/85x/865G     */
-#define FB_ACCEL_NV_10          43      /* nVidia Arch 10               */
-#define FB_ACCEL_NV_20          44      /* nVidia Arch 20               */
-#define FB_ACCEL_NV_30          45      /* nVidia Arch 30               */
-#define FB_ACCEL_NV_40          46      /* nVidia Arch 40               */
-#define FB_ACCEL_NEOMAGIC_NM2070 90	/* NeoMagic NM2070              */
-#define FB_ACCEL_NEOMAGIC_NM2090 91	/* NeoMagic NM2090              */
-#define FB_ACCEL_NEOMAGIC_NM2093 92	/* NeoMagic NM2093              */
-#define FB_ACCEL_NEOMAGIC_NM2097 93	/* NeoMagic NM2097              */
-#define FB_ACCEL_NEOMAGIC_NM2160 94	/* NeoMagic NM2160              */
-#define FB_ACCEL_NEOMAGIC_NM2200 95	/* NeoMagic NM2200              */
-#define FB_ACCEL_NEOMAGIC_NM2230 96	/* NeoMagic NM2230              */
-#define FB_ACCEL_NEOMAGIC_NM2360 97	/* NeoMagic NM2360              */
-#define FB_ACCEL_NEOMAGIC_NM2380 98	/* NeoMagic NM2380              */
+#define FB_ACCEL_NONE               0	/* no hardware accelerator	*/
+#define FB_ACCEL_ATARIBLITT         1	/* Atari Blitter		*/
+#define FB_ACCEL_AMIGABLITT         2	/* Amiga Blitter                */
+#define FB_ACCEL_S3_TRIO64          3	/* Cybervision64 (S3 Trio64)    */
+#define FB_ACCEL_NCR_77C32BLT       4	/* RetinaZ3 (NCR 77C32BLT)      */
+#define FB_ACCEL_S3_VIRGE           5	/* Cybervision64/3D (S3 ViRGE)	*/
+#define FB_ACCEL_ATI_MACH64GX       6	/* ATI Mach 64GX family		*/
+#define FB_ACCEL_DEC_TGA            7	/* DEC 21030 TGA		*/
+#define FB_ACCEL_ATI_MACH64CT       8	/* ATI Mach 64CT family		*/
+#define FB_ACCEL_ATI_MACH64VT       9	/* ATI Mach 64CT family VT class */
+#define FB_ACCEL_ATI_MACH64GT       10	/* ATI Mach 64CT family GT class */
+#define FB_ACCEL_SUN_CREATOR        11	/* Sun Creator/Creator3D	*/
+#define FB_ACCEL_SUN_CGSIX          12	/* Sun cg6			*/
+#define FB_ACCEL_SUN_LEO            13	/* Sun leo/zx			*/
+#define FB_ACCEL_IMS_TWINTURBO      14	/* IMS Twin Turbo		*/
+#define FB_ACCEL_3DLABS_PERMEDIA2   15	/* 3Dlabs Permedia 2		*/
+#define FB_ACCEL_MATROX_MGA2064W    16	/* Matrox MGA2064W (Millenium)	*/
+#define FB_ACCEL_MATROX_MGA1064SG   17	/* Matrox MGA1064SG (Mystique)	*/
+#define FB_ACCEL_MATROX_MGA2164W    18	/* Matrox MGA2164W (Millenium II) */
+#define FB_ACCEL_MATROX_MGA2164W_AGP    19	/* Matrox MGA2164W (Millenium II) */
+#define FB_ACCEL_MATROX_MGAG100     20	/* Matrox G100 (Productiva G100) */
+#define FB_ACCEL_MATROX_MGAG200     21	/* Matrox G200 (Myst, Mill, ...) */
+#define FB_ACCEL_SUN_CG14           22	/* Sun cgfourteen		 */
+#define FB_ACCEL_SUN_BWTWO          23	/* Sun bwtwo			*/
+#define FB_ACCEL_SUN_CGTHREE        24	/* Sun cgthree			*/
+#define FB_ACCEL_SUN_TCX            25	/* Sun tcx			*/
+#define FB_ACCEL_MATROX_MGAG400     26	/* Matrox G400			*/
+#define FB_ACCEL_NV3                27	/* nVidia RIVA 128              */
+#define FB_ACCEL_NV4                28	/* nVidia RIVA TNT		*/
+#define FB_ACCEL_NV5                29	/* nVidia RIVA TNT2		*/
+#define FB_ACCEL_CT_6555x           30	/* C&T 6555x			*/
+#define FB_ACCEL_3DFX_BANSHEE       31	/* 3Dfx Banshee			*/
+#define FB_ACCEL_ATI_RAGE128        32	/* ATI Rage128 family		*/
+#define FB_ACCEL_IGS_CYBER2000      33	/* CyberPro 2000		*/
+#define FB_ACCEL_IGS_CYBER2010      34	/* CyberPro 2010		*/
+#define FB_ACCEL_IGS_CYBER5000      35	/* CyberPro 5000		*/
+#define FB_ACCEL_SIS_GLAMOUR        36	/* SiS 300/630/540              */
+#define FB_ACCEL_3DLABS_PERMEDIA3   37	/* 3Dlabs Permedia 3		*/
+#define FB_ACCEL_ATI_RADEON         38	/* ATI Radeon family		*/
+#define FB_ACCEL_I810               39      /* Intel 810/815                */
+#define FB_ACCEL_SIS_GLAMOUR_2      40	/* SiS 315, 650, 740		*/
+#define FB_ACCEL_SIS_XABRE          41	/* SiS 330 ("Xabre")		*/
+#define FB_ACCEL_I830               42      /* Intel 830M/845G/85x/865G     */
+#define FB_ACCEL_NV_10              43      /* nVidia Arch 10               */
+#define FB_ACCEL_NV_20              44      /* nVidia Arch 20               */
+#define FB_ACCEL_NV_30              45      /* nVidia Arch 30               */
+#define FB_ACCEL_NV_40              46      /* nVidia Arch 40               */
+#define FB_ACCEL_NEOMAGIC_NM2070    90	/* NeoMagic NM2070              */
+#define FB_ACCEL_NEOMAGIC_NM2090    91	/* NeoMagic NM2090              */
+#define FB_ACCEL_NEOMAGIC_NM2093    92	/* NeoMagic NM2093              */
+#define FB_ACCEL_NEOMAGIC_NM2097    93	/* NeoMagic NM2097              */
+#define FB_ACCEL_NEOMAGIC_NM2160    94	/* NeoMagic NM2160              */
+#define FB_ACCEL_NEOMAGIC_NM2200    95	/* NeoMagic NM2200              */
+#define FB_ACCEL_NEOMAGIC_NM2230    96	/* NeoMagic NM2230              */
+#define FB_ACCEL_NEOMAGIC_NM2360    97	/* NeoMagic NM2360              */
+#define FB_ACCEL_NEOMAGIC_NM2380    98	/* NeoMagic NM2380              */
 
-#define FB_ACCEL_SAVAGE4        0x80	/* S3 Savage4                   */
-#define FB_ACCEL_SAVAGE3D       0x81	/* S3 Savage3D                  */
-#define FB_ACCEL_SAVAGE3D_MV    0x82	/* S3 Savage3D-MV               */
-#define FB_ACCEL_SAVAGE2000     0x83	/* S3 Savage2000                */
-#define FB_ACCEL_SAVAGE_MX_MV   0x84	/* S3 Savage/MX-MV              */
-#define FB_ACCEL_SAVAGE_MX      0x85	/* S3 Savage/MX                 */
-#define FB_ACCEL_SAVAGE_IX_MV   0x86	/* S3 Savage/IX-MV              */
-#define FB_ACCEL_SAVAGE_IX      0x87	/* S3 Savage/IX                 */
-#define FB_ACCEL_PROSAVAGE_PM   0x88	/* S3 ProSavage PM133           */
-#define FB_ACCEL_PROSAVAGE_KM   0x89	/* S3 ProSavage KM133           */
-#define FB_ACCEL_S3TWISTER_P    0x8a	/* S3 Twister                   */
-#define FB_ACCEL_S3TWISTER_K    0x8b	/* S3 TwisterK                  */
-#define FB_ACCEL_SUPERSAVAGE    0x8c    /* S3 Supersavage               */
-#define FB_ACCEL_PROSAVAGE_DDR  0x8d	/* S3 ProSavage DDR             */
-#define FB_ACCEL_PROSAVAGE_DDRK 0x8e	/* S3 ProSavage DDR-K           */
+#define FB_ACCEL_SAVAGE4            0x80	/* S3 Savage4                   */
+#define FB_ACCEL_SAVAGE3D           0x81	/* S3 Savage3D                  */
+#define FB_ACCEL_SAVAGE3D_MV        0x82	/* S3 Savage3D-MV               */
+#define FB_ACCEL_SAVAGE2000         0x83	/* S3 Savage2000                */
+#define FB_ACCEL_SAVAGE_MX_MV       0x84	/* S3 Savage/MX-MV              */
+#define FB_ACCEL_SAVAGE_MX          0x85	/* S3 Savage/MX                 */
+#define FB_ACCEL_SAVAGE_IX_MV       0x86	/* S3 Savage/IX-MV              */
+#define FB_ACCEL_SAVAGE_IX          0x87	/* S3 Savage/IX                 */
+#define FB_ACCEL_PROSAVAGE_PM       0x88	/* S3 ProSavage PM133           */
+#define FB_ACCEL_PROSAVAGE_KM       0x89	/* S3 ProSavage KM133           */
+#define FB_ACCEL_S3TWISTER_P        0x8a	/* S3 Twister                   */
+#define FB_ACCEL_S3TWISTER_K        0x8b	/* S3 TwisterK                  */
+#define FB_ACCEL_SUPERSAVAGE        0x8c    /* S3 Supersavage               */
+#define FB_ACCEL_PROSAVAGE_DDR      0x8d	/* S3 ProSavage DDR             */
+#define FB_ACCEL_PROSAVAGE_DDRK     0x8e	/* S3 ProSavage DDR-K           */
 
-struct fb_fix_screeninfo {
-	char id[16];					/* identification string eg "TT Builtin" */
-	unsigned long smem_start;		/* Start of frame buffer mem */
-									/* (physical address) */
-	unsigned long smem_len;			/* Length of frame buffer mem */
-	unsigned long type;				/* see FB_TYPE_*		*/
-	unsigned long type_aux;			/* Interleave for interleaved Planes */
-	unsigned long visual;			/* see FB_VISUAL_*		*/ 
-	unsigned short xpanstep;		/* zero if no hardware panning  */
-	unsigned short ypanstep;		/* zero if no hardware panning  */
-	unsigned short ywrapstep;		/* zero if no hardware ywrap    */
-	unsigned long line_length;		/* length of a line in bytes    */
-	unsigned long mmio_start;		/* Start of Memory Mapped I/O   */
-									/* (physical address) */
-	unsigned long mmio_len;			/* Length of Memory Mapped I/O  */
-	unsigned long accel;			/* Indicate to driver which	*/
-									/*  specific chip/card we have	*/
-	unsigned short reserved[3];		/* Reserved for future compatibility */
+struct fb_fix_screeninfo
+{
+    char id[16];                    /* identification string eg "TT Builtin" */
+    uint32_t smem_start;       /* Start of frame buffer mem */
+    /* (physical address) */
+    uint32_t smem_len;         /* Length of frame buffer mem */
+    uint32_t type;             /* see FB_TYPE_*		*/
+    uint32_t type_aux;         /* Interleave for interleaved Planes */
+    uint32_t visual;           /* see FB_VISUAL_*		*/
+    uint16_t xpanstep;        /* zero if no hardware panning  */
+    uint16_t ypanstep;        /* zero if no hardware panning  */
+    uint16_t ywrapstep;       /* zero if no hardware ywrap    */
+    uint32_t line_length;      /* length of a line in bytes    */
+    uint32_t mmio_start;       /* Start of Memory Mapped I/O   */
+    /* (physical address) */
+    uint32_t mmio_len;         /* Length of Memory Mapped I/O  */
+    uint32_t accel;            /* Indicate to driver which	*/
+    /*  specific chip/card we have	*/
+    uint16_t reserved[3];     /* Reserved for future compatibility */
 };
 
 /* Interpretation of offset for color fields: All offsets are from the right,
@@ -199,87 +209,89 @@ struct fb_fix_screeninfo {
  * stream and is written to video memory as that unmodified. This implies
  * big-endian byte order if bits_per_pixel is greater than 8.
  */
-struct fb_bitfield {
-	unsigned long offset;			/* beginning of bitfield	*/
-	unsigned long length;			/* length of bitfield		*/
-	unsigned long msb_right;		/* != 0 : Most significant bit is */ 
-					/* right */ 
+struct fb_bitfield
+{
+    uint32_t offset;           /* beginning of bitfield	*/
+    uint32_t length;           /* length of bitfield		*/
+    uint32_t msb_right;        /* != 0 : Most significant bit is */
+    /* right */
 };
 
-#define FB_NONSTD_HAM		1	/* Hold-And-Modify (HAM)        */
+#define FB_NONSTD_HAM           1   /* Hold-And-Modify (HAM)        */
 
-#define FB_ACTIVATE_NOW		0	/* set values immediately (or vbl)*/
-#define FB_ACTIVATE_NXTOPEN	1	/* activate on next open	*/
-#define FB_ACTIVATE_TEST	2	/* don't set, round up impossible */
+#define FB_ACTIVATE_NOW         0   /* set values immediately (or vbl)*/
+#define FB_ACTIVATE_NXTOPEN     1   /* activate on next open	*/
+#define FB_ACTIVATE_TEST        2   /* don't set, round up impossible */
 #define FB_ACTIVATE_MASK       15
-					/* values			*/
-#define FB_ACTIVATE_VBL	       16	/* activate values on next vbl  */
-#define FB_CHANGE_CMAP_VBL     32	/* change colormap on vbl	*/
-#define FB_ACTIVATE_ALL	       64	/* change all VCs on this fb	*/
-#define FB_ACTIVATE_FORCE     128	/* force apply even when no change*/
-#define FB_ACTIVATE_INV_MODE  256 /* invalidate videomode */
+/* values */
+#define FB_ACTIVATE_VBL	       16   /* activate values on next vbl  */
+#define FB_CHANGE_CMAP_VBL     32   /* change colormap on vbl	*/
+#define FB_ACTIVATE_ALL	       64   /* change all VCs on this fb	*/
+#define FB_ACTIVATE_FORCE     128   /* force apply even when no change*/
+#define FB_ACTIVATE_INV_MODE  256   /* invalidate videomode */
 
-#define FB_ACCELF_TEXT		1	/* (OBSOLETE) see fb_info.flags and vc_mode */
+#define FB_ACCELF_TEXT          1   /* (OBSOLETE) see fb_info.flags and vc_mode */
 
-#define FB_SYNC_HOR_HIGH_ACT	1	/* horizontal sync high active	*/
-#define FB_SYNC_VERT_HIGH_ACT	2	/* vertical sync high active	*/
-#define FB_SYNC_EXT		4	/* external sync		*/
-#define FB_SYNC_COMP_HIGH_ACT	8	/* composite sync high active   */
-#define FB_SYNC_BROADCAST	16	/* broadcast video timings      */
-					/* vtotal = 144d/288n/576i => PAL  */
-					/* vtotal = 121d/242n/484i => NTSC */
-#define FB_SYNC_ON_GREEN	32	/* sync on green */
+#define FB_SYNC_HOR_HIGH_ACT    1   /* horizontal sync high active	*/
+#define FB_SYNC_VERT_HIGH_ACT   2   /* vertical sync high active	*/
+#define FB_SYNC_EXT             4   /* external sync		*/
+#define FB_SYNC_COMP_HIGH_ACT   8   /* composite sync high active   */
+#define FB_SYNC_BROADCAST       16  /* broadcast video timings      */
+/* vtotal = 144d/288n/576i => PAL  */
+/* vtotal = 121d/242n/484i => NTSC */
+#define FB_SYNC_ON_GREEN        32  /* sync on green */
 
-#define FB_VMODE_NONINTERLACED  0	/* non interlaced */
-#define FB_VMODE_INTERLACED	1	/* interlaced	*/
-#define FB_VMODE_DOUBLE		2	/* double scan */
-#define FB_VMODE_MASK		255
+#define FB_VMODE_NONINTERLACED  0   /* non interlaced */
+#define FB_VMODE_INTERLACED     1   /* interlaced	*/
+#define FB_VMODE_DOUBLE         2   /* double scan */
+#define FB_VMODE_MASK           255
 
-#define FB_VMODE_YWRAP		256	/* ywrap instead of panning     */
-#define FB_VMODE_SMOOTH_XPAN	512	/* smooth xpan possible (internally used) */
-#define FB_VMODE_CONUPDATE	512	/* don't update x/yoffset	*/
+#define FB_VMODE_YWRAP          256	/* ywrap instead of panning     */
+#define FB_VMODE_SMOOTH_XPAN    512	/* smooth xpan possible (internally used) */
+#define FB_VMODE_CONUPDATE      512	/* don't update x/yoffset	*/
 
-#define PICOS2KHZ(a) (1000000000UL/(a))
-#define KHZ2PICOS(a) (1000000000UL/(a))
+#define PICOS2KHZ(a)            (1000000000UL / (a))
+#define KHZ2PICOS(a)            (1000000000UL / (a))
 
-struct fb_var_screeninfo {
-	unsigned long xres;				/* visible resolution		*/
-	unsigned long yres;
-	unsigned long xres_virtual;		/* virtual resolution		*/
-	unsigned long yres_virtual;
-	unsigned long xoffset;			/* offset from virtual to visible */
-	unsigned long yoffset;			/* resolution			*/
+struct fb_var_screeninfo
+{
+    uint32_t xres;             /* visible resolution */
+    uint32_t yres;
+    uint32_t xres_virtual;     /* virtual resolution */
+    uint32_t yres_virtual;
+    uint32_t xoffset;          /* offset from virtual to visible */
+    uint32_t yoffset;          /* resolution			*/
 
-	unsigned long bits_per_pixel;	/* guess what			*/
-	unsigned long grayscale;		/* != 0 Graylevels instead of colors */
+    uint32_t bits_per_pixel;   /* guess what			*/
+    uint32_t grayscale;        /* != 0 Graylevels instead of colors */
 
-	struct fb_bitfield red;			/* bitfield in fb mem if true color, */
-	struct fb_bitfield green;		/* else only length is significant */
-	struct fb_bitfield blue;
-	struct fb_bitfield transp;		/* transparency			*/	
+    struct fb_bitfield red;         /* bitfield in fb mem if true color, */
+    struct fb_bitfield green;       /* else only length is significant */
+    struct fb_bitfield blue;
+    struct fb_bitfield transp;      /* transparency			*/
 
-	unsigned long nonstd;			/* != 0 Non standard pixel format */
+    uint32_t nonstd;           /* != 0 Non standard pixel format */
 
-	unsigned long activate;			/* see FB_ACTIVATE_*		*/
+    uint32_t activate;         /* see FB_ACTIVATE_*		*/
 
-	unsigned long height;			/* height of picture in mm    */
-	unsigned long width;			/* width of picture in mm     */
+    uint32_t height;           /* height of picture in mm    */
+    uint32_t width;            /* width of picture in mm     */
 
-	unsigned long accel_flags;		/* (OBSOLETE) see fb_info.flags */
+    uint32_t accel_flags;      /* (OBSOLETE) see fb_info.flags */
 
-	/* Timing: All values in pixclocks, except pixclock (of course) */
-	unsigned long pixclock;			/* pixel clock in ps (pico seconds) */
-	unsigned long left_margin;		/* time from sync to picture	*/
-	unsigned long right_margin;		/* time from picture to sync	*/
-	unsigned long upper_margin;		/* time from sync to picture	*/
-	unsigned long lower_margin;
-	unsigned long hsync_len;		/* length of horizontal sync	*/
-	unsigned long vsync_len;		/* length of vertical sync	*/
-	unsigned long sync;				/* see FB_SYNC_*		*/
-	unsigned long vmode;			/* see FB_VMODE_*		*/
-	unsigned long rotate;			/* angle we rotate counter clockwise */
-	unsigned long refresh;
-	unsigned long reserved[4];		/* Reserved for future compatibility */
+    /* Timing: All values in pixclocks, except pixclock (of course) */
+    uint32_t pixclock;         /* pixel clock in ps (pico seconds) */
+    uint32_t left_margin;      /* time from sync to picture	*/
+    uint32_t right_margin;     /* time from picture to sync	*/
+    uint32_t upper_margin;     /* time from sync to picture	*/
+    uint32_t lower_margin;
+    uint32_t hsync_len;        /* length of horizontal sync	*/
+    uint32_t vsync_len;        /* length of vertical sync	*/
+    uint32_t sync;             /* see FB_SYNC_*		*/
+    uint32_t vmode;            /* see FB_VMODE_*		*/
+    uint32_t rotate;           /* angle we rotate counter clockwise */
+    uint32_t refresh;
+    uint32_t reserved[4];      /* Reserved for future compatibility */
 };
 
 /* VESA Blanking Levels */
@@ -288,35 +300,37 @@ struct fb_var_screeninfo {
 #define VESA_HSYNC_SUSPEND      2
 #define VESA_POWERDOWN          3
 
-enum {
-	/* screen: unblanked, hsync: on,  vsync: on */
-	FB_BLANK_UNBLANK       = VESA_NO_BLANKING,
-	/* screen: blanked,   hsync: on,  vsync: on */
-	FB_BLANK_NORMAL        = VESA_NO_BLANKING + 1,
-	/* screen: blanked,   hsync: on,  vsync: off */
-	FB_BLANK_VSYNC_SUSPEND = VESA_VSYNC_SUSPEND + 1,
-	/* screen: blanked,   hsync: off, vsync: on */
-	FB_BLANK_HSYNC_SUSPEND = VESA_HSYNC_SUSPEND + 1,
-	/* screen: blanked,   hsync: off, vsync: off */
-	FB_BLANK_POWERDOWN     = VESA_POWERDOWN + 1
+enum
+{
+    /* screen: unblanked, hsync: on,  vsync: on */
+    FB_BLANK_UNBLANK       = VESA_NO_BLANKING,
+    /* screen: blanked,   hsync: on,  vsync: on */
+    FB_BLANK_NORMAL        = VESA_NO_BLANKING + 1,
+    /* screen: blanked,   hsync: on,  vsync: off */
+    FB_BLANK_VSYNC_SUSPEND = VESA_VSYNC_SUSPEND + 1,
+    /* screen: blanked,   hsync: off, vsync: on */
+    FB_BLANK_HSYNC_SUSPEND = VESA_HSYNC_SUSPEND + 1,
+    /* screen: blanked,   hsync: off, vsync: off */
+    FB_BLANK_POWERDOWN     = VESA_POWERDOWN + 1
 };
 
-#define FB_VBLANK_VBLANKING	0x001	/* currently in a vertical blank */
-#define FB_VBLANK_HBLANKING	0x002	/* currently in a horizontal blank */
+#define FB_VBLANK_VBLANKING     0x001	/* currently in a vertical blank */
+#define FB_VBLANK_HBLANKING     0x002	/* currently in a horizontal blank */
 #define FB_VBLANK_HAVE_VBLANK	0x004	/* vertical blanks can be detected */
 #define FB_VBLANK_HAVE_HBLANK	0x008	/* horizontal blanks can be detected */
 #define FB_VBLANK_HAVE_COUNT	0x010	/* global retrace counter is available */
 #define FB_VBLANK_HAVE_VCOUNT	0x020	/* the vcount field is valid */
 #define FB_VBLANK_HAVE_HCOUNT	0x040	/* the hcount field is valid */
-#define FB_VBLANK_VSYNCING	0x080	/* currently in a vsync */
+#define FB_VBLANK_VSYNCING      0x080	/* currently in a vsync */
 #define FB_VBLANK_HAVE_VSYNC	0x100	/* verical syncs can be detected */
 
-struct fb_vblank {
-	unsigned long flags;			/* FB_VBLANK flags */
-	unsigned long count;			/* counter of retraces since boot */
-	unsigned long vcount;			/* current scanline position */
-	unsigned long hcount;			/* current scandot position */
-	unsigned long reserved[4];		/* reserved for future compatibility */
+struct fb_vblank
+{
+    uint32_t flags;			/* FB_VBLANK flags */
+    uint32_t count;			/* counter of retraces since boot */
+    uint32_t vcount;			/* current scanline position */
+    uint32_t hcount;			/* current scandot position */
+    uint32_t reserved[4];		/* reserved for future compatibility */
 };
 
 struct vm_area_struct;
@@ -325,155 +339,160 @@ struct device;
 struct file;
 
 /* Definitions below are used in the parsed monitor specs */
-#define FB_DPMS_ACTIVE_OFF	1
-#define FB_DPMS_SUSPEND		2
-#define FB_DPMS_STANDBY		4
+#define FB_DPMS_ACTIVE_OFF      1
+#define FB_DPMS_SUSPEND         2
+#define FB_DPMS_STANDBY         4
 
-#define FB_DISP_DDI		1
-#define FB_DISP_ANA_700_300	2
-#define FB_DISP_ANA_714_286	4
-#define FB_DISP_ANA_1000_400	8
-#define FB_DISP_ANA_700_000	16
+#define FB_DISP_DDI             1
+#define FB_DISP_ANA_700_300     2
+#define FB_DISP_ANA_714_286     4
+#define FB_DISP_ANA_1000_400    8
+#define FB_DISP_ANA_700_000     16
 
-#define FB_DISP_MONO		32
-#define FB_DISP_RGB		64
-#define FB_DISP_MULTI		128
-#define FB_DISP_UNKNOWN		256
+#define FB_DISP_MONO            32
+#define FB_DISP_RGB             64
+#define FB_DISP_MULTI           128
+#define FB_DISP_UNKNOWN         256
 
-#define FB_SIGNAL_NONE		0
-#define FB_SIGNAL_BLANK_BLANK	1
-#define FB_SIGNAL_SEPARATE	2
-#define FB_SIGNAL_COMPOSITE	4
+#define FB_SIGNAL_NONE          0
+#define FB_SIGNAL_BLANK_BLANK   1
+#define FB_SIGNAL_SEPARATE      2
+#define FB_SIGNAL_COMPOSITE     4
 #define FB_SIGNAL_SYNC_ON_GREEN	8
-#define FB_SIGNAL_SERRATION_ON	16
+#define FB_SIGNAL_SERRATION_ON  16
 
-#define FB_MISC_PRIM_COLOR	1
-#define FB_MISC_1ST_DETAIL	2	/* First Detailed Timing is preferred */
-struct fb_chroma {
-	unsigned long redx;	/* in fraction of 1024 */
-	unsigned long greenx;
-	unsigned long bluex;
-	unsigned long whitex;
-	unsigned long redy;
-	unsigned long greeny;
-	unsigned long bluey;
-	unsigned long whitey;
+#define FB_MISC_PRIM_COLOR      1
+#define FB_MISC_1ST_DETAIL      2	/* First Detailed Timing is preferred */
+
+struct fb_chroma
+{
+    uint32_t redx;	/* in fraction of 1024 */
+    uint32_t greenx;
+    uint32_t bluex;
+    uint32_t whitex;
+    uint32_t redy;
+    uint32_t greeny;
+    uint32_t bluey;
+    uint32_t whitey;
 };
 
-struct fb_monspecs {
-	struct fb_chroma chroma;
-	struct fb_videomode *modedb;	/* mode database */
-	unsigned char  manufacturer[4];	/* Manufacturer */
-	unsigned char  monitor[14];		/* Monitor String */
-	unsigned char  serial_no[14];	/* Serial Number */
-	unsigned char  ascii[14];		/* ? */
-	unsigned long modedb_len;		/* mode database length */
-	unsigned long model;			/* Monitor Model */
-	unsigned long serial;			/* Serial Number - Integer */
-	unsigned long year;				/* Year manufactured */
-	unsigned long week;				/* Week Manufactured */
-	unsigned long hfmin;			/* hfreq lower limit (Hz) */
-	unsigned long hfmax;			/* hfreq upper limit (Hz) */
-	unsigned long dclkmin;			/* pixelclock lower limit (Hz) */
-	unsigned long dclkmax;			/* pixelclock upper limit (Hz) */
-	unsigned short input;			/* display type - see FB_DISP_* */
-	unsigned short dpms;			/* DPMS support - see FB_DPMS_ */
-	unsigned short signal;			/* Signal Type - see FB_SIGNAL_* */
-	unsigned short vfmin;			/* vfreq lower limit (Hz) */
-	unsigned short vfmax;			/* vfreq upper limit (Hz) */
-	unsigned short gamma;			/* Gamma - in fractions of 100 */
-	unsigned short gtf	: 1;		/* supports GTF */
-	unsigned short misc;			/* Misc flags - see FB_MISC_* */
-	unsigned char  version;			/* EDID version... */
-	unsigned char  revision;		/* ...and revision */
-	unsigned char  max_x;			/* Maximum horizontal size (cm) */
-	unsigned char  max_y;			/* Maximum vertical size (cm) */
+struct fb_monspecs
+{
+    struct fb_chroma chroma;
+    struct fb_videomode *modedb;	/* mode database */
+    uint8_t  manufacturer[4];	/* Manufacturer */
+    uint8_t  monitor[14];		/* Monitor String */
+    uint8_t  serial_no[14];	/* Serial Number */
+    uint8_t  ascii[14];		/* ? */
+    uint32_t modedb_len;		/* mode database length */
+    uint32_t model;			/* Monitor Model */
+    uint32_t serial;			/* Serial Number - Integer */
+    uint32_t year;				/* Year manufactured */
+    uint32_t week;				/* Week Manufactured */
+    uint32_t hfmin;			/* hfreq lower limit (Hz) */
+    uint32_t hfmax;			/* hfreq upper limit (Hz) */
+    uint32_t dclkmin;			/* pixelclock lower limit (Hz) */
+    uint32_t dclkmax;			/* pixelclock upper limit (Hz) */
+    uint16_t input;			/* display type - see FB_DISP_* */
+    uint16_t dpms;			/* DPMS support - see FB_DPMS_ */
+    uint16_t signal;			/* Signal Type - see FB_SIGNAL_* */
+    uint16_t vfmin;			/* vfreq lower limit (Hz) */
+    uint16_t vfmax;			/* vfreq upper limit (Hz) */
+    uint16_t gamma;			/* Gamma - in fractions of 100 */
+    uint16_t gtf	: 1;		/* supports GTF */
+    uint16_t misc;			/* Misc flags - see FB_MISC_* */
+    uint8_t  version;			/* EDID version... */
+    uint8_t  revision;		/* ...and revision */
+    uint8_t  max_x;			/* Maximum horizontal size (cm) */
+    uint8_t  max_y;			/* Maximum vertical size (cm) */
 };
 
-struct fb_ops {
-	/* checks var and eventually tweaks if to soomething supported,
-	 * DO NOT MODIFY PAR  */
-	int (*fb_check_var)(struct fb_var_screeninfo *var, struct fb_info *info);
-	/* set the video mode according to info->var */
-	int (*fb_set_par)(struct fb_info *info);
-	/* set color register */
-	int (*fb_setcolreg)(unsigned regno, unsigned red, unsigned green,
-	                    unsigned blue, unsigned transp, struct fb_info *info);
-	/* pan display */
-	int (*fb_pan_display)(struct fb_var_screeninfo *var, struct fb_info *info);
-	/* blank display */
-	int (*fb_blank)(int blank, struct fb_info *info);
-	/* wait for blit idle */
-	int (*fb_sync)(struct fb_info *info);
-	/* perform fb specific ioctl */
-	int (*fb_ioctl)(unsigned int cmd, unsigned long arg, struct fb_info *info);
-	/* Buildthe modedb for head 1 (head 2 will come later), check panel infos
-	 * from either BIOS or EDID, and pick up the default mode */
-	void (*fb_check_modes)(struct fb_info *info, struct mode_option *resolution);
-  /* Accel functions */
+struct fb_ops
+{
+    /* checks var and eventually tweaks if to something supported,
+     * DO NOT MODIFY PAR  */
+    int32_t (*fb_check_var)(struct fb_var_screeninfo *var, struct fb_info *info);
+    /* set the video mode according to info->var */
+    int32_t (*fb_set_par)(struct fb_info *info);
+    /* set color register */
+    int32_t (*fb_setcolreg)(uint32_t regno, uint32_t red, uint32_t green,
+                        uint32_t blue, uint32_t transp, struct fb_info *info);
+    /* pan display */
+    int32_t (*fb_pan_display)(struct fb_var_screeninfo *var, struct fb_info *info);
+    /* blank display */
+    int32_t (*fb_blank)(int32_t blank, struct fb_info *info);
+    /* wait for blit idle */
+    int32_t (*fb_sync)(struct fb_info *info);
+    /* perform fb specific ioctl */
+    int32_t (*fb_ioctl)(uint32_t cmd, uint32_t arg, struct fb_info *info);
+    /* Buildthe modedb for head 1 (head 2 will come later), check panel infos
+     * from either BIOS or EDID, and pick up the default mode */
+    void (*fb_check_modes)(struct fb_info *info, struct mode_option *resolution);
+    /* Accel functions */
 #define DEGREES_0	0
 #define DEGREES_90	1
 #define DEGREES_180	2
 #define DEGREES_270	3
 #define OMIT_LAST	1
-	void (*SetupForSolidFill)(struct fb_info *info, int color, int rop, unsigned int planemask);
-	void (*SubsequentSolidFillRect)(struct fb_info *info, int x, int y, int w, int h);
-	void (*SetupForSolidLine)(struct fb_info *info, int color, int rop, unsigned int planemask);
-	void (*SubsequentSolidHorVertLine)(struct fb_info *info, int x, int y, int len, int dir);   
-	void (*SubsequentSolidTwoPointLine)(struct fb_info *info, int xa, int ya, int xb, int yb, int flags);  
-	void (*SetupForDashedLine)(struct fb_info *info, int fg, int bg, int rop, unsigned int planemask, int length, unsigned char *pattern);
-	void (*SubsequentDashedTwoPointLine)(struct fb_info *info, int xa, int ya, int xb, int yb, int flags, int phase);  
-	void (*SetupForScreenToScreenCopy)(struct fb_info *info, int xdir, int ydir, int rop, unsigned int planemask, int trans_color);
-	void (*SubsequentScreenToScreenCopy)(struct fb_info *info, int xa, int ya, int xb, int yb, int w, int h);   
-	void (*ScreenToScreenCopy)(struct fb_info *info, int xa, int ya, int xb, int yb, int w, int h, int rop);
-	void (*SetupForMono8x8PatternFill)(struct fb_info *info, int patternx, int patterny, int fg, int bg, int rop, unsigned int planemask);
-	void (*SubsequentMono8x8PatternFillRect)(struct fb_info *info, int patternx, int patterny, int x, int y, int w, int h);
-	void (*SetupForScanlineCPUToScreenColorExpandFill)(struct fb_info *info, int fg, int bg, int rop, unsigned int planemask);
-	void (*SubsequentScanlineCPUToScreenColorExpandFill)(struct fb_info *info, int x, int y, int w, int h, int skipleft);
-	void (*SubsequentScanline)(struct fb_info *info, unsigned long *buf);
-	void (*SetupForScanlineImageWrite)(struct fb_info *info, int rop, unsigned int planemask, int trans_color, int bpp);
-	void (*SubsequentScanlineImageWriteRect)(struct fb_info *info, int x, int y, int w, int h, int skipleft);  
-	void (*SetClippingRectangle)(struct fb_info *info, int xa, int ya, int xb, int yb);
-	void (*DisableClipping)(struct fb_info *info);
-	int (*SetupForCPUToScreenAlphaTexture)(struct fb_info *info, 
-      int op, unsigned short red, unsigned short green, unsigned short blue, unsigned short alpha, unsigned long maskFormat, unsigned long dstFormat, unsigned char *alphaPtr, int alphaPitch, int width, int height, int flags);
-	int (*SetupForCPUToScreenTexture)(struct fb_info *info, int op, unsigned long srcFormat, unsigned long dstFormat, unsigned char *texPtr, int texPitch, int width, int height, int flags);
-	void (*SubsequentCPUToScreenTexture)(struct fb_info *info, int dstx, int dsty, int srcx, int srcy, int width, int height);
-	/* Cursor functions */
-	void (*SetCursorColors)(struct fb_info *info, int bg, int fg);
-	void (*SetCursorPosition)(struct fb_info *info, int x, int y);
-	void (*LoadCursorImage)(struct fb_info *info, unsigned short *mask, unsigned short *data, int zoom);
-	void (*HideCursor)(struct fb_info *info);
-	void (*ShowCursor)(struct fb_info *info);
-	long (*CursorInit)(struct fb_info *info);
-	void (*WaitVbl)(struct fb_info *info);
+    void (*SetupForSolidFill)(struct fb_info *info, int32_t color, int32_t rop, uint32_t planemask);
+    void (*SubsequentSolidFillRect)(struct fb_info *info, int32_t x, int32_t y, int32_t w, int32_t h);
+    void (*SetupForSolidLine)(struct fb_info *info, int32_t color, int32_t rop, uint32_t planemask);
+    void (*SubsequentSolidHorVertLine)(struct fb_info *info, int32_t x, int32_t y, int32_t len, int32_t dir);
+    void (*SubsequentSolidTwoPointLine)(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t flags);
+    void (*SetupForDashedLine)(struct fb_info *info, int32_t fg, int32_t bg, int32_t rop, uint32_t planemask, int32_t length, uint8_t *pattern);
+    void (*SubsequentDashedTwoPointLine)(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t flags, int32_t phase);
+    void (*SetupForScreenToScreenCopy)(struct fb_info *info, int32_t xdir, int32_t ydir, int32_t rop, uint32_t planemask, int32_t trans_color);
+    void (*SubsequentScreenToScreenCopy)(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h);
+    void (*ScreenToScreenCopy)(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h, int32_t rop);
+    void (*SetupForMono8x8PatternFill)(struct fb_info *info, int32_t patternx, int32_t patterny, int32_t fg, int32_t bg, int32_t rop, uint32_t planemask);
+    void (*SubsequentMono8x8PatternFillRect)(struct fb_info *info, int32_t patternx, int32_t patterny, int32_t x, int32_t y, int32_t w, int32_t h);
+    void (*SetupForScanlineCPUToScreenColorExpandFill)(struct fb_info *info, int32_t fg, int32_t bg, int32_t rop, uint32_t planemask);
+    void (*SubsequentScanlineCPUToScreenColorExpandFill)(struct fb_info *info, int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft);
+    void (*SubsequentScanline)(struct fb_info *info, uint32_t *buf);
+    void (*SetupForScanlineImageWrite)(struct fb_info *info, int32_t rop, uint32_t planemask, int32_t trans_color, int32_t bpp);
+    void (*SubsequentScanlineImageWriteRect)(struct fb_info *info, int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft);
+    void (*SetClippingRectangle)(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb);
+    void (*DisableClipping)(struct fb_info *info);
+    int32_t (*SetupForCPUToScreenAlphaTexture)(struct fb_info *info,
+                                           int32_t op, uint16_t red, uint16_t green, uint16_t blue, uint16_t alpha, uint32_t maskFormat, uint32_t dstFormat, uint8_t *alphaPtr, int32_t alphaPitch, int32_t width, int32_t height, int32_t flags);
+    int32_t (*SetupForCPUToScreenTexture)(struct fb_info *info, int32_t op, uint32_t srcFormat, uint32_t dstFormat, uint8_t *texPtr, int32_t texPitch, int32_t width, int32_t height, int32_t flags);
+    void (*SubsequentCPUToScreenTexture)(struct fb_info *info, int32_t dstx, int32_t dsty, int32_t srcx, int32_t srcy, int32_t width, int32_t height);
+    /* Cursor functions */
+    void (*SetCursorColors)(struct fb_info *info, int32_t bg, int32_t fg);
+    void (*SetCursorPosition)(struct fb_info *info, int32_t x, int32_t y);
+    void (*LoadCursorImage)(struct fb_info *info, uint16_t *mask, uint16_t *data, int32_t zoom);
+    void (*HideCursor)(struct fb_info *info);
+    void (*ShowCursor)(struct fb_info *info);
+    long (*CursorInit)(struct fb_info *info);
+    void (*WaitVbl)(struct fb_info *info);
 };
 
-struct fb_info {
-	struct fb_var_screeninfo var;	/* Current var */
-	struct fb_fix_screeninfo fix;	/* Current fix */
-	struct fb_monspecs monspecs;	/* Current Monitor specs */
-	struct fb_videomode *mode;	/* current mode */
-	char *screen_base;	/* Virtual address */
-	unsigned long screen_size;
-	char *ram_base;	        /* base vram */
-	unsigned long ram_size; /* vram size */
-	char *screen_mono;
-	long update_mono;
-	struct fb_ops *fbops;
-	void *par; /* device dependent */
+struct fb_info
+{
+    struct fb_var_screeninfo var;   /* Current var */
+    struct fb_fix_screeninfo fix;   /* Current fix */
+    struct fb_monspecs monspecs;    /* Current Monitor specs */
+    struct fb_videomode *mode;      /* current mode */
+    char *screen_base;              /* Virtual address */
+    uint32_t screen_size;
+    char *ram_base;                 /* base vram */
+    uint32_t ram_size;         /* vram size */
+    char *screen_mono;
+    long update_mono;
+    struct fb_ops *fbops;
+    void *par;                      /* device dependent */
 };
 
 /* fbmem.c */
-extern int fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var); 
-extern int fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var); 
-extern int fb_blank(struct fb_info *info, int blank);
-extern int fb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg);
-extern struct fb_info *framebuffer_alloc(unsigned long size);
+extern int32_t fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var);
+extern int32_t fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var);
+extern int32_t fb_blank(struct fb_info *info, int32_t blank);
+extern int32_t fb_ioctl(struct fb_info *info, uint32_t cmd, uint32_t arg);
+extern struct fb_info *framebuffer_alloc(uint32_t size);
 extern void framebuffer_release(struct fb_info *info);
 
 /* offscreen.c */
-extern long offscreen_free(struct fb_info *info, long addr);
+extern long offscreen_free(struct fb_info *info, void *addr);
 extern long offscreen_alloc(struct fb_info *info, long amount);
 extern long offscren_reserved(struct fb_info *info);
 extern void offscreen_init(struct fb_info *info);
@@ -494,57 +513,44 @@ extern void offscreen_init(struct fb_info *info);
 #define FB_MODE_IS_FROM_VAR     32
 
 extern void fb_destroy_modedb(struct fb_videomode *modedb);
-extern int fb_parse_edid(unsigned char *edid, struct fb_var_screeninfo *var);
-extern void fb_edid_to_monspecs(unsigned char *edid, struct fb_monspecs *specs);
-extern int fb_get_mode(int flags, unsigned long val, struct fb_var_screeninfo *var, struct fb_info *info);
-extern int fb_validate_mode(const struct fb_var_screeninfo *var, struct fb_info *info);
+extern int32_t fb_parse_edid(uint8_t *edid, struct fb_var_screeninfo *var);
+extern void fb_edid_to_monspecs(uint8_t *edid, struct fb_monspecs *specs);
+extern int32_t fb_get_mode(int32_t flags, uint32_t val, struct fb_var_screeninfo *var, struct fb_info *info);
+extern int32_t fb_validate_mode(const struct fb_var_screeninfo *var, struct fb_info *info);
 
 /* modedb.c */
 #define VESA_MODEDB_SIZE 34
-extern int fb_find_mode(struct fb_var_screeninfo *var,
-           struct fb_info *info, struct mode_option *resolution ,
-           const struct fb_videomode *db, unsigned int dbsize,
-           const struct fb_videomode *default_mode, unsigned int default_bpp);
+extern int32_t fb_find_mode(struct fb_var_screeninfo *var,
+                        struct fb_info *info, struct mode_option *resolution ,
+                        const struct fb_videomode *db, uint32_t dbsize,
+                        const struct fb_videomode *default_mode, uint32_t default_bpp);
 extern void fb_var_to_videomode(struct fb_videomode *mode, struct fb_var_screeninfo *var);
 extern void fb_videomode_to_var(struct fb_var_screeninfo *var, struct fb_videomode *mode);
-extern int fb_mode_is_equal(struct fb_videomode *mode1, struct fb_videomode *mode2);
+extern int32_t fb_mode_is_equal(struct fb_videomode *mode1, struct fb_videomode *mode2);
 
-struct fb_videomode {
-	unsigned short refresh;		/* optional */
-	unsigned short xres;
-	unsigned short yres;
-	unsigned long pixclock;
-	unsigned short left_margin;
-	unsigned short right_margin;
-	unsigned short upper_margin;
-	unsigned short lower_margin;
-	unsigned short hsync_len;
-	unsigned short vsync_len;
-	unsigned short sync;
-	unsigned short vmode;
-	unsigned short flag;
+struct fb_videomode
+{
+    uint16_t refresh;		/* optional */
+    uint16_t xres;
+    uint16_t yres;
+    uint32_t pixclock;
+    uint16_t left_margin;
+    uint16_t right_margin;
+    uint16_t upper_margin;
+    uint16_t lower_margin;
+    uint16_t hsync_len;
+    uint16_t vsync_len;
+    uint16_t sync;
+    uint16_t vmode;
+    uint16_t flag;
 };
 
 extern const struct fb_videomode vesa_modes[];
 
-/* timer */
-#ifdef COLDFIRE
-#ifdef MCF5445X
-#define US_TO_TIMER(a) (a)
-#define TIMER_TO_US(a) (a)
-#else /* MCF548X */
-#define US_TO_TIMER(a) ((a)*100)
-#define TIMER_TO_US(a) ((a)/100)
-#endif
-#else
-#define US_TO_TIMER(a) (((a)*256)/5000)
-#define TIMER_TO_US(a) (((a)*5000)/256)
-#endif
-
 extern void start_timeout(void);
-extern int end_timeout(long msec);
+extern int32_t end_timeout(long msec);
 extern void mdelay(long msec);
-extern void install_vbl_timer(void *func, int remove);
+extern void install_vbl_timer(void *func, int32_t remove);
 extern void uninstall_vbl_timer(void *func);
 
 extern struct fb_info *info_fvdi;

include/firebee.h

@@ -40,6 +40,7 @@
 #define TARGET_ADDRESS  	(SDRAM_START + SDRAM_SIZE - 0x200000)
 #else
 #define TARGET_ADDRESS  	BOOTFLASH_BASE_ADDRESS
+#define BFL_TARGET_ADDRESS  0x0100000           /* load address for basflash */
 
 #endif /* COMPILE_RAM */
 

include/font.h

@@ -95,4 +95,6 @@ struct font_head {
 void font_init(void);           /* initialize BIOS font ring */
 void font_set_default(void);    /* choose the default font */
 
+extern struct font_head *fnt;
+
 #endif /* FONT_H */

include/i2c.h

@@ -84,6 +84,7 @@ struct i2c_msg
     unsigned char *buf;     /* pointer to msg data			*/
 };
 
+/*
 extern void i2c_init(void);
 extern void i2c_set_frequency(int hz);
 extern int i2c_read(int address, char *data, int lengt, bool repeated);
@@ -92,5 +93,5 @@ extern int i2c_write(int address, const char *data, int length, bool repeated);
 extern int i2c_write_byte(int data);
 extern void i2c_start(void);
 extern void i2c_stop(void);
-
+*/
 #endif /* _I2C_H */

include/interrupts.h

@@ -144,6 +144,7 @@ extern bool isr_execute_handler(int vector);
 extern bool pic_interrupt_handler(void *arg1, void *arg2);
 extern bool xlbpci_interrupt_handler(void *arg1, void *arg2);
 extern bool pciarb_interrupt_handler(void *arg1, void *arg2);
+extern bool xlbarb_interrupt_handler(void *arg1, void *arg2, ...);
 extern bool gpt0_interrupt_handler(void *arg1, void *arg2);
 extern bool irq5_handler(void *arg1, void *arg2);
 #endif /* _INTERRUPTS_H_ */

include/m54455.h

@@ -41,6 +41,7 @@
 #else
 #define TARGET_ADDRESS	BOOTFLASH_BASE_ADDRESS
 #endif /* COMPILE_RAM */
+#define BFL_TARGET_ADDRESS  0x0100000           /* load address for basflash */
 
 #define DRIVER_MEM_BUFFER_SIZE	0x100000
 

include/m5484l.h

@@ -27,7 +27,7 @@
  *      Author: Markus Fröschle
  */
 
-#define SYSCLK			100000
+#define SYSCLK			100000UL
 
 #define BOOTFLASH_BASE_ADDRESS		0xe0000000
 #define BOOTFLASH_SIZE				0x400000	/* LITEKIT has 4MB flash */
@@ -41,6 +41,7 @@
 #else
 #define TARGET_ADDRESS	BOOTFLASH_BASE_ADDRESS
 #endif /* COMPILE_RAM */
+#define BFL_TARGET_ADDRESS  0x0100000           /* load address for basflash */
 
 #define DRIVER_MEM_BUFFER_SIZE	0x100000
 

include/mmu.h

@@ -30,8 +30,8 @@
 /*
  * ACR register handling macros
  */
-#define ACR_BA(x)                   ((x) & 0xffff0000)
-#define ACR_ADMSK(x)                (((x) & 0xffff) << 16)
+#define ACR_BA(x)                   ((x) & 0xff000000)
+#define ACR_ADMSK(x)                (((x) & 0xff) << 16)
 #define ACR_E(x)                    (((x) & 1) << 15)
 
 #define ACR_S(x)                    (((x) & 3) << 13)
@@ -45,6 +45,17 @@
 #define ACR_SUPERVISOR_PROTECT(x)	(((x) & 1) << 3)
 #define ACR_WRITE_PROTECT(x)		(((x) & 1) << 2)
 
+#define ACR_AMM(x)                  (((x) & 1) << 10)
+
+#define ACR_CM(x)                   (((x) & 3) << 5)
+#define ACR_CM_CACHEABLE_WT         0x0
+#define ACR_CM_CACHEABLE_CB         0x1
+#define ACR_CM_CACHE_INH_PRECISE    0x2
+#define ACR_CM_CACHE_INH_IMPRECISE  0x3
+
+#define ACR_SP(x)           (((x) & 1) << 3)
+#define ACR_W(x)            (((x) & 1) << 2)
+
 
 /*
  * MMU register handling macros
@@ -64,13 +75,14 @@ enum mmu_page_size
     MMU_PAGE_SIZE_1K	= 3
 };
 
+#define MMU_PAGE_SIZE_DEFAULT   MMU_PAGE_SIZE_1M    /* note: if this changes, SIZE_DEFAULT below _must_ also change */
+
 #define SIZE_1M             0x100000        /* 1 Megabyte */
 #define SIZE_4K             0x1000          /* 4 KB */
 #define SIZE_8K             0x2000          /* 8 KB */
 #define SIZE_1K             0x400           /* 1 KB */
 
-#define DEFAULT_PAGE_SIZE   0x00100000      /* 1M pagesize */
-
+#define SIZE_DEFAULT        SIZE_1M
 /*
  * cache modes
  */
@@ -97,16 +109,25 @@ enum mmu_page_size
 extern long video_tlb;
 extern long video_sbt;
 
-struct mmu_page_descriptor;
+struct mmu_page_descriptor_ram
+{
+    uint8_t cache_mode          : 2;
+    uint8_t supervisor_protect  : 1;
+    uint8_t read                : 1;
+    uint8_t write               : 1;
+    uint8_t execute             : 1;
+    uint8_t global              : 1;
+    uint8_t locked              : 1;
+};
 
 extern void mmu_init(void);
-extern int mmu_map_page(int32_t virt, int32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor *flags);
+extern uint32_t mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor_ram *flags);
 
 /*
  * API functions for the BaS driver interface
  */
-extern int32_t mmu_map_data_page_locked(uint32_t address, uint32_t length, int asid);
-extern int32_t mmu_unlock_data_page(uint32_t address, uint32_t length, int asid);
-extern int32_t mmu_report_locked_pages(uint32_t *num_itlb, uint32_t *num_dtlb);
+extern uint32_t mmu_map_data_page_locked(uint32_t address, uint32_t length, int asid);
+extern uint32_t mmu_unlock_data_page(uint32_t address, uint32_t length, int asid);
+extern uint32_t mmu_report_locked_pages(uint32_t *num_itlb, uint32_t *num_dtlb);
 extern uint32_t mmu_report_pagesize(void);
 #endif /* _MMU_H_ */

include/pci.h

@@ -27,22 +27,27 @@
 #define  PCI_MEMORY_OFFSET  0x80000000
 #define  PCI_MEMORY_SIZE    0x40000000  /* 1 GByte PCI memory window */
 #define  PCI_IO_OFFSET      0xD0000000
-#define  PCI_IO_SIZE        0x10000000  /* 128 MByte PCI I/O window */
+#define  PCI_IO_SIZE        0x10000000  /* 256 MByte PCI I/O window */
 
+#define PCI_LANESWAP_B(x)     (x ^ 3)
+#define PCI_LANESWAP_W(x)     (x ^ 2)
+#define PCI_LANESWAP_L(x)     (x)     /* for completeness only */
 /*
- * Note: the byte offsets are in little endian format, so you can't use them
- * on byteswapped (Motorola format) values!
+ * Note: the byte offsets are in little endian format, so for pci_xxx_config_byte()
+ * accesses to hit the right offset, you'll need to wrap them into PCI_LANESWAP_B()
+ * and for pci_xxx_config_word() into PCI_LANESWAP_W()
  */
 #define PCIIDR                0x00   /* PCI Configuration ID Register       */
 #define PCICSR                0x04   /* PCI Command/Status Register         */
-#define PCICR                 0x04   /* PCI Command Register                */
-#define PCISR                 0x06   /* PCI Status Register                 */
-#define PCIREV                0x08   /* PCI Revision ID Register            */
-#define PCICCR                0x0B   /* PCI Class Code Register             */
-#define PCICLSR               0x0C   /* PCI Cache Line Size Register        */
-#define PCILTR                0x0D   /* PCI Latency Timer Register          */
-#define PCIHTR                0x0E   /* PCI Header Type Register            */
-#define PCIBISTR              0x0F   /* PCI Build-In Self Test Register     */
+#define PCICR                 0x06   /* PCI Command Register                */
+#define PCISR                 0x04   /* PCI Status Register                 */
+#define PCIREV                0x0B   /* PCI Revision ID Register            */
+#define PCICCR                0x08   /* PCI Class Code Register             */
+#define PCICLSR               0x0F   /* PCI Cache Line Size Register        */
+#define PCILTR                0x0E   /* PCI Latency Timer Register          */
+#define PCIHTR                0x0D   /* PCI Header Type Register            */
+#define PCIBISTR              0x0C   /* PCI Build-In Self Test Register     */
+
 #define PCIBAR0               0x10   /* PCI Base Address Register for Memory
                                         Accesses to Local, Runtime, and DMA */
 #define PCIBAR1               0x14   /* PCI Base Address Register for I/O
@@ -55,13 +60,13 @@
 #define PCIBAR5               0x24   /* PCI Base Address Register, reserved */
 #define PCICIS                0x28   /* PCI Cardbus CIS Pointer, not support*/
 #define PCISVID               0x2E   /* PCI Subsystem Vendor ID             */
-#define PCISID                0x2E   /* PCI Subsystem ID                    */
+#define PCISID                0x2D   /* PCI Subsystem ID                    */
 #define PCIERBAR              0x30   /* PCI Expansion ROM Base Register     */
 #define CAP_PTR               0x34   /* New Capability Pointer              */
-#define PCIILR                0x3C   /* PCI Interrupt Line Register         */
-#define PCIIPR                0x3D   /* PCI Interrupt Pin Register          */
-#define PCIMGR                0x3E   /* PCI Min_Gnt Register                */
-#define PCIMLR                0x3F   /* PCI Max_Lat Register                */
+#define PCIILR                0x3F   /* PCI Interrupt Line Register         */
+#define PCIIPR                0x3E   /* PCI Interrupt Pin Register          */
+#define PCIMGR                0x3D   /* PCI Min_Gnt Register                */
+#define PCIMLR                0x3C   /* PCI Max_Lat Register                */
 #define PMCAPID               0x40   /* Power Management Capability ID      */
 #define PMNEXT                0x41   /* Power Management Next Capability
                                         Pointer                             */
@@ -81,41 +86,41 @@
 /*
  * bit definitions for PCICSR lower half (Command Register)
  */
-#define PCICSR_IO           (1 << 0)    /* if set: device responds to I/O space accesses */
-#define PCICSR_MEMORY       (1 << 1)    /* if set: device responds to memory space accesses */
-#define PCICSR_MASTER       (1 << 2)    /* if set: device is master */
-#define PCICSR_SPECIAL      (1 << 3)    /* if set: device reacts on special cycles */
-#define PCICSR_MEMWI        (1 << 4)    /* if set: device deals with memory write and invalidate */
-#define PCICSR_VGA_SNOOP    (1 << 5)    /* if set: capable of palette snoop */
-#define PCICSR_PERR         (1 << 6)    /* if set: reacts to parity errors */
-#define PCICSR_STEPPING     (1 << 7)    /* if set: stepping enabled */
-#define PCICSR_SERR         (1 << 8)    /* if set: SERR pin enabled */
-#define PCICSR_FAST_BTOB_E  (1 << 9)    /* if set: fast back-to-back enabled */
-#define PCICSR_INT_DISABLE  (1 << 10)   /* if set: disable interrupts from this device */
+#define PCICR_IO           (1 << 0)    /* if set: device responds to I/O space accesses */
+#define PCICR_MEMORY       (1 << 1)    /* if set: device responds to memory space accesses */
+#define PCICR_MASTER       (1 << 2)    /* if set: device is master */
+#define PCICR_SPECIAL      (1 << 3)    /* if set: device reacts on special cycles */
+#define PCICR_MEMWI        (1 << 4)    /* if set: device deals with memory write and invalidate */
+#define PCICR_VGA_SNOOP    (1 << 5)    /* if set: capable of palette snoop */
+#define PCICR_PERR         (1 << 6)    /* if set: reacts to parity errors */
+#define PCICR_STEPPING     (1 << 7)    /* if set: stepping enabled */
+#define PCICR_SERR         (1 << 8)    /* if set: SERR pin enabled */
+#define PCICR_FAST_BTOB_E  (1 << 9)    /* if set: fast back-to-back enabled */
+#define PCICR_INT_DISABLE  (1 << 10)   /* if set: disable interrupts from this device */
 /*
  * bit definitions for PCICSR upper half (Status Register)
  */
-#define PCICSR_INTERRUPT    (1 << 3)    /* device requested interrupt */
-#define PCICSR_CAPABILITIES (1 << 4)    /* if set, capabilities pointer is valid */
-#define PCICSR_66MHZ        (1 << 5)    /* 66 MHz capable */
-#define PCICSR_UDF          (1 << 6)    /* UDF supported */
-#define PCICSR_FAST_BTOB    (1 << 7)    /* Fast back-to-back enabled */
-#define PCICSR_DPARITY_ERROR    (1 << 8)    /* data parity error detected */
+#define PCISR_INTERRUPT    (1 << 3)    /* device requested interrupt */
+#define PCISR_CAPABILITIES (1 << 4)    /* if set, capabilities pointer is valid */
+#define PCISR_66MHZ        (1 << 5)    /* 66 MHz capable */
+#define PCISR_UDF          (1 << 6)    /* UDF supported */
+#define PCISR_FAST_BTOB    (1 << 7)    /* Fast back-to-back enabled */
+#define PCISR_DPARITY_ERROR    (1 << 8)    /* data parity error detected */
 
-#define PCICSR_T_ABORT_S    (1 << 11)   /* target abort signaled */
-#define PCICSR_T_ABORT_R    (1 << 12)   /* target abort received */
-#define PCICSR_M_ABORT_R    (1 << 13)   /* master abort received */
-#define PCICSR_S_ERROR_S    (1 << 14)   /* system error signaled */
-#define PCICSR_PARITY_ERR   (1 << 15)   /* data parity error */
+#define PCISR_T_ABORT_S    (1 << 11)   /* target abort signaled */
+#define PCISR_T_ABORT_R    (1 << 12)   /* target abort received */
+#define PCISR_M_ABORT_R    (1 << 13)   /* master abort received */
+#define PCISR_S_ERROR_S    (1 << 14)   /* system error signaled */
+#define PCISR_PARITY_ERR   (1 << 15)   /* data parity error */
 
 /* Header type 1 (PCI-to-PCI bridges) */
-#define PCI_PRIMARY_BUS        0x18  /* Primary bus number */
-#define PCI_SECONDARY_BUS      0x19  /* Secondary bus number */
-#define PCI_SUBORDINATE_BUS    0x1A  /* Highest bus number behind the bridge */
-#define PCI_SEC_LATENCY_TIMER  0x1B  /* Latency timer for secondary interface */
+#define PCI_PRIMARY_BUS        0x1B  /* Primary bus number */
+#define PCI_SECONDARY_BUS      0x1A  /* Secondary bus number */
+#define PCI_SUBORDINATE_BUS    0x19  /* Highest bus number behind the bridge */
+#define PCI_SEC_LATENCY_TIMER  0x18  /* Latency timer for secondary interface */
 #define PCI_IO_BASE            0x1C  /* I/O range behind the bridge */
 #define PCI_IO_LIMIT           0x1D
-#define PCI_SEC_STATUS         0x1E  /* Secondary status register, only bit 14 used */
+#define PCI_SEC_STATUS         0x1C  /* Secondary status register, only bit 14 used */
 #define PCI_MEMORY_BASE        0x20  /* Memory range behind */
 #define PCI_MEMORY_LIMIT       0x22
 #define PCI_PREF_MEMORY_BASE   0x24  /* Prefetchable memory range behind */
@@ -186,28 +191,28 @@ typedef struct                       /* structure of address conversion     */
 /* PCI configuration space macros */
 
 /* register 0x00 macros */
-#define PCI_VENDOR_ID(i)    swpw((uint16_t)(((i) & 0xffff0000) >> 16))
-#define PCI_DEVICE_ID(i)    swpw((uint16_t) ((i) & 0xffff))
+#define PCI_DEVICE_ID(i)    (uint16_t)(((i) & 0xffff0000) >> 16)
+#define PCI_VENDOR_ID(i)    (uint16_t) ((i) & 0xffff)
 
 /* register 0x04 macros */
 #define PCI_STATUS(i)       ((i) & 0xffff)
 #define PCI_COMMAND(i)      (((i) >> 16) & 0xffff)
 
-/* register 0x08 macros */
-#define PCI_CLASS_CODE(i)   ((swpl((i)) & 0xff000000) >> 24)
-#define PCI_SUBCLASS(i)     ((swpl((i)) & 0xffff0000) >> 16)
-#define PCI_PROG_IF(i)      ((swpl((i)) & 0x0000ff00) >> 8)
-#define PCI_REVISION_ID(i)  ((swpl((i)) & 0x000000ff))
+/* register 0x08 macros (use on little endian value!) */
+#define PCI_CLASS_CODE(i)   (((i) & 0x00ff0000) >> 16)
+#define PCI_SUBCLASS(i)     (((i) & 0x0000ff00) >> 8)
+#define PCI_PROG_IF(i)      (((i) & 0x000000ff) >> 0)
+#define PCI_REVISION_ID(i)  (((i) & 0xff000000) >> 24)
 
 /* register 0x0c macros */
-#define PCI_BIST(i)         ((swpl((i)) & 0xff000000) >> 24)
-#define PCI_HEADER_TYPE(i)  ((swpl((i)) & 0x00ff0000) >> 16)
-#define PCI_LAT_TIMER(i)    ((swpl((i)) & 0x0000ff00) >> 8)
-#define PCI_CACHELINE_SIZE(i)   ((swpl((i)) & 0x000000ff))
+#define PCI_BIST(i)         (((i) & 0xff000000) >> 24)
+#define PCI_HEADER_TYPE(i)  (((i) & 0x00ff0000) >> 16)
+#define PCI_LAT_TIMER(i)    (((i) & 0x0000ff00) >> 8)
+#define PCI_CACHELINE_SIZE(i)   (((i) & 0x000000ff))
 
 /* register 0x2c macros */
-#define PCI_SUBSYS_ID(i)    (((i) & 0xffff0000) >> 16)
-#define PCI_SUBSYS_VID(i)   (((i) & 0xffff))
+#define PCI_SUBSYS_ID(i)    ((i) & 0xffff0000) >> 16)
+#define PCI_SUBSYS_VID(i)   ((i) & 0xffff))
 
 /* register 0x34 macros */
 #define PCI_CAPABILITIES(i) ((i) & 0xff)
@@ -350,4 +355,6 @@ extern int32_t wrapper_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);
 #define PCI_DEVICE_FROM_HANDLE(h)           (((h) & 0xf8) >> 3)
 #define PCI_FUNCTION_FROM_HANDLE(h)         (((h) & 0x7))
 
+extern void pci_dump_registers(int32_t handle);
+
 #endif /* _PCI_H_ */

include/pci_errata.h

@@ -0,0 +1,11 @@
+#ifndef PCI_ERRATA_H
+#define PCI_ERRATA_H
+
+#include <stdint.h>
+
+
+extern void chip_errata_135(void);
+extern void chip_errata_055(int32_t handle);
+
+#endif // PCI_ERRATA_H
+

include/radeonfb.h

@@ -10,6 +10,9 @@
 #include "i2c-algo-bit.h"
 #include "util.h"			/* for swpX() */
 #include "wait.h"
+#include "video.h"
+
+// #define RADEON_TILING
 
 //#include "radeon_theatre.h"
 
@@ -23,7 +26,7 @@
 #define RADEON_MMIOSIZE   0x80000
 
 #define RADEON_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1))
-  
+
 #define ATY_RADEON_LCD_ON	0x00000001
 #define ATY_RADEON_CRT_ON	0x00000002
 
@@ -39,50 +42,50 @@
  */
 enum radeon_family
 {
-	CHIP_FAMILY_UNKNOW,
-	CHIP_FAMILY_LEGACY,
-	CHIP_FAMILY_RADEON,
-	CHIP_FAMILY_RV100,
-	CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/
-	CHIP_FAMILY_RV200,
-	CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
-	CHIP_FAMILY_R200,
-	CHIP_FAMILY_RV250,
-	CHIP_FAMILY_RS300,    /* Radeon 9000 IGP */
-	CHIP_FAMILY_RV280,
-	CHIP_FAMILY_R300,
-	CHIP_FAMILY_R350,
-	CHIP_FAMILY_RV350,
-	CHIP_FAMILY_RV380,    /* RV370/RV380/M22/M24 */
-	CHIP_FAMILY_R420,     /* R420/R423/M18 */
-	CHIP_FAMILY_LAST,
+    CHIP_FAMILY_UNKNOW,
+    CHIP_FAMILY_LEGACY,
+    CHIP_FAMILY_RADEON,
+    CHIP_FAMILY_RV100,
+    CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/
+    CHIP_FAMILY_RV200,
+    CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
+    CHIP_FAMILY_R200,
+    CHIP_FAMILY_RV250,
+    CHIP_FAMILY_RS300,    /* Radeon 9000 IGP */
+    CHIP_FAMILY_RV280,
+    CHIP_FAMILY_R300,
+    CHIP_FAMILY_R350,
+    CHIP_FAMILY_RV350,
+    CHIP_FAMILY_RV380,    /* RV370/RV380/M22/M24 */
+    CHIP_FAMILY_R420,     /* R420/R423/M18 */
+    CHIP_FAMILY_LAST,
 };
 
 #define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100)  || \
-				 ((rinfo)->family == CHIP_FAMILY_RV200)  || \
-				 ((rinfo)->family == CHIP_FAMILY_RS100)  || \
-				 ((rinfo)->family == CHIP_FAMILY_RS200)  || \
-				 ((rinfo)->family == CHIP_FAMILY_RV250)  || \
-				 ((rinfo)->family == CHIP_FAMILY_RV280)  || \
-				 ((rinfo)->family == CHIP_FAMILY_RS300))
+    ((rinfo)->family == CHIP_FAMILY_RV200)  || \
+    ((rinfo)->family == CHIP_FAMILY_RS100)  || \
+    ((rinfo)->family == CHIP_FAMILY_RS200)  || \
+    ((rinfo)->family == CHIP_FAMILY_RV250)  || \
+    ((rinfo)->family == CHIP_FAMILY_RV280)  || \
+    ((rinfo)->family == CHIP_FAMILY_RS300))
 
 
 #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300)  || \
-				((rinfo)->family == CHIP_FAMILY_RV350) || \
-				((rinfo)->family == CHIP_FAMILY_R350)  || \
-				((rinfo)->family == CHIP_FAMILY_RV380) || \
-				((rinfo)->family == CHIP_FAMILY_R420))
+    ((rinfo)->family == CHIP_FAMILY_RV350) || \
+    ((rinfo)->family == CHIP_FAMILY_R350)  || \
+    ((rinfo)->family == CHIP_FAMILY_RV380) || \
+    ((rinfo)->family == CHIP_FAMILY_R420))
 
 /*
  * Chip flags
  */
 enum radeon_chip_flags
 {
-	CHIP_FAMILY_MASK	= 0x0000ffffUL,
-	CHIP_FLAGS_MASK		= 0xffff0000UL,
-	CHIP_IS_MOBILITY	= 0x00010000UL,
-	CHIP_IS_IGP		= 0x00020000UL,
-	CHIP_HAS_CRTC2		= 0x00040000UL,	
+    CHIP_FAMILY_MASK	= 0x0000ffffUL,
+    CHIP_FLAGS_MASK		= 0xffff0000UL,
+    CHIP_IS_MOBILITY	= 0x00010000UL,
+    CHIP_IS_IGP		= 0x00020000UL,
+    CHIP_HAS_CRTC2		= 0x00040000UL,
 };
 
 /*
@@ -90,9 +93,9 @@ enum radeon_chip_flags
  */
 enum radeon_errata
 {
-	CHIP_ERRATA_R300_CG		= 0x00000001,
-	CHIP_ERRATA_PLL_DUMMYREADS	= 0x00000002,
-	CHIP_ERRATA_PLL_DELAY		= 0x00000004,
+    CHIP_ERRATA_R300_CG		= 0x00000001,
+    CHIP_ERRATA_PLL_DUMMYREADS	= 0x00000002,
+    CHIP_ERRATA_PLL_DELAY		= 0x00000004,
 };
 
 
@@ -101,12 +104,12 @@ enum radeon_errata
  */
 enum radeon_montype
 {
-	MT_NONE = 0,
-	MT_CRT,		/* CRT */
-	MT_LCD,		/* LCD */
-	MT_DFP,		/* DVI */
-	MT_CTV,		/* composite TV */
-	MT_STV		/* S-Video out */
+    MT_NONE = 0,
+    MT_CRT,		/* CRT */
+    MT_LCD,		/* LCD */
+    MT_DFP,		/* DVI */
+    MT_CTV,		/* composite TV */
+    MT_STV		/* S-Video out */
 };
 
 /*
@@ -114,11 +117,11 @@ enum radeon_montype
  */
 enum ddc_type
 {
-	ddc_none,
-	ddc_monid,
-	ddc_dvi,
-	ddc_vga,
-	ddc_crt2,
+    ddc_none,
+    ddc_monid,
+    ddc_dvi,
+    ddc_vga,
+    ddc_crt2,
 };
 
 /*
@@ -126,11 +129,11 @@ enum ddc_type
  */
 enum conn_type
 {
-	conn_none,
-	conn_proprietary,
-	conn_crt,
-	conn_DVI_I,
-	conn_DVI_D,
+    conn_none,
+    conn_proprietary,
+    conn_crt,
+    conn_DVI_I,
+    conn_DVI_D,
 };
 
 
@@ -139,11 +142,11 @@ enum conn_type
  */
 struct pll_info
 {
-	int32_t ppll_max;
-	int32_t ppll_min;
-	int32_t sclk, mclk;
-	int32_t ref_div;
-	int32_t ref_clk;
+    int32_t ppll_max;
+    int32_t ppll_min;
+    int32_t sclk, mclk;
+    int32_t ref_div;
+    int32_t ref_clk;
 };
 
 
@@ -155,120 +158,120 @@ struct pll_info
  */
 struct radeon_regs
 {
-	/* Common registers */
-	uint32_t		ovr_clr;
-	uint32_t		ovr_wid_left_right;
-	uint32_t		ovr_wid_top_bottom;
-	uint32_t		ov0_scale_cntl;
-	uint32_t		mpp_tb_config;
-	uint32_t		mpp_gp_config;
-	uint32_t		subpic_cntl;
-	uint32_t		viph_control;
-	uint32_t		i2c_cntl_1;
-	uint32_t		gen_int32_t_cntl;
-	uint32_t		cap0_trig_cntl;
-	uint32_t		cap1_trig_cntl;
-	uint32_t		bus_cntl;
-	uint32_t		surface_cntl;
-	uint32_t		bios_5_scratch;
+    /* Common registers */
+    uint32_t		ovr_clr;
+    uint32_t		ovr_wid_left_right;
+    uint32_t		ovr_wid_top_bottom;
+    uint32_t		ov0_scale_cntl;
+    uint32_t		mpp_tb_config;
+    uint32_t		mpp_gp_config;
+    uint32_t		subpic_cntl;
+    uint32_t		viph_control;
+    uint32_t		i2c_cntl_1;
+    uint32_t		gen_int32_t_cntl;
+    uint32_t		cap0_trig_cntl;
+    uint32_t		cap1_trig_cntl;
+    uint32_t		bus_cntl;
+    uint32_t		surface_cntl;
+    uint32_t		bios_5_scratch;
 
-	/* Other registers to save for VT switches or driver load/unload */
-	uint32_t		dp_datatype;
-	uint32_t		rbbm_soft_reset;
-	uint32_t		clock_cntl_index;
-	uint32_t		amcgpio_en_reg;
-	uint32_t		amcgpio_mask;
+    /* Other registers to save for VT switches or driver load/unload */
+    uint32_t		dp_datatype;
+    uint32_t		rbbm_soft_reset;
+    uint32_t		clock_cntl_index;
+    uint32_t		amcgpio_en_reg;
+    uint32_t		amcgpio_mask;
 
-	/* Surface/tiling registers */
-	uint32_t		surf_lower_bound[8];
-	uint32_t		surf_upper_bound[8];
-	uint32_t		surf_info[8];
+    /* Surface/tiling registers */
+    uint32_t		surf_lower_bound[8];
+    uint32_t		surf_upper_bound[8];
+    uint32_t		surf_info[8];
 
-	/* CRTC registers */
-	uint32_t		crtc_gen_cntl;
-	uint32_t		crtc_ext_cntl;
-	uint32_t		dac_cntl;
-	uint32_t		crtc_h_total_disp;
-	uint32_t		crtc_h_sync_strt_wid;
-	uint32_t		crtc_v_total_disp;
-	uint32_t		crtc_v_sync_strt_wid;
-	uint32_t		crtc_offset;
-	uint32_t		crtc_offset_cntl;
-	uint32_t		crtc_pitch;
-	uint32_t		disp_merge_cntl;
-	uint32_t		grph_buffer_cntl;
-	uint32_t		crtc_more_cntl;
+    /* CRTC registers */
+    uint32_t		crtc_gen_cntl;
+    uint32_t		crtc_ext_cntl;
+    uint32_t		dac_cntl;
+    uint32_t		crtc_h_total_disp;
+    uint32_t		crtc_h_sync_strt_wid;
+    uint32_t		crtc_v_total_disp;
+    uint32_t		crtc_v_sync_strt_wid;
+    uint32_t		crtc_offset;
+    uint32_t		crtc_offset_cntl;
+    uint32_t		crtc_pitch;
+    uint32_t		disp_merge_cntl;
+    uint32_t		grph_buffer_cntl;
+    uint32_t		crtc_more_cntl;
 
-	/* CRTC2 registers */
-	uint32_t		crtc2_gen_cntl;
-	uint32_t		dac2_cntl;
-	uint32_t		disp_output_cntl;
-	uint32_t		disp_hw_debug;
-	uint32_t		disp2_merge_cntl;
-	uint32_t		grph2_buffer_cntl;
-	uint32_t		crtc2_h_total_disp;
-	uint32_t		crtc2_h_sync_strt_wid;
-	uint32_t		crtc2_v_total_disp;
-	uint32_t		crtc2_v_sync_strt_wid;
-	uint32_t		crtc2_offset;
-	uint32_t		crtc2_offset_cntl;
-	uint32_t		crtc2_pitch;
+    /* CRTC2 registers */
+    uint32_t		crtc2_gen_cntl;
+    uint32_t		dac2_cntl;
+    uint32_t		disp_output_cntl;
+    uint32_t		disp_hw_debug;
+    uint32_t		disp2_merge_cntl;
+    uint32_t		grph2_buffer_cntl;
+    uint32_t		crtc2_h_total_disp;
+    uint32_t		crtc2_h_sync_strt_wid;
+    uint32_t		crtc2_v_total_disp;
+    uint32_t		crtc2_v_sync_strt_wid;
+    uint32_t		crtc2_offset;
+    uint32_t		crtc2_offset_cntl;
+    uint32_t		crtc2_pitch;
 
-	/* Flat panel regs */
-	uint32_t 	fp_crtc_h_total_disp;
-	uint32_t		fp_crtc_v_total_disp;
-	uint32_t		fp_gen_cntl;
-	uint32_t		fp2_gen_cntl;
-	uint32_t		fp_h_sync_strt_wid;
-	uint32_t		fp2_h_sync_strt_wid;
-	uint32_t		fp_horz_stretch;
-	uint32_t		fp_panel_cntl;
-	uint32_t		fp_v_sync_strt_wid;
-	uint32_t		fp2_v_sync_strt_wid;
-	uint32_t		fp_vert_stretch;
-	uint32_t		lvds_gen_cntl;
-	uint32_t		lvds_pll_cntl;
-	uint32_t		tmds_crc;
-	uint32_t		tmds_transmitter_cntl;
+    /* Flat panel regs */
+    uint32_t 	fp_crtc_h_total_disp;
+    uint32_t		fp_crtc_v_total_disp;
+    uint32_t		fp_gen_cntl;
+    uint32_t		fp2_gen_cntl;
+    uint32_t		fp_h_sync_strt_wid;
+    uint32_t		fp2_h_sync_strt_wid;
+    uint32_t		fp_horz_stretch;
+    uint32_t		fp_panel_cntl;
+    uint32_t		fp_v_sync_strt_wid;
+    uint32_t		fp2_v_sync_strt_wid;
+    uint32_t		fp_vert_stretch;
+    uint32_t		lvds_gen_cntl;
+    uint32_t		lvds_pll_cntl;
+    uint32_t		tmds_crc;
+    uint32_t		tmds_transmitter_cntl;
 
-	/* Computed values for PLL */
-	uint32_t		dot_clock_freq;
-	uint32_t		pll_output_freq;
-	int32_t		feedback_div;
-	int32_t		post_div;	
+    /* Computed values for PLL */
+    uint32_t		dot_clock_freq;
+    uint32_t		pll_output_freq;
+    int32_t		feedback_div;
+    int32_t		post_div;
 
-	/* PLL registers */
-	uint32_t		ppll_div_3;
-	uint32_t		ppll_ref_div;
-	uint32_t		vclk_ecp_cntl;
-	uint32_t		clk_cntl_index;
-	uint32_t		htotal_cntl;
+    /* PLL registers */
+    uint32_t		ppll_div_3;
+    uint32_t		ppll_ref_div;
+    uint32_t		vclk_ecp_cntl;
+    uint32_t		clk_cntl_index;
+    uint32_t		htotal_cntl;
 
-	/* Computed values for PLL2 */
-	uint32_t		dot_clock_freq_2;
-	uint32_t		pll_output_freq_2;
-	int32_t		feedback_div_2;
-	int32_t		post_div_2;
+    /* Computed values for PLL2 */
+    uint32_t		dot_clock_freq_2;
+    uint32_t		pll_output_freq_2;
+    int32_t		feedback_div_2;
+    int32_t		post_div_2;
 
-	/* PLL2 registers */
-	uint32_t		p2pll_ref_div;
-	uint32_t		p2pll_div_0;
-	uint32_t		htotal_cntl2;
+    /* PLL2 registers */
+    uint32_t		p2pll_ref_div;
+    uint32_t		p2pll_div_0;
+    uint32_t		htotal_cntl2;
 };
 
 struct panel_info
 {
-	int32_t xres, yres;
-	int32_t valid;
-	int32_t clock;
-	int32_t hOver_plus, hSync_width, hblank;
-	int32_t vOver_plus, vSync_width, vblank;
-	int32_t hAct_high, vAct_high, int32_terlaced;
-	int32_t pwr_delay;
-	int32_t use_bios_dividers;
-	int32_t ref_divider;
-	int32_t post_divider;
-	int32_t fbk_divider;
+    int32_t xres, yres;
+    int32_t valid;
+    int32_t clock;
+    int32_t hOver_plus, hSync_width, hblank;
+    int32_t vOver_plus, vSync_width, vblank;
+    int32_t hAct_high, vAct_high, int32_terlaced;
+    int32_t pwr_delay;
+    int32_t use_bios_dividers;
+    int32_t ref_divider;
+    int32_t post_divider;
+    int32_t fbk_divider;
 };
 
 struct radeonfb_info;
@@ -276,186 +279,186 @@ struct radeonfb_info;
 #ifdef CONFIG_FB_RADEON_I2C
 struct radeon_i2c_chan
 {
-	struct radeonfb_info *rinfo;
-	uint32_t ddc_reg;
-	struct i2c_adapter adapter;
-	struct i2c_algo_bit_data algo;
+    struct radeonfb_info *rinfo;
+    uint32_t ddc_reg;
+    struct i2c_adapter adapter;
+    struct i2c_algo_bit_data algo;
 };
 #endif
 
 enum radeon_pm_mode
 {
-	radeon_pm_none	= 0,			/* Nothing supported */
-	radeon_pm_d2	= 0x00000001,	/* Can do D2 state */
-	radeon_pm_off	= 0x00000002,	/* Can resume from D3 cold */
+    radeon_pm_none	= 0,			/* Nothing supported */
+    radeon_pm_d2	= 0x00000001,	/* Can do D2 state */
+    radeon_pm_off	= 0x00000002,	/* Can resume from D3 cold */
 };
 
 typedef struct
 {
-	uint8_t table_revision;
-	uint8_t table_size;
-	uint8_t tuner_type;
-	uint8_t audio_chip;
-	uint8_t product_id;
-	uint8_t tuner_voltage_teletext_fm;
-	uint8_t i2s_config; /* configuration of the sound chip */
-	uint8_t video_decoder_type;
-	uint8_t video_decoder_host_config;
-	uint8_t input[5];
+    uint8_t table_revision;
+    uint8_t table_size;
+    uint8_t tuner_type;
+    uint8_t audio_chip;
+    uint8_t product_id;
+    uint8_t tuner_voltage_teletext_fm;
+    uint8_t i2s_config; /* configuration of the sound chip */
+    uint8_t video_decoder_type;
+    uint8_t video_decoder_host_config;
+    uint8_t input[5];
 } _MM_TABLE;
 
 struct radeonfb_info
 {
-	int32_t handle;     /* PCI BIOS, must be 1st place */
-	int32_t big_endian; /* PCI BIOS */
-	
-	uint32_t cursor_x;
-	uint32_t cursor_y;
-	int32_t cursor_show;
-	uint32_t cursor_start;
-	uint32_t cursor_end;
-	int32_t cursor_fg;
-	int32_t cursor_bg;
+    int32_t handle;     /* PCI BIOS, must be 1st place */
+    int32_t big_endian; /* PCI BIOS */
 
-	int32_t fifo_slots;       /* Free slots in the FIFO (64 max)   */
+    uint32_t cursor_x;
+    uint32_t cursor_y;
+    int32_t cursor_show;
+    uint32_t cursor_start;
+    uint32_t cursor_end;
+    int32_t cursor_fg;
+    int32_t cursor_bg;
 
-	/* Computed values for Radeon */
-	uint32_t dp_gui_master_cntl_clip;
-	uint32_t trans_color;
+    int32_t fifo_slots;       /* Free slots in the FIFO (64 max)   */
 
-	/* Saved values for ScreenToScreenCopy */
-	int32_t xdir;
-	int32_t ydir;
+    /* Computed values for Radeon */
+    uint32_t dp_gui_master_cntl_clip;
+    uint32_t trans_color;
 
-	/* ScanlineScreenToScreenColorExpand support */
-	int32_t scanline_h;
-	int32_t scanline_words;
-	int32_t scanline_bpp;     /* Only used for ImageWrite */
+    /* Saved values for ScreenToScreenCopy */
+    int32_t xdir;
+    int32_t ydir;
 
-	/* Saved values for DashedTwoPoint32_tLine */
-	int32_t dashLen;
-	uint32_t dashPattern;
-	int32_t dash_fg;
-	int32_t dash_bg;
+    /* ScanlineScreenToScreenColorExpand support */
+    int32_t scanline_h;
+    int32_t scanline_words;
+    int32_t scanline_bpp;     /* Only used for ImageWrite */
 
-	struct fb_info *info;
+    /* Saved values for DashedTwoPoint32_tLine */
+    int32_t dashLen;
+    uint32_t dashPattern;
+    int32_t dash_fg;
+    int32_t dash_bg;
 
-	struct radeon_regs state;
-	struct radeon_regs init_state;
+    struct fb_info *info;
 
-	uint8_t name[50];
+    struct radeon_regs state;
+    struct radeon_regs init_state;
 
-	uint32_t io_base_phys;
-	uint32_t mmio_base_phys;
-	uint32_t fb_base_phys;
+    uint8_t name[50];
 
-	void *io_base;
-	void *mmio_base;
-	void *fb_base;
-	
-	uint32_t fb_local_base;
-	uint32_t fb_offset;
-	
-	uint32_t bios_seg_phys;
-	void *bios_seg;
-	int32_t fp_bios_start;
+    uint32_t io_base_phys;
+    uint32_t mmio_base_phys;
+    uint32_t fb_base_phys;
 
-	struct
-	{
-		uint8_t red;
-		uint8_t green;
-		uint8_t blue;
-		uint8_t pad;
-	} palette[256];
+    void *io_base;
+    void *mmio_base;
+    void *fb_base;
 
-	int32_t	chipset;
-	uint8_t family;
-	uint8_t rev;
-	int32_t errata;
-	uint32_t video_ram;
-	uint32_t mapped_vram;
-	int32_t vram_width;
-	int32_t vram_ddr;
+    uint32_t fb_local_base;
+    uint32_t fb_offset;
 
-	int32_t pitch, bpp, depth;
+    uint32_t bios_seg_phys;
+    void *bios_seg;
+    int32_t fp_bios_start;
 
-	int32_t has_CRTC2;
-	int32_t is_mobility;
-	int32_t is_IGP;
-	int32_t reversed_DAC;
-	int32_t reversed_TMDS;
-	struct panel_info	panel_info;
-	int32_t mon1_type;
-	uint8_t *mon1_EDID;
-	struct fb_videomode	*mon1_modedb;
-	int32_t mon1_dbsize;
-	int32_t mon2_type;
-	uint8_t *mon2_EDID;
+    struct
+    {
+        uint8_t red;
+        uint8_t green;
+        uint8_t blue;
+        uint8_t pad;
+    } palette[256];
 
-	uint32_t dp_gui_master_cntl;
+    int32_t	chipset;
+    uint8_t family;
+    uint8_t rev;
+    int32_t errata;
+    uint32_t video_ram;
+    uint32_t mapped_vram;
+    int32_t vram_width;
+    int32_t vram_ddr;
 
-	struct pll_info bios_pll;
-	struct pll_info pll;
+    int32_t pitch, bpp, depth;
 
-	uint32_t save_regs[100];
-	int32_t asleep;
-	int32_t lock_blank;
-	int32_t dynclk;
-	int32_t no_schedule;
-	enum radeon_pm_mode	pm_mode;
+    int32_t has_CRTC2;
+    int32_t is_mobility;
+    int32_t is_IGP;
+    int32_t reversed_DAC;
+    int32_t reversed_TMDS;
+    struct panel_info panel_info;
+    int32_t mon1_type;
+    uint8_t *mon1_EDID;
+    struct fb_videomode	*mon1_modedb;
+    int32_t mon1_dbsize;
+    int32_t mon2_type;
+    uint8_t *mon2_EDID;
 
-	/* Timer used for delayed LVDS operations */
-	int32_t lvds_timer;
-	uint32_t pending_lvds_gen_cntl;
+    uint32_t dp_gui_master_cntl;
+
+    struct pll_info bios_pll;
+    struct pll_info pll;
+
+    uint32_t save_regs[100];
+    int32_t asleep;
+    int32_t lock_blank;
+    int32_t dynclk;
+    int32_t no_schedule;
+    enum radeon_pm_mode	pm_mode;
+
+    /* Timer used for delayed LVDS operations */
+    int32_t lvds_timer;
+    uint32_t pending_lvds_gen_cntl;
 
 #ifdef CONFIG_FB_RADEON_I2C
-	struct radeon_i2c_chan i2c[4];
+    struct radeon_i2c_chan i2c[4];
 #endif
 
-  /* Texture */
-  
-	int32_t RenderInited3D;
-	int32_t tilingEnabled;
-	void *RenderTex;
-	uint32_t RenderTexOffset;
-	int32_t RenderTexSize;
-	void (*RenderCallback)(struct radeonfb_info *rinfo);
-	uint32_t RenderTimeout;
-	uint32_t dst_pitch_offset;
+    /* Texture */
+
+    int32_t RenderInited3D;
+    int32_t tilingEnabled;
+    void *RenderTex;
+    uint32_t RenderTexOffset;
+    int32_t RenderTexSize;
+    void (*RenderCallback)(struct radeonfb_info *rinfo);
+    uint32_t RenderTimeout;
+    uint32_t dst_pitch_offset;
 
 
 #ifdef _NOT_USED_
-	/* Video & theatre */
+    /* Video & theatre */
 
-	TheatrePtr theatre;
+    TheatrePtr theatre;
 
-	int32_t MM_TABLE_valid;
-	_MM_TABLE MM_TABLE;
+    int32_t MM_TABLE_valid;
+    _MM_TABLE MM_TABLE;
 
-	int32_t RageTheatreCrystal;
-	int32_t RageTheatreTunerPort;
-	int32_t RageTheatreCompositePort;
-	int32_t RageTheatreSVideoPort;
-	int32_t tunerType;
-	
-	int32_t videoStatus;
-	int32_t encoding;
-	int32_t overlay_deint32_terlacing_method;
-	int32_t video_stream_active;
-	int32_t capture_vbi_data;
-	int32_t v;
-	void *videoLinear;
-	int32_t videoLinearSize;
-	struct
-	{
-		uint32_t y,u,v;
-	} videoLinearOffset;
+    int32_t RageTheatreCrystal;
+    int32_t RageTheatreTunerPort;
+    int32_t RageTheatreCompositePort;
+    int32_t RageTheatreSVideoPort;
+    int32_t tunerType;
+
+    int32_t videoStatus;
+    int32_t encoding;
+    int32_t overlay_deint32_terlacing_method;
+    int32_t video_stream_active;
+    int32_t capture_vbi_data;
+    int32_t v;
+    void *videoLinear;
+    int32_t videoLinearSize;
+    struct
+    {
+        uint32_t y,u,v;
+    } videoLinearOffset;
 #endif /* _NOT_USED_ */
-	
-	int32_t dec_hue;
-	int32_t dec_saturation;
-	int32_t dec_contrast;
-	int32_t dec_brightness;
+
+    int32_t dec_hue;
+    int32_t dec_saturation;
+    int32_t dec_contrast;
+    int32_t dec_brightness;
 };
 
 #define PRIMARY_MONITOR(rinfo)	(rinfo->mon1_type)
@@ -473,7 +476,7 @@ struct radeonfb_info
  */
 static inline void _radeon_msleep(struct radeonfb_info *rinfo, uint32_t ms)
 {
-	wait_ms(ms);
+    wait_ms(ms);
 }
 
 #define radeon_msleep(ms)		_radeon_msleep(rinfo,ms)
@@ -485,17 +488,17 @@ extern uint32_t __INPLL(struct radeonfb_info *rinfo, uint32_t addr);
 extern void __OUTPLL(struct radeonfb_info *rinfo, uint32_t index, uint32_t val);
 extern void __OUTPLLP(struct radeonfb_info *rinfo, uint32_t index, uint32_t val, uint32_t mask);
 
-#define INREG8(addr)		*((uint8_t *)(rinfo->mmio_base + addr))
-#define INREG16(addr)		swpw(*(uint16_t *)(rinfo->mmio_base + addr))
-#define INREG(addr)			swpl(*(uint32_t *)(rinfo->mmio_base + addr))
-#define OUTREG8(addr, val)	(*((uint8_t *)(rinfo->mmio_base + addr)) = val)
-#define OUTREG16(addr, val)	(*((uint16_t *)(rinfo->mmio_base + addr)) = swpw(val))
-#define OUTREG(addr, val)	(*((uint32_t *)(rinfo->mmio_base + addr)) = swpl(val))
+#define INREG8(addr)		*((volatile uint8_t *)(rinfo->mmio_base + addr))
+#define INREG16(addr)		swpw(*(volatile uint16_t *)(rinfo->mmio_base + addr))
+#define INREG(addr)			swpl(*(volatile uint32_t *)(rinfo->mmio_base + addr))
+#define OUTREG8(addr, val)	(*((volatile uint8_t *)(rinfo->mmio_base + addr)) = val)
+#define OUTREG16(addr, val)	(*((volatile uint16_t *)(rinfo->mmio_base + addr)) = swpw((uint32_t) val))
+#define OUTREG(addr, val)	(*((volatile uint32_t *)(rinfo->mmio_base + addr)) = swpl((uint32_t) val))
 
 extern int32_t *tab_funcs_pci;
-#define BIOS_IN8(v)		(* ((uint8_t *) rinfo->bios_seg_phys + v))
-#define BIOS_IN16(v)	(swpw(*(uint16_t *) ((uint8_t *) rinfo->bios_seg_phys + v)))
-#define BIOS_IN32(v)	(swpl(*(uint32_t *) ((uint8_t *) rinfo->bios_seg_phys + v)))
+#define BIOS_IN8(v)		(* ((volatile uint8_t *) rinfo->bios_seg_phys + v))
+#define BIOS_IN16(v)	(swpw(*(volatile uint16_t *) ((uint8_t *) rinfo->bios_seg_phys + v)))
+#define BIOS_IN32(v)	(swpl(*(volatile uint32_t *) ((uint8_t *) rinfo->bios_seg_phys + v)))
 
 #define ADDRREG(addr)			((volatile uint32_t *)(rinfo->mmio_base + (addr)))
 #define OUTREGP(addr, val, mask)	_OUTREGP(rinfo, addr, val, mask)
@@ -509,14 +512,14 @@ extern int32_t *tab_funcs_pci;
 
 static inline uint32_t radeon_get_dstbpp(uint16_t depth)
 {
-	switch(depth)
-	{
-		case 8: return DST_8BPP;
-		case 15: return DST_15BPP;
-		case 16: return DST_16BPP;
-		case 32: return DST_32BPP;
-		default: return 0;
-	}
+    switch(depth)
+    {
+        case 8: return DST_8BPP;
+        case 15: return DST_15BPP;
+        case 16: return DST_16BPP;
+        case 32: return DST_32BPP;
+        default: return 0;
+    }
 }
 
 /* I2C Functions */
@@ -532,11 +535,11 @@ extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);
 
 /* Monitor probe functions */
 extern void radeon_probe_screens(struct radeonfb_info *rinfo,
-									const char *monitor_layout, int ignore_edid);
+                                 const char *monitor_layout, int32_t ignore_edid);
 extern void radeon_check_modes(struct radeonfb_info *rinfo, struct mode_option *resolution);
-extern int radeon_match_mode(struct radeonfb_info *rinfo,
-									struct fb_var_screeninfo *dest,
-									const struct fb_var_screeninfo *src);
+extern int32_t radeon_match_mode(struct radeonfb_info *rinfo,
+                             struct fb_var_screeninfo *dest,
+                             const struct fb_var_screeninfo *src);
 
 /* Video functions */
 void RADEONResetVideo(struct radeonfb_info *rinfo);
@@ -549,7 +552,7 @@ void RADEONVIP_reset(struct radeonfb_info *rinfo);
 void RADEONInitVideo(struct radeonfb_info *rinfo);
 void RADEONShutdownVideo(struct radeonfb_info *rinfo);
 int32_t RADEONPutVideo(struct radeonfb_info *rinfo, int32_t src_x, int32_t src_y, int32_t src_w, int32_t src_h,
-						int32_t drw_x, int32_t drw_y, int32_t drw_w, int32_t drw_h);
+                       int32_t drw_x, int32_t drw_y, int32_t drw_w, int32_t drw_h);
 void RADEONStopVideo(struct radeonfb_info *rinfo, int32_t cleanup);
 
 /* Theatre functions */
@@ -572,7 +575,7 @@ extern void RADEONVIP_reset(struct radeonfb_info *rinfo);
 
 /* Accel functions */
 
-extern void radeon_wait_for_fifo_function(struct radeonfb_info *rinfo, int entries);
+extern void radeon_wait_for_fifo_function(struct radeonfb_info *rinfo, int32_t entries);
 extern void radeon_engine_flush(struct radeonfb_info *rinfo);
 extern void radeon_engine_reset(struct radeonfb_info *rinfo);
 extern void radeon_engine_restore(struct radeonfb_info *rinfo);
@@ -582,71 +585,71 @@ extern void radeon_wait_for_idle_mmio(struct radeonfb_info *rinfo);
 #define radeon_engine_idle() radeon_wait_for_idle_mmio(rinfo)
 
 #define radeon_wait_for_fifo(rinfo, entries)				\
-do															\
-{															\
-	if (rinfo->fifo_slots < entries)						\
-		radeon_wait_for_fifo_function(rinfo, entries);		\
-	rinfo->fifo_slots -= entries;							\
-} while (0)
+    do															\
+    {															\
+        if (rinfo->fifo_slots < entries)						\
+            radeon_wait_for_fifo_function(rinfo, entries);		\
+        rinfo->fifo_slots -= entries;							\
+    } while (0)
 
-static inline int radeonfb_sync(struct fb_info *info)
+static inline int32_t radeonfb_sync(struct fb_info *info)
 {
-	struct radeonfb_info *rinfo = info->par;
-	radeon_engine_idle();
-	return 0;
+    struct radeonfb_info *rinfo = info->par;
+    radeon_engine_idle();
+    return 0;
 }
 
 extern void radeon_restore_accel_state_mmio(struct fb_info *info);
-extern void radeon_setup_for_solid_fill(struct fb_info *info, int color, int rop, unsigned int planemask);
-extern void radeon_subsequent_solid_fill_rect_mmio(struct fb_info *info, int x, int y, int w, int h);
-extern void radeon_setup_for_solid_line_mmio(struct fb_info *info, int color, int rop, unsigned int planemask);
-extern void radeon_subsequent_solid_hor_vert_line_mmio(struct fb_info *info, int x, int y, int len, int dir);   
-extern void radeon_subsequent_solid_two_point_line_mmio(struct fb_info *info, int xa, int ya, int xb,
-														int yb, int flags);  
-extern void radeon_setup_for_dashed_line_mmio(struct fb_info *info, int fg, int bg,
-												int rop, unsigned int planemask, int length, unsigned char *pattern);
+extern void radeon_setup_for_solid_fill(struct fb_info *info, int32_t color, int32_t rop, uint32_t planemask);
+extern void radeon_subsequent_solid_fill_rect_mmio(struct fb_info *info, int32_t x, int32_t y, int32_t w, int32_t h);
+extern void radeon_setup_for_solid_line_mmio(struct fb_info *info, int32_t color, int32_t rop, uint32_t planemask);
+extern void radeon_subsequent_solid_hor_vert_line_mmio(struct fb_info *info, int32_t x, int32_t y, int32_t len, int32_t dir);
+extern void radeon_subsequent_solid_two_point_line_mmio(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb,
+                                                        int32_t yb, int32_t flags);
+extern void radeon_setup_for_dashed_line_mmio(struct fb_info *info, int32_t fg, int32_t bg,
+                                              int32_t rop, uint32_t planemask, int32_t length, unsigned char *pattern);
 extern void radeon_subsequent_dashed_two_point_line_mmio(struct fb_info *info,
-            				int xa, int ya, int xb, int yb, int flags, int phase);  
+                                                         int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t flags, int32_t phase);
 extern void radeon_setup_for_screen_to_screen_copy_mmio(struct fb_info *info,
-            				int xdir, int ydir, int rop, unsigned int planemask, int trans_color);
+                                                        int32_t xdir, int32_t ydir, int32_t rop, uint32_t planemask, int32_t trans_color);
 extern void radeon_subsequent_screen_to_screen_copy_mmio(struct fb_info *info,
-            				int xa, int ya, int xb, int yb, int w, int h);   
+                                                         int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h);
 extern void radeon_screen_to_screen_copy_mmio(struct fb_info *info,
-            				int xa, int ya, int xb, int yb, int w, int h, int rop);
+                                              int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h, int32_t rop);
 extern void radeon_setup_for_mono_8x8_pattern_fill_mmio(struct fb_info *info,
-            			int patternx, int patterny, int fg, int bg, int rop, unsigned int planemask);
+                                                        int32_t patternx, int32_t patterny, int32_t fg, int32_t bg, int32_t rop, uint32_t planemask);
 extern void radeon_subsequent_mono_8x8_pattern_fill_rect_mmio(struct fb_info *info,
-            				int patternx, int patterny, int x, int y, int w, int h);
-extern void radeon_setup_for_scanline_cpu_to_screen_color_expand_fill_mmio(struct fb_info *info, 
-            				int fg, int bg, int rop, unsigned int planemask);
+                                                              int32_t patternx, int32_t patterny, int32_t x, int32_t y, int32_t w, int32_t h);
+extern void radeon_setup_for_scanline_cpu_to_screen_color_expand_fill_mmio(struct fb_info *info,
+                                                                           int32_t fg, int32_t bg, int32_t rop, uint32_t planemask);
 extern void radeon_subsequent_scanline_cpu_to_screen_color_expand_fill_mmio(struct fb_info *info,
-            				int x, int y, int w, int h, int skipleft);
-extern void radeon_subsequent_scanline_mmio(struct fb_info *info, unsigned long *buf);
+                                                                            int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft);
+extern void radeon_subsequent_scanline_mmio(struct fb_info *info, uint32_t *buf);
 extern void radeon_setup_for_scanline_image_write_mmio(struct fb_info *info,
-            							int rop, unsigned int planemask, int trans_color, int bpp);
+                                                       int32_t rop, uint32_t planemask, int32_t trans_color, int32_t bpp);
 extern void radeon_subsequent_scanline_image_write_rect_mmio(struct fb_info *info,
-            				int x, int y, int w, int h, int skipleft);  
+                                                             int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft);
 extern void radeon_set_clipping_rectangle_mmio(struct fb_info *info,
-            				int xa, int ya, int xb, int yb);
+                                               int32_t xa, int32_t ya, int32_t xb, int32_t yb);
 extern void radeon_disable_clipping_mmio(struct fb_info *info);
 
-extern int32_t radeon_setup_for_cpu_to_screen_alpha_texture_mmio(struct fb_info *info, 
-           					int op, int red, int green, int blue,
-							int alpha, int maskFormat, int dstFormat,
-							uint8_t *alphaPtr, int alphaPitch,
-							int width, int height, int32_t flags);
+extern int32_t radeon_setup_for_cpu_to_screen_alpha_texture_mmio(struct fb_info *info,
+                                                                 int32_t op, int32_t red, int32_t green, int32_t blue,
+                                                                 int32_t alpha, int32_t maskFormat, int32_t dstFormat,
+                                                                 uint8_t *alphaPtr, int32_t alphaPitch,
+                                                                 int32_t width, int32_t height, int32_t flags);
 extern int32_t radeon_setup_for_cpu_to_screen_texture_mmio(struct fb_info *info, int32_t op,
-							uint32_t srcFormat, uint32_t dstFormat,
-							uint8_t *texPtr, int32_t texPitch,
-							int32_t width, int32_t height, int32_t flags);
+                                                           uint32_t srcFormat, uint32_t dstFormat,
+                                                           uint8_t *texPtr, int32_t texPitch,
+                                                           int32_t width, int32_t height, int32_t flags);
 extern void radeon_subsequent_cpu_to_screen_texture_mmio(struct fb_info *info,
-            				int32_t dstx, int32_t dsty,
-							int32_t srcx, int32_t srcy,
-							int32_t width, int32_t height);
+                                                         int32_t dstx, int32_t dsty,
+                                                         int32_t srcx, int32_t srcy,
+                                                         int32_t width, int32_t height);
 /* Cursor functions */
-extern void radeon_set_cursor_colors(struct fb_info *info, int bg, int fg);
-extern void radeon_set_cursor_position(struct fb_info *info, int x, int y);
-extern void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsigned short *data, int zoom);
+extern void radeon_set_cursor_colors(struct fb_info *info, int32_t bg, int32_t fg);
+extern void radeon_set_cursor_position(struct fb_info *info, int32_t x, int32_t y);
+extern void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsigned short *data, int32_t zoom);
 extern void radeon_hide_cursor(struct fb_info *info);
 extern void radeon_show_cursor(struct fb_info *info);
 extern long radeon_cursor_init(struct fb_info *info);
@@ -654,8 +657,8 @@ extern long radeon_cursor_init(struct fb_info *info);
 /* Other functions */
 extern int32_t radeon_screen_blank(struct radeonfb_info *rinfo, int32_t blank, int32_t mode_switch);
 extern void radeon_write_mode(struct radeonfb_info *rinfo, struct radeon_regs *mode, int32_t reg_only);
-int radeonfb_setcolreg(unsigned regno, unsigned red, unsigned green,
-    					unsigned blue, unsigned transp, struct fb_info *info);
+int32_t radeonfb_setcolreg(uint32_t regno, uint32_t red, uint32_t green,
+                       uint32_t blue, uint32_t transp, struct fb_info *info);
 extern int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent);
 extern void radeonfb_pci_unregister(void);
 

include/s19reader.h

@@ -43,5 +43,6 @@ typedef err_t (*memcpy_callback_t)(uint8_t *dst, uint8_t *src, size_t length);
 
 extern void srec_execute(char *filename);
 extern err_t read_srecords(char *filename, void **start_address, uint32_t *actual_length, memcpy_callback_t callback);
+extern err_t srec_memcpy(uint8_t *dst, uint8_t *src, size_t n);
 
 #endif /* _S19READER_H_ */

include/util.h

@@ -22,8 +22,8 @@
  *      Author: mfro
  */
 
-#ifndef UTIL_H_
-#define UTIL_H_
+#ifndef _UTIL_H_
+#define _UTIL_H_
 
 #include <bas_types.h>
 
@@ -35,18 +35,7 @@
  */
 static inline uint16_t swpw(uint16_t w)
 {
-	register uint32_t result asm("d0");
-	__asm__ __volatile__
-	(
-		"lea		%[input],a0\n\t"				\
-		"mvz.b	1(a0),%[output]\n\t"			\
-		"lsl.l	#8,%[output]\n\t"				\
-		"move.b	(a0),%[output]\n\t"			\
-		:	[output] "=d" (result)	/* output */
-		:	[input] "o" (w)			/* input */
-		: "cc", "a0", "memory"	/* clobbered */
-	);
-	return result;
+    return (w << 8) | (w >> 8);
 }
 
 /*
@@ -56,23 +45,8 @@ static inline uint16_t swpw(uint16_t w)
  */
 static inline uint32_t swpl(uint32_t l)
 {
-	register uint32_t result asm("d0");
-
-	__asm__ __volatile__
-	(
-		"lea		%[input],a0\n\t"				\
-		"mvz.b	3(a0),%[output]\n\t"			\
-		"lsl.l	#8,%[output]\n\t"				\
-		"move.b	2(a0),%[output]\n\t"			\
-		"lsl.l	#8,%[output]\n\t"				\
-		"move.b	1(a0),%[output]\n\t"			\
-		"lsl.l	#8,%[output]\n\t"				\
-		"move.b	(a0),%[output]\n\t"			\
-		:	[output] "=d" (result)	/* output */
-		:	[input] "o" (l)			/* input */
-		: "cc", "a0", "memory"	/* clobbered */
-	);
-	return result;
+    return ((l & 0xff000000) >> 24) | ((l & 0x00ff0000) >> 8) |
+            ((l & 0x0000ff00) << 8) | (l << 24);
 }
 
 
@@ -144,10 +118,10 @@ __extension__                             \
 #define regsafe_call(addr)                         \
 __extension__                                      \
 ({__asm__ volatile ("lea     -60(sp),sp\n\t"       \
-					"movem.l d0-d7/a0-a6,(sp)");   \
+                    "movem.l d0-d7/a0-a6,(sp)");   \
   ((void (*) (void)) addr)();                      \
   __asm__ volatile ("movem.l (sp),d0-d7/a0-a6\n\t" \
-					"lea     60(sp),sp");          \
+                    "lea     60(sp),sp");          \
 })
 
 

include/version.h

@@ -28,8 +28,8 @@
  * increment version number for release
  */
 
-#define MAJOR_VERSION	0
-#define MINOR_VERSION	88
+#define MAJOR_VERSION   0
+#define MINOR_VERSION   93
 
 
 #endif /* VERSION_H_ */

include/video.h

@@ -3,6 +3,7 @@
 
 #include <bas_types.h>
 #include "bas_printf.h"
+#define CONFIG_FB_RADEON_I2C
 
 extern void video_init(void);
 

include/wait.h

@@ -55,4 +55,7 @@ extern bool waitfor(uint32_t us, checker_func condition);
 extern uint32_t get_timer(void);
 extern void wait_ms(uint32_t ms);
 
+#define US_TO_TIMER(a) ((a) * SYSCLK) / 1000000UL
+#define TIMER_TO_US(a) ((a) * 1000000UL) / SYSCLK)
+
 #endif /* _WAIT_H_ */

include/x86emu.h

@@ -122,9 +122,9 @@ struct X86EMU
 
     uint64_t        cur_cycles;
 
-	unsigned int	cur_mod:2;
-	unsigned int	cur_rl:3;
-	unsigned int	cur_rh:3;
+    unsigned int	cur_mod:2;
+    unsigned int	cur_rl:3;
+    unsigned int	cur_rh:3;
     uint32_t        cur_offset;
 
     uint8_t         (*emu_rdb)(struct X86EMU *, uint32_t addr);
@@ -145,14 +145,14 @@ struct X86EMU
 };
 
 
-void	X86EMU_init_default(struct X86EMU *);
+void X86EMU_init_default(struct X86EMU *);
 
 /* decode.c */
 
-void 	X86EMU_exec(struct X86EMU *);
-void	X86EMU_exec_call(struct X86EMU *, uint16_t, uint16_t);
-void	X86EMU_exec_intr(struct X86EMU *, uint8_t);
-void 	X86EMU_halt_sys(struct X86EMU *);
+void X86EMU_exec(struct X86EMU *);
+void X86EMU_exec_call(struct X86EMU *, uint16_t, uint16_t);
+void X86EMU_exec_intr(struct X86EMU *, uint8_t);
+void X86EMU_halt_sys(struct X86EMU *);
 
 
 #endif /* __X86EMU_X86EMU_H */

include/x86pcibios.h

@@ -25,5 +25,27 @@ enum {
     SET_FAILED          = 0x88,
 	BUFFER_TOO_SMALL	= 0x89
 };
+
+extern int x86_pcibios_handler(struct X86EMU *emu);
+
+
+#define USE_SDRAM
+#define DIRECT_ACCESS
+
+#define MEM_WB(where, what) emu->emu_wrb(emu, where, what)
+#define MEM_WW(where, what) emu->emu_wrw(emu, where, what)
+#define MEM_WL(where, what) emu->emu_wrl(emu, where, what)
+
+#define MEM_RB(where) emu->emu_rdb(emu, where)
+#define MEM_RW(where) emu->emu_rdw(emu, where)
+#define MEM_RL(where) emu->emu_rdl(emu, where)
+
+#define PCI_VGA_RAM_IMAGE_START     0xC0000
+#define PCI_RAM_IMAGE_START         0xD0000
+#define SYS_BIOS                    0xF0000
+#define SIZE_EMU                    0x100000
+#define BIOS_MEM                    0x0UL
+
+
 #endif /* PCI_BIOS_H */
 

kbd/ikbd.c

@@ -26,6 +26,8 @@
 //#include "hardware.h"
 #include "ikbd.h"
 
+#include "debug.h"
+
 // atari ikbd stuff
 #define IKBD_STATE_JOYSTICK_EVENT_REPORTING  0x01
 #define IKBD_STATE_MOUSE_Y_BOTTOM            0x02
@@ -213,7 +215,18 @@ void ikbd_handle_input(unsigned char cmd)
     }
 }
 
-void ikbd_poll(void) {
+/*
+ * FIXME: temporarily provide function prototypes for unimplemented functions here to make compiler happy
+ */
+
+extern int GetTimer(int);
+extern int CheckTimer(int);
+extern void EnableIO(void);
+extern void DisableIO(void);
+extern int SPI(int);
+
+void ikbd_poll(void)
+{
     static int mtimer = 0;
     if (CheckTimer(mtimer))
     {

nutil/s19header.c

@@ -378,8 +378,3 @@ static err_t verify(uint8_t *dst, uint8_t *src, uint32_t length)
 
     return OK;
 }
-
-void srec_execute(char *flasher_filename)
-{
-}
-

pci/ehci-hcd.c

@@ -30,15 +30,7 @@
 #include "ehci.h"
 #include "pci.h"
 
-#define DBG_EHCI
-#ifdef DBG_EHCI
-#define dbg(format, arg...) xprintf("DEBUG %s(): " format, __FUNCTION__, ## arg)
-#else
-#define dbg(format, arg...) do {} while (0)
-#endif /* DBG_EHCI */
-#define err(format, arg...) xprintf("ERROR %s(): " format, __FUNCTION__, ## arg)
-#define info(format, arg...) xprintf("INFO %s(): " format, __FUNCTION__, ## arg)
-
+#include "debug.h"
 
 static char ehci_inited;
 static int rootdev;
@@ -1068,7 +1060,7 @@ int ehci_usb_lowlevel_init(long handle, const struct pci_device_id *ent, void **
     ehci_writel(&gehci.hcor->or_asynclistaddr, (uint32_t) gehci.qh_list - gehci.dma_offset);
     reg = ehci_readl(&gehci.hccr->cr_hcsparams);
     gehci.descriptor->hub.bNbrPorts = HCS_N_PORTS(reg);
-    info("Register %x NbrPorts %d\r\n", reg, gehci.descriptor->hub.bNbrPorts);
+    xprintf("Register %x NbrPorts %d\r\n", reg, gehci.descriptor->hub.bNbrPorts);
 
     /* Port Indicators */
     if (HCS_INDICATOR(reg))
@@ -1101,7 +1093,7 @@ int ehci_usb_lowlevel_init(long handle, const struct pci_device_id *ent, void **
     wait(5 * 1000);
 
     reg = HC_VERSION(ehci_readl(&gehci.hccr->cr_capbase));
-    info("USB EHCI host controller version %x.%02x\r\n", reg >> 8, reg & 0xff);
+    xprintf("USB EHCI host controller version %x.%02x\r\n", reg >> 8, reg & 0xff);
 
     /* turn on interrupts */
     pci_hook_interrupt(handle, handle_usb_interrupt, &gehci);

pci/ohci-hcd.c

@@ -49,19 +49,14 @@
 #include "pci.h"
 #include "interrupts.h"
 
+// // #define DEBUG
+#include "debug.h"
+
 #undef OHCI_USE_NPS         /* force NoPowerSwitching mode */
 
 #undef OHCI_VERBOSE_DEBUG	/* not always helpful */
 #undef OHCI_FILL_TRACE
 
-#define DEBUG_OHCI
-#ifdef DEBUG_OHCI
-#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
-#else
-#define dbg(format, arg...) do { ; } while (0)
-#endif /* DEBUG_OHCI */
-#define err(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
-
 #include "usb.h"
 #include "ohci.h"
 #include "util.h"			/* for endian conversions */
@@ -79,7 +74,7 @@
 /*
  * do a longword read from addr and byteswap the result
  */
-inline uint32_t readl(volatile uint32_t *addr)
+static inline uint32_t readl(volatile uint32_t *addr)
 {
     uint32_t res;
 
@@ -92,7 +87,7 @@ inline uint32_t readl(volatile uint32_t *addr)
 /*
  * byteswap value and write it to address
  */
-inline void writel(uint32_t value, uint32_t *address)
+static inline void writel(uint32_t value, uint32_t *address)
 {
     // dbg("writing %08x to %08x\r\n", value, address);
     * (volatile uint32_t *) address = swpl(value);

pci/pci.c

@@ -26,6 +26,7 @@
 
 #include <MCF5475.h>
 #include "pci.h"
+#include "pci_errata.h"
 #include "bas_types.h"
 #include "bas_printf.h"
 #include "bas_string.h"
@@ -33,13 +34,8 @@
 #include "interrupts.h"
 #include "wait.h"
 
-//#define DEBUG_PCI
-#ifdef DEBUG_PCI
-#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
-#else
-#define dbg(format, arg...) do { ; } while (0)
-#endif /* DEBUG_PCI */
-#define err(format, arg...) do { xprintf("ERROR: %s(): " format, __FUNCTION__, ##arg); } while (0)
+// #define DEBUG
+#include "debug.h"
 
 #define pci_config_wait() do { __asm__ __volatile("tpf" ::: "memory"); } while (0)
 
@@ -52,25 +48,25 @@ static struct pci_class
     char *description;
 } pci_classes[] =
 {
-    { 0x00, "device was built prior definition of the class code field" },
-    { 0x01, "Mass Storage Controller" },
-    { 0x02, "Network Controller" },
-    { 0x03, "Display Controller" },
-    { 0x04, "Multimedia Controller" },
-    { 0x05, "Memory Controller" },
-    { 0x06, "Bridge Device" },
-    { 0x07, "Simple Communication Controller" },
-    { 0x08, "Base System Peripherial" },
-    { 0x09, "Input Device" },
-    { 0x0a, "Docking Station" },
-    { 0x0b, "Processor" },
-    { 0x0c, "Serial Bus Controller" },
-    { 0x0d, "Wireless Controller" },
-    { 0x0e, "Intelligent I/O Controller" },
-    { 0x0f, "Satellite Communication Controller" },
-    { 0x10, "Encryption/Decryption Controller" },
-    { 0x11, "Data Acquisition and Signal Processing Controller" },
-    { 0xff, "Device does not fit any defined class" },
+{ 0x00, "device was built prior definition of the class code field" },
+{ 0x01, "Mass Storage Controller" },
+{ 0x02, "Network Controller" },
+{ 0x03, "Display Controller" },
+{ 0x04, "Multimedia Controller" },
+{ 0x05, "Memory Controller" },
+{ 0x06, "Bridge Device" },
+{ 0x07, "Simple Communication Controller" },
+{ 0x08, "Base System Peripherial" },
+{ 0x09, "Input Device" },
+{ 0x0a, "Docking Station" },
+{ 0x0b, "Processor" },
+{ 0x0c, "Serial Bus Controller" },
+{ 0x0d, "Wireless Controller" },
+{ 0x0e, "Intelligent I/O Controller" },
+{ 0x0f, "Satellite Communication Controller" },
+{ 0x10, "Encryption/Decryption Controller" },
+{ 0x11, "Data Acquisition and Signal Processing Controller" },
+{ 0xff, "Device does not fit any defined class" },
 };
 static int num_pci_classes = sizeof(pci_classes) / sizeof(struct pci_class);
 
@@ -98,65 +94,6 @@ struct pci_interrupt
 #define MAX_INTERRUPTS  (NUM_CARDS * 3)
 static struct pci_interrupt interrupts[MAX_INTERRUPTS];
 
-static inline __attribute__((aligned(16))) void chip_errata_135(void)
-{
-    /*
-     * Errata type: Silicon
-     * Affected component: PCI
-     * Description: When core PCI transactions that involve writes to configuration or I/O space
-     * are followed by a core line access to line addresses 0x4 and 0xC, core access
-     * to the XL bus can hang.
-     * Workaround: Prevent PCI configuration and I/O writes from being followed by the described
-     * line access by the core by generating a known good XL bus transaction after
-     * the PCI transaction.
-     * Create a dummy function which is called immediately after each of the affected
-     * transactions. There are three requirements for this dummy function.
-     * 1. The function must be aligned to a 16-byte boundary.
-     * 2. The function must contain a dummy write to a location on the XL bus,
-     * preferably one with no side effects.
-     * 3. The function must be longer than 32 bytes. If it is not, the function should
-     * be padded with 16- or 48-bit TPF instructions placed after the end of
-     * the function (after the RTS instruction) such that the length is longer
-     * than 32 bytes.
-     */
-
-     __asm__ __volatile(
-        "       .extern __MBAR          \n\t"
-        "       clr.l   d0              \n\t"
-        "       move.l  d0,__MBAR+0xF0C \n\t"       /* Must use direct addressing. write to EPORT module */
-                                                    /* xlbus -> slavebus -> eport, writing '0' to register */
-                                                    /* has no effect */
-        "       rts                     \n\t"
-        "       tpf.l   #0x0            \n\t"
-        "       tpf.l   #0x0            \n\t"
-        "       tpf.l   #0x0            \n\t"
-        "       tpf.l   #0x0            \n\t"
-        "       tpf.l   #0x0            \n\t"
-        ::: "d0", "memory");
-}
-
-static inline void chip_errata_055(int32_t handle)
-{
-    uint32_t dummy;
-
-    return;     /* test */
-
-    /* initiate PCI configuration access to device */
-    MCF_PCI_PCICAR = MCF_PCI_PCICAR_E |         /* enable configuration access special cycle */
-            MCF_PCI_PCICAR_BUSNUM(3) |          /* note: invalid bus number */
-            MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | /* device number, devices 0 - 9 are reserved */
-            MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |  /* function number */
-            MCF_PCI_PCICAR_DWORD(0);
-
-    /* issue a dummy read to an unsupported bus number (will fail) */
-    dummy =  * (volatile uint32_t *) PCI_IO_OFFSET; /* access device */
-
-    /* silently clear the PCI errors we produced just now */
-    MCF_PCI_PCIISR = 0xffffffff;     /* clear all errors */
-    MCF_PCI_PCIGSCR = MCF_PCI_PCIGSCR_PE | MCF_PCI_PCIGSCR_SE;
-
-    (void) dummy;
-}
 
 /*
  * Although this pragma stuff should work according to the GCC docs, it doesn't seem to
@@ -176,13 +113,13 @@ int32_t pci_get_interrupt_cause(void)
     dbg("");
     while ((handle = *hdl++) != -1)
     {
-        uint16_t command_register = swpw(pci_read_config_word(handle, PCICR));
-        uint16_t status_register = swpw(pci_read_config_word(handle, PCISR));
+        uint16_t command_register = swpw(pci_read_config_word(handle, PCI_LANESWAP_W(PCICR)));
+        uint16_t status_register = swpw(pci_read_config_word(handle, PCI_LANESWAP_W(PCISR)));
 
         /*
          * ...to see which device caused the interrupt
          */
-        if ((status_register & PCICSR_INTERRUPT) && !(command_register & PCICSR_INT_DISABLE))
+        if ((status_register & PCISR_INTERRUPT) && !(command_register & PCICR_INT_DISABLE))
         {
             /* device has interrupts enabled and has an active interrupt, so its probably ours */
 
@@ -348,7 +285,7 @@ uint16_t pci_read_config_word(int32_t handle, int offset)
 
     NOP();
 
-    value = * (volatile uint16_t *) PCI_IO_OFFSET + (offset & 2);
+    value = * (volatile uint16_t *) (PCI_IO_OFFSET + (offset & 2));
 
     NOP();
 
@@ -366,10 +303,10 @@ uint8_t pci_read_config_byte(int32_t handle, int offset)
 
     /* initiate PCI configuration access to device */
     MCF_PCI_PCICAR = MCF_PCI_PCICAR_E |             /* enable configuration access special cycle */
-        MCF_PCI_PCICAR_BUSNUM(PCI_BUS_FROM_HANDLE(handle)) |
-        MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) |     /* device number, devices 0 - 9 are reserved */
-        MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |  /* function number */
-        MCF_PCI_PCICAR_DWORD(offset / 4);
+            MCF_PCI_PCICAR_BUSNUM(PCI_BUS_FROM_HANDLE(handle)) |
+            MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) |     /* device number, devices 0 - 9 are reserved */
+            MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |  /* function number */
+            MCF_PCI_PCICAR_DWORD(offset / 4);
 
     NOP();
 
@@ -393,17 +330,15 @@ int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t value)
 {
     /* initiate PCI configuration access to device */
 
-    dbg("initiate configuration access\r\n");
-
     MCF_PCI_PCICAR = MCF_PCI_PCICAR_E |             /* enable configuration access special cycle */
-        MCF_PCI_PCICAR_BUSNUM(PCI_BUS_FROM_HANDLE(handle)) |
-        MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) |     /* device number, devices 0 - 9 are reserved */
-        MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |  /* function number */
-        MCF_PCI_PCICAR_DWORD(offset / 4);
+            MCF_PCI_PCICAR_BUSNUM(PCI_BUS_FROM_HANDLE(handle)) |
+            MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) |     /* device number, devices 0 - 9 are reserved */
+            MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |  /* function number */
+            MCF_PCI_PCICAR_DWORD(offset / 4);
 
+    chip_errata_135();
     NOP();
 
-    dbg("access device\r\n");
     * (volatile uint32_t *) PCI_IO_OFFSET = value;  /* access device */
 
     dbg("chip errata\r\n");
@@ -411,7 +346,6 @@ int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t value)
 
     NOP();
 
-    dbg("finish config space access cycle\r\n");
     /* finish configuration space access cycle */
     MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E;
 
@@ -431,12 +365,14 @@ int32_t pci_write_config_word(int32_t handle, int offset, uint16_t value)
             MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) |
             MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |
             MCF_PCI_PCICAR_DWORD(offset / 4);
+
     chip_errata_135();
 
     NOP();
 
     * (volatile uint16_t *) (PCI_IO_OFFSET + (offset & 2)) = value;
     chip_errata_135();
+    NOP();
 
     /* finish configuration space access cycle */
     MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E;
@@ -463,7 +399,8 @@ int32_t pci_write_config_byte(int32_t handle, int offset, uint8_t value)
     * (volatile uint8_t *) (PCI_IO_OFFSET + (offset & 3)) = value;
     chip_errata_135();
 
-    __asm__ __volatile__("tpf" ::: "memory");
+    NOP();
+
 
     /* finish configuration space access cycle */
     MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E;
@@ -472,6 +409,7 @@ int32_t pci_write_config_byte(int32_t handle, int offset, uint8_t value)
 
     return PCI_SUCCESSFUL;
 }
+
 /*
  * pci_get_resource
  *
@@ -519,11 +457,11 @@ int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index)
             uint8_t htr;
 
             handle = PCI_HANDLE(bus, device, 0);
-            value = pci_read_config_longword(handle, PCIIDR);
+            value = swpl(pci_read_config_longword(handle, PCIIDR));
             if (value != 0xffffffff)    /* we have a device at this position */
             {
                 if (vendor_id == 0xffff ||
-                    (PCI_VENDOR_ID(value) == vendor_id && PCI_DEVICE_ID(value) == device_id))
+                        (PCI_VENDOR_ID(value) == vendor_id && PCI_DEVICE_ID(value) == device_id))
                 {
                     if (n == index)
                     {
@@ -537,18 +475,18 @@ int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index)
                  * Check to see if it is a multi-function device. We need to look "behind" it
                  * for the other functions in that case.
                  */
-                if ((htr = pci_read_config_byte(handle, PCIHTR)) & 0x80)
+                if ((htr = pci_read_config_byte(handle, PCI_LANESWAP_B(PCIHTR))) & 0x80)
                 {
                     /* yes, this is a multi-function device, look for more functions */
 
                     for (function = 1; function < 8; function++)
                     {
                         handle = PCI_HANDLE(bus, device, function);
-                        value = pci_read_config_longword(handle, PCIIDR);
+                        value = swpl(pci_read_config_longword(handle, PCIIDR));
                         if (value != 0xffffffff)    /* device found */
                         {
                             if (vendor_id == 0xffff ||
-                                ((PCI_VENDOR_ID(value) == vendor_id) && (PCI_DEVICE_ID(value) == device_id)))
+                                    ((PCI_VENDOR_ID(value) == vendor_id) && (PCI_DEVICE_ID(value) == device_id)))
                             {
                                 if (n == index)
                                 {
@@ -565,6 +503,34 @@ int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index)
     return PCI_DEVICE_NOT_FOUND;
 }
 
+static bool match_classcode(uint32_t handle, uint32_t classcode)
+{
+    uint8_t find_mask = (classcode >> 24) & 0xff;
+    uint32_t value = swpl(pci_read_config_longword(handle, PCICCR));
+    int i;
+
+    classcode &= 0x00ffffff;
+    value >>= 8;                /* shift away revision id */
+
+    //dbg("classcode=0x%08x, value=0x%08x\r\n", classcode, value);
+
+    for (i = 0; i < 3; i++)        /* loop through mask */
+    {
+        if ((find_mask >> i) & 1)
+        {
+            //dbg("compare 0x%02x against 0x%02x\r\n", value  & 0xff, classcode & 0xff);
+            if ((value & 0xff) != (classcode & 0xff))
+                return false;
+            //dbg("match\r\n");
+            classcode >>= 8;
+        }
+        value >>= 8;
+        //dbg("value=0x%08x\r\n", value);
+    }
+    dbg("return true\r\n");
+    return true;
+}
+
 /*
  * pci_find_classcode(uint32_t classcode, int index)
  *
@@ -575,78 +541,23 @@ int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index)
  */
 int32_t pci_find_classcode(uint32_t classcode, int index)
 {
-    uint16_t bus;
-    uint16_t device;
-    uint16_t function = 0;
-    uint16_t n = 0;
-    int32_t handle;
+    int i;
+    uint32_t handle;
+    int n = 0;
 
-    for (bus = 0; bus < 2; bus++)
+    for (i = 0; (handle = handles[i]) != -1; i++)
     {
-        for (device = 10; device < 31; device++)
+        dbg("handle=0x%x, n=%d, index=%d\r\n", handle, n, index);
+        if (match_classcode(handle, classcode))
         {
-            uint32_t value;
-            uint8_t htr;
-
-            handle = PCI_HANDLE(bus, device, 0);
-            dbg("check handle %d\r\n", handle);
-
-            value = pci_read_config_longword(handle, PCIIDR);
-
-            if (value != 0xffffffff)    /* device found */
-            {
-                value = pci_read_config_longword(handle, PCICCR);
-
-                dbg("classcode to search for=%x\r\n", classcode);
-                dbg("PCI_CLASSCODE found=%x\r\n", PCI_CLASS_CODE(value));
-                dbg("PCI_SUBCLASS found=%x\r\n", PCI_SUBCLASS(value));
-                dbg("PCI_PROG_IF found=%x\r\n", PCI_PROG_IF(value));
-
-                if ((classcode & (1 << 26) ? ((PCI_CLASS_CODE(value) == (classcode & 0xff))) : true) &&
-                    (classcode & (1 << 25) ? ((PCI_SUBCLASS(value) == ((classcode & 0xff00) >> 8))) : true) &&
-                    (classcode & (1 << 24) ? ((PCI_PROG_IF(value) == ((classcode & 0xff0000) >> 16))) : true))
-                {
-                    if (n == index)
-                    {
-                        return handle;
-                    }
-                    n++;
-                }
-
-                /*
-                * there is a device at this position, but not the one we are looking for.
-                * Check to see if it is a multi-function device. We need to look "behind" it
-                * for the other functions in that case.
-                */
-                if ((htr = pci_read_config_byte(handle, PCIHTR)) & 0x80)
-                {
-                    /* yes, this is a multi-function device, look for more functions */
-
-                    for (function = 1; function < 8; function++)
-                    {
-                        handle = PCI_HANDLE(bus, device, function);
-                        value = pci_read_config_longword(handle, PCIIDR);
-
-                        if (value != 0xffffffff)    /* device found */
-                        {
-                            value = pci_read_config_longword(handle, PCICCR);
-
-                            if ((classcode & (1 << 26) ? ((PCI_CLASS_CODE(value) == (classcode & 0xff))) : true) &&
-                                (classcode & (1 << 25) ? ((PCI_SUBCLASS(value) == ((classcode & 0xff00) >> 8))) : true) &&
-                                (classcode & (1 << 24) ? ((PCI_PROG_IF(value) == ((classcode & 0xff0000) >> 16))) : true))
-                            {
-                                if (n == index)
-                                {
-                                    return handle;
-                                }
-                                n++;
-                            }
-                        }
-                    }
-                }
-            }
+            if (n == index)
+                return handle;
+            else
+                n++;
         }
     }
+
+    dbg("not found\r\n");
     return PCI_DEVICE_NOT_FOUND;
 }
 
@@ -892,9 +803,9 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
      * disable device
      */
 
-    cr = swpw(pci_read_config_word(handle, PCICSR));
+    cr = swpw(pci_read_config_word(handle, PCI_LANESWAP_W(PCICR)));
     cr &= ~3;   /* disable device response to address */
-    pci_write_config_word(handle, PCICSR, swpw(cr));
+    pci_write_config_word(handle, PCI_LANESWAP_W(PCICR), swpw(cr));
 
     int barnum = 0;
 
@@ -922,8 +833,8 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
             if (IS_PCI_MEM_BAR(address))
             {
                 /* adjust base address to card's alignment requirements */
-                int size = ~(address & 0xfffffff0) + 1;
-                dbg("device 0x%x: BAR[%d] requests %d bytes of memory\r\n", handle, i / 4, size);
+                size_t size = ~(address & 0xfffffff0) + 1;
+                dbg("device 0x%02x: BAR[%d] requests %ld kBytes of memory\r\n", handle, i / 4, size / 1024);
 
                 /* calculate a valid map adress with alignment requirements */
                 address = (mem_address + size - 1) & ~(size - 1);
@@ -935,7 +846,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
                 value = swpl(pci_read_config_longword(handle, PCIBAR0 + i)) & ~1;
 
                 dbg("set PCIBAR%d on device 0x%02x to 0x%08x\r\n",
-                        i / 4, handle, value);
+                    i / 4, handle, value);
 
                 /* fill resource descriptor */
                 rd->next = sizeof(struct pci_rd);
@@ -984,7 +895,6 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
     /*
      * check if we have an expansion ROM
      */
-    value = swpl(pci_read_config_longword(handle, PCIERBAR));
 
     /*
      * write all bits of PCIERBAR
@@ -997,8 +907,15 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
     address = swpl(pci_read_config_longword(handle, PCIERBAR));
     if (address & 1)
     {
+        /*
+         * there is a ROM
+         */
+
         struct pci_rd *rd = &descriptors[barnum];
-        int size = ~(address & ~0x7ff);
+        int size = ~(address & ~0x7ff) + 1;
+
+        dbg("expansion ROM requested size=0x%08x\r\n", size);
+        dbg("device 0x%02x: requests %ld kBytes for expansion ROM\r\n", handle, size / 1024);
 
         /* expansion ROM active and mapped */
 
@@ -1020,6 +937,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
         rd->length = size;
         rd->dmaoffset = 0;
 
+        cr |= 2;   /* enable Memory */
         mem_address += size;
         barnum++;
     }
@@ -1029,19 +947,17 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
         descriptors[barnum - 1].flags |= FLG_LAST;
 
     /* check if device requests an interrupt */
-    il = pci_read_config_byte(handle, PCIIPR);
+    il = pci_read_config_byte(handle, PCI_LANESWAP_B(PCIIPR));
     dbg("device requests interrupts on interrupt pin %d\r\n", il);
 
-    /* enable interrupt on PCI device */
+    /* disable interrupt on PCI device */
 
-    il = pci_read_config_byte(handle, PCICR);
-    il &= ~PCICSR_INT_DISABLE;
-    pci_write_config_byte(handle, PCICR, il);
+    cr |= PCICR_INT_DISABLE;
 
     /*
      * enable device memory or I/O access
      */
-    pci_write_config_word(handle, PCICSR, swpw(cr));
+    pci_write_config_word(handle, PCI_LANESWAP_W(PCICR), swpw(cr));
 }
 
 static void pci_bridge_config(uint16_t bus, uint16_t device, uint16_t function)
@@ -1056,9 +972,18 @@ static void pci_bridge_config(uint16_t bus, uint16_t device, uint16_t function)
     handle = PCI_HANDLE(bus, device, function);
     dbg("handle=%d\r\n", handle);
 
-    pci_write_config_longword(handle, PCIBAR0, 0x40000000);
+    pci_write_config_longword(handle, PCIBISTR, MCF_PCI_PCICR1_CACHELINESIZE(8) |
+                              MCF_PCI_PCICR1_LATTIMER(0x20));
+    pci_write_config_longword(handle, PCIBAR0, swpl(0x40000000));
     pci_write_config_longword(handle, PCIBAR1, 0x0);
-    pci_write_config_longword(handle, PCICSR, 0x146);
+    pci_write_config_word(handle, PCI_LANESWAP_W(PCICR), swpw(
+                              (1 << 1)  /* memory space */
+                              | (1 << 2)  /* bus master */
+                              | (1 << 4)  /* memory write and invalidate */
+                              | (1 << 6)  /* parity errors */
+                              | (1 << 8)  /* SERR */
+                              | (1 << 9)  /* fast back-to-back */
+                              ));
 }
 
 /*
@@ -1078,16 +1003,17 @@ void pci_scan(void)
     {
         uint32_t value;
 
-        value = pci_read_config_longword(handle, PCIIDR);
+        value = swpl(pci_read_config_longword(handle, PCIIDR));
 
-        xprintf(" %02x | %02x | %02x |%04x|%04x|%04x| %s (0x%02x)\r\n",
+        xprintf(" %02x | %02x | %02x |%04x|%04x|%04x| %s (0x%02x, 0x%04x)\r\n",
                 PCI_BUS_FROM_HANDLE(handle),
                 PCI_DEVICE_FROM_HANDLE(handle),
                 PCI_FUNCTION_FROM_HANDLE(handle),
                 PCI_VENDOR_ID(value), PCI_DEVICE_ID(value),
                 handle,
-                device_class(pci_read_config_byte(handle, PCICCR)),
-                pci_read_config_byte(handle, PCICCR));
+                device_class(pci_read_config_byte(handle, PCI_LANESWAP_B(PCICCR))),
+                pci_read_config_byte(handle, PCI_LANESWAP_B(PCICCR)),
+                pci_read_config_word(handle, PCI_LANESWAP_W(PCICCR)));
 
         /* save handle to index value so that we'll be able to later find our resources */
         handles[index] = handle;
@@ -1097,17 +1023,17 @@ void pci_scan(void)
         {
             /* configure memory and I/O for card */
             pci_device_config(PCI_BUS_FROM_HANDLE(handle),
-                        PCI_DEVICE_FROM_HANDLE(handle),
-                        PCI_FUNCTION_FROM_HANDLE(handle));
+                              PCI_DEVICE_FROM_HANDLE(handle),
+                              PCI_FUNCTION_FROM_HANDLE(handle));
         }
         else
         {
-            dbg("");
+            dbg("\r\n");
             pci_bridge_config(PCI_BUS_FROM_HANDLE(handle),
-                        PCI_DEVICE_FROM_HANDLE(handle),
-                        PCI_FUNCTION_FROM_HANDLE(handle));
+                              PCI_DEVICE_FROM_HANDLE(handle),
+                              PCI_FUNCTION_FROM_HANDLE(handle));
         }
-        dbg("");
+        dbg("\r\n");
         handle = pci_find_device(0x0, 0xFFFF, ++index);
     }
     xprintf("\r\n...finished\r\n");
@@ -1119,11 +1045,11 @@ void init_eport(void)
     /* configure IRQ1-7 pins on EPORT falling edge triggered */
     MCF_EPORT_EPPAR = MCF_EPORT_EPPAR_EPPA7(MCF_EPORT_EPPAR_FALLING) |
             MCF_EPORT_EPPAR_EPPA6(MCF_EPORT_EPPAR_FALLING) |
-#if defined(MACHINE_FIREBEE)     /* irq5 level triggered on FireBee */
+        #if defined(MACHINE_FIREBEE)     /* irq5 level triggered on FireBee */
             MCF_EPORT_EPPAR_EPPA5(MCF_EPORT_EPPAR_LEVEL) |
-#elif defined(MACHINE_M5484LITE)
+        #elif defined(MACHINE_M5484LITE)
             MCF_EPORT_EPPAR_EPPA5(MCF_EPORT_EPPAR_FALLING) |
-#endif /* MACHINE_FIREBEE */
+        #endif /* MACHINE_FIREBEE */
             MCF_EPORT_EPPAR_EPPA4(MCF_EPORT_EPPAR_FALLING) |
             MCF_EPORT_EPPAR_EPPA3(MCF_EPORT_EPPAR_FALLING) |
             MCF_EPORT_EPPAR_EPPA2(MCF_EPORT_EPPAR_FALLING) |
@@ -1143,15 +1069,15 @@ void init_xlbus_arbiter(void)
     if (clock_ratio == 4)
     {
         MCF_XLB_XARB_CFG = MCF_XLB_XARB_CFG_BA |
-            MCF_XLB_XARB_CFG_DT |
-            MCF_XLB_XARB_CFG_AT |
-            MCF_XLB_XARB_CFG_PLDIS;
+                MCF_XLB_XARB_CFG_DT |
+                MCF_XLB_XARB_CFG_AT |
+                MCF_XLB_XARB_CFG_PLDIS;
     }
     else
     {
         MCF_XLB_XARB_CFG = MCF_XLB_XARB_CFG_BA |
-            MCF_XLB_XARB_CFG_DT |
-            MCF_XLB_XARB_CFG_AT;
+                MCF_XLB_XARB_CFG_DT |
+                MCF_XLB_XARB_CFG_AT;
     }
 
     MCF_XLB_XARB_ADRTO = 0x1fffff;
@@ -1165,13 +1091,14 @@ void init_xlbus_arbiter(void)
      * M2 = Multichannel DMA
      * M3 = PCI target interface
      */
-
+#if 0
     MCF_XLB_XARB_PRIEN = MCF_XLB_XARB_PRIEN_M0 |    /* activate programmed priority for Coldfire core */
-                    MCF_XLB_XARB_PRIEN_M2 |         /* activate programmed priority for Multichannel DMA */
-                    MCF_XLB_XARB_PRIEN_M3;          /* activate programmed priority for PCI target interface */
+            MCF_XLB_XARB_PRIEN_M2 |         /* activate programmed priority for Multichannel DMA */
+            MCF_XLB_XARB_PRIEN_M3;          /* activate programmed priority for PCI target interface */
     MCF_XLB_XARB_PRI = MCF_XLB_XARB_PRI_M0P(7) |    /* Coldfire core gets lowest */
-                    MCF_XLB_XARB_PRI_M2P(5) |       /* Multichannel DMA mid priority */
-                    MCF_XLB_XARB_PRI_M3P(3);        /* PCI target interface is highest priority */
+            MCF_XLB_XARB_PRI_M2P(5) |       /* Multichannel DMA mid priority */
+            MCF_XLB_XARB_PRI_M3P(3);        /* PCI target interface is highest priority */
+#endif
 }
 
 void init_pci(void)
@@ -1185,15 +1112,16 @@ void init_pci(void)
     init_eport();
     init_xlbus_arbiter();
 
-    MCF_PCI_PCIGSCR = -1;
+    MCF_PCI_PCIGSCR |= MCF_PCI_PCIGSCR_PR;           /* reset PCI devices */
+
 
     /*
      * setup the PCI arbiter
      */
     MCF_PCIARB_PACR = MCF_PCIARB_PACR_INTMPRI   /* internal master priority: high */
-       | MCF_PCIARB_PACR_EXTMPRI(0xf)           /* external master priority: high */
-       | MCF_PCIARB_PACR_INTMINTEN              /* enable "internal master broken" interrupt */
-       | MCF_PCIARB_PACR_EXTMINTEN(0x0f);       /* enable "external master broken" interrupt */
+            | MCF_PCIARB_PACR_EXTMPRI(0x0)           /* external master priority: high */
+            | MCF_PCIARB_PACR_INTMINTEN              /* enable "internal master broken" interrupt */
+            | MCF_PCIARB_PACR_EXTMINTEN(0x0f);       /* enable "external master broken" interrupt */
 
 #if defined(MACHINE_FIREBEE)
     MCF_PAD_PAR_PCIBG = MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST |
@@ -1206,44 +1134,53 @@ void init_pci(void)
             MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 |
             MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 |
             MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0;
-#elif MACHINE_M5484LITE
-    MCF_PAD_PAR_PCIBG = 0x3ff; /* enable all PCI bus grant and bus requests on the LITE board */
-    MCF_PAD_PAR_PCIBR = 0x3ff;
+#elif defined(MACHINE_M5484LITE)
+    MCF_PAD_PAR_PCIBG = MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0 |
+            MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 |
+            MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 |
+            MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3 |
+            MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4; /* enable all PCI bus grant and bus requests on the LITE board */
+    MCF_PAD_PAR_PCIBR = MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0 |
+            MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 |
+            MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 |
+            MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3 |
+            MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4;
 #endif /* MACHINE_FIREBEE */
 
     MCF_PCI_PCISCR =  MCF_PCI_PCISCR_M |    /* memory access control enabled */
-        MCF_PCI_PCISCR_B |                  /* bus master enabled */
-        MCF_PCI_PCISCR_M |                  /* mem access enable */
-        MCF_PCI_PCISCR_MA |                 /* clear master abort error */
-        MCF_PCI_PCISCR_MW;                  /* memory write and invalidate enabled */
+            MCF_PCI_PCISCR_B |                  /* bus master enabled */
+            MCF_PCI_PCISCR_M |                  /* mem access enable */
+            MCF_PCI_PCISCR_MA |                 /* clear master abort error */
+            MCF_PCI_PCISCR_MW |                 /* memory write and invalidate enabled */
+            MCF_PCI_PCISCR_PER;                 /* assert PERR on parity error */
 
 
     /* Setup burst parameters */
-    MCF_PCI_PCICR1 = MCF_PCI_PCICR1_CACHELINESIZE(0) |
-                        MCF_PCI_PCICR1_LATTIMER(0x20); /* TODO: test increased latency timer */
+    MCF_PCI_PCICR1 = MCF_PCI_PCICR1_CACHELINESIZE(8) |
+            MCF_PCI_PCICR1_LATTIMER(0x20); /* TODO: test increased latency timer */
 
     MCF_PCI_PCICR2 = MCF_PCI_PCICR2_MINGNT(1) |
-                    MCF_PCI_PCICR2_MAXLAT(32);
+            MCF_PCI_PCICR2_MAXLAT(32);
 
     // MCF_PCI_PCICR2 = 0;      /* this is what Linux does */
 
     /* error signaling */
 
     MCF_PCI_PCIICR = MCF_PCI_PCIICR_TAE |   /* target abort enable */
-        MCF_PCI_PCIICR_IAE;                 /* initiator abort enable */
+            MCF_PCI_PCIICR_IAE;                 /* initiator abort enable */
 
     // MCF_PCI_PCIICR = 0;                      /* this is what Linux does */
 
-    MCF_PCI_PCIGSCR |= MCF_PCI_PCIGSCR_SEE; /* system error interrupt enable */
-
+    MCF_PCI_PCIGSCR |= MCF_PCI_PCIGSCR_SEE |    /* system error interrupt enable */
+            MCF_PCI_PCIGSCR_PEE;     /* parity error interrupt enable */
     /* Configure Initiator Windows */
 
     /*
      * initiator window 0 base / translation adress register
      * used for PCI memory access
      */
-    MCF_PCI_PCIIW0BTAR = (PCI_MEMORY_OFFSET + ((PCI_MEMORY_SIZE - 1) >> 8))
-                          + (PCI_MEMORY_OFFSET >> 16);
+    MCF_PCI_PCIIW0BTAR = ((PCI_MEMORY_OFFSET + ((PCI_MEMORY_SIZE - 1) >> 8)) & 0xffff0000)
+            | (PCI_MEMORY_OFFSET >> 16);
 
     NOP();
     dbg("PCIIW0BTAR=0x%08x\r\n", MCF_PCI_PCIIW0BTAR);
@@ -1252,16 +1189,17 @@ void init_pci(void)
      * initiator window 1 base / translation adress register
      * used for PCI I/O access
      */
-    MCF_PCI_PCIIW1BTAR = (PCI_IO_OFFSET + ((PCI_IO_SIZE - 1) >> 8)) & 0xffff0000;
+    MCF_PCI_PCIIW1BTAR = ((PCI_IO_OFFSET + ((PCI_IO_SIZE - 1) >> 8)) & 0xffff0000)
+            | (PCI_IO_OFFSET >> 16);
     NOP();
     /* initiator window 2 base / translation address register */
     MCF_PCI_PCIIW2BTAR = 0L;   /* not used */
     NOP();
     /* initiator window configuration register */
     MCF_PCI_PCIIWCR = MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE |
-                    MCF_PCI_PCIIWCR_WINCTRL1_IO |
-                    MCF_PCI_PCIIWCR_WINCTRL0_E |
-                    MCF_PCI_PCIIWCR_WINCTRL1_E;
+            MCF_PCI_PCIIWCR_WINCTRL1_IO |
+            MCF_PCI_PCIIWCR_WINCTRL0_E |
+            MCF_PCI_PCIIWCR_WINCTRL1_E;
     NOP();
 
     /*
@@ -1276,6 +1214,8 @@ void init_pci(void)
     /* reset PCI devices */
     MCF_PCI_PCIGSCR &= ~MCF_PCI_PCIGSCR_PR;
     do { NOP(); } while (MCF_PCI_PCIGSCR & MCF_PCI_PCIGSCR_PR); /* wait until reset finished */
+    wait(200);
+
     xprintf("finished\r\n");
 
     /* initialize/clear resource descriptor table */
@@ -1310,16 +1250,16 @@ void pci_print_device_abilities(int32_t handle)
     pci_write_config_word(handle, PCICSR, 0xffff);
     value = swpw(pci_read_config_word(handle, PCICSR));
     dbg("IO: %1d MEM: %1d MSTR:%1d SPCC: %1d MEMW: %1d VGAS: %1d PERR: %1d STEP: %1d SERR: %1d FBTB: %1d\r\n",
-            value & PCICSR_IO ? 1 : 0,
-            value & PCICSR_MEMORY ? 1 : 0,
-            value & PCICSR_MASTER ? 1 : 0,
-            value & PCICSR_SPECIAL ? 1 : 0,
-            value & PCICSR_MEMWI ? 1 : 0,
-            value & PCICSR_VGA_SNOOP ? 1 : 0,
-            value & PCICSR_PERR ? 1 : 0,
-            value & PCICSR_STEPPING ? 1 : 0,
-            value & PCICSR_SERR ? 1 : 0,
-            value & PCICSR_FAST_BTOB_E ? 1 : 0);
+        value & PCICSR_IO ? 1 : 0,
+        value & PCICSR_MEMORY ? 1 : 0,
+        value & PCICSR_MASTER ? 1 : 0,
+        value & PCICSR_SPECIAL ? 1 : 0,
+        value & PCICSR_MEMWI ? 1 : 0,
+        value & PCICSR_VGA_SNOOP ? 1 : 0,
+        value & PCICSR_PERR ? 1 : 0,
+        value & PCICSR_STEPPING ? 1 : 0,
+        value & PCICSR_SERR ? 1 : 0,
+        value & PCICSR_FAST_BTOB_E ? 1 : 0);
     pci_write_config_word(handle, PCICSR, saved_value);
 }
 
@@ -1330,15 +1270,15 @@ void pci_print_device_config(int32_t handle)
 
     value = swpw(pci_read_config_word(handle, PCICSR + 2));
     dbg("66M: %1d UDF: %1d FB2B:%1d PERR: %1d TABR: %1d DABR: %1d SERR: %1d PPER: %1d\r\n",
-            value & PCICSR_66MHZ ? 1 : 0,
-            value & PCICSR_UDF ? 1 : 0,
-            value & PCICSR_FAST_BTOB ? 1 : 0,
-            value & PCICSR_DPARITY_ERROR ? 1 : 0,
-            value & PCICSR_T_ABORT_S ? 1 : 0,
-            value & PCICSR_T_ABORT_R ? 1 : 0,
-            value & PCICSR_M_ABORT_R ? 1 : 0,
-            value & PCICSR_S_ERROR_S ? 1 : 0,
-            value & PCICSR_PARITY_ERR ? 1 : 0);
+        value & PCICSR_66MHZ ? 1 : 0,
+        value & PCICSR_UDF ? 1 : 0,
+        value & PCICSR_FAST_BTOB ? 1 : 0,
+        value & PCICSR_DPARITY_ERROR ? 1 : 0,
+        value & PCICSR_T_ABORT_S ? 1 : 0,
+        value & PCICSR_T_ABORT_R ? 1 : 0,
+        value & PCICSR_M_ABORT_R ? 1 : 0,
+        value & PCICSR_S_ERROR_S ? 1 : 0,
+        value & PCICSR_PARITY_ERR ? 1 : 0);
 }
 #endif /* DEBUG_PCI */
 

pci/pci_errata.c

@@ -0,0 +1,66 @@
+#include "pci_errata.h"
+#include "pci.h"
+#include <MCF5475.h>
+
+#include "debug.h"
+
+__attribute__((aligned(16))) void chip_errata_135(void)
+{
+    /*
+     * Errata type: Silicon
+     * Affected component: PCI
+     * Description: When core PCI transactions that involve writes to configuration or I/O space
+     * are followed by a core line access to line addresses 0x4 and 0xC, core access
+     * to the XL bus can hang.
+     * Workaround: Prevent PCI configuration and I/O writes from being followed by the described
+     * line access by the core by generating a known good XL bus transaction after
+     * the PCI transaction.
+     * Create a dummy function which is called immediately after each of the affected
+     * transactions. There are three requirements for this dummy function.
+     * 1. The function must be aligned to a 16-byte boundary.
+     * 2. The function must contain a dummy write to a location on the XL bus,
+     * preferably one with no side effects.
+     * 3. The function must be longer than 32 bytes. If it is not, the function should
+     * be padded with 16- or 48-bit TPF instructions placed after the end of
+     * the function (after the RTS instruction) such that the length is longer
+     * than 32 bytes.
+     */
+
+     __asm__ __volatile(
+        "       .extern __MBAR          \n\t"
+        "       clr.l   d0              \n\t"
+        "       move.l  d0,__MBAR+0xF0C \n\t"       /* Must use direct addressing. write to EPORT module */
+                                                    /* xlbus -> slavebus -> eport, writing '0' to register */
+                                                    /* has no effect */
+        "       rts                     \n\t"
+        "       tpf.l   #0x0            \n\t"
+        "       tpf.l   #0x0            \n\t"
+        "       tpf.l   #0x0            \n\t"
+        "       tpf.l   #0x0            \n\t"
+        "       tpf.l   #0x0            \n\t"
+        ::: "d0", "memory");
+}
+
+void chip_errata_055(int32_t handle)
+{
+    uint32_t dummy;
+
+    return;     /* test */
+
+    /* initiate PCI configuration access to device */
+    MCF_PCI_PCICAR = MCF_PCI_PCICAR_E |         /* enable configuration access special cycle */
+            MCF_PCI_PCICAR_BUSNUM(3) |          /* note: invalid bus number */
+            MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | /* device number, devices 0 - 9 are reserved */
+            MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |  /* function number */
+            MCF_PCI_PCICAR_DWORD(0);
+
+    /* issue a dummy read to an unsupported bus number (will fail) */
+    dummy =  * (volatile uint32_t *) PCI_IO_OFFSET; /* access device */
+
+    /* silently clear the PCI errors we produced just now */
+    MCF_PCI_PCIISR = 0xffffffff;     /* clear all errors */
+    MCF_PCI_PCIGSCR = MCF_PCI_PCIGSCR_PE | MCF_PCI_PCIGSCR_SE;
+
+    (void) dummy;
+}
+

radeon/i2c-algo-bit.c

@@ -0,0 +1,474 @@
+/* ------------------------------------------------------------------------- */
+/* i2c-algo-bit.c i2c driver algorithms for bit-shift adapters		     */
+/* ------------------------------------------------------------------------- */
+/*   Copyright (C) 1995-2000 Simon G. Vogl
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.		     */
+/* ------------------------------------------------------------------------- */
+
+/* With some changes from Frodo Looijaard <frodol@dds.nl>, Ky<4B>sti M<>lkki
+   <kmalkki@cc.hut.fi> and Jean Delvare <khali@linux-fr.org> */
+
+#include "wait.h"
+#include "i2c.h"
+#include "i2c-algo-bit.h"
+
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+// #define DEBUG
+#include "debug.h"
+
+extern void start_timeout(void);
+extern int end_timeout(long msec);
+
+/* --- setting states on the bus with the right timing: ---------------	*/
+
+#define setsda(adap,val) adap->setsda(adap->data, val)
+#define setscl(adap,val) adap->setscl(adap->data, val)
+#define getsda(adap) adap->getsda(adap->data)
+#define getscl(adap) adap->getscl(adap->data)
+
+static inline void sdalo(struct i2c_algo_bit_data *adap)
+{
+    setsda(adap,0);
+    wait_us(adap->udelay);
+}
+
+static inline void sdahi(struct i2c_algo_bit_data *adap)
+{
+    setsda(adap,1);
+    wait_us(adap->udelay);
+}
+
+static inline void scllo(struct i2c_algo_bit_data *adap)
+{
+    setscl(adap,0);
+    wait_us(adap->udelay);
+}
+
+/*
+ * Raise scl line, and do checking for delays. This is necessary for slower
+ * devices.
+ */
+static inline int sclhi(struct i2c_algo_bit_data *adap)
+{
+    setscl(adap, 1);
+    /* Not all adapters have scl sense line... */
+    if(adap->getscl == NULL )
+    {
+        wait_us(adap->udelay);
+        return 0;
+    }
+    start_timeout();
+    while (! getscl(adap))
+    {
+        /* the hw knows how to read the clock line,
+         * so we wait until it actually gets high.
+         * This is safer as some chips may hold it low
+         * while they are processing data internally.
+         */
+        if (end_timeout((long)adap->timeout))
+            return -110;
+    }
+    wait_us(adap->udelay);
+    return 0;
+}
+
+
+/* --- other auxiliary functions --------------------------------------	*/
+void i2c_start(struct i2c_algo_bit_data *adap)
+{
+    /* assert: scl, sda are high */
+    sdalo(adap);
+    scllo(adap);
+}
+
+static void i2c_repstart(struct i2c_algo_bit_data *adap)
+{
+    /* scl, sda may not be high */
+    setsda(adap, 1);
+    sclhi(adap);
+    wait_us(adap->udelay);
+    sdalo(adap);
+    scllo(adap);
+}
+
+static void i2c_stop(struct i2c_algo_bit_data *adap)
+{
+    /* assert: scl is low */
+    sdalo(adap);
+    sclhi(adap);
+    sdahi(adap);
+}
+
+/*
+ * send a byte without start cond., look for arbitration,
+ * check ackn. from slave
+ *
+ * returns:
+ * 1 if the device acknowledged
+ * 0 if the device did not ack
+ * -ETIMEDOUT if an error occurred (while raising the scl line)
+ */
+static int i2c_outb(struct i2c_adapter *i2c_adap, char c)
+{
+    int i;
+    int sb;
+    int ack;
+    struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
+    /* assert: scl is low */
+
+    for (i = 7; i >= 0; i--)
+    {
+        sb = c & (1 << i);
+        setsda(adap,sb);
+        wait_us(adap->udelay);
+        if (sclhi(adap) < 0)
+        {
+            /* timed out */
+            sdahi(adap); /* we don't want to block the net */
+#ifdef DEBUG
+            dbg("ETIMEDOUT\r\n");
+#endif
+            return -110;
+        };
+        /* do arbitration here:
+         * if ( sb && ! getsda(adap) ) -> ouch! Get out of here.
+         */
+        setscl(adap, 0 );
+        wait_us(adap->udelay);
+    }
+    sdahi(adap);
+    if(sclhi(adap)<0)
+    {
+        /* timeout */
+
+        dbg("ETIMEDOUT\r\n");
+
+        return -110;
+    }
+    /* read ack: SDA should be pulled down by slave */
+    ack = getsda(adap);	/* ack: sda is pulled low ->success.	 */
+    scllo(adap);
+
+    dbg("0x%02x, ack=0x%02x\r\n", (unsigned long)(c & 0xff), ack);
+
+    return 0 == ack;		/* return 1 if device acked	 */
+    /* assert: scl is low (sda undef) */
+}
+
+static int i2c_inb(struct i2c_adapter *i2c_adap)
+{
+    /* read byte via i2c port, without start/stop sequence	*/
+    /* acknowledge is sent in i2c_read.			*/
+    int i;
+    unsigned char indata = 0;
+    struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
+    /* assert: scl is low */
+    sdahi(adap);
+    for(i = 0; i < 8; i++)
+    {
+        if (sclhi(adap) < 0)
+        {
+            /* timeout */
+            dbg("i2c_inb TIMEDOUT\r\n");
+            return -110;
+        }
+        indata *= 2;
+        if (getsda(adap))
+            indata |= 0x01;
+        scllo(adap);
+    }
+    /* assert: scl is low */
+    dbg("0x%02x\r\n", (unsigned long)(indata & 0xff));
+
+    return (int) (indata & 0xff);
+}
+
+/*
+ * Sanity check for the adapter hardware - check the reaction of
+ * the bus lines only if it seems to be idle.
+ */
+static int test_bus(struct i2c_algo_bit_data *adap)
+{
+    int scl, sda;
+    sda = getsda(adap);
+    scl = (adap->getscl == NULL ? 1 : getscl(adap));
+    if (!scl || !sda )
+        goto bailout;
+    sdalo(adap);
+    sda = getsda(adap);
+    scl = (adap->getscl == NULL ? 1 : getscl(adap));
+    if (sda !=0 || scl == 0)
+        goto bailout;
+    sdahi(adap);
+    sda = getsda(adap);
+    scl = (adap->getscl == NULL ? 1 : getscl(adap));
+    if (sda == 0 || scl ==0)
+        goto bailout;
+    scllo(adap);
+    sda = getsda(adap);
+    scl = (adap->getscl == NULL ? 0 : getscl(adap));
+    if (scl !=0 || sda == 0)
+        goto bailout;
+    sclhi(adap);
+    sda = getsda(adap);
+    scl = (adap->getscl == NULL ? 1 : getscl(adap));
+    if (scl == 0 || sda ==0)
+        goto bailout;
+    return 0;
+bailout:
+    sdahi(adap);
+    sclhi(adap);
+    return -110;
+}
+
+/* ----- Utility functions
+ */
+
+/* try_address tries to contact a chip for a number of
+ * times before it gives up.
+ * return values:
+ * 1 chip answered
+ * 0 chip did not answer
+ * -x transmission error
+ */
+static inline int try_address(struct i2c_adapter *i2c_adap,
+                              unsigned char addr, int retries)
+{
+    struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
+    int i, ret = -1;
+    for (i = 0; i <= retries; i++)
+    {
+        ret = i2c_outb(i2c_adap, addr);
+        if (ret == 1)
+            break;	/* success! */
+        i2c_stop(adap);
+        wait_us(5);
+        if (i == retries)  /* no success */
+            break;
+        i2c_start(adap);
+        wait_us(adap->udelay);
+    }
+    return ret;
+}
+
+static int sendbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msg)
+{
+    struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
+    char c;
+    const char *temp = (const char *)msg->buf;
+    int count = msg->len;
+    unsigned short nak_ok = msg->flags & I2C_M_IGNORE_NAK;
+    int retval;
+    int wrcount=0;
+    while(count > 0)
+    {
+        c = *temp;
+        retval = i2c_outb(i2c_adap,c);
+        if ((retval > 0) || (nak_ok && (retval==0)))
+        { /* ok or ignored NAK */
+            count--;
+            temp++;
+            wrcount++;
+        }
+        else
+        { /* arbitration or no acknowledge */
+            i2c_stop(adap);
+            return (retval < 0)? retval : -110;
+            /* got a better one ?? */
+        }
+    }
+    return wrcount;
+}
+
+static inline int readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msg)
+{
+    int inval;
+    int rdcount=0;   	/* counts bytes read */
+    struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
+    char *temp = (char *)msg->buf;
+    int count = msg->len;
+    while(count > 0)
+    {
+        inval = i2c_inb(i2c_adap);
+        if (inval >= 0)
+        {
+            *temp = inval;
+            rdcount++;
+        }
+        else
+            /* read timed out */
+            break;
+        temp++;
+        count--;
+        if (msg->flags & I2C_M_NO_RD_ACK)
+            continue;
+        if (count > 0)
+            /* send ack */
+            sdalo(adap);
+        else
+            sdahi(adap);	/* neg. ack on last byte */
+        if (sclhi(adap) < 0)
+        {
+            /* timeout */
+            sdahi(adap);
+            return -1;
+        };
+        scllo(adap);
+        sdahi(adap);
+    }
+    return rdcount;
+}
+
+/* doAddress initiates the transfer by generating the start condition (in
+ * try_address) and transmits the address in the necessary format to handle
+ * reads, writes as well as 10bit-addresses.
+ * returns:
+ *  0 everything went okay, the chip ack'ed, or IGNORE_NAK flag was set
+ * -x an error occurred (like: -EREMOTEIO if the device did not answer, or
+ *	-ETIMEDOUT, for example if the lines are stuck...)
+ */
+static inline int bit_doAddress(struct i2c_adapter *i2c_adap, struct i2c_msg *msg)
+{
+    unsigned short flags = msg->flags;
+    unsigned short nak_ok = msg->flags & I2C_M_IGNORE_NAK;
+    struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
+    unsigned char addr;
+    int ret, retries;
+    retries = nak_ok ? 0 : i2c_adap->retries;
+    if (flags & I2C_M_TEN)
+    {
+        /* a ten bit address */
+        addr = 0xf0 | (( msg->addr >> 7) & 0x03);
+        /* try extended address code...*/
+        ret = try_address(i2c_adap, addr, retries);
+        if ((ret != 1) && !nak_ok)
+            return -1;
+        /* the remaining 8 bit address */
+        ret = i2c_outb(i2c_adap,msg->addr & 0x7f);
+        if ((ret != 1) && !nak_ok)
+            /* the chip did not ack / xmission error occurred */
+            return -1;
+        if (flags & I2C_M_RD)
+        {
+            i2c_repstart(adap);
+            /* okay, now switch into reading mode */
+            addr |= 0x01;
+            ret = try_address(i2c_adap, addr, retries);
+            if ((ret != 1) && !nak_ok)
+                return -1;
+        }
+    }
+    else
+    {		/* normal 7bit address	*/
+        addr = (msg->addr << 1);
+        if (flags & I2C_M_RD )
+            addr |= 1;
+        if (flags & I2C_M_REV_DIR_ADDR )
+            addr ^= 1;
+        ret = try_address(i2c_adap, addr, retries);
+        if ((ret != 1) && !nak_ok)
+            return -1;
+    }
+    return 0;
+}
+
+static int bit_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[], int num)
+{
+    struct i2c_msg *pmsg;
+    struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
+    int i,ret;
+    unsigned short nak_ok;
+    i2c_start(adap);
+    for(i=0;i<num;i++)
+    {
+        pmsg = &msgs[i];
+        nak_ok = pmsg->flags & I2C_M_IGNORE_NAK;
+        if(!(pmsg->flags & I2C_M_NOSTART))
+        {
+            if (i)
+                i2c_repstart(adap);
+            ret = bit_doAddress(i2c_adap, pmsg);
+            if ((ret != 0) && !nak_ok)
+                return (ret < 0) ? ret : -1;
+        }
+        if(pmsg->flags & I2C_M_RD )
+        {
+            /* read bytes into buffer*/
+            ret = readbytes(i2c_adap, pmsg);
+            if(ret < pmsg->len)
+                return (ret < 0)? ret : -1;
+        }
+        else
+        {
+            /* write bytes from buffer */
+            ret = sendbytes(i2c_adap, pmsg);
+            if (ret < pmsg->len )
+                return (ret < 0) ? ret : -1;
+        }
+    }
+    i2c_stop(adap);
+    return num;
+}
+
+/* -----exported algorithm data: -------------------------------------	*/
+
+static struct i2c_algorithm i2c_bit_algo = {
+    .master_xfer = bit_xfer,
+};
+
+/*
+ * registering functions to load algorithms at runtime
+ */
+int i2c_bit_add_bus(struct i2c_adapter *adap)
+{
+    struct i2c_algo_bit_data *bit_adap = adap->algo_data;
+    if (1)
+    {
+        int ret = test_bus(bit_adap);
+        if (ret < 0)
+            return -1;
+    }
+    /* register new adapter to i2c module... */
+    adap->algo = &i2c_bit_algo;
+    adap->timeout = 10;         /* default values, should	*/
+    adap->retries = 3;          /* be replaced by defines	*/
+    return 0;
+}
+
+int i2c_bit_del_bus(struct i2c_adapter *adap)
+{
+    return 0;
+}
+
+/* ----------------------------------------------------
+ * the functional interface to the i2c busses.
+ * ----------------------------------------------------
+ */
+
+int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
+{
+    int ret;
+    if (adap->algo->master_xfer)
+    {
+        ret = adap->algo->master_xfer(adap, msgs, num);
+        return ret;
+    }
+    else
+        return -1;
+}

radeon/radeon_accel.c

@@ -64,12 +64,15 @@
  *
  */
 
+// #define DEBUG
+#include "debug.h"
+
 #include "fb.h"
 #include "radeonfb.h"
 
 static struct {
-    int rop;
-    int pattern;
+    int32_t rop;
+    int32_t pattern;
 } RADEON_ROP[] = {
     { ROP3_ZERO, ROP3_ZERO }, /* GXclear        */
     { ROP3_DSa,  ROP3_DPa  }, /* Gxand          */
@@ -103,7 +106,7 @@ static struct {
  */
 void radeon_wait_for_idle_mmio(struct radeonfb_info *rinfo)
 {
-    int i = 0;
+    int32_t i = 0;
     /* Wait for the engine to go idle */
     radeon_wait_for_fifo_function(rinfo, 64);
     while(1)
@@ -136,7 +139,7 @@ void RADEONRestoreAccelStateMMIO(struct fb_info *info)
 #endif
 
 /* Setup for XAA SolidFill */
-void radeon_setup_for_solid_fill(struct fb_info *info, int color, int rop, unsigned int planemask)
+void radeon_setup_for_solid_fill(struct fb_info *info, int32_t color, int32_t rop, uint32_t planemask)
 {
     struct radeonfb_info *rinfo = info->par;
     ACCEL_PREAMBLE();
@@ -152,7 +155,7 @@ void radeon_setup_for_solid_fill(struct fb_info *info, int color, int rop, unsig
 }
 
 /* Subsequent XAA SolidFillRect */
-void radeon_subsequent_solid_fill_rect_mmio(struct fb_info *info, int x, int y, int w, int h)
+void radeon_subsequent_solid_fill_rect_mmio(struct fb_info *info, int32_t x, int32_t y, int32_t w, int32_t h)
 {
     struct radeonfb_info *rinfo = info->par;
     ACCEL_PREAMBLE();
@@ -169,7 +172,7 @@ void radeon_subsequent_solid_fill_rect_mmio(struct fb_info *info, int x, int y,
 }
 
 /* Setup for XAA solid lines */
-void radeon_setup_for_solid_line_mmio(struct fb_info *info, int color, int rop, unsigned int planemask)
+void radeon_setup_for_solid_line_mmio(struct fb_info *info, int32_t color, int32_t rop, uint32_t planemask)
 {
     struct radeonfb_info *rinfo = info->par;
     ACCEL_PREAMBLE();
@@ -189,11 +192,11 @@ void radeon_setup_for_solid_line_mmio(struct fb_info *info, int color, int rop,
 }
 
 /* Subsequent XAA solid horizontal and vertical lines */
-void radeon_subsequent_solid_hor_vert_line_mmio(struct fb_info *info, int x, int y, int len, int dir)
+void radeon_subsequent_solid_hor_vert_line_mmio(struct fb_info *info, int32_t x, int32_t y, int32_t len, int32_t dir)
 {
     struct radeonfb_info *rinfo = info->par;
-    int w = 1;
-    int h = 1;
+    int32_t w = 1;
+    int32_t h = 1;
     ACCEL_PREAMBLE();
     if (dir == DEGREES_0)
         w = len;
@@ -215,7 +218,7 @@ void radeon_subsequent_solid_hor_vert_line_mmio(struct fb_info *info, int x, int
 
 /* Subsequent XAA solid TwoPointLine line */
 void radeon_subsequent_solid_two_point_line_mmio(struct fb_info *info,
-     int xa, int ya, int xb, int yb, int flags)
+     int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t flags)
 {
     struct radeonfb_info *rinfo = info->par;
 
@@ -239,8 +242,8 @@ void radeon_subsequent_solid_two_point_line_mmio(struct fb_info *info,
 /* Setup for XAA dashed lines
  * NOTE: Since we can only accelerate lines with power-of-2 patterns of * length <= 32
  */
-void radeon_setup_for_dashed_line_mmio(struct fb_info *info, int fg, int bg,
-                                        int rop, unsigned int planemask, int length, unsigned char *pattern)
+void radeon_setup_for_dashed_line_mmio(struct fb_info *info, int32_t fg, int32_t bg,
+                                        int32_t rop, uint32_t planemask, int32_t length, unsigned char *pattern)
 {
     struct radeonfb_info *rinfo = info->par;
     unsigned long pat = *(unsigned long *) pattern;
@@ -287,7 +290,7 @@ void radeon_setup_for_dashed_line_mmio(struct fb_info *info, int fg, int bg,
 
 /* Helper function to draw last point for dashed lines */
 static void RADEONDashedLastPelMMIO(struct fb_info *info,
-       int x, int y, int fg)
+       int32_t x, int32_t y, int32_t fg)
 {
     struct radeonfb_info *rinfo = info->par;
     unsigned long dp_gui_master_cntl = rinfo->dp_gui_master_cntl_clip;
@@ -317,7 +320,7 @@ static void RADEONDashedLastPelMMIO(struct fb_info *info,
 }
 
 /* Subsequent XAA dashed line */
-void radeon_subsequent_dashed_two_point_line_mmio(struct fb_info *info, int xa, int ya, int xb, int yb, int flags, int phase)
+void radeon_subsequent_dashed_two_point_line_mmio(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t flags, int32_t phase)
 {
     struct radeonfb_info *rinfo = info->par;
 
@@ -326,9 +329,9 @@ void radeon_subsequent_dashed_two_point_line_mmio(struct fb_info *info, int xa,
     /* TODO: Check bounds -- RADEON only has 14 bits */
     if (!(flags & OMIT_LAST))
     {
-        int deltax = xa - xb;
-        int deltay = ya - yb;
-        int shift;
+        int32_t deltax = xa - xb;
+        int32_t deltay = ya - yb;
+        int32_t shift;
         if (deltax < 0)
             deltax = -deltax;
         if (deltay < 0)
@@ -363,7 +366,7 @@ void radeon_subsequent_dashed_two_point_line_mmio(struct fb_info *info, int xa,
  * It should only draw when source != trans_color, this is the opposite
  * of that.
  */
-static void radeon_set_transparency_mmio(struct radeonfb_info *rinfo, int trans_color)
+static void radeon_set_transparency_mmio(struct radeonfb_info *rinfo, int32_t trans_color)
 {
     if (trans_color != -1)
     {
@@ -378,7 +381,7 @@ static void radeon_set_transparency_mmio(struct radeonfb_info *rinfo, int trans_
 
 /* Setup for XAA screen-to-screen copy */
 void radeon_setup_for_screen_to_screen_copy_mmio(struct fb_info *info,
-                    int xdir, int ydir, int rop, unsigned int planemask, int trans_color)
+                    int32_t xdir, int32_t ydir, int32_t rop, uint32_t planemask, int32_t trans_color)
 {
     struct radeonfb_info *rinfo = info->par;
 
@@ -405,7 +408,7 @@ void radeon_setup_for_screen_to_screen_copy_mmio(struct fb_info *info,
 }
 
 /* Subsequent XAA screen-to-screen copy */
-void radeon_subsequent_screen_to_screen_copy_mmio(struct fb_info *info, int xa, int ya, int xb, int yb, int w, int h)
+void radeon_subsequent_screen_to_screen_copy_mmio(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h)
 {
     struct radeonfb_info *rinfo = info->par;
 
@@ -432,12 +435,12 @@ void radeon_subsequent_screen_to_screen_copy_mmio(struct fb_info *info, int xa,
 }
 
 /* XAA screen-to-screen copy */
-void radeon_screen_to_screen_copy_mmio(struct fb_info *info, int xa, int ya, int xb, int yb, int w, int h, int rop)
+void radeon_screen_to_screen_copy_mmio(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h, int32_t rop)
 {
     struct radeonfb_info *rinfo = info->par;
 
-    int xdir = xa - xb;
-    int ydir = ya - yb;
+    int32_t xdir = xa - xb;
+    int32_t ydir = ya - yb;
     ACCEL_PREAMBLE();
     if (xdir < 0)
         xa += w - 1, xb += w - 1;
@@ -473,8 +476,8 @@ void radeon_screen_to_screen_copy_mmio(struct fb_info *info, int xa, int ya, int
  * transparency use `bg == -1'.  This routine is only used if the XAA
  * pixmap cache is turned on.
  */
-void radeon_setup_for_mono_8x8_pattern_fill_mmio(struct fb_info *info, int patternx, int patterny,
-                                                int fg, int bg, int rop, unsigned int planemask)
+void radeon_setup_for_mono_8x8_pattern_fill_mmio(struct fb_info *info, int32_t patternx, int32_t patterny,
+                                                int32_t fg, int32_t bg, int32_t rop, uint32_t planemask)
 {
     struct radeonfb_info *rinfo = info->par;
     unsigned char pattern[8];
@@ -509,8 +512,8 @@ void radeon_setup_for_mono_8x8_pattern_fill_mmio(struct fb_info *info, int patte
         OUT_ACCEL_REG(DP_BRUSH_BKGD_CLR, bg);
     if (rinfo->big_endian)
     {
-        OUT_ACCEL_REG(BRUSH_DATA0, *(unsigned long *) &pattern[0]);
-        OUT_ACCEL_REG(BRUSH_DATA1, *(unsigned long *) &pattern[4]);
+        OUT_ACCEL_REG(BRUSH_DATA0, &pattern[0]);
+        OUT_ACCEL_REG(BRUSH_DATA1, &pattern[4]);
     }
     else
     {
@@ -523,8 +526,8 @@ void radeon_setup_for_mono_8x8_pattern_fill_mmio(struct fb_info *info, int patte
 /* Subsequent XAA 8x8 pattern color expansion.  Because they are used in
  * the setup function, `patternx' and `patterny' are not used here.
  */
-void radeon_subsequent_mono_8x8_pattern_fill_rect_mmio(struct fb_info *info, int patternx, int patterny,
-                                                    int x, int y, int w, int h)
+void radeon_subsequent_mono_8x8_pattern_fill_rect_mmio(struct fb_info *info, int32_t patternx, int32_t patterny,
+                                                    int32_t x, int32_t y, int32_t w, int32_t h)
 {
     struct radeonfb_info *rinfo = info->par;
 
@@ -548,7 +551,7 @@ void radeon_subsequent_mono_8x8_pattern_fill_rect_mmio(struct fb_info *info, int
  * `bg == -1'.
  */
 void radeon_setup_for_scanline_cpu_to_screen_color_expand_fill_mmio(struct fb_info *info,
-                                                    int fg, int bg, int rop, unsigned int planemask)
+                                                    int32_t fg, int32_t bg, int32_t rop, uint32_t planemask)
 {
     struct radeonfb_info *rinfo = info->par;
 
@@ -582,7 +585,7 @@ void radeon_setup_for_scanline_cpu_to_screen_color_expand_fill_mmio(struct fb_in
  * called once for each rectangle.
  */
 void radeon_subsequent_scanline_cpu_to_screen_color_expand_fill_mmio(struct fb_info *info,
-                            int x, int y, int w, int h, int skipleft)
+                            int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft)
 {
     struct radeonfb_info *rinfo = info->par;
     ACCEL_PREAMBLE();
@@ -595,8 +598,8 @@ void radeon_subsequent_scanline_cpu_to_screen_color_expand_fill_mmio(struct fb_i
 #else
     BEGIN_ACCEL(4);
 #endif
-    OUT_ACCEL_REG(SC_TOP_LEFT, (y << 16) | ((x+skipleft) & 0xffff));
-    OUT_ACCEL_REG(SC_BOTTOM_RIGHT, ((y+h) << 16) | ((x+w) & 0xffff));
+    OUT_ACCEL_REG(SC_TOP_LEFT, (y << 16) | ((x + skipleft) & 0xffff));
+    OUT_ACCEL_REG(SC_BOTTOM_RIGHT, ((y+h) << 16) | ((x + w) & 0xffff));
     OUT_ACCEL_REG(DST_Y_X, (y << 16) | (x & 0xffff));
     /* Have to pad the width here and use clipping engine */
     OUT_ACCEL_REG(DST_HEIGHT_WIDTH, (h << 16) | ((w + 31) & ~31));
@@ -609,7 +612,7 @@ void radeon_subsequent_scanline_cpu_to_screen_color_expand_fill_mmio(struct fb_i
 void radeon_subsequent_scanline_mmio(struct fb_info *info, unsigned long *src)
 {
     struct radeonfb_info *rinfo = info->par;
-    int left = rinfo->scanline_words;
+    int32_t left = rinfo->scanline_words;
     volatile unsigned long *d;
     ACCEL_PREAMBLE();
     --rinfo->scanline_h;
@@ -654,8 +657,8 @@ void radeon_subsequent_scanline_mmio(struct fb_info *info, unsigned long *src)
 }
 
 /* Setup for XAA indirect image write */
-void radeon_setup_for_scanline_image_write_mmio(struct fb_info *info, int rop, unsigned int planemask,
-                                                int trans_color, int bpp)
+void radeon_setup_for_scanline_image_write_mmio(struct fb_info *info, int32_t rop, uint32_t planemask,
+                                                int32_t trans_color, int32_t bpp)
 {
     struct radeonfb_info *rinfo = info->par;
 
@@ -686,10 +689,10 @@ void radeon_setup_for_scanline_image_write_mmio(struct fb_info *info, int rop, u
 }
 
 /* Subsequent XAA indirect image write. This is only called once for each rectangle. */
-void radeon_subsequent_scanline_image_write_rect_mmio(struct fb_info *info, int x, int y, int w, int h, int skipleft)
+void radeon_subsequent_scanline_image_write_rect_mmio(struct fb_info *info, int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft)
 {
     struct radeonfb_info *rinfo = info->par;
-    int shift = 0; /* 32bpp */
+    int32_t shift = 0; /* 32bpp */
     ACCEL_PREAMBLE();
     if (rinfo->bpp == 8)
         shift = 3;
@@ -713,7 +716,7 @@ void radeon_subsequent_scanline_image_write_rect_mmio(struct fb_info *info, int
 }
 
 /* Set up the clipping rectangle */
-void radeon_set_clipping_rectangle_mmio(struct fb_info *info, int xa, int ya, int xb, int yb)
+void radeon_set_clipping_rectangle_mmio(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb)
 {
     struct radeonfb_info *rinfo = info->par;
 
@@ -786,11 +789,11 @@ void radeon_disable_clipping_mmio(struct fb_info *info)
 void RADEONChangeSurfaces(struct fb_info *info)
 {
     struct radeonfb_info *rinfo = info->par;
-    int cpp = rinfo->bpp >> 3;
+    int32_t cpp = rinfo->bpp >> 3;
     /* depth/front/back pitch must be identical (and the same as displayWidth) */
-    int width_bytes = info->var.xres_virtual * cpp;
-    int bufferSize = (((((info->var.yres_virtual + 15) & ~15) * width_bytes) + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN);
-    unsigned int depth_pattern, color_pattern, swap_pattern, surf_info;
+    int32_t width_bytes = info->var.xres_virtual * cpp;
+    int32_t bufferSize = (((((info->var.yres_virtual + 15) & ~15) * width_bytes) + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN);
+    uint32_t depth_pattern, color_pattern, swap_pattern, surf_info;
     if (rinfo->big_endian)
     {
         switch(rinfo->bpp)
@@ -850,12 +853,13 @@ void RADEONChangeSurfaces(struct fb_info *info)
 
 #endif
 
-/* The FIFO has 64 slots.  This routines waits until at least `entries'
+/*
+ * The FIFO has 64 slots.  This routines waits until at least `entries'
  * of these slots are empty.
  */
-void radeon_wait_for_fifo_function(struct radeonfb_info *rinfo, int entries)
+void radeon_wait_for_fifo_function(struct radeonfb_info *rinfo, int32_t entries)
 {
-    int i;
+    int32_t i;
     while(1)
     {
         for(i = 0; i < RADEON_TIMEOUT; i++)
@@ -872,7 +876,7 @@ void radeon_wait_for_fifo_function(struct radeonfb_info *rinfo, int entries)
 /* Flush all dirty data in the Pixel Cache to memory */
 void radeon_engine_flush(struct radeonfb_info *rinfo)
 {
-    int i;
+    int32_t i;
     OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, ~RB2D_DC_FLUSH_ALL);
     for(i = 0; i < RADEON_TIMEOUT; i++)
     {
@@ -881,7 +885,9 @@ void radeon_engine_flush(struct radeonfb_info *rinfo)
     }
 }
 
-/* Reset graphics card to known state */
+/*
+ * Reset graphics card to known state
+ */
 void radeon_engine_reset(struct radeonfb_info *rinfo)
 {
     unsigned long clock_cntl_index;
@@ -891,12 +897,14 @@ void radeon_engine_reset(struct radeonfb_info *rinfo)
 
     radeon_engine_flush(rinfo);
     clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
+
     /* Some ASICs have bugs with dynamic-on feature, which are
      * ASIC-version dependent, so we force all blocks on for now
      */
     if (rinfo->has_CRTC2)
     {
         unsigned long tmp;
+
         tmp = INPLL(SCLK_CNTL);
         OUTPLL(SCLK_CNTL, ((tmp & ~DYN_STOP_LAT_MASK) | CP_MAX_DYN_STOP_LAT | SCLK_FORCEON_MASK));
         if (rinfo->family == CHIP_FAMILY_RV200)
@@ -906,21 +914,28 @@ void radeon_engine_reset(struct radeonfb_info *rinfo)
         }
     }
     mclk_cntl = INPLL(MCLK_CNTL);
-    OUTPLL(MCLK_CNTL, (mclk_cntl | FORCEON_MCLKA | FORCEON_MCLKB
-     | FORCEON_YCLKA | FORCEON_YCLKB | FORCEON_MC | FORCEON_AIC));
-    /* Soft resetting HDP thru RBBM_SOFT_RESET register can cause some
+    OUTPLL(MCLK_CNTL, (mclk_cntl | FORCEON_MCLKA
+                                 | FORCEON_MCLKB
+                                 | FORCEON_YCLKA
+                                 | FORCEON_YCLKB
+                                 | FORCEON_MC
+                                 | FORCEON_AIC));
+
+    /*
+     * Soft resetting HDP thru RBBM_SOFT_RESET register can cause some
      * unexpected behaviour on some machines.  Here we use
      * HOST_PATH_CNTL to reset it.
      */
     host_path_cntl = INREG(HOST_PATH_CNTL);
+
     rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
-    if ((rinfo->family == CHIP_FAMILY_R300)
-     || (rinfo->family == CHIP_FAMILY_R350)
-     || (rinfo->family == CHIP_FAMILY_RV350))
+
+    if ((rinfo->family == CHIP_FAMILY_R300) || (rinfo->family == CHIP_FAMILY_R350)
+                                            || (rinfo->family == CHIP_FAMILY_RV350))
     {
         unsigned long tmp;
-        OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset
-         | SOFT_RESET_CP | SOFT_RESET_HI | SOFT_RESET_E2));
+
+        OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset | SOFT_RESET_CP | SOFT_RESET_HI | SOFT_RESET_E2));
         INREG(RBBM_SOFT_RESET);
         OUTREG(RBBM_SOFT_RESET, 0);
         tmp = INREG(RB2D_DSTCACHE_MODE);
@@ -929,26 +944,31 @@ void radeon_engine_reset(struct radeonfb_info *rinfo)
     else
     {
         OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset | SOFT_RESET_CP
-         | SOFT_RESET_HI | SOFT_RESET_SE | SOFT_RESET_RE
-         | SOFT_RESET_PP | SOFT_RESET_E2 | SOFT_RESET_RB));
+                                                 | SOFT_RESET_HI | SOFT_RESET_SE | SOFT_RESET_RE
+                                                 | SOFT_RESET_PP | SOFT_RESET_E2 | SOFT_RESET_RB));
+
         INREG(RBBM_SOFT_RESET);
-        OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset
-         & (unsigned long) ~(SOFT_RESET_CP | SOFT_RESET_HI | SOFT_RESET_SE
-          | SOFT_RESET_RE | SOFT_RESET_PP | SOFT_RESET_E2 | SOFT_RESET_RB)));
+
+        OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset & (unsigned long) ~(SOFT_RESET_CP | SOFT_RESET_HI | SOFT_RESET_SE
+                                                                   | SOFT_RESET_RE | SOFT_RESET_PP | SOFT_RESET_E2 | SOFT_RESET_RB)));
         INREG(RBBM_SOFT_RESET);
     }
     OUTREG(HOST_PATH_CNTL, host_path_cntl | HDP_SOFT_RESET);
     INREG(HOST_PATH_CNTL);
     OUTREG(HOST_PATH_CNTL, host_path_cntl);
+
     if ((rinfo->family != CHIP_FAMILY_R300)
      && (rinfo->family != CHIP_FAMILY_R350)
      && (rinfo->family != CHIP_FAMILY_RV350))
-    OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
+        OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
+
     OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
     OUTPLL(MCLK_CNTL, mclk_cntl);
 }
 
-/* Restore the acceleration hardware to its previous state */
+/*
+ * Restore the acceleration hardware to its previous state
+ */
 void radeon_engine_restore(struct radeonfb_info *rinfo)
 {
     BEGIN_ACCEL(1);
@@ -959,26 +979,33 @@ void radeon_engine_restore(struct radeonfb_info *rinfo)
      */
     /* Turn of all automatic flushing - we'll do it all */
     if ((rinfo->family != CHIP_FAMILY_R300)
-     && (rinfo->family != CHIP_FAMILY_R350)
-     && (rinfo->family != CHIP_FAMILY_RV350))
+            && (rinfo->family != CHIP_FAMILY_R350)
+            && (rinfo->family != CHIP_FAMILY_RV350))
         OUTREG(RB2D_DSTCACHE_MODE, 0);
+
     rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
+
     BEGIN_ACCEL(3);
     OUTREG(DEFAULT_PITCH_OFFSET, rinfo->dst_pitch_offset);
     OUTREG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset);
     OUTREG(SRC_PITCH_OFFSET, rinfo->dst_pitch_offset);
+
     BEGIN_ACCEL(1);
     if (rinfo->big_endian)
         OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
     else
-    OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
+        OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
+
     /* Restore SURFACE_CNTL - only the first head contains valid data */
     OUTREG(SURFACE_CNTL, rinfo->state.surface_cntl);
+
     BEGIN_ACCEL(2);
     OUTREG(DEFAULT_SC_TOP_LEFT, 0);
     OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | DEFAULT_SC_BOTTOM_MAX));
+
     BEGIN_ACCEL(1);
     OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl | GMC_BRUSH_SOLID_COLOR | GMC_SRC_DATATYPE_COLOR));
+
     BEGIN_ACCEL(7);
     OUTREG(DST_LINE_START, 0);
     OUTREG(DST_LINE_END, 0);
@@ -987,6 +1014,7 @@ void radeon_engine_restore(struct radeonfb_info *rinfo)
     OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
     OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
     OUTREG(DP_WRITE_MSK, 0xffffffff);
+
     radeon_wait_for_idle_mmio(rinfo);
 }
 
@@ -994,6 +1022,7 @@ void radeon_engine_restore(struct radeonfb_info *rinfo)
 void radeon_engine_init(struct radeonfb_info *rinfo)
 {
     unsigned long temp;
+
     OUTREG(RB3D_CNTL, 0);
     radeon_engine_reset(rinfo);
     temp = radeon_get_dstbpp(rinfo->depth);

radeon/radeon_cursor.c

@@ -78,7 +78,7 @@
     (OUTREG(SURFACE_CNTL, __surface_cntl));
 
 /* Set cursor foreground and background colors */
-void radeon_set_cursor_colors(struct fb_info *info, int bg, int fg)
+void radeon_set_cursor_colors(struct fb_info *info, int32_t bg, int32_t fg)
 {
     struct radeonfb_info *rinfo = info->par;
     unsigned long *pixels = (unsigned long *)((unsigned long) rinfo->fb_base + rinfo->cursor_start);
@@ -110,7 +110,7 @@ void radeon_set_cursor_colors(struct fb_info *info, int bg, int fg)
 /* Set cursor position to (x,y) with offset into cursor bitmap at
  * (xorigin,yorigin)
  */
-void radeon_set_cursor_position(struct fb_info *info, int x, int y)
+void radeon_set_cursor_position(struct fb_info *info, int32_t x, int32_t y)
 {
     struct radeonfb_info *rinfo = info->par;
     struct fb_var_screeninfo *mode = &info->var;
@@ -142,7 +142,7 @@ void radeon_set_cursor_position(struct fb_info *info, int x, int y)
  * Copy cursor image from `image' to video memory.  RADEONSetCursorPosition
  * will be called after this, so we can ignore xorigin and yorigin.
  */
-void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsigned short *data, int zoom)
+void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsigned short *data, int32_t zoom)
 {
     struct radeonfb_info *rinfo = info->par;
     unsigned long *d = (unsigned long *)((unsigned long)rinfo->fb_base+rinfo->cursor_start);

radeon/radeon_i2c.c

@@ -0,0 +1,237 @@
+#include "video.h"
+#include "radeonfb.h"
+#include "edid.h"
+#include "i2c.h"
+#include "driver_mem.h"
+
+// #define DEBUG
+#include "debug.h"
+
+
+#define CONFIG_FB_RADEON_I2C
+#ifdef CONFIG_FB_RADEON_I2C
+
+#define RADEON_DDC 	0x50
+
+static void radeon_gpio_setscl(void* data, int state)
+{
+    struct radeon_i2c_chan *chan = data;
+    struct radeonfb_info *rinfo = chan->rinfo;
+    unsigned long val;
+
+    val = INREG(chan->ddc_reg) & ~(VGA_DDC_CLK_OUT_EN);
+
+    if (!state)
+        val |= VGA_DDC_CLK_OUT_EN;
+    OUTREG(chan->ddc_reg, val);
+    (void) INREG(chan->ddc_reg);
+}
+
+static void radeon_gpio_setsda(void* data, int state)
+{
+    struct radeon_i2c_chan *chan = data;
+    struct radeonfb_info *rinfo = chan->rinfo;
+    unsigned long val;
+
+    val = INREG(chan->ddc_reg) & ~(VGA_DDC_DATA_OUT_EN);
+    if (!state)
+        val |= VGA_DDC_DATA_OUT_EN;
+    OUTREG(chan->ddc_reg, val);
+    (void) INREG(chan->ddc_reg);
+}
+
+static int radeon_gpio_getscl(void* data)
+{
+    struct radeon_i2c_chan *chan = data;
+    struct radeonfb_info *rinfo = chan->rinfo;
+    unsigned long val;
+
+    val = INREG(chan->ddc_reg);
+    return (val & VGA_DDC_CLK_INPUT) ? 1 : 0;
+}
+
+static int radeon_gpio_getsda(void* data)
+{
+    struct radeon_i2c_chan *chan = data;
+    struct radeonfb_info *rinfo = chan->rinfo;
+    unsigned long val;
+    val = INREG(chan->ddc_reg);
+    return(val & VGA_DDC_DATA_INPUT) ? 1 : 0;
+}
+
+static int radeon_setup_i2c_bus(struct radeon_i2c_chan *chan)
+{
+    int rc;
+    chan->adapter.algo_data = &chan->algo;
+    chan->algo.setsda = radeon_gpio_setsda;
+    chan->algo.setscl = radeon_gpio_setscl;
+    chan->algo.getsda = radeon_gpio_getsda;
+    chan->algo.getscl = radeon_gpio_getscl;
+    chan->algo.udelay = 40;
+    chan->algo.timeout = 20;
+    chan->algo.data = chan;
+    /* Raise SCL and SDA */
+    radeon_gpio_setsda(chan, 1);
+    radeon_gpio_setscl(chan, 1);
+    udelay(20);
+    rc = i2c_bit_add_bus(&chan->adapter);
+    return rc;
+}
+
+void radeon_create_i2c_busses(struct radeonfb_info *rinfo)
+{
+    rinfo->i2c[0].rinfo	= rinfo;
+    rinfo->i2c[0].ddc_reg	= GPIO_MONID;
+    radeon_setup_i2c_bus(&rinfo->i2c[0]);
+    rinfo->i2c[1].rinfo	= rinfo;
+    rinfo->i2c[1].ddc_reg	= GPIO_DVI_DDC;
+    radeon_setup_i2c_bus(&rinfo->i2c[1]);
+    rinfo->i2c[2].rinfo	= rinfo;
+    rinfo->i2c[2].ddc_reg	= GPIO_VGA_DDC;
+    radeon_setup_i2c_bus(&rinfo->i2c[2]);
+    rinfo->i2c[3].rinfo	= rinfo;
+    rinfo->i2c[3].ddc_reg	= GPIO_CRT2_DDC;
+    radeon_setup_i2c_bus(&rinfo->i2c[3]);
+}
+
+#if 0
+void radeon_delete_i2c_busses(struct radeonfb_info *rinfo)
+{
+    if(rinfo->i2c[0].rinfo)
+        i2c_bit_del_bus(&rinfo->i2c[0].adapter);
+    rinfo->i2c[0].rinfo = NULL;
+    if(rinfo->i2c[1].rinfo)
+        i2c_bit_del_bus(&rinfo->i2c[1].adapter);
+    rinfo->i2c[1].rinfo = NULL;
+    if(rinfo->i2c[2].rinfo)
+        i2c_bit_del_bus(&rinfo->i2c[2].adapter);
+    rinfo->i2c[2].rinfo = NULL;
+    if(rinfo->i2c[3].rinfo)
+        i2c_bit_del_bus(&rinfo->i2c[3].adapter);
+    rinfo->i2c[3].rinfo = NULL;
+}
+#endif
+
+static unsigned char *radeon_do_probe_i2c_edid(struct radeon_i2c_chan *chan)
+{
+    unsigned char start = 0x0;
+    struct i2c_msg msgs[] =
+    {
+        {
+            .addr = RADEON_DDC,
+            .len = 1,
+            .buf = &start,
+        },
+        {
+            .addr = RADEON_DDC,
+            .flags = I2C_M_RD,
+            .len = EDID_LENGTH,
+        },
+    };
+
+    unsigned char *buf;
+
+    buf = driver_mem_alloc(EDID_LENGTH * 3);
+    if (!buf)
+        return NULL;
+
+    msgs[1].buf = buf;
+    if (i2c_transfer(&chan->adapter, msgs, 2) == 2)
+        return buf;
+    else
+        dbg("i2c_transfer() failed\r\n");
+
+    driver_mem_free(buf);
+    return NULL;
+}
+
+int32_t radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int32_t conn, uint8_t **out_edid)
+{
+    unsigned long reg = rinfo->i2c[conn - 1].ddc_reg;
+    unsigned char *edid = NULL;
+    int i, j;
+
+    OUTREG(reg, INREG(reg) & ~(VGA_DDC_DATA_OUTPUT | VGA_DDC_CLK_OUTPUT));
+    OUTREG(reg, INREG(reg) & ~(VGA_DDC_CLK_OUT_EN));
+    (void) INREG(reg);
+
+    for(i = 0; i < 3; i++)
+    {
+        /* For some old monitors we need the
+         * following process to initialize/stop DDC
+         */
+        OUTREG(reg, INREG(reg) & ~(VGA_DDC_DATA_OUT_EN));
+        (void)INREG(reg);
+        wait_ms(13);
+
+        OUTREG(reg, INREG(reg) & ~(VGA_DDC_CLK_OUT_EN));
+        (void)INREG(reg);
+
+        for(j = 0; j < 5; j++)
+        {
+            wait_ms(10);
+            if (INREG(reg) & VGA_DDC_CLK_INPUT)
+                break;
+        }
+
+        if (j == 5)
+            continue;
+
+        OUTREG(reg, INREG(reg) | VGA_DDC_DATA_OUT_EN);
+        (void) INREG(reg);
+        wait_ms(15);
+
+        OUTREG(reg, INREG(reg) | VGA_DDC_CLK_OUT_EN);
+        (void) INREG(reg);
+        wait_ms(15);
+
+        OUTREG(reg, INREG(reg) & ~(VGA_DDC_DATA_OUT_EN));
+        (void) INREG(reg);
+        wait_ms(15);
+
+        /* Do the real work */
+        edid = radeon_do_probe_i2c_edid(&rinfo->i2c[conn - 1]);
+        OUTREG(reg, INREG(reg) | (VGA_DDC_DATA_OUT_EN | VGA_DDC_CLK_OUT_EN));
+        (void) INREG(reg);
+        wait_ms(15);
+        OUTREG(reg, INREG(reg) & ~(VGA_DDC_CLK_OUT_EN));
+        (void) INREG(reg);
+        for(j = 0; j < 10; j++)
+        {
+            wait_ms(10);
+            if (INREG(reg) & VGA_DDC_CLK_INPUT)
+                break;
+        }
+        OUTREG(reg, INREG(reg) & ~(VGA_DDC_DATA_OUT_EN));
+        (void) INREG(reg);
+        wait_ms(15);
+
+        OUTREG(reg, INREG(reg) | (VGA_DDC_DATA_OUT_EN | VGA_DDC_CLK_OUT_EN));
+        (void) INREG(reg);
+
+        if (edid)
+            break;
+    }
+    /* Release the DDC lines when done or the Apple Cinema HD display
+     * will switch off */
+    OUTREG(reg, INREG(reg) & ~(VGA_DDC_CLK_OUT_EN | VGA_DDC_DATA_OUT_EN));
+    (void) INREG(reg);
+
+    if (out_edid)
+        *out_edid = edid;
+
+    if (!edid)
+        return MT_NONE;
+
+    if (edid[0x14] & 0x80)
+    {
+        /* Fix detection using BIOS tables */
+        if(rinfo->is_mobility /*&& conn == ddc_dvi*/ && (INREG(LVDS_GEN_CNTL) & LVDS_ON))
+            return MT_LCD;
+        else
+            return MT_DFP;
+    }
+    return MT_CRT;
+}
+
+#endif /* CONFIG_FB_RADEON_I2C */

radeon/radeon_monitor.c

@@ -4,13 +4,10 @@
 #include "driver_mem.h"
 #include "bas_printf.h"
 #include "bas_string.h"
+#include "video.h"
 
-//#define DBG_MONITOR
-#ifdef DBG_MONITOR
-#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
-#else
-#define dbg(format, arg...) do { ; } while (0)
-#endif /* DBG_MONITOR */
+// #define DEBUG
+#include "debug.h"
 
 #ifndef INT_MAX
 #define INT_MAX ((int) (~0U >> 1))
@@ -29,7 +26,7 @@ static struct fb_var_screeninfo radeonfb_default_var =
     .activate = FB_ACTIVATE_NOW,
     .height = -1,
     .width = -1,
-    .pixclock = 39721,
+    .pixclock = 9295,
     .left_margin = 40,
     .right_margin = 24,
     .upper_margin = 32,
@@ -39,7 +36,7 @@ static struct fb_var_screeninfo radeonfb_default_var =
     .vmode = FB_VMODE_NONINTERLACED
 };
 
-static char *radeon_get_mon_name(int type)
+char *radeon_get_mon_name(int type)
 {
     char *pret = NULL;
     switch(type)
@@ -136,7 +133,7 @@ static int radeon_parse_monitor_layout(struct radeonfb_info *rinfo, const char *
 
     if ((monitor_layout == NULL) || (*monitor_layout == '\0'))
     {
-        dbg("%s: monitor_layout missing\r\n");
+        dbg("monitor_layout missing\r\n");
         return 0;
     }
 
@@ -175,36 +172,38 @@ static int radeon_parse_monitor_layout(struct radeonfb_info *rinfo, const char *
         s2[0] = '\0';
     }
 
-    if (strcmp(s1, "CRT"))
+    dbg("s1=%s, s2=%s \r\n", s1, s2);
+
+    if (!strcmp(s1, "CRT"))
     {
         rinfo->mon1_type = MT_CRT;
-        dbg("%s: monitor 1 set to CRT\r\n", __FUNCTION__);
+        dbg("monitor 1 set to CRT\r\n");
     }
-    else if (strcmp(s1, "TMDS"))
+    else if (!strcmp(s1, "TMDS"))
     {
         rinfo->mon1_type = MT_DFP;
-        dbg("%s: monitor 1 set to TMDS\r\n", __FUNCTION__);
+        dbg("monitor 1 set to TMDS\r\n");
     }
-    else if (strcmp(s1, "LVDS"))
+    else if (!strcmp(s1, "LVDS"))
     {
         rinfo->mon1_type = MT_LCD;
-        dbg("%s: monitor 1 set to LVDS\r\n", __FUNCTION__);
+        dbg("monitor 1 set to LVDS\r\n");
     }
 
-    if (strcmp(s2, "CRT"))
+    if (!strcmp(s2, "CRT"))
     {
         rinfo->mon2_type = MT_CRT;
-        dbg("%s: monitor 2 set to CRT\r\n", __FUNCTION__);
+        dbg("monitor 2 set to CRT\r\n");
     }
-    else if (strcmp(s2, "TMDS"))
+    else if (!strcmp(s2, "TMDS"))
     {
         rinfo->mon2_type = MT_DFP;
-        dbg("%s: monitor 2 set to TMDS\r\n", __FUNCTION__);
+        dbg("monitor 2 set to TMDS\r\n");
     }
-    else if (strcmp(s2, "LVDS"))
+    else if (!strcmp(s2, "LVDS"))
     {
         rinfo->mon2_type = MT_LCD;
-        dbg("%s: monitor 2 set to LVDS\r\n", __FUNCTION__);
+        dbg("monitor 2 set to LVDS\r\n");
     }
     return 1;
 }
@@ -213,11 +212,14 @@ static int radeon_parse_monitor_layout(struct radeonfb_info *rinfo, const char *
  * Probe display on both primary and secondary card's connector (if any)
  * by i2c and try to retreive EDID. The algorithm here comes from XFree's * radeon driver
  */
-void radeon_probe_screens(struct radeonfb_info *rinfo, const char *monitor_layout, int ignore_edid)
+void radeon_probe_screens(struct radeonfb_info *rinfo, const char *monitor_layout, int32_t ignore_edid)
 {
+
 #ifdef CONFIG_FB_RADEON_I2C
     int ddc_crt2_used = 0;
 #endif
+
+    dbg("monitor_layout=%s\r\n", monitor_layout);
     if (radeon_parse_monitor_layout(rinfo, monitor_layout))
     {
         /*
@@ -227,25 +229,25 @@ void radeon_probe_screens(struct radeonfb_info *rinfo, const char *monitor_layou
          * a layout for each card ?
          */
 #ifdef CONFIG_FB_RADEON_I2C
-        dbg("%s: use monitor layout\r\n", __FUNCTION__);
+        dbg("use monitor layout\r\n");
         if (!ignore_edid)
         {
             if (rinfo->mon1_type != MT_NONE)
             {
-                dbg("%s: probe ddc_dvi on MON1\r\n", __FUNCTION__);
+                dbg("probe ddc_dvi on MON1\r\n");
                 if (!radeon_probe_i2c_connector(rinfo, ddc_dvi, &rinfo->mon1_EDID))
                 {
-                    dbg("%s: probe ddc_crt2 on MON1\r\n", __FUNCTION__);
+                    dbg("probe ddc_crt2 on MON1\r\n");
                     radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon1_EDID);
                     ddc_crt2_used = 1;
                 }
             }
             if (rinfo->mon2_type != MT_NONE)
             {
-                dbg("%s: probe ddc_vga on MON2\r\n", __FUNCTION__);
+                dbg("probe ddc_vga on MON2\r\n");
                 if (!radeon_probe_i2c_connector(rinfo, ddc_vga, &rinfo->mon2_EDID) && !ddc_crt2_used)
                 {
-                    dbg("%s: probe ddc_crt2 on MON2\r\n", __FUNCTION__);
+                    dbg("probe ddc_crt2 on MON2\r\n");
                     radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon2_EDID);
                 }
             }
@@ -261,7 +263,7 @@ void radeon_probe_screens(struct radeonfb_info *rinfo, const char *monitor_layou
             else
             {
                 rinfo->mon1_type = MT_CRT;
-                dbg("%s: No valid monitor, assuming CRT on first port\r\n", __FUNCTION__);
+                dbg("No valid monitor, assuming CRT on first port\r\n");
             }
             rinfo->mon2_type = MT_NONE;
             rinfo->mon2_EDID = NULL;
@@ -273,7 +275,7 @@ void radeon_probe_screens(struct radeonfb_info *rinfo, const char *monitor_layou
          * Auto-detecting display type (well... trying to ...)
          */
 #ifdef CONFIG_FB_RADEON_I2C
-        dbg("%s: Auto-detecting\r\n", __FUNCTION__);
+        dbg("Auto-detecting\r\n");
 #endif
 #if 0 //#if DEBUG && defined(CONFIG_FB_RADEON_I2C)
         {
@@ -292,17 +294,17 @@ void radeon_probe_screens(struct radeonfb_info *rinfo, const char *monitor_layou
 #ifdef CONFIG_FB_RADEON_I2C
             if (rinfo->mon1_type == MT_NONE)
             {
-                dbg("%s: probe ddc_dvi on MON1\r\n", __FUNCTION__);
+                dbg("probe ddc_dvi on MON1\r\n");
                 rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_dvi, &rinfo->mon1_EDID);
             }
             if (rinfo->mon1_type == MT_NONE)
             {
-                dbg("%s: probe ddc_vga on MON1\r\n", __FUNCTION__);
+                dbg("probe ddc_vga on MON1\r\n");
                 rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_vga, &rinfo->mon1_EDID);
             }
             if (rinfo->mon1_type == MT_NONE)
             {
-                dbg("%s: probe ddc_crt2 on MON1\r\n", __FUNCTION__);
+                dbg("probe ddc_crt2 on MON1\r\n");
                 rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon1_EDID);
             }
 #endif /* CONFIG_FB_RADEON_I2C */
@@ -316,12 +318,12 @@ void radeon_probe_screens(struct radeonfb_info *rinfo, const char *monitor_layou
 #ifdef CONFIG_FB_RADEON_I2C
         if (rinfo->mon1_type == MT_NONE)
         {
-            dbg("%s: probe ddc_dvi on MON1\r\n", __FUNCTION__);
+            dbg("probe ddc_dvi on MON1\r\n");
             rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_dvi, &rinfo->mon1_EDID);
         }
         if (rinfo->mon1_type == MT_NONE)
         {
-            dbg("%s: probe ddc_crt2 on MON1\r\n", __FUNCTION__);
+            dbg("probe ddc_crt2 on MON1\r\n");
             rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon1_EDID);
             if (rinfo->mon1_type != MT_NONE)
                 ddc_crt2_used = 1;
@@ -331,7 +333,7 @@ void radeon_probe_screens(struct radeonfb_info *rinfo, const char *monitor_layou
                 && (INREG(LVDS_GEN_CNTL) & LVDS_ON))
         {
             rinfo->mon1_type = MT_LCD;
-            dbg("%s: Non-DDC laptop panel detected\r\n", __FUNCTION__);
+            dbg("Non-DDC laptop panel detected\r\n");
         }
         if (rinfo->mon1_type == MT_NONE)
             rinfo->mon1_type = radeon_crt_is_connected(rinfo, rinfo->reversed_DAC);
@@ -341,12 +343,12 @@ void radeon_probe_screens(struct radeonfb_info *rinfo, const char *monitor_layou
 #ifdef CONFIG_FB_RADEON_I2C
         if (rinfo->mon2_type == MT_NONE)
         {
-            dbg("%s: probe ddc_vga on MON2\r\n", __FUNCTION__);
+            dbg("probe ddc_vga on MON2\r\n");
             rinfo->mon2_type = radeon_probe_i2c_connector(rinfo, ddc_vga,	&rinfo->mon2_EDID);
         }
         if (rinfo->mon2_type == MT_NONE && !ddc_crt2_used)
         {
-            dbg("%s: probe ddc_crt2 on MON2\r\n", __FUNCTION__);
+            dbg("probe ddc_crt2 on MON2\r\n");
             rinfo->mon2_type = radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon2_EDID);
         }
 #endif /* CONFIG_FB_RADEON_I2C */
@@ -399,18 +401,18 @@ void radeon_probe_screens(struct radeonfb_info *rinfo, const char *monitor_layou
     }
 
 bail:
-    dbg("%s: Monitor 1 type %s found\r\n", __FUNCTION__, radeon_get_mon_name(rinfo->mon1_type));
+    dbg("Monitor 1 type %s found\r\n", radeon_get_mon_name(rinfo->mon1_type));
     if (rinfo->mon1_EDID)
     {
-        dbg("%s: EDID probed\r\n", __FUNCTION__);
+        dbg("EDID probed\r\n");
     }
 
     if (!rinfo->has_CRTC2)
         return;
-    dbg("%s: Monitor 2 type %s\r\n", __FUNCTION__, radeon_get_mon_name(rinfo->mon2_type));
+    dbg("Monitor 2 type %s\r\n", radeon_get_mon_name(rinfo->mon2_type));
     if (rinfo->mon2_EDID)
     {
-        dbg("%s: EDID probed\r\n", __FUNCTION__);
+        dbg("EDID probed\r\n");
     }
 }
 
@@ -432,6 +434,7 @@ static void radeon_var_to_panel_info(struct radeonfb_info *rinfo, struct fb_var_
     rinfo->panel_info.hAct_high = (var->sync & FB_SYNC_HOR_HIGH_ACT) != 0;
     rinfo->panel_info.vAct_high = (var->sync & FB_SYNC_VERT_HIGH_ACT) != 0;
     rinfo->panel_info.valid = 1;
+
     /*
      * We use a default of 200ms for the panel power delay,
      * I need to have a real schedule() instead of mdelay's in the panel code.
@@ -470,7 +473,7 @@ void radeon_check_modes(struct radeonfb_info *rinfo, struct mode_option *resolut
     struct fb_info *info = rinfo->info;
     int has_default_mode = 0;
     struct mode_option xres_yres;
-    dbg("%s: radeon_check_modes\r\n", __FUNCTION__);
+    dbg("\r\n");
 
     /*
      * Fill default var first
@@ -487,7 +490,7 @@ void radeon_check_modes(struct radeonfb_info *rinfo, struct mode_option *resolut
     {
         struct fb_var_screeninfo var;
 
-        dbg("%s: fb_parse_edid\r\n", __FUNCTION__);
+        dbg("fb_parse_edid\r\n");
         if (fb_parse_edid(rinfo->mon1_EDID, &var) == 0)
         {
             if ((var.xres >= rinfo->panel_info.xres) && (var.yres >= rinfo->panel_info.yres))
@@ -495,7 +498,7 @@ void radeon_check_modes(struct radeonfb_info *rinfo, struct mode_option *resolut
         }
         else
         {
-            dbg("%s: no data to parse\r\n", __FUNCTION__);
+            dbg("no data to parse\r\n");
         }
     }
     /*
@@ -505,7 +508,8 @@ void radeon_check_modes(struct radeonfb_info *rinfo, struct mode_option *resolut
     if (rinfo->mon1_type != MT_CRT && rinfo->panel_info.valid)
     {
         struct fb_var_screeninfo *var = &info->var;
-        dbg("%s: setup the default mode based on panel info\r\n", __FUNCTION__);
+
+        dbg("setup the default mode based on panel info\r\n");
         var->xres = rinfo->panel_info.xres;
         var->yres = rinfo->panel_info.yres;
         var->xres_virtual = rinfo->panel_info.xres;
@@ -580,7 +584,9 @@ void radeon_check_modes(struct radeonfb_info *rinfo, struct mode_option *resolut
         has_default_mode = 1;
         radeon_var_to_panel_info(rinfo, &info->var);
     }
+
 pickup_default:
+
     /*
      * Apply passed-in mode option if any
      */
@@ -590,6 +596,7 @@ pickup_default:
                          info->monspecs.modedb_len, NULL, (resolution->bpp >= 8) ? (unsigned int)resolution->bpp : 8) != 0)
             has_default_mode = 1;
     }
+
     /*
      * Still no mode, let's pick up a default from the db
      */
@@ -654,7 +661,7 @@ static int radeon_compare_modes(const struct fb_var_screeninfo *var,
  * outputs a valid mode matching the passed-in one as closely as possible.
  * We need something better ultimately.
  */
-int radeon_match_mode(struct radeonfb_info *rinfo,
+int32_t radeon_match_mode(struct radeonfb_info *rinfo,
                       struct fb_var_screeninfo *dest,
                       const struct fb_var_screeninfo *src)
 {
@@ -664,7 +671,7 @@ int radeon_match_mode(struct radeonfb_info *rinfo,
     int	distance = INT_MAX;
     const struct fb_videomode	*candidate = NULL;
 
-    dbg("%s:\r\n", __FUNCTION__);
+    dbg("\r\n");
 
     /* Start with a copy of the requested mode */
     memcpy(dest, src, sizeof(struct fb_var_screeninfo));
@@ -698,7 +705,7 @@ int radeon_match_mode(struct radeonfb_info *rinfo,
         }
         return 0;
     }
-    dbg("%s:look for a mode in the database\r\n", __FUNCTION__);
+    dbg("look for a mode in the database\r\n");
 
     /* Now look for a mode in the database */
     while(db)

spi/dspi.c

@@ -127,7 +127,8 @@ int dspi_set_baudrate(int rate)
         pbr = baudrates[i].pbr_divisor;
 
         /* TODO: set br and pbr here */
-
+        (void) pbr;
+        (void) br;
         return set_baudrate;
     }
 
@@ -162,7 +163,7 @@ uint8_t dspi_xchg_byte(int device, uint8_t byte, int last)
  * buff: pointer to data buffer
  * btr: number of bytes to receive (16, 64 or 512)
  */
-static void dspi_rcv_byte_multi(int device, uint8_t *buff, uint32_t count)
+void dspi_rcv_byte_multi(int device, uint8_t *buff, uint32_t count)
 {
     int i;
 
@@ -176,7 +177,7 @@ static void dspi_rcv_byte_multi(int device, uint8_t *buff, uint32_t count)
  * buff: pointer to data
  * btx: number of bytes to send
  */
-static void dspi_xmt_byte_multi(int device, const uint8_t *buff, uint32_t btx)
+void dspi_xmt_byte_multi(int device, const uint8_t *buff, uint32_t btx)
 {
     int i;
 

spi/mmc.c

@@ -20,7 +20,7 @@
 
 /* Copyright (C) 2012, mfro, all rights reserved. */
 
-// #define DEBUG_MMC
+// // #define DEBUG_MMC
 #ifdef DEBUG_MMC
 #define debug_printf(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg); } while (0)
 #else

sys/BaS.c

@@ -31,6 +31,7 @@
 #include "bas_printf.h"
 #include "bas_string.h"
 #include "bas_types.h"
+#include "bas_utils.h"
 #include "sd_card.h"
 #include "wait.h"
 
@@ -51,13 +52,8 @@
 #include "pci.h"
 #include "video.h"
 
-//#define BAS_DEBUG
-#if defined(BAS_DEBUG)
-#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
-#else
-#define dbg(format, arg...) do { ; } while (0)
-#endif
-#define err(format, arg...) do { xprintf("ERROR: %s(): " format, __FUNCTION__, ##arg); } while (0)
+// // #define DEBUG
+#include "debug.h"
 
 /* imported routines */
 extern int vec_init();
@@ -222,6 +218,7 @@ void enable_coldfire_interrupts()
 
     MCF_EPORT_EPPAR = 0xaaa8;               /* all interrupts on falling edge */
 
+#ifdef _NOT_USED_
 #if defined(MACHINE_FIREBEE)
     /*
      * TIN0 on the Coldfire is connected to the FPGA. TIN0 triggers every write
@@ -231,10 +228,10 @@ void enable_coldfire_interrupts()
             MCF_GPT_GMS_IEN |
             MCF_GPT_GMS_TMS(1);             /* route GPT0 interrupt on interrupt controller */
     MCF_INTC_ICR62 = MCF_INTC_ICR_IL(7) |
-                     MCF_INTC_ICR_IP(6);    /* interrupt level 7, interrupt priority 7 */
+                     MCF_INTC_ICR_IP(6);    /* interrupt level 7, interrupt priority 6 */
     MCF_INTC_IMRH = 0xbffffffe;             /* psc3 and timer 0 int on */
 #endif
-
+#endif
     xprintf("finished\r\n");
 }
 
@@ -293,9 +290,10 @@ NIF nif2;
 
 bool spurious_interrupt_handler(void *arg1, void *arg2)
 {
-    dbg("IMRH=%lx, IMRL=%lx\r\n", MCF_INTC_IMRH, MCF_INTC_IMRL);
-    dbg("IPRH=%lx, IPRL=%lx\r\n", MCF_INTC_IPRH, MCF_INTC_IPRL);
-    dbg("IRLR=%x\r\n", MCF_INTC_IRLR);
+    err("spurious interrupt\r\n");
+    err("IMRH=%lx, IMRL=%lx\r\n", MCF_INTC_IMRH, MCF_INTC_IMRL);
+    err("IPRH=%lx, IPRL=%lx\r\n", MCF_INTC_IPRH, MCF_INTC_IPRL);
+    err("IRLR=%x\r\n", MCF_INTC_IRLR);
 
     return true;
 }
@@ -353,7 +351,7 @@ void init_isr(void)
     /*
      * register the XLB PCI interrupt handler
      */
-    if (!isr_register_handler(64 + INT_SOURCE_XLBPCI, 7, 0, xlbpci_interrupt_handler, NULL, NULL))
+    if (!isr_register_handler(64 + INT_SOURCE_XLBPCI, 3, 0, xlbpci_interrupt_handler, NULL, NULL))
     {
         dbg("Error: unable to register isr for XLB PCI interrupts\r\n");
     }
@@ -366,7 +364,7 @@ void init_isr(void)
                        MCF_XLB_XARB_IMR_TTME |          /* TBST/TSIZ mismatch interrupt */
                        MCF_XLB_XARB_IMR_BAE;            /* bus activity tenure timeout interrupt */
 
-    if (!isr_register_handler(64 + INT_SOURCE_PCIARB, 5, 1, pciarb_interrupt_handler, NULL, NULL))
+    if (!isr_register_handler(64 + INT_SOURCE_PCIARB, 5, 0, pciarb_interrupt_handler, NULL, NULL))
     {
         dbg("Error: unable to register isr for PCIARB interrupts\r\n");
 
@@ -374,6 +372,34 @@ void init_isr(void)
     }
     MCF_PCIARB_PACR = MCF_PCIARB_PACR_EXTMINTEN(0x1f) | /* external master broken interrupt */
                       MCF_PCIARB_PACR_INTMINTEN;        /* internal master broken interrupt */
+
+    if (!isr_register_handler(64 + INT_SOURCE_XLBARB, 7, 1, xlbarb_interrupt_handler, NULL, NULL))
+    {
+        dbg("Error: unable to register isr for XLB ARB interrupts\r\n");
+    }
+}
+
+/* Jump into the OS */
+typedef void void_func(void);
+struct rom_header
+{
+    void *initial_sp;
+    void_func *initial_pc;
+};
+
+/*
+ * fix ST RAM header (address 0x0 and 0x4). FreeMiNT uses these vectors on CTRL-ALT-DEL.
+ *
+ * Beware: Newer compilers refuse to dereference pointers to NULL and abort if the following
+ * attribute isn't set.
+ */
+static void fix_stram_header() __attribute__((optimize("no-delete-null-pointer-checks")));
+static void fix_stram_header()
+{
+    struct rom_header *bas_header = (struct rom_header *) TARGET_ADDRESS;
+    struct rom_header *stram_header = (struct rom_header *) 0x0;
+
+    *stram_header = *bas_header;
 }
 
 void BaS(void)
@@ -397,7 +423,7 @@ void BaS(void)
     xprintf("copy EmuTOS: ");
     /* copy EMUTOS */
     src = (uint8_t *) EMUTOS;
-    dma_memcpy(dst, src, EMUTOS_SIZE);
+    memcpy(dst, src, EMUTOS_SIZE);
     xprintf("finished\r\n");
 
     xprintf("initialize exception vector table: ");
@@ -443,7 +469,7 @@ void BaS(void)
     /*
      * memory setup
      */
-    memset((void *) 0x200, 0, 0x400);
+    // memset((void *) 0x200, 0, 0x400);
 
 #if defined(MACHINE_FIREBEE)
     /* set Falcon bus control register */
@@ -470,14 +496,6 @@ void BaS(void)
 
     srec_execute("BASFLASH.S19");
 
-    /* Jump into the OS */
-    typedef void void_func(void);
-    struct rom_header
-    {
-        void *initial_sp;
-        void_func *initial_pc;
-    };
-
     xprintf("BaS initialization finished, enable interrupts\r\n");
     init_isr();
 
@@ -509,6 +527,12 @@ void BaS(void)
         MCF_MMU_MMUCR = 0;  /* MMU off */
         NOP();              /* force pipeline sync */
 
+
+        /*
+         * FireTOS wants to have the TOS system variables cleared
+         */
+        memset((void *) 0x400, 0, 0x400);
+
         /* ST RAM */
 
         * (uint32_t *) 0x42e = STRAM_END;   /* phystop TOS system variable */
@@ -523,11 +547,18 @@ void BaS(void)
 
         xprintf("call FireTOS\r\n");
         /* Jump into FireTOS */
-        typedef void void_func(void);
+
         void_func* FireTOS = (void_func*) FIRETOS;
         FireTOS();  // Should never return
     }
 
+    /*
+     * fix initial pc/sp in ST RAM for FreeMiNT. It expects valid values there
+     * like on original STs (where these values reside in ROM) and uses them on
+     * CTRL-ALT-DELETE reboots.
+     */
+    fix_stram_header();
+
     xprintf("call EmuTOS\r\n");
     struct rom_header *os_header = (struct rom_header *) TOS;
     os_header->initial_pc();

sys/cache.c

@@ -66,17 +66,17 @@ void flush_and_invalidate_caches(void)
             "	clr.l		d0                  \n\t"
             "	clr.l		d1                  \n\t"
             "	move.l		d0,a0               \n\t"
-            "cfa_setloop:                       \n\t"
+            "1:                                 \n\t"
             "	cpushl		bc,(a0)				| flush\n\t"
             "	lea			0x10(a0),a0			| index+1\n\t"
             "	addq.l		#1,d1				| index+1\n\t"
             "	cmpi.w		#512,d1				| all sets?\n\t"
-            "	bne.s		cfa_setloop			| no->\n\t"
+            "	bne.s		1b					| no->\n\t"
             "	clr.l		d1                  \n\t"
             "	addq.l		#1,d0               \n\t"
             "	move.l		d0,a0               \n\t"
             "	cmpi.w		#4,d0				| all ways?\n\t"
-            "	bne.s		cfa_setloop			| no->\n\t"
+            "	bne.s		1b					| no->\n\t"
             /* input */	:
             /* output */	:
             /* clobber */	: "cc", "d0", "d1", "a0"

sys/driver_mem.c

@@ -11,6 +11,7 @@
  * option any later version.
  */
 
+
 #include <bas_types.h>
 #include "bas_string.h"
 #include "bas_printf.h"
@@ -27,13 +28,8 @@
 #error "unknown machine!"
 #endif
 
-//#define DBG_DM
-#ifdef	DBG_DM
-#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
-#else
-#define dbg(format, arg...) do { ; } while (0)
-#endif
-#define err(format, arg...) do { xprintf("ERROR: %s(): " format, __FUNCTION__, ##arg); } while (0)
+// #define DEBUG
+#include "debug.h"
 
 extern long offscren_reserved(void);
 
@@ -259,7 +255,7 @@ int32_t driver_mem_free(void *addr)
     freeit(p, mpb);
     set_ipl(level);
 
-    dbg("%s: driver_mem_free(0x%08X)\r\n", __FUNCTION__, addr);
+    dbg("addr=0x%08X)\r\n", addr);
 
     return(0);
 }
@@ -293,7 +289,7 @@ void *driver_mem_alloc(uint32_t amount)
         ret = (void *) m->m_start;
     }
     set_ipl(level);
-    dbg("%s: driver_mem_alloc(%d) = 0x%08X\r\n", __FUNCTION__, amount, ret);
+    dbg("alloc(%d) = 0x%08X\r\n", amount, ret);
 
     return ret;
 }
@@ -304,7 +300,7 @@ int driver_mem_init(void)
 {
     if (use_count == 0)
     {
-        dbg("%s: initialise driver_mem_buffer[] at %p, size 0x%x\r\n", __FUNCTION__, driver_mem_buffer, DRIVER_MEM_BUFFER_SIZE);
+        dbg("initialise driver_mem_buffer[] at %p, size 0x%x\r\n", driver_mem_buffer, DRIVER_MEM_BUFFER_SIZE);
         memset(driver_mem_buffer, 0, DRIVER_MEM_BUFFER_SIZE);
 
         pmd.mp_mfl = pmd.mp_rover = &tab_md[0];
@@ -315,10 +311,10 @@ int driver_mem_init(void)
         pmd.mp_mal = (MD *) NULL;
         memset(driver_mem_buffer, 0, tab_md[0].m_length);
 
-        dbg("%s: uncached driver memory buffer at 0x%08X size %d\r\n", __FUNCTION__, tab_md[0].m_start, tab_md[0].m_length);
+        dbg("uncached driver memory buffer at 0x%08X size %d\r\n", tab_md[0].m_start, tab_md[0].m_length);
     }
     use_count++;
-    dbg("%s: driver_mem now has a use count of %d\r\n", __FUNCTION__, use_count);
+    dbg("driver_mem now has a use count of %d\r\n", use_count);
 
     return 0;
 }
@@ -335,7 +331,7 @@ void driver_mem_release(void)
 #endif
 #endif
     }
-    dbg("%s: driver_mem use count now %d\r\n", __FUNCTION__, use_count);
+    dbg("driver_mem use count now %d\r\n", use_count);
 }
 
 

sys/exceptions.S

@@ -236,6 +236,9 @@ init_vec_loop:
 // install lowlevel_isr_handler for the XLBPCI interrupt
         move.l  a1,(INT_SOURCE_XLBPCI + 64) * 4(a0)
 
+// install lowlevel_isr_handler for the XLBARB interrupt
+	move.l	a1,(INT_SOURCE_XLBARB + 64) * 4(a0)
+
 // install lowlevel_isr_handler for the FEC0  interrupt
         move.l  a1,(INT_SOURCE_FEC0 + 64) * 4(a0)
 
@@ -247,7 +250,7 @@ init_vec_loop:
 #ifdef MACHINE_FIREBEE
 
 // timer vectors (triggers when vbashi gets changed, used for video page copy)
-        move.l  a1,(INT_SOURCE_GPT0 + 64) * 4(a0)
+        // move.l  a1,(INT_SOURCE_GPT0 + 64) * 4(a0)
 #endif /* MACHINE_FIREBEE */
 
         move.l  (sp)+,a2                        // Restore registers
@@ -265,7 +268,7 @@ _std_exc_vec:
         movem.l d0/a5,(sp)                      // save registers
         move.w  8(sp),d0                        // fetch vector
         and.l   #0x3fc,d0                       // mask out vector number
-//#define DBG_EXC
+// #define DBG_EXC
 #ifdef DBG_EXC
         // printout vector number of exception
 
@@ -326,8 +329,9 @@ access:
         move.l  4(a6),-(sp)                     // push format_status
         move.l  8(a6),-(sp)                     // pc at exception
         move.l  MCF_MMU_MMUAR,-(sp)             // MMU fault address
-        move.l  MCF_MMU_MMUSR,-(sp)             // MMU status regisrter
-        move.w  #0x2300,sr                      // can lower interrupt mask now that MMU status is safe
+        move.l  MCF_MMU_MMUSR,-(sp)             // MMU status register
+        // probably doesn't make sense since we still have a potential unmapped MMU page
+        // move.w  #0x2300,sr                      // can lower interrupt mask now that MMU status is safe
         jsr     _mmutr_miss                     // call C routine
         lea     4 * 4(sp),sp                    // adjust stack
 
@@ -341,7 +345,9 @@ access:
 bus_error:
         movem.l (sp),d0-d1/a0-a1                // restore registers
         unlk    a6
-        bra     std_exc_vec                     // FIXME: this seems to be bogous...
+        move.l  0x08,-(sp)
+        rts
+        // bra     std_exc_vec                     // FIXME: this seems to be bogous...
 
 zero_divide:
         move.w  #0x2700,sr                      // disable interrupt
@@ -581,7 +587,7 @@ _lowlevel_isr_handler:
         jsr     _isr_execute_handler            // call the C handler
         addq.l	#4,sp                           // adjust stack
         tst.b	d0                              // handled?
-        beq	lowlevel_forward                    // no, forward it to TOS
+        beq     lowlevel_forward                // no, forward it to TOS
 
         movem.l	(sp),d0-d1/a0-a1                // restore registers
         unlk	a6

sys/init_fpga.c

@@ -95,13 +95,15 @@ bool init_fpga(void)
     int i;
 
     xprintf("FPGA load config...\r\n");
+    xprintf("_FPGA_JTAG_LOADED = 0x%x\r\n", _FPGA_JTAG_LOADED);
+    xprintf("_FPGA_JTAG_VALID = 0x%x\r\n", _FPGA_JTAG_VALID);
     if (_FPGA_JTAG_LOADED == 1 && _FPGA_JTAG_VALID == VALID_JTAG)
     {
         xprintf("detected _FPGA_JTAG_LOADED flag. FPGA config skipped.\r\n");
 
         /* reset the flag so that next boot will load config again from flash */
-        _FPGA_JTAG_LOADED = 0;
-        _FPGA_JTAG_VALID = 0;
+        // _FPGA_JTAG_LOADED = 0;
+        // _FPGA_JTAG_VALID = 0;
 
         return true;
     }
@@ -180,6 +182,16 @@ bool init_fpga(void)
 
         xprintf("finished (took %f seconds).\r\n", time / 1000.0);
         config_gpio_for_jtag_config();
+
+        /*
+         * assure skipping fpga load on warm boot
+         */
+
+        _FPGA_JTAG_LOADED = 1;
+        _FPGA_JTAG_VALID = VALID_JTAG;
+
+        xprintf("SRAM now set to FPGA load skip\r\n");
+
         return true;
     }
     xprintf("FAILED!\r\n");

sys/interrupts.c

@@ -36,15 +36,10 @@
 #include "util.h"
 #include "dma.h"
 #include "pci.h"
+#include <stdarg.h>
 
-//#define IRQ_DEBUG
-#if defined(IRQ_DEBUG)
-#define dbg(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0)
-#else
-#define dbg(format, arg...) do { ; } while (0)
-#endif
-#define err(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0)
-
+// #define DEBUG
+#include "debug.h"
 
 #ifndef MAX_ISR_ENTRY
 #define MAX_ISR_ENTRY   (20)
@@ -61,6 +56,7 @@ struct isrentry
 
 static struct isrentry isrtab[MAX_ISR_ENTRY];      /* list of interrupt service routines */
 
+
 /*
  * clear the table of interrupt service handlers
  */
@@ -205,6 +201,140 @@ void isr_remove_handler(bool (*handler)(void *, void *))
     dbg("no such handler registered (handler=%p\r\n", handler);
 }
 
+#ifdef DEBUG
+static char *vector_to_str[] =
+{
+    "initial stack pointer",                    /* 0 */
+    "initial program counter",                  /* 1 */
+    "access error",                             /* 2 */
+    "address error",                            /* 3 */
+    "illegal instruction",                      /* 4 */
+    "divide by zero",                           /* 5 */
+    "reserved6",                                /* 6 */
+    "reserved7",                                /* 7 */
+    "privilege violation",                      /* 8 */
+    "trace",                                    /* 9 */
+    "unimplemented line-a opcode",              /* 10 */
+    "unimplemented line-f opcode",              /* 11 */
+    "non-PC breakpoint debug interrupt",        /* 12 */
+    "PC breakpoint debug interrupt",            /* 13 */
+    "format error",                             /* 14 */
+    "uninitialized interrupt",                  /* 15 */
+    "reserved16",
+    "reserved17",
+    "reserved18",
+    "reserved19",
+    "reserved20",
+    "reserved21",
+    "reserved22",
+    "reserved23",
+    "spurious interrupt",                       /* 24 */
+    "level 1 autovector",                       /* 25 */
+    "level 2 autovector",                       /* 26 */
+    "level 3 autovector",                       /* 27 */
+    "level 4 autovector",                       /* 28 */
+    "level 5 autovector",                       /* 29 */
+    "level 6 autovector",                       /* 30 */
+    "level 7 autovector",                       /* 31 */
+    "trap #0",                                  /* 32 */
+    "trap #1",                                  /* 33 */
+    "trap #2",                                  /* 34 */
+    "trap #3",                                  /* 35 */
+    "trap #4",                                  /* 36 */
+    "trap #5",                                  /* 37 */
+    "trap #6",                                  /* 38 */
+    "trap #7",                                  /* 39 */
+    "trap #8",                                  /* 40 */
+    "trap #9",                                  /* 41 */
+    "trap #10"                                  /* 42 */
+    "trap #11",                                 /* 43 */
+    "trap #12",                                 /* 44 */
+    "trap #13",                                 /* 45 */
+    "trap #14",                                 /* 46 */
+    "trap #15",                                 /* 47 */
+    "floating point branch on unordered condition", /* 48 */
+    "floting point inexact result",             /* 49 */
+    "floating point divide by zero",            /* 50 */
+    "floating point underflow",                 /* 51 */
+    "floating point operand error",             /* 52 */
+    "floating point overflow",                  /* 53 */
+    "floating point NaN",                       /* 54 */
+    "floating point denormalized number",       /* 55 */
+    "reserved56",                               /* 56 */
+    "reserved57",
+    "reserved58",
+    "reserved59",
+    "reserved60",
+    "unsupported instruction",                  /* 61 */
+    "reserved62",                               /* 62 */
+    "reserved63",                               /* 63 */
+    "", "",
+    "edge port 1",                              /* 1 */
+    "edge port 2",                              /* 2 */
+    "edge port 3",                              /* 3 */
+    "edge port 4",                              /* 4 */
+    "edge port 5",                              /* 5 */
+    "edge port 6",                              /* 6 */
+    "edge port 7",                              /* 7 */
+    "unused8",
+    "unused9",
+    "unused10",
+    "unused11",
+    "unused12",
+    "unused13",
+    "unused14",
+    "USB endpoint 0",                           /* 15 */
+    "USB endpoint 1",                           /* 16 */
+    "USB endpoint 2",                           /* 17 */
+    "USB endpoint 3",                           /* 18 */
+    "USB endpoint 4",                           /* 19 */
+    "USB endpoint 5",                           /* 20 */
+    "USB endpoint 6",                           /* 21 */
+    "USB general interrupt",                    /* 22 */
+    "USB core interrupt",                       /* 23 */
+    "USB OR interrupt",                         /* 24 */
+    "DSPI over/underflow",                      /* 25 */
+    "DSPI receive FIFO overflow",               /* 26 */
+    "DSPI receive FIFO drain",                  /* 27 */
+    "DSPI transmit FIFO underflow",             /* 28 */
+    "DSPI transfer complete",                   /* 29 */
+    "DSPI trasmit FIFO full",                   /* 30 */
+    "DSPI end of queue",                        /* 31 */
+    "PSC3",                                     /* 32 */
+    "PSC2",                                     /* 33 */
+    "PSC1",                                     /* 34 */
+    "PSC0",                                     /* 35 */
+    "Comm timer",                               /* 36 */
+    "SEC",                                      /* 37 */
+    "FEC1",                                     /* 38 */
+    "FEC0",                                     /* 39 */
+    "I2C",                                      /* 40 */
+    "PCI arbiter",                              /* 41 */
+    "comm bus PCI",                             /* 42 */
+    "XLB PCI",                                  /* 43 */
+    "not used44",
+    "not used45",
+    "not used46",
+    "XLB arbiter to CPU",                       /* 47 */
+    "multichannel DMA",                         /* 48 */
+    "FlexCAN 0 error",                          /* 49 */
+    "FlexCAN 0 bus off",                        /* 50 */
+    "FlexCAN 0 message buffer",                 /* 51 */
+    "not used52"
+    "slice timer 1",                            /* 53 */
+    "slice timer 0",                            /* 54 */
+    "FlexCAN 1 error",                          /* 55 */
+    "FlexCAN 1 bus off",                        /* 56 */
+    "FlexCAN 1 message buffer",                 /* 57 */
+    "not used58",
+    "GPT3",                                     /* 59 */
+    "GPT2",                                     /* 60 */
+    "GPT1",                                     /* 61 */
+    "GPT0",                                     /* 62 */
+    "not used63"
+};
+#endif /* DEBUG */
+
 /*
  * This routine searches the ISR table for an entry that matches
  * 'vector'. If one is found, then 'handler' is executed.
@@ -217,7 +347,7 @@ bool isr_execute_handler(int vector)
 {
     int index;
 
-    dbg("vector = %d\r\n", vector);
+    dbg("vector = %d (%s)\r\n", vector, vector_to_str[vector]);
 
     /*
      * locate an interrupt service routine handler.
@@ -235,6 +365,7 @@ bool isr_execute_handler(int vector)
     return true;
 }
 
+#if defined(MACHINE_FIREBEE)
 /*
  * PIC interrupt handler for Firebee
  *
@@ -247,24 +378,25 @@ bool pic_interrupt_handler(void *arg1, void *arg2)
 
     dbg("PIC interrupt\r\n");
 
-    rcv_byte = MCF_PSC3_PSCRB_8BIT;
+    rcv_byte = read_pic_byte();
     if (rcv_byte == 2)                  /* PIC requests RTC data */
     {
-        uint8_t *rtc_reg = (uint8_t *) 0xffff8961;
-        uint8_t *rtc_data = (uint8_t *) 0xffff8963;
+        volatile uint8_t *rtc_reg = (uint8_t *) 0xffff8961;
+        volatile uint8_t *rtc_data = (uint8_t *) 0xffff8963;
         int index = 0;
 
         err("PIC interrupt: requesting RTC data\r\n");
 
-        MCF_PSC3_PSCTB_8BIT = 0x82;     // header byte to PIC
+        write_pic_byte(0x82);     // header byte to PIC
         do
         {
-            *rtc_reg = 0;
-            MCF_PSC3_PSCTB_8BIT = *rtc_data;
-        } while (index++ < 64);
+            *rtc_reg = index;
+            write_pic_byte(*rtc_data);
+        } while (++index < 64);
     }
     return true;
 }
+#endif /* MACHINE_FIREBEE */
 
 bool xlbpci_interrupt_handler(void *arg1, void *arg2)
 {
@@ -299,6 +431,58 @@ bool pciarb_interrupt_handler(void *arg1, void *arg2)
 {
     dbg("PCI ARB interrupt\r\n");
 
+    MCF_PCIARB_PASR |= MCF_PCIARB_PASR_EXTMBK(0x1f) | MCF_PCIARB_PASR_ITLMBK;
+    return true;
+}
+
+bool xlbarb_interrupt_handler(void *arg1, void *arg2, ...)
+{
+    va_list args;
+    int i;
+    uint32_t status = MCF_XLB_XARB_SR;
+
+    dbg("arg1=0x%08x arg2=0x%08x\r\n", arg1, arg2);
+    va_start(args, arg2);
+    for (i = 0; i < 20; i++)
+    {
+        dbg("arg[%d]=0x%08x\r\n", i, va_arg(args, int));
+    }
+    va_end(args);
+
+    /*
+     * TODO: we should probably issue a bus error when this occors
+     */
+    err("XLB arbiter interrupt.\r\n");
+    err("XARB_ADRCAP=0x%08lx\r\n", MCF_XLB_XARB_ADRCAP);
+    err("XARB_SIGCAP=0x%08lx\r\n", MCF_XLB_XARB_SIGCAP);
+
+    MCF_XLB_XARB_ADRCAP = 0x0L;
+    MCF_XLB_XARB_SIGCAP = 0x0L;
+
+    if (status & MCF_XLB_XARB_SR_AT)
+        err("address tenure timeout\r\n");
+    if (status & MCF_XLB_XARB_SR_DT)
+        err("data tenure timeout\r\n");
+    if (status & MCF_XLB_XARB_SR_BA)
+        err("bus activity tenure timeout\r\n");
+    if (status & MCF_XLB_XARB_SR_TTM)
+        err("TBST/TSIZ mismatch\r\n");
+    if (status & MCF_XLB_XARB_SR_ECW)
+        err("external control word read/write\r\n");
+    if (status & MCF_XLB_XARB_SR_TTR)
+        err("TT reserved\r\n");
+    if (status & MCF_XLB_XARB_SR_TTA)
+        err("TT address only\r\n");
+    if (status & MCF_XLB_XARB_SR_MM)
+        err("multiple masters at priority 0\r\n");
+    if (status & MCF_XLB_XARB_SR_SEA)
+        err("slave error acknowledge\r\n");
+
+    /*
+     * acknowledge interrupt
+     */
+    MCF_XLB_XARB_SR = status;       /* rwc bits */
+
     return true;
 }
 
@@ -476,7 +660,7 @@ bool irq7_handler(void)
  */
 bool gpt0_interrupt_handler(void *arg0, void *arg1)
 {
-    dbg("handler called\n\r");
+    dbg("gpt0 handler called\n\r");
 
     MCF_GPT0_GMS &= ~1;     /* rearm trigger */
     NOP();
@@ -485,3 +669,26 @@ bool gpt0_interrupt_handler(void *arg0, void *arg1)
     return true;
 }
 #endif /* MACHINE_FIREBEE */
+
+
+uint32_t set_ipl(uint32_t ipl)
+{
+    uint32_t ret;
+
+    __asm__ __volatile__(
+        "		move.w	sr,%[ret]\r\n"			/* retrieve status register */
+        "		andi.l	#0x07,%[ipl]\n\t"		/* mask out ipl bits on new value */
+        "		lsl.l	#8,%[ipl]\n\t"			/* shift them to position */
+        "		move.l	%[ret],d0\n\t"			/* retrieve original value */
+        "		andi.l	#0x0000f8ff,d0\n\t"		/* clear ipl part */
+        "		or.l	%[ipl],d0\n\t"			/* or in new value */
+        "		move.w	d0,sr\n\t"				/* put it in place */
+        "		andi.l	#0x0700,%[ret]\r\n"		/* mask out ipl bits */
+        "		lsr.l	#8,%[ret]\r\n"			/* shift them to position */
+        : [ret] "=&d" (ret)		/* output */
+        : [ipl] "d" (ipl)		/* input */
+        : "cc"	/* clobber */
+    );
+
+    return ret;
+}

sys/mmu.c

@@ -3,15 +3,8 @@
 #include "exceptions.h"
 #include "pci.h"
 
-#if defined(MACHINE_FIREBEE)
-#include "firebee.h"
-#elif defined(MACHINE_M5484LITE)
-#include "m5484l.h"
-#elif defined(MACHINE_M54455)
-#include "m54455.h"
-#else
-#error "unknown machine!"
-#endif
+// #define DEBUG
+#include "debug.h"
 
 /*
  * mmu.c
@@ -36,26 +29,6 @@
  * Copyright 2013        M. Froeschle
  */
 
-#define ACR_BA(x)                   ((x) & 0xffff0000)
-#define ACR_ADMSK(x)                (((x) & 0xffff) << 16)
-#define ACR_E(x)                    (((x) & 1) << 15)
-
-#define ACR_S(x)                    (((x) & 3) << 13)
-#define ACR_S_USERMODE              0
-#define ACR_S_SUPERVISOR_MODE       1
-#define ACR_S_ALL                   2
-
-#define ACR_AMM(x)                  (((x) & 1) << 10)
-
-#define ACR_CM(x)                   (((x) & 3) << 5)
-#define ACR_CM_CACHEABLE_WT         0x0
-#define ACR_CM_CACHEABLE_CB         0x1
-#define ACR_CM_CACHE_INH_PRECISE    0x2
-#define ACR_CM_CACHE_INH_IMPRECISE  0x3
-
-#define ACR_SP(x)           (((x) & 1) << 3)
-#define ACR_W(x)            (((x) & 1) << 2)
-
 #include <stdint.h>
 #include "bas_printf.h"
 #include "bas_types.h"
@@ -74,14 +47,6 @@
 #error "unknown machine!"x
 #endif /* MACHINE_FIREBEE */
 
-//#define DBG_MMU
-#ifdef DBG_MMU
-#define dbg(format, arg...) do { xprintf("DEBUG (%s()): " format, __FUNCTION__, ##arg);} while(0)
-#else
-#define dbg(format, arg...) do {;} while (0)
-#endif /* DBG_MMU */
-#define err(format, arg...) do { xprintf("ERROR (%s()): " format, __FUNCTION__, ##arg); } while(0)
-
 /*
  * set ASID register
  * saves new value to rt_asid and returns former value
@@ -230,6 +195,9 @@ static struct virt_to_phys translation[] =
     { 0x00000000, 0x00e00000, 0x00000000 },     /* map first 14 MByte to first 14 Mb of SD ram */
     { 0x00e00000, 0x00100000, 0x00000000 },     /* map TOS to SDRAM */
     { 0x01000000, 0x04000000, 0x00000000 },     /* map rest of ram virt = phys */
+#if 0
+    { 0x04000000, 0x08000000, 0x7C000000 },     /* experimental mapping for PCI memory */
+#endif
 };
 #elif defined(MACHINE_M54455)
 /* FIXME: this is not determined yet! */
@@ -247,7 +215,7 @@ static struct virt_to_phys translation[] =
 
 static int num_translations = sizeof(translation) / sizeof(struct virt_to_phys);
 
-static inline int32_t lookup_phys(int32_t virt)
+static inline uint32_t lookup_phys(int32_t virt)
 {
     int i;
 
@@ -263,36 +231,27 @@ static inline int32_t lookup_phys(int32_t virt)
     return -1;
 }
 
-struct mmu_page_descriptor
-{
-    uint8_t cache_mode          : 2;
-    uint8_t supervisor_protect  : 1;
-    uint8_t read                : 1;
-    uint8_t write               : 1;
-    uint8_t execute             : 1;
-    uint8_t global              : 1;
-    uint8_t locked              : 1;
-};
 
 /*
  * page descriptors. Size depending on DEFAULT_PAGE_SIZE, either 1M (resulting in 512
  * bytes size) or 8k pages (64k descriptor array size)
  */
-static struct mmu_page_descriptor pages[SDRAM_SIZE / DEFAULT_PAGE_SIZE];
+#define NUM_PAGES    (SDRAM_SIZE / SIZE_DEFAULT)
+static struct mmu_page_descriptor_ram pages[NUM_PAGES];
 
 
-int mmu_map_instruction_page(int32_t virt, uint8_t asid)
+int mmu_map_instruction_page(uint32_t virt, uint8_t asid)
 {
-    const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1);       /* pagesize */
-    int page_index = (virt & size_mask) / DEFAULT_PAGE_SIZE;    /* index into page_descriptor array */
-    struct mmu_page_descriptor *page = &pages[page_index];      /* attributes of page to map */
+    const uint32_t size_mask = ~ (SIZE_DEFAULT - 1);                /* pagesize */
+    int page_index = (virt & size_mask) / SIZE_DEFAULT;             /* index into page_descriptor array */
+    struct mmu_page_descriptor_ram *page = &pages[page_index];      /* attributes of page to map */
     int ipl;
-    int32_t phys = lookup_phys(virt);                           /* virtual to physical translation of page */
+    uint32_t phys = lookup_phys(virt);                               /* virtual to physical translation of page */
 
-    if (phys == -1)
+    if (phys == (uint32_t) -1)
     {
         /* no valid mapping found, caller will issue a bus error in return */
-
+        dbg("no mapping found\r\n");
         return 0;
     }
 
@@ -315,7 +274,7 @@ int mmu_map_instruction_page(int32_t virt, uint8_t asid)
         MCF_MMU_MMUTR_V;                                            /* valid */
 
     MCF_MMU_MMUDR = (phys & size_mask) |                            /* physical address */
-        MCF_MMU_MMUDR_SZ(DEFAULT_PAGE_SIZE) |                       /* page size */
+        MCF_MMU_MMUDR_SZ(MMU_PAGE_SIZE_DEFAULT) |                   /* page size */
         MCF_MMU_MMUDR_CM(page->cache_mode) |                        /* cache mode */
         (page->supervisor_protect ? MCF_MMU_MMUDR_SP : 0) |         /* supervisor protect */
         (page->read ? MCF_MMU_MMUDR_R : 0) |                        /* read access enable */
@@ -336,23 +295,52 @@ int mmu_map_instruction_page(int32_t virt, uint8_t asid)
     return 1;
 }
 
-int mmu_map_data_page(int32_t virt, uint8_t asid)
+struct mmu_page_descriptor_ram pci_descriptor =
+{
+    .cache_mode = CACHE_NOCACHE_PRECISE,
+    .supervisor_protect = 0,
+    .read = 1,
+    .write = 1,
+    .execute = 1,
+    .global = 1,
+    .locked = 0
+};
+
+int mmu_map_data_page(uint32_t virt, uint8_t asid)
 {
     uint16_t ipl;
-    const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1);       /* pagesize */
-    int page_index = (virt & size_mask) / DEFAULT_PAGE_SIZE;    /* index into page_descriptor array */
-    struct mmu_page_descriptor *page = &pages[page_index];      /* attributes of page to map */
+    const uint32_t size_mask = ~ (SIZE_DEFAULT - 1);            /* pagesize */
+    int page_index = (virt & size_mask) / SIZE_DEFAULT;         /* index into page_descriptor array */
+    struct mmu_page_descriptor_ram *page;
+    uint32_t phys = 0L;
 
-    int32_t phys = lookup_phys(virt);                           /* virtual to physical translation of page */
+    if (page_index < sizeof(pages) / sizeof(struct mmu_page_descriptor_ram))
+    {
+        page = &pages[page_index];  /* attributes of page to map */
+        phys = lookup_phys(virt);                           /* virtual to physical translation of page */
+    }
 
-    if (phys == -1)
+    /*
+     * check if we are trying to access PCI space
+     */
+    else if (virt >= PCI_MEMORY_OFFSET && virt <= PCI_MEMORY_OFFSET + PCI_MEMORY_SIZE)
+    {
+        phys = virt;
+        page = &pci_descriptor;
+    }
+    else
+        return 0;
+
+
+
+    if (phys == (uint32_t) -1)
     {
         /* no valid mapping found, caller will issue a bus error in return */
-
+        dbg("no mapping found\r\n");
         return 0;
     }
 
-#ifdef DBG_MMU
+#ifdef DEBUG
     register int sp asm("sp");
     dbg("page_descriptor: 0x%02x, ssp = 0x%08x\r\n", * (uint8_t *) page, sp);
 #endif /* DBG_MMU */
@@ -369,7 +357,7 @@ int mmu_map_data_page(int32_t virt, uint8_t asid)
         MCF_MMU_MMUTR_V;                                            /* valid */
 
     MCF_MMU_MMUDR = (phys & size_mask) |                            /* physical address */
-        MCF_MMU_MMUDR_SZ(DEFAULT_PAGE_SIZE) |                       /* page size */
+        MCF_MMU_MMUDR_SZ(MMU_PAGE_SIZE_DEFAULT) |                   /* page size */
         MCF_MMU_MMUDR_CM(page->cache_mode) |                        /* cache mode */
         (page->supervisor_protect ? MCF_MMU_MMUDR_SP : 0) |         /* supervisor protect */
         (page->read ? MCF_MMU_MMUDR_R : 0) |                        /* read access enable */
@@ -381,6 +369,7 @@ int mmu_map_data_page(int32_t virt, uint8_t asid)
         MCF_MMU_MMUOR_UAA;                  /* update allocation address field */
 
     set_ipl(ipl);
+
     dbg("mapped virt=0x%08x to phys=0x%08x\r\n", virt & size_mask, phys & size_mask);
 
     dbg("DTLB: MCF_MMU_MMUOR = %08x\r\n", MCF_MMU_MMUOR);
@@ -398,7 +387,7 @@ int mmu_map_data_page(int32_t virt, uint8_t asid)
  * per instruction as a minimum, more for performance. Thus locked pages (that can't be touched by the
  * LRU algorithm) should be used sparsingly.
  */
-int mmu_map_page(int32_t virt, int32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor *flags)
+uint32_t mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor_ram *flags)
 {
     int size_mask;
     int ipl;
@@ -432,17 +421,18 @@ int mmu_map_page(int32_t virt, int32_t phys, enum mmu_page_size sz, uint8_t page
 
     ipl = set_ipl(7);       /* do not disturb */
 
-    MCF_MMU_MMUTR = ((int) virt & size_mask) |                      /* virtual address */
+    MCF_MMU_MMUTR = (virt & size_mask) |                            /* virtual address */
         MCF_MMU_MMUTR_ID(page_id) |                                 /* address space id (ASID) */
         (flags->global ? MCF_MMU_MMUTR_SG : 0) |                    /* shared global */
         MCF_MMU_MMUTR_V;                                            /* valid */
 
-    MCF_MMU_MMUDR = ((int) phys & size_mask) |                      /* physical address */
+    MCF_MMU_MMUDR = (phys & size_mask) |                            /* physical address */
         MCF_MMU_MMUDR_SZ(sz) |                                      /* page size */
         MCF_MMU_MMUDR_CM(flags->cache_mode) |
         (flags->read ? MCF_MMU_MMUDR_R : 0) |                       /* read access enable */
         (flags->write ? MCF_MMU_MMUDR_W : 0) |                      /* write access enable */
         (flags->execute ? MCF_MMU_MMUDR_X : 0) |                    /* execute access enable */
+        (flags->supervisor_protect ? MCF_MMU_MMUDR_SP : 0) |        /* supervisor protect */
         (flags->locked ? MCF_MMU_MMUDR_LK : 0);
 
     MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |     /* access TLB, data */
@@ -455,7 +445,7 @@ int mmu_map_page(int32_t virt, int32_t phys, enum mmu_page_size sz, uint8_t page
 
     set_ipl(ipl);
 
-    dbg("mapped virt=0x%08x to phys=0x%08x\r\n", virt, phys);
+    dbg("mapped virt=0x%08x to phys=0x%08x size mask 0x%lx\r\n", virt, phys, size_mask);
 
     return 1;
 }
@@ -464,7 +454,7 @@ void mmu_init(void)
 {
     extern uint8_t _MMUBAR[];
     uint32_t MMUBAR = (uint32_t) &_MMUBAR[0];
-    struct mmu_page_descriptor flags;
+    struct mmu_page_descriptor_ram flags;
     int i;
 
     /*
@@ -476,26 +466,24 @@ void mmu_init(void)
     /*
      * prelaminary initialization of page descriptor 0 (root) table
      */
-    for (i = 0; i < sizeof(pages) / sizeof(struct mmu_page_descriptor); i++)
+    for (i = 0; i < NUM_PAGES; i++)
     {
-        uint32_t addr = i * DEFAULT_PAGE_SIZE;
+        uint32_t addr = i * SIZE_DEFAULT;
 
 #if defined(MACHINE_FIREBEE)
         if (addr >= 0x00f00000UL && addr < 0x00ffffffUL)        /* Falcon I/O area on the Firebee */
         {
             pages[i].cache_mode = CACHE_NOCACHE_PRECISE;
-            pages[i].execute = 0;
+            pages[i].supervisor_protect = 1;
             pages[i].read = 1;
             pages[i].write = 1;
             pages[i].execute = 0;
             pages[i].global = 1;
-            pages[i].supervisor_protect = 1;
         }
         else if (addr >= 0x0UL && addr < 0x00e00000UL)          /* ST-RAM, potential video memory */
         {
             pages[i].cache_mode = CACHE_WRITETHROUGH;
-            pages[i].execute = 1;
-            pages[i].supervisor_protect = 0;
+            pages[i].supervisor_protect = 0; // (addr == 0x0L ? 1 : 0);
             pages[i].read = 1;
             pages[i].write = 1;
             pages[i].execute = 1;
@@ -504,24 +492,31 @@ void mmu_init(void)
         else if (addr >= 0x00e00000UL && addr < 0x00f00000UL)   /* EmuTOS */
         {
             pages[i].cache_mode = CACHE_COPYBACK;
-            pages[i].execute = 1;
-            pages[i].supervisor_protect = 1;
+            pages[i].supervisor_protect = 0;
             pages[i].read = 1;
             pages[i].write = 0;
             pages[i].execute = 1;
             pages[i].global = 1;
         }
+        else if (addr >= 0x00000000 && addr <= 0x00010000)      /* first Megabyte of ST RAM */
+        {
+            pages[i].cache_mode = CACHE_COPYBACK;
+            pages[i].supervisor_protect = 0;
+            pages[i].read = 1;
+            pages[i].write = 1;
+            pages[i].execute = 1;
+            pages[i].global = 1;
+        }
         else
         {
             pages[i].cache_mode = CACHE_COPYBACK;
-            pages[i].execute = 1;
+            pages[i].supervisor_protect = 0;
             pages[i].read = 1;
             pages[i].write = 1;
-            pages[i].supervisor_protect = 0;
+            pages[i].execute = 1;
             pages[i].global = 1;
         }
         pages[i].locked = 0;                /* not locked */
-        pages[0].supervisor_protect = 0;    /* protect system vectors */
 
 #elif defined(MACHINE_M5484LITE)
         if (addr >= 0x60000000UL && addr < 0x70000000UL)        /* Compact Flash on the m5484lite */
@@ -562,7 +557,6 @@ void mmu_init(void)
             pages[i].global = 1;
         }
         pages[i].locked = 0;                /* not locked */
-        pages[0].supervisor_protect = 0;    /* protect system vectors */
 
 #elif defined(MACHINE_M54455)
         if (addr >= 0x60000000UL && addr < 0x70000000UL)        /* Compact Flash on the m5484lite */
@@ -605,29 +599,33 @@ void mmu_init(void)
             pages[i].global = 1;
         }
         pages[i].locked = 0;                /* not locked */
-        pages[0].supervisor_protect = 0;    /* protect system vectors */
 #else
 #error Unknown machine!
 #endif /* MACHINE_FIREBEE */
     }
 
-    set_asid(0);            /* do not use address extension (ASID provides virtual 48 bit addresses */
+    set_asid(0);                        /* do not use address extension (ASID provides virtual 48 bit addresses */
+
+    // pages[0].supervisor_protect = 1;    /* protect system vectors */
 
     /* set data access attributes in ACR0 and ACR1 */
 
     /* map PCI address space */
+    /* set SRAM and MBAR access */
     set_acr0(ACR_W(0) |                             /* read and write accesses permitted */
-            ACR_SP(1) |                             /* supervisor and user mode access permitted */
+            // ACR_SP(1) |                             /* supervisor only access permitted */
             ACR_CM(ACR_CM_CACHE_INH_PRECISE) |      /* cache inhibit, precise */
             ACR_AMM(0) |                            /* control region > 16 MB */
-            ACR_S(ACR_S_SUPERVISOR_MODE) |          /* match addresses in supervisor mode only */
+            ACR_S(ACR_S_SUPERVISOR_MODE) |          /* match addresses in supervisor and user mode */
             ACR_E(1) |                              /* enable ACR */
 #if defined(MACHINE_FIREBEE)
             ACR_ADMSK(0x7f) |                       /* cover 2GB area from 0x80000000 to 0xffffffff */
-            ACR_BA(0x80000000));                    /* (equals area from 3 to 4 GB */
+            // ACR_BA(PCI_MEMORY_OFFSET));             /* (equals area from 3 to 4 GB */
+            ACR_BA(0xe0000000));
 #elif defined(MACHINE_M5484LITE)
             ACR_ADMSK(0x7f) |                       /* cover 2 GB area from 0x80000000 to 0xffffffff */
-            ACR_BA(PCI_MEMORY_OFFSET));
+            // ACR_BA(PCI_MEMORY_OFFSET));
+            ACR_BA(0xe0000000));
 #elif defined(MACHINE_M54455)
             ACR_ADMSK(0x7f) |
             ACR_BA(0x80000000));                    /* FIXME: not determined yet */
@@ -671,30 +669,18 @@ void mmu_init(void)
             ACR_ADMSK(0x7) |
             ACR_BA(0xe0000000));
 
-    /* disable ACR1 - 3, essentially disabling all of the above */
 
+    /* disable ACR3 */
     set_acr3(0x0);
 
     set_mmubar(MMUBAR + 1);     /* set and enable MMUBAR */
 
-    /* create locked TLB entries */
-
-    flags.cache_mode = CACHE_COPYBACK;
-    flags.supervisor_protect = 0;
-    flags.read = 1;
-    flags.write = 1;
-    flags.execute = 1;
-    flags.locked = true;
-
-    /* 0x00000000 - 0x00100000 (first MB of physical memory) locked virt = phys */
-    mmu_map_page(0x0, 0x0, MMU_PAGE_SIZE_1M, 0, &flags);
-
     /*
      * Make the TOS (in SDRAM) read-only
      * This maps virtual 0x00e0'0000 - 0x00ef'ffff to the same virtual address
      */
     flags.cache_mode = CACHE_COPYBACK;
-    flags.supervisor_protect = 0;
+    flags.supervisor_protect = 0;  // needs to stay like this or cf_flasher will choke */
     flags.read = 1;
     flags.write = 0;
     flags.execute = 1;
@@ -724,6 +710,10 @@ void mmu_init(void)
     flags.execute = 0;
     flags.locked = 1;
     mmu_map_page(0x6a000000, 0x6a000000, MMU_PAGE_SIZE_1M, 0, &flags);
+#elif defined(MACHINE_M54455)
+#warning MMU specs for M54455 not yet determined
+#else
+#error Unknown machine
 #endif /* MACHINE_FIREBEE */
 
     /*
@@ -731,7 +721,7 @@ void mmu_init(void)
      * virtual address. This is also used (completely) when BaS is in RAM
      */
     flags.cache_mode = CACHE_COPYBACK;
-    flags.supervisor_protect = 1;
+    flags.supervisor_protect = 0;
     flags.read = 1;
     flags.write = 1;
     flags.execute = 1;
@@ -743,7 +733,7 @@ void mmu_init(void)
      * virtual address. Used uncached for drivers.
      */
     flags.cache_mode = CACHE_NOCACHE_PRECISE;
-    flags.supervisor_protect = 1;
+    flags.supervisor_protect = 0;
     flags.read = 1;
     flags.write = 1;
     flags.execute = 0;
@@ -774,22 +764,24 @@ uint32_t mmutr_miss(uint32_t mmu_sr, uint32_t fault_address, uint32_t pc, uint32
 
             if (!mmu_map_instruction_page(pc, 0))
             {
-                dbg("bus error\r\n");
+                dbg("ITLB miss bus error\r\n");
                 return 1;   /* bus error */
             }
 
+#ifdef _NOT_USED_
             /* due to prefetch, it makes sense to map the next adjacent page also for ITLBs */
-            if (pc + DEFAULT_PAGE_SIZE < TARGET_ADDRESS)
+            if (pc + SIZE_DEFAULT < TARGET_ADDRESS)
             {
                 /*
                  * only do this if the next page is still valid RAM
                  */
-                if (!mmu_map_instruction_page(pc + DEFAULT_PAGE_SIZE, 0))
+                if (!mmu_map_instruction_page(pc + MMU_DEFAULT_PAGE_SIZE, 0))
                 {
-                    dbg("bus error\r\n");
+                    dbg("ITLB next page bus error\r\n");
                     return 1;   /* bus error */
                 }
             }
+#endif /* _NOT_USED_ */
             break;
 
         case 0x08020000:    /* TLB miss on data write */
@@ -803,14 +795,58 @@ uint32_t mmutr_miss(uint32_t mmu_sr, uint32_t fault_address, uint32_t pc, uint32
 
             if (!mmu_map_data_page(fault_address, 0))
             {
-                dbg("bus error\r\n");
+                dbg("DTLB miss bus error\r\n");
                 return 1;   /* bus error */
             }
             break;
 
+        case 0x0c010000:
+        case 0x08010000:
+            dbg("privilege violation accessing 0x%08x\r\n"
+                "FS = 0x%08x\r\n"
+                "MMUSR = 0x%08x\r\n"
+                "PC = 0x%08x\r\n",
+                fault_address, format_status, mmu_sr, pc);
+            dbg("fault = 0x%08x\r\n", fault);
+#ifdef _DOES_NOT_WORK_
+            /*
+             * check if its one of our "special cases" and map a user page on top of it if user
+             * mode access should be allowed
+             */
+            if (fault_address >= 1024 && fault_address < 0x00100000) /* ST-RAM */
+            {
+                struct mmu_page_descriptor flags =
+                {
+                    .cache_mode = CACHE_COPYBACK,
+                    .supervisor_protect = 0,
+                    .read = 1,
+                    .write = 1,
+                    .execute = 1,
+                    .global = 1,
+                    .locked = 0
+                };
+
+                uint32_t virt = fault_address & ~(SIZE_1K - 1);
+                uint32_t phys = (fault_address & (~(SIZE_1K - 1))) + 0x60000000;
+                dbg("mapping helper page virt=0x%08x to phys=0x%08x\r\n", virt, phys);
+                if (!mmu_map_page(virt, phys, MMU_PAGE_SIZE_1K, 0, &flags))
+                {
+                    dbg("privilege violation (bus error)\r\n");
+                    return 1;
+                }
+            }
+#endif
+            return 1;
+            break;
+
         /* else issue a bus error */
         default:
-            dbg("bus error\r\n");
+            dbg("bus error accessing 0x%08x\r\n"
+                "FS = 0x%08x\r\n"
+                "MMUSR = 0x%08x\r\n"
+                "PC = 0x%08x\r\n",
+                fault_address, format_status, mmu_sr, pc);
+            dbg("fault = 0x%08x\r\n", fault);
             return 1;       /* signal bus error to caller */
     }
 #ifdef DBG_MMU
@@ -846,14 +882,14 @@ uint32_t mmutr_miss(uint32_t mmu_sr, uint32_t fault_address, uint32_t pc, uint32
  *
  * return: 0 if failed (page not in translation table), 1 otherwise
  */
-int32_t mmu_map_data_page_locked(uint32_t virt, uint32_t size, int asid)
+uint32_t mmu_map_data_page_locked(uint32_t virt, uint32_t size, int asid)
 {
-    const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1);       /* pagesize */
-    int page_index = (virt & size_mask) / DEFAULT_PAGE_SIZE;    /* index into page_descriptor array */
-    struct mmu_page_descriptor *page = &pages[page_index];          /* attributes of page to map */
+    const uint32_t size_mask = ~ (SIZE_DEFAULT - 1);       /* pagesize */
+    int page_index = (virt & size_mask) / SIZE_DEFAULT;    /* index into page_descriptor array */
+    struct mmu_page_descriptor_ram *page = &pages[page_index];          /* attributes of page to map */
     int i = 0;
 
-    while (page_index * DEFAULT_PAGE_SIZE < virt + size)
+    while (page_index * SIZE_DEFAULT < virt + size)
     {
         if (page->locked)
         {
@@ -865,7 +901,7 @@ int32_t mmu_map_data_page_locked(uint32_t virt, uint32_t size, int asid)
             mmu_map_data_page(virt, 0);
             i++;
         }
-        virt += DEFAULT_PAGE_SIZE;
+        virt += SIZE_DEFAULT;
     }
 
     dbg("%d pages locked\r\n", i);
@@ -878,18 +914,18 @@ int32_t mmu_map_data_page_locked(uint32_t virt, uint32_t size, int asid)
  *
  * return: 0 if failed (page not found), 1 otherwise
  */
-int32_t mmu_unlock_data_page(uint32_t address, uint32_t size, int asid)
+uint32_t mmu_unlock_data_page(uint32_t address, uint32_t size, int asid)
 {
     int curr_asid;
-    const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1);
-    int page_index = (address & size_mask) / DEFAULT_PAGE_SIZE;     /* index into page descriptor array */
-    struct mmu_page_descriptor *page = &pages[page_index];
+    const uint32_t size_mask = ~ (SIZE_DEFAULT - 1);
+    int page_index = (address & size_mask) / SIZE_DEFAULT;     /* index into page descriptor array */
+    struct mmu_page_descriptor_ram *page = &pages[page_index];
 
     curr_asid = set_asid(asid);         /* set asid to the one to search for */
 
     /* TODO: check for pages[] array bounds */
 
-    while (page_index * DEFAULT_PAGE_SIZE < address + size)
+    while (page_index * SIZE_DEFAULT < address + size)
     {
         MCF_MMU_MMUAR = address + page->supervisor_protect;
         MCF_MMU_MMUOR = MCF_MMU_MMUOR_STLB |        /* search TLB */
@@ -897,7 +933,7 @@ int32_t mmu_unlock_data_page(uint32_t address, uint32_t size, int asid)
                 MCF_MMU_MMUOR_RW;
         if (MCF_MMU_MMUSR & MCF_MMU_MMUSR_HIT)      /* found */
         {
-#ifdef DBG_MMU
+#ifdef DEBUG
             uint32_t tlb_aa = MCF_MMU_MMUOR >> 16;  /* MMU internal allocation address for TLB */
 #endif /* DBG_MMU */
 
@@ -918,7 +954,7 @@ int32_t mmu_unlock_data_page(uint32_t address, uint32_t size, int asid)
     return 1;   /* success */
 }
 
-int32_t mmu_report_locked_pages(uint32_t *num_itlb, uint32_t *num_dtlb)
+uint32_t mmu_report_locked_pages(uint32_t *num_itlb, uint32_t *num_dtlb)
 {
     int i;
     int li = 0;
@@ -967,5 +1003,6 @@ int32_t mmu_report_locked_pages(uint32_t *num_itlb, uint32_t *num_dtlb)
 
 uint32_t mmu_report_pagesize(void)
 {
-    return DEFAULT_PAGE_SIZE;
+    return SIZE_DEFAULT;
 }
+

sys/startcf.S

@@ -4,73 +4,74 @@
  * so it will be placed at the very beginning of the ROM.
  */
 
-		.equ	MCF_MMU_MMUCR, __MMUBAR + 0
+        .equ	MCF_MMU_MMUCR, __MMUBAR + 0
 
-		.globl	_rom_header
-		.globl	_rom_entry
+        .globl	_rom_header
+        .globl	_rom_entry
 
-		.extern	_initialize_hardware
-		.extern	_rt_mbar
+        .extern	_initialize_hardware
+        .extern	_rt_mbar
 
 /* ROM header */
 _rom_header:
-		/* The first long is supposed to be the initial SP.
-		 * We replace it by bra.s to allow running the ROM from the first byte.
-		 * Then we add a fake jmp instruction for pretty disassembly.
-		 */
-		bra.s	_rom_entry		// Short jump to the real entry point
-		.short	0x4ef9			// Fake jmp instruction
-		/* The second long is the initial PC */
-		.long	_rom_entry		// Real entry point
+        /* The first long is supposed to be the initial SP.
+         * We replace it by bra.s to allow running the ROM from the first byte.
+         * Then we add a fake jmp instruction for pretty disassembly.
+         */
+        bra.s	_rom_entry		// Short jump to the real entry point
+        .short	0x4ef9			// Fake jmp instruction
+        /* The second long is the initial PC */
+        .long	_rom_entry		// Real entry point
 
 /* ROM entry point */
 _rom_entry:
-		/* disable interrupts */
-		move.w #0x2700,sr
+        /* disable interrupts */
+        move.w #0x2700,sr
 
 #if !defined(MACHINE_M54455)			// MCF54455 does not have the MBAR register
-		/* Initialize MBAR */
-		move.l	#__MBAR,d0
-		movec	d0,MBAR
-		move.l	d0,_rt_mbar
+        /* Initialize MBAR */
+        move.l	#__MBAR,d0
+        movec	d0,MBAR
+        move.l	d0,_rt_mbar
 #endif
 
-		/* mmu off */
-		move.l	#__MMUBAR+1,d0
-		movec	d0,MMUBAR
+        /* mmu off */
+        move.l	#__MMUBAR+1,d0
+        movec	d0,MMUBAR
 
-		clr.l	d0
-		move.l	d0,MCF_MMU_MMUCR
+        clr.l	d0
+        move.l	d0,MCF_MMU_MMUCR
+        nop
 
 #if !defined(MACHINE_M54455)			// MCF54455 does not have RAMBAR0 and RAMBAR1 registers */
 
-		/* Initialize RAMBARs: locate SRAM and validate it */
-		move.l	#__RAMBAR0 + 0x7,d0 	// supervisor only
-		movec	d0,RAMBAR0
-		move.l	#__RAMBAR1 + 0x1,d0
-		movec	d0,RAMBAR1
+        /* Initialize RAMBARs: locate SRAM and validate it */
+        move.l	#__RAMBAR0 + 0x7,d0 	// supervisor only
+        movec	d0,RAMBAR0
+        move.l	#__RAMBAR1 + 0x1,d0
+        movec	d0,RAMBAR1
 #else
-		move.l	#__RAMBAR0 + 0x7,d0
-		movec	d0,RAMBAR
+        move.l	#__RAMBAR0 + 0x7,d0
+        movec	d0,RAMBAR
 #endif
 
-		/* set stack pointer to end of SRAM */
-		lea 	__SUP_SP,a7
-		move.l	#0,(sp)
+        /* set stack pointer to end of SRAM */
+        lea 	__SUP_SP,a7
+        move.l	#0,(sp)
 
-		/*
-		 * Initialize the processor caches.
-		 * The instruction cache is fully enabled.
-		 * The data cache is enabled, but cache-inhibited by default.
-		 * Later, the MMU will fully activate the data cache for specific areas.
-		 * It is important to enable both caches now, otherwise cpushl would hang.
-		 */
+        /*
+         * Initialize the processor caches.
+         * The instruction cache is fully enabled.
+         * The data cache is enabled, but cache-inhibited by default.
+         * Later, the MMU will fully activate the data cache for specific areas.
+         * It is important to enable both caches now, otherwise cpushl would hang.
+         */
 
-		move.l	#0xa50c8120,d0
-		movec	d0,cacr
-		andi.l	#0xfefbfeff,d0			// Clear invalidate bits
-		move.l	d0,_rt_cacr
+        move.l	#0xa50c8120,d0
+        movec	d0,cacr
+        andi.l	#0xfefbfeff,d0			// Clear invalidate bits
+        move.l	d0,_rt_cacr
 
-		/* initialize any hardware specific issues */
-		bra    _initialize_hardware
+        /* initialize any hardware specific issues */
+        bra    _initialize_hardware
 

sys/sysinit.c

@@ -53,6 +53,9 @@
 #include "usb.h"
 #include "video.h"
 
+// #define DEBUG
+#include "debug.h"
+
 #define UNUSED(x) (void)(x)             /* Unused variable         */
 
 bool fpga_configured = false;           /* for FPGA JTAG configuration */
@@ -265,9 +268,6 @@ static void init_serial(void)
     MCF_PSC3_PSCCR = 0x05;
 #endif /* MACHINE_FIREBEE */
 
-    MCF_INTC_ICR32 = MCF_INTC_ICR_IL(7) |
-                     MCF_INTC_ICR_IL(4);      /* PSC3 interrupt vector. Do we need it? */
-
     xprintf("\r\nserial interfaces initialization: finished\r\n");
 }
 
@@ -428,13 +428,19 @@ static void init_fbcs()
     MCF_FBCS2_CSMR = (MCF_FBCS_CSMR_BAM_128M            /* F000'0000-F7FF'FFFF */
               | MCF_FBCS_CSMR_V);
 
-    MCF_FBCS3_CSAR = MCF_FBCS_CSAR_BA(0xF8000000);      /* Firebee new I/O address range */
+    MCF_FBCS3_CSAR = MCF_FBCS_CSAR_BA(0xF8000000);      /* Firebee SRAM */
     MCF_FBCS3_CSCR = MCF_FBCS_CSCR_PS_16                /* 16 bit port */
         | MCF_FBCS_CSCR_WS(32)                          /* 0 wait states */
         | MCF_FBCS_CSCR_AA;                             /* auto /TA acknowledge */
     MCF_FBCS3_CSMR = (MCF_FBCS_CSMR_BAM_64M             /* F800'0000-FBFF'FFFF */
               | MCF_FBCS_CSMR_V);
 
+    /*
+     * Note: burst read/write settings of the following FBCS are purely "cosmetical".
+     * The Coldfire FlexBus only "bursts" on a smaller port size than 32 bit up to 32 bit,
+     * i.e. it can burst on an 8 bit port up to 4 burst cycles or two on a 16 bit port.
+     * Enabling burst on a 32 bit port has no effect (unfortunately).
+     */
     MCF_FBCS4_CSAR = MCF_FBCS_CSAR_BA(0x40000000);      /* video ram area, FB_CS3 not used, decoded on FPGA */
     MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32                /* 32 bit port */
         | MCF_FBCS_CSCR_WS(32)                          /* 0 wait states */
@@ -459,6 +465,9 @@ static void init_fbcs()
     MCF_FBCS3_CSMR = 0;
     MCF_FBCS4_CSMR = 0;
 
+    /*
+     * the FireEngine needs AA for its CPLD accessed registers
+     */
     MCF_FBCS5_CSAR = MCF_FBCS_CSAR_BA(0x60000000);
     MCF_FBCS5_CSCR = MCF_FBCS_CSCR_PS_16 |              /* CPLD access 16 bit wide */
                      MCF_FBCS_CSCR_WS(32) |             /* 32 wait states */
@@ -579,25 +588,26 @@ void init_usb(void)
     int usb_found = 0;
     int index = 0;
 
-    xprintf("USB controller initialization:\r\n");
+    inf("USB controller initialization:\r\n");
 
     do
     {
-        handle = pci_find_classcode(PCI_CLASS_SERIAL_USB | (1 << 25) | (1 << 26), index++);
+        handle = pci_find_classcode(PCI_CLASS_SERIAL_USB | PCI_FIND_BASE_CLASS | PCI_FIND_SUB_CLASS, index++);
+        dbg("handle 0x%02x\r\n", handle);
         if (handle > 0)
         {
             long id;
-            long class;
+            long pci_class;
 
             xprintf("serial USB found at bus=0x%x, dev=0x%x, fnc=0x%x (0x%x)\r\n",
                     PCI_BUS_FROM_HANDLE(handle),
                     PCI_DEVICE_FROM_HANDLE(handle),
                     PCI_FUNCTION_FROM_HANDLE(handle),
                     handle);
-            id = pci_read_config_longword(handle, PCIIDR);
-            class = pci_read_config_longword(handle, PCIREV);
+            id = swpl(pci_read_config_longword(handle, PCIIDR));
+            pci_class = swpl(pci_read_config_longword(handle, PCIREV));
 
-            if (PCI_SUBCLASS(class) == PCI_CLASS_SERIAL_USB_EHCI)
+            if (pci_class >> 8 == PCI_CLASS_SERIAL_USB_EHCI)
             {
                 board = ehci_usb_pci_table;
                 while (board->vendor)
@@ -612,7 +622,7 @@ void init_usb(void)
                     board++;
                 }
             }
-            if (PCI_SUBCLASS(class) == PCI_CLASS_SERIAL_USB_OHCI)
+            if (pci_class >> 8 == PCI_CLASS_SERIAL_USB_OHCI)
             {
                 board = ohci_usb_pci_table;
                 while (board->vendor)
@@ -1057,18 +1067,18 @@ void initialize_hardware(void)
     init_ddram();
 
 #if defined(MACHINE_M5484LITE)
-    xprintf("Fire Engine Control register:          %02x\r\n", * (uint8_t *) 0x61000000);
-    xprintf("Fire Engine interrupt register:        %02x\r\n", * (uint8_t *) 0x62000000);
-    xprintf("Fire Engine interrupt mask register:   %02x\r\n", * (uint8_t *) 0x63000000);
-    xprintf("Fire Engine power management register: %02x\r\n", * (uint8_t *) 0x64000000);
-    xprintf("Fire Engine EEPROM SPI register:       %02x\r\n", * (uint8_t *) 0x65000000);
-    xprintf("Fire Engine Flash register:            %02x\r\n", * (uint8_t *) 0x66000000);
-    xprintf("Fire Engine CPLD revision register:    %02x\r\n", * (uint8_t *) 0x67000000);
-    xprintf("Fire Engine Hardware revision register:%02x\r\n", * (uint8_t *) 0x68000000);
+    dbg("Fire Engine Control register:          %02x\r\n", * (uint8_t *) 0x61000000);
+    dbg("Fire Engine interrupt register:        %02x\r\n", * (uint8_t *) 0x62000000);
+    dbg("Fire Engine interrupt mask register:   %02x\r\n", * (uint8_t *) 0x63000000);
+    dbg("Fire Engine power management register: %02x\r\n", * (uint8_t *) 0x64000000);
+    dbg("Fire Engine EEPROM SPI register:       %02x\r\n", * (uint8_t *) 0x65000000);
+    dbg("Fire Engine Flash register:            %02x\r\n", * (uint8_t *) 0x66000000);
+    dbg("Fire Engine CPLD revision register:    %02x\r\n", * (uint8_t *) 0x67000000);
+    dbg("Fire Engine Hardware revision register:%02x\r\n", * (uint8_t *) 0x68000000);
 
-    xprintf("write control register 0x%02x\r\n", 1 << 7);
+    dbg("write control register 0x%02x\r\n", 1 << 7);
     * (uint8_t *) 0x61000000 = 1 << 7;
-    xprintf("Fire Engine Control register:          %02x\r\n", * (uint8_t *) 0x61000000);
+    dbg("Fire Engine Control register:          %02x\r\n", * (uint8_t *) 0x61000000);
 #endif /* MACHINE_M5484LITE */
 
     /*

tos/Makefile

@@ -3,17 +3,35 @@
 .PHONY: bascook
 .PHONY: vmem_test
 .PHONY: pci_test
-tos: jtagwait bascook vmem_test pci_test
+.PHONY: pci_mem
+.PHONY: fpga_test
+tos: jtagwait bascook vmem_test pci_test pci_mem fpga_test
 
 jtagwait:
-	$(MAKE) -C $@
+	@$(MAKE) -s -C $@
 
 bascook:
-	$(MAKE) -C $@
+	@$(MAKE) -s -C $@
 
 vmem_test:
-	$(MAKE) -C $@
+	@$(MAKE) -s -C $@
 
 pci_test:
-	$(MAKE) -C $@
+	@$(MAKE) -s -C $@
+
+pci_mem:
+	@$(MAKE) -s -C $@
+
+fpga_test:
+	@$(MAKE) -s -C $@
+
+.PHONY: clean
+clean:
+	@(cd jtagwait; $(MAKE) -s clean)
+	@(cd bascook; $(MAKE) -s clean)
+	@(cd vmem_test; $(MAKE) -s clean)
+	@(cd pci_test; $(MAKE) -s clean)
+	@(cd pci_mem; $(MAKE) -s clean)
+	@(cd fpga_test; $(MAKE) -s clean)
+
 

tos/bascook/Makefile

@@ -23,7 +23,9 @@ TOPDIR= ../..
 
 BAS_INCLUDE=-I$(TOPDIR)/../BaS_gcc/include
 
-INCLUDE=-I$(TOPDIR)/../libcmini/include $(BAS_INCLUDE) -nostdlib
+LIBCMINI=$(TOPDIR)/../libcmini/libcmini
+
+INCLUDE=-I$(LIBCMINI)/include $(BAS_INCLUDE) -nostdlib
 LIBS=-lcmini -nostdlib -lgcc
 CC=$(PREFIX)/bin/gcc
 
@@ -65,21 +67,24 @@ all: $(TEST_APP)
 #
 define CC_TEMPLATE
 $(1)/objs/%.o:$(SRCDIR)/%.c
-	$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
+	@echo CC $$<
+	@$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
 
 $(1)/objs/%.o:$(SRCDIR)/%.S
-	$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
+	@echo CC $$<
+	@$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
 
 $(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
 $(1)/$(APP): $$($(1)_OBJS)
-	$(CC) $$(CFLAGS) -o $$@ $(TOPDIR)/../libcmini/m5475/startup.o $$($(1)_OBJS) -L$(TOPDIR)/../libcmini/m5475 $(LIBS)
-	$(STRIP) $$@
+	@echo CC $$<
+	@$(CC) $$(CFLAGS) -o $$@ $(LIBCMINI)/m5475/startup.o $$($(1)_OBJS) -L$(LIBCMINI)/m5475 $(LIBS)
+	@$(STRIP) $$@
 endef
 $(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
 
 $(DEPEND): $(ASRCS) $(CSRCS)
-	-rm -f $(DEPEND)
-	for d in $(TRGTDIRS);\
+	@-rm -f $(DEPEND)
+	@for d in $(TRGTDIRS);\
 		do $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e "s#^\(.*\).o:#$$d/objs/\1.o:#" >> $(DEPEND); \
     done
 
@@ -90,8 +95,7 @@ clean:
 
 .PHONY: printvars
 printvars:
-	@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
-
+	@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V)))) 
 ifneq (clean,$(MAKECMDGOALS))
 -include $(DEPEND)
 endif

tos/fpga_test/Makefile

@@ -0,0 +1,109 @@
+CROSS=Y
+
+CROSSBINDIR_IS_Y=m68k-atari-mint-
+CROSSBINDIR_IS_N=
+
+CROSSBINDIR=$(CROSSBINDIR_IS_$(CROSS))
+
+UNAME := $(shell uname)
+ifeq ($(CROSS), Y)
+ifeq ($(UNAME),Linux)
+PREFIX=m68k-atari-mint
+HATARI=hatari
+else
+PREFIX=m68k-atari-mint
+HATARI=/usr/local/bin/hatari
+endif
+else
+PREFIX=/usr
+endif
+
+DEPEND=depend
+TOPDIR = ../..
+
+LIBCMINI=$(TOPDIR)/../libcmini/libcmini
+
+INCLUDE=-I$(LIBCMINI)/include -nostdlib
+LIBS=-lcmini -nostdlib -lgcc
+CC=$(PREFIX)/bin/gcc
+
+CC=$(CROSSBINDIR)gcc
+STRIP=$(CROSSBINDIR)strip
+STACK=$(CROSSBINDIR)stack
+
+APP=fpga_test.prg
+TEST_APP=$(APP)
+
+CFLAGS=\
+	-O0\
+	-g\
+	-Wl,-Map,mapfile\
+	-Wl,--defsym -Wl,__MBAR=0xff000000\
+	-Wl,--defsym -Wl,__MMUBAR=0xff040000\
+	-Wl,--defsym -Wl,__FPGA_JTAG_LOADED=0xff101000\
+	-Wl,--defsym -Wl,__FPGA_JTAG_VALID=0xff101004\
+	-Wl,--defsym -Wl,__VRAM=0x60000000\
+	-Wall
+
+SRCDIR=sources
+INCDIR=include
+INCLUDE+=-I$(INCDIR)
+
+CSRCS=\
+	$(SRCDIR)/fpga_test.c \
+	$(SRCDIR)/bas_printf.c
+
+ASRCS=$(SRCDIR)/printf_helper.S
+
+COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS)))
+AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS)))
+OBJS=$(COBJS) $(AOBJS)
+
+TRGTDIRS=./m5475 ./m5475/mshort
+OBJDIRS=$(patsubst %,%/objs,$(TRGTDIRS))
+
+#
+# multilib flags. These must match m68k-atari-mint-gcc -print-multi-lib output
+#
+m5475/$(APP):CFLAGS += -mcpu=5475
+m5475/mshort/$(APP): CFLAGS += -mcpu=5475 -mshort
+
+all:$(patsubst %,%/$(APP),$(TRGTDIRS))
+#
+# generate pattern rules for multilib object files.
+#
+define CC_TEMPLATE
+$(1)/objs/%.o:$(SRCDIR)/%.c
+	@echo CC $$<
+	@$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
+
+$(1)/objs/%.o:$(SRCDIR)/%.S
+	@echo CC $$<
+	@$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
+
+$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
+$(1)/$(APP): $$($(1)_OBJS)
+	@echo CC $$@
+	@$(CC) $$(CFLAGS) -o $$@ $(LIBCMINI)/$(1)/startup.o $$($(1)_OBJS) -L$(LIBCMINI)/$(1) $(LIBS)
+	#$(STRIP) $$@
+endef
+$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
+
+$(DEPEND): $(ASRCS) $(CSRCS)
+	@-rm -f $(DEPEND)
+	@for d in $(TRGTDIRS);\
+		do $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e "s#^\(.*\).o:#$$d/objs/\1.o:#" >> $(DEPEND); \
+    done
+
+
+clean:
+	@rm -f $(patsubst %,%/objs/*.o,$(TRGTDIRS)) $(patsubst %,%/$(APP),$(TRGTDIRS))
+	@rm -f $(DEPEND) mapfile
+
+.PHONY: printvars
+printvars:
+	@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
+
+ifneq (clean,$(MAKECMDGOALS))
+-include $(DEPEND)
+endif

tos/fpga_test/include/MCF5475.h

@@ -0,0 +1,67 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_H__
+#define __MCF5475_H__
+
+#include <stdint.h>
+/***
+ * MCF5475 Derivative Memory map definitions from linker command files:
+ * __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
+ * linker symbols must be defined in the linker command file.
+ */
+
+typedef uint32_t __attribute__((__may_alias__)) uint32_t_a;	/* a type to avoid gcc's complaints about pointer aliasing */
+
+extern uint8_t _MBAR[];
+extern uint8_t _MMUBAR[];
+extern uint8_t _RAMBAR0[];
+extern uint8_t _RAMBAR0_SIZE[];
+extern uint8_t _RAMBAR1[];
+extern uint8_t _RAMBAR1_SIZE[];
+
+#define MBAR_ADDRESS    (uint32_t)_MBAR
+#define MMUBAR_ADDRESS  (uint32_t)_MMUBAR
+#define RAMBAR0_ADDRESS (uint32_t)_RAMBAR0
+#define RAMBAR0_SIZE    (uint32_t)_RAMBAR0_SIZE
+#define RAMBAR1_ADDRESS (uint32_t)_RAMBAR1
+#define RAMBAR1_SIZE    (uint32_t)_RAMBAR1_SIZE
+
+
+#include "MCF5475_SIU.h"
+#include "MCF5475_MMU.h"
+#include "MCF5475_SDRAMC.h"
+#include "MCF5475_XLB.h"
+#include "MCF5475_CLOCK.h"
+#include "MCF5475_FBCS.h"
+#include "MCF5475_INTC.h"
+#include "MCF5475_GPT.h"
+#include "MCF5475_SLT.h"
+#include "MCF5475_GPIO.h"
+#include "MCF5475_PAD.h"
+#include "MCF5475_PCI.h"
+#include "MCF5475_PCIARB.h"
+#include "MCF5475_EPORT.h"
+#include "MCF5475_CTM.h"
+#include "MCF5475_DMA.h"
+#include "MCF5475_PSC.h"
+#include "MCF5475_DSPI.h"
+#include "MCF5475_I2C.h"
+#include "MCF5475_FEC.h"
+#include "MCF5475_USB.h"
+#include "MCF5475_SRAM.h"
+#include "MCF5475_SEC.h"
+
+#endif /* __MCF5475_H__ */

tos/fpga_test/include/MCF5475_CLOCK.h

@@ -0,0 +1,47 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_CLOCK_H__
+#define __MCF5475_CLOCK_H__
+
+
+/*********************************************************************
+*
+* Clock Module (CLOCK)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CLOCK_SPCR                       (*(volatile uint32_t*)(&_MBAR[0x300]))
+
+
+/* Bit definitions and macros for MCF_CLOCK_SPCR */
+#define MCF_CLOCK_SPCR_MEMEN                 (0x1)
+#define MCF_CLOCK_SPCR_PCIEN                 (0x2)
+#define MCF_CLOCK_SPCR_FBEN                  (0x4)
+#define MCF_CLOCK_SPCR_CAN0EN                (0x8)
+#define MCF_CLOCK_SPCR_DMAEN                 (0x10)
+#define MCF_CLOCK_SPCR_FEC0EN                (0x20)
+#define MCF_CLOCK_SPCR_FEC1EN                (0x40)
+#define MCF_CLOCK_SPCR_USBEN                 (0x80)
+#define MCF_CLOCK_SPCR_PSCEN                 (0x200)
+#define MCF_CLOCK_SPCR_CAN1EN                (0x800)
+#define MCF_CLOCK_SPCR_CRYENA                (0x1000)
+#define MCF_CLOCK_SPCR_CRYENB                (0x2000)
+#define MCF_CLOCK_SPCR_COREN                 (0x4000)
+#define MCF_CLOCK_SPCR_PLLK                  (0x80000000)
+
+
+#endif /* __MCF5475_CLOCK_H__ */

tos/fpga_test/include/MCF5475_CTM.h

@@ -0,0 +1,76 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_CTM_H__
+#define __MCF5475_CTM_H__
+
+
+/*********************************************************************
+*
+* Comm Timer Module (CTM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CTM_CTCR0                        (*(volatile uint32_t*)(&_MBAR[0x7F00]))
+#define MCF_CTM_CTCR1                        (*(volatile uint32_t*)(&_MBAR[0x7F04]))
+#define MCF_CTM_CTCR2                        (*(volatile uint32_t*)(&_MBAR[0x7F08]))
+#define MCF_CTM_CTCR3                        (*(volatile uint32_t*)(&_MBAR[0x7F0C]))
+#define MCF_CTM_CTCR4                        (*(volatile uint32_t*)(&_MBAR[0x7F10]))
+#define MCF_CTM_CTCR5                        (*(volatile uint32_t*)(&_MBAR[0x7F14]))
+#define MCF_CTM_CTCR6                        (*(volatile uint32_t*)(&_MBAR[0x7F18]))
+#define MCF_CTM_CTCR7                        (*(volatile uint32_t*)(&_MBAR[0x7F1C]))
+#define MCF_CTM_CTCRF(x)                     (*(volatile uint32_t*)(&_MBAR[0x7F00 + ((x)*0x4)]))
+#define MCF_CTM_CTCRV(x)                     (*(volatile uint32_t*)(&_MBAR[0x7F10 + ((x-4)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_CTM_CTCRF */
+#define MCF_CTM_CTCRF_CRV(x)                 (((x)&0xFFFF)<<0)
+#define MCF_CTM_CTCRF_S(x)                   (((x)&0xF)<<0x10)
+#define MCF_CTM_CTCRF_S_CLK_1                (0)
+#define MCF_CTM_CTCRF_S_CLK_2                (0x10000)
+#define MCF_CTM_CTCRF_S_CLK_4                (0x20000)
+#define MCF_CTM_CTCRF_S_CLK_8                (0x30000)
+#define MCF_CTM_CTCRF_S_CLK_16               (0x40000)
+#define MCF_CTM_CTCRF_S_CLK_32               (0x50000)
+#define MCF_CTM_CTCRF_S_CLK_64               (0x60000)
+#define MCF_CTM_CTCRF_S_CLK_128              (0x70000)
+#define MCF_CTM_CTCRF_S_CLK_256              (0x80000)
+#define MCF_CTM_CTCRF_S_CLK_EXT              (0x90000)
+#define MCF_CTM_CTCRF_PCT(x)                 (((x)&0x7)<<0x14)
+#define MCF_CTM_CTCRF_PCT_100                (0)
+#define MCF_CTM_CTCRF_PCT_50                 (0x100000)
+#define MCF_CTM_CTCRF_PCT_25                 (0x200000)
+#define MCF_CTM_CTCRF_PCT_12p5               (0x300000)
+#define MCF_CTM_CTCRF_PCT_6p25               (0x400000)
+#define MCF_CTM_CTCRF_PCT_OFF                (0x500000)
+#define MCF_CTM_CTCRF_M                      (0x800000)
+#define MCF_CTM_CTCRF_IM                     (0x1000000)
+#define MCF_CTM_CTCRF_I                      (0x80000000)
+
+/* Bit definitions and macros for MCF_CTM_CTCRV */
+#define MCF_CTM_CTCRV_CRV(x)                 (((x)&0xFFFFFF)<<0)
+#define MCF_CTM_CTCRV_PCT(x)                 (((x)&0x7)<<0x18)
+#define MCF_CTM_CTCRV_PCT_100                (0)
+#define MCF_CTM_CTCRV_PCT_50                 (0x1000000)
+#define MCF_CTM_CTCRV_PCT_25                 (0x2000000)
+#define MCF_CTM_CTCRV_PCT_12p5               (0x3000000)
+#define MCF_CTM_CTCRV_PCT_6p25               (0x4000000)
+#define MCF_CTM_CTCRV_PCT_OFF                (0x5000000)
+#define MCF_CTM_CTCRV_M                      (0x8000000)
+#define MCF_CTM_CTCRV_S                      (0x10000000)
+
+
+#endif /* __MCF5475_CTM_H__ */

tos/fpga_test/include/MCF5475_DMA.h

@@ -0,0 +1,234 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_DMA_H__
+#define __MCF5475_DMA_H__
+
+
+/*********************************************************************
+*
+* Multichannel DMA (DMA)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_DMA_TASKBAR                      (*(volatile uint32_t*)(&_MBAR[0x8000]))
+#define MCF_DMA_CP                           (*(volatile uint32_t*)(&_MBAR[0x8004]))
+#define MCF_DMA_EP                           (*(volatile uint32_t*)(&_MBAR[0x8008]))
+#define MCF_DMA_VP                           (*(volatile uint32_t*)(&_MBAR[0x800C]))
+#define MCF_DMA_PTD                          (*(volatile uint32_t*)(&_MBAR[0x8010]))
+#define MCF_DMA_DIPR                         (*(volatile uint32_t*)(&_MBAR[0x8014]))
+#define MCF_DMA_DIMR                         (*(volatile uint32_t*)(&_MBAR[0x8018]))
+#define MCF_DMA_TCR0                         (*(volatile uint16_t*)(&_MBAR[0x801C]))
+#define MCF_DMA_TCR1                         (*(volatile uint16_t*)(&_MBAR[0x801E]))
+#define MCF_DMA_TCR2                         (*(volatile uint16_t*)(&_MBAR[0x8020]))
+#define MCF_DMA_TCR3                         (*(volatile uint16_t*)(&_MBAR[0x8022]))
+#define MCF_DMA_TCR4                         (*(volatile uint16_t*)(&_MBAR[0x8024]))
+#define MCF_DMA_TCR5                         (*(volatile uint16_t*)(&_MBAR[0x8026]))
+#define MCF_DMA_TCR6                         (*(volatile uint16_t*)(&_MBAR[0x8028]))
+#define MCF_DMA_TCR7                         (*(volatile uint16_t*)(&_MBAR[0x802A]))
+#define MCF_DMA_TCR8                         (*(volatile uint16_t*)(&_MBAR[0x802C]))
+#define MCF_DMA_TCR9                         (*(volatile uint16_t*)(&_MBAR[0x802E]))
+#define MCF_DMA_TCR10                        (*(volatile uint16_t*)(&_MBAR[0x8030]))
+#define MCF_DMA_TCR11                        (*(volatile uint16_t*)(&_MBAR[0x8032]))
+#define MCF_DMA_TCR12                        (*(volatile uint16_t*)(&_MBAR[0x8034]))
+#define MCF_DMA_TCR13                        (*(volatile uint16_t*)(&_MBAR[0x8036]))
+#define MCF_DMA_TCR14                        (*(volatile uint16_t*)(&_MBAR[0x8038]))
+#define MCF_DMA_TCR15                        (*(volatile uint16_t*)(&_MBAR[0x803A]))
+#define MCF_DMA_PRIOR0                       (*(volatile uint8_t *)(&_MBAR[0x803C]))
+#define MCF_DMA_PRIOR1                       (*(volatile uint8_t *)(&_MBAR[0x803D]))
+#define MCF_DMA_PRIOR2                       (*(volatile uint8_t *)(&_MBAR[0x803E]))
+#define MCF_DMA_PRIOR3                       (*(volatile uint8_t *)(&_MBAR[0x803F]))
+#define MCF_DMA_PRIOR4                       (*(volatile uint8_t *)(&_MBAR[0x8040]))
+#define MCF_DMA_PRIOR5                       (*(volatile uint8_t *)(&_MBAR[0x8041]))
+#define MCF_DMA_PRIOR6                       (*(volatile uint8_t *)(&_MBAR[0x8042]))
+#define MCF_DMA_PRIOR7                       (*(volatile uint8_t *)(&_MBAR[0x8043]))
+#define MCF_DMA_PRIOR8                       (*(volatile uint8_t *)(&_MBAR[0x8044]))
+#define MCF_DMA_PRIOR9                       (*(volatile uint8_t *)(&_MBAR[0x8045]))
+#define MCF_DMA_PRIOR10                      (*(volatile uint8_t *)(&_MBAR[0x8046]))
+#define MCF_DMA_PRIOR11                      (*(volatile uint8_t *)(&_MBAR[0x8047]))
+#define MCF_DMA_PRIOR12                      (*(volatile uint8_t *)(&_MBAR[0x8048]))
+#define MCF_DMA_PRIOR13                      (*(volatile uint8_t *)(&_MBAR[0x8049]))
+#define MCF_DMA_PRIOR14                      (*(volatile uint8_t *)(&_MBAR[0x804A]))
+#define MCF_DMA_PRIOR15                      (*(volatile uint8_t *)(&_MBAR[0x804B]))
+#define MCF_DMA_PRIOR16                      (*(volatile uint8_t *)(&_MBAR[0x804C]))
+#define MCF_DMA_PRIOR17                      (*(volatile uint8_t *)(&_MBAR[0x804D]))
+#define MCF_DMA_PRIOR18                      (*(volatile uint8_t *)(&_MBAR[0x804E]))
+#define MCF_DMA_PRIOR19                      (*(volatile uint8_t *)(&_MBAR[0x804F]))
+#define MCF_DMA_PRIOR20                      (*(volatile uint8_t *)(&_MBAR[0x8050]))
+#define MCF_DMA_PRIOR21                      (*(volatile uint8_t *)(&_MBAR[0x8051]))
+#define MCF_DMA_PRIOR22                      (*(volatile uint8_t *)(&_MBAR[0x8052]))
+#define MCF_DMA_PRIOR23                      (*(volatile uint8_t *)(&_MBAR[0x8053]))
+#define MCF_DMA_PRIOR24                      (*(volatile uint8_t *)(&_MBAR[0x8054]))
+#define MCF_DMA_PRIOR25                      (*(volatile uint8_t *)(&_MBAR[0x8055]))
+#define MCF_DMA_PRIOR26                      (*(volatile uint8_t *)(&_MBAR[0x8056]))
+#define MCF_DMA_PRIOR27                      (*(volatile uint8_t *)(&_MBAR[0x8057]))
+#define MCF_DMA_PRIOR28                      (*(volatile uint8_t *)(&_MBAR[0x8058]))
+#define MCF_DMA_PRIOR29                      (*(volatile uint8_t *)(&_MBAR[0x8059]))
+#define MCF_DMA_PRIOR30                      (*(volatile uint8_t *)(&_MBAR[0x805A]))
+#define MCF_DMA_PRIOR31                      (*(volatile uint8_t *)(&_MBAR[0x805B]))
+#define MCF_DMA_IMCR                         (*(volatile uint32_t*)(&_MBAR[0x805C]))
+#define MCF_DMA_TSKSZ0                       (*(volatile uint32_t*)(&_MBAR[0x8060]))
+#define MCF_DMA_TSKSZ1                       (*(volatile uint32_t*)(&_MBAR[0x8064]))
+#define MCF_DMA_DBGCOMP0                     (*(volatile uint32_t*)(&_MBAR[0x8070]))
+#define MCF_DMA_DBGCOMP2                     (*(volatile uint32_t*)(&_MBAR[0x8074]))
+#define MCF_DMA_DBGCTL                       (*(volatile uint32_t*)(&_MBAR[0x8078]))
+#define MCF_DMA_TCR(x)                       (*(volatile uint16_t*)(&_MBAR[0x801C + ((x)*0x2)]))
+#define MCF_DMA_PRIOR(x)                     (*(volatile uint8_t *)(&_MBAR[0x803C + ((x)*0x1)]))
+
+
+/* Bit definitions and macros for MCF_DMA_TASKBAR */
+#define MCF_DMA_TASKBAR_TASK_BASE_ADDRESS(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_CP */
+#define MCF_DMA_CP_DESCRIPTOR_POINTER(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_EP */
+#define MCF_DMA_EP_DESCRIPTOR_POINTER(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_VP */
+#define MCF_DMA_VP_VARIABLE_POINTER(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_PTD */
+#define MCF_DMA_PTD_PCTL0                    (0x1)
+#define MCF_DMA_PTD_PCTL1                    (0x2)
+#define MCF_DMA_PTD_PCTL13                   (0x2000)
+#define MCF_DMA_PTD_PCTL14                   (0x4000)
+#define MCF_DMA_PTD_PCTL15                   (0x8000)
+
+/* Bit definitions and macros for MCF_DMA_DIPR */
+#define MCF_DMA_DIPR_TASK(x)                 (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DIMR */
+#define MCF_DMA_DIMR_TASK(x)                 (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_TCR */
+#define MCF_DMA_TCR_ASTSKNUM(x)              (((x)&0xF)<<0)
+#define MCF_DMA_TCR_HLDINITNUM               (0x20)
+#define MCF_DMA_TCR_HIPRITSKEN               (0x40)
+#define MCF_DMA_TCR_ASTRT                    (0x80)
+#define MCF_DMA_TCR_INITNUM(x)               (((x)&0x1F)<<0x8)
+#define MCF_DMA_TCR_ALWINIT                  (0x2000)
+#define MCF_DMA_TCR_V                        (0x4000)
+#define MCF_DMA_TCR_EN                       (0x8000)
+
+/* Bit definitions and macros for MCF_DMA_PRIOR */
+#define MCF_DMA_PRIOR_PRI(x)                 (((x)&0x7)<<0)
+#define MCF_DMA_PRIOR_HLD                    (0x80)
+
+/* Bit definitions and macros for MCF_DMA_IMCR */
+#define MCF_DMA_IMCR_IMC16(x)	(((x)&0x3)<<0)
+#define MCF_DMA_IMCR_IMC17(x)	(((x)&0x3)<<0x2)
+#define MCF_DMA_IMCR_IMC18(x)	(((x)&0x3)<<0x4)
+#define MCF_DMA_IMCR_IMC19(x)	(((x)&0x3)<<0x6)
+#define MCF_DMA_IMCR_IMC20(x)	(((x)&0x3)<<0x8)
+#define MCF_DMA_IMCR_IMC21(x)	(((x)&0x3)<<0xA)
+#define MCF_DMA_IMCR_IMC22(x)	(((x)&0x3)<<0xC)
+#define MCF_DMA_IMCR_IMC23(x)	(((x)&0x3)<<0xE)
+#define MCF_DMA_IMCR_IMC24(x)	(((x)&0x3)<<0x10)
+#define MCF_DMA_IMCR_IMC25(x)	(((x)&0x3)<<0x12)
+#define MCF_DMA_IMCR_IMC26(x)	(((x)&0x3)<<0x14)
+#define MCF_DMA_IMCR_IMC27(x)	(((x)&0x3)<<0x16)
+#define MCF_DMA_IMCR_IMC28(x)	(((x)&0x3)<<0x18)
+#define MCF_DMA_IMCR_IMC29(x)	(((x)&0x3)<<0x1A)
+#define MCF_DMA_IMCR_IMC30(x)	(((x)&0x3)<<0x1C)
+#define MCF_DMA_IMCR_IMC31(x)	(((x)&0x3)<<0x1E)
+
+
+#define MCF_DMA_IMCR_IMC16_FEC0RX    (0x00000000)
+#define MCF_DMA_IMCR_IMC17_FEC0TX    (0x00000000)
+#define MCF_DMA_IMCR_IMC18_FEC0RX    (0x00000020)
+#define MCF_DMA_IMCR_IMC19_FEC0TX    (0x00000080)
+#define MCF_DMA_IMCR_IMC20_FEC1RX    (0x00000100)
+#define MCF_DMA_IMCR_IMC21_DREQ1     (0x00000000)
+#define MCF_DMA_IMCR_IMC21_FEC1TX    (0x00000400)
+#define MCF_DMA_IMCR_IMC22_FEC0RX    (0x00001000)
+#define MCF_DMA_IMCR_IMC23_FEC0TX    (0x00004000)
+#define MCF_DMA_IMCR_IMC24_CTM0      (0x00010000)
+#define MCF_DMA_IMCR_IMC24_FEC1RX    (0x00020000)
+#define MCF_DMA_IMCR_IMC25_CTM1      (0x00040000)
+#define MCF_DMA_IMCR_IMC25_FEC1TX    (0x00080000)
+#define MCF_DMA_IMCR_IMC26_USBEP4    (0x00000000)
+#define MCF_DMA_IMCR_IMC26_CTM2      (0x00200000)
+#define MCF_DMA_IMCR_IMC27_USBEP5    (0x00000000)
+#define MCF_DMA_IMCR_IMC27_CTM3      (0x00800000)
+#define MCF_DMA_IMCR_IMC28_USBEP6    (0x00000000)
+#define MCF_DMA_IMCR_IMC28_CTM4      (0x01000000)
+#define MCF_DMA_IMCR_IMC28_DREQ1     (0x02000000)
+#define MCF_DMA_IMCR_IMC28_PSC2RX    (0x03000000)
+#define MCF_DMA_IMCR_IMC29_DREQ1     (0x04000000)
+#define MCF_DMA_IMCR_IMC29_CTM5      (0x08000000)
+#define MCF_DMA_IMCR_IMC29_PSC2TX    (0x0C000000)
+#define MCF_DMA_IMCR_IMC30_FEC1RX    (0x00000000)
+#define MCF_DMA_IMCR_IMC30_CTM6      (0x10000000)
+#define MCF_DMA_IMCR_IMC30_PSC3RX    (0x30000000)
+#define MCF_DMA_IMCR_IMC31_FEC1TX    (0x00000000)
+#define MCF_DMA_IMCR_IMC31_CTM7      (0x80000000)
+#define MCF_DMA_IMCR_IMC31_PSC3TX    (0xC0000000)
+
+/* Bit definitions and macros for MCF_DMA_TSKSZ0 */
+#define MCF_DMA_TSKSZ0_DSTSZ7(x)             (((x)&0x3)<<0)
+#define MCF_DMA_TSKSZ0_SRCSZ7(x)             (((x)&0x3)<<0x2)
+#define MCF_DMA_TSKSZ0_DSTSZ6(x)             (((x)&0x3)<<0x4)
+#define MCF_DMA_TSKSZ0_SRCSZ6(x)             (((x)&0x3)<<0x6)
+#define MCF_DMA_TSKSZ0_DSTSZ5(x)             (((x)&0x3)<<0x8)
+#define MCF_DMA_TSKSZ0_SRCSZ5(x)             (((x)&0x3)<<0xA)
+#define MCF_DMA_TSKSZ0_DSTSZ4(x)             (((x)&0x3)<<0xC)
+#define MCF_DMA_TSKSZ0_SRCSZ4(x)             (((x)&0x3)<<0xE)
+#define MCF_DMA_TSKSZ0_DSTSZ3(x)             (((x)&0x3)<<0x10)
+#define MCF_DMA_TSKSZ0_SRCSZ3(x)             (((x)&0x3)<<0x12)
+#define MCF_DMA_TSKSZ0_DSTSZ2(x)             (((x)&0x3)<<0x14)
+#define MCF_DMA_TSKSZ0_SRCSZ2(x)             (((x)&0x3)<<0x16)
+#define MCF_DMA_TSKSZ0_DSTSZ1(x)             (((x)&0x3)<<0x18)
+#define MCF_DMA_TSKSZ0_SRCSZ1(x)             (((x)&0x3)<<0x1A)
+#define MCF_DMA_TSKSZ0_DSTSZ0(x)             (((x)&0x3)<<0x1C)
+#define MCF_DMA_TSKSZ0_SRCSZ0(x)             (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_DMA_TSKSZ1 */
+#define MCF_DMA_TSKSZ1_DSTSZ15(x)            (((x)&0x3)<<0)
+#define MCF_DMA_TSKSZ1_SRCSZ15(x)            (((x)&0x3)<<0x2)
+#define MCF_DMA_TSKSZ1_DSTSZ14(x)            (((x)&0x3)<<0x4)
+#define MCF_DMA_TSKSZ1_SRCSZ14(x)            (((x)&0x3)<<0x6)
+#define MCF_DMA_TSKSZ1_DSTSZ13(x)            (((x)&0x3)<<0x8)
+#define MCF_DMA_TSKSZ1_SRCSZ13(x)            (((x)&0x3)<<0xA)
+#define MCF_DMA_TSKSZ1_DSTSZ12(x)            (((x)&0x3)<<0xC)
+#define MCF_DMA_TSKSZ1_SRCSZ12(x)            (((x)&0x3)<<0xE)
+#define MCF_DMA_TSKSZ1_DSTSZ11(x)            (((x)&0x3)<<0x10)
+#define MCF_DMA_TSKSZ1_SRCSZ11(x)            (((x)&0x3)<<0x12)
+#define MCF_DMA_TSKSZ1_DSTSZ10(x)            (((x)&0x3)<<0x14)
+#define MCF_DMA_TSKSZ1_SRCSZ10(x)            (((x)&0x3)<<0x16)
+#define MCF_DMA_TSKSZ1_DSTSZ9(x)             (((x)&0x3)<<0x18)
+#define MCF_DMA_TSKSZ1_SRCSZ9(x)             (((x)&0x3)<<0x1A)
+#define MCF_DMA_TSKSZ1_DSTSZ8(x)             (((x)&0x3)<<0x1C)
+#define MCF_DMA_TSKSZ1_SRCSZ8(x)             (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_DMA_DBGCOMP0 */
+#define MCF_DMA_DBGCOMP0_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DBGCOMP2 */
+#define MCF_DMA_DBGCOMP2_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DBGCTL */
+#define MCF_DMA_DBGCTL_I                     (0x2)
+#define MCF_DMA_DBGCTL_E                     (0x4)
+#define MCF_DMA_DBGCTL_AND_OR                (0x80)
+#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_2(x)  (((x)&0x7)<<0x8)
+#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_1(x)  (((x)&0x7)<<0xB)
+#define MCF_DMA_DBGCTL_B                     (0x4000)
+#define MCF_DMA_DBGCTL_AA                    (0x8000)
+#define MCF_DMA_DBGCTL_BLOCK_TASKS(x)        (((x)&0xFFFF)<<0x10)
+
+
+#endif /* __MCF5475_DMA_H__ */

tos/fpga_test/include/MCF5475_DSPI.h

@@ -0,0 +1,150 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_DSPI_H__
+#define __MCF5475_DSPI_H__
+
+
+/*********************************************************************
+*
+* DMA Serial Peripheral Interface (DSPI)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_DSPI_DMCR                        (*(volatile uint32_t*)(&_MBAR[0x8A00]))
+#define MCF_DSPI_DTCR                        (*(volatile uint32_t*)(&_MBAR[0x8A08]))
+#define MCF_DSPI_DCTAR0                      (*(volatile uint32_t*)(&_MBAR[0x8A0C]))
+#define MCF_DSPI_DCTAR1                      (*(volatile uint32_t*)(&_MBAR[0x8A10]))
+#define MCF_DSPI_DCTAR2                      (*(volatile uint32_t*)(&_MBAR[0x8A14]))
+#define MCF_DSPI_DCTAR3                      (*(volatile uint32_t*)(&_MBAR[0x8A18]))
+#define MCF_DSPI_DCTAR4                      (*(volatile uint32_t*)(&_MBAR[0x8A1C]))
+#define MCF_DSPI_DCTAR5                      (*(volatile uint32_t*)(&_MBAR[0x8A20]))
+#define MCF_DSPI_DCTAR6                      (*(volatile uint32_t*)(&_MBAR[0x8A24]))
+#define MCF_DSPI_DCTAR7                      (*(volatile uint32_t*)(&_MBAR[0x8A28]))
+#define MCF_DSPI_DSR                         (*(volatile uint32_t*)(&_MBAR[0x8A2C]))
+#define MCF_DSPI_DIRSR                       (*(volatile uint32_t*)(&_MBAR[0x8A30]))
+#define MCF_DSPI_DTFR                        (*(volatile uint32_t*)(&_MBAR[0x8A34]))
+#define MCF_DSPI_DRFR                        (*(volatile uint32_t*)(&_MBAR[0x8A38]))
+#define MCF_DSPI_DTFDR0                      (*(volatile uint32_t*)(&_MBAR[0x8A3C]))
+#define MCF_DSPI_DTFDR1                      (*(volatile uint32_t*)(&_MBAR[0x8A40]))
+#define MCF_DSPI_DTFDR2                      (*(volatile uint32_t*)(&_MBAR[0x8A44]))
+#define MCF_DSPI_DTFDR3                      (*(volatile uint32_t*)(&_MBAR[0x8A48]))
+#define MCF_DSPI_DRFDR0                      (*(volatile uint32_t*)(&_MBAR[0x8A7C]))
+#define MCF_DSPI_DRFDR1                      (*(volatile uint32_t*)(&_MBAR[0x8A80]))
+#define MCF_DSPI_DRFDR2                      (*(volatile uint32_t*)(&_MBAR[0x8A84]))
+#define MCF_DSPI_DRFDR3                      (*(volatile uint32_t*)(&_MBAR[0x8A88]))
+#define MCF_DSPI_DCTAR(x)                    (*(volatile uint32_t*)(&_MBAR[0x8A0C + ((x)*0x4)]))
+#define MCF_DSPI_DTFDR(x)                    (*(volatile uint32_t*)(&_MBAR[0x8A3C + ((x)*0x4)]))
+#define MCF_DSPI_DRFDR(x)                    (*(volatile uint32_t*)(&_MBAR[0x8A7C + ((x)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_DSPI_DMCR */
+#define MCF_DSPI_DMCR_HALT                   (0x1)
+#define MCF_DSPI_DMCR_SMPL_PT(x)             (((x)&0x3)<<0x8)
+#define MCF_DSPI_DMCR_SMPL_PT_0CLK           (0)
+#define MCF_DSPI_DMCR_SMPL_PT_1CLK           (0x100)
+#define MCF_DSPI_DMCR_SMPL_PT_2CLK           (0x200)
+#define MCF_DSPI_DMCR_CRXF                   (0x400)
+#define MCF_DSPI_DMCR_CTXF                   (0x800)
+#define MCF_DSPI_DMCR_DRXF                   (0x1000)
+#define MCF_DSPI_DMCR_DTXF                   (0x2000)
+#define MCF_DSPI_DMCR_CSIS0                  (0x10000)
+#define MCF_DSPI_DMCR_CSIS2                  (0x40000)
+#define MCF_DSPI_DMCR_CSIS3                  (0x80000)
+#define MCF_DSPI_DMCR_CSIS5                  (0x200000)
+#define MCF_DSPI_DMCR_ROOE                   (0x1000000)
+#define MCF_DSPI_DMCR_PCSSE                  (0x2000000)
+#define MCF_DSPI_DMCR_MTFE                   (0x4000000)
+#define MCF_DSPI_DMCR_FRZ                    (0x8000000)
+#define MCF_DSPI_DMCR_DCONF(x)               (((x)&0x3)<<0x1C)
+#define MCF_DSPI_DMCR_CSCK                   (0x40000000)
+#define MCF_DSPI_DMCR_MSTR                   (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DTCR */
+#define MCF_DSPI_DTCR_SPI_TCNT(x)            (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_DSPI_DCTAR */
+#define MCF_DSPI_DCTAR_BR(x)                 (((x)&0xF)<<0)
+#define MCF_DSPI_DCTAR_DT(x)                 (((x)&0xF)<<0x4)
+#define MCF_DSPI_DCTAR_ASC(x)                (((x)&0xF)<<0x8)
+#define MCF_DSPI_DCTAR_CSSCK(x)              (((x)&0xF)<<0xC)
+#define MCF_DSPI_DCTAR_PBR(x)                (((x)&0x3)<<0x10)
+#define MCF_DSPI_DCTAR_PBR_1CLK              (0)
+#define MCF_DSPI_DCTAR_PBR_3CLK              (0x10000)
+#define MCF_DSPI_DCTAR_PBR_5CLK              (0x20000)
+#define MCF_DSPI_DCTAR_PBR_7CLK              (0x30000)
+#define MCF_DSPI_DCTAR_PDT(x)                (((x)&0x3)<<0x12)
+#define MCF_DSPI_DCTAR_PDT_1CLK              (0)
+#define MCF_DSPI_DCTAR_PDT_3CLK              (0x40000)
+#define MCF_DSPI_DCTAR_PDT_5CLK              (0x80000)
+#define MCF_DSPI_DCTAR_PDT_7CLK              (0xC0000)
+#define MCF_DSPI_DCTAR_PASC(x)               (((x)&0x3)<<0x14)
+#define MCF_DSPI_DCTAR_PASC_1CLK             (0)
+#define MCF_DSPI_DCTAR_PASC_3CLK             (0x100000)
+#define MCF_DSPI_DCTAR_PASC_5CLK             (0x200000)
+#define MCF_DSPI_DCTAR_PASC_7CLK             (0x300000)
+#define MCF_DSPI_DCTAR_PCSSCK(x)             (((x)&0x3)<<0x16)
+#define MCF_DSPI_DCTAR_LSBFE                 (0x1000000)
+#define MCF_DSPI_DCTAR_CPHA                  (0x2000000)
+#define MCF_DSPI_DCTAR_CPOL                  (0x4000000)
+#define MCF_DSPI_DCTAR_TRSZ(x)               (((x)&0xF)<<0x1B)
+
+/* Bit definitions and macros for MCF_DSPI_DSR */
+#define MCF_DSPI_DSR_RXPTR(x)                (((x)&0xF)<<0)
+#define MCF_DSPI_DSR_RXCTR(x)                (((x)&0xF)<<0x4)
+#define MCF_DSPI_DSR_TXPTR(x)                (((x)&0xF)<<0x8)
+#define MCF_DSPI_DSR_TXCTR(x)                (((x)&0xF)<<0xC)
+#define MCF_DSPI_DSR_RFDF                    (0x20000)
+#define MCF_DSPI_DSR_RFOF                    (0x80000)
+#define MCF_DSPI_DSR_TFFF                    (0x2000000)
+#define MCF_DSPI_DSR_TFUF                    (0x8000000)
+#define MCF_DSPI_DSR_EOQF                    (0x10000000)
+#define MCF_DSPI_DSR_TXRXS                   (0x40000000)
+#define MCF_DSPI_DSR_TCF                     (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DIRSR */
+#define MCF_DSPI_DIRSR_RFDFS                 (0x10000)
+#define MCF_DSPI_DIRSR_RFDFE                 (0x20000)
+#define MCF_DSPI_DIRSR_RFOFE                 (0x80000)
+#define MCF_DSPI_DIRSR_TFFFS                 (0x1000000)
+#define MCF_DSPI_DIRSR_TFFFE                 (0x2000000)
+#define MCF_DSPI_DIRSR_TFUFE                 (0x8000000)
+#define MCF_DSPI_DIRSR_EOQFE                 (0x10000000)
+#define MCF_DSPI_DIRSR_TCFE                  (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DTFR */
+#define MCF_DSPI_DTFR_TXDATA(x)              (((x)&0xFFFF)<<0)
+#define MCF_DSPI_DTFR_CS0                    (0x10000)
+#define MCF_DSPI_DTFR_CS2                    (0x40000)
+#define MCF_DSPI_DTFR_CS3                    (0x80000)
+#define MCF_DSPI_DTFR_CS5                    (0x200000)
+#define MCF_DSPI_DTFR_CTCNT                  (0x4000000)
+#define MCF_DSPI_DTFR_EOQ                    (0x8000000)
+#define MCF_DSPI_DTFR_CTAS(x)                (((x)&0x7)<<0x1C)
+#define MCF_DSPI_DTFR_CONT                   (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DRFR */
+#define MCF_DSPI_DRFR_RXDATA(x)              (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DSPI_DTFDR */
+#define MCF_DSPI_DTFDR_TXDATA(x)             (((x)&0xFFFF)<<0)
+#define MCF_DSPI_DTFDR_TXCMD(x)              (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_DSPI_DRFDR */
+#define MCF_DSPI_DRFDR_RXDATA(x)             (((x)&0xFFFF)<<0)
+
+
+#endif /* __MCF5475_DSPI_H__ */

tos/fpga_test/include/MCF5475_EPORT.h

@@ -0,0 +1,123 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_EPORT_H__
+#define __MCF5475_EPORT_H__
+
+
+/*********************************************************************
+*
+* Edge Port Module (EPORT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_EPORT_EPPAR                      (*(volatile uint16_t*)(&_MBAR[0xF00]))
+#define MCF_EPORT_EPDDR                      (*(volatile uint8_t *)(&_MBAR[0xF04]))
+#define MCF_EPORT_EPIER                      (*(volatile uint8_t *)(&_MBAR[0xF05]))
+#define MCF_EPORT_EPDR                       (*(volatile uint8_t *)(&_MBAR[0xF08]))
+#define MCF_EPORT_EPPDR                      (*(volatile uint8_t *)(&_MBAR[0xF09]))
+#define MCF_EPORT_EPFR                       (*(volatile uint8_t *)(&_MBAR[0xF0C]))
+
+
+
+/* Bit definitions and macros for MCF_EPORT_EPPAR */
+#define MCF_EPORT_EPPAR_EPPA1(x)             (((x)&0x3)<<0x2)
+#define MCF_EPORT_EPPAR_EPPA1_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA1_RISING         (0x4)
+#define MCF_EPORT_EPPAR_EPPA1_FALLING        (0x8)
+#define MCF_EPORT_EPPAR_EPPA1_BOTH           (0xC)
+#define MCF_EPORT_EPPAR_EPPA2(x)             (((x)&0x3)<<0x4)
+#define MCF_EPORT_EPPAR_EPPA2_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA2_RISING         (0x10)
+#define MCF_EPORT_EPPAR_EPPA2_FALLING        (0x20)
+#define MCF_EPORT_EPPAR_EPPA2_BOTH           (0x30)
+#define MCF_EPORT_EPPAR_EPPA3(x)             (((x)&0x3)<<0x6)
+#define MCF_EPORT_EPPAR_EPPA3_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA3_RISING         (0x40)
+#define MCF_EPORT_EPPAR_EPPA3_FALLING        (0x80)
+#define MCF_EPORT_EPPAR_EPPA3_BOTH           (0xC0)
+#define MCF_EPORT_EPPAR_EPPA4(x)             (((x)&0x3)<<0x8)
+#define MCF_EPORT_EPPAR_EPPA4_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA4_RISING         (0x100)
+#define MCF_EPORT_EPPAR_EPPA4_FALLING        (0x200)
+#define MCF_EPORT_EPPAR_EPPA4_BOTH           (0x300)
+#define MCF_EPORT_EPPAR_EPPA5(x)             (((x)&0x3)<<0xA)
+#define MCF_EPORT_EPPAR_EPPA5_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA5_RISING         (0x400)
+#define MCF_EPORT_EPPAR_EPPA5_FALLING        (0x800)
+#define MCF_EPORT_EPPAR_EPPA5_BOTH           (0xC00)
+#define MCF_EPORT_EPPAR_EPPA6(x)             (((x)&0x3)<<0xC)
+#define MCF_EPORT_EPPAR_EPPA6_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA6_RISING         (0x1000)
+#define MCF_EPORT_EPPAR_EPPA6_FALLING        (0x2000)
+#define MCF_EPORT_EPPAR_EPPA6_BOTH           (0x3000)
+#define MCF_EPORT_EPPAR_EPPA7(x)             (((x)&0x3)<<0xE)
+#define MCF_EPORT_EPPAR_EPPA7_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA7_RISING         (0x4000)
+#define MCF_EPORT_EPPAR_EPPA7_FALLING        (0x8000)
+#define MCF_EPORT_EPPAR_EPPA7_BOTH           (0xC000)
+#define MCF_EPORT_EPPAR_LEVEL                (0)
+#define MCF_EPORT_EPPAR_RISING               (0x1)
+#define MCF_EPORT_EPPAR_FALLING              (0x2)
+#define MCF_EPORT_EPPAR_BOTH                 (0x3)
+
+/* Bit definitions and macros for MCF_EPORT_EPDDR */
+#define MCF_EPORT_EPDDR_EPDD1                (0x2)
+#define MCF_EPORT_EPDDR_EPDD2                (0x4)
+#define MCF_EPORT_EPDDR_EPDD3                (0x8)
+#define MCF_EPORT_EPDDR_EPDD4                (0x10)
+#define MCF_EPORT_EPDDR_EPDD5                (0x20)
+#define MCF_EPORT_EPDDR_EPDD6                (0x40)
+#define MCF_EPORT_EPDDR_EPDD7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPIER */
+#define MCF_EPORT_EPIER_EPIE1                (0x2)
+#define MCF_EPORT_EPIER_EPIE2                (0x4)
+#define MCF_EPORT_EPIER_EPIE3                (0x8)
+#define MCF_EPORT_EPIER_EPIE4                (0x10)
+#define MCF_EPORT_EPIER_EPIE5                (0x20)
+#define MCF_EPORT_EPIER_EPIE6                (0x40)
+#define MCF_EPORT_EPIER_EPIE7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPDR */
+#define MCF_EPORT_EPDR_EPD1                  (0x2)
+#define MCF_EPORT_EPDR_EPD2                  (0x4)
+#define MCF_EPORT_EPDR_EPD3                  (0x8)
+#define MCF_EPORT_EPDR_EPD4                  (0x10)
+#define MCF_EPORT_EPDR_EPD5                  (0x20)
+#define MCF_EPORT_EPDR_EPD6                  (0x40)
+#define MCF_EPORT_EPDR_EPD7                  (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPPDR */
+#define MCF_EPORT_EPPDR_EPPD1                (0x2)
+#define MCF_EPORT_EPPDR_EPPD2                (0x4)
+#define MCF_EPORT_EPPDR_EPPD3                (0x8)
+#define MCF_EPORT_EPPDR_EPPD4                (0x10)
+#define MCF_EPORT_EPPDR_EPPD5                (0x20)
+#define MCF_EPORT_EPPDR_EPPD6                (0x40)
+#define MCF_EPORT_EPPDR_EPPD7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPFR */
+#define MCF_EPORT_EPFR_EPF1                  (0x2)
+#define MCF_EPORT_EPFR_EPF2                  (0x4)
+#define MCF_EPORT_EPFR_EPF3                  (0x8)
+#define MCF_EPORT_EPFR_EPF4                  (0x10)
+#define MCF_EPORT_EPFR_EPF5                  (0x20)
+#define MCF_EPORT_EPFR_EPF6                  (0x40)
+#define MCF_EPORT_EPFR_EPF7                  (0x80)
+
+
+#endif /* __MCF5475_EPORT_H__ */

tos/fpga_test/include/MCF5475_FBCS.h

@@ -0,0 +1,100 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_FBCS_H__
+#define __MCF5475_FBCS_H__
+
+
+/*********************************************************************
+*
+* FlexBus Chip Select Module (FBCS)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FBCS0_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x500]))
+#define MCF_FBCS0_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x504]))
+#define MCF_FBCS0_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x508]))
+
+#define MCF_FBCS1_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x50C]))
+#define MCF_FBCS1_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x510]))
+#define MCF_FBCS1_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x514]))
+
+#define MCF_FBCS2_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x518]))
+#define MCF_FBCS2_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x51C]))
+#define MCF_FBCS2_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x520]))
+
+#define MCF_FBCS3_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x524]))
+#define MCF_FBCS3_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x528]))
+#define MCF_FBCS3_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x52C]))
+
+#define MCF_FBCS4_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x530]))
+#define MCF_FBCS4_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x534]))
+#define MCF_FBCS4_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x538]))
+
+#define MCF_FBCS5_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x53C]))
+#define MCF_FBCS5_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x540]))
+#define MCF_FBCS5_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x544]))
+
+#define MCF_FBCS_CSAR(x)                     (*(volatile uint32_t*)(&_MBAR[0x500 + ((x)*0xC)]))
+#define MCF_FBCS_CSMR(x)                     (*(volatile uint32_t*)(&_MBAR[0x504 + ((x)*0xC)]))
+#define MCF_FBCS_CSCR(x)                     (*(volatile uint32_t*)(&_MBAR[0x508 + ((x)*0xC)]))
+
+
+/* Bit definitions and macros for MCF_FBCS_CSAR */
+#define MCF_FBCS_CSAR_BA(x)                  ((x)&0xFFFF0000)
+
+/* Bit definitions and macros for MCF_FBCS_CSMR */
+#define MCF_FBCS_CSMR_V                      (0x1)
+#define MCF_FBCS_CSMR_WP                     (0x100)
+#define MCF_FBCS_CSMR_BAM(x)                 (((x)&0xFFFF)<<0x10)
+#define MCF_FBCS_CSMR_BAM_4G                 (0xFFFF0000)
+#define MCF_FBCS_CSMR_BAM_2G                 (0x7FFF0000)
+#define MCF_FBCS_CSMR_BAM_1G                 (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_1024M              (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_512M               (0x1FFF0000)
+#define MCF_FBCS_CSMR_BAM_256M               (0xFFF0000)
+#define MCF_FBCS_CSMR_BAM_128M               (0x7FF0000)
+#define MCF_FBCS_CSMR_BAM_64M                (0x3FF0000)
+#define MCF_FBCS_CSMR_BAM_32M                (0x1FF0000)
+#define MCF_FBCS_CSMR_BAM_16M                (0xFF0000)
+#define MCF_FBCS_CSMR_BAM_8M                 (0x7F0000)
+#define MCF_FBCS_CSMR_BAM_4M                 (0x3F0000)
+#define MCF_FBCS_CSMR_BAM_2M                 (0x1F0000)
+#define MCF_FBCS_CSMR_BAM_1M                 (0xF0000)
+#define MCF_FBCS_CSMR_BAM_1024K              (0xF0000)
+#define MCF_FBCS_CSMR_BAM_512K               (0x70000)
+#define MCF_FBCS_CSMR_BAM_256K               (0x30000)
+#define MCF_FBCS_CSMR_BAM_128K               (0x10000)
+#define MCF_FBCS_CSMR_BAM_64K                (0)
+
+/* Bit definitions and macros for MCF_FBCS_CSCR */
+#define MCF_FBCS_CSCR_BSTW                   (0x8)
+#define MCF_FBCS_CSCR_BSTR                   (0x10)
+#define MCF_FBCS_CSCR_BEM                    (0x20)
+#define MCF_FBCS_CSCR_PS(x)                  (((x)&0x3)<<0x6)
+#define MCF_FBCS_CSCR_PS_32                  (0)
+#define MCF_FBCS_CSCR_PS_8                   (0x40)
+#define MCF_FBCS_CSCR_PS_16                  (0x80)
+#define MCF_FBCS_CSCR_AA                     (0x100)
+#define MCF_FBCS_CSCR_WS(x)                  (((x)&0x3F)<<0xA)
+#define MCF_FBCS_CSCR_WRAH(x)                (((x)&0x3)<<0x10)
+#define MCF_FBCS_CSCR_RDAH(x)                (((x)&0x3)<<0x12)
+#define MCF_FBCS_CSCR_ASET(x)                (((x)&0x3)<<0x14)
+#define MCF_FBCS_CSCR_SWSEN                  (0x800000)
+#define MCF_FBCS_CSCR_SWS(x)                 (((x)&0x3F)<<0x1A)
+
+
+#endif /* __MCF5475_FBCS_H__ */

tos/fpga_test/include/MCF5475_FEC.h

@@ -0,0 +1,680 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_FEC_H__
+#define __MCF5475_FEC_H__
+
+
+/*********************************************************************
+*
+* Fast Ethernet Controller(FEC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FEC0_EIR                         (*(volatile uint32_t*)(&_MBAR[0x9004]))
+#define MCF_FEC0_EIMR                        (*(volatile uint32_t*)(&_MBAR[0x9008]))
+#define MCF_FEC0_ECR                         (*(volatile uint32_t*)(&_MBAR[0x9024]))
+#define MCF_FEC0_MMFR                        (*(volatile uint32_t*)(&_MBAR[0x9040]))
+#define MCF_FEC0_MSCR                        (*(volatile uint32_t*)(&_MBAR[0x9044]))
+#define MCF_FEC0_MIBC                        (*(volatile uint32_t*)(&_MBAR[0x9064]))
+#define MCF_FEC0_RCR                         (*(volatile uint32_t*)(&_MBAR[0x9084]))
+#define MCF_FEC0_RHR                         (*(volatile uint32_t*)(&_MBAR[0x9088]))
+#define MCF_FEC0_TCR                         (*(volatile uint32_t*)(&_MBAR[0x90C4]))
+#define MCF_FEC0_PALR                        (*(volatile uint32_t*)(&_MBAR[0x90E4]))
+#define MCF_FEC0_PAHR                        (*(volatile uint32_t*)(&_MBAR[0x90E8]))
+#define MCF_FEC0_OPD                         (*(volatile uint32_t*)(&_MBAR[0x90EC]))
+#define MCF_FEC0_IAUR                        (*(volatile uint32_t*)(&_MBAR[0x9118]))
+#define MCF_FEC0_IALR                        (*(volatile uint32_t*)(&_MBAR[0x911C]))
+#define MCF_FEC0_GAUR                        (*(volatile uint32_t*)(&_MBAR[0x9120]))
+#define MCF_FEC0_GALR                        (*(volatile uint32_t*)(&_MBAR[0x9124]))
+#define MCF_FEC0_FECTFWR                     (*(volatile uint32_t*)(&_MBAR[0x9144]))
+#define MCF_FEC0_FECRFDR                     (*(volatile uint32_t*)(&_MBAR[0x9184]))
+#define MCF_FEC0_FECRFSR                     (*(volatile uint32_t*)(&_MBAR[0x9188]))
+#define MCF_FEC0_FECRFCR                     (*(volatile uint32_t*)(&_MBAR[0x918C]))
+#define MCF_FEC0_FECRLRFP                    (*(volatile uint32_t*)(&_MBAR[0x9190]))
+#define MCF_FEC0_FECRLWFP                    (*(volatile uint32_t*)(&_MBAR[0x9194]))
+#define MCF_FEC0_FECRFAR                     (*(volatile uint32_t*)(&_MBAR[0x9198]))
+#define MCF_FEC0_FECRFRP                     (*(volatile uint32_t*)(&_MBAR[0x919C]))
+#define MCF_FEC0_FECRFWP                     (*(volatile uint32_t*)(&_MBAR[0x91A0]))
+#define MCF_FEC0_FECTFDR                     (*(volatile uint32_t*)(&_MBAR[0x91A4]))
+#define MCF_FEC0_FECTFSR                     (*(volatile uint32_t*)(&_MBAR[0x91A8]))
+#define MCF_FEC0_FECTFCR                     (*(volatile uint32_t*)(&_MBAR[0x91AC]))
+#define MCF_FEC0_FECTLRFP                    (*(volatile uint32_t*)(&_MBAR[0x91B0]))
+#define MCF_FEC0_FECTLWFP                    (*(volatile uint32_t*)(&_MBAR[0x91B4]))
+#define MCF_FEC0_FECTFAR                     (*(volatile uint32_t*)(&_MBAR[0x91B8]))
+#define MCF_FEC0_FECTFRP                     (*(volatile uint32_t*)(&_MBAR[0x91BC]))
+#define MCF_FEC0_FECTFWP                     (*(volatile uint32_t*)(&_MBAR[0x91C0]))
+#define MCF_FEC0_FECFRST                     (*(volatile uint32_t*)(&_MBAR[0x91C4]))
+#define MCF_FEC0_FECCTCWR                    (*(volatile uint32_t*)(&_MBAR[0x91C8]))
+#define MCF_FEC0_RMON_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9200]))
+#define MCF_FEC0_RMON_T_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9204]))
+#define MCF_FEC0_RMON_T_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9208]))
+#define MCF_FEC0_RMON_T_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x920C]))
+#define MCF_FEC0_RMON_T_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9210]))
+#define MCF_FEC0_RMON_T_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9214]))
+#define MCF_FEC0_RMON_T_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9218]))
+#define MCF_FEC0_RMON_T_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x921C]))
+#define MCF_FEC0_RMON_T_JAB                  (*(volatile uint32_t*)(&_MBAR[0x9220]))
+#define MCF_FEC0_RMON_T_COL                  (*(volatile uint32_t*)(&_MBAR[0x9224]))
+#define MCF_FEC0_RMON_T_P64                  (*(volatile uint32_t*)(&_MBAR[0x9228]))
+#define MCF_FEC0_RMON_T_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x922C]))
+#define MCF_FEC0_RMON_T_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x9230]))
+#define MCF_FEC0_RMON_T_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x9234]))
+#define MCF_FEC0_RMON_T_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x9238]))
+#define MCF_FEC0_RMON_T_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x923C]))
+#define MCF_FEC0_RMON_T_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x9240]))
+#define MCF_FEC0_RMON_T_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x9244]))
+#define MCF_FEC0_IEEE_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9248]))
+#define MCF_FEC0_IEEE_T_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x924C]))
+#define MCF_FEC0_IEEE_T_1COL                 (*(volatile uint32_t*)(&_MBAR[0x9250]))
+#define MCF_FEC0_IEEE_T_MCOL                 (*(volatile uint32_t*)(&_MBAR[0x9254]))
+#define MCF_FEC0_IEEE_T_DEF                  (*(volatile uint32_t*)(&_MBAR[0x9258]))
+#define MCF_FEC0_IEEE_T_LCOL                 (*(volatile uint32_t*)(&_MBAR[0x925C]))
+#define MCF_FEC0_IEEE_T_EXCOL                (*(volatile uint32_t*)(&_MBAR[0x9260]))
+#define MCF_FEC0_IEEE_T_MACERR               (*(volatile uint32_t*)(&_MBAR[0x9264]))
+#define MCF_FEC0_IEEE_T_CSERR                (*(volatile uint32_t*)(&_MBAR[0x9268]))
+#define MCF_FEC0_IEEE_T_SQE                  (*(volatile uint32_t*)(&_MBAR[0x926C]))
+#define MCF_FEC0_IEEE_T_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x9270]))
+#define MCF_FEC0_IEEE_T_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x9274]))
+#define MCF_FEC0_RMON_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9280]))
+#define MCF_FEC0_RMON_R_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9284]))
+#define MCF_FEC0_RMON_R_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9288]))
+#define MCF_FEC0_RMON_R_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x928C]))
+#define MCF_FEC0_RMON_R_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9290]))
+#define MCF_FEC0_RMON_R_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9294]))
+#define MCF_FEC0_RMON_R_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9298]))
+#define MCF_FEC0_RMON_R_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x929C]))
+#define MCF_FEC0_RMON_R_JAB                  (*(volatile uint32_t*)(&_MBAR[0x92A0]))
+#define MCF_FEC0_RMON_R_RESVD_0              (*(volatile uint32_t*)(&_MBAR[0x92A4]))
+#define MCF_FEC0_RMON_R_P64                  (*(volatile uint32_t*)(&_MBAR[0x92A8]))
+#define MCF_FEC0_RMON_R_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x92AC]))
+#define MCF_FEC0_RMON_R_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x92B0]))
+#define MCF_FEC0_RMON_R_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x92B4]))
+#define MCF_FEC0_RMON_R_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x92B8]))
+#define MCF_FEC0_RMON_R_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x92BC]))
+#define MCF_FEC0_RMON_R_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x92C0]))
+#define MCF_FEC0_RMON_R_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x92C4]))
+#define MCF_FEC0_IEEE_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x92C8]))
+#define MCF_FEC0_IEEE_R_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x92CC]))
+#define MCF_FEC0_IEEE_R_CRC                  (*(volatile uint32_t*)(&_MBAR[0x92D0]))
+#define MCF_FEC0_IEEE_R_ALIGN                (*(volatile uint32_t*)(&_MBAR[0x92D4]))
+#define MCF_FEC0_IEEE_R_MACERR               (*(volatile uint32_t*)(&_MBAR[0x92D8]))
+#define MCF_FEC0_IEEE_R_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x92DC]))
+#define MCF_FEC0_IEEE_R_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x92E0]))
+
+#define MCF_FEC1_EIR                         (*(volatile uint32_t*)(&_MBAR[0x9804]))
+#define MCF_FEC1_EIMR                        (*(volatile uint32_t*)(&_MBAR[0x9808]))
+#define MCF_FEC1_ECR                         (*(volatile uint32_t*)(&_MBAR[0x9824]))
+#define MCF_FEC1_MMFR                        (*(volatile uint32_t*)(&_MBAR[0x9840]))
+#define MCF_FEC1_MSCR                        (*(volatile uint32_t*)(&_MBAR[0x9844]))
+#define MCF_FEC1_MIBC                        (*(volatile uint32_t*)(&_MBAR[0x9864]))
+#define MCF_FEC1_RCR                         (*(volatile uint32_t*)(&_MBAR[0x9884]))
+#define MCF_FEC1_RHR                         (*(volatile uint32_t*)(&_MBAR[0x9888]))
+#define MCF_FEC1_TCR                         (*(volatile uint32_t*)(&_MBAR[0x98C4]))
+#define MCF_FEC1_PALR                        (*(volatile uint32_t*)(&_MBAR[0x98E4]))
+#define MCF_FEC1_PAHR                        (*(volatile uint32_t*)(&_MBAR[0x98E8]))
+#define MCF_FEC1_OPD                         (*(volatile uint32_t*)(&_MBAR[0x98EC]))
+#define MCF_FEC1_IAUR                        (*(volatile uint32_t*)(&_MBAR[0x9918]))
+#define MCF_FEC1_IALR                        (*(volatile uint32_t*)(&_MBAR[0x991C]))
+#define MCF_FEC1_GAUR                        (*(volatile uint32_t*)(&_MBAR[0x9920]))
+#define MCF_FEC1_GALR                        (*(volatile uint32_t*)(&_MBAR[0x9924]))
+#define MCF_FEC1_FECTFWR                     (*(volatile uint32_t*)(&_MBAR[0x9944]))
+#define MCF_FEC1_FECRFDR                     (*(volatile uint32_t*)(&_MBAR[0x9984]))
+#define MCF_FEC1_FECRFSR                     (*(volatile uint32_t*)(&_MBAR[0x9988]))
+#define MCF_FEC1_FECRFCR                     (*(volatile uint32_t*)(&_MBAR[0x998C]))
+#define MCF_FEC1_FECRLRFP                    (*(volatile uint32_t*)(&_MBAR[0x9990]))
+#define MCF_FEC1_FECRLWFP                    (*(volatile uint32_t*)(&_MBAR[0x9994]))
+#define MCF_FEC1_FECRFAR                     (*(volatile uint32_t*)(&_MBAR[0x9998]))
+#define MCF_FEC1_FECRFRP                     (*(volatile uint32_t*)(&_MBAR[0x999C]))
+#define MCF_FEC1_FECRFWP                     (*(volatile uint32_t*)(&_MBAR[0x99A0]))
+#define MCF_FEC1_FECTFDR                     (*(volatile uint32_t*)(&_MBAR[0x99A4]))
+#define MCF_FEC1_FECTFSR                     (*(volatile uint32_t*)(&_MBAR[0x99A8]))
+#define MCF_FEC1_FECTFCR                     (*(volatile uint32_t*)(&_MBAR[0x99AC]))
+#define MCF_FEC1_FECTLRFP                    (*(volatile uint32_t*)(&_MBAR[0x99B0]))
+#define MCF_FEC1_FECTLWFP                    (*(volatile uint32_t*)(&_MBAR[0x99B4]))
+#define MCF_FEC1_FECTFAR                     (*(volatile uint32_t*)(&_MBAR[0x99B8]))
+#define MCF_FEC1_FECTFRP                     (*(volatile uint32_t*)(&_MBAR[0x99BC]))
+#define MCF_FEC1_FECTFWP                     (*(volatile uint32_t*)(&_MBAR[0x99C0]))
+#define MCF_FEC1_FECFRST                     (*(volatile uint32_t*)(&_MBAR[0x99C4]))
+#define MCF_FEC1_FECCTCWR                    (*(volatile uint32_t*)(&_MBAR[0x99C8]))
+#define MCF_FEC1_RMON_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9A00]))
+#define MCF_FEC1_RMON_T_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9A04]))
+#define MCF_FEC1_RMON_T_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A08]))
+#define MCF_FEC1_RMON_T_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A0C]))
+#define MCF_FEC1_RMON_T_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9A10]))
+#define MCF_FEC1_RMON_T_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9A14]))
+#define MCF_FEC1_RMON_T_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9A18]))
+#define MCF_FEC1_RMON_T_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x9A1C]))
+#define MCF_FEC1_RMON_T_JAB                  (*(volatile uint32_t*)(&_MBAR[0x9A20]))
+#define MCF_FEC1_RMON_T_COL                  (*(volatile uint32_t*)(&_MBAR[0x9A24]))
+#define MCF_FEC1_RMON_T_P64                  (*(volatile uint32_t*)(&_MBAR[0x9A28]))
+#define MCF_FEC1_RMON_T_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x9A2C]))
+#define MCF_FEC1_RMON_T_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x9A30]))
+#define MCF_FEC1_RMON_T_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x9A34]))
+#define MCF_FEC1_RMON_T_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x9A38]))
+#define MCF_FEC1_RMON_T_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x9A3C]))
+#define MCF_FEC1_RMON_T_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x9A40]))
+#define MCF_FEC1_RMON_T_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x9A44]))
+#define MCF_FEC1_IEEE_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9A48]))
+#define MCF_FEC1_IEEE_T_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x9A4C]))
+#define MCF_FEC1_IEEE_T_1COL                 (*(volatile uint32_t*)(&_MBAR[0x9A50]))
+#define MCF_FEC1_IEEE_T_MCOL                 (*(volatile uint32_t*)(&_MBAR[0x9A54]))
+#define MCF_FEC1_IEEE_T_DEF                  (*(volatile uint32_t*)(&_MBAR[0x9A58]))
+#define MCF_FEC1_IEEE_T_LCOL                 (*(volatile uint32_t*)(&_MBAR[0x9A5C]))
+#define MCF_FEC1_IEEE_T_EXCOL                (*(volatile uint32_t*)(&_MBAR[0x9A60]))
+#define MCF_FEC1_IEEE_T_MACERR               (*(volatile uint32_t*)(&_MBAR[0x9A64]))
+#define MCF_FEC1_IEEE_T_CSERR                (*(volatile uint32_t*)(&_MBAR[0x9A68]))
+#define MCF_FEC1_IEEE_T_SQE                  (*(volatile uint32_t*)(&_MBAR[0x9A6C]))
+#define MCF_FEC1_IEEE_T_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x9A70]))
+#define MCF_FEC1_IEEE_T_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x9A74]))
+#define MCF_FEC1_RMON_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9A80]))
+#define MCF_FEC1_RMON_R_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9A84]))
+#define MCF_FEC1_RMON_R_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A88]))
+#define MCF_FEC1_RMON_R_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A8C]))
+#define MCF_FEC1_RMON_R_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9A90]))
+#define MCF_FEC1_RMON_R_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9A94]))
+#define MCF_FEC1_RMON_R_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9A98]))
+#define MCF_FEC1_RMON_R_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x9A9C]))
+#define MCF_FEC1_RMON_R_JAB                  (*(volatile uint32_t*)(&_MBAR[0x9AA0]))
+#define MCF_FEC1_RMON_R_RESVD_0              (*(volatile uint32_t*)(&_MBAR[0x9AA4]))
+#define MCF_FEC1_RMON_R_P64                  (*(volatile uint32_t*)(&_MBAR[0x9AA8]))
+#define MCF_FEC1_RMON_R_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x9AAC]))
+#define MCF_FEC1_RMON_R_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x9AB0]))
+#define MCF_FEC1_RMON_R_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x9AB4]))
+#define MCF_FEC1_RMON_R_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x9AB8]))
+#define MCF_FEC1_RMON_R_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x9ABC]))
+#define MCF_FEC1_RMON_R_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x9AC0]))
+#define MCF_FEC1_RMON_R_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x9AC4]))
+#define MCF_FEC1_IEEE_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9AC8]))
+#define MCF_FEC1_IEEE_R_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x9ACC]))
+#define MCF_FEC1_IEEE_R_CRC                  (*(volatile uint32_t*)(&_MBAR[0x9AD0]))
+#define MCF_FEC1_IEEE_R_ALIGN                (*(volatile uint32_t*)(&_MBAR[0x9AD4]))
+#define MCF_FEC1_IEEE_R_MACERR               (*(volatile uint32_t*)(&_MBAR[0x9AD8]))
+#define MCF_FEC1_IEEE_R_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x9ADC]))
+#define MCF_FEC1_IEEE_R_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x9AE0]))
+
+#define MCF_FEC_EIR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9004 + ((x)*0x800)]))
+#define MCF_FEC_EIMR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9008 + ((x)*0x800)]))
+#define MCF_FEC_ECR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9024 + ((x)*0x800)]))
+#define MCF_FEC_MMFR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9040 + ((x)*0x800)]))
+#define MCF_FEC_MSCR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9044 + ((x)*0x800)]))
+#define MCF_FEC_MIBC(x)                      (*(volatile uint32_t*)(&_MBAR[0x9064 + ((x)*0x800)]))
+#define MCF_FEC_RCR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9084 + ((x)*0x800)]))
+#define MCF_FEC_RHR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9088 + ((x)*0x800)]))
+#define MCF_FEC_TCR(x)                       (*(volatile uint32_t*)(&_MBAR[0x90C4 + ((x)*0x800)]))
+#define MCF_FEC_PALR(x)                      (*(volatile uint32_t*)(&_MBAR[0x90E4 + ((x)*0x800)]))
+#define MCF_FEC_PAHR(x)                      (*(volatile uint32_t*)(&_MBAR[0x90E8 + ((x)*0x800)]))
+#define MCF_FEC_OPD(x)                       (*(volatile uint32_t*)(&_MBAR[0x90EC + ((x)*0x800)]))
+#define MCF_FEC_IAUR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9118 + ((x)*0x800)]))
+#define MCF_FEC_IALR(x)                      (*(volatile uint32_t*)(&_MBAR[0x911C + ((x)*0x800)]))
+#define MCF_FEC_GAUR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9120 + ((x)*0x800)]))
+#define MCF_FEC_GALR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9124 + ((x)*0x800)]))
+#define MCF_FEC_FECTFWR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9144 + ((x)*0x800)]))
+#define MCF_FEC_FECRFDR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9184 + ((x)*0x800)]))
+#define MCF_FEC_FECRFSR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9188 + ((x)*0x800)]))
+#define MCF_FEC_FECRFCR(x)                   (*(volatile uint32_t*)(&_MBAR[0x918C + ((x)*0x800)]))
+#define MCF_FEC_FECRLRFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x9190 + ((x)*0x800)]))
+#define MCF_FEC_FECRLWFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x9194 + ((x)*0x800)]))
+#define MCF_FEC_FECRFAR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9198 + ((x)*0x800)]))
+#define MCF_FEC_FECRFRP(x)                   (*(volatile uint32_t*)(&_MBAR[0x919C + ((x)*0x800)]))
+#define MCF_FEC_FECRFWP(x)                   (*(volatile uint32_t*)(&_MBAR[0x91A0 + ((x)*0x800)]))
+#define MCF_FEC_FECTFDR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91A4 + ((x)*0x800)]))
+#define MCF_FEC_FECTFSR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91A8 + ((x)*0x800)]))
+#define MCF_FEC_FECTFCR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91AC + ((x)*0x800)]))
+#define MCF_FEC_FECTLRFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x91B0 + ((x)*0x800)]))
+#define MCF_FEC_FECTLWFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x91B4 + ((x)*0x800)]))
+#define MCF_FEC_FECTFAR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91B8 + ((x)*0x800)]))
+#define MCF_FEC_FECTFRP(x)                   (*(volatile uint32_t*)(&_MBAR[0x91BC + ((x)*0x800)]))
+#define MCF_FEC_FECTFWP(x)                   (*(volatile uint32_t*)(&_MBAR[0x91C0 + ((x)*0x800)]))
+#define MCF_FEC_FECFRST(x)                   (*(volatile uint32_t*)(&_MBAR[0x91C4 + ((x)*0x800)]))
+#define MCF_FEC_FECCTCWR(x)                  (*(volatile uint32_t*)(&_MBAR[0x91C8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x9200 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_PACKETS(x)            (*(volatile uint32_t*)(&_MBAR[0x9204 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_BC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x9208 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_MC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x920C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_CRC_ALIGN(x)          (*(volatile uint32_t*)(&_MBAR[0x9210 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_UNDERSIZE(x)          (*(volatile uint32_t*)(&_MBAR[0x9214 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_OVERSIZE(x)           (*(volatile uint32_t*)(&_MBAR[0x9218 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_FRAG(x)               (*(volatile uint32_t*)(&_MBAR[0x921C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_JAB(x)                (*(volatile uint32_t*)(&_MBAR[0x9220 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_COL(x)                (*(volatile uint32_t*)(&_MBAR[0x9224 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P64(x)                (*(volatile uint32_t*)(&_MBAR[0x9228 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P65TO127(x)           (*(volatile uint32_t*)(&_MBAR[0x922C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P128TO255(x)          (*(volatile uint32_t*)(&_MBAR[0x9230 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P256TO511(x)          (*(volatile uint32_t*)(&_MBAR[0x9234 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P512TO1023(x)         (*(volatile uint32_t*)(&_MBAR[0x9238 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P1024TO2047(x)        (*(volatile uint32_t*)(&_MBAR[0x923C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P_GTE2048(x)          (*(volatile uint32_t*)(&_MBAR[0x9240 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_OCTETS(x)             (*(volatile uint32_t*)(&_MBAR[0x9244 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x9248 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_FRAME_OK(x)           (*(volatile uint32_t*)(&_MBAR[0x924C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_1COL(x)               (*(volatile uint32_t*)(&_MBAR[0x9250 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_MCOL(x)               (*(volatile uint32_t*)(&_MBAR[0x9254 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_DEF(x)                (*(volatile uint32_t*)(&_MBAR[0x9258 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_LCOL(x)               (*(volatile uint32_t*)(&_MBAR[0x925C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_EXCOL(x)              (*(volatile uint32_t*)(&_MBAR[0x9260 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_MACERR(x)             (*(volatile uint32_t*)(&_MBAR[0x9264 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_CSERR(x)              (*(volatile uint32_t*)(&_MBAR[0x9268 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_SQE(x)                (*(volatile uint32_t*)(&_MBAR[0x926C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_FDXFC(x)              (*(volatile uint32_t*)(&_MBAR[0x9270 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_OCTETS_OK(x)          (*(volatile uint32_t*)(&_MBAR[0x9274 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x9280 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_PACKETS(x)            (*(volatile uint32_t*)(&_MBAR[0x9284 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_BC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x9288 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_MC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x928C + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_CRC_ALIGN(x)          (*(volatile uint32_t*)(&_MBAR[0x9290 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_UNDERSIZE(x)          (*(volatile uint32_t*)(&_MBAR[0x9294 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_OVERSIZE(x)           (*(volatile uint32_t*)(&_MBAR[0x9298 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_FRAG(x)               (*(volatile uint32_t*)(&_MBAR[0x929C + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_JAB(x)                (*(volatile uint32_t*)(&_MBAR[0x92A0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_RESVD_0(x)            (*(volatile uint32_t*)(&_MBAR[0x92A4 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P64(x)                (*(volatile uint32_t*)(&_MBAR[0x92A8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P65TO127(x)           (*(volatile uint32_t*)(&_MBAR[0x92AC + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P128TO255(x)          (*(volatile uint32_t*)(&_MBAR[0x92B0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P256TO511(x)          (*(volatile uint32_t*)(&_MBAR[0x92B4 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P512TO1023(x)         (*(volatile uint32_t*)(&_MBAR[0x92B8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P1024TO2047(x)        (*(volatile uint32_t*)(&_MBAR[0x92BC + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P_GTE2048(x)          (*(volatile uint32_t*)(&_MBAR[0x92C0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_OCTETS(x)             (*(volatile uint32_t*)(&_MBAR[0x92C4 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x92C8 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_FRAME_OK(x)           (*(volatile uint32_t*)(&_MBAR[0x92CC + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_CRC(x)                (*(volatile uint32_t*)(&_MBAR[0x92D0 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_ALIGN(x)              (*(volatile uint32_t*)(&_MBAR[0x92D4 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_MACERR(x)             (*(volatile uint32_t*)(&_MBAR[0x92D8 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_FDXFC(x)              (*(volatile uint32_t*)(&_MBAR[0x92DC + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_OCTETS_OK(x)          (*(volatile uint32_t*)(&_MBAR[0x92E0 + ((x)*0x800)]))
+
+
+/* Bit definitions and macros for MCF_FEC_EIR */
+#define MCF_FEC_EIR_RFERR                    (0x20000)
+#define MCF_FEC_EIR_XFERR                    (0x40000)
+#define MCF_FEC_EIR_XFUN                     (0x80000)
+#define MCF_FEC_EIR_RL                       (0x100000)
+#define MCF_FEC_EIR_LC                       (0x200000)
+#define MCF_FEC_EIR_MII                      (0x800000)
+#define MCF_FEC_EIR_TXF                      (0x8000000)
+#define MCF_FEC_EIR_GRA                      (0x10000000)
+#define MCF_FEC_EIR_BABT                     (0x20000000)
+#define MCF_FEC_EIR_BABR                     (0x40000000)
+#define MCF_FEC_EIR_HBERR                    (0x80000000)
+#define MCF_FEC_EIR_CLEAR_ALL                (0xFFFFFFFF)
+
+/* Bit definitions and macros for MCF_FEC_EIMR */
+#define MCF_FEC_EIMR_RFERR                   (0x20000)
+#define MCF_FEC_EIMR_XFERR                   (0x40000)
+#define MCF_FEC_EIMR_XFUN                    (0x80000)
+#define MCF_FEC_EIMR_RL                      (0x100000)
+#define MCF_FEC_EIMR_LC                      (0x200000)
+#define MCF_FEC_EIMR_MII                     (0x800000)
+#define MCF_FEC_EIMR_TXF                     (0x8000000)
+#define MCF_FEC_EIMR_GRA                     (0x10000000)
+#define MCF_FEC_EIMR_BABT                    (0x20000000)
+#define MCF_FEC_EIMR_BABR                    (0x40000000)
+#define MCF_FEC_EIMR_HBERR                   (0x80000000)
+#define MCF_FEC_EIMR_MASK_ALL                (0)
+#define MCF_FEC_EIMR_UNMASK_ALL              (0xFFFFFFFF)
+
+/* Bit definitions and macros for MCF_FEC_ECR */
+#define MCF_FEC_ECR_RESET                    (0x1)
+#define MCF_FEC_ECR_ETHER_EN                 (0x2)
+
+/* Bit definitions and macros for MCF_FEC_MMFR */
+#define MCF_FEC_MMFR_DATA(x)                 (((x)&0xFFFF)<<0)
+#define MCF_FEC_MMFR_TA(x)                   (((x)&0x3)<<0x10)
+#define MCF_FEC_MMFR_TA_10                   (0x20000)
+#define MCF_FEC_MMFR_RA(x)                   (((x)&0x1F)<<0x12)
+#define MCF_FEC_MMFR_PA(x)                   (((x)&0x1F)<<0x17)
+#define MCF_FEC_MMFR_OP(x)                   (((x)&0x3)<<0x1C)
+#define MCF_FEC_MMFR_OP_READ                 (0x20000000)
+#define MCF_FEC_MMFR_OP_WRITE                (0x10000000)
+#define MCF_FEC_MMFR_ST(x)                   (((x)&0x3)<<0x1E)
+#define MCF_FEC_MMFR_ST_01                   (0x40000000)
+
+/* Bit definitions and macros for MCF_FEC_MSCR */
+#define MCF_FEC_MSCR_MII_SPEED(x)            (((x)&0x3F)<<0x1)
+#define MCF_FEC_MSCR_DIS_PREAMBLE            (0x80)
+#define MCF_FEC_MSCR_MII_SPEED_133           (0x1B<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_120           (0x18<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_66            (0xE<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_60            (0xC<<0x1)
+
+/* Bit definitions and macros for MCF_FEC_MIBC */
+#define MCF_FEC_MIBC_MIB_IDLE                (0x40000000)
+#define MCF_FEC_MIBC_MIB_DISABLE             (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_RCR */
+#define MCF_FEC_RCR_LOOP                     (0x1)
+#define MCF_FEC_RCR_DRT                      (0x2)
+#define MCF_FEC_RCR_MII_MODE                 (0x4)
+#define MCF_FEC_RCR_PROM                     (0x8)
+#define MCF_FEC_RCR_BC_REJ                   (0x10)
+#define MCF_FEC_RCR_FCE                      (0x20)
+#define MCF_FEC_RCR_MAX_FL(x)                (((x)&0x7FF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_RHR */
+#define MCF_FEC_RHR_HASH(x)                  (((x)&0x3F)<<0x18)
+#define MCF_FEC_RHR_MULTCAST                 (0x40000000)
+#define MCF_FEC_RHR_FCE                      (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_TCR */
+#define MCF_FEC_TCR_GTS                      (0x1)
+#define MCF_FEC_TCR_HBC                      (0x2)
+#define MCF_FEC_TCR_FDEN                     (0x4)
+#define MCF_FEC_TCR_TFC_PAUSE                (0x8)
+#define MCF_FEC_TCR_RFC_PAUSE                (0x10)
+
+/* Bit definitions and macros for MCF_FEC_PALR */
+#define MCF_FEC_PALR_PADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_PAHR */
+#define MCF_FEC_PAHR_TYPE(x)                 (((x)&0xFFFF)<<0)
+#define MCF_FEC_PAHR_PADDR2(x)               (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_OPD */
+#define MCF_FEC_OPD_PAUSE_DUR(x)             (((x)&0xFFFF)<<0)
+#define MCF_FEC_OPD_OPCODE(x)                (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_IAUR */
+#define MCF_FEC_IAUR_IADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IALR */
+#define MCF_FEC_IALR_IADDR2(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_GAUR */
+#define MCF_FEC_GAUR_GADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_GALR */
+#define MCF_FEC_GALR_GADDR2(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFWR */
+#define MCF_FEC_FECTFWR_X_WMRK(x)            (((x)&0xF)<<0)
+#define MCF_FEC_FECTFWR_X_WMRK_64            (0)
+#define MCF_FEC_FECTFWR_X_WMRK_128           (0x1)
+#define MCF_FEC_FECTFWR_X_WMRK_192           (0x2)
+#define MCF_FEC_FECTFWR_X_WMRK_256           (0x3)
+#define MCF_FEC_FECTFWR_X_WMRK_320           (0x4)
+#define MCF_FEC_FECTFWR_X_WMRK_384           (0x5)
+#define MCF_FEC_FECTFWR_X_WMRK_448           (0x6)
+#define MCF_FEC_FECTFWR_X_WMRK_512           (0x7)
+#define MCF_FEC_FECTFWR_X_WMRK_576           (0x8)
+#define MCF_FEC_FECTFWR_X_WMRK_640           (0x9)
+#define MCF_FEC_FECTFWR_X_WMRK_704           (0xA)
+#define MCF_FEC_FECTFWR_X_WMRK_768           (0xB)
+#define MCF_FEC_FECTFWR_X_WMRK_832           (0xC)
+#define MCF_FEC_FECTFWR_X_WMRK_896           (0xD)
+#define MCF_FEC_FECTFWR_X_WMRK_960           (0xE)
+#define MCF_FEC_FECTFWR_X_WMRK_1024          (0xF)
+
+/* Bit definitions and macros for MCF_FEC_FECRFDR */
+#define MCF_FEC_FECRFDR_FIFO_DATA(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFSR */
+#define MCF_FEC_FECRFSR_EMT                  (0x10000)
+#define MCF_FEC_FECRFSR_ALARM                (0x20000)
+#define MCF_FEC_FECRFSR_FU                   (0x40000)
+#define MCF_FEC_FECRFSR_FRMRDY               (0x80000)
+#define MCF_FEC_FECRFSR_OF                   (0x100000)
+#define MCF_FEC_FECRFSR_UF                   (0x200000)
+#define MCF_FEC_FECRFSR_RXW                  (0x400000)
+#define MCF_FEC_FECRFSR_FAE                  (0x800000)
+#define MCF_FEC_FECRFSR_FRM(x)               (((x)&0xF)<<0x18)
+#define MCF_FEC_FECRFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_FECRFCR */
+#define MCF_FEC_FECRFCR_COUNTER(x)           (((x)&0xFFFF)<<0)
+#define MCF_FEC_FECRFCR_OF_MSK               (0x80000)
+#define MCF_FEC_FECRFCR_UF_MSK               (0x100000)
+#define MCF_FEC_FECRFCR_RXW_MSK              (0x200000)
+#define MCF_FEC_FECRFCR_FAE_MSK              (0x400000)
+#define MCF_FEC_FECRFCR_IP_MSK               (0x800000)
+#define MCF_FEC_FECRFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_FEC_FECRFCR_FRMEN                (0x8000000)
+#define MCF_FEC_FECRFCR_TIMER                (0x10000000)
+
+/* Bit definitions and macros for MCF_FEC_FECRLRFP */
+#define MCF_FEC_FECRLRFP_LRFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRLWFP */
+#define MCF_FEC_FECRLWFP_LWFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFAR */
+#define MCF_FEC_FECRFAR_ALARM(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFRP */
+#define MCF_FEC_FECRFRP_READ(x)              (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFWP */
+#define MCF_FEC_FECRFWP_WRITE(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFDR */
+#define MCF_FEC_FECTFDR_FIFO_DATA(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFSR */
+#define MCF_FEC_FECTFSR_EMT                  (0x10000)
+#define MCF_FEC_FECTFSR_ALARM                (0x20000)
+#define MCF_FEC_FECTFSR_FU                   (0x40000)
+#define MCF_FEC_FECTFSR_FRMRDY               (0x80000)
+#define MCF_FEC_FECTFSR_OF                   (0x100000)
+#define MCF_FEC_FECTFSR_UF                   (0x200000)
+#define MCF_FEC_FECTFSR_FAE                  (0x800000)
+#define MCF_FEC_FECTFSR_FRM(x)               (((x)&0xF)<<0x18)
+#define MCF_FEC_FECTFSR_TXW                  (0x40000000)
+#define MCF_FEC_FECTFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_FECTFCR */
+#define MCF_FEC_FECTFCR_RESERVED             (0x200000)
+#define MCF_FEC_FECTFCR_COUNTER(x)           (((x)&0xFFFF)<<0|0x200000)
+#define MCF_FEC_FECTFCR_TXW_MASK             (0x240000)
+#define MCF_FEC_FECTFCR_OF_MSK               (0x280000)
+#define MCF_FEC_FECTFCR_UF_MSK               (0x300000)
+#define MCF_FEC_FECTFCR_FAE_MSK              (0x600000)
+#define MCF_FEC_FECTFCR_IP_MSK               (0xA00000)
+#define MCF_FEC_FECTFCR_GR(x)                (((x)&0x7)<<0x18|0x200000)
+#define MCF_FEC_FECTFCR_FRMEN                (0x8200000)
+#define MCF_FEC_FECTFCR_TIMER                (0x10200000)
+#define MCF_FEC_FECTFCR_WFR                  (0x20200000)
+#define MCF_FEC_FECTFCR_WCTL                 (0x40200000)
+
+/* Bit definitions and macros for MCF_FEC_FECTLRFP */
+#define MCF_FEC_FECTLRFP_LRFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTLWFP */
+#define MCF_FEC_FECTLWFP_LWFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFAR */
+#define MCF_FEC_FECTFAR_ALARM(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFRP */
+#define MCF_FEC_FECTFRP_READ(x)              (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFWP */
+#define MCF_FEC_FECTFWP_WRITE(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECFRST */
+#define MCF_FEC_FECFRST_RST_CTL              (0x1000000)
+#define MCF_FEC_FECFRST_SW_RST               (0x2000000)
+
+/* Bit definitions and macros for MCF_FEC_FECCTCWR */
+#define MCF_FEC_FECCTCWR_TFCW                (0x1000000)
+#define MCF_FEC_FECCTCWR_CRC                 (0x2000000)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */
+#define MCF_FEC_RMON_T_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */
+#define MCF_FEC_RMON_T_PACKETS_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */
+#define MCF_FEC_RMON_T_BC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */
+#define MCF_FEC_RMON_T_MC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */
+#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */
+#define MCF_FEC_RMON_T_UNDERSIZE_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */
+#define MCF_FEC_RMON_T_OVERSIZE_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */
+#define MCF_FEC_RMON_T_FRAG_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */
+#define MCF_FEC_RMON_T_JAB_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_COL */
+#define MCF_FEC_RMON_T_COL_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */
+#define MCF_FEC_RMON_T_P64_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */
+#define MCF_FEC_RMON_T_P65TO127_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */
+#define MCF_FEC_RMON_T_P128TO255_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */
+#define MCF_FEC_RMON_T_P256TO511_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */
+#define MCF_FEC_RMON_T_P512TO1023_Value(x)   (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */
+#define MCF_FEC_RMON_T_P1024TO2047_Value(x)  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */
+#define MCF_FEC_RMON_T_P_GTE2048_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */
+#define MCF_FEC_RMON_T_OCTETS_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */
+#define MCF_FEC_IEEE_T_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */
+#define MCF_FEC_IEEE_T_FRAME_OK_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */
+#define MCF_FEC_IEEE_T_1COL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */
+#define MCF_FEC_IEEE_T_MCOL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */
+#define MCF_FEC_IEEE_T_DEF_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */
+#define MCF_FEC_IEEE_T_LCOL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */
+#define MCF_FEC_IEEE_T_EXCOL_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */
+#define MCF_FEC_IEEE_T_MACERR_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */
+#define MCF_FEC_IEEE_T_CSERR_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */
+#define MCF_FEC_IEEE_T_SQE_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */
+#define MCF_FEC_IEEE_T_FDXFC_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */
+#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_DROP */
+#define MCF_FEC_RMON_R_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */
+#define MCF_FEC_RMON_R_PACKETS_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */
+#define MCF_FEC_RMON_R_BC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */
+#define MCF_FEC_RMON_R_MC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */
+#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */
+#define MCF_FEC_RMON_R_UNDERSIZE_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */
+#define MCF_FEC_RMON_R_OVERSIZE_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */
+#define MCF_FEC_RMON_R_FRAG_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */
+#define MCF_FEC_RMON_R_JAB_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */
+#define MCF_FEC_RMON_R_RESVD_0_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */
+#define MCF_FEC_RMON_R_P64_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */
+#define MCF_FEC_RMON_R_P65TO127_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */
+#define MCF_FEC_RMON_R_P128TO255_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */
+#define MCF_FEC_RMON_R_P256TO511_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */
+#define MCF_FEC_RMON_R_P512TO1023_Value(x)   (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */
+#define MCF_FEC_RMON_R_P1024TO2047_Value(x)  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */
+#define MCF_FEC_RMON_R_P_GTE2048_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */
+#define MCF_FEC_RMON_R_OCTETS_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */
+#define MCF_FEC_IEEE_R_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */
+#define MCF_FEC_IEEE_R_FRAME_OK_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */
+#define MCF_FEC_IEEE_R_CRC_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */
+#define MCF_FEC_IEEE_R_ALIGN_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */
+#define MCF_FEC_IEEE_R_MACERR_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */
+#define MCF_FEC_IEEE_R_FDXFC_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */
+#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+
+#endif /* __MCF5475_FEC_H__ */

tos/fpga_test/include/MCF5475_GPIO.h

@@ -0,0 +1,543 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_GPIO_H__
+#define __MCF5475_GPIO_H__
+
+
+/*********************************************************************
+*
+* General Purpose I/O (GPIO)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPIO_PODR_FBCTL                  (*(volatile uint8_t *)(&_MBAR[0xA00]))
+#define MCF_GPIO_PDDR_FBCTL                  (*(volatile uint8_t *)(&_MBAR[0xA10]))
+#define MCF_GPIO_PPDSDR_FBCTL                (*(volatile uint8_t *)(&_MBAR[0xA20]))
+#define MCF_GPIO_PCLRR_FBCTL                 (*(volatile uint8_t *)(&_MBAR[0xA30]))
+
+#define MCF_GPIO_PODR_FBCS                   (*(volatile uint8_t *)(&_MBAR[0xA01]))
+#define MCF_GPIO_PDDR_FBCS                   (*(volatile uint8_t *)(&_MBAR[0xA11]))
+#define MCF_GPIO_PPDSDR_FBCS                 (*(volatile uint8_t *)(&_MBAR[0xA21]))
+#define MCF_GPIO_PCLRR_FBCS                  (*(volatile uint8_t *)(&_MBAR[0xA31]))
+
+#define MCF_GPIO_PODR_DMA                    (*(volatile uint8_t *)(&_MBAR[0xA02]))
+#define MCF_GPIO_PDDR_DMA                    (*(volatile uint8_t *)(&_MBAR[0xA12]))
+#define MCF_GPIO_PPDSDR_DMA                  (*(volatile uint8_t *)(&_MBAR[0xA22]))
+#define MCF_GPIO_PCLRR_DMA                   (*(volatile uint8_t *)(&_MBAR[0xA32]))
+
+#define MCF_GPIO_PODR_FEC0H                  (*(volatile uint8_t *)(&_MBAR[0xA04]))
+#define MCF_GPIO_PDDR_FEC0H                  (*(volatile uint8_t *)(&_MBAR[0xA14]))
+#define MCF_GPIO_PPDSDR_FEC0H                (*(volatile uint8_t *)(&_MBAR[0xA24]))
+#define MCF_GPIO_PCLRR_FEC0H                 (*(volatile uint8_t *)(&_MBAR[0xA34]))
+
+#define MCF_GPIO_PODR_FEC0L                  (*(volatile uint8_t *)(&_MBAR[0xA05]))
+#define MCF_GPIO_PDDR_FEC0L                  (*(volatile uint8_t *)(&_MBAR[0xA15]))
+#define MCF_GPIO_PPDSDR_FEC0L                (*(volatile uint8_t *)(&_MBAR[0xA25]))
+#define MCF_GPIO_PCLRR_FEC0L                 (*(volatile uint8_t *)(&_MBAR[0xA35]))
+
+#define MCF_GPIO_PODR_FEC1H                  (*(volatile uint8_t *)(&_MBAR[0xA06]))
+#define MCF_GPIO_PDDR_FEC1H                  (*(volatile uint8_t *)(&_MBAR[0xA16]))
+#define MCF_GPIO_PPDSDR_FEC1H                (*(volatile uint8_t *)(&_MBAR[0xA26]))
+#define MCF_GPIO_PCLRR_FEC1H                 (*(volatile uint8_t *)(&_MBAR[0xA36]))
+
+#define MCF_GPIO_PODR_FEC1L                  (*(volatile uint8_t *)(&_MBAR[0xA07]))
+#define MCF_GPIO_PDDR_FEC1L                  (*(volatile uint8_t *)(&_MBAR[0xA17]))
+#define MCF_GPIO_PPDSDR_FEC1L                (*(volatile uint8_t *)(&_MBAR[0xA27]))
+#define MCF_GPIO_PCLRR_FEC1L                 (*(volatile uint8_t *)(&_MBAR[0xA37]))
+
+#define MCF_GPIO_PODR_FECI2C                 (*(volatile uint8_t *)(&_MBAR[0xA08]))
+#define MCF_GPIO_PDDR_FECI2C                 (*(volatile uint8_t *)(&_MBAR[0xA18]))
+#define MCF_GPIO_PPDSDR_FECI2C               (*(volatile uint8_t *)(&_MBAR[0xA28]))
+#define MCF_GPIO_PCLRR_FECI2C                (*(volatile uint8_t *)(&_MBAR[0xA38]))
+
+#define MCF_GPIO_PODR_PCIBG                  (*(volatile uint8_t *)(&_MBAR[0xA09]))
+#define MCF_GPIO_PDDR_PCIBG                  (*(volatile uint8_t *)(&_MBAR[0xA19]))
+#define MCF_GPIO_PPDSDR_PCIBG                (*(volatile uint8_t *)(&_MBAR[0xA29]))
+#define MCF_GPIO_PCLRR_PCIBG                 (*(volatile uint8_t *)(&_MBAR[0xA39]))
+
+#define MCF_GPIO_PODR_PCIBR                  (*(volatile uint8_t *)(&_MBAR[0xA0A]))
+#define MCF_GPIO_PDDR_PCIBR                  (*(volatile uint8_t *)(&_MBAR[0xA1A]))
+#define MCF_GPIO_PPDSDR_PCIBR                (*(volatile uint8_t *)(&_MBAR[0xA2A]))
+#define MCF_GPIO_PCLRR_PCIBR                 (*(volatile uint8_t *)(&_MBAR[0xA3A]))
+
+#define MCF_GPIO2_PODR_PSC3PSC               (*(volatile uint8_t *)(&_MBAR[0xA0C]))
+#define MCF_GPIO2_PDDR_PSC3PSC               (*(volatile uint8_t *)(&_MBAR[0xA1C]))
+#define MCF_GPIO2_PPDSDR_PSC3PSC             (*(volatile uint8_t *)(&_MBAR[0xA2C]))
+#define MCF_GPIO2_PCLRR_PSC3PSC              (*(volatile uint8_t *)(&_MBAR[0xA3C]))
+
+#define MCF_GPIO0_PODR_PSC1PSC               (*(volatile uint8_t *)(&_MBAR[0xA0D]))
+#define MCF_GPIO0_PDDR_PSC1PSC               (*(volatile uint8_t *)(&_MBAR[0xA1D]))
+#define MCF_GPIO0_PPDSDR_PSC1PSC             (*(volatile uint8_t *)(&_MBAR[0xA2D]))
+#define MCF_GPIO0_PCLRR_PSC1PSC              (*(volatile uint8_t *)(&_MBAR[0xA3D]))
+
+#define MCF_GPIO_PODR_DSPI                   (*(volatile uint8_t *)(&_MBAR[0xA0E]))
+#define MCF_GPIO_PDDR_DSPI                   (*(volatile uint8_t *)(&_MBAR[0xA1E]))
+#define MCF_GPIO_PPDSDR_DSPI                 (*(volatile uint8_t *)(&_MBAR[0xA2E]))
+#define MCF_GPIO_PCLRR_DSPI                  (*(volatile uint8_t *)(&_MBAR[0xA3E]))
+
+
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0      (0x1)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1      (0x2)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2      (0x4)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3      (0x8)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4      (0x10)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5      (0x20)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6      (0x40)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0      (0x1)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1      (0x2)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2      (0x4)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3      (0x8)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4      (0x10)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5      (0x20)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6      (0x40)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0  (0x1)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1  (0x2)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2  (0x4)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3  (0x8)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4  (0x10)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5  (0x20)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6  (0x40)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0    (0x1)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1    (0x2)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2    (0x4)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3    (0x8)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4    (0x10)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5    (0x20)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6    (0x40)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS1        (0x2)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS2        (0x4)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS3        (0x8)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS4        (0x10)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS5        (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1        (0x2)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2        (0x4)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3        (0x8)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4        (0x10)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5        (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1    (0x2)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2    (0x4)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3    (0x8)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4    (0x10)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5    (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1      (0x2)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2      (0x4)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3      (0x8)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4      (0x10)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5      (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_DMA */
+#define MCF_GPIO_PODR_DMA_PODR_DMA0          (0x1)
+#define MCF_GPIO_PODR_DMA_PODR_DMA1          (0x2)
+#define MCF_GPIO_PODR_DMA_PODR_DMA2          (0x4)
+#define MCF_GPIO_PODR_DMA_PODR_DMA3          (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA0          (0x1)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA1          (0x2)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA2          (0x4)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA3          (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0      (0x1)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1      (0x2)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2      (0x4)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3      (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0        (0x1)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1        (0x2)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2        (0x4)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3        (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0      (0x1)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1      (0x2)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2      (0x4)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3      (0x8)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4      (0x10)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5      (0x20)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6      (0x40)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0      (0x1)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1      (0x2)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2      (0x4)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3      (0x8)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4      (0x10)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5      (0x20)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6      (0x40)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0    (0x1)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1    (0x2)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2    (0x4)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3    (0x8)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4    (0x10)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5    (0x20)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6    (0x40)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0      (0x1)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1      (0x2)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2      (0x4)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3      (0x8)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4      (0x10)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5      (0x20)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6      (0x40)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0      (0x1)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1      (0x2)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2      (0x4)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3      (0x8)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4      (0x10)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5      (0x20)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6      (0x40)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0    (0x1)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1    (0x2)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2    (0x4)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3    (0x8)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4    (0x10)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5    (0x20)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6    (0x40)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0      (0x1)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1      (0x2)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2      (0x4)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3      (0x8)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4      (0x10)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5      (0x20)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6      (0x40)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0      (0x1)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1      (0x2)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2      (0x4)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3      (0x8)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4      (0x10)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5      (0x20)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6      (0x40)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0    (0x1)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1    (0x2)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2    (0x4)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3    (0x8)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4    (0x10)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5    (0x20)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6    (0x40)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0      (0x1)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1      (0x2)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2      (0x4)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3      (0x8)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4      (0x10)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5      (0x20)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6      (0x40)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0      (0x1)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1      (0x2)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2      (0x4)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3      (0x8)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4      (0x10)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5      (0x20)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6      (0x40)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0    (0x1)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1    (0x2)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2    (0x4)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3    (0x8)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4    (0x10)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5    (0x20)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6    (0x40)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0    (0x1)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1    (0x2)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2    (0x4)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3    (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0    (0x1)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1    (0x2)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2    (0x4)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3    (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0  (0x1)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1  (0x2)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2  (0x4)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3  (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0      (0x1)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1      (0x2)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2      (0x4)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3      (0x8)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0      (0x1)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1      (0x2)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2      (0x4)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3      (0x8)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0  (0x1)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1  (0x2)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2  (0x4)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3  (0x8)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4  (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0    (0x1)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1    (0x2)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2    (0x4)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3    (0x8)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4    (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0      (0x1)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1      (0x2)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2      (0x4)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3      (0x8)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0      (0x1)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1      (0x2)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2      (0x4)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3      (0x8)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0  (0x1)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1  (0x2)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2  (0x4)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3  (0x8)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4  (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0    (0x1)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1    (0x2)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2    (0x4)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3    (0x8)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4    (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI0        (0x1)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI1        (0x2)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI2        (0x4)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI3        (0x8)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI4        (0x10)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI5        (0x20)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI6        (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0        (0x1)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1        (0x2)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2        (0x4)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3        (0x8)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4        (0x10)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5        (0x20)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6        (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0    (0x1)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1    (0x2)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2    (0x4)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3    (0x8)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4    (0x10)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5    (0x20)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6    (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0      (0x1)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1      (0x2)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2      (0x4)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3      (0x8)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4      (0x10)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5      (0x20)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6      (0x40)
+
+
+#endif /* __MCF5475_GPIO_H__ */

tos/fpga_test/include/MCF5475_GPT.h

@@ -0,0 +1,100 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_GPT_H__
+#define __MCF5475_GPT_H__
+
+
+/*********************************************************************
+*
+* General Purpose Timers (GPT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPT0_GMS                         (*(volatile uint32_t*)(&_MBAR[0x800]))
+#define MCF_GPT0_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x804]))
+#define MCF_GPT0_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x808]))
+#define MCF_GPT0_GSR                         (*(volatile uint32_t*)(&_MBAR[0x80C]))
+
+#define MCF_GPT1_GMS                         (*(volatile uint32_t*)(&_MBAR[0x810]))
+#define MCF_GPT1_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x814]))
+#define MCF_GPT1_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x818]))
+#define MCF_GPT1_GSR                         (*(volatile uint32_t*)(&_MBAR[0x81C]))
+
+#define MCF_GPT2_GMS                         (*(volatile uint32_t*)(&_MBAR[0x820]))
+#define MCF_GPT2_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x824]))
+#define MCF_GPT2_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x828]))
+#define MCF_GPT2_GSR                         (*(volatile uint32_t*)(&_MBAR[0x82C]))
+
+#define MCF_GPT3_GMS                         (*(volatile uint32_t*)(&_MBAR[0x830]))
+#define MCF_GPT3_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x834]))
+#define MCF_GPT3_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x838]))
+#define MCF_GPT3_GSR                         (*(volatile uint32_t*)(&_MBAR[0x83C]))
+
+#define MCF_GPT_GMS(x)                       (*(volatile uint32_t*)(&_MBAR[0x800 + ((x)*0x10)]))
+#define MCF_GPT_GCIR(x)                      (*(volatile uint32_t*)(&_MBAR[0x804 + ((x)*0x10)]))
+#define MCF_GPT_GPWM(x)                      (*(volatile uint32_t*)(&_MBAR[0x808 + ((x)*0x10)]))
+#define MCF_GPT_GSR(x)                       (*(volatile uint32_t*)(&_MBAR[0x80C + ((x)*0x10)]))
+
+
+/* Bit definitions and macros for MCF_GPT_GMS */
+#define MCF_GPT_GMS_TMS(x)                   (((x)&0x7)<<0)
+#define MCF_GPT_GMS_TMS_DISABLE              (0)
+#define MCF_GPT_GMS_TMS_INCAPT               (0x1)
+#define MCF_GPT_GMS_TMS_OUTCAPT              (0x2)
+#define MCF_GPT_GMS_TMS_PWM                  (0x3)
+#define MCF_GPT_GMS_TMS_GPIO                 (0x4)
+#define MCF_GPT_GMS_GPIO(x)                  (((x)&0x3)<<0x4)
+#define MCF_GPT_GMS_GPIO_INPUT               (0)
+#define MCF_GPT_GMS_GPIO_OUTLO               (0x20)
+#define MCF_GPT_GMS_GPIO_OUTHI               (0x30)
+#define MCF_GPT_GMS_IEN                      (0x100)
+#define MCF_GPT_GMS_OD                       (0x200)
+#define MCF_GPT_GMS_SC                       (0x400)
+#define MCF_GPT_GMS_CE                       (0x1000)
+#define MCF_GPT_GMS_WDEN                     (0x8000)
+#define MCF_GPT_GMS_ICT(x)                   (((x)&0x3)<<0x10)
+#define MCF_GPT_GMS_ICT_ANY                  (0)
+#define MCF_GPT_GMS_ICT_RISE                 (0x10000)
+#define MCF_GPT_GMS_ICT_FALL                 (0x20000)
+#define MCF_GPT_GMS_ICT_PULSE                (0x30000)
+#define MCF_GPT_GMS_OCT(x)                   (((x)&0x3)<<0x14)
+#define MCF_GPT_GMS_OCT_FRCLOW               (0)
+#define MCF_GPT_GMS_OCT_PULSEHI              (0x100000)
+#define MCF_GPT_GMS_OCT_PULSELO              (0x200000)
+#define MCF_GPT_GMS_OCT_TOGGLE               (0x300000)
+#define MCF_GPT_GMS_OCPW(x)                  (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_GPT_GCIR */
+#define MCF_GPT_GCIR_CNT(x)                  (((x)&0xFFFF)<<0)
+#define MCF_GPT_GCIR_PRE(x)                  (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_GPT_GPWM */
+#define MCF_GPT_GPWM_LOAD                    (0x1)
+#define MCF_GPT_GPWM_PWMOP                   (0x100)
+#define MCF_GPT_GPWM_WIDTH(x)                (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_GPT_GSR */
+#define MCF_GPT_GSR_CAPT                     (0x1)
+#define MCF_GPT_GSR_COMP                     (0x2)
+#define MCF_GPT_GSR_PWMP                     (0x4)
+#define MCF_GPT_GSR_TEXP                     (0x8)
+#define MCF_GPT_GSR_PIN                      (0x100)
+#define MCF_GPT_GSR_OVF(x)                   (((x)&0x7)<<0xC)
+#define MCF_GPT_GSR_CAPTURE(x)               (((x)&0xFFFF)<<0x10)
+
+
+#endif /* __MCF5475_GPT_H__ */

tos/fpga_test/include/MCF5475_I2C.h

@@ -0,0 +1,69 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_I2C_H__
+#define __MCF5475_I2C_H__
+
+
+/*********************************************************************
+*
+* I2C Module (I2C)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_I2C_I2ADR                        (*(volatile uint8_t *)(&_MBAR[0x8F00]))
+#define MCF_I2C_I2FDR                        (*(volatile uint8_t *)(&_MBAR[0x8F04]))
+#define MCF_I2C_I2CR                         (*(volatile uint8_t *)(&_MBAR[0x8F08]))
+#define MCF_I2C_I2SR                         (*(volatile uint8_t *)(&_MBAR[0x8F0C]))
+#define MCF_I2C_I2DR                         (*(volatile uint8_t *)(&_MBAR[0x8F10]))
+#define MCF_I2C_I2ICR                        (*(volatile uint8_t *)(&_MBAR[0x8F20]))
+
+
+
+/* Bit definitions and macros for MCF_I2C_I2ADR */
+#define MCF_I2C_I2ADR_ADR(x)                 (((x)&0x7F)<<0x1)
+
+/* Bit definitions and macros for MCF_I2C_I2FDR */
+#define MCF_I2C_I2FDR_IC(x)                  (((x)&0x3F)<<0)
+
+/* Bit definitions and macros for MCF_I2C_I2CR */
+#define MCF_I2C_I2CR_RSTA                    (0x4)
+#define MCF_I2C_I2CR_TXAK                    (0x8)
+#define MCF_I2C_I2CR_MTX                     (0x10)
+#define MCF_I2C_I2CR_MSTA                    (0x20)
+#define MCF_I2C_I2CR_IIEN                    (0x40)
+#define MCF_I2C_I2CR_IEN                     (0x80)
+
+/* Bit definitions and macros for MCF_I2C_I2SR */
+#define MCF_I2C_I2SR_RXAK                    (0x1)
+#define MCF_I2C_I2SR_IIF                     (0x2)
+#define MCF_I2C_I2SR_SRW                     (0x4)
+#define MCF_I2C_I2SR_IAL                     (0x10)
+#define MCF_I2C_I2SR_IBB                     (0x20)
+#define MCF_I2C_I2SR_IAAS                    (0x40)
+#define MCF_I2C_I2SR_ICF                     (0x80)
+
+/* Bit definitions and macros for MCF_I2C_I2DR */
+#define MCF_I2C_I2DR_DATA(x)                 (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_I2C_I2ICR */
+#define MCF_I2C_I2ICR_IE                     (0x1)
+#define MCF_I2C_I2ICR_RE                     (0x2)
+#define MCF_I2C_I2ICR_TE                     (0x4)
+#define MCF_I2C_I2ICR_BNBE                   (0x8)
+
+
+#endif /* __MCF5475_I2C_H__ */

tos/fpga_test/include/MCF5475_INTC.h

@@ -0,0 +1,331 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_INTC_H__
+#define __MCF5475_INTC_H__
+
+
+/*********************************************************************
+*
+* Interrupt Controller (INTC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_INTC_IPRH                        (*(volatile uint32_t*)(&_MBAR[0x700]))
+#define MCF_INTC_IPRL                        (*(volatile uint32_t*)(&_MBAR[0x704]))
+#define MCF_INTC_IMRH                        (*(volatile uint32_t*)(&_MBAR[0x708]))
+#define MCF_INTC_IMRL                        (*(volatile uint32_t*)(&_MBAR[0x70C]))
+#define MCF_INTC_INTFRCH                     (*(volatile uint32_t*)(&_MBAR[0x710]))
+#define MCF_INTC_INTFRCL                     (*(volatile uint32_t*)(&_MBAR[0x714]))
+#define MCF_INTC_IRLR                        (*(volatile uint8_t *)(&_MBAR[0x718]))
+#define MCF_INTC_IACKLPR                     (*(volatile uint8_t *)(&_MBAR[0x719]))
+#define MCF_INTC_ICR01                       (*(volatile uint8_t *)(&_MBAR[0x741]))
+#define MCF_INTC_ICR02                       (*(volatile uint8_t *)(&_MBAR[0x742]))
+#define MCF_INTC_ICR03                       (*(volatile uint8_t *)(&_MBAR[0x743]))
+#define MCF_INTC_ICR04                       (*(volatile uint8_t *)(&_MBAR[0x744]))
+#define MCF_INTC_ICR05                       (*(volatile uint8_t *)(&_MBAR[0x745]))
+#define MCF_INTC_ICR06                       (*(volatile uint8_t *)(&_MBAR[0x746]))
+#define MCF_INTC_ICR07                       (*(volatile uint8_t *)(&_MBAR[0x747]))
+#define MCF_INTC_ICR08                       (*(volatile uint8_t *)(&_MBAR[0x748]))
+#define MCF_INTC_ICR09                       (*(volatile uint8_t *)(&_MBAR[0x749]))
+#define MCF_INTC_ICR10                       (*(volatile uint8_t *)(&_MBAR[0x74A]))
+#define MCF_INTC_ICR11                       (*(volatile uint8_t *)(&_MBAR[0x74B]))
+#define MCF_INTC_ICR12                       (*(volatile uint8_t *)(&_MBAR[0x74C]))
+#define MCF_INTC_ICR13                       (*(volatile uint8_t *)(&_MBAR[0x74D]))
+#define MCF_INTC_ICR14                       (*(volatile uint8_t *)(&_MBAR[0x74E]))
+#define MCF_INTC_ICR15                       (*(volatile uint8_t *)(&_MBAR[0x74F]))
+#define MCF_INTC_ICR16                       (*(volatile uint8_t *)(&_MBAR[0x750]))
+#define MCF_INTC_ICR17                       (*(volatile uint8_t *)(&_MBAR[0x751]))
+#define MCF_INTC_ICR18                       (*(volatile uint8_t *)(&_MBAR[0x752]))
+#define MCF_INTC_ICR19                       (*(volatile uint8_t *)(&_MBAR[0x753]))
+#define MCF_INTC_ICR20                       (*(volatile uint8_t *)(&_MBAR[0x754]))
+#define MCF_INTC_ICR21                       (*(volatile uint8_t *)(&_MBAR[0x755]))
+#define MCF_INTC_ICR22                       (*(volatile uint8_t *)(&_MBAR[0x756]))
+#define MCF_INTC_ICR23                       (*(volatile uint8_t *)(&_MBAR[0x757]))
+#define MCF_INTC_ICR24                       (*(volatile uint8_t *)(&_MBAR[0x758]))
+#define MCF_INTC_ICR25                       (*(volatile uint8_t *)(&_MBAR[0x759]))
+#define MCF_INTC_ICR26                       (*(volatile uint8_t *)(&_MBAR[0x75A]))
+#define MCF_INTC_ICR27                       (*(volatile uint8_t *)(&_MBAR[0x75B]))
+#define MCF_INTC_ICR28                       (*(volatile uint8_t *)(&_MBAR[0x75C]))
+#define MCF_INTC_ICR29                       (*(volatile uint8_t *)(&_MBAR[0x75D]))
+#define MCF_INTC_ICR30                       (*(volatile uint8_t *)(&_MBAR[0x75E]))
+#define MCF_INTC_ICR31                       (*(volatile uint8_t *)(&_MBAR[0x75F]))
+#define MCF_INTC_ICR32                       (*(volatile uint8_t *)(&_MBAR[0x760]))
+#define MCF_INTC_ICR33                       (*(volatile uint8_t *)(&_MBAR[0x761]))
+#define MCF_INTC_ICR34                       (*(volatile uint8_t *)(&_MBAR[0x762]))
+#define MCF_INTC_ICR35                       (*(volatile uint8_t *)(&_MBAR[0x763]))
+#define MCF_INTC_ICR36                       (*(volatile uint8_t *)(&_MBAR[0x764]))
+#define MCF_INTC_ICR37                       (*(volatile uint8_t *)(&_MBAR[0x765]))
+#define MCF_INTC_ICR38                       (*(volatile uint8_t *)(&_MBAR[0x766]))
+#define MCF_INTC_ICR39                       (*(volatile uint8_t *)(&_MBAR[0x767]))
+#define MCF_INTC_ICR40                       (*(volatile uint8_t *)(&_MBAR[0x768]))
+#define MCF_INTC_ICR41                       (*(volatile uint8_t *)(&_MBAR[0x769]))
+#define MCF_INTC_ICR42                       (*(volatile uint8_t *)(&_MBAR[0x76A]))
+#define MCF_INTC_ICR43                       (*(volatile uint8_t *)(&_MBAR[0x76B]))
+#define MCF_INTC_ICR44                       (*(volatile uint8_t *)(&_MBAR[0x76C]))
+#define MCF_INTC_ICR45                       (*(volatile uint8_t *)(&_MBAR[0x76D]))
+#define MCF_INTC_ICR46                       (*(volatile uint8_t *)(&_MBAR[0x76E]))
+#define MCF_INTC_ICR47                       (*(volatile uint8_t *)(&_MBAR[0x76F]))
+#define MCF_INTC_ICR48                       (*(volatile uint8_t *)(&_MBAR[0x770]))
+#define MCF_INTC_ICR49                       (*(volatile uint8_t *)(&_MBAR[0x771]))
+#define MCF_INTC_ICR50                       (*(volatile uint8_t *)(&_MBAR[0x772]))
+#define MCF_INTC_ICR51                       (*(volatile uint8_t *)(&_MBAR[0x773]))
+#define MCF_INTC_ICR52                       (*(volatile uint8_t *)(&_MBAR[0x774]))
+#define MCF_INTC_ICR53                       (*(volatile uint8_t *)(&_MBAR[0x775]))
+#define MCF_INTC_ICR54                       (*(volatile uint8_t *)(&_MBAR[0x776]))
+#define MCF_INTC_ICR55                       (*(volatile uint8_t *)(&_MBAR[0x777]))
+#define MCF_INTC_ICR56                       (*(volatile uint8_t *)(&_MBAR[0x778]))
+#define MCF_INTC_ICR57                       (*(volatile uint8_t *)(&_MBAR[0x779]))
+#define MCF_INTC_ICR58                       (*(volatile uint8_t *)(&_MBAR[0x77A]))
+#define MCF_INTC_ICR59                       (*(volatile uint8_t *)(&_MBAR[0x77B]))
+#define MCF_INTC_ICR60                       (*(volatile uint8_t *)(&_MBAR[0x77C]))
+#define MCF_INTC_ICR61                       (*(volatile uint8_t *)(&_MBAR[0x77D]))
+#define MCF_INTC_ICR62                       (*(volatile uint8_t *)(&_MBAR[0x77E]))
+#define MCF_INTC_ICR63                       (*(volatile uint8_t *)(&_MBAR[0x77F]))
+#define MCF_INTC_SWIACK                      (*(volatile uint8_t *)(&_MBAR[0x7E0]))
+#define MCF_INTC_L1IACK                      (*(volatile uint8_t *)(&_MBAR[0x7E4]))
+#define MCF_INTC_L2IACK                      (*(volatile uint8_t *)(&_MBAR[0x7E8]))
+#define MCF_INTC_L3IACK                      (*(volatile uint8_t *)(&_MBAR[0x7EC]))
+#define MCF_INTC_L4IACK                      (*(volatile uint8_t *)(&_MBAR[0x7F0]))
+#define MCF_INTC_L5IACK                      (*(volatile uint8_t *)(&_MBAR[0x7F4]))
+#define MCF_INTC_L6IACK                      (*(volatile uint8_t *)(&_MBAR[0x7F8]))
+#define MCF_INTC_L7IACK                      (*(volatile uint8_t *)(&_MBAR[0x7FC]))
+#define MCF_INTC_ICR(x)                      (*(volatile uint8_t *)(&_MBAR[0x741 + ((x-1)*0x1)]))
+#define MCF_INTC_LIACK(x)                    (*(volatile uint8_t *)(&_MBAR[0x7E4 + ((x-1)*0x4)]))
+
+
+
+/* Bit definitions and macros for MCF_INTC_IPRH */
+#define MCF_INTC_IPRH_INT32                  (0x1)
+#define MCF_INTC_IPRH_INT33                  (0x2)
+#define MCF_INTC_IPRH_INT34                  (0x4)
+#define MCF_INTC_IPRH_INT35                  (0x8)
+#define MCF_INTC_IPRH_INT36                  (0x10)
+#define MCF_INTC_IPRH_INT37                  (0x20)
+#define MCF_INTC_IPRH_INT38                  (0x40)
+#define MCF_INTC_IPRH_INT39                  (0x80)
+#define MCF_INTC_IPRH_INT40                  (0x100)
+#define MCF_INTC_IPRH_INT41                  (0x200)
+#define MCF_INTC_IPRH_INT42                  (0x400)
+#define MCF_INTC_IPRH_INT43                  (0x800)
+#define MCF_INTC_IPRH_INT44                  (0x1000)
+#define MCF_INTC_IPRH_INT45                  (0x2000)
+#define MCF_INTC_IPRH_INT46                  (0x4000)
+#define MCF_INTC_IPRH_INT47                  (0x8000)
+#define MCF_INTC_IPRH_INT48                  (0x10000)
+#define MCF_INTC_IPRH_INT49                  (0x20000)
+#define MCF_INTC_IPRH_INT50                  (0x40000)
+#define MCF_INTC_IPRH_INT51                  (0x80000)
+#define MCF_INTC_IPRH_INT52                  (0x100000)
+#define MCF_INTC_IPRH_INT53                  (0x200000)
+#define MCF_INTC_IPRH_INT54                  (0x400000)
+#define MCF_INTC_IPRH_INT55                  (0x800000)
+#define MCF_INTC_IPRH_INT56                  (0x1000000)
+#define MCF_INTC_IPRH_INT57                  (0x2000000)
+#define MCF_INTC_IPRH_INT58                  (0x4000000)
+#define MCF_INTC_IPRH_INT59                  (0x8000000)
+#define MCF_INTC_IPRH_INT60                  (0x10000000)
+#define MCF_INTC_IPRH_INT61                  (0x20000000)
+#define MCF_INTC_IPRH_INT62                  (0x40000000)
+#define MCF_INTC_IPRH_INT63                  (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IPRL */
+#define MCF_INTC_IPRL_INT1                   (0x2)
+#define MCF_INTC_IPRL_INT2                   (0x4)
+#define MCF_INTC_IPRL_INT3                   (0x8)
+#define MCF_INTC_IPRL_INT4                   (0x10)
+#define MCF_INTC_IPRL_INT5                   (0x20)
+#define MCF_INTC_IPRL_INT6                   (0x40)
+#define MCF_INTC_IPRL_INT7                   (0x80)
+#define MCF_INTC_IPRL_INT8                   (0x100)
+#define MCF_INTC_IPRL_INT9                   (0x200)
+#define MCF_INTC_IPRL_INT10                  (0x400)
+#define MCF_INTC_IPRL_INT11                  (0x800)
+#define MCF_INTC_IPRL_INT12                  (0x1000)
+#define MCF_INTC_IPRL_INT13                  (0x2000)
+#define MCF_INTC_IPRL_INT14                  (0x4000)
+#define MCF_INTC_IPRL_INT15                  (0x8000)
+#define MCF_INTC_IPRL_INT16                  (0x10000)
+#define MCF_INTC_IPRL_INT17                  (0x20000)
+#define MCF_INTC_IPRL_INT18                  (0x40000)
+#define MCF_INTC_IPRL_INT19                  (0x80000)
+#define MCF_INTC_IPRL_INT20                  (0x100000)
+#define MCF_INTC_IPRL_INT21                  (0x200000)
+#define MCF_INTC_IPRL_INT22                  (0x400000)
+#define MCF_INTC_IPRL_INT23                  (0x800000)
+#define MCF_INTC_IPRL_INT24                  (0x1000000)
+#define MCF_INTC_IPRL_INT25                  (0x2000000)
+#define MCF_INTC_IPRL_INT26                  (0x4000000)
+#define MCF_INTC_IPRL_INT27                  (0x8000000)
+#define MCF_INTC_IPRL_INT28                  (0x10000000)
+#define MCF_INTC_IPRL_INT29                  (0x20000000)
+#define MCF_INTC_IPRL_INT30                  (0x40000000)
+#define MCF_INTC_IPRL_INT31                  (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IMRH */
+#define MCF_INTC_IMRH_INT_MASK32             (0x1)
+#define MCF_INTC_IMRH_INT_MASK33             (0x2)
+#define MCF_INTC_IMRH_INT_MASK34             (0x4)
+#define MCF_INTC_IMRH_INT_MASK35             (0x8)
+#define MCF_INTC_IMRH_INT_MASK36             (0x10)
+#define MCF_INTC_IMRH_INT_MASK37             (0x20)
+#define MCF_INTC_IMRH_INT_MASK38             (0x40)
+#define MCF_INTC_IMRH_INT_MASK39             (0x80)
+#define MCF_INTC_IMRH_INT_MASK40             (0x100)
+#define MCF_INTC_IMRH_INT_MASK41             (0x200)
+#define MCF_INTC_IMRH_INT_MASK42             (0x400)
+#define MCF_INTC_IMRH_INT_MASK43             (0x800)
+#define MCF_INTC_IMRH_INT_MASK44             (0x1000)
+#define MCF_INTC_IMRH_INT_MASK45             (0x2000)
+#define MCF_INTC_IMRH_INT_MASK46             (0x4000)
+#define MCF_INTC_IMRH_INT_MASK47             (0x8000)
+#define MCF_INTC_IMRH_INT_MASK48             (0x10000)
+#define MCF_INTC_IMRH_INT_MASK49             (0x20000)
+#define MCF_INTC_IMRH_INT_MASK50             (0x40000)
+#define MCF_INTC_IMRH_INT_MASK51             (0x80000)
+#define MCF_INTC_IMRH_INT_MASK52             (0x100000)
+#define MCF_INTC_IMRH_INT_MASK53             (0x200000)
+#define MCF_INTC_IMRH_INT_MASK54             (0x400000)
+#define MCF_INTC_IMRH_INT_MASK55             (0x800000)
+#define MCF_INTC_IMRH_INT_MASK56             (0x1000000)
+#define MCF_INTC_IMRH_INT_MASK57             (0x2000000)
+#define MCF_INTC_IMRH_INT_MASK58             (0x4000000)
+#define MCF_INTC_IMRH_INT_MASK59             (0x8000000)
+#define MCF_INTC_IMRH_INT_MASK60             (0x10000000)
+#define MCF_INTC_IMRH_INT_MASK61             (0x20000000)
+#define MCF_INTC_IMRH_INT_MASK62             (0x40000000)
+#define MCF_INTC_IMRH_INT_MASK63             (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IMRL */
+#define MCF_INTC_IMRL_MASKALL                (0x1)
+#define MCF_INTC_IMRL_INT_MASK1              (0x2)
+#define MCF_INTC_IMRL_INT_MASK2              (0x4)
+#define MCF_INTC_IMRL_INT_MASK3              (0x8)
+#define MCF_INTC_IMRL_INT_MASK4              (0x10)
+#define MCF_INTC_IMRL_INT_MASK5              (0x20)
+#define MCF_INTC_IMRL_INT_MASK6              (0x40)
+#define MCF_INTC_IMRL_INT_MASK7              (0x80)
+#define MCF_INTC_IMRL_INT_MASK8              (0x100)
+#define MCF_INTC_IMRL_INT_MASK9              (0x200)
+#define MCF_INTC_IMRL_INT_MASK10             (0x400)
+#define MCF_INTC_IMRL_INT_MASK11             (0x800)
+#define MCF_INTC_IMRL_INT_MASK12             (0x1000)
+#define MCF_INTC_IMRL_INT_MASK13             (0x2000)
+#define MCF_INTC_IMRL_INT_MASK14             (0x4000)
+#define MCF_INTC_IMRL_INT_MASK15             (0x8000)
+#define MCF_INTC_IMRL_INT_MASK16             (0x10000)
+#define MCF_INTC_IMRL_INT_MASK17             (0x20000)
+#define MCF_INTC_IMRL_INT_MASK18             (0x40000)
+#define MCF_INTC_IMRL_INT_MASK19             (0x80000)
+#define MCF_INTC_IMRL_INT_MASK20             (0x100000)
+#define MCF_INTC_IMRL_INT_MASK21             (0x200000)
+#define MCF_INTC_IMRL_INT_MASK22             (0x400000)
+#define MCF_INTC_IMRL_INT_MASK23             (0x800000)
+#define MCF_INTC_IMRL_INT_MASK24             (0x1000000)
+#define MCF_INTC_IMRL_INT_MASK25             (0x2000000)
+#define MCF_INTC_IMRL_INT_MASK26             (0x4000000)
+#define MCF_INTC_IMRL_INT_MASK27             (0x8000000)
+#define MCF_INTC_IMRL_INT_MASK28             (0x10000000)
+#define MCF_INTC_IMRL_INT_MASK29             (0x20000000)
+#define MCF_INTC_IMRL_INT_MASK30             (0x40000000)
+#define MCF_INTC_IMRL_INT_MASK31             (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_INTFRCH */
+#define MCF_INTC_INTFRCH_INTFRC32            (0x1)
+#define MCF_INTC_INTFRCH_INTFRC33            (0x2)
+#define MCF_INTC_INTFRCH_INTFRC34            (0x4)
+#define MCF_INTC_INTFRCH_INTFRC35            (0x8)
+#define MCF_INTC_INTFRCH_INTFRC36            (0x10)
+#define MCF_INTC_INTFRCH_INTFRC37            (0x20)
+#define MCF_INTC_INTFRCH_INTFRC38            (0x40)
+#define MCF_INTC_INTFRCH_INTFRC39            (0x80)
+#define MCF_INTC_INTFRCH_INTFRC40            (0x100)
+#define MCF_INTC_INTFRCH_INTFRC41            (0x200)
+#define MCF_INTC_INTFRCH_INTFRC42            (0x400)
+#define MCF_INTC_INTFRCH_INTFRC43            (0x800)
+#define MCF_INTC_INTFRCH_INTFRC44            (0x1000)
+#define MCF_INTC_INTFRCH_INTFRC45            (0x2000)
+#define MCF_INTC_INTFRCH_INTFRC46            (0x4000)
+#define MCF_INTC_INTFRCH_INTFRC47            (0x8000)
+#define MCF_INTC_INTFRCH_INTFRC48            (0x10000)
+#define MCF_INTC_INTFRCH_INTFRC49            (0x20000)
+#define MCF_INTC_INTFRCH_INTFRC50            (0x40000)
+#define MCF_INTC_INTFRCH_INTFRC51            (0x80000)
+#define MCF_INTC_INTFRCH_INTFRC52            (0x100000)
+#define MCF_INTC_INTFRCH_INTFRC53            (0x200000)
+#define MCF_INTC_INTFRCH_INTFRC54            (0x400000)
+#define MCF_INTC_INTFRCH_INTFRC55            (0x800000)
+#define MCF_INTC_INTFRCH_INTFRC56            (0x1000000)
+#define MCF_INTC_INTFRCH_INTFRC57            (0x2000000)
+#define MCF_INTC_INTFRCH_INTFRC58            (0x4000000)
+#define MCF_INTC_INTFRCH_INTFRC59            (0x8000000)
+#define MCF_INTC_INTFRCH_INTFRC60            (0x10000000)
+#define MCF_INTC_INTFRCH_INTFRC61            (0x20000000)
+#define MCF_INTC_INTFRCH_INTFRC62            (0x40000000)
+#define MCF_INTC_INTFRCH_INTFRC63            (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_INTFRCL */
+#define MCF_INTC_INTFRCL_INTFRC1             (0x2)
+#define MCF_INTC_INTFRCL_INTFRC2             (0x4)
+#define MCF_INTC_INTFRCL_INTFRC3             (0x8)
+#define MCF_INTC_INTFRCL_INTFRC4             (0x10)
+#define MCF_INTC_INTFRCL_INTFRC5             (0x20)
+#define MCF_INTC_INTFRCL_INTFRC6             (0x40)
+#define MCF_INTC_INTFRCL_INTFRC7             (0x80)
+#define MCF_INTC_INTFRCL_INTFRC8             (0x100)
+#define MCF_INTC_INTFRCL_INTFRC9             (0x200)
+#define MCF_INTC_INTFRCL_INTFRC10            (0x400)
+#define MCF_INTC_INTFRCL_INTFRC11            (0x800)
+#define MCF_INTC_INTFRCL_INTFRC12            (0x1000)
+#define MCF_INTC_INTFRCL_INTFRC13            (0x2000)
+#define MCF_INTC_INTFRCL_INTFRC14            (0x4000)
+#define MCF_INTC_INTFRCL_INTFRC15            (0x8000)
+#define MCF_INTC_INTFRCL_INTFRC16            (0x10000)
+#define MCF_INTC_INTFRCL_INTFRC17            (0x20000)
+#define MCF_INTC_INTFRCL_INTFRC18            (0x40000)
+#define MCF_INTC_INTFRCL_INTFRC19            (0x80000)
+#define MCF_INTC_INTFRCL_INTFRC20            (0x100000)
+#define MCF_INTC_INTFRCL_INTFRC21            (0x200000)
+#define MCF_INTC_INTFRCL_INTFRC22            (0x400000)
+#define MCF_INTC_INTFRCL_INTFRC23            (0x800000)
+#define MCF_INTC_INTFRCL_INTFRC24            (0x1000000)
+#define MCF_INTC_INTFRCL_INTFRC25            (0x2000000)
+#define MCF_INTC_INTFRCL_INTFRC26            (0x4000000)
+#define MCF_INTC_INTFRCL_INTFRC27            (0x8000000)
+#define MCF_INTC_INTFRCL_INTFRC28            (0x10000000)
+#define MCF_INTC_INTFRCL_INTFRC29            (0x20000000)
+#define MCF_INTC_INTFRCL_INTFRC30            (0x40000000)
+#define MCF_INTC_INTFRCL_INTFRC31            (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IRLR */
+#define MCF_INTC_IRLR_IRQ(x)                 (((x)&0x7F)<<0x1)
+
+/* Bit definitions and macros for MCF_INTC_IACKLPR */
+#define MCF_INTC_IACKLPR_PRI(x)              (((x)&0xF)<<0)
+#define MCF_INTC_IACKLPR_LEVEL(x)            (((x)&0x7)<<0x4)
+
+/* Bit definitions and macros for MCF_INTC_ICR */
+#define MCF_INTC_ICR_IP(x)                   (((x)&0x7)<<0)
+#define MCF_INTC_ICR_IL(x)                   (((x)&0x7)<<0x3)
+
+/* Bit definitions and macros for MCF_INTC_SWIACK */
+#define MCF_INTC_SWIACK_VECTOR(x)            (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_INTC_LIACK */
+#define MCF_INTC_LIACK_VECTOR(x)             (((x)&0xFF)<<0)
+
+
+#endif /* __MCF5475_INTC_H__ */

tos/fpga_test/include/MCF5475_MMU.h

@@ -0,0 +1,79 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_MMU_H__
+#define __MCF5475_MMU_H__
+
+
+/*********************************************************************
+*
+* Memory Management Unit (MMU)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+
+/* note the uint32_t_a - this is to avoid gcc warnings about pointer aliasing */
+#define MCF_MMU_MMUCR                        (*(volatile uint32_t_a*)(&_MMUBAR[0]))
+#define MCF_MMU_MMUOR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x4]))
+#define MCF_MMU_MMUSR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x8]))
+#define MCF_MMU_MMUAR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x10]))
+#define MCF_MMU_MMUTR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x14]))
+#define MCF_MMU_MMUDR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x18]))
+
+
+/* Bit definitions and macros for MCF_MMU_MMUCR */
+#define MCF_MMU_MMUCR_EN                     (0x1)
+#define MCF_MMU_MMUCR_ASM                    (0x2)
+
+/* Bit definitions and macros for MCF_MMU_MMUOR */
+#define MCF_MMU_MMUOR_UAA                    (0x1)
+#define MCF_MMU_MMUOR_ACC                    (0x2)
+#define MCF_MMU_MMUOR_RW                     (0x4)
+#define MCF_MMU_MMUOR_ADR                    (0x8)
+#define MCF_MMU_MMUOR_ITLB                   (0x10)
+#define MCF_MMU_MMUOR_CAS                    (0x20)
+#define MCF_MMU_MMUOR_CNL                    (0x40)
+#define MCF_MMU_MMUOR_CA                     (0x80)
+#define MCF_MMU_MMUOR_STLB                   (0x100)
+#define MCF_MMU_MMUOR_AA(x)                  (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_MMU_MMUSR */
+#define MCF_MMU_MMUSR_HIT                    (0x2)
+#define MCF_MMU_MMUSR_WF                     (0x8)
+#define MCF_MMU_MMUSR_RF                     (0x10)
+#define MCF_MMU_MMUSR_SPF                    (0x20)
+
+/* Bit definitions and macros for MCF_MMU_MMUAR */
+#define MCF_MMU_MMUAR_FA(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_MMU_MMUTR */
+#define MCF_MMU_MMUTR_V                      (0x1)
+#define MCF_MMU_MMUTR_SG                     (0x2)
+#define MCF_MMU_MMUTR_ID(x)                  (((x)&0xFF)<<0x2)
+#define MCF_MMU_MMUTR_VA(x)                  (((x)&0x3FFFFF)<<0xA)
+
+/* Bit definitions and macros for MCF_MMU_MMUDR */
+#define MCF_MMU_MMUDR_LK                     (0x2)
+#define MCF_MMU_MMUDR_X                      (0x4)
+#define MCF_MMU_MMUDR_W                      (0x8)
+#define MCF_MMU_MMUDR_R                      (0x10)
+#define MCF_MMU_MMUDR_SP                     (0x20)
+#define MCF_MMU_MMUDR_CM(x)                  (((x)&0x3)<<0x6)
+#define MCF_MMU_MMUDR_SZ(x)                  (((x)&0x3)<<0x8)
+#define MCF_MMU_MMUDR_PA(x)                  (((x)&0x3FFFFF)<<0xA)
+
+
+#endif /* __MCF5475_MMU_H__ */

tos/fpga_test/include/MCF5475_PAD.h

@@ -0,0 +1,233 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PAD_H__
+#define __MCF5475_PAD_H__
+
+
+/*********************************************************************
+*
+* Common GPIO
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PAD_PAR_FBCTL                    (*(volatile uint16_t*)(&_MBAR[0xA40]))
+#define MCF_PAD_PAR_FBCS                     (*(volatile uint8_t *)(&_MBAR[0xA42]))
+#define MCF_PAD_PAR_DMA                      (*(volatile uint8_t *)(&_MBAR[0xA43]))
+#define MCF_PAD_PAR_FECI2CIRQ                (*(volatile uint16_t*)(&_MBAR[0xA44]))
+#define MCF_PAD_PAR_PCIBG                    (*(volatile uint16_t*)(&_MBAR[0xA48]))
+#define MCF_PAD_PAR_PCIBR                    (*(volatile uint16_t*)(&_MBAR[0xA4A]))
+#define MCF_PAD_PAR_PSC3                     (*(volatile uint8_t *)(&_MBAR[0xA4C]))
+#define MCF_PAD_PAR_PSC2                     (*(volatile uint8_t *)(&_MBAR[0xA4D]))
+#define MCF_PAD_PAR_PSC1                     (*(volatile uint8_t *)(&_MBAR[0xA4E]))
+#define MCF_PAD_PAR_PSC0                     (*(volatile uint8_t *)(&_MBAR[0xA4F]))
+#define MCF_PAD_PAR_DSPI                     (*(volatile uint16_t*)(&_MBAR[0xA50]))
+#define MCF_PAD_PAR_TIMER                    (*(volatile uint8_t *)(&_MBAR[0xA52]))
+
+
+/* Bit definitions and macros for MCF_PAD_PAR_FBCTL */
+#define MCF_PAD_PAR_FBCTL_PAR_ALE(x)         (((x)&0x3)<<0)
+#define MCF_PAD_PAR_FBCTL_PAR_ALE_GPIO       (0)
+#define MCF_PAD_PAR_FBCTL_PAR_ALE_TBST       (0x2)
+#define MCF_PAD_PAR_FBCTL_PAR_ALE_ALE        (0x3)
+#define MCF_PAD_PAR_FBCTL_PAR_TA             (0x4)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB_GPIO       (0)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB_TBST       (0x20)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB_RW         (0x30)
+#define MCF_PAD_PAR_FBCTL_PAR_OE             (0x40)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE0           (0x100)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE1           (0x400)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE2           (0x1000)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE3           (0x4000)
+
+/* Bit definitions and macros for MCF_PAD_PAR_FBCS */
+#define MCF_PAD_PAR_FBCS_PAR_CS1             (0x2)
+#define MCF_PAD_PAR_FBCS_PAR_CS2             (0x4)
+#define MCF_PAD_PAR_FBCS_PAR_CS3             (0x8)
+#define MCF_PAD_PAR_FBCS_PAR_CS4             (0x10)
+#define MCF_PAD_PAR_FBCS_PAR_CS5             (0x20)
+
+/* Bit definitions and macros for MCF_PAD_PAR_DMA */
+#define MCF_PAD_PAR_DMA_PAR_DREQ0(x)         (((x)&0x3)<<0)
+#define MCF_PAD_PAR_DMA_PAR_DREQ0_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DREQ0_TIN0       (0x2)
+#define MCF_PAD_PAR_DMA_PAR_DREQ0_DREQ0      (0x3)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1(x)         (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_IRQ1       (0x4)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_TIN1       (0x8)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_DREQ1      (0xC)
+#define MCF_PAD_PAR_DMA_PAR_DACK0(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_DMA_PAR_DACK0_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DACK0_TOUT0      (0x20)
+#define MCF_PAD_PAR_DMA_PAR_DACK0_DACK0      (0x30)
+#define MCF_PAD_PAR_DMA_PAR_DACK1(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_DMA_PAR_DACK1_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DACK1_TOUT1      (0x80)
+#define MCF_PAD_PAR_DMA_PAR_DACK1_DACK1      (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_FECI2CIRQ */
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ5       (0x1)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ6       (0x2)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_SCL        (0x4)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_SDA        (0x8)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC(x)   (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_SCL  (0x80)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC (0xC0)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO(x)  (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x200)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO (0x300)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MII      (0x400)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E17        (0x800)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC      (0x1000)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO     (0x2000)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII      (0x4000)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E07        (0x8000)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PCIBG */
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0(x)      (((x)&0x3)<<0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_TOUT0   (0x2)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0  (0x3)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1(x)      (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_TOUT1   (0x8)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1  (0xC)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2(x)      (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_TOUT2   (0x20)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2  (0x30)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3(x)      (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_TOUT3   (0x80)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3  (0xC0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4(x)      (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST    (0x200)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4  (0x300)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PCIBR */
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0(x)      (((x)&0x3)<<0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_TIN0    (0x2)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0  (0x3)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1(x)      (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_TIN1    (0x8)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1  (0xC)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2(x)      (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_TIN2    (0x20)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2  (0x30)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3(x)      (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_TIN3    (0x80)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3  (0xC0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4(x)      (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4    (0x200)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4  (0x300)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC3 */
+#define MCF_PAD_PAR_PSC3_PAR_TXD3            (0x4)
+#define MCF_PAD_PAR_PSC3_PAR_RXD3            (0x8)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3_GPIO       (0)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3_RTS        (0x30)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3_GPIO       (0)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC2 */
+#define MCF_PAD_PAR_PSC2_PAR_TXD2            (0x4)
+#define MCF_PAD_PAR_PSC2_PAR_RXD2            (0x8)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2_GPIO       (0)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2_RTS        (0x30)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2_GPIO       (0)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC1 */
+#define MCF_PAD_PAR_PSC1_PAR_TXD1            (0x4)
+#define MCF_PAD_PAR_PSC1_PAR_RXD1            (0x8)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1_GPIO       (0)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1_RTS        (0x30)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1_GPIO       (0)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC0 */
+#define MCF_PAD_PAR_PSC0_PAR_TXD0            (0x4)
+#define MCF_PAD_PAR_PSC0_PAR_RXD0            (0x8)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0_GPIO       (0)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0_RTS        (0x30)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0_GPIO       (0)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_DSPI */
+#define MCF_PAD_PAR_DSPI_PAR_SOUT(x)         (((x)&0x3)<<0)
+#define MCF_PAD_PAR_DSPI_PAR_SOUT_GPIO       (0)
+#define MCF_PAD_PAR_DSPI_PAR_SOUT_TXD        (0x2)
+#define MCF_PAD_PAR_DSPI_PAR_SOUT_SOUT       (0x3)
+#define MCF_PAD_PAR_DSPI_PAR_SIN(x)          (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_DSPI_PAR_SIN_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_SIN_RXD         (0x8)
+#define MCF_PAD_PAR_DSPI_PAR_SIN_SIN         (0xC)
+#define MCF_PAD_PAR_DSPI_PAR_SCK(x)          (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_BCLK        (0x10)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_CTS         (0x20)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_SCK         (0x30)
+#define MCF_PAD_PAR_DSPI_PAR_CS0(x)          (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_FSYNC       (0x40)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_RTS         (0x80)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_DSPICS0     (0xC0)
+#define MCF_PAD_PAR_DSPI_PAR_CS2(x)          (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_DSPI_PAR_CS2_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_CS2_TOUT2       (0x200)
+#define MCF_PAD_PAR_DSPI_PAR_CS2_DSPICS2     (0x300)
+#define MCF_PAD_PAR_DSPI_PAR_CS3(x)          (((x)&0x3)<<0xA)
+#define MCF_PAD_PAR_DSPI_PAR_CS3_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_CS3_TOUT3       (0x800)
+#define MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3     (0xC00)
+#define MCF_PAD_PAR_DSPI_PAR_CS5             (0x1000)
+
+/* Bit definitions and macros for MCF_PAD_PAR_TIMER */
+#define MCF_PAD_PAR_TIMER_PAR_TOUT2          (0x1)
+#define MCF_PAD_PAR_TIMER_PAR_TIN2(x)        (((x)&0x3)<<0x1)
+#define MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2      (0x4)
+#define MCF_PAD_PAR_TIMER_PAR_TIN2_TIN2      (0x6)
+#define MCF_PAD_PAR_TIMER_PAR_TOUT3          (0x8)
+#define MCF_PAD_PAR_TIMER_PAR_TIN3(x)        (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_TIMER_PAR_TIN3_IRQ3      (0x20)
+#define MCF_PAD_PAR_TIMER_PAR_TIN3_TIN3      (0x30)
+
+
+#endif /* __MCF5475_PAD_H__ */

tos/fpga_test/include/MCF5475_PCI.h

@@ -0,0 +1,376 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PCI_H__
+#define __MCF5475_PCI_H__
+
+
+/*********************************************************************
+*
+* PCI Bus Controller (PCI)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PCI_PCIIDR                       (*(volatile uint32_t*)(&_MBAR[0xB00]))
+#define MCF_PCI_PCISCR                       (*(volatile uint32_t*)(&_MBAR[0xB04]))
+#define MCF_PCI_PCICCRIR                     (*(volatile uint32_t*)(&_MBAR[0xB08]))
+#define MCF_PCI_PCICR1                       (*(volatile uint32_t*)(&_MBAR[0xB0C]))
+#define MCF_PCI_PCIBAR0                      (*(volatile uint32_t*)(&_MBAR[0xB10]))
+#define MCF_PCI_PCIBAR1                      (*(volatile uint32_t*)(&_MBAR[0xB14]))
+#define MCF_PCI_PCICCPR                      (*(volatile uint32_t*)(&_MBAR[0xB28]))
+#define MCF_PCI_PCISID                       (*(volatile uint32_t*)(&_MBAR[0xB2C]))
+#define MCF_PCI_PCICR2                       (*(volatile uint32_t*)(&_MBAR[0xB3C]))
+#define MCF_PCI_PCIGSCR                      (*(volatile uint32_t*)(&_MBAR[0xB60]))
+#define MCF_PCI_PCITBATR0                    (*(volatile uint32_t*)(&_MBAR[0xB64]))
+#define MCF_PCI_PCITBATR1                    (*(volatile uint32_t*)(&_MBAR[0xB68]))
+#define MCF_PCI_PCITCR                       (*(volatile uint32_t*)(&_MBAR[0xB6C]))
+#define MCF_PCI_PCIIW0BTAR                   (*(volatile uint32_t*)(&_MBAR[0xB70]))
+#define MCF_PCI_PCIIW1BTAR                   (*(volatile uint32_t*)(&_MBAR[0xB74]))
+#define MCF_PCI_PCIIW2BTAR                   (*(volatile uint32_t*)(&_MBAR[0xB78]))
+#define MCF_PCI_PCIIWCR                      (*(volatile uint32_t*)(&_MBAR[0xB80]))
+#define MCF_PCI_PCIICR                       (*(volatile uint32_t*)(&_MBAR[0xB84]))
+#define MCF_PCI_PCIISR                       (*(volatile uint32_t*)(&_MBAR[0xB88]))
+#define MCF_PCI_PCICAR                       (*(volatile uint32_t*)(&_MBAR[0xBF8]))
+#define MCF_PCI_PCITPSR                      (*(volatile uint32_t*)(&_MBAR[0x8400]))
+#define MCF_PCI_PCITSAR                      (*(volatile uint32_t*)(&_MBAR[0x8404]))
+#define MCF_PCI_PCITTCR                      (*(volatile uint32_t*)(&_MBAR[0x8408]))
+#define MCF_PCI_PCITER                       (*(volatile uint32_t*)(&_MBAR[0x840C]))
+#define MCF_PCI_PCITNAR                      (*(volatile uint32_t*)(&_MBAR[0x8410]))
+#define MCF_PCI_PCITLWR                      (*(volatile uint32_t*)(&_MBAR[0x8414]))
+#define MCF_PCI_PCITDCR                      (*(volatile uint32_t*)(&_MBAR[0x8418]))
+#define MCF_PCI_PCITSR                       (*(volatile uint32_t*)(&_MBAR[0x841C]))
+#define MCF_PCI_PCITFDR                      (*(volatile uint32_t*)(&_MBAR[0x8440]))
+#define MCF_PCI_PCITFSR                      (*(volatile uint32_t*)(&_MBAR[0x8444]))
+#define MCF_PCI_PCITFCR                      (*(volatile uint32_t*)(&_MBAR[0x8448]))
+#define MCF_PCI_PCITFAR                      (*(volatile uint32_t*)(&_MBAR[0x844C]))
+#define MCF_PCI_PCITFRPR                     (*(volatile uint32_t*)(&_MBAR[0x8450]))
+#define MCF_PCI_PCITFWPR                     (*(volatile uint32_t*)(&_MBAR[0x8454]))
+#define MCF_PCI_PCIRPSR                      (*(volatile uint32_t*)(&_MBAR[0x8480]))
+#define MCF_PCI_PCIRSAR                      (*(volatile uint32_t*)(&_MBAR[0x8484]))
+#define MCF_PCI_PCIRTCR                      (*(volatile uint32_t*)(&_MBAR[0x8488]))
+#define MCF_PCI_PCIRER                       (*(volatile uint32_t*)(&_MBAR[0x848C]))
+#define MCF_PCI_PCIRNAR                      (*(volatile uint32_t*)(&_MBAR[0x8490]))
+#define MCF_PCI_PCIRDCR                      (*(volatile uint32_t*)(&_MBAR[0x8498]))
+#define MCF_PCI_PCIRSR                       (*(volatile uint32_t*)(&_MBAR[0x849C]))
+#define MCF_PCI_PCIRFDR                      (*(volatile uint32_t*)(&_MBAR[0x84C0]))
+#define MCF_PCI_PCIRFSR                      (*(volatile uint32_t*)(&_MBAR[0x84C4]))
+#define MCF_PCI_PCIRFCR                      (*(volatile uint32_t*)(&_MBAR[0x84C8]))
+#define MCF_PCI_PCIRFAR                      (*(volatile uint32_t*)(&_MBAR[0x84CC]))
+#define MCF_PCI_PCIRFRPR                     (*(volatile uint32_t*)(&_MBAR[0x84D0]))
+#define MCF_PCI_PCIRFWPR                     (*(volatile uint32_t*)(&_MBAR[0x84D4]))
+
+
+/* Bit definitions and macros for MCF_PCI_PCIIDR */
+#define MCF_PCI_PCIIDR_VENDORID(x)           (((x)&0xFFFF)<<0)
+#define MCF_PCI_PCIIDR_DEVICEID(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCISCR */
+#define MCF_PCI_PCISCR_IO                    (0x1)
+#define MCF_PCI_PCISCR_M                     (0x2)
+#define MCF_PCI_PCISCR_B                     (0x4)
+#define MCF_PCI_PCISCR_SP                    (0x8)
+#define MCF_PCI_PCISCR_MW                    (0x10)
+#define MCF_PCI_PCISCR_V                     (0x20)
+#define MCF_PCI_PCISCR_PER                   (0x40)
+#define MCF_PCI_PCISCR_ST                    (0x80)
+#define MCF_PCI_PCISCR_S                     (0x100)
+#define MCF_PCI_PCISCR_F                     (0x200)
+#define MCF_PCI_PCISCR_C                     (0x100000)
+#define MCF_PCI_PCISCR_66M                   (0x200000)
+#define MCF_PCI_PCISCR_R                     (0x400000)
+#define MCF_PCI_PCISCR_FC                    (0x800000)
+#define MCF_PCI_PCISCR_DP                    (0x1000000)
+#define MCF_PCI_PCISCR_DT(x)                 (((x)&0x3)<<0x19)
+#define MCF_PCI_PCISCR_TS                    (0x8000000)
+#define MCF_PCI_PCISCR_TR                    (0x10000000)
+#define MCF_PCI_PCISCR_MA                    (0x20000000)
+#define MCF_PCI_PCISCR_SE                    (0x40000000)
+#define MCF_PCI_PCISCR_PE                    (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCICCRIR */
+#define MCF_PCI_PCICCRIR_REVISIONID(x)       (((x)&0xFF)<<0)
+#define MCF_PCI_PCICCRIR_CLASSCODE(x)        (((x)&0xFFFFFF)<<0x8)
+
+/* Bit definitions and macros for MCF_PCI_PCICR1 */
+#define MCF_PCI_PCICR1_CACHELINESIZE(x)      (((x)&0xFF)<<0)
+#define MCF_PCI_PCICR1_LATTIMER(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCICR1_HEADERTYPE(x)         (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCICR1_BIST(x)               (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIBAR0 */
+#define MCF_PCI_PCIBAR0_IOM                  (0x1)
+#define MCF_PCI_PCIBAR0_RANGE(x)             (((x)&0x3)<<0x1)
+#define MCF_PCI_PCIBAR0_PREF                 (0x8)
+#define MCF_PCI_PCIBAR0_BAR0(x)              (((x)&0x3FFF)<<0x12)
+
+/* Bit definitions and macros for MCF_PCI_PCIBAR1 */
+#define MCF_PCI_PCIBAR1_IOM                  (0x1)
+#define MCF_PCI_PCIBAR1_RANGE(x)             (((x)&0x3)<<0x1)
+#define MCF_PCI_PCIBAR1_PREF                 (0x8)
+#define MCF_PCI_PCIBAR1_BAR1(x)              (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_PCI_PCICCPR */
+#define MCF_PCI_PCICCPR_PCICCP(x)            (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCISID */
+#define MCF_PCI_PCISID_VENDORID(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCICR2 */
+#define MCF_PCI_PCICR2_INTLINE(x)            (((x)&0xFF)<<0)
+#define MCF_PCI_PCICR2_INTPIN(x)             (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCICR2_MINGNT(x)             (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCICR2_MAXLAT(x)             (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIGSCR */
+#define MCF_PCI_PCIGSCR_PR                   (0x1)
+#define MCF_PCI_PCIGSCR_SEE                  (0x1000)
+#define MCF_PCI_PCIGSCR_PEE                  (0x2000)
+#define MCF_PCI_PCIGSCR_CLKINRESERVED(x)     (((x)&0x7)<<0x10)
+#define MCF_PCI_PCIGSCR_XLB2CLKIN(x)         (((x)&0x7)<<0x18)
+#define MCF_PCI_PCIGSCR_SE                   (0x10000000)
+#define MCF_PCI_PCIGSCR_PE                   (0x20000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITBATR0 */
+#define MCF_PCI_PCITBATR0_EN                 (0x1)
+#define MCF_PCI_PCITBATR0_BAT0(x)            (((x)&0x3FFF)<<0x12)
+
+/* Bit definitions and macros for MCF_PCI_PCITBATR1 */
+#define MCF_PCI_PCITBATR1_EN                 (0x1)
+#define MCF_PCI_PCITBATR1_BAT1(x)            (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_PCI_PCITCR */
+#define MCF_PCI_PCITCR_P                     (0x10000)
+#define MCF_PCI_PCITCR_LD                    (0x1000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */
+#define MCF_PCI_PCIIW0BTAR_WTA0(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCIIW0BTAR_WAM0(x)           (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIIW0BTAR_WBA0(x)           (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */
+#define MCF_PCI_PCIIW1BTAR_WTA1(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCIIW1BTAR_WAM1(x)           (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIIW1BTAR_WBA1(x)           (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */
+#define MCF_PCI_PCIIW2BTAR_WTA2(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCIIW2BTAR_WAM2(x)           (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIIW2BTAR_WBA2(x)           (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIIWCR */
+#define MCF_PCI_PCIIWCR_WINCTRL2_E           (0x100)
+#define MCF_PCI_PCIIWCR_WINCTRL2_PRC(x)      (((x)&0x3)<<0x9)
+#define MCF_PCI_PCIIWCR_WINCTRL2_IOM         (0x800)
+#define MCF_PCI_PCIIWCR_WINCTRL1_E           (0x10000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_PRC(x)      (((x)&0x3)<<0x11)
+#define MCF_PCI_PCIIWCR_WINCTRL1_IOM         (0x80000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_E           (0x1000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_PRC(x)      (((x)&0x3)<<0x19)
+#define MCF_PCI_PCIIWCR_WINCTRL0_IOM         (0x8000000)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD     (0x100)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE   (0x300)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL    (0x500)
+#define MCF_PCI_PCIIWCR_WINCTRL2_IO          (0x900)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD     (0x10000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE   (0x30000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL    (0x50000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_IO          (0x90000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD     (0x1000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE   (0x3000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL    (0x5000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_IO          (0x9000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIICR */
+#define MCF_PCI_PCIICR_MAXRETRY(x)           (((x)&0xFF)<<0)
+#define MCF_PCI_PCIICR_TAE                   (0x1000000)
+#define MCF_PCI_PCIICR_IAE                   (0x2000000)
+#define MCF_PCI_PCIICR_REE                   (0x4000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIISR */
+#define MCF_PCI_PCIISR_TA                    (0x1000000)
+#define MCF_PCI_PCIISR_IA                    (0x2000000)
+#define MCF_PCI_PCIISR_RE                    (0x4000000)
+
+/* Bit definitions and macros for MCF_PCI_PCICAR */
+#define MCF_PCI_PCICAR_DWORD(x)              (((x)&0x3F)<<0x2)
+#define MCF_PCI_PCICAR_FUNCNUM(x)            (((x)&0x7)<<0x8)
+#define MCF_PCI_PCICAR_DEVNUM(x)             (((x)&0x1F)<<0xB)
+#define MCF_PCI_PCICAR_BUSNUM(x)             (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCICAR_E                     (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITPSR */
+#define MCF_PCI_PCITPSR_PKTSIZE(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCITSAR */
+#define MCF_PCI_PCITSAR_STARTADD(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITTCR */
+#define MCF_PCI_PCITTCR_DI                   (0x1)
+#define MCF_PCI_PCITTCR_W                    (0x10)
+#define MCF_PCI_PCITTCR_MAXBEATS(x)          (((x)&0x7)<<0x8)
+#define MCF_PCI_PCITTCR_MAXRETRY(x)          (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCITTCR_PCICMD(x)            (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCITER */
+#define MCF_PCI_PCITER_NE                    (0x10000)
+#define MCF_PCI_PCITER_IAE                   (0x20000)
+#define MCF_PCI_PCITER_TAE                   (0x40000)
+#define MCF_PCI_PCITER_RE                    (0x80000)
+#define MCF_PCI_PCITER_SE                    (0x100000)
+#define MCF_PCI_PCITER_FEE                   (0x200000)
+#define MCF_PCI_PCITER_ME                    (0x1000000)
+#define MCF_PCI_PCITER_BE                    (0x8000000)
+#define MCF_PCI_PCITER_CM                    (0x10000000)
+#define MCF_PCI_PCITER_RF                    (0x40000000)
+#define MCF_PCI_PCITER_RC                    (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITNAR */
+#define MCF_PCI_PCITNAR_NEXTADDRESS(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITLWR */
+#define MCF_PCI_PCITLWR_LASTWORD(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITDCR */
+#define MCF_PCI_PCITDCR_PKTSDONE(x)          (((x)&0xFFFF)<<0)
+#define MCF_PCI_PCITDCR_BYTESDONE(x)         (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCITSR */
+#define MCF_PCI_PCITSR_IA                    (0x10000)
+#define MCF_PCI_PCITSR_TA                    (0x20000)
+#define MCF_PCI_PCITSR_RE                    (0x40000)
+#define MCF_PCI_PCITSR_SE                    (0x80000)
+#define MCF_PCI_PCITSR_FE                    (0x100000)
+#define MCF_PCI_PCITSR_BE1                   (0x200000)
+#define MCF_PCI_PCITSR_BE2                   (0x400000)
+#define MCF_PCI_PCITSR_BE3                   (0x800000)
+#define MCF_PCI_PCITSR_NT                    (0x1000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITFDR */
+#define MCF_PCI_PCITFDR_FIFODATAWORD(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITFSR */
+#define MCF_PCI_PCITFSR_EMPTY                (0x10000)
+#define MCF_PCI_PCITFSR_ALARM                (0x20000)
+#define MCF_PCI_PCITFSR_FULL                 (0x40000)
+#define MCF_PCI_PCITFSR_FR                   (0x80000)
+#define MCF_PCI_PCITFSR_OF                   (0x100000)
+#define MCF_PCI_PCITFSR_UF                   (0x200000)
+#define MCF_PCI_PCITFSR_RXW                  (0x400000)
+#define MCF_PCI_PCITFSR_FAE                  (0x800000)
+#define MCF_PCI_PCITFSR_TXW                  (0x40000000)
+#define MCF_PCI_PCITFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITFCR */
+#define MCF_PCI_PCITFCR_TXW_MASK             (0x40000)
+#define MCF_PCI_PCITFCR_OF_MASK              (0x80000)
+#define MCF_PCI_PCITFCR_UF_MASK              (0x100000)
+#define MCF_PCI_PCITFCR_RXW_MASK             (0x200000)
+#define MCF_PCI_PCITFCR_FAE_MASK             (0x400000)
+#define MCF_PCI_PCITFCR_IP_MASK              (0x800000)
+#define MCF_PCI_PCITFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PCI_PCITFCR_WFR                  (0x20000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITFAR */
+#define MCF_PCI_PCITFAR_ALARM(x)             (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITFRPR */
+#define MCF_PCI_PCITFRPR_READPTR(x)          (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITFWPR */
+#define MCF_PCI_PCITFWPR_WRITEPTR(x)         (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRPSR */
+#define MCF_PCI_PCIRPSR_PKTSIZE(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCIRSAR */
+#define MCF_PCI_PCIRSAR_STARTADD(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRTCR */
+#define MCF_PCI_PCIRTCR_DI                   (0x1)
+#define MCF_PCI_PCIRTCR_W                    (0x10)
+#define MCF_PCI_PCIRTCR_MAXBEATS(x)          (((x)&0x7)<<0x8)
+#define MCF_PCI_PCIRTCR_FB                   (0x1000)
+#define MCF_PCI_PCIRTCR_MAXRETRY(x)          (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIRTCR_PCICMD(x)            (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIRER */
+#define MCF_PCI_PCIRER_NE                    (0x10000)
+#define MCF_PCI_PCIRER_IAE                   (0x20000)
+#define MCF_PCI_PCIRER_TAE                   (0x40000)
+#define MCF_PCI_PCIRER_RE                    (0x80000)
+#define MCF_PCI_PCIRER_SE                    (0x100000)
+#define MCF_PCI_PCIRER_FEE                   (0x200000)
+#define MCF_PCI_PCIRER_ME                    (0x1000000)
+#define MCF_PCI_PCIRER_BE                    (0x8000000)
+#define MCF_PCI_PCIRER_CM                    (0x10000000)
+#define MCF_PCI_PCIRER_FE                    (0x20000000)
+#define MCF_PCI_PCIRER_RF                    (0x40000000)
+#define MCF_PCI_PCIRER_RC                    (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRNAR */
+#define MCF_PCI_PCIRNAR_NEXTADDRESS(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRDCR */
+#define MCF_PCI_PCIRDCR_PKTSDONE(x)          (((x)&0xFFFF)<<0)
+#define MCF_PCI_PCIRDCR_BYTESDONE(x)         (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCIRSR */
+#define MCF_PCI_PCIRSR_IA                    (0x10000)
+#define MCF_PCI_PCIRSR_TA                    (0x20000)
+#define MCF_PCI_PCIRSR_RE                    (0x40000)
+#define MCF_PCI_PCIRSR_SE                    (0x80000)
+#define MCF_PCI_PCIRSR_FE                    (0x100000)
+#define MCF_PCI_PCIRSR_BE1                   (0x200000)
+#define MCF_PCI_PCIRSR_BE2                   (0x400000)
+#define MCF_PCI_PCIRSR_BE3                   (0x800000)
+#define MCF_PCI_PCIRSR_NT                    (0x1000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFDR */
+#define MCF_PCI_PCIRFDR_FIFODATAWORD(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFSR */
+#define MCF_PCI_PCIRFSR_EMPTY                (0x10000)
+#define MCF_PCI_PCIRFSR_ALARM                (0x20000)
+#define MCF_PCI_PCIRFSR_FULL                 (0x40000)
+#define MCF_PCI_PCIRFSR_FR                   (0x80000)
+#define MCF_PCI_PCIRFSR_OF                   (0x100000)
+#define MCF_PCI_PCIRFSR_UF                   (0x200000)
+#define MCF_PCI_PCIRFSR_RXW                  (0x400000)
+#define MCF_PCI_PCIRFSR_FAE                  (0x800000)
+#define MCF_PCI_PCIRFSR_TXW                  (0x40000000)
+#define MCF_PCI_PCIRFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFCR */
+#define MCF_PCI_PCIRFCR_TXW_MASK             (0x40000)
+#define MCF_PCI_PCIRFCR_OF_MASK              (0x80000)
+#define MCF_PCI_PCIRFCR_UF_MASK              (0x100000)
+#define MCF_PCI_PCIRFCR_RXW_MASK             (0x200000)
+#define MCF_PCI_PCIRFCR_FAE_MASK             (0x400000)
+#define MCF_PCI_PCIRFCR_IP_MASK              (0x800000)
+#define MCF_PCI_PCIRFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PCI_PCIRFCR_WFR                  (0x20000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFAR */
+#define MCF_PCI_PCIRFAR_ALARM(x)             (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFRPR */
+#define MCF_PCI_PCIRFRPR_READPTR(x)          (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFWPR */
+#define MCF_PCI_PCIRFWPR_WRITEPTR(x)         (((x)&0x7F)<<0)
+
+
+#endif /* __MCF5475_PCI_H__ */

tos/fpga_test/include/MCF5475_PCIARB.h

@@ -0,0 +1,43 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PCIARB_H__
+#define __MCF5475_PCIARB_H__
+
+
+/*********************************************************************
+*
+* PCI Bus Arbiter Module (PCIARB)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PCIARB_PACR                      (*(volatile uint32_t*)(&_MBAR[0xC00]))
+#define MCF_PCIARB_PASR                      (*(volatile uint32_t*)(&_MBAR[0xC04]))
+
+
+/* Bit definitions and macros for MCF_PCIARB_PACR */
+#define MCF_PCIARB_PACR_INTMPRI              (0x1)
+#define MCF_PCIARB_PACR_EXTMPRI(x)           (((x)&0x1F)<<0x1)
+#define MCF_PCIARB_PACR_INTMINTEN            (0x10000)
+#define MCF_PCIARB_PACR_EXTMINTEN(x)         (((x)&0x1F)<<0x11)
+#define MCF_PCIARB_PACR_DS                   (0x80000000)
+
+/* Bit definitions and macros for MCF_PCIARB_PASR */
+#define MCF_PCIARB_PASR_ITLMBK               (0x10000)
+#define MCF_PCIARB_PASR_EXTMBK(x)            (((x)&0x1F)<<0x11)
+
+
+#endif /* __MCF5475_PCIARB_H__ */

tos/fpga_test/include/MCF5475_PSC.h

@@ -0,0 +1,527 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PSC_H__
+#define __MCF5475_PSC_H__
+
+
+/*********************************************************************
+*
+* Programmable Serial Controller (PSC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PSC0_PSCMR2                      (*(volatile uint8_t *)(&_MBAR[0x8600]))
+#define MCF_PSC0_PSCMR1                      (*(volatile uint8_t *)(&_MBAR[0x8600]))
+#define MCF_PSC0_PSCCSR                      (*(volatile uint8_t *)(&_MBAR[0x8604]))
+#define MCF_PSC0_PSCSR                       (*(volatile uint16_t*)(&_MBAR[0x8604]))
+#define MCF_PSC0_PSCCR                       (*(volatile uint8_t *)(&_MBAR[0x8608]))
+#define MCF_PSC0_PSCRB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCTB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCRB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCTB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCRB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCTB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCIPCR                     (*(volatile uint8_t *)(&_MBAR[0x8610]))
+#define MCF_PSC0_PSCACR                      (*(volatile uint8_t *)(&_MBAR[0x8610]))
+#define MCF_PSC0_PSCIMR                      (*(volatile uint16_t*)(&_MBAR[0x8614]))
+#define MCF_PSC0_PSCISR                      (*(volatile uint16_t*)(&_MBAR[0x8614]))
+#define MCF_PSC0_PSCCTUR                     (*(volatile uint8_t *)(&_MBAR[0x8618]))
+#define MCF_PSC0_PSCCTLR                     (*(volatile uint8_t *)(&_MBAR[0x861C]))
+#define MCF_PSC0_PSCIP                       (*(volatile uint8_t *)(&_MBAR[0x8634]))
+#define MCF_PSC0_PSCOPSET                    (*(volatile uint8_t *)(&_MBAR[0x8638]))
+#define MCF_PSC0_PSCOPRESET                  (*(volatile uint8_t *)(&_MBAR[0x863C]))
+#define MCF_PSC0_PSCSICR                     (*(volatile uint8_t *)(&_MBAR[0x8640]))
+#define MCF_PSC0_PSCIRCR1                    (*(volatile uint8_t *)(&_MBAR[0x8644]))
+#define MCF_PSC0_PSCIRCR2                    (*(volatile uint8_t *)(&_MBAR[0x8648]))
+#define MCF_PSC0_PSCIRSDR                    (*(volatile uint8_t *)(&_MBAR[0x864C]))
+#define MCF_PSC0_PSCIRMDR                    (*(volatile uint8_t *)(&_MBAR[0x8650]))
+#define MCF_PSC0_PSCIRFDR                    (*(volatile uint8_t *)(&_MBAR[0x8654]))
+#define MCF_PSC0_PSCRFCNT                    (*(volatile uint16_t*)(&_MBAR[0x8658]))
+#define MCF_PSC0_PSCTFCNT                    (*(volatile uint16_t*)(&_MBAR[0x865C]))
+#define MCF_PSC0_PSCRFDR                     (*(volatile uint32_t*)(&_MBAR[0x8660]))
+#define MCF_PSC0_PSCRFSR                     (*(volatile uint16_t*)(&_MBAR[0x8664]))
+#define MCF_PSC0_PSCRFCR                     (*(volatile uint32_t*)(&_MBAR[0x8668]))
+#define MCF_PSC0_PSCRFAR                     (*(volatile uint16_t*)(&_MBAR[0x866E]))
+#define MCF_PSC0_PSCRFRP                     (*(volatile uint16_t*)(&_MBAR[0x8672]))
+#define MCF_PSC0_PSCRFWP                     (*(volatile uint16_t*)(&_MBAR[0x8676]))
+#define MCF_PSC0_PSCRLRFP                    (*(volatile uint16_t*)(&_MBAR[0x867A]))
+#define MCF_PSC0_PSCRLWFP                    (*(volatile uint16_t*)(&_MBAR[0x867E]))
+#define MCF_PSC0_PSCTFDR                     (*(volatile uint32_t*)(&_MBAR[0x8680]))
+#define MCF_PSC0_PSCTFSR                     (*(volatile uint16_t*)(&_MBAR[0x8684]))
+#define MCF_PSC0_PSCTFCR                     (*(volatile uint32_t*)(&_MBAR[0x8688]))
+#define MCF_PSC0_PSCTFAR                     (*(volatile uint16_t*)(&_MBAR[0x868E]))
+#define MCF_PSC0_PSCTFRP                     (*(volatile uint16_t*)(&_MBAR[0x8692]))
+#define MCF_PSC0_PSCTFWP                     (*(volatile uint16_t*)(&_MBAR[0x8696]))
+#define MCF_PSC0_PSCTLRFP                    (*(volatile uint16_t*)(&_MBAR[0x869A]))
+#define MCF_PSC0_PSCTLWFP                    (*(volatile uint16_t*)(&_MBAR[0x869E]))
+
+#define MCF_PSC1_PSCMR2                      (*(volatile uint8_t *)(&_MBAR[0x8700]))
+#define MCF_PSC1_PSCMR1                      (*(volatile uint8_t *)(&_MBAR[0x8700]))
+#define MCF_PSC1_PSCCSR                      (*(volatile uint8_t *)(&_MBAR[0x8704]))
+#define MCF_PSC1_PSCSR                       (*(volatile uint16_t*)(&_MBAR[0x8704]))
+#define MCF_PSC1_PSCCR                       (*(volatile uint8_t *)(&_MBAR[0x8708]))
+#define MCF_PSC1_PSCRB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCTB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCRB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCTB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCRB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCTB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCIPCR                     (*(volatile uint8_t *)(&_MBAR[0x8710]))
+#define MCF_PSC1_PSCACR                      (*(volatile uint8_t *)(&_MBAR[0x8710]))
+#define MCF_PSC1_PSCIMR                      (*(volatile uint16_t*)(&_MBAR[0x8714]))
+#define MCF_PSC1_PSCISR                      (*(volatile uint16_t*)(&_MBAR[0x8714]))
+#define MCF_PSC1_PSCCTUR                     (*(volatile uint8_t *)(&_MBAR[0x8718]))
+#define MCF_PSC1_PSCCTLR                     (*(volatile uint8_t *)(&_MBAR[0x871C]))
+#define MCF_PSC1_PSCIP                       (*(volatile uint8_t *)(&_MBAR[0x8734]))
+#define MCF_PSC1_PSCOPSET                    (*(volatile uint8_t *)(&_MBAR[0x8738]))
+#define MCF_PSC1_PSCOPRESET                  (*(volatile uint8_t *)(&_MBAR[0x873C]))
+#define MCF_PSC1_PSCSICR                     (*(volatile uint8_t *)(&_MBAR[0x8740]))
+#define MCF_PSC1_PSCIRCR1                    (*(volatile uint8_t *)(&_MBAR[0x8744]))
+#define MCF_PSC1_PSCIRCR2                    (*(volatile uint8_t *)(&_MBAR[0x8748]))
+#define MCF_PSC1_PSCIRSDR                    (*(volatile uint8_t *)(&_MBAR[0x874C]))
+#define MCF_PSC1_PSCIRMDR                    (*(volatile uint8_t *)(&_MBAR[0x8750]))
+#define MCF_PSC1_PSCIRFDR                    (*(volatile uint8_t *)(&_MBAR[0x8754]))
+#define MCF_PSC1_PSCRFCNT                    (*(volatile uint16_t*)(&_MBAR[0x8758]))
+#define MCF_PSC1_PSCTFCNT                    (*(volatile uint16_t*)(&_MBAR[0x875C]))
+#define MCF_PSC1_PSCRFDR                     (*(volatile uint32_t*)(&_MBAR[0x8760]))
+#define MCF_PSC1_PSCRFSR                     (*(volatile uint16_t*)(&_MBAR[0x8764]))
+#define MCF_PSC1_PSCRFCR                     (*(volatile uint32_t*)(&_MBAR[0x8768]))
+#define MCF_PSC1_PSCRFAR                     (*(volatile uint16_t*)(&_MBAR[0x876E]))
+#define MCF_PSC1_PSCRFRP                     (*(volatile uint16_t*)(&_MBAR[0x8772]))
+#define MCF_PSC1_PSCRFWP                     (*(volatile uint16_t*)(&_MBAR[0x8776]))
+#define MCF_PSC1_PSCRLRFP                    (*(volatile uint16_t*)(&_MBAR[0x877A]))
+#define MCF_PSC1_PSCRLWFP                    (*(volatile uint16_t*)(&_MBAR[0x877E]))
+#define MCF_PSC1_PSCTFDR                     (*(volatile uint32_t*)(&_MBAR[0x8780]))
+#define MCF_PSC1_PSCTFSR                     (*(volatile uint16_t*)(&_MBAR[0x8784]))
+#define MCF_PSC1_PSCTFCR                     (*(volatile uint32_t*)(&_MBAR[0x8788]))
+#define MCF_PSC1_PSCTFAR                     (*(volatile uint16_t*)(&_MBAR[0x878E]))
+#define MCF_PSC1_PSCTFRP                     (*(volatile uint16_t*)(&_MBAR[0x8792]))
+#define MCF_PSC1_PSCTFWP                     (*(volatile uint16_t*)(&_MBAR[0x8796]))
+#define MCF_PSC1_PSCTLRFP                    (*(volatile uint16_t*)(&_MBAR[0x879A]))
+#define MCF_PSC1_PSCTLWFP                    (*(volatile uint16_t*)(&_MBAR[0x879E]))
+
+#define MCF_PSC2_PSCMR2                      (*(volatile uint8_t *)(&_MBAR[0x8800]))
+#define MCF_PSC2_PSCMR1                      (*(volatile uint8_t *)(&_MBAR[0x8800]))
+#define MCF_PSC2_PSCCSR                      (*(volatile uint8_t *)(&_MBAR[0x8804]))
+#define MCF_PSC2_PSCSR                       (*(volatile uint16_t*)(&_MBAR[0x8804]))
+#define MCF_PSC2_PSCCR                       (*(volatile uint8_t *)(&_MBAR[0x8808]))
+#define MCF_PSC2_PSCRB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCTB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCRB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCTB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCRB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCTB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCIPCR                     (*(volatile uint8_t *)(&_MBAR[0x8810]))
+#define MCF_PSC2_PSCACR                      (*(volatile uint8_t *)(&_MBAR[0x8810]))
+#define MCF_PSC2_PSCIMR                      (*(volatile uint16_t*)(&_MBAR[0x8814]))
+#define MCF_PSC2_PSCISR                      (*(volatile uint16_t*)(&_MBAR[0x8814]))
+#define MCF_PSC2_PSCCTUR                     (*(volatile uint8_t *)(&_MBAR[0x8818]))
+#define MCF_PSC2_PSCCTLR                     (*(volatile uint8_t *)(&_MBAR[0x881C]))
+#define MCF_PSC2_PSCIP                       (*(volatile uint8_t *)(&_MBAR[0x8834]))
+#define MCF_PSC2_PSCOPSET                    (*(volatile uint8_t *)(&_MBAR[0x8838]))
+#define MCF_PSC2_PSCOPRESET                  (*(volatile uint8_t *)(&_MBAR[0x883C]))
+#define MCF_PSC2_PSCSICR                     (*(volatile uint8_t *)(&_MBAR[0x8840]))
+#define MCF_PSC2_PSCIRCR1                    (*(volatile uint8_t *)(&_MBAR[0x8844]))
+#define MCF_PSC2_PSCIRCR2                    (*(volatile uint8_t *)(&_MBAR[0x8848]))
+#define MCF_PSC2_PSCIRSDR                    (*(volatile uint8_t *)(&_MBAR[0x884C]))
+#define MCF_PSC2_PSCIRMDR                    (*(volatile uint8_t *)(&_MBAR[0x8850]))
+#define MCF_PSC2_PSCIRFDR                    (*(volatile uint8_t *)(&_MBAR[0x8854]))
+#define MCF_PSC2_PSCRFCNT                    (*(volatile uint16_t*)(&_MBAR[0x8858]))
+#define MCF_PSC2_PSCTFCNT                    (*(volatile uint16_t*)(&_MBAR[0x885C]))
+#define MCF_PSC2_PSCRFDR                     (*(volatile uint32_t*)(&_MBAR[0x8860]))
+#define MCF_PSC2_PSCRFSR                     (*(volatile uint16_t*)(&_MBAR[0x8864]))
+#define MCF_PSC2_PSCRFCR                     (*(volatile uint32_t*)(&_MBAR[0x8868]))
+#define MCF_PSC2_PSCRFAR                     (*(volatile uint16_t*)(&_MBAR[0x886E]))
+#define MCF_PSC2_PSCRFRP                     (*(volatile uint16_t*)(&_MBAR[0x8872]))
+#define MCF_PSC2_PSCRFWP                     (*(volatile uint16_t*)(&_MBAR[0x8876]))
+#define MCF_PSC2_PSCRLRFP                    (*(volatile uint16_t*)(&_MBAR[0x887A]))
+#define MCF_PSC2_PSCRLWFP                    (*(volatile uint16_t*)(&_MBAR[0x887E]))
+#define MCF_PSC2_PSCTFDR                     (*(volatile uint32_t*)(&_MBAR[0x8880]))
+#define MCF_PSC2_PSCTFSR                     (*(volatile uint16_t*)(&_MBAR[0x8884]))
+#define MCF_PSC2_PSCTFCR                     (*(volatile uint32_t*)(&_MBAR[0x8888]))
+#define MCF_PSC2_PSCTFAR                     (*(volatile uint16_t*)(&_MBAR[0x888E]))
+#define MCF_PSC2_PSCTFRP                     (*(volatile uint16_t*)(&_MBAR[0x8892]))
+#define MCF_PSC2_PSCTFWP                     (*(volatile uint16_t*)(&_MBAR[0x8896]))
+#define MCF_PSC2_PSCTLRFP                    (*(volatile uint16_t*)(&_MBAR[0x889A]))
+#define MCF_PSC2_PSCTLWFP                    (*(volatile uint16_t*)(&_MBAR[0x889E]))
+
+#define MCF_PSC3_PSCMR2                      (*(volatile uint8_t *)(&_MBAR[0x8900]))
+#define MCF_PSC3_PSCMR1                      (*(volatile uint8_t *)(&_MBAR[0x8900]))
+#define MCF_PSC3_PSCCSR                      (*(volatile uint8_t *)(&_MBAR[0x8904]))
+#define MCF_PSC3_PSCSR                       (*(volatile uint16_t*)(&_MBAR[0x8904]))
+#define MCF_PSC3_PSCCR                       (*(volatile uint8_t *)(&_MBAR[0x8908]))
+#define MCF_PSC3_PSCRB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCTB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCRB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCTB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCRB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCTB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCIPCR                     (*(volatile uint8_t *)(&_MBAR[0x8910]))
+#define MCF_PSC3_PSCACR                      (*(volatile uint8_t *)(&_MBAR[0x8910]))
+#define MCF_PSC3_PSCIMR                      (*(volatile uint16_t*)(&_MBAR[0x8914]))
+#define MCF_PSC3_PSCISR                      (*(volatile uint16_t*)(&_MBAR[0x8914]))
+#define MCF_PSC3_PSCCTUR                     (*(volatile uint8_t *)(&_MBAR[0x8918]))
+#define MCF_PSC3_PSCCTLR                     (*(volatile uint8_t *)(&_MBAR[0x891C]))
+#define MCF_PSC3_PSCIP                       (*(volatile uint8_t *)(&_MBAR[0x8934]))
+#define MCF_PSC3_PSCOPSET                    (*(volatile uint8_t *)(&_MBAR[0x8938]))
+#define MCF_PSC3_PSCOPRESET                  (*(volatile uint8_t *)(&_MBAR[0x893C]))
+#define MCF_PSC3_PSCSICR                     (*(volatile uint8_t *)(&_MBAR[0x8940]))
+#define MCF_PSC3_PSCIRCR1                    (*(volatile uint8_t *)(&_MBAR[0x8944]))
+#define MCF_PSC3_PSCIRCR2                    (*(volatile uint8_t *)(&_MBAR[0x8948]))
+#define MCF_PSC3_PSCIRSDR                    (*(volatile uint8_t *)(&_MBAR[0x894C]))
+#define MCF_PSC3_PSCIRMDR                    (*(volatile uint8_t *)(&_MBAR[0x8950]))
+#define MCF_PSC3_PSCIRFDR                    (*(volatile uint8_t *)(&_MBAR[0x8954]))
+#define MCF_PSC3_PSCRFCNT                    (*(volatile uint16_t*)(&_MBAR[0x8958]))
+#define MCF_PSC3_PSCTFCNT                    (*(volatile uint16_t*)(&_MBAR[0x895C]))
+#define MCF_PSC3_PSCRFDR                     (*(volatile uint32_t*)(&_MBAR[0x8960]))
+#define MCF_PSC3_PSCRFSR                     (*(volatile uint16_t*)(&_MBAR[0x8964]))
+#define MCF_PSC3_PSCRFCR                     (*(volatile uint32_t*)(&_MBAR[0x8968]))
+#define MCF_PSC3_PSCRFAR                     (*(volatile uint16_t*)(&_MBAR[0x896E]))
+#define MCF_PSC3_PSCRFRP                     (*(volatile uint16_t*)(&_MBAR[0x8972]))
+#define MCF_PSC3_PSCRFWP                     (*(volatile uint16_t*)(&_MBAR[0x8976]))
+#define MCF_PSC3_PSCRLRFP                    (*(volatile uint16_t*)(&_MBAR[0x897A]))
+#define MCF_PSC3_PSCRLWFP                    (*(volatile uint16_t*)(&_MBAR[0x897E]))
+#define MCF_PSC3_PSCTFDR                     (*(volatile uint32_t*)(&_MBAR[0x8980]))
+#define MCF_PSC3_PSCTFSR                     (*(volatile uint16_t*)(&_MBAR[0x8984]))
+#define MCF_PSC3_PSCTFCR                     (*(volatile uint32_t*)(&_MBAR[0x8988]))
+#define MCF_PSC3_PSCTFAR                     (*(volatile uint16_t*)(&_MBAR[0x898E]))
+#define MCF_PSC3_PSCTFRP                     (*(volatile uint16_t*)(&_MBAR[0x8992]))
+#define MCF_PSC3_PSCTFWP                     (*(volatile uint16_t*)(&_MBAR[0x8996]))
+#define MCF_PSC3_PSCTLRFP                    (*(volatile uint16_t*)(&_MBAR[0x899A]))
+#define MCF_PSC3_PSCTLWFP                    (*(volatile uint16_t*)(&_MBAR[0x899E]))
+
+#define MCF_PSC_PSCMR(x)                     (*(volatile uint8_t *)(&_MBAR[0x8600 + ((x)*0x100)]))
+#define MCF_PSC_PSCCSR(x)                    (*(volatile uint8_t *)(&_MBAR[0x8604 + ((x)*0x100)]))
+#define MCF_PSC_PSCSR(x)                     (*(volatile uint16_t*)(&_MBAR[0x8604 + ((x)*0x100)]))
+#define MCF_PSC_PSCCR(x)                     (*(volatile uint8_t *)(&_MBAR[0x8608 + ((x)*0x100)]))
+#define MCF_PSC_PSCRB_8BIT(x)                (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCTB_8BIT(x)                (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCRB_16BIT(x)               (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCTB_16BIT(x)               (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCRB_AC97(x)                (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCTB_AC97(x)                (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCIPCR(x)                   (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)]))
+#define MCF_PSC_PSCACR(x)                    (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)]))
+#define MCF_PSC_PSCIMR(x)                    (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)]))
+#define MCF_PSC_PSCISR(x)                    (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)]))
+#define MCF_PSC_PSCCTUR(x)                   (*(volatile uint8_t *)(&_MBAR[0x8618 + ((x)*0x100)]))
+#define MCF_PSC_PSCCTLR(x)                   (*(volatile uint8_t *)(&_MBAR[0x861C + ((x)*0x100)]))
+#define MCF_PSC_PSCIP(x)                     (*(volatile uint8_t *)(&_MBAR[0x8634 + ((x)*0x100)]))
+#define MCF_PSC_PSCOPSET(x)                  (*(volatile uint8_t *)(&_MBAR[0x8638 + ((x)*0x100)]))
+#define MCF_PSC_PSCOPRESET(x)                (*(volatile uint8_t *)(&_MBAR[0x863C + ((x)*0x100)]))
+#define MCF_PSC_PSCSICR(x)                   (*(volatile uint8_t *)(&_MBAR[0x8640 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRCR1(x)                  (*(volatile uint8_t *)(&_MBAR[0x8644 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRCR2(x)                  (*(volatile uint8_t *)(&_MBAR[0x8648 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRSDR(x)                  (*(volatile uint8_t *)(&_MBAR[0x864C + ((x)*0x100)]))
+#define MCF_PSC_PSCIRMDR(x)                  (*(volatile uint8_t *)(&_MBAR[0x8650 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRFDR(x)                  (*(volatile uint8_t *)(&_MBAR[0x8654 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFCNT(x)                  (*(volatile uint16_t*)(&_MBAR[0x8658 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFCNT(x)                  (*(volatile uint16_t*)(&_MBAR[0x865C + ((x)*0x100)]))
+#define MCF_PSC_PSCRFDR(x)                   (*(volatile uint32_t*)(&_MBAR[0x8660 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFSR(x)                   (*(volatile uint16_t*)(&_MBAR[0x8664 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFCR(x)                   (*(volatile uint32_t*)(&_MBAR[0x8668 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFAR(x)                   (*(volatile uint16_t*)(&_MBAR[0x866E + ((x)*0x100)]))
+#define MCF_PSC_PSCRFRP(x)                   (*(volatile uint16_t*)(&_MBAR[0x8672 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFWP(x)                   (*(volatile uint16_t*)(&_MBAR[0x8676 + ((x)*0x100)]))
+#define MCF_PSC_PSCRLRFP(x)                  (*(volatile uint16_t*)(&_MBAR[0x867A + ((x)*0x100)]))
+#define MCF_PSC_PSCRLWFP(x)                  (*(volatile uint16_t*)(&_MBAR[0x867E + ((x)*0x100)]))
+#define MCF_PSC_PSCTFDR(x)                   (*(volatile uint32_t*)(&_MBAR[0x8680 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFSR(x)                   (*(volatile uint16_t*)(&_MBAR[0x8684 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFCR(x)                   (*(volatile uint32_t*)(&_MBAR[0x8688 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFAR(x)                   (*(volatile uint16_t*)(&_MBAR[0x868E + ((x)*0x100)]))
+#define MCF_PSC_PSCTFRP(x)                   (*(volatile uint16_t*)(&_MBAR[0x8692 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFWP(x)                   (*(volatile uint16_t*)(&_MBAR[0x8696 + ((x)*0x100)]))
+#define MCF_PSC_PSCTLRFP(x)                  (*(volatile uint16_t*)(&_MBAR[0x869A + ((x)*0x100)]))
+#define MCF_PSC_PSCTLWFP(x)                  (*(volatile uint16_t*)(&_MBAR[0x869E + ((x)*0x100)]))
+
+/* Bit definitions and macros for MCF_PSC_PSCMR */
+#define MCF_PSC_PSCMR_SB(x)                  (((x)&0xF)<<0)
+#define MCF_PSC_PSCMR_TXCTS                  (0x10)
+#define MCF_PSC_PSCMR_TXRTS                  (0x20)
+#define MCF_PSC_PSCMR_CM(x)                  (((x)&0x3)<<0x6)
+#define MCF_PSC_PSCMR_CM_NORMAL              (0)
+#define MCF_PSC_PSCMR_CM_ECHO                (0x40)
+#define MCF_PSC_PSCMR_CM_LOCAL_LOOP          (0x80)
+#define MCF_PSC_PSCMR_CM_REMOTE_LOOP         (0xC0)
+#define MCF_PSC_PSCMR_SB_STOP_BITS_1         (0x7)
+#define MCF_PSC_PSCMR_SB_STOP_BITS_15        (0x8)
+#define MCF_PSC_PSCMR_SB_STOP_BITS_2         (0xF)
+#define MCF_PSC_PSCMR_PM_MULTI_ADDR          (0x1C)
+#define MCF_PSC_PSCMR_PM_MULTI_DATA          (0x18)
+#define MCF_PSC_PSCMR_PM_NONE                (0x10)
+#define MCF_PSC_PSCMR_PM_FORCE_HI            (0xC)
+#define MCF_PSC_PSCMR_PM_FORCE_LO            (0x8)
+#define MCF_PSC_PSCMR_PM_ODD                 (0x4)
+#define MCF_PSC_PSCMR_PM_EVEN                (0)
+#define MCF_PSC_PSCMR_BC(x)                  (((x)&0x3)<<0)
+#define MCF_PSC_PSCMR_BC_5                   (0)
+#define MCF_PSC_PSCMR_BC_6                   (0x1)
+#define MCF_PSC_PSCMR_BC_7                   (0x2)
+#define MCF_PSC_PSCMR_BC_8                   (0x3)
+#define MCF_PSC_PSCMR_PT                     (0x4)
+#define MCF_PSC_PSCMR_PM(x)                  (((x)&0x3)<<0x3)
+#define MCF_PSC_PSCMR_ERR                    (0x20)
+#define MCF_PSC_PSCMR_RXIRQ_FU               (0x40)
+#define MCF_PSC_PSCMR_RXRTS                  (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCCSR */
+#define MCF_PSC_PSCCSR_TCSEL(x)              (((x)&0xF)<<0)
+#define MCF_PSC_PSCCSR_RCSEL(x)              (((x)&0xF)<<0x4)
+#define MCF_PSC_PSCCSR_TCSEL_SYS_CLK         (0x0D)
+#define MCF_PSC_PSCCSR_TCSEL_CTM16           (0x0E)
+#define MCF_PSC_PSCCSR_TCSEL_CTM             (0x0F)
+#define MCF_PSC_PSCCSR_RCSEL_SYS_CLK         (0xD0)
+#define MCF_PSC_PSCCSR_RCSEL_CTM16           (0xE0)
+#define MCF_PSC_PSCCSR_RCSEL_CTM             (0xF0)
+
+/* Bit definitions and macros for MCF_PSC_PSCSR */
+#define MCF_PSC_PSCSR_ERR                    (0x40)
+#define MCF_PSC_PSCSR_CDE_DEOF               (0x80)
+#define MCF_PSC_PSCSR_RXRDY                  (0x100)
+#define MCF_PSC_PSCSR_FU                     (0x200)
+#define MCF_PSC_PSCSR_TXRDY                  (0x400)
+#define MCF_PSC_PSCSR_TXEMP_URERR            (0x800)
+#define MCF_PSC_PSCSR_OE                     (0x1000)
+#define MCF_PSC_PSCSR_PE_CRCERR              (0x2000)
+#define MCF_PSC_PSCSR_FE_PHYERR              (0x4000)
+#define MCF_PSC_PSCSR_RB_NEOF                (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCCR */
+#define MCF_PSC_PSCCR_RXC(x)                 (((x)&0x3)<<0)
+#define MCF_PSC_PSCCR_RX_ENABLED             (0x1)
+#define MCF_PSC_PSCCR_RX_DISABLED            (0x2)
+#define MCF_PSC_PSCCR_TXC(x)                 (((x)&0x3)<<0x2)
+#define MCF_PSC_PSCCR_TX_ENABLED             (0x4)
+#define MCF_PSC_PSCCR_TX_DISABLED            (0x8)
+#define MCF_PSC_PSCCR_MISC(x)                (((x)&0x7)<<0x4)
+#define MCF_PSC_PSCCR_NONE                   (0)
+#define MCF_PSC_PSCCR_RESET_MR               (0x10)
+#define MCF_PSC_PSCCR_RESET_RX               (0x20)
+#define MCF_PSC_PSCCR_RESET_TX               (0x30)
+#define MCF_PSC_PSCCR_RESET_ERROR            (0x40)
+#define MCF_PSC_PSCCR_RESET_BKCHGINT         (0x50)
+#define MCF_PSC_PSCCR_START_BREAK            (0x60)
+#define MCF_PSC_PSCCR_STOP_BREAK             (0x70)
+
+/* Bit definitions and macros for MCF_PSC_PSCRB_8BIT */
+#define MCF_PSC_PSCRB_8BIT_RB3(x)            (((x)&0xFF)<<0)
+#define MCF_PSC_PSCRB_8BIT_RB2(x)            (((x)&0xFF)<<0x8)
+#define MCF_PSC_PSCRB_8BIT_RB1(x)            (((x)&0xFF)<<0x10)
+#define MCF_PSC_PSCRB_8BIT_RB0(x)            (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PSC_PSCTB_8BIT */
+#define MCF_PSC_PSCTB_8BIT_TB3(x)            (((x)&0xFF)<<0)
+#define MCF_PSC_PSCTB_8BIT_TB2(x)            (((x)&0xFF)<<0x8)
+#define MCF_PSC_PSCTB_8BIT_TB1(x)            (((x)&0xFF)<<0x10)
+#define MCF_PSC_PSCTB_8BIT_TB0(x)            (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PSC_PSCRB_16BIT */
+#define MCF_PSC_PSCRB_16BIT_RB1(x)           (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCRB_16BIT_RB0(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PSC_PSCTB_16BIT */
+#define MCF_PSC_PSCTB_16BIT_TB1(x)           (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCTB_16BIT_TB0(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PSC_PSCRB_AC97 */
+#define MCF_PSC_PSCRB_AC97_SOF               (0x800)
+#define MCF_PSC_PSCRB_AC97_RB(x)             (((x)&0xFFFFF)<<0xC)
+
+/* Bit definitions and macros for MCF_PSC_PSCTB_AC97 */
+#define MCF_PSC_PSCTB_AC97_TB(x)             (((x)&0xFFFFF)<<0xC)
+
+/* Bit definitions and macros for MCF_PSC_PSCIPCR */
+#define MCF_PSC_PSCIPCR_RESERVED             (0xC)
+#define MCF_PSC_PSCIPCR_CTS                  (0xD)
+#define MCF_PSC_PSCIPCR_D_CTS                (0x1C)
+#define MCF_PSC_PSCIPCR_SYNC                 (0x8C)
+
+/* Bit definitions and macros for MCF_PSC_PSCACR */
+#define MCF_PSC_PSCACR_IEC0                  (0x1)
+
+/* Bit definitions and macros for MCF_PSC_PSCIMR */
+#define MCF_PSC_PSCIMR_ERR                   (0x40)
+#define MCF_PSC_PSCIMR_DEOF                  (0x80)
+#define MCF_PSC_PSCIMR_TXRDY                 (0x100)
+#define MCF_PSC_PSCIMR_RXRDY_FU              (0x200)
+#define MCF_PSC_PSCIMR_DB                    (0x400)
+#define MCF_PSC_PSCIMR_IPC                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCISR */
+#define MCF_PSC_PSCISR_ERR                   (0x40)
+#define MCF_PSC_PSCISR_DEOF                  (0x80)
+#define MCF_PSC_PSCISR_TXRDY                 (0x100)
+#define MCF_PSC_PSCISR_RXRDY_FU              (0x200)
+#define MCF_PSC_PSCISR_DB                    (0x400)
+#define MCF_PSC_PSCISR_IPC                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCCTUR */
+#define MCF_PSC_PSCCTUR_CT(x)                (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCCTLR */
+#define MCF_PSC_PSCCTLR_CT(x)                (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCIP */
+#define MCF_PSC_PSCIP_CTS                    (0x1)
+#define MCF_PSC_PSCIP_TGL                    (0x40)
+#define MCF_PSC_PSCIP_LPWR_B                 (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCOPSET */
+#define MCF_PSC_PSCOPSET_RTS                 (0x1)
+
+/* Bit definitions and macros for MCF_PSC_PSCOPRESET */
+#define MCF_PSC_PSCOPRESET_RTS               (0x1)
+
+/* Bit definitions and macros for MCF_PSC_PSCSICR */
+#define MCF_PSC_PSCSICR_SIM(x)               (((x)&0x7)<<0)
+#define MCF_PSC_PSCSICR_SIM_UART             (0)
+#define MCF_PSC_PSCSICR_SIM_MODEM8           (0x1)
+#define MCF_PSC_PSCSICR_SIM_MODEM16          (0x2)
+#define MCF_PSC_PSCSICR_SIM_AC97             (0x3)
+#define MCF_PSC_PSCSICR_SIM_SIR              (0x4)
+#define MCF_PSC_PSCSICR_SIM_MIR              (0x5)
+#define MCF_PSC_PSCSICR_SIM_FIR              (0x6)
+#define MCF_PSC_PSCSICR_SHDIR                (0x10)
+#define MCF_PSC_PSCSICR_DTS1                 (0x20)
+#define MCF_PSC_PSCSICR_AWR                  (0x40)
+#define MCF_PSC_PSCSICR_ACRB                 (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRCR1 */
+#define MCF_PSC_PSCIRCR1_SPUL                (0x1)
+#define MCF_PSC_PSCIRCR1_SIPEN               (0x2)
+#define MCF_PSC_PSCIRCR1_FD                  (0x4)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRCR2 */
+#define MCF_PSC_PSCIRCR2_NXTEOF              (0x1)
+#define MCF_PSC_PSCIRCR2_ABORT               (0x2)
+#define MCF_PSC_PSCIRCR2_SIPREQ              (0x4)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRSDR */
+#define MCF_PSC_PSCIRSDR_IRSTIM(x)           (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRMDR */
+#define MCF_PSC_PSCIRMDR_M_FDIV(x)           (((x)&0x7F)<<0)
+#define MCF_PSC_PSCIRMDR_FREQ                (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRFDR */
+#define MCF_PSC_PSCIRFDR_F_FDIV(x)           (((x)&0xF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFCNT */
+#define MCF_PSC_PSCRFCNT_CNT(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFCNT */
+#define MCF_PSC_PSCTFCNT_CNT(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFDR */
+#define MCF_PSC_PSCRFDR_DATA(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFSR */
+#define MCF_PSC_PSCRFSR_EMT                  (0x1)
+#define MCF_PSC_PSCRFSR_ALARM                (0x2)
+#define MCF_PSC_PSCRFSR_FU                   (0x4)
+#define MCF_PSC_PSCRFSR_FRMRDY               (0x8)
+#define MCF_PSC_PSCRFSR_OF                   (0x10)
+#define MCF_PSC_PSCRFSR_UF                   (0x20)
+#define MCF_PSC_PSCRFSR_RXW                  (0x40)
+#define MCF_PSC_PSCRFSR_FAE                  (0x80)
+#define MCF_PSC_PSCRFSR_FRM(x)               (((x)&0xF)<<0x8)
+#define MCF_PSC_PSCRFSR_FRM_BYTE0            (0x800)
+#define MCF_PSC_PSCRFSR_FRM_BYTE1            (0x400)
+#define MCF_PSC_PSCRFSR_FRM_BYTE2            (0x200)
+#define MCF_PSC_PSCRFSR_FRM_BYTE3            (0x100)
+#define MCF_PSC_PSCRFSR_TAG(x)               (((x)&0x3)<<0xC)
+#define MCF_PSC_PSCRFSR_TXW                  (0x4000)
+#define MCF_PSC_PSCRFSR_IP                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFCR */
+#define MCF_PSC_PSCRFCR_CNTR(x)              (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCRFCR_TXW_MSK              (0x40000)
+#define MCF_PSC_PSCRFCR_OF_MSK               (0x80000)
+#define MCF_PSC_PSCRFCR_UF_MSK               (0x100000)
+#define MCF_PSC_PSCRFCR_RXW_MSK              (0x200000)
+#define MCF_PSC_PSCRFCR_FAE_MSK              (0x400000)
+#define MCF_PSC_PSCRFCR_IP_MSK               (0x800000)
+#define MCF_PSC_PSCRFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PSC_PSCRFCR_FRMEN                (0x8000000)
+#define MCF_PSC_PSCRFCR_TIMER                (0x10000000)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFAR */
+#define MCF_PSC_PSCRFAR_ALARM(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFRP */
+#define MCF_PSC_PSCRFRP_READ(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFWP */
+#define MCF_PSC_PSCRFWP_WRITE(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRLRFP */
+#define MCF_PSC_PSCRLRFP_LRFP(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRLWFP */
+#define MCF_PSC_PSCRLWFP_LWFP(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFDR */
+#define MCF_PSC_PSCTFDR_DATA(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFSR */
+#define MCF_PSC_PSCTFSR_EMT                  (0x1)
+#define MCF_PSC_PSCTFSR_ALARM                (0x2)
+#define MCF_PSC_PSCTFSR_FU                   (0x4)
+#define MCF_PSC_PSCTFSR_FRMRDY               (0x8)
+#define MCF_PSC_PSCTFSR_OF                   (0x10)
+#define MCF_PSC_PSCTFSR_UF                   (0x20)
+#define MCF_PSC_PSCTFSR_RXW                  (0x40)
+#define MCF_PSC_PSCTFSR_FAE                  (0x80)
+#define MCF_PSC_PSCTFSR_FRM(x)               (((x)&0xF)<<0x8)
+#define MCF_PSC_PSCTFSR_FRM_BYTE0            (0x800)
+#define MCF_PSC_PSCTFSR_FRM_BYTE1            (0x400)
+#define MCF_PSC_PSCTFSR_FRM_BYTE2            (0x200)
+#define MCF_PSC_PSCTFSR_FRM_BYTE3            (0x100)
+#define MCF_PSC_PSCTFSR_TAG(x)               (((x)&0x3)<<0xC)
+#define MCF_PSC_PSCTFSR_TXW                  (0x4000)
+#define MCF_PSC_PSCTFSR_IP                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFCR */
+#define MCF_PSC_PSCTFCR_CNTR(x)              (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCTFCR_TXW_MSK              (0x40000)
+#define MCF_PSC_PSCTFCR_OF_MSK               (0x80000)
+#define MCF_PSC_PSCTFCR_UF_MSK               (0x100000)
+#define MCF_PSC_PSCTFCR_RXW_MSK              (0x200000)
+#define MCF_PSC_PSCTFCR_FAE_MSK              (0x400000)
+#define MCF_PSC_PSCTFCR_IP_MSK               (0x800000)
+#define MCF_PSC_PSCTFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PSC_PSCTFCR_FRMEN                (0x8000000)
+#define MCF_PSC_PSCTFCR_TIMER                (0x10000000)
+#define MCF_PSC_PSCTFCR_WFR                  (0x20000000)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFAR */
+#define MCF_PSC_PSCTFAR_ALARM(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFRP */
+#define MCF_PSC_PSCTFRP_READ(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFWP */
+#define MCF_PSC_PSCTFWP_WRITE(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTLRFP */
+#define MCF_PSC_PSCTLRFP_LRFP(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTLWFP */
+#define MCF_PSC_PSCTLWFP_LWFP(x)             (((x)&0x1FF)<<0)
+
+
+#endif /* __MCF5475_PSC_H__ */

tos/fpga_test/include/MCF5475_SDRAMC.h

@@ -0,0 +1,106 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SDRAMC_H__
+#define __MCF5475_SDRAMC_H__
+
+
+/*********************************************************************
+*
+* Synchronous DRAM Controller (SDRAMC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SDRAMC_SDRAMDS                   (*(volatile uint32_t*)(&_MBAR[0x4]))
+#define MCF_SDRAMC_CS0CFG                    (*(volatile uint32_t*)(&_MBAR[0x20]))
+#define MCF_SDRAMC_CS1CFG                    (*(volatile uint32_t*)(&_MBAR[0x24]))
+#define MCF_SDRAMC_CS2CFG                    (*(volatile uint32_t*)(&_MBAR[0x28]))
+#define MCF_SDRAMC_CS3CFG                    (*(volatile uint32_t*)(&_MBAR[0x2C]))
+#define MCF_SDRAMC_SDMR                      (*(volatile uint32_t*)(&_MBAR[0x100]))
+#define MCF_SDRAMC_SDCR                      (*(volatile uint32_t*)(&_MBAR[0x104]))
+#define MCF_SDRAMC_SDCFG1                    (*(volatile uint32_t*)(&_MBAR[0x108]))
+#define MCF_SDRAMC_SDCFG2                    (*(volatile uint32_t*)(&_MBAR[0x10C]))
+#define MCF_SDRAMC_CSCFG(x)                  (*(volatile uint32_t*)(&_MBAR[0x20 + ((x)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */
+#define MCF_SDRAMC_SDRAMDS_SB_D(x)           (((x)&0x3)<<0)
+#define MCF_SDRAMC_SDRAMDS_SB_S(x)           (((x)&0x3)<<0x2)
+#define MCF_SDRAMC_SDRAMDS_SB_A(x)           (((x)&0x3)<<0x4)
+#define MCF_SDRAMC_SDRAMDS_SB_C(x)           (((x)&0x3)<<0x6)
+#define MCF_SDRAMC_SDRAMDS_SB_E(x)           (((x)&0x3)<<0x8)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA        (0)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA        (0x1)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA         (0x2)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE        (0x3)
+
+/* Bit definitions and macros for MCF_SDRAMC_CSCFG */
+#define MCF_SDRAMC_CSCFG_CSSZ(x)             (((x)&0x1F)<<0)
+#define MCF_SDRAMC_CSCFG_CSSZ_DISABLED       (0)
+#define MCF_SDRAMC_CSCFG_CSSZ_1MBYTE         (0x13)
+#define MCF_SDRAMC_CSCFG_CSSZ_2MBYTE         (0x14)
+#define MCF_SDRAMC_CSCFG_CSSZ_4MBYTE         (0x15)
+#define MCF_SDRAMC_CSCFG_CSSZ_8MBYTE         (0x16)
+#define MCF_SDRAMC_CSCFG_CSSZ_16MBYTE        (0x17)
+#define MCF_SDRAMC_CSCFG_CSSZ_32MBYTE        (0x18)
+#define MCF_SDRAMC_CSCFG_CSSZ_64MBYTE        (0x19)
+#define MCF_SDRAMC_CSCFG_CSSZ_128MBYTE       (0x1A)
+#define MCF_SDRAMC_CSCFG_CSSZ_256MBYTE       (0x1B)
+#define MCF_SDRAMC_CSCFG_CSSZ_512MBYTE       (0x1C)
+#define MCF_SDRAMC_CSCFG_CSSZ_1GBYTE         (0x1D)
+#define MCF_SDRAMC_CSCFG_CSSZ_2GBYTE         (0x1E)
+#define MCF_SDRAMC_CSCFG_CSSZ_4GBYTE         (0x1F)
+#define MCF_SDRAMC_CSCFG_CSBA(x)             (((x)&0xFFF)<<0x14)
+#define MCF_SDRAMC_CSCFG_BA(x)               ((x)&0xFFF00000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDMR */
+#define MCF_SDRAMC_SDMR_CMD                  (0x10000)
+#define MCF_SDRAMC_SDMR_AD(x)                (((x)&0xFFF)<<0x12)
+#define MCF_SDRAMC_SDMR_BNKAD(x)             (((x)&0x3)<<0x1E)
+#define MCF_SDRAMC_SDMR_BK_LMR               (0)
+#define MCF_SDRAMC_SDMR_BK_LEMR              (0x40000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCR */
+#define MCF_SDRAMC_SDCR_IPALL                (0x2)
+#define MCF_SDRAMC_SDCR_IREF                 (0x4)
+#define MCF_SDRAMC_SDCR_BUFF                 (0x10)
+#define MCF_SDRAMC_SDCR_DQS_OE(x)            (((x)&0xF)<<0x8)
+#define MCF_SDRAMC_SDCR_RCNT(x)              (((x)&0x3F)<<0x10)
+#define MCF_SDRAMC_SDCR_DRIVE                (0x400000)
+#define MCF_SDRAMC_SDCR_AP                   (0x800000)
+#define MCF_SDRAMC_SDCR_MUX(x)               (((x)&0x3)<<0x18)
+#define MCF_SDRAMC_SDCR_REF                  (0x10000000)
+#define MCF_SDRAMC_SDCR_DDR                  (0x20000000)
+#define MCF_SDRAMC_SDCR_CKE                  (0x40000000)
+#define MCF_SDRAMC_SDCR_MODE_EN              (0x80000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
+#define MCF_SDRAMC_SDCFG1_WTLAT(x)           (((x)&0x7)<<0x4)
+#define MCF_SDRAMC_SDCFG1_REF2ACT(x)         (((x)&0xF)<<0x8)
+#define MCF_SDRAMC_SDCFG1_PRE2ACT(x)         (((x)&0x7)<<0xC)
+#define MCF_SDRAMC_SDCFG1_ACT2RW(x)          (((x)&0x7)<<0x10)
+#define MCF_SDRAMC_SDCFG1_RDLAT(x)           (((x)&0xF)<<0x14)
+#define MCF_SDRAMC_SDCFG1_SWT2RD(x)          (((x)&0x7)<<0x18)
+#define MCF_SDRAMC_SDCFG1_SRD2RW(x)          (((x)&0xF)<<0x1C)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
+#define MCF_SDRAMC_SDCFG2_BL(x)              (((x)&0xF)<<0x10)
+#define MCF_SDRAMC_SDCFG2_BRD2WT(x)          (((x)&0xF)<<0x14)
+#define MCF_SDRAMC_SDCFG2_BWT2RW(x)          (((x)&0xF)<<0x18)
+#define MCF_SDRAMC_SDCFG2_BRD2PRE(x)         (((x)&0xF)<<0x1C)
+
+
+#endif /* __MCF5475_SDRAMC_H__ */

tos/fpga_test/include/MCF5475_SEC.h

@@ -0,0 +1,398 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SEC_H__
+#define __MCF5475_SEC_H__
+
+
+/*********************************************************************
+*
+* Integrated Security Engine (SEC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SEC_EUACRH                       (*(volatile uint32_t*)(&_MBAR[0x21000]))
+#define MCF_SEC_EUACRL                       (*(volatile uint32_t*)(&_MBAR[0x21004]))
+#define MCF_SEC_SIMRH                        (*(volatile uint32_t*)(&_MBAR[0x21008]))
+#define MCF_SEC_SIMRL                        (*(volatile uint32_t*)(&_MBAR[0x2100C]))
+#define MCF_SEC_SISRH                        (*(volatile uint32_t*)(&_MBAR[0x21010]))
+#define MCF_SEC_SISRL                        (*(volatile uint32_t*)(&_MBAR[0x21014]))
+#define MCF_SEC_SICRH                        (*(volatile uint32_t*)(&_MBAR[0x21018]))
+#define MCF_SEC_SICRL                        (*(volatile uint32_t*)(&_MBAR[0x2101C]))
+#define MCF_SEC_SIDR                         (*(volatile uint32_t*)(&_MBAR[0x21020]))
+#define MCF_SEC_EUASRH                       (*(volatile uint32_t*)(&_MBAR[0x21028]))
+#define MCF_SEC_EUASRL                       (*(volatile uint32_t*)(&_MBAR[0x2102C]))
+#define MCF_SEC_SMCR                         (*(volatile uint32_t*)(&_MBAR[0x21030]))
+#define MCF_SEC_MEAR                         (*(volatile uint32_t*)(&_MBAR[0x21038]))
+#define MCF_SEC_CCCR0                        (*(volatile uint32_t*)(&_MBAR[0x2200C]))
+#define MCF_SEC_CCPSRH0                      (*(volatile uint32_t*)(&_MBAR[0x22010]))
+#define MCF_SEC_CCPSRL0                      (*(volatile uint32_t*)(&_MBAR[0x22014]))
+#define MCF_SEC_CDPR0                        (*(volatile uint32_t*)(&_MBAR[0x22044]))
+#define MCF_SEC_FR0                          (*(volatile uint32_t*)(&_MBAR[0x2204C]))
+#define MCF_SEC_CCCR1                        (*(volatile uint32_t*)(&_MBAR[0x2300C]))
+#define MCF_SEC_CCPSRH1                      (*(volatile uint32_t*)(&_MBAR[0x23010]))
+#define MCF_SEC_CCPSRL1                      (*(volatile uint32_t*)(&_MBAR[0x23014]))
+#define MCF_SEC_CDPR1                        (*(volatile uint32_t*)(&_MBAR[0x23044]))
+#define MCF_SEC_FR1                          (*(volatile uint32_t*)(&_MBAR[0x2304C]))
+#define MCF_SEC_AFRCR                        (*(volatile uint32_t*)(&_MBAR[0x28018]))
+#define MCF_SEC_AFSR                         (*(volatile uint32_t*)(&_MBAR[0x28028]))
+#define MCF_SEC_AFISR                        (*(volatile uint32_t*)(&_MBAR[0x28030]))
+#define MCF_SEC_AFIMR                        (*(volatile uint32_t*)(&_MBAR[0x28038]))
+#define MCF_SEC_DRCR                         (*(volatile uint32_t*)(&_MBAR[0x2A018]))
+#define MCF_SEC_DSR                          (*(volatile uint32_t*)(&_MBAR[0x2A028]))
+#define MCF_SEC_DISR                         (*(volatile uint32_t*)(&_MBAR[0x2A030]))
+#define MCF_SEC_DIMR                         (*(volatile uint32_t*)(&_MBAR[0x2A038]))
+#define MCF_SEC_MDRCR                        (*(volatile uint32_t*)(&_MBAR[0x2C018]))
+#define MCF_SEC_MDSR                         (*(volatile uint32_t*)(&_MBAR[0x2C028]))
+#define MCF_SEC_MDISR                        (*(volatile uint32_t*)(&_MBAR[0x2C030]))
+#define MCF_SEC_MDIMR                        (*(volatile uint32_t*)(&_MBAR[0x2C038]))
+#define MCF_SEC_RNGRCR                       (*(volatile uint32_t*)(&_MBAR[0x2E018]))
+#define MCF_SEC_RNGSR                        (*(volatile uint32_t*)(&_MBAR[0x2E028]))
+#define MCF_SEC_RNGISR                       (*(volatile uint32_t*)(&_MBAR[0x2E030]))
+#define MCF_SEC_RNGIMR                       (*(volatile uint32_t*)(&_MBAR[0x2E038]))
+#define MCF_SEC_AESRCR                       (*(volatile uint32_t*)(&_MBAR[0x32018]))
+#define MCF_SEC_AESSR                        (*(volatile uint32_t*)(&_MBAR[0x32028]))
+#define MCF_SEC_AESISR                       (*(volatile uint32_t*)(&_MBAR[0x32030]))
+#define MCF_SEC_AESIMR                       (*(volatile uint32_t*)(&_MBAR[0x32038]))
+#define MCF_SEC_CCCRn(x)                     (*(volatile uint32_t*)(&_MBAR[0x2200C + ((x)*0x1000)]))
+#define MCF_SEC_CCPSRHn(x)                   (*(volatile uint32_t*)(&_MBAR[0x22010 + ((x)*0x1000)]))
+#define MCF_SEC_CCPSRLn(x)                   (*(volatile uint32_t*)(&_MBAR[0x22014 + ((x)*0x1000)]))
+#define MCF_SEC_CDPRn(x)                     (*(volatile uint32_t*)(&_MBAR[0x22044 + ((x)*0x1000)]))
+#define MCF_SEC_FRn(x)                       (*(volatile uint32_t*)(&_MBAR[0x2204C + ((x)*0x1000)]))
+
+
+/* Bit definitions and macros for MCF_SEC_EUACRH */
+#define MCF_SEC_EUACRH_AFEU(x)               (((x)&0xF)<<0)
+#define MCF_SEC_EUACRH_AFFEU_NOASSIGN        (0)
+#define MCF_SEC_EUACRH_AFFEU_CHA0            (0x1)
+#define MCF_SEC_EUACRH_AFFEU_CHA1            (0x2)
+#define MCF_SEC_EUACRH_MDEU(x)               (((x)&0xF)<<0x8)
+#define MCF_SEC_EUACRH_MDEU_NOASSIGN         (0)
+#define MCF_SEC_EUACRH_MDEU_CHA0             (0x100)
+#define MCF_SEC_EUACRH_MDEU_CHA1             (0x200)
+#define MCF_SEC_EUACRH_RNG(x)                (((x)&0xF)<<0x18)
+#define MCF_SEC_EUACRH_RNG_NOASSIGN          (0)
+#define MCF_SEC_EUACRH_RNG_CHA0              (0x1000000)
+#define MCF_SEC_EUACRH_RNG_CHA1              (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_EUACRL */
+#define MCF_SEC_EUACRL_AESU(x)               (((x)&0xF)<<0x10)
+#define MCF_SEC_EUACRL_AESU_NOASSIGN         (0)
+#define MCF_SEC_EUACRL_AESU_CHA0             (0x10000)
+#define MCF_SEC_EUACRL_AESU_CHA1             (0x20000)
+#define MCF_SEC_EUACRL_DEU(x)                (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SEC_SIMRH */
+#define MCF_SEC_SIMRH_AERR                   (0x8000000)
+#define MCF_SEC_SIMRH_CHA_0_DN               (0x10000000)
+#define MCF_SEC_SIMRH_CHA_0_ERR              (0x20000000)
+#define MCF_SEC_SIMRH_CHA_1_DN               (0x40000000)
+#define MCF_SEC_SIMRH_CHA_1_ERR              (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_SIMRL */
+#define MCF_SEC_SIMRL_TEA                    (0x40)
+#define MCF_SEC_SIMRL_DEU_DN                 (0x100)
+#define MCF_SEC_SIMRL_DEU_ERR                (0x200)
+#define MCF_SEC_SIMRL_AESU_DN                (0x1000)
+#define MCF_SEC_SIMRL_AESU_ERR               (0x2000)
+#define MCF_SEC_SIMRL_MDEU_DN                (0x10000)
+#define MCF_SEC_SIMRL_MDEU_ERR               (0x20000)
+#define MCF_SEC_SIMRL_AFEU_DN                (0x100000)
+#define MCF_SEC_SIMRL_AFEU_ERR               (0x200000)
+#define MCF_SEC_SIMRL_RNG_DN                 (0x1000000)
+#define MCF_SEC_SIMRL_RNG_ERR                (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_SISRH */
+#define MCF_SEC_SISRH_AERR                   (0x8000000)
+#define MCF_SEC_SISRH_CHA_0_DN               (0x10000000)
+#define MCF_SEC_SISRH_CHA_0_ERR              (0x20000000)
+#define MCF_SEC_SISRH_CHA_1_DN               (0x40000000)
+#define MCF_SEC_SISRH_CHA_1_ERR              (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_SISRL */
+#define MCF_SEC_SISRL_TEA                    (0x40)
+#define MCF_SEC_SISRL_DEU_DN                 (0x100)
+#define MCF_SEC_SISRL_DEU_ERR                (0x200)
+#define MCF_SEC_SISRL_AESU_DN                (0x1000)
+#define MCF_SEC_SISRL_AESU_ERR               (0x2000)
+#define MCF_SEC_SISRL_MDEU_DN                (0x10000)
+#define MCF_SEC_SISRL_MDEU_ERR               (0x20000)
+#define MCF_SEC_SISRL_AFEU_DN                (0x100000)
+#define MCF_SEC_SISRL_AFEU_ERR               (0x200000)
+#define MCF_SEC_SISRL_RNG_DN                 (0x1000000)
+#define MCF_SEC_SISRL_RNG_ERR                (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_SICRH */
+#define MCF_SEC_SICRH_AERR                   (0x8000000)
+#define MCF_SEC_SICRH_CHA_0_DN               (0x10000000)
+#define MCF_SEC_SICRH_CHA_0_ERR              (0x20000000)
+#define MCF_SEC_SICRH_CHA_1_DN               (0x40000000)
+#define MCF_SEC_SICRH_CHA_1_ERR              (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_SICRL */
+#define MCF_SEC_SICRL_TEA                    (0x40)
+#define MCF_SEC_SICRL_DEU_DN                 (0x100)
+#define MCF_SEC_SICRL_DEU_ERR                (0x200)
+#define MCF_SEC_SICRL_AESU_DN                (0x1000)
+#define MCF_SEC_SICRL_AESU_ERR               (0x2000)
+#define MCF_SEC_SICRL_MDEU_DN                (0x10000)
+#define MCF_SEC_SICRL_MDEU_ERR               (0x20000)
+#define MCF_SEC_SICRL_AFEU_DN                (0x100000)
+#define MCF_SEC_SICRL_AFEU_ERR               (0x200000)
+#define MCF_SEC_SICRL_RNG_DN                 (0x1000000)
+#define MCF_SEC_SICRL_RNG_ERR                (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_SIDR */
+#define MCF_SEC_SIDR_VERSION(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_EUASRH */
+#define MCF_SEC_EUASRH_AFEU(x)               (((x)&0xF)<<0)
+#define MCF_SEC_EUASRH_MDEU(x)               (((x)&0xF)<<0x8)
+#define MCF_SEC_EUASRH_RNG(x)                (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SEC_EUASRL */
+#define MCF_SEC_EUASRL_AESU(x)               (((x)&0xF)<<0x10)
+#define MCF_SEC_EUASRL_DEU(x)                (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SEC_SMCR */
+#define MCF_SEC_SMCR_CURR_CHAN(x)            (((x)&0xF)<<0x4)
+#define MCF_SEC_SMCR_CURR_CHAN_1             (0x10)
+#define MCF_SEC_SMCR_CURR_CHAN_2             (0x20)
+#define MCF_SEC_SMCR_SWR                     (0x1000000)
+
+/* Bit definitions and macros for MCF_SEC_MEAR */
+#define MCF_SEC_MEAR_ADDRESS(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_CCCRn */
+#define MCF_SEC_CCCRn_RST                    (0x1)
+#define MCF_SEC_CCCRn_CDIE                   (0x2)
+#define MCF_SEC_CCCRn_NT                     (0x4)
+#define MCF_SEC_CCCRn_NE                     (0x8)
+#define MCF_SEC_CCCRn_WE                     (0x10)
+#define MCF_SEC_CCCRn_BURST_SIZE(x)          (((x)&0x7)<<0x8)
+#define MCF_SEC_CCCRn_BURST_SIZE_2           (0)
+#define MCF_SEC_CCCRn_BURST_SIZE_8           (0x100)
+#define MCF_SEC_CCCRn_BURST_SIZE_16          (0x200)
+#define MCF_SEC_CCCRn_BURST_SIZE_24          (0x300)
+#define MCF_SEC_CCCRn_BURST_SIZE_32          (0x400)
+#define MCF_SEC_CCCRn_BURST_SIZE_40          (0x500)
+#define MCF_SEC_CCCRn_BURST_SIZE_48          (0x600)
+#define MCF_SEC_CCCRn_BURST_SIZE_56          (0x700)
+
+/* Bit definitions and macros for MCF_SEC_CCPSRHn */
+#define MCF_SEC_CCPSRHn_STATE(x)             (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_CCPSRLn */
+#define MCF_SEC_CCPSRLn_PAIR_PTR(x)          (((x)&0xFF)<<0)
+#define MCF_SEC_CCPSRLn_EUERR                (0x100)
+#define MCF_SEC_CCPSRLn_SERR                 (0x200)
+#define MCF_SEC_CCPSRLn_DERR                 (0x400)
+#define MCF_SEC_CCPSRLn_PERR                 (0x1000)
+#define MCF_SEC_CCPSRLn_TEA                  (0x2000)
+#define MCF_SEC_CCPSRLn_SD                   (0x10000)
+#define MCF_SEC_CCPSRLn_PD                   (0x20000)
+#define MCF_SEC_CCPSRLn_SRD                  (0x40000)
+#define MCF_SEC_CCPSRLn_PRD                  (0x80000)
+#define MCF_SEC_CCPSRLn_SG                   (0x100000)
+#define MCF_SEC_CCPSRLn_PG                   (0x200000)
+#define MCF_SEC_CCPSRLn_SR                   (0x400000)
+#define MCF_SEC_CCPSRLn_PR                   (0x800000)
+#define MCF_SEC_CCPSRLn_MO                   (0x1000000)
+#define MCF_SEC_CCPSRLn_MI                   (0x2000000)
+#define MCF_SEC_CCPSRLn_STAT                 (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_CDPRn */
+#define MCF_SEC_CDPRn_CDP(x)                 (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_FRn */
+#define MCF_SEC_FRn_FETCH_ADDR(x)            (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_AFRCR */
+#define MCF_SEC_AFRCR_SR                     (0x1000000)
+#define MCF_SEC_AFRCR_MI                     (0x2000000)
+#define MCF_SEC_AFRCR_RI                     (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_AFSR */
+#define MCF_SEC_AFSR_RD                      (0x1000000)
+#define MCF_SEC_AFSR_ID                      (0x2000000)
+#define MCF_SEC_AFSR_IE                      (0x4000000)
+#define MCF_SEC_AFSR_OFR                     (0x8000000)
+#define MCF_SEC_AFSR_IFW                     (0x10000000)
+#define MCF_SEC_AFSR_HALT                    (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_AFISR */
+#define MCF_SEC_AFISR_DSE                    (0x10000)
+#define MCF_SEC_AFISR_KSE                    (0x20000)
+#define MCF_SEC_AFISR_CE                     (0x40000)
+#define MCF_SEC_AFISR_ERE                    (0x80000)
+#define MCF_SEC_AFISR_IE                     (0x100000)
+#define MCF_SEC_AFISR_OFU                    (0x2000000)
+#define MCF_SEC_AFISR_IFO                    (0x4000000)
+#define MCF_SEC_AFISR_IFE                    (0x10000000)
+#define MCF_SEC_AFISR_OFE                    (0x20000000)
+#define MCF_SEC_AFISR_AE                     (0x40000000)
+#define MCF_SEC_AFISR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_AFIMR */
+#define MCF_SEC_AFIMR_DSE                    (0x10000)
+#define MCF_SEC_AFIMR_KSE                    (0x20000)
+#define MCF_SEC_AFIMR_CE                     (0x40000)
+#define MCF_SEC_AFIMR_ERE                    (0x80000)
+#define MCF_SEC_AFIMR_IE                     (0x100000)
+#define MCF_SEC_AFIMR_OFU                    (0x2000000)
+#define MCF_SEC_AFIMR_IFO                    (0x4000000)
+#define MCF_SEC_AFIMR_IFE                    (0x10000000)
+#define MCF_SEC_AFIMR_OFE                    (0x20000000)
+#define MCF_SEC_AFIMR_AE                     (0x40000000)
+#define MCF_SEC_AFIMR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_DRCR */
+#define MCF_SEC_DRCR_SR                      (0x1000000)
+#define MCF_SEC_DRCR_MI                      (0x2000000)
+#define MCF_SEC_DRCR_RI                      (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_DSR */
+#define MCF_SEC_DSR_RD                       (0x1000000)
+#define MCF_SEC_DSR_ID                       (0x2000000)
+#define MCF_SEC_DSR_IE                       (0x4000000)
+#define MCF_SEC_DSR_OFR                      (0x8000000)
+#define MCF_SEC_DSR_IFW                      (0x10000000)
+#define MCF_SEC_DSR_HALT                     (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_DISR */
+#define MCF_SEC_DISR_DSE                     (0x10000)
+#define MCF_SEC_DISR_KSE                     (0x20000)
+#define MCF_SEC_DISR_CE                      (0x40000)
+#define MCF_SEC_DISR_ERE                     (0x80000)
+#define MCF_SEC_DISR_IE                      (0x100000)
+#define MCF_SEC_DISR_KPE                     (0x200000)
+#define MCF_SEC_DISR_OFU                     (0x2000000)
+#define MCF_SEC_DISR_IFO                     (0x4000000)
+#define MCF_SEC_DISR_IFE                     (0x10000000)
+#define MCF_SEC_DISR_OFE                     (0x20000000)
+#define MCF_SEC_DISR_AE                      (0x40000000)
+#define MCF_SEC_DISR_ME                      (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_DIMR */
+#define MCF_SEC_DIMR_DSE                     (0x10000)
+#define MCF_SEC_DIMR_KSE                     (0x20000)
+#define MCF_SEC_DIMR_CE                      (0x40000)
+#define MCF_SEC_DIMR_ERE                     (0x80000)
+#define MCF_SEC_DIMR_IE                      (0x100000)
+#define MCF_SEC_DIMR_KPE                     (0x200000)
+#define MCF_SEC_DIMR_OFU                     (0x2000000)
+#define MCF_SEC_DIMR_IFO                     (0x4000000)
+#define MCF_SEC_DIMR_IFE                     (0x10000000)
+#define MCF_SEC_DIMR_OFE                     (0x20000000)
+#define MCF_SEC_DIMR_AE                      (0x40000000)
+#define MCF_SEC_DIMR_ME                      (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_MDRCR */
+#define MCF_SEC_MDRCR_SR                     (0x1000000)
+#define MCF_SEC_MDRCR_MI                     (0x2000000)
+#define MCF_SEC_MDRCR_RI                     (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_MDSR */
+#define MCF_SEC_MDSR_RD                      (0x1000000)
+#define MCF_SEC_MDSR_ID                      (0x2000000)
+#define MCF_SEC_MDSR_IE                      (0x4000000)
+#define MCF_SEC_MDSR_IFW                     (0x10000000)
+#define MCF_SEC_MDSR_HALT                    (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_MDISR */
+#define MCF_SEC_MDISR_DSE                    (0x10000)
+#define MCF_SEC_MDISR_KSE                    (0x20000)
+#define MCF_SEC_MDISR_CE                     (0x40000)
+#define MCF_SEC_MDISR_ERE                    (0x80000)
+#define MCF_SEC_MDISR_IE                     (0x100000)
+#define MCF_SEC_MDISR_IFO                    (0x4000000)
+#define MCF_SEC_MDISR_AE                     (0x40000000)
+#define MCF_SEC_MDISR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_MDIMR */
+#define MCF_SEC_MDIMR_DSE                    (0x10000)
+#define MCF_SEC_MDIMR_KSE                    (0x20000)
+#define MCF_SEC_MDIMR_CE                     (0x40000)
+#define MCF_SEC_MDIMR_ERE                    (0x80000)
+#define MCF_SEC_MDIMR_IE                     (0x100000)
+#define MCF_SEC_MDIMR_IFO                    (0x4000000)
+#define MCF_SEC_MDIMR_AE                     (0x40000000)
+#define MCF_SEC_MDIMR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGRCR */
+#define MCF_SEC_RNGRCR_SR                    (0x1000000)
+#define MCF_SEC_RNGRCR_MI                    (0x2000000)
+#define MCF_SEC_RNGRCR_RI                    (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGSR */
+#define MCF_SEC_RNGSR_RD                     (0x1000000)
+#define MCF_SEC_RNGSR_IE                     (0x4000000)
+#define MCF_SEC_RNGSR_OFR                    (0x8000000)
+#define MCF_SEC_RNGSR_HALT                   (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGISR */
+#define MCF_SEC_RNGISR_IE                    (0x100000)
+#define MCF_SEC_RNGISR_OFU                   (0x2000000)
+#define MCF_SEC_RNGISR_AE                    (0x40000000)
+#define MCF_SEC_RNGISR_ME                    (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGIMR */
+#define MCF_SEC_RNGIMR_IE                    (0x100000)
+#define MCF_SEC_RNGIMR_OFU                   (0x2000000)
+#define MCF_SEC_RNGIMR_AE                    (0x40000000)
+#define MCF_SEC_RNGIMR_ME                    (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_AESRCR */
+#define MCF_SEC_AESRCR_SR                    (0x1000000)
+#define MCF_SEC_AESRCR_MI                    (0x2000000)
+#define MCF_SEC_AESRCR_RI                    (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_AESSR */
+#define MCF_SEC_AESSR_RD                     (0x1000000)
+#define MCF_SEC_AESSR_ID                     (0x2000000)
+#define MCF_SEC_AESSR_IE                     (0x4000000)
+#define MCF_SEC_AESSR_OFR                    (0x8000000)
+#define MCF_SEC_AESSR_IFW                    (0x10000000)
+#define MCF_SEC_AESSR_HALT                   (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_AESISR */
+#define MCF_SEC_AESISR_DSE                   (0x10000)
+#define MCF_SEC_AESISR_KSE                   (0x20000)
+#define MCF_SEC_AESISR_CE                    (0x40000)
+#define MCF_SEC_AESISR_ERE                   (0x80000)
+#define MCF_SEC_AESISR_IE                    (0x100000)
+#define MCF_SEC_AESISR_OFU                   (0x2000000)
+#define MCF_SEC_AESISR_IFO                   (0x4000000)
+#define MCF_SEC_AESISR_IFE                   (0x10000000)
+#define MCF_SEC_AESISR_OFE                   (0x20000000)
+#define MCF_SEC_AESISR_AE                    (0x40000000)
+#define MCF_SEC_AESISR_ME                    (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_AESIMR */
+#define MCF_SEC_AESIMR_DSE                   (0x10000)
+#define MCF_SEC_AESIMR_KSE                   (0x20000)
+#define MCF_SEC_AESIMR_CE                    (0x40000)
+#define MCF_SEC_AESIMR_ERE                   (0x80000)
+#define MCF_SEC_AESIMR_IE                    (0x100000)
+#define MCF_SEC_AESIMR_OFU                   (0x2000000)
+#define MCF_SEC_AESIMR_IFO                   (0x4000000)
+#define MCF_SEC_AESIMR_IFE                   (0x10000000)
+#define MCF_SEC_AESIMR_OFE                   (0x20000000)
+#define MCF_SEC_AESIMR_AE                    (0x40000000)
+#define MCF_SEC_AESIMR_ME                    (0x80000000)
+
+
+#endif /* __MCF5475_SEC_H__ */

tos/fpga_test/include/MCF5475_SIU.h

@@ -0,0 +1,67 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SIU_H__
+#define __MCF5475_SIU_H__
+
+
+/*********************************************************************
+*
+* System Integration Unit (SIU)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SIU_SBCR                         (*(volatile uint32_t*)(&_MBAR[0x10]))
+#define MCF_SIU_SECSACR                      (*(volatile uint32_t*)(&_MBAR[0x38]))
+#define MCF_SIU_RSR                          (*(volatile uint32_t*)(&_MBAR[0x44]))
+#define MCF_SIU_JTAGID                       (*(volatile uint32_t*)(&_MBAR[0x50]))
+
+
+/* Bit definitions and macros for MCF_SIU_SBCR */
+#define MCF_SIU_SBCR_PIN2DSPI                (0x8000000)
+#define MCF_SIU_SBCR_DMA2CPU                 (0x10000000)
+#define MCF_SIU_SBCR_CPU2DMA                 (0x20000000)
+#define MCF_SIU_SBCR_PIN2DMA                 (0x40000000)
+#define MCF_SIU_SBCR_PIN2CPU                 (0x80000000)
+
+/* Bit definitions and macros for MCF_SIU_SECSACR */
+#define MCF_SIU_SECSACR_SEQEN                (0x1)
+
+/* Bit definitions and macros for MCF_SIU_RSR */
+#define MCF_SIU_RSR_RST                      (0x1)
+#define MCF_SIU_RSR_RSTWD                    (0x2)
+#define MCF_SIU_RSR_RSTJTG                   (0x8)
+
+/* Bit definitions and macros for MCF_SIU_JTAGID */
+#define MCF_SIU_JTAGID_JTAGID(x)             (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SIU_JTAGID */
+#define MCF_SIU_JTAGID_REV          (0xF0000000)
+#define MCF_SIU_JTAGID_PROCESSOR    (0x0FFFFFFF)
+#define MCF_SIU_JTAGID_MCF5485      (0x0800C01D)
+#define MCF_SIU_JTAGID_MCF5484      (0x0800D01D)
+#define MCF_SIU_JTAGID_MCF5483      (0x0800E01D)
+#define MCF_SIU_JTAGID_MCF5482      (0x0800F01D)
+#define MCF_SIU_JTAGID_MCF5481      (0x0801001D)
+#define MCF_SIU_JTAGID_MCF5480      (0x0801101D)
+#define MCF_SIU_JTAGID_MCF5475      (0x0801201D)
+#define MCF_SIU_JTAGID_MCF5474      (0x0801301D)
+#define MCF_SIU_JTAGID_MCF5473      (0x0801401D)
+#define MCF_SIU_JTAGID_MCF5472      (0x0801501D)
+#define MCF_SIU_JTAGID_MCF5471      (0x0801601D)
+#define MCF_SIU_JTAGID_MCF5470      (0x0801701D)
+
+#endif /* __MCF5475_SIU_H__ */

tos/fpga_test/include/MCF5475_SLT.h

@@ -0,0 +1,59 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SLT_H__
+#define __MCF5475_SLT_H__
+
+
+/*********************************************************************
+*
+* Slice Timers (SLT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SLT0_STCNT                       (*(volatile uint32_t*)(&_MBAR[0x900]))
+#define MCF_SLT0_SCR                         (*(volatile uint32_t*)(&_MBAR[0x904]))
+#define MCF_SLT0_SCNT                        (*(volatile uint32_t*)(&_MBAR[0x908]))
+#define MCF_SLT0_SSR                         (*(volatile uint32_t*)(&_MBAR[0x90C]))
+
+#define MCF_SLT1_STCNT                       (*(volatile uint32_t*)(&_MBAR[0x910]))
+#define MCF_SLT1_SCR                         (*(volatile uint32_t*)(&_MBAR[0x914]))
+#define MCF_SLT1_SCNT                        (*(volatile uint32_t*)(&_MBAR[0x918]))
+#define MCF_SLT1_SSR                         (*(volatile uint32_t*)(&_MBAR[0x91C]))
+
+#define MCF_SLT_STCNT(x)                     (*(volatile uint32_t*)(&_MBAR[0x900 + ((x)*0x10)]))
+#define MCF_SLT_SCR(x)                       (*(volatile uint32_t*)(&_MBAR[0x904 + ((x)*0x10)]))
+#define MCF_SLT_SCNT(x)                      (*(volatile int32_t*)(&_MBAR[0x908 + ((x)*0x10)]))
+#define MCF_SLT_SSR(x)                       (*(volatile uint32_t*)(&_MBAR[0x90C + ((x)*0x10)]))
+
+
+/* Bit definitions and macros for MCF_SLT_STCNT */
+#define MCF_SLT_STCNT_TC(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SLT_SCR */
+#define MCF_SLT_SCR_TEN                      (0x1000000)
+#define MCF_SLT_SCR_IEN                      (0x2000000)
+#define MCF_SLT_SCR_RUN                      (0x4000000)
+
+/* Bit definitions and macros for MCF_SLT_SCNT */
+#define MCF_SLT_SCNT_CNT(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SLT_SSR */
+#define MCF_SLT_SSR_ST                       (0x1000000)
+#define MCF_SLT_SSR_BE                       (0x2000000)
+
+
+#endif /* __MCF5475_SLT_H__ */

tos/fpga_test/include/MCF5475_SRAM.h

@@ -0,0 +1,62 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SRAM_H__
+#define __MCF5475_SRAM_H__
+
+
+/*********************************************************************
+*
+* System SRAM Module (SRAM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SRAM_SSCR                        (*(volatile uint32_t*)(&__MBAR[0x1FFC0]))
+#define MCF_SRAM_TCCR                        (*(volatile uint32_t*)(&__MBAR[0x1FFC4]))
+#define MCF_SRAM_TCCRDR                      (*(volatile uint32_t*)(&__MBAR[0x1FFC8]))
+#define MCF_SRAM_TCCRDW                      (*(volatile uint32_t*)(&__MBAR[0x1FFCC]))
+#define MCF_SRAM_TCCRSEC                     (*(volatile uint32_t*)(&__MBAR[0x1FFD0]))
+
+
+/* Bit definitions and macros for MCF_SRAM_SSCR */
+#define MCF_SRAM_SSCR_INLV                   (0x10000)
+
+/* Bit definitions and macros for MCF_SRAM_TCCR */
+#define MCF_SRAM_TCCR_BANK0_TC(x)            (((x)&0xF)<<0)
+#define MCF_SRAM_TCCR_BANK1_TC(x)            (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCR_BANK2_TC(x)            (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCR_BANK3_TC(x)            (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SRAM_TCCRDR */
+#define MCF_SRAM_TCCRDR_BANK0_TC(x)          (((x)&0xF)<<0)
+#define MCF_SRAM_TCCRDR_BANK1_TC(x)          (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCRDR_BANK2_TC(x)          (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCRDR_BANK3_TC(x)          (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SRAM_TCCRDW */
+#define MCF_SRAM_TCCRDW_BANK0_TC(x)          (((x)&0xF)<<0)
+#define MCF_SRAM_TCCRDW_BANK1_TC(x)          (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCRDW_BANK2_TC(x)          (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCRDW_BANK3_TC(x)          (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SRAM_TCCRSEC */
+#define MCF_SRAM_TCCRSEC_BANK0_TC(x)         (((x)&0xF)<<0)
+#define MCF_SRAM_TCCRSEC_BANK1_TC(x)         (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCRSEC_BANK2_TC(x)         (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCRSEC_BANK3_TC(x)         (((x)&0xF)<<0x18)
+
+
+#endif /* __MCF5475_SRAM_H__ */

tos/fpga_test/include/MCF5475_USB.h

@@ -0,0 +1,554 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_USB_H__
+#define __MCF5475_USB_H__
+
+
+/*********************************************************************
+*
+* Universal Serial Bus Interface (USB)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_USB_USBAISR                      (*(volatile uint8_t *)(&__MBAR[0xB000]))
+#define MCF_USB_USBAIMR                      (*(volatile uint8_t *)(&__MBAR[0xB001]))
+#define MCF_USB_EPINFO                       (*(volatile uint8_t *)(&__MBAR[0xB003]))
+#define MCF_USB_CFGR                         (*(volatile uint8_t *)(&__MBAR[0xB004]))
+#define MCF_USB_CFGAR                        (*(volatile uint8_t *)(&__MBAR[0xB005]))
+#define MCF_USB_SPEEDR                       (*(volatile uint8_t *)(&__MBAR[0xB006]))
+#define MCF_USB_FRMNUMR                      (*(volatile uint16_t*)(&__MBAR[0xB00E]))
+#define MCF_USB_EPTNR                        (*(volatile uint16_t*)(&__MBAR[0xB010]))
+#define MCF_USB_IFUR                         (*(volatile uint16_t*)(&__MBAR[0xB014]))
+#define MCF_USB_IFR0                         (*(volatile uint16_t*)(&__MBAR[0xB040]))
+#define MCF_USB_IFR1                         (*(volatile uint16_t*)(&__MBAR[0xB042]))
+#define MCF_USB_IFR2                         (*(volatile uint16_t*)(&__MBAR[0xB044]))
+#define MCF_USB_IFR3                         (*(volatile uint16_t*)(&__MBAR[0xB046]))
+#define MCF_USB_IFR4                         (*(volatile uint16_t*)(&__MBAR[0xB048]))
+#define MCF_USB_IFR5                         (*(volatile uint16_t*)(&__MBAR[0xB04A]))
+#define MCF_USB_IFR6                         (*(volatile uint16_t*)(&__MBAR[0xB04C]))
+#define MCF_USB_IFR7                         (*(volatile uint16_t*)(&__MBAR[0xB04E]))
+#define MCF_USB_IFR8                         (*(volatile uint16_t*)(&__MBAR[0xB050]))
+#define MCF_USB_IFR9                         (*(volatile uint16_t*)(&__MBAR[0xB052]))
+#define MCF_USB_IFR10                        (*(volatile uint16_t*)(&__MBAR[0xB054]))
+#define MCF_USB_IFR11                        (*(volatile uint16_t*)(&__MBAR[0xB056]))
+#define MCF_USB_IFR12                        (*(volatile uint16_t*)(&__MBAR[0xB058]))
+#define MCF_USB_IFR13                        (*(volatile uint16_t*)(&__MBAR[0xB05A]))
+#define MCF_USB_IFR14                        (*(volatile uint16_t*)(&__MBAR[0xB05C]))
+#define MCF_USB_IFR15                        (*(volatile uint16_t*)(&__MBAR[0xB05E]))
+#define MCF_USB_IFR16                        (*(volatile uint16_t*)(&__MBAR[0xB060]))
+#define MCF_USB_IFR17                        (*(volatile uint16_t*)(&__MBAR[0xB062]))
+#define MCF_USB_IFR18                        (*(volatile uint16_t*)(&__MBAR[0xB064]))
+#define MCF_USB_IFR19                        (*(volatile uint16_t*)(&__MBAR[0xB066]))
+#define MCF_USB_IFR20                        (*(volatile uint16_t*)(&__MBAR[0xB068]))
+#define MCF_USB_IFR21                        (*(volatile uint16_t*)(&__MBAR[0xB06A]))
+#define MCF_USB_IFR22                        (*(volatile uint16_t*)(&__MBAR[0xB06C]))
+#define MCF_USB_IFR23                        (*(volatile uint16_t*)(&__MBAR[0xB06E]))
+#define MCF_USB_IFR24                        (*(volatile uint16_t*)(&__MBAR[0xB070]))
+#define MCF_USB_IFR25                        (*(volatile uint16_t*)(&__MBAR[0xB072]))
+#define MCF_USB_IFR26                        (*(volatile uint16_t*)(&__MBAR[0xB074]))
+#define MCF_USB_IFR27                        (*(volatile uint16_t*)(&__MBAR[0xB076]))
+#define MCF_USB_IFR28                        (*(volatile uint16_t*)(&__MBAR[0xB078]))
+#define MCF_USB_IFR29                        (*(volatile uint16_t*)(&__MBAR[0xB07A]))
+#define MCF_USB_IFR30                        (*(volatile uint16_t*)(&__MBAR[0xB07C]))
+#define MCF_USB_IFR31                        (*(volatile uint16_t*)(&__MBAR[0xB07E]))
+#define MCF_USB_PPCNT                        (*(volatile uint16_t*)(&__MBAR[0xB080]))
+#define MCF_USB_DPCNT                        (*(volatile uint16_t*)(&__MBAR[0xB082]))
+#define MCF_USB_CRCECNT                      (*(volatile uint16_t*)(&__MBAR[0xB084]))
+#define MCF_USB_BSECNT                       (*(volatile uint16_t*)(&__MBAR[0xB086]))
+#define MCF_USB_PIDECNT                      (*(volatile uint16_t*)(&__MBAR[0xB088]))
+#define MCF_USB_FRMECNT                      (*(volatile uint16_t*)(&__MBAR[0xB08A]))
+#define MCF_USB_TXPCNT                       (*(volatile uint16_t*)(&__MBAR[0xB08C]))
+#define MCF_USB_CNTOVR                       (*(volatile uint8_t *)(&__MBAR[0xB08E]))
+#define MCF_USB_EP0ACR                       (*(volatile uint8_t *)(&__MBAR[0xB101]))
+#define MCF_USB_EP0MPSR                      (*(volatile uint16_t*)(&__MBAR[0xB102]))
+#define MCF_USB_EP0IFR                       (*(volatile uint8_t *)(&__MBAR[0xB104]))
+#define MCF_USB_EP0SR                        (*(volatile uint8_t *)(&__MBAR[0xB105]))
+#define MCF_USB_BMRTR                        (*(volatile uint8_t *)(&__MBAR[0xB106]))
+#define MCF_USB_BRTR                         (*(volatile uint8_t *)(&__MBAR[0xB107]))
+#define MCF_USB_WVALUER                      (*(volatile uint16_t*)(&__MBAR[0xB108]))
+#define MCF_USB_WINDEXR                      (*(volatile uint16_t*)(&__MBAR[0xB10A]))
+#define MCF_USB_WLENGTHR                     (*(volatile uint16_t*)(&__MBAR[0xB10C]))
+#define MCF_USB_EP1OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB131]))
+#define MCF_USB_EP1OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB132]))
+#define MCF_USB_EP1OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB134]))
+#define MCF_USB_EP1OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB135]))
+#define MCF_USB_EP1OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB13E]))
+#define MCF_USB_EP1INACR                     (*(volatile uint8_t *)(&__MBAR[0xB149]))
+#define MCF_USB_EP1INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB14A]))
+#define MCF_USB_EP1INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB14C]))
+#define MCF_USB_EP1INSR                      (*(volatile uint8_t *)(&__MBAR[0xB14D]))
+#define MCF_USB_EP1INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB156]))
+#define MCF_USB_EP2OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB161]))
+#define MCF_USB_EP2OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB162]))
+#define MCF_USB_EP2OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB164]))
+#define MCF_USB_EP2OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB165]))
+#define MCF_USB_EP2OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB16E]))
+#define MCF_USB_EP2INACR                     (*(volatile uint8_t *)(&__MBAR[0xB179]))
+#define MCF_USB_EP2INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB17A]))
+#define MCF_USB_EP2INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB17C]))
+#define MCF_USB_EP2INSR                      (*(volatile uint8_t *)(&__MBAR[0xB17D]))
+#define MCF_USB_EP2INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB186]))
+#define MCF_USB_EP3OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB191]))
+#define MCF_USB_EP3OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB192]))
+#define MCF_USB_EP3OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB194]))
+#define MCF_USB_EP3OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB195]))
+#define MCF_USB_EP3OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB19E]))
+#define MCF_USB_EP3INACR                     (*(volatile uint8_t *)(&__MBAR[0xB1A9]))
+#define MCF_USB_EP3INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB1AA]))
+#define MCF_USB_EP3INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB1AC]))
+#define MCF_USB_EP3INSR                      (*(volatile uint8_t *)(&__MBAR[0xB1AD]))
+#define MCF_USB_EP3INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB1B6]))
+#define MCF_USB_EP4OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB1C1]))
+#define MCF_USB_EP4OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB1C2]))
+#define MCF_USB_EP4OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB1C4]))
+#define MCF_USB_EP4OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB1C5]))
+#define MCF_USB_EP4OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB1CE]))
+#define MCF_USB_EP4INACR                     (*(volatile uint8_t *)(&__MBAR[0xB1D9]))
+#define MCF_USB_EP4INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB1DA]))
+#define MCF_USB_EP4INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB1DC]))
+#define MCF_USB_EP4INSR                      (*(volatile uint8_t *)(&__MBAR[0xB1DD]))
+#define MCF_USB_EP4INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB1E6]))
+#define MCF_USB_EP5OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB1F1]))
+#define MCF_USB_EP5OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB1F2]))
+#define MCF_USB_EP5OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB1F4]))
+#define MCF_USB_EP5OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB1F5]))
+#define MCF_USB_EP5OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB1FE]))
+#define MCF_USB_EP5INACR                     (*(volatile uint8_t *)(&__MBAR[0xB209]))
+#define MCF_USB_EP5INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB20A]))
+#define MCF_USB_EP5INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB20C]))
+#define MCF_USB_EP5INSR                      (*(volatile uint8_t *)(&__MBAR[0xB20D]))
+#define MCF_USB_EP5INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB216]))
+#define MCF_USB_EP6OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB221]))
+#define MCF_USB_EP6OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB222]))
+#define MCF_USB_EP6OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB224]))
+#define MCF_USB_EP6OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB225]))
+#define MCF_USB_EP6OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB22E]))
+#define MCF_USB_EP6INACR                     (*(volatile uint8_t *)(&__MBAR[0xB239]))
+#define MCF_USB_EP6INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB23A]))
+#define MCF_USB_EP6INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB23C]))
+#define MCF_USB_EP6INSR                      (*(volatile uint8_t *)(&__MBAR[0xB23D]))
+#define MCF_USB_EP6INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB246]))
+#define MCF_USB_USBSR                        (*(volatile uint32_t*)(&__MBAR[0xB400]))
+#define MCF_USB_USBCR                        (*(volatile uint32_t*)(&__MBAR[0xB404]))
+#define MCF_USB_DRAMCR                       (*(volatile uint32_t*)(&__MBAR[0xB408]))
+#define MCF_USB_DRAMDR                       (*(volatile uint32_t*)(&__MBAR[0xB40C]))
+#define MCF_USB_USBISR                       (*(volatile uint32_t*)(&__MBAR[0xB410]))
+#define MCF_USB_USBIMR                       (*(volatile uint32_t*)(&__MBAR[0xB414]))
+#define MCF_USB_EP0STAT                      (*(volatile uint32_t*)(&__MBAR[0xB440]))
+#define MCF_USB_EP0ISR                       (*(volatile uint32_t*)(&__MBAR[0xB444]))
+#define MCF_USB_EP0IMR                       (*(volatile uint32_t*)(&__MBAR[0xB448]))
+#define MCF_USB_EP0FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB44C]))
+#define MCF_USB_EP0FDR                       (*(volatile uint32_t*)(&__MBAR[0xB450]))
+#define MCF_USB_EP0FSR                       (*(volatile uint32_t*)(&__MBAR[0xB454]))
+#define MCF_USB_EP0FCR                       (*(volatile uint32_t*)(&__MBAR[0xB458]))
+#define MCF_USB_EP0FAR                       (*(volatile uint32_t*)(&__MBAR[0xB45C]))
+#define MCF_USB_EP0FRP                       (*(volatile uint32_t*)(&__MBAR[0xB460]))
+#define MCF_USB_EP0FWP                       (*(volatile uint32_t*)(&__MBAR[0xB464]))
+#define MCF_USB_EP0LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB468]))
+#define MCF_USB_EP0LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB46C]))
+#define MCF_USB_EP1STAT                      (*(volatile uint32_t*)(&__MBAR[0xB470]))
+#define MCF_USB_EP1ISR                       (*(volatile uint32_t*)(&__MBAR[0xB474]))
+#define MCF_USB_EP1IMR                       (*(volatile uint32_t*)(&__MBAR[0xB478]))
+#define MCF_USB_EP1FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB47C]))
+#define MCF_USB_EP1FDR                       (*(volatile uint32_t*)(&__MBAR[0xB480]))
+#define MCF_USB_EP1FSR                       (*(volatile uint32_t*)(&__MBAR[0xB484]))
+#define MCF_USB_EP1FCR                       (*(volatile uint32_t*)(&__MBAR[0xB488]))
+#define MCF_USB_EP1FAR                       (*(volatile uint32_t*)(&__MBAR[0xB48C]))
+#define MCF_USB_EP1FRP                       (*(volatile uint32_t*)(&__MBAR[0xB490]))
+#define MCF_USB_EP1FWP                       (*(volatile uint32_t*)(&__MBAR[0xB494]))
+#define MCF_USB_EP1LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB498]))
+#define MCF_USB_EP1LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB49C]))
+#define MCF_USB_EP2STAT                      (*(volatile uint32_t*)(&__MBAR[0xB4A0]))
+#define MCF_USB_EP2ISR                       (*(volatile uint32_t*)(&__MBAR[0xB4A4]))
+#define MCF_USB_EP2IMR                       (*(volatile uint32_t*)(&__MBAR[0xB4A8]))
+#define MCF_USB_EP2FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB4AC]))
+#define MCF_USB_EP2FDR                       (*(volatile uint32_t*)(&__MBAR[0xB4B0]))
+#define MCF_USB_EP2FSR                       (*(volatile uint32_t*)(&__MBAR[0xB4B4]))
+#define MCF_USB_EP2FCR                       (*(volatile uint32_t*)(&__MBAR[0xB4B8]))
+#define MCF_USB_EP2FAR                       (*(volatile uint32_t*)(&__MBAR[0xB4BC]))
+#define MCF_USB_EP2FRP                       (*(volatile uint32_t*)(&__MBAR[0xB4C0]))
+#define MCF_USB_EP2FWP                       (*(volatile uint32_t*)(&__MBAR[0xB4C4]))
+#define MCF_USB_EP2LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB4C8]))
+#define MCF_USB_EP2LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB4CC]))
+#define MCF_USB_EP3STAT                      (*(volatile uint32_t*)(&__MBAR[0xB4D0]))
+#define MCF_USB_EP3ISR                       (*(volatile uint32_t*)(&__MBAR[0xB4D4]))
+#define MCF_USB_EP3IMR                       (*(volatile uint32_t*)(&__MBAR[0xB4D8]))
+#define MCF_USB_EP3FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB4DC]))
+#define MCF_USB_EP3FDR                       (*(volatile uint32_t*)(&__MBAR[0xB4E0]))
+#define MCF_USB_EP3FSR                       (*(volatile uint32_t*)(&__MBAR[0xB4E4]))
+#define MCF_USB_EP3FCR                       (*(volatile uint32_t*)(&__MBAR[0xB4E8]))
+#define MCF_USB_EP3FAR                       (*(volatile uint32_t*)(&__MBAR[0xB4EC]))
+#define MCF_USB_EP3FRP                       (*(volatile uint32_t*)(&__MBAR[0xB4F0]))
+#define MCF_USB_EP3FWP                       (*(volatile uint32_t*)(&__MBAR[0xB4F4]))
+#define MCF_USB_EP3LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB4F8]))
+#define MCF_USB_EP3LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB4FC]))
+#define MCF_USB_EP4STAT                      (*(volatile uint32_t*)(&__MBAR[0xB500]))
+#define MCF_USB_EP4ISR                       (*(volatile uint32_t*)(&__MBAR[0xB504]))
+#define MCF_USB_EP4IMR                       (*(volatile uint32_t*)(&__MBAR[0xB508]))
+#define MCF_USB_EP4FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB50C]))
+#define MCF_USB_EP4FDR                       (*(volatile uint32_t*)(&__MBAR[0xB510]))
+#define MCF_USB_EP4FSR                       (*(volatile uint32_t*)(&__MBAR[0xB514]))
+#define MCF_USB_EP4FCR                       (*(volatile uint32_t*)(&__MBAR[0xB518]))
+#define MCF_USB_EP4FAR                       (*(volatile uint32_t*)(&__MBAR[0xB51C]))
+#define MCF_USB_EP4FRP                       (*(volatile uint32_t*)(&__MBAR[0xB520]))
+#define MCF_USB_EP4FWP                       (*(volatile uint32_t*)(&__MBAR[0xB524]))
+#define MCF_USB_EP4LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB528]))
+#define MCF_USB_EP4LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB52C]))
+#define MCF_USB_EP5STAT                      (*(volatile uint32_t*)(&__MBAR[0xB530]))
+#define MCF_USB_EP5ISR                       (*(volatile uint32_t*)(&__MBAR[0xB534]))
+#define MCF_USB_EP5IMR                       (*(volatile uint32_t*)(&__MBAR[0xB538]))
+#define MCF_USB_EP5FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB53C]))
+#define MCF_USB_EP5FDR                       (*(volatile uint32_t*)(&__MBAR[0xB540]))
+#define MCF_USB_EP5FSR                       (*(volatile uint32_t*)(&__MBAR[0xB544]))
+#define MCF_USB_EP5FCR                       (*(volatile uint32_t*)(&__MBAR[0xB548]))
+#define MCF_USB_EP5FAR                       (*(volatile uint32_t*)(&__MBAR[0xB54C]))
+#define MCF_USB_EP5FRP                       (*(volatile uint32_t*)(&__MBAR[0xB550]))
+#define MCF_USB_EP5FWP                       (*(volatile uint32_t*)(&__MBAR[0xB554]))
+#define MCF_USB_EP5LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB558]))
+#define MCF_USB_EP5LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB55C]))
+#define MCF_USB_EP6STAT                      (*(volatile uint32_t*)(&__MBAR[0xB560]))
+#define MCF_USB_EP6ISR                       (*(volatile uint32_t*)(&__MBAR[0xB564]))
+#define MCF_USB_EP6IMR                       (*(volatile uint32_t*)(&__MBAR[0xB568]))
+#define MCF_USB_EP6FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB56C]))
+#define MCF_USB_EP6FDR                       (*(volatile uint32_t*)(&__MBAR[0xB570]))
+#define MCF_USB_EP6FSR                       (*(volatile uint32_t*)(&__MBAR[0xB574]))
+#define MCF_USB_EP6FCR                       (*(volatile uint32_t*)(&__MBAR[0xB578]))
+#define MCF_USB_EP6FAR                       (*(volatile uint32_t*)(&__MBAR[0xB57C]))
+#define MCF_USB_EP6FRP                       (*(volatile uint32_t*)(&__MBAR[0xB580]))
+#define MCF_USB_EP6FWP                       (*(volatile uint32_t*)(&__MBAR[0xB584]))
+#define MCF_USB_EP6LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB588]))
+#define MCF_USB_EP6LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB58C]))
+#define MCF_USB_IFR(x)                       (*(volatile uint16_t*)(&__MBAR[0xB040 + ((x)*0x2)]))
+#define MCF_USB_EPOUTACR(x)                  (*(volatile uint8_t *)(&__MBAR[0xB131 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTMPSR(x)                 (*(volatile uint16_t*)(&__MBAR[0xB132 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTIFR(x)                  (*(volatile uint8_t *)(&__MBAR[0xB134 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTSR(x)                   (*(volatile uint8_t *)(&__MBAR[0xB135 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTSFR(x)                  (*(volatile uint16_t*)(&__MBAR[0xB13E + ((x-1)*0x30)]))
+#define MCF_USB_EPINACR(x)                   (*(volatile uint8_t *)(&__MBAR[0xB149 + ((x-1)*0x30)]))
+#define MCF_USB_EPINMPSR(x)                  (*(volatile uint16_t*)(&__MBAR[0xB14A + ((x-1)*0x30)]))
+#define MCF_USB_EPINIFR(x)                   (*(volatile uint8_t *)(&__MBAR[0xB14C + ((x-1)*0x30)]))
+#define MCF_USB_EPINSR(x)                    (*(volatile uint8_t *)(&__MBAR[0xB14D + ((x-1)*0x30)]))
+#define MCF_USB_EPINSFR(x)                   (*(volatile uint16_t*)(&__MBAR[0xB156 + ((x-1)*0x30)]))
+#define MCF_USB_EPSTAT(x)                    (*(volatile uint32_t*)(&__MBAR[0xB440 + ((x)*0x30)]))
+#define MCF_USB_EPISR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB444 + ((x)*0x30)]))
+#define MCF_USB_EPIMR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB448 + ((x)*0x30)]))
+#define MCF_USB_EPFRCFGR(x)                  (*(volatile uint32_t*)(&__MBAR[0xB44C + ((x)*0x30)]))
+#define MCF_USB_EPFDR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB450 + ((x)*0x30)]))
+#define MCF_USB_EPFSR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB454 + ((x)*0x30)]))
+#define MCF_USB_EPFCR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB458 + ((x)*0x30)]))
+#define MCF_USB_EPFAR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB45C + ((x)*0x30)]))
+#define MCF_USB_EPFRP(x)                     (*(volatile uint32_t*)(&__MBAR[0xB460 + ((x)*0x30)]))
+#define MCF_USB_EPFWP(x)                     (*(volatile uint32_t*)(&__MBAR[0xB464 + ((x)*0x30)]))
+#define MCF_USB_EPLRFP(x)                    (*(volatile uint32_t*)(&__MBAR[0xB468 + ((x)*0x30)]))
+#define MCF_USB_EPLWFP(x)                    (*(volatile uint32_t*)(&__MBAR[0xB46C + ((x)*0x30)]))
+
+
+/* Bit definitions and macros for MCF_USB_USBAISR */
+#define MCF_USB_USBAISR_SETUP                (0x1)
+#define MCF_USB_USBAISR_IN                   (0x2)
+#define MCF_USB_USBAISR_OUT                  (0x4)
+#define MCF_USB_USBAISR_EPHALT               (0x8)
+#define MCF_USB_USBAISR_TRANSERR             (0x10)
+#define MCF_USB_USBAISR_ACK                  (0x20)
+#define MCF_USB_USBAISR_CTROVFL              (0x40)
+#define MCF_USB_USBAISR_EPSTALL              (0x80)
+
+/* Bit definitions and macros for MCF_USB_USBAIMR */
+#define MCF_USB_USBAIMR_SETUPEN              (0x1)
+#define MCF_USB_USBAIMR_INEN                 (0x2)
+#define MCF_USB_USBAIMR_OUTEN                (0x4)
+#define MCF_USB_USBAIMR_EPHALTEN             (0x8)
+#define MCF_USB_USBAIMR_TRANSERREN           (0x10)
+#define MCF_USB_USBAIMR_ACKEN                (0x20)
+#define MCF_USB_USBAIMR_CTROVFLEN            (0x40)
+#define MCF_USB_USBAIMR_EPSTALLEN            (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPINFO */
+#define MCF_USB_EPINFO_EPDIR                 (0x1)
+#define MCF_USB_EPINFO_EPNUM(x)              (((x)&0x7)<<0x1)
+
+/* Bit definitions and macros for MCF_USB_CFGR */
+#define MCF_USB_CFGR_Configuration_Value(x)  (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_CFGAR */
+#define MCF_USB_CFGAR_RESERVED               (0xA0)
+#define MCF_USB_CFGAR_RMTWKEUP               (0xE0)
+
+/* Bit definitions and macros for MCF_USB_SPEEDR */
+#define MCF_USB_SPEEDR_SPEED(x)              (((x)&0x3)<<0)
+
+/* Bit definitions and macros for MCF_USB_FRMNUMR */
+#define MCF_USB_FRMNUMR_FRMNUM(x)            (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPTNR */
+#define MCF_USB_EPTNR_EP1T(x)                (((x)&0x3)<<0)
+#define MCF_USB_EPTNR_EP2T(x)                (((x)&0x3)<<0x2)
+#define MCF_USB_EPTNR_EP3T(x)                (((x)&0x3)<<0x4)
+#define MCF_USB_EPTNR_EP4T(x)                (((x)&0x3)<<0x6)
+#define MCF_USB_EPTNR_EP5T(x)                (((x)&0x3)<<0x8)
+#define MCF_USB_EPTNR_EP6T(x)                (((x)&0x3)<<0xA)
+#define MCF_USB_EPTNR_EPnT1                  (0)
+#define MCF_USB_EPTNR_EPnT2                  (0x1)
+#define MCF_USB_EPTNR_EPnT3                  (0x2)
+
+/* Bit definitions and macros for MCF_USB_IFUR */
+#define MCF_USB_IFUR_ALTSET(x)               (((x)&0xFF)<<0)
+#define MCF_USB_IFUR_IFNUM(x)                (((x)&0xFF)<<0x8)
+
+/* Bit definitions and macros for MCF_USB_IFR */
+#define MCF_USB_IFR_ALTSET(x)                (((x)&0xFF)<<0)
+#define MCF_USB_IFR_IFNUM(x)                 (((x)&0xFF)<<0x8)
+
+/* Bit definitions and macros for MCF_USB_PPCNT */
+#define MCF_USB_PPCNT_PPCNT(x)               (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_DPCNT */
+#define MCF_USB_DPCNT_DPCNT(x)               (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_CRCECNT */
+#define MCF_USB_CRCECNT_CRCECNT(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_BSECNT */
+#define MCF_USB_BSECNT_BSECNT(x)             (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_PIDECNT */
+#define MCF_USB_PIDECNT_PIDECNT(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_FRMECNT */
+#define MCF_USB_FRMECNT_FRMECNT(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_TXPCNT */
+#define MCF_USB_TXPCNT_TXPCNT(x)             (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_CNTOVR */
+#define MCF_USB_CNTOVR_PPCNT                 (0x1)
+#define MCF_USB_CNTOVR_DPCNT                 (0x2)
+#define MCF_USB_CNTOVR_CRCECNT               (0x4)
+#define MCF_USB_CNTOVR_BSECNT                (0x8)
+#define MCF_USB_CNTOVR_PIDECNT               (0x10)
+#define MCF_USB_CNTOVR_FRMECNT               (0x20)
+#define MCF_USB_CNTOVR_TXPCNT                (0x40)
+
+/* Bit definitions and macros for MCF_USB_EP0ACR */
+#define MCF_USB_EP0ACR_TTYPE(x)              (((x)&0x3)<<0)
+#define MCF_USB_EP0ACR_TTYPE_CTRL            (0)
+#define MCF_USB_EP0ACR_TTYPE_ISOC            (0x1)
+#define MCF_USB_EP0ACR_TTYPE_BULK            (0x2)
+#define MCF_USB_EP0ACR_TTYPE_INT             (0x3)
+
+/* Bit definitions and macros for MCF_USB_EP0MPSR */
+#define MCF_USB_EP0MPSR_MAXPKTSZ(x)          (((x)&0x7FF)<<0)
+#define MCF_USB_EP0MPSR_ADDTRANS(x)          (((x)&0x3)<<0xB)
+
+/* Bit definitions and macros for MCF_USB_EP0IFR */
+#define MCF_USB_EP0IFR_IFNUM(x)              (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EP0SR */
+#define MCF_USB_EP0SR_HALT                   (0x1)
+#define MCF_USB_EP0SR_ACTIVE                 (0x2)
+#define MCF_USB_EP0SR_PSTALL                 (0x4)
+#define MCF_USB_EP0SR_CCOMP                  (0x8)
+#define MCF_USB_EP0SR_TXZERO                 (0x20)
+#define MCF_USB_EP0SR_INT                    (0x80)
+
+/* Bit definitions and macros for MCF_USB_BMRTR */
+#define MCF_USB_BMRTR_REC(x)                 (((x)&0x1F)<<0)
+#define MCF_USB_BMRTR_REC_DEVICE             (0)
+#define MCF_USB_BMRTR_REC_INTERFACE          (0x1)
+#define MCF_USB_BMRTR_REC_ENDPOINT           (0x2)
+#define MCF_USB_BMRTR_REC_OTHER              (0x3)
+#define MCF_USB_BMRTR_TYPE(x)                (((x)&0x3)<<0x5)
+#define MCF_USB_BMRTR_TYPE_STANDARD          (0)
+#define MCF_USB_BMRTR_TYPE_CLASS             (0x20)
+#define MCF_USB_BMRTR_TYPE_VENDOR            (0x40)
+#define MCF_USB_BMRTR_DIR                    (0x80)
+
+/* Bit definitions and macros for MCF_USB_BRTR */
+#define MCF_USB_BRTR_BREQ(x)                 (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_WVALUER */
+#define MCF_USB_WVALUER_WVALUE(x)            (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_WINDEXR */
+#define MCF_USB_WINDEXR_WINDEX(x)            (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_WLENGTHR */
+#define MCF_USB_WLENGTHR_WLENGTH(x)          (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPOUTACR */
+#define MCF_USB_EPOUTACR_TTYPE(x)            (((x)&0x3)<<0)
+#define MCF_USB_EPOUTACR_TTYPE_ISOC          (0x1)
+#define MCF_USB_EPOUTACR_TTYPE_BULK          (0x2)
+#define MCF_USB_EPOUTACR_TTYPE_INT           (0x3)
+
+/* Bit definitions and macros for MCF_USB_EPOUTMPSR */
+#define MCF_USB_EPOUTMPSR_MAXPKTSZ(x)        (((x)&0x7FF)<<0)
+#define MCF_USB_EPOUTMPSR_ADDTRANS(x)        (((x)&0x3)<<0xB)
+
+/* Bit definitions and macros for MCF_USB_EPOUTIFR */
+#define MCF_USB_EPOUTIFR_IFNUM(x)            (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPOUTSR */
+#define MCF_USB_EPOUTSR_HALT                 (0x1)
+#define MCF_USB_EPOUTSR_ACTIVE               (0x2)
+#define MCF_USB_EPOUTSR_PSTALL               (0x4)
+#define MCF_USB_EPOUTSR_CCOMP                (0x8)
+#define MCF_USB_EPOUTSR_TXZERO               (0x20)
+#define MCF_USB_EPOUTSR_INT                  (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPOUTSFR */
+#define MCF_USB_EPOUTSFR_FRMNUM(x)           (((x)&0x7FF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPINACR */
+#define MCF_USB_EPINACR_TTYPE(x)             (((x)&0x3)<<0)
+#define MCF_USB_EPINACR_TTYPE_ISOC           (0x1)
+#define MCF_USB_EPINACR_TTYPE_BULK           (0x2)
+#define MCF_USB_EPINACR_TTYPE_INT            (0x3)
+
+/* Bit definitions and macros for MCF_USB_EPINMPSR */
+#define MCF_USB_EPINMPSR_MAXPKTSZ(x)         (((x)&0x7FF)<<0)
+#define MCF_USB_EPINMPSR_ADDTRANS(x)         (((x)&0x3)<<0xB)
+
+/* Bit definitions and macros for MCF_USB_EPINIFR */
+#define MCF_USB_EPINIFR_IFNUM(x)             (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPINSR */
+#define MCF_USB_EPINSR_HALT                  (0x1)
+#define MCF_USB_EPINSR_ACTIVE                (0x2)
+#define MCF_USB_EPINSR_PSTALL                (0x4)
+#define MCF_USB_EPINSR_CCOMP                 (0x8)
+#define MCF_USB_EPINSR_TXZERO                (0x20)
+#define MCF_USB_EPINSR_INT                   (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPINSFR */
+#define MCF_USB_EPINSFR_FRMNUM(x)            (((x)&0x7FF)<<0)
+
+/* Bit definitions and macros for MCF_USB_USBSR */
+#define MCF_USB_USBSR_ISOERREP(x)            (((x)&0xF)<<0)
+#define MCF_USB_USBSR_SUSP                   (0x80)
+
+/* Bit definitions and macros for MCF_USB_USBCR */
+#define MCF_USB_USBCR_RESUME                 (0x1)
+#define MCF_USB_USBCR_APPLOCK                (0x2)
+#define MCF_USB_USBCR_RST                    (0x4)
+#define MCF_USB_USBCR_RAMEN                  (0x8)
+#define MCF_USB_USBCR_RAMSPLIT               (0x20)
+
+/* Bit definitions and macros for MCF_USB_DRAMCR */
+#define MCF_USB_DRAMCR_DADR(x)               (((x)&0x3FF)<<0)
+#define MCF_USB_DRAMCR_DSIZE(x)              (((x)&0x7FF)<<0x10)
+#define MCF_USB_DRAMCR_BSY                   (0x40000000)
+#define MCF_USB_DRAMCR_START                 (0x80000000)
+
+/* Bit definitions and macros for MCF_USB_DRAMDR */
+#define MCF_USB_DRAMDR_DDAT(x)               (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_USBISR */
+#define MCF_USB_USBISR_ISOERR                (0x1)
+#define MCF_USB_USBISR_FTUNLCK               (0x2)
+#define MCF_USB_USBISR_SUSP                  (0x4)
+#define MCF_USB_USBISR_RES                   (0x8)
+#define MCF_USB_USBISR_UPDSOF                (0x10)
+#define MCF_USB_USBISR_RSTSTOP               (0x20)
+#define MCF_USB_USBISR_SOF                   (0x40)
+#define MCF_USB_USBISR_MSOF                  (0x80)
+
+/* Bit definitions and macros for MCF_USB_USBIMR */
+#define MCF_USB_USBIMR_ISOERR                (0x1)
+#define MCF_USB_USBIMR_FTUNLCK               (0x2)
+#define MCF_USB_USBIMR_SUSP                  (0x4)
+#define MCF_USB_USBIMR_RES                   (0x8)
+#define MCF_USB_USBIMR_UPDSOF                (0x10)
+#define MCF_USB_USBIMR_RSTSTOP               (0x20)
+#define MCF_USB_USBIMR_SOF                   (0x40)
+#define MCF_USB_USBIMR_MSOF                  (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPSTAT */
+#define MCF_USB_EPSTAT_RST                   (0x1)
+#define MCF_USB_EPSTAT_FLUSH                 (0x2)
+#define MCF_USB_EPSTAT_DIR                   (0x80)
+#define MCF_USB_EPSTAT_BYTECNT(x)            (((x)&0xFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_USB_EPISR */
+#define MCF_USB_EPISR_EOF                    (0x1)
+#define MCF_USB_EPISR_EOT                    (0x4)
+#define MCF_USB_EPISR_FIFOLO                 (0x10)
+#define MCF_USB_EPISR_FIFOHI                 (0x20)
+#define MCF_USB_EPISR_ERR                    (0x40)
+#define MCF_USB_EPISR_EMT                    (0x80)
+#define MCF_USB_EPISR_FU                     (0x100)
+
+/* Bit definitions and macros for MCF_USB_EPIMR */
+#define MCF_USB_EPIMR_EOF                    (0x1)
+#define MCF_USB_EPIMR_EOT                    (0x4)
+#define MCF_USB_EPIMR_FIFOLO                 (0x10)
+#define MCF_USB_EPIMR_FIFOHI                 (0x20)
+#define MCF_USB_EPIMR_ERR                    (0x40)
+#define MCF_USB_EPIMR_EMT                    (0x80)
+#define MCF_USB_EPIMR_FU                     (0x100)
+
+/* Bit definitions and macros for MCF_USB_EPFRCFGR */
+#define MCF_USB_EPFRCFGR_DEPTH(x)            (((x)&0x1FFF)<<0)
+#define MCF_USB_EPFRCFGR_BASE(x)             (((x)&0xFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_USB_EPFDR */
+#define MCF_USB_EPFDR_RX_TXDATA(x)           (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPFSR */
+#define MCF_USB_EPFSR_EMT                    (0x10000)
+#define MCF_USB_EPFSR_ALRM                   (0x20000)
+#define MCF_USB_EPFSR_FU                     (0x40000)
+#define MCF_USB_EPFSR_FR                     (0x80000)
+#define MCF_USB_EPFSR_OF                     (0x100000)
+#define MCF_USB_EPFSR_UF                     (0x200000)
+#define MCF_USB_EPFSR_RXW                    (0x400000)
+#define MCF_USB_EPFSR_FAE                    (0x800000)
+#define MCF_USB_EPFSR_FRM(x)                 (((x)&0xF)<<0x18)
+#define MCF_USB_EPFSR_TXW                    (0x40000000)
+#define MCF_USB_EPFSR_IP                     (0x80000000)
+
+/* Bit definitions and macros for MCF_USB_EPFCR */
+#define MCF_USB_EPFCR_COUNTER(x)             (((x)&0xFFFF)<<0)
+#define MCF_USB_EPFCR_TXWMSK                 (0x40000)
+#define MCF_USB_EPFCR_OFMSK                  (0x80000)
+#define MCF_USB_EPFCR_UFMSK                  (0x100000)
+#define MCF_USB_EPFCR_RXWMSK                 (0x200000)
+#define MCF_USB_EPFCR_FAEMSK                 (0x400000)
+#define MCF_USB_EPFCR_IPMSK                  (0x800000)
+#define MCF_USB_EPFCR_GR(x)                  (((x)&0x7)<<0x18)
+#define MCF_USB_EPFCR_FRM                    (0x8000000)
+#define MCF_USB_EPFCR_TMR                    (0x10000000)
+#define MCF_USB_EPFCR_WFR                    (0x20000000)
+#define MCF_USB_EPFCR_SHAD                   (0x80000000)
+
+/* Bit definitions and macros for MCF_USB_EPFAR */
+#define MCF_USB_EPFAR_ALRMP(x)               (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPFRP */
+#define MCF_USB_EPFRP_RP(x)                  (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPFWP */
+#define MCF_USB_EPFWP_WP(x)                  (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPLRFP */
+#define MCF_USB_EPLRFP_LRFP(x)               (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPLWFP */
+#define MCF_USB_EPLWFP_LWFP(x)               (((x)&0xFFF)<<0)
+
+
+#endif /* __MCF5475_USB_H__ */

tos/fpga_test/include/MCF5475_XLB.h

@@ -0,0 +1,101 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_XLB_H__
+#define __MCF5475_XLB_H__
+
+
+/*********************************************************************
+*
+* XL Bus Arbiter (XLB)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_XLB_XARB_CFG                     (*(volatile uint32_t*)(&_MBAR[0x240]))
+#define MCF_XLB_XARB_VER                     (*(volatile uint32_t*)(&_MBAR[0x244]))
+#define MCF_XLB_XARB_SR                      (*(volatile uint32_t*)(&_MBAR[0x248]))
+#define MCF_XLB_XARB_IMR                     (*(volatile uint32_t*)(&_MBAR[0x24C]))
+#define MCF_XLB_XARB_ADRCAP                  (*(volatile uint32_t*)(&_MBAR[0x250]))
+#define MCF_XLB_XARB_SIGCAP                  (*(volatile uint32_t*)(&_MBAR[0x254]))
+#define MCF_XLB_XARB_ADRTO                   (*(volatile uint32_t*)(&_MBAR[0x258]))
+#define MCF_XLB_XARB_DATTO                   (*(volatile uint32_t*)(&_MBAR[0x25C]))
+#define MCF_XLB_XARB_BUSTO                   (*(volatile uint32_t*)(&_MBAR[0x260]))
+#define MCF_XLB_XARB_PRIEN                   (*(volatile uint32_t*)(&_MBAR[0x264]))
+#define MCF_XLB_XARB_PRI                     (*(volatile uint32_t*)(&_MBAR[0x268]))
+
+
+/* Bit definitions and macros for MCF_XLB_XARB_CFG */
+#define MCF_XLB_XARB_CFG_AT                  (0x2)
+#define MCF_XLB_XARB_CFG_DT                  (0x4)
+#define MCF_XLB_XARB_CFG_BA                  (0x8)
+#define MCF_XLB_XARB_CFG_PM(x)               (((x)&0x3)<<0x5)
+#define MCF_XLB_XARB_CFG_SP(x)               (((x)&0x7)<<0x8)
+#define MCF_XLB_XARB_CFG_PLDIS               (0x80000000)
+
+/* Bit definitions and macros for MCF_XLB_XARB_VER */
+#define MCF_XLB_XARB_VER_VER(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_SR */
+#define MCF_XLB_XARB_SR_AT                   (0x1)
+#define MCF_XLB_XARB_SR_DT                   (0x2)
+#define MCF_XLB_XARB_SR_BA                   (0x4)
+#define MCF_XLB_XARB_SR_TTM                  (0x8)
+#define MCF_XLB_XARB_SR_ECW                  (0x10)
+#define MCF_XLB_XARB_SR_TTR                  (0x20)
+#define MCF_XLB_XARB_SR_TTA                  (0x40)
+#define MCF_XLB_XARB_SR_MM                   (0x80)
+#define MCF_XLB_XARB_SR_SEA                  (0x100)
+
+/* Bit definitions and macros for MCF_XLB_XARB_IMR */
+#define MCF_XLB_XARB_IMR_ATE                 (0x1)
+#define MCF_XLB_XARB_IMR_DTE                 (0x2)
+#define MCF_XLB_XARB_IMR_BAE                 (0x4)
+#define MCF_XLB_XARB_IMR_TTME                (0x8)
+#define MCF_XLB_XARB_IMR_ECWE                (0x10)
+#define MCF_XLB_XARB_IMR_TTRE                (0x20)
+#define MCF_XLB_XARB_IMR_TTAE                (0x40)
+#define MCF_XLB_XARB_IMR_MME                 (0x80)
+#define MCF_XLB_XARB_IMR_SEAE                (0x100)
+
+/* Bit definitions and macros for MCF_XLB_XARB_ADRCAP */
+#define MCF_XLB_XARB_ADRCAP_ADRCAP(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_SIGCAP */
+#define MCF_XLB_XARB_SIGCAP_TT(x)            (((x)&0x1F)<<0)
+#define MCF_XLB_XARB_SIGCAP_TBST             (0x20)
+#define MCF_XLB_XARB_SIGCAP_TSIZ(x)          (((x)&0x7)<<0x7)
+
+/* Bit definitions and macros for MCF_XLB_XARB_ADRTO */
+#define MCF_XLB_XARB_ADRTO_ADRTO(x)          (((x)&0xFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_DATTO */
+#define MCF_XLB_XARB_DATTO_DATTO(x)          (((x)&0xFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_BUSTO */
+#define MCF_XLB_XARB_BUSTO_BUSTO(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_PRIEN */
+#define MCF_XLB_XARB_PRIEN_M0                (0x1)
+#define MCF_XLB_XARB_PRIEN_M2                (0x4)
+#define MCF_XLB_XARB_PRIEN_M3                (0x8)
+
+/* Bit definitions and macros for MCF_XLB_XARB_PRI */
+#define MCF_XLB_XARB_PRI_M0P(x)              (((x)&0x7)<<0)
+#define MCF_XLB_XARB_PRI_M2P(x)              (((x)&0x7)<<0x8)
+#define MCF_XLB_XARB_PRI_M3P(x)              (((x)&0x7)<<0xC)
+
+
+#endif /* __MCF5475_XLB_H__ */

tos/fpga_test/include/bas_printf.h

@@ -31,5 +31,5 @@ extern int sprintf(char *str, const char *format, ...);
 
 
 extern void display_progress(void);
-extern void hexdump(uint8_t buffer[], int size);
+extern void hexdump(volatile uint8_t buffer[], int size);
 #endif /* _BAS_PRINTF_H_ */

tos/fpga_test/include/bas_string.h

@@ -0,0 +1,47 @@
+/*
+ * bas_string.h
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  Created on: 26.02.2013
+ *      Author: Markus Fröschle
+ */
+
+#ifndef BAS_STRING_H_
+#define BAS_STRING_H_
+
+#include <stddef.h>
+
+extern int strncmp(const char *s1, const char *s2, size_t max);
+extern char *strcpy(char *dst, const char *src);
+char *strncpy(char *dst, const char *src, size_t max);
+extern int strcmp(const char *s1, const char *s2);
+extern size_t strlen(const char *str);
+extern char *strcat(char *dst, const char *src);
+extern char *strncat(char *dst, const char *src, size_t max);
+extern int atoi(const char *c);
+extern void *memcpy(void *dst, const void *src, size_t n);
+extern void *memset(void *s, int c, size_t n);
+extern int memcmp(const void *s1, const void *s2, size_t max);
+extern void bzero(void *s, size_t n);
+
+#define isdigit(c)	(((c) >= '0') && ((c) <= '9'))
+#define isupper(c)	((c) >= 'A' && ((c) <= 'Z'))
+#define islower(c)	((c) >= 'a' && ((c) <= 'z'))
+#define isalpha(c)	(isupper((c)) || islower(c))
+#define tolower(c)	(isupper(c) ? ((c) + 'a' - 'A') : (c))
+
+#endif /* BAS_STRING_H_ */

tos/fpga_test/include/driver_vec.h

@@ -0,0 +1,125 @@
+/*
+ * driver_vec.h
+ *
+ * Interface for exposure of BaS drivers to the OS
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  Created on: 24.10.2013
+ *      Author: Markus Fröschle
+ */
+
+#ifndef _DRIVER_VEC_H_
+#define _DRIVER_VEC_H_
+
+
+enum driver_type
+{
+	END_OF_DRIVERS,		/* marks end of driver list */
+	BLOCKDEV_DRIVER,
+	CHARDEV_DRIVER,
+	VIDEO_DRIVER,
+	XHDI_DRIVER,
+	MCD_DRIVER,
+};
+
+struct generic_driver_interface
+{
+	uint32_t (*init)(void);
+	uint32_t (*read)(void *buf, size_t count);
+	uint32_t (*write)(const void *buf, size_t count);
+	uint32_t (*ioctl)(uint32_t request, ...);
+};
+
+
+/* Chained buffer descriptor */
+typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
+struct MCD_bufDesc_struct {
+	uint32_t flags;         /* flags describing the DMA */
+    uint32_t csumResult;    /* checksum from checksumming performed since last checksum reset */
+	int8_t  *srcAddr;      /* the address to move data from */
+	int8_t  *destAddr;     /* the address to move data to */
+	int8_t  *lastDestAddr; /* the last address written to */
+    uint32_t dmaSize;       /* the number of bytes to transfer independent of the transfer size */
+    MCD_bufDesc *next; /* next buffer descriptor in chain */
+    uint32_t info;          /* private information about this descriptor;  DMA does not affect it */
+};
+
+/* Progress Query struct */
+typedef volatile struct MCD_XferProg_struct {
+	int8_t *lastSrcAddr;         /* the most-recent or last, post-increment source address */
+	int8_t *lastDestAddr;        /* the most-recent or last, post-increment destination address */
+	uint32_t  dmaSize;            /* the amount of data transferred for the current buffer */
+	MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */
+} MCD_XferProg;
+
+struct dma_driver_interface
+{
+	int32_t version;
+	int32_t magic;
+	int32_t (*dma_set_initiator)(int initiator);
+	uint32_t (*dma_get_initiator)(int requestor);
+	void (*dma_free_initiator)(int requestor);
+	int32_t (*dma_set_channel)(int requestor, void (*handler)(void));
+	int (*dma_get_channel)(int requestor);
+	void (*dma_free_channel)(int requestor);
+	void (*dma_clear_channel)(int channel);
+	int (*MCD_startDma)(int channel, int8_t *srcAddr, int16_t srcIncr, int8_t *destAddr, int16_t destIncr,
+						uint32_t dmaSize, uint32_t xferSize, uint32_t initiator, int32_t priority, uint32_t flags,
+						uint32_t funcDesc);
+	int (*MCD_dmaStatus)(int channel);
+	int (*MCD_XferProgrQuery)(int channel, MCD_XferProg *progRep);
+	int (*MCD_killDma)(int channel);
+	int (*MCD_continDma)(int channel);
+	int (*MCD_pauseDma)(int channel);
+	int (*MCD_resumeDma)(int channel);
+	int (*MCD_csumQuery)(int channel, uint32_t *csum);
+	void *(*dma_malloc)(long amount);
+	int (*dma_free)(void *addr);
+};
+	
+struct xhdi_driver_interface
+{
+	uint32_t (*xhdivec)();
+};
+
+union interface
+{
+	struct generic_driver_interface *gdi;
+	struct xhdi_driver_interface *xhdi;
+	struct dma_driver_interface *dma;
+};
+
+struct generic_interface
+{
+	enum driver_type type;
+	char name[16];
+	char description[64];
+	int version;
+	int revision;
+	union interface interface;
+};
+
+struct driver_table
+{
+	uint32_t bas_version;
+	uint32_t bas_revision;
+	uint32_t (*remove_handler)();			/* calling this will disable the BaS' hook into trap #0 */
+	struct generic_interface *interfaces;
+};
+
+
+#endif /* _DRIVER_VEC_H_ */

tos/fpga_test/sources/bas_printf.c

@@ -417,27 +417,28 @@ void display_progress()
     xputchar('\r');
 }
 
-void hexdump(uint8_t buffer[], int size)
+void hexdump(volatile uint8_t buffer[], int size)
 {
    int i;
    int line = 0;
-   uint8_t *bp = buffer;
+   volatile uint8_t *bp = buffer;
 
    while (bp < buffer + size) {
-      uint8_t *lbp = bp;
+      volatile uint8_t *lbp = bp;
 
       xprintf("%08x  ", line);
 
       for (i = 0; i < 16; i++) {
+          uint8_t c = *lbp++;
          if (bp + i > buffer + size) {
             break;
          }
-         xprintf("%02x ", (uint8_t) *lbp++);
+         xprintf("%02x ", c);
       }
 
       lbp = bp;
       for (i = 0; i < 16; i++) {
-         int8_t c = *lbp++;
+         volatile int8_t c = *lbp++;
 
          if (bp + i > buffer + size) {
             break;

tos/fpga_test/sources/bas_string.c

@@ -26,9 +26,8 @@
 
 void *memcpy(void *dst, const void *src, size_t n)
 {
-    uint8_t *to = dst;
-
-    while (to < (uint8_t *) dst + n)
+    void *to = dst;
+    while (size--)
         *to++ = * (uint8_t *) src++;
 
     return dst;

tos/fpga_test/sources/fpga_test.c

@@ -0,0 +1,152 @@
+#include <stdio.h>
+#include <mint/osbind.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "bas_printf.h"
+#include "MCF5475.h"
+#include "driver_vec.h"
+
+#define FPGA_CONFIG                         (1 << 2)
+#define FPGA_CONF_DONE                      (1 << 5)
+
+#define SRAM1_START     0xff101000
+#define SRAM1_END       SRAM1_START + 0x1000
+#define SAFE_STACK      SRAM1_END - 4
+
+#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory")
+
+#define SYSCLK 132000
+
+long bas_start = 0xe0000000;
+extern volatile uint32_t _VRAM[];
+
+volatile int32_t time, start, end;
+int i;
+
+void do_tests(void)
+{
+    volatile unsigned long *t1 = (volatile unsigned long *) 0xf0000000;
+    volatile unsigned short *t2 = (volatile unsigned short *) 0xf0000000;
+    volatile unsigned short *t3 = (volatile unsigned short *) 0xf0000002;
+    long value = 0;
+
+    while (1)
+    {
+        *t1 = value;
+        *t2 = (short) value;
+        *t3 = (short) (value >> 16);
+        xprintf("W: 0x%lx R: 0x%lx W: 0x%04x R: 0x%04x W: 0x%04x R: 0x%04x\r\n", value, *t1,
+                 (unsigned short) value, *t2, (unsigned short)(value >> 16), *t3);
+        value++;
+    }
+}
+
+
+void wait_for_jtag(void)
+{
+    long i;
+
+    /* set supervisor stack to end of SRAM1 */
+    __asm__ __volatile__ (
+        "       move    #0x2700,sr\n\t"         /* disable interrupts */
+        "       move.l  %[stack],d0\n\t"        /* 4KB on-chip core SRAM1 */
+        "       move.l  d0,sp\n\t"              /* set stack pointer */
+        :
+        : [stack] "i" (SAFE_STACK)
+        : "d0", "cc"    /* clobber */
+    );
+
+    MCF_EPORT_EPIER = 0x0;              /* disable EPORT interrupts */
+    MCF_INTC_IMRL = 0xffffffff;
+    MCF_INTC_IMRH = 0xffffffff;         /* disable interrupt controller */
+
+    MCF_MMU_MMUCR &= ~MCF_MMU_MMUCR_EN; /* disable MMU */
+
+    xprintf("relocated supervisor stack, disabled interrupts and disabled MMU\r\n");
+
+    /*
+     * configure FEC1L port directions to enable external JTAG configuration download to FPGA
+     */
+    MCF_GPIO_PDDR_FEC1L = 0 |
+                          MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4;  /* bit 4 = LED => output */
+                                                            /* all other bits = input */
+
+    /*
+     * configure DSPI_CS3 as GPIO input to avoid the MCU driving against the FPGA blink
+     */
+    MCF_PAD_PAR_DSPI &= ~MCF_PAD_PAR_DSPI_PAR_CS3(MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3);
+    /*
+     * now that GPIO ports have been switched to input, we can poll for FPGA config
+     * started from the JTAG interface (CONF_DONE goes low) and finish (CONF_DONE goes high)
+     */
+    xprintf("waiting for JTAG configuration start\r\n");
+    while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));       /* wait for JTAG config load started */
+
+    xprintf("waiting for JTAG configuration to finish\r\n");
+    while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));     /* wait for JTAG config load finished */
+
+    xprintf("JTAG configuration finished.\r\n");
+
+    /* wait */
+    xprintf("wait a little to let things settle...\r\n");
+    for (i = 0; i < 100000L; i++);
+
+    xprintf("disable caches\r\n");
+    __asm__ __volatile(
+                "move.l     #0x01000000,d0      \r\n"
+                "movec      d0,CACR             \r\n"
+                : /* no output */
+                : /* no input */
+                : "d0", "memory");
+
+    /* begin of tests */
+
+    do_tests();
+
+    xprintf("wait a little to let things settle...\r\n");
+    for (i = 0; i < 100000L; i++);
+
+    xprintf("INFO: endless loop now. Press reset to reboot\r\n");
+    while (1)
+        ;
+}
+
+int main(int argc, char *argv[])
+{
+    printf("FPGA JTAG configuration support\r\n");
+    printf("test FPGA DDR RAM controller\r\n");
+    printf("\xbd 2014 M. F\x94schle\r\n");
+
+    printf("You may now savely load a new FPGA configuration through the JTAG interface\r\n"
+           "and your Firebee will reboot once finished using that new configuration.\r\n");
+    if (argc == 2)
+    {
+        /*
+         * we got an argument. This is supposed to be the address that we need to jump to after JTAG
+         * configuration has been finished. Meant to support BaS in RAM testing
+         */
+        char *addr_str = argv[1];
+        char *addr = NULL;
+        char *end = NULL;
+
+        addr = (char *) strtol(addr_str, &end, 16);
+        if (addr != NULL && addr <= (char *) 0xe0000000 && addr >= (char *) 0x10000000)
+        {
+            /*
+             * seems to be a valid address
+             */
+            bas_start = (long) addr;
+
+            printf("BaS start address set to %p\r\n", (void *) bas_start);
+        }
+        else
+        {
+            printf("\r\nNote: BaS start address %p not valid. Stick to %p.\r\n", addr, (void *) bas_start);
+        }
+    }
+    Supexec(wait_for_jtag);
+
+    return 0;       /* just to make the compiler happy, we will never return */
+}
+

tos/fpga_test/sources/printf_helper.S

@@ -20,19 +20,19 @@
  *
  * Copyright 2010 - 2012 F. Aschwanden
  * Copyright 2011 - 2012 V. Riviere
- * Copyright 2012        M. Froeschle
+ * Copyright 2012 - 2025 M. Froeschle
  */
 
 
-			.global printf_helper
-printf_helper:
-			.extern		__MBAR
-.wait_txready:
-			move.w		__MBAR+0x8604,d2	// PSCSCR0 status register
-			btst		#10,d2				// space left in TX fifo?
-			beq.s		.wait_txready		// no, loop
-			lea			__MBAR+0x860C,a0	// PSCSTB0 transmitter buffer register
-			move.b		d0,(a0)				// send byte
-			rts
+	.globl	printf_helper
 
-// vim: set syntax=asm68k :
+printf_helper:
+	.extern	__MBAR
+
+.wait_txready:
+	move.w	__MBAR+0x8604,d2		// PSCSCR0 status register
+	btst	#10,d2				// space left in TX fifo?
+	beq.s	.wait_txready			// no, loop
+	lea	__MBAR+0x860C,a0		// PSCSTB0 transmitter buffer register
+	move.b	d0,(a0)				// send byte
+	rts