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Fixed comments (that were obviously copy/pasted wrongly long ago)

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This commit is contained in:
Markus Fröschle
2016-08-02 08:45:26 +00:00
parent bc4a45aba4
commit b2015265e2
4 changed files with 56 additions and 50 deletions
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2
Makefile
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@@ -10,7 +10,7 @@
# can be either "Y" or "N" (without quotes). "Y" for using the m68k-elf-, "N" for using the m68k-atari-mint
# toolchain
COMPILE_ELF=Y
COMPILE_ELF=N
ifeq (Y,$(COMPILE_ELF))
TCPREFIX=m68k-elf-

2
dma/dma.c
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@@ -39,7 +39,7 @@
#error "unknown machine!"
#endif /* MACHINE_FIREBEE */
// #define DBG_DMA
//#define DBG_DMA
#ifdef DBG_DMA
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#else

94
sys/startcf.S
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@@ -4,74 +4,74 @@
* so it will be placed at the very beginning of the ROM.
*/
.equ MCF_MMU_MMUCR, __MMUBAR + 0
.equ MCF_MMU_MMUCR, __MMUBAR + 0
.globl _rom_header
.globl _rom_entry
.globl _rom_header
.globl _rom_entry
.extern _initialize_hardware
.extern _rt_mbar
.extern _initialize_hardware
.extern _rt_mbar
/* ROM header */
_rom_header:
/* The first long is supposed to be the initial SP.
* We replace it by bra.s to allow running the ROM from the first byte.
* Then we add a fake jmp instruction for pretty disassembly.
*/
bra.s _rom_entry // Short jump to the real entry point
.short 0x4ef9 // Fake jmp instruction
/* The second long is the initial PC */
.long _rom_entry // Real entry point
/* The first long is supposed to be the initial SP.
* We replace it by bra.s to allow running the ROM from the first byte.
* Then we add a fake jmp instruction for pretty disassembly.
*/
bra.s _rom_entry // Short jump to the real entry point
.short 0x4ef9 // Fake jmp instruction
/* The second long is the initial PC */
.long _rom_entry // Real entry point
/* ROM entry point */
_rom_entry:
/* disable interrupts */
move.w #0x2700,sr
/* disable interrupts */
move.w #0x2700,sr
#if !defined(MACHINE_M54455) // MCF54455 does not have the MBAR register
/* Initialize MBAR */
move.l #__MBAR,d0
movec d0,MBAR
move.l d0,_rt_mbar
/* Initialize MBAR */
move.l #__MBAR,d0
movec d0,MBAR
move.l d0,_rt_mbar
#endif
/* mmu off */
move.l #__MMUBAR+1,d0
movec d0,MMUBAR
/* mmu off */
move.l #__MMUBAR+1,d0
movec d0,MMUBAR
clr.l d0
move.l d0,MCF_MMU_MMUCR
clr.l d0
move.l d0,MCF_MMU_MMUCR
nop
#if !defined(MACHINE_M54455) // MCF54455 does not have RAMBAR0 and RAMBAR1 registers */
/* Initialize RAMBARs: locate SRAM and validate it */
move.l #__RAMBAR0 + 0x7,d0 // supervisor only
movec d0,RAMBAR0
move.l #__RAMBAR1 + 0x1,d0
movec d0,RAMBAR1
/* Initialize RAMBARs: locate SRAM and validate it */
move.l #__RAMBAR0 + 0x7,d0 // supervisor only
movec d0,RAMBAR0
move.l #__RAMBAR1 + 0x1,d0
movec d0,RAMBAR1
#else
move.l #__RAMBAR0 + 0x7,d0
movec d0,RAMBAR
move.l #__RAMBAR0 + 0x7,d0
movec d0,RAMBAR
#endif
/* set stack pointer to end of SRAM */
lea __SUP_SP,a7
move.l #0,(sp)
/* set stack pointer to end of SRAM */
lea __SUP_SP,a7
move.l #0,(sp)
/*
* Initialize the processor caches.
* The instruction cache is fully enabled.
* The data cache is enabled, but cache-inhibited by default.
* Later, the MMU will fully activate the data cache for specific areas.
* It is important to enable both caches now, otherwise cpushl would hang.
*/
/*
* Initialize the processor caches.
* The instruction cache is fully enabled.
* The data cache is enabled, but cache-inhibited by default.
* Later, the MMU will fully activate the data cache for specific areas.
* It is important to enable both caches now, otherwise cpushl would hang.
*/
move.l #0xa50c8120,d0
movec d0,cacr
andi.l #0xfefbfeff,d0 // Clear invalidate bits
move.l d0,_rt_cacr
move.l #0xa50c8120,d0
movec d0,cacr
andi.l #0xfefbfeff,d0 // Clear invalidate bits
move.l d0,_rt_cacr
/* initialize any hardware specific issues */
bra _initialize_hardware
/* initialize any hardware specific issues */
bra _initialize_hardware

8
sys/sysinit.c
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@@ -425,13 +425,19 @@ static void init_fbcs()
MCF_FBCS2_CSMR = (MCF_FBCS_CSMR_BAM_128M /* F000'0000-F7FF'FFFF */
| MCF_FBCS_CSMR_V);
MCF_FBCS3_CSAR = MCF_FBCS_CSAR_BA(0xF8000000); /* Firebee new I/O address range */
MCF_FBCS3_CSAR = MCF_FBCS_CSAR_BA(0xF8000000); /* Firebee SRAM */
MCF_FBCS3_CSCR = MCF_FBCS_CSCR_PS_16 /* 16 bit port */
| MCF_FBCS_CSCR_WS(32) /* 0 wait states */
| MCF_FBCS_CSCR_AA; /* auto /TA acknowledge */
MCF_FBCS3_CSMR = (MCF_FBCS_CSMR_BAM_64M /* F800'0000-FBFF'FFFF */
| MCF_FBCS_CSMR_V);
/*
* Note: burst read/write settings of the following FBCS are purely "cosmetical".
* The Coldfire FlexBus only "bursts" on a smaller port size than 32 bit up to 32 bit,
* i.e. it can burst on an 8 bit port up to 4 burst cycles or two on a 16 bit port.
* Enabling burst on a 32 bit port has no effect (unfortunately).
*/
MCF_FBCS4_CSAR = MCF_FBCS_CSAR_BA(0x40000000); /* video ram area, FB_CS3 not used, decoded on FPGA */
MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32 /* 32 bit port */
| MCF_FBCS_CSCR_WS(32) /* 0 wait states */