Markus Fröschle
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acaafef944
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added more tests
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2014-12-27 20:22:09 +00:00 |
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Markus Fröschle
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2adda3f946
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various changes
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2014-12-27 20:21:33 +00:00 |
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Markus Fröschle
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6fcd8c2cf2
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disabled caches for tests to work reliably
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2014-12-27 16:49:57 +00:00 |
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Markus Fröschle
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5cb3becb63
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reformatted
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2014-12-27 07:07:46 +00:00 |
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Markus Fröschle
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525253f70a
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compile ELF by default
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2014-12-26 22:15:38 +00:00 |
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Markus Fröschle
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09b8c3acb7
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reformatted
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2014-12-26 22:14:57 +00:00 |
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Markus Fröschle
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851e2a455f
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DDR RAM read and write both seem to work but writing is eeeextreeeeeeemly slow for now...
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2014-12-26 20:01:53 +00:00 |
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Markus Fröschle
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0cc08d4bed
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more FPGA tests
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2014-12-26 20:01:03 +00:00 |
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Markus Fröschle
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0c26287af7
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moved logic into process
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2014-12-26 19:47:22 +00:00 |
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Markus Fröschle
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df5164157d
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fixed earlier misunderstandings, but still doesn't work
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2014-12-26 16:29:40 +00:00 |
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Markus Fröschle
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22f39a7414
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added more FPGA tests
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2014-12-26 15:35:01 +00:00 |
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Markus Fröschle
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aea1a66956
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do first tests with FPGA config. SDRAM doesn't seem to work, reading and writing of Firebee CLUT does work, hovever.
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2014-12-26 12:31:44 +00:00 |
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Markus Fröschle
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6ecdcbb3d1
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added test program for FPGA
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2014-12-26 11:38:27 +00:00 |
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Markus Fröschle
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551375c12e
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fixed to support bugfix from 0.8.6
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2014-12-26 10:33:53 +00:00 |
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Markus Fröschle
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8081df42a6
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merged fixes from 0.8.6.1 (errornous skip of FPGA load)
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2014-12-26 09:36:45 +00:00 |
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Markus Fröschle
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b1c7851f34
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start merging R_0.8.6.1 (jtag load bug fix)
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2014-12-26 09:07:22 +00:00 |
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Markus Fröschle
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8706322f96
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added to the DDR RAM model
reformatted (converted tabs to spaces)
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2014-12-25 15:20:14 +00:00 |
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Markus Fröschle
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a7eb46e158
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used design assistant to force the fitter to put more effort into getting the timing right which removed negative slack
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2014-12-25 10:08:53 +00:00 |
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Markus Fröschle
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674406e4d3
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formatting
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2014-12-24 17:54:51 +00:00 |
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Markus Fröschle
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06688a9a02
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got rid of BIT signal types
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2014-12-24 17:07:51 +00:00 |
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Markus Fröschle
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5a923ddada
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fixed formatting
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2014-12-24 16:24:21 +00:00 |
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Markus Fröschle
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ef1807665e
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removed UNSIGNED() conversions that are not needed anymore
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2014-12-24 16:17:17 +00:00 |
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Markus Fröschle
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517599bc33
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reenabled all modules
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2014-12-24 16:11:12 +00:00 |
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Markus Fröschle
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e7e4fa4e75
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added a little bus toggling to the test bench
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2014-12-24 09:42:57 +00:00 |
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Markus Fröschle
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766d75a5d3
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fixed pin assignments for renamed pins fb_cs_n[..]
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2014-12-23 22:35:03 +00:00 |
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Markus Fröschle
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71db27849b
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started implementing SAMSUNG's Verilog DDR model in VHDL
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2014-12-23 22:30:23 +00:00 |
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Markus Fröschle
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63c0a2f167
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added testbench files
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2014-12-23 18:25:15 +00:00 |
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Markus Fröschle
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5eac75430e
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renamed files, fixed testbench
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2014-12-23 18:20:11 +00:00 |
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Markus Fröschle
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5cc8c3bbbf
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fixed type inconistencies
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2014-12-23 16:44:21 +00:00 |
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Markus Fröschle
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c197609be6
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started "full fledged" testbench to analyze where fb_ta_n gets lost
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2014-12-23 14:56:53 +00:00 |
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Markus Fröschle
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5c9253c6a9
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implemented video_control_register as ALIAS
fb_ta_n stuck at GND?
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2014-12-23 11:21:56 +00:00 |
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Markus Fröschle
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a4835a305c
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experimental
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2014-12-23 08:59:40 +00:00 |
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Markus Fröschle
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1f50d16cfc
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got rid of several unnecessary UNSIGNED() type conversions
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2014-12-23 08:33:59 +00:00 |
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Markus Fröschle
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85ec4c726c
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added io_register.vhd
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2014-12-22 22:14:33 +00:00 |
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Markus Fröschle
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1612d52010
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more formatting
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2014-12-22 21:09:46 +00:00 |
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Markus Fröschle
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0f55615b45
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converted more STD_LOGIC_VECTORs to UNSIGNED
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2014-12-22 19:58:01 +00:00 |
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Markus Fröschle
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822f5a64d2
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finished fixing formatting
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2014-12-22 12:36:35 +00:00 |
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Markus Fröschle
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e2c69a75f6
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changed all STD_LOGIC_VECTOR signals to UNSIGNED to ease calculations
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2014-12-22 12:09:53 +00:00 |
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Markus Fröschle
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e0a1dfedcf
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enabled flow analysis
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2014-12-22 10:05:59 +00:00 |
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Markus Fröschle
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7963f9c8ae
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fixed formatting
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2014-12-22 08:50:22 +00:00 |
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Markus Fröschle
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7d98e35c50
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fixed fifo_mw initialization
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2014-12-22 08:40:35 +00:00 |
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Markus Fröschle
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4bb0527539
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fifo_mw never got a value assigned - fixed for testbench, but still open for toplevel
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2014-12-22 08:31:07 +00:00 |
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Markus Fröschle
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89f75bd4e8
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fixed IRQn[x] to IRQ_n[x]
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2014-12-22 06:42:16 +00:00 |
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Markus Fröschle
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2de4cceb00
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fixed assignment to the new postfixed names
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2014-12-22 06:37:25 +00:00 |
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Markus Fröschle
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5b64c3d6cf
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fixed CLOCK_TICK generic
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2014-12-22 06:09:10 +00:00 |
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Markus Fröschle
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3e769ceeb4
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DDR2 simulation compiles in ModelSim
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2014-12-22 05:57:17 +00:00 |
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Markus Fröschle
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1aab3c25d2
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further extended testbench.
Need to fix difference between clock ticks and TIME in original code
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2014-12-21 20:40:51 +00:00 |
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Markus Fröschle
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9d7858a144
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fixed missing data_in
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2014-12-21 11:13:58 +00:00 |
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Markus Fröschle
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ff7faf4395
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more formatting and corrections of testbench code
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2014-12-21 10:55:49 +00:00 |
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Markus Fröschle
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04c32593cf
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renamed RAM model
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2014-12-21 08:33:17 +00:00 |
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