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Sync with Fredi's source tree 13/06/2015

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Parallel port fix.
This commit is contained in:
David Gálvez
2018-04-09 17:19:13 +02:00
parent 3fb6e3bd8a
commit 68129dbe57
107 changed files with 12435 additions and 27384 deletions
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75
FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd
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-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
-- Created on Fri Oct 16 15:40:59 2009
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY BLITTER IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
nRSTO : IN STD_LOGIC;
MAIN_CLK : IN STD_LOGIC;
FB_ALE : IN STD_LOGIC;
nFB_WR : IN STD_LOGIC;
nFB_OE : IN STD_LOGIC;
FB_SIZE0 : IN STD_LOGIC;
FB_SIZE1 : IN STD_LOGIC;
VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0);
BLITTER_ON : IN STD_LOGIC;
FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
nFB_CS1 : IN STD_LOGIC;
nFB_CS2 : IN STD_LOGIC;
nFB_CS3 : IN STD_LOGIC;
DDRCLK0 : IN STD_LOGIC;
BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0);
BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0);
BLITTER_RUN : OUT STD_LOGIC;
BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0);
BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0);
BLITTER_SIG : OUT STD_LOGIC;
BLITTER_WR : OUT STD_LOGIC;
BLITTER_TA : OUT STD_LOGIC;
FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0)
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END BLITTER;
-- Architecture Body
ARCHITECTURE BLITTER_architecture OF BLITTER IS
BEGIN
BLITTER_RUN <= '0';
BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0";
BLITTER_ADR <= x"76543210";
BLITTER_SIG <= '0';
BLITTER_WR <= '0';
BLITTER_TA <= '0';
END BLITTER_architecture;

75
FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd.bak
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-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
-- Created on Fri Oct 16 15:40:59 2009
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY BLITTER IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
nRSTO : IN STD_LOGIC;
MAIN_CLK : IN STD_LOGIC;
FB_ALE : IN STD_LOGIC;
nFB_WR : IN STD_LOGIC;
nFB_OE : IN STD_LOGIC;
FB_SIZE0 : IN STD_LOGIC;
FB_SIZE1 : IN STD_LOGIC;
VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0);
BLITTER_ON : IN STD_LOGIC;
FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
nFB_CS1 : IN STD_LOGIC;
nFB_CS2 : IN STD_LOGIC;
nFB_CS3 : IN STD_LOGIC;
DDRCLK0 : IN STD_LOGIC;
BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0);
BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0);
BLITTER_RUN : OUT STD_LOGIC;
BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0);
BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0);
BLITTER_SIG : OUT STD_LOGIC;
BLITTER_WR : OUT STD_LOGIC;
BLITTER_TA : OUT STD_LOGIC;
FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0)
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END BLITTER;
-- Architecture Body
ARCHITECTURE BLITTER_architecture OF BLITTER IS
BEGIN
BLITTER_RUN <= '0';
BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0";
BLITTER_ADR <= x"FEDCBA9876543210";
BLITTER_SIG <= '0';
BLITTER_WR <= '0';
BLITTER_TA <= '0';
END BLITTER_architecture;

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FPGA_by_Fredi/Video/BLITTER/altsyncram0.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 256 128)
(text "altsyncram0" (rect 84 2 187 21)(font "Arial" (font_size 10)))
(text "inst" (rect 8 109 31 124)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "data[15..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
(text "data[15..0]" (rect 4 16 66 32)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 112 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "address[3..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
(text "address[3..0]" (rect 4 32 80 48)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 112 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "wren" (rect 0 0 31 16)(font "Arial" (font_size 8)))
(text "wren" (rect 4 48 31 64)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 112 64)(line_width 1))
)
(port
(pt 0 88)
(input)
(text "byteena_a[1..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
(text "byteena_a[1..0]" (rect 4 72 94 88)(font "Arial" (font_size 8)))
(line (pt 0 88)(pt 112 88)(line_width 3))
)
(port
(pt 0 104)
(input)
(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
(text "clock" (rect 4 88 35 104)(font "Arial" (font_size 8)))
(line (pt 0 104)(pt 104 104)(line_width 1))
)
(port
(pt 256 32)
(output)
(text "q[15..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
(text "q[15..0]" (rect 209 16 253 32)(font "Arial" (font_size 8)))
(line (pt 256 32)(pt 168 32)(line_width 3))
)
(drawing
(text "16 Word(s)" (rect 133 35 147 90)(font "Arial" )(vertical))
(text "RAM" (rect 149 49 163 72)(font "Arial" )(vertical))
(text "Block Type: AUTO" (rect 41 106 129 120)(font "Arial" ))
(line (pt 128 24)(pt 168 24)(line_width 1))
(line (pt 168 24)(pt 168 96)(line_width 1))
(line (pt 168 96)(pt 128 96)(line_width 1))
(line (pt 128 96)(pt 128 24)(line_width 1))
(line (pt 112 27)(pt 120 27)(line_width 1))
(line (pt 120 27)(pt 120 39)(line_width 1))
(line (pt 120 39)(pt 112 39)(line_width 1))
(line (pt 112 39)(pt 112 27)(line_width 1))
(line (pt 112 34)(pt 114 36)(line_width 1))
(line (pt 114 36)(pt 112 38)(line_width 1))
(line (pt 104 36)(pt 112 36)(line_width 1))
(line (pt 120 32)(pt 128 32)(line_width 3))
(line (pt 112 43)(pt 120 43)(line_width 1))
(line (pt 120 43)(pt 120 55)(line_width 1))
(line (pt 120 55)(pt 112 55)(line_width 1))
(line (pt 112 55)(pt 112 43)(line_width 1))
(line (pt 112 50)(pt 114 52)(line_width 1))
(line (pt 114 52)(pt 112 54)(line_width 1))
(line (pt 104 52)(pt 112 52)(line_width 1))
(line (pt 120 48)(pt 128 48)(line_width 3))
(line (pt 112 59)(pt 120 59)(line_width 1))
(line (pt 120 59)(pt 120 71)(line_width 1))
(line (pt 120 71)(pt 112 71)(line_width 1))
(line (pt 112 71)(pt 112 59)(line_width 1))
(line (pt 112 66)(pt 114 68)(line_width 1))
(line (pt 114 68)(pt 112 70)(line_width 1))
(line (pt 104 68)(pt 112 68)(line_width 1))
(line (pt 120 64)(pt 128 64)(line_width 1))
(line (pt 112 83)(pt 120 83)(line_width 1))
(line (pt 120 83)(pt 120 95)(line_width 1))
(line (pt 120 95)(pt 112 95)(line_width 1))
(line (pt 112 95)(pt 112 83)(line_width 1))
(line (pt 112 90)(pt 114 92)(line_width 1))
(line (pt 114 92)(pt 112 94)(line_width 1))
(line (pt 104 92)(pt 112 92)(line_width 1))
(line (pt 120 88)(pt 128 88)(line_width 3))
(line (pt 104 36)(pt 104 105)(line_width 1))
)
)

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FPGA_by_Fredi/Video/BLITTER/altsyncram0.cmp Normal file
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--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component altsyncram0
PORT
(
address : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '1');
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component;

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FPGA_by_Fredi/Video/BLITTER/altsyncram0.inc Normal file
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--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION altsyncram0
(
address[3..0],
byteena_a[1..0],
clock,
data[15..0],
wren
)
RETURNS (
q[15..0]
);

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FPGA_by_Fredi/Video/BLITTER/altsyncram0.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTSYNCRAM"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.cmp"]

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FPGA_by_Fredi/Video/BLITTER/altsyncram0.tdf Normal file
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-- megafunction wizard: %ALTSYNCRAM%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: altsyncram0.tdf
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
INCLUDE "altsyncram.inc";
SUBDESIGN altsyncram0
(
address[3..0] : INPUT;
byteena_a[1..0] : INPUT = VCC;
clock : INPUT = VCC;
data[15..0] : INPUT;
wren : INPUT = GND;
q[15..0] : OUTPUT;
)
VARIABLE
altsyncram_component : altsyncram WITH (
BYTE_SIZE = 8,
CLOCK_ENABLE_INPUT_A = "BYPASS",
CLOCK_ENABLE_OUTPUT_A = "BYPASS",
INTENDED_DEVICE_FAMILY = "Cyclone III",
LPM_HINT = "ENABLE_RUNTIME_MOD=NO",
LPM_TYPE = "altsyncram",
NUMWORDS_A = 16,
OPERATION_MODE = "SINGLE_PORT",
OUTDATA_ACLR_A = "NONE",
OUTDATA_REG_A = "UNREGISTERED",
POWER_UP_UNINITIALIZED = "FALSE",
READ_DURING_WRITE_MODE_PORT_A = "NEW_DATA_WITH_NBE_READ",
READ_DURING_WRITE_MODE_PORT_B = "NEW_DATA_WITH_NBE_READ",
WIDTHAD_A = 4,
WIDTH_A = 16,
WIDTH_BYTEENA_A = 2
);
BEGIN
q[15..0] = altsyncram_component.q_a[15..0];
altsyncram_component.wren_a = wren;
altsyncram_component.clock0 = clock;
altsyncram_component.byteena_a[1..0] = byteena_a[1..0];
altsyncram_component.address_a[3..0] = address[3..0];
altsyncram_component.data_a[15..0] = data[15..0];
END;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "256"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "1"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_WITH_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_WITH_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
-- Retrieval info: USED_PORT: address 0 0 4 0 INPUT NODEFVAL address[3..0]
-- Retrieval info: USED_PORT: byteena_a 0 0 2 0 INPUT VCC byteena_a[1..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND wren
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: CONNECT: @address_a 0 0 4 0 address 0 0 4 0
-- Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena_a 0 0 2 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.tdf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_inst.tdf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf

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<html>
<head>
<title>Sample Waveforms for "altsyncram0.tdf" </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file "altsyncram0.tdf" </CENTER></h2>
<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design "altsyncram0.tdf". For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( FFF0, FFF1, FFF2, FFF3, ...). The design "altsyncram0.tdf" has </P>
<CENTER><img src=altsyncram0_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. </P>
<P></P>
</body>
</html>

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FPGA_by_Fredi/Video/BLITTER/blitter.tdf.ALT Normal file
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-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2010 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
-- Created on Sat Jan 15 11:06:17 2011
INCLUDE "lpm_bustri_WORD.inc";
INCLUDE "VIDEO/BLITTER/lpm_clshift0.INC";
CONSTANT BL_SKEW_LF = 255;
-- Title Statement (optional)
TITLE "Blitter";
-- Parameters Statement (optional)
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-- Subdesign Section
SUBDESIGN BLITTER
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
nRSTO : INPUT;
MAIN_CLK : INPUT;
FB_ALE : INPUT;
nFB_WR : INPUT;
nFB_OE : INPUT;
FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT;
VIDEO_RAM_CTR[15..0] : INPUT;
BLITTER_ON : INPUT;
FB_ADR[31..0] : INPUT;
nFB_CS1 : INPUT;
nFB_CS2 : INPUT;
nFB_CS3 : INPUT;
DDRCLK0 : INPUT;
BLITTER_DIN[127..0] : INPUT;
BLITTER_DACK[4..0] : INPUT;
SR_BLITTER_DACK : INPUT;
BLITTER_RUN : OUTPUT;
BLITTER_DOUT[127..0] : OUTPUT;
BLITTER_ADR[31..0] : OUTPUT;
BLITTER_SIG : OUTPUT;
BLITTER_WR : OUTPUT;
BLITTER_TA : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
VARIABLE
FB_B[3..0] :NODE;
FB_16B[1..0] :NODE;
BLITTER_CS :NODE;
BL_HRAM0_CS :NODE;
BL_HRAM0[15..0] :DFFE;
BL_HRAM1_CS :NODE;
BL_HRAM1[15..0] :DFFE;
BL_HRAM2_CS :NODE;
BL_HRAM2[15..0] :DFFE;
BL_HRAM3_CS :NODE;
BL_HRAM3[15..0] :DFFE;
BL_HRAM4_CS :NODE;
BL_HRAM4[15..0] :DFFE;
BL_HRAM5_CS :NODE;
BL_HRAM5[15..0] :DFFE;
BL_HRAM6_CS :NODE;
BL_HRAM6[15..0] :DFFE;
BL_HRAM7_CS :NODE;
BL_HRAM7[15..0] :DFFE;
BL_HRAM8_CS :NODE;
BL_HRAM8[15..0] :DFFE;
BL_HRAM9_CS :NODE;
BL_HRAM9[15..0] :DFFE;
BL_HRAMA_CS :NODE;
BL_HRAMA[15..0] :DFFE;
BL_HRAMB_CS :NODE;
BL_HRAMB[15..0] :DFFE;
BL_HRAMC_CS :NODE;
BL_HRAMC[15..0] :DFFE;
BL_HRAMD_CS :NODE;
BL_HRAMD[15..0] :DFFE;
BL_HRAME_CS :NODE;
BL_HRAME[15..0] :DFFE;
BL_HRAMF_CS :NODE;
BL_HRAMF[15..0] :DFFE;
BL_SRC_X_INC_CS :NODE;
BL_SRC_X_INC[15..0] :DFFE;
BL_SRC_Y_INC_CS :NODE;
BL_SRC_Y_INC[15..0] :DFFE;
BL_ENDMASK1_CS :NODE;
BL_ENDMASK1[15..0] :DFFE;
BL_ENDMASK2_CS :NODE;
BL_ENDMASK2[15..0] :DFFE;
BL_ENDMASK3_CS :NODE;
BL_ENDMASK3[15..0] :DFFE;
BL_SRC_ADRH_CS :NODE;
BL_SRC_ADRL_CS :NODE;
BL_SRC_ADR[31..0] :DFFE;
BL_DST_X_INC_CS :NODE;
BL_DST_X_INC[15..0] :DFFE;
BL_DST_Y_INC_CS :NODE;
BL_DST_Y_INC[15..0] :DFFE;
BL_DST_ADRH_CS :NODE;
BL_DST_ADRL_CS :NODE;
BL_DST_ADR[31..0] :DFFE;
BL_X_CNT_CS :NODE;
BL_X_CNT[15..0] :DFFE;
BL_Y_CNT_CS :NODE;
BL_Y_CNT[15..0] :DFFE;
BL_HT_OP_CS :NODE;
BL_HT_OP[7..0] :DFFE;
BL_LC_OP[7..0] :DFFE;
BL_LN_CS :NODE;
BL_LN[7..0] :DFFE;
BL_SKEW[7..0] :DFFE;
BL_SKEW_EXT[6..0] :NODE;
BL_SKEW_IN[255..0] :DFFE;
BL_SKEW_OUT[255..0] :DFFE;
BL_DATA_DDR_READY :DFF; -- 1 WENN DATEN GESCHRIEBEN ODER LESBAR
BL_READ_SRC :DFFE;
BL_DST_BUFFER[127..0] :DFFE;
BL_READ_DST :DFFE;
COUNT[18..0] :DFF;
BEGIN
-- BYT SELECT 32 BIT
FB_B0 = FB_ADR[1..0]==0; -- ADR==0
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- BYT SELECT 16 BIT
FB_16B0 = FB_ADR[0]==0; -- ADR==0
FB_16B1 = FB_ADR[0]==1 -- ADR==1
# !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT
-- BLITTER CS
BLITTER_CS = !nFB_CS1 & FB_ADR[19..6]==H"3E28"; -- FFFF8A00-3F/40
BLITTER_TA = BLITTER_CS;
-- REGISTER
-- HALFTON RAM 0
BL_HRAM0[].CLK = MAIN_CLK;
BL_HRAM0[15..0] = FB_AD[31..16];
BL_HRAM0_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C500"; -- $F8A00/2
BL_HRAM0[15..8].ENA = BL_HRAM0_CS & !nFB_WR & FB_16B0;
BL_HRAM0[7..0].ENA = BL_HRAM0_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 1
BL_HRAM1[].CLK = MAIN_CLK;
BL_HRAM1[15..0] = FB_AD[31..16];
BL_HRAM1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C501"; -- $F8A02/2
BL_HRAM1[15..8].ENA = BL_HRAM1_CS & !nFB_WR & FB_16B0;
BL_HRAM1[7..0].ENA = BL_HRAM1_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 2
BL_HRAM2[].CLK = MAIN_CLK;
BL_HRAM2[15..0] = FB_AD[31..16];
BL_HRAM2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C502"; -- $F8A04/2
BL_HRAM2[15..8].ENA = BL_HRAM2_CS & !nFB_WR & FB_16B0;
BL_HRAM2[7..0].ENA = BL_HRAM2_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 3
BL_HRAM3[].CLK = MAIN_CLK;
BL_HRAM3[15..0] = FB_AD[31..16];
BL_HRAM3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C503"; -- $F8A06/2
BL_HRAM3[15..8].ENA = BL_HRAM3_CS & !nFB_WR & FB_16B0;
BL_HRAM3[7..0].ENA = BL_HRAM3_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 4
BL_HRAM4[].CLK = MAIN_CLK;
BL_HRAM4[15..0] = FB_AD[31..16];
BL_HRAM4_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C504"; -- $F8A08/2
BL_HRAM4[15..8].ENA = BL_HRAM4_CS & !nFB_WR & FB_16B0;
BL_HRAM4[7..0].ENA = BL_HRAM4_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 5
BL_HRAM5[].CLK = MAIN_CLK;
BL_HRAM5[15..0] = FB_AD[31..16];
BL_HRAM5_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C505"; -- $F8A08/2
BL_HRAM5[15..8].ENA = BL_HRAM5_CS & !nFB_WR & FB_16B0;
BL_HRAM5[7..0].ENA = BL_HRAM5_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 6
BL_HRAM6[].CLK = MAIN_CLK;
BL_HRAM6[15..0] = FB_AD[31..16];
BL_HRAM6_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C506"; -- $F8A08/2
BL_HRAM6[15..8].ENA = BL_HRAM6_CS & !nFB_WR & FB_16B0;
BL_HRAM6[7..0].ENA = BL_HRAM6_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 7
BL_HRAM7[].CLK = MAIN_CLK;
BL_HRAM7[15..0] = FB_AD[31..16];
BL_HRAM7_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C507"; -- $F8A08/2
BL_HRAM7[15..8].ENA = BL_HRAM7_CS & !nFB_WR & FB_16B0;
BL_HRAM7[7..0].ENA = BL_HRAM7_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 8
BL_HRAM8[].CLK = MAIN_CLK;
BL_HRAM8[15..0] = FB_AD[31..16];
BL_HRAM8_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C508"; -- $F8A10/2
BL_HRAM8[15..8].ENA = BL_HRAM8_CS & !nFB_WR & FB_16B0;
BL_HRAM8[7..0].ENA = BL_HRAM8_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 9
BL_HRAM9[].CLK = MAIN_CLK;
BL_HRAM9[15..0] = FB_AD[31..16];
BL_HRAM9_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C509"; -- $F8A12/2
BL_HRAM9[15..8].ENA = BL_HRAM9_CS & !nFB_WR & FB_16B0;
BL_HRAM9[7..0].ENA = BL_HRAM9_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 10
BL_HRAMA[].CLK = MAIN_CLK;
BL_HRAMA[15..0] = FB_AD[31..16];
BL_HRAMA_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50A"; -- $F8A4/2
BL_HRAMA[15..8].ENA = BL_HRAMA_CS & !nFB_WR & FB_16B0;
BL_HRAMA[7..0].ENA = BL_HRAMA_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 11
BL_HRAMB[].CLK = MAIN_CLK;
BL_HRAMB[15..0] = FB_AD[31..16];
BL_HRAMB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50B"; -- $F8A16/2
BL_HRAMB[15..8].ENA = BL_HRAMB_CS & !nFB_WR & FB_16B0;
BL_HRAMB[7..0].ENA = BL_HRAMB_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 12
BL_HRAMC[].CLK = MAIN_CLK;
BL_HRAMC[15..0] = FB_AD[31..16];
BL_HRAMC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50C"; -- $F8A18/2
BL_HRAMC[15..8].ENA = BL_HRAMC_CS & !nFB_WR & FB_16B0;
BL_HRAMC[7..0].ENA = BL_HRAMC_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 13
BL_HRAMD[].CLK = MAIN_CLK;
BL_HRAMD[15..0] = FB_AD[31..16];
BL_HRAMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50D"; -- $F8A1A/2
BL_HRAMD[15..8].ENA = BL_HRAMD_CS & !nFB_WR & FB_16B0;
BL_HRAMD[7..0].ENA = BL_HRAMD_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 14
BL_HRAME[].CLK = MAIN_CLK;
BL_HRAME[15..0] = FB_AD[31..16];
BL_HRAME_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50E"; -- $F8A1C/2
BL_HRAME[15..8].ENA = BL_HRAME_CS & !nFB_WR & FB_16B0;
BL_HRAME[7..0].ENA = BL_HRAME_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 15
BL_HRAMF[].CLK = MAIN_CLK;
BL_HRAMF[15..0] = FB_AD[31..16];
BL_HRAMF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50F"; -- $F8A1E/2
BL_HRAMF[15..8].ENA = BL_HRAMF_CS & !nFB_WR & FB_16B0;
BL_HRAMF[7..0].ENA = BL_HRAMF_CS & !nFB_WR & FB_16B1;
-- SRC X INC
BL_SRC_X_INC[].CLK = MAIN_CLK;
BL_SRC_X_INC[] = FB_AD[31..16];
BL_SRC_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C510"; -- $F8A20/2
BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_X_INC[7..0].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
-- SRC Y INC
BL_SRC_Y_INC[].CLK = MAIN_CLK;
BL_SRC_Y_INC[] = FB_AD[31..16];
BL_SRC_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C511"; -- $F8A22/2
BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_Y_INC[7..0].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
-- SRC ADR HIGH
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[31..16] = FB_AD[31..16];
BL_SRC_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512"; -- $F8A24/2
BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
-- SRC ADR LOW
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[15..0] = FB_AD[31..16];
BL_SRC_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513"; -- $F8A26/2
BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[7..0].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
-- ENDMASK 1
BL_ENDMASK1[].CLK = MAIN_CLK;
BL_ENDMASK1[] = FB_AD[31..16];
BL_ENDMASK1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C514"; -- $F8A28/2
BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
BL_ENDMASK1[7..0].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
-- ENDMASK 2
BL_ENDMASK2[].CLK = MAIN_CLK;
BL_ENDMASK2[] = FB_AD[31..16];
BL_ENDMASK2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C515"; -- $F8A2A/2
BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
BL_ENDMASK2[7..0].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
-- ENDMASK 3
BL_ENDMASK3[].CLK = MAIN_CLK;
BL_ENDMASK3[] = FB_AD[31..16];
BL_ENDMASK3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C516"; -- $F8A2C/2
BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
BL_ENDMASK3[7..0].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
-- DST X INC
BL_DST_X_INC[].CLK = MAIN_CLK;
BL_DST_X_INC[] = FB_AD[31..16];
BL_DST_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C517"; -- $F8A2E/2
BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
BL_DST_X_INC[7..0].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
-- DST Y INC
BL_DST_Y_INC[].CLK = MAIN_CLK;
BL_DST_Y_INC[] = FB_AD[31..16];
BL_DST_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C518"; -- $F8A30/2
BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
BL_DST_Y_INC[7..0].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
-- DST ADR HIGH
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[31..16] = FB_AD[31..16];
BL_DST_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512"; -- $F8A24/2
BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
-- DST ADR LOW
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[15..0] = FB_AD[31..16];
BL_DST_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513"; -- $F8A26/2
BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[7..0].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
-- X COUNT
BL_X_CNT[].CLK = MAIN_CLK;
BL_X_CNT[] = FB_AD[31..16];
BL_X_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51B"; -- $F8A36/2
BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
BL_X_CNT[7..0].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B1;
-- Y COUNT
BL_Y_CNT[].CLK = MAIN_CLK;
BL_Y_CNT[] = FB_AD[31..16];
BL_Y_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51C"; -- $F8A38/2
BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
BL_Y_CNT[7..0].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
-- HALFTONE OP BYT
BL_HT_OP[].CLK = MAIN_CLK;
BL_HT_OP[] = FB_AD[31..24];
BL_HT_OP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51D"; -- $F8A3A/2
BL_HT_OP[7..0].ENA = BL_HT_OP_CS & !nFB_WR & FB_16B0;
-- LOGIC OP BYT
BL_LC_OP[].CLK = MAIN_CLK;
BL_LC_OP[] = FB_AD[23..16];
BL_LC_OP[7..0].ENA = BL_HT_OP_CS & !nFB_WR & FB_16B1; -- $F8A3B
-- LINE NUMBER BYT
BL_LN[].CLK = MAIN_CLK;
BL_LN[] = FB_AD[31..24];
BL_LN_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51E"; -- $F8A3C/2
BL_LN[7..0].ENA = BL_LN_CS & !nFB_WR & FB_16B0;
-- SKEW BYT
BL_SKEW[].CLK = MAIN_CLK;
BL_SKEW[] = FB_AD[31..24];
BL_SKEW[7..0].ENA = BL_LN_CS & !nFB_WR & FB_16B1; -- $F8A3D
--- REGISTER OUT
FB_AD[31..16] = lpm_bustri_WORD(
BL_HRAM0_CS & BL_HRAM0[15..0]
# BL_HRAM1_CS & BL_HRAM1[15..0]
# BL_HRAM2_CS & BL_HRAM2[15..0]
# BL_HRAM3_CS & BL_HRAM3[15..0]
# BL_HRAM4_CS & BL_HRAM4[15..0]
# BL_HRAM5_CS & BL_HRAM5[15..0]
# BL_HRAM6_CS & BL_HRAM6[15..0]
# BL_HRAM7_CS & BL_HRAM7[15..0]
# BL_HRAM8_CS & BL_HRAM8[15..0]
# BL_HRAM9_CS & BL_HRAM9[15..0]
# BL_HRAMA_CS & BL_HRAMA[15..0]
# BL_HRAMB_CS & BL_HRAMB[15..0]
# BL_HRAMC_CS & BL_HRAMC[15..0]
# BL_HRAMD_CS & BL_HRAMD[15..0]
# BL_HRAME_CS & BL_HRAME[15..0]
# BL_HRAMF_CS & BL_HRAMF[15..0]
# BL_SRC_X_INC_CS & BL_SRC_X_INC[]
# BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
# BL_SRC_ADRH_CS & BL_SRC_ADR[31..16]
# BL_SRC_ADRL_CS & BL_SRC_ADR[15..0]
# BL_ENDMASK1_CS & BL_ENDMASK1[]
# BL_ENDMASK2_CS & BL_ENDMASK2[]
# BL_ENDMASK3_CS & BL_ENDMASK3[]
# BL_DST_X_INC_CS & BL_DST_X_INC[]
# BL_DST_Y_INC_CS & BL_DST_Y_INC[]
# BL_DST_ADRH_CS & BL_DST_ADR[31..16]
# BL_DST_ADRL_CS & BL_DST_ADR[15..0]
# BL_X_CNT_CS & BL_X_CNT[]
# BL_Y_CNT_CS & BL_Y_CNT[]
# BL_HT_OP_CS & (BL_HT_OP[],BL_LC_OP[])
# BL_LN_CS & (BL_LN[],BL_SKEW[])
,!nFB_CS1 & FB_ADR[19..6]==H"3E28" & !nFB_OE); -- FFFF8A00-3F/40
-----------------------------------------
--
BL_READ_SRC.CLK = DDRCLK0;
BL_READ_DST.CLK = DDRCLK0;
BLITTER_RUN = VCC;
BLITTER_SIG = VCC;
BLITTER_WR = VCC;
-- READY SIGNAL 1 CLOCK SP<53>TER
BL_DATA_DDR_READY.CLK = DDRCLK0;
BL_DATA_DDR_READY = BL_DATA_DDR_READY & BLITTER_DACK0;
-- SRC BUFFER LADEN
BL_SKEW_IN[].CLK = DDRCLK0;
BL_SKEW_IN[].ENA = BL_DATA_DDR_READY & BL_READ_SRC;
BL_SKEW_IN[255..128] = BLITTER_DIN[];
BL_SKEW_IN[127..0] = BL_SKEW_IN[255..128];
-- DST BUFFER LADEN
BL_DST_BUFFER[].CLK = DDRCLK0;
BL_DST_BUFFER[].ENA = BL_DATA_DDR_READY & BL_READ_DST;
BL_DST_BUFFER[] = BLITTER_DIN[];
-- SKEW EXTENDET
BL_SKEW_EXT[6..4] = BL_SRC_ADR[3..1];
BL_SKEW_EXT[3..0] = BL_SKEW[3..0];
-- SKEW EXT MUX
BL_SKEW_OUT[].CLK = DDRCLK0;
BL_SKEW_OUT[].ENA = BL_DATA_DDR_READY & BL_READ_DST;
BL_SKEW_OUT[] = lpm_clshift0(BL_SKEW_IN[],BL_SKEW_EXT[]); -- BIT 127..0 SIND RELEVANT
COUNT[] = COUNT[] + 16;
COUNT[].CLK = BLITTER_DACK0;
BLITTER_DOUT[] = H"112233445566778899AABBCCDDEEFF00";
BLITTER_ADR[] = (0, COUNT[]) + 400000;
END;

54
FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.bsf Normal file
View File

@@ -0,0 +1,54 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 208 80)
(text "lpm_clshift0" (rect 62 3 162 22)(font "Arial" (font_size 10)))
(text "inst" (rect 8 61 31 76)(font "Arial" ))
(port
(pt 0 24)
(input)
(text "data[255..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
(text "data[255..0]" (rect 20 16 89 32)(font "Arial" (font_size 8)))
(line (pt 0 24)(pt 16 24)(line_width 3))
)
(port
(pt 0 40)
(input)
(text "distance[6..0]" (rect 0 0 93 16)(font "Arial" (font_size 8)))
(text "distance[6..0]" (rect 20 32 99 48)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 16 40)(line_width 3))
)
(port
(pt 208 24)
(output)
(text "result[255..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
(text "result[255..0]" (rect 113 16 189 32)(font "Arial" (font_size 8)))
(line (pt 208 24)(pt 192 24)(line_width 3))
)
(drawing
(text "LOGICAL right shift" (rect 21 50 114 64)(font "Arial" ))
(line (pt 16 16)(pt 16 64)(line_width 1))
(line (pt 192 16)(pt 192 64)(line_width 1))
(line (pt 16 16)(pt 192 16)(line_width 1))
(line (pt 16 64)(pt 192 64)(line_width 1))
)
)

23
FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.cmp Normal file
View File

@@ -0,0 +1,23 @@
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_clshift0
PORT
(
data : IN STD_LOGIC_VECTOR (255 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (255 DOWNTO 0)
);
end component;

24
FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.inc Normal file
View File

@@ -0,0 +1,24 @@
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION lpm_clshift0
(
data[255..0],
distance[6..0]
)
RETURNS (
result[255..0]
);

6
FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.qip Normal file
View File

@@ -0,0 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "LPM_CLSHIFT"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.cmp"]

92
FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.tdf Normal file
View File

@@ -0,0 +1,92 @@
-- megafunction wizard: %LPM_CLSHIFT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_clshift
-- ============================================================
-- File Name: lpm_clshift0.tdf
-- Megafunction Name(s):
-- lpm_clshift
--
-- Simulation Library Files(s):
--
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
INCLUDE "lpm_clshift.inc";
SUBDESIGN lpm_clshift0
(
data[255..0] : INPUT;
distance[6..0] : INPUT;
result[255..0] : OUTPUT;
)
VARIABLE
lpm_clshift_component : lpm_clshift WITH (
LPM_SHIFTTYPE = "LOGICAL",
LPM_TYPE = "LPM_CLSHIFT",
LPM_WIDTH = 256,
LPM_WIDTHDIST = 7
);
BEGIN
result[255..0] = lpm_clshift_component.result[255..0];
lpm_clshift_component.distance[6..0] = distance[6..0];
lpm_clshift_component.direction = VCC;
lpm_clshift_component.data[255..0] = data[255..0];
END;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_SHIFTTYPE NUMERIC "0"
-- Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "256"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: lpm_width_varies NUMERIC "0"
-- Retrieval info: PRIVATE: lpm_widthdist NUMERIC "7"
-- Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "1"
-- Retrieval info: PRIVATE: port_direction NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_SHIFTTYPE STRING "LOGICAL"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CLSHIFT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "256"
-- Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "7"
-- Retrieval info: USED_PORT: data 0 0 256 0 INPUT NODEFVAL data[255..0]
-- Retrieval info: USED_PORT: distance 0 0 7 0 INPUT NODEFVAL distance[6..0]
-- Retrieval info: USED_PORT: result 0 0 256 0 OUTPUT NODEFVAL result[255..0]
-- Retrieval info: CONNECT: @distance 0 0 7 0 distance 0 0 7 0
-- Retrieval info: CONNECT: @data 0 0 256 0 data 0 0 256 0
-- Retrieval info: CONNECT: result 0 0 256 0 @result 0 0 256 0
-- Retrieval info: CONNECT: @direction 0 0 0 0 VCC 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.tdf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0_inst.tdf FALSE

6
FPGA_by_Fredi/Video/DDR_CTR.tdf
View File

@@ -373,8 +373,8 @@ BEGIN
VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
BA_S[] = CPU_AC & CPU_BA[]
# BLITTER_AC & BLITTER_BA[];
SR_VDMP[7..4] = FB_B[]; -- BYTE ENABLE WRITE
SR_VDMP[3..0] = LINE & B"1111"; -- LINE ENABLE WRITE
SR_VDMP[7..4] = FB_B[] # BLITTER_AC & B"1111"; -- BYTE ENABLE WRITE, BEI BLITTER IMMER LINE
SR_VDMP[3..0] = (LINE # BLITTER_AC) & B"1111"; -- LINE ENABLE WRITE, BEI BLITTER IMMER LINE
DDR_SM = DS_T6W;
WHEN DS_T6W =>
@@ -384,7 +384,7 @@ BEGIN
VWE = VCC;
SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV
SR_VDMP[] = (LINE # BLITTER_AC) & B"11111111"; -- WENN LINE DANN ACTIV
DDR_SM = DS_T7W;
WHEN DS_T7W =>

1
FPGA_by_Fredi/Video/DDR_CTR.tdf.bak
View File

@@ -43,7 +43,6 @@ SUBDESIGN DDR_CTR
nVCAS : OUTPUT;
FB_LE[3..0] : OUTPUT;
FB_VDOE[3..0] : OUTPUT;
CLEAR_FIFO_CNT : OUTPUT;
SR_FIFO_WRE : OUTPUT;
SR_DDR_FB : OUTPUT;
SR_DDR_WR : OUTPUT;

2
FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
View File

@@ -620,7 +620,7 @@ BEGIN
VERZ[][8] = VERZ[][7];
VERZ[][9] = VERZ[][8];
VERZ[0][0] = DISP_ON;
VERZ[1][0] = HSYNC_I[]!=0;
-- VERZ[1][0] = HSYNC_I[]!=0;
VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
# ACP_VCTR15 & VDL_VCT6 & HSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE
VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0

6
FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
View File

@@ -650,11 +650,11 @@ BEGIN
START_ZEILE.ENA = LAST;
START_ZEILE = VVCNT[]==0; -- ZEILE 1
SYNC_PIX.CLK = PIXEL_CLK;
SYNC_PIX = VHCNT[]==1 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX = VHCNT[]==3 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX1.CLK = PIXEL_CLK;
SYNC_PIX1 = VHCNT[]==3 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX1 = VHCNT[]==5 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX2.CLK = PIXEL_CLK;
SYNC_PIX2 = VHCNT[]==5 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX2 = VHCNT[]==7 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX; --count up if display on sonst clear bei sync pix

380
FPGA_by_Fredi/Video/Video.bdf
View File

@@ -6758,124 +6758,6 @@ applicable agreement for further details.
(line (pt 22 96)(pt 16 102)(line_width 1))
)
)
(block
(rect 296 2552 568 3000)
(text "BLITTER" (rect 5 5 65 21)(font "Arial" (font_size 8))) (text "BLITTER" (rect 5 434 62 449)(font "Arial" )) (block_io "nRSTO" (input))
(block_io "MAIN_CLK" (input))
(block_io "FB_ALE" (input))
(block_io "nFB_WR" (input))
(block_io "nFB_OE" (input))
(block_io "FB_SIZE0" (input))
(block_io "FB_SIZE1" (input))
(block_io "VIDEO_RAM_CTR[15..0]" (input))
(block_io "BLITTER_ON" (input))
(block_io "FB_ADR[31..0]" (input))
(block_io "nFB_CS1" (input))
(block_io "nFB_CS2" (input))
(block_io "nFB_CS3" (input))
(block_io "DDRCLK0" (input))
(block_io "BLITTER_DIN[127..0]" (input))
(block_io "BLITTER_DACK[4..0]" (input))
(block_io "BLITTER_RUN" (output))
(block_io "BLITTER_DOUT[127..0]" (output))
(block_io "BLITTER_ADR[31..0]" (output))
(block_io "BLITTER_SIG" (output))
(block_io "BLITTER_WR" (output))
(block_io "BLITTER_TA" (output))
(block_io "FB_AD[31..0]" (bidir))
(mapper
(pt 272 176)
(bidir)
)
(mapper
(pt 272 208)
(bidir)
)
(mapper
(pt 272 240)
(bidir)
)
(mapper
(pt 272 264)
(bidir)
)
(mapper
(pt 272 288)
(bidir)
)
(mapper
(pt 0 384)
(bidir)
)
(mapper
(pt 272 72)
(bidir)
)
(mapper
(pt 0 56)
(bidir)
)
(mapper
(pt 0 32)
(bidir)
)
(mapper
(pt 0 296)
(bidir)
)
(mapper
(pt 0 272)
(bidir)
)
(mapper
(pt 0 104)
(bidir)
)
(mapper
(pt 0 128)
(bidir)
)
(mapper
(pt 0 80)
(bidir)
)
(mapper
(pt 0 248)
(bidir)
)
(mapper
(pt 0 224)
(bidir)
)
(mapper
(pt 0 200)
(bidir)
)
(mapper
(pt 0 176)
(bidir)
)
(mapper
(pt 0 152)
(bidir)
)
(mapper
(pt 0 360)
(bidir)
)
(mapper
(pt 0 328)
(bidir)
)
(mapper
(pt 272 424)
(bidir)
)
(mapper
(pt 0 408)
(bidir)
)
)
(block
(rect 1664 1664 2016 2600)
(text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 5 211 21)(font "Arial" (font_size 8))) (text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 922 200 937)(font "Arial" )) (block_io "nRSTO" (input))
@@ -7322,6 +7204,129 @@ applicable agreement for further details.
(bidir)
)
)
(block
(rect 296 2552 568 3040)
(text "BLITTER" (rect 5 5 65 21)(font "Arial" (font_size 8))) (text "BLITTER" (rect 5 474 62 489)(font "Arial" )) (block_io "nRSTO" (input))
(block_io "MAIN_CLK" (input))
(block_io "FB_ALE" (input))
(block_io "nFB_WR" (input))
(block_io "nFB_OE" (input))
(block_io "FB_SIZE0" (input))
(block_io "FB_SIZE1" (input))
(block_io "VIDEO_RAM_CTR[15..0]" (input))
(block_io "BLITTER_ON" (input))
(block_io "FB_ADR[31..0]" (input))
(block_io "nFB_CS1" (input))
(block_io "nFB_CS2" (input))
(block_io "nFB_CS3" (input))
(block_io "DDRCLK0" (input))
(block_io "BLITTER_DIN[127..0]" (input))
(block_io "BLITTER_DACK[4..0]" (input))
(block_io "SR_BLITTER_DACK" (input))
(block_io "BLITTER_RUN" (output))
(block_io "BLITTER_DOUT[127..0]" (output))
(block_io "BLITTER_ADR[31..0]" (output))
(block_io "BLITTER_SIG" (output))
(block_io "BLITTER_WR" (output))
(block_io "BLITTER_TA" (output))
(block_io "FB_AD[31..0]" (bidir))
(mapper
(pt 272 176)
(bidir)
)
(mapper
(pt 272 208)
(bidir)
)
(mapper
(pt 272 240)
(bidir)
)
(mapper
(pt 272 264)
(bidir)
)
(mapper
(pt 272 288)
(bidir)
)
(mapper
(pt 0 384)
(bidir)
)
(mapper
(pt 272 72)
(bidir)
)
(mapper
(pt 0 56)
(bidir)
)
(mapper
(pt 0 32)
(bidir)
)
(mapper
(pt 0 296)
(bidir)
)
(mapper
(pt 0 272)
(bidir)
)
(mapper
(pt 0 104)
(bidir)
)
(mapper
(pt 0 128)
(bidir)
)
(mapper
(pt 0 80)
(bidir)
)
(mapper
(pt 0 248)
(bidir)
)
(mapper
(pt 0 224)
(bidir)
)
(mapper
(pt 0 200)
(bidir)
)
(mapper
(pt 0 176)
(bidir)
)
(mapper
(pt 0 152)
(bidir)
)
(mapper
(pt 0 360)
(bidir)
)
(mapper
(pt 0 328)
(bidir)
)
(mapper
(pt 272 424)
(bidir)
)
(mapper
(pt 0 408)
(bidir)
)
(mapper
(pt 0 440)
(bidir)
)
)
(connector
(text "CLUT_ADR0" (rect 2786 1272 2869 1287)(font "Arial" ))
(pt 2776 1288)
@@ -8363,34 +8368,12 @@ applicable agreement for further details.
(pt 560 2376)
(pt 664 2376)
)
(connector
(text "BLITTER_ON" (rect 226 2920 313 2935)(font "Arial" ))
(pt 296 2936)
(pt 216 2936)
)
(connector
(text "BLITTER_RUN" (rect 578 2712 675 2727)(font "Arial" ))
(pt 568 2728)
(pt 648 2728)
)
(connector
(text "VDVZ[127..0]" (rect 810 2920 892 2935)(font "Arial" ))
(pt 800 2936)
(pt 888 2936)
(bus)
)
(connector
(text "BLITTER_DOUT[127..0]" (rect 578 2744 731 2759)(font "Arial" ))
(pt 680 2760)
(pt 568 2760)
(bus)
)
(connector
(text "BLITTER_ADR[31..0]" (rect 578 2776 712 2791)(font "Arial" ))
(pt 568 2792)
(pt 680 2792)
(bus)
)
(connector
(text "BLITTER_SIG" (rect 578 2800 667 2815)(font "Arial" ))
(pt 568 2816)
@@ -8457,12 +8440,6 @@ applicable agreement for further details.
(pt 192 2584)
(pt 296 2584)
)
(connector
(text "VIDEO_RAM_CTR[15..0]" (rect 178 2896 334 2911)(font "Arial" ))
(pt 296 2912)
(pt 168 2912)
(bus)
)
(connector
(text "FB_AD[31..0]" (rect 578 2608 661 2623)(font "Arial" ))
(pt 688 2624)
@@ -8613,23 +8590,6 @@ applicable agreement for further details.
(pt 1192 1288)
(bus)
)
(connector
(text "BLITTER_DACK[0]" (rect 802 2952 922 2967)(font "Arial" ))
(pt 888 2968)
(pt 808 2968)
)
(connector
(text "BLITTER_DIN[127..0]" (rect 1042 2944 1180 2959)(font "Arial" ))
(pt 1144 2960)
(pt 1032 2960)
(bus)
)
(connector
(text "BLITTER_DIN[127..0]" (rect 194 2944 332 2959)(font "Arial" ))
(pt 296 2960)
(pt 184 2960)
(bus)
)
(connector
(text "SR_BLITTER_DACK" (rect 570 2464 703 2479)(font "Arial" ))
(pt 664 2480)
@@ -8671,12 +8631,6 @@ applicable agreement for further details.
(pt 1168 2192)
(bus)
)
(connector
(text "BLITTER_DACK[4..0]" (rect 202 2864 337 2879)(font "Arial" ))
(pt 192 2880)
(pt 296 2880)
(bus)
)
(connector
(text "CLK33M" (rect 218 2432 273 2447)(font "Arial" ))
(pt 208 2448)
@@ -8971,22 +8925,6 @@ applicable agreement for further details.
(pt 1032 2400)
(pt 1096 2400)
)
(connector
(text "SR_BLITTER_DACK" (rect 810 2560 943 2575)(font "Arial" ))
(pt 904 2576)
(pt 800 2576)
)
(connector
(text "DDRCLK0" (rect 826 2544 894 2559)(font "Arial" ))
(pt 816 2560)
(pt 904 2560)
)
(connector
(text "BLITTER_DACK[4..0]" (rect 1058 2560 1193 2575)(font "Arial" ))
(pt 1048 2576)
(pt 1152 2576)
(bus)
)
(connector
(text "DDRCLK2" (rect 1018 2672 1086 2687)(font "Arial" ))
(pt 1008 2688)
@@ -10625,6 +10563,78 @@ applicable agreement for further details.
(pt 1712 1472)
(pt 1632 1472)
)
(connector
(text "BLITTER_DACK[4..0]" (rect 178 2864 313 2879)(font "Arial" ))
(pt 296 2880)
(pt 184 2880)
(bus)
)
(connector
(text "VIDEO_RAM_CTR[15..0]" (rect 154 2896 310 2911)(font "Arial" ))
(pt 296 2912)
(pt 144 2912)
(bus)
)
(connector
(text "BLITTER_ON" (rect 202 2920 289 2935)(font "Arial" ))
(pt 296 2936)
(pt 192 2936)
)
(connector
(text "BLITTER_DIN[127..0]" (rect 162 2944 300 2959)(font "Arial" ))
(pt 296 2960)
(pt 152 2960)
(bus)
)
(connector
(text "SR_BLITTER_DACK" (rect 778 2560 911 2575)(font "Arial" ))
(pt 904 2576)
(pt 768 2576)
)
(connector
(text "DDRCLK0" (rect 794 2544 862 2559)(font "Arial" ))
(pt 904 2560)
(pt 784 2560)
)
(connector
(text "BLITTER_DACK[4..0]" (rect 1058 2560 1193 2575)(font "Arial" ))
(pt 1176 2576)
(pt 1048 2576)
(bus)
)
(connector
(text "BLITTER_DOUT[127..0]" (rect 578 2744 731 2759)(font "Arial" ))
(pt 712 2760)
(pt 568 2760)
(bus)
)
(connector
(text "BLITTER_ADR[31..0]" (rect 578 2776 712 2791)(font "Arial" ))
(pt 704 2792)
(pt 568 2792)
(bus)
)
(connector
(text "BLITTER_RUN" (rect 578 2712 675 2727)(font "Arial" ))
(pt 672 2728)
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(connector
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)
(connector
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(pt 1160 2960)
(pt 1032 2960)
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(junction (pt 792 1192))
(junction (pt 792 1312))

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