27 lines
1.1 KiB
Plaintext
27 lines
1.1 KiB
Plaintext
--Copyright (C) 1991-2010 Altera Corporation
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--Your use of Altera Corporation's design tools, logic functions
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--and other software and tools, and its AMPP partner logic
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--functions, and any output files from any of the foregoing
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--(including device programming or simulation files), and any
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--associated documentation or information are expressly subject
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--to the terms and conditions of the Altera Program License
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--Subscription Agreement, Altera MegaCore Function License
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--Agreement, or other applicable license agreement, including,
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--without limitation, that your use is for the sole purpose of
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--programming logic devices manufactured by Altera and sold by
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--Altera or its authorized distributors. Please refer to the
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--applicable agreement for further details.
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component altsyncram0
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PORT
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(
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address : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
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byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '1');
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clock : IN STD_LOGIC := '1';
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data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
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wren : IN STD_LOGIC := '0';
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q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
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);
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end component;
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