forked from Firebee/FPGA_Config
51 lines
1.8 KiB
VHDL
51 lines
1.8 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY flexbus_register IS
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GENERIC
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(
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reg_width : integer := 11;
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match_address : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
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match_mask : std_logic_vector(31 DOWNTO 0) := (OTHERS => '1');
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match_fbcs : integer := 0
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);
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PORT
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(
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clk : IN std_logic;
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fb_addr : IN std_logic_vector(31 DOWNTO 0);
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fb_data : INOUT std_logic_vector(31 DOWNTO 0);
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fb_cs : IN std_logic_vector(5 DOWNTO 1);
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fb_wr_n : IN std_logic;
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fb_ta_n : OUT std_logic;
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reg_value : INOUT std_logic_vector(reg_width - 1 DOWNTO 0);
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cs : OUT std_logic := '0'
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);
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END ENTITY flexbus_register;
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ARCHITECTURE rtl OF flexbus_register IS
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SIGNAL fbcs_match : std_logic;
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SIGNAL address_match : std_logic;
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BEGIN
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fbcs_match <= '1' WHEN fb_cs(match_fbcs) = '1' ELSE '0';
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address_match <= '1' WHEN (fb_addr and match_mask) = (match_address and match_mask) ELSE '0';
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p_register_access : PROCESS(ALL)
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BEGIN
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IF rising_edge(clk) THEN
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IF fbcs_match = '1' and address_match = '1' THEN
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cs <= '1';
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IF fb_wr_n = '0' THEN -- write access
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reg_value <= fb_data(reg_width - 1 DOWNTO 0);
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ELSE -- read access
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fb_data(reg_width - 1 DOWNTO 0) <= reg_value;
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fb_ta_n <= '0';
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END IF;
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ELSE
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fb_data <= (OTHERS => 'Z');
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fb_ta_n <= 'Z';
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cs <= '0';
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END IF;
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END IF;
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END PROCESS p_register_access;
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END ARCHITECTURE rtl; |