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Sync with Fredi's source 22/06/2017

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Blitter work.
This commit is contained in:
David Gálvez
2018-04-09 17:25:52 +02:00
parent 343ede8328
commit 3a91813da7
58 changed files with 2380 additions and 3603 deletions
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79
FPGA_by_Fredi/DSP/DSP.vhd.bak
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@@ -1,79 +0,0 @@
-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
-- Created on Tue Sep 08 16:24:57 2009
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY DSP IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
CLK33M : IN STD_LOGIC;
MAIN_CLK : IN STD_LOGIC;
nFB_OE : IN STD_LOGIC;
nFB_WR : IN STD_LOGIC;
nFB_CS1 : IN STD_LOGIC;
nFB_CS2 : IN STD_LOGIC;
FB_SIZE0 : IN STD_LOGIC;
FB_SIZE1 : IN STD_LOGIC;
nFB_BURST : IN STD_LOGIC;
FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
nRSTO : IN STD_LOGIC;
nFB_CS3 : IN STD_LOGIC;
nSRCS : OUT STD_LOGIC;
nSRBLE : OUT STD_LOGIC;
nSRBHE : OUT STD_LOGIC;
nSRWE : OUT STD_LOGIC;
nSROE : OUT STD_LOGIC;
DSP_INT : OUT STD_LOGIC;
DSP_TA : OUT STD_LOGIC;
FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
IO : INOUT STD_LOGIC_VECTOR(17 downto 0);
SRD : INOUT STD_LOGIC_VECTOR(15 downto 0)
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END DSP;
-- Architecture Body
ARCHITECTURE DSP_architecture OF DSP IS
BEGIN
nSRCS <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --nFB_CS3;
nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1';
nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0';
nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1';
nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1';
DSP_INT <= '0';
DSP_TA <= '0';
IO(17 downto 0) <= FB_ADR(18 downto 1);
SRD(15 downto 0) <= FB_AD(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
END DSP_architecture;

2
FPGA_by_Fredi/FPGA_DATE.bsf
View File

@@ -31,7 +31,7 @@ applicable agreement for further details.
(line (pt 88 24)(pt 72 24)(line_width 3))
)
(drawing
(text "402923543" (rect 27 18 72 30)(font "Arial" ))
(text "570826775" (rect 27 18 72 30)(font "Arial" ))
(text "32" (rect 77 25 87 37)(font "Arial" ))
(line (pt 16 16)(pt 72 16)(line_width 1))
(line (pt 72 16)(pt 72 32)(line_width 1))

10
FPGA_by_Fredi/FPGA_DATE.tdf
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@@ -33,7 +33,7 @@
--applicable agreement for further details.
-- Clearbox generated function header
FUNCTION FPGA_DATE_lpm_constant_i19 ()
FUNCTION FPGA_DATE_lpm_constant_f19 ()
RETURNS ( result[31..0]);
@@ -46,11 +46,11 @@ SUBDESIGN FPGA_DATE
VARIABLE
FPGA_DATE_lpm_constant_i19_component : FPGA_DATE_lpm_constant_i19;
FPGA_DATE_lpm_constant_f19_component : FPGA_DATE_lpm_constant_f19;
BEGIN
result[31..0] = FPGA_DATE_lpm_constant_i19_component.result[31..0];
result[31..0] = FPGA_DATE_lpm_constant_f19_component.result[31..0];
END;
@@ -63,9 +63,9 @@ END;
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: Radix NUMERIC "16"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "402923543"
-- Retrieval info: PRIVATE: Value NUMERIC "570826775"
-- Retrieval info: PRIVATE: nBit NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "402923543"
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "570826775"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"

6
FPGA_by_Fredi/FPGA_DATE_lpm_constant_d19.tdf → FPGA_by_Fredi/FPGA_DATE_lpm_constant_e19.tdf
View File

@@ -1,4 +1,4 @@
--lpm_constant CBX_AUTO_BLACKBOX="ALL" ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=13042017 LPM_WIDTH=32 result
--lpm_constant CBX_AUTO_BLACKBOX="ALL" ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=21062017 LPM_WIDTH=32 result
--VERSION_BEGIN 9.1SP2 cbx_lpm_constant 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ VERSION_END
@@ -19,12 +19,12 @@
--synthesis_resources =
SUBDESIGN FPGA_DATE_lpm_constant_d19
SUBDESIGN FPGA_DATE_lpm_constant_e19
(
result[31..0] : output;
)
BEGIN
result[] = B"00010011000001000010000000010111";
result[] = B"00100001000001100010000000010111";
END;
--VALID FILE

6
FPGA_by_Fredi/FPGA_DATE_lpm_constant_i19.tdf → FPGA_by_Fredi/FPGA_DATE_lpm_constant_f19.tdf
View File

@@ -1,4 +1,4 @@
--lpm_constant CBX_AUTO_BLACKBOX="ALL" ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=18042017 LPM_WIDTH=32 result
--lpm_constant CBX_AUTO_BLACKBOX="ALL" ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=22062017 LPM_WIDTH=32 result
--VERSION_BEGIN 9.1SP2 cbx_lpm_constant 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ VERSION_END
@@ -19,12 +19,12 @@
--synthesis_resources =
SUBDESIGN FPGA_DATE_lpm_constant_i19
SUBDESIGN FPGA_DATE_lpm_constant_f19
(
result[31..0] : output;
)
BEGIN
result[] = B"00011000000001000010000000010111";
result[] = B"00100010000001100010000000010111";
END;
--VALID FILE

30
FPGA_by_Fredi/FPGA_DATE_lpm_constant_g19.tdf Normal file
View File

@@ -0,0 +1,30 @@
--lpm_constant CBX_AUTO_BLACKBOX="ALL" ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=05062017 LPM_WIDTH=32 result
--VERSION_BEGIN 9.1SP2 cbx_lpm_constant 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ VERSION_END
-- Copyright (C) 1991-2010 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources =
SUBDESIGN FPGA_DATE_lpm_constant_g19
(
result[31..0] : output;
)
BEGIN
result[] = B"00000101000001100010000000010111";
END;
--VALID FILE

92
FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
View File

@@ -184,10 +184,14 @@ signal TDO : STD_LOGIC;
signal SNDCS : STD_LOGIC;
signal SNDCS_I : STD_LOGIC;
signal SNDIR_I : STD_LOGIC;
signal LP_DIR_X : STD_LOGIC;
signal DA_OUT_X : STD_LOGIC_VECTOR(7 downto 0);
signal LP_D_X : STD_LOGIC_VECTOR(7 downto 0);
signal nLP_STR : STD_LOGIC;
signal LP_STR_X : STD_LOGIC;
signal LP_STR_NS1 : STD_LOGIC;
signal LP_STR_NS0 : STD_LOGIC;
signal LP_DIR_X : STD_LOGIC;
signal LP_DIR_NS1 : STD_LOGIC;
signal LP_DIR_NS0 : STD_LOGIC;
-- DMA SOUND
signal dma_snd_cs : STD_LOGIC;
signal sndmactl : STD_LOGIC_VECTOR(7 downto 0);
@@ -298,8 +302,7 @@ FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0';
FALCON_IO_TA <= '1' when ACIA_CS_I = '1' or DTACK_OUT_MFPn = '0' or DMA_MODUS_CS ='1' or dma_snd_cs = '1' or paddle_cs = '1'
or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_TA = '1' else '0'; --SNDCS = '1' or
SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE
'1' when IDE_CF_CS = '1' ELSE
'1' when nFB_CS3 = '0' ELSE '0';
'1' when IDE_CF_CS = '1' ELSE '0'; -- DARF NICHT AKTIV SEIN BEI ZUGRIFF AUF DRIVE 0 UND 1 DA KOMMEN DIE DATEN DIREKT VOM FPGA
nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1';
nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1';
@@ -325,6 +328,22 @@ SD_CDM_D1 <= 'Z';
----------------------------------------------------------------------------
-- IDE
----------------------------------------------------------------------------
IDE_RES <= not ACP_CONF(25) and nRSTO; -- !!!!ACHTUNG: RESET wenn 0!!!!!!!!!!!!!!! -- IDE_RES manuel oder weil nRSTO
IDE_CF_CS <= '1' when (nFB_CS1 = '0' OR nFB_CS3 = '0') and FB_ADR(23 downto 7) = x"1E000" else '0'; -- FFF0'0000-FFF0'007F
IDE_DRIVE0 <= '1' when (nFB_CS1 = '0' OR nFB_CS3 = '0') and FB_ADR(23 downto 0) = x"F00099" else '0'; -- FFF0'0099 (19+80!)
IDE_DRIVE1 <= '1' when (nFB_CS1 = '0' OR nFB_CS3 = '0') and FB_ADR(23 downto 0) = x"F000D9" else '0'; -- FFF0'00D9 (19+40+80!)
IDE_DCS <= '1' when FB_ALE = '1' and FB_ADR(31 downto 2) = x"3FFC0000" else -- FFF0'000x 0-3
'1' when (nFB_CS1 = '0' OR nFB_CS3 = '0') and FB_ADR(23 downto 2) = x"3C0000" else -- FFF0'000x 0-3
'1' when FB_ALE = '1' and FB_ADR(31 downto 2) = x"3FFC0010" else -- FFF0'004x 0-3
'1' when (nFB_CS1 = '0' OR nFB_CS3 = '0') and FB_ADR(23 downto 2) = x"3C0010" else '0'; -- FFF0'004x 0-3
nCF_CS0 <= FB_ADR(5) or (FB_ADR(6) xor (ACP_CONF(31) xnor HD_DD)); -- xxxx'xx00-1F
nCF_CS1 <= not FB_ADR(5) or (FB_ADR(6) xor (ACP_CONF(31) xnor HD_DD)); -- xxxx'xx20-3F
nIDE_CS0 <= FB_ADR(5) or (FB_ADR(6) xnor (ACP_CONF(30) xnor HD_DD)); -- xxxx'xx40-5F
nIDE_CS1 <= not FB_ADR(5) or (FB_ADR(6) xnor (ACP_CONF(30) xnor HD_DD)); -- xxxx'xx60-7F
nDREQ0 <= '1';
FB_AD(23 downto 20) <= ACP_CONF(19 downto 16) when IDE_DRIVE0 = '1' and nFB_OE = '0' else "ZZZZ";
FB_AD(23 downto 20) <= ACP_CONF(23 downto 20) when IDE_DRIVE1 = '1' and nFB_OE = '0' else "ZZZZ";
CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE)
begin
if nRSTO = '0' then
@@ -336,7 +355,7 @@ CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE)
end if;
end process CMD_REG;
CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, nIDE_RD, nIDE_WR, IDE_RDY)
CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, nIDE_RD, nIDE_WR, IDE_RDY,IDE_DCS, IDE_CF_CS, FB_ADR, ACP_CONF, nFB_WR, FB_SIZE0, FB_SIZE1)
begin
case CMD_STATE is
when IDLE =>
@@ -453,23 +472,6 @@ CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE)
end if;
end case;
end process CMD_DECODER;
IDE_RES <= not ACP_CONF(25) and nRSTO; -- !!!!ACHTUNG: RESET wenn 0!!!!!!!!!!!!!!! -- IDE_RES manuel oder weil nRSTO
IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0'; -- FFF0'0000-FFF0'007F
IDE_DRIVE0 <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 0) = x"99" else '0'; -- FFF0'0099 (19+80!)
IDE_DRIVE1 <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 0) = x"D9" else '0'; -- FFF0'00D9 (19+40+80!)
IDE_DCS <= '1' when FB_ALE = '1' and FB_ADR(31 downto 2) = x"3FFC0000" else -- FFF0'000x 0-3
'1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"0" else -- FFF0'000x 0-3
'1' when FB_ALE = '1' and FB_ADR(31 downto 2) = x"3FFC0010" else -- FFF0'004x 0-3
'1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"10" else '0'; -- FFF0'004x 0-3
nCF_CS0 <= FB_ADR(5) or (FB_ADR(6) xor (ACP_CONF(31) xnor HD_DD)); -- xxxx'xx00-1F
nCF_CS1 <= not FB_ADR(5) or (FB_ADR(6) xor (ACP_CONF(31) xnor HD_DD)); -- xxxx'xx20-3F
nIDE_CS0 <= FB_ADR(5) or (FB_ADR(6) xnor (ACP_CONF(30) xnor HD_DD)); -- xxxx'xx40-5F
nIDE_CS1 <= not FB_ADR(5) or (FB_ADR(6) xnor (ACP_CONF(30) xnor HD_DD)); -- xxxx'xx60-7F
nDREQ0 <= '1';
FB_AD(23 downto 20) <= ACP_CONF(19 downto 16) when IDE_DRIVE0 = '1' and nFB_OE = '0' else "ZZZZ";
FB_AD(23 downto 20) <= ACP_CONF(23 downto 20) when IDE_DRIVE1 = '1' and nFB_OE = '0' else "ZZZZ";
-----------------------------------------------------------------------------------------------------------------------------------------
-- ACSI, SCSI UND FLOPPY WD1772
-------------------------------------------------------------------------------------------------------------------------------------------
@@ -915,7 +917,7 @@ KEYB_RxD <= '0' when AMKB_REG(3) = '0' or PIC_AMKB_RX = '0' else '1'; -- TAST
FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else
DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
-- AMKB_TX: SPIKES AUSFILTERN und sychronisieren ------------------------------------------
process(CLK2M, AMKB_RX, AMKB_REG)
process(CLK2M, AMKB_RX, AMKB_TX, AMKB_REG, CLK500k)
begin
if rising_edge(CLK500k) then
AMKB_TX <= AMKB_TX_sync;
@@ -995,7 +997,7 @@ MIDI_OLR <= MIDI_OUT;
GPIP_IN(3) => BLITTER_INT OR DSP_INT,
GPIP_IN(2) => not CTS,
GPIP_IN(1) => not DCD,
GPIP_IN(0) => LP_BUSY,
GPIP_IN(0) => LP_BUSY XOR ACP_CONF(1),
-- GPIP_OUT =>, -- Not used; all GPIPs are direction input.
-- GPIP_EN =>, -- Not used; all GPIPs are direction input.
-- Interrupt control:
@@ -1032,7 +1034,8 @@ FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ";
DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else
'0' when FDINT = '1' else
'0' when SCSI_INT = '1' AND ACP_CONF(27) = '1' else '1';
----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Sound
----------------------------------------------------------------------------
I_SOUND: WF2149IP_TOP_SOC
@@ -1054,8 +1057,8 @@ DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else
IO_A_IN => x"00", -- All port pins are dedicated outputs.
IO_A_OUT(7) => nnIDE_RES,
IO_A_OUT(6) => LP_DIR_X,
IO_A_OUT(5) => nLP_STR,
IO_A_OUT(6) => LP_DIR_NS0,
IO_A_OUT(5) => LP_STR_NS0,
IO_A_OUT(4) => DTR,
IO_A_OUT(3) => RTS,
-- IO_A_OUT(2) => FDD_D1SEL,
@@ -1075,17 +1078,38 @@ SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0'; --
SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0';
SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0';
FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ";
LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ";
LP_DIR <= LP_DIR_X;
LP_STR <= not nLP_STR;
LP_D <= LP_D_X when (LP_DIR_X = '0' OR ACP_CONF(2) = '0') else "ZZZZZZZZ";
LP_STR <= LP_STR_X XOR ACP_CONF(0);
LP_DIR <= LP_DIR_X XOR ACP_CONF(3);
-- spikes weg ------------------------------------------
process(CLK2M,LP_STR_NS1,LP_STR_NS0,LP_STR_X)
begin
if rising_edge(CLK2M) then
LP_STR_X <= (LP_STR_NS1 AND LP_STR_NS0) OR (LP_STR_X AND LP_STR_NS1);
LP_STR_NS1 <= LP_STR_NS0;
else
LP_STR_X <= LP_STR_X;
LP_STR_NS1 <= LP_STR_NS1;
end if;
END PROCESS;
process(CLK2M,LP_DIR_NS1,LP_DIR_NS0,LP_DIR_X)
begin
if rising_edge(CLK2M) then
LP_DIR_X <= (LP_DIR_NS1 AND LP_DIR_NS0) OR (LP_DIR_X AND LP_DIR_NS1);
LP_DIR_NS1 <= LP_DIR_NS0;
else
LP_DIR_X <= LP_DIR_X;
LP_DIR_NS1 <= LP_DIR_NS1;
end if;
END PROCESS;
----------------------------------------------------------------------------
-- DMA Sound register
----------------------------------------------------------------------------
dma_snd_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3E24" else '0'; -- F8900-F893F
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs, nFB_WR, FB_B1, sndmactl)
begin
if nRSTO = '0' THEN
sndmactl <= x"00";
@@ -1097,7 +1121,7 @@ dma_snd_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3E24" else '0';
END PROCESS;
FB_AD(23 downto 16) <= sndmactl when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_OE = '0' else "ZZZZZZZZ";
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs, sndbashi)
begin
if nRSTO = '0' THEN
sndbashi <= x"00";
@@ -1220,7 +1244,6 @@ FB_AD(23 downto 16) <= sndmode when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"
----------------------------------------------------------------------------
-- Paddle
----------------------------------------------------------------------------
paddle_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3E48" else '0'; -- F9200-F923F
FB_AD(31 downto 16) <= x"bfff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
@@ -1232,4 +1255,5 @@ FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"B
FB_AD(31 downto 16) <= x"0000" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"10" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
FB_AD(31 downto 16) <= x"0000" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"11" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
--****************************************************************
END FalconIO_SDCard_IDE_CF_architecture;

202
FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak
View File

@@ -1,202 +0,0 @@
-- megafunction wizard: %LPM_FIFO+%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo_mixed_widths
-- ============================================================
-- File Name: dcfifo1.vhd
-- Megafunction Name(s):
-- dcfifo_mixed_widths
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dcfifo1 IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END dcfifo1;
ARCHITECTURE SYN OF dcfifo1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT dcfifo_mixed_widths
GENERIC (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
lpm_widthu_r : NATURAL;
lpm_width_r : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
wrclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
aclr : IN STD_LOGIC ;
rdclk : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wrreq : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
wrusedw <= sub_wire0(3 DOWNTO 0);
q <= sub_wire1(7 DOWNTO 0);
dcfifo_mixed_widths_component : dcfifo_mixed_widths
GENERIC MAP (
intended_device_family => "Cyclone III",
lpm_numwords => 16,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => 16,
lpm_widthu => 4,
lpm_widthu_r => 5,
lpm_width_r => 8,
overflow_checking => "ON",
rdsync_delaypipe => 5,
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 5
)
PORT MAP (
wrclk => wrclk,
rdreq => rdreq,
aclr => aclr,
rdclk => rdclk,
wrreq => wrreq,
data => data,
wrusedw => sub_wire0,
q => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "16"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "16"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "8"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-- Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL wrusedw[3..0]
-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf

391
FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak
View File

@@ -1,391 +0,0 @@
TITLE "INTERRUPT HANDLER UND C1287";
-- CREATED BY FREDI ASCHWANDEN
INCLUDE "lpm_bustri_LONG.inc";
INCLUDE "lpm_bustri_BYT.inc";
-- Parameters Statement (optional)
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-- Subdesign Section
SUBDESIGN interrupt_handler
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
MAIN_CLK : INPUT;
nFB_WR : INPUT;
nFB_CS1 : INPUT;
nFB_CS2 : INPUT;
FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT;
FB_ADR[31..0] : INPUT;
FPGA_DATE[31..0] : INPUT;
PIC_INT : INPUT;
E0_INT : INPUT;
DVI_INT : INPUT;
nPCI_INTA : INPUT;
nPCI_INTB : INPUT;
nPCI_INTC : INPUT;
nPCI_INTD : INPUT;
nMFP_INT : INPUT;
nFB_OE : INPUT;
DSP_INT : INPUT;
VSYNC : INPUT;
HSYNC : INPUT;
DMA_DRQ : INPUT;
nRSTO : INPUT;
nIRQ[7..2] : OUTPUT;
INT_HANDLER_TA : OUTPUT;
ACP_CONF[31..0] : OUTPUT;
TIN0 : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
VARIABLE
FB_B[3..0] :NODE;
INT_CTR[31..0] :DFFE;
INT_CTR_CS :NODE;
INT_LATCH[31..0] :DFF;
INT_LATCH_CS :NODE;
INT_CLEAR[31..0] :DFF;
INT_CLEAR_CS :NODE;
INT_IN[31..0] :NODE;
INT_ENA[31..0] :DFFE;
INT_ENA_CS :NODE;
INT_L[9..0] :DFF;
INT_LA[9..0][3..0] :DFF;
ACP_CONF[31..0] :DFFE;
ACP_CONF_CS :NODE;
FPGA_DATE_CS :NODE;
PSEUDO_BUS_ERROR :NODE;
UHR_AS :NODE;
UHR_DS :NODE;
RTC_ADR[5..0] :DFFE;
ACHTELSEKUNDEN[2..0] :DFFE;
WERTE[7..0][63..0] :DFFE; -- WERTE REGISTER 0-63
PIC_INT_SYNC[2..0] :DFF;
INC_SEC :NODE;
INC_MIN :NODE;
INC_STD :NODE;
INC_TAG :NODE;
ANZAHL_TAGE_DES_MONATS[7..0]:NODE;
WINTERZEIT :NODE;
SOMMERZEIT :NODE;
INC_MONAT :NODE;
INC_JAHR :NODE;
UPDATE_ON :NODE;
BEGIN
-- BYT SELECT
FB_B0 = FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HWORD
# !FB_SIZE1 & FB_SIZE0 & !FB_ADR1 & !FB_ADR0 -- HHBYT
# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE
FB_B1 = FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HWORD
# !FB_SIZE1 & FB_SIZE0 & !FB_ADR1 & FB_ADR0 -- HLBYT
# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LWORD
# !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & !FB_ADR0 -- LHBYT
# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LWORD
# !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & FB_ADR0 -- LLBYT
# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE
-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSL<53>SEN, 1=INT7 AUSL<53>SEN
INT_CTR[].CLK = MAIN_CLK;
INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000"; -- $10000/4
INT_CTR[] = FB_AD[];
INT_CTR[31..24].ENA = INT_CTR_CS & FB_B0 & !nFB_WR;
INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR;
INT_CTR[15..8].ENA = INT_CTR_CS & FB_B2 & !nFB_WR;
INT_CTR[7..0].ENA = INT_CTR_CS & FB_B3 & !nFB_WR;
-- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
INT_ENA[].CLK = MAIN_CLK;
INT_ENA[].CLRN = nRSTO;
INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001"; -- $10004/4
INT_ENA[] = FB_AD[];
INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR;
INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR;
INT_ENA[15..8].ENA = INT_ENA_CS & FB_B2 & !nFB_WR;
INT_ENA[7..0].ENA = INT_ENA_CS & FB_B3 & !nFB_WR;
-- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR
INT_CLEAR[].CLK = MAIN_CLK;
INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002"; -- $10008/4
INT_CLEAR[31..24] = FB_AD[31..24] & INT_CLEAR_CS & FB_B0 & !nFB_WR;
INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR;
INT_CLEAR[15..8] = FB_AD[15..8] & INT_CLEAR_CS & FB_B2 & !nFB_WR;
INT_CLEAR[7..0] = FB_AD[7..0] & INT_CLEAR_CS & FB_B3 & !nFB_WR;
-- INTERRUPT LATCH REGISTER READ ONLY
INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003"; -- $1000C/4
-- INTERRUPT
!nIRQ2 = HSYNC & INT_ENA[26];
!nIRQ3 = INT_CTR0 & INT_ENA[27];
!nIRQ4 = VSYNC & INT_ENA[28];
!nIRQ5 = INT_LATCH[]!=H"00000000" & INT_ENA[29];
!nIRQ6 = !nMFP_INT & INT_ENA[30];
!nIRQ7 = PSEUDO_BUS_ERROR & INT_ENA[31];
PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC
# FB_ADR[19..4]==H"F8E0" -- VME
-- # FB_ADR[19..4]==H"F920" -- PADDLE
-- # FB_ADR[19..4]==H"F921" -- PADDLE
-- # FB_ADR[19..4]==H"F922" -- PADDLE
# FB_ADR[19..4]==H"FFA8" -- MFP2
# FB_ADR[19..4]==H"FFA9" -- MFP2
# FB_ADR[19..4]==H"FFAA" -- MFP2
# FB_ADR[19..4]==H"FFA8" -- MFP2
# FB_ADR[19..8]==H"F87" -- TT SCSI
# FB_ADR[19..4]==H"FFC2" -- ST UHR
# FB_ADR[19..4]==H"FFC3" -- ST UHR
-- # FB_ADR[19..4]==H"F890" -- DMA SOUND
-- # FB_ADR[19..4]==H"F891" -- DMA SOUND
-- # FB_ADR[19..4]==H"F892" -- DMA SOUND
);
-- IF VIDEO ADR CHANGE
TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2
-- INTERRUPT LATCH
INT_L[].CLK = MAIN_CLK;
INT_L[].CLRN = nRSTO;
INT_L0 = PIC_INT & INT_ENA[0];
INT_L1 = E0_INT & INT_ENA[1];
INT_L2 = DVI_INT & INT_ENA[2];
INT_L3 = !nPCI_INTA & INT_ENA[3];
INT_L4 = !nPCI_INTB & INT_ENA[4];
INT_L5 = !nPCI_INTC & INT_ENA[5];
INT_L6 = !nPCI_INTD & INT_ENA[6];
INT_L7 = DSP_INT & INT_ENA[7];
INT_L8 = VSYNC & INT_ENA[8];
INT_L9 = HSYNC & INT_ENA[9];
INT_LA[][].CLK = MAIN_CLK;
INT_LATCH[] = H"FFFFFFFF";
INT_LATCH[].CLRN = !INT_CLEAR[] & nRSTO;
FOR I IN 0 TO 9 GENERATE
INT_LA[I][].CLRN = INT_ENA[I] & nRSTO;
INT_LA[I][] = INT_LA[I][]+1 & INT_L[I] & INT_LA[I][]<7
# INT_LA[I][]-1 & !INT_L[I] & INT_LA[I][]>8
# 15 & INT_L[I] & INT_LA[I][]>6
# 0 & !INT_L[I] & INT_LA[I][]<9;
INT_LATCH[I].CLK = INT_LA[I][3];
END GENERATE;
-- INT_IN
INT_IN0 = PIC_INT;
INT_IN1 = E0_INT;
INT_IN2 = DVI_INT;
INT_IN3 = !nPCI_INTA;
INT_IN4 = !nPCI_INTB;
INT_IN5 = !nPCI_INTC;
INT_IN6 = !nPCI_INTD;
INT_IN7 = DSP_INT;
INT_IN8 = VSYNC;
INT_IN9 = HSYNC;
INT_IN[25..10] = H"0";
INT_IN26 = HSYNC;
INT_IN27 = INT_CTR0;
INT_IN28 = VSYNC;
INT_IN29 = INT_LATCH[]!=H"00000000";
INT_IN30 = !nMFP_INT;
INT_IN31 = DMA_DRQ;
--***************************************************************************************
-- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE
ACP_CONF[].CLK = MAIN_CLK;
ACP_CONF_CS = !nFB_CS2 & FB_ADR[27..2]==H"10000"; -- $4'0000/4
ACP_CONF[] = FB_AD[];
ACP_CONF[31..24].ENA = ACP_CONF_CS & FB_B0 & !nFB_WR;
ACP_CONF[23..16].ENA = ACP_CONF_CS & FB_B1 & !nFB_WR;
ACP_CONF[15..8].ENA = ACP_CONF_CS & FB_B2 & !nFB_WR;
ACP_CONF[7..0].ENA = ACP_CONF_CS & FB_B3 & !nFB_WR;
--***************************************************************************************
-- FPGA DATE HEX (ddmmyyyy)
FPGA_DATE_CS = !nFB_CS2 & FB_ADR[27..2]==H"10040"; -- $4'0000/4
--***************************************************************************************
--------------------------------------------------------------
-- C1287 0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR
----------------------------------------------------------
RTC_ADR[].CLK = MAIN_CLK;
RTC_ADR[] = FB_AD[21..16];
UHR_AS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B0" & FB_B1; -- FFFF8961
UHR_DS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B1" & FB_B3; -- FFFF8963
RTC_ADR[].ENA = UHR_AS & !nFB_WR;
WERTE[][].CLK = MAIN_CLK;
WERTE[7..0][0] = FB_AD[23..16] & RTC_ADR[]==0 & UHR_DS & !nFB_WR;
WERTE[7..0][1] = FB_AD[23..16];
WERTE[7..0][2] = FB_AD[23..16] & RTC_ADR[]==2 & UHR_DS & !nFB_WR;
WERTE[7..0][3] = FB_AD[23..16];
WERTE[7..0][4] = FB_AD[23..16] & RTC_ADR[]==4 & UHR_DS & !nFB_WR;
WERTE[7..0][5] = FB_AD[23..16];
WERTE[7..0][6] = FB_AD[23..16] & RTC_ADR[]==6 & UHR_DS & !nFB_WR;
WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR;
WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR;
WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR;
FOR I IN 10 TO 63 GENERATE
WERTE[7..0][I] = FB_AD[23..16];
END GENERATE;
FOR I IN 0 TO 63 GENERATE
WERTE[][I].ENA = RTC_ADR[]==I & UHR_DS & !nFB_WR;
END GENERATE;
PIC_INT_SYNC[].CLK = MAIN_CLK;
PIC_INT_SYNC[0] = PIC_INT;
PIC_INT_SYNC[1] = PIC_INT_SYNC[0];
PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0];
UPDATE_ON = !WERTE[7][11];
WERTE[6][10].CLRN = GND; -- KEIN UIP
UPDATE_ON = !WERTE[7][11]; -- UPDATE ON OFF
WERTE[2][11] = VCC; -- IMMER BINARY
WERTE[1][11] = VCC; -- IMMER 24H FORMAT
WERTE[0][11] = VCC; -- IMMER SOMMERZEITKORREKTUR
WERTE[7][13] = VCC; -- IMMER RICHTIG
-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN F<>R R<>CKSCHALTUNG)
SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4 & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL
WERTE[0][13] = SOMMERZEIT;
WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT);
WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13]; --LETZTER SONNTAG IM OKTOBER
-- ACHTELSEKUNDEN
ACHTELSEKUNDEN[].CLK = MAIN_CLK;
ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1;
ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON;
-- SEKUNDEN
INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON;
WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN Z<>HLEN BIS 59
WERTE[][0].ENA = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);
-- MINUTEN
INC_MIN = INC_SEC & WERTE[][0]==59; --
WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN Z<>HLEN BIS 59
WERTE[][2].ENA = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); --
-- STUNDEN
INC_STD = INC_MIN & WERTE[][2]==59;
WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN Z<>HLEN BIS 23
WERTE[][4].ENA = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT
-- WOCHENTAG UND TAG
INC_TAG = INC_STD & WERTE[][2]==23;
WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG Z<>HLEN BIS 7
# 1 & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER
WERTE[][6].ENA = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);
ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12)
# 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11)
# 29 & WERTE[][8]==2 & WERTE[1..0][9]==0
# 28 & WERTE[][8]==2 & WERTE[1..0][9]!=0;
WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG Z<>HLEN BIS MONATSENDE
# 1 & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER
WERTE[][7].ENA = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); --
-- MONATE
INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[]; --
WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE Z<>HLEN BIS 12
# 1 & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER
WERTE[][8].ENA = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);
-- JAHR
INC_JAHR = INC_MONAT & WERTE[][8]==12; --
WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE Z<>HLEN BIS 99
WERTE[][9].ENA = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);
-- TRISTATE OUTPUT
FB_AD[31..24] = lpm_bustri_BYT(
INT_CTR_CS & INT_CTR[31..24]
# INT_ENA_CS & INT_ENA[31..24]
# INT_LATCH_CS & INT_LATCH[31..24]
# INT_CLEAR_CS & INT_IN[31..24]
# ACP_CONF_CS & ACP_CONF[31..24]
# FPGA_DATE_CS & FPGA_DATE[31..24]
,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
FB_AD[23..16] = lpm_bustri_BYT(
WERTE[][0] & RTC_ADR[]==0 & UHR_DS
# WERTE[][1] & RTC_ADR[]==1 & UHR_DS
# WERTE[][2] & RTC_ADR[]==2 & UHR_DS
# WERTE[][3] & RTC_ADR[]==3 & UHR_DS
# WERTE[][4] & RTC_ADR[]==4 & UHR_DS
# WERTE[][5] & RTC_ADR[]==5 & UHR_DS
# WERTE[][6] & RTC_ADR[]==6 & UHR_DS
# WERTE[][7] & RTC_ADR[]==7 & UHR_DS
# WERTE[][8] & RTC_ADR[]==8 & UHR_DS
# WERTE[][9] & RTC_ADR[]==9 & UHR_DS
# WERTE[][10] & RTC_ADR[]==10 & UHR_DS
# WERTE[][11] & RTC_ADR[]==11 & UHR_DS
# WERTE[][12] & RTC_ADR[]==12 & UHR_DS
# WERTE[][13] & RTC_ADR[]==13 & UHR_DS
# WERTE[][14] & RTC_ADR[]==14 & UHR_DS
# WERTE[][15] & RTC_ADR[]==15 & UHR_DS
# WERTE[][16] & RTC_ADR[]==16 & UHR_DS
# WERTE[][17] & RTC_ADR[]==17 & UHR_DS
# WERTE[][18] & RTC_ADR[]==18 & UHR_DS
# WERTE[][19] & RTC_ADR[]==19 & UHR_DS
# WERTE[][20] & RTC_ADR[]==20 & UHR_DS
# WERTE[][21] & RTC_ADR[]==21 & UHR_DS
# WERTE[][22] & RTC_ADR[]==22 & UHR_DS
# WERTE[][23] & RTC_ADR[]==23 & UHR_DS
# WERTE[][24] & RTC_ADR[]==24 & UHR_DS
# WERTE[][25] & RTC_ADR[]==25 & UHR_DS
# WERTE[][26] & RTC_ADR[]==26 & UHR_DS
# WERTE[][27] & RTC_ADR[]==27 & UHR_DS
# WERTE[][28] & RTC_ADR[]==28 & UHR_DS
# WERTE[][29] & RTC_ADR[]==29 & UHR_DS
# WERTE[][30] & RTC_ADR[]==30 & UHR_DS
# WERTE[][31] & RTC_ADR[]==31 & UHR_DS
# WERTE[][32] & RTC_ADR[]==32 & UHR_DS
# WERTE[][33] & RTC_ADR[]==33 & UHR_DS
# WERTE[][34] & RTC_ADR[]==34 & UHR_DS
# WERTE[][35] & RTC_ADR[]==35 & UHR_DS
# WERTE[][36] & RTC_ADR[]==36 & UHR_DS
# WERTE[][37] & RTC_ADR[]==37 & UHR_DS
# WERTE[][38] & RTC_ADR[]==38 & UHR_DS
# WERTE[][39] & RTC_ADR[]==39 & UHR_DS
# WERTE[][40] & RTC_ADR[]==40 & UHR_DS
# WERTE[][41] & RTC_ADR[]==41 & UHR_DS
# WERTE[][42] & RTC_ADR[]==42 & UHR_DS
# WERTE[][43] & RTC_ADR[]==43 & UHR_DS
# WERTE[][44] & RTC_ADR[]==44 & UHR_DS
# WERTE[][45] & RTC_ADR[]==45 & UHR_DS
# WERTE[][46] & RTC_ADR[]==46 & UHR_DS
# WERTE[][47] & RTC_ADR[]==47 & UHR_DS
# WERTE[][48] & RTC_ADR[]==48 & UHR_DS
# WERTE[][49] & RTC_ADR[]==49 & UHR_DS
# WERTE[][50] & RTC_ADR[]==50 & UHR_DS
# WERTE[][51] & RTC_ADR[]==51 & UHR_DS
# WERTE[][52] & RTC_ADR[]==52 & UHR_DS
# WERTE[][53] & RTC_ADR[]==53 & UHR_DS
# WERTE[][54] & RTC_ADR[]==54 & UHR_DS
# WERTE[][55] & RTC_ADR[]==55 & UHR_DS
# WERTE[][56] & RTC_ADR[]==56 & UHR_DS
# WERTE[][57] & RTC_ADR[]==57 & UHR_DS
# WERTE[][58] & RTC_ADR[]==58 & UHR_DS
# WERTE[][59] & RTC_ADR[]==59 & UHR_DS
# WERTE[][60] & RTC_ADR[]==60 & UHR_DS
# WERTE[][61] & RTC_ADR[]==61 & UHR_DS
# WERTE[][62] & RTC_ADR[]==62 & UHR_DS
# WERTE[][63] & RTC_ADR[]==63 & UHR_DS
# (0,RTC_ADR[]) & UHR_AS
# INT_CTR_CS & INT_CTR[23..16]
# INT_ENA_CS & INT_ENA[23..16]
# INT_LATCH_CS & INT_LATCH[23..16]
# INT_CLEAR_CS & INT_IN[23..16]
# ACP_CONF_CS & ACP_CONF[23..16]
# FPGA_DATE_CS & FPGA_DATE[23..16]
,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
FB_AD[15..8] = lpm_bustri_BYT(
INT_CTR_CS & INT_CTR[15..8]
# INT_ENA_CS & INT_ENA[15..8]
# INT_LATCH_CS & INT_LATCH[15..8]
# INT_CLEAR_CS & INT_IN[15..8]
# ACP_CONF_CS & ACP_CONF[15..8]
# FPGA_DATE_CS & FPGA_DATE[15..8]
,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
FB_AD[7..0] = lpm_bustri_BYT(
INT_CTR_CS & INT_CTR[7..0]
# INT_ENA_CS & INT_ENA[7..0]
# INT_LATCH_CS & INT_LATCH[7..0]
# INT_CLEAR_CS & INT_IN[7..0]
# ACP_CONF_CS & ACP_CONF[7..0]
# FPGA_DATE_CS & FPGA_DATE[7..0]
,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
INT_HANDLER_TA = INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS;
END;

20
FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt
View File

@@ -1,20 +0,0 @@
PLL_Name altpll1:inst|altpll:altpll_component|altpll_3vp2:auto_generated|pll1
PLLJITTER 36
PLLSPEmax 84
PLLSPEmin -53
PLL_Name altpll2:inst12|altpll:altpll_component|altpll_1r33:auto_generated|pll1
PLLJITTER 43
PLLSPEmax 84
PLLSPEmin -53
PLL_Name altpll3:inst13|altpll:altpll_component|altpll_aus2:auto_generated|pll1
PLLJITTER NA
PLLSPEmax 84
PLLSPEmin -53
PLL_Name altpll4:inst22|altpll:altpll_component|altpll_r4n2:auto_generated|pll1
PLLJITTER 31
PLLSPEmax 84
PLLSPEmin -53

27
FPGA_by_Fredi/UNUSED
View File

@@ -1,27 +0,0 @@
-- Clearbox generated Memory Initialization File (.mif)
WIDTH=3;
DEPTH=16;
ADDRESS_RADIX=HEX;
DATA_RADIX=HEX;
CONTENT BEGIN
00 : 7;
01 : 6;
02 : 5;
03 : 4;
04 : 3;
05 : 2;
06 : 1;
07 : 0;
08 : 7;
09 : 6;
0a : 5;
0b : 4;
0c : 3;
0d : 2;
0e : 1;
0f : 0;
END;

20
FPGA_by_Fredi/Video/lpm_fifoDZ.cmp → FPGA_by_Fredi/Video/BLITTER/lpm_ror128.inc
View File

@@ -13,14 +13,12 @@
--applicable agreement for further details.
component lpm_fifoDZ
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
);
end component;
FUNCTION lpm_ror128
(
data[127..0],
distance[6..0]
)
RETURNS (
result[127..0]
);

5
FPGA_by_Fredi/Video/BLITTER/lpm_ror128.qip Normal file
View File

@@ -0,0 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "LPM_CLSHIFT"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ror128.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ror128.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ror128.cmp"]

92
FPGA_by_Fredi/Video/BLITTER/lpm_ror128.tdf Normal file
View File

@@ -0,0 +1,92 @@
-- megafunction wizard: %LPM_CLSHIFT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_clshift
-- ============================================================
-- File Name: lpm_ror128.tdf
-- Megafunction Name(s):
-- lpm_clshift
--
-- Simulation Library Files(s):
--
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
INCLUDE "lpm_clshift.inc";
SUBDESIGN lpm_ror128
(
data[127..0] : INPUT;
distance[6..0] : INPUT;
result[127..0] : OUTPUT;
)
VARIABLE
lpm_clshift_component : lpm_clshift WITH (
LPM_SHIFTTYPE = "ROTATE",
LPM_TYPE = "LPM_CLSHIFT",
LPM_WIDTH = 128,
LPM_WIDTHDIST = 7
);
BEGIN
result[127..0] = lpm_clshift_component.result[127..0];
lpm_clshift_component.distance[6..0] = distance[6..0];
lpm_clshift_component.direction = VCC;
lpm_clshift_component.data[127..0] = data[127..0];
END;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_SHIFTTYPE NUMERIC "2"
-- Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "128"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: lpm_width_varies NUMERIC "0"
-- Retrieval info: PRIVATE: lpm_widthdist NUMERIC "7"
-- Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "1"
-- Retrieval info: PRIVATE: port_direction NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_SHIFTTYPE STRING "ROTATE"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CLSHIFT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
-- Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "7"
-- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0]
-- Retrieval info: USED_PORT: distance 0 0 7 0 INPUT NODEFVAL distance[6..0]
-- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL result[127..0]
-- Retrieval info: CONNECT: @distance 0 0 7 0 distance 0 0 7 0
-- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
-- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
-- Retrieval info: CONNECT: @direction 0 0 0 0 VCC 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ror128.tdf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ror128.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ror128.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ror128.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ror128_inst.tdf FALSE

659
FPGA_by_Fredi/Video/DDR_CTR.tdf.bak
View File

@@ -1,659 +0,0 @@
TITLE "DDR_CTR";
-- CREATED BY FREDI ASCHWANDEN
INCLUDE "lpm_bustri_BYT.inc";
-- FIFO WATER MARK
CONSTANT FIFO_LWM = 0;
CONSTANT FIFO_MWM = 1000;
CONSTANT FIFO_HWM = 2000;
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
SUBDESIGN DDR_CTR
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
FB_ADR[31..0] : INPUT;
nFB_CS1 : INPUT;
nFB_CS2 : INPUT;
nFB_CS3 : INPUT;
nFB_OE : INPUT;
FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT;
nRSTO : INPUT;
MAIN_CLK : INPUT;
FB_ALE : INPUT;
nFB_WR : INPUT;
DDR_SYNC_66M : INPUT;
CLR_FIFO : INPUT;
VIDEO_RAM_CTR[15..0] : INPUT;
BLITTER_ADR[31..0] : INPUT;
BLITTER_SIG : INPUT;
BLITTER_WR : INPUT;
DDRCLK0 : INPUT;
CLK33M : INPUT;
FIFO_MW[10..0] : INPUT;
VA[12..0] : OUTPUT;
nVWE : OUTPUT;
nVRAS : OUTPUT;
nVCS : OUTPUT;
VCKE : OUTPUT;
nVCAS : OUTPUT;
FB_LE[3..0] : OUTPUT;
FB_VDOE[3..0] : OUTPUT;
SR_FIFO_WRE : OUTPUT;
SR_DDR_FB : OUTPUT;
SR_DDR_WR : OUTPUT;
SR_DDRWR_D_SEL : OUTPUT;
SR_VDMP[7..0] : OUTPUT;
VIDEO_DDR_TA : OUTPUT;
SR_BLITTER_DACK : OUTPUT;
BA[1..0] : OUTPUT;
DDRWR_D_SEL1 : OUTPUT;
VDM_SEL[3..0] : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
VARIABLE
FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);
DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8, -- START (NORMAL 8 CYCLES TOTAL = 60ns)
DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, -- CONFIG
DS_T4R,DS_T5R, -- READ CPU UND BLITTER,
DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W, -- WRITE CPU UND BLITTER
DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, -- READ FIFO
DS_CB6, DS_CB8, -- CLOSE FIFO BANK
DS_R2,DS_R3,DS_R4, DS_R5, DS_R6); -- REFRESH 10X7.5NS=75NS
LINE :NODE;
FB_B[3..0] :NODE;
VCAS :NODE;
VRAS :NODE;
VWE :NODE;
VA_P[12..0] :DFF;
BA_P[1..0] :DFF;
VA_S[12..0] :DFF;
BA_S[1..0] :DFF;
MCS[1..0] :DFF;
CPU_DDR_SYNC :DFF;
DDR_SEL :NODE;
DDR_CS :DFFE;
DDR_CONFIG :NODE;
SR_DDR_WR :DFF;
SR_DDRWR_D_SEL :DFF;
SR_VDMP[7..0] :DFF;
CPU_ROW_ADR[12..0] :NODE;
CPU_BA[1..0] :NODE;
CPU_COL_ADR[9..0] :NODE;
CPU_SIG :NODE;
CPU_REQ :DFF;
CPU_AC :DFF;
BUS_CYC :DFF;
BUS_CYC_END :NODE;
BLITTER_REQ :DFF;
BLITTER_AC :DFF;
BLITTER_ROW_ADR[12..0] :NODE;
BLITTER_BA[1..0] :NODE;
BLITTER_COL_ADR[9..0] :NODE;
FIFO_REQ :DFF;
FIFO_AC :DFF;
FIFO_ROW_ADR[12..0] :NODE;
FIFO_BA[1..0] :NODE;
FIFO_COL_ADR[9..0] :NODE;
FIFO_ACTIVE :NODE;
CLR_FIFO_SYNC :DFF;
CLEAR_FIFO_CNT :DFF;
STOP :DFF;
SR_FIFO_WRE :DFF;
FIFO_BANK_OK :DFF;
FIFO_BANK_NOT_OK :NODE;
DDR_REFRESH_ON :NODE;
DDR_REFRESH_CNT[10..0] :DFF;
DDR_REFRESH_REQ :DFF;
DDR_REFRESH_SIG[3..0] :DFFE;
REFRESH_TIME :DFF;
VIDEO_BASE_L_D[7..0] :DFFE;
VIDEO_BASE_L :NODE;
VIDEO_BASE_M_D[7..0] :DFFE;
VIDEO_BASE_M :NODE;
VIDEO_BASE_H_D[7..0] :DFFE;
VIDEO_BASE_H :NODE;
VIDEO_BASE_X_D[2..0] :DFFE;
VIDEO_ADR_CNT[22..0] :DFFE;
VIDEO_CNT_L :NODE;
VIDEO_CNT_M :NODE;
VIDEO_CNT_H :NODE;
VIDEO_BASE_ADR[22..0] :NODE;
VIDEO_ACT_ADR[26..0] :NODE;
BEGIN
LINE = FB_SIZE0 & FB_SIZE1;
-- BYT SELECT
FB_B0 = FB_ADR[1..0]==0 -- ADR==0
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) --------------------------------------------------
FB_REGDDR.CLK = MAIN_CLK;
CASE FB_REGDDR IS
WHEN FR_WAIT =>
FB_LE0 = !nFB_WR;
IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE
FB_REGDDR = FR_S0;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S0 =>
IF DDR_CS THEN
FB_LE0 = !nFB_WR;
VIDEO_DDR_TA = VCC;
IF LINE THEN
FB_VDOE0 = !nFB_OE & !DDR_CONFIG;
FB_REGDDR = FR_S1;
ELSE
BUS_CYC_END = VCC;
FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
FB_REGDDR = FR_WAIT;
END IF;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S1 =>
IF DDR_CS THEN
FB_VDOE1 = !nFB_OE & !DDR_CONFIG;
FB_LE1 = !nFB_WR;
VIDEO_DDR_TA = VCC;
FB_REGDDR = FR_S2;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S2 =>
IF DDR_CS THEN
FB_VDOE2 = !nFB_OE & !DDR_CONFIG;
FB_LE2 = !nFB_WR;
IF !BUS_CYC & LINE & !nFB_WR THEN -- BEI LINE WRITE EVT. WARTEN
FB_REGDDR = FR_S2;
ELSE
VIDEO_DDR_TA = VCC;
FB_REGDDR = FR_S3;
END IF;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S3 =>
IF DDR_CS THEN
FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
FB_LE3 = !nFB_WR;
VIDEO_DDR_TA = VCC;
BUS_CYC_END = VCC;
FB_REGDDR = FR_WAIT;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
END CASE;
-- DDR STEUERUNG -----------------------------------------------------
-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE;
VCKE = VIDEO_RAM_CTR0;
nVCS = !VIDEO_RAM_CTR1;
DDR_REFRESH_ON = VIDEO_RAM_CTR2;
DDR_CONFIG = VIDEO_RAM_CTR3;
FIFO_ACTIVE = VIDEO_RAM_CTR8;
--------------------------------
CPU_ROW_ADR[] = FB_ADR[26..14];
CPU_BA[] = FB_ADR[13..12];
CPU_COL_ADR[] = FB_ADR[11..2];
nVRAS = !VRAS;
nVCAS = !VCAS;
nVWE = !VWE;
SR_DDR_WR.CLK = DDRCLK0;
SR_DDRWR_D_SEL.CLK = DDRCLK0;
SR_VDMP[7..0].CLK = DDRCLK0;
SR_FIFO_WRE.CLK = DDRCLK0;
CPU_AC.CLK = DDRCLK0;
FIFO_AC.CLK = DDRCLK0;
BLITTER_AC.CLK = DDRCLK0;
DDRWR_D_SEL1 = BLITTER_AC;
-- SELECT LOGIC
DDR_SEL = FB_ALE & FB_AD[31..30]==B"01";
DDR_CS.CLK = MAIN_CLK;
DDR_CS.ENA = FB_ALE;
DDR_CS = DDR_SEL;
-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP<53>TER
CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
# DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS
# FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SP<53>TER
CPU_REQ.CLK = DDR_SYNC_66M;
CPU_REQ = CPU_SIG
# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG
BUS_CYC.CLK = DDRCLK0;
BUS_CYC = BUS_CYC & !BUS_CYC_END;
-- STATE MACHINE SYNCHRONISIEREN -----------------
MCS[].CLK = DDRCLK0;
MCS0 = MAIN_CLK;
MCS1 = MCS0;
CPU_DDR_SYNC.CLK = DDRCLK0;
CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS; -- NUR 1 WENN EIN
---------------------------------------------------
VA_S[].CLK = DDRCLK0;
BA_S[].CLK = DDRCLK0;
VA[] = VA_S[];
BA[] = BA_S[];
VA_P[].CLK = DDRCLK0;
BA_P[].CLK = DDRCLK0;
-- DDR STATE MACHINE -----------------------------------------------
DDR_SM.CLK = DDRCLK0;
CASE DDR_SM IS
WHEN DS_T1 =>
IF DDR_REFRESH_REQ THEN
DDR_SM = DS_R2;
ELSE
IF CPU_DDR_SYNC THEN -- SYNCHRON UND EIN?
IF DDR_CONFIG THEN -- JA
DDR_SM = DS_C2;
ELSE
IF CPU_REQ THEN -- BEI WAIT UND LINE WRITE
VA_S[] = CPU_ROW_ADR[];
BA_S[] = CPU_BA[];
CPU_AC = VCC;
BUS_CYC = VCC;
DDR_SM = DS_T2B;
ELSE
IF FIFO_REQ # !BLITTER_REQ THEN -- FIFO IST DEFAULT
VA_P[] = FIFO_ROW_ADR[];
BA_P[] = FIFO_BA[];
FIFO_AC = VCC; -- VORBESETZEN
ELSE
VA_P[] = BLITTER_ROW_ADR[];
BA_P[] = BLITTER_BA[];
BLITTER_AC = VCC; -- VORBESETZEN
END IF;
DDR_SM = DS_T2A;
END IF;
END IF;
ELSE
DDR_SM = DS_T1; -- NEIN ->SYNCHRONISIEREN
END IF;
END IF;
WHEN DS_T2A => -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK ***
IF DDR_SEL & (nFB_WR # !LINE) THEN
VRAS = VCC;
VA[] = FB_AD[26..14];
BA[] = FB_AD[13..12];
VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO PAGE
CPU_AC = VCC;
BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN
ELSE
VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ;
VA[] = VA_P[];
BA[] = BA_P[];
VA_S[10] = !(FIFO_AC & FIFO_REQ);
FIFO_BANK_OK = FIFO_AC & FIFO_REQ;
FIFO_AC = FIFO_AC & FIFO_REQ;
BLITTER_AC = BLITTER_AC & BLITTER_REQ;
END IF;
DDR_SM = DS_T3;
WHEN DS_T2B =>
VRAS = VCC;
FIFO_BANK_NOT_OK = VCC;
CPU_AC = VCC;
BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN
DDR_SM = DS_T3;
WHEN DS_T3 =>
CPU_AC = CPU_AC;
FIFO_AC = FIFO_AC;
BLITTER_AC = BLITTER_AC;
VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN
DDR_SM = DS_T4W;
ELSE
IF CPU_AC THEN -- CPU?
VA_S[9..0] = CPU_COL_ADR[];
BA_S[] = CPU_BA[];
DDR_SM = DS_T4R;
ELSE
IF FIFO_AC THEN -- FIFO?
VA_S[9..0] = FIFO_COL_ADR[];
BA_S[] = FIFO_BA[];
DDR_SM = DS_T4F;
ELSE
IF BLITTER_AC THEN
VA_S[9..0] = BLITTER_COL_ADR[];
BA_S[] = BLITTER_BA[];
DDR_SM = DS_T4R;
ELSE
DDR_SM = DS_N8;
END IF;
END IF;
END IF;
END IF;
-- READ
WHEN DS_T4R =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
VCAS = VCC;
SR_DDR_FB = CPU_AC; -- READ DATEN F<>R CPU
SR_BLITTER_DACK = BLITTER_AC; -- BLITTER DACK AND BLITTER LATCH DATEN
DDR_SM = DS_T5R;
WHEN DS_T5R =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
IF FIFO_REQ & FIFO_BANK_OK THEN -- FIFO READ EINSCHIEBEN WENN BANK OK
VA_S[9..0] = FIFO_COL_ADR[];
VA_S[10] = GND; -- MANUEL PRECHARGE
BA_S[] = FIFO_BA[];
DDR_SM = DS_T6F;
ELSE
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB6;
END IF;
-- WRITE
WHEN DS_T4W =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
SR_BLITTER_DACK = BLITTER_AC; -- BLITTER ACK AND BLITTER LATCH DATEN
VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
DDR_SM = DS_T5W;
WHEN DS_T5W =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
VA_S[9..0] = CPU_AC & CPU_COL_ADR[]
# BLITTER_AC & BLITTER_COL_ADR[];
VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
BA_S[] = CPU_AC & CPU_BA[]
# BLITTER_AC & BLITTER_BA[];
SR_VDMP[7..4] = FB_B[] # BLITTER_AC & B"1111"; -- BYTE ENABLE WRITE, BEI BLITTER IMMER LINE
SR_VDMP[3..0] = (LINE # BLITTER_AC) & B"1111"; -- LINE ENABLE WRITE, BEI BLITTER IMMER LINE
DDR_SM = DS_T6W;
WHEN DS_T6W =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
VCAS = VCC;
VWE = VCC;
SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
SR_VDMP[] = (LINE # BLITTER_AC) & B"11111111"; -- WENN LINE DANN ACTIV
DDR_SM = DS_T7W;
WHEN DS_T7W =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITE
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
DDR_SM = DS_T8W;
WHEN DS_T8W =>
DDR_SM = DS_T9W;
WHEN DS_T9W =>
IF FIFO_REQ & FIFO_BANK_OK THEN
VA_S[9..0] = FIFO_COL_ADR[];
VA_S[10] = GND; -- NON AUTO PRECHARGE
BA_S[] = FIFO_BA[];
DDR_SM = DS_T6F;
ELSE
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB6;
END IF;
-- FIFO READ
WHEN DS_T4F =>
VCAS = VCC;
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
DDR_SM = DS_T5F;
WHEN DS_T5F =>
IF FIFO_REQ THEN
IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE?
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB6; -- BANK SCHLIESSEN
ELSE
VA_S[9..0] = FIFO_COL_ADR[]+4;
VA_S[10] = GND; -- NON AUTO PRECHARGE
BA_S[] = FIFO_BA[];
DDR_SM = DS_T6F;
END IF;
ELSE
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB6; -- NOCH OFFEN LASSEN
END IF;
WHEN DS_T6F =>
VCAS = VCC;
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
DDR_SM = DS_T7F;
WHEN DS_T7F =>
IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN
VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN
DDR_SM = DS_CB8; -- BANK SCHLIESSEN
ELSE
IF FIFO_REQ THEN
IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE?
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB8; -- BANK SCHLIESSEN
ELSE
VA_S[9..0] = FIFO_COL_ADR[]+4;
VA_S[10] = GND; -- NON AUTO PRECHARGE
BA_S[] = FIFO_BA[];
DDR_SM = DS_T8F;
END IF;
ELSE
VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN
DDR_SM = DS_CB8; -- BANK SCHLIESSEN
END IF;
END IF;
WHEN DS_T8F =>
VCAS = VCC;
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
IF FIFO_MW[]<FIFO_LWM THEN -- NOTFALL?
DDR_SM = DS_T5F; -- JA->
ELSE
DDR_SM = DS_T9F;
END IF;
WHEN DS_T9F =>
IF FIFO_REQ THEN
IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE?
VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN
DDR_SM = DS_CB6; -- BANK SCHLIESSEN
ELSE
VA_P[9..0] = FIFO_COL_ADR[]+4;
VA_P[10] = GND; -- NON AUTO PRECHARGE
BA_P[] = FIFO_BA[];
DDR_SM = DS_T10F;
END IF;
ELSE
VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN
DDR_SM = DS_CB6; -- BANK SCHLIESSEN
END IF;
WHEN DS_T10F =>
IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN
VRAS = VCC;
VA[] = FB_AD[26..14];
BA[] = FB_AD[13..12];
CPU_AC = VCC;
BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN
VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO BANK
DDR_SM = DS_T3;
ELSE
VCAS = VCC;
VA[] = VA_P[];
BA[] = BA_P[];
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
DDR_SM = DS_T7F;
END IF;
-- CONFIG CYCLUS
WHEN DS_C2 =>
DDR_SM = DS_C3;
WHEN DS_C3 =>
BUS_CYC = CPU_REQ;
DDR_SM = DS_C4;
WHEN DS_C4 =>
IF CPU_REQ THEN
DDR_SM = DS_C5;
ELSE
DDR_SM = DS_T1;
END IF;
WHEN DS_C5 =>
DDR_SM = DS_C6;
WHEN DS_C6 =>
VA_S[] = FB_AD[12..0];
BA_S[] = FB_AD[14..13];
DDR_SM = DS_C7;
WHEN DS_C7 =>
VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE
VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE
VWE = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE
DDR_SM = DS_N8;
-- CLOSE FIFO BANK
WHEN DS_CB6 =>
FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK
VRAS = VCC; -- B<>NKE SCHLIESSEN
VWE = VCC;
DDR_SM = DS_N7;
WHEN DS_CB8 =>
FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK
VRAS = VCC; -- B<>NKE SCHLIESSEN
VWE = VCC;
DDR_SM = DS_T1;
-- REFRESH 70NS = 10 ZYCLEN
WHEN DS_R2 =>
IF DDR_REFRESH_SIG[]==9 THEN -- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN
VRAS = VCC; -- ALLE BANKS SCHLIESSEN
VWE = VCC;
VA[10] = VCC;
FIFO_BANK_NOT_OK = VCC;
DDR_SM = DS_R4;
ELSE
VCAS = VCC;
VRAS = VCC;
DDR_SM = DS_R3;
END IF;
WHEN DS_R3 =>
DDR_SM = DS_R4;
WHEN DS_R4 =>
DDR_SM = DS_R5;
WHEN DS_R5 =>
DDR_SM = DS_R6;
WHEN DS_R6 =>
DDR_SM = DS_N5;
-- LEERSCHLAUFE
WHEN DS_N5 =>
DDR_SM = DS_N6;
WHEN DS_N6 =>
DDR_SM = DS_N7;
WHEN DS_N7 =>
DDR_SM = DS_N8;
WHEN DS_N8 =>
DDR_SM = DS_T1;
END CASE;
---------------------------------------------------------------
-- BLITTER ----------------------
-----------------------------------------
BLITTER_REQ.CLK = DDRCLK0;
BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS;
BLITTER_ROW_ADR[] = BLITTER_ADR[26..14];
BLITTER_BA1 = BLITTER_ADR13;
BLITTER_BA0 = BLITTER_ADR12;
BLITTER_COL_ADR[] = BLITTER_ADR[11..2];
------------------------------------------------------------------------------
-- FIFO ---------------------------------
--------------------------------------------------------
FIFO_REQ.CLK = DDRCLK0;
FIFO_REQ = (FIFO_MW[]<FIFO_MWM
# FIFO_MW[]<FIFO_HWM & FIFO_REQ) & FIFO_ACTIVE & !CLEAR_FIFO_CNT & !STOP & !DDR_CONFIG & VCKE & !nVCS;
FIFO_ROW_ADR[] = VIDEO_ADR_CNT[22..10];
FIFO_BA1 = VIDEO_ADR_CNT9;
FIFO_BA0 = VIDEO_ADR_CNT8;
FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00");
FIFO_BANK_OK.CLK = DDRCLK0;
FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK;
-- Z<>HLER R<>CKSETZEN WENN CLR FIFO ----------------
CLR_FIFO_SYNC.CLK =DDRCLK0;
CLR_FIFO_SYNC = CLR_FIFO; -- SYNCHRONISIEREN
CLEAR_FIFO_CNT.CLK = DDRCLK0;
CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE;
STOP.CLK = DDRCLK0;
STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT;
-- Z<>HLEN -----------------------------------------------
VIDEO_ADR_CNT[].CLK = DDRCLK0;
VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT;
VIDEO_ADR_CNT[] = CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]
# !CLEAR_FIFO_CNT & VIDEO_ADR_CNT[]+1;
VIDEO_BASE_ADR[22..20] = VIDEO_BASE_X_D[];
VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[];
VIDEO_BASE_ADR[11..4] = VIDEO_BASE_M_D[];
VIDEO_BASE_ADR[3..0] = VIDEO_BASE_L_D[7..4];
VDM_SEL[] = VIDEO_BASE_L_D[3..0];
-- AKTUELLE VIDEO ADRESSE
VIDEO_ACT_ADR[26..4] = VIDEO_ADR_CNT[] - (0,FIFO_MW[]);
VIDEO_ACT_ADR[3..0] = VDM_SEL[];
-----------------------------------------------------------------------------------------
-- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
-----------------------------------------------------------------------------------------
DDR_REFRESH_CNT[].CLK = CLK33M;
DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- Z<>HLEN 0-2047
REFRESH_TIME.CLK = DDRCLK0;
REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK; -- SYNC
DDR_REFRESH_SIG[].CLK = DDRCLK0;
DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6;
DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 ST<53>CK (8 REFRESH UND 1 ALS VORLAUF)
# !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; -- MINUS 1 WENN GEMACHT
DDR_REFRESH_REQ.CLK = DDRCLK0;
DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG;
-----------------------------------------------------------
-- VIDEO REGISTER -----------------------
---------------------------------------------------------------------------------------------------------------------
VIDEO_BASE_L_D[].CLK = MAIN_CLK;
VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; -- 820D/2
VIDEO_BASE_L_D[] = FB_AD[23..16]; -- SORRY, NUR 16 BYT GRENZEN
VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1;
VIDEO_BASE_M_D[].CLK = MAIN_CLK;
VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; -- 8203/2
VIDEO_BASE_M_D[] = FB_AD[23..16];
VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3;
VIDEO_BASE_H_D[].CLK = MAIN_CLK;
VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100"; -- 8200-1/2
VIDEO_BASE_H_D[] = FB_AD[23..16];
VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1;
VIDEO_BASE_X_D[].CLK = MAIN_CLK;
VIDEO_BASE_X_D[] = FB_AD[26..24];
VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0;
VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; -- 8209/2
VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2
VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2
FB_AD[31..24] = lpm_bustri_BYT(
VIDEO_BASE_H & (0,VIDEO_BASE_X_D[])
# VIDEO_CNT_H & (0,VIDEO_ACT_ADR[26..24])
,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
FB_AD[23..16] = lpm_bustri_BYT(
VIDEO_BASE_L & VIDEO_BASE_L_D[]
# VIDEO_BASE_M & VIDEO_BASE_M_D[]
# VIDEO_BASE_H & VIDEO_BASE_H_D[]
# VIDEO_CNT_L & VIDEO_ACT_ADR[7..0]
# VIDEO_CNT_M & VIDEO_ACT_ADR[15..8]
# VIDEO_CNT_H & VIDEO_ACT_ADR[23..16]
,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE);
END;

3
FPGA_by_Fredi/Video/lpm_fifoDZ.bsf → FPGA_by_Fredi/Video/Doppelzeilen_Fifo.bsf
View File

@@ -21,7 +21,7 @@ applicable agreement for further details.
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 160 144)
(text "lpm_fifoDZ" (rect 50 1 120 17)(font "Arial" (font_size 10)))
(text "Doppelzeilen_Fifo" (rect 29 1 149 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 128 25 140)(font "Arial" ))
(port
(pt 0 32)
@@ -66,7 +66,6 @@ applicable agreement for further details.
(line (pt 160 32)(pt 144 32)(line_width 3))
)
(drawing
(text "(ack)" (rect 51 67 72 79)(font "Arial" ))
(text "128 bits x 512 words" (rect 58 116 144 128)(font "Arial" ))
(line (pt 16 16)(pt 144 16)(line_width 1))
(line (pt 144 16)(pt 144 128)(line_width 1))

27
FPGA_by_Fredi/Video/Doppelzeilen_Fifo.inc Normal file
View File

@@ -0,0 +1,27 @@
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION Doppelzeilen_Fifo
(
aclr,
clock,
data[127..0],
rdreq,
wrreq
)
RETURNS (
q[127..0]
);

5
FPGA_by_Fredi/Video/Doppelzeilen_Fifo.qip Normal file
View File

@@ -0,0 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "FIFO"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Doppelzeilen_Fifo.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Doppelzeilen_Fifo.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Doppelzeilen_Fifo.inc"]

44
FPGA_by_Fredi/Video/lpm_fifoDZ.vhd → FPGA_by_Fredi/Video/Doppelzeilen_Fifo.vhd
View File

@@ -1,10 +1,10 @@
-- megafunction wizard: %LPM_FIFO+%
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
-- ============================================================
-- File Name: lpm_fifoDZ.vhd
-- File Name: Doppelzeilen_Fifo.vhd
-- Megafunction Name(s):
-- scfifo
--
@@ -39,7 +39,7 @@ USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY lpm_fifoDZ IS
ENTITY Doppelzeilen_Fifo IS
PORT
(
aclr : IN STD_LOGIC ;
@@ -49,10 +49,10 @@ ENTITY lpm_fifoDZ IS
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
);
END lpm_fifoDZ;
END Doppelzeilen_Fifo;
ARCHITECTURE SYN OF lpm_fifodz IS
ARCHITECTURE SYN OF doppelzeilen_fifo IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (127 DOWNTO 0);
@@ -86,10 +86,10 @@ BEGIN
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "OFF",
add_ram_output_register => "ON",
intended_device_family => "Cyclone III",
lpm_numwords => 512,
lpm_showahead => "ON",
lpm_showahead => "OFF",
lpm_type => "scfifo",
lpm_width => 128,
lpm_widthu => 9,
@@ -117,38 +117,38 @@ END SYN;
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "512"
-- Retrieval info: PRIVATE: Empty NUMERIC "0"
-- Retrieval info: PRIVATE: Full NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
-- Retrieval info: PRIVATE: UsedW NUMERIC "0"
-- Retrieval info: PRIVATE: Width NUMERIC "128"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "128"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
@@ -168,11 +168,11 @@ END SYN;
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ_wave*.jpg FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Doppelzeilen_Fifo.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Doppelzeilen_Fifo.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Doppelzeilen_Fifo.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Doppelzeilen_Fifo.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Doppelzeilen_Fifo_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Doppelzeilen_Fifo_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Doppelzeilen_Fifo_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf

267
FPGA_by_Fredi/Video/UNUSED
View File

@@ -1,267 +0,0 @@
-- Clearbox generated Memory Initialization File (.mif)
WIDTH=6;
DEPTH=256;
ADDRESS_RADIX=HEX;
DATA_RADIX=HEX;
CONTENT BEGIN
000 : 0F;
001 : 0E;
002 : 0D;
003 : 0C;
004 : 0B;
005 : 0A;
006 : 09;
007 : 08;
008 : 07;
009 : 06;
00a : 05;
00b : 04;
00c : 03;
00d : 02;
00e : 01;
00f : 00;
010 : 0F;
011 : 0E;
012 : 0D;
013 : 0C;
014 : 0B;
015 : 0A;
016 : 09;
017 : 08;
018 : 07;
019 : 06;
01a : 05;
01b : 04;
01c : 03;
01d : 02;
01e : 01;
01f : 00;
020 : 0F;
021 : 0E;
022 : 0D;
023 : 0C;
024 : 0B;
025 : 0A;
026 : 09;
027 : 08;
028 : 07;
029 : 06;
02a : 05;
02b : 04;
02c : 03;
02d : 02;
02e : 01;
02f : 00;
030 : 0F;
031 : 0E;
032 : 0D;
033 : 0C;
034 : 0B;
035 : 0A;
036 : 09;
037 : 08;
038 : 07;
039 : 06;
03a : 05;
03b : 04;
03c : 03;
03d : 02;
03e : 01;
03f : 00;
040 : 0F;
041 : 0E;
042 : 0D;
043 : 0C;
044 : 0B;
045 : 0A;
046 : 09;
047 : 08;
048 : 07;
049 : 06;
04a : 05;
04b : 04;
04c : 03;
04d : 02;
04e : 01;
04f : 00;
050 : 0F;
051 : 0E;
052 : 0D;
053 : 0C;
054 : 0B;
055 : 0A;
056 : 09;
057 : 08;
058 : 07;
059 : 06;
05a : 05;
05b : 04;
05c : 03;
05d : 02;
05e : 01;
05f : 00;
060 : 0F;
061 : 0E;
062 : 0D;
063 : 0C;
064 : 0B;
065 : 0A;
066 : 09;
067 : 08;
068 : 07;
069 : 06;
06a : 05;
06b : 04;
06c : 03;
06d : 02;
06e : 01;
06f : 00;
070 : 0F;
071 : 0E;
072 : 0D;
073 : 0C;
074 : 0B;
075 : 0A;
076 : 09;
077 : 08;
078 : 07;
079 : 06;
07a : 05;
07b : 04;
07c : 03;
07d : 02;
07e : 01;
07f : 00;
080 : 0F;
081 : 0E;
082 : 0D;
083 : 0C;
084 : 0B;
085 : 0A;
086 : 09;
087 : 08;
088 : 07;
089 : 06;
08a : 05;
08b : 04;
08c : 03;
08d : 02;
08e : 01;
08f : 00;
090 : 0F;
091 : 0E;
092 : 0D;
093 : 0C;
094 : 0B;
095 : 0A;
096 : 09;
097 : 08;
098 : 07;
099 : 06;
09a : 05;
09b : 04;
09c : 03;
09d : 02;
09e : 01;
09f : 00;
0a0 : 0F;
0a1 : 0E;
0a2 : 0D;
0a3 : 0C;
0a4 : 0B;
0a5 : 0A;
0a6 : 09;
0a7 : 08;
0a8 : 07;
0a9 : 06;
0aa : 05;
0ab : 04;
0ac : 03;
0ad : 02;
0ae : 01;
0af : 00;
0b0 : 0F;
0b1 : 0E;
0b2 : 0D;
0b3 : 0C;
0b4 : 0B;
0b5 : 0A;
0b6 : 09;
0b7 : 08;
0b8 : 07;
0b9 : 06;
0ba : 05;
0bb : 04;
0bc : 03;
0bd : 02;
0be : 01;
0bf : 00;
0c0 : 0F;
0c1 : 0E;
0c2 : 0D;
0c3 : 0C;
0c4 : 0B;
0c5 : 0A;
0c6 : 09;
0c7 : 08;
0c8 : 07;
0c9 : 06;
0ca : 05;
0cb : 04;
0cc : 03;
0cd : 02;
0ce : 01;
0cf : 00;
0d0 : 0F;
0d1 : 0E;
0d2 : 0D;
0d3 : 0C;
0d4 : 0B;
0d5 : 0A;
0d6 : 09;
0d7 : 08;
0d8 : 07;
0d9 : 06;
0da : 05;
0db : 04;
0dc : 03;
0dd : 02;
0de : 01;
0df : 00;
0e0 : 0F;
0e1 : 0E;
0e2 : 0D;
0e3 : 0C;
0e4 : 0B;
0e5 : 0A;
0e6 : 09;
0e7 : 08;
0e8 : 07;
0e9 : 06;
0ea : 05;
0eb : 04;
0ec : 03;
0ed : 02;
0ee : 01;
0ef : 00;
0f0 : 0F;
0f1 : 0E;
0f2 : 0D;
0f3 : 0C;
0f4 : 0B;
0f5 : 0A;
0f6 : 09;
0f7 : 08;
0f8 : 07;
0f9 : 06;
0fa : 05;
0fb : 04;
0fc : 03;
0fd : 02;
0fe : 01;
0ff : 00;
END;

480
FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
View File

@@ -59,6 +59,7 @@ SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
VR_WR : OUTPUT;
VR_RD : OUTPUT;
CLR_FIFO : OUTPUT;
DPZF_CLKENA: OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
@@ -80,7 +81,7 @@ VARIABLE
ST_CLUT :NODE;
FB_B[3..0] :NODE;
FB_16B[1..0] :NODE;
ST_SHIFT_MODE[1..0] :DFFE;
ST_SHIFT_MODE[2..0] :DFFE;
ST_SHIFT_MODE_CS :NODE;
FALCON_SHIFT_MODE[10..0] :DFFE;
FALCON_SHIFT_MODE_CS :NODE;
@@ -105,20 +106,19 @@ VARIABLE
HSYNC_START :DFF;
LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT
VSYNC :DFF;
VSYNC_START :DFFE;
VSYNC_I[2..0] :DFFE;
VSYNC_I[2..0] :DFF;
nBLANK :DFF;
DISP_ON :DFF;
DPO_ZL :DFFE;
DPO_ZL :DFF;
DPO_ON :DFF;
DPO_OFF :DFF;
VDTRON :DFF;
VDO_ZL :DFFE;
VDO_ZL :DFF;
VDO_ON :DFF;
VDO_OFF :DFF;
VHCNT[11..0] :DFF;
VHCNT[12..0] :DFF;
SUB_PIXEL_CNT[6..0] :DFFE;
VVCNT[10..0] :DFFE;
VVCNT[12..0] :DFFE;
VERZ[2..0][9..0] :DFF;
RAND[6..0] :DFF;
RAND_ON :NODE;
@@ -130,67 +130,63 @@ VARIABLE
SYNC_PIX2 :DFF;
CCSEL[2..0] :DFF;
COLOR16 :NODE;
COLOR24 :NODE;
-- ATARI RESOLUTION
ATARI_SYNC :NODE;
ATARI_HH[31..0] :DFFE; -- HORIZONTAL TIMING 640x480
ATARI_HH_CS :NODE;
ATARI_VH[31..0] :DFFE; -- VERTIKAL TIMING 640x480
ATARI_VH_CS :NODE;
ATARI_HL[31..0] :DFFE; -- HORIZONTAL TIMING 320x240
ATARI_HL_CS :NODE;
ATARI_VL[31..0] :DFFE; -- VERTIKAL TIMING 320x240
ATARI_VL_CS :NODE;
COLOR24 :NODE; -- IST ABER 32BIT BREIT
TE :NODE;
-- HORIZONTAL
RAND_LINKS[11..0] :NODE;
HDIS_START[11..0] :NODE;
HDIS_END[11..0] :NODE;
RAND_RECHTS[11..0] :NODE;
HS_START[11..0] :NODE;
H_TOTAL[11..0] :NODE;
HDIS_LEN[11..0] :NODE;
MULF[5..0] :NODE;
VDL_HHT[11..0] :DFFE;
RAND_LINKS[12..0] :NODE;
HDIS_START[12..0] :NODE;
STARTP[12..0] :NODE;
HDIS_END[12..0] :NODE;
RAND_RECHTS[12..0] :NODE;
MULF[12..0] :NODE;
HS_START[12..0] :NODE;
H_TOTAL[12..0] :NODE;
HDIS_LEN[12..0] :NODE;
WPL[15..0] :NODE;
VDL_HHT[12..0] :DFFE;
VDL_HHT_CS :NODE;
VDL_HBE[11..0] :DFFE;
VDL_HBE[12..0] :DFFE;
VDL_HBE_CS :NODE;
VDL_HDB[11..0] :DFFE;
VDL_HDB[12..0] :DFFE;
VDL_HDB_CS :NODE;
VDL_HDE[11..0] :DFFE;
VDL_HDE[12..0] :DFFE;
VDL_HDE_CS :NODE;
VDL_HBB[11..0] :DFFE;
VDL_HBB[12..0] :DFFE;
VDL_HBB_CS :NODE;
VDL_HSS[11..0] :DFFE;
VDL_HSS[12..0] :DFFE;
VDL_HSS_CS :NODE;
-- VERTIKAL
RAND_OBEN[10..0] :NODE;
VDIS_START[10..0] :NODE;
VDIS_END[10..0] :NODE;
RAND_UNTEN[10..0] :NODE;
VS_START[10..0] :NODE;
V_TOTAL[10..0] :NODE;
RAND_OBEN[12..0] :NODE;
VDIS_START[12..0] :NODE;
VDIS_END[12..0] :NODE;
RAND_UNTEN[12..0] :NODE;
VS_START[12..0] :NODE;
V_TOTAL[12..0] :NODE;
FALCON_VIDEO :NODE;
ST_VIDEO :NODE;
INTER_ZEI :DFF;
DOP_ZEI :DFF;
DOP_FIFO_CLR :DFF;
VDL_VBE[10..0] :DFFE;
VIDEL_CS :NODE;
VDL_VBE[12..0] :DFFE;
VDL_VBE_CS :NODE;
VDL_VDB[10..0] :DFFE;
VDL_VDB[12..0] :DFFE;
VDL_VDB_CS :NODE;
VDL_VDE[10..0] :DFFE;
VDL_VDE[12..0] :DFFE;
VDL_VDE_CS :NODE;
VDL_VBB[10..0] :DFFE;
VDL_VBB[12..0] :DFFE;
VDL_VBB_CS :NODE;
VDL_VSS[10..0] :DFFE;
VDL_VSS[12..0] :DFFE;
VDL_VSS_CS :NODE;
VDL_VFT[10..0] :DFFE;
VDL_VFT[12..0] :DFFE;
VDL_VFT_CS :NODE;
VDL_VCT[8..0] :DFFE;
VDL_VCT[12..0] :DFFE;
VDL_VCT_CS :NODE;
VDL_VMD[3..0] :DFFE;
VDL_VMD_CS :NODE;
VDL_BPP_CS :NODE;
VDL_PH_CS :NODE;
VDL_PV_CS :NODE;
BEGIN
-- BYT SELECT 32 BIT
@@ -207,6 +203,8 @@ BEGIN
FB_16B0 = FB_ADR[0]==0; -- ADR==0
FB_16B1 = FB_ADR[0]==1 -- ADR==1
# !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT
-- VIDEL CS
VIDEL_CS = !nFB_CS1 & FB_ADR[19..8]==H"F82"; -- FFF'F8200-FFF'F82FF
-- ACP CLUT --
ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0"; -- 0-3FF/1024
ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
@@ -226,11 +224,11 @@ BEGIN
-- ST SHIFT MODE
ST_SHIFT_MODE[].CLK = MAIN_CLK;
ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130"; -- $F8260/2
ST_SHIFT_MODE[] = FB_AD[25..24];
ST_SHIFT_MODE[] = FB_AD[26..24];
ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO
COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN
COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN
COLOR1 = ST_SHIFT_MODE[]==B"010" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO
COLOR2 = ST_SHIFT_MODE[]==B"001" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN
COLOR4 = ST_SHIFT_MODE[]==B"000" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN
-- FALCON SHIFT MODE
FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133"; -- $F8266/2
@@ -238,13 +236,13 @@ BEGIN
FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
FALCON_SHIFT_MODE[7..0].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
COLOR1 = FALCON_SHIFT_MODE[] == H"400" & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR4 = FALCON_SHIFT_MODE[] == H"000" & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR8 = FALCON_SHIFT_MODE[] == H"010" & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR16 = FALCON_SHIFT_MODE[] == H"100" & FALCON_VIDEO & !ACP_VIDEO_ON;
-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN
ACP_VCTR[].CLK = MAIN_CLK;
ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100"; -- $400/4
ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100"; -- $F000'0400
ACP_VCTR[31..8] = FB_AD[31..8];
ACP_VCTR[5..0] = FB_AD[5..0];
ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
@@ -253,42 +251,8 @@ BEGIN
ACP_VCTR[5..0].ENA = ACP_VCTR_CS & FB_B3 & !nFB_WR;
ACP_VIDEO_ON = ACP_VCTR0;
nPD_VGA = ACP_VCTR1;
-- ATARI MODUS
ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFL<46>SUNG
-- HORIZONTAL TIMING 640x480
ATARI_HH[].CLK = MAIN_CLK;
ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4
ATARI_HH[] = FB_AD[];
ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR;
ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR;
ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR;
-- VERTIKAL TIMING 640x480
ATARI_VH[].CLK = MAIN_CLK;
ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105"; -- $414/4
ATARI_VH[] = FB_AD[];
ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR;
ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR;
ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR;
-- HORIZONTAL TIMING 320x240
ATARI_HL[].CLK = MAIN_CLK;
ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106"; -- $418/4
ATARI_HL[] = FB_AD[];
ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR;
ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR;
ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR;
-- VERTIKAL TIMING 320x240
ATARI_VL[].CLK = MAIN_CLK;
ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107"; -- $41C/4
ATARI_VL[] = FB_AD[];
ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR;
ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR;
ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR;
-- VIDEO PLL CONFIG
VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $F000'0600-7FF ->6/2 WORD RESP LONG ONLY
VR_WR.CLK = MAIN_CLK;
VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & !VR_BUSY;
@@ -299,7 +263,7 @@ BEGIN
VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
VR_FRQ[] = FB_AD[23..16];
-- VIDEO PLL RECONFIG
VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800
VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $F000'0800
VIDEO_RECONFIG.CLK = MAIN_CLK;
VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
------------------------------------------------------------------------------------------------------------------------
@@ -313,11 +277,11 @@ BEGIN
-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
ACP_VCTR[7..6].ENA = (FALCON_SHIFT_MODE_CS # ST_SHIFT_MODE_CS) & !nFB_WR;
FALCON_VIDEO = ACP_VCTR7;
ST_VIDEO = ACP_VCTR6 & !ACP_VCTR7;
FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
ST_VIDEO = ACP_VCTR6;
ST_CLUT = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1;
ST_CLUT = ST_VIDEO & !ACP_VIDEO_ON & !COLOR1;
CCSEL[].CLK = PIXEL_CLK;
CCSEL[] = B"000" & ST_CLUT -- ONLY FOR INFORMATION
# B"001" & FALCON_CLUT
@@ -328,108 +292,112 @@ BEGIN
-- DIVERSE (VIDEO)-REGISTER ----------------------------
-- RANDFARBE
CCR[].CLK = MAIN_CLK;
CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4
CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $F004'0404/4
CCR[] = FB_AD[23..0];
CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR;
CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR;
--SYS CTR
SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2
SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $FFFF'8006
SYS_CTR[].CLK = MAIN_CLK;
SYS_CTR[6..0] = FB_AD[22..16];
SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3;
BLITTER_ON = SYS_CTR3;
--VDL_LOF
VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2
VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $F820E/2
VDL_LOF[].CLK = MAIN_CLK;
VDL_LOF[] = FB_AD[31..16];
VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3;
--VDL_LWD
VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2
VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $F8210/2
VDL_LWD[].CLK = MAIN_CLK;
VDL_LWD[] = FB_AD[31..16];
VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1;
-- DATEN AUFL<46>SUNG
VDL_BPP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C109"; -- $F8212: BITS PER PIXEL
VDL_PH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C10A"; -- $F8214: BREITE IN PIXE
VDL_PV_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C10B"; -- $F8216: BREITE IN PIXE
-- HORIZONTAL
-- VDL_HHT
VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2
VDL_HHT[].CLK = MAIN_CLK;
VDL_HHT[] = FB_AD[27..16];
VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
VDL_HHT[] = FB_AD[28..16];
VDL_HHT[12..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3;
-- VDL_HBE
VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2
VDL_HBE[].CLK = MAIN_CLK;
VDL_HBE[] = FB_AD[27..16];
VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
VDL_HBE[] = FB_AD[28..16];
VDL_HBE[12..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3;
-- VDL_HDB
VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2
VDL_HDB[].CLK = MAIN_CLK;
VDL_HDB[] = FB_AD[27..16];
VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
VDL_HDB[] = FB_AD[28..16];
VDL_HDB[12..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1;
-- VDL_HDE
VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2
VDL_HDE[].CLK = MAIN_CLK;
VDL_HDE[] = FB_AD[27..16];
VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
VDL_HDE[] = FB_AD[28..16];
VDL_HDE[12..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3;
-- VDL_HBB
VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2
VDL_HBB[].CLK = MAIN_CLK;
VDL_HBB[] = FB_AD[27..16];
VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
VDL_HBB[] = FB_AD[28..16];
VDL_HBB[12..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1;
-- VDL_HSS
VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2
VDL_HSS[].CLK = MAIN_CLK;
VDL_HSS[] = FB_AD[27..16];
VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
VDL_HSS[] = FB_AD[28..16];
VDL_HSS[12..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1;
-- VERTIKAL
-- VDL_VBE
VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2
VDL_VBE[].CLK = MAIN_CLK;
VDL_VBE[] = FB_AD[26..16];
VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
VDL_VBE[] = FB_AD[28..16];
VDL_VBE[12..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3;
-- VDL_VDB
VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2
VDL_VDB[].CLK = MAIN_CLK;
VDL_VDB[] = FB_AD[26..16];
VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
VDL_VDB[] = FB_AD[28..16];
VDL_VDB[12..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1;
-- VDL_VDE
VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2
VDL_VDE[].CLK = MAIN_CLK;
VDL_VDE[] = FB_AD[26..16];
VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
VDL_VDE[] = FB_AD[28..16];
VDL_VDE[12..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3;
-- VDL_VBB
VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2
VDL_VBB[].CLK = MAIN_CLK;
VDL_VBB[] = FB_AD[26..16];
VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
VDL_VBB[] = FB_AD[28..16];
VDL_VBB[12..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1;
-- VDL_VSS
VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2
VDL_VSS[].CLK = MAIN_CLK;
VDL_VSS[] = FB_AD[26..16];
VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
VDL_VSS[] = FB_AD[28..16];
VDL_VSS[12..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1;
-- VDL_VFT
VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2
VDL_VFT[].CLK = MAIN_CLK;
VDL_VFT[] = FB_AD[26..16];
VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
VDL_VFT[] = FB_AD[28..16];
VDL_VFT[12..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3;
-- VDL_VCT
VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2
VDL_VCT[].CLK = MAIN_CLK;
VDL_VCT[] = FB_AD[24..16];
VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0;
VDL_VCT[] = FB_AD[28..16];
VDL_VCT[12..8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0;
VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1;
-- VDL_VMD
VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2
@@ -438,177 +406,152 @@ BEGIN
VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3;
--- REGISTER OUT
FB_AD[31..16] = lpm_bustri_WORD(
ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000")
ST_SHIFT_MODE_CS & (B"00000",ST_SHIFT_MODE[],H"FF")
# FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[])
# SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],BLITTER_RUN,SYS_CTR[2..0])
# VDL_LOF_CS & VDL_LOF[]
# VDL_LWD_CS & VDL_LWD[]
# VDL_HBE_CS & (0,VDL_HBE[])
# VDL_HDB_CS & (0,VDL_HDB[])
# VDL_HDE_CS & (0,VDL_HDE[])
# VDL_HBB_CS & (0,VDL_HBB[])
# VDL_HSS_CS & (0,VDL_HSS[])
# VDL_HHT_CS & (0,VDL_HHT[])
# VDL_VBE_CS & (0,VDL_VBE[])
# VDL_VDB_CS & (0,VDL_VDB[])
# VDL_VDE_CS & (0,VDL_VDE[])
# VDL_VBB_CS & (0,VDL_VBB[])
# VDL_VSS_CS & (0,VDL_VSS[])
# VDL_VFT_CS & (0,VDL_VFT[])
# VDL_VCT_CS & (0,VDL_VCT[])
# VDL_VMD_CS & (0,VDL_VMD[])
# ACP_VCTR_CS & ACP_VCTR[31..16]
# ATARI_HH_CS & ATARI_HH[31..16]
# ATARI_VH_CS & ATARI_VH[31..16]
# ATARI_HL_CS & ATARI_HL[31..16]
# ATARI_VL_CS & ATARI_VL[31..16]
# CCR_CS & (0,CCR[23..16])
# VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
# VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
# VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
# ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS
# VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE);
# SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],BLITTER_RUN,SYS_CTR[2..0])
# VDL_LOF_CS & VDL_LOF[]
# VDL_LWD_CS & WPL[]
# VDL_BPP_CS & (0 + (32 & COLOR24) + (16 & COLOR16) + (8 & COLOR8) + (4 & COLOR4) + (1 & COLOR1))
# VDL_PH_CS & (0,HDIS_LEN[])
# VDL_PV_CS & (0,(VDIS_END[] - VDIS_START[] + 1))
# VDL_HBE_CS & (0,VDL_HBE[])
# VDL_HDB_CS & (0,VDL_HDB[])
# VDL_HDE_CS & (0,VDL_HDE[])
# VDL_HBB_CS & (0,VDL_HBB[])
# VDL_HSS_CS & (0,VDL_HSS[])
# VDL_HHT_CS & (0,VDL_HHT[])
# VDL_VBE_CS & (0,VDL_VBE[])
# VDL_VDB_CS & (0,VDL_VDB[])
# VDL_VDE_CS & (0,VDL_VDE[])
# VDL_VBB_CS & (0,VDL_VBB[])
# VDL_VSS_CS & (0,VDL_VSS[])
# VDL_VFT_CS & (0,VDL_VFT[])
# VDL_VCT_CS & (0,VDL_VCT[])
# VDL_VMD_CS & (0,VDL_VMD[])
# ACP_VCTR_CS & ACP_VCTR[31..16]
# CCR_CS & (0,CCR[23..16])
# VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
# VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
,(ACP_VCTR_CS # CCR_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS # VIDEL_CS # SYS_CTR_CS) & !nFB_OE);
FB_AD[15..0] = lpm_bustri_WORD(
ACP_VCTR_CS & ACP_VCTR[15..0]
# ATARI_HH_CS & ATARI_HH[15..0]
# ATARI_VH_CS & ATARI_VH[15..0]
# ATARI_HL_CS & ATARI_HL[15..0]
# ATARI_VL_CS & ATARI_VL[15..0]
# CCR_CS & CCR[15..0]
,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE);
VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
# VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
# ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
# VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS;
-- VIDEO AUSGABE SETZEN
ACP_VCTR_CS & ACP_VCTR[15..0]
# CCR_CS & CCR[15..0]
,(ACP_VCTR_CS # CCR_CS) & !nFB_OE);
VIDEO_MOD_TA = CLUT_TA # ACP_VCTR_CS # SYS_CTR_CS # VIDEL_CS;
-- VIDEO AUSGABE SETZEN --------------------------------------------------------------
CLK17M.CLK = CLK33M;
CLK17M = !CLK17M;
CLK13M.CLK = CLK25M;
CLK13M = !CLK13M;
PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0)
# CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0)
# CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0
# CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
# CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
# CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
# CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9];
--------------------------------------------------------------
-- HORIZONTALE SYNC L<>NGE in PIXEL_CLK
----------------------------------------------------------------
TE = VDL_VMD2 & !VDL_VCT0 # !VDL_VMD2 & VDL_VCT0; -- 1 WENN HALBE FREQUENZ UND 320*... (200.240.400.480)
PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & VDL_VCT2 & TE
# CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & TE
# CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & VDL_VCT2 & !TE
# CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & !TE
# CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
# CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
# CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9];
-- HORIZONTALE SYNC L<>NGE in PIXEL_CLK -----------------------------------------------------
HSY_LEN[].CLK = MAIN_CLK;
HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0)
# 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0)
# 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0
# 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
# 28 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
# 32 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
# 16 + (0,VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync puls length in pixeln=frequenz/ = 500ns
MULF[] = 2 & !ST_VIDEO & VDL_VMD2 -- MULTIPLIKATIONS FAKTOR
# 4 & !ST_VIDEO & !VDL_VMD2
# 16 & ST_VIDEO & VDL_VMD2
# 32 & ST_VIDEO & !VDL_VMD2;
HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN
# 640 & !VDL_VMD2;
-- DOPPELZEILENMODUS
DOP_ZEI.CLK = MAIN_CLK;
DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS
HSY_LEN[] = 19 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & VDL_VCT2 & TE
# 25 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & TE
# 38 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & VDL_VCT2 & !TE
# 50 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & !TE
# 38 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
# 50 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
# VR_FRQ[] & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync puls length in pixeln=frequenz/ = ca. 1us
-- MULTIPLIKATIONS FAKTOR ----------------------------------------
MULF[] = 1 & !ST_VIDEO & ( TE # VDL_VCT0)
# 2 & !ST_VIDEO & !TE & !VDL_VCT0
# 4 & ST_VIDEO & TE & VDL_VCT0
# 8 & ST_VIDEO & ( TE & !VDL_VCT0 # !TE & VDL_VCT0) -- WENN ST_VIDEO VORTEILER *8
# 16 & ST_VIDEO & !TE & !VDL_VCT0;
-- BREITE IN PIXELN ------------------------------------------------
HDIS_LEN[] = 320 & TE & !ACP_VIDEO_ON
# 640 & !TE & !ACP_VIDEO_ON
# (HDIS_END[] - HDIS_START[] + 1) & ACP_VIDEO_ON;
WPL[] = VDL_LWD[] & !ACP_VIDEO_ON
# (0,HDIS_LEN[12..4]) & COLOR1 & ACP_VIDEO_ON
# (0,HDIS_LEN[12..1]) & COLOR8 & ACP_VIDEO_ON
# (0,HDIS_LEN[]) & COLOR16 & ACP_VIDEO_ON
# (0,HDIS_LEN[],B"0") & COLOR24 & ACP_VIDEO_ON;
-- DOPPELZEILENMODUS ---------------------------------------------
INTER_ZEI.CLK = PIXEL_CLK;
INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
# DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
INTER_ZEI = VDL_VMD0 & (FALCON_VIDEO # ST_VIDEO) & (VVCNT0!=VDIS_START0) & DPZF_CLKENA; -- EINSCHIEBEZEILE BEI UNGERADEN ZEILEN AB DISPLAY START UND NICHT AM ANFANG WEGEN DATATSHIFTOUT
DOP_FIFO_CLR.CLK = PIXEL_CLK;
DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO L<>SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON
# 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# VDL_HBE[] * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
HDIS_START[] = VDL_HDB[] & ACP_VIDEO_ON
# RAND_LINKS[]+1 & !ACP_VIDEO_ON; --
HDIS_END[] = VDL_HDE[] & ACP_VIDEO_ON
# RAND_LINKS[]+HDIS_LEN[] & !ACP_VIDEO_ON; --
RAND_RECHTS[] = VDL_HBB[] & ACP_VIDEO_ON
# HDIS_END[]+1 & !ACP_VIDEO_ON; --
HS_START[] = VDL_HSS[] & ACP_VIDEO_ON
# ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
H_TOTAL[] = VDL_HHT[] & ACP_VIDEO_ON
# ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (VDL_HHT[]+2) * (0,MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
RAND_OBEN[] = VDL_VBE[] & ACP_VIDEO_ON
# 31 & !ACP_VIDEO_ON & ATARI_SYNC
# (0,VDL_VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
VDIS_START[] = VDL_VDB[] & ACP_VIDEO_ON
# 32 & !ACP_VIDEO_ON & ATARI_SYNC
# (0,VDL_VDB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC;
VDIS_END[] = VDL_VDE[] & ACP_VIDEO_ON
# 431 & !ACP_VIDEO_ON & ATARI_SYNC & ST_VIDEO
# 511 & !ACP_VIDEO_ON & ATARI_SYNC & !ST_VIDEO
# (0,VDL_VDE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
RAND_UNTEN[] = VDL_VBB[] & ACP_VIDEO_ON
# VDIS_END[]+1 & !ACP_VIDEO_ON & ATARI_SYNC
# (0,VDL_VBB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC;
VS_START[] = VDL_VSS[] & ACP_VIDEO_ON
# ATARI_VL[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_VH[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (0,VDL_VSS[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
V_TOTAL[] = VDL_VFT[] & ACP_VIDEO_ON
# ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
-- Z<>HLER
DOP_FIFO_CLR = INTER_ZEI & (VHCNT[]==HS_START[]); -- DOPPELZEILENFIFO L<>SCHEN AM ENDE DER UNGERADEN ZEILEN
DPZF_CLKENA = VVCNT[] > 4; -- FIFO DATASHIFTOUT UNTERBINDEN F<>R DOP.ZEI.FIFO
-- TIMING HORIZONTAL
STARTP[] = RAND_LINKS[] + RAND_RECHTS[] - HDIS_LEN[]; -- 2x MITTE SCREEN
RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON
# ((VDL_HBE[] + 1) * MULF[]) & !ACP_VIDEO_ON; --
HDIS_START[] = VDL_HDB[] & ACP_VIDEO_ON
# ((RAND_LINKS[] + 1) & !VDL_VCT0) & !ACP_VIDEO_ON -- MONITOR GANZ RECHTS
# (((0,STARTP[12..1]) + 1) & VDL_VCT0) & !ACP_VIDEO_ON; -- RGB/TV EINMITTEN ZWISCHEN BLANKS
HDIS_END[] = VDL_HDE[] & ACP_VIDEO_ON
# (HDIS_START[] + HDIS_LEN[] - 1) & !ACP_VIDEO_ON; --
RAND_RECHTS[] = VDL_HBB[] & ACP_VIDEO_ON
# ((VDL_HHT[] + 2 + VDL_HBB[]) * MULF[] + 1)& !ACP_VIDEO_ON; --
HS_START[] = VDL_HSS[] & ACP_VIDEO_ON
# ((VDL_HHT[] + 2 + VDL_HSS[]) * MULF[] + 1)& !ACP_VIDEO_ON; --
H_TOTAL[] = VDL_HHT[] & ACP_VIDEO_ON
# ((VDL_HHT[] + 2) * 2 * MULF[]) & !ACP_VIDEO_ON; --
-- TIMING VERTICAL
RAND_OBEN[] = VDL_VBE[] & ACP_VIDEO_ON
# ((0,VDL_VBE[12..1]) & !VDL_VCT0) & !ACP_VIDEO_ON
# (VDL_VBE[] & VDL_VCT0) & !ACP_VIDEO_ON;
VDIS_START[] = VDL_VDB[] & ACP_VIDEO_ON
# (((0,VDL_VDB[12..1]) + 1) & !VDL_VCT0) & !ACP_VIDEO_ON
# (( VDL_VDB[] + 1) & VDL_VCT0) & !ACP_VIDEO_ON;
VDIS_END[] = VDL_VDE[] & ACP_VIDEO_ON
# ((0,VDL_VDE[12..1]) & !VDL_VCT0) & !ACP_VIDEO_ON
# ( VDL_VDE[] & VDL_VCT0) & !ACP_VIDEO_ON;
RAND_UNTEN[] = VDL_VBB[] & ACP_VIDEO_ON
# (((0,VDL_VBB[12..1]) + 1) & !VDL_VCT0) & !ACP_VIDEO_ON
# (( VDL_VBB[] + 1) & VDL_VCT0) & !ACP_VIDEO_ON;
VS_START[] = VDL_VSS[] & ACP_VIDEO_ON
# ((0,VDL_VSS[12..1]) & !VDL_VCT0) & !ACP_VIDEO_ON
# ( VDL_VSS[] & VDL_VCT0) & !ACP_VIDEO_ON;
V_TOTAL[] = VDL_VFT[] & ACP_VIDEO_ON
# (((0,VDL_VFT[12..1]) + 1) & !VDL_VCT0) & !ACP_VIDEO_ON
# ((VDL_VFT[] + 1) & VDL_VCT0) & !ACP_VIDEO_ON;
-- Z<>HLER ---------------------------------------------------------------------------
LAST.CLK = PIXEL_CLK;
LAST = VHCNT[]==(H_TOTAL[]-2);
LAST = VHCNT[]==(H_TOTAL[] - 1);
VHCNT[].CLK = PIXEL_CLK;
VHCNT[] = (VHCNT[] + 1) & !LAST;
VVCNT[].CLK = PIXEL_CLK;
VVCNT[].ENA = LAST;
VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1);
VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]);
-- DISPLAY ON OFF
DPO_ZL.CLK = PIXEL_CLK;
DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1); -- 1 ZEILE DAVOR ON OFF
DPO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN
DPO_ZL = (VVCNT[]>RAND_OBEN[]) & (VVCNT[]<RAND_UNTEN[]); -- ON OFF
DPO_ON.CLK = PIXEL_CLK;
DPO_ON = VHCNT[]==RAND_LINKS[]; -- BESSER EINZELN WEGEN TIMING
DPO_ON = VHCNT[]==RAND_LINKS[] - 1; -- BESSER EINZELN WEGEN TIMING
DPO_OFF.CLK = PIXEL_CLK;
DPO_OFF = VHCNT[]==(RAND_RECHTS[]-1);
DPO_OFF = VHCNT[]==(RAND_RECHTS[] - 2);
DISP_ON.CLK = PIXEL_CLK;
DISP_ON = DISP_ON & !DPO_OFF
# DPO_ON & DPO_ZL;
-- DATENTRANSFER ON OFF
VDO_ON.CLK = PIXEL_CLK;
VDO_ON = VHCNT[]==(HDIS_START[]-1); -- BESSER EINZELN WEGEN TIMING
VDO_ON = VHCNT[]==(HDIS_START[] - 2); -- BESSER EINZELN WEGEN TIMING
VDO_OFF.CLK = PIXEL_CLK;
VDO_OFF = VHCNT[]==HDIS_END[];
VDO_OFF = VHCNT[]==(HDIS_END[] - 1);
VDO_ZL.CLK = PIXEL_CLK;
VDO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN
VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]); -- 1 ZEILE DAVOR ON OFF
VDO_ZL = (VVCNT[]>=(VDIS_START[])) & (VVCNT[]<=VDIS_END[]); -- ON OFF
VDTRON.CLK = PIXEL_CLK;
VDTRON = VDTRON & !VDO_OFF
# VDO_ON & VDO_ZL;
-- VERZ<52>GERUNG UND SYNC
HSYNC_START.CLK = PIXEL_CLK;
HSYNC_START = VHCNT[]==HS_START[]-3;
HSYNC_START = VHCNT[]==HS_START[] - 2;
HSYNC_I[].CLK = PIXEL_CLK;
HSYNC_I[] = HSY_LEN[] & HSYNC_START
# (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
VSYNC_START.CLK = PIXEL_CLK;
VSYNC_START.ENA = LAST;
VSYNC_START = VVCNT[]==(VS_START[]-3); -- start am ende der Zeile vor dem vsync
VSYNC_I[].CLK = PIXEL_CLK;
VSYNC_I[].ENA = LAST; -- start am ende der Zeile vor dem vsync
VSYNC_I[] = 3 & VSYNC_START -- 3 zeilen vsync length
# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0; -- runterz<72>hlen bis 0
VSYNC_I[] = VVCNT[12..1]==VS_START[12..1]; -- VSYNC BEI VS_START 2 ZEILEN LANG
VSYNC_I[].CLK = PIXEL_CLK;
VERZ[][].CLK = PIXEL_CLK;
VERZ[][1] = VERZ[][0];
VERZ[][2] = VERZ[][1];
@@ -620,11 +563,10 @@ BEGIN
VERZ[][8] = VERZ[][7];
VERZ[][9] = VERZ[][8];
VERZ[0][0] = DISP_ON;
-- VERZ[1][0] = HSYNC_I[]!=0;
VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
# ACP_VCTR15 & VDL_VCT6 & HSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE
VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
# ACP_VCTR15 & VDL_VCT5 & VSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE
VERZ[1][0] = !VDL_VCT6 & HSYNC_I[]!=0
# VDL_VCT6 & HSYNC_I[]==0;
VERZ[2][0] = !VDL_VCT5 & VSYNC_I[]!=0
# VDL_VCT5 & VSYNC_I[]==0;
nBLANK.CLK = PIXEL_CLK;
nBLANK = VERZ[0][8];
HSYNC.CLK = PIXEL_CLK;
@@ -645,10 +587,10 @@ BEGIN
----------------------------------------------------------
CLR_FIFO.CLK = PIXEL_CLK;
CLR_FIFO.ENA = LAST;
CLR_FIFO = VVCNT[]==V_TOTAL[]-2; -- IN LETZTER ZEILE L<>SCHEN
CLR_FIFO = VVCNT[]==(VDIS_END[] + 2); -- FIFO NACH ENDE ANZEIGE L<>SCHEN (GENUG FR<46>H DAMIT ES GEF<45>LLT WERDEN KANN BIS ZUR NEUEN <20>BERTRAGUNG)
START_ZEILE.CLK = PIXEL_CLK;
START_ZEILE.ENA = LAST;
START_ZEILE = VVCNT[]==0; -- ZEILE 1
START_ZEILE = VVCNT[]==1; -- ZEILE 1
SYNC_PIX.CLK = PIXEL_CLK;
SYNC_PIX = VHCNT[]==3 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX1.CLK = PIXEL_CLK;

482
FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
View File

@@ -59,6 +59,7 @@ SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
VR_WR : OUTPUT;
VR_RD : OUTPUT;
CLR_FIFO : OUTPUT;
DPZF_CLKENA: OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
@@ -80,7 +81,7 @@ VARIABLE
ST_CLUT :NODE;
FB_B[3..0] :NODE;
FB_16B[1..0] :NODE;
ST_SHIFT_MODE[1..0] :DFFE;
ST_SHIFT_MODE[2..0] :DFFE;
ST_SHIFT_MODE_CS :NODE;
FALCON_SHIFT_MODE[10..0] :DFFE;
FALCON_SHIFT_MODE_CS :NODE;
@@ -105,20 +106,19 @@ VARIABLE
HSYNC_START :DFF;
LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT
VSYNC :DFF;
VSYNC_START :DFFE;
VSYNC_I[2..0] :DFFE;
VSYNC_I[2..0] :DFF;
nBLANK :DFF;
DISP_ON :DFF;
DPO_ZL :DFFE;
DPO_ZL :DFF;
DPO_ON :DFF;
DPO_OFF :DFF;
VDTRON :DFF;
VDO_ZL :DFFE;
VDO_ZL :DFF;
VDO_ON :DFF;
VDO_OFF :DFF;
VHCNT[11..0] :DFF;
VHCNT[12..0] :DFF;
SUB_PIXEL_CNT[6..0] :DFFE;
VVCNT[10..0] :DFFE;
VVCNT[12..0] :DFFE;
VERZ[2..0][9..0] :DFF;
RAND[6..0] :DFF;
RAND_ON :NODE;
@@ -130,67 +130,63 @@ VARIABLE
SYNC_PIX2 :DFF;
CCSEL[2..0] :DFF;
COLOR16 :NODE;
COLOR24 :NODE;
-- ATARI RESOLUTION
ATARI_SYNC :NODE;
ATARI_HH[31..0] :DFFE; -- HORIZONTAL TIMING 640x480
ATARI_HH_CS :NODE;
ATARI_VH[31..0] :DFFE; -- VERTIKAL TIMING 640x480
ATARI_VH_CS :NODE;
ATARI_HL[31..0] :DFFE; -- HORIZONTAL TIMING 320x240
ATARI_HL_CS :NODE;
ATARI_VL[31..0] :DFFE; -- VERTIKAL TIMING 320x240
ATARI_VL_CS :NODE;
COLOR24 :NODE; -- IST ABER 32BIT BREIT
TE :NODE;
-- HORIZONTAL
RAND_LINKS[11..0] :NODE;
HDIS_START[11..0] :NODE;
HDIS_END[11..0] :NODE;
RAND_RECHTS[11..0] :NODE;
HS_START[11..0] :NODE;
H_TOTAL[11..0] :NODE;
HDIS_LEN[11..0] :NODE;
MULF[5..0] :NODE;
VDL_HHT[11..0] :DFFE;
RAND_LINKS[12..0] :NODE;
HDIS_START[12..0] :NODE;
STARTP[12..0] :NODE;
HDIS_END[12..0] :NODE;
RAND_RECHTS[12..0] :NODE;
MULF[12..0] :NODE;
HS_START[12..0] :NODE;
H_TOTAL[12..0] :NODE;
HDIS_LEN[12..0] :NODE;
WPL[15..0] :NODE;
VDL_HHT[12..0] :DFFE;
VDL_HHT_CS :NODE;
VDL_HBE[11..0] :DFFE;
VDL_HBE[12..0] :DFFE;
VDL_HBE_CS :NODE;
VDL_HDB[11..0] :DFFE;
VDL_HDB[12..0] :DFFE;
VDL_HDB_CS :NODE;
VDL_HDE[11..0] :DFFE;
VDL_HDE[12..0] :DFFE;
VDL_HDE_CS :NODE;
VDL_HBB[11..0] :DFFE;
VDL_HBB[12..0] :DFFE;
VDL_HBB_CS :NODE;
VDL_HSS[11..0] :DFFE;
VDL_HSS[12..0] :DFFE;
VDL_HSS_CS :NODE;
-- VERTIKAL
RAND_OBEN[10..0] :NODE;
VDIS_START[10..0] :NODE;
VDIS_END[10..0] :NODE;
RAND_UNTEN[10..0] :NODE;
VS_START[10..0] :NODE;
V_TOTAL[10..0] :NODE;
RAND_OBEN[12..0] :NODE;
VDIS_START[12..0] :NODE;
VDIS_END[12..0] :NODE;
RAND_UNTEN[12..0] :NODE;
VS_START[12..0] :NODE;
V_TOTAL[12..0] :NODE;
FALCON_VIDEO :NODE;
ST_VIDEO :NODE;
INTER_ZEI :DFF;
DOP_ZEI :DFF;
DOP_FIFO_CLR :DFF;
VDL_VBE[10..0] :DFFE;
VIDEL_CS :NODE;
VDL_VBE[12..0] :DFFE;
VDL_VBE_CS :NODE;
VDL_VDB[10..0] :DFFE;
VDL_VDB[12..0] :DFFE;
VDL_VDB_CS :NODE;
VDL_VDE[10..0] :DFFE;
VDL_VDE[12..0] :DFFE;
VDL_VDE_CS :NODE;
VDL_VBB[10..0] :DFFE;
VDL_VBB[12..0] :DFFE;
VDL_VBB_CS :NODE;
VDL_VSS[10..0] :DFFE;
VDL_VSS[12..0] :DFFE;
VDL_VSS_CS :NODE;
VDL_VFT[10..0] :DFFE;
VDL_VFT[12..0] :DFFE;
VDL_VFT_CS :NODE;
VDL_VCT[8..0] :DFFE;
VDL_VCT[12..0] :DFFE;
VDL_VCT_CS :NODE;
VDL_VMD[3..0] :DFFE;
VDL_VMD_CS :NODE;
VDL_BPP_CS :NODE;
VDL_PH_CS :NODE;
VDL_PV_CS :NODE;
BEGIN
-- BYT SELECT 32 BIT
@@ -207,6 +203,8 @@ BEGIN
FB_16B0 = FB_ADR[0]==0; -- ADR==0
FB_16B1 = FB_ADR[0]==1 -- ADR==1
# !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT
-- VIDEL CS
VIDEL_CS = !nFB_CS1 & FB_ADR[19..8]==H"F82"; -- FFF'F8200-FFF'F82FF
-- ACP CLUT --
ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0"; -- 0-3FF/1024
ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
@@ -226,11 +224,11 @@ BEGIN
-- ST SHIFT MODE
ST_SHIFT_MODE[].CLK = MAIN_CLK;
ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130"; -- $F8260/2
ST_SHIFT_MODE[] = FB_AD[25..24];
ST_SHIFT_MODE[] = FB_AD[26..24];
ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO
COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN
COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN
COLOR1 = ST_SHIFT_MODE[]==B"010" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO
COLOR2 = ST_SHIFT_MODE[]==B"001" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN
COLOR4 = ST_SHIFT_MODE[]==B"000" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN
-- FALCON SHIFT MODE
FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133"; -- $F8266/2
@@ -238,13 +236,13 @@ BEGIN
FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
FALCON_SHIFT_MODE[7..0].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
COLOR1 = FALCON_SHIFT_MODE[] == H"400" & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR4 = FALCON_SHIFT_MODE[] == H"000" & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR8 = FALCON_SHIFT_MODE[] == H"010" & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR16 = FALCON_SHIFT_MODE[] == H"100" & FALCON_VIDEO & !ACP_VIDEO_ON;
-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN
ACP_VCTR[].CLK = MAIN_CLK;
ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100"; -- $400/4
ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100"; -- $F000'0400
ACP_VCTR[31..8] = FB_AD[31..8];
ACP_VCTR[5..0] = FB_AD[5..0];
ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
@@ -253,42 +251,8 @@ BEGIN
ACP_VCTR[5..0].ENA = ACP_VCTR_CS & FB_B3 & !nFB_WR;
ACP_VIDEO_ON = ACP_VCTR0;
nPD_VGA = ACP_VCTR1;
-- ATARI MODUS
ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFL<46>SUNG
-- HORIZONTAL TIMING 640x480
ATARI_HH[].CLK = MAIN_CLK;
ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4
ATARI_HH[] = FB_AD[];
ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR;
ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR;
ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR;
-- VERTIKAL TIMING 640x480
ATARI_VH[].CLK = MAIN_CLK;
ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105"; -- $414/4
ATARI_VH[] = FB_AD[];
ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR;
ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR;
ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR;
-- HORIZONTAL TIMING 320x240
ATARI_HL[].CLK = MAIN_CLK;
ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106"; -- $418/4
ATARI_HL[] = FB_AD[];
ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR;
ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR;
ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR;
-- VERTIKAL TIMING 320x240
ATARI_VL[].CLK = MAIN_CLK;
ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107"; -- $41C/4
ATARI_VL[] = FB_AD[];
ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR;
ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR;
ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR;
-- VIDEO PLL CONFIG
VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $F000'0600-7FF ->6/2 WORD RESP LONG ONLY
VR_WR.CLK = MAIN_CLK;
VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & !VR_BUSY;
@@ -299,7 +263,7 @@ BEGIN
VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
VR_FRQ[] = FB_AD[23..16];
-- VIDEO PLL RECONFIG
VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800
VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $F000'0800
VIDEO_RECONFIG.CLK = MAIN_CLK;
VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
------------------------------------------------------------------------------------------------------------------------
@@ -313,11 +277,11 @@ BEGIN
-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
ACP_VCTR[7..6].ENA = (FALCON_SHIFT_MODE_CS # ST_SHIFT_MODE_CS) & !nFB_WR;
FALCON_VIDEO = ACP_VCTR7;
ST_VIDEO = ACP_VCTR6 & !ACP_VCTR7;
FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
ST_VIDEO = ACP_VCTR6;
ST_CLUT = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1;
ST_CLUT = ST_VIDEO & !ACP_VIDEO_ON & !COLOR1;
CCSEL[].CLK = PIXEL_CLK;
CCSEL[] = B"000" & ST_CLUT -- ONLY FOR INFORMATION
# B"001" & FALCON_CLUT
@@ -328,108 +292,112 @@ BEGIN
-- DIVERSE (VIDEO)-REGISTER ----------------------------
-- RANDFARBE
CCR[].CLK = MAIN_CLK;
CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4
CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $F004'0404/4
CCR[] = FB_AD[23..0];
CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR;
CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR;
--SYS CTR
SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2
SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $FFFF'8006
SYS_CTR[].CLK = MAIN_CLK;
SYS_CTR[6..0] = FB_AD[22..16];
SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3;
BLITTER_ON = !SYS_CTR3;
BLITTER_ON = SYS_CTR3;
--VDL_LOF
VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2
VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $F820E/2
VDL_LOF[].CLK = MAIN_CLK;
VDL_LOF[] = FB_AD[31..16];
VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3;
--VDL_LWD
VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2
VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $F8210/2
VDL_LWD[].CLK = MAIN_CLK;
VDL_LWD[] = FB_AD[31..16];
VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1;
-- DATEN AUFL<46>SUNG
VDL_BPP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C109"; -- $F8212: BITS PER PIXEL
VDL_PH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C10A"; -- $F8214: BREITE IN PIXE
VDL_PV_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C10B"; -- $F8216: BREITE IN PIXE
-- HORIZONTAL
-- VDL_HHT
VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2
VDL_HHT[].CLK = MAIN_CLK;
VDL_HHT[] = FB_AD[27..16];
VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
VDL_HHT[] = FB_AD[28..16];
VDL_HHT[12..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3;
-- VDL_HBE
VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2
VDL_HBE[].CLK = MAIN_CLK;
VDL_HBE[] = FB_AD[27..16];
VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
VDL_HBE[] = FB_AD[28..16];
VDL_HBE[12..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3;
-- VDL_HDB
VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2
VDL_HDB[].CLK = MAIN_CLK;
VDL_HDB[] = FB_AD[27..16];
VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
VDL_HDB[] = FB_AD[28..16];
VDL_HDB[12..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1;
-- VDL_HDE
VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2
VDL_HDE[].CLK = MAIN_CLK;
VDL_HDE[] = FB_AD[27..16];
VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
VDL_HDE[] = FB_AD[28..16];
VDL_HDE[12..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3;
-- VDL_HBB
VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2
VDL_HBB[].CLK = MAIN_CLK;
VDL_HBB[] = FB_AD[27..16];
VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
VDL_HBB[] = FB_AD[28..16];
VDL_HBB[12..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1;
-- VDL_HSS
VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2
VDL_HSS[].CLK = MAIN_CLK;
VDL_HSS[] = FB_AD[27..16];
VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
VDL_HSS[] = FB_AD[28..16];
VDL_HSS[12..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1;
-- VERTIKAL
-- VDL_VBE
VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2
VDL_VBE[].CLK = MAIN_CLK;
VDL_VBE[] = FB_AD[26..16];
VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
VDL_VBE[] = FB_AD[28..16];
VDL_VBE[12..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3;
-- VDL_VDB
VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2
VDL_VDB[].CLK = MAIN_CLK;
VDL_VDB[] = FB_AD[26..16];
VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
VDL_VDB[] = FB_AD[28..16];
VDL_VDB[12..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1;
-- VDL_VDE
VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2
VDL_VDE[].CLK = MAIN_CLK;
VDL_VDE[] = FB_AD[26..16];
VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
VDL_VDE[] = FB_AD[28..16];
VDL_VDE[12..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3;
-- VDL_VBB
VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2
VDL_VBB[].CLK = MAIN_CLK;
VDL_VBB[] = FB_AD[26..16];
VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
VDL_VBB[] = FB_AD[28..16];
VDL_VBB[12..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1;
-- VDL_VSS
VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2
VDL_VSS[].CLK = MAIN_CLK;
VDL_VSS[] = FB_AD[26..16];
VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
VDL_VSS[] = FB_AD[28..16];
VDL_VSS[12..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1;
-- VDL_VFT
VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2
VDL_VFT[].CLK = MAIN_CLK;
VDL_VFT[] = FB_AD[26..16];
VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
VDL_VFT[] = FB_AD[28..16];
VDL_VFT[12..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3;
-- VDL_VCT
VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2
VDL_VCT[].CLK = MAIN_CLK;
VDL_VCT[] = FB_AD[24..16];
VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0;
VDL_VCT[] = FB_AD[28..16];
VDL_VCT[12..8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0;
VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1;
-- VDL_VMD
VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2
@@ -438,177 +406,152 @@ BEGIN
VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3;
--- REGISTER OUT
FB_AD[31..16] = lpm_bustri_WORD(
ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000")
ST_SHIFT_MODE_CS & (B"00000",ST_SHIFT_MODE[],H"FF")
# FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[])
# SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],BLITTER_RUN,SYS_CTR[2..0])
# VDL_LOF_CS & VDL_LOF[]
# VDL_LWD_CS & VDL_LWD[]
# VDL_HBE_CS & (0,VDL_HBE[])
# VDL_HDB_CS & (0,VDL_HDB[])
# VDL_HDE_CS & (0,VDL_HDE[])
# VDL_HBB_CS & (0,VDL_HBB[])
# VDL_HSS_CS & (0,VDL_HSS[])
# VDL_HHT_CS & (0,VDL_HHT[])
# VDL_VBE_CS & (0,VDL_VBE[])
# VDL_VDB_CS & (0,VDL_VDB[])
# VDL_VDE_CS & (0,VDL_VDE[])
# VDL_VBB_CS & (0,VDL_VBB[])
# VDL_VSS_CS & (0,VDL_VSS[])
# VDL_VFT_CS & (0,VDL_VFT[])
# VDL_VCT_CS & (0,VDL_VCT[])
# VDL_VMD_CS & (0,VDL_VMD[])
# ACP_VCTR_CS & ACP_VCTR[31..16]
# ATARI_HH_CS & ATARI_HH[31..16]
# ATARI_VH_CS & ATARI_VH[31..16]
# ATARI_HL_CS & ATARI_HL[31..16]
# ATARI_VL_CS & ATARI_VL[31..16]
# CCR_CS & (0,CCR[23..16])
# VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
# VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
# VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
# ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS
# VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE);
# SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],BLITTER_RUN,SYS_CTR[2..0])
# VDL_LOF_CS & VDL_LOF[]
# VDL_LWD_CS & WPL[]
# VDL_BPP_CS & (0 + (32 & COLOR24) + (16 & COLOR16) + (8 & COLOR8) + (4 & COLOR4) + (1 & COLOR1))
# VDL_PH_CS & (0,HDIS_LEN[])
# VDL_PV_CS & (0,(VDIS_END[] - VDIS_START[] + 1))
# VDL_HBE_CS & (0,VDL_HBE[])
# VDL_HDB_CS & (0,VDL_HDB[])
# VDL_HDE_CS & (0,VDL_HDE[])
# VDL_HBB_CS & (0,VDL_HBB[])
# VDL_HSS_CS & (0,VDL_HSS[])
# VDL_HHT_CS & (0,VDL_HHT[])
# VDL_VBE_CS & (0,VDL_VBE[])
# VDL_VDB_CS & (0,VDL_VDB[])
# VDL_VDE_CS & (0,VDL_VDE[])
# VDL_VBB_CS & (0,VDL_VBB[])
# VDL_VSS_CS & (0,VDL_VSS[])
# VDL_VFT_CS & (0,VDL_VFT[])
# VDL_VCT_CS & (0,VDL_VCT[])
# VDL_VMD_CS & (0,VDL_VMD[])
# ACP_VCTR_CS & ACP_VCTR[31..16]
# CCR_CS & (0,CCR[23..16])
# VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
# VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
,(ACP_VCTR_CS # CCR_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS # VIDEL_CS # SYS_CTR_CS) & !nFB_OE);
FB_AD[15..0] = lpm_bustri_WORD(
ACP_VCTR_CS & ACP_VCTR[15..0]
# ATARI_HH_CS & ATARI_HH[15..0]
# ATARI_VH_CS & ATARI_VH[15..0]
# ATARI_HL_CS & ATARI_HL[15..0]
# ATARI_VL_CS & ATARI_VL[15..0]
# CCR_CS & CCR[15..0]
,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE);
VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
# VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
# ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
# VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS;
-- VIDEO AUSGABE SETZEN
ACP_VCTR_CS & ACP_VCTR[15..0]
# CCR_CS & CCR[15..0]
,(ACP_VCTR_CS # CCR_CS) & !nFB_OE);
VIDEO_MOD_TA = CLUT_TA # ACP_VCTR_CS # SYS_CTR_CS # VIDEL_CS;
-- VIDEO AUSGABE SETZEN --------------------------------------------------------------
CLK17M.CLK = CLK33M;
CLK17M = !CLK17M;
CLK13M.CLK = CLK25M;
CLK13M = !CLK13M;
PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0)
# CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0)
# CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0
# CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
# CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
# CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
# CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9];
--------------------------------------------------------------
-- HORIZONTALE SYNC L<>NGE in PIXEL_CLK
----------------------------------------------------------------
TE = VDL_VMD2 & !VDL_VCT0 # !VDL_VMD2 & VDL_VCT0; -- 1 WENN HALBE FREQUENZ UND 320*... (200.240.400.480)
PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & VDL_VCT2 & TE
# CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & TE
# CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & VDL_VCT2 & !TE
# CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & !TE
# CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
# CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
# CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9];
-- HORIZONTALE SYNC L<>NGE in PIXEL_CLK -----------------------------------------------------
HSY_LEN[].CLK = MAIN_CLK;
HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0)
# 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0)
# 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0
# 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
# 28 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
# 32 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
# 16 + (0,VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync puls length in pixeln=frequenz/ = 500ns
MULF[] = 2 & !ST_VIDEO & VDL_VMD2 -- MULTIPLIKATIONS FAKTOR
# 4 & !ST_VIDEO & !VDL_VMD2
# 16 & ST_VIDEO & VDL_VMD2
# 32 & ST_VIDEO & !VDL_VMD2;
HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN
# 640 & !VDL_VMD2;
-- DOPPELZEILENMODUS
DOP_ZEI.CLK = MAIN_CLK;
DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS
HSY_LEN[] = 19 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & VDL_VCT2 & TE
# 25 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & TE
# 38 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & VDL_VCT2 & !TE
# 50 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & !TE
# 38 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
# 50 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
# VR_FRQ[] & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync puls length in pixeln=frequenz/ = ca. 1us
-- MULTIPLIKATIONS FAKTOR ----------------------------------------
MULF[] = 1 & !ST_VIDEO & ( TE # VDL_VCT0)
# 2 & !ST_VIDEO & !TE & !VDL_VCT0
# 4 & ST_VIDEO & TE & VDL_VCT0
# 8 & ST_VIDEO & ( TE & !VDL_VCT0 # !TE & VDL_VCT0) -- WENN ST_VIDEO VORTEILER *8
# 16 & ST_VIDEO & !TE & !VDL_VCT0;
-- BREITE IN PIXELN ------------------------------------------------
HDIS_LEN[] = 320 & TE & !ACP_VIDEO_ON
# 640 & !TE & !ACP_VIDEO_ON
# (HDIS_END[] - HDIS_START[] + 1) & ACP_VIDEO_ON;
WPL[] = VDL_LWD[] & !ACP_VIDEO_ON
# (0,HDIS_LEN[12..4]) & COLOR1 & ACP_VIDEO_ON
# (0,HDIS_LEN[12..1]) & COLOR8 & ACP_VIDEO_ON
# (0,HDIS_LEN[]) & COLOR16 & ACP_VIDEO_ON
# (0,HDIS_LEN[],B"0") & COLOR24 & ACP_VIDEO_ON;
-- DOPPELZEILENMODUS ---------------------------------------------
INTER_ZEI.CLK = PIXEL_CLK;
INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
# DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
INTER_ZEI = VDL_VMD0 & (FALCON_VIDEO # ST_VIDEO) & (VVCNT0!=VDIS_START0) & DPZF_CLKENA; -- EINSCHIEBEZEILE BEI UNGERADEN ZEILEN AB DISPLAY START UND NICHT AM ANFANG WEGEN DATATSHIFTOUT
DOP_FIFO_CLR.CLK = PIXEL_CLK;
DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO L<>SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON
# 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# VDL_HBE[] * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
HDIS_START[] = VDL_HDB[] & ACP_VIDEO_ON
# RAND_LINKS[]+1 & !ACP_VIDEO_ON; --
HDIS_END[] = VDL_HDE[] & ACP_VIDEO_ON
# RAND_LINKS[]+HDIS_LEN[] & !ACP_VIDEO_ON; --
RAND_RECHTS[] = VDL_HBB[] & ACP_VIDEO_ON
# HDIS_END[]+1 & !ACP_VIDEO_ON; --
HS_START[] = VDL_HSS[] & ACP_VIDEO_ON
# ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
H_TOTAL[] = VDL_HHT[] & ACP_VIDEO_ON
# ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (VDL_HHT[]+2) * (0,MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
RAND_OBEN[] = VDL_VBE[] & ACP_VIDEO_ON
# 31 & !ACP_VIDEO_ON & ATARI_SYNC
# (0,VDL_VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
VDIS_START[] = VDL_VDB[] & ACP_VIDEO_ON
# 32 & !ACP_VIDEO_ON & ATARI_SYNC
# (0,VDL_VDB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC;
VDIS_END[] = VDL_VDE[] & ACP_VIDEO_ON
# 431 & !ACP_VIDEO_ON & ATARI_SYNC & ST_VIDEO
# 511 & !ACP_VIDEO_ON & ATARI_SYNC & !ST_VIDEO
# (0,VDL_VDE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
RAND_UNTEN[] = VDL_VBB[] & ACP_VIDEO_ON
# VDIS_END[]+1 & !ACP_VIDEO_ON & ATARI_SYNC
# (0,VDL_VBB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC;
VS_START[] = VDL_VSS[] & ACP_VIDEO_ON
# ATARI_VL[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_VH[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (0,VDL_VSS[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
V_TOTAL[] = VDL_VFT[] & ACP_VIDEO_ON
# ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
-- Z<>HLER
DOP_FIFO_CLR = INTER_ZEI & (VHCNT[]==HS_START[]); -- DOPPELZEILENFIFO L<>SCHEN AM ENDE DER UNGERADEN ZEILEN
DPZF_CLKENA = VVCNT[] > 4; -- FIFO DATASHIFTOUT UNTERBINDEN F<>R DOP.ZEI.FIFO
-- TIMING HORIZONTAL
STARTP[] = RAND_LINKS[] + RAND_RECHTS[] - HDIS_LEN[]; -- 2x MITTE SCREEN
RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON
# ((VDL_HBE[] + 1) * MULF[]) & !ACP_VIDEO_ON; --
HDIS_START[] = VDL_HDB[] & ACP_VIDEO_ON
# ((RAND_LINKS[] + 1) & !VDL_VCT0) & !ACP_VIDEO_ON -- MONITOR GANZ RECHTS
# (((0,STARTP[12..1]) + 1) & VDL_VCT0) & !ACP_VIDEO_ON; -- RGB/TV EINMITTEN ZWISCHEN BLANKS
HDIS_END[] = VDL_HDE[] & ACP_VIDEO_ON
# (HDIS_START[] + HDIS_LEN[] - 1) & !ACP_VIDEO_ON; --
RAND_RECHTS[] = VDL_HBB[] & ACP_VIDEO_ON
# ((VDL_HHT[] + (2 & !ST_VIDEO) + VDL_HBB[]) * MULF[] + 1)& !ACP_VIDEO_ON; --
HS_START[] = VDL_HSS[] & ACP_VIDEO_ON
# ((VDL_HHT[] + (2 & !ST_VIDEO) + VDL_HSS[]) * MULF[] + 1)& !ACP_VIDEO_ON; --
H_TOTAL[] = VDL_HHT[] & ACP_VIDEO_ON
# ((VDL_HHT[] + 2) * 2 * MULF[]) & !ACP_VIDEO_ON; --
-- TIMING VERTICAL
RAND_OBEN[] = VDL_VBE[] & ACP_VIDEO_ON
# ((0,VDL_VBE[12..1]) & !VDL_VCT0) & !ACP_VIDEO_ON
# (VDL_VBE[] & VDL_VCT0) & !ACP_VIDEO_ON;
VDIS_START[] = VDL_VDB[] & ACP_VIDEO_ON
# (((0,VDL_VDB[12..1]) + 1) & !VDL_VCT0) & !ACP_VIDEO_ON
# (( VDL_VDB[] + 1) & VDL_VCT0) & !ACP_VIDEO_ON;
VDIS_END[] = VDL_VDE[] & ACP_VIDEO_ON
# ((0,VDL_VDE[12..1]) & !VDL_VCT0) & !ACP_VIDEO_ON
# ( VDL_VDE[] & VDL_VCT0) & !ACP_VIDEO_ON;
RAND_UNTEN[] = VDL_VBB[] & ACP_VIDEO_ON
# (((0,VDL_VBB[12..1]) + 1) & !VDL_VCT0) & !ACP_VIDEO_ON
# (( VDL_VBB[] + 1) & VDL_VCT0) & !ACP_VIDEO_ON;
VS_START[] = VDL_VSS[] & ACP_VIDEO_ON
# ((0,VDL_VSS[12..1]) & !VDL_VCT0) & !ACP_VIDEO_ON
# ( VDL_VSS[] & VDL_VCT0) & !ACP_VIDEO_ON;
V_TOTAL[] = VDL_VFT[] & ACP_VIDEO_ON
# (((0,VDL_VFT[12..1]) + 1) & !VDL_VCT0) & !ACP_VIDEO_ON
# ((VDL_VFT[] + 1) & VDL_VCT0) & !ACP_VIDEO_ON;
-- Z<>HLER ---------------------------------------------------------------------------
LAST.CLK = PIXEL_CLK;
LAST = VHCNT[]==(H_TOTAL[]-2);
LAST = VHCNT[]==(H_TOTAL[] - 1);
VHCNT[].CLK = PIXEL_CLK;
VHCNT[] = (VHCNT[] + 1) & !LAST;
VVCNT[].CLK = PIXEL_CLK;
VVCNT[].ENA = LAST;
VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1);
VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]);
-- DISPLAY ON OFF
DPO_ZL.CLK = PIXEL_CLK;
DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1); -- 1 ZEILE DAVOR ON OFF
DPO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN
DPO_ZL = (VVCNT[]>RAND_OBEN[]) & (VVCNT[]<RAND_UNTEN[]); -- ON OFF
DPO_ON.CLK = PIXEL_CLK;
DPO_ON = VHCNT[]==RAND_LINKS[]; -- BESSER EINZELN WEGEN TIMING
DPO_ON = VHCNT[]==RAND_LINKS[] - 1; -- BESSER EINZELN WEGEN TIMING
DPO_OFF.CLK = PIXEL_CLK;
DPO_OFF = VHCNT[]==(RAND_RECHTS[]-1);
DPO_OFF = VHCNT[]==(RAND_RECHTS[] - 2);
DISP_ON.CLK = PIXEL_CLK;
DISP_ON = DISP_ON & !DPO_OFF
# DPO_ON & DPO_ZL;
-- DATENTRANSFER ON OFF
VDO_ON.CLK = PIXEL_CLK;
VDO_ON = VHCNT[]==(HDIS_START[]-1); -- BESSER EINZELN WEGEN TIMING
VDO_ON = VHCNT[]==(HDIS_START[] - 2); -- BESSER EINZELN WEGEN TIMING
VDO_OFF.CLK = PIXEL_CLK;
VDO_OFF = VHCNT[]==HDIS_END[];
VDO_OFF = VHCNT[]==(HDIS_END[] - 1);
VDO_ZL.CLK = PIXEL_CLK;
VDO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN
VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]); -- 1 ZEILE DAVOR ON OFF
VDO_ZL = (VVCNT[]>=(VDIS_START[])) & (VVCNT[]<=VDIS_END[]); -- ON OFF
VDTRON.CLK = PIXEL_CLK;
VDTRON = VDTRON & !VDO_OFF
# VDO_ON & VDO_ZL;
-- VERZ<52>GERUNG UND SYNC
HSYNC_START.CLK = PIXEL_CLK;
HSYNC_START = VHCNT[]==HS_START[]-3;
HSYNC_START = VHCNT[]==HS_START[] - 2;
HSYNC_I[].CLK = PIXEL_CLK;
HSYNC_I[] = HSY_LEN[] & HSYNC_START
# (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
VSYNC_START.CLK = PIXEL_CLK;
VSYNC_START.ENA = LAST;
VSYNC_START = VVCNT[]==(VS_START[]-3); -- start am ende der Zeile vor dem vsync
VSYNC_I[].CLK = PIXEL_CLK;
VSYNC_I[].ENA = LAST; -- start am ende der Zeile vor dem vsync
VSYNC_I[] = 3 & VSYNC_START -- 3 zeilen vsync length
# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0; -- runterz<72>hlen bis 0
VSYNC_I[] = VVCNT[12..1]==VS_START[12..1]; -- VSYNC BEI VS_START 2 ZEILEN LANG
VSYNC_I[].CLK = PIXEL_CLK;
VERZ[][].CLK = PIXEL_CLK;
VERZ[][1] = VERZ[][0];
VERZ[][2] = VERZ[][1];
@@ -620,11 +563,10 @@ BEGIN
VERZ[][8] = VERZ[][7];
VERZ[][9] = VERZ[][8];
VERZ[0][0] = DISP_ON;
-- VERZ[1][0] = HSYNC_I[]!=0;
VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
# ACP_VCTR15 & VDL_VCT6 & HSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE
VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
# ACP_VCTR15 & VDL_VCT5 & VSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE
VERZ[1][0] = !VDL_VCT6 & HSYNC_I[]!=0
# VDL_VCT6 & HSYNC_I[]==0;
VERZ[2][0] = !VDL_VCT5 & VSYNC_I[]!=0
# VDL_VCT5 & VSYNC_I[]==0;
nBLANK.CLK = PIXEL_CLK;
nBLANK = VERZ[0][8];
HSYNC.CLK = PIXEL_CLK;
@@ -645,10 +587,10 @@ BEGIN
----------------------------------------------------------
CLR_FIFO.CLK = PIXEL_CLK;
CLR_FIFO.ENA = LAST;
CLR_FIFO = VVCNT[]==V_TOTAL[]-2; -- IN LETZTER ZEILE L<>SCHEN
CLR_FIFO = VVCNT[]==(VDIS_END[] + 2); -- FIFO NACH ENDE ANZEIGE L<>SCHEN (GENUG FR<46>H DAMIT ES GEF<45>LLT WERDEN KANN BIS ZUR NEUEN <20>BERTRAGUNG)
START_ZEILE.CLK = PIXEL_CLK;
START_ZEILE.ENA = LAST;
START_ZEILE = VVCNT[]==0; -- ZEILE 1
START_ZEILE = VVCNT[]==1; -- ZEILE 1
SYNC_PIX.CLK = PIXEL_CLK;
SYNC_PIX = VHCNT[]==3 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX1.CLK = PIXEL_CLK;

767
FPGA_by_Fredi/Video/Video.bdf
View File

@@ -6594,64 +6594,6 @@ applicable agreement for further details.
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)
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(text "wrreq" (rect 20 50 55 64)(font "Arial" (font_size 8)))
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(port
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(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
(text "aclr" (rect 20 114 41 128)(font "Arial" (font_size 8)))
(line (pt 0 120)(pt 16 120)(line_width 1))
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(port
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(text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
(text "q[127..0]" (rect 99 26 148 40)(font "Arial" (font_size 8)))
(line (pt 160 32)(pt 144 32)(line_width 3))
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(drawing
(text "(ack)" (rect 51 67 75 79)(font "Arial" ))
(text "128 bits x 512 words" (rect 58 116 159 128)(font "Arial" ))
(line (pt 16 16)(pt 144 16)(line_width 1))
(line (pt 144 16)(pt 144 128)(line_width 1))
(line (pt 144 128)(pt 16 128)(line_width 1))
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@@ -6726,253 +6668,144 @@ applicable agreement for further details.
(line (pt 22 120)(pt 16 126)(line_width 1))
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(rect 1664 1664 2016 2600)
(text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 5 170 19)(font "Arial" (font_size 8))) (text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 922 154 934)(font "Arial" )) (block_io "nRSTO" (input))
(block_io "MAIN_CLK" (input))
(block_io "nFB_CS1" (input))
(block_io "nFB_CS2" (input))
(block_io "nFB_CS3" (input))
(block_io "nFB_WR" (input))
(block_io "nFB_OE" (input))
(block_io "FB_SIZE0" (input))
(block_io "FB_SIZE1" (input))
(block_io "nFB_BURST" (input))
(block_io "FB_ADR[31..0]" (input))
(block_io "CLK33M" (input))
(block_io "CLK25M" (input))
(block_io "BLITTER_RUN" (input))
(block_io "CLK_VIDEO" (input))
(block_io "VR_D[8..0]" (input))
(block_io "VR_BUSY" (input))
(block_io "COLOR8" (output))
(block_io "ACP_CLUT_RD" (output))
(block_io "COLOR1" (output))
(block_io "FALCON_CLUT_RDH" (output))
(block_io "FALCON_CLUT_RDL" (output))
(block_io "FALCON_CLUT_WR[3..0]" (output))
(block_io "ST_CLUT_RD" (output))
(block_io "ST_CLUT_WR[1..0]" (output))
(block_io "CLUT_MUX_ADR[3..0]" (output))
(block_io "HSYNC" (output))
(block_io "VSYNC" (output))
(block_io "nBLANK" (output))
(block_io "nSYNC" (output))
(block_io "nPD_VGA" (output))
(block_io "FIFO_RDE" (output))
(block_io "COLOR2" (output))
(block_io "COLOR4" (output))
(block_io "PIXEL_CLK" (output))
(block_io "CLUT_OFF[3..0]" (output))
(block_io "BLITTER_ON" (output))
(block_io "VIDEO_RAM_CTR[15..0]" (output))
(block_io "VIDEO_MOD_TA" (output))
(block_io "CCR[23..0]" (output))
(block_io "CCSEL[2..0]" (output))
(block_io "ACP_CLUT_WR[3..0]" (output))
(block_io "INTER_ZEI" (output))
(block_io "DOP_FIFO_CLR" (output))
(block_io "VIDEO_RECONFIG" (output))
(block_io "VR_WR" (output))
(block_io "VR_RD" (output))
(block_io "CLR_FIFO" (output))
(block_io "FB_AD[31..0]" (bidir))
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(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
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(line (pt 16 90)(pt 22 96)(line_width 1))
(line (pt 22 96)(pt 16 102)(line_width 1))
)
)
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(rect 1856 1208 1920 1256)
(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
(text "inst99" (rect 3 37 32 49)(font "Arial" ))
(port
(pt 0 16)
(input)
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 14 16)(line_width 1))
)
(port
(pt 0 32)
(input)
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
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(line (pt 0 32)(pt 14 32)(line_width 1))
)
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(pt 64 24)
(output)
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)
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(line (pt 14 12)(pt 14 37)(line_width 1))
(arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)(line_width 1))
)
)
(block
(rect 296 1872 560 2536)
@@ -7300,6 +7133,259 @@ applicable agreement for further details.
(bidir)
)
)
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(rect 1664 1664 2016 2600)
(text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 5 170 19)(font "Arial" (font_size 8))) (text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 922 154 934)(font "Arial" )) (block_io "nRSTO" (input))
(block_io "MAIN_CLK" (input))
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(block_io "nFB_CS2" (input))
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(block_io "nFB_WR" (input))
(block_io "nFB_OE" (input))
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(block_io "CLK33M" (input))
(block_io "CLK25M" (input))
(block_io "BLITTER_RUN" (input))
(block_io "CLK_VIDEO" (input))
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(block_io "VR_BUSY" (input))
(block_io "COLOR8" (output))
(block_io "ACP_CLUT_RD" (output))
(block_io "COLOR1" (output))
(block_io "FALCON_CLUT_RDH" (output))
(block_io "FALCON_CLUT_RDL" (output))
(block_io "FALCON_CLUT_WR[3..0]" (output))
(block_io "ST_CLUT_RD" (output))
(block_io "ST_CLUT_WR[1..0]" (output))
(block_io "CLUT_MUX_ADR[3..0]" (output))
(block_io "HSYNC" (output))
(block_io "VSYNC" (output))
(block_io "nBLANK" (output))
(block_io "nSYNC" (output))
(block_io "nPD_VGA" (output))
(block_io "FIFO_RDE" (output))
(block_io "COLOR2" (output))
(block_io "COLOR4" (output))
(block_io "PIXEL_CLK" (output))
(block_io "CLUT_OFF[3..0]" (output))
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(block_io "VIDEO_RAM_CTR[15..0]" (output))
(block_io "VIDEO_MOD_TA" (output))
(block_io "CCR[23..0]" (output))
(block_io "CCSEL[2..0]" (output))
(block_io "ACP_CLUT_WR[3..0]" (output))
(block_io "INTER_ZEI" (output))
(block_io "DOP_FIFO_CLR" (output))
(block_io "VIDEO_RECONFIG" (output))
(block_io "VR_WR" (output))
(block_io "VR_RD" (output))
(block_io "CLR_FIFO" (output))
(block_io "DPZF_CLKENA" (output))
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(pt 352 72)
(bidir)
)
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(bidir)
)
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(bidir)
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(bidir)
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(bidir)
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(bidir)
)
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(bidir)
)
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(bidir)
)
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(pt 0 176)
(bidir)
)
(mapper
(pt 0 248)
(bidir)
)
(mapper
(pt 0 200)
(bidir)
)
(mapper
(pt 0 224)
(bidir)
)
(mapper
(pt 0 520)
(bidir)
)
(mapper
(pt 0 544)
(bidir)
)
(mapper
(pt 0 880)
(bidir)
)
(mapper
(pt 352 600)
(bidir)
)
(mapper
(pt 352 624)
(bidir)
)
(mapper
(pt 352 648)
(bidir)
)
(mapper
(pt 352 672)
(bidir)
)
(mapper
(pt 352 696)
(bidir)
)
(mapper
(pt 352 720)
(bidir)
)
(mapper
(pt 352 840)
(bidir)
)
(mapper
(pt 352 472)
(bidir)
)
(mapper
(pt 352 448)
(bidir)
)
(mapper
(pt 352 528)
(bidir)
)
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(pt 352 320)
(bidir)
)
(mapper
(pt 352 576)
(bidir)
)
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(pt 352 400)
(bidir)
)
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(pt 352 376)
(bidir)
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(pt 352 352)
(bidir)
)
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(pt 352 504)
(bidir)
)
(mapper
(pt 352 296)
(bidir)
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(pt 352 424)
(bidir)
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(pt 352 552)
(bidir)
)
(mapper
(pt 352 752)
(bidir)
)
(mapper
(pt 352 776)
(bidir)
)
(mapper
(pt 352 872)
(bidir)
)
(mapper
(pt 0 496)
(bidir)
)
(mapper
(pt 352 88)
(bidir)
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(pt 352 264)
(bidir)
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(pt 352 248)
(bidir)
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(bidir)
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(mapper
(pt 352 216)
(bidir)
)
(mapper
(pt 352 136)
(bidir)
)
(mapper
(pt 352 40)
(bidir)
)
(mapper
(pt 352 152)
(bidir)
)
(mapper
(pt 0 472)
(bidir)
)
(mapper
(pt 0 456)
(bidir)
)
(mapper
(pt 352 104)
(bidir)
)
(mapper
(pt 352 800)
(bidir)
)
)
(connector
(text "CLUT_ADR0" (rect 2786 1272 2849 1284)(font "Arial" ))
(pt 2776 1288)
@@ -8629,11 +8715,6 @@ applicable agreement for further details.
(pt 2512 1568)
(pt 2512 1728)
)
(connector
(text "PIXEL_CLK" (rect 1634 1432 1690 1444)(font "Arial" ))
(pt 1640 1448)
(pt 1712 1448)
)
(connector
(text "PIXEL_CLK" (rect 1938 1424 1994 1436)(font "Arial" ))
(pt 1928 1440)
@@ -10289,22 +10370,6 @@ applicable agreement for further details.
(pt 1800 1160)
(bus)
)
(connector
(pt 1608 1432)
(pt 1608 1232)
)
(connector
(pt 1600 1432)
(pt 1608 1432)
)
(connector
(pt 1608 1432)
(pt 1712 1432)
)
(connector
(pt 1608 1232)
(pt 2072 1232)
)
(connector
(pt 2072 1248)
(pt 1944 1248)
@@ -10591,6 +10656,57 @@ applicable agreement for further details.
(pt 848 2744)
(pt 928 2744)
)
(connector
(pt 1920 1232)
(pt 2072 1232)
)
(connector
(pt 1608 1432)
(pt 1608 1240)
)
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(pt 1608 1240)
(pt 1656 1240)
)
(connector
(pt 1624 1256)
(pt 1656 1256)
)
(connector
(pt 1624 1448)
(pt 1624 1256)
)
(connector
(pt 1600 1432)
(pt 1608 1432)
)
(connector
(pt 1608 1432)
(pt 1712 1432)
)
(connector
(pt 1608 1448)
(pt 1624 1448)
)
(connector
(text "PIXEL_CLK" (rect 1634 1432 1690 1444)(font "Arial" ))
(pt 1624 1448)
(pt 1712 1448)
)
(connector
(pt 1720 1240)
(pt 1856 1240)
)
(connector
(text "DPZF_CLKENA" (rect 1754 1208 1833 1220)(font "Arial" ))
(pt 1856 1224)
(pt 1744 1224)
)
(connector
(text "DPZF_CLKENA" (rect 2026 2448 2105 2460)(font "Arial" ))
(pt 2128 2464)
(pt 2016 2464)
)
(junction (pt 2984 1688))
(junction (pt 792 1192))
(junction (pt 792 1312))
@@ -10615,3 +10731,4 @@ applicable agreement for further details.
(junction (pt 3232 3024))
(junction (pt 1968 1424))
(junction (pt 1608 1432))
(junction (pt 1624 1448))

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FPGA_by_Fredi/Video/altdpram0_wave0.jpg
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16
FPGA_by_Fredi/Video/altdpram0_waveforms.html
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@@ -1,16 +0,0 @@
<html>
<head>
<title>Sample Waveforms for altdpram0.vhd </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file altdpram0.vhd </CENTER></h2>
<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram0.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 7, 6, 5, 4, ...). The design altdpram0.vhd has two read/write ports. Read/write port A has 16 words of 3 bits each and Read/write port B has 16 words of 3 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
<CENTER><img src=altdpram0_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
<CENTER><img src=altdpram0_wave1.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
<P></P>
</body>
</html>

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FPGA_by_Fredi/Video/altdpram1_waveforms.html
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@@ -1,16 +0,0 @@
<html>
<head>
<title>Sample Waveforms for altdpram1.vhd </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file altdpram1.vhd </CENTER></h2>
<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram1.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 0F, 0E, 0D, 0C, ...). The design altdpram1.vhd has two read/write ports. Read/write port A has 256 words of 6 bits each and Read/write port B has 256 words of 6 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
<CENTER><img src=altdpram1_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
<CENTER><img src=altdpram1_wave1.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
<P></P>
</body>
</html>

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FPGA_by_Fredi/Video/altdpram2_wave0.jpg
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FPGA_by_Fredi/Video/altdpram2_waveforms.html
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@@ -1,16 +0,0 @@
<html>
<head>
<title>Sample Waveforms for altdpram2.vhd </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file altdpram2.vhd </CENTER></h2>
<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram2.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( F0, F1, F2, F3, ...). The design altdpram2.vhd has two read/write ports. Read/write port A has 256 words of 8 bits each and Read/write port B has 256 words of 8 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
<CENTER><img src=altdpram2_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
<CENTER><img src=altdpram2_wave1.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
<P></P>
</body>
</html>

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FPGA_by_Fredi/Video/lpm_compare1_waveforms.html
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@@ -1,13 +0,0 @@
<html>
<head>
<title>Sample Waveforms for lpm_compare1.vhd </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file lpm_compare1.vhd </CENTER></h2>
<P>The following waveforms show the behavior of lpm_comparator megafunction for the chosen set of parameters in design lpm_compare1.vhd. The design lpm_compare1.vhd is 11 bit UNSIGNED comparator. </P>
<CENTER><img src=lpm_compare1_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing comparator operation. </CENTER></P>
<P><FONT size=3></P>
<P></P>
</body>
</html>

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FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html
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@@ -1,13 +0,0 @@
<html>
<head>
<title>Sample Waveforms for "lpm_fifoDZ.vhd" </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file "lpm_fifoDZ.vhd" </CENTER></h2>
<P>The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design "lpm_fifoDZ.vhd". The design "lpm_fifoDZ.vhd" has a depth of 512 words of 128 bits each. The fifo is in show-ahead synchronous mode. The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge. </P>
<CENTER><img src=lpm_fifoDZ_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P>
<P></P>
</body>
</html>

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FPGA_by_Fredi/Video/lpm_fifo_dc0_waveforms.html
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@@ -1,13 +0,0 @@
<html>
<head>
<title>Sample Waveforms for "lpm_fifo_dc0.vhd" </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file "lpm_fifo_dc0.vhd" </CENTER></h2>
<P>The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design "lpm_fifo_dc0.vhd". The design "lpm_fifo_dc0.vhd" has a depth of 2048 words of 128 bits each. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request. </P>
<CENTER><img src=lpm_fifo_dc0_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P>
<P></P>
</body>
</html>

56
FPGA_by_Fredi/Video/shiftreg_dpz.bsf Normal file
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@@ -0,0 +1,56 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 144 80)
(text "shiftreg_dpz" (rect 37 1 119 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 64 25 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 144 48)
(output)
(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8)))
(line (pt 144 48)(pt 128 48)(line_width 1))
)
(drawing
(text "right shift" (rect 88 17 128 29)(font "Arial" ))
(line (pt 16 16)(pt 128 16)(line_width 1))
(line (pt 128 16)(pt 128 64)(line_width 1))
(line (pt 128 64)(pt 16 64)(line_width 1))
(line (pt 16 64)(pt 16 16)(line_width 1))
(line (pt 16 26)(pt 22 32)(line_width 1))
(line (pt 22 32)(pt 16 38)(line_width 1))
)
)

24
FPGA_by_Fredi/Video/shiftreg_dpz.inc Normal file
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@@ -0,0 +1,24 @@
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION shiftreg_dpz
(
clock,
shiftin
)
RETURNS (
shiftout
);

8
FPGA_by_Fredi/Video/lpm_fifoDZ.qip → FPGA_by_Fredi/Video/shiftreg_dpz.qip
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@@ -1,5 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+"
set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.cmp"]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "shiftreg_dpz.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "shiftreg_dpz.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "shiftreg_dpz.inc"]

125
FPGA_by_Fredi/Video/shiftreg_dpz.vhd Normal file
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@@ -0,0 +1,125 @@
-- megafunction wizard: %LPM_SHIFTREG%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_shiftreg
-- ============================================================
-- File Name: shiftreg_dpz.vhd
-- Megafunction Name(s):
-- lpm_shiftreg
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY shiftreg_dpz IS
PORT
(
clock : IN STD_LOGIC ;
shiftin : IN STD_LOGIC ;
shiftout : OUT STD_LOGIC
);
END shiftreg_dpz;
ARCHITECTURE SYN OF shiftreg_dpz IS
SIGNAL sub_wire0 : STD_LOGIC ;
COMPONENT lpm_shiftreg
GENERIC (
lpm_direction : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
shiftout : OUT STD_LOGIC ;
shiftin : IN STD_LOGIC
);
END COMPONENT;
BEGIN
shiftout <= sub_wire0;
lpm_shiftreg_component : lpm_shiftreg
GENERIC MAP (
lpm_direction => "RIGHT",
lpm_type => "LPM_SHIFTREG",
lpm_width => 3
)
PORT MAP (
clock => clock,
shiftin => shiftin,
shiftout => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LeftShift NUMERIC "0"
-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "3"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "3"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_dpz.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_dpz.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_dpz.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_dpz.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_dpz_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

532
FPGA_by_Fredi/blitter.tdf
View File

@@ -23,6 +23,8 @@ INCLUDE "lpm_bustri_WORD.inc";
INCLUDE "VIDEO/BLITTER/lpm_clshift384.INC";
INCLUDE "VIDEO/BLITTER/altsyncram0.INC";
INCLUDE "VIDEO/BLITTER/lpm_clshift144.inc";
INCLUDE "VIDEO/BLITTER/lpm_ror128.inc";
--CONSTANT BL_SKEW_LF = 255;
@@ -71,66 +73,70 @@ SUBDESIGN BLITTER
VARIABLE
BYT :NODE;
LONGLINE :NODE;
W_ADR[18..0] :NODE;
FB_16B[1..0] :NODE;
W_A1 :DFFE;
BLITTER_CS :NODE;
BL_HRAM_CS :NODE;
DP_RAM_CS :NODE;
BL_HRAM_BE[1..0] :NODE;
BL_HRAM_OUT[15..0] :NODE;
BL_DPRAM_OUT[15..0] :NODE;
BL_SRC_X_INC_CS :NODE;
BL_SRC_X_INC[15..0] :DFFE;
SRC_XINC_NODE[31..0] :NODE;
SRC_ADR_INC[31..0] :NODE;
SRC_XINC32[31..0] :NODE;
BL_SRC_Y_INC_CS :NODE;
BL_SRC_Y_INC[15..0] :DFFE;
SRC_YINC_NODE[31..0] :NODE;
SRC_YINC32[31..0] :NODE;
BL_ENDMASK1_CS :NODE;
BL_ENDMASK1[15..0] :DFFE;
BL_ENDMASK2_CS :NODE;
BL_ENDMASK2[15..0] :DFFE;
BL_ENDMASK3_CS :NODE;
BL_ENDMASK3[15..0] :DFFE;
BL_ENDMASK0[15..0] :NODE;
BL_ENDMASKF[15..0] :NODE;
BL_ENDMASKL[15..0] :NODE;
BL_ENDMASKR[15..0] :NODE;
BL_SRC_ADRH_CS :NODE;
BL_SRC_ADRL_CS :NODE;
BL_SRC_ADR[31..0] :DFFE;
SRC_OLD[27..0] :DFFE;
SRC_IADRH_CS :NODE;
SRC_IADRL_CS :NODE;
SRC_IADR[31..0] :DFF;
SRC_IADR_CLR :NODE;
SIINC :NODE;
SRC_ADR_NODE[31..0] :NODE;
SRC_IADR_CLR :DFF;
SRC_ADR32[31..0] :NODE;
BL_DST_X_INC_CS :NODE;
BL_DST_X_INC[15..0] :DFFE;
DST_XINC_NODE[31..0] :NODE;
DST_ADR_INC[31..0] :NODE;
DST_XINC32[31..0] :NODE;
BL_DST_Y_INC_CS :NODE;
BL_DST_Y_INC[15..0] :DFFE;
DST_YINC_NODE[31..0] :NODE;
DST_YINC32[31..0] :NODE;
BL_DST_ADRH_CS :NODE;
BL_DST_ADRL_CS :NODE;
BL_DST_ADR[31..0] :DFFE;
DST_IADRH_CS :NODE;
DST_IADRL_CS :NODE;
DST_IADR[31..0] :DFF;
DST_IADR_CLR :NODE;
DST_ADR_NODE[31..0] :NODE;
DIINC :NODE;
DST_IADR_CLR :DFF;
DST_ADR32[31..0] :NODE;
BL_X_CNT_CS :NODE;
BL_X_CNT[15..0] :DFFE;
X_CNT_NODE[15..0] :NODE;
X_CNT16[15..0] :NODE;
BL_Y_CNT_CS :NODE;
BL_Y_CNT[15..0] :DFFE;
BL_HOP_CS :NODE;
BL_HOP[7..0] :DFFE;
BL_OP[7..0] :DFFE;
BL_LN_CS :NODE;
LN7CLR :NODE;
BL_LN_WR :NODE;
LN7_CLR :NODE;
BL_LN[7..0] :DFFE;
BL_SKEW[7..0] :DFFE;
-- barell shifter
DIST_RIGHT[8..0] :NODE;
BL_BS_SKEW[7..0] :NODE;
BS_SKEW[7..0] :NODE;
BL_BSIN[383..0] :NODE;
BL_BSOUT[383..0] :NODE;
SHIFT_DIR :NODE;
@@ -145,15 +151,17 @@ VARIABLE
WREN_B :NODE; -- WR ENA HALFTONE RAM
X_INDEX_CS :NODE;
X_INDEX[15..0] :DFF; -- LAUFZEIGER X COUNT
X_INDEX_CLR :NODE;
X_INDEX_CLR :DFF; -- X INDEX L<>SCHEN CPU WRITE
X_INDEX_CLR_DIR :NODE; -- X INDEX L<>SCHEN STATE MACHINE
DST_X_INC[15..0] :NODE; -- ANZAHL WORTE PRO DURCHLAUF
X_CNT_T[15..0] :NODE;
Y_INDEX_CS :NODE;
Y_INDEX[15..0] :DFF; -- LAUFZEIGER Y COUNT
Y_INDEX_CLR :NODE;
Y_INDEX_CLR :DFF;
LINE_NR[3..0] :NODE;
XIINC :NODE; -- INC INDEX SPALTE
SDXINC :DFF; -- INC INDEX SPALTE
YIINC :NODE; -- INC INDEX ZEILE
ZIINC :NODE; -- INC ADRESSEN ZEILENUMBRUCH
ZYINC :NODE; -- KORREKTUR ADRESSEN WENN FERTIG
ZAINC :NODE; -- INC ADRESSEN ZEILENUMBRUCH
HOP_OUT[127..0] :NODE;
OP_OUT[127..0] :NODE;
ENDMASK1_SHIFT[7..0] :NODE;
@@ -162,24 +170,22 @@ VARIABLE
ENDMASK12_OUT[143..0] :NODE;
ENDMASK23_IN[143..0] :NODE;
ENDMASK23_OUT[143..0] :NODE;
ENDMASK123[127..0] :NODE;
ENDMASKEND[15..0] :NODE;
SRC_DDR_ADR[31..0] :NODE;
DST_DDR_ADR[31..0] :NODE;
BLITTER_REQ :DFF;
ENDMASKM_IN[127..0] :NODE;
ENDMASKM_OUT[127..0] :NODE;
ROR_CNT[8..0] :NODE;
ENDMASK123[127..0] :DFF;
ENDMASKEND[31..0] :NODE;
BLITTER_SIG :DFF;
BLITTER_REQ :NODE;
BL_START :DFF;
BL_NOTRUN :NODE;
-- MAIN STATE MACHINE
BL_SM :MACHINE WITH STATES(START,NEW_LINE,NEW_LINEW,RDSRC0,RDSRC1,RDSRC2,RDDST,WRDSTW1,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG);
BL_SM :MACHINE WITH STATES(START,NEW_LINE,RDSRC3,RDSRC2,RDSRC1,RDDST,WRDSTW,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG);
BEGIN
-- BYT UND WORD SELECT 16 BIT
BYT = !FB_SIZE1 & FB_SIZE0;
LONGLINE = !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG OR LINE
W_A1.CLK = MAIN_CLK;
W_A1.ENA = FB_ALE # BLITTER_TA & LONGLINE;
W_A1 = FB_ADR[1] & FB_ALE # BLITTER_TA & LONGLINE; -- A1 HOCHZ<48>HLEN BEI LONG UND LINE WEGEN BURST
W_ADR[18..1] = FB_ADR[19..2];
W_ADR0 = W_A1;
FB_16B0 = FB_ADR[0]==0; -- wenn ADR==0
FB_16B1 = FB_ADR[0]==1 # !BYT; -- wenn ADR==1 or NOT BYT
-- BLITTER CS
@@ -191,156 +197,229 @@ BEGIN
BL_HRAM_BE1 = BL_HRAM_CS & FB_16B0;
BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1;
WREN_B = B"0";
LINE_NR[] = ((Y_INDEX[3..0] & !BL_DST_Y_INC15) # (!Y_INDEX[3..0] & BL_DST_Y_INC15));
(BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(W_ADR[3..0],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B);
LINE_NR[] = BL_LN[3..0] + ((Y_INDEX[3..0] & !BL_DST_X_INC15) - (Y_INDEX[3..0] & BL_DST_X_INC15));
(BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(FB_ADR[4..1],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B);
DP_RAM_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C528"; -- $F8A50.w
-- SRC X INC
BL_SRC_X_INC[].CLK = MAIN_CLK;
BL_SRC_X_INC[] = FB_AD[31..16];
BL_SRC_X_INC_CS = !nFB_CS1 & W_ADR[]==H"7C510"; -- $F8A20.w
BL_SRC_X_INC[15..1] = FB_AD[31..17];
BL_SRC_X_INC0 = GND;
BL_SRC_X_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C510"); -- $F8A20.w
BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_X_INC[7..0].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
SRC_XINC_NODE[] = (H"FFFF0000" & BL_SRC_X_INC15) # (H"0000",BL_SRC_X_INC[]); -- ERWEITERN AUF 32 BIT
SRC_XINC32[15..0] = BL_SRC_X_INC[]; -- ERWEITERN AUF 32 BIT
SRC_XINC32[31..16] = H"FFFF" & BL_SRC_X_INC15; -- ERWEITERN AUF 32 BIT
-- SRC Y INC
BL_SRC_Y_INC[].CLK = MAIN_CLK;
BL_SRC_Y_INC[] = FB_AD[31..16];
BL_SRC_Y_INC_CS = !nFB_CS1 & W_ADR[]==H"7C511"; -- $F8A22.w
BL_SRC_Y_INC[15..1] = FB_AD[31..17];
BL_SRC_Y_INC0 = GND;
BL_SRC_Y_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C511"); -- $F8A22.w
BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_Y_INC[7..0].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
SRC_YINC_NODE[] = (H"FFFF0000" & BL_SRC_Y_INC15) # (H"0000",BL_SRC_Y_INC[]); -- ERWEITERN AUF 32 BIT
SRC_YINC32[15..0] = BL_SRC_Y_INC[]; -- ERWEITERN AUF 32 BIT
SRC_YINC32[31..16] = H"FFFF" & BL_SRC_Y_INC15; -- ERWEITERN AUF 32 BIT
-- SRC ADR HIGH
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[31..16] = FB_AD[31..16];
BL_SRC_ADRH_CS = !nFB_CS1 & W_ADR[]==H"7C512"; -- $F8A24.w
BL_SRC_ADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C512"); -- $F8A24.w
BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
-- SRC ADR LOW
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[15..0] = FB_AD[31..16];
BL_SRC_ADRL_CS = !nFB_CS1 & W_ADR[]==H"7C513"; -- $F8A26.w
BL_SRC_ADR[15..1] = FB_AD[31..17];
BL_SRC_ADR0 = GND;
BL_SRC_ADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C513"); -- $F8A26.w
BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[7..0].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
SRC_IADR[].CLK = DDRCLK0;
SRC_IADRH_CS = !nFB_CS1 & W_ADR[]==H"7C520"; -- $F8A40.w
SRC_IADRL_CS = !nFB_CS1 & W_ADR[]==H"7C521"; -- $F8A42.w
SRC_IADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C520"); -- $F8A40.w
SRC_IADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C521"); -- $F8A42.w
SRC_IADR_CLR.CLK = MAIN_CLK;
SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR; -- L<>SCHEN BEI WRITE
SRC_IADR[] = (SRC_IADR[] + (((8 * SRC_XINC_NODE[]) & SIINC) + (SRC_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[]) - 8) * SRC_XINC_NODE[]) & ZIINC)) & SRC_READ) & !SRC_IADR_CLR;
SRC_ADR_NODE[] = BL_SRC_ADR[] + SRC_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH
SRC_IADR[] = (((SRC_IADR[] + (SRC_ADR_INC[] & SDXINC)) & !ZAINC) + ((((((0,BL_X_CNT[]) - 1) * SRC_XINC32[]) + SRC_YINC32[]) * (0,Y_INDEX[])) & ZAINC)) & SRC_READ & !SRC_IADR_CLR;
SRC_ADR32[] = BL_SRC_ADR[] + SRC_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH
-- ENDMASK 1
BL_ENDMASK1[].CLK = MAIN_CLK;
BL_ENDMASK1[] = FB_AD[31..16];
BL_ENDMASK1_CS = !nFB_CS1 & W_ADR[]==H"7C514"; -- $F8A28.w
BL_ENDMASK1_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C514"); -- $F8A28.w
BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
BL_ENDMASK1[7..0].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
-- ENDMASK 2
BL_ENDMASK2[].CLK = MAIN_CLK;
BL_ENDMASK2[] = FB_AD[31..16];
BL_ENDMASK2_CS = !nFB_CS1 & W_ADR[]==H"7C515"; -- $F8A2A.w
BL_ENDMASK2_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C515"); -- $F8A2A.w
BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
BL_ENDMASK2[7..0].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
-- ENDMASK 3
BL_ENDMASK3[].CLK = MAIN_CLK;
BL_ENDMASK3[] = FB_AD[31..16];
BL_ENDMASK3_CS = !nFB_CS1 & W_ADR[]==H"7C516"; -- $F8A2C.w
BL_ENDMASK3_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C516"); -- $F8A2C.w
BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
BL_ENDMASK3[7..0].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
-- DST X INC
BL_DST_X_INC[].CLK = MAIN_CLK;
BL_DST_X_INC[] = FB_AD[31..16];
BL_DST_X_INC_CS = !nFB_CS1 & W_ADR[]==H"7C517"; -- $F8A2E.w
BL_DST_X_INC[15..1] = FB_AD[31..17];
BL_DST_X_INC0 = GND;
BL_DST_X_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C517"); -- $F8A2E.w
BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
BL_DST_X_INC[7..0].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
DST_XINC_NODE[] = (H"FFFF0000" & BL_DST_X_INC15) # (H"0000",BL_DST_X_INC[]); -- ERWEITERN AUF 32 BIT
DST_XINC32[15..0] = BL_DST_X_INC[]; -- ERWEITERN AUF 32 BIT
DST_XINC32[31..16] = H"FFFF" & BL_DST_X_INC15; -- ERWEITERN AUF 32 BIT
-- DST Y INC
BL_DST_Y_INC[].CLK = MAIN_CLK;
BL_DST_Y_INC[] = FB_AD[31..16];
BL_DST_Y_INC_CS = !nFB_CS1 & W_ADR[]==H"7C518"; -- $F8A30.w
BL_DST_Y_INC[15..1] = FB_AD[31..17];
BL_DST_Y_INC0 = GND;
BL_DST_Y_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C518"); -- $F8A30.w
BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
BL_DST_Y_INC[7..0].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
DST_YINC_NODE[] = (H"FFFF0000" & BL_DST_Y_INC15) # (H"0000",BL_DST_Y_INC[]); -- ERWEITERN AUF 32 BIT
DST_YINC32[15..0] = BL_DST_Y_INC[]; -- ERWEITERN AUF 32 BIT
DST_YINC32[31..16] = H"FFFF" & BL_DST_Y_INC15; -- ERWEITERN AUF 32 BIT
-- DST ADR HIGH
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[31..16] = FB_AD[31..16];
BL_DST_ADRH_CS = !nFB_CS1 & W_ADR[]==H"7C519"; -- $F8A32.w
BL_DST_ADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C519"); -- $F8A32.w
BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
-- DST ADR LOW
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[15..0] = FB_AD[31..16];
BL_DST_ADRL_CS = !nFB_CS1 & W_ADR[]==H"7C51A"; -- $F8A34.w
BL_DST_ADR[15..1] = FB_AD[31..17];
BL_DST_ADR0 = GND;
BL_DST_ADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C51A"); -- $F8A34.w
BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[7..0].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
DST_IADR[].CLK = DDRCLK0;
DST_IADRH_CS = !nFB_CS1 & W_ADR[]==H"7C522"; -- $F8A44.w
DST_IADRL_CS = !nFB_CS1 & W_ADR[]==H"7C523"; -- $F8A46.w
DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR; -- L<>SCHEN BEI WRITE
DST_IADR[] = (DST_IADR[] + ((8 * DST_XINC_NODE[]) & DIINC) + (DST_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[])) * DST_XINC_NODE[]) & ZIINC)) & !DST_IADR_CLR;
DST_ADR_NODE[] = BL_DST_ADR[] + DST_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH
DST_IADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C522"); -- $F8A44.w
DST_IADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C523"); -- $F8A46.w
DST_IADR_CLR.CLK = MAIN_CLK;
DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR; -- L<>SCHEN BEI WRITE
DST_IADR[] = (((DST_IADR[] + (DST_ADR_INC[] & SDXINC)) & !ZAINC) + ((((((0,BL_X_CNT[]) - 1) * DST_XINC32[]) + DST_YINC32[]) * (0,Y_INDEX[])) & ZAINC)) & !DST_IADR_CLR;
DST_ADR32[] = BL_DST_ADR[] + DST_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH
-- X COUNT
BL_X_CNT[].CLK = MAIN_CLK;
BL_X_CNT[] = FB_AD[31..16];
BL_X_CNT_CS = !nFB_CS1 & W_ADR[]==H"7C51B"; -- $F8A36.w
BL_X_CNT_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C51B"); -- $F8A36.w
BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
BL_X_CNT[7..0].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B1;
X_INDEX[].CLK = DDRCLK0;
X_INDEX_CS = !nFB_CS1 & W_ADR[]==H"7C524"; -- $F8A48.w
X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR; -- L<>SCHEN BEI WRITE
X_INDEX[] = (X_INDEX[] + (8 & XIINC) + ((BL_X_CNT[] - X_INDEX[]) & ZIINC)) & !X_INDEX_CLR;
X_CNT_NODE[] = X_INDEX[] - ((0,DST_ADR_NODE[3..1]) & (X_INDEX[]!=0));-- EFFEKTIV GELESENE
X_INDEX_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C524"); -- $F8A48.w
X_INDEX_CLR.CLK = MAIN_CLK;
X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR; -- L<>SCHEN BEI WRITE
X_INDEX[] = ((X_INDEX[] & !ZAINC) + (DST_X_INC[] & SDXINC) + (BL_X_CNT[] & ZAINC)) & !X_INDEX_CLR & !X_INDEX_CLR_DIR;
X_CNT16[] = X_INDEX[] - (X_CNT_T[] & (X_INDEX[]!=0)); -- EFFEKTIV geschrieben
-- SCHRITTWEITEN BEI PALLETTENMOD
IF (BL_SRC_X_INC[] != BL_DST_X_INC[]) # (BL_X_CNT[] < 4) THEN
DST_X_INC[] = 1;
X_CNT_T[] = 0;
SRC_ADR_INC[] = SRC_XINC32[]; -- SRC X INC
DST_ADR_INC[] = DST_XINC32[]; -- DST X INC
ELSE
IF BL_SRC_X_INC[] == H"0002" THEN
DST_X_INC[] = 8;
X_CNT_T[] = (0,DST_ADR32[3..1]);
SRC_ADR_INC[] = 16; -- SRC X INC
DST_ADR_INC[] = 16; -- DST X INC
ELSE
IF BL_SRC_X_INC[] == H"FFFE" THEN
DST_X_INC[] = 8;
X_CNT_T[] = 7 - (0,DST_ADR32[3..1]);
SRC_ADR_INC[] = -16; -- SRC X INC
DST_ADR_INC[] = -16; -- DST X INC
ELSE
IF BL_SRC_X_INC[] == H"0004" THEN
DST_X_INC[] = 4;
X_CNT_T[] = (0,DST_ADR32[3..2]);
SRC_ADR_INC[] = 16; -- SRC X INC
DST_ADR_INC[] = 16; -- DST X INC
ELSE
IF BL_SRC_X_INC[] == H"FFFC" THEN
DST_X_INC[] = 4;
X_CNT_T[] = 3 - (0,DST_ADR32[3..2]);
SRC_ADR_INC[] = -16; -- SRC X INC
DST_ADR_INC[] = -16; -- DST X INC
ELSE
IF BL_SRC_X_INC[] == H"0008" THEN
DST_X_INC[] = 2;
X_CNT_T[] = (0,DST_ADR32[3]);
SRC_ADR_INC[] = 16; -- SRC X INC
DST_ADR_INC[] = 16; -- DST X INC
ELSE
IF BL_SRC_X_INC[] == H"FFF8" THEN
DST_X_INC[] = 2;
X_CNT_T[] = 1 - (0,DST_ADR32[3]);
SRC_ADR_INC[] = -16; -- SRC X INC
DST_ADR_INC[] = -16; -- DST X INC
ELSE
DST_X_INC[] = 1;
X_CNT_T[] = 0;
SRC_ADR_INC[] = SRC_XINC32[]; -- SRC X INC
DST_ADR_INC[] = DST_XINC32[]; -- DST X INC
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
-- Y COUNT
BL_Y_CNT[].CLK = MAIN_CLK;
BL_Y_CNT[] = FB_AD[31..16];
BL_Y_CNT_CS = !nFB_CS1 & W_ADR[]==H"7C51C"; -- $F8A38.w
BL_Y_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51C"; -- $F8A38.w
BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
BL_Y_CNT[7..0].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
Y_INDEX[].CLK = DDRCLK0;
Y_INDEX_CS = !nFB_CS1 & W_ADR[]==H"7C525"; -- $F8A4A.w
Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR; -- L<>SCHEN BEI WRITE
Y_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C525"; -- $F8A4A.w
Y_INDEX_CLR.CLK = MAIN_CLK;
Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR; -- L<>SCHEN BEI WRITE
Y_INDEX[] = (Y_INDEX[] + (1 & YIINC)) & !Y_INDEX_CLR;
-- HOP LOGIC
BL_HOP[].CLK = MAIN_CLK;
BL_HOP[] = FB_AD[31..24];
BL_HOP_CS = !nFB_CS1 & W_ADR[]==H"7C51D"; -- $F8A3A.w
BL_HOP[7..0].ENA = BL_HOP_CS & !nFB_WR & FB_16B0; -- $F8A3A
BL_HOP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51D"; -- $F8A3A.w
BL_HOP[7..0].ENA = BL_HOP_CS & !nFB_WR & FB_16B0; -- $F8A3A
-- OP LOGIC
BL_OP[].CLK = MAIN_CLK;
BL_OP[] = FB_AD[23..16];
BL_OP[7..0].ENA = BL_HOP_CS & !nFB_WR & FB_16B1; -- $F8A3B
BL_OP[7..0].ENA = BL_HOP_CS & !nFB_WR & FB_16B1; -- $F8A3B
-- LINE NUMBER BYT
BL_LN[].CLK = MAIN_CLK;
BL_LN[6..0] = FB_AD[30..24];
BL_LN7 = FB_AD31 & !LN7CLR; -- BUSY HOG UND SMUDGE
BL_LN_CS = !nFB_CS1 & W_ADR[]==H"7C51E"; -- $F8A3C.w
BL_LN[].ENA = BL_LN_CS & !nFB_WR & FB_16B0; -- $F8A3C
BL_LN7.ENA = LN7CLR;
BL_LN_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C51E"); -- $F8A3C.w
BL_LN_WR = BL_LN_CS & !nFB_WR & FB_16B0; -- $F8A3C WRITE SIGNAL
BL_LN[6..0] = FB_AD[30..24]; -- HOG UND SMUDGE
BL_LN[6..0].ENA = BL_LN_WR; -- $F8A3C
BL_LN7.ENA = BL_LN_WR # LN7_CLR; -- $F8A3C
BL_LN7 = FB_AD31 & BLITTER_ON & (BL_X_CNT[] > X_CNT16[]) & (BL_Y_CNT[] > Y_INDEX[]) & !LN7_CLR; -- BUSY
BL_START.CLK = MAIN_CLK;
BL_START = BL_LN7 & !BL_LN_CS & BLITTER_ON & (BL_X_CNT[] > X_CNT16[]) & (BL_Y_CNT[] > Y_INDEX[]) & !LN7_CLR;
-- SKEW BYT
BL_SKEW[].CLK = MAIN_CLK;
BL_SKEW[] = FB_AD[23..16];
BL_SKEW[].ENA = BL_LN_CS & !nFB_WR & FB_16B1; -- $F8A3D
BL_SKEW[].ENA = BL_LN_CS & !nFB_WR & FB_16B1; -- $F8A3D
--- REGISTER OUT
FB_AD[31..16] = lpm_bustri_WORD(
BL_HRAM_CS & BL_DPRAM_OUT[]
# BL_SRC_X_INC_CS & BL_SRC_X_INC[]
# BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
# BL_SRC_ADRH_CS & SRC_ADR_NODE[31..16]
# BL_SRC_ADRL_CS & SRC_ADR_NODE[15..0]
# BL_SRC_ADRH_CS & SRC_ADR32[31..16]
# BL_SRC_ADRL_CS & SRC_ADR32[15..0]
# BL_ENDMASK1_CS & BL_ENDMASK1[]
# BL_ENDMASK2_CS & BL_ENDMASK2[]
# BL_ENDMASK3_CS & BL_ENDMASK3[]
# BL_DST_X_INC_CS & BL_DST_X_INC[]
# BL_DST_Y_INC_CS & BL_DST_Y_INC[]
# BL_DST_ADRH_CS & DST_ADR_NODE[31..16]
# BL_DST_ADRL_CS & DST_ADR_NODE[15..0]
# BL_DST_ADRH_CS & DST_ADR32[31..16]
# BL_DST_ADRL_CS & DST_ADR32[15..0]
# BL_X_CNT_CS & (BL_X_CNT[]-X_INDEX[])
# BL_Y_CNT_CS & (BL_Y_CNT[]-Y_INDEX[])
# BL_HOP_CS & (BL_HOP[],BL_OP[])
# BL_LN_CS & (BL_LN[7..4],Y_INDEX[3..0],BL_SKEW[])
# BL_LN_CS & (BL_LN7 # !BL_NOTRUN,BL_LN[6..0],BL_SKEW[])
# SRC_IADRH_CS & SRC_IADR[31..16]
# SRC_IADRL_CS & SRC_IADR[15..0]
# DST_IADRH_CS & DST_IADR[31..16]
# DST_IADRL_CS & DST_IADR[15..0]
# X_INDEX_CS & X_INDEX[]
# Y_INDEX_CS & Y_INDEX[]
,BLITTER_CS & !nFB_OE); -- FFFF8A00-7F
# DP_RAM_CS & BL_HRAM_OUT[]
,BLITTER_CS & !nFB_OE); -- FFFF8A00-7F
--------------------------------------------------------------------------------------
-- SRC BUFFER LADEN
BL_SRC_BUF1[].CLK = DDRCLK0;
@@ -355,34 +434,11 @@ BEGIN
BL_SRC_BUF3[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC;
BL_SRC_BUF3[63..0].ENA = BLITTER_DACK0 & BL_READ_SRC;
BL_SRC_BUF3[] = BL_SRC_BUF2[];
-- ZUORDNUNG ---------
-- ZUORDNUNG ---------------------------------------------------
IF BL_SRC_X_INC15 THEN -- WENN NEGATIV -> REIHENFOLGE KEHREN
CASE BL_HOP[7..4] IS -- SPIEGELN?
WHEN H"0" => -- LINE WEISE
BL_BSIN[127..0] = BL_SRC_BUF3[];
BL_BSIN[255..128] = BL_SRC_BUF2[];
BL_BSIN[383..256] = BL_SRC_BUF1[];
WHEN H"1" => --- BIT WEISE
BL_BSIN[0..127] = BL_SRC_BUF3[];
BL_BSIN[128..255] = BL_SRC_BUF2[];
BL_BSIN[256..383] = BL_SRC_BUF1[];
WHEN H"2" => -- BYT WEISE
BL_BSIN[127..0] = (BL_SRC_BUF3[7..0],BL_SRC_BUF3[15..8],BL_SRC_BUF3[23..16],BL_SRC_BUF3[31..24],BL_SRC_BUF3[39..32],BL_SRC_BUF3[47..40],BL_SRC_BUF3[55..48],BL_SRC_BUF3[63..56],BL_SRC_BUF3[71..64],BL_SRC_BUF3[79..72],BL_SRC_BUF3[87..80],BL_SRC_BUF3[95..88],BL_SRC_BUF3[103..96],BL_SRC_BUF3[111..104],BL_SRC_BUF3[119..112],BL_SRC_BUF3[127..120]);
BL_BSIN[255..128] = (BL_SRC_BUF2[7..0],BL_SRC_BUF2[15..8],BL_SRC_BUF2[23..16],BL_SRC_BUF2[31..24],BL_SRC_BUF2[39..32],BL_SRC_BUF2[47..40],BL_SRC_BUF2[55..48],BL_SRC_BUF2[63..56],BL_SRC_BUF2[71..64],BL_SRC_BUF2[79..72],BL_SRC_BUF2[87..80],BL_SRC_BUF2[95..88],BL_SRC_BUF2[103..96],BL_SRC_BUF2[111..104],BL_SRC_BUF2[119..112],BL_SRC_BUF2[127..120]);
BL_BSIN[383..256] = (BL_SRC_BUF1[7..0],BL_SRC_BUF1[15..8],BL_SRC_BUF1[23..16],BL_SRC_BUF1[31..24],BL_SRC_BUF1[39..32],BL_SRC_BUF1[47..40],BL_SRC_BUF1[55..48],BL_SRC_BUF1[63..56],BL_SRC_BUF1[71..64],BL_SRC_BUF1[79..72],BL_SRC_BUF1[87..80],BL_SRC_BUF1[95..88],BL_SRC_BUF1[103..96],BL_SRC_BUF1[111..104],BL_SRC_BUF1[119..112],BL_SRC_BUF1[127..120]);
WHEN H"3" => -- WORD WEISE
BL_BSIN[127..0] = (BL_SRC_BUF3[15..0],BL_SRC_BUF3[31..16],BL_SRC_BUF3[47..32],BL_SRC_BUF3[63..48],BL_SRC_BUF3[79..64],BL_SRC_BUF3[95..80],BL_SRC_BUF3[111..96],BL_SRC_BUF3[127..112]);
BL_BSIN[255..128] = (BL_SRC_BUF2[15..0],BL_SRC_BUF2[31..16],BL_SRC_BUF2[47..32],BL_SRC_BUF2[63..48],BL_SRC_BUF2[79..64],BL_SRC_BUF2[95..80],BL_SRC_BUF2[111..96],BL_SRC_BUF2[127..112]);
BL_BSIN[383..256] = (BL_SRC_BUF1[15..0],BL_SRC_BUF1[31..16],BL_SRC_BUF1[47..32],BL_SRC_BUF1[63..48],BL_SRC_BUF1[79..64],BL_SRC_BUF1[95..80],BL_SRC_BUF1[111..96],BL_SRC_BUF1[127..112]);
WHEN H"4" => -- LONG WEISE
BL_BSIN[127..0] = (BL_SRC_BUF3[31..0],BL_SRC_BUF3[63..32],BL_SRC_BUF3[95..64],BL_SRC_BUF3[127..96]);
BL_BSIN[255..128] = (BL_SRC_BUF2[31..0],BL_SRC_BUF2[63..32],BL_SRC_BUF2[95..64],BL_SRC_BUF2[127..96]);
BL_BSIN[383..256] = (BL_SRC_BUF1[31..0],BL_SRC_BUF1[63..32],BL_SRC_BUF1[95..64],BL_SRC_BUF1[127..96]);
WHEN OTHERS => -- LINE WEISE
BL_BSIN[127..0] = BL_SRC_BUF3[];
BL_BSIN[255..128] = BL_SRC_BUF2[];
BL_BSIN[383..256] = BL_SRC_BUF1[];
END CASE;
BL_BSIN[127..0] = BL_SRC_BUF3[];
BL_BSIN[255..128] = BL_SRC_BUF2[];
BL_BSIN[383..256] = BL_SRC_BUF1[];
ELSE -- SONST NORMAL BEI VORW<52>RTS
BL_BSIN[127..0] = BL_SRC_BUF1[];
BL_BSIN[255..128] = BL_SRC_BUF2[];
@@ -395,16 +451,16 @@ BEGIN
BL_DST_BUFRD[] = (VDP_IN[],VDP_IN[]);
-- barell shift *****************************************************************************
-- SOURCE SHIFT RIGHT = LPM_CSHIFT RIGTH ;SKEW SHIFT: IF FXRS==0 THEN RIGHT ELSE LEFT
DIST_RIGHT[] = (16 * ((0,DST_ADR_NODE[3..1]) - (0,SRC_ADR_NODE[3..1]))) + (!BL_SKEW7 & (0,BL_SKEW[3..0])) - (BL_SKEW7 & (0,BL_SKEW[3..0]));
IF DIST_RIGHT8 == 0 THEN
BL_BS_SKEW[] = DIST_RIGHT[7..0]; -- LPM SHIFT RIGHT
SHIFT_DIR = VCC; -- DIR = RIGHT
else
BL_BS_SKEW[] = !DIST_RIGHT[7..0] + 1; -- LPM SHIFT LEFT
DIST_RIGHT[] = (16 * ((0,DST_ADR32[3..1]) - (0,SRC_ADR32[3..1]))) + (!BL_SKEW7 & (0,BL_SKEW[3..0])) - (BL_SKEW7 & (0,BL_SKEW[3..0]));
IF DIST_RIGHT8 THEN
BS_SKEW[] = 0 - DIST_RIGHT[7..0]; -- LPM SHIFT LEFT
SHIFT_DIR = GND; -- DIR = LEFT
else
BS_SKEW[] = DIST_RIGHT[7..0]; -- LPM SHIFT RIGHT
SHIFT_DIR = VCC; -- DIR = RIGHT
end if;
-- barell shifter: direction 0=links 1=rechts IN BEZUG AUF ausgabewert!
BL_BSOUT[] = lpm_clshift384(BL_BSIN[], SHIFT_DIR , BL_BS_SKEW[]); -- wir brauchen 128bit
BL_BSOUT[] = lpm_clshift384(BL_BSIN[], SHIFT_DIR , BS_SKEW[]); -- wir brauchen 128bit
-- HOP ***************************************************************************************
CASE BL_HOP[1..0] IS
WHEN H"0" =>
@@ -423,47 +479,47 @@ BEGIN
OP_OUT[] = H"0";
SRC_READ = B"0";
WHEN H"1" =>
OP_OUT[] = HOP_OUT[] & BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
OP_OUT[] = HOP_OUT[] AND BL_DST_BUFRD[];
SRC_READ = BL_HOP1;
WHEN H"2" =>
OP_OUT[] = HOP_OUT[] & !BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
OP_OUT[] = HOP_OUT[] AND !BL_DST_BUFRD[];
SRC_READ = BL_HOP1;
WHEN H"3" =>
OP_OUT[] = HOP_OUT[];
SRC_READ = BL_HOP1 # BL_HOP0;
SRC_READ = BL_HOP1;
WHEN H"4" =>
OP_OUT[] = !HOP_OUT[] & BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
OP_OUT[] = !HOP_OUT[] AND BL_DST_BUFRD[];
SRC_READ = BL_HOP1;
WHEN H"5" =>
OP_OUT[] = BL_DST_BUFRD[];
SRC_READ = B"0";
WHEN H"6" =>
OP_OUT[] = HOP_OUT[] $ BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
OP_OUT[] = HOP_OUT[] XOR BL_DST_BUFRD[];
SRC_READ = BL_HOP1;
WHEN H"7" =>
OP_OUT[] = HOP_OUT[] # BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
OP_OUT[] = HOP_OUT[] OR BL_DST_BUFRD[];
SRC_READ = BL_HOP1;
WHEN H"8" =>
OP_OUT[] = !HOP_OUT[] & !BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
OP_OUT[] = !HOP_OUT[] AND !BL_DST_BUFRD[];
SRC_READ = BL_HOP1;
WHEN H"9" =>
OP_OUT[] = !HOP_OUT[] $ BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
OP_OUT[] = !HOP_OUT[] XOR BL_DST_BUFRD[];
SRC_READ = BL_HOP1;
WHEN H"A" =>
OP_OUT[] = !BL_DST_BUFRD[];
SRC_READ = B"0";
WHEN H"B" =>
OP_OUT[] = HOP_OUT[] # !BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
OP_OUT[] = HOP_OUT[] OR !BL_DST_BUFRD[];
SRC_READ = BL_HOP1;
WHEN H"C" =>
OP_OUT[] = !HOP_OUT[];
SRC_READ = BL_HOP1 # BL_HOP0;
SRC_READ = BL_HOP1;
WHEN H"D" =>
OP_OUT[] = !HOP_OUT[] # BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
OP_OUT[] = !HOP_OUT[] OR BL_DST_BUFRD[];
SRC_READ = BL_HOP1;
WHEN H"E" =>
OP_OUT[] = !HOP_OUT[] # !BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
OP_OUT[] = !HOP_OUT[] OR !BL_DST_BUFRD[];
SRC_READ = BL_HOP1;
WHEN OTHERS =>
-- 12345678901234567890123456789012
OP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
@@ -472,145 +528,167 @@ BEGIN
------------ ENDMASKEN SETZEN ******************************************************************************
ENDMASK1_SHIFT[3..0] = 0;
ENDMASK2_SHIFT[3..0] = 0;
ENDMASKEND[] = DST_ADR32[] + (0,(BL_X_CNT[] - X_INDEX[]) - 1) * DST_XINC32[];
IF BL_DST_X_INC15 THEN ---------------------------- R<>CKW<4B>RTS X_INC NEGATIV
IF X_INDEX[]==0 THEN -- ENDE?
ENDMASK2_SHIFT[7..4] = 9 - (0,(DST_ADR_NODE[3..1])) + (8 & (DST_ADR_NODE[3..1]==0)); -- JA ENDMASK 3 SETZEN
IF X_INDEX[] == 0 THEN -- ENDE?
ENDMASK2_SHIFT[7..4] = 8 - (0,(DST_ADR32[3..1])); -- JA ENDMASK 3 SETZEN
ELSE
ENDMASK2_SHIFT[7..4] = 0; -- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN
END IF;
IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN -- SCHON ZEILENANFANG?
ENDMASKEND[] = X_INDEX[] - BL_X_CNT[] + (0,(DST_ADR_NODE[3..1]));
ENDMASK2_SHIFT[7..4] = 1 + (0,(ENDMASKEND[3..1])); -- JA: ENDMASK 3 SETZEN
IF (X_CNT16[] + DST_X_INC[]) >= BL_X_CNT[] THEN -- SCHON ZEILENENDE?
ENDMASK1_SHIFT[7..4] = 1 + (0,(ENDMASKEND[3..1])); -- JA -> ENDMASK 1 SETZEN
ELSE
ENDMASK1_SHIFT[7..4] = 0; -- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN
END IF;
ELSE ------------------------------------------- VORW<52>RTS X_INC POSITIV
IF X_INDEX[]==0 THEN -- ANFANG?
ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); -- JA -> ENDMASK 1 SETZEN
ELSE ------------------------------------------- VORW<52>RTS X_INC POSITIV (immer bei memcopy)
IF X_INDEX[] == 0 THEN -- ANFANG?
ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR32[3..1])); -- JA -> ENDMASK 1 SETZEN
ELSE
ENDMASK1_SHIFT[7..4] = 0; -- NEIN->ENDMASK1 AUF ENDMASK2 SETZEN
END IF;
IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN -- SCHON ZEILENENDE?
ENDMASKEND[] = X_CNT_NODE[] + 8 - BL_X_CNT[];
ENDMASK2_SHIFT[7..4] = 1 + ENDMASKEND[3..0]; -- JA: ENDMASK 3 SETZEN
IF (X_CNT16[] + DST_X_INC[]) >= BL_X_CNT[] THEN -- SCHON ZEILENENDE?
ENDMASK2_SHIFT[7..4] = 8 - (0,(ENDMASKEND[3..1])); -- JA: ENDMASK 3 SETZEN
ELSE
ENDMASK2_SHIFT[7..4] = 0; -- NOCH NICHT AKTIV->ENDMASK 3 AUF ENDMASK2 SETZEN
END IF;
END IF;
-- ENDMASKEN -- barell shifter 144 bit, direction 0 = links 1 = rechts
-- 1234567890123456789012345678
ENDMASK12_IN[] = (BL_ENDMASK1[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
BL_ENDMASK0[] = 0;
BL_ENDMASKF[] = -1;
BL_ENDMASKL[] = BL_ENDMASK1[] & !BL_DST_X_INC15 # BL_ENDMASK3[] & BL_DST_X_INC15;
BL_ENDMASKR[] = BL_ENDMASK3[] & !BL_DST_X_INC15 # BL_ENDMASK1[] & BL_DST_X_INC15;
CASE DST_X_INC[] IS
WHEN 8 => -- INC 2
ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
ENDMASKM_IN[] = (BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[]);
ENDMASK23_IN[] = (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]);
WHEN 4 => -- INC 4
ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
ENDMASKM_IN[] = (BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[]);
ENDMASK23_IN[] = (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]);
WHEN 2 => -- INC 8
ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
ENDMASKM_IN[] = (BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[]);
ENDMASK23_IN[] = (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]);
WHEN OTHERS =>
ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
ENDMASKM_IN[] = (BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[]);
ENDMASK23_IN[] = (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]);
END CASE;
ENDMASK12_OUT[] = lpm_clshift144(ENDMASK12_IN[],1,ENDMASK1_SHIFT[]); -- IMMER rechts SCHIEBEN
ENDMASK23_IN[] = (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK3[]);
ENDMASK23_OUT[] = lpm_clshift144(ENDMASK23_IN[],0,ENDMASK2_SHIFT[]); -- IMMER LINKS SCHIEBEN
ENDMASK123[] = ENDMASK12_OUT[127..0] & ENDMASK23_OUT[143..16];
ROR_CNT[] = 16 * (0,DST_ADR32[3..1]);
ENDMASKM_OUT[] = lpm_ror128(ENDMASKM_IN[],ROR_CNT[6..0]);
ENDMASK123[].CLK = DDRCLK0;
ENDMASK123[] = ENDMASK12_OUT[127..0] & ENDMASK23_OUT[143..16] & ENDMASKM_OUT[];
BLITTER_DOUT[] = ((ENDMASK123[] & OP_OUT[]) # (!ENDMASK123[] & BL_DST_BUFRD[]));
NOT_DST_READ = ((BL_OP[3..0]==H"0") # (BL_OP[3..0]==H"3") # (BL_OP[3..0]==H"C") # (BL_OP[3..0]==H"F")) & (ENDMASK123[]==H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");
NOT_DST_READ = ((BL_OP[3..0] == H"0") # (BL_OP[3..0] == H"3") # (BL_OP[3..0] == H"C") # (BL_OP[3..0] == H"F")) & (ENDMASK123[] == H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");
-- STATE MACHINE **********************************************************************************---------------------------12345678901234567890123456789012
BLITTER_RUN = BLITTER_ON; -- BLITTER IST DA!
BLITTER_ADR[3..0] = H"0"; -- IMMER LINE
SRC_DDR_ADR[] = (SRC_ADR_NODE[] - (0,(16 & BL_SRC_X_INC15))); -- WENN R<>CKW<4B>RTS NEXT ADRESS SRC
DST_DDR_ADR[] = (DST_ADR_NODE[] - (0,(16 & BL_DST_X_INC15))); -- WENN R<>CKW<4B>RTS NEXT ADRESS DST
BLITTER_REQ.CLK = DDRCLK0;
BLITTER_SIG = BLITTER_REQ & BLITTER_DACK[]==H"0";
BLITTER_SIG.CLK = DDRCLK0;
BLITTER_SIG = BLITTER_REQ & !BLITTER_DACK0 & !BLITTER_DACK1;
-- BLITTER MAIN STATE MACHINE -----------------------------------------------
BL_SM.CLK = DDRCLK0;
SRC_OLD[].CLK = DDRCLK0;
SRC_OLD[] = SRC_ADR32[31..4];
SDXINC.CLK = DDRCLK0;
CASE BL_SM IS
WHEN START => ------------------------- START
IF BLITTER_ON & BL_LN7 & ((BL_X_CNT[] - X_CNT_NODE[])>0) & ((BL_Y_CNT[] - Y_INDEX[]) > 0) THEN
BL_SM = NEW_LINE;
BL_NOTRUN = VCC; -- BLITTER NOT RUN
IF BLITTER_ON & BL_START & (BL_X_CNT[] > X_CNT16[]) & (BL_Y_CNT[] > Y_INDEX[]) THEN -- STARTEN?
BL_SM = NEW_LINE; -- JA START
ELSE
BL_SM = START;
BL_SM = START; -- NICHT STARTEN
END IF;
WHEN NEW_LINE => ----------------------- NEU LINIE
X_INDEX_CLR = VCC; -- L<EFBFBD>SCHEN
BL_SM = RDSRC0;
WHEN RDSRC0 => ------------------------ READ SRC1
IF SRC_READ THEN
BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4] - 1;
BLITTER_REQ = VCC;
BL_READ_SRC = VCC; -- LATCH UND SB1->SB2
IF BLITTER_DACK0 THEN
BL_SM = RDSRC2;
ELSE
BL_SM = RDSRC1;
END IF;
X_INDEX_CLR_DIR = VCC; -- JA -> X INDEX L<>SCHEN F<>R START LINE
IF SRC_READ THEN -- SOURCE READ N<>TIG?
BL_SM = RDSRC3; -- JA
ELSE
BL_SM = RDDST;
BL_SM = RDDST; -- NEIN -> DIREKT ZU READ DEST
END IF;
WHEN RDSRC1 => ------------------------ READ SRC1
IF SRC_READ THEN
BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4];
BLITTER_REQ = VCC;
BL_READ_SRC = VCC; -- LATCH UND SB1->SB2
IF BLITTER_DACK0 THEN
SIINC = VCC; -- INC SRC ADR
BL_SM = RDSRC2;
ELSE
BL_SM = RDSRC1;
END IF;
ELSE
BL_SM = RDDST;
WHEN RDSRC3 => ------------------------ READ SRC3
BLITTER_ADR[31..4] = SRC_ADR32[31..4] - 1 + (2 & BL_SRC_X_INC15);
BLITTER_REQ = VCC;
BL_READ_SRC = VCC; -- LATCH UND SB1->SB2
IF BLITTER_DACK0 THEN
BL_SM = RDSRC2;
ELSE
BL_SM = RDSRC3;
END IF;
WHEN RDSRC2 => ------------------------ READ SRC2
IF SRC_READ THEN
BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4];
BLITTER_REQ = VCC;
BL_READ_SRC = VCC; -- LATCH UND SB1->SB2
IF BLITTER_DACK0 THEN
SIINC = VCC; -- INC SRC ADR
BL_SM = RDDST;
ELSE
BL_SM = RDSRC2;
END IF;
ELSE
BL_SM = RDDST;
WHEN RDSRC2 => ------------------------- READ SRC2
BLITTER_ADR[31..4] = SRC_ADR32[31..4];
BLITTER_REQ = VCC;
BL_READ_SRC = VCC; -- LATCH UND SB1->SB2
IF BLITTER_DACK0 THEN
BL_SM = RDSRC1;
ELSE
BL_SM = RDSRC2;
END IF;
WHEN RDDST => ----------------------- READ DEST
WHEN RDSRC1 => ------------------------ READ SRC1
BLITTER_ADR[31..4] = SRC_ADR32[31..4] + 1 - (2 & BL_SRC_X_INC15);
BLITTER_REQ = VCC;
BL_READ_SRC = VCC; -- LATCH UND SB1->SB2
SRC_OLD[].ENA = VCC;
IF BLITTER_DACK0 THEN
BL_SM = RDDST;
ELSE
BL_SM = RDSRC1;
END IF;
WHEN RDDST => ------------------------ READ DEST
BLITTER_ADR[31..4] = DST_ADR32[31..4];
IF NOT_DST_READ THEN
BL_SM = WRDSTW1;
BL_SM = WRDSTW;
ELSE
BLITTER_ADR[31..4] = DST_DDR_ADR[31..4];
BLITTER_REQ = VCC;
BL_READ_DST = VCC;
IF BLITTER_DACK0 THEN
BL_SM = WRDSTW1;
BL_SM = WRDSTW;
ELSE
BL_SM = RDDST;
END IF;
END IF;
WHEN WRDSTW1 => ------------------- WRITE DEST WAIT AUF ERGEBNIS
WHEN WRDSTW => ------------------------ KURZ WARTEN AUF ERGEBNIS
BLITTER_ADR[31..4] = DST_ADR32[31..4];
BL_SM = WRDST;
WHEN WRDST => ------------------- WRITE DEST
BLITTER_ADR[31..4] = DST_DDR_ADR[31..4];
WHEN WRDST => ------------------------- WRITE DEST
BLITTER_ADR[31..4] = DST_ADR32[31..4];
BLITTER_WR = VCC;
BLITTER_REQ = VCC;
SDXINC = BLITTER_DACK2; -- INCCREMENT SRC, DST, X_INDEX
IF BLITTER_DACK0 THEN
XIINC = VCC; -- INC X_INDEX
DIINC = VCC; -- INC DEST ADR
BL_SM = TESTZEILENENDE;
ELSE
BL_SM = WRDST;
END IF;
WHEN TESTZEILENENDE => ----------------- ZEILENDE?
IF X_CNT_NODE[] >= BL_X_CNT[] THEN -- SCHON ZEILENENDE?
YIINC = VCC; -- JA -> INC Y-INDEX UND ZEILE SRC UND DEST
BL_SM = TESTFERTIG; -- ->
IF X_CNT16[] >= BL_X_CNT[] THEN -- SCHON ZEILENENDE?
YIINC = VCC; -- JA -> INC Y-INDEX
BL_SM = TESTFERTIG; -- => TEST OB FERTIG
ELSE
BL_SM = RDSRC2; -- NEIN NEXT
IF !SRC_READ THEN -- KEIN SOURCE READ?
BL_SM = RDDST; -- JA => LESEN UNN<4E>TIG ->
ELSE
IF SRC_ADR32[31..4] == SRC_OLD[] THEN -- ADRESSE IMMER NOCH IN DER LINE?
BL_SM = RDDST; -- DATEN SIND G<>LTIG -> READ DEST
ELSE
BL_SM = RDSRC1; -- SONST NEXT SRC
END IF;
END IF;
END IF;
WHEN TESTFERTIG => --------------------- TEST AUF FERTIG
ZIINC = VCC; -- INC ADRESSEN ZEILENUMBRUCH
IF Y_INDEX[] >= BL_Y_CNT[] THEN -- LETZTE ZEILE?
BL_SM = FERTIG; -- JA -->
ZAINC = VCC; -- ZEILENENDE: INC SRC UND DST ADRESSEN
IF Y_INDEX[] >= BL_Y_CNT[] THEN -- LETZTE ZEILE?
BL_SM = FERTIG; -- JA => FERTIG
ELSE
ZYINC = VCC; -- YINC ADDIEREN ZEILENENDE
BL_SM = NEW_LINE; -- NEIN NEXT ->
BL_SM = NEW_LINE; -- NEIN => NEXT LINE
END IF;
WHEN FERTIG => -------------------------- FERTIG
BLITTER_INT = VCC; -- BLITTER INTERRUPT
LN7CLR = VCC; -- BUSY BIT L<>SCHEN
IF BL_LN7==0 THEN -- WARTEN BIS GEL<45>SCHT (GEHT NUR MIT 33MHz)
BL_NOTRUN = VCC; -- BLITTER NOT RUN
BLITTER_INT = VCC; -- BLITTER INTERRUPT
LN7_CLR = VCC; -- BUSY BIT L<>SCHEN
IF (BL_LN7 == 0) & (BL_START == 0) THEN -- WARTEN BIS GEL<45>SCHT (SYNC MIT 33MHz)
BL_SM = START;
ELSE
BL_SM = FERTIG;

534
FPGA_by_Fredi/blitter.tdf.bak
View File

@@ -23,6 +23,8 @@ INCLUDE "lpm_bustri_WORD.inc";
INCLUDE "VIDEO/BLITTER/lpm_clshift384.INC";
INCLUDE "VIDEO/BLITTER/altsyncram0.INC";
INCLUDE "VIDEO/BLITTER/lpm_clshift144.inc";
INCLUDE "VIDEO/BLITTER/lpm_ror128.inc";
--CONSTANT BL_SKEW_LF = 255;
@@ -71,66 +73,70 @@ SUBDESIGN BLITTER
VARIABLE
BYT :NODE;
LONGLINE :NODE;
W_ADR[18..0] :NODE;
FB_16B[1..0] :NODE;
W_A1 :DFFE;
BLITTER_CS :NODE;
BL_HRAM_CS :NODE;
DP_RAM_CS :NODE;
BL_HRAM_BE[1..0] :NODE;
BL_HRAM_OUT[15..0] :NODE;
BL_DPRAM_OUT[15..0] :NODE;
BL_SRC_X_INC_CS :NODE;
BL_SRC_X_INC[15..0] :DFFE;
SRC_XINC_NODE[31..0] :NODE;
SRC_ADR_INC[31..0] :NODE;
SRC_XINC32[31..0] :NODE;
BL_SRC_Y_INC_CS :NODE;
BL_SRC_Y_INC[15..0] :DFFE;
SRC_YINC_NODE[31..0] :NODE;
SRC_YINC32[31..0] :NODE;
BL_ENDMASK1_CS :NODE;
BL_ENDMASK1[15..0] :DFFE;
BL_ENDMASK2_CS :NODE;
BL_ENDMASK2[15..0] :DFFE;
BL_ENDMASK3_CS :NODE;
BL_ENDMASK3[15..0] :DFFE;
BL_ENDMASK0[15..0] :NODE;
BL_ENDMASKF[15..0] :NODE;
BL_ENDMASKL[15..0] :NODE;
BL_ENDMASKR[15..0] :NODE;
BL_SRC_ADRH_CS :NODE;
BL_SRC_ADRL_CS :NODE;
BL_SRC_ADR[31..0] :DFFE;
SRC_OLD[27..0] :DFFE;
SRC_IADRH_CS :NODE;
SRC_IADRL_CS :NODE;
SRC_IADR[31..0] :DFF;
SRC_IADR_CLR :NODE;
SIINC :NODE;
SRC_ADR_NODE[31..0] :NODE;
SRC_IADR_CLR :DFF;
SRC_ADR32[31..0] :NODE;
BL_DST_X_INC_CS :NODE;
BL_DST_X_INC[15..0] :DFFE;
DST_XINC_NODE[31..0] :NODE;
DST_ADR_INC[31..0] :NODE;
DST_XINC32[31..0] :NODE;
BL_DST_Y_INC_CS :NODE;
BL_DST_Y_INC[15..0] :DFFE;
DST_YINC_NODE[31..0] :NODE;
DST_YINC32[31..0] :NODE;
BL_DST_ADRH_CS :NODE;
BL_DST_ADRL_CS :NODE;
BL_DST_ADR[31..0] :DFFE;
DST_IADRH_CS :NODE;
DST_IADRL_CS :NODE;
DST_IADR[31..0] :DFF;
DST_IADR_CLR :NODE;
DST_ADR_NODE[31..0] :NODE;
DIINC :NODE;
DST_IADR_CLR :DFF;
DST_ADR32[31..0] :NODE;
BL_X_CNT_CS :NODE;
BL_X_CNT[15..0] :DFFE;
X_CNT_NODE[15..0] :NODE;
X_CNT16[15..0] :NODE;
BL_Y_CNT_CS :NODE;
BL_Y_CNT[15..0] :DFFE;
BL_HOP_CS :NODE;
BL_HOP[7..0] :DFFE;
BL_OP[7..0] :DFFE;
BL_LN_CS :NODE;
LN7CLR :NODE;
BL_LN_WR :NODE;
LN7_CLR :NODE;
BL_LN[7..0] :DFFE;
BL_SKEW[7..0] :DFFE;
-- barell shifter
DIST_RIGHT[8..0] :NODE;
BL_BS_SKEW[7..0] :NODE;
BS_SKEW[7..0] :NODE;
BL_BSIN[383..0] :NODE;
BL_BSOUT[383..0] :NODE;
SHIFT_DIR :NODE;
@@ -145,15 +151,17 @@ VARIABLE
WREN_B :NODE; -- WR ENA HALFTONE RAM
X_INDEX_CS :NODE;
X_INDEX[15..0] :DFF; -- LAUFZEIGER X COUNT
X_INDEX_CLR :NODE;
X_INDEX_CLR :DFF; -- X INDEX L<>SCHEN CPU WRITE
X_INDEX_CLR_DIR :NODE; -- X INDEX L<>SCHEN STATE MACHINE
DST_X_INC[15..0] :NODE; -- ANZAHL WORTE PRO DURCHLAUF
X_CNT_T[15..0] :NODE;
Y_INDEX_CS :NODE;
Y_INDEX[15..0] :DFF; -- LAUFZEIGER Y COUNT
Y_INDEX_CLR :NODE;
Y_INDEX_CLR :DFF;
LINE_NR[3..0] :NODE;
XIINC :NODE; -- INC INDEX SPALTE
SDXINC :DFF; -- INC INDEX SPALTE
YIINC :NODE; -- INC INDEX ZEILE
ZIINC :NODE; -- INC ADRESSEN ZEILENUMBRUCH
ZYINC :NODE; -- KORREKTUR ADRESSEN WENN FERTIG
ZAINC :NODE; -- INC ADRESSEN ZEILENUMBRUCH
HOP_OUT[127..0] :NODE;
OP_OUT[127..0] :NODE;
ENDMASK1_SHIFT[7..0] :NODE;
@@ -162,24 +170,22 @@ VARIABLE
ENDMASK12_OUT[143..0] :NODE;
ENDMASK23_IN[143..0] :NODE;
ENDMASK23_OUT[143..0] :NODE;
ENDMASK123[127..0] :NODE;
ENDMASKEND[15..0] :NODE;
SRC_DDR_ADR[31..0] :NODE;
DST_DDR_ADR[31..0] :NODE;
BLITTER_REQ :DFF;
ENDMASKM_IN[127..0] :NODE;
ENDMASKM_OUT[127..0] :NODE;
ROR_CNT[8..0] :NODE;
ENDMASK123[127..0] :DFF;
ENDMASKEND[31..0] :NODE;
BLITTER_SIG :DFF;
BLITTER_REQ :NODE;
BL_START :DFF;
BL_NOTRUN :NODE;
-- MAIN STATE MACHINE
BL_SM :MACHINE WITH STATES(START,NEW_LINE,NEW_LINEW,RDSRC0,RDSRC1,RDSRC2,RDDST,WRDSTW1,WRDSTW2,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG);
BL_SM :MACHINE WITH STATES(START,NEW_LINE,RDSRC3,RDSRC2,RDSRC1,RDDST,WRDSTW,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG);
BEGIN
-- BYT UND WORD SELECT 16 BIT
BYT = !FB_SIZE1 & FB_SIZE0;
LONGLINE = !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG OR LINE
W_A1.CLK = MAIN_CLK;
W_A1.ENA = FB_ALE # BLITTER_TA & LONGLINE;
W_A1 = FB_ADR[1] & FB_ALE # BLITTER_TA & LONGLINE; -- A1 HOCHZ<48>HLEN BEI LONG UND LINE WEGEN BURST
W_ADR[18..1] = FB_ADR[19..2];
W_ADR0 = W_A1;
FB_16B0 = FB_ADR[0]==0; -- wenn ADR==0
FB_16B1 = FB_ADR[0]==1 # !BYT; -- wenn ADR==1 or NOT BYT
-- BLITTER CS
@@ -191,156 +197,229 @@ BEGIN
BL_HRAM_BE1 = BL_HRAM_CS & FB_16B0;
BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1;
WREN_B = B"0";
LINE_NR[] = ((Y_INDEX[3..0] & !BL_DST_Y_INC15) # (!Y_INDEX[3..0] & BL_DST_Y_INC15));
(BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(W_ADR[3..0],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B);
LINE_NR[] = BL_LN[3..0] + ((Y_INDEX[3..0] & !BL_DST_X_INC15) - (Y_INDEX[3..0] & BL_DST_X_INC15));
(BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(FB_ADR[4..1],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B);
DP_RAM_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C528"; -- $F8A50.w
-- SRC X INC
BL_SRC_X_INC[].CLK = MAIN_CLK;
BL_SRC_X_INC[] = FB_AD[31..16];
BL_SRC_X_INC_CS = !nFB_CS1 & W_ADR[]==H"7C510"; -- $F8A20.w
BL_SRC_X_INC[15..1] = FB_AD[31..17];
BL_SRC_X_INC0 = GND;
BL_SRC_X_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C510"); -- $F8A20.w
BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_X_INC[7..0].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
SRC_XINC_NODE[] = (H"FFFF0000" & BL_SRC_X_INC15) # (H"0000",BL_SRC_X_INC[]); -- ERWEITERN AUF 32 BIT
SRC_XINC32[15..0] = BL_SRC_X_INC[]; -- ERWEITERN AUF 32 BIT
SRC_XINC32[31..16] = H"FFFF" & BL_SRC_X_INC15; -- ERWEITERN AUF 32 BIT
-- SRC Y INC
BL_SRC_Y_INC[].CLK = MAIN_CLK;
BL_SRC_Y_INC[] = FB_AD[31..16];
BL_SRC_Y_INC_CS = !nFB_CS1 & W_ADR[]==H"7C511"; -- $F8A22.w
BL_SRC_Y_INC[15..1] = FB_AD[31..17];
BL_SRC_Y_INC0 = GND;
BL_SRC_Y_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C511"); -- $F8A22.w
BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_Y_INC[7..0].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
SRC_YINC_NODE[] = (H"FFFF0000" & BL_SRC_Y_INC15) # (H"0000",BL_SRC_Y_INC[]); -- ERWEITERN AUF 32 BIT
SRC_YINC32[15..0] = BL_SRC_Y_INC[]; -- ERWEITERN AUF 32 BIT
SRC_YINC32[31..16] = H"FFFF" & BL_SRC_Y_INC15; -- ERWEITERN AUF 32 BIT
-- SRC ADR HIGH
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[31..16] = FB_AD[31..16];
BL_SRC_ADRH_CS = !nFB_CS1 & W_ADR[]==H"7C512"; -- $F8A24.w
BL_SRC_ADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C512"); -- $F8A24.w
BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
-- SRC ADR LOW
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[15..0] = FB_AD[31..16];
BL_SRC_ADRL_CS = !nFB_CS1 & W_ADR[]==H"7C513"; -- $F8A26.w
BL_SRC_ADR[15..1] = FB_AD[31..17];
BL_SRC_ADR0 = GND;
BL_SRC_ADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C513"); -- $F8A26.w
BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[7..0].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
SRC_IADR[].CLK = DDRCLK0;
SRC_IADRH_CS = !nFB_CS1 & W_ADR[]==H"7C520"; -- $F8A40.w
SRC_IADRL_CS = !nFB_CS1 & W_ADR[]==H"7C521"; -- $F8A42.w
SRC_IADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C520"); -- $F8A40.w
SRC_IADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C521"); -- $F8A42.w
SRC_IADR_CLR.CLK = MAIN_CLK;
SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR; -- L<>SCHEN BEI WRITE
SRC_IADR[] = (SRC_IADR[] + (((8 * SRC_XINC_NODE[]) & SIINC) + (SRC_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[]) - 8) * SRC_XINC_NODE[]) & ZIINC)) & SRC_READ) & !SRC_IADR_CLR;
SRC_ADR_NODE[] = BL_SRC_ADR[] + SRC_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH
SRC_IADR[] = (((SRC_IADR[] + (SRC_ADR_INC[] & SDXINC)) & !ZAINC) + ((((((0,BL_X_CNT[]) - 1) * SRC_XINC32[]) + SRC_YINC32[]) * (0,Y_INDEX[])) & ZAINC)) & SRC_READ & !SRC_IADR_CLR;
SRC_ADR32[] = BL_SRC_ADR[] + SRC_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH
-- ENDMASK 1
BL_ENDMASK1[].CLK = MAIN_CLK;
BL_ENDMASK1[] = FB_AD[31..16];
BL_ENDMASK1_CS = !nFB_CS1 & W_ADR[]==H"7C514"; -- $F8A28.w
BL_ENDMASK1_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C514"); -- $F8A28.w
BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
BL_ENDMASK1[7..0].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
-- ENDMASK 2
BL_ENDMASK2[].CLK = MAIN_CLK;
BL_ENDMASK2[] = FB_AD[31..16];
BL_ENDMASK2_CS = !nFB_CS1 & W_ADR[]==H"7C515"; -- $F8A2A.w
BL_ENDMASK2_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C515"); -- $F8A2A.w
BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
BL_ENDMASK2[7..0].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
-- ENDMASK 3
BL_ENDMASK3[].CLK = MAIN_CLK;
BL_ENDMASK3[] = FB_AD[31..16];
BL_ENDMASK3_CS = !nFB_CS1 & W_ADR[]==H"7C516"; -- $F8A2C.w
BL_ENDMASK3_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C516"); -- $F8A2C.w
BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
BL_ENDMASK3[7..0].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
-- DST X INC
BL_DST_X_INC[].CLK = MAIN_CLK;
BL_DST_X_INC[] = FB_AD[31..16];
BL_DST_X_INC_CS = !nFB_CS1 & W_ADR[]==H"7C517"; -- $F8A2E.w
BL_DST_X_INC[15..1] = FB_AD[31..17];
BL_DST_X_INC0 = GND;
BL_DST_X_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C517"); -- $F8A2E.w
BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
BL_DST_X_INC[7..0].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
DST_XINC_NODE[] = (H"FFFF0000" & BL_DST_X_INC15) # (H"0000",BL_DST_X_INC[]); -- ERWEITERN AUF 32 BIT
DST_XINC32[15..0] = BL_DST_X_INC[]; -- ERWEITERN AUF 32 BIT
DST_XINC32[31..16] = H"FFFF" & BL_DST_X_INC15; -- ERWEITERN AUF 32 BIT
-- DST Y INC
BL_DST_Y_INC[].CLK = MAIN_CLK;
BL_DST_Y_INC[] = FB_AD[31..16];
BL_DST_Y_INC_CS = !nFB_CS1 & W_ADR[]==H"7C518"; -- $F8A30.w
BL_DST_Y_INC[15..1] = FB_AD[31..17];
BL_DST_Y_INC0 = GND;
BL_DST_Y_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C518"); -- $F8A30.w
BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
BL_DST_Y_INC[7..0].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
DST_YINC_NODE[] = (H"FFFF0000" & BL_DST_Y_INC15) # (H"0000",BL_DST_Y_INC[]); -- ERWEITERN AUF 32 BIT
DST_YINC32[15..0] = BL_DST_Y_INC[]; -- ERWEITERN AUF 32 BIT
DST_YINC32[31..16] = H"FFFF" & BL_DST_Y_INC15; -- ERWEITERN AUF 32 BIT
-- DST ADR HIGH
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[31..16] = FB_AD[31..16];
BL_DST_ADRH_CS = !nFB_CS1 & W_ADR[]==H"7C519"; -- $F8A32.w
BL_DST_ADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C519"); -- $F8A32.w
BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
-- DST ADR LOW
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[15..0] = FB_AD[31..16];
BL_DST_ADRL_CS = !nFB_CS1 & W_ADR[]==H"7C51A"; -- $F8A34.w
BL_DST_ADR[15..1] = FB_AD[31..17];
BL_DST_ADR0 = GND;
BL_DST_ADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C51A"); -- $F8A34.w
BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[7..0].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
DST_IADR[].CLK = DDRCLK0;
DST_IADRH_CS = !nFB_CS1 & W_ADR[]==H"7C522"; -- $F8A44.w
DST_IADRL_CS = !nFB_CS1 & W_ADR[]==H"7C523"; -- $F8A46.w
DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR; -- L<>SCHEN BEI WRITE
DST_IADR[] = (DST_IADR[] + ((8 * DST_XINC_NODE[]) & DIINC) + (DST_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[])) * DST_XINC_NODE[]) & ZIINC)) & !DST_IADR_CLR;
DST_ADR_NODE[] = BL_DST_ADR[] + DST_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH
DST_IADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C522"); -- $F8A44.w
DST_IADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C523"); -- $F8A46.w
DST_IADR_CLR.CLK = MAIN_CLK;
DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR; -- L<>SCHEN BEI WRITE
DST_IADR[] = (((DST_IADR[] + (DST_ADR_INC[] & SDXINC)) & !ZAINC) + ((((((0,BL_X_CNT[]) - 1) * DST_XINC32[]) + DST_YINC32[]) * (0,Y_INDEX[])) & ZAINC)) & !DST_IADR_CLR;
DST_ADR32[] = BL_DST_ADR[] + DST_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH
-- X COUNT
BL_X_CNT[].CLK = MAIN_CLK;
BL_X_CNT[] = FB_AD[31..16];
BL_X_CNT_CS = !nFB_CS1 & W_ADR[]==H"7C51B"; -- $F8A36.w
BL_X_CNT_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C51B"); -- $F8A36.w
BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
BL_X_CNT[7..0].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B1;
X_INDEX[].CLK = DDRCLK0;
X_INDEX_CS = !nFB_CS1 & W_ADR[]==H"7C524"; -- $F8A48.w
X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR; -- L<>SCHEN BEI WRITE
X_INDEX[] = (X_INDEX[] + (8 & XIINC) + ((BL_X_CNT[] - X_INDEX[]) & ZIINC)) & !X_INDEX_CLR;
X_CNT_NODE[] = X_INDEX[] - ((0,DST_ADR_NODE[3..1]) & (X_INDEX[]!=0));-- EFFEKTIV GELESENE
X_INDEX_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C524"); -- $F8A48.w
X_INDEX_CLR.CLK = MAIN_CLK;
X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR; -- L<>SCHEN BEI WRITE
X_INDEX[] = ((X_INDEX[] & !ZAINC) + (DST_X_INC[] & SDXINC) + (BL_X_CNT[] & ZAINC)) & !X_INDEX_CLR & !X_INDEX_CLR_DIR;
X_CNT16[] = X_INDEX[] - (X_CNT_T[] & (X_INDEX[]!=0)); -- EFFEKTIV geschrieben
-- SCHRITTWEITEN BEI PALLETTENMOD
IF (BL_SRC_X_INC[] != BL_DST_X_INC[]) # (BL_X_CNT[] < 8) THEN
DST_X_INC[] = 1;
X_CNT_T[] = 0;
SRC_ADR_INC[] = SRC_XINC32[]; -- SRC X INC
DST_ADR_INC[] = DST_XINC32[]; -- DST X INC
ELSE
IF BL_SRC_X_INC[] == H"0002" THEN
DST_X_INC[] = 8;
X_CNT_T[] = (0,DST_ADR32[3..1]);
SRC_ADR_INC[] = 16; -- SRC X INC
DST_ADR_INC[] = 16; -- DST X INC
ELSE
IF BL_SRC_X_INC[] == H"FFFE" THEN
DST_X_INC[] = 8;
X_CNT_T[] = 7 - (0,DST_ADR32[3..1]);
SRC_ADR_INC[] = -16; -- SRC X INC
DST_ADR_INC[] = -16; -- DST X INC
ELSE
IF BL_SRC_X_INC[] == H"0004" THEN
DST_X_INC[] = 4;
X_CNT_T[] = (0,DST_ADR32[3..2]);
SRC_ADR_INC[] = 16; -- SRC X INC
DST_ADR_INC[] = 16; -- DST X INC
ELSE
IF BL_SRC_X_INC[] == H"FFFC" THEN
DST_X_INC[] = 4;
X_CNT_T[] = 3 - (0,DST_ADR32[3..2]);
SRC_ADR_INC[] = -16; -- SRC X INC
DST_ADR_INC[] = -16; -- DST X INC
ELSE
IF BL_SRC_X_INC[] == H"0008" THEN
DST_X_INC[] = 2;
X_CNT_T[] = (0,DST_ADR32[3]);
SRC_ADR_INC[] = 16; -- SRC X INC
DST_ADR_INC[] = 16; -- DST X INC
ELSE
IF BL_SRC_X_INC[] == H"FFF8" THEN
DST_X_INC[] = 2;
X_CNT_T[] = 1 - (0,DST_ADR32[3]);
SRC_ADR_INC[] = -16; -- SRC X INC
DST_ADR_INC[] = -16; -- DST X INC
ELSE
DST_X_INC[] = 1;
X_CNT_T[] = 0;
SRC_ADR_INC[] = SRC_XINC32[]; -- SRC X INC
DST_ADR_INC[] = DST_XINC32[]; -- DST X INC
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
-- Y COUNT
BL_Y_CNT[].CLK = MAIN_CLK;
BL_Y_CNT[] = FB_AD[31..16];
BL_Y_CNT_CS = !nFB_CS1 & W_ADR[]==H"7C51C"; -- $F8A38.w
BL_Y_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51C"; -- $F8A38.w
BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
BL_Y_CNT[7..0].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
Y_INDEX[].CLK = DDRCLK0;
Y_INDEX_CS = !nFB_CS1 & W_ADR[]==H"7C525"; -- $F8A4A.w
Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR; -- L<>SCHEN BEI WRITE
Y_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C525"; -- $F8A4A.w
Y_INDEX_CLR.CLK = MAIN_CLK;
Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR; -- L<>SCHEN BEI WRITE
Y_INDEX[] = (Y_INDEX[] + (1 & YIINC)) & !Y_INDEX_CLR;
-- HOP LOGIC
BL_HOP[].CLK = MAIN_CLK;
BL_HOP[] = FB_AD[31..24];
BL_HOP_CS = !nFB_CS1 & W_ADR[]==H"7C51D"; -- $F8A3A.w
BL_HOP[7..0].ENA = BL_HOP_CS & !nFB_WR & FB_16B0; -- $F8A3A
BL_HOP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51D"; -- $F8A3A.w
BL_HOP[7..0].ENA = BL_HOP_CS & !nFB_WR & FB_16B0; -- $F8A3A
-- OP LOGIC
BL_OP[].CLK = MAIN_CLK;
BL_OP[] = FB_AD[23..16];
BL_OP[7..0].ENA = BL_HOP_CS & !nFB_WR & FB_16B1; -- $F8A3B
BL_OP[7..0].ENA = BL_HOP_CS & !nFB_WR & FB_16B1; -- $F8A3B
-- LINE NUMBER BYT
BL_LN[].CLK = MAIN_CLK;
BL_LN[6..0] = FB_AD[30..24];
BL_LN7 = FB_AD31 & !LN7CLR; -- BUSY HOG UND SMUDGE
BL_LN_CS = !nFB_CS1 & W_ADR[]==H"7C51E"; -- $F8A3C.w
BL_LN[].ENA = BL_LN_CS & !nFB_WR & FB_16B0; -- $F8A3C
BL_LN7.ENA = LN7CLR;
BL_LN_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C51E"); -- $F8A3C.w
BL_LN_WR = BL_LN_CS & !nFB_WR & FB_16B0; -- $F8A3C WRITE SIGNAL
BL_LN[6..0] = FB_AD[30..24]; -- HOG UND SMUDGE
BL_LN[6..0].ENA = BL_LN_WR; -- $F8A3C
BL_LN7.ENA = BL_LN_WR # LN7_CLR; -- $F8A3C
BL_LN7 = FB_AD31 & BLITTER_ON & (BL_X_CNT[] > X_CNT16[]) & (BL_Y_CNT[] > Y_INDEX[]) & !LN7_CLR; -- BUSY
BL_START.CLK = MAIN_CLK;
BL_START = BL_LN7 & !BL_LN_CS & BLITTER_ON & (BL_X_CNT[] > X_CNT16[]) & (BL_Y_CNT[] > Y_INDEX[]) & !LN7_CLR;
-- SKEW BYT
BL_SKEW[].CLK = MAIN_CLK;
BL_SKEW[] = FB_AD[23..16];
BL_SKEW[].ENA = BL_LN_CS & !nFB_WR & FB_16B1; -- $F8A3D
BL_SKEW[].ENA = BL_LN_CS & !nFB_WR & FB_16B1; -- $F8A3D
--- REGISTER OUT
FB_AD[31..16] = lpm_bustri_WORD(
BL_HRAM_CS & BL_DPRAM_OUT[]
# BL_SRC_X_INC_CS & BL_SRC_X_INC[]
# BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
# BL_SRC_ADRH_CS & SRC_ADR_NODE[31..16]
# BL_SRC_ADRL_CS & SRC_ADR_NODE[15..0]
# BL_SRC_ADRH_CS & SRC_ADR32[31..16]
# BL_SRC_ADRL_CS & SRC_ADR32[15..0]
# BL_ENDMASK1_CS & BL_ENDMASK1[]
# BL_ENDMASK2_CS & BL_ENDMASK2[]
# BL_ENDMASK3_CS & BL_ENDMASK3[]
# BL_DST_X_INC_CS & BL_DST_X_INC[]
# BL_DST_Y_INC_CS & BL_DST_Y_INC[]
# BL_DST_ADRH_CS & DST_ADR_NODE[31..16]
# BL_DST_ADRL_CS & DST_ADR_NODE[15..0]
# BL_DST_ADRH_CS & DST_ADR32[31..16]
# BL_DST_ADRL_CS & DST_ADR32[15..0]
# BL_X_CNT_CS & (BL_X_CNT[]-X_INDEX[])
# BL_Y_CNT_CS & (BL_Y_CNT[]-Y_INDEX[])
# BL_HOP_CS & (BL_HOP[],BL_OP[])
# BL_LN_CS & (BL_LN[7..4],Y_INDEX[3..0],BL_SKEW[])
# BL_LN_CS & (BL_LN7 # !BL_NOTRUN,BL_LN[6..0],BL_SKEW[])
# SRC_IADRH_CS & SRC_IADR[31..16]
# SRC_IADRL_CS & SRC_IADR[15..0]
# DST_IADRH_CS & DST_IADR[31..16]
# DST_IADRL_CS & DST_IADR[15..0]
# X_INDEX_CS & X_INDEX[]
# Y_INDEX_CS & Y_INDEX[]
,BLITTER_CS & !nFB_OE); -- FFFF8A00-7F
# DP_RAM_CS & BL_HRAM_OUT[]
,BLITTER_CS & !nFB_OE); -- FFFF8A00-7F
--------------------------------------------------------------------------------------
-- SRC BUFFER LADEN
BL_SRC_BUF1[].CLK = DDRCLK0;
@@ -355,34 +434,11 @@ BEGIN
BL_SRC_BUF3[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC;
BL_SRC_BUF3[63..0].ENA = BLITTER_DACK0 & BL_READ_SRC;
BL_SRC_BUF3[] = BL_SRC_BUF2[];
-- ZUORDNUNG ---------
-- ZUORDNUNG ---------------------------------------------------
IF BL_SRC_X_INC15 THEN -- WENN NEGATIV -> REIHENFOLGE KEHREN
CASE BL_HOP[7..4] IS -- SPIEGELN?
WHEN H"0" => -- LINE WEISE
BL_BSIN[127..0] = BL_SRC_BUF3[];
BL_BSIN[255..128] = BL_SRC_BUF2[];
BL_BSIN[383..256] = BL_SRC_BUF1[];
WHEN H"1" => --- BIT WEISE
BL_BSIN[0..127] = BL_SRC_BUF3[];
BL_BSIN[128..255] = BL_SRC_BUF2[];
BL_BSIN[256..383] = BL_SRC_BUF1[];
WHEN H"2" => -- BYT WEISE
BL_BSIN[127..0] = (BL_SRC_BUF3[7..0],BL_SRC_BUF3[15..8],BL_SRC_BUF3[23..16],BL_SRC_BUF3[31..24],BL_SRC_BUF3[39..32],BL_SRC_BUF3[47..40],BL_SRC_BUF3[55..48],BL_SRC_BUF3[63..56],BL_SRC_BUF3[71..64],BL_SRC_BUF3[79..72],BL_SRC_BUF3[87..80],BL_SRC_BUF3[95..88],BL_SRC_BUF3[103..96],BL_SRC_BUF3[111..104],BL_SRC_BUF3[119..112],BL_SRC_BUF3[127..120]);
BL_BSIN[255..128] = (BL_SRC_BUF2[7..0],BL_SRC_BUF2[15..8],BL_SRC_BUF2[23..16],BL_SRC_BUF2[31..24],BL_SRC_BUF2[39..32],BL_SRC_BUF2[47..40],BL_SRC_BUF2[55..48],BL_SRC_BUF2[63..56],BL_SRC_BUF2[71..64],BL_SRC_BUF2[79..72],BL_SRC_BUF2[87..80],BL_SRC_BUF2[95..88],BL_SRC_BUF2[103..96],BL_SRC_BUF2[111..104],BL_SRC_BUF2[119..112],BL_SRC_BUF2[127..120]);
BL_BSIN[383..256] = (BL_SRC_BUF1[7..0],BL_SRC_BUF1[15..8],BL_SRC_BUF1[23..16],BL_SRC_BUF1[31..24],BL_SRC_BUF1[39..32],BL_SRC_BUF1[47..40],BL_SRC_BUF1[55..48],BL_SRC_BUF1[63..56],BL_SRC_BUF1[71..64],BL_SRC_BUF1[79..72],BL_SRC_BUF1[87..80],BL_SRC_BUF1[95..88],BL_SRC_BUF1[103..96],BL_SRC_BUF1[111..104],BL_SRC_BUF1[119..112],BL_SRC_BUF1[127..120]);
WHEN H"3" => -- WORD WEISE
BL_BSIN[127..0] = (BL_SRC_BUF3[15..0],BL_SRC_BUF3[31..16],BL_SRC_BUF3[47..32],BL_SRC_BUF3[63..48],BL_SRC_BUF3[79..64],BL_SRC_BUF3[95..80],BL_SRC_BUF3[111..96],BL_SRC_BUF3[127..112]);
BL_BSIN[255..128] = (BL_SRC_BUF2[15..0],BL_SRC_BUF2[31..16],BL_SRC_BUF2[47..32],BL_SRC_BUF2[63..48],BL_SRC_BUF2[79..64],BL_SRC_BUF2[95..80],BL_SRC_BUF2[111..96],BL_SRC_BUF2[127..112]);
BL_BSIN[383..256] = (BL_SRC_BUF1[15..0],BL_SRC_BUF1[31..16],BL_SRC_BUF1[47..32],BL_SRC_BUF1[63..48],BL_SRC_BUF1[79..64],BL_SRC_BUF1[95..80],BL_SRC_BUF1[111..96],BL_SRC_BUF1[127..112]);
WHEN H"4" => -- LONG WEISE
BL_BSIN[127..0] = (BL_SRC_BUF3[31..0],BL_SRC_BUF3[63..32],BL_SRC_BUF3[95..64],BL_SRC_BUF3[127..96]);
BL_BSIN[255..128] = (BL_SRC_BUF2[31..0],BL_SRC_BUF2[63..32],BL_SRC_BUF2[95..64],BL_SRC_BUF2[127..96]);
BL_BSIN[383..256] = (BL_SRC_BUF1[31..0],BL_SRC_BUF1[63..32],BL_SRC_BUF1[95..64],BL_SRC_BUF1[127..96]);
WHEN OTHERS => -- LINE WEISE
BL_BSIN[127..0] = BL_SRC_BUF3[];
BL_BSIN[255..128] = BL_SRC_BUF2[];
BL_BSIN[383..256] = BL_SRC_BUF1[];
END CASE;
BL_BSIN[127..0] = BL_SRC_BUF3[];
BL_BSIN[255..128] = BL_SRC_BUF2[];
BL_BSIN[383..256] = BL_SRC_BUF1[];
ELSE -- SONST NORMAL BEI VORW<52>RTS
BL_BSIN[127..0] = BL_SRC_BUF1[];
BL_BSIN[255..128] = BL_SRC_BUF2[];
@@ -395,16 +451,16 @@ BEGIN
BL_DST_BUFRD[] = (VDP_IN[],VDP_IN[]);
-- barell shift *****************************************************************************
-- SOURCE SHIFT RIGHT = LPM_CSHIFT RIGTH ;SKEW SHIFT: IF FXRS==0 THEN RIGHT ELSE LEFT
DIST_RIGHT[] = (16 * ((0,DST_ADR_NODE[3..1]) - (0,SRC_ADR_NODE[3..1]))) + (!BL_SKEW7 & (0,BL_SKEW[3..0])) - (BL_SKEW7 & (0,BL_SKEW[3..0]));
IF DIST_RIGHT8 == 0 THEN
BL_BS_SKEW[] = DIST_RIGHT[7..0]; -- LPM SHIFT RIGHT
SHIFT_DIR = VCC; -- DIR = RIGHT
else
BL_BS_SKEW[] = !DIST_RIGHT[7..0] + 1; -- LPM SHIFT LEFT
DIST_RIGHT[] = (16 * ((0,DST_ADR32[3..1]) - (0,SRC_ADR32[3..1]))) + (!BL_SKEW7 & (0,BL_SKEW[3..0])) - (BL_SKEW7 & (0,BL_SKEW[3..0]));
IF DIST_RIGHT8 THEN
BS_SKEW[] = 0 - DIST_RIGHT[7..0]; -- LPM SHIFT LEFT
SHIFT_DIR = GND; -- DIR = LEFT
else
BS_SKEW[] = DIST_RIGHT[7..0]; -- LPM SHIFT RIGHT
SHIFT_DIR = VCC; -- DIR = RIGHT
end if;
-- barell shifter: direction 0=links 1=rechts IN BEZUG AUF ausgabewert!
BL_BSOUT[] = lpm_clshift384(BL_BSIN[], SHIFT_DIR , BL_BS_SKEW[]); -- wir brauchen 128bit
BL_BSOUT[] = lpm_clshift384(BL_BSIN[], SHIFT_DIR , BS_SKEW[]); -- wir brauchen 128bit
-- HOP ***************************************************************************************
CASE BL_HOP[1..0] IS
WHEN H"0" =>
@@ -423,47 +479,47 @@ BEGIN
OP_OUT[] = H"0";
SRC_READ = B"0";
WHEN H"1" =>
OP_OUT[] = HOP_OUT[] & BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
OP_OUT[] = HOP_OUT[] AND BL_DST_BUFRD[];
SRC_READ = BL_HOP1;
WHEN H"2" =>
OP_OUT[] = HOP_OUT[] & !BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
OP_OUT[] = HOP_OUT[] AND !BL_DST_BUFRD[];
SRC_READ = BL_HOP1;
WHEN H"3" =>
OP_OUT[] = HOP_OUT[];
SRC_READ = BL_HOP1 # BL_HOP0;
SRC_READ = BL_HOP1;
WHEN H"4" =>
OP_OUT[] = !HOP_OUT[] & BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
OP_OUT[] = !HOP_OUT[] AND BL_DST_BUFRD[];
SRC_READ = BL_HOP1;
WHEN H"5" =>
OP_OUT[] = BL_DST_BUFRD[];
SRC_READ = B"0";
WHEN H"6" =>
OP_OUT[] = HOP_OUT[] $ BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
OP_OUT[] = HOP_OUT[] XOR BL_DST_BUFRD[];
SRC_READ = BL_HOP1;
WHEN H"7" =>
OP_OUT[] = HOP_OUT[] # BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
OP_OUT[] = HOP_OUT[] OR BL_DST_BUFRD[];
SRC_READ = BL_HOP1;
WHEN H"8" =>
OP_OUT[] = !HOP_OUT[] & !BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
OP_OUT[] = !HOP_OUT[] AND !BL_DST_BUFRD[];
SRC_READ = BL_HOP1;
WHEN H"9" =>
OP_OUT[] = !HOP_OUT[] $ BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
OP_OUT[] = !HOP_OUT[] XOR BL_DST_BUFRD[];
SRC_READ = BL_HOP1;
WHEN H"A" =>
OP_OUT[] = !BL_DST_BUFRD[];
SRC_READ = B"0";
WHEN H"B" =>
OP_OUT[] = HOP_OUT[] # !BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
OP_OUT[] = HOP_OUT[] OR !BL_DST_BUFRD[];
SRC_READ = BL_HOP1;
WHEN H"C" =>
OP_OUT[] = !HOP_OUT[];
SRC_READ = BL_HOP1 # BL_HOP0;
SRC_READ = BL_HOP1;
WHEN H"D" =>
OP_OUT[] = !HOP_OUT[] # BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
OP_OUT[] = !HOP_OUT[] OR BL_DST_BUFRD[];
SRC_READ = BL_HOP1;
WHEN H"E" =>
OP_OUT[] = !HOP_OUT[] # !BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
OP_OUT[] = !HOP_OUT[] OR !BL_DST_BUFRD[];
SRC_READ = BL_HOP1;
WHEN OTHERS =>
-- 12345678901234567890123456789012
OP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
@@ -472,147 +528,167 @@ BEGIN
------------ ENDMASKEN SETZEN ******************************************************************************
ENDMASK1_SHIFT[3..0] = 0;
ENDMASK2_SHIFT[3..0] = 0;
ENDMASKEND[] = DST_ADR32[] + (0,(BL_X_CNT[] - X_INDEX[]) - 1) * DST_XINC32[];
IF BL_DST_X_INC15 THEN ---------------------------- R<>CKW<4B>RTS X_INC NEGATIV
IF X_INDEX[]==0 THEN -- ENDE?
ENDMASK2_SHIFT[7..4] = 9 - (0,(DST_ADR_NODE[3..1])) + (8 & (DST_ADR_NODE[3..1]==0)); -- JA ENDMASK 3 SETZEN
IF X_INDEX[] == 0 THEN -- ENDE?
ENDMASK2_SHIFT[7..4] = 8 - (0,(DST_ADR32[3..1])); -- JA ENDMASK 3 SETZEN
ELSE
ENDMASK2_SHIFT[7..4] = 0; -- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN
END IF;
IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN -- SCHON ZEILENANFANG?
ENDMASKEND[] = X_INDEX[] - BL_X_CNT[] + (0,(DST_ADR_NODE[3..1]));
ENDMASK2_SHIFT[7..4] = 1 + (0,(ENDMASKEND[3..1])); -- JA: ENDMASK 3 SETZEN
IF (X_CNT16[] + DST_X_INC[]) >= BL_X_CNT[] THEN -- SCHON ZEILENENDE?
ENDMASK1_SHIFT[7..4] = 1 + (0,(ENDMASKEND[3..1])); -- JA -> ENDMASK 1 SETZEN
ELSE
ENDMASK1_SHIFT[7..4] = 0; -- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN
END IF;
ELSE ------------------------------------------- VORW<52>RTS X_INC POSITIV
IF X_INDEX[]==0 THEN -- ANFANG?
ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); -- JA -> ENDMASK 1 SETZEN
ELSE ------------------------------------------- VORW<52>RTS X_INC POSITIV (immer bei memcopy)
IF X_INDEX[] == 0 THEN -- ANFANG?
ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR32[3..1])); -- JA -> ENDMASK 1 SETZEN
ELSE
ENDMASK1_SHIFT[7..4] = 0; -- NEIN->ENDMASK1 AUF ENDMASK2 SETZEN
END IF;
IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN -- SCHON ZEILENENDE?
ENDMASKEND[] = X_CNT_NODE[] + 8 - BL_X_CNT[];
ENDMASK2_SHIFT[7..4] = 1 + ENDMASKEND[3..0]; -- JA: ENDMASK 3 SETZEN
IF (X_CNT16[] + DST_X_INC[]) >= BL_X_CNT[] THEN -- SCHON ZEILENENDE?
ENDMASK2_SHIFT[7..4] = 8 - (0,(ENDMASKEND[3..1])); -- JA: ENDMASK 3 SETZEN
ELSE
ENDMASK2_SHIFT[7..4] = 0; -- NOCH NICHT AKTIV->ENDMASK 3 AUF ENDMASK2 SETZEN
END IF;
END IF;
-- ENDMASKEN -- barell shifter 144 bit, direction 0 = links 1 = rechts
-- 1234567890123456789012345678
ENDMASK12_IN[] = (BL_ENDMASK1[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
BL_ENDMASK0[] = 0;
BL_ENDMASKF[] = -1;
BL_ENDMASKL[] = BL_ENDMASK1[] & !BL_DST_X_INC15 # BL_ENDMASK3[] & BL_DST_X_INC15;
BL_ENDMASKR[] = BL_ENDMASK3[] & !BL_DST_X_INC15 # BL_ENDMASK1[] & BL_DST_X_INC15;
CASE DST_X_INC[] IS
WHEN 8 => -- INC 2
ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
ENDMASKM_IN[] = (BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[]);
ENDMASK23_IN[] = (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]);
WHEN 4 => -- INC 4
ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
ENDMASKM_IN[] = (BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[]);
ENDMASK23_IN[] = (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]);
WHEN 2 => -- INC 8
ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
ENDMASKM_IN[] = (BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[]);
ENDMASK23_IN[] = (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]);
WHEN OTHERS =>
ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
ENDMASKM_IN[] = (BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[]);
ENDMASK23_IN[] = (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]);
END CASE;
ENDMASK12_OUT[] = lpm_clshift144(ENDMASK12_IN[],1,ENDMASK1_SHIFT[]); -- IMMER rechts SCHIEBEN
ENDMASK23_IN[] = (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK3[]);
ENDMASK23_OUT[] = lpm_clshift144(ENDMASK23_IN[],0,ENDMASK2_SHIFT[]); -- IMMER LINKS SCHIEBEN
ENDMASK123[] = ENDMASK12_OUT[127..0] & ENDMASK23_OUT[143..16];
ROR_CNT[] = 16 * (0,DST_ADR32[3..1]);
ENDMASKM_OUT[] = lpm_ror128(ENDMASKM_IN[],ROR_CNT[6..0]);
ENDMASK123[].CLK = DDRCLK0;
ENDMASK123[] = ENDMASK12_OUT[127..0] & ENDMASK23_OUT[143..16] & ENDMASKM_OUT[];
BLITTER_DOUT[] = ((ENDMASK123[] & OP_OUT[]) # (!ENDMASK123[] & BL_DST_BUFRD[]));
NOT_DST_READ = ((BL_OP[3..0]==H"0") # (BL_OP[3..0]==H"3") # (BL_OP[3..0]==H"C") # (BL_OP[3..0]==H"F")) & (ENDMASK123[]==H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");
NOT_DST_READ = ((BL_OP[3..0] == H"0") # (BL_OP[3..0] == H"3") # (BL_OP[3..0] == H"C") # (BL_OP[3..0] == H"F")) & (ENDMASK123[] == H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");
-- STATE MACHINE **********************************************************************************---------------------------12345678901234567890123456789012
BLITTER_RUN = BLITTER_ON; -- BLITTER IST DA!
BLITTER_ADR[3..0] = H"0"; -- IMMER LINE
SRC_DDR_ADR[] = (SRC_ADR_NODE[] - (0,(16 & BL_SRC_X_INC15))); -- WENN R<>CKW<4B>RTS NEXT ADRESS SRC
DST_DDR_ADR[] = (DST_ADR_NODE[] - (0,(16 & BL_DST_X_INC15))); -- WENN R<>CKW<4B>RTS NEXT ADRESS DST
BLITTER_REQ.CLK = DDRCLK0;
BLITTER_SIG = BLITTER_REQ & BLITTER_DACK[]==H"0";
BLITTER_SIG.CLK = DDRCLK0;
BLITTER_SIG = BLITTER_REQ & !BLITTER_DACK0 & !BLITTER_DACK1;
-- BLITTER MAIN STATE MACHINE -----------------------------------------------
BL_SM.CLK = DDRCLK0;
SRC_OLD[].CLK = DDRCLK0;
SRC_OLD[] = SRC_ADR32[31..4];
SDXINC.CLK = DDRCLK0;
CASE BL_SM IS
WHEN START => ------------------------- START
IF BLITTER_ON & BL_LN7 & ((BL_X_CNT[] - X_CNT_NODE[])>0) & ((BL_Y_CNT[] - Y_INDEX[]) > 0) THEN
BL_SM = NEW_LINE;
BL_NOTRUN = VCC; -- BLITTER NOT RUN
IF BLITTER_ON & BL_START & (BL_X_CNT[] > X_CNT16[]) & (BL_Y_CNT[] > Y_INDEX[]) THEN -- STARTEN?
BL_SM = NEW_LINE; -- JA START
ELSE
BL_SM = START;
BL_SM = START; -- NICHT STARTEN
END IF;
WHEN NEW_LINE => ----------------------- NEU LINIE
X_INDEX_CLR = VCC; -- L<EFBFBD>SCHEN
BL_SM = RDSRC0;
WHEN RDSRC0 => ------------------------ READ SRC1
IF SRC_READ THEN
BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4] - 1;
BLITTER_REQ = VCC;
BL_READ_SRC = VCC; -- LATCH UND SB1->SB2
IF BLITTER_DACK0 THEN
BL_SM = RDSRC2;
ELSE
BL_SM = RDSRC1;
END IF;
X_INDEX_CLR_DIR = VCC; -- JA -> X INDEX L<>SCHEN F<>R START LINE
IF SRC_READ THEN -- SOURCE READ N<>TIG?
BL_SM = RDSRC3; -- JA
ELSE
BL_SM = RDDST;
BL_SM = RDDST; -- NEIN -> DIREKT ZU READ DEST
END IF;
WHEN RDSRC1 => ------------------------ READ SRC1
IF SRC_READ THEN
BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4];
BLITTER_REQ = VCC;
BL_READ_SRC = VCC; -- LATCH UND SB1->SB2
IF BLITTER_DACK0 THEN
SIINC = VCC; -- INC SRC ADR
BL_SM = RDSRC2;
ELSE
BL_SM = RDSRC1;
END IF;
ELSE
BL_SM = RDDST;
WHEN RDSRC3 => ------------------------ READ SRC3
BLITTER_ADR[31..4] = SRC_ADR32[31..4] - 1 + (2 & BL_SRC_X_INC15);
BLITTER_REQ = VCC;
BL_READ_SRC = VCC; -- LATCH UND SB1->SB2
IF BLITTER_DACK0 THEN
BL_SM = RDSRC2;
ELSE
BL_SM = RDSRC3;
END IF;
WHEN RDSRC2 => ------------------------ READ SRC2
IF SRC_READ THEN
BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4];
BLITTER_REQ = VCC;
BL_READ_SRC = VCC; -- LATCH UND SB1->SB2
IF BLITTER_DACK0 THEN
SIINC = VCC; -- INC SRC ADR
BL_SM = RDDST;
ELSE
BL_SM = RDSRC2;
END IF;
ELSE
BL_SM = RDDST;
WHEN RDSRC2 => ------------------------- READ SRC2
BLITTER_ADR[31..4] = SRC_ADR32[31..4];
BLITTER_REQ = VCC;
BL_READ_SRC = VCC; -- LATCH UND SB1->SB2
IF BLITTER_DACK0 THEN
BL_SM = RDSRC1;
ELSE
BL_SM = RDSRC2;
END IF;
WHEN RDDST => ----------------------- READ DEST
WHEN RDSRC1 => ------------------------ READ SRC1
BLITTER_ADR[31..4] = SRC_ADR32[31..4] + 1 - (2 & BL_SRC_X_INC15);
BLITTER_REQ = VCC;
BL_READ_SRC = VCC; -- LATCH UND SB1->SB2
SRC_OLD[].ENA = VCC;
IF BLITTER_DACK0 THEN
BL_SM = RDDST;
ELSE
BL_SM = RDSRC1;
END IF;
WHEN RDDST => ------------------------ READ DEST
BLITTER_ADR[31..4] = DST_ADR32[31..4];
IF NOT_DST_READ THEN
BL_SM = WRDSTW1;
BL_SM = WRDSTW;
ELSE
BLITTER_ADR[31..4] = DST_DDR_ADR[31..4];
BLITTER_REQ = VCC;
BL_READ_DST = VCC;
IF BLITTER_DACK0 THEN
BL_SM = WRDSTW1;
BL_SM = WRDSTW;
ELSE
BL_SM = RDDST;
END IF;
END IF;
WHEN WRDSTW1 => ------------------- WRITE DEST WAIT AUF ERGEBNIS
BL_SM = WRDSTW2;
WHEN WRDSTW2 => ------------------- WRITE DEST WAIT AUF ERGEBNIS
WHEN WRDSTW => ------------------------ KURZ WARTEN AUF ERGEBNIS
BLITTER_ADR[31..4] = DST_ADR32[31..4];
BL_SM = WRDST;
WHEN WRDST => ------------------- WRITE DEST
BLITTER_ADR[31..4] = DST_DDR_ADR[31..4];
WHEN WRDST => ------------------------- WRITE DEST
BLITTER_ADR[31..4] = DST_ADR32[31..4];
BLITTER_WR = VCC;
BLITTER_REQ = VCC;
SDXINC = BLITTER_DACK2; -- INCCREMENT SRC, DST, X_INDEX
IF BLITTER_DACK0 THEN
XIINC = VCC; -- INC X_INDEX
DIINC = VCC; -- INC DEST ADR
BL_SM = TESTZEILENENDE;
ELSE
BL_SM = WRDST;
END IF;
WHEN TESTZEILENENDE => ----------------- ZEILENDE?
IF X_CNT_NODE[] >= BL_X_CNT[] THEN -- SCHON ZEILENENDE?
YIINC = VCC; -- JA -> INC Y-INDEX UND ZEILE SRC UND DEST
BL_SM = TESTFERTIG; -- ->
IF X_CNT16[] >= BL_X_CNT[] THEN -- SCHON ZEILENENDE?
YIINC = VCC; -- JA -> INC Y-INDEX
BL_SM = TESTFERTIG; -- => TEST OB FERTIG
ELSE
BL_SM = RDSRC2; -- NEIN NEXT
IF !SRC_READ THEN -- KEIN SOURCE READ?
BL_SM = RDDST; -- JA => LESEN UNN<4E>TIG ->
ELSE
IF SRC_ADR32[31..4] == SRC_OLD[] THEN -- ADRESSE IMMER NOCH IN DER LINE?
BL_SM = RDDST; -- DATEN SIND G<>LTIG -> READ DEST
ELSE
BL_SM = RDSRC1; -- SONST NEXT SRC
END IF;
END IF;
END IF;
WHEN TESTFERTIG => --------------------- TEST AUF FERTIG
ZIINC = VCC; -- INC ADRESSEN ZEILENUMBRUCH
IF Y_INDEX[] >= BL_Y_CNT[] THEN -- LETZTE ZEILE?
BL_SM = FERTIG; -- JA -->
ZAINC = VCC; -- ZEILENENDE: INC SRC UND DST ADRESSEN
IF Y_INDEX[] >= BL_Y_CNT[] THEN -- LETZTE ZEILE?
BL_SM = FERTIG; -- JA => FERTIG
ELSE
ZYINC = VCC; -- YINC ADDIEREN ZEILENENDE
BL_SM = NEW_LINE; -- NEIN NEXT ->
BL_SM = NEW_LINE; -- NEIN => NEXT LINE
END IF;
WHEN FERTIG => -------------------------- FERTIG
BLITTER_INT = VCC; -- BLITTER INTERRUPT
LN7CLR = VCC; -- BUSY BIT L<>SCHEN
IF BL_LN7==0 THEN -- WARTEN BIS GEL<45>SCHT (GEHT NUR MIT 33MHz)
BL_NOTRUN = VCC; -- BLITTER NOT RUN
BLITTER_INT = VCC; -- BLITTER INTERRUPT
LN7_CLR = VCC; -- BUSY BIT L<>SCHEN
IF (BL_LN7 == 0) & (BL_START == 0) THEN -- WARTEN BIS GEL<45>SCHT (SYNC MIT 33MHz)
BL_SM = START;
ELSE
BL_SM = FERTIG;

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FPGA_by_Fredi/blitter.tdf.pdf
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FPGA_by_Fredi/firebee1.bdf
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(rect 1944 3256 2120 3272)
(rect 2216 3256 2392 3272)
(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
(text "SRD[15..0]" (rect 90 0 145 12)(font "Arial" ))
(pt 0 8)
@@ -2295,7 +2295,7 @@ applicable agreement for further details.
(line (pt 52 8)(pt 56 12)(line_width 1))
)
(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 2120 3272 2208 3512))
(annotation_block (location)(rect 2304 3272 2392 3512))
)
(pin
(bidir)
@@ -3506,7 +3506,7 @@ applicable agreement for further details.
(line (pt 88 24)(pt 72 24)(line_width 3))
)
(drawing
(text "402923543" (rect 27 18 80 30)(font "Arial" ))
(text "570826775" (rect 27 18 80 30)(font "Arial" ))
(text "32" (rect 77 25 88 37)(font "Arial" ))
(line (pt 16 16)(pt 72 16)(line_width 1))
(line (pt 72 16)(pt 72 32)(line_width 1))
@@ -4302,10 +4302,6 @@ applicable agreement for further details.
(pt 408 320)
(bidir)
)
(mapper
(pt 408 440)
(bidir)
)
(mapper
(pt 408 344)
(bidir)
@@ -4374,6 +4370,10 @@ applicable agreement for further details.
(pt 0 200)
(bidir)
)
(mapper
(pt 408 440)
(bidir)
)
)
(block
(rect 1264 2344 1672 2920)
@@ -4685,31 +4685,6 @@ applicable agreement for further details.
(pt 1264 3048)
(pt 1160 3048)
)
(connector
(text "nSRCS" (rect 1682 3272 1718 3284)(font "Arial" ))
(pt 1824 3288)
(pt 1672 3288)
)
(connector
(text "nSRBLE" (rect 1682 3296 1723 3308)(font "Arial" ))
(pt 1824 3312)
(pt 1672 3312)
)
(connector
(text "nSRBHE" (rect 1682 3320 1725 3332)(font "Arial" ))
(pt 1824 3336)
(pt 1672 3336)
)
(connector
(text "nSRWE" (rect 1682 3344 1720 3356)(font "Arial" ))
(pt 1824 3360)
(pt 1672 3360)
)
(connector
(text "nSROE" (rect 1682 3368 1718 3380)(font "Arial" ))
(pt 1824 3384)
(pt 1672 3384)
)
(connector
(text "DSP_INT" (rect 1130 2832 1176 2844)(font "Arial" ))
(pt 1264 2848)
@@ -4810,18 +4785,6 @@ applicable agreement for further details.
(pt 2080 80)
(bus)
)
(connector
(text "IO[17..0]" (rect 1962 3224 2005 3236)(font "Arial" ))
(pt 1672 3240)
(pt 2104 3240)
(bus)
)
(connector
(text "SRD[15..0]" (rect 1802 3248 1857 3260)(font "Arial" ))
(pt 1672 3264)
(pt 1944 3264)
(bus)
)
(connector
(text "CLK25M" (rect 1202 608 1243 620)(font "Arial" ))
(pt 1192 624)
@@ -5444,16 +5407,6 @@ applicable agreement for further details.
(pt 1144 2008)
(pt 1264 2008)
)
(connector
(text "LP_STR" (rect 1682 824 1722 836)(font "Arial" ))
(pt 1672 840)
(pt 1832 840)
)
(connector
(text "LP_DIR" (rect 1682 848 1720 860)(font "Arial" ))
(pt 1672 864)
(pt 1832 864)
)
(connector
(text "nACSI_ACK" (rect 1682 928 1742 940)(font "Arial" ))
(pt 1672 944)
@@ -5799,18 +5752,6 @@ applicable agreement for further details.
(pt 1160 920)
(pt 1264 920)
)
(connector
(text "LP_D[7..0]" (rect 1810 800 1863 812)(font "Arial" ))
(pt 1672 816)
(pt 1960 816)
(bus)
)
(connector
(text "ACSI_D[7..0]" (rect 1754 880 1820 892)(font "Arial" ))
(pt 1672 896)
(pt 1904 896)
(bus)
)
(connector
(text "SCSI_D[7..0]" (rect 1786 1056 1852 1068)(font "Arial" ))
(pt 1672 1072)
@@ -5877,10 +5818,6 @@ applicable agreement for further details.
(pt 824 440)
(pt 952 440)
)
(connector
(pt 1120 328)
(pt 920 328)
)
(connector
(pt 920 328)
(pt 920 432)
@@ -5983,10 +5920,6 @@ applicable agreement for further details.
(pt 376 -16)
(pt 368 -16)
)
(connector
(pt 1120 328)
(pt 1120 48)
)
(connector
(pt 400 -16)
(pt 464 -16)
@@ -5999,10 +5932,6 @@ applicable agreement for further details.
(pt 400 -16)
(pt 400 160)
)
(connector
(pt 736 48)
(pt 1120 48)
)
(connector
(text "CLK25M" (rect 802 -32 843 -20)(font "Arial" ))
(pt 736 -16)
@@ -6080,6 +6009,77 @@ applicable agreement for further details.
(pt 1264 2896)
(bus)
)
(connector
(pt 920 328)
(pt 1080 328)
)
(connector
(pt 1080 328)
(pt 1080 48)
)
(connector
(pt 736 48)
(pt 1080 48)
)
(connector
(text "ACSI_D[7..0]" (rect 1754 880 1820 892)(font "Arial" ))
(pt 1672 896)
(pt 1904 896)
(bus)
)
(connector
(text "IO[17..0]" (rect 2178 3224 2221 3236)(font "Arial" ))
(pt 1672 3240)
(pt 2320 3240)
(bus)
)
(connector
(text "nSRWE" (rect 1682 3344 1720 3356)(font "Arial" ))
(pt 1672 3360)
(pt 1816 3360)
)
(connector
(text "nSRBHE" (rect 1682 3320 1725 3332)(font "Arial" ))
(pt 1672 3336)
(pt 1904 3336)
)
(connector
(text "nSRBLE" (rect 1682 3296 1723 3308)(font "Arial" ))
(pt 1672 3312)
(pt 1992 3312)
)
(connector
(text "nSRCS" (rect 1682 3272 1718 3284)(font "Arial" ))
(pt 1672 3288)
(pt 2112 3288)
)
(connector
(text "SRD[15..0]" (rect 2074 3248 2129 3260)(font "Arial" ))
(pt 1672 3264)
(pt 2216 3264)
(bus)
)
(connector
(text "LP_D[7..0]" (rect 2154 800 2207 812)(font "Arial" ))
(pt 1672 816)
(pt 2304 816)
(bus)
)
(connector
(text "LP_STR" (rect 2042 824 2082 836)(font "Arial" ))
(pt 1672 840)
(pt 2192 840)
)
(connector
(text "LP_DIR" (rect 1922 848 1960 860)(font "Arial" ))
(pt 1672 864)
(pt 2072 864)
)
(connector
(text "nSROE" (rect 1682 3368 1718 3380)(font "Arial" ))
(pt 1672 3384)
(pt 1768 3384)
)
(junction (pt 2504 760))
(junction (pt 1856 -64))
(junction (pt 2424 -80))

2
FPGA_by_Fredi/firebee1.done
View File

@@ -1 +1 @@
Tue Apr 18 20:21:44 2017
Thu Jun 22 14:21:02 2017

16
FPGA_by_Fredi/firebee1.fit.summary Normal file
View File

@@ -0,0 +1,16 @@
Fitter Status : Successful - Thu Jun 22 14:20:25 2017
Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
Revision Name : firebee1
Top-level Entity Name : firebee1
Family : Cyclone III
Device : EP3C40F484C6
Timing Models : Final
Total logic elements : 20,227 / 39,600 ( 51 % )
Total combinational functions : 18,217 / 39,600 ( 46 % )
Dedicated logic registers : 5,767 / 39,600 ( 15 % )
Total registers : 5906
Total pins : 296 / 332 ( 89 % )
Total virtual pins : 0
Total memory bits : 355,360 / 1,161,216 ( 31 % )
Embedded Multiplier 9-bit elements : 20 / 252 ( 8 % )
Total PLLs : 4 / 4 ( 100 % )

14
FPGA_by_Fredi/firebee1.map.summary Normal file
View File

@@ -0,0 +1,14 @@
Analysis & Synthesis Status : Successful - Thu Jun 22 14:14:13 2017
Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
Revision Name : firebee1
Top-level Entity Name : firebee1
Family : Cyclone III
Total logic elements : 21,573
Total combinational functions : 18,134
Dedicated logic registers : 5,773
Total registers : 5901
Total pins : 296
Total virtual pins : 0
Total memory bits : 355,360
Embedded Multiplier 9-bit elements : 20
Total PLLs : 4

73
FPGA_by_Fredi/firebee1.qsf
View File

@@ -347,7 +347,7 @@ set_global_assignment -name TPD_REQUIREMENT "1 ns"
set_global_assignment -name TSU_REQUIREMENT "1 ns"
set_global_assignment -name TCO_REQUIREMENT "1 ns"
set_global_assignment -name TH_REQUIREMENT "1 ns"
set_global_assignment -name FMAX_REQUIREMENT "30 ns"
set_global_assignment -name FMAX_REQUIREMENT "33 MHz"
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
# Analysis & Synthesis Assignments
@@ -445,21 +445,6 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast
# Assignment Group Assignments
# ============================
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast
# end ASSIGNMENT_GROUP(fast)
# --------------------------
@@ -515,12 +500,6 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD
set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M
@@ -631,28 +610,33 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_C
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D
set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to LPDIR
set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to LP_STR
set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to LP_D
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX
set_location_assignment PIN_V2 -to nDREQ0
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8]
set_instance_assignment -name SLEW_RATE 0 -to LP_D
set_instance_assignment -name SLEW_RATE 0 -to LP_STR
set_instance_assignment -name SLEW_RATE 0 -to LPDIR
set_global_assignment -name SOURCE_FILE Video/BLITTER/lpm_ror128.cmp
set_global_assignment -name AHDL_FILE Video/BLITTER/lpm_ror128.tdf
set_global_assignment -name AHDL_FILE Video/BLITTER/lpm_clshift144.tdf
set_global_assignment -name SOURCE_FILE Video/BLITTER/altsyncram0.cmp
set_global_assignment -name AHDL_FILE Video/BLITTER/altsyncram0.tdf
@@ -715,8 +699,6 @@ set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp
set_global_assignment -name VHDL_FILE lpm_latch0.vhd
set_global_assignment -name SOURCE_FILE lpm_latch0.cmp
set_global_assignment -name QIP_FILE altpll1.qip
set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp
set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp
set_global_assignment -name QIP_FILE altpll2.qip
@@ -834,4 +816,13 @@ set_global_assignment -name INCLUDE_FILE Video/BLITTER/lpm_clshift383.inc
set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift384.qip
set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift144.qip
set_global_assignment -name QIP_FILE FPGA_DATE.qip
set_global_assignment -name QIP_FILE Video/Doppelzeilen_Fifo.qip
set_global_assignment -name QIP_FILE Video/shiftreg_dpz.qip
set_global_assignment -name QIP_FILE Video/BLITTER/lpm_ror128.qip
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS ON
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS ON
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK ON
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS ON
set_global_assignment -name FMAX_REQUIREMENT "33 MHz" -section_id Main
set_instance_assignment -name CLOCK_SETTINGS Main -to MAIN_CLK
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

BIN
FPGA_by_Fredi/firebee1.rbf
View File

Binary file not shown.

BIN
FPGA_by_Fredi/firebee1.sof Normal file
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Binary file not shown.

276
FPGA_by_Fredi/firebee1.tan.summary Normal file
View File

@@ -0,0 +1,276 @@
--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------
Type : Worst-case tsu
Slack : -10.868 ns
Required Time : 1.000 ns
Actual Time : 11.868 ns
From : FB_SIZE0
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_datain_reg0
From Clock : --
To Clock : MAIN_CLK
Failed Paths : 9538
Type : Worst-case tco
Slack : -96.119 ns
Required Time : 1.000 ns
Actual Time : 97.119 ns
From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1]
To : FB_AD[16]
From Clock : MAIN_CLK
To Clock : --
Failed Paths : 8562
Type : Worst-case tpd
Slack : -13.155 ns
Required Time : 1.000 ns
Actual Time : 14.155 ns
From : nFB_CS2
To : FB_AD[27]
From Clock : --
To Clock : --
Failed Paths : 550
Type : Worst-case th
Slack : -0.274 ns
Required Time : 1.000 ns
Actual Time : 1.274 ns
From : VD[18]
To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18]
From Clock : --
To Clock : MAIN_CLK
Failed Paths : 11
Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]'
Slack : -92.241 ns
Required Time : 25.00 MHz ( period = 39.999 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1]
To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF
From Clock : MAIN_CLK
To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
Failed Paths : 6009
Type : Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
Slack : -90.899 ns
Required Time : 96.01 MHz ( period = 10.416 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1]
To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF
From Clock : MAIN_CLK
To Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
Failed Paths : 5954
Type : Clock Setup: 'MAIN_CLK'
Slack : -63.646 ns
Required Time : 33.00 MHz ( period = 30.303 ns )
Actual Time : 10.64 MHz ( period = 93.949 ns )
From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1]
To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF
From Clock : MAIN_CLK
To Clock : MAIN_CLK
Failed Paths : 41189
Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
Slack : -17.307 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|BLITTER:BLITTER|BL_SRC_ADR[1]
To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO
From Clock : MAIN_CLK
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
Failed Paths : 26373
Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
Slack : -12.626 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|BLITTER:BLITTER|BL_X_CNT[0]
To : Video:Fredi_Aschwanden|BLITTER:BLITTER|SRC_IADR[30]
From Clock : MAIN_CLK
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
Failed Paths : 22076
Type : Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]'
Slack : -5.032 ns
Required Time : 16.00 MHz ( period = 62.499 ns )
Actual Time : N/A
From : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_datain_reg0
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
To Clock : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
Failed Paths : 2839
Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
Slack : -3.374 ns
Required Time : 66.00 MHz ( period = 15.151 ns )
Actual Time : N/A
From : FB_ALE
To : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]
From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
Failed Paths : 33
Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
Slack : 2.966 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : Restricted to 500.00 MHz ( period = 2.000 ns )
From : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15]
To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15]
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
Failed Paths : 0
Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
Slack : 3.965 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5]
To : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5]
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
Failed Paths : 0
Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[1]'
Slack : 13.509 ns
Required Time : 2.00 MHz ( period = 499.999 ns )
Actual Time : N/A
From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|LP_DIR_NS1
From Clock : MAIN_CLK
To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[1]
Failed Paths : 0
Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]'
Slack : 26.728 ns
Required Time : 0.50 MHz ( period = 1999.998 ns )
Actual Time : N/A
From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|PARITY_I
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_TX
From Clock : MAIN_CLK
To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]
Failed Paths : 0
Type : Clock Hold: 'MAIN_CLK'
Slack : -6.235 ns
Required Time : 33.00 MHz ( period = 30.303 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[2]
To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[2]
From Clock : MAIN_CLK
To Clock : MAIN_CLK
Failed Paths : 5610
Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]'
Slack : -0.919 ns
Required Time : 25.00 MHz ( period = 39.999 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|Doppelzeilen_Fifo:inst98|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
To : Video:Fredi_Aschwanden|Doppelzeilen_Fifo:inst98|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
Failed Paths : 405
Type : Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]'
Slack : 0.456 ns
Required Time : 16.00 MHz ( period = 62.499 ns )
Actual Time : N/A
From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[1]
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_address_reg0
From Clock : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
To Clock : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
Failed Paths : 0
Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[1]'
Slack : 0.502 ns
Required Time : 2.00 MHz ( period = 499.999 ns )
Actual Time : N/A
From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|LP_STR_X
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|LP_STR_X
From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[1]
To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[1]
Failed Paths : 0
Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]'
Slack : 0.502 ns
Required Time : 0.50 MHz ( period = 1999.998 ns )
Actual Time : N/A
From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]
From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]
To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]
Failed Paths : 0
Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
Slack : 0.502 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|BLITTER:BLITTER|FERTIG
To : Video:Fredi_Aschwanden|BLITTER:BLITTER|FERTIG
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
Failed Paths : 0
Type : Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
Slack : 0.502 ns
Required Time : 96.01 MHz ( period = 10.416 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|Doppelzeilen_Fifo:inst98|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
To : Video:Fredi_Aschwanden|Doppelzeilen_Fifo:inst98|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
From Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
To Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
Failed Paths : 0
Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
Slack : 1.815 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]
To : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
Failed Paths : 0
Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
Slack : 2.291 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|inst90~_Duplicate_4
To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
Failed Paths : 0
Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
Slack : 2.612 ns
Required Time : 66.00 MHz ( period = 15.151 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ
To : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
Failed Paths : 0
Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
Slack : 4.336 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31]
To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31]
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
Failed Paths : 0
Type : Total number of failed paths
Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 129149
--------------------------------------------------------------------------------------

16
FPGA_by_Fredi/firebeei1.qws
View File

@@ -1,16 +0,0 @@
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
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ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
DocPathName=blitter.tdf
DocumentCLSID={5d384c4f-893c-11d1-a087-0020affa43f2}
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IsActiveChildFrame=True
ptn_Child1=StateMap
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0.StateMap]
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185
FPGA_by_Fredi/lpm_mux0.s19
View File

@@ -1,185 +0,0 @@
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115
FPGA_by_Fredi/serv_req_info.txt
View File

@@ -1,115 +0,0 @@
<internal_error>
<executable>quartus.exe</executable>
<sub_system>VDB</sub_system>
<file>/quartus/db/vdb/vdb_value_bus.cpp</file>
<line>4101</line>
<callstack>
0x0382cb44: db_vdb + 0x5cb44 (?get_element@VDB_VALUE_BUS@@QBIPAVVDB_VALUE@@I@Z + 0x54)
</callstack>
<error>loc &lt; m_value-&gt;size()</error>
<date>Tue Oct 13 17:01:46 2009</date>
<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
<full_error>loc &lt; m_value-&gt;size()
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
</internal_error>
<internal_error>
<executable>quartus.exe</executable>
<sub_system>VDB</sub_system>
<file>/quartus/db/vdb/vdb_value_bus.cpp</file>
<line>4101</line>
<callstack>
0x0382cb44: db_vdb + 0x5cb44 (?get_element@VDB_VALUE_BUS@@QBIPAVVDB_VALUE@@I@Z + 0x54)
</callstack>
<error>loc &lt; m_value-&gt;size()</error>
<date>Tue Oct 13 17:11:00 2009</date>
<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
<full_error>loc &lt; m_value-&gt;size()
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
</internal_error>
<internal_error>
<executable>quartus.exe</executable>
<sub_system>unknown</sub_system>
<file>unknown</file>
<line>0</line>
<error>Current editor: GED</error>
<date>Wed Oct 14 23:17:06 2009</date>
<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
<full_error>Access Violation at 00000000
Current editor: GED
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
</internal_error>
<internal_error>
<executable>quartus.exe</executable>
<sub_system>unknown</sub_system>
<file>unknown</file>
<line>0</line>
<error>Current editor: SFW, STED</error>
<date>Thu Oct 15 19:23:19 2009</date>
<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
<full_error>Access Violation at 00000000
Current editor: SFW, STED
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
</internal_error>
<internal_error>
<executable>quartus.exe</executable>
<sub_system>unknown</sub_system>
<file>unknown</file>
<line>0</line>
<callstack>
0x1002d196: GCL_AFC + 0x2d196 (?open_document_file@AFC_TEMPLATE_MANAGER@@UAIPAVCDocument@@PBDPBVAFC_DOC_INFO@@PAVAFC_PROJECT_STATE_MAP@@_N33@Z + 0x7b6)
</callstack>
<error>Current editor: RPW, SFW
Current dockable window: PJN</error>
<date>Fri Oct 16 00:14:03 2009</date>
<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
<full_error>Access Violation at 0X1002D196
Current editor: RPW, SFW
Current dockable window: PJN
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
</internal_error>
<internal_error>
<executable>quartus.exe</executable>
<sub_system>unknown</sub_system>
<file>unknown</file>
<line>0</line>
<error>Current editor: SFW</error>
<date>Sat Oct 17 19:01:54 2009</date>
<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
<full_error>Access Violation at 00000000
Current editor: SFW
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
</internal_error>
<internal_error>
<executable>quartus.exe</executable>
<sub_system>AFC</sub_system>
<file>/quartus/gcl/afc/afc_child_frame.cpp</file>
<line>1940</line>
<callstack>
0x100084fa: GCL_AFC + 0x84fa (?enable_docking@AFC_CHILD_FRAME@@QAIXK@Z + 0x7a)
</callstack>
<error>(bar != NULL) &amp;&amp; bar-&gt;Create(this, WS_CLIPSIBLINGS | WS_CLIPCHILDREN | WS_CHILD | WS_VISIBLE | m_s_dock_bar_map[i][1], 0, m_s_dock_bar_map[i][0])</error>
<date>Mon Oct 19 21:58:36 2009</date>
<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
<full_error>(bar != NULL) &amp;&amp; bar-&gt;Create(this, WS_CLIPSIBLINGS | WS_CLIPCHILDREN | WS_CHILD | WS_VISIBLE | m_s_dock_bar_map[i][1], 0, m_s_dock_bar_map[i][0])
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
</internal_error>
<internal_error>
<executable>quartus.exe</executable>
<sub_system>unknown</sub_system>
<file>unknown</file>
<line>0</line>
<error>Current editor: RPW, GED</error>
<date>Tue Oct 20 00:53:11 2009</date>
<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
<full_error>Access Violation at 00000000
Current editor: RPW, GED
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
</internal_error>

0
FPGA_by_Fredi/sopc_builder_log.txt
View File

12
FPGA_by_Fredi/undo_redo.txt
View File

@@ -1,12 +0,0 @@
GED
Undo Commands
1. Properties
2. Move
3. Paste
4. Properties
5. Properties
6. Move
7. Paste