forked from Firebee/FPGA_Config
80 lines
2.7 KiB
VHDL
80 lines
2.7 KiB
VHDL
-- WARNING: Do NOT edit the input and output ports in this file in a text
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-- editor if you plan to continue editing the block that represents it in
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-- the Block Editor! File corruption is VERY likely to occur.
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-- Copyright (C) 1991-2008 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
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-- Created on Tue Sep 08 16:24:57 2009
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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-- Entity Declaration
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ENTITY DSP IS
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-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
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PORT
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(
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CLK33M : IN STD_LOGIC;
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MAIN_CLK : IN STD_LOGIC;
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nFB_OE : IN STD_LOGIC;
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nFB_WR : IN STD_LOGIC;
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nFB_CS1 : IN STD_LOGIC;
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nFB_CS2 : IN STD_LOGIC;
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FB_SIZE0 : IN STD_LOGIC;
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FB_SIZE1 : IN STD_LOGIC;
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nFB_BURST : IN STD_LOGIC;
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FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
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nRSTO : IN STD_LOGIC;
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nFB_CS3 : IN STD_LOGIC;
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nSRCS : OUT STD_LOGIC;
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nSRBLE : OUT STD_LOGIC;
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nSRBHE : OUT STD_LOGIC;
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nSRWE : OUT STD_LOGIC;
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nSROE : OUT STD_LOGIC;
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DSP_INT : OUT STD_LOGIC;
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DSP_TA : OUT STD_LOGIC;
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FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
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IO : INOUT STD_LOGIC_VECTOR(17 downto 0);
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SRD : INOUT STD_LOGIC_VECTOR(15 downto 0)
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);
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-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
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END DSP;
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-- Architecture Body
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ARCHITECTURE DSP_architecture OF DSP IS
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BEGIN
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nSRCS <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --nFB_CS3;
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nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1';
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nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0';
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nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1';
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nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1';
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DSP_INT <= '0';
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DSP_TA <= '0';
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IO(17 downto 0) <= FB_ADR(18 downto 1);
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SRD(15 downto 0) <= FB_AD(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
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FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
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END DSP_architecture;
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