Checker of chk.
This is a simple program designed to test the BDM driver and BDM
hardware.
To make the test program do :
$ make
To clean the directory do :
$ make clean
Running the program without any command line options displays the options
which you can use :
$ ./chk
chk -d -p [pc] -r [loops] -s [loops] -C -Q -R [device]
where :
-d [level] : enable driver debug output
-p [pc] : address to run to for the CPU32 target
-r [loops] : number or register check loops
-s [loops] : number or SRAM check loops on the Coldfire
-D [delay] : delay count for the clock generation
-C : continue on an error
-Q : be quite on errors
-R : reset on a register check fail
[device] : the bdm device, eg /dev/bdmcf0
The `-r', `-s', `-R' are specific to the Coldfire processor.
The basic test requires nothing more than the device path :
$ ./chk kea:/dev/bdmcf1
Driver Ver : 2.4
Processor : Coldfire
Interface : P&E Coldfire
CSR break set, target stopped.
Target status: 0x2 -- NOT RESET, HALTED, NOT STOPPED, POWER ON, CONNECTED.
Register test, 1 of 1 :
D00 : ........................................
D01 : ........................................
D02 : ........................................
D03 : ........................................
D04 : ........................................
D05 : ........................................
D06 : ........................................
D07 : ........................................
A08 : ........................................
A09 : ........................................
A10 : ........................................
A11 : ........................................
A12 : ........................................
A13 : ........................................
A14 : ........................................
A15 : ........................................
Read/Write SRAM Test, 1 loops
1 : ........................................
Coldfire execution test, loading code to SRAM.
Stepping code.
Stepping, pc is 0x20000000, csr = 0x01100000
Stepping, pc is 0x20000004, csr = 0x01100030
Stepping, pc is 0x2000000a, csr = 0x01100030
Stepping, pc is 0x20000010, csr = 0x01100030
Stepping, pc is 0x20000016, csr = 0x01100030
Stepping, pc is 0x2000001c, csr = 0x01100030
Stepping, pc is 0x20000022, csr = 0x01100030
Stepping, pc is 0x20000028, csr = 0x01100030
Stepping, pc is 0x2000002e, csr = 0x01100030
Stepping, pc is 0x20000034, csr = 0x01100030
Stepping, pc is 0x2000003a, csr = 0x01100030
Stepping, pc is 0x20000040, csr = 0x01100030
Stepping, pc is 0x20000046, csr = 0x01100030
Stepping, pc is 0x2000004c, csr = 0x01100030
Stepping, pc is 0x20000052, csr = 0x01100030
Stepping, pc is 0x20000058, csr = 0x01100030
Stepping, pc is 0x2000005e, csr = 0x01100030
Stepping, pc is 0x20000064, csr = 0x01100030
A0: A0A0A0A0 D0: D0D0D0D0
A1: A1A1A1A1 D1: D1D1D1D1
A2: A2A2A2A2 D2: D2D2D2D2
A3: A3A3A3A3 D3: D3D3D3D3
A4: A4A4A4A4 D4: D4D4D4D4
A5: A5A5A5A5 D5: D5D5D5D5
A6: A6A6A6A6 D6: D6D6D6D6
A7: A7A7A7A7 D7: D7D7D7D7
RPC:2000006A
SR:00002708
VBR:000002F8
CACR:00000000
ACR0:00004000
ACR1:FF004000
RAMBAR:20000001
MBAR:10000000
CSR:01100030
AATR:00000005
TDR:00000000
PBR:00000000
PBMR:00000000
ABHR:00000000
ABLR:00000000
DBR:00000000
DBMR:00000000
CSR halt set, target halted.
Target status: 0x2 -- NOT RESET, HALTED, NOT STOPPED, POWER ON, CONNECTED.
A0: A0A0A0A0 D0: D0D0D0D0
A1: A1A1A1A1 D1: D1D1D1D1
A2: A2A2A2A2 D2: D2D2D2D2
A3: A3A3A3A3 D3: D3D3D3D3
A4: A4A4A4A4 D4: D4D4D4D4
A5: A5A5A5A5 D5: D5D5D5D5
A6: A6A6A6A6 D6: D6D6D6D6
A7: A7A7A7A7 D7: D7D7D7D7
RPC:20000088
SR:00002708
VBR:000002F8
CACR:00000000
ACR0:00004000
ACR1:FF004000
RAMBAR:20000001
MBAR:10000000
CSR:02100000
AATR:00000005
TDR:00000000
PBR:00000000
PBMR:00000000
ABHR:00000000
ABLR:00000000
DBR:00000000
DBMR:00000000
0FC00000: 00009D74
01000000: 00009D74
01001000: 00000000
01001050: FFE0156C
01001054: FFE01580
The checker first tests if it can halt the processor.
Next is a register test. Here each register on the processor is sent a
range of bit patterns. You can, using the `-r' command line option,
specify the number times this test is run. If you select 0 the test
will not be run. A `W' or `R' will be displayed instead of a `.' if an
error occurs.
The third test is an SRAM test. A bit pattern is written and read from
the SRAM which is internal to the Coldfire. The write then read is a
block write then read. This is a special operation which typically
only results in two calls to the driver. If a mismatch occurs the
address is displayed and the test stops unless the continue option is
provided. The conintue option is useful when probing an interface
which is not working. The `-s' option controls the number of times the
test is run.
The next test is a code execution test. A small section of code is
downloaded to the SRAM of the Coldfire. The program counter is set to
point to the SRAM and a serial of single step operations
occur. Finally a go occurs. The processor should execute some
instructions until a HALT. The code can be found in the file
`sram-test.S'. It loads each register witch its register label.
Finally, all the registers are printed, and some memory locations are
read and written to.
