162 lines
5.7 KiB
Plaintext
162 lines
5.7 KiB
Plaintext
Checker of chk.
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This is a simple program designed to test the BDM driver and BDM
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hardware.
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To make the test program do :
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$ make
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To clean the directory do :
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$ make clean
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Running the program without any command line options displays the options
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which you can use :
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$ ./chk
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chk -d -p [pc] -r [loops] -s [loops] -C -Q -R [device]
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where :
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-d [level] : enable driver debug output
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-p [pc] : address to run to for the CPU32 target
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-r [loops] : number or register check loops
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-s [loops] : number or SRAM check loops on the Coldfire
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-D [delay] : delay count for the clock generation
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-C : continue on an error
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-Q : be quite on errors
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-R : reset on a register check fail
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[device] : the bdm device, eg /dev/bdmcf0
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The `-r', `-s', `-R' are specific to the Coldfire processor.
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The basic test requires nothing more than the device path :
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$ ./chk kea:/dev/bdmcf1
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Driver Ver : 2.4
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Processor : Coldfire
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Interface : P&E Coldfire
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CSR break set, target stopped.
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Target status: 0x2 -- NOT RESET, HALTED, NOT STOPPED, POWER ON, CONNECTED.
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Register test, 1 of 1 :
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D00 : ........................................
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D01 : ........................................
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D02 : ........................................
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D03 : ........................................
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D04 : ........................................
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D05 : ........................................
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D06 : ........................................
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D07 : ........................................
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A08 : ........................................
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A09 : ........................................
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A10 : ........................................
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A11 : ........................................
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A12 : ........................................
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A13 : ........................................
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A14 : ........................................
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A15 : ........................................
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Read/Write SRAM Test, 1 loops
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1 : ........................................
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Coldfire execution test, loading code to SRAM.
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Stepping code.
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Stepping, pc is 0x20000000, csr = 0x01100000
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Stepping, pc is 0x20000004, csr = 0x01100030
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Stepping, pc is 0x2000000a, csr = 0x01100030
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Stepping, pc is 0x20000010, csr = 0x01100030
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Stepping, pc is 0x20000016, csr = 0x01100030
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Stepping, pc is 0x2000001c, csr = 0x01100030
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Stepping, pc is 0x20000022, csr = 0x01100030
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Stepping, pc is 0x20000028, csr = 0x01100030
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Stepping, pc is 0x2000002e, csr = 0x01100030
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Stepping, pc is 0x20000034, csr = 0x01100030
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Stepping, pc is 0x2000003a, csr = 0x01100030
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Stepping, pc is 0x20000040, csr = 0x01100030
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Stepping, pc is 0x20000046, csr = 0x01100030
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Stepping, pc is 0x2000004c, csr = 0x01100030
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Stepping, pc is 0x20000052, csr = 0x01100030
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Stepping, pc is 0x20000058, csr = 0x01100030
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Stepping, pc is 0x2000005e, csr = 0x01100030
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Stepping, pc is 0x20000064, csr = 0x01100030
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A0: A0A0A0A0 D0: D0D0D0D0
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A1: A1A1A1A1 D1: D1D1D1D1
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A2: A2A2A2A2 D2: D2D2D2D2
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A3: A3A3A3A3 D3: D3D3D3D3
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A4: A4A4A4A4 D4: D4D4D4D4
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A5: A5A5A5A5 D5: D5D5D5D5
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A6: A6A6A6A6 D6: D6D6D6D6
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A7: A7A7A7A7 D7: D7D7D7D7
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RPC:2000006A
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SR:00002708
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VBR:000002F8
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CACR:00000000
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ACR0:00004000
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ACR1:FF004000
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RAMBAR:20000001
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MBAR:10000000
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CSR:01100030
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AATR:00000005
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TDR:00000000
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PBR:00000000
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PBMR:00000000
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ABHR:00000000
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ABLR:00000000
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DBR:00000000
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DBMR:00000000
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CSR halt set, target halted.
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Target status: 0x2 -- NOT RESET, HALTED, NOT STOPPED, POWER ON, CONNECTED.
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A0: A0A0A0A0 D0: D0D0D0D0
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A1: A1A1A1A1 D1: D1D1D1D1
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A2: A2A2A2A2 D2: D2D2D2D2
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A3: A3A3A3A3 D3: D3D3D3D3
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A4: A4A4A4A4 D4: D4D4D4D4
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A5: A5A5A5A5 D5: D5D5D5D5
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A6: A6A6A6A6 D6: D6D6D6D6
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A7: A7A7A7A7 D7: D7D7D7D7
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RPC:20000088
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SR:00002708
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VBR:000002F8
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CACR:00000000
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ACR0:00004000
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ACR1:FF004000
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RAMBAR:20000001
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MBAR:10000000
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CSR:02100000
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AATR:00000005
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TDR:00000000
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PBR:00000000
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PBMR:00000000
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ABHR:00000000
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ABLR:00000000
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DBR:00000000
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DBMR:00000000
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0FC00000: 00009D74
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01000000: 00009D74
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01001000: 00000000
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01001050: FFE0156C
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01001054: FFE01580
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The checker first tests if it can halt the processor.
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Next is a register test. Here each register on the processor is sent a
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range of bit patterns. You can, using the `-r' command line option,
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specify the number times this test is run. If you select 0 the test
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will not be run. A `W' or `R' will be displayed instead of a `.' if an
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error occurs.
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The third test is an SRAM test. A bit pattern is written and read from
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the SRAM which is internal to the Coldfire. The write then read is a
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block write then read. This is a special operation which typically
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only results in two calls to the driver. If a mismatch occurs the
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address is displayed and the test stops unless the continue option is
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provided. The conintue option is useful when probing an interface
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which is not working. The `-s' option controls the number of times the
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test is run.
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The next test is a code execution test. A small section of code is
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downloaded to the SRAM of the Coldfire. The program counter is set to
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point to the SRAM and a serial of single step operations
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occur. Finally a go occurs. The processor should execute some
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instructions until a HALT. The code can be found in the file
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`sram-test.S'. It loads each register witch its register label.
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Finally, all the registers are printed, and some memory locations are
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read and written to. |