146 lines
7.1 KiB
VHDL
146 lines
7.1 KiB
VHDL
LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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LIBRARY work;
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PACKAGE ddr_ram_model_pkg IS
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COMPONENT ddr_ram_model IS
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GENERIC
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(
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VERBOSE : BOOLEAN := TRUE; -- define if you want additional debug output
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CLOCK_TICK : TIME := (1000000 / 132000) * 1 ps; -- time for one clock tick
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NBANK : INTEGER := 4;
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ADDRTOP : INTEGER := 12;
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A10_LESS : BOOLEAN := TRUE; -- top column address is less than A10
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B : INTEGER := 16; -- number of bit (x16)
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NCOL : INTEGER := 10; -- top column address is CA9 (NCOL- 1)
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PAGEDEPTH : INTEGER := 1024;
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NDM : INTEGER := 2;
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NDQS : INTEGER := 2
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);
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PORT
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(
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dqi : INOUT STD_LOGIC_VECTOR (B - 1 DOWNTO 0);
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ba : IN UNSIGNED (NBANK / 2 - 1 DOWNTO 0);
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ad : IN STD_LOGIC_VECTOR (ADDRTOP DOWNTO 0);
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rasb : IN STD_LOGIC;
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casb : IN STD_LOGIC;
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web : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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clkb : IN STD_LOGIC;
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cke : IN STD_LOGIC;
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csb : IN STD_LOGIC;
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dm : IN UNSIGNED (NDM - 1 DOWNTO 0);
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dqs : INOUT STD_LOGIC_VECTOR (NDQS - 1 DOWNTO 0);
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qfc : OUT STD_LOGIC
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);
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END COMPONENT;
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END PACKAGE;
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PACKAGE BODY ddr_ram_model_pkg IS
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END PACKAGE BODY ddr_ram_model_pkg;
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---------------------------------------------------------------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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LIBRARY work;
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USE work.ddr_ram_model_pkg.ALL;
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ENTITY ddr_ram_model IS
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GENERIC
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(
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VERBOSE : BOOLEAN := TRUE; -- define if you want additional debug output
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CLOCK_TICK : TIME := (1000000 / 132000) * 1 ps; -- time for one clock tick
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NBANK : INTEGER := 4;
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ADDRTOP : INTEGER := 12;
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A10_LESS : BOOLEAN := TRUE; -- top column address is less than A10
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B : INTEGER := 16; -- number of bit (x16)
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NCOL : INTEGER := 10; -- top column address is CA9 (NCOL- 1)
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PAGEDEPTH : INTEGER := 1024;
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NDM : INTEGER := 2;
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NDQS : INTEGER := 2
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);
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PORT
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(
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dqi : INOUT STD_LOGIC_VECTOR (B - 1 DOWNTO 0);
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ba : IN UNSIGNED (NBANK / 2 - 1 DOWNTO 0);
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ad : IN STD_LOGIC_VECTOR (ADDRTOP DOWNTO 0);
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rasb : IN STD_LOGIC;
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casb : IN STD_LOGIC;
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web : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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clkb : IN STD_LOGIC;
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cke : IN STD_LOGIC;
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csb : IN STD_LOGIC;
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dm : IN UNSIGNED (NDM - 1 DOWNTO 0);
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dqs : INOUT STD_LOGIC_VECTOR (NDQS - 1 DOWNTO 0);
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qfc : OUT STD_LOGIC
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);
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END ENTITY ddr_ram_model;
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ARCHITECTURE rtl OF ddr_ram_model IS
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-- DDR RAM timing constants
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CONSTANT TRC : TIME := 65 ps; -- row cycle time (min)
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CONSTANT TRFC : TIME := 115 ps; -- Refresh Row cycle time (min)
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CONSTANT TRASMIN : TIME := 45 ps; -- Row active minimum time
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CONSTANT TRASMAX : TIME := 120000 ps; -- Row active maximum time
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CONSTANT TRCD : TIME := 20 ps; -- Ras to cas delay (min)
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CONSTANT TRP : TIME := 20 ps; -- Row precharge time (min)
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CONSTANT TRRD : TIME := 15 ps; -- Row to row delay (min)
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CONSTANT TCCD : TIME := CLOCK_TICK; -- Col. address to col. address delay: 1 clk
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CONSTANT TCKMIN : TIME := 7.5 ps; -- Clock minimum cycle time
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CONSTANT TCKMAX : TIME := 12 ps; -- Clock maximum cycle time
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CONSTANT TCK15 : TIME := 10 ps; -- Clock minimum cycle time at cas latency=1.5
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CONSTANT TCK2 : TIME := 10 ps; -- Clock minimum cycle time at cas latency=2
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CONSTANT TCK25 : TIME := 7.5 ps; -- Clock minimum cycle time at cas latency=2.5
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CONSTANT TCK3 : TIME := 7.5 ps; -- Clock minimum cycle time at cas latency=3
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CONSTANT TCHMIN : TIME := 0.45 ps; -- Clock high pulse width (min. 0.45 tCK, max: 0.55 tCK)
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CONSTANT TCHMAX : TIME := 0.55 ps;
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CONSTANT TCLMIN : TIME := 0.45 ps; -- Clock low pulse width (min. 0.45 tCK, max: 0.55 tCK)
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CONSTANT TCLMAX : TIME := 0.55 ps;
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CONSTANT TIS : TIME := 0.9 ps; -- input setup time (old Tss)
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CONSTANT TIH : TIME := 0.9 ps; -- input hold time (old Tsh)
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CONSTANT TWR : TIME := 15 ps; -- write recovery time
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CONSTANT TDS : TIME := 0.5 ps; -- Data in & DQM setup time
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CONSTANT TDH : TIME := 0.5 ps; -- Data in & DQM hold time
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CONSTANT TDQSH : TIME := 0.6 ps; -- DQS-in high level width (min. 0.4 tCK, max. 0.6 tCK)
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CONSTANT TDQSL : TIME := 0.6 ps; --
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CONSTANT TDSC : TIME := 1 ps; -- DQS-in cycle time tCIC changed following tDSC
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CONSTANT TPDEX : TIME := 7.5 ps; -- Power down exit time
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CONSTANT TSREX : TIME := 200 ps; -- Self refresh exit time : 200 clk
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CONSTANT THZQ : TIME := 0.75 ps; -- Data out active to High-Z (min:-0.75, max: +0.75)
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CONSTANT TDQSCK : TIME := 0.75 ps; -- DQS out edge to clock edge
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CONSTANT TAC : TIME := 0.75 ps; -- Output data access time from CK/CKB (min: -0.75, max: +0.75)
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CONSTANT TQCSW : TIME := 3.5 ps; -- Delay from the clock edge of write command to QFC out on writes (max: 4ns)
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CONSTANT TQCHW : TIME := 0.5 ps; -- QFC hold time on writes (min 1.25 ns, max: 0.5 tCK)
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CONSTANT TQCH : TIME := 0.4 ps; -- QFC hold time on reads (min 0.4 tCK, max 0.6 tCK)
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CONSTANT TQCS : TIME := 0.9 ps; -- QFC setup time on reads (min: 0.9 tCK, max 1.1 tCK)
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CONSTANT K1 : INTEGER := 1024;
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CONSTANT M1 : INTEGER := 1048576;
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CONSTANT BYTE : INTEGER := 8;
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CONSTANT TBITS : INTEGER := 512 * M1;
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--SIGNAL BITs : UNSIGNED (B - 1 DOWNTO 0);
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SIGNAL BIT_C : UNSIGNED (NCOL - 1 DOWNTO 0);
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CONSTANT NWORD : INTEGER := TBITS / B / NBANK;
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SIGNAL BIT_T : UNSIGNED (NCOL + ADDRTOP DOWNTO 0);
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SIGNAL WORD : UNSIGNED (NWORD - 1 DOWNTO 0);
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CONSTANT HB : INTEGER := B / 2;
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BEGIN
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END rtl;
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