Markus Fröschle e7e4fa4e75 added a little bus toggling to the test bench

2014-12-24 09:42:57 +00:00

..

ddr_ctlr_tb.vhd

converted more STD_LOGIC_VECTORs to UNSIGNED

2014-12-22 19:58:01 +00:00

ddr_ram_model.vhd

started implementing SAMSUNG's Verilog DDR model in VHDL

2014-12-23 22:30:23 +00:00

firebee_tb.vhd

added a little bus toggling to the test bench

2014-12-24 09:42:57 +00:00

k4h560438e_a2_0501.v

renamed files, fixed testbench

2014-12-23 18:20:11 +00:00