485 lines
19 KiB
VHDL
485 lines
19 KiB
VHDL
LIBRARY work;
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USE work.firebee_pkg.ALL;
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USE work.ddr_ram_model_pkg.ALL;
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE std.textio.ALL;
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ENTITY firebee_tb IS
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END firebee_tb;
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ARCHITECTURE beh OF firebee_tb IS
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COMPONENT firebee IS
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PORT(
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rsto_mcf_n : IN STD_LOGIC; -- reset SIGNAL from Coldfire
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clk_33m : IN STD_LOGIC; -- 33 MHz clock
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clk_main : IN STD_LOGIC; -- 33 MHz clock
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clk_24m576 : OUT STD_LOGIC; --
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clk_25m : OUT STD_LOGIC;
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clk_ddr_out : OUT STD_LOGIC;
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clk_ddr_out_n : OUT STD_LOGIC;
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clk_usb : OUT STD_LOGIC;
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fb_ad : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
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fb_ale : IN STD_LOGIC;
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fb_burst_n : IN STD_LOGIC;
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fb_cs_n : IN STD_LOGIC_VECTOR (3 DOWNTO 1);
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fb_size : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
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fb_oe_n : IN STD_LOGIC;
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fb_wr_n : IN STD_LOGIC;
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fb_ta_n : OUT STD_LOGIC;
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dack1_n : IN STD_LOGIC;
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dreq1_n : OUT STD_LOGIC;
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master_n : IN STD_LOGIC; -- determines if the Firebee is PCI master (='0') OR slave. Not used so far.
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tout0_n : IN STD_LOGIC; -- Not used so far.
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led_fpga_ok : OUT STD_LOGIC;
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reserved_1 : OUT STD_LOGIC;
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va : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
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ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
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vwe_n : OUT STD_LOGIC;
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vcas_n : OUT STD_LOGIC;
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vras_n : OUT STD_LOGIC;
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vcs_n : OUT STD_LOGIC;
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clk_pixel : OUT STD_LOGIC;
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sync_n : OUT STD_LOGIC;
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vsync : OUT STD_LOGIC;
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hsync : OUT STD_LOGIC;
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blank_n : OUT STD_LOGIC;
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vr : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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vg : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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vb : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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vdm : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
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vd : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
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vd_qs : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
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pd_vga_n : OUT STD_LOGIC;
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vcke : OUT STD_LOGIC;
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pic_int : IN STD_LOGIC;
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e0_int : IN STD_LOGIC;
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dvi_int : IN STD_LOGIC;
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pci_inta_n : IN STD_LOGIC;
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pci_intb_n : IN STD_LOGIC;
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pci_intc_n : IN STD_LOGIC;
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pci_intd_n : IN STD_LOGIC;
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irq_n : OUT STD_LOGIC_VECTOR (7 DOWNTO 2);
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tin0 : OUT STD_LOGIC;
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ym_qa : OUT STD_LOGIC;
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ym_qb : OUT STD_LOGIC;
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ym_qc : OUT STD_LOGIC;
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lp_d : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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lp_dir : OUT STD_LOGIC;
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dsa_d : OUT STD_LOGIC;
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lp_str : OUT STD_LOGIC;
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dtr : OUT STD_LOGIC;
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rts : OUT STD_LOGIC;
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cts : IN STD_LOGIC;
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ri : IN STD_LOGIC;
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dcd : IN STD_LOGIC;
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lp_busy : IN STD_LOGIC;
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rxd : IN STD_LOGIC;
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txd : OUT STD_LOGIC;
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midi_in : IN STD_LOGIC;
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midi_olr : OUT STD_LOGIC;
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midi_tlr : OUT STD_LOGIC;
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pic_amkb_rx : IN STD_LOGIC;
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amkb_rx : IN STD_LOGIC;
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amkb_tx : OUT STD_LOGIC;
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dack0_n : IN STD_LOGIC; -- Not used.
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scsi_drqn : IN STD_LOGIC;
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SCSI_MSGn : IN STD_LOGIC;
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SCSI_CDn : IN STD_LOGIC;
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SCSI_IOn : IN STD_LOGIC;
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SCSI_ACKn : OUT STD_LOGIC;
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SCSI_ATNn : OUT STD_LOGIC;
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SCSI_SELn : INOUT STD_LOGIC;
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SCSI_BUSYn : INOUT STD_LOGIC;
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SCSI_RSTn : INOUT STD_LOGIC;
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SCSI_DIR : OUT STD_LOGIC;
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SCSI_D : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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SCSI_PAR : INOUT STD_LOGIC;
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ACSI_DIR : OUT STD_LOGIC;
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ACSI_D : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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ACSI_CSn : OUT STD_LOGIC;
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ACSI_A1 : OUT STD_LOGIC;
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ACSI_reset_n : OUT STD_LOGIC;
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ACSI_ACKn : OUT STD_LOGIC;
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ACSI_DRQn : IN STD_LOGIC;
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ACSI_INTn : IN STD_LOGIC;
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FDD_DCHGn : IN STD_LOGIC;
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FDD_SDSELn : OUT STD_LOGIC;
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FDD_HD_DD : IN STD_LOGIC;
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FDD_RDn : IN STD_LOGIC;
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FDD_TRACK00 : IN STD_LOGIC;
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FDD_INDEXn : IN STD_LOGIC;
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FDD_WPn : IN STD_LOGIC;
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FDD_MOT_ON : OUT STD_LOGIC;
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FDD_WR_GATE : OUT STD_LOGIC;
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FDD_WDn : OUT STD_LOGIC;
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FDD_STEP : OUT STD_LOGIC;
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FDD_STEP_DIR : OUT STD_LOGIC;
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ROM4n : OUT STD_LOGIC;
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ROM3n : OUT STD_LOGIC;
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RP_UDSn : OUT STD_LOGIC;
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RP_ldsn : OUT STD_LOGIC;
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SD_CLK : OUT STD_LOGIC;
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SD_D3 : INOUT STD_LOGIC;
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SD_CMD_D1 : INOUT STD_LOGIC;
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SD_D0 : IN STD_LOGIC;
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SD_D1 : IN STD_LOGIC;
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SD_D2 : IN STD_LOGIC;
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SD_caRD_DETECT : IN STD_LOGIC;
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SD_WP : IN STD_LOGIC;
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CF_WP : IN STD_LOGIC;
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CF_CSn : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
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DSP_IO : INOUT STD_LOGIC_VECTOR (17 DOWNTO 0);
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DSP_SRD : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
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DSP_SRCSn : OUT STD_LOGIC;
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DSP_SRBLEn : OUT STD_LOGIC;
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DSP_SRBHEn : OUT STD_LOGIC;
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DSP_SRWEn : OUT STD_LOGIC;
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DSP_SROEn : OUT STD_LOGIC;
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ide_int : IN STD_LOGIC;
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ide_rdy : IN STD_LOGIC;
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ide_res : OUT STD_LOGIC;
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IDE_WRn : OUT STD_LOGIC;
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IDE_RDn : OUT STD_LOGIC;
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IDE_CSn : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
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);
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END COMPONENT firebee;
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SIGNAL clock : STD_LOGIC := '0'; -- main clock
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SIGNAL rsto_mcf_n : STD_LOGIC; -- reset SIGNAL from Coldfire
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SIGNAL clk_33m : STD_LOGIC; -- 33 MHz clock
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SIGNAL clk_main : STD_LOGIC; -- 33 MHz clock
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SIGNAL clk_24m576 : STD_LOGIC; --
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SIGNAL clk_25m : STD_LOGIC;
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SIGNAL clk_ddr_out : STD_LOGIC;
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SIGNAL clk_ddr_out_n : STD_LOGIC;
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SIGNAL clk_usb : STD_LOGIC;
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SIGNAL fb_ad : STD_LOGIC_VECTOR (31 DOWNTO 0);
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SIGNAL fb_ale : STD_LOGIC;
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SIGNAL fb_burst_n : STD_LOGIC;
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SIGNAL fb_cs_n : STD_LOGIC_VECTOR (3 DOWNTO 1);
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SIGNAL fb_size : STD_LOGIC_VECTOR (1 DOWNTO 0);
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SIGNAL fb_oe_n : STD_LOGIC;
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SIGNAL fb_wr_n : STD_LOGIC;
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SIGNAL fb_ta_n : STD_LOGIC;
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SIGNAL dack1_n : STD_LOGIC;
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SIGNAL dreq1_n : STD_LOGIC;
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SIGNAL master_n : STD_LOGIC; -- determines if the Firebee is PCI master (='0') OR slave. Not used so far.
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SIGNAL tout0_n : STD_LOGIC; -- Not used so far.
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SIGNAL led_fpga_ok : STD_LOGIC;
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SIGNAL reserved_1 : STD_LOGIC;
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SIGNAL va : STD_LOGIC_VECTOR (12 DOWNTO 0);
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SIGNAL ba : STD_LOGIC_VECTOR (1 DOWNTO 0);
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SIGNAL vwe_n : STD_LOGIC;
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SIGNAL vcas_n : STD_LOGIC;
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SIGNAL vras_n : STD_LOGIC;
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SIGNAL vcs_n : STD_LOGIC;
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SIGNAL clk_pixel : STD_LOGIC;
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SIGNAL sync_n : STD_LOGIC;
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SIGNAL vsync : STD_LOGIC;
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SIGNAL hsync : STD_LOGIC;
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SIGNAL blank_n : STD_LOGIC;
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SIGNAL vr : STD_LOGIC_VECTOR (7 DOWNTO 0);
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SIGNAL vg : STD_LOGIC_VECTOR (7 DOWNTO 0);
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SIGNAL vb : STD_LOGIC_VECTOR (7 DOWNTO 0);
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SIGNAL vdm : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL vd : STD_LOGIC_VECTOR (31 DOWNTO 0);
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SIGNAL vd_qs : STD_LOGIC_VECTOR (3 DOWNTO 0);
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SIGNAL pd_vga_n : STD_LOGIC;
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SIGNAL vcke : STD_LOGIC;
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SIGNAL pic_int : STD_LOGIC;
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SIGNAL e0_int : STD_LOGIC;
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SIGNAL dvi_int : STD_LOGIC;
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SIGNAL pci_inta_n : STD_LOGIC;
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SIGNAL pci_intb_n : STD_LOGIC;
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SIGNAL pci_intc_n : STD_LOGIC;
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SIGNAL pci_intd_n : STD_LOGIC;
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SIGNAL irq_n : STD_LOGIC_VECTOR (7 DOWNTO 2);
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SIGNAL tin0 : STD_LOGIC;
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SIGNAL ym_qa : STD_LOGIC;
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SIGNAL ym_qb : STD_LOGIC;
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SIGNAL ym_qc : STD_LOGIC;
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SIGNAL lp_d : STD_LOGIC_VECTOR (7 DOWNTO 0);
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SIGNAL lp_dir : STD_LOGIC;
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SIGNAL dsa_d : STD_LOGIC;
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SIGNAL lp_str : STD_LOGIC;
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SIGNAL dtr : STD_LOGIC;
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SIGNAL rts : STD_LOGIC;
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SIGNAL cts : STD_LOGIC;
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SIGNAL ri : STD_LOGIC;
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SIGNAL dcd : STD_LOGIC;
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SIGNAL lp_busy : STD_LOGIC;
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SIGNAL rxd : STD_LOGIC;
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SIGNAL txd : STD_LOGIC;
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SIGNAL midi_in : STD_LOGIC;
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SIGNAL midi_olr : STD_LOGIC;
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SIGNAL midi_tlr : STD_LOGIC;
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SIGNAL pic_amkb_rx : STD_LOGIC;
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SIGNAL amkb_rx : STD_LOGIC;
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SIGNAL amkb_tx : STD_LOGIC;
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SIGNAL dack0_n : STD_LOGIC; -- Not used.
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SIGNAL scsi_drqn : STD_LOGIC;
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SIGNAL SCSI_MSGn : STD_LOGIC;
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SIGNAL SCSI_CDn : STD_LOGIC;
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SIGNAL SCSI_IOn : STD_LOGIC;
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SIGNAL SCSI_ACKn : STD_LOGIC;
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SIGNAL SCSI_ATNn : STD_LOGIC;
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SIGNAL SCSI_SELn : STD_LOGIC;
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SIGNAL SCSI_BUSYn : STD_LOGIC;
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SIGNAL SCSI_RSTn : STD_LOGIC;
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SIGNAL SCSI_DIR : STD_LOGIC;
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SIGNAL SCSI_D : STD_LOGIC_VECTOR (7 DOWNTO 0);
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SIGNAL SCSI_PAR : STD_LOGIC;
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SIGNAL ACSI_DIR : STD_LOGIC;
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SIGNAL ACSI_D : STD_LOGIC_VECTOR (7 DOWNTO 0);
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SIGNAL ACSI_CSn : STD_LOGIC;
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SIGNAL ACSI_A1 : STD_LOGIC;
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SIGNAL ACSI_reset_n : STD_LOGIC;
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SIGNAL ACSI_ACKn : STD_LOGIC;
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SIGNAL ACSI_DRQn : STD_LOGIC;
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SIGNAL ACSI_INTn : STD_LOGIC;
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SIGNAL FDD_DCHGn : STD_LOGIC;
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SIGNAL FDD_SDSELn : STD_LOGIC;
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SIGNAL FDD_HD_DD : STD_LOGIC;
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SIGNAL FDD_RDn : STD_LOGIC;
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SIGNAL FDD_TRACK00 : STD_LOGIC;
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SIGNAL FDD_INDEXn : STD_LOGIC;
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SIGNAL FDD_WPn : STD_LOGIC;
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SIGNAL FDD_MOT_ON : STD_LOGIC;
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SIGNAL FDD_WR_GATE : STD_LOGIC;
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SIGNAL FDD_WDn : STD_LOGIC;
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SIGNAL FDD_STEP : STD_LOGIC;
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SIGNAL FDD_STEP_DIR : STD_LOGIC;
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SIGNAL ROM4n : STD_LOGIC;
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SIGNAL ROM3n : STD_LOGIC;
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SIGNAL RP_UDSn : STD_LOGIC;
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SIGNAL RP_ldsn : STD_LOGIC;
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SIGNAL SD_CLK : STD_LOGIC;
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SIGNAL SD_D3 : STD_LOGIC;
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SIGNAL SD_CMD_D1 : STD_LOGIC;
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SIGNAL SD_D0 : STD_LOGIC;
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SIGNAL SD_D1 : STD_LOGIC;
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SIGNAL SD_D2 : STD_LOGIC;
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SIGNAL SD_caRD_DETECT : STD_LOGIC;
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SIGNAL SD_WP : STD_LOGIC;
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SIGNAL CF_WP : STD_LOGIC;
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SIGNAL CF_CSn : STD_LOGIC_VECTOR (1 DOWNTO 0);
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SIGNAL DSP_IO : STD_LOGIC_VECTOR (17 DOWNTO 0);
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SIGNAL DSP_SRD : STD_LOGIC_VECTOR (15 DOWNTO 0);
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SIGNAL DSP_SRCSn : STD_LOGIC;
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SIGNAL DSP_SRBLEn : STD_LOGIC;
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SIGNAL DSP_SRBHEn : STD_LOGIC;
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SIGNAL DSP_SRWEn : STD_LOGIC;
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SIGNAL DSP_SROEn : STD_LOGIC;
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SIGNAL ide_int : STD_LOGIC;
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SIGNAL ide_rdy : STD_LOGIC;
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SIGNAL ide_res : STD_LOGIC;
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SIGNAL IDE_WRn : STD_LOGIC;
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SIGNAL IDE_RDn : STD_LOGIC;
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SIGNAL IDE_CSn : STD_LOGIC_VECTOR (1 DOWNTO 0);
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BEGIN
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I_FIREBEE : firebee
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PORT MAP (
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rsto_mcf_n => rsto_mcf_n,
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clk_33m => clk_33m,
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clk_main => clk_main,
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clk_24m576 => clk_24m576,
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clk_25m => clk_25m,
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clk_ddr_out => clk_ddr_out,
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clk_ddr_out_n => clk_ddr_out_n,
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clk_usb => clk_usb,
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fb_ad => fb_ad,
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fb_ale => fb_ale,
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fb_burst_n => fb_burst_n,
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fb_cs_n => fb_cs_n,
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fb_size => fb_size,
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fb_oe_n => fb_oe_n,
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fb_wr_n => fb_wr_n,
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fb_ta_n => fb_ta_n,
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dack1_n => dack1_n,
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dreq1_n => dreq1_n,
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master_n => master_n,
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tout0_n => tout0_n,
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led_fpga_ok => led_fpga_ok,
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reserved_1 => reserved_1,
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va => va,
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ba => ba,
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vwe_n => vwe_n,
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vcas_n => vcas_n,
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vras_n => vras_n,
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vcs_n => vcs_n,
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clk_pixel => clk_pixel,
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sync_n => sync_n,
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vsync => vsync,
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hsync => hsync,
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blank_n => blank_n,
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vr => vr,
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vg => vg,
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vb => vb,
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vdm => vdm,
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vd => vd,
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vd_qs => vd_qs,
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pd_vga_n => pd_vga_n,
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vcke => vcke,
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pic_int => pic_int,
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e0_int => e0_int,
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dvi_int => dvi_int,
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pci_inta_n => pci_inta_n,
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pci_intb_n => pci_intb_n,
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pci_intc_n => pci_intc_n,
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pci_intd_n => pci_intd_n,
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irq_n => irq_n,
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tin0 => tin0,
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ym_qa => ym_qa,
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ym_qb => ym_qb,
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ym_qc => ym_qc,
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lp_d => lp_d,
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lp_dir => lp_dir,
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dsa_d => dsa_d,
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lp_str => lp_str,
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dtr => dtr,
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rts => rts,
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cts => cts,
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ri => ri,
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dcd => dcd,
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lp_busy => lp_busy,
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rxd => rxd,
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txd => txd,
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midi_in => midi_in,
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midi_olr => midi_olr,
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midi_tlr => midi_tlr,
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pic_amkb_rx => pic_amkb_rx,
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amkb_rx => amkb_rx,
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amkb_tx => amkb_tx,
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dack0_n => dack0_n,
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scsi_drqn => scsi_drqn,
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SCSI_MSGn => scsi_msgn,
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SCSI_CDn => scsi_cdn,
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SCSI_IOn => scsi_ion,
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SCSI_ACKn => scsi_ackn,
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SCSI_ATNn => scsi_atnn,
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SCSI_SELn => scsi_seln,
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SCSI_BUSYn => scsi_busyn,
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SCSI_RSTn => scsi_rstn,
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SCSI_DIR => scsi_dir,
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SCSI_D => scsi_d,
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SCSI_PAR => scsi_par,
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ACSI_DIR => acsi_dir,
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ACSI_D => acsi_d,
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ACSI_CSn => acsi_csn,
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ACSI_A1 => acsi_a1,
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ACSI_reset_n => acsi_reset_n,
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ACSI_ACKn => acsi_ackn,
|
|
ACSI_DRQn => acsi_drqn,
|
|
ACSI_INTn => acsi_intn,
|
|
FDD_DCHGn => fdd_dchgn,
|
|
FDD_SDSELn => fdd_sdseln,
|
|
FDD_HD_DD => fdd_hd_dd,
|
|
FDD_RDn => fdd_rdn,
|
|
FDD_TRACK00 => fdd_track00,
|
|
FDD_INDEXn => fdd_indexn,
|
|
FDD_WPn => fdd_wpn,
|
|
FDD_MOT_ON => fdd_mot_on,
|
|
FDD_WR_GATE => fdd_wr_gate,
|
|
FDD_WDn => fdd_wdn,
|
|
FDD_STEP => fdd_step,
|
|
FDD_STEP_DIR => fdd_step_dir,
|
|
ROM4n => rom4n,
|
|
ROM3n => rom3n,
|
|
RP_UDSn => rp_udsn,
|
|
RP_ldsn => rp_ldsn,
|
|
SD_CLK => sd_clk,
|
|
SD_D3 => sd_d3,
|
|
SD_CMD_D1 => sd_cmd_d1,
|
|
SD_D0 => sd_d0,
|
|
SD_D1 => sd_d1,
|
|
SD_D2 => sd_d2,
|
|
SD_caRD_DETECT => sd_card_detect,
|
|
SD_WP => sd_wp,
|
|
CF_WP => cf_wp,
|
|
CF_CSn => cf_csn,
|
|
DSP_IO => dsp_io,
|
|
DSP_SRD => dsp_srd,
|
|
DSP_SRCSn => dsp_srcsn,
|
|
DSP_SRBLEn => dsp_srblen,
|
|
DSP_SRBHEn => dsp_srbhen,
|
|
DSP_SRWEn => dsp_srwen,
|
|
DSP_SROEn => dsp_sroen,
|
|
ide_int => ide_int,
|
|
ide_rdy => ide_rdy,
|
|
ide_res => ide_res,
|
|
IDE_WRn => ide_wrn,
|
|
IDE_RDn => ide_rdn,
|
|
IDE_CSn => ide_csn
|
|
);
|
|
|
|
I_DDR_1 : ddr_ram_model
|
|
PORT MAP
|
|
(
|
|
clk => clk_ddr_out,
|
|
clkb => clk_ddr_out_n,
|
|
cke => vcke,
|
|
csb => vcs_n,
|
|
rasb => vras_n,
|
|
casb => vcas_n,
|
|
web => vwe_n,
|
|
ba => UNSIGNED(ba),
|
|
ad => va (12 DOWNTO 0),
|
|
dqi => vd (30 DOWNTO 15),
|
|
dm => UNSIGNED(vdm (3 DOWNTO 2)),
|
|
dqs => vd_qs (3 DOWNTO 2)
|
|
);
|
|
END beh; |