Markus Fröschle 766d75a5d3 fixed pin assignments for renamed pins fb_cs_n[..]

2014-12-23 22:35:03 +00:00

..

backend/Altera/Firebee

fixed pin assignments for renamed pins fb_cs_n[..]

2014-12-23 22:35:03 +00:00

rtl/vhdl

added testbench files

2014-12-23 18:25:15 +00:00

testbenches

started implementing SAMSUNG's Verilog DDR model in VHDL

2014-12-23 22:30:23 +00:00