make FireTOS always cold boot (clear sys vars)

bump version
disabled debug output. This is version 0.88, "official" release
2016-08-14 09:55:28 +00:00 · 2016-08-14 09:09:12 +00:00 · 2016-08-14 08:16:20 +00:00 · 2016-08-02 08:45:26 +00:00 · 2016-07-31 19:13:16 +00:00 · 2016-07-30 09:55:11 +00:00
184 changed files with 68699 additions and 59913 deletions
--- a/BaS_gcc.config
+++ b/BaS_gcc.config
@@ -1 +1,2 @@
 // ADD PREDEFINED MACROS HERE!
+#define MACHINE_FIREBEE
--- a/BaS_gcc.files
+++ b/BaS_gcc.files
@@ -185,10 +185,6 @@ usb/usb_kbd.c
 tos/jtagwait/sources/bas_printf.c
 tos/jtagwait/sources/bas_string.c
 tos/vmem_test/Makefile
-tos/vmem_test/sources/bas_printf.c
-tos/vmem_test/sources/bas_string.c
-tos/vmem_test/sources/printf_helper.S
-tos/vmem_test/sources/vmem_test.c
 sys/startcf.S
 sys/exceptions.S
 util/bas_printf.c
@@ -198,3 +194,541 @@ util/wait.c
 bas.lk.in
 i2c/i2c.c
 Makefile
+x86emu/x86biosemu.c
+x86emu/x86emu.c
+x86emu/x86pcibios.c
+util/libgcc_helper.S
+util/setjmp.c
+util/setjmp.S
+include/x86emu_regs.h
+x86emu/x86emu_util.c
+include/setjmp.h
+video/video.c
+video/fbmem.c
+video/fbmodedb.c
+video/fbmon.c
+video/fnt_st_8x16.c
+video/offscreen.c
+video/vdi_fill.c
+video/videl.c
+video/video.c
+tos/jtagwait/Makefile
+tos/Makefile
+dma/dma.c
+dma/MCD_dmaApi.c
+dma/MCD_tasks.c
+dma/MCD_tasksInit.c
+exe/basflash.c
+exe/basflash_start.c
+firebee/bas.elf
+firebee/bas.lk
+firebee/bas.map
+firebee/bas.s19
+firebee/basflash.elf
+firebee/basflash.map
+firebee/basflash.s19
+firebee/bashflash.lk
+firebee/depend
+firebee/ram.elf
+firebee/ram.lk
+firebee/ram.s19
+flash/flash.c
+flash/s19reader.c
+flash_scripts/flash_firebee_bas.bdm
+flash_scripts/flash_firebee_etos.bdm
+flash_scripts/flash_firebee_firetos.bdm
+flash_scripts/flash_firebee_fpga.bdm
+flash_scripts/flash_m548x_bas.bdm
+flash_scripts/flash_m548x_dbug.bdm
+flash_scripts/flash_m548x_etos.bdm
+fs/cc932.c
+fs/cc936.c
+fs/cc949.c
+fs/cc950.c
+fs/ccsbcs.c
+fs/ff.c
+fs/unicode.c
+i2c/i2c.c
+if/driver_vec.c
+include/acia.h
+include/am79c874.h
+include/arp.h
+include/ati_ids.h
+include/bas_printf.h
+include/bas_string.h
+include/bas_types.h
+include/bas_utils.h
+include/bcm5222.h
+include/bootp.h
+include/cache.h
+include/diskio.h
+include/dma.h
+include/driver_mem.h
+include/driver_vec.h
+include/edid.h
+include/ehci.h
+include/eth.h
+include/exceptions.h
+include/fb.h
+include/fec.h
+include/fecbd.h
+include/ff.h
+include/ffconf.h
+include/firebee.h
+include/font.h
+include/i2c-algo-bit.h
+include/i2c.h
+include/icmp.h
+include/ikbd.h
+include/interrupts.h
+include/ip.h
+include/m54455.h
+include/m5484l.h
+include/MCD_dma.h
+include/mcd_initiators.h
+include/MCD_progCheck.h
+include/MCD_tasksInit.h
+include/MCF5475.h
+include/MCF5475_CLOCK.h
+include/MCF5475_CTM.h
+include/MCF5475_DMA.h
+include/MCF5475_DSPI.h
+include/MCF5475_EPORT.h
+include/MCF5475_FBCS.h
+include/MCF5475_FEC.h
+include/MCF5475_GPIO.h
+include/MCF5475_GPT.h
+include/MCF5475_I2C.h
+include/MCF5475_INTC.h
+include/MCF5475_MMU.h
+include/MCF5475_PAD.h
+include/MCF5475_PCI.h
+include/MCF5475_PCIARB.h
+include/MCF5475_PSC.h
+include/MCF5475_SDRAMC.h
+include/MCF5475_SEC.h
+include/MCF5475_SIU.h
+include/MCF5475_SLT.h
+include/MCF5475_SRAM.h
+include/MCF5475_USB.h
+include/MCF5475_XLB.h
+include/mmu.h
+include/mod_devicetable.h
+include/nbuf.h
+include/net.h
+include/net_timer.h
+include/nif.h
+include/ohci.h
+include/part.h
+include/pci.h
+include/pci_ids.h
+include/queue.h
+include/radeon_reg.h
+include/radeonfb.h
+include/s19reader.h
+include/screen.h
+include/sd_card.h
+include/setjmp.h
+include/startcf.h
+include/sysinit.h
+include/tftp.h
+include/udp.h
+include/usb.h
+include/usb_defs.h
+include/usb_hub.h
+include/user_io.h
+include/util.h
+include/version.h
+include/videl.h
+include/video.h
+include/wait.h
+include/x86emu.h
+include/x86emu_regs.h
+include/x86pcibios.h
+include/xhdi_sd.h
+kbd/ikbd.c
+m54455/bas.elf
+m54455/bas.lk
+m54455/bas.map
+m54455/bas.s19
+m54455/basflash.elf
+m54455/basflash.map
+m54455/basflash.s19
+m54455/bashflash.lk
+m54455/depend
+m54455/ram.elf
+m54455/ram.lk
+m54455/ram.s19
+m5484lite/bas.elf
+m5484lite/bas.lk
+m5484lite/bas.map
+m5484lite/bas.s19
+m5484lite/basflash.elf
+m5484lite/basflash.map
+m5484lite/basflash.s19
+m5484lite/bashflash.lk
+m5484lite/depend
+m5484lite/ram.elf
+m5484lite/ram.lk
+m5484lite/ram.s19
+net/am79c874.c
+net/arp.c
+net/bcm5222.c
+net/bootp.c
+net/fec.c
+net/fecbd.c
+net/ip.c
+net/nbuf.c
+net/net_timer.c
+net/nif.c
+net/queue.c
+net/tftp.c
+net/udp.c
+nutil/s19header.c
+pci/ehci-hcd.c
+pci/ohci-hcd.c
+pci/pci.c
+pci/pci_wrappers.S
+radeon/radeon_accel.c
+radeon/radeon_base.c
+radeon/radeon_cursor.c
+radeon/radeon_monitor.c
+spi/dspi.c
+spi/mmc.c
+spi/sd_card.c
+sys/BaS.c
+sys/cache.c
+sys/driver_mem.c
+sys/exceptions.S
+sys/fault_vectors.c
+sys/init_fpga.c
+sys/interrupts.c
+sys/mmu.c
+sys/startcf.S
+sys/sysinit.c
+tos/bascook/sources/bascook.c
+tos/bascook/bascook.prg
+tos/bascook/depend
+tos/bascook/Makefile
+tos/bascook/mapfile
+tos/jtagwait/include/bas_printf.h
+tos/jtagwait/include/bas_string.h
+tos/jtagwait/include/driver_vec.h
+tos/jtagwait/include/MCF5475.h
+tos/jtagwait/include/MCF5475_CLOCK.h
+tos/jtagwait/include/MCF5475_CTM.h
+tos/jtagwait/include/MCF5475_DMA.h
+tos/jtagwait/include/MCF5475_DSPI.h
+tos/jtagwait/include/MCF5475_EPORT.h
+tos/jtagwait/include/MCF5475_FBCS.h
+tos/jtagwait/include/MCF5475_FEC.h
+tos/jtagwait/include/MCF5475_GPIO.h
+tos/jtagwait/include/MCF5475_GPT.h
+tos/jtagwait/include/MCF5475_I2C.h
+tos/jtagwait/include/MCF5475_INTC.h
+tos/jtagwait/include/MCF5475_MMU.h
+tos/jtagwait/include/MCF5475_PAD.h
+tos/jtagwait/include/MCF5475_PCI.h
+tos/jtagwait/include/MCF5475_PCIARB.h
+tos/jtagwait/include/MCF5475_PSC.h
+tos/jtagwait/include/MCF5475_SDRAMC.h
+tos/jtagwait/include/MCF5475_SEC.h
+tos/jtagwait/include/MCF5475_SIU.h
+tos/jtagwait/include/MCF5475_SLT.h
+tos/jtagwait/include/MCF5475_SRAM.h
+tos/jtagwait/include/MCF5475_USB.h
+tos/jtagwait/include/MCF5475_XLB.h
+tos/jtagwait/m5475/mshort/jtagwait.prg
+tos/jtagwait/m5475/jtagwait.prg
+tos/jtagwait/sources/bas_printf.c
+tos/jtagwait/sources/bas_string.c
+tos/jtagwait/sources/jtagwait.c
+tos/jtagwait/sources/printf_helper.S
+tos/jtagwait/depend
+tos/jtagwait/jtagwait.config
+tos/jtagwait/jtagwait.creator
+tos/jtagwait/jtagwait.creator.user
+tos/jtagwait/jtagwait.files
+tos/jtagwait/jtagwait.includes
+tos/jtagwait/Makefile
+tos/jtagwait/mapfile
+tos/pci_test/include/bas_printf.h
+tos/pci_test/include/bas_string.h
+tos/pci_test/include/driver_vec.h
+tos/pci_test/include/MCF5475.h
+tos/pci_test/include/MCF5475_CLOCK.h
+tos/pci_test/include/MCF5475_CTM.h
+tos/pci_test/include/MCF5475_DMA.h
+tos/pci_test/include/MCF5475_DSPI.h
+tos/pci_test/include/MCF5475_EPORT.h
+tos/pci_test/include/MCF5475_FBCS.h
+tos/pci_test/include/MCF5475_FEC.h
+tos/pci_test/include/MCF5475_GPIO.h
+tos/pci_test/include/MCF5475_GPT.h
+tos/pci_test/include/MCF5475_I2C.h
+tos/pci_test/include/MCF5475_INTC.h
+tos/pci_test/include/MCF5475_MMU.h
+tos/pci_test/include/MCF5475_PAD.h
+tos/pci_test/include/MCF5475_PCI.h
+tos/pci_test/include/MCF5475_PCIARB.h
+tos/pci_test/include/MCF5475_PSC.h
+tos/pci_test/include/MCF5475_SDRAMC.h
+tos/pci_test/include/MCF5475_SEC.h
+tos/pci_test/include/MCF5475_SIU.h
+tos/pci_test/include/MCF5475_SLT.h
+tos/pci_test/include/MCF5475_SRAM.h
+tos/pci_test/include/MCF5475_USB.h
+tos/pci_test/include/MCF5475_XLB.h
+tos/pci_test/m5475/mshort/pci_test.prg
+tos/pci_test/m5475/pci_test.prg
+tos/pci_test/sources/bas_printf.c
+tos/pci_test/sources/bas_string.c
+tos/pci_test/sources/pci_test.c
+tos/pci_test/sources/printf_helper.S
+tos/pci_test/depend
+tos/pci_test/Makefile
+tos/pci_test/mapfile
+tos/pci_test/pci_test.config
+tos/pci_test/pci_test.creator
+tos/pci_test/pci_test.files
+tos/pci_test/pci_test.includes
+tos/vmem_test/include/bas_printf.h
+tos/vmem_test/include/bas_string.h
+tos/vmem_test/include/driver_vec.h
+tos/vmem_test/include/MCF5475.h
+tos/vmem_test/include/MCF5475_CLOCK.h
+tos/vmem_test/include/MCF5475_CTM.h
+tos/vmem_test/include/MCF5475_DMA.h
+tos/vmem_test/include/MCF5475_DSPI.h
+tos/vmem_test/include/MCF5475_EPORT.h
+tos/vmem_test/include/MCF5475_FBCS.h
+tos/vmem_test/include/MCF5475_FEC.h
+tos/vmem_test/include/MCF5475_GPIO.h
+tos/vmem_test/include/MCF5475_GPT.h
+tos/vmem_test/include/MCF5475_I2C.h
+tos/vmem_test/include/MCF5475_INTC.h
+tos/vmem_test/include/MCF5475_MMU.h
+tos/vmem_test/include/MCF5475_PAD.h
+tos/vmem_test/include/MCF5475_PCI.h
+tos/vmem_test/include/MCF5475_PCIARB.h
+tos/vmem_test/include/MCF5475_PSC.h
+tos/vmem_test/include/MCF5475_SDRAMC.h
+tos/vmem_test/include/MCF5475_SEC.h
+tos/vmem_test/include/MCF5475_SIU.h
+tos/vmem_test/include/MCF5475_SLT.h
+tos/vmem_test/include/MCF5475_SRAM.h
+tos/vmem_test/include/MCF5475_USB.h
+tos/vmem_test/include/MCF5475_XLB.h
+tos/vmem_test/m5475/mshort/vmem_test.prg
+tos/vmem_test/m5475/vmem_test.prg
+tos/vmem_test/Makefile
+tos/vmem_test/mapfile
+tos/vmem_test/vmem_test.config
+tos/vmem_test/vmem_test.creator
+tos/vmem_test/vmem_test.files
+tos/vmem_test/vmem_test.includes
+tos/Makefile
+usb/usb.c
+usb/usb_hub.c
+usb/usb_kbd.c
+usb/usb_mouse.c
+util/bas_printf.c
+util/bas_string.c
+util/libgcc_helper.S
+util/printf_helper.S
+util/setjmp.S
+util/wait.c
+video/fbmem.c
+video/fbmodedb.c
+video/fbmon.c
+video/fnt_st_8x16.c
+video/offscreen.c
+video/vdi_fill.c
+video/videl.c
+video/video.c
+x86emu/x86biosemu.c
+x86emu/x86emu.c
+x86emu/x86emu_util.c
+x86emu/x86pcibios.c
+xhdi/xhdi_interface.c
+xhdi/xhdi_sd.c
+xhdi/xhdi_vec.S
+bas.lk.in
+bas_firebee.bdm
+BaS_gcc.config
+BaS_gcc.creator
+BaS_gcc.creator.user
+BaS_gcc.creator.user.3.2-pre1
+BaS_gcc.creator.user.ori
+BaS_gcc.files
+BaS_gcc.includes
+bas_m5484.bdm
+basflash.lk.in
+check.bdm
+COPYING
+COPYING.LESSER
+Doxyfile
+dump.bdm
+Makefile
+mcf5474.gdb
+svn-commit.tmp
+tos/pci_test/include/bas_printf.h
+tos/pci_test/include/bas_string.h
+tos/pci_test/include/driver_vec.h
+tos/pci_test/include/MCF5475_CLOCK.h
+tos/pci_test/include/MCF5475_CTM.h
+tos/pci_test/include/MCF5475_DMA.h
+tos/pci_test/include/MCF5475_DSPI.h
+tos/pci_test/include/MCF5475_EPORT.h
+tos/pci_test/include/MCF5475_FBCS.h
+tos/pci_test/include/MCF5475_FEC.h
+tos/pci_test/include/MCF5475_GPIO.h
+tos/pci_test/include/MCF5475_GPT.h
+tos/pci_test/include/MCF5475_I2C.h
+tos/pci_test/include/MCF5475_INTC.h
+tos/pci_test/include/MCF5475_MMU.h
+tos/pci_test/include/MCF5475_PAD.h
+tos/pci_test/include/MCF5475_PCI.h
+tos/pci_test/include/MCF5475_PCIARB.h
+tos/pci_test/include/MCF5475_PSC.h
+tos/pci_test/include/MCF5475_SDRAMC.h
+tos/pci_test/include/MCF5475_SEC.h
+tos/pci_test/include/MCF5475_SIU.h
+tos/pci_test/include/MCF5475_SLT.h
+tos/pci_test/include/MCF5475_SRAM.h
+tos/pci_test/include/MCF5475_USB.h
+tos/pci_test/include/MCF5475_XLB.h
+tos/pci_test/include/MCF5475.h
+tos/pci_test/include/pci.h
+memory_map.txt
+pci/pci_errata.c
+include/pci_errata.h
+tos/bascook/sources/bascook.c
+tos/bascook/Makefile
+tos/fpga_test/include/bas_printf.h
+tos/fpga_test/include/bas_string.h
+tos/fpga_test/include/driver_vec.h
+tos/fpga_test/include/MCF5475.h
+tos/fpga_test/include/MCF5475_CLOCK.h
+tos/fpga_test/include/MCF5475_CTM.h
+tos/fpga_test/include/MCF5475_DMA.h
+tos/fpga_test/include/MCF5475_DSPI.h
+tos/fpga_test/include/MCF5475_EPORT.h
+tos/fpga_test/include/MCF5475_FBCS.h
+tos/fpga_test/include/MCF5475_FEC.h
+tos/fpga_test/include/MCF5475_GPIO.h
+tos/fpga_test/include/MCF5475_GPT.h
+tos/fpga_test/include/MCF5475_I2C.h
+tos/fpga_test/include/MCF5475_INTC.h
+tos/fpga_test/include/MCF5475_MMU.h
+tos/fpga_test/include/MCF5475_PAD.h
+tos/fpga_test/include/MCF5475_PCI.h
+tos/fpga_test/include/MCF5475_PCIARB.h
+tos/fpga_test/include/MCF5475_PSC.h
+tos/fpga_test/include/MCF5475_SDRAMC.h
+tos/fpga_test/include/MCF5475_SEC.h
+tos/fpga_test/include/MCF5475_SIU.h
+tos/fpga_test/include/MCF5475_SLT.h
+tos/fpga_test/include/MCF5475_SRAM.h
+tos/fpga_test/include/MCF5475_USB.h
+tos/fpga_test/include/MCF5475_XLB.h
+tos/fpga_test/sources/bas_printf.c
+tos/fpga_test/sources/bas_string.c
+tos/fpga_test/sources/printf_helper.S
+tos/fpga_test/Makefile
+tos/jtagwait/include/bas_printf.h
+tos/jtagwait/include/bas_string.h
+tos/jtagwait/include/driver_vec.h
+tos/jtagwait/include/MCF5475.h
+tos/jtagwait/include/MCF5475_CLOCK.h
+tos/jtagwait/include/MCF5475_CTM.h
+tos/jtagwait/include/MCF5475_DMA.h
+tos/jtagwait/include/MCF5475_DSPI.h
+tos/jtagwait/include/MCF5475_EPORT.h
+tos/jtagwait/include/MCF5475_FBCS.h
+tos/jtagwait/include/MCF5475_FEC.h
+tos/jtagwait/include/MCF5475_GPIO.h
+tos/jtagwait/include/MCF5475_GPT.h
+tos/jtagwait/include/MCF5475_I2C.h
+tos/jtagwait/include/MCF5475_INTC.h
+tos/jtagwait/include/MCF5475_MMU.h
+tos/jtagwait/include/MCF5475_PAD.h
+tos/jtagwait/include/MCF5475_PCI.h
+tos/jtagwait/include/MCF5475_PCIARB.h
+tos/jtagwait/include/MCF5475_PSC.h
+tos/jtagwait/include/MCF5475_SDRAMC.h
+tos/jtagwait/include/MCF5475_SEC.h
+tos/jtagwait/include/MCF5475_SIU.h
+tos/jtagwait/include/MCF5475_SLT.h
+tos/jtagwait/include/MCF5475_SRAM.h
+tos/jtagwait/include/MCF5475_USB.h
+tos/jtagwait/include/MCF5475_XLB.h
+tos/jtagwait/sources/bas_printf.c
+tos/jtagwait/sources/bas_string.c
+tos/jtagwait/sources/jtagwait.c
+tos/jtagwait/sources/printf_helper.S
+tos/jtagwait/Makefile
+tos/pci_test/include/bas_printf.h
+tos/pci_test/include/bas_string.h
+tos/pci_test/include/driver_vec.h
+tos/pci_test/include/MCF5475.h
+tos/pci_test/include/MCF5475_CLOCK.h
+tos/pci_test/include/MCF5475_CTM.h
+tos/pci_test/include/MCF5475_DMA.h
+tos/pci_test/include/MCF5475_DSPI.h
+tos/pci_test/include/MCF5475_EPORT.h
+tos/pci_test/include/MCF5475_FBCS.h
+tos/pci_test/include/MCF5475_FEC.h
+tos/pci_test/include/MCF5475_GPIO.h
+tos/pci_test/include/MCF5475_GPT.h
+tos/pci_test/include/MCF5475_I2C.h
+tos/pci_test/include/MCF5475_INTC.h
+tos/pci_test/include/MCF5475_MMU.h
+tos/pci_test/include/MCF5475_PAD.h
+tos/pci_test/include/MCF5475_PCI.h
+tos/pci_test/include/MCF5475_PCIARB.h
+tos/pci_test/include/MCF5475_PSC.h
+tos/pci_test/include/MCF5475_SDRAMC.h
+tos/pci_test/include/MCF5475_SEC.h
+tos/pci_test/include/MCF5475_SIU.h
+tos/pci_test/include/MCF5475_SLT.h
+tos/pci_test/include/MCF5475_SRAM.h
+tos/pci_test/include/MCF5475_USB.h
+tos/pci_test/include/MCF5475_XLB.h
+tos/pci_test/include/pci.h
+tos/pci_test/sources/bas_printf.c
+tos/pci_test/sources/bas_string.c
+tos/pci_test/sources/pci_test.c
+tos/pci_test/sources/printf_helper.S
+tos/pci_test/Makefile
+tos/vmem_test/include/bas_printf.h
+tos/vmem_test/include/bas_string.h
+tos/vmem_test/include/driver_vec.h
+tos/vmem_test/include/MCF5475.h
+tos/vmem_test/include/MCF5475_CLOCK.h
+tos/vmem_test/include/MCF5475_CTM.h
+tos/vmem_test/include/MCF5475_DMA.h
+tos/vmem_test/include/MCF5475_DSPI.h
+tos/vmem_test/include/MCF5475_EPORT.h
+tos/vmem_test/include/MCF5475_FBCS.h
+tos/vmem_test/include/MCF5475_FEC.h
+tos/vmem_test/include/MCF5475_GPIO.h
+tos/vmem_test/include/MCF5475_GPT.h
+tos/vmem_test/include/MCF5475_I2C.h
+tos/vmem_test/include/MCF5475_INTC.h
+tos/vmem_test/include/MCF5475_MMU.h
+tos/vmem_test/include/MCF5475_PAD.h
+tos/vmem_test/include/MCF5475_PCI.h
+tos/vmem_test/include/MCF5475_PCIARB.h
+tos/vmem_test/include/MCF5475_PSC.h
+tos/vmem_test/include/MCF5475_SDRAMC.h
+tos/vmem_test/include/MCF5475_SEC.h
+tos/vmem_test/include/MCF5475_SIU.h
+tos/vmem_test/include/MCF5475_SLT.h
+tos/vmem_test/include/MCF5475_SRAM.h
+tos/vmem_test/include/MCF5475_USB.h
+tos/vmem_test/include/MCF5475_XLB.h
+tos/vmem_test/sources/fpga_test.c
+tos/vmem_test/Makefile
+tos/Makefile
+tos/fpga_test/sources/fpga_test.c
--- a/BaS_gcc.includes
+++ b/BaS_gcc.includes
@@ -1,2 +1,49 @@
 include
-tos/jtagwait/include
+tos/jtagwait/include
+tos/pci_test/include
+/usr/m68k-atari-mint/include
+/opt/cross-mint/m68k-atari-mint/include
+/opt/gygwin/opt/cross-mint/m68k-atari-mint/include
+dma
+m54455
+sys
+pci
+tos/pci_test
+tos/jtagwait/m5475/mshort
+m5484lite
+tos/pci_test/include
+tos/bascook
+tos/vmem_test/m5475/mshort
+i2c
+fs
+tos/vmem_test/m5475
+tos/pci_test/m5475
+spi
+if
+tos/jtagwait/m5475
+util
+kbd
+flash_scripts
+video
+usb
+exe
+tos/vmem_test/sources
+tos
+nutil
+tos/jtagwait/sources
+x86emu
+flash
+tos/vmem_test/include
+tos/bascook/sources
+tos/pci_test/m5475/mshort
+.
+radeon
+net
+xhdi
+tos/vmem_test
+tos/pci_test/sources
+firebee
+tos/jtagwait
+tos/fpga_test/include
+tos/fpga_test
+tos/fpga_test/sources
--- a/2582
+++ b/2582
--- a/94
+++ b/94
@@ -3,6 +3,7 @@
 # This Makefile is meant for cross compiling the BaS with Vincent Riviere's cross compilers.
 # If you want to compile native on an Atari (you will need at least GCC 4.6.3), set
 # TCPREFIX to be empty.
+#
 # If you want to compile with the m68k-elf- toolchain, set TCPREFIX accordingly. Requires an extra
 # installation, but allows source level debugging over BDM with a recent gdb (tested with 7.5),
 # the m68k BDM tools from sourceforge (http://bdm.sourceforge.net) and a BDM pod (TBLCF and P&E tested).
@@ -29,26 +30,32 @@ AR=$(TCPREFIX)ar
 RANLIB=$(TCPREFIX)ranlib
 NATIVECC=gcc

+ifeq (Y,$(COMPILE_ELF))
+LDLIBS=-lgcc
+else
+LDLIBS=-lgcc
+endif
+
 INCLUDE=-Iinclude
-CFLAGS=-mcpu=5474 \
-        -g \
-		-Wall \
-		-fomit-frame-pointer \
-		-ffreestanding \
-		-fleading-underscore \
-		-mno-strict-align \
-		-Wa,--register-prefix-optional
+CFLAGS=	-Wall \
+	-O2 \
+	-fomit-frame-pointer \
+	-ffreestanding \
+	-fleading-underscore \
+	-Winline \
+	-Wshadow \
+	-Wa,--register-prefix-optional \
+	-g2
 CFLAGS_OPTIMIZED = -mcpu=5474 \
 		-Wall \
 		-O2 \
-		-g \
 		-fomit-frame-pointer \
 		-ffreestanding \
 		-fleading-underscore \
 		-Wa,--register-prefix-optional
-LDFLAGS=-g
+LDFLAGS=

-TRGTDIRS= ./firebee ./m5484lite ./m54455
+TRGTDIRS= ./firebee ./m54455 ./m5484lite
 OBJDIRS=$(patsubst %, %/objs,$(TRGTDIRS))
 TOOLDIR=util

@@ -85,16 +92,19 @@ CSRCS= \
 	s19reader.c \
 	flash.c \
 	dma.c \
-        i2c.c \
+	i2c.c \
 	xhdi_sd.c \
 	xhdi_interface.c \
 	pci.c \
+	pci_errata.c \
 	dspi.c \
 	driver_vec.c \
 	driver_mem.c \
+	\
 	MCD_dmaApi.c \
 	MCD_tasks.c \
 	MCD_tasksInit.c \
+	\
 	usb.c \
 	ohci-hcd.c \
 	ehci-hcd.c \
@@ -131,15 +141,10 @@ CSRCS= \
 	radeon_monitor.c \
 	fnt_st_8x16.c \
 	\
-	x86decode.c \
-	x86sys.c \
-	x86debug.c \
-	x86prim_ops.c \
-	x86ops.c \
-	x86ops2.c \
-	x86fpu.c \
-	x86biosemu.c \
+	x86emu.c \
 	x86pcibios.c \
+	x86biosemu.c \
+	x86emu_util.c \
 	\
 	basflash.c \
 	basflash_start.c
@@ -149,9 +154,14 @@ ASRCS= \
 	startcf.S \
 	printf_helper.S \
 	exceptions.S \
+	setjmp.S \
 	xhdi_vec.S \
 	pci_wrappers.S

+ifeq (Y,$(COMPILE_ELF))			# needed for __ vs ___ kludge
+	ASRCS += libgcc_helper.S
+endif
+
 SRCS=$(ASRCS) $(CSRCS)
 COBJS=$(patsubst %.c,%.o,$(CSRCS))
 AOBJS=$(patsubst %.S,%.o,$(ASRCS))
@@ -172,7 +182,7 @@ ver:
 	touch include/version.h
 .PHONY: tos
 tos:
-	(cd tos; make)
+	(cd tos; $(MAKE))

 .PHONY: clean
 clean:
@@ -180,40 +190,39 @@ clean:
 		do rm -f $$d/*.map $$d/*.s19 $$d/*.elf $$d/*.lk $$d/*.a $$d/objs/* $$d/depend;\
 	done
 	rm -f tags
+	(cd tos; make clean)
+


 # flags for targets
 m5484lite/bas.$(EXE): MACHINE=MACHINE_M5484LITE
 m54455/bas.$(EXE): MACHINE=MACHINE_M54455
 firebee/bas.$(EXE): MACHINE=MACHINE_FIREBEE
+
 m5484lite/ram.$(EXE): MACHINE=MACHINE_M5484LITE
 m54455/ram.$(EXE): MACHINE=MACHINE_M54455
 firebee/ram.$(EXE): MACHINE=MACHINE_FIREBEE
+
 m5484lite/basflash.$(EXE): MACHINE=MACHINE_M5484LITE
 m54455/basflash.$(EXE): MACHINE=MACHINE_M54455
 firebee/basflash.$(EXE): MACHINE=MACHINE_FIREBEE

+m5484lite/bas.$(EXE): CFLAGS += -mcpu=5484
+m54455/bas.$(EXE): CFLAGS += -mcpu=54455 -msoft-float
+firebee/bas.$(EXE): CFLAGS += -mcpu=5474
+
+m5484lite/ram.$(EXE): CFLAGS += -mcpu=5484
+m54455/ram.$(EXE): CFLAGS += -mcpu=54455 -msoft-float
+firebee/ram.$(EXE): CFLAGS += -mcpu=5474
+
+m5484lite/basflash.$(EXE): CFLAGS += -mcpu=5484
+m54455/basflash.$(EXE): CFLAGS += -mcpu=54455 -msoft-float
+firebee/basflash.$(EXE): CFLAGS += -mcpu=5474
+
 #
 # generate pattern rules for different object files
 #
 define CC_TEMPLATE
-#ifeq (firebee,$(1))
-	#MACHINE=MACHINE_FIREBEE
-#else
-	#MACHINE=MACHINE_M5484LITE
-#endif
-
-# always optimize x86 emulator objects
-#$(1)/objs/x86decode.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
-#$(1)/objs/x86sys.o:		CFLAGS=$(CFLAGS_OPTIMIZED)
-#$(1)/objs/x86debug.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
-#$(1)/objs/x86prim_ops.o:CFLAGS=$(CFLAGS_OPTIMIZED)
-#$(1)/objs/x86ops.o:		CFLAGS=$(CFLAGS_OPTIMIZED)
-#$(1)/objs/x86ops2.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
-#$(1)/objs/x86fpu.o:		CFLAGS=$(CFLAGS_OPTIMIZED)
-#$(1)/objs/x86biosemu.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
-#$(1)/objs/x86pcibios.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
-
 $(1)/objs/%.o:%.c
 	$(CC) $$(CFLAGS) -D$$(MACHINE) $(INCLUDE) -c $$< -o $$@

@@ -263,7 +272,8 @@ define EX_TEMPLATE
 $(1)_MAPFILE=$(1)/$$(basename $$(FLASH_EXEC)).map
 $(1)/$$(FLASH_EXEC): $(1)/$(LIBBAS) $(LDCSRC)
 	$(CPP) $(INCLUDE) -DOBJDIR=$(1)/objs -P -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCSRC) -o $(1)/$$(LDCFILE)
-	$(LD) --oformat $$(FORMAT) -Map $$($(1)_MAPFILE) --cref -T $(1)/$$(LDCFILE) -o $$@
+	#$(LD) --oformat $$(FORMAT) -Map $$($(1)_MAPFILE) --cref -T $(1)/$$(LDCFILE) $(LDLIBS) -o $$@
+	$(CC) $$(CFLAGS) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDCFILE) $(LDLIBS) -o $$@
 ifeq ($(COMPILE_ELF),Y)
 	$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
 else
@@ -274,7 +284,8 @@ endif
 $(1)_MAPFILE_RAM=$(1)/$$(basename $$(RAM_EXEC)).map
 $(1)/$$(RAM_EXEC): $(1)/$(LIBBAS) $(LDCSRC)
 	$(CPP) $(INCLUDE) -DCOMPILE_RAM -DOBJDIR=$(1)/objs -P -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCSRC) -o $(1)/$$(LDRFILE)
-	$(LD) $(LDFLAGS) --oformat $$(FORMAT) -Map $$($(1)_MAPFILE_RAM) --cref -T $(1)/$$(LDRFILE) -o $$@
+	#$(LD) $(LDFLAGS) --oformat $$(FORMAT) -Map $$($(1)_MAPFILE_RAM) --cref -T $(1)/$$(LDRFILE) $(LDLIBS) -o $$@
+	$(CC) $$(CFLAGS) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE_RAM) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDRFILE) $(LDLIBS) -o $$@
 ifeq ($(COMPILE_ELF),Y)
 	$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
 else
@@ -285,7 +296,8 @@ endif
 $(1)_MAPFILE_BFL=$(1)/$$(basename $$(BASFLASH_EXEC)).map
 $(1)/$$(BASFLASH_EXEC): $(1)/objs/basflash.o $(1)/objs/basflash_start.o $(1)/$(LIBBAS) $(LDCBFL)
 	$(CPP) $(INCLUDE) -P -DOBJDIR=$(1)/objs -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCBSRC) -o $(1)/$$(LDCBFS)
-	$(LD) --oformat $$(FORMAT) -Map $$($(1)_MAPFILE_BFL) --cref -T $(1)/$$(LDCFILE) -L$(1) -lbas -o $$@
+	#$(LD) --oformat $$(FORMAT) -Map $$($(1)_MAPFILE_BFL) --cref -T $(1)/$$(LDCFILE) -L$(1) -lbas $(LDLIBS) -o $$@
+	$(CC) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE_BFL) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDCFILE) -L$(1) -lbas $(LDLIBS) -o $$@
 ifeq ($(COMPILE_ELF),Y)
 	$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
 else
--- a/bas.lk.in
+++ b/bas.lk.in
@@ -1,7 +1,7 @@
 #if defined(MACHINE_FIREBEE)
 #include "firebee.h"
 #elif defined(MACHINE_M5484LITE)
-#include "m5484l.h"
+#    include "m5484l.h"
 #elif defined(MACHINE_M54455)
 #include "m54455.h"
 #else
@@ -42,12 +42,15 @@ SECTIONS
 #endif /* MACHINE_FIREBEE */
                OBJDIR/wait.o(.text)
                OBJDIR/exceptions.o(.text)
+                OBJDIR/setjmp.o(.text)
                OBJDIR/driver_vec.o(.text)
                OBJDIR/interrupts.o(.text)
                OBJDIR/mmu.o(.text)

                OBJDIR/BaS.o(.text)
                OBJDIR/pci.o(.text)
+                . = ALIGN(16);
+                OBJDIR/pci_errata.o(.text)
                OBJDIR/pci_wrappers.o(.text)
                OBJDIR/usb.o(.text)
                OBJDIR/driver_mem.o(.text)
@@ -79,6 +82,9 @@ SECTIONS
                OBJDIR/s19reader.o(.text)
                OBJDIR/bas_printf.o(.text)
                OBJDIR/bas_string.o(.text)
+#if (FORMAT_ELF == 1)
+                OBJDIR/libgcc_helper.o(.text)
+#endif
                OBJDIR/printf_helper.o(.text)
                OBJDIR/cache.o(.text)
                OBJDIR/dma.o(.text)
@@ -93,15 +99,10 @@ SECTIONS
                OBJDIR/fbmodedb.o(.text)
                OBJDIR/offscreen.o(.text)

-                OBJDIR/x86decode.o(.text)
-                OBJDIR/x86ops.o(.text)
-                OBJDIR/x86ops2.o(.text)
-                OBJDIR/x86fpu.o(.text)
-                OBJDIR/x86sys.o(.text)
-                OBJDIR/x86biosemu.o(.text)
-                OBJDIR/x86debug.o(.text)
-                OBJDIR/x86prim_ops.o(.text)
+                OBJDIR/x86emu.o(.text)
+                OBJDIR/x86emu_util.o(.text)
                OBJDIR/x86pcibios.o(.text)
+                OBJDIR/x86biosemu.o(.text)

                OBJDIR/radeon_base.o(.text)
                OBJDIR/radeon_accel.o(.text)
@@ -126,11 +127,13 @@ SECTIONS
 #endif /* COMPILE_RAM */

 #if (FORMAT_ELF == 1)
+                *(.eh_frame)
                *(.rodata)
                *(.rodata.*)
 #endif
        } > bas_rom

+
 #if (TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS)
        /*
         * put BaS .data and .bss segments to flash, but relocate it to RAM after initialize_hardware() ran
@@ -222,6 +225,7 @@ SECTIONS
        /* MMU memory mapped registers */
        __MMUBAR                = 0xFF040000;

+#if !defined(MACHINE_M54455)        /* MCF54455 does not have RAMBAR0 and RAMBAR1 registers */
        /*
         * 4KB on-chip Core SRAM0: -> exception table
         */
@@ -232,34 +236,43 @@ SECTIONS
        __RAMBAR1               = 0xFF101000;
        __RAMBAR1_SIZE          = 0x00001000;
        __SUP_SP                = __RAMBAR1 + __RAMBAR1_SIZE - 4;
+#else
+        __RAMBAR0               = 0x80000000;   /* RAMBAR must be between 0x80000000 on MCF54455 */
+        __RAMBAR0_SIZE          = 0x1000;
+        __SUP_SP                = __RAMBAR0 + __RAMBAR0_SIZE + 0x1000 - 4;
+#endif

    /*
-     * this flag (if 1) indicates that FPGA configuration has been loaded through JTAG
-     * and shouldn't be overwritten on boot
+     * FPGA_JTAG_LOADED (if 1) indicates that FPGA configuration has been loaded through JTAG
+     * and shouldn't be overwritten on boot. For this to work (and not let us be faked
+     * by a random uninitialised value), __FPGA_JTAG_VALID is used as a "magic value" and must be
+     * 0xaffeaffe to make this work.
     */
+#if !defined(MACHINE_M54455)        /* MCF54455 does not have RAMBAR0 and RAMBAR1 */
    __FPGA_JTAG_LOADED      = __RAMBAR1;
    __FPGA_JTAG_VALID       = __RAMBAR1 + 4;
+#else
+    __FPGA_JTAG_LOADED      = __RAMBAR0 + 0x1000;
+    __FPGA_JTAG_VALID       = __RAMBAR0 + 0x1000 + 4;
+#endif
+
    /* system variables */
-
-        /* system variables */
-
-        /* RAMBAR0 0 to 0x7FF -> exception vectors */
-        _rt_mod    = __RAMBAR0 + 0x800;
-        _rt_ssp    = __RAMBAR0 + 0x804;
-        _rt_usp    = __RAMBAR0 + 0x808;
-        _rt_vbr    = __RAMBAR0 + 0x80C;     /* (8)01 */
-        _rt_cacr   = __RAMBAR0 + 0x810;     /* 002 */
-        _rt_asid   = __RAMBAR0 + 0x814;     /* 003 */
-        _rt_acr0   = __RAMBAR0 + 0x818;     /* 004 */
-        _rt_acr1   = __RAMBAR0 + 0x81c;     /* 005 */
-        _rt_acr2   = __RAMBAR0 + 0x820;     /* 006 */
-        _rt_acr3   = __RAMBAR0 + 0x824;     /* 007 */
-        _rt_mmubar = __RAMBAR0 + 0x828;     /* 008 */
-        _rt_sr     = __RAMBAR0 + 0x82c;
-        _d0_save   = __RAMBAR0 + 0x830;
-        _a7_save   = __RAMBAR0 + 0x834;
-        _video_tlb = __RAMBAR0 + 0x838;
-        _video_sbt = __RAMBAR0 + 0x83C;
-        _rt_mbar   = __RAMBAR0 + 0x844;     /* (c)0f */
-
+    /* RAMBAR0 0 to 0x7FF -> exception vectors */
+    _rt_mod    = __RAMBAR0 + 0x800;
+    _rt_ssp    = __RAMBAR0 + 0x804;
+    _rt_usp    = __RAMBAR0 + 0x808;
+    _rt_vbr    = __RAMBAR0 + 0x80C;     /* (8)01 */
+    _rt_cacr   = __RAMBAR0 + 0x810;     /* 002 */
+    _rt_asid   = __RAMBAR0 + 0x814;     /* 003 */
+    _rt_acr0   = __RAMBAR0 + 0x818;     /* 004 */
+    _rt_acr1   = __RAMBAR0 + 0x81c;     /* 005 */
+    _rt_acr2   = __RAMBAR0 + 0x820;     /* 006 */
+    _rt_acr3   = __RAMBAR0 + 0x824;     /* 007 */
+    _rt_mmubar = __RAMBAR0 + 0x828;     /* 008 */
+    _rt_sr     = __RAMBAR0 + 0x82c;
+    _d0_save   = __RAMBAR0 + 0x830;
+    _a7_save   = __RAMBAR0 + 0x834;
+    _video_tlb = __RAMBAR0 + 0x838;
+    _video_sbt = __RAMBAR0 + 0x83C;
+    _rt_mbar   = __RAMBAR0 + 0x844;     /* (c)0f */
 }
--- a/dma/dma.c
+++ b/dma/dma.c
@@ -646,8 +646,8 @@ void *dma_memcpy(void *dst, void *src, size_t n)
 #ifdef DBG_DMA
    end = MCF_SLT0_SCNT;
    time = (start - end) / (SYSCLK / 1000) / 1000;
-#endif /* DBG_DMA */
    dbg("took %d ms (%f Mbytes/second)\r\n", time, n / (float) time / 1000.0);
+#endif /* DBG_DMA */

    return dst;
 }
--- a/flash/flash.c
+++ b/flash/flash.c
@@ -1,9 +1,9 @@
 #include <stddef.h>
 #include "bas_types.h"

-#if MACHINE_FIREBEE
+#if defined(MACHINE_FIREBEE)
 #include "firebee.h"
-#elif MACHINE_M5484LITE
+#elif defined(MACHINE_M5484LITE)
 #include "m5484l.h"
 #endif /* MACHINE_FIREBEE */

@@ -15,8 +15,8 @@

 struct amd_flash_sector_info
 {
-	uint32_t size; /* sector size in bytes */
-	uint32_t offset; /* offset from base of device */
+    uint32_t size; /* sector size in bytes */
+    uint32_t offset; /* offset from base of device */
 };

 /*
@@ -24,134 +24,134 @@ struct amd_flash_sector_info
 */
 static struct amd_flash_sector_info sector[] =
 {
-		{  8 * 1024, 0x00000000 }, /* SA0 */
-		{  8 * 1024, 0x00008000 }, /* SA1 */
-		{  8 * 1024, 0x00010000 }, /* SA2 */
-		{  8 * 1024, 0x00018000 }, /* SA3 */
-		{  8 * 1024, 0x00020000 }, /* SA4 */
-		{  8 * 1024, 0x00028000 }, /* SA5 */
-		{  8 * 1024, 0x00030000 }, /* SA6 */
-		{  8 * 1024, 0x00038000 }, /* SA7 */
-		{  8 * 1024, 0x00040000 }, /* SA8 */
-		{ 64 * 1024, 0x00048000 }, /* SA9 */
-		{ 64 * 1024, 0x00050000 }, /* SA10 */
-		{ 64 * 1024, 0x00058000 }, /* SA11 */
-		{ 64 * 1024, 0x00060000 }, /* SA12 */
-		{ 64 * 1024, 0x00068000 }, /* SA13 */
-		{ 64 * 1024, 0x00070000 }, /* SA14 */
-		{ 64 * 1024, 0x00078000 }, /* SA15 */
-		{ 64 * 1024, 0x00080000 }, /* SA16 */
-		{ 64 * 1024, 0x00088000 }, /* SA17 */
-		{ 64 * 1024, 0x00090000 }, /* SA18 */
-		{ 64 * 1024, 0x00098000 }, /* SA19 */
-		{ 64 * 1024, 0x000a0000 }, /* SA20 */
-		{ 64 * 1024, 0x000a8000 }, /* SA21 */
-		{ 64 * 1024, 0x000b0000 }, /* SA22 */
-		{ 64 * 1024, 0x000b8000 }, /* SA23 */
-		{ 64 * 1024, 0x000c0000 }, /* SA24 */
-		{ 64 * 1024, 0x000c8000 }, /* SA25 */
-		{ 64 * 1024, 0x000d0000 }, /* SA26 */
-		{ 64 * 1024, 0x000d8000 }, /* SA27 */
-		{ 64 * 1024, 0x000e0000 }, /* SA28 */
-		{ 64 * 1024, 0x000e8000 }, /* SA29 */
-		{ 64 * 1024, 0x000f0000 }, /* SA30 */
-		{ 64 * 1024, 0x000f8000 }, /* SA31 */
-		{ 64 * 1024, 0x00100000 }, /* SA32 */
-		{ 64 * 1024, 0x00108000 }, /* SA32 */
-		{ 64 * 1024, 0x00110000 }, /* SA34 */
-		{ 64 * 1024, 0x00118000 }, /* SA35 */
-		{ 64 * 1024, 0x00120000 }, /* SA36 */
-		{ 64 * 1024, 0x00128000 }, /* SA37 */
-		{ 64 * 1024, 0x00130000 }, /* SA38 */
-		{ 64 * 1024, 0x00138000 }, /* SA39 */
-		{ 64 * 1024, 0x00140000 }, /* SA40 */
-		{ 64 * 1024, 0x00148000 }, /* SA41 */
-		{ 64 * 1024, 0x00150000 }, /* SA42 */
-		{ 64 * 1024, 0x00158000 }, /* SA43 */
-		{ 64 * 1024, 0x00160000 }, /* SA44 */
-		{ 64 * 1024, 0x00168000 }, /* SA45 */
-		{ 64 * 1024, 0x00170000 }, /* SA46 */
-		{ 64 * 1024, 0x00178000 }, /* SA47 */
-		{ 64 * 1024, 0x00180000 }, /* SA48 */
-		{ 64 * 1024, 0x00188000 }, /* SA49 */
-		{ 64 * 1024, 0x00190000 }, /* SA50 */
-		{ 64 * 1024, 0x00198000 }, /* SA51 */
-		{ 64 * 1024, 0x001a0000 }, /* SA52 */
-		{ 64 * 1024, 0x001a8000 }, /* SA53 */
-		{ 64 * 1024, 0x001b0000 }, /* SA54 */
-		{ 64 * 1024, 0x001b8000 }, /* SA55 */
-		{ 64 * 1024, 0x001c0000 }, /* SA56 */
-		{ 64 * 1024, 0x001c8000 }, /* SA57 */
-		{ 64 * 1024, 0x001d0000 }, /* SA58 */
-		{ 64 * 1024, 0x001d8000 }, /* SA59 */
-		{ 64 * 1024, 0x001e0000 }, /* SA60 */
-		{ 64 * 1024, 0x001e8000 }, /* SA61 */
-		{ 64 * 1024, 0x001f0000 }, /* SA62 */
-		{ 64 * 1024, 0x001f8000 }, /* SA63 */
-		{ 64 * 1024, 0x00200000 }, /* SA64 */
-		{ 64 * 1024, 0x00208000 }, /* SA65 */
-		{ 64 * 1024, 0x00210000 }, /* SA66 */
-		{ 64 * 1024, 0x00218000 }, /* SA67 */
-		{ 64 * 1024, 0x00220000 }, /* SA68 */
-		{ 64 * 1024, 0x00228000 }, /* SA69 */
-		{ 64 * 1024, 0x00230000 }, /* SA70 */
-		{ 64 * 1024, 0x00238000 }, /* SA71 */
-		{ 64 * 1024, 0x00240000 }, /* SA72 */
-		{ 64 * 1024, 0x00248000 }, /* SA73 */
-		{ 64 * 1024, 0x00250000 }, /* SA74 */
-		{ 64 * 1024, 0x00258000 }, /* SA75 */
-		{ 64 * 1024, 0x00260000 }, /* SA76 */
-		{ 64 * 1024, 0x00268000 }, /* SA77 */
-		{ 64 * 1024, 0x00270000 }, /* SA78 */
-		{ 64 * 1024, 0x00278000 }, /* SA79 */
-		{ 64 * 1024, 0x00280000 }, /* SA80 */
-		{ 64 * 1024, 0x00288000 }, /* SA81 */
-		{ 64 * 1024, 0x00290000 }, /* SA82 */
-		{ 64 * 1024, 0x00298000 }, /* SA83 */
-		{ 64 * 1024, 0x002a0000 }, /* SA84 */
-		{ 64 * 1024, 0x002a8000 }, /* SA85 */
-		{ 64 * 1024, 0x002b0000 }, /* SA86 */
-		{ 64 * 1024, 0x002b8000 }, /* SA87 */
-		{ 64 * 1024, 0x002c0000 }, /* SA88 */
-		{ 64 * 1024, 0x002c8000 }, /* SA89 */
-		{ 64 * 1024, 0x002d0000 }, /* SA90 */
-		{ 64 * 1024, 0x002d8000 }, /* SA91 */
-		{ 64 * 1024, 0x002e0000 }, /* SA92 */
-		{ 64 * 1024, 0x002e8000 }, /* SA93 */
-		{ 64 * 1024, 0x002f0000 }, /* SA94 */
-		{ 64 * 1024, 0x002f8000 }, /* SA95 */
-		{ 64 * 1024, 0x00300000 }, /* SA96 */
-		{ 64 * 1024, 0x00308000 }, /* SA97 */
-		{ 64 * 1024, 0x00310000 }, /* SA98 */
-		{ 64 * 1024, 0x00318000 }, /* SA99 */
-		{ 64 * 1024, 0x00320000 }, /* SA100 */
-		{ 64 * 1024, 0x00328000 }, /* SA101 */
-		{ 64 * 1024, 0x00330000 }, /* SA102 */
-		{ 64 * 1024, 0x00338000 }, /* SA103 */
-		{ 64 * 1024, 0x00340000 }, /* SA104 */
-		{ 64 * 1024, 0x00348000 }, /* SA105 */
-		{ 64 * 1024, 0x00350000 }, /* SA106 */
-		{ 64 * 1024, 0x00358000 }, /* SA107 */
-		{ 64 * 1024, 0x00360000 }, /* SA108 */
-		{ 64 * 1024, 0x00368000 }, /* SA109 */
-		{ 64 * 1024, 0x00370000 }, /* SA110 */
-		{ 64 * 1024, 0x00378000 }, /* SA111 */
-		{ 64 * 1024, 0x00380000 }, /* SA112 */
-		{ 64 * 1024, 0x00388000 }, /* SA113 */
-		{ 64 * 1024, 0x00390000 }, /* SA114 */
-		{ 64 * 1024, 0x00398000 }, /* SA115 */
-		{ 64 * 1024, 0x003a0000 }, /* SA116 */
-		{ 64 * 1024, 0x003a8000 }, /* SA117 */
-		{ 64 * 1024, 0x003b0000 }, /* SA118 */
-		{ 64 * 1024, 0x003b8000 }, /* SA119 */
-		{ 64 * 1024, 0x003c0000 }, /* SA120 */
-		{ 64 * 1024, 0x003c8000 }, /* SA121 */
-		{ 64 * 1024, 0x003d0000 }, /* SA122 */
-		{ 64 * 1024, 0x003d8000 }, /* SA123 */
-		{ 64 * 1024, 0x003e0000 }, /* SA124 */
-		{ 64 * 1024, 0x003e8000 }, /* SA125 */
-		{ 64 * 1024, 0x003f0000 }, /* SA126 */
-		{ 64 * 1024, 0x003f8000 }, /* SA127 */
+{  8 * 1024, 0x00000000 }, /* SA0 */
+{  8 * 1024, 0x00008000 }, /* SA1 */
+{  8 * 1024, 0x00010000 }, /* SA2 */
+{  8 * 1024, 0x00018000 }, /* SA3 */
+{  8 * 1024, 0x00020000 }, /* SA4 */
+{  8 * 1024, 0x00028000 }, /* SA5 */
+{  8 * 1024, 0x00030000 }, /* SA6 */
+{  8 * 1024, 0x00038000 }, /* SA7 */
+{  8 * 1024, 0x00040000 }, /* SA8 */
+{ 64 * 1024, 0x00048000 }, /* SA9 */
+{ 64 * 1024, 0x00050000 }, /* SA10 */
+{ 64 * 1024, 0x00058000 }, /* SA11 */
+{ 64 * 1024, 0x00060000 }, /* SA12 */
+{ 64 * 1024, 0x00068000 }, /* SA13 */
+{ 64 * 1024, 0x00070000 }, /* SA14 */
+{ 64 * 1024, 0x00078000 }, /* SA15 */
+{ 64 * 1024, 0x00080000 }, /* SA16 */
+{ 64 * 1024, 0x00088000 }, /* SA17 */
+{ 64 * 1024, 0x00090000 }, /* SA18 */
+{ 64 * 1024, 0x00098000 }, /* SA19 */
+{ 64 * 1024, 0x000a0000 }, /* SA20 */
+{ 64 * 1024, 0x000a8000 }, /* SA21 */
+{ 64 * 1024, 0x000b0000 }, /* SA22 */
+{ 64 * 1024, 0x000b8000 }, /* SA23 */
+{ 64 * 1024, 0x000c0000 }, /* SA24 */
+{ 64 * 1024, 0x000c8000 }, /* SA25 */
+{ 64 * 1024, 0x000d0000 }, /* SA26 */
+{ 64 * 1024, 0x000d8000 }, /* SA27 */
+{ 64 * 1024, 0x000e0000 }, /* SA28 */
+{ 64 * 1024, 0x000e8000 }, /* SA29 */
+{ 64 * 1024, 0x000f0000 }, /* SA30 */
+{ 64 * 1024, 0x000f8000 }, /* SA31 */
+{ 64 * 1024, 0x00100000 }, /* SA32 */
+{ 64 * 1024, 0x00108000 }, /* SA32 */
+{ 64 * 1024, 0x00110000 }, /* SA34 */
+{ 64 * 1024, 0x00118000 }, /* SA35 */
+{ 64 * 1024, 0x00120000 }, /* SA36 */
+{ 64 * 1024, 0x00128000 }, /* SA37 */
+{ 64 * 1024, 0x00130000 }, /* SA38 */
+{ 64 * 1024, 0x00138000 }, /* SA39 */
+{ 64 * 1024, 0x00140000 }, /* SA40 */
+{ 64 * 1024, 0x00148000 }, /* SA41 */
+{ 64 * 1024, 0x00150000 }, /* SA42 */
+{ 64 * 1024, 0x00158000 }, /* SA43 */
+{ 64 * 1024, 0x00160000 }, /* SA44 */
+{ 64 * 1024, 0x00168000 }, /* SA45 */
+{ 64 * 1024, 0x00170000 }, /* SA46 */
+{ 64 * 1024, 0x00178000 }, /* SA47 */
+{ 64 * 1024, 0x00180000 }, /* SA48 */
+{ 64 * 1024, 0x00188000 }, /* SA49 */
+{ 64 * 1024, 0x00190000 }, /* SA50 */
+{ 64 * 1024, 0x00198000 }, /* SA51 */
+{ 64 * 1024, 0x001a0000 }, /* SA52 */
+{ 64 * 1024, 0x001a8000 }, /* SA53 */
+{ 64 * 1024, 0x001b0000 }, /* SA54 */
+{ 64 * 1024, 0x001b8000 }, /* SA55 */
+{ 64 * 1024, 0x001c0000 }, /* SA56 */
+{ 64 * 1024, 0x001c8000 }, /* SA57 */
+{ 64 * 1024, 0x001d0000 }, /* SA58 */
+{ 64 * 1024, 0x001d8000 }, /* SA59 */
+{ 64 * 1024, 0x001e0000 }, /* SA60 */
+{ 64 * 1024, 0x001e8000 }, /* SA61 */
+{ 64 * 1024, 0x001f0000 }, /* SA62 */
+{ 64 * 1024, 0x001f8000 }, /* SA63 */
+{ 64 * 1024, 0x00200000 }, /* SA64 */
+{ 64 * 1024, 0x00208000 }, /* SA65 */
+{ 64 * 1024, 0x00210000 }, /* SA66 */
+{ 64 * 1024, 0x00218000 }, /* SA67 */
+{ 64 * 1024, 0x00220000 }, /* SA68 */
+{ 64 * 1024, 0x00228000 }, /* SA69 */
+{ 64 * 1024, 0x00230000 }, /* SA70 */
+{ 64 * 1024, 0x00238000 }, /* SA71 */
+{ 64 * 1024, 0x00240000 }, /* SA72 */
+{ 64 * 1024, 0x00248000 }, /* SA73 */
+{ 64 * 1024, 0x00250000 }, /* SA74 */
+{ 64 * 1024, 0x00258000 }, /* SA75 */
+{ 64 * 1024, 0x00260000 }, /* SA76 */
+{ 64 * 1024, 0x00268000 }, /* SA77 */
+{ 64 * 1024, 0x00270000 }, /* SA78 */
+{ 64 * 1024, 0x00278000 }, /* SA79 */
+{ 64 * 1024, 0x00280000 }, /* SA80 */
+{ 64 * 1024, 0x00288000 }, /* SA81 */
+{ 64 * 1024, 0x00290000 }, /* SA82 */
+{ 64 * 1024, 0x00298000 }, /* SA83 */
+{ 64 * 1024, 0x002a0000 }, /* SA84 */
+{ 64 * 1024, 0x002a8000 }, /* SA85 */
+{ 64 * 1024, 0x002b0000 }, /* SA86 */
+{ 64 * 1024, 0x002b8000 }, /* SA87 */
+{ 64 * 1024, 0x002c0000 }, /* SA88 */
+{ 64 * 1024, 0x002c8000 }, /* SA89 */
+{ 64 * 1024, 0x002d0000 }, /* SA90 */
+{ 64 * 1024, 0x002d8000 }, /* SA91 */
+{ 64 * 1024, 0x002e0000 }, /* SA92 */
+{ 64 * 1024, 0x002e8000 }, /* SA93 */
+{ 64 * 1024, 0x002f0000 }, /* SA94 */
+{ 64 * 1024, 0x002f8000 }, /* SA95 */
+{ 64 * 1024, 0x00300000 }, /* SA96 */
+{ 64 * 1024, 0x00308000 }, /* SA97 */
+{ 64 * 1024, 0x00310000 }, /* SA98 */
+{ 64 * 1024, 0x00318000 }, /* SA99 */
+{ 64 * 1024, 0x00320000 }, /* SA100 */
+{ 64 * 1024, 0x00328000 }, /* SA101 */
+{ 64 * 1024, 0x00330000 }, /* SA102 */
+{ 64 * 1024, 0x00338000 }, /* SA103 */
+{ 64 * 1024, 0x00340000 }, /* SA104 */
+{ 64 * 1024, 0x00348000 }, /* SA105 */
+{ 64 * 1024, 0x00350000 }, /* SA106 */
+{ 64 * 1024, 0x00358000 }, /* SA107 */
+{ 64 * 1024, 0x00360000 }, /* SA108 */
+{ 64 * 1024, 0x00368000 }, /* SA109 */
+{ 64 * 1024, 0x00370000 }, /* SA110 */
+{ 64 * 1024, 0x00378000 }, /* SA111 */
+{ 64 * 1024, 0x00380000 }, /* SA112 */
+{ 64 * 1024, 0x00388000 }, /* SA113 */
+{ 64 * 1024, 0x00390000 }, /* SA114 */
+{ 64 * 1024, 0x00398000 }, /* SA115 */
+{ 64 * 1024, 0x003a0000 }, /* SA116 */
+{ 64 * 1024, 0x003a8000 }, /* SA117 */
+{ 64 * 1024, 0x003b0000 }, /* SA118 */
+{ 64 * 1024, 0x003b8000 }, /* SA119 */
+{ 64 * 1024, 0x003c0000 }, /* SA120 */
+{ 64 * 1024, 0x003c8000 }, /* SA121 */
+{ 64 * 1024, 0x003d0000 }, /* SA122 */
+{ 64 * 1024, 0x003d8000 }, /* SA123 */
+{ 64 * 1024, 0x003e0000 }, /* SA124 */
+{ 64 * 1024, 0x003e8000 }, /* SA125 */
+{ 64 * 1024, 0x003f0000 }, /* SA126 */
+{ 64 * 1024, 0x003f8000 }, /* SA127 */
 };

 static const int AMD_FLASH_SECTORS = sizeof(sector)	/ sizeof(struct amd_flash_sector_info);
@@ -166,17 +166,17 @@ static AMD_FLASH_CELL *pFlash;

 typedef struct romram
 {
-	uint32_t flash_address;
-	uint32_t ram_address;
-	char *name;
+    uint32_t flash_address;
+    uint32_t ram_address;
+    char *name;
 } ROMRAM;

 static const struct romram flash_areas[] =
 {
-	{ 0xe0000000, 0x00e00000, "BaS" },		/* BaS */
-	{ 0xe0600000, 0x00e00000, "EmuTOS" }, 	/* EmuTOS */
-	{ 0xe0400000, 0x00e00000, "FireTOS" }, 	/* FireTOS */
-	{ 0xe0700000, 0x00e00000, "FPGA" },		/* FPGA config */
+{ 0xe0000000, 0x00e00000, "BaS" },		/* BaS */
+{ 0xe0600000, 0x00e00000, "EmuTOS" }, 	/* EmuTOS */
+{ 0xe0400000, 0x00e00000, "FireTOS" }, 	/* FireTOS */
+{ 0xe0700000, 0x00e00000, "FPGA" },		/* FPGA config */
 };
 static const int num_flash_areas = sizeof(flash_areas) / sizeof(struct romram);

@@ -191,191 +191,191 @@ static const int num_flash_areas = sizeof(flash_areas) / sizeof(struct romram);
 */
 void amd_flash_sector_erase(int n)
 {
-	volatile AMD_FLASH_CELL status;
+    volatile AMD_FLASH_CELL status;

-	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
-	pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
-	pFlash[0x555] = AMD_FLASH_CMD_DATA(0x80);
-	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
-	pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
-	pFlash[SADDR(n)] = AMD_FLASH_CMD_DATA(0x30);
+    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+    pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+    pFlash[0x555] = AMD_FLASH_CMD_DATA(0x80);
+    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+    pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+    pFlash[SADDR(n)] = AMD_FLASH_CMD_DATA(0x30);

-	do
-		status = pFlash[SADDR(n)];
-	while ((status & AMD_FLASH_CMD_DATA(0x80)) != AMD_FLASH_CMD_DATA(0x80));
+    do
+        status = pFlash[SADDR(n)];
+    while ((status & AMD_FLASH_CMD_DATA(0x80)) != AMD_FLASH_CMD_DATA(0x80));

-	/*
-	 * Place device in read mode
-	 */
-	pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
-	pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
-	pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+    /*
+     * Place device in read mode
+     */
+    pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+    pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+    pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
 }

 int amd_flash_erase(void *start, int bytes, void (*putchar)(int))
 {
-	int i, ebytes = 0;
+    int i, ebytes = 0;

-	if (bytes == 0)
-		return 0;
+    if (bytes == 0)
+        return 0;

-	for (i = 0; i < AMD_FLASH_SECTORS; i++)
-	{
-		if (start >= (void *)((void *) pFlash + SOFFSET(i)) &&
-			start <= (void *)((void *) pFlash + SOFFSET(i) + (SSIZE(i) - 1)))
-		{
-			break;
-		}
-	}
+    for (i = 0; i < AMD_FLASH_SECTORS; i++)
+    {
+        if (start >= (void *)((void *) pFlash + SOFFSET(i)) &&
+                start <= (void *)((void *) pFlash + SOFFSET(i) + (SSIZE(i) - 1)))
+        {
+            break;
+        }
+    }

-	while (ebytes < bytes)
-	{
-		if (putchar != NULL)
-		{
-			putchar('.');
-		}
-		amd_flash_sector_erase(i);
-		ebytes += SSIZE(i);
-		i++;
-	}
+    while (ebytes < bytes)
+    {
+        if (putchar != NULL)
+        {
+            putchar('.');
+        }
+        amd_flash_sector_erase(i);
+        ebytes += SSIZE(i);
+        i++;
+    }

-	if (putchar != NULL)
-	{
-		putchar(10);    /* LF */
-		putchar(13);    /* CR */
-	}
+    if (putchar != NULL)
+    {
+        putchar(10);    /* LF */
+        putchar(13);    /* CR */
+    }

-	return ebytes;
+    return ebytes;
 }

 void amd_flash_program_cell(AMD_FLASH_CELL *dst, AMD_FLASH_CELL data)
 {
-	volatile AMD_FLASH_CELL status;
-	int retry;
+    volatile AMD_FLASH_CELL status;
+    int retry;

-	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
-	pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
-	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xA0);
-	*dst = data;
+    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+    pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xA0);
+    *dst = data;

-	/*
-	 * Wait for program operation to finish
-	 *  (Data# Polling Algorithm)
-	 */
-	retry = 0;
-	while (1)
-	{
-		status = *dst;
-		if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
-			(data & AMD_FLASH_CMD_DATA(0x80)))
-		{
-			break;
-		}
-		if (status & AMD_FLASH_CMD_DATA(0x20))
-		{
-			status = *dst;
-			if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
-				(data & AMD_FLASH_CMD_DATA(0x80)))
-			{
-				break;
-			}
-			if (++retry > 1024)
-			{
-				break;
-			}
-		}
-	}
+    /*
+     * Wait for program operation to finish
+     *  (Data# Polling Algorithm)
+     */
+    retry = 0;
+    while (1)
+    {
+        status = *dst;
+        if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
+                (data & AMD_FLASH_CMD_DATA(0x80)))
+        {
+            break;
+        }
+        if (status & AMD_FLASH_CMD_DATA(0x20))
+        {
+            status = *dst;
+            if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
+                    (data & AMD_FLASH_CMD_DATA(0x80)))
+            {
+                break;
+            }
+            if (++retry > 1024)
+            {
+                break;
+            }
+        }
+    }
 }


 int amd_flash_program(void *dest, void *source, int bytes, int erase, void (*func)(void), void (*putchar)(int))
 {
-	AMD_FLASH_CELL *src;
-	AMD_FLASH_CELL *dst;
-	int hashi = 1;
-	int hashj = 0;
-	char hash[5];
+    AMD_FLASH_CELL *src;
+    AMD_FLASH_CELL *dst;
+    int hashi = 1;
+    int hashj = 0;
+    char hash[5];

-	hash[0] = 8;  /* Backspace */
-	hash[1] = 124;/* "|" */
-	hash[2] = 47; /* "/" */
-	hash[3] = 45; /* "-" */
-	hash[4] = 92; /* "\" */
+    hash[0] = 8;  /* Backspace */
+    hash[1] = 124;/* "|" */
+    hash[2] = 47; /* "/" */
+    hash[3] = 45; /* "-" */
+    hash[4] = 92; /* "\" */

-	src = (AMD_FLASH_CELL *)source;
-	dst = (AMD_FLASH_CELL *)dest;
+    src = (AMD_FLASH_CELL *)source;
+    dst = (AMD_FLASH_CELL *)dest;

-	/*
-	 * Place device in read mode
-	 */
-	pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
-	pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
-	pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+    /*
+     * Place device in read mode
+     */
+    pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+    pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+    pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);

-	/*
-	 * Erase device if necessary
-	 */
-	if (erase)
-	{
-		amd_flash_erase(dest, bytes, putchar);
-	}
+    /*
+     * Erase device if necessary
+     */
+    if (erase)
+    {
+        amd_flash_erase(dest, bytes, putchar);
+    }

-	/*
-	 * Program device
-	 */
-	while (bytes > 0)
-	{
-		amd_flash_program_cell(dst, *src);
+    /*
+     * Program device
+     */
+    while (bytes > 0)
+    {
+        amd_flash_program_cell(dst, *src);

-		/* Verify Write */
-		if (*dst == *src)
-		{
-			bytes -= AMD_FLASH_CELL_BYTES;
-			*dst++, *src++;
+        /* Verify Write */
+        if (*dst == *src)
+        {
+            bytes -= AMD_FLASH_CELL_BYTES;
+            *dst++, *src++;

-			if ((putchar != NULL))
-			{
-				/* Hash marks to indicate progress */
-				if (hashj == 0x1000)
-				{
-					hashj = -1;
-					putchar(hash[0]);
-					putchar(hash[hashi]);
+            if ((putchar != NULL))
+            {
+                /* Hash marks to indicate progress */
+                if (hashj == 0x1000)
+                {
+                    hashj = -1;
+                    putchar(hash[0]);
+                    putchar(hash[hashi]);

-					hashi++;
-					if (hashi == 5)
-					{
-						hashi = 1;
-					}
+                    hashi++;
+                    if (hashi == 5)
+                    {
+                        hashi = 1;
+                    }

-				}
-				hashj++;
-			}
-		}
-		else
-			break;
-	}
+                }
+                hashj++;
+            }
+        }
+        else
+            break;
+    }

-	/*
-	 * Place device in read mode
-	 */
-	pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
-	pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
-	pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+    /*
+     * Place device in read mode
+     */
+    pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+    pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+    pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);

-	if (putchar != NULL)
-	{
-		putchar(hash[0]);
-	}
+    if (putchar != NULL)
+    {
+        putchar(hash[0]);
+    }

-	/*
-	 * If a function was passed in, call it now
-	 */
-	if ((func != NULL))
-	{
-		func();
-	}
+    /*
+     * If a function was passed in, call it now
+     */
+    if ((func != NULL))
+    {
+        func();
+    }

-	return ((int)src - (int)source);
+    return ((int)src - (int)source);
 }

--- a/flash/s19reader.c
+++ b/flash/s19reader.c
@@ -40,33 +40,33 @@
 * and finally ended up with this. Not nice, put paid (and working).
 *
 */
-#define SREC_TYPE(a) 		(a)[0]							/* type of record */
-#define SREC_COUNT(a) 		(a)[1]							/* length of valid bytes to follow */
-#define SREC_ADDR16(a) 		(256 * (a)[2] + (a)[3])			/* 2 byte address field */
-#define SREC_ADDR24(a)		(0x10000 * (a)[2] + 0x100 *  \
-							(a)[3] + (a)[4])				/* 3 byte address field */
+#define SREC_TYPE(a)        (a)[0]                          /* type of record */
+#define SREC_COUNT(a)       (a)[1]                          /* length of valid bytes to follow */
+#define SREC_ADDR16(a)      (256 * (a)[2] + (a)[3])         /* 2 byte address field */
+#define SREC_ADDR24(a)      (0x10000 * (a)[2] + 0x100 *  \
+    (a)[3] + (a)[4])                                        /* 3 byte address field */
 #define SREC_ADDR32(a) 		(0x1000000 * a[2] + 0x10000 * \
-							a[3] + 0x100 * (a)[4] + (a)[5])	/* 4 byte address field */
-#define SREC_DATA16(a)		((uint8_t *)&((a)[4]))			/* address of first byte of data in a record */
-#define SREC_DATA24(a)		((uint8_t *)&((a)[5]))			/* address of first data byte in 24 bit record */
-#define SREC_DATA32(a)		((uint8_t *)&((a)[6]))			/* adress of first byte of a record with 32 bit address field */
-#define SREC_DATA16_SIZE(a)	(SREC_COUNT((a)) - 3)			/* length of the data[] array without the checksum field */
-#define SREC_DATA24_SIZE(a)	(SREC_COUNT((a)) - 4)			/* length of the data[] array without the checksum field */
-#define SREC_DATA32_SIZE(a)	(SREC_COUNT((a)) - 5)			/* length of the data[] array without the checksum field */
-#define SREC_CHECKSUM(a)	(a)[SREC_COUNT(a) + 2 - 1]		/* record's checksum (two's complement of the sum of all bytes) */
+    (a)[3] + 0x100 * (a)[4] + (a)[5])   /* 4 byte address field */
+#define SREC_DATA16(a)      ((uint8_t *)&((a)[4]))          /* address of first byte of data in a record */
+#define SREC_DATA24(a)      ((uint8_t *)&((a)[5]))          /* address of first data byte in 24 bit record */
+#define SREC_DATA32(a)      ((uint8_t *)&((a)[6]))          /* adress of first byte of a record with 32 bit address field */
+#define SREC_DATA16_SIZE(a)	(SREC_COUNT((a)) - 3)           /* length of the data[] array without the checksum field */
+#define SREC_DATA24_SIZE(a)	(SREC_COUNT((a)) - 4)           /* length of the data[] array without the checksum field */
+#define SREC_DATA32_SIZE(a)	(SREC_COUNT((a)) - 5)           /* length of the data[] array without the checksum field */
+#define SREC_CHECKSUM(a)    (a)[SREC_COUNT(a) + 2 - 1]      /* record's checksum (two's complement of the sum of all bytes) */

 /*
 * convert a single hex character into byte
 */
 static uint8_t nibble_to_byte(uint8_t nibble)
 {
-	if ((nibble >= '0') && (nibble <= '9'))
-		return nibble - '0';
-	else if ((nibble >= 'A' && nibble <= 'F'))
-		return 10 + nibble - 'A';
-	else if ((nibble >= 'a' && nibble <= 'f'))
-		return 10 + nibble - 'a';
-	return 0;
+    if ((nibble >= '0') && (nibble <= '9'))
+        return nibble - '0';
+    else if ((nibble >= 'A' && nibble <= 'F'))
+        return 10 + nibble - 'A';
+    else if ((nibble >= 'a' && nibble <= 'f'))
+        return 10 + nibble - 'a';
+    return 0;
 }

 /*
@@ -74,7 +74,7 @@ static uint8_t nibble_to_byte(uint8_t nibble)
 */
 static uint8_t hex_to_byte(uint8_t hex[2])
 {
-	return 16 * (nibble_to_byte(hex[0])) + (nibble_to_byte(hex[1]));
+    return 16 * (nibble_to_byte(hex[0])) + (nibble_to_byte(hex[1]));
 }

 #ifdef _NOT_USED_
@@ -83,7 +83,7 @@ static uint8_t hex_to_byte(uint8_t hex[2])
 */
 static uint16_t hex_to_word(uint8_t hex[4])
 {
-	return 256 * hex_to_byte(&hex[0]) + hex_to_byte(&hex[2]);
+    return 256 * hex_to_byte(&hex[0]) + hex_to_byte(&hex[2]);
 }

 /*
@@ -91,7 +91,7 @@ static uint16_t hex_to_word(uint8_t hex[4])
 */
 static uint32_t hex_to_long(uint8_t hex[8])
 {
-	return 65536 * hex_to_word(&hex[0]) + hex_to_word(&hex[4]);
+    return 65536 * hex_to_word(&hex[0]) + hex_to_word(&hex[4]);
 }
 #endif /* _NOT_USED_ */

@@ -102,47 +102,47 @@ static uint32_t hex_to_long(uint8_t hex[8])
 */
 static uint8_t checksum(uint8_t arr[])
 {
-	int i;
-	uint8_t checksum = SREC_COUNT(arr);
+    int i;
+    uint8_t checksum = SREC_COUNT(arr);

-	for (i = 0; i < SREC_COUNT(arr) - 1; i++)
-	{
-		checksum += arr[i + 2];
-	}
-	return ~checksum;
+    for (i = 0; i < SREC_COUNT(arr) - 1; i++)
+    {
+        checksum += arr[i + 2];
+    }
+    return ~checksum;
 }

 #ifdef _NOT_USED_
 void print_record(uint8_t *arr)
 {
-	switch (SREC_TYPE(arr))
-	{
-		case 0:
-		{
-			xprintf("type 0x%x ", SREC_TYPE(arr));
-			xprintf("count 0x%x ", SREC_COUNT(arr));
-			xprintf("addr 0x%x ", SREC_ADDR16(arr));
-			xprintf("module %11.11s ", SREC_DATA16(arr));
-			xprintf("chk 0x%x 0x%x\r\n", SREC_CHECKSUM(arr), checksum(arr));
-		}
-		break;
+    switch (SREC_TYPE(arr))
+    {
+        case 0:
+            {
+                xprintf("type 0x%x ", SREC_TYPE(arr));
+                xprintf("count 0x%x ", SREC_COUNT(arr));
+                xprintf("addr 0x%x ", SREC_ADDR16(arr));
+                xprintf("module %11.11s ", SREC_DATA16(arr));
+                xprintf("chk 0x%x 0x%x\r\n", SREC_CHECKSUM(arr), checksum(arr));
+            }
+            break;

-		case 3:
-		case 7:
-		{
-			xprintf("type 0x%x ", SREC_TYPE(arr));
-			xprintf("count 0x%x ", SREC_COUNT(arr));
-			xprintf("addr 0x%x ", SREC_ADDR32(arr));
-			xprintf("data %02x,%02x,%02x,%02x,... ",
-					SREC_DATA32(arr)[0], SREC_DATA32(arr)[1], SREC_DATA32(arr)[3], SREC_DATA32(arr)[4]);
-			xprintf("chk 0x%x 0x%x\r\n", SREC_CHECKSUM(arr), checksum(arr));
-		}
-		break;
+        case 3:
+        case 7:
+            {
+                xprintf("type 0x%x ", SREC_TYPE(arr));
+                xprintf("count 0x%x ", SREC_COUNT(arr));
+                xprintf("addr 0x%x ", SREC_ADDR32(arr));
+                xprintf("data %02x,%02x,%02x,%02x,... ",
+                        SREC_DATA32(arr)[0], SREC_DATA32(arr)[1], SREC_DATA32(arr)[3], SREC_DATA32(arr)[4]);
+                xprintf("chk 0x%x 0x%x\r\n", SREC_CHECKSUM(arr), checksum(arr));
+            }
+            break;

-		default:
-			xprintf("unsupported report type %d in print_record\r\n", arr[0]);
-			break;
-	}
+        default:
+            xprintf("unsupported report type %d in print_record\r\n", arr[0]);
+            break;
+    }
 }
 #endif /* _NOT_USED_ */

@@ -151,21 +151,21 @@ void print_record(uint8_t *arr)
 */
 static void line_to_vector(uint8_t *buff, uint8_t *vector)
 {
-	int i;
-	int length;
-	uint8_t *vp = vector;
+    int i;
+    int length;
+    uint8_t *vp = vector;

-	length = hex_to_byte(buff + 2);
+    length = hex_to_byte(buff + 2);

-	buff++;
-	*vp++ = nibble_to_byte(*buff); /* record type. Only one single nibble */
-	buff++;
+    buff++;
+    *vp++ = nibble_to_byte(*buff); /* record type. Only one single nibble */
+    buff++;

-	for (i = 0; i <= length; i++)
-	{
-		*vp++ = hex_to_byte(buff);
-		buff += 2;
-	}
+    for (i = 0; i <= length; i++)
+    {
+        *vp++ = hex_to_byte(buff);
+        buff += 2;
+    }
 }

 /*
@@ -189,114 +189,114 @@ static void line_to_vector(uint8_t *buff, uint8_t *vector)
 */
 err_t read_srecords(char *filename, void **start_address, uint32_t *actual_length, memcpy_callback_t callback)
 {
-	FRESULT fres;
-	FIL file;
-	err_t ret = OK;
+    FRESULT fres;
+    FIL file;
+    err_t ret = OK;

-	if ((fres = f_open(&file, filename, FA_READ) == FR_OK))
-	{
-		uint8_t line[80];
-		int lineno = 0;
-		int data_records = 0;
-		bool found_block_header = false;
-		bool found_block_end = false;
-		bool found_block_data = false;
+    if ((fres = f_open(&file, filename, FA_READ) == FR_OK))
+    {
+        uint8_t line[80];
+        int lineno = 0;
+        int data_records = 0;
+        bool found_block_header = false;
+        bool found_block_end = false;
+        bool found_block_data = false;

-		while (ret == OK && (uint8_t *) f_gets((char *) line, sizeof(line), &file) != NULL)
-		{
-			lineno++;
-			uint8_t vector[80];
+        while (ret == OK && (uint8_t *) f_gets((char *) line, sizeof(line), &file) != NULL)
+        {
+            lineno++;
+            uint8_t vector[80];

-			line_to_vector(line, vector);	/* vector now contains the decoded contents of line, from line[1] on */
+            line_to_vector(line, vector);	/* vector now contains the decoded contents of line, from line[1] on */

-			if (line[0] == 'S')
-			{
-				if (SREC_CHECKSUM(vector) != checksum(vector))
-				{
-					xprintf("invalid checksum 0x%x (should be 0x%x) in line %d\r\n",
-							SREC_CHECKSUM(vector), checksum(vector), lineno);
-					ret = FAIL;
-				}
+            if (line[0] == 'S')
+            {
+                if (SREC_CHECKSUM(vector) != checksum(vector))
+                {
+                    xprintf("invalid checksum 0x%x (should be 0x%x) in line %d\r\n",
+                            SREC_CHECKSUM(vector), checksum(vector), lineno);
+                    ret = FAIL;
+                }

-				switch (vector[0])
-				{
-				case 0:	/* block header */
-					found_block_header = true;
-					if (found_block_data || found_block_end)
-					{
-						xprintf("S7 or S3 record found before S0: S-records corrupt?\r\n");
-						ret = FAIL;
-					}
+                switch (vector[0])
+                {
+                    case 0:	/* block header */
+                        found_block_header = true;
+                        if (found_block_data || found_block_end)
+                        {
+                            xprintf("S7 or S3 record found before S0: S-records corrupt?\r\n");
+                            ret = FAIL;
+                        }

-					break;
+                        break;

-				case 2: /* three byte address field data record */
-					if (!found_block_header || found_block_end)
-					{
-						xprintf("S3 record found before S0 or after S7: S-records corrupt?\r\n");
-						ret = FAIL;
-					}
-					ret = callback((uint8_t *) SREC_ADDR24(vector), SREC_DATA24(vector), SREC_DATA24_SIZE(vector));
-					data_records++;
-					break;
+                    case 2: /* three byte address field data record */
+                        if (!found_block_header || found_block_end)
+                        {
+                            xprintf("S3 record found before S0 or after S7: S-records corrupt?\r\n");
+                            ret = FAIL;
+                        }
+                        ret = callback((uint8_t *) SREC_ADDR24(vector), SREC_DATA24(vector), SREC_DATA24_SIZE(vector));
+                        data_records++;
+                        break;

-				case 3: /* four byte address field data record */
-					if (!found_block_header || found_block_end)
-					{
-						xprintf("S3 record found before S0 or after S7: S-records corrupt?\r\n");
-						ret = FAIL;
-					}
-					ret = callback((uint8_t *) SREC_ADDR32(vector), SREC_DATA32(vector), SREC_DATA32_SIZE(vector));
-					data_records++;
-					break;
+                    case 3: /* four byte address field data record */
+                        if (!found_block_header || found_block_end)
+                        {
+                            xprintf("S3 record found before S0 or after S7: S-records corrupt?\r\n");
+                            ret = FAIL;
+                        }
+                        ret = callback((uint8_t *) SREC_ADDR32(vector), SREC_DATA32(vector), SREC_DATA32_SIZE(vector));
+                        data_records++;
+                        break;

-				case 7: /* four byte address field end record */
-					if (!found_block_header || found_block_end)
-					{
-						xprintf("S7 record found before S0 or after S7: S-records corrupt?\r\n");
-					}
-					else
-					{
-						// xprintf("S7 record (end) found after %d valid data blocks\r\n", data_records);
-						*start_address = (void *) SREC_ADDR32(vector);
-					}
-					break;
+                    case 7: /* four byte address field end record */
+                        if (!found_block_header || found_block_end)
+                        {
+                            xprintf("S7 record found before S0 or after S7: S-records corrupt?\r\n");
+                        }
+                        else
+                        {
+                            // xprintf("S7 record (end) found after %d valid data blocks\r\n", data_records);
+                            *start_address = (void *) SREC_ADDR32(vector);
+                        }
+                        break;

-				case 8: /* three byte address field end record */
-					if (!found_block_header || found_block_end)
-					{
-						xprintf("S8 record found before S0 or after S8: S-records corrupt?\r\n");
-					}
-					else
-					{
-						// xprintf("S7 record (end) found after %d valid data blocks\r\n", data_records);
-						*start_address = (void *) SREC_ADDR24(vector);
-					}
-					break;
+                    case 8: /* three byte address field end record */
+                        if (!found_block_header || found_block_end)
+                        {
+                            xprintf("S8 record found before S0 or after S8: S-records corrupt?\r\n");
+                        }
+                        else
+                        {
+                            // xprintf("S7 record (end) found after %d valid data blocks\r\n", data_records);
+                            *start_address = (void *) SREC_ADDR24(vector);
+                        }
+                        break;

-				default:
-					xprintf("unsupported record type (%d) found in line %d\r\n", vector[0], lineno);
-					xprintf("offending line: \r\n");
-					xprintf("%s\r\n", line);
-					ret = FAIL;
-					break;
-				}
-			}
-			else
-			{
-				xprintf("illegal character ('%c') found on line %d: S-records corrupt?\r\n", line[0], lineno);
-				ret = FAIL;
-				break;
-			}
-		}
-		f_close(&file);
-	}
-	else
-	{
-		xprintf("could not open file %s\r\n", filename);
-		ret = FILE_OPEN;
-	}
-	return ret;
+                    default:
+                        xprintf("unsupported record type (%d) found in line %d\r\n", vector[0], lineno);
+                        xprintf("offending line: \r\n");
+                        xprintf("%s\r\n", line);
+                        ret = FAIL;
+                        break;
+                }
+            }
+            else
+            {
+                xprintf("illegal character ('%c') found on line %d: S-records corrupt?\r\n", line[0], lineno);
+                ret = FAIL;
+                break;
+            }
+        }
+        f_close(&file);
+    }
+    else
+    {
+        xprintf("could not open file %s\r\n", filename);
+        ret = FILE_OPEN;
+    }
+    return ret;
 }

 /*
@@ -304,21 +304,21 @@ err_t read_srecords(char *filename, void **start_address, uint32_t *actual_lengt
 */
 static err_t simulate()
 {
-	err_t ret = OK;
+    err_t ret = OK;

-	return ret;
+    return ret;
 }


 #ifdef _NOT_USED_
 static err_t flash(uint8_t *dst, uint8_t *src, uint32_t length)
 {
-	err_t ret = OK;
+    err_t ret = OK;

-	/* TODO: do the actual flash */
-	amd_flash_program(dst, src, length, false, NULL, xputchar);
+    /* TODO: do the actual flash */
+    amd_flash_program(dst, src, length, false, NULL, xputchar);

-	return ret;
+    return ret;
 }
 #endif /* _NOT_USED_ */

@@ -326,17 +326,17 @@ static err_t flash(uint8_t *dst, uint8_t *src, uint32_t length)
 /*
 * this callback verifies the data against the S-record file contents after a write to destination
 */
-static err_t verify(uint8_t *dst, uint8_t *src, uint32_t length)
+static err_t verify(uint8_t *dst, uint8_t *src, size_t length)
 {
-	uint8_t *end = src + length;
+    uint8_t *end = src + length;

-	do
-	{
-		if (*src++ != *dst++)
-			return FAIL;
-	} while (src < end);
+    do
+    {
+        if (*src++ != *dst++)
+            return FAIL;
+    } while (src < end);

-	return OK;
+    return OK;
 }

 /*
@@ -344,86 +344,86 @@ static err_t verify(uint8_t *dst, uint8_t *src, uint32_t length)
 */
 static inline err_t srec_memcpy(uint8_t *dst, uint8_t *src, size_t n)
 {
-	err_t e = OK;
+    err_t e = OK;

-	memcpy((void *) dst, (void *) src, n);
-	return e;
+    memcpy((void *) dst, (void *) src, n);
+    return e;
 }

 void srec_execute(char *flasher_filename)
 {
-	DRESULT res;
-	FRESULT fres;
-	FATFS fs;
-	FIL file;
-	err_t err;
-	void *start_address;
-	uint32_t length;
+    DRESULT res;
+    FRESULT fres;
+    FATFS fs;
+    FIL file;
+    err_t err;
+    void *start_address;
+    uint32_t length;

-	disk_initialize(0);
-	res = disk_status(0);
-	if (res == RES_OK)
-	{
-		fres = f_mount(0, &fs);
-		if (fres == FR_OK)
-		{
-			if ((fres = f_open(&file, flasher_filename, FA_READ) != FR_OK))
-			{
-				xprintf("flasher file %s not present on disk\r\n", flasher_filename);
-			}
-			else
-			{
-				f_close(&file);
+    disk_initialize(0);
+    res = disk_status(0);
+    if (res == RES_OK)
+    {
+        fres = f_mount(0, &fs);
+        if (fres == FR_OK)
+        {
+            if ((fres = f_open(&file, flasher_filename, FA_READ) != FR_OK))
+            {
+                xprintf("flasher file %s not present on disk\r\n", flasher_filename);
+            }
+            else
+            {
+                f_close(&file);

-				/* first pass: parse and check for inconsistencies */
-				xprintf("check file integrity: ");
-				err = read_srecords(flasher_filename, &start_address, &length, simulate);
-				if (err == OK)
-				{
-					/* next pass: copy data to destination */
-					xprintf("OK.\r\ncopy/flash data: ");
-					err = read_srecords(flasher_filename, &start_address, &length, srec_memcpy);
-					if (err == OK)
-					{
-						/* next pass: verify data */
-						xprintf("OK.\r\nverify data: ");
-						err = read_srecords(flasher_filename, &start_address, &length, verify);
-						if (err == OK)
-						{
-							xprintf("OK.\r\n");
-							typedef void void_func(void);
-							void_func *func;
-							xprintf("target successfully written and verified. Start address: %p\r\n", start_address);
+                /* first pass: parse and check for inconsistencies */
+                xprintf("check file integrity: ");
+                err = read_srecords(flasher_filename, &start_address, &length, simulate);
+                if (err == OK)
+                {
+                    /* next pass: copy data to destination */
+                    xprintf("OK.\r\ncopy/flash data: ");
+                    err = read_srecords(flasher_filename, &start_address, &length, srec_memcpy);
+                    if (err == OK)
+                    {
+                        /* next pass: verify data */
+                        xprintf("OK.\r\nverify data: ");
+                        err = read_srecords(flasher_filename, &start_address, &length, verify);
+                        if (err == OK)
+                        {
+                            xprintf("OK.\r\n");
+                            typedef void void_func(void);
+                            void_func *func;
+                            xprintf("target successfully written and verified. Start address: %p\r\n", start_address);

-							func = start_address;
-							flush_and_invalidate_caches();
-							(*func)();
-						}
-						else
-						{
-							xprintf("failed\r\n");
-						}
-					}
-					else
-					{
-						xprintf("failed\r\n");
-					}
-				}
-				else
-				{
-					xprintf("failed\r\n");
-				}
-			}
-		}
-		else
-		{
-			// xprintf("could not mount FAT FS\r\n");
-		}
-		f_mount(0, NULL);
-	}
-	else
-	{
-		// xprintf("could not initialize SD card\r\n");
-	}
+                            func = start_address;
+                            flush_and_invalidate_caches();
+                            (*func)();
+                        }
+                        else
+                        {
+                            xprintf("failed\r\n");
+                        }
+                    }
+                    else
+                    {
+                        xprintf("failed\r\n");
+                    }
+                }
+                else
+                {
+                    xprintf("failed\r\n");
+                }
+            }
+        }
+        else
+        {
+            // xprintf("could not mount FAT FS\r\n");
+        }
+        f_mount(0, NULL);
+    }
+    else
+    {
+        // xprintf("could not initialize SD card\r\n");
+    }
 }

--- a/flash_scripts/flash_firebee_bas.bdm
+++ b/flash_scripts/flash_firebee_bas.bdm
@@ -11,7 +11,7 @@ wait
 # use system sdram as flashlib scratch area.
 # TODO: plugin flashing seems to work o.k. now for smaller binaries, while it doesn't for larger ones (EmuTOS) yet.
 # This seems to be related to large flash buffers and PC-relative adressing of the plugin
-#flash-plugin 0x1000 0xf000 flash29-5475.plugin
+flash-plugin 0x1000 0xf000 flash29.plugin
 # notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
 flash 0xe0000000

--- a/flash_scripts/flash_m548x_bas.bdm
+++ b/flash_scripts/flash_m548x_bas.bdm
@@ -54,7 +54,7 @@ sleep 10
 #flash-plugin 0x1000 0xf000 flash29.plugin
 # notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
 flash 0xE0000000
-flash-plugin 0x1000 0xf000 flashintelc3.plugin
+#flash-plugin 0x1000 0xf000 flashintelc3.plugin

 # Erase flash from 0xE0000000 to 0xE00FFFFF (reserved space for bas)
 #
--- a/flash_scripts/flash_m548x_dbug.bdm
+++ b/flash_scripts/flash_m548x_dbug.bdm
@@ -10,20 +10,20 @@ wait
 write-ctrl 0x0801 0x00000000
 dump-register VBR

-# Turn on MBAR at 0xFF00_0000
-write-ctrl 0x0C0F 0xFF000000
+# Turn on MBAR at 0x1000_0000
+write-ctrl 0x0C0F 0x10000000
 dump-register MBAR

-# Turn on RAMBAR0 at address FF10_0000 
-write-ctrl 0x0C04 0xFF100007
+# Turn on RAMBAR0 at address 2000_0000 
+write-ctrl 0x0C04 0x20000007

 # Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently)
-write-ctrl 0x0C05 0xFF101001
+write-ctrl 0x0C05 0x20001001

 #
-# Init CS0 (BootFLASH @ E000_0000 - E03F_FFFF 4Mbytes)
-write 0xFF000500 0xE0000000 4
-write 0xFF000508 0x00041180 4
+# Init CS0 (BootFLASH @ FF80_0000 - FFBF_FFFF 4Mbytes)
+write 0xFF000500 0xFF800000 4
+write 0xFF000508 0x00100D80 4
 write 0xFF000504 0x003F0001 4

 # SDRAM Initialization @ 0000_0000 - 03FF_FFFF 64 Mbytes
@@ -52,27 +52,26 @@ sleep 10
 # This seems to be related to large flash buffers and PC-relative adressing of the plugin
 #flash-plugin 0x1000 0xf000 flash29.plugin
 # notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
-flash 0xE0000000
-flash-plugin 0x1000 0xf000 flashintelc3.plugin
+flash 0xFF800000
+#flash-plugin 0x1000 0xf000 flashintelc3.plugin

-# Erase flash from 0xE0000000 to 0xE00FFFFF (reserved space for bas)
-#
-# Caution: sector offset numbers need to be the ones from the x16 address range
-# column and they vary in size - needs to be exactly as in the data sheet (p. 9)
+# Erase flash from 0xFF800000 to 0xFFBFFFFF (reserved space for bas)
 #
 # contrary to documentation, it seems we need to erase-wait after each sector

-#erase 0xE0000000 0x0
-#erase 0xE0002000 0x0
-#erase 0xE0000000 0x00004000
-#erase 0xE0000000 0x00005000
-#erase 0xE0000000 0x00006000
-#erase 0xE0000000 0x00007000
-#erase 0xE0000000 0x00008000
-#erase 0xE0000000 0x00009000
-#erase 0xE0000000 0x0000a000
-#erase 0xE0000000 0x0000b000
-#erase-wait 0xe0000000
-#blank-chk 0xE0000000 0x0
-load -v m5484lite_dbug_flash.elf
+erase 0xFF800000 0
+erase 0xFF800000 1
+erase 0xFF800000 2
+erase 0xFF800000 3
+erase 0xFF800000 4
+erase 0xFF800000 5
+erase 0xFF800000 6
+erase 0xFF800000 7
+erase 0xFF800000 8
+erase 0xFF800000 9
+erase 0xFF800000 10
+erase 0xFF800000 11
+erase 0xFF800000 12
+erase 0xFF800000 13
+load -v m548xlite_dbug_flash.elf
 wait
--- a/flash_scripts/flash_m548x_etos.bdm
+++ b/flash_scripts/flash_m548x_etos.bdm
@@ -63,4 +63,4 @@ erase 0xe0000000 37
 erase 0xe0000000 38
 erase 0xe0000000 39

-load ../../emutos/emutos-m548x-bas_gcc.elf
+load ../../emutos/emutos-m548xbas.elf
--- a/fs/cc932.c
+++ b/fs/cc932.c
--- a/fs/cc936.c
+++ b/fs/cc936.c
--- a/fs/cc949.c
+++ b/fs/cc949.c
--- a/fs/cc950.c
+++ b/fs/cc950.c
--- a/fs/ccsbcs.c
+++ b/fs/ccsbcs.c
@@ -31,463 +31,505 @@
 #if _CODE_PAGE == 437
 #define _TBLDEF 1
 static
-const uint16_t Tbl[] = {	/*  CP437(0x80-0xFF) to Unicode conversion table */
-	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
-	0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
-	0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
-	0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
-	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
-	0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
-	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
-	0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
-	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
-	0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
-	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
-	0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
-	0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4,
-	0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
-	0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248,
-	0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+const uint16_t Tbl[] =
+{
+    /*  CP437(0x80-0xFF) to Unicode conversion table */
+    0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
+    0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+    0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
+    0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
+    0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
+    0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+    0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
+    0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+    0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
+    0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+    0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
+    0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+    0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4,
+    0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+    0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248,
+    0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
 };

 #elif _CODE_PAGE == 720
 #define _TBLDEF 1
 static
-const uint16_t Tbl[] = {	/*  CP720(0x80-0xFF) to Unicode conversion table */
-	0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7,
-	0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000,
-	0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9,
-	0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627,
-	0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F,
-	0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB,
-	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
-	0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
-	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
-	0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
-	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
-	0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
-	0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642,
-	0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A,
-	0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0xO650, 0x2248,
-	0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+const uint16_t Tbl[] =
+{
+    /*  CP720(0x80-0xFF) to Unicode conversion table */
+    0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7,
+    0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9,
+    0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627,
+    0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F,
+    0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB,
+    0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
+    0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+    0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
+    0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+    0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
+    0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+    0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642,
+    0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A,
+    0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0xO650, 0x2248,
+    0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
 };

 #elif _CODE_PAGE == 737
 #define _TBLDEF 1
 static
-const uint16_t Tbl[] = {	/*  CP737(0x80-0xFF) to Unicode conversion table */
-	0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398,
-	0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0,
-	0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9,
-	0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8,
-	0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0,
-	0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8,
-	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
-	0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
-	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
-	0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
-	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
-	0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
-	0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD,
-	0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E,
-	0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248,
-	0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+const uint16_t Tbl[] =
+{
+    /*  CP737(0x80-0xFF) to Unicode conversion table */
+    0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398,
+    0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0,
+    0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9,
+    0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8,
+    0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0,
+    0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8,
+    0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
+    0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+    0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
+    0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+    0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
+    0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+    0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD,
+    0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E,
+    0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248,
+    0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
 };

 #elif _CODE_PAGE == 775
 #define _TBLDEF 1
 static
-const uint16_t Tbl[] = {	/*  CP775(0x80-0xFF) to Unicode conversion table */
-	0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107,
-	0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5,
-	0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A,
-	0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4,
-	0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6,
-	0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB,
-	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118,
-	0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510,
-	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A,
-	0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D,
-	0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B,
-	0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
-	0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144,
-	0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019,
-	0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E,
-	0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+const uint16_t Tbl[] =
+{
+    /*  CP775(0x80-0xFF) to Unicode conversion table */
+    0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107,
+    0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5,
+    0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A,
+    0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4,
+    0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6,
+    0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB,
+    0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118,
+    0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510,
+    0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A,
+    0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D,
+    0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B,
+    0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+    0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144,
+    0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019,
+    0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E,
+    0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
 };

 #elif _CODE_PAGE == 850
 #define _TBLDEF 1
 static
-const uint16_t Tbl[] = {	/*  CP850(0x80-0xFF) to Unicode conversion table */
-	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
-	0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
-	0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
-	0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192,
-	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
-	0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
-	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0,
-	0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
-	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3,
-	0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
-	0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE,
-	0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
-	0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE,
-	0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4,
-	0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8,
-	0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+const uint16_t Tbl[] =
+{
+    /*  CP850(0x80-0xFF) to Unicode conversion table */
+    0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
+    0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+    0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
+    0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192,
+    0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
+    0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+    0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0,
+    0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
+    0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3,
+    0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+    0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE,
+    0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
+    0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE,
+    0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4,
+    0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8,
+    0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
 };

 #elif _CODE_PAGE == 852
 #define _TBLDEF 1
 static
-const uint16_t Tbl[] = {	/*  CP852(0x80-0xFF) to Unicode conversion table */
-	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7,
-	0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106,
-	0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A,
-	0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D,
-	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E,
-	0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB,
-	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A,
-	0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510,
-	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103,
-	0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
-	0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE,
-	0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580,
-	0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161,
-	0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4,
-	0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8,
-	0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0
+const uint16_t Tbl[] =
+{
+    /*  CP852(0x80-0xFF) to Unicode conversion table */
+    0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7,
+    0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106,
+    0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A,
+    0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D,
+    0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E,
+    0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB,
+    0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A,
+    0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510,
+    0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103,
+    0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+    0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE,
+    0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580,
+    0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161,
+    0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4,
+    0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8,
+    0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0
 };

 #elif _CODE_PAGE == 855
 #define _TBLDEF 1
 static
-const uint16_t Tbl[] = {	/*  CP855(0x80-0xFF) to Unicode conversion table */
-	0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404,
-	0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408,
-	0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C,
-	0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A,
-	0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414,
-	0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB,
-	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438,
-	0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510,
-	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A,
-	0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
-	0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E,
-	0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580,
-	0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443,
-	0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116,
-	0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D,
-	0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0
+const uint16_t Tbl[] =
+{
+    /*  CP855(0x80-0xFF) to Unicode conversion table */
+    0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404,
+    0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408,
+    0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C,
+    0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A,
+    0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414,
+    0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB,
+    0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438,
+    0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510,
+    0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A,
+    0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+    0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E,
+    0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580,
+    0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443,
+    0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116,
+    0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D,
+    0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0
 };

 #elif _CODE_PAGE == 857
 #define _TBLDEF 1
 static
-const uint16_t Tbl[] = {	/*  CP857(0x80-0xFF) to Unicode conversion table */
-	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
-	0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5,
-	0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
-	0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F,
-	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F,
-	0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
-	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0,
-	0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
-	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3,
-	0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
-	0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE,
-	0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
-	0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000,
-	0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4,
-	0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8,
-	0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+const uint16_t Tbl[] =
+{
+    /*  CP857(0x80-0xFF) to Unicode conversion table */
+    0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
+    0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5,
+    0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
+    0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F,
+    0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F,
+    0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+    0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0,
+    0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
+    0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3,
+    0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+    0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE,
+    0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
+    0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000,
+    0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4,
+    0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8,
+    0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
 };

 #elif _CODE_PAGE == 858
 #define _TBLDEF 1
 static
-const uint16_t Tbl[] = {	/*  CP858(0x80-0xFF) to Unicode conversion table */
-	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
-	0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
-	0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
-	0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192,
-	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
-	0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
-	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0,
-	0x00A9, 0x2563, 0x2551, 0x2557, 0x2550, 0x00A2, 0x00A5, 0x2510,
-	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3,
-	0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
-	0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x20AC, 0x00CD, 0x00CE,
-	0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00C6, 0x00CC, 0x2580,
-	0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE,
-	0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4,
-	0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8,
-	0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+const uint16_t Tbl[] =
+{
+    /*  CP858(0x80-0xFF) to Unicode conversion table */
+    0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
+    0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+    0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
+    0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192,
+    0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
+    0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+    0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0,
+    0x00A9, 0x2563, 0x2551, 0x2557, 0x2550, 0x00A2, 0x00A5, 0x2510,
+    0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3,
+    0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+    0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x20AC, 0x00CD, 0x00CE,
+    0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00C6, 0x00CC, 0x2580,
+    0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE,
+    0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4,
+    0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8,
+    0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
 };

 #elif _CODE_PAGE == 862
 #define _TBLDEF 1
 static
-const uint16_t Tbl[] = {	/*  CP862(0x80-0xFF) to Unicode conversion table */
-	0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7,
-	0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF,
-	0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7,
-	0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
-	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
-	0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
-	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
-	0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
-	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
-	0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
-	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
-	0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
-	0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4,
-	0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
-	0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248,
-	0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+const uint16_t Tbl[] =
+{
+    /*  CP862(0x80-0xFF) to Unicode conversion table */
+    0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7,
+    0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF,
+    0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7,
+    0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
+    0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
+    0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+    0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
+    0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+    0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
+    0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+    0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
+    0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+    0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4,
+    0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+    0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248,
+    0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
 };

 #elif _CODE_PAGE == 866
 #define _TBLDEF 1
 static
-const uint16_t Tbl[] = {	/*  CP866(0x80-0xFF) to Unicode conversion table */
-	0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417,
-	0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
-	0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427,
-	0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
-	0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437,
-	0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
-	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
-	0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
-	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
-	0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
-	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
-	0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
-	0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447,
-	0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F,
-	0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E,
-	0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0
+const uint16_t Tbl[] =
+{
+    /*  CP866(0x80-0xFF) to Unicode conversion table */
+    0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417,
+    0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
+    0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427,
+    0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
+    0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437,
+    0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
+    0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
+    0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+    0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
+    0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+    0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
+    0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+    0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447,
+    0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F,
+    0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E,
+    0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0
 };

 #elif _CODE_PAGE == 874
 #define _TBLDEF 1
 static
-const uint16_t Tbl[] = {	/*  CP874(0x80-0xFF) to Unicode conversion table */
-	0x20AC, 0x0000, 0x0000, 0x0000, 0x0000, 0x2026, 0x0000, 0x0000,
-	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-	0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
-	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-	0x00A0, 0x0E01, 0x0E02, 0x0E03, 0x0E04, 0x0E05, 0x0E06, 0x0E07,
-	0x0E08, 0x0E09, 0x0E0A, 0x0E0B, 0x0E0C, 0x0E0D, 0x0E0E, 0x0E0F,
-	0x0E10, 0x0E11, 0x0E12, 0x0E13, 0x0E14, 0x0E15, 0x0E16, 0x0E17,
-	0x0E18, 0x0E19, 0x0E1A, 0x0E1B, 0x0E1C, 0x0E1D, 0x0E1E, 0x0E1F,
-	0x0E20, 0x0E21, 0x0E22, 0x0E23, 0x0E24, 0x0E25, 0x0E26, 0x0E27,
-	0x0E28, 0x0E29, 0x0E2A, 0x0E2B, 0x0E2C, 0x0E2D, 0x0E2E, 0x0E2F,
-	0x0E30, 0x0E31, 0x0E32, 0x0E33, 0x0E34, 0x0E35, 0x0E36, 0x0E37,
-	0x0E38, 0x0E39, 0x0E3A, 0x0000, 0x0000, 0x0000, 0x0000, 0x0E3F,
-	0x0E40, 0x0E41, 0x0E42, 0x0E43, 0x0E44, 0x0E45, 0x0E46, 0x0E47,
-	0x0E48, 0x0E49, 0x0E4A, 0x0E4B, 0x0E4C, 0x0E4D, 0x0E4E, 0x0E4F,
-	0x0E50, 0x0E51, 0x0E52, 0x0E53, 0x0E54, 0x0E55, 0x0E56, 0x0E57,
-	0x0E58, 0x0E59, 0x0E5A, 0x0E5B, 0x0000, 0x0000, 0x0000, 0x0000
+const uint16_t Tbl[] =
+{
+    /*  CP874(0x80-0xFF) to Unicode conversion table */
+    0x20AC, 0x0000, 0x0000, 0x0000, 0x0000, 0x2026, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x00A0, 0x0E01, 0x0E02, 0x0E03, 0x0E04, 0x0E05, 0x0E06, 0x0E07,
+    0x0E08, 0x0E09, 0x0E0A, 0x0E0B, 0x0E0C, 0x0E0D, 0x0E0E, 0x0E0F,
+    0x0E10, 0x0E11, 0x0E12, 0x0E13, 0x0E14, 0x0E15, 0x0E16, 0x0E17,
+    0x0E18, 0x0E19, 0x0E1A, 0x0E1B, 0x0E1C, 0x0E1D, 0x0E1E, 0x0E1F,
+    0x0E20, 0x0E21, 0x0E22, 0x0E23, 0x0E24, 0x0E25, 0x0E26, 0x0E27,
+    0x0E28, 0x0E29, 0x0E2A, 0x0E2B, 0x0E2C, 0x0E2D, 0x0E2E, 0x0E2F,
+    0x0E30, 0x0E31, 0x0E32, 0x0E33, 0x0E34, 0x0E35, 0x0E36, 0x0E37,
+    0x0E38, 0x0E39, 0x0E3A, 0x0000, 0x0000, 0x0000, 0x0000, 0x0E3F,
+    0x0E40, 0x0E41, 0x0E42, 0x0E43, 0x0E44, 0x0E45, 0x0E46, 0x0E47,
+    0x0E48, 0x0E49, 0x0E4A, 0x0E4B, 0x0E4C, 0x0E4D, 0x0E4E, 0x0E4F,
+    0x0E50, 0x0E51, 0x0E52, 0x0E53, 0x0E54, 0x0E55, 0x0E56, 0x0E57,
+    0x0E58, 0x0E59, 0x0E5A, 0x0E5B, 0x0000, 0x0000, 0x0000, 0x0000
 };

 #elif _CODE_PAGE == 1250
 #define _TBLDEF 1
 static
-const uint16_t Tbl[] = {	/*  CP1250(0x80-0xFF) to Unicode conversion table */
-	0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021,
-	0x0000, 0x2030, 0x0160, 0x2039, 0x015A, 0x0164, 0x017D, 0x0179,
-	0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
-	0x0000, 0x2122, 0x0161, 0x203A, 0x015B, 0x0165, 0x017E, 0x017A,
-	0x00A0, 0x02C7, 0x02D8, 0x0141, 0x00A4, 0x0104, 0x00A6, 0x00A7,
-	0x00A8, 0x00A9, 0x015E, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x017B,
-	0x00B0, 0x00B1, 0x02DB, 0x0142, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
-	0x00B8, 0x0105, 0x015F, 0x00BB, 0x013D, 0x02DD, 0x013E, 0x017C,
-	0x0154, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x0139, 0x0106, 0x00C7,
-	0x010C, 0x00C9, 0x0118, 0x00CB, 0x011A, 0x00CD, 0x00CE, 0x010E,
-	0x0110, 0x0143, 0x0147, 0x00D3, 0x00D4, 0x0150, 0x00D6, 0x00D7,
-	0x0158, 0x016E, 0x00DA, 0x0170, 0x00DC, 0x00DD, 0x0162, 0x00DF,
-	0x0155, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x013A, 0x0107, 0x00E7,
-	0x010D, 0x00E9, 0x0119, 0x00EB, 0x011B, 0x00ED, 0x00EE, 0x010F,
-	0x0111, 0x0144, 0x0148, 0x00F3, 0x00F4, 0x0151, 0x00F6, 0x00F7,
-	0x0159, 0x016F, 0x00FA, 0x0171, 0x00FC, 0x00FD, 0x0163, 0x02D9
+const uint16_t Tbl[] =
+{
+    /*  CP1250(0x80-0xFF) to Unicode conversion table */
+    0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021,
+    0x0000, 0x2030, 0x0160, 0x2039, 0x015A, 0x0164, 0x017D, 0x0179,
+    0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+    0x0000, 0x2122, 0x0161, 0x203A, 0x015B, 0x0165, 0x017E, 0x017A,
+    0x00A0, 0x02C7, 0x02D8, 0x0141, 0x00A4, 0x0104, 0x00A6, 0x00A7,
+    0x00A8, 0x00A9, 0x015E, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x017B,
+    0x00B0, 0x00B1, 0x02DB, 0x0142, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+    0x00B8, 0x0105, 0x015F, 0x00BB, 0x013D, 0x02DD, 0x013E, 0x017C,
+    0x0154, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x0139, 0x0106, 0x00C7,
+    0x010C, 0x00C9, 0x0118, 0x00CB, 0x011A, 0x00CD, 0x00CE, 0x010E,
+    0x0110, 0x0143, 0x0147, 0x00D3, 0x00D4, 0x0150, 0x00D6, 0x00D7,
+    0x0158, 0x016E, 0x00DA, 0x0170, 0x00DC, 0x00DD, 0x0162, 0x00DF,
+    0x0155, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x013A, 0x0107, 0x00E7,
+    0x010D, 0x00E9, 0x0119, 0x00EB, 0x011B, 0x00ED, 0x00EE, 0x010F,
+    0x0111, 0x0144, 0x0148, 0x00F3, 0x00F4, 0x0151, 0x00F6, 0x00F7,
+    0x0159, 0x016F, 0x00FA, 0x0171, 0x00FC, 0x00FD, 0x0163, 0x02D9
 };

 #elif _CODE_PAGE == 1251
 #define _TBLDEF 1
 static
-const uint16_t Tbl[] = {	/*  CP1251(0x80-0xFF) to Unicode conversion table */
-	0x0402, 0x0403, 0x201A, 0x0453, 0x201E, 0x2026, 0x2020, 0x2021,
-	0x20AC, 0x2030, 0x0409, 0x2039, 0x040A, 0x040C, 0x040B, 0x040F,
-	0x0452, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
-	0x0000, 0x2111, 0x0459, 0x203A, 0x045A, 0x045C, 0x045B, 0x045F,
-	0x00A0, 0x040E, 0x045E, 0x0408, 0x00A4, 0x0490, 0x00A6, 0x00A7,
-	0x0401, 0x00A9, 0x0404, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x0407,
-	0x00B0, 0x00B1, 0x0406, 0x0456, 0x0491, 0x00B5, 0x00B6, 0x00B7,
-	0x0451, 0x2116, 0x0454, 0x00BB, 0x0458, 0x0405, 0x0455, 0x0457,
-	0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417,
-	0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
-	0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427,
-	0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
-	0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437,
-	0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
-	0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447,
-	0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F
+const uint16_t Tbl[] =
+{
+    /*  CP1251(0x80-0xFF) to Unicode conversion table */
+    0x0402, 0x0403, 0x201A, 0x0453, 0x201E, 0x2026, 0x2020, 0x2021,
+    0x20AC, 0x2030, 0x0409, 0x2039, 0x040A, 0x040C, 0x040B, 0x040F,
+    0x0452, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+    0x0000, 0x2111, 0x0459, 0x203A, 0x045A, 0x045C, 0x045B, 0x045F,
+    0x00A0, 0x040E, 0x045E, 0x0408, 0x00A4, 0x0490, 0x00A6, 0x00A7,
+    0x0401, 0x00A9, 0x0404, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x0407,
+    0x00B0, 0x00B1, 0x0406, 0x0456, 0x0491, 0x00B5, 0x00B6, 0x00B7,
+    0x0451, 0x2116, 0x0454, 0x00BB, 0x0458, 0x0405, 0x0455, 0x0457,
+    0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417,
+    0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
+    0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427,
+    0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
+    0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437,
+    0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
+    0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447,
+    0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F
 };

 #elif _CODE_PAGE == 1252
 #define _TBLDEF 1
 static
-const uint16_t Tbl[] = {	/*  CP1252(0x80-0xFF) to Unicode conversion table */
-	0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
-	0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x017D, 0x0000,
-	0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
-	0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x017E, 0x0178,
-	0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
-	0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
-	0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
-	0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
-	0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7,
-	0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF,
-	0x00D0, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7,
-	0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x00DD, 0x00DE, 0x00DF,
-	0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7,
-	0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF,
-	0x00F0, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7,
-	0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x00FD, 0x00FE, 0x00FF
+const uint16_t Tbl[] =
+{
+    /*  CP1252(0x80-0xFF) to Unicode conversion table */
+    0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+    0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x017D, 0x0000,
+    0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+    0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x017E, 0x0178,
+    0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+    0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+    0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+    0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
+    0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7,
+    0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF,
+    0x00D0, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7,
+    0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x00DD, 0x00DE, 0x00DF,
+    0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7,
+    0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF,
+    0x00F0, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7,
+    0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x00FD, 0x00FE, 0x00FF
 };

 #elif _CODE_PAGE == 1253
 #define _TBLDEF 1
 static
-const uint16_t Tbl[] = {	/*  CP1253(0x80-0xFF) to Unicode conversion table */
-	0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
-	0x0000, 0x2030, 0x0000, 0x2039, 0x000C, 0x0000, 0x0000, 0x0000,
-	0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
-	0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000,
-	0x00A0, 0x0385, 0x0386, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
-	0x00A8, 0x00A9, 0x0000, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x2015,
-	0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x0384, 0x00B5, 0x00B6, 0x00B7,
-	0x0388, 0x0389, 0x038A, 0x00BB, 0x038C, 0x00BD, 0x038E, 0x038F,
-	0x0390, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397,
-	0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F,
-	0x03A0, 0x03A1, 0x0000, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7,
-	0x03A8, 0x03A9, 0x03AA, 0x03AD, 0x03AC, 0x03AD, 0x03AE, 0x03AF,
-	0x03B0, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7,
-	0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF,
-	0x03C0, 0x03C1, 0x03C2, 0x03C3, 0x03C4, 0x03C5, 0x03C6, 0x03C7,
-	0x03C8, 0x03C9, 0x03CA, 0x03CB, 0x03CC, 0x03CD, 0x03CE, 0x0000
+const uint16_t Tbl[] =
+{
+    /*  CP1253(0x80-0xFF) to Unicode conversion table */
+    0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+    0x0000, 0x2030, 0x0000, 0x2039, 0x000C, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+    0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x00A0, 0x0385, 0x0386, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+    0x00A8, 0x00A9, 0x0000, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x2015,
+    0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x0384, 0x00B5, 0x00B6, 0x00B7,
+    0x0388, 0x0389, 0x038A, 0x00BB, 0x038C, 0x00BD, 0x038E, 0x038F,
+    0x0390, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397,
+    0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F,
+    0x03A0, 0x03A1, 0x0000, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7,
+    0x03A8, 0x03A9, 0x03AA, 0x03AD, 0x03AC, 0x03AD, 0x03AE, 0x03AF,
+    0x03B0, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7,
+    0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF,
+    0x03C0, 0x03C1, 0x03C2, 0x03C3, 0x03C4, 0x03C5, 0x03C6, 0x03C7,
+    0x03C8, 0x03C9, 0x03CA, 0x03CB, 0x03CC, 0x03CD, 0x03CE, 0x0000
 };

 #elif _CODE_PAGE == 1254
 #define _TBLDEF 1
 static
-const uint16_t Tbl[] = {	/*  CP1254(0x80-0xFF) to Unicode conversion table */
-	0x20AC, 0x0000, 0x210A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
-	0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000,
-	0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
-	0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178,
-	0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
-	0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
-	0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
-	0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
-	0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7,
-	0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF,
-	0x011E, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7,
-	0x00D8, 0x00D9, 0x00DA, 0x00BD, 0x00DC, 0x0130, 0x015E, 0x00DF,
-	0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7,
-	0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF,
-	0x011F, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7,
-	0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x0131, 0x015F, 0x00FF
+const uint16_t Tbl[] =
+{
+    /*  CP1254(0x80-0xFF) to Unicode conversion table */
+    0x20AC, 0x0000, 0x210A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+    0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+    0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178,
+    0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+    0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+    0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+    0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
+    0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7,
+    0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF,
+    0x011E, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7,
+    0x00D8, 0x00D9, 0x00DA, 0x00BD, 0x00DC, 0x0130, 0x015E, 0x00DF,
+    0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7,
+    0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF,
+    0x011F, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7,
+    0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x0131, 0x015F, 0x00FF
 };

 #elif _CODE_PAGE == 1255
 #define _TBLDEF 1
 static
-const uint16_t Tbl[] = {	/*  CP1255(0x80-0xFF) to Unicode conversion table */
-	0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
-	0x02C6, 0x2030, 0x0000, 0x2039, 0x0000, 0x0000, 0x0000, 0x0000,
-	0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
-	0x02DC, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000,
-	0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
-	0x00A8, 0x00A9, 0x00D7, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
-	0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
-	0x00B8, 0x00B9, 0x00F7, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
-	0x05B0, 0x05B1, 0x05B2, 0x05B3, 0x05B4, 0x05B5, 0x05B6, 0x05B7,
-	0x05B8, 0x05B9, 0x0000, 0x05BB, 0x05BC, 0x05BD, 0x05BE, 0x05BF,
-	0x05C0, 0x05C1, 0x05C2, 0x05C3, 0x05F0, 0x05F1, 0x05F2, 0x05F3,
-	0x05F4, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-	0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7,
-	0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF,
-	0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7,
-	0x05E8, 0x05E9, 0x05EA, 0x0000, 0x0000, 0x200E, 0x200F, 0x0000
+const uint16_t Tbl[] =
+{
+    /*  CP1255(0x80-0xFF) to Unicode conversion table */
+    0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+    0x02C6, 0x2030, 0x0000, 0x2039, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+    0x02DC, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+    0x00A8, 0x00A9, 0x00D7, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+    0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+    0x00B8, 0x00B9, 0x00F7, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
+    0x05B0, 0x05B1, 0x05B2, 0x05B3, 0x05B4, 0x05B5, 0x05B6, 0x05B7,
+    0x05B8, 0x05B9, 0x0000, 0x05BB, 0x05BC, 0x05BD, 0x05BE, 0x05BF,
+    0x05C0, 0x05C1, 0x05C2, 0x05C3, 0x05F0, 0x05F1, 0x05F2, 0x05F3,
+    0x05F4, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7,
+    0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF,
+    0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7,
+    0x05E8, 0x05E9, 0x05EA, 0x0000, 0x0000, 0x200E, 0x200F, 0x0000
 };

 #elif _CODE_PAGE == 1256
 #define _TBLDEF 1
 static
-const uint16_t Tbl[] = {	/*  CP1256(0x80-0xFF) to Unicode conversion table */
-	0x20AC, 0x067E, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
-	0x02C6, 0x2030, 0x0679, 0x2039, 0x0152, 0x0686, 0x0698, 0x0688,
-	0x06AF, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
-	0x06A9, 0x2122, 0x0691, 0x203A, 0x0153, 0x200C, 0x200D, 0x06BA,
-	0x00A0, 0x060C, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
-	0x00A8, 0x00A9, 0x06BE, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
-	0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
-	0x00B8, 0x00B9, 0x061B, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x061F,
-	0x06C1, 0x0621, 0x0622, 0x0623, 0x0624, 0x0625, 0x0626, 0x0627,
-	0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F,
-	0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x0636, 0x00D7,
-	0x0637, 0x0638, 0x0639, 0x063A, 0x0640, 0x0640, 0x0642, 0x0643,
-	0x00E0, 0x0644, 0x00E2, 0x0645, 0x0646, 0x0647, 0x0648, 0x00E7,
-	0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0649, 0x064A, 0x00EE, 0x00EF,
-	0x064B, 0x064C, 0x064D, 0x064E, 0x00F4, 0x064F, 0x0650, 0x00F7,
-	0x0651, 0x00F9, 0x0652, 0x00FB, 0x00FC, 0x200E, 0x200F, 0x06D2
+const uint16_t Tbl[] =
+{
+    /*  CP1256(0x80-0xFF) to Unicode conversion table */
+    0x20AC, 0x067E, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+    0x02C6, 0x2030, 0x0679, 0x2039, 0x0152, 0x0686, 0x0698, 0x0688,
+    0x06AF, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+    0x06A9, 0x2122, 0x0691, 0x203A, 0x0153, 0x200C, 0x200D, 0x06BA,
+    0x00A0, 0x060C, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+    0x00A8, 0x00A9, 0x06BE, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+    0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+    0x00B8, 0x00B9, 0x061B, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x061F,
+    0x06C1, 0x0621, 0x0622, 0x0623, 0x0624, 0x0625, 0x0626, 0x0627,
+    0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F,
+    0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x0636, 0x00D7,
+    0x0637, 0x0638, 0x0639, 0x063A, 0x0640, 0x0640, 0x0642, 0x0643,
+    0x00E0, 0x0644, 0x00E2, 0x0645, 0x0646, 0x0647, 0x0648, 0x00E7,
+    0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0649, 0x064A, 0x00EE, 0x00EF,
+    0x064B, 0x064C, 0x064D, 0x064E, 0x00F4, 0x064F, 0x0650, 0x00F7,
+    0x0651, 0x00F9, 0x0652, 0x00FB, 0x00FC, 0x200E, 0x200F, 0x06D2
 }

 #elif _CODE_PAGE == 1257
 #define _TBLDEF 1
 static
-const uint16_t Tbl[] = {	/*  CP1257(0x80-0xFF) to Unicode conversion table */
-	0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021,
-	0x0000, 0x2030, 0x0000, 0x2039, 0x0000, 0x00A8, 0x02C7, 0x00B8,
-	0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
-	0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x00AF, 0x02DB, 0x0000,
-	0x00A0, 0x0000, 0x00A2, 0x00A3, 0x00A4, 0x0000, 0x00A6, 0x00A7,
-	0x00D8, 0x00A9, 0x0156, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
-	0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
-	0x00B8, 0x00B9, 0x0157, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00E6,
-	0x0104, 0x012E, 0x0100, 0x0106, 0x00C4, 0x00C5, 0x0118, 0x0112,
-	0x010C, 0x00C9, 0x0179, 0x0116, 0x0122, 0x0136, 0x012A, 0x013B,
-	0x0160, 0x0143, 0x0145, 0x00D3, 0x014C, 0x00D5, 0x00D6, 0x00D7,
-	0x0172, 0x0141, 0x015A, 0x016A, 0x00DC, 0x017B, 0x017D, 0x00DF,
-	0x0105, 0x012F, 0x0101, 0x0107, 0x00E4, 0x00E5, 0x0119, 0x0113,
-	0x010D, 0x00E9, 0x017A, 0x0117, 0x0123, 0x0137, 0x012B, 0x013C,
-	0x0161, 0x0144, 0x0146, 0x00F3, 0x014D, 0x00F5, 0x00F6, 0x00F7,
-	0x0173, 0x014E, 0x015B, 0x016B, 0x00FC, 0x017C, 0x017E, 0x02D9
+const uint16_t Tbl[] =
+{
+    /*  CP1257(0x80-0xFF) to Unicode conversion table */
+    0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021,
+    0x0000, 0x2030, 0x0000, 0x2039, 0x0000, 0x00A8, 0x02C7, 0x00B8,
+    0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+    0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x00AF, 0x02DB, 0x0000,
+    0x00A0, 0x0000, 0x00A2, 0x00A3, 0x00A4, 0x0000, 0x00A6, 0x00A7,
+    0x00D8, 0x00A9, 0x0156, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+    0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+    0x00B8, 0x00B9, 0x0157, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00E6,
+    0x0104, 0x012E, 0x0100, 0x0106, 0x00C4, 0x00C5, 0x0118, 0x0112,
+    0x010C, 0x00C9, 0x0179, 0x0116, 0x0122, 0x0136, 0x012A, 0x013B,
+    0x0160, 0x0143, 0x0145, 0x00D3, 0x014C, 0x00D5, 0x00D6, 0x00D7,
+    0x0172, 0x0141, 0x015A, 0x016A, 0x00DC, 0x017B, 0x017D, 0x00DF,
+    0x0105, 0x012F, 0x0101, 0x0107, 0x00E4, 0x00E5, 0x0119, 0x0113,
+    0x010D, 0x00E9, 0x017A, 0x0117, 0x0123, 0x0137, 0x012B, 0x013C,
+    0x0161, 0x0144, 0x0146, 0x00F3, 0x014D, 0x00F5, 0x00F6, 0x00F7,
+    0x0173, 0x014E, 0x015B, 0x016B, 0x00FC, 0x017C, 0x017E, 0x02D9
 };

 #elif _CODE_PAGE == 1258
 #define _TBLDEF 1
 static
-const uint16_t Tbl[] = {	/*  CP1258(0x80-0xFF) to Unicode conversion table */
-	0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
-	0x02C6, 0x2030, 0x0000, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000,
-	0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
-	0x02DC, 0x2122, 0x0000, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178,
-	0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
-	0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
-	0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
-	0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
-	0x00C0, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x00C5, 0x00C6, 0x00C7,
-	0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x0300, 0x00CD, 0x00CE, 0x00CF,
-	0x0110, 0x00D1, 0x0309, 0x00D3, 0x00D4, 0x01A0, 0x00D6, 0x00D7,
-	0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x01AF, 0x0303, 0x00DF,
-	0x00E0, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x00E5, 0x00E6, 0x00E7,
-	0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0301, 0x00ED, 0x00EE, 0x00EF,
-	0x0111, 0x00F1, 0x0323, 0x00F3, 0x00F4, 0x01A1, 0x00F6, 0x00F7,
-	0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x01B0, 0x20AB, 0x00FF
+const uint16_t Tbl[] =
+{
+    /*  CP1258(0x80-0xFF) to Unicode conversion table */
+    0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+    0x02C6, 0x2030, 0x0000, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+    0x02DC, 0x2122, 0x0000, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178,
+    0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+    0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+    0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+    0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
+    0x00C0, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x00C5, 0x00C6, 0x00C7,
+    0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x0300, 0x00CD, 0x00CE, 0x00CF,
+    0x0110, 0x00D1, 0x0309, 0x00D3, 0x00D4, 0x01A0, 0x00D6, 0x00D7,
+    0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x01AF, 0x0303, 0x00DF,
+    0x00E0, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x00E5, 0x00E6, 0x00E7,
+    0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0301, 0x00ED, 0x00EE, 0x00EF,
+    0x0111, 0x00F1, 0x0323, 0x00F3, 0x00F4, 0x01A1, 0x00F6, 0x00F7,
+    0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x01B0, 0x20AB, 0x00FF
 };

 #endif
@@ -499,42 +541,79 @@ const uint16_t Tbl[] = {	/*  CP1258(0x80-0xFF) to Unicode conversion table */


 uint16_t ff_convert (	/* Converted character, Returns zero on error */
-	uint16_t	src,	/* Character code to be converted */
-	uint32_t	dir		/* 0: Unicode to OEMCP, 1: OEMCP to Unicode */
-)
+                        uint16_t	src,	/* Character code to be converted */
+                        uint32_t	dir		/* 0: Unicode to OEMCP, 1: OEMCP to Unicode */
+                        )
 {
-	uint16_t c;
+    uint16_t c;


-	if (src < 0x80) {	/* ASCII */
-		c = src;
+    if (src < 0x80) {	/* ASCII */
+        c = src;

-	} else {
-		if (dir) {		/* OEMCP to Unicode */
-			c = (src >= 0x100) ? 0 : Tbl[src - 0x80];
+    } else {
+        if (dir) {		/* OEMCP to Unicode */
+            c = (src >= 0x100) ? 0 : Tbl[src - 0x80];

-		} else {		/* Unicode to OEMCP */
-			for (c = 0; c < 0x80; c++) {
-				if (src == Tbl[c]) break;
-			}
-			c = (c + 0x80) & 0xFF;
-		}
-	}
+        } else {		/* Unicode to OEMCP */
+            for (c = 0; c < 0x80; c++) {
+                if (src == Tbl[c]) break;
+            }
+            c = (c + 0x80) & 0xFF;
+        }
+    }

-	return c;
+    return c;
 }


 uint16_t ff_wtoupper (	/* Upper converted character */
-	uint16_t chr		/* Input character */
-)
+                        uint16_t chr		/* Input character */
+                        )
 {
-	static const uint16_t tbl_lower[] = { 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0xA1, 0x00A2, 0x00A3, 0x00A5, 0x00AC, 0x00AF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0x0FF, 0x101, 0x103, 0x105, 0x107, 0x109, 0x10B, 0x10D, 0x10F, 0x111, 0x113, 0x115, 0x117, 0x119, 0x11B, 0x11D, 0x11F, 0x121, 0x123, 0x125, 0x127, 0x129, 0x12B, 0x12D, 0x12F, 0x131, 0x133, 0x135, 0x137, 0x13A, 0x13C, 0x13E, 0x140, 0x142, 0x144, 0x146, 0x148, 0x14B, 0x14D, 0x14F, 0x151, 0x153, 0x155, 0x157, 0x159, 0x15B, 0x15D, 0x15F, 0x161, 0x163, 0x165, 0x167, 0x169, 0x16B, 0x16D, 0x16F, 0x171, 0x173, 0x175, 0x177, 0x17A, 0x17C, 0x17E, 0x192, 0x3B1, 0x3B2, 0x3B3, 0x3B4, 0x3B5, 0x3B6, 0x3B7, 0x3B8, 0x3B9, 0x3BA, 0x3BB, 0x3BC, 0x3BD, 0x3BE, 0x3BF, 0x3C0, 0x3C1, 0x3C3, 0x3C4, 0x3C5, 0x3C6, 0x3C7, 0x3C8, 0x3C9, 0x3CA, 0x430, 0x431, 0x432, 0x433, 0x434, 0x435, 0x436, 0x437, 0x438, 0x439, 0x43A, 0x43B, 0x43C, 0x43D, 0x43E, 0x43F, 0x440, 0x441, 0x442, 0x443, 0x444, 0x445, 0x446, 0x447, 0x448, 0x449, 0x44A, 0x44B, 0x44C, 0x44D, 0x44E, 0x44F, 0x451, 0x452, 0x453, 0x454, 0x455, 0x456, 0x457, 0x458, 0x459, 0x45A, 0x45B, 0x45C, 0x45E, 0x45F, 0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177, 0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F, 0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48, 0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, 0xFF50, 0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58, 0xFF59, 0xFF5A, 0 };
-	static const uint16_t tbl_upper[] = { 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x21, 0xFFE0, 0xFFE1, 0xFFE5, 0xFFE2, 0xFFE3, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0x178, 0x100, 0x102, 0x104, 0x106, 0x108, 0x10A, 0x10C, 0x10E, 0x110, 0x112, 0x114, 0x116, 0x118, 0x11A, 0x11C, 0x11E, 0x120, 0x122, 0x124, 0x126, 0x128, 0x12A, 0x12C, 0x12E, 0x130, 0x132, 0x134, 0x136, 0x139, 0x13B, 0x13D, 0x13F, 0x141, 0x143, 0x145, 0x147, 0x14A, 0x14C, 0x14E, 0x150, 0x152, 0x154, 0x156, 0x158, 0x15A, 0x15C, 0x15E, 0x160, 0x162, 0x164, 0x166, 0x168, 0x16A, 0x16C, 0x16E, 0x170, 0x172, 0x174, 0x176, 0x179, 0x17B, 0x17D, 0x191, 0x391, 0x392, 0x393, 0x394, 0x395, 0x396, 0x397, 0x398, 0x399, 0x39A, 0x39B, 0x39C, 0x39D, 0x39E, 0x39F, 0x3A0, 0x3A1, 0x3A3, 0x3A4, 0x3A5, 0x3A6, 0x3A7, 0x3A8, 0x3A9, 0x3AA, 0x410, 0x411, 0x412, 0x413, 0x414, 0x415, 0x416, 0x417, 0x418, 0x419, 0x41A, 0x41B, 0x41C, 0x41D, 0x41E, 0x41F, 0x420, 0x421, 0x422, 0x423, 0x424, 0x425, 0x426, 0x427, 0x428, 0x429, 0x42A, 0x42B, 0x42C, 0x42D, 0x42E, 0x42F, 0x401, 0x402, 0x403, 0x404, 0x405, 0x406, 0x407, 0x408, 0x409, 0x40A, 0x40B, 0x40C, 0x40E, 0x40F, 0x2160, 0x2161, 0x2162, 0x2163, 0x2164, 0x2165, 0x2166, 0x2167, 0x2168, 0x2169, 0x216A, 0x216B, 0x216C, 0x216D, 0x216E, 0x216F, 0xFF21, 0xFF22, 0xFF23, 0xFF24, 0xFF25, 0xFF26, 0xFF27, 0xFF28, 0xFF29, 0xFF2A, 0xFF2B, 0xFF2C, 0xFF2D, 0xFF2E, 0xFF2F, 0xFF30, 0xFF31, 0xFF32, 0xFF33, 0xFF34, 0xFF35, 0xFF36, 0xFF37, 0xFF38, 0xFF39, 0xFF3A, 0 };
-	int i;
+    static const uint16_t tbl_lower[] =
+    {
+        0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
+        0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70,
+        0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
+        0x79, 0x7A, 0xA1, 0x00A2, 0x00A3, 0x00A5, 0x00AC, 0x00AF,
+        0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7,
+        0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF,
+        0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF8,
+        0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0x0FF, 0x101,
+        0x103, 0x105, 0x107, 0x109, 0x10B, 0x10D, 0x10F,
+        0x111, 0x113, 0x115, 0x117, 0x119, 0x11B, 0x11D,
+        0x11F, 0x121, 0x123, 0x125, 0x127, 0x129, 0x12B,
+        0x12D, 0x12F, 0x131, 0x133, 0x135, 0x137, 0x13A,
+        0x13C, 0x13E, 0x140, 0x142, 0x144, 0x146, 0x148,
+        0x14B, 0x14D, 0x14F, 0x151, 0x153, 0x155, 0x157,
+        0x159, 0x15B, 0x15D, 0x15F, 0x161, 0x163, 0x165,
+        0x167, 0x169, 0x16B, 0x16D, 0x16F, 0x171, 0x173,
+        0x175, 0x177, 0x17A, 0x17C, 0x17E, 0x192, 0x3B1,
+        0x3B2, 0x3B3, 0x3B4, 0x3B5, 0x3B6, 0x3B7, 0x3B8,
+        0x3B9, 0x3BA, 0x3BB, 0x3BC, 0x3BD, 0x3BE, 0x3BF,
+        0x3C0, 0x3C1, 0x3C3, 0x3C4, 0x3C5, 0x3C6, 0x3C7,
+        0x3C8, 0x3C9, 0x3CA, 0x430, 0x431, 0x432, 0x433,
+        0x434, 0x435, 0x436, 0x437, 0x438, 0x439, 0x43A,
+        0x43B, 0x43C, 0x43D, 0x43E, 0x43F, 0x440, 0x441,
+        0x442, 0x443, 0x444, 0x445, 0x446, 0x447, 0x448,
+        0x449, 0x44A, 0x44B, 0x44C, 0x44D, 0x44E, 0x44F,
+        0x451, 0x452, 0x453, 0x454, 0x455, 0x456, 0x457,
+        0x458, 0x459, 0x45A, 0x45B, 0x45C, 0x45E, 0x45F,
+        0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177,
+        0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F,
+        0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48,
+        0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, 0xFF50,
+        0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58,
+        0xFF59, 0xFF5A, 0
+    };
+    static const uint16_t tbl_upper[] =
+    {
+        0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x21, 0xFFE0, 0xFFE1, 0xFFE5, 0xFFE2, 0xFFE3, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0x178, 0x100, 0x102, 0x104, 0x106, 0x108, 0x10A, 0x10C, 0x10E, 0x110, 0x112, 0x114, 0x116, 0x118, 0x11A, 0x11C, 0x11E, 0x120, 0x122, 0x124, 0x126, 0x128, 0x12A, 0x12C, 0x12E, 0x130, 0x132, 0x134, 0x136, 0x139, 0x13B, 0x13D, 0x13F, 0x141, 0x143, 0x145, 0x147, 0x14A, 0x14C, 0x14E, 0x150, 0x152, 0x154, 0x156, 0x158, 0x15A, 0x15C, 0x15E, 0x160, 0x162, 0x164, 0x166, 0x168, 0x16A, 0x16C, 0x16E, 0x170, 0x172, 0x174, 0x176, 0x179, 0x17B, 0x17D, 0x191, 0x391, 0x392, 0x393, 0x394, 0x395, 0x396, 0x397, 0x398, 0x399, 0x39A, 0x39B, 0x39C, 0x39D, 0x39E, 0x39F, 0x3A0, 0x3A1, 0x3A3, 0x3A4, 0x3A5, 0x3A6, 0x3A7, 0x3A8, 0x3A9, 0x3AA, 0x410, 0x411, 0x412, 0x413, 0x414, 0x415, 0x416, 0x417, 0x418, 0x419, 0x41A, 0x41B, 0x41C, 0x41D, 0x41E, 0x41F, 0x420, 0x421, 0x422, 0x423, 0x424, 0x425, 0x426, 0x427, 0x428, 0x429, 0x42A, 0x42B, 0x42C, 0x42D, 0x42E, 0x42F, 0x401, 0x402, 0x403, 0x404, 0x405, 0x406, 0x407, 0x408, 0x409, 0x40A, 0x40B, 0x40C, 0x40E, 0x40F, 0x2160, 0x2161, 0x2162, 0x2163, 0x2164, 0x2165, 0x2166, 0x2167, 0x2168, 0x2169, 0x216A, 0x216B, 0x216C, 0x216D, 0x216E, 0x216F, 0xFF21, 0xFF22, 0xFF23, 0xFF24, 0xFF25, 0xFF26, 0xFF27, 0xFF28, 0xFF29, 0xFF2A, 0xFF2B, 0xFF2C, 0xFF2D, 0xFF2E, 0xFF2F, 0xFF30, 0xFF31, 0xFF32, 0xFF33, 0xFF34, 0xFF35, 0xFF36, 0xFF37, 0xFF38, 0xFF39, 0xFF3A, 0 };
+    int i;


-	for (i = 0; tbl_lower[i] && chr != tbl_lower[i]; i++) ;
+    for (i = 0; tbl_lower[i] && chr != tbl_lower[i]; i++) ;

-	return tbl_lower[i] ? tbl_upper[i] : chr;
+    return tbl_lower[i] ? tbl_upper[i] : chr;
 }
--- a/fs/ff.c
+++ b/fs/ff.c
--- a/if/driver_vec.c
+++ b/if/driver_vec.c
@@ -124,6 +124,33 @@ static struct pci_bios_interface pci_interface =
    .phys_to_virt = wrapper_phys_to_virt,
 };

+static struct pci_native_driver_interface_0_1 pci_native_interface_0_1 =
+{
+    .pci_read_config_longword = pci_read_config_longword,
+    .pci_read_config_word = pci_read_config_word,
+    .pci_read_config_byte = pci_read_config_byte,
+    .pci_write_config_longword = pci_write_config_longword,
+    .pci_write_config_word = pci_write_config_word,
+    .pci_write_config_byte = pci_write_config_byte,
+    .pci_hook_interrupt = pci_hook_interrupt,
+    .pci_unhook_interrupt = pci_unhook_interrupt,
+    .pci_get_resource = pci_get_resource,
+};
+
+static struct pci_native_driver_interface pci_native_interface =
+{
+    .pci_read_config_longword = pci_read_config_longword,
+    .pci_read_config_word = pci_read_config_word,
+    .pci_read_config_byte = pci_read_config_byte,
+    .pci_write_config_longword = pci_write_config_longword,
+    .pci_write_config_word = pci_write_config_word,
+    .pci_write_config_byte = pci_write_config_byte,
+    .pci_hook_interrupt = pci_hook_interrupt,
+    .pci_unhook_interrupt = pci_unhook_interrupt,
+    .pci_find_device = pci_find_device,
+    .pci_find_classcode = pci_find_classcode,
+    .pci_get_resource = pci_get_resource,
+};
 /*
 * driver interface struct for the BaS framebuffer video driver
 */
@@ -187,6 +214,23 @@ static struct generic_interface interfaces[] =
        .revision = 1,
        .interface.mmu = &mmu_interface,
    },
+    {
+        .type = PCI_NATIVE_DRIVER,
+        .name = "PCI_N",
+        .description = "BaS PCI native",
+        .version = 0,
+        .revision = 1,
+        .interface.pci_native = (struct pci_native_driver_interface *) &pci_native_interface_0_1,
+    },
+    {
+        .type = PCI_NATIVE_DRIVER,
+        .name = "PCI_N",
+        .description = "BaS PCI native",
+        .version = 0,
+        .revision = 2,
+        .interface.pci_native = &pci_native_interface,
+    },
+
    /* insert new drivers here */

    {
@@ -215,36 +259,41 @@ void remove_handler(void)
    *trap_0_vector = (uint32_t) std_exc_vec;
 }

+/*
+ * trap #0 entry point
+ *
+ * this is used to retrieve the driver table that gets exposed to the OS by BaS
+ */
 void __attribute__((interrupt)) get_bas_drivers(void)
 {
    __asm__ __volatile(
        /*
-         * sp should now point to the next instruction after the trap
+         * (sp) should now point to the next instruction after the trap
         * The trap itself is 2 bytes, the four bytes before that must
-         * read '_BAS' or we are not meant by this call
+         * read '_BAS', otherwise we are not meant by this call
         */
-        "		move.l	a0,-(sp)				\n\t"	// save registers
+        "       move.l  a0,-(sp)                \n\t"   // save registers
        "       move.l  d0,-(sp)                \n\t"
-        "		move.l	12(sp),a0         		\n\t"	// get return address
+        "       move.l  12(sp),a0               \n\t"   // get return address
        "       move.l  -6(a0),d0               \n\t"   //
-        "		cmp.l	#0x5f424153,d0			\n\t"	// is it '_BAS'?
-        "		beq		fetch_drivers			\n\t"	// yes
+        "       cmp.l   #0x5f424153,d0          \n\t"   // is it '_BAS'?
+        "       beq     fetch_drivers           \n\t"   // yes
        /*
         * This seems indeed a "normal" trap #0. Better pass control to "normal" trap #0 processing
         * If trap #0 isn't set to something sensible, we'll probably crash here, but this must be
         * prevented on the caller side.
         */
-        "		move.l	(sp)+,d0				\n\t"	// restore registers
-        "		move.l	(sp)+,a0				\n\t"
-        "		move.l	0x80,-(sp)				\n\t"	// fetch vector
-        "		rts								\n\t"	// and jump through it
+        "       move.l  (sp)+,d0                \n\t"   // restore registers
+        "       move.l  (sp)+,a0                \n\t"
+        "       move.l  0x80,-(sp)              \n\t"   // fetch vector
+        "       rts                             \n\t"   // and jump through it

-        "fetch_drivers:							\n\t"
-        "		move.l	#%[drivers],d0			\n\t"	// return driver struct in d0
-        "		addq.l	#4,sp					\n\t"	// adjust stack
+        "fetch_drivers:                         \n\t"
+        "       move.l	#%[drivers],d0          \n\t"   // return driver struct in d0
+        "       addq.l	#4,sp                   \n\t"   // adjust stack
        "       move.l  (sp)+,a0                \n\t"   // restore register
-        :	                            /* no output */
-        :	[drivers] "o" (bas_drivers)		/* input */
-        :									/* clobber */
+        :                                   /* no output */
+        :   [drivers] "o" (bas_drivers)     /* input */
+        :                                   /* clobber */
    );
 }
--- a/include/bas_utils.h
+++ b/include/bas_utils.h
@@ -26,4 +26,7 @@
 #define CLEAR_BIT(p,bit)        p &= ~(bit)
 #define CLEAR_BIT_NO(p,nr)      CLEAR_BIT(p, (1 << (nr)))

+extern void write_pic_byte(uint8_t value);
+extern uint8_t read_pic_byte(void);
+
 #endif /* _BAS_UTILS_H_ */
--- a/include/driver_vec.h
+++ b/include/driver_vec.h
@@ -38,7 +38,8 @@ enum driver_type
    VIDEO_DRIVER,
    PCI_DRIVER,
    MMU_DRIVER,
-    END_OF_DRIVERS = 0xffffffff,        /* marks end of driver list */
+    PCI_NATIVE_DRIVER,
+    END_OF_DRIVERS = 0xffffffffL,        /* marks end of driver list */
 };

 struct generic_driver_interface
@@ -264,12 +265,43 @@ struct pci_bios_interface

 struct mmu_driver_interface
 {
-    int32_t (*map_page_locked)(uint32_t address, uint32_t length, int asid);
-    int32_t (*unlock_page)(uint32_t address, uint32_t length, int asid);
-    int32_t (*report_locked_pages)(uint32_t *num_itlb, uint32_t *num_dtlb);
+    uint32_t (*map_page_locked)(uint32_t address, uint32_t length, int asid);
+    uint32_t (*unlock_page)(uint32_t address, uint32_t length, int asid);
+    uint32_t (*report_locked_pages)(uint32_t *num_itlb, uint32_t *num_dtlb);
    uint32_t (*report_pagesize)(void);
 };

+struct pci_native_driver_interface_0_1
+{
+    uint32_t (*pci_read_config_longword)(int32_t handle, int offset);
+    uint16_t (*pci_read_config_word)(int32_t handle, int offset);
+    uint8_t (*pci_read_config_byte)(int32_t handle, int offset);
+
+    int32_t (*pci_write_config_longword)(int32_t handle, int offset, uint32_t value);
+    int32_t (*pci_write_config_word)(int32_t handle, int offset, uint16_t value);
+    int32_t (*pci_write_config_byte)(int32_t handle, int offset, uint8_t value);
+    int32_t (*pci_hook_interrupt)(int32_t handle, void *handler, void *parameter);
+    int32_t (*pci_unhook_interrupt)(int32_t handle);
+
+    struct pci_rd * (*pci_get_resource)(int32_t handle);
+};
+
+struct pci_native_driver_interface
+{
+    uint32_t (*pci_read_config_longword)(int32_t handle, int offset);
+    uint16_t (*pci_read_config_word)(int32_t handle, int offset);
+    uint8_t (*pci_read_config_byte)(int32_t handle, int offset);
+
+    int32_t (*pci_write_config_longword)(int32_t handle, int offset, uint32_t value);
+    int32_t (*pci_write_config_word)(int32_t handle, int offset, uint16_t value);
+    int32_t (*pci_write_config_byte)(int32_t handle, int offset, uint8_t value);
+    int32_t (*pci_hook_interrupt)(int32_t handle, void *handler, void *parameter);
+    int32_t (*pci_unhook_interrupt)(int32_t handle);
+    int32_t (*pci_find_device)(uint16_t device_id, uint16_t vendor_id, int index);
+    int32_t (*pci_find_classcode)(uint32_t classcode, int index);
+    struct pci_rd * (*pci_get_resource)(int32_t handle);
+};
+
 union interface
 {
    struct generic_driver_interface *gdi;
@@ -278,6 +310,8 @@ union interface
    struct framebuffer_driver_interface *fb;
    struct pci_bios_interface *pci;
    struct mmu_driver_interface *mmu;
+    struct pci_native_driver_interface_0_1 *pci_native_0_1;
+    struct pci_native_driver_interface *pci_native;
 };

 struct generic_interface
--- a/include/exceptions.h
+++ b/include/exceptions.h
@@ -3,26 +3,6 @@

 #include <bas_types.h>

-static inline uint32_t set_ipl(uint32_t ipl)
-{
-	uint32_t ret;
-
-	__asm__ __volatile__(
-		"		move.w	sr,%[ret]\r\n"			/* retrieve status register */
-		"		andi.l	#0x07,%[ipl]\n\t"		/* mask out ipl bits on new value */
-		"		lsl.l	#8,%[ipl]\n\t"			/* shift them to position */
-		"		move.l	%[ret],d0\n\t"			/* retrieve original value */
-		"		andi.l	#0x0000f8ff,d0\n\t"		/* clear ipl part */
-		"		or.l	%[ipl],d0\n\t"			/* or in new value */
-		"		move.w	d0,sr\n\t"				/* put it in place */
-		"		andi.l	#0x0700,%[ret]\r\n"		/* mask out ipl bits */
-		"		lsr.l	#8,%[ret]\r\n"			/* shift them to position */
-		: [ret] "=&d" (ret)		/* output */
-		: [ipl] "d" (ipl)		/* input */
-		: "cc", "d0"	/* clobber */
-	);
-
-	return ret;
-}
+extern uint32_t set_ipl(uint32_t ipl);

 #endif /* _EXCEPTIONS_H_ */
--- a/include/firebee.h
+++ b/include/firebee.h
@@ -30,7 +30,7 @@
 #define SYSCLK			132000		/* NOTE: 132 _is_ correct. 133 _is_ wrong. Do not change! */

 #define BOOTFLASH_BASE_ADDRESS		0xE0000000
-#define BOOTFLASH_SIZE				0x800000		/* FireBee has 8 MByte Flash */
+#define BOOTFLASH_SIZE				0x800000                /* FireBee has 8 MByte Flash */
 #define BOOTFLASH_BAM				(BOOTFLASH_SIZE - 1)

 #define SDRAM_START					0x00000000	/* start at address 0 */
--- a/include/mmu.h
+++ b/include/mmu.h
@@ -64,13 +64,14 @@ enum mmu_page_size
    MMU_PAGE_SIZE_1K	= 3
 };

+#define MMU_PAGE_SIZE_DEFAULT   MMU_PAGE_SIZE_1M    /* note: if this changes, SIZE_DEFAULT below _must_ also change */
+
 #define SIZE_1M             0x100000        /* 1 Megabyte */
 #define SIZE_4K             0x1000          /* 4 KB */
 #define SIZE_8K             0x2000          /* 8 KB */
 #define SIZE_1K             0x400           /* 1 KB */

-#define DEFAULT_PAGE_SIZE   0x00100000      /* 1M pagesize */
-
+#define SIZE_DEFAULT        SIZE_1M
 /*
 * cache modes
 */
@@ -97,16 +98,25 @@ enum mmu_page_size
 extern long video_tlb;
 extern long video_sbt;

-struct mmu_page_descriptor;
+struct mmu_page_descriptor
+{
+    uint8_t cache_mode          : 2;
+    uint8_t supervisor_protect  : 1;
+    uint8_t read                : 1;
+    uint8_t write               : 1;
+    uint8_t execute             : 1;
+    uint8_t global              : 1;
+    uint8_t locked              : 1;
+};

 extern void mmu_init(void);
-extern int mmu_map_page(int32_t virt, int32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor *flags);
+extern uint32_t mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor *flags);

 /*
 * API functions for the BaS driver interface
 */
-extern int32_t mmu_map_data_page_locked(uint32_t address, uint32_t length, int asid);
-extern int32_t mmu_unlock_data_page(uint32_t address, uint32_t length, int asid);
-extern int32_t mmu_report_locked_pages(uint32_t *num_itlb, uint32_t *num_dtlb);
+extern uint32_t mmu_map_data_page_locked(uint32_t address, uint32_t length, int asid);
+extern uint32_t mmu_unlock_data_page(uint32_t address, uint32_t length, int asid);
+extern uint32_t mmu_report_locked_pages(uint32_t *num_itlb, uint32_t *num_dtlb);
 extern uint32_t mmu_report_pagesize(void);
 #endif /* _MMU_H_ */
--- a/include/pci.h
+++ b/include/pci.h
@@ -22,12 +22,12 @@
 */

 #include <bas_types.h>
-#include "util.h" 	/* for swpX() */
+#include "util.h"   /* for swpX() */

-#define	 PCI_MEMORY_OFFSET	(0x80000000)
-#define	 PCI_MEMORY_SIZE	(0x40000000)	/* 1 GByte PCI memory window */
-#define	 PCI_IO_OFFSET		(0xD0000000)
-#define	 PCI_IO_SIZE		(0x10000000)	/* 128 MByte PCI I/O window */
+#define  PCI_MEMORY_OFFSET  0x80000000
+#define  PCI_MEMORY_SIZE    0x40000000  /* 1 GByte PCI memory window */
+#define  PCI_IO_OFFSET      0xD0000000
+#define  PCI_IO_SIZE        0x10000000  /* 128 MByte PCI I/O window */

 /*
 * Note: the byte offsets are in little endian format, so you can't use them
@@ -81,32 +81,32 @@
 /*
 * bit definitions for PCICSR lower half (Command Register)
 */
-#define	PCICSR_IO			(1 << 0)	/* if set: device responds to I/O space accesses */
-#define	PCICSR_MEMORY		(1 << 1)	/* if set: device responds to memory space accesses */
-#define PCICSR_MASTER		(1 << 2)	/* if set: device is master */
-#define PCICSR_SPECIAL		(1 << 3)	/* if set: device reacts on special cycles */
-#define PCICSR_MEMWI		(1 << 4)	/* if set: device deals with memory write and invalidate */
-#define	PCICSR_VGA_SNOOP	(1 << 5)	/* if set: capable of palette snoop */
-#define PCICSR_PERR			(1 << 6)	/* if set: reacts to parity errors */
-#define PCICSR_STEPPING		(1 << 7)	/* if set: stepping enabled */
-#define PCICSR_SERR			(1 << 8)	/* if set: SERR pin enabled */
-#define PCICSR_FAST_BTOB_E	(1 << 9)	/* if set: fast back-to-back enabled */
+#define PCICSR_IO           (1 << 0)    /* if set: device responds to I/O space accesses */
+#define PCICSR_MEMORY       (1 << 1)    /* if set: device responds to memory space accesses */
+#define PCICSR_MASTER       (1 << 2)    /* if set: device is master */
+#define PCICSR_SPECIAL      (1 << 3)    /* if set: device reacts on special cycles */
+#define PCICSR_MEMWI        (1 << 4)    /* if set: device deals with memory write and invalidate */
+#define PCICSR_VGA_SNOOP    (1 << 5)    /* if set: capable of palette snoop */
+#define PCICSR_PERR         (1 << 6)    /* if set: reacts to parity errors */
+#define PCICSR_STEPPING     (1 << 7)    /* if set: stepping enabled */
+#define PCICSR_SERR         (1 << 8)    /* if set: SERR pin enabled */
+#define PCICSR_FAST_BTOB_E  (1 << 9)    /* if set: fast back-to-back enabled */
 #define PCICSR_INT_DISABLE  (1 << 10)   /* if set: disable interrupts from this device */
 /*
 * bit definitions for PCICSR upper half (Status Register)
 */
 #define PCICSR_INTERRUPT    (1 << 3)    /* device requested interrupt */
 #define PCICSR_CAPABILITIES (1 << 4)    /* if set, capabilities pointer is valid */
-#define PCICSR_66MHZ		(1 << 5)	/* 66 MHz capable */
-#define PCICSR_UDF			(1 << 6)	/* UDF supported */
-#define PCICSR_FAST_BTOB	(1 << 7)	/* Fast back-to-back enabled */
-#define PCICSR_DPARITY_ERROR	(1 << 8)	/* data parity error detected */
+#define PCICSR_66MHZ        (1 << 5)    /* 66 MHz capable */
+#define PCICSR_UDF          (1 << 6)    /* UDF supported */
+#define PCICSR_FAST_BTOB    (1 << 7)    /* Fast back-to-back enabled */
+#define PCICSR_DPARITY_ERROR    (1 << 8)    /* data parity error detected */

-#define PCICSR_T_ABORT_S	(1 << 11)	/* target abort signaled */
-#define PCICSR_T_ABORT_R	(1 << 12)	/* target abort received */
-#define PCICSR_M_ABORT_R	(1 << 13)	/* master abort received */
-#define PCICSR_S_ERROR_S	(1 << 14)	/* system error signaled */
-#define PCICSR_PARITY_ERR	(1 << 15)	/* data parity error */
+#define PCICSR_T_ABORT_S    (1 << 11)   /* target abort signaled */
+#define PCICSR_T_ABORT_R    (1 << 12)   /* target abort received */
+#define PCICSR_M_ABORT_R    (1 << 13)   /* master abort received */
+#define PCICSR_S_ERROR_S    (1 << 14)   /* system error signaled */
+#define PCICSR_PARITY_ERR   (1 << 15)   /* data parity error */

 /* Header type 1 (PCI-to-PCI bridges) */
 #define PCI_PRIMARY_BUS        0x18  /* Primary bus number */
@@ -134,7 +134,7 @@ struct pci_rd          /* structure of resource descriptor    */
    unsigned long length;              /* length of resource                  */
    unsigned long offset;              /* offset PCI to phys. CPU Address     */
    unsigned long dmaoffset;           /* offset for DMA-transfers            */
-} __attribute__ ((packed));
+};

 typedef struct                       /* structure of address conversion     */
 {
@@ -186,43 +186,43 @@ typedef struct                       /* structure of address conversion     */
 /* PCI configuration space macros */

 /* register 0x00 macros */
-#define PCI_VENDOR_ID(i)	swpw((uint16_t)(((i) & 0xffff0000) >> 16))
-#define PCI_DEVICE_ID(i)	swpw((uint16_t) ((i) & 0xffff))
+#define PCI_VENDOR_ID(i)    swpw((uint16_t)(((i) & 0xffff0000) >> 16))
+#define PCI_DEVICE_ID(i)    swpw((uint16_t) ((i) & 0xffff))

 /* register 0x04 macros */
-#define PCI_STATUS(i)		((i) & 0xffff)
-#define PCI_COMMAND(i)		(((i) >> 16) & 0xffff)
+#define PCI_STATUS(i)       ((i) & 0xffff)
+#define PCI_COMMAND(i)      (((i) >> 16) & 0xffff)

 /* register 0x08 macros */
-#define PCI_CLASS_CODE(i)	((swpl((i)) & 0xffff0000) >> 16)
-#define PCI_SUBCLASS(i)		((swpl((i)) & 0xffffff00) >> 8)
-#define PCI_PROG_IF(i)		((swpl((i)) & 0x0000ff00) >> 8)
-#define PCI_REVISION_ID(i)	((swpl((i)) & 0x000000ff))
+#define PCI_CLASS_CODE(i)   ((swpl((i)) & 0xff000000) >> 24)
+#define PCI_SUBCLASS(i)     ((swpl((i)) & 0x00ff0000) >> 16)
+#define PCI_PROG_IF(i)      ((swpl((i)) & 0x0000ff00) >> 8)
+#define PCI_REVISION_ID(i)  ((swpl((i)) & 0x000000ff))

 /* register 0x0c macros */
-#define PCI_BIST(i)			((swpl((i)) & 0xff000000) >> 24)
-#define PCI_HEADER_TYPE(i)	((swpl((i)) & 0x00ff0000) >> 16)
-#define PCI_LAT_TIMER(i)	((swpl((i)) & 0x0000ff00) >> 8)
-#define PCI_CACHELINE_SIZE(i)	((swpl((i)) & 0x000000ff))
+#define PCI_BIST(i)         ((swpl((i)) & 0xff000000) >> 24)
+#define PCI_HEADER_TYPE(i)  ((swpl((i)) & 0x00ff0000) >> 16)
+#define PCI_LAT_TIMER(i)    ((swpl((i)) & 0x0000ff00) >> 8)
+#define PCI_CACHELINE_SIZE(i)   ((swpl((i)) & 0x000000ff))

 /* register 0x2c macros */
-#define PCI_SUBSYS_ID(i)	(((i) & 0xffff0000) >> 16)
-#define PCI_SUBSYS_VID(i)	(((i) & 0xffff))
+#define PCI_SUBSYS_ID(i)    (((i) & 0xffff0000) >> 16)
+#define PCI_SUBSYS_VID(i)   (((i) & 0xffff))

 /* register 0x34 macros */
-#define PCI_CAPABILITIES(i)	((i) & 0xff)
+#define PCI_CAPABILITIES(i) ((i) & 0xff)

 /* register 0x3c macros */
-#define PCI_MAX_LATENCY(i)	(((i) & 0xff000000) >> 24)
-#define PCI_MIN_GRANT(i)	(((i) & 0xff0000) >> 16)
-#define PCI_INTERRUPT_PIN(i)	(((i) & 0xff00) >> 8)
-#define PCI_INTERRUPT_LINE(i)	(((i)) & 0xff)
+#define PCI_MAX_LATENCY(i)  (((i) & 0xff000000) >> 24)
+#define PCI_MIN_GRANT(i)    (((i) & 0xff0000) >> 16)
+#define PCI_INTERRUPT_PIN(i)    (((i) & 0xff00) >> 8)
+#define PCI_INTERRUPT_LINE(i)   (((i)) & 0xff)

-#define IS_PCI_MEM_BAR(i)	((i) & 1) == 0
-#define IS_PCI_IO_BAR(i)	((i) & 1) == 1
-#define PCI_MEMBAR_TYPE(i)	(((i) & 0x6) >> 1)
-#define PCI_IOBAR_ADR(i)	(((i) & 0xfffffffc))
-#define PCI_MEMBAR_ADR(i)	(((i) & 0xfffffff0))
+#define IS_PCI_MEM_BAR(i)   ((i) & 1) == 0
+#define IS_PCI_IO_BAR(i)    ((i) & 1) == 1
+#define PCI_MEMBAR_TYPE(i)  (((i) & 0x6) >> 1)
+#define PCI_IOBAR_ADR(i)    (((i) & 0xfffffffc))
+#define PCI_MEMBAR_ADR(i)   (((i) & 0xfffffff0))

 extern void init_eport(void);
 extern void init_xlbus_arbiter(void);
@@ -238,9 +238,9 @@ extern int32_t pci_call_interrupt_chain(int32_t handle, int32_t data);
 /*
 * match bits for pci_find_classcode()
 */
-#define PCI_FIND_BASE_CLASS		(1 << 26)
-#define PCI_FIND_SUB_CLASS		(1 << 25)
-#define PCI_FIND_PROG_IF		(1 << 24)
+#define PCI_FIND_BASE_CLASS     (1 << 26)
+#define PCI_FIND_SUB_CLASS      (1 << 25)
+#define PCI_FIND_PROG_IF        (1 << 24)

 extern uint32_t pci_read_config_longword(int32_t handle, int offset);
 extern uint16_t pci_read_config_word(int32_t handle, int offset);
@@ -340,14 +340,14 @@ extern int32_t wrapper_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_AD
 extern int32_t wrapper_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer);
 extern int32_t wrapper_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);

-#define PCI_MK_CONF_ADDR(bus, device, function)	(MCF_PCI_PCICAR_E | \
+#define PCI_MK_CONF_ADDR(bus, device, function) (MCF_PCI_PCICAR_E | \
                                                ((bus) << 16) | \
                                                ((device << 8) | \
                                                (function))

-#define PCI_HANDLE(bus, slot, function)	(0 | ((bus & 0xff) << 10 | (slot & 0x1f) << 3 | (function & 7)))
-#define PCI_BUS_FROM_HANDLE(h)				(((h) & 0xff00) >> 10)
-#define PCI_DEVICE_FROM_HANDLE(h)			(((h) & 0xf8) >> 3)
-#define PCI_FUNCTION_FROM_HANDLE(h)			(((h) & 0x7))
+#define PCI_HANDLE(bus, slot, function) (0 | ((bus & 0xff) << 10 | (slot & 0x1f) << 3 | (function & 7)))
+#define PCI_BUS_FROM_HANDLE(h)              (((h) & 0xff00) >> 10)
+#define PCI_DEVICE_FROM_HANDLE(h)           (((h) & 0xf8) >> 3)
+#define PCI_FUNCTION_FROM_HANDLE(h)         (((h) & 0x7))

 #endif /* _PCI_H_ */
--- a/include/pci_errata.h
+++ b/include/pci_errata.h
@@ -0,0 +1,11 @@
+#ifndef PCI_ERRATA_H
+#define PCI_ERRATA_H
+
+#include <stdint.h>
+
+
+extern void chip_errata_135(void);
+extern void chip_errata_055(int32_t handle);
+
+#endif // PCI_ERRATA_H
+
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -45,7 +45,7 @@
 #define PCI_CLASS_BRIDGE_HOST		0x0600
 #define PCI_CLASS_BRIDGE_ISA		0x0601
 #define PCI_CLASS_BRIDGE_EISA		0x0602
-#define PCI_CLASS_BRIDGE_MC		0x0603
+#define PCI_CLASS_BRIDGE_MC         0x0603
 #define PCI_CLASS_BRIDGE_PCI		0x0604
 #define PCI_CLASS_BRIDGE_PCMCIA		0x0605
 #define PCI_CLASS_BRIDGE_NUBUS		0x0606
--- a/include/setjmp.h
+++ b/include/setjmp.h
@@ -0,0 +1,11 @@
+#ifndef _SETJMP_H_
+#define _SETJMP_H_
+
+#include "bas_types.h"
+
+typedef uint32_t jmp_buf[18];
+
+extern int setjmp(jmp_buf env);
+extern void longjmp(jmp_buf env, int val);
+
+#endif /* _SETJMP_H_ */
--- a/include/util.h
+++ b/include/util.h
@@ -61,13 +61,13 @@ static inline uint32_t swpl(uint32_t l)
 	__asm__ __volatile__
 	(
 		"lea		%[input],a0\n\t"				\
-		"mvz.b	3(a0),%[output]\n\t"			\
-		"lsl.l	#8,%[output]\n\t"				\
-		"move.b	2(a0),%[output]\n\t"			\
-		"lsl.l	#8,%[output]\n\t"				\
-		"move.b	1(a0),%[output]\n\t"			\
-		"lsl.l	#8,%[output]\n\t"				\
-		"move.b	(a0),%[output]\n\t"			\
+        "mvz.b      3(a0),%[output]\n\t"			\
+        "lsl.l      #8,%[output]\n\t"				\
+        "move.b     2(a0),%[output]\n\t"			\
+        "lsl.l      #8,%[output]\n\t"				\
+        "move.b     1(a0),%[output]\n\t"			\
+        "lsl.l      #8,%[output]\n\t"				\
+        "move.b     (a0),%[output]\n\t"			\
 		:	[output] "=d" (result)	/* output */
 		:	[input] "o" (l)			/* input */
 		: "cc", "a0", "memory"	/* clobbered */
--- a/include/version.h
+++ b/include/version.h
@@ -28,8 +28,8 @@
 * increment version number for release
 */

-#define MAJOR_VERSION	0
-#define MINOR_VERSION	87
+#define MAJOR_VERSION   0
+#define MINOR_VERSION   91


 #endif /* VERSION_H_ */
--- a/include/videl.h
+++ b/include/videl.h
@@ -83,8 +83,8 @@ extern int16_t vsetmode(int16_t mode);
 extern int16_t vmontype(void);
 extern int16_t vsetsync(int16_t external);
 extern int32_t vgetsize(int16_t mode);
-extern int16_t vsetrgb(int16_t index,int16_t count,int32_t *rgb);
-extern int16_t vgetrgb(int16_t index,int16_t count,int32_t *rgb);
+extern int16_t vsetrgb(int16_t index,int16_t count, uint32_t *rgb);
+extern int16_t vgetrgb(int16_t index,int16_t count, uint32_t *rgb);

 /* misc routines */
 extern int16_t get_videl_mode(void);
--- a/include/x86debug.h
+++ b/include/x86debug.h
@@ -1,241 +0,0 @@
-/****************************************************************************
-*
-*						Realmode X86 Emulator Library
-*
-*            	Copyright (C) 1996-1999 SciTech Software, Inc.
-* 				     Copyright (C) David Mosberger-Tang
-* 					   Copyright (C) 1999 Egbert Eich
-*
-*  ========================================================================
-*
-*  Permission to use, copy, modify, distribute, and sell this software and
-*  its documentation for any purpose is hereby granted without fee,
-*  provided that the above copyright notice appear in all copies and that
-*  both that copyright notice and this permission notice appear in
-*  supporting documentation, and that the name of the authors not be used
-*  in advertising or publicity pertaining to distribution of the software
-*  without specific, written prior permission.  The authors makes no
-*  representations about the suitability of this software for any purpose.
-*  It is provided "as is" without express or implied warranty.
-*
-*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
-*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
-*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
-*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
-*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
-*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
-*  PERFORMANCE OF THIS SOFTWARE.
-*
-*  ========================================================================
-*
-* Language:		ANSI C
-* Environment:	Any
-* Developer:    Kendall Bennett
-*
-* Description:  Header file for debug definitions.
-*
-****************************************************************************/
-/* $XFree86: xc/extras/x86emu/src/x86emu/x86emu/debug.h,v 1.4 2000/11/21 23:10:27 tsi Exp $ */
-
-#include <bas_types.h>
-#include "bas_printf.h"
-
-/*
- * for the X86 emulator, debug cannot be enabled and disabled on a per-file mode
- * as with all the other modules. It must be centrally enabled here.
- */
-
-#define DBG_X86EMU
-
-#ifdef DBG_X86EMU
-#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
-#else
-#define dbg(format, arg...) do { ; } while (0)
-#endif /* DBG_X86EMU */
-
-#ifndef __X86EMU_DEBUG_H
-#define __X86EMU_DEBUG_H
-
-/*---------------------- Macros and type definitions ----------------------*/
-
-/* checks to be enabled for "runtime" */
-
-#define CHECK_IP_FETCH_F                0x1
-#define CHECK_SP_ACCESS_F               0x2
-#define CHECK_MEM_ACCESS_F              0x4 /*using regular linear pointer */
-#define CHECK_DATA_ACCESS_F             0x8 /*using segment:offset*/
-
-#ifdef DBG_X86EMU
-# define CHECK_IP_FETCH()              	(M.x86.check & CHECK_IP_FETCH_F)
-# define CHECK_SP_ACCESS()             	(M.x86.check & CHECK_SP_ACCESS_F)
-# define CHECK_MEM_ACCESS()            	(M.x86.check & CHECK_MEM_ACCESS_F)
-# define CHECK_DATA_ACCESS()           	(M.x86.check & CHECK_DATA_ACCESS_F)
-#else
-# define CHECK_IP_FETCH()
-# define CHECK_SP_ACCESS()
-# define CHECK_MEM_ACCESS()
-# define CHECK_DATA_ACCESS()
-#endif
-
-#ifdef DBG_X86EMU
-# define DEBUG_INSTRUMENT()    	(M.x86.debug & DEBUG_INSTRUMENT_F)
-# define DEBUG_DECODE()        	(M.x86.debug & DEBUG_DECODE_F)
-# define DEBUG_TRACE()         	(M.x86.debug & DEBUG_TRACE_F)
-# define DEBUG_STEP()          	(M.x86.debug & DEBUG_STEP_F)
-# define DEBUG_DISASSEMBLE()   	(M.x86.debug & DEBUG_DISASSEMBLE_F)
-# define DEBUG_BREAK()         	(M.x86.debug & DEBUG_BREAK_F)
-# define DEBUG_SVC()           	(M.x86.debug & DEBUG_SVC_F)
-# define DEBUG_SAVE_IP_CS()     (M.x86.debug & DEBUG_SAVE_IP_CS_F)
-
-# define DEBUG_FS()            	(M.x86.debug & DEBUG_FS_F)
-# define DEBUG_PROC()          	(M.x86.debug & DEBUG_PROC_F)
-# define DEBUG_SYSINT()        	(M.x86.debug & DEBUG_SYSINT_F)
-# define DEBUG_TRACECALL()     	(M.x86.debug & DEBUG_TRACECALL_F)
-# define DEBUG_TRACECALLREGS() 	(M.x86.debug & DEBUG_TRACECALL_REGS_F)
-# define DEBUG_SYS()           	(M.x86.debug & DEBUG_SYS_F)
-# define DEBUG_MEM_TRACE()     	(M.x86.debug & DEBUG_MEM_TRACE_F)
-# define DEBUG_IO_TRACE()      	(M.x86.debug & DEBUG_IO_TRACE_F)
-# define DEBUG_DECODE_NOPRINT() (M.x86.debug & DEBUG_DECODE_NOPRINT_F)
-#else
-# define DEBUG_INSTRUMENT()    	0
-# define DEBUG_DECODE()        	0
-# define DEBUG_TRACE()         	0
-# define DEBUG_STEP()          	0
-# define DEBUG_DISASSEMBLE()   	0
-# define DEBUG_BREAK()         	0
-# define DEBUG_SVC()           	0
-# define DEBUG_SAVE_IP_CS()     0
-# define DEBUG_FS()            	0
-# define DEBUG_PROC()          	0
-# define DEBUG_SYSINT()        	0
-# define DEBUG_TRACECALL()     	0
-# define DEBUG_TRACECALLREGS() 	0
-# define DEBUG_SYS()           	0
-# define DEBUG_MEM_TRACE()     	0
-# define DEBUG_IO_TRACE()      	0
-# define DEBUG_DECODE_NOPRINT() 0
-#endif
-
-#ifdef DBG_X86EMU
-
-# define DECODE_PRINTF(x)     	if (DEBUG_DECODE()) \
-									x86emu_decode_printf(x)
-# define DECODE_PRINTF2(x,y)  	if (DEBUG_DECODE()) \
-									x86emu_decode_printf2(x,y)
-
-/*
- * The following allow us to look at the bytes of an instruction.  The
- * first INCR_INSTRN_LEN, is called everytime bytes are consumed in
- * the decoding process.  The SAVE_IP_CS is called initially when the
- * major opcode of the instruction is accessed.
- */
-#define INC_DECODED_INST_LEN(x)                    	\
-	if (DEBUG_DECODE())  	                       	\
-		x86emu_inc_decoded_inst_len(x)
-
-#define SAVE_IP_CS(x,y)                               			\
-	if (DEBUG_DECODE() | DEBUG_TRACECALL() | DEBUG_BREAK() \
-			  | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \
-		M.x86.saved_cs = x;                          			\
-		M.x86.saved_ip = y;                          			\
-	}
-#else
-# define INC_DECODED_INST_LEN(x)
-# define DECODE_PRINTF(x)
-# define DECODE_PRINTF2(x,y)
-# define SAVE_IP_CS(x,y)
-#endif
-
-#ifdef DBG_X86EMU
-#define TRACE_REGS()                                   		\
-	if (DEBUG_DISASSEMBLE()) {                         		\
-		x86emu_just_disassemble();                        	\
-		goto EndOfTheInstructionProcedure;             		\
-	}                                                   	\
-	if (DEBUG_TRACE() || DEBUG_DECODE()) X86EMU_trace_regs()
-#else
-# define TRACE_REGS()
-#endif
-
-#ifdef DBG_X86EMU
-# define SINGLE_STEP()		if (DEBUG_STEP()) x86emu_single_step()
-#else
-# define SINGLE_STEP()
-#endif
-
-#define TRACE_AND_STEP()	\
-	TRACE_REGS();			\
-	SINGLE_STEP()
-
-#ifdef DBG_X86EMU
-# define START_OF_INSTR()
-# define END_OF_INSTR()		EndOfTheInstructionProcedure: x86emu_end_instr();
-# define END_OF_INSTR_NO_TRACE()	x86emu_end_instr();
-#else
-# define START_OF_INSTR()
-# define END_OF_INSTR()
-# define END_OF_INSTR_NO_TRACE()
-#endif
-
-#ifdef DBG_X86EMU
-# define  CALL_TRACE(u,v,w,x,s)		\
-	if (DEBUG_TRACECALLREGS())		\
-		x86emu_dump_regs();         \
-	if (DEBUG_TRACECALL()) {        \
-		xprintf("%x", u);           \
-		xprintf(":%x", v);			\
-		xprintf(": CALL ");			\
-		xprintf("%x", s); 			\
-		xprintf(" %x", w);			\
-		xprintf(":%x", x);			\
-		xprintf("%s", "\r\n");		\
-	}
-
-# define RETURN_TRACE(n,u,v)		\
-	if (DEBUG_TRACECALLREGS())		\
-		x86emu_dump_regs();			\
-	if (DEBUG_TRACECALL())			\
-	{								\
-		xprintf("%x", (unsigned long)u);	\
-		xprintf(":%x", (unsigned long)v);	\
-		xprintf(": CALL ");			\
-		xprintf("%x", n);			\
-		xprintf("\r\n");			\
-	}
-#else
-# define CALL_TRACE(u,v,w,x,s)
-# define RETURN_TRACE(n,u,v)
-#endif
-
-#ifdef DBG_X86EMU
-#define	DB(x)	x
-#else
-#define	DB(x)
-#endif
-
-/*-------------------------- Function Prototypes --------------------------*/
-
-#ifdef  __cplusplus
-extern "C" {            			/* Use "C" linkage when in C++ mode */
-#endif
-
-extern void x86emu_inc_decoded_inst_len (int x);
-extern void x86emu_decode_printf (char *x);
-extern void x86emu_decode_printf2 (char *x, int y);
-extern void x86emu_just_disassemble (void);
-extern void x86emu_single_step (void);
-extern void x86emu_end_instr (void);
-extern void x86emu_dump_regs (void);
-extern void x86emu_dump_xregs (void);
-extern void x86emu_print_int_vect (uint16_t iv);
-extern void x86emu_instrument_instruction (void);
-extern void x86emu_check_ip_access (void);
-extern void x86emu_check_sp_access (void);
-extern void x86emu_check_mem_access (uint32_t p);
-extern void x86emu_check_data_access (unsigned int s, unsigned int o);
-
-#ifdef  __cplusplus
-}                       			/* End of "C" linkage for C++   	*/
-#endif
-
-#endif /* __X86EMU_DEBUG_H */
--- a/include/x86decode.h
+++ b/include/x86decode.h
@@ -1,89 +0,0 @@
-/****************************************************************************
-*
-*						Realmode X86 Emulator Library
-*
-*            	Copyright (C) 1996-1999 SciTech Software, Inc.
-* 				     Copyright (C) David Mosberger-Tang
-* 					   Copyright (C) 1999 Egbert Eich
-*
-*  ========================================================================
-*
-*  Permission to use, copy, modify, distribute, and sell this software and
-*  its documentation for any purpose is hereby granted without fee,
-*  provided that the above copyright notice appear in all copies and that
-*  both that copyright notice and this permission notice appear in
-*  supporting documentation, and that the name of the authors not be used
-*  in advertising or publicity pertaining to distribution of the software
-*  without specific, written prior permission.  The authors makes no
-*  representations about the suitability of this software for any purpose.
-*  It is provided "as is" without express or implied warranty.
-*
-*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
-*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
-*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
-*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
-*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
-*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
-*  PERFORMANCE OF THIS SOFTWARE.
-*
-*  ========================================================================
-*
-* Language:		ANSI C
-* Environment:	Any
-* Developer:    Kendall Bennett
-*
-* Description:  Header file for instruction decoding logic.
-*
-****************************************************************************/
-
-#ifndef __X86EMU_DECODE_H
-#define __X86EMU_DECODE_H
-
-/*---------------------- Macros and type definitions ----------------------*/
-
-/* Instruction Decoding Stuff */
-
-#define FETCH_DECODE_MODRM(mod,rh,rl) 	fetch_decode_modrm(&mod,&rh,&rl)
-#define DECODE_RM_BYTE_REGISTER(r)    	decode_rm_byte_register(r)
-#define DECODE_RM_WORD_REGISTER(r)    	decode_rm_word_register(r)
-#define DECODE_RM_LONG_REGISTER(r)    	decode_rm_long_register(r)
-#define DECODE_CLEAR_SEGOVR()         	M.x86.mode &= ~SYSMODE_CLRMASK
-
-/*-------------------------- Function Prototypes --------------------------*/
-
-#include "bas_types.h"
-
-#ifdef  __cplusplus
-extern "C" {            			/* Use "C" linkage when in C++ mode */
-#endif
-
-void x86emu_intr_raise(uint8_t type);
-void fetch_decode_modrm(int *mod, int *regh, int *regl);
-uint8_t fetch_byte_imm(void);
-uint16_t fetch_word_imm(void);
-uint32_t fetch_long_imm(void);
-uint8_t fetch_data_byte(unsigned int offset);
-uint8_t fetch_data_byte_abs(unsigned int segment, unsigned int offset);
-uint16_t fetch_data_word(unsigned int offset);
-uint16_t fetch_data_word_abs(unsigned int segment, unsigned int offset);
-uint32_t fetch_data_long(unsigned int offset);
-uint32_t fetch_data_long_abs(unsigned int segment, unsigned int offset);
-void store_data_byte(unsigned int offset, uint8_t val);
-void store_data_byte_abs(unsigned int segment, unsigned int offset, uint8_t val);
-void store_data_word(unsigned int offset, uint16_t val);
-void store_data_word_abs(unsigned int segment, unsigned int offset, uint16_t val);
-void store_data_long(unsigned int offset, uint32_t val);
-void store_data_long_abs(unsigned int segment, unsigned int offset, uint32_t val);
-uint8_t *decode_rm_byte_register(int reg);
-uint16_t *decode_rm_word_register(int reg);
-uint32_t *decode_rm_long_register(int reg);
-uint16_t *decode_rm_seg_register(int reg);
-unsigned decode_rm00_address(int rm);
-unsigned decode_rm01_address(int rm);
-unsigned decode_rm10_address(int rm);
-
-#ifdef  __cplusplus
-}                       			/* End of "C" linkage for C++   	*/
-#endif
-
-#endif /* __X86EMU_DECODE_H */
--- a/include/x86emu.h
+++ b/include/x86emu.h
@@ -1,192 +1,158 @@
+/*	$NetBSD: x86emu.h,v 1.1 2007/12/01 20:14:10 joerg Exp $	*/
+
 /****************************************************************************
- *
- *						Realmode X86 Emulator Library
- *
- *            	Copyright (C) 1996-1999 SciTech Software, Inc.
- * 				     Copyright (C) David Mosberger-Tang
- * 					   Copyright (C) 1999 Egbert Eich
- *
- *  ========================================================================
- *
- *  Permission to use, copy, modify, distribute, and sell this software and
- *  its documentation for any purpose is hereby granted without fee,
- *  provided that the above copyright notice appear in all copies and that
- *  both that copyright notice and this permission notice appear in
- *  supporting documentation, and that the name of the authors not be used
- *  in advertising or publicity pertaining to distribution of the software
- *  without specific, written prior permission.  The authors makes no
- *  representations about the suitability of this software for any purpose.
- *  It is provided "as is" without express or implied warranty.
- *
- *  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- *  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
- *  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- *  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
- *  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
- *  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- *  PERFORMANCE OF THIS SOFTWARE.
- *
- *  ========================================================================
- *
- * Language:		ANSI C
- * Environment:	Any
- * Developer:    Kendall Bennett
- *
- * Description:  Header file for public specific functions.
- *               Any application linking against us should only
- *               include this header
- *
- ****************************************************************************/
-/* $XFree86: xc/extras/x86emu/include/x86emu.h,v 1.2 2000/11/21 23:10:25 tsi Exp $ */
+*
+*  Realmode X86 Emulator Library
+*
+*  Copyright (C) 1996-1999 SciTech Software, Inc.
+*  Copyright (C) David Mosberger-Tang
+*  Copyright (C) 1999 Egbert Eich
+*  Copyright (C) 2007 Joerg Sonnenberger
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+****************************************************************************/

 #ifndef __X86EMU_X86EMU_H
 #define __X86EMU_X86EMU_H

 #include "bas_types.h"
-#define	X86API
-#define	X86APIP	*
-#include "x86regs.h"
+#include "setjmp.h"

-typedef uint16_t X86EMU_pioAddr;
+/*
+ * General EAX, EBX, ECX, EDX type registers.  Note that for
+ * portability, and speed, the issue of byte swapping is not addressed
+ * in the registers.  All registers are stored in the default format
+ * available on the host machine.  The only critical issue is that the
+ * registers should line up EXACTLY in the same manner as they do in
+ * the 386.  That is:
+ *
+ * EAX & 0xff  === AL
+ * EAX & 0xffff == AX
+ *
+ * etc.  The result is that alot of the calculations can then be
+ * done using the native instruction set fully.
+ */

-/*---------------------- Macros and type definitions ----------------------*/

-//#pragma	pack(1)
+struct X86EMU_register32 {
+	uint32_t e_reg;
+};

-/****************************************************************************
-REMARKS:
-Data structure containing ponters to programmed I/O functions used by the
-emulator. This is used so that the user program can hook all programmed
-I/O for the emulator to handled as necessary by the user program. By
-default the emulator contains simple functions that do not do access the
-hardware in any way. To allow the emualtor access the hardware, you will
-need to override the programmed I/O functions using the X86EMU_setupPioFuncs
-function.
+struct X86EMU_register16 {
+	uint16_t filler0;
+	uint16_t x_reg;
+};

-HEADER:
-x86emu.h
+struct X86EMU_register8 {
+	uint8_t filler0, filler1;
+	uint8_t h_reg, l_reg;
+};

-MEMBERS:
-inb		- Function to read a byte from an I/O port
-inw		- Function to read a word from an I/O port
-inl     - Function to read a dword from an I/O port
-outb	- Function to write a byte to an I/O port
-outw    - Function to write a word to an I/O port
-outl    - Function to write a dword to an I/O port
- ****************************************************************************/
-typedef struct
+
+union X86EMU_register {
+	struct X86EMU_register32	I32_reg;
+	struct X86EMU_register16	I16_reg;
+	struct X86EMU_register8		I8_reg;
+};
+
+struct X86EMU_regs {
+	uint16_t		register_cs;
+	uint16_t		register_ds;
+	uint16_t		register_es;
+	uint16_t		register_fs;
+	uint16_t		register_gs;
+	uint16_t		register_ss;
+	uint32_t		register_flags;
+	union X86EMU_register	register_a;
+	union X86EMU_register	register_b;
+	union X86EMU_register	register_c;
+	union X86EMU_register	register_d;
+
+	union X86EMU_register	register_sp;
+	union X86EMU_register	register_bp;
+	union X86EMU_register	register_si;
+	union X86EMU_register	register_di;
+	union X86EMU_register	register_ip;
+
+	/*
+	 * MODE contains information on:
+	 *  REPE prefix             2 bits  repe,repne
+	 *  SEGMENT overrides       5 bits  normal,DS,SS,CS,ES
+	 *  Delayed flag set        3 bits  (zero, signed, parity)
+	 *  reserved                6 bits
+	 *  interrupt #             8 bits  instruction raised interrupt
+	 *  BIOS video segregs      4 bits  
+	 *  Interrupt Pending       1 bits  
+	 *  Extern interrupt        1 bits
+	 *  Halted                  1 bits
+	 */
+	uint32_t		mode;
+    volatile int	intr;   /* mask of pending interrupts */
+	uint8_t			intno;
+	uint8_t			__pad[3];
+};
+
+struct X86EMU
 {
-	uint8_t  	(X86APIP inb)(X86EMU_pioAddr addr);
-	uint16_t 	(X86APIP inw)(X86EMU_pioAddr addr);
-	uint32_t 	(X86APIP inl)(X86EMU_pioAddr addr);
-	void 	(X86APIP outb)(X86EMU_pioAddr addr, uint8_t val);
-	void 	(X86APIP outw)(X86EMU_pioAddr addr, uint16_t val);
-	void 	(X86APIP outl)(X86EMU_pioAddr addr, uint32_t val);
-} X86EMU_pioFuncs;
+    char            *mem_base;
+    size_t          mem_size;
+    void            *sys_private;
+    struct          X86EMU_regs	x86;

-/****************************************************************************
-REMARKS:
-Data structure containing ponters to memory access functions used by the
-emulator. This is used so that the user program can hook all memory
-access functions as necessary for the emulator. By default the emulator
-contains simple functions that only access the internal memory of the
-emulator. If you need specialised functions to handle access to different
-types of memory (ie: hardware framebuffer accesses and BIOS memory access
-etc), you will need to override this using the X86EMU_setupMemFuncs
-function.
+    jmp_buf         exec_state;

-HEADER:
-x86emu.h
+    uint64_t        cur_cycles;

-MEMBERS:
-rdb		- Function to read a byte from an address
-rdw		- Function to read a word from an address
-rdl     - Function to read a dword from an address
-wrb		- Function to write a byte to an address
-wrw    	- Function to write a word to an address
-wrl    	- Function to write a dword to an address
- ****************************************************************************/
-typedef struct {
-	uint8_t  	(X86APIP rdb)(uint32_t addr);
-	uint16_t 	(X86APIP rdw)(uint32_t addr);
-	uint32_t 	(X86APIP rdl)(uint32_t addr);
-	void 	(X86APIP wrb)(uint32_t addr, uint8_t val);
-	void 	(X86APIP wrw)(uint32_t addr, uint16_t val);
-	void	(X86APIP wrl)(uint32_t addr, uint32_t val);
-} X86EMU_memFuncs;
+	unsigned int	cur_mod:2;
+	unsigned int	cur_rl:3;
+	unsigned int	cur_rh:3;
+    uint32_t        cur_offset;

-/****************************************************************************
-  Here are the default memory read and write
-  function in case they are needed as fallbacks.
- ***************************************************************************/
-extern uint8_t X86API rdb(uint32_t addr);
-extern uint16_t X86API rdw(uint32_t addr);
-extern uint32_t X86API rdl(uint32_t addr);
-extern void X86API wrb(uint32_t addr, uint8_t val);
-extern void X86API wrw(uint32_t addr, uint16_t val);
-extern void X86API wrl(uint32_t addr, uint32_t val);
+    uint8_t         (*emu_rdb)(struct X86EMU *, uint32_t addr);
+    uint16_t        (*emu_rdw)(struct X86EMU *, uint32_t addr);
+    uint32_t        (*emu_rdl)(struct X86EMU *, uint32_t addr);
+    void            (*emu_wrb)(struct X86EMU *, uint32_t addr,uint8_t val);
+    void            (*emu_wrw)(struct X86EMU *, uint32_t addr, uint16_t val);
+    void            (*emu_wrl)(struct X86EMU *, uint32_t addr, uint32_t val);

-//#pragma	pack()
+    uint8_t         (*emu_inb)(struct X86EMU *, uint16_t addr);
+    uint16_t        (*emu_inw)(struct X86EMU *, uint16_t addr);
+    uint32_t        (*emu_inl)(struct X86EMU *, uint16_t addr);
+    void            (*emu_outb)(struct X86EMU *, uint16_t addr, uint8_t val);
+    void            (*emu_outw)(struct X86EMU *, uint16_t addr, uint16_t val);
+    void            (*emu_outl)(struct X86EMU *, uint16_t addr, uint32_t val);

-/*--------------------- type definitions -----------------------------------*/
+    void            (*_X86EMU_intrTab[256])(struct X86EMU *, int);
+};

-typedef void (X86APIP X86EMU_intrFuncs)(int num);
-extern X86EMU_intrFuncs _X86EMU_intrTab[256];

-/*-------------------------- Function Prototypes --------------------------*/
+void	X86EMU_init_default(struct X86EMU *);

-#ifdef  __cplusplus
-extern "C" {            			/* Use "C" linkage when in C++ mode */
-#endif
+/* decode.c */

-	void 	X86EMU_setupMemFuncs(X86EMU_memFuncs *funcs);
-	void 	X86EMU_setupPioFuncs(X86EMU_pioFuncs *funcs);
-	void 	X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]);
-	void 	X86EMU_prepareForInt(int num);
+void 	X86EMU_exec(struct X86EMU *);
+void	X86EMU_exec_call(struct X86EMU *, uint16_t, uint16_t);
+void	X86EMU_exec_intr(struct X86EMU *, uint8_t);
+void 	X86EMU_halt_sys(struct X86EMU *);

-	/* decode.c */
-
-	void 	X86EMU_exec(void);
-	void 	X86EMU_halt_sys(void);
-
-#ifdef	DBG_X86EMU
-#define	HALT_SYS() \
-	dbg("%s: halt_sys: file %s line %d\r\n", __FUNCTION__, __FILE__, __LINE__);\
-	X86EMU_halt_sys();
-#else
-#define	HALT_SYS()	X86EMU_halt_sys()
-#endif
-
-	/* Debug options */
-
-#define DEBUG_DECODE_F          0x000001 /* print decoded instruction  */
-#define DEBUG_TRACE_F           0x000002 /* dump regs before/after execution */
-#define DEBUG_STEP_F            0x000004
-#define DEBUG_DISASSEMBLE_F     0x000008
-#define DEBUG_BREAK_F           0x000010
-#define DEBUG_SVC_F             0x000020
-#define DEBUG_FS_F              0x000080
-#define DEBUG_PROC_F            0x000100
-#define DEBUG_SYSINT_F          0x000200 /* bios system interrupts. */
-#define DEBUG_TRACECALL_F       0x000400
-#define DEBUG_INSTRUMENT_F      0x000800
-#define DEBUG_MEM_TRACE_F       0x001000 
-#define DEBUG_IO_TRACE_F        0x002000 
-#define DEBUG_TRACECALL_REGS_F  0x004000
-#define DEBUG_DECODE_NOPRINT_F  0x008000 
-#define DEBUG_SAVE_IP_CS_F      0x010000
-#define DEBUG_SYS_F             (DEBUG_SVC_F|DEBUG_FS_F|DEBUG_PROC_F)
-
-	void 	X86EMU_trace_regs(void);
-	void 	X86EMU_trace_xregs(void);
-	void 	X86EMU_dump_memory(uint16_t seg, uint16_t off, uint32_t amt);
-	int 	X86EMU_trace_on(void);
-	int 	X86EMU_trace_off(void);
-	int		X86EMU_set_debug(int debug);
-	void	X86EMU_setMemBase(void *base, unsigned long size);
-
-#ifdef  __cplusplus
-}                       			/* End of "C" linkage for C++   	*/
-#endif

 #endif /* __X86EMU_X86EMU_H */
--- a/include/x86emu_regs.h
+++ b/include/x86emu_regs.h
@@ -0,0 +1,169 @@
+/*	$NetBSD: x86emu_regs.h,v 1.1 2007/12/01 20:14:10 joerg Exp $	*/
+
+/****************************************************************************
+*
+*  Realmode X86 Emulator Library
+*
+*  Copyright (C) 1996-1999 SciTech Software, Inc.
+*  Copyright (C) David Mosberger-Tang
+*  Copyright (C) 1999 Egbert Eich
+*  Copyright (C) 2007 Joerg Sonnenberger
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+****************************************************************************/
+
+#ifndef __X86EMU_REGS_H
+#define __X86EMU_REGS_H
+
+/*---------------------- Macros and type definitions ----------------------*/
+
+/* 8 bit registers */
+#define R_AH  register_a.I8_reg.h_reg
+#define R_AL  register_a.I8_reg.l_reg
+#define R_BH  register_b.I8_reg.h_reg
+#define R_BL  register_b.I8_reg.l_reg
+#define R_CH  register_c.I8_reg.h_reg
+#define R_CL  register_c.I8_reg.l_reg
+#define R_DH  register_d.I8_reg.h_reg
+#define R_DL  register_d.I8_reg.l_reg
+
+/* 16 bit registers */
+#define R_AX  register_a.I16_reg.x_reg
+#define R_BX  register_b.I16_reg.x_reg
+#define R_CX  register_c.I16_reg.x_reg
+#define R_DX  register_d.I16_reg.x_reg
+
+/* 32 bit extended registers */
+#define R_EAX  register_a.I32_reg.e_reg
+#define R_EBX  register_b.I32_reg.e_reg
+#define R_ECX  register_c.I32_reg.e_reg
+#define R_EDX  register_d.I32_reg.e_reg
+
+/* special registers */
+#define R_SP  register_sp.I16_reg.x_reg
+#define R_BP  register_bp.I16_reg.x_reg
+#define R_SI  register_si.I16_reg.x_reg
+#define R_DI  register_di.I16_reg.x_reg
+#define R_IP  register_ip.I16_reg.x_reg
+#define R_FLG register_flags
+
+/* special registers */
+#define R_ESP  register_sp.I32_reg.e_reg
+#define R_EBP  register_bp.I32_reg.e_reg
+#define R_ESI  register_si.I32_reg.e_reg
+#define R_EDI  register_di.I32_reg.e_reg
+#define R_EIP  register_ip.I32_reg.e_reg
+#define R_EFLG register_flags
+
+/* segment registers */
+#define R_CS  register_cs
+#define R_DS  register_ds
+#define R_SS  register_ss
+#define R_ES  register_es
+#define R_FS  register_fs
+#define R_GS  register_gs
+
+/* flag conditions   */
+#define FB_CF 0x0001            /* CARRY flag  */
+#define FB_PF 0x0004            /* PARITY flag */
+#define FB_AF 0x0010            /* AUX  flag   */
+#define FB_ZF 0x0040            /* ZERO flag   */
+#define FB_SF 0x0080            /* SIGN flag   */
+#define FB_TF 0x0100            /* TRAP flag   */
+#define FB_IF 0x0200            /* INTERRUPT ENABLE flag */
+#define FB_DF 0x0400            /* DIR flag    */
+#define FB_OF 0x0800            /* OVERFLOW flag */
+
+/* 80286 and above always have bit#1 set */
+#define F_ALWAYS_ON  (0x0002)   /* flag bits always on */
+
+/*
+ * Define a mask for only those flag bits we will ever pass back 
+ * (via PUSHF) 
+ */
+#define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF)
+
+/* following bits masked in to a 16bit quantity */
+
+#define F_CF 0x0001             /* CARRY flag  */
+#define F_PF 0x0004             /* PARITY flag */
+#define F_AF 0x0010             /* AUX  flag   */
+#define F_ZF 0x0040             /* ZERO flag   */
+#define F_SF 0x0080             /* SIGN flag   */
+#define F_TF 0x0100             /* TRAP flag   */
+#define F_IF 0x0200             /* INTERRUPT ENABLE flag */
+#define F_DF 0x0400             /* DIR flag    */
+#define F_OF 0x0800             /* OVERFLOW flag */
+
+#define SET_FLAG(flag)        	(emu->x86.R_FLG |= (flag))
+#define CLEAR_FLAG(flag)      	(emu->x86.R_FLG &= ~(flag))
+#define ACCESS_FLAG(flag)     	(emu->x86.R_FLG & (flag))
+#define CLEARALL_FLAG(m)    	(emu->x86.R_FLG = 0)
+
+#define CONDITIONAL_SET_FLAG(COND,FLAG) \
+  if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG)
+
+#define F_PF_CALC 0x010000      /* PARITY flag has been calced    */
+#define F_ZF_CALC 0x020000      /* ZERO flag has been calced      */
+#define F_SF_CALC 0x040000      /* SIGN flag has been calced      */
+
+#define F_ALL_CALC      0xff0000        /* All have been calced   */
+
+/*
+ * Emulator machine state.
+ * Segment usage control.
+ */
+#define SYSMODE_SEG_DS_SS       0x00000001
+#define SYSMODE_SEGOVR_CS       0x00000002
+#define SYSMODE_SEGOVR_DS       0x00000004
+#define SYSMODE_SEGOVR_ES       0x00000008
+#define SYSMODE_SEGOVR_FS       0x00000010
+#define SYSMODE_SEGOVR_GS       0x00000020
+#define SYSMODE_SEGOVR_SS       0x00000040
+#define SYSMODE_PREFIX_REPE     0x00000080
+#define SYSMODE_PREFIX_REPNE    0x00000100
+#define SYSMODE_PREFIX_DATA     0x00000200
+#define SYSMODE_PREFIX_ADDR     0x00000400
+#define SYSMODE_INTR_PENDING    0x10000000
+#define SYSMODE_EXTRN_INTR      0x20000000
+#define SYSMODE_HALTED          0x40000000
+
+#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS      | \
+						 SYSMODE_SEGOVR_CS      | \
+						 SYSMODE_SEGOVR_DS      | \
+						 SYSMODE_SEGOVR_ES      | \
+						 SYSMODE_SEGOVR_FS      | \
+						 SYSMODE_SEGOVR_GS      | \
+						 SYSMODE_SEGOVR_SS)
+#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS      | \
+						 SYSMODE_SEGOVR_CS      | \
+						 SYSMODE_SEGOVR_DS      | \
+						 SYSMODE_SEGOVR_ES      | \
+						 SYSMODE_SEGOVR_FS      | \
+						 SYSMODE_SEGOVR_GS      | \
+						 SYSMODE_SEGOVR_SS      | \
+						 SYSMODE_PREFIX_DATA    | \
+						 SYSMODE_PREFIX_ADDR)
+
+#define  INTR_SYNCH           0x1
+
+#endif /* __X86EMU_REGS_H */
--- a/include/x86emui.h
+++ b/include/x86emui.h
@@ -1,99 +0,0 @@
-/****************************************************************************
-*
-*						Realmode X86 Emulator Library
-*
-*            	Copyright (C) 1996-1999 SciTech Software, Inc.
-* 				     Copyright (C) David Mosberger-Tang
-* 					   Copyright (C) 1999 Egbert Eich
-*
-*  ========================================================================
-*
-*  Permission to use, copy, modify, distribute, and sell this software and
-*  its documentation for any purpose is hereby granted without fee,
-*  provided that the above copyright notice appear in all copies and that
-*  both that copyright notice and this permission notice appear in
-*  supporting documentation, and that the name of the authors not be used
-*  in advertising or publicity pertaining to distribution of the software
-*  without specific, written prior permission.  The authors makes no
-*  representations about the suitability of this software for any purpose.
-*  It is provided "as is" without express or implied warranty.
-*
-*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
-*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
-*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
-*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
-*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
-*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
-*  PERFORMANCE OF THIS SOFTWARE.
-*
-*  ========================================================================
-*
-* Language:		ANSI C
-* Environment:	Any
-* Developer:    Kendall Bennett
-*
-* Description:  Header file for system specific functions. These functions
-*				are always compiled and linked in the OS depedent libraries,
-*				and never in a binary portable driver.
-*
-****************************************************************************/
-
-/* $XFree86: xc/extras/x86emu/src/x86emu/x86emu/x86emui.h,v 1.4 2001/04/01 13:59:58 tsi Exp $ */
-
-#ifndef __X86EMU_X86EMUI_H
-#define __X86EMU_X86EMUI_H
-
-/*
- * If we are compiling in C++ mode, we can compile some functions as
- * inline to increase performance (however the code size increases quite
- * dramatically in this case).
- */
-
-#if	defined(__cplusplus) && !defined(_NO_INLINE)
-#define	_INLINE	inline
-#else
-#define	_INLINE static
-#endif
-
-/* Get rid of unused parameters in C++ compilation mode */
-
-#ifdef __cplusplus
-#define	X86EMU_UNUSED(v)
-#else
-#define	X86EMU_UNUSED(v)	v
-#endif
-
-#include "radeonfb.h"
-
-#include "x86emu.h"
-#include "x86regs.h"
-#include "x86decode.h"
-#include "x86ops.h"
-#include "x86prim_ops.h"
-#include "x86fpu.h"
-
-/*--------------------------- Inline Functions ----------------------------*/
-
-#ifdef  __cplusplus
-extern "C" {            			/* Use "C" linkage when in C++ mode */
-#endif
-
-extern uint8_t  	(X86APIP sys_rdb)(uint32_t addr);
-extern uint16_t 	(X86APIP sys_rdw)(uint32_t addr);
-extern uint32_t 	(X86APIP sys_rdl)(uint32_t addr);
-extern void (X86APIP sys_wrb)(uint32_t addr,uint8_t val);
-extern void (X86APIP sys_wrw)(uint32_t addr,uint16_t val);
-extern void (X86APIP sys_wrl)(uint32_t addr,uint32_t val);
-
-extern uint8_t  	(X86APIP sys_inb)(X86EMU_pioAddr addr);
-extern uint16_t 	(X86APIP sys_inw)(X86EMU_pioAddr addr);
-extern uint32_t 	(X86APIP sys_inl)(X86EMU_pioAddr addr);
-extern void (X86APIP sys_outb)(X86EMU_pioAddr addr,uint8_t val);
-extern void (X86APIP sys_outw)(X86EMU_pioAddr addr,uint16_t val);
-extern void	(X86APIP sys_outl)(X86EMU_pioAddr addr,uint32_t val);
-
-#ifdef  __cplusplus
-}                       			/* End of "C" linkage for C++   	*/
-#endif
-
-#endif /* __X86EMU_X86EMUI_H */
--- a/include/x86fpu.h
+++ b/include/x86fpu.h
@@ -1,61 +0,0 @@
-/****************************************************************************
-*
-*						Realmode X86 Emulator Library
-*
-*            	Copyright (C) 1996-1999 SciTech Software, Inc.
-* 				     Copyright (C) David Mosberger-Tang
-* 					   Copyright (C) 1999 Egbert Eich
-*
-*  ========================================================================
-*
-*  Permission to use, copy, modify, distribute, and sell this software and
-*  its documentation for any purpose is hereby granted without fee,
-*  provided that the above copyright notice appear in all copies and that
-*  both that copyright notice and this permission notice appear in
-*  supporting documentation, and that the name of the authors not be used
-*  in advertising or publicity pertaining to distribution of the software
-*  without specific, written prior permission.  The authors makes no
-*  representations about the suitability of this software for any purpose.
-*  It is provided "as is" without express or implied warranty.
-*
-*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
-*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
-*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
-*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
-*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
-*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
-*  PERFORMANCE OF THIS SOFTWARE.
-*
-*  ========================================================================
-*
-* Language:		ANSI C
-* Environment:	Any
-* Developer:    Kendall Bennett
-*
-* Description:  Header file for FPU instruction decoding.
-*
-****************************************************************************/
-
-#ifndef __X86EMU_FPU_H
-#define __X86EMU_FPU_H
-
-#ifdef  __cplusplus
-extern "C" {            			/* Use "C" linkage when in C++ mode */
-#endif
-
-/* these have to be defined, whether 8087 support compiled in or not. */
-
-extern void x86emuOp_esc_coprocess_d8 (uint8_t op1);
-extern void x86emuOp_esc_coprocess_d9 (uint8_t op1);
-extern void x86emuOp_esc_coprocess_da (uint8_t op1);
-extern void x86emuOp_esc_coprocess_db (uint8_t op1);
-extern void x86emuOp_esc_coprocess_dc (uint8_t op1);
-extern void x86emuOp_esc_coprocess_dd (uint8_t op1);
-extern void x86emuOp_esc_coprocess_de (uint8_t op1);
-extern void x86emuOp_esc_coprocess_df (uint8_t op1);
-
-#ifdef  __cplusplus
-}                       			/* End of "C" linkage for C++   	*/
-#endif
-
-#endif /* __X86EMU_FPU_H */
--- a/include/x86fpu_regs.h
+++ b/include/x86fpu_regs.h
@@ -1,116 +0,0 @@
-/****************************************************************************
-*
-*						Realmode X86 Emulator Library
-*
-*            	Copyright (C) 1996-1999 SciTech Software, Inc.
-* 				     Copyright (C) David Mosberger-Tang
-* 					   Copyright (C) 1999 Egbert Eich
-*
-*  ========================================================================
-*
-*  Permission to use, copy, modify, distribute, and sell this software and
-*  its documentation for any purpose is hereby granted without fee,
-*  provided that the above copyright notice appear in all copies and that
-*  both that copyright notice and this permission notice appear in
-*  supporting documentation, and that the name of the authors not be used
-*  in advertising or publicity pertaining to distribution of the software
-*  without specific, written prior permission.  The authors makes no
-*  representations about the suitability of this software for any purpose.
-*  It is provided "as is" without express or implied warranty.
-*
-*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
-*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
-*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
-*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
-*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
-*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
-*  PERFORMANCE OF THIS SOFTWARE.
-*
-*  ========================================================================
-*
-* Language:		ANSI C
-* Environment:	Any
-* Developer:    Kendall Bennett
-*
-* Description:  Header file for FPU register definitions.
-*
-****************************************************************************/
-
-#ifndef __X86EMU_FPU_REGS_H
-#define __X86EMU_FPU_REGS_H
-
-#ifdef X86_FPU_SUPPORT
-
-#pragma	pack(1)
-
-/* Basic 8087 register can hold any of the following values: */
-
-union x86_fpu_reg_u {
-    s8                  tenbytes[10];
-    double              dval;
-    float               fval;
-    s16                 sval;
-    s32                 lval;
-	};
-
-struct x86_fpu_reg {
-	union x86_fpu_reg_u reg;
-	char                tag;
-	};
-
-/*
- * Since we are not going to worry about the problems of aliasing
- * registers, every time a register is modified, its result type is
- * set in the tag fields for that register.  If some operation
- * attempts to access the type in a way inconsistent with its current
- * storage format, then we flag the operation.  If common, we'll
- * attempt the conversion.
- */
-
-#define  X86_FPU_VALID          0x80
-#define  X86_FPU_REGTYP(r)      ((r) & 0x7F)
-
-#define  X86_FPU_WORD           0x0
-#define  X86_FPU_SHORT          0x1
-#define  X86_FPU_LONG           0x2
-#define  X86_FPU_FLOAT          0x3
-#define  X86_FPU_DOUBLE         0x4
-#define  X86_FPU_LDBL           0x5
-#define  X86_FPU_BSD            0x6
-
-#define  X86_FPU_STKTOP  0
-
-struct x86_fpu_registers
-{
-    struct x86_fpu_reg  x86_fpu_stack[8];
-    int                 x86_fpu_flags;
-    int                 x86_fpu_config;         /* rounding modes, etc. */
-    short               x86_fpu_tos, x86_fpu_bos;
-};
-
-#pragma	pack()
-
-/*
- * There are two versions of the following macro.
- *
- * One version is for opcode D9, for which there are more than 32
- * instructions encoded in the second byte of the opcode.
- *
- * The other version, deals with all the other 7 i87 opcodes, for
- * which there are only 32 strings needed to describe the
- * instructions.
- */
-
-#endif /* X86_FPU_SUPPORT */
-
-#ifdef DBG_X86EMU
-#define DECODE_PRINTINSTR32(t, mod, rh, rl)		\
-	DECODE_PRINTF(t[(mod << 3) + (rh)]);
-#define DECODE_PRINTINSTR256(t, mod, rh, rl)   	\
-	DECODE_PRINTF(t[(mod << 6) + (rh << 3) + (rl)]);
-#else
-#define DECODE_PRINTINSTR32(t,mod,rh,rl)
-#define DECODE_PRINTINSTR256(t,mod,rh,rl)
-#endif
-
-#endif /* __X86EMU_FPU_REGS_H */
--- a/include/x86ops.h
+++ b/include/x86ops.h
@@ -1,45 +0,0 @@
-/****************************************************************************
-*
-*						Realmode X86 Emulator Library
-*
-*            	Copyright (C) 1996-1999 SciTech Software, Inc.
-* 				     Copyright (C) David Mosberger-Tang
-* 					   Copyright (C) 1999 Egbert Eich
-*
-*  ========================================================================
-*
-*  Permission to use, copy, modify, distribute, and sell this software and
-*  its documentation for any purpose is hereby granted without fee,
-*  provided that the above copyright notice appear in all copies and that
-*  both that copyright notice and this permission notice appear in
-*  supporting documentation, and that the name of the authors not be used
-*  in advertising or publicity pertaining to distribution of the software
-*  without specific, written prior permission.  The authors makes no
-*  representations about the suitability of this software for any purpose.
-*  It is provided "as is" without express or implied warranty.
-*
-*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
-*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
-*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
-*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
-*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
-*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
-*  PERFORMANCE OF THIS SOFTWARE.
-*
-*  ========================================================================
-*
-* Language:		ANSI C
-* Environment:	Any
-* Developer:    Kendall Bennett
-*
-* Description:  Header file for operand decoding functions.
-*
-****************************************************************************/
-
-#ifndef __X86EMU_OPS_H
-#define __X86EMU_OPS_H
-
-extern void (*x86emu_optab[0x100])(uint8_t op1);
-extern void (*x86emu_optab2[0x100])(uint8_t op2);
-
-#endif /* __X86EMU_OPS_H */
--- a/include/x86pcibios.h
+++ b/include/x86pcibios.h
@@ -2,27 +2,27 @@
 #define PCI_BIOS_H

 enum {
-	PCI_BIOS_PRESENT	= 0xB101,
-	FIND_PCI_DEVICE		= 0xB102,
-	FIND_PCI_CLASS_CODE	= 0xB103,
+    PCI_BIOS_PRESENT        = 0xB101,
+    FIND_PCI_DEVICE         = 0xB102,
+    FIND_PCI_CLASS_CODE     = 0xB103,
 	GENERATE_SPECIAL_CYCLE	= 0xB106,
-	READ_CONFIG_BYTE	= 0xB108,
-	READ_CONFIG_WORD	= 0xB109,
-	READ_CONFIG_DWORD	= 0xB10A,
-	WRITE_CONFIG_BYTE	= 0xB10B,
-	WRITE_CONFIG_WORD	= 0xB10C,
-	WRITE_CONFIG_DWORD	= 0xB10D,
+    READ_CONFIG_BYTE        = 0xB108,
+    READ_CONFIG_WORD        = 0xB109,
+    READ_CONFIG_DWORD       = 0xB10A,
+    WRITE_CONFIG_BYTE       = 0xB10B,
+    WRITE_CONFIG_WORD       = 0xB10C,
+    WRITE_CONFIG_DWORD      = 0xB10D,
 	GET_IRQ_ROUTING_OPTIONS	= 0xB10E,
-	SET_PCI_IRQ		= 0xB10F
+    SET_PCI_IRQ             = 0xB10F
 };

 enum {
-	SUCCESSFUL		= 0x00,
+    SUCCESSFUL          = 0x00,
 	FUNC_NOT_SUPPORTED	= 0x81,
 	BAD_VENDOR_ID		= 0x83,
 	DEVICE_NOT_FOUND	= 0x86,
 	BAD_REGISTER_NUMBER	= 0x87,
-	SET_FAILED		= 0x88,
+    SET_FAILED          = 0x88,
 	BUFFER_TOO_SMALL	= 0x89
 };
 #endif /* PCI_BIOS_H */
--- a/include/x86prim_asm.h
+++ b/include/x86prim_asm.h
@@ -1,971 +0,0 @@
-/****************************************************************************
-*
-*						Realmode X86 Emulator Library
-*
-*            	Copyright (C) 1996-1999 SciTech Software, Inc.
-* 				     Copyright (C) David Mosberger-Tang
-* 					   Copyright (C) 1999 Egbert Eich
-*
-*  ========================================================================
-*
-*  Permission to use, copy, modify, distribute, and sell this software and
-*  its documentation for any purpose is hereby granted without fee,
-*  provided that the above copyright notice appear in all copies and that
-*  both that copyright notice and this permission notice appear in
-*  supporting documentation, and that the name of the authors not be used
-*  in advertising or publicity pertaining to distribution of the software
-*  without specific, written prior permission.  The authors makes no
-*  representations about the suitability of this software for any purpose.
-*  It is provided "as is" without express or implied warranty.
-*
-*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
-*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
-*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
-*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
-*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
-*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
-*  PERFORMANCE OF THIS SOFTWARE.
-*
-*  ========================================================================
-*
-* Language:		Watcom C++ 10.6 or later
-* Environment:	Any
-* Developer:    Kendall Bennett
-*
-* Description:  Inline assembler versions of the primitive operand
-*				functions for faster performance. At the moment this is
-*				x86 inline assembler, but these functions could be replaced
-*				with native inline assembler for each supported processor
-*				platform.
-*
-****************************************************************************/
-/* $XFree86: xc/extras/x86emu/src/x86emu/x86emu/prim_asm.h,v 1.3 2000/04/19 15:48:15 tsi Exp $ */
-
-#ifndef	__X86EMU_PRIM_ASM_H
-#define	__X86EMU_PRIM_ASM_H
-
-#ifdef	__WATCOMC__
-
-#ifndef	VALIDATE
-#define	__HAVE_INLINE_ASSEMBLER__
-#endif
-
-u32		get_flags_asm(void);
-#pragma aux get_flags_asm =			\
-	"pushf"                         \
-	"pop	eax"                  	\
-	value [eax]                     \
-	modify exact [eax];
-
-u16     aaa_word_asm(u32 *flags,u16 d);
-#pragma aux aaa_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"aaa"                  			\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax] 				\
-	value [ax]                      \
-	modify exact [ax];
-
-u16     aas_word_asm(u32 *flags,u16 d);
-#pragma aux aas_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"aas"                  			\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax] 				\
-	value [ax]                      \
-	modify exact [ax];
-
-u16     aad_word_asm(u32 *flags,u16 d);
-#pragma aux aad_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"aad"                  			\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax] 				\
-	value [ax]                      \
-	modify exact [ax];
-
-u16     aam_word_asm(u32 *flags,u8 d);
-#pragma aux aam_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"aam"                  			\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al] 				\
-	value [ax]                      \
-	modify exact [ax];
-
-u8      adc_byte_asm(u32 *flags,u8 d, u8 s);
-#pragma aux adc_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"adc	al,bl"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al] [bl]            \
-	value [al]                      \
-	modify exact [al bl];
-
-u16     adc_word_asm(u32 *flags,u16 d, u16 s);
-#pragma aux adc_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"adc	ax,bx"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax] [bx]            \
-	value [ax]                      \
-	modify exact [ax bx];
-
-u32     adc_long_asm(u32 *flags,u32 d, u32 s);
-#pragma aux adc_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"adc	eax,ebx"                \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [eax] [ebx]          \
-	value [eax]                     \
-	modify exact [eax ebx];
-
-u8      add_byte_asm(u32 *flags,u8 d, u8 s);
-#pragma aux add_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"add	al,bl"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al] [bl]            \
-	value [al]                      \
-	modify exact [al bl];
-
-u16     add_word_asm(u32 *flags,u16 d, u16 s);
-#pragma aux add_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"add	ax,bx"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax] [bx]            \
-	value [ax]                      \
-	modify exact [ax bx];
-
-u32     add_long_asm(u32 *flags,u32 d, u32 s);
-#pragma aux add_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"add	eax,ebx"                \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [eax] [ebx]          \
-	value [eax]                     \
-	modify exact [eax ebx];
-
-u8      and_byte_asm(u32 *flags,u8 d, u8 s);
-#pragma aux and_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"and	al,bl"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al] [bl]            \
-	value [al]                      \
-	modify exact [al bl];
-
-u16     and_word_asm(u32 *flags,u16 d, u16 s);
-#pragma aux and_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"and	ax,bx"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax] [bx]            \
-	value [ax]                      \
-	modify exact [ax bx];
-
-u32     and_long_asm(u32 *flags,u32 d, u32 s);
-#pragma aux and_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"and	eax,ebx"                \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [eax] [ebx]          \
-	value [eax]                     \
-	modify exact [eax ebx];
-
-u8      cmp_byte_asm(u32 *flags,u8 d, u8 s);
-#pragma aux cmp_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"cmp	al,bl"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al] [bl]            \
-	value [al]                      \
-	modify exact [al bl];
-
-u16     cmp_word_asm(u32 *flags,u16 d, u16 s);
-#pragma aux cmp_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"cmp	ax,bx"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax] [bx]            \
-	value [ax]                      \
-	modify exact [ax bx];
-
-u32     cmp_long_asm(u32 *flags,u32 d, u32 s);
-#pragma aux cmp_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"cmp	eax,ebx"                \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [eax] [ebx]          \
-	value [eax]                     \
-	modify exact [eax ebx];
-
-u8      daa_byte_asm(u32 *flags,u8 d);
-#pragma aux daa_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"daa"                  			\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al]            		\
-	value [al]                      \
-	modify exact [al];
-
-u8      das_byte_asm(u32 *flags,u8 d);
-#pragma aux das_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"das"                  			\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al]            		\
-	value [al]                      \
-	modify exact [al];
-
-u8      dec_byte_asm(u32 *flags,u8 d);
-#pragma aux dec_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"dec	al"                  	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al]            		\
-	value [al]                      \
-	modify exact [al];
-
-u16     dec_word_asm(u32 *flags,u16 d);
-#pragma aux dec_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"dec	ax"                  	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax]            		\
-	value [ax]                      \
-	modify exact [ax];
-
-u32     dec_long_asm(u32 *flags,u32 d);
-#pragma aux dec_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"dec	eax"                	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [eax]          		\
-	value [eax]                     \
-	modify exact [eax];
-
-u8      inc_byte_asm(u32 *flags,u8 d);
-#pragma aux inc_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"inc	al"                  	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al]            		\
-	value [al]                      \
-	modify exact [al];
-
-u16     inc_word_asm(u32 *flags,u16 d);
-#pragma aux inc_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"inc	ax"                  	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax]            		\
-	value [ax]                      \
-	modify exact [ax];
-
-u32     inc_long_asm(u32 *flags,u32 d);
-#pragma aux inc_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"inc	eax"                	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [eax]          		\
-	value [eax]                     \
-	modify exact [eax];
-
-u8      or_byte_asm(u32 *flags,u8 d, u8 s);
-#pragma aux or_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"or	al,bl"                  	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al] [bl]            \
-	value [al]                      \
-	modify exact [al bl];
-
-u16     or_word_asm(u32 *flags,u16 d, u16 s);
-#pragma aux or_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"or	ax,bx"                  	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax] [bx]            \
-	value [ax]                      \
-	modify exact [ax bx];
-
-u32     or_long_asm(u32 *flags,u32 d, u32 s);
-#pragma aux or_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"or	eax,ebx"                	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [eax] [ebx]          \
-	value [eax]                     \
-	modify exact [eax ebx];
-
-u8      neg_byte_asm(u32 *flags,u8 d);
-#pragma aux neg_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"neg	al"                  	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al]            		\
-	value [al]                      \
-	modify exact [al];
-
-u16     neg_word_asm(u32 *flags,u16 d);
-#pragma aux neg_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"neg	ax"                  	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax]            		\
-	value [ax]                      \
-	modify exact [ax];
-
-u32     neg_long_asm(u32 *flags,u32 d);
-#pragma aux neg_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"neg	eax"                	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [eax]          		\
-	value [eax]                     \
-	modify exact [eax];
-
-u8      not_byte_asm(u32 *flags,u8 d);
-#pragma aux not_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"not	al"                  	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al]            		\
-	value [al]                      \
-	modify exact [al];
-
-u16     not_word_asm(u32 *flags,u16 d);
-#pragma aux not_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"not	ax"                  	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax]            		\
-	value [ax]                      \
-	modify exact [ax];
-
-u32     not_long_asm(u32 *flags,u32 d);
-#pragma aux not_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"not	eax"                	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [eax]          		\
-	value [eax]                     \
-	modify exact [eax];
-
-u8      rcl_byte_asm(u32 *flags,u8 d, u8 s);
-#pragma aux rcl_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"rcl	al,cl"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al] [cl]            \
-	value [al]                      \
-	modify exact [al cl];
-
-u16     rcl_word_asm(u32 *flags,u16 d, u8 s);
-#pragma aux rcl_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"rcl	ax,cl"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax] [cl]            \
-	value [ax]                      \
-	modify exact [ax cl];
-
-u32     rcl_long_asm(u32 *flags,u32 d, u8 s);
-#pragma aux rcl_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"rcl	eax,cl"                	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [eax] [cl]          	\
-	value [eax]                     \
-	modify exact [eax cl];
-
-u8      rcr_byte_asm(u32 *flags,u8 d, u8 s);
-#pragma aux rcr_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"rcr	al,cl"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al] [cl]            \
-	value [al]                      \
-	modify exact [al cl];
-
-u16     rcr_word_asm(u32 *flags,u16 d, u8 s);
-#pragma aux rcr_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"rcr	ax,cl"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax] [cl]            \
-	value [ax]                      \
-	modify exact [ax cl];
-
-u32     rcr_long_asm(u32 *flags,u32 d, u8 s);
-#pragma aux rcr_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"rcr	eax,cl"                	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [eax] [cl]          	\
-	value [eax]                     \
-	modify exact [eax cl];
-
-u8      rol_byte_asm(u32 *flags,u8 d, u8 s);
-#pragma aux rol_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"rol	al,cl"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al] [cl]            \
-	value [al]                      \
-	modify exact [al cl];
-
-u16     rol_word_asm(u32 *flags,u16 d, u8 s);
-#pragma aux rol_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"rol	ax,cl"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax] [cl]            \
-	value [ax]                      \
-	modify exact [ax cl];
-
-u32     rol_long_asm(u32 *flags,u32 d, u8 s);
-#pragma aux rol_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"rol	eax,cl"                	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [eax] [cl]          	\
-	value [eax]                     \
-	modify exact [eax cl];
-
-u8      ror_byte_asm(u32 *flags,u8 d, u8 s);
-#pragma aux ror_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"ror	al,cl"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al] [cl]            \
-	value [al]                      \
-	modify exact [al cl];
-
-u16     ror_word_asm(u32 *flags,u16 d, u8 s);
-#pragma aux ror_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"ror	ax,cl"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax] [cl]            \
-	value [ax]                      \
-	modify exact [ax cl];
-
-u32     ror_long_asm(u32 *flags,u32 d, u8 s);
-#pragma aux ror_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"ror	eax,cl"                	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [eax] [cl]          	\
-	value [eax]                     \
-	modify exact [eax cl];
-
-u8      shl_byte_asm(u32 *flags,u8 d, u8 s);
-#pragma aux shl_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"shl	al,cl"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al] [cl]            \
-	value [al]                      \
-	modify exact [al cl];
-
-u16     shl_word_asm(u32 *flags,u16 d, u8 s);
-#pragma aux shl_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"shl	ax,cl"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax] [cl]            \
-	value [ax]                      \
-	modify exact [ax cl];
-
-u32     shl_long_asm(u32 *flags,u32 d, u8 s);
-#pragma aux shl_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"shl	eax,cl"                	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [eax] [cl]          	\
-	value [eax]                     \
-	modify exact [eax cl];
-
-u8      shr_byte_asm(u32 *flags,u8 d, u8 s);
-#pragma aux shr_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"shr	al,cl"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al] [cl]            \
-	value [al]                      \
-	modify exact [al cl];
-
-u16     shr_word_asm(u32 *flags,u16 d, u8 s);
-#pragma aux shr_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"shr	ax,cl"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax] [cl]            \
-	value [ax]                      \
-	modify exact [ax cl];
-
-u32     shr_long_asm(u32 *flags,u32 d, u8 s);
-#pragma aux shr_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"shr	eax,cl"                	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [eax] [cl]          	\
-	value [eax]                     \
-	modify exact [eax cl];
-
-u8      sar_byte_asm(u32 *flags,u8 d, u8 s);
-#pragma aux sar_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"sar	al,cl"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al] [cl]            \
-	value [al]                      \
-	modify exact [al cl];
-
-u16     sar_word_asm(u32 *flags,u16 d, u8 s);
-#pragma aux sar_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"sar	ax,cl"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax] [cl]            \
-	value [ax]                      \
-	modify exact [ax cl];
-
-u32     sar_long_asm(u32 *flags,u32 d, u8 s);
-#pragma aux sar_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"sar	eax,cl"                	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [eax] [cl]          	\
-	value [eax]                     \
-	modify exact [eax cl];
-
-u16		shld_word_asm(u32 *flags,u16 d, u16 fill, u8 s);
-#pragma aux shld_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"shld	ax,dx,cl"               \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax] [dx] [cl]       \
-	value [ax]                      \
-	modify exact [ax dx cl];
-
-u32     shld_long_asm(u32 *flags,u32 d, u32 fill, u8 s);
-#pragma aux shld_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"shld	eax,edx,cl"             \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [eax] [edx] [cl]     \
-	value [eax]                     \
-	modify exact [eax edx cl];
-
-u16		shrd_word_asm(u32 *flags,u16 d, u16 fill, u8 s);
-#pragma aux shrd_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"shrd	ax,dx,cl"               \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax] [dx] [cl]       \
-	value [ax]                      \
-	modify exact [ax dx cl];
-
-u32     shrd_long_asm(u32 *flags,u32 d, u32 fill, u8 s);
-#pragma aux shrd_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"shrd	eax,edx,cl"             \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [eax] [edx] [cl]     \
-	value [eax]                     \
-	modify exact [eax edx cl];
-
-u8      sbb_byte_asm(u32 *flags,u8 d, u8 s);
-#pragma aux sbb_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"sbb	al,bl"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al] [bl]            \
-	value [al]                      \
-	modify exact [al bl];
-
-u16     sbb_word_asm(u32 *flags,u16 d, u16 s);
-#pragma aux sbb_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"sbb	ax,bx"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax] [bx]            \
-	value [ax]                      \
-	modify exact [ax bx];
-
-u32     sbb_long_asm(u32 *flags,u32 d, u32 s);
-#pragma aux sbb_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"sbb	eax,ebx"                \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [eax] [ebx]          \
-	value [eax]                     \
-	modify exact [eax ebx];
-
-u8      sub_byte_asm(u32 *flags,u8 d, u8 s);
-#pragma aux sub_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"sub	al,bl"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al] [bl]            \
-	value [al]                      \
-	modify exact [al bl];
-
-u16     sub_word_asm(u32 *flags,u16 d, u16 s);
-#pragma aux sub_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"sub	ax,bx"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax] [bx]            \
-	value [ax]                      \
-	modify exact [ax bx];
-
-u32     sub_long_asm(u32 *flags,u32 d, u32 s);
-#pragma aux sub_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"sub	eax,ebx"                \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [eax] [ebx]          \
-	value [eax]                     \
-	modify exact [eax ebx];
-
-void	test_byte_asm(u32 *flags,u8 d, u8 s);
-#pragma aux test_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"test	al,bl"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al] [bl]            \
-	modify exact [al bl];
-
-void	test_word_asm(u32 *flags,u16 d, u16 s);
-#pragma aux test_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"test	ax,bx"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax] [bx]            \
-	modify exact [ax bx];
-
-void	test_long_asm(u32 *flags,u32 d, u32 s);
-#pragma aux test_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"test	eax,ebx"                \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [eax] [ebx]          \
-	modify exact [eax ebx];
-
-u8      xor_byte_asm(u32 *flags,u8 d, u8 s);
-#pragma aux xor_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"xor	al,bl"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [al] [bl]            \
-	value [al]                      \
-	modify exact [al bl];
-
-u16     xor_word_asm(u32 *flags,u16 d, u16 s);
-#pragma aux xor_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"xor	ax,bx"                  \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [ax] [bx]            \
-	value [ax]                      \
-	modify exact [ax bx];
-
-u32     xor_long_asm(u32 *flags,u32 d, u32 s);
-#pragma aux xor_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"xor	eax,ebx"                \
-	"pushf"                         \
-	"pop	[edi]"            		\
-	parm [edi] [eax] [ebx]          \
-	value [eax]                     \
-	modify exact [eax ebx];
-
-void    imul_byte_asm(u32 *flags,u16 *ax,u8 d,u8 s);
-#pragma aux imul_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"imul	bl"                  	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	"mov	[esi],ax"				\
-	parm [edi] [esi] [al] [bl]      \
-	modify exact [esi ax bl];
-
-void    imul_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 d,u16 s);
-#pragma aux imul_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"imul	bx"                  	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	"mov	[esi],ax"				\
-	"mov	[ecx],dx"				\
-	parm [edi] [esi] [ecx] [ax] [bx]\
-	modify exact [esi edi ax bx dx];
-
-void    imul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s);
-#pragma aux imul_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"imul	ebx"                  	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	"mov	[esi],eax"				\
-	"mov	[ecx],edx"				\
-	parm [edi] [esi] [ecx] [eax] [ebx] \
-	modify exact [esi edi eax ebx edx];
-
-void    mul_byte_asm(u32 *flags,u16 *ax,u8 d,u8 s);
-#pragma aux mul_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"mul	bl"                  	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	"mov	[esi],ax"				\
-	parm [edi] [esi] [al] [bl]      \
-	modify exact [esi ax bl];
-
-void    mul_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 d,u16 s);
-#pragma aux mul_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"mul	bx"                  	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	"mov	[esi],ax"				\
-	"mov	[ecx],dx"				\
-	parm [edi] [esi] [ecx] [ax] [bx]\
-	modify exact [esi edi ax bx dx];
-
-void    mul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s);
-#pragma aux mul_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"mul	ebx"                  	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	"mov	[esi],eax"				\
-	"mov	[ecx],edx"				\
-	parm [edi] [esi] [ecx] [eax] [ebx] \
-	modify exact [esi edi eax ebx edx];
-
-void	idiv_byte_asm(u32 *flags,u8 *al,u8 *ah,u16 d,u8 s);
-#pragma aux idiv_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"idiv	bl"                  	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	"mov	[esi],al"				\
-	"mov	[ecx],ah"				\
-	parm [edi] [esi] [ecx] [ax] [bl]\
-	modify exact [esi edi ax bl];
-
-void	idiv_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 dlo,u16 dhi,u16 s);
-#pragma aux idiv_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"idiv	bx"                  	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	"mov	[esi],ax"				\
-	"mov	[ecx],dx"				\
-	parm [edi] [esi] [ecx] [ax] [dx] [bx]\
-	modify exact [esi edi ax dx bx];
-
-void	idiv_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 dlo,u32 dhi,u32 s);
-#pragma aux idiv_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"idiv	ebx"                  	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	"mov	[esi],eax"				\
-	"mov	[ecx],edx"				\
-	parm [edi] [esi] [ecx] [eax] [edx] [ebx]\
-	modify exact [esi edi eax edx ebx];
-
-void	div_byte_asm(u32 *flags,u8 *al,u8 *ah,u16 d,u8 s);
-#pragma aux div_byte_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"div	bl"                  	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	"mov	[esi],al"				\
-	"mov	[ecx],ah"				\
-	parm [edi] [esi] [ecx] [ax] [bl]\
-	modify exact [esi edi ax bl];
-
-void	div_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 dlo,u16 dhi,u16 s);
-#pragma aux div_word_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"div	bx"                  	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	"mov	[esi],ax"				\
-	"mov	[ecx],dx"				\
-	parm [edi] [esi] [ecx] [ax] [dx] [bx]\
-	modify exact [esi edi ax dx bx];
-
-void	div_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 dlo,u32 dhi,u32 s);
-#pragma aux div_long_asm =			\
-	"push	[edi]"            		\
-	"popf"                         	\
-	"div	ebx"                  	\
-	"pushf"                         \
-	"pop	[edi]"            		\
-	"mov	[esi],eax"				\
-	"mov	[ecx],edx"				\
-	parm [edi] [esi] [ecx] [eax] [edx] [ebx]\
-	modify exact [esi edi eax edx ebx];
-
-#endif
-
-#endif /* __X86EMU_PRIM_ASM_H */
--- a/include/x86prim_ops.h
+++ b/include/x86prim_ops.h
@@ -1,232 +0,0 @@
-/****************************************************************************
-*
-*						Realmode X86 Emulator Library
-*
-*            	Copyright (C) 1996-1999 SciTech Software, Inc.
-* 				     Copyright (C) David Mosberger-Tang
-* 					   Copyright (C) 1999 Egbert Eich
-*
-*  ========================================================================
-*
-*  Permission to use, copy, modify, distribute, and sell this software and
-*  its documentation for any purpose is hereby granted without fee,
-*  provided that the above copyright notice appear in all copies and that
-*  both that copyright notice and this permission notice appear in
-*  supporting documentation, and that the name of the authors not be used
-*  in advertising or publicity pertaining to distribution of the software
-*  without specific, written prior permission.  The authors makes no
-*  representations about the suitability of this software for any purpose.
-*  It is provided "as is" without express or implied warranty.
-*
-*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
-*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
-*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
-*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
-*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
-*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
-*  PERFORMANCE OF THIS SOFTWARE.
-*
-*  ========================================================================
-*
-* Language:		ANSI C
-* Environment:	Any
-* Developer:    Kendall Bennett
-*
-* Description:  Header file for primitive operation functions.
-*
-****************************************************************************/
-
-#ifndef __X86EMU_PRIM_OPS_H
-#define __X86EMU_PRIM_OPS_H
-
-#include "x86prim_asm.h"
-
-#ifdef  __cplusplus
-extern "C" {            			/* Use "C" linkage when in C++ mode */
-#endif
-
-uint16_t     aaa_word (uint16_t d);
-uint16_t     aas_word (uint16_t d);
-uint16_t     aad_word (uint16_t d);
-uint16_t     aam_word (uint8_t d);
-uint8_t      adc_byte (uint8_t d, uint8_t s);
-uint16_t     adc_word (uint16_t d, uint16_t s);
-uint32_t     adc_long (uint32_t d, uint32_t s);
-uint8_t      add_byte (uint8_t d, uint8_t s);
-uint16_t     add_word (uint16_t d, uint16_t s);
-uint32_t     add_long (uint32_t d, uint32_t s);
-uint8_t      and_byte (uint8_t d, uint8_t s);
-uint16_t     and_word (uint16_t d, uint16_t s);
-uint32_t     and_long (uint32_t d, uint32_t s);
-uint8_t      cmp_byte (uint8_t d, uint8_t s);
-uint16_t     cmp_word (uint16_t d, uint16_t s);
-uint32_t     cmp_long (uint32_t d, uint32_t s);
-uint8_t      daa_byte (uint8_t d);
-uint8_t      das_byte (uint8_t d);
-uint8_t      dec_byte (uint8_t d);
-uint16_t     dec_word (uint16_t d);
-uint32_t     dec_long (uint32_t d);
-uint8_t      inc_byte (uint8_t d);
-uint16_t     inc_word (uint16_t d);
-uint32_t     inc_long (uint32_t d);
-uint8_t      or_byte (uint8_t d, uint8_t s);
-uint16_t     or_word (uint16_t d, uint16_t s);
-uint32_t     or_long (uint32_t d, uint32_t s);
-uint8_t      neg_byte (uint8_t s);
-uint16_t     neg_word (uint16_t s);
-uint32_t     neg_long (uint32_t s);
-uint8_t      not_byte (uint8_t s);
-uint16_t     not_word (uint16_t s);
-uint32_t     not_long (uint32_t s);
-uint8_t      rcl_byte (uint8_t d, uint8_t s);
-uint16_t     rcl_word (uint16_t d, uint8_t s);
-uint32_t     rcl_long (uint32_t d, uint8_t s);
-uint8_t      rcr_byte (uint8_t d, uint8_t s);
-uint16_t     rcr_word (uint16_t d, uint8_t s);
-uint32_t     rcr_long (uint32_t d, uint8_t s);
-uint8_t      rol_byte (uint8_t d, uint8_t s);
-uint16_t     rol_word (uint16_t d, uint8_t s);
-uint32_t     rol_long (uint32_t d, uint8_t s);
-uint8_t      ror_byte (uint8_t d, uint8_t s);
-uint16_t     ror_word (uint16_t d, uint8_t s);
-uint32_t     ror_long (uint32_t d, uint8_t s);
-uint8_t      shl_byte (uint8_t d, uint8_t s);
-uint16_t     shl_word (uint16_t d, uint8_t s);
-uint32_t     shl_long (uint32_t d, uint8_t s);
-uint8_t      shr_byte (uint8_t d, uint8_t s);
-uint16_t     shr_word (uint16_t d, uint8_t s);
-uint32_t     shr_long (uint32_t d, uint8_t s);
-uint8_t      sar_byte (uint8_t d, uint8_t s);
-uint16_t     sar_word (uint16_t d, uint8_t s);
-uint32_t     sar_long (uint32_t d, uint8_t s);
-uint16_t     shld_word (uint16_t d, uint16_t fill, uint8_t s);
-uint32_t     shld_long (uint32_t d, uint32_t fill, uint8_t s);
-uint16_t     shrd_word (uint16_t d, uint16_t fill, uint8_t s);
-uint32_t     shrd_long (uint32_t d, uint32_t fill, uint8_t s);
-uint8_t      sbb_byte (uint8_t d, uint8_t s);
-uint16_t     sbb_word (uint16_t d, uint16_t s);
-uint32_t     sbb_long (uint32_t d, uint32_t s);
-uint8_t      sub_byte (uint8_t d, uint8_t s);
-uint16_t     sub_word (uint16_t d, uint16_t s);
-uint32_t     sub_long (uint32_t d, uint32_t s);
-void    test_byte (uint8_t d, uint8_t s);
-void    test_word (uint16_t d, uint16_t s);
-void    test_long (uint32_t d, uint32_t s);
-uint8_t      xor_byte (uint8_t d, uint8_t s);
-uint16_t     xor_word (uint16_t d, uint16_t s);
-uint32_t     xor_long (uint32_t d, uint32_t s);
-void    imul_byte (uint8_t s);
-void    imul_word (uint16_t s);
-void    imul_long (uint32_t s);
-void 	imul_long_direct(uint32_t *res_lo, uint32_t* res_hi,uint32_t d, uint32_t s);
-void    mul_byte (uint8_t s);
-void    mul_word (uint16_t s);
-void    mul_long (uint32_t s);
-void    idiv_byte (uint8_t s);
-void    idiv_word (uint16_t s);
-void    idiv_long (uint32_t s);
-void    div_byte (uint8_t s);
-void    div_word (uint16_t s);
-void    div_long (uint32_t s);
-void    ins (int size);
-void    outs (int size);
-uint16_t     mem_access_word (int addr);
-void    push_word (uint16_t w);
-void    push_long (uint32_t w);
-uint16_t     pop_word (void);
-uint32_t		pop_long (void);
-
-
-#if  defined(__HAVE_INLINE_ASSEMBLER__) && !defined(PRIM_OPS_NO_REDEFINE_ASM)
-
-#define	aaa_word(d)		aaa_word_asm(&M.x86.R_EFLG,d)
-#define aas_word(d)		aas_word_asm(&M.x86.R_EFLG,d)
-#define aad_word(d)		aad_word_asm(&M.x86.R_EFLG,d)
-#define aam_word(d)		aam_word_asm(&M.x86.R_EFLG,d)
-#define adc_byte(d,s)	adc_byte_asm(&M.x86.R_EFLG,d,s)
-#define adc_word(d,s)	adc_word_asm(&M.x86.R_EFLG,d,s)
-#define adc_long(d,s)	adc_long_asm(&M.x86.R_EFLG,d,s)
-#define add_byte(d,s) 	add_byte_asm(&M.x86.R_EFLG,d,s)
-#define add_word(d,s)	add_word_asm(&M.x86.R_EFLG,d,s)
-#define add_long(d,s)	add_long_asm(&M.x86.R_EFLG,d,s)
-#define and_byte(d,s)	and_byte_asm(&M.x86.R_EFLG,d,s)
-#define and_word(d,s)	and_word_asm(&M.x86.R_EFLG,d,s)
-#define and_long(d,s)	and_long_asm(&M.x86.R_EFLG,d,s)
-#define cmp_byte(d,s)	cmp_byte_asm(&M.x86.R_EFLG,d,s)
-#define cmp_word(d,s)	cmp_word_asm(&M.x86.R_EFLG,d,s)
-#define cmp_long(d,s)	cmp_long_asm(&M.x86.R_EFLG,d,s)
-#define daa_byte(d)		daa_byte_asm(&M.x86.R_EFLG,d)
-#define das_byte(d)		das_byte_asm(&M.x86.R_EFLG,d)
-#define dec_byte(d)		dec_byte_asm(&M.x86.R_EFLG,d)
-#define dec_word(d)		dec_word_asm(&M.x86.R_EFLG,d)
-#define dec_long(d)		dec_long_asm(&M.x86.R_EFLG,d)
-#define inc_byte(d)		inc_byte_asm(&M.x86.R_EFLG,d)
-#define inc_word(d)		inc_word_asm(&M.x86.R_EFLG,d)
-#define inc_long(d)		inc_long_asm(&M.x86.R_EFLG,d)
-#define or_byte(d,s)	or_byte_asm(&M.x86.R_EFLG,d,s)
-#define or_word(d,s)	or_word_asm(&M.x86.R_EFLG,d,s)
-#define or_long(d,s)	or_long_asm(&M.x86.R_EFLG,d,s)
-#define neg_byte(s)		neg_byte_asm(&M.x86.R_EFLG,s)
-#define neg_word(s)		neg_word_asm(&M.x86.R_EFLG,s)
-#define neg_long(s)		neg_long_asm(&M.x86.R_EFLG,s)
-#define not_byte(s)		not_byte_asm(&M.x86.R_EFLG,s)
-#define not_word(s)		not_word_asm(&M.x86.R_EFLG,s)
-#define not_long(s)		not_long_asm(&M.x86.R_EFLG,s)
-#define rcl_byte(d,s)	rcl_byte_asm(&M.x86.R_EFLG,d,s)
-#define rcl_word(d,s)	rcl_word_asm(&M.x86.R_EFLG,d,s)
-#define rcl_long(d,s)	rcl_long_asm(&M.x86.R_EFLG,d,s)
-#define rcr_byte(d,s)	rcr_byte_asm(&M.x86.R_EFLG,d,s)
-#define rcr_word(d,s)	rcr_word_asm(&M.x86.R_EFLG,d,s)
-#define rcr_long(d,s)	rcr_long_asm(&M.x86.R_EFLG,d,s)
-#define rol_byte(d,s)	rol_byte_asm(&M.x86.R_EFLG,d,s)
-#define rol_word(d,s)	rol_word_asm(&M.x86.R_EFLG,d,s)
-#define rol_long(d,s)	rol_long_asm(&M.x86.R_EFLG,d,s)
-#define ror_byte(d,s)	ror_byte_asm(&M.x86.R_EFLG,d,s)
-#define ror_word(d,s)	ror_word_asm(&M.x86.R_EFLG,d,s)
-#define ror_long(d,s)	ror_long_asm(&M.x86.R_EFLG,d,s)
-#define shl_byte(d,s)	shl_byte_asm(&M.x86.R_EFLG,d,s)
-#define shl_word(d,s)	shl_word_asm(&M.x86.R_EFLG,d,s)
-#define shl_long(d,s)	shl_long_asm(&M.x86.R_EFLG,d,s)
-#define shr_byte(d,s)	shr_byte_asm(&M.x86.R_EFLG,d,s)
-#define shr_word(d,s)	shr_word_asm(&M.x86.R_EFLG,d,s)
-#define shr_long(d,s)	shr_long_asm(&M.x86.R_EFLG,d,s)
-#define sar_byte(d,s)	sar_byte_asm(&M.x86.R_EFLG,d,s)
-#define sar_word(d,s)	sar_word_asm(&M.x86.R_EFLG,d,s)
-#define sar_long(d,s)	sar_long_asm(&M.x86.R_EFLG,d,s)
-#define shld_word(d,fill,s)	shld_word_asm(&M.x86.R_EFLG,d,fill,s)
-#define shld_long(d,fill,s)	shld_long_asm(&M.x86.R_EFLG,d,fill,s)
-#define shrd_word(d,fill,s)	shrd_word_asm(&M.x86.R_EFLG,d,fill,s)
-#define shrd_long(d,fill,s)	shrd_long_asm(&M.x86.R_EFLG,d,fill,s)
-#define sbb_byte(d,s)	sbb_byte_asm(&M.x86.R_EFLG,d,s)
-#define sbb_word(d,s)	sbb_word_asm(&M.x86.R_EFLG,d,s)
-#define sbb_long(d,s)	sbb_long_asm(&M.x86.R_EFLG,d,s)
-#define sub_byte(d,s)	sub_byte_asm(&M.x86.R_EFLG,d,s)
-#define sub_word(d,s)	sub_word_asm(&M.x86.R_EFLG,d,s)
-#define sub_long(d,s)	sub_long_asm(&M.x86.R_EFLG,d,s)
-#define test_byte(d,s)	test_byte_asm(&M.x86.R_EFLG,d,s)
-#define test_word(d,s)	test_word_asm(&M.x86.R_EFLG,d,s)
-#define test_long(d,s)	test_long_asm(&M.x86.R_EFLG,d,s)
-#define xor_byte(d,s)	xor_byte_asm(&M.x86.R_EFLG,d,s)
-#define xor_word(d,s)	xor_word_asm(&M.x86.R_EFLG,d,s)
-#define xor_long(d,s)	xor_long_asm(&M.x86.R_EFLG,d,s)
-#define imul_byte(s)	imul_byte_asm(&M.x86.R_EFLG,&M.x86.R_AX,M.x86.R_AL,s)
-#define imul_word(s)	imul_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,s)
-#define imul_long(s)	imul_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s)
-#define imul_long_direct(res_lo,res_hi,d,s)	imul_long_asm(&M.x86.R_EFLG,res_lo,res_hi,d,s)
-#define mul_byte(s)		mul_byte_asm(&M.x86.R_EFLG,&M.x86.R_AX,M.x86.R_AL,s)
-#define mul_word(s)		mul_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,s)
-#define mul_long(s)		mul_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s)
-#define idiv_byte(s)	idiv_byte_asm(&M.x86.R_EFLG,&M.x86.R_AL,&M.x86.R_AH,M.x86.R_AX,s)
-#define idiv_word(s)	idiv_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,M.x86.R_DX,s)
-#define idiv_long(s)	idiv_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s)
-#define div_byte(s)		div_byte_asm(&M.x86.R_EFLG,&M.x86.R_AL,&M.x86.R_AH,M.x86.R_AX,s)
-#define div_word(s)		div_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,M.x86.R_DX,s)
-#define div_long(s)		div_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s)
-
-#endif
-
-#ifdef  __cplusplus
-}                       			/* End of "C" linkage for C++   	*/
-#endif
-
-#endif /* __X86EMU_PRIM_OPS_H */
--- a/include/x86regs.h
+++ b/include/x86regs.h
@@ -1,358 +0,0 @@
-/****************************************************************************
- *
- *						Realmode X86 Emulator Library
- *
- *            	Copyright (C) 1996-1999 SciTech Software, Inc.
- * 				     Copyright (C) David Mosberger-Tang
- * 					   Copyright (C) 1999 Egbert Eich
- *
- *  ========================================================================
- *
- *  Permission to use, copy, modify, distribute, and sell this software and
- *  its documentation for any purpose is hereby granted without fee,
- *  provided that the above copyright notice appear in all copies and that
- *  both that copyright notice and this permission notice appear in
- *  supporting documentation, and that the name of the authors not be used
- *  in advertising or publicity pertaining to distribution of the software
- *  without specific, written prior permission.  The authors makes no
- *  representations about the suitability of this software for any purpose.
- *  It is provided "as is" without express or implied warranty.
- *
- *  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- *  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
- *  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- *  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
- *  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
- *  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- *  PERFORMANCE OF THIS SOFTWARE.
- *
- *  ========================================================================
- *
- * Language:		ANSI C
- * Environment:	Any
- * Developer:    Kendall Bennett
- *
- * Description:  Header file for x86 register definitions.
- *
- ****************************************************************************/
-/* $XFree86: xc/extras/x86emu/include/x86emu/regs.h,v 1.3 2001/10/28 03:32:25 tsi Exp $ */
-
-#ifndef __X86EMU_REGS_H
-#define __X86EMU_REGS_H
-#include "x86debug.h"
-
-/*---------------------- Macros and type definitions ----------------------*/
-
-//#pragma pack(1)
-
-/*
- * General EAX, EBX, ECX, EDX type registers.  Note that for
- * portability, and speed, the issue of byte swapping is not addressed
- * in the registers.  All registers are stored in the default format
- * available on the host machine.  The only critical issue is that the
- * registers should line up EXACTLY in the same manner as they do in
- * the 386.  That is:
- *
- * EAX & 0xff  === AL
- * EAX & 0xffff == AX
- *
- * etc.  The result is that alot of the calculations can then be
- * done using the native instruction set fully.
- */
-
-typedef struct {
-	uint32_t e_reg;
-} I32_reg_t;
-
-typedef struct {
-	uint16_t filler0, x_reg;
-} I16_reg_t;
-
-typedef struct {
-	uint8_t filler0, filler1, h_reg, l_reg;
-} I8_reg_t;
-
-typedef union {
-	I32_reg_t   I32_reg;
-	I16_reg_t   I16_reg;
-	I8_reg_t    I8_reg;
-} i386_general_register;
-
-struct i386_general_regs {
-	i386_general_register A, B, C, D;
-};
-
-typedef struct i386_general_regs Gen_reg_t;
-
-struct i386_special_regs {
-	i386_general_register SP, BP, SI, DI, IP;
-	uint32_t FLAGS;
-};
-
-/*  
- * Segment registers here represent the 16 bit quantities
- * CS, DS, ES, SS.
- */
-
-struct i386_segment_regs {
-	uint16_t CS, DS, SS, ES, FS, GS;
-};
-
-/* 8 bit registers */
-#define R_AH  gen.A.I8_reg.h_reg
-#define R_AL  gen.A.I8_reg.l_reg
-#define R_BH  gen.B.I8_reg.h_reg
-#define R_BL  gen.B.I8_reg.l_reg
-#define R_CH  gen.C.I8_reg.h_reg
-#define R_CL  gen.C.I8_reg.l_reg
-#define R_DH  gen.D.I8_reg.h_reg
-#define R_DL  gen.D.I8_reg.l_reg
-
-/* 16 bit registers */
-#define R_AX  gen.A.I16_reg.x_reg
-#define R_BX  gen.B.I16_reg.x_reg
-#define R_CX  gen.C.I16_reg.x_reg
-#define R_DX  gen.D.I16_reg.x_reg
-
-/* 32 bit extended registers */
-#define R_EAX  gen.A.I32_reg.e_reg
-#define R_EBX  gen.B.I32_reg.e_reg
-#define R_ECX  gen.C.I32_reg.e_reg
-#define R_EDX  gen.D.I32_reg.e_reg
-
-/* special registers */
-#define R_SP  spc.SP.I16_reg.x_reg
-#define R_BP  spc.BP.I16_reg.x_reg
-#define R_SI  spc.SI.I16_reg.x_reg
-#define R_DI  spc.DI.I16_reg.x_reg
-#define R_IP  spc.IP.I16_reg.x_reg
-#define R_FLG spc.FLAGS
-
-/* special registers */
-#define R_SP  spc.SP.I16_reg.x_reg
-#define R_BP  spc.BP.I16_reg.x_reg
-#define R_SI  spc.SI.I16_reg.x_reg
-#define R_DI  spc.DI.I16_reg.x_reg
-#define R_IP  spc.IP.I16_reg.x_reg
-#define R_FLG spc.FLAGS
-
-/* special registers */
-#define R_ESP  spc.SP.I32_reg.e_reg
-#define R_EBP  spc.BP.I32_reg.e_reg
-#define R_ESI  spc.SI.I32_reg.e_reg
-#define R_EDI  spc.DI.I32_reg.e_reg
-#define R_EIP  spc.IP.I32_reg.e_reg
-#define R_EFLG spc.FLAGS
-
-/* segment registers */
-#define R_CS  seg.CS
-#define R_DS  seg.DS
-#define R_SS  seg.SS
-#define R_ES  seg.ES
-#define R_FS  seg.FS
-#define R_GS  seg.GS
-
-/* flag conditions   */
-#define FB_CF 0x0001            /* CARRY flag  */
-#define FB_PF 0x0004            /* PARITY flag */
-#define FB_AF 0x0010            /* AUX  flag   */
-#define FB_ZF 0x0040            /* ZERO flag   */
-#define FB_SF 0x0080            /* SIGN flag   */
-#define FB_TF 0x0100            /* TRAP flag   */
-#define FB_IF 0x0200            /* INTERRUPT ENABLE flag */
-#define FB_DF 0x0400            /* DIR flag    */
-#define FB_OF 0x0800            /* OVERFLOW flag */
-
-/* 80286 and above always have bit#1 set */
-#define F_ALWAYS_ON  (0x0002)   /* flag bits always on */
-
-/*
- * Define a mask for only those flag bits we will ever pass back 
- * (via PUSHF) 
- */
-#define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF)
-
-/* following bits masked in to a 16bit quantity */
-
-#define F_CF 0x0001             /* CARRY flag  */
-#define F_PF 0x0004             /* PARITY flag */
-#define F_AF 0x0010             /* AUX  flag   */
-#define F_ZF 0x0040             /* ZERO flag   */
-#define F_SF 0x0080             /* SIGN flag   */
-#define F_TF 0x0100             /* TRAP flag   */
-#define F_IF 0x0200             /* INTERRUPT ENABLE flag */
-#define F_DF 0x0400             /* DIR flag    */
-#define F_OF 0x0800             /* OVERFLOW flag */
-
-#define TOGGLE_FLAG(flag)     	(M.x86.R_FLG ^= (flag))
-#define SET_FLAG(flag)        	(M.x86.R_FLG |= (flag))
-#define CLEAR_FLAG(flag)      	(M.x86.R_FLG &= ~(flag))
-#define ACCESS_FLAG(flag)     	(M.x86.R_FLG & (flag))
-#define CLEARALL_FLAG(m)    	(M.x86.R_FLG = 0)
-
-#define CONDITIONAL_SET_FLAG(COND,FLAG) \
-	if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG)
-
-#define F_PF_CALC 0x010000      /* PARITY flag has been calced    */
-#define F_ZF_CALC 0x020000      /* ZERO flag has been calced      */
-#define F_SF_CALC 0x040000      /* SIGN flag has been calced      */
-
-#define F_ALL_CALC      0xff0000        /* All have been calced   */
-
-/*
- * Emulator machine state.
- * Segment usage control.
- */
-#define SYSMODE_SEG_DS_SS       0x00000001
-#define SYSMODE_SEGOVR_CS       0x00000002
-#define SYSMODE_SEGOVR_DS       0x00000004
-#define SYSMODE_SEGOVR_ES       0x00000008
-#define SYSMODE_SEGOVR_FS       0x00000010
-#define SYSMODE_SEGOVR_GS       0x00000020
-#define SYSMODE_SEGOVR_SS       0x00000040
-#define SYSMODE_PREFIX_REPE     0x00000080
-#define SYSMODE_PREFIX_REPNE    0x00000100
-#define SYSMODE_PREFIX_DATA     0x00000200
-#define SYSMODE_PREFIX_ADDR     0x00000400
-#define SYSMODE_INTR_PENDING    0x10000000
-#define SYSMODE_EXTRN_INTR      0x20000000
-#define SYSMODE_HALTED          0x40000000
-
-#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS      | \
-		SYSMODE_SEGOVR_CS      | \
-		SYSMODE_SEGOVR_DS      | \
-		SYSMODE_SEGOVR_ES      | \
-		SYSMODE_SEGOVR_FS      | \
-		SYSMODE_SEGOVR_GS      | \
-		SYSMODE_SEGOVR_SS)
-#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS      | \
-		SYSMODE_SEGOVR_CS      | \
-		SYSMODE_SEGOVR_DS      | \
-		SYSMODE_SEGOVR_ES      | \
-		SYSMODE_SEGOVR_FS      | \
-		SYSMODE_SEGOVR_GS      | \
-		SYSMODE_SEGOVR_SS      | \
-		SYSMODE_PREFIX_DATA    | \
-		SYSMODE_PREFIX_ADDR)
-
-#define  INTR_SYNCH           0x1
-#define  INTR_ASYNCH          0x2
-#define  INTR_HALTED          0x4
-
-typedef struct {
-	struct i386_general_regs    gen;
-	struct i386_special_regs    spc;
-	struct i386_segment_regs    seg;
-	/*
-	 * MODE contains information on:
-	 *  REPE prefix             2 bits  repe,repne
-	 *  SEGMENT overrides       5 bits  normal,DS,SS,CS,ES
-	 *  Delayed flag set        3 bits  (zero, signed, parity)
-	 *  reserved                6 bits
-	 *  interrupt #             8 bits  instruction raised interrupt
-	 *  BIOS video segregs      4 bits  
-	 *  Interrupt Pending       1 bits  
-	 *  Extern interrupt        1 bits
-	 *  Halted                  1 bits
-	 */
-	uint32_t                         mode;
-	volatile int                intr;   /* mask of pending interrupts */
-	int                         debug;
-#ifdef DBG_X86EMU
-	int check;
-	uint16_t saved_ip;
-	uint16_t saved_cs;
-	int enc_pos;
-	int enc_str_pos;
-	//    char decode_buf[32]; /* encoded byte stream  */
-	char decoded_buf[256]; /* disassembled strings */
-#endif
-	uint8_t intno;
-	uint8_t __pad[3];
-} X86EMU_regs;
-
-/****************************************************************************
-REMARKS:
-Structure maintaining the emulator machine state.
-
-MEMBERS:
-mem_base		- Base real mode memory for the emulator
-abseg			- Base for the absegment
-mem_size		- Size of the real mode memory block for the emulator
-private			- private data pointer
-x86			- X86 registers
- ****************************************************************************/
-typedef struct
-{
-	unsigned long mem_base;
-	unsigned long mem_size;
-	unsigned long abseg;
-	void* private;
-	X86EMU_regs x86;
-} X86EMU_sysEnv;
-
-//#pragma pack()
-
-/*----------------------------- Global Variables --------------------------*/
-
-#ifdef  __cplusplus
-extern "C" {            			/* Use "C" linkage when in C++ mode */
-#endif
-
-/* Global emulator machine state.
- *
- * We keep it global to avoid pointer dereferences in the code for speed.
- */
-
-extern X86EMU_sysEnv	_X86EMU_env;
-
-#define M _X86EMU_env
-
-#define X86_EAX M.x86.R_EAX
-#define X86_EBX M.x86.R_EBX
-#define X86_ECX M.x86.R_ECX
-#define X86_EDX M.x86.R_EDX
-#define X86_ESI M.x86.R_ESI
-#define X86_EDI M.x86.R_EDI
-#define X86_EBP M.x86.R_EBP
-#define X86_EIP M.x86.R_EIP
-#define X86_ESP M.x86.R_ESP
-#define X86_EFLAGS M.x86.R_EFLG
-
-#define X86_FLAGS M.x86.R_FLG
-#define X86_AX M.x86.R_AX
-#define X86_BX M.x86.R_BX
-#define X86_CX M.x86.R_CX
-#define X86_DX M.x86.R_DX
-#define X86_SI M.x86.R_SI
-#define X86_DI M.x86.R_DI
-#define X86_BP M.x86.R_BP
-#define X86_IP M.x86.R_IP
-#define X86_SP M.x86.R_SP
-#define X86_CS M.x86.R_CS
-#define X86_DS M.x86.R_DS
-#define X86_ES M.x86.R_ES
-#define X86_SS M.x86.R_SS
-#define X86_FS M.x86.R_FS
-#define X86_GS M.x86.R_GS
-
-#define X86_AL M.x86.R_AL
-#define X86_BL M.x86.R_BL
-#define X86_CL M.x86.R_CL
-#define X86_DL M.x86.R_DL
-
-#define X86_AH M.x86.R_AH
-#define X86_BH M.x86.R_BH
-#define X86_CH M.x86.R_CH
-#define X86_DH M.x86.R_DH
-
-
-/*-------------------------- Function Prototypes --------------------------*/
-
-/* Function to log information at runtime */
-
-#ifdef  __cplusplus
-}                       			/* End of "C" linkage for C++   	*/
-#endif
-
-#endif /* __X86EMU_REGS_H */
--- a/kbd/ikbd.c
+++ b/kbd/ikbd.c
@@ -35,305 +35,305 @@

 #define IKBD_DEFAULT IKBD_STATE_JOYSTICK_EVENT_REPORTING

-#define QUEUE_LEN 16    // power of 2!
+#define QUEUE_LEN 16        // power of 2!
 static unsigned char tx_queue[QUEUE_LEN];
 static unsigned char wptr = 0, rptr = 0;

 // structure to keep track of ikbd state
 static struct
 {
-	unsigned char cmd;
-	unsigned char state;
-	unsigned char expect;
+    unsigned char cmd;
+    unsigned char state;
+    unsigned char expect;

-	// joystick state
-	unsigned char joystick[2];
+    // joystick state
+    unsigned char joystick[2];

-	// mouse state
-	unsigned short mouse_pos_x, mouse_pos_y;
-	unsigned char mouse_buttons;
+    // mouse state
+    unsigned short mouse_pos_x, mouse_pos_y;
+    unsigned char mouse_buttons;
 } ikbd;

 // #define IKBD_DEBUG

 void ikbd_init()
 {
-	// reset ikbd state
-	memset(&ikbd, 0, sizeof(ikbd));
-	ikbd.state = IKBD_DEFAULT;
+    // reset ikbd state
+    memset(&ikbd, 0, sizeof(ikbd));
+    ikbd.state = IKBD_DEFAULT;
 }

 static void enqueue(unsigned char b)
 {
-	if (((wptr + 1)&(QUEUE_LEN-1)) == rptr)
-	{
-		xprintf("IKBD: !!!!!!! tx queue overflow !!!!!!!!!\n");
-		return;
-	}
+    if (((wptr + 1)&(QUEUE_LEN-1)) == rptr)
+    {
+        xprintf("IKBD: !!!!!!! tx queue overflow !!!!!!!!!\n");
+        return;
+    }

-	tx_queue[wptr] = b;
-	wptr = (wptr + 1) & (QUEUE_LEN - 1);
+    tx_queue[wptr] = b;
+    wptr = (wptr + 1) & (QUEUE_LEN - 1);
 }

 // convert internal joystick format into atari ikbd format
 static unsigned char joystick_map2ikbd(unsigned in)
 {
-	unsigned char out = 0;
+    unsigned char out = 0;

-	if (in & JOY_UP)    out |= 0x01;
-	if (in & JOY_DOWN)  out |= 0x02;
-	if (in & JOY_LEFT)  out |= 0x04;
-	if (in & JOY_RIGHT) out |= 0x08;
-	if (in & JOY_BTN1)  out |= 0x80;
+    if (in & JOY_UP)    out |= 0x01;
+    if (in & JOY_DOWN)  out |= 0x02;
+    if (in & JOY_LEFT)  out |= 0x04;
+    if (in & JOY_RIGHT) out |= 0x08;
+    if (in & JOY_BTN1)  out |= 0x80;

-	return out;
+    return out;
 }

 // process inout from atari core into ikbd
 void ikbd_handle_input(unsigned char cmd)
 {
-	// expecting a second byte for command
-	if (ikbd.expect)
-	{
-		ikbd.expect--;
+    // expecting a second byte for command
+    if (ikbd.expect)
+    {
+        ikbd.expect--;

-		// last byte of command received
-		if (!ikbd.expect)
-		{
-			switch(ikbd.cmd)
-			{
-				case 0x07: // set mouse button action
-					xprintf("IKBD: mouse button action = %x\n", cmd);
+        // last byte of command received
+        if (!ikbd.expect)
+        {
+            switch(ikbd.cmd)
+            {
+                case 0x07: // set mouse button action
+                    xprintf("IKBD: mouse button action = %x\n", cmd);

-					// bit 2: Mouse buttons act like keys (LEFT=0x74 & RIGHT=0x75)
-					if(cmd & 0x04) ikbd.state |=  IKBD_STATE_MOUSE_BUTTON_AS_KEY;
-					else           ikbd.state &= ~IKBD_STATE_MOUSE_BUTTON_AS_KEY;
+                    // bit 2: Mouse buttons act like keys (LEFT=0x74 & RIGHT=0x75)
+                    if(cmd & 0x04) ikbd.state |=  IKBD_STATE_MOUSE_BUTTON_AS_KEY;
+                    else           ikbd.state &= ~IKBD_STATE_MOUSE_BUTTON_AS_KEY;

-					break;
+                    break;

-				case 0x80: // ibkd reset
-					// reply "everything is ok"
-					enqueue(0xf0);
-					break;
+                case 0x80: // ibkd reset
+                    // reply "everything is ok"
+                    enqueue(0xf0);
+                    break;

-				default:
-					break;
-			}
-		}
+                default:
+                    break;
+            }
+        }

-		return;
-	}
+        return;
+    }

-	ikbd.cmd = cmd;
+    ikbd.cmd = cmd;

-	switch(cmd)
-	{
-		case 0x07:
-			xprintf("IKBD: Set mouse button action");
-			ikbd.expect = 1;
-			break;
+    switch(cmd)
+    {
+        case 0x07:
+            xprintf("IKBD: Set mouse button action");
+            ikbd.expect = 1;
+            break;

-		case 0x08:
-			xprintf("IKBD: Set relative mouse positioning");
-			ikbd.state &= ~IKBD_STATE_MOUSE_DISABLED;
-			ikbd.state &= ~IKBD_STATE_MOUSE_ABSOLUTE;
-			break;
+        case 0x08:
+            xprintf("IKBD: Set relative mouse positioning");
+            ikbd.state &= ~IKBD_STATE_MOUSE_DISABLED;
+            ikbd.state &= ~IKBD_STATE_MOUSE_ABSOLUTE;
+            break;

-		case 0x09:
-			xprintf("IKBD: Set absolute mouse positioning");
-			ikbd.state &= ~IKBD_STATE_MOUSE_DISABLED;
-			ikbd.state |=  IKBD_STATE_MOUSE_ABSOLUTE;
-			ikbd.expect = 4;
-			break;
+        case 0x09:
+            xprintf("IKBD: Set absolute mouse positioning");
+            ikbd.state &= ~IKBD_STATE_MOUSE_DISABLED;
+            ikbd.state |=  IKBD_STATE_MOUSE_ABSOLUTE;
+            ikbd.expect = 4;
+            break;

-		case 0x0b:
-			xprintf("IKBD: Set Mouse threshold");
-			ikbd.expect = 2;
-			break;
+        case 0x0b:
+            xprintf("IKBD: Set Mouse threshold");
+            ikbd.expect = 2;
+            break;

-		case 0x0f:
-			xprintf("IKBD: Set Y at bottom");
-			ikbd.state |= IKBD_STATE_MOUSE_Y_BOTTOM;
-			break;
+        case 0x0f:
+            xprintf("IKBD: Set Y at bottom");
+            ikbd.state |= IKBD_STATE_MOUSE_Y_BOTTOM;
+            break;

-		case 0x10:
-			xprintf("IKBD: Set Y at top");
-			ikbd.state &= ~IKBD_STATE_MOUSE_Y_BOTTOM;
-			break;
+        case 0x10:
+            xprintf("IKBD: Set Y at top");
+            ikbd.state &= ~IKBD_STATE_MOUSE_Y_BOTTOM;
+            break;

-		case 0x12:
-			xprintf("IKBD: Disable mouse");
-			ikbd.state |= IKBD_STATE_MOUSE_DISABLED;
-			break;
+        case 0x12:
+            xprintf("IKBD: Disable mouse");
+            ikbd.state |= IKBD_STATE_MOUSE_DISABLED;
+            break;

-		case 0x14:
-			xprintf("IKBD: Set Joystick event reporting");
-			ikbd.state |= IKBD_STATE_JOYSTICK_EVENT_REPORTING;
-			break;
+        case 0x14:
+            xprintf("IKBD: Set Joystick event reporting");
+            ikbd.state |= IKBD_STATE_JOYSTICK_EVENT_REPORTING;
+            break;

-		case 0x15:
-			xprintf("IKBD: Set Joystick interrogation mode");
-			ikbd.state &= ~IKBD_STATE_JOYSTICK_EVENT_REPORTING;
-			break;
+        case 0x15:
+            xprintf("IKBD: Set Joystick interrogation mode");
+            ikbd.state &= ~IKBD_STATE_JOYSTICK_EVENT_REPORTING;
+            break;

-		case 0x16: // interrogate joystick
-			// send reply
-			enqueue(0xfd);
-			enqueue(joystick_map2ikbd(ikbd.joystick[0]));
-			enqueue(joystick_map2ikbd(ikbd.joystick[1]));
-			break;
+        case 0x16: // interrogate joystick
+            // send reply
+            enqueue(0xfd);
+            enqueue(joystick_map2ikbd(ikbd.joystick[0]));
+            enqueue(joystick_map2ikbd(ikbd.joystick[1]));
+            break;

-		case 0x1a:
-			xprintf("IKBD: Disable joysticks");
-			ikbd.state &= ~IKBD_STATE_JOYSTICK_EVENT_REPORTING;
-			break;
+        case 0x1a:
+            xprintf("IKBD: Disable joysticks");
+            ikbd.state &= ~IKBD_STATE_JOYSTICK_EVENT_REPORTING;
+            break;

-		case 0x1c:
-			xprintf("IKBD: Interrogate time of day");
+        case 0x1c:
+            xprintf("IKBD: Interrogate time of day");

-			enqueue(0xfc);
-			enqueue(0x13);  // year bcd
-			enqueue(0x03);  // month bcd
-			enqueue(0x07);  // day bcd
-			enqueue(0x20);  // hour bcd
-			enqueue(0x58);  // minute bcd
-			enqueue(0x00);  // second bcd
-			break;
+            enqueue(0xfc);
+            enqueue(0x13);  // year bcd
+            enqueue(0x03);  // month bcd
+            enqueue(0x07);  // day bcd
+            enqueue(0x20);  // hour bcd
+            enqueue(0x58);  // minute bcd
+            enqueue(0x00);  // second bcd
+            break;


-		case 0x80:
-			xprintf("IKBD: Reset");
-			ikbd.expect = 1;
-			ikbd.state = IKBD_DEFAULT;
-			break;
+        case 0x80:
+            xprintf("IKBD: Reset");
+            ikbd.expect = 1;
+            ikbd.state = IKBD_DEFAULT;
+            break;

-		default:
-			xprintf("IKBD: unknown command: %x\n", cmd);
-			break;
-	}
+        default:
+            xprintf("IKBD: unknown command: %x\n", cmd);
+            break;
+    }
 }

 void ikbd_poll(void) {
-	static int mtimer = 0;
-	if (CheckTimer(mtimer))
-	{
-		mtimer = GetTimer(10);
+    static int mtimer = 0;
+    if (CheckTimer(mtimer))
+    {
+        mtimer = GetTimer(10);

-		// check for incoming ikbd data
-		EnableIO();
-		SPI(UIO_IKBD_IN);
+        // check for incoming ikbd data
+        EnableIO();
+        SPI(UIO_IKBD_IN);

-		while(SPI(0))
-			ikbd_handle_input(SPI(0));
+        while(SPI(0))
+            ikbd_handle_input(SPI(0));

-		DisableIO();
-	}
+        DisableIO();
+    }

-	// send data from queue if present
-	if(rptr == wptr) return;
+    // send data from queue if present
+    if(rptr == wptr) return;

-	// transmit data from queue
-	EnableIO();
-	SPI(UIO_IKBD_OUT);
-	SPI(tx_queue[rptr]);
-	DisableIO();
+    // transmit data from queue
+    EnableIO();
+    SPI(UIO_IKBD_OUT);
+    SPI(tx_queue[rptr]);
+    DisableIO();

-	rptr = (rptr + 1) & (QUEUE_LEN - 1);
+    rptr = (rptr + 1) & (QUEUE_LEN - 1);
 }

 void ikbd_joystick(unsigned char joystick, unsigned char map)
 {
-	// todo: suppress events for joystick 0 as long as mouse
-	// is enabled?
+    // todo: suppress events for joystick 0 as long as mouse
+    // is enabled?

-	if (ikbd.state & IKBD_STATE_JOYSTICK_EVENT_REPORTING)
-	{
+    if (ikbd.state & IKBD_STATE_JOYSTICK_EVENT_REPORTING)
+    {
 #ifdef IKBD_DEBUG
-		xprintf("IKBD: joy %d %x\n", joystick, map);
+        xprintf("IKBD: joy %d %x\n", joystick, map);
 #endif

-		// only report joystick data for joystick 0 if the mouse is disabled
-		if ((ikbd.state & IKBD_STATE_MOUSE_DISABLED) || (joystick == 1))
-		{
-			enqueue(0xfe + joystick);
-			enqueue(joystick_map2ikbd(map));
-		}
+        // only report joystick data for joystick 0 if the mouse is disabled
+        if ((ikbd.state & IKBD_STATE_MOUSE_DISABLED) || (joystick == 1))
+        {
+            enqueue(0xfe + joystick);
+            enqueue(joystick_map2ikbd(map));
+        }

-		if (!(ikbd.state & IKBD_STATE_MOUSE_DISABLED))
-		{
-			// the fire button also generates a mouse event if
-			// mouse reporting is enabled
-			if ((map & JOY_BTN1) != (ikbd.joystick[joystick] & JOY_BTN1))
-			{
-				// generate mouse event (ikbd_joystick_buttons is evaluated inside
-				// user_io_mouse)
-				ikbd.joystick[joystick] = map;
-				ikbd_mouse(0, 0, 0);
-			}
-		}
-	}
+        if (!(ikbd.state & IKBD_STATE_MOUSE_DISABLED))
+        {
+            // the fire button also generates a mouse event if
+            // mouse reporting is enabled
+            if ((map & JOY_BTN1) != (ikbd.joystick[joystick] & JOY_BTN1))
+            {
+                // generate mouse event (ikbd_joystick_buttons is evaluated inside
+                // user_io_mouse)
+                ikbd.joystick[joystick] = map;
+                ikbd_mouse(0, 0, 0);
+            }
+        }
+    }
 #ifdef IKBD_DEBUG
-	else
-		xprintf("IKBD: no monitor, drop joy %d %x\n", joystick, map);
+    else
+        xprintf("IKBD: no monitor, drop joy %d %x\n", joystick, map);
 #endif

-	// save state of joystick for interrogation mode
-	ikbd.joystick[joystick] = map;
+    // save state of joystick for interrogation mode
+    ikbd.joystick[joystick] = map;
 }

 void ikbd_keyboard(unsigned char code)
 {
 #ifdef IKBD_DEBUG
-	xprintf("IKBD: send keycode %x%s\n", code&0x7f, (code&0x80)?" BREAK":"");
+    xprintf("IKBD: send keycode %x%s\n", code&0x7f, (code&0x80)?" BREAK":"");
 #endif
-	enqueue(code);
+    enqueue(code);
 }

 void ikbd_mouse(uint8_t b, int8_t x, int8_t y)
 {
-	if (ikbd.state & IKBD_STATE_MOUSE_DISABLED)
-		return;
+    if (ikbd.state & IKBD_STATE_MOUSE_DISABLED)
+        return;

-	// joystick and mouse buttons are wired together in
-	// atari st
-	b |= (ikbd.joystick[0] & JOY_BTN1)?1:0;
-	b |= (ikbd.joystick[1] & JOY_BTN1)?2:0;
+    // joystick and mouse buttons are wired together in
+    // atari st
+    b |= (ikbd.joystick[0] & JOY_BTN1)?1:0;
+    b |= (ikbd.joystick[1] & JOY_BTN1)?2:0;

-	static unsigned char b_old = 0;
-	// monitor state of two mouse buttons
-	if (b != b_old)
-	{
-		// check if mouse buttons are supposed to be treated like keys
-		if (ikbd.state & IKBD_STATE_MOUSE_BUTTON_AS_KEY)
-		{
-			// Mouse buttons act like keys (LEFT=0x74 & RIGHT=0x75)
+    static unsigned char b_old = 0;
+    // monitor state of two mouse buttons
+    if (b != b_old)
+    {
+        // check if mouse buttons are supposed to be treated like keys
+        if (ikbd.state & IKBD_STATE_MOUSE_BUTTON_AS_KEY)
+        {
+            // Mouse buttons act like keys (LEFT=0x74 & RIGHT=0x75)

-			// handle left mouse button
-			if((b ^ b_old) & 1) ikbd_keyboard(0x74 | ((b&1)?0x00:0x80));
-			// handle right mouse button
-			if((b ^ b_old) & 2) ikbd_keyboard(0x75 | ((b&2)?0x00:0x80));
-		}
-		b_old = b;
-	}
+            // handle left mouse button
+            if((b ^ b_old) & 1) ikbd_keyboard(0x74 | ((b&1)?0x00:0x80));
+            // handle right mouse button
+            if((b ^ b_old) & 2) ikbd_keyboard(0x75 | ((b&2)?0x00:0x80));
+        }
+        b_old = b;
+    }

 #if 0
-	if(ikbd.state & IKBD_STATE_MOUSE_BUTTON_AS_KEY)
-	{
-		b = 0;
-		// if mouse position is 0/0 quit here
-		if(!x && !y) return;
-	}
+    if(ikbd.state & IKBD_STATE_MOUSE_BUTTON_AS_KEY)
+    {
+        b = 0;
+        // if mouse position is 0/0 quit here
+        if(!x && !y) return;
+    }
 #endif

-	if (ikbd.state & IKBD_STATE_MOUSE_ABSOLUTE)
-	{
-	}
-	else
-	{
-		// atari has mouse button bits swapped
-		enqueue(0xf8|((b&1)?2:0)|((b&2)?1:0));
-		enqueue(x);
-		enqueue((ikbd.state & IKBD_STATE_MOUSE_Y_BOTTOM)?-y:y);
-	}
+    if (ikbd.state & IKBD_STATE_MOUSE_ABSOLUTE)
+    {
+    }
+    else
+    {
+        // atari has mouse button bits swapped
+        enqueue(0xf8|((b&1)?2:0)|((b&2)?1:0));
+        enqueue(x);
+        enqueue((ikbd.state & IKBD_STATE_MOUSE_Y_BOTTOM)?-y:y);
+    }
 }

--- a/mcf5474.gdb
+++ b/mcf5474.gdb
@@ -67,5 +67,5 @@ end

 tr
 ib
-add-symbol-file ../emutos/emutos2.img 0xe00000
-load firebee/ram.elf
+#add-symbol-file ../emutos/emutos2.img 0xe00000
+#load firebee/ram.elf
--- a/memory_map.txt
+++ b/memory_map.txt
@@ -0,0 +1,8 @@
+Firebee memory map
+==================
+
+		Virt. Start	Virt. End	Phys. Start	Phys. End
+ST-RAM		0x00000000	0x00dfffff	0x60000000	0x60dfffff
+TOS		0x00e00000	0x00efffff	0x00e00000	0x00efffff
+ST I/O area	0x00f00000	0x01000000	0xfff00000	0xffffffff
+TT-RAM		0x01000000	0x20ffffff	0x00000000	0x1fffffff
--- a/net/am79c874.c
+++ b/net/am79c874.c
@@ -32,7 +32,7 @@
 * This function sets up the Auto-Negotiate Advertisement register
 * within the PHY and then forces the PHY to auto-negotiate for
 * it's settings.
- * 
+ *
 * Params:
 *  fec_ch      FEC channel
 *  phy_addr    Address of the PHY.
@@ -45,80 +45,80 @@
 */
 int am79c874_init(uint8_t fec_ch, uint8_t phy_addr, uint8_t speed, uint8_t duplex)
 {
-	int timeout;
-	uint16_t settings;
-	if (speed); /* to do */
-	if (duplex); /* to do */
-	
-	/* Initialize the MII interface */
-	fec_mii_init(fec_ch, SYSCLK / 1000);
-	dbg("%s: PHY reset\r\n", __FUNCTION__);
-	
-	/* Reset the PHY */
-	if (!fec_mii_write(fec_ch, phy_addr, MII_AM79C874_CR, MII_AM79C874_CR_RESET))
-		return 0;
+    int timeout;
+    uint16_t settings;
+    if (speed); /* to do */
+    if (duplex); /* to do */

-	/* Wait for the PHY to reset */
-	for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
-	{
-		fec_mii_read(fec_ch, phy_addr, MII_AM79C874_CR, &settings);
-		if (!(settings & MII_AM79C874_CR_RESET))
-			break;
-	}
+    /* Initialize the MII interface */
+    fec_mii_init(fec_ch, SYSCLK / 1000);
+    dbg("%s: PHY reset\r\n", __FUNCTION__);

-	if (timeout >= FEC_MII_TIMEOUT)
-	{
-		dbg("%s: PHY reset failed\r\n", __FUNCTION__);
-		return 0;
-	};
-	dbg("%s: PHY reset OK\r\n", __FUNCTION__);
-	dbg("%s: PHY Enable Auto-Negotiation\r\n", __FUNCTION__);
+    /* Reset the PHY */
+    if (!fec_mii_write(fec_ch, phy_addr, MII_AM79C874_CR, MII_AM79C874_CR_RESET))
+        return 0;

-	/* Enable Auto-Negotiation */
-	if (!fec_mii_write(fec_ch, phy_addr, MII_AM79C874_CR, MII_AM79C874_CR_AUTON | MII_AM79C874_CR_RST_NEG))
-		return 0;
-		
-	dbg("%s:PHY Wait for auto-negotiation to complete\r\n", __FUNCTION__);
+    /* Wait for the PHY to reset */
+    for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
+    {
+        fec_mii_read(fec_ch, phy_addr, MII_AM79C874_CR, &settings);
+        if (!(settings & MII_AM79C874_CR_RESET))
+            break;
+    }

-	/* Wait for auto-negotiation to complete */
-	for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
-	{
-		settings = 0;
-		fec_mii_read(fec_ch, phy_addr, MII_AM79C874_SR, &settings);
-		if ((settings & AUTONEGLINK) == AUTONEGLINK)
-			break;
-	}
+    if (timeout >= FEC_MII_TIMEOUT)
+    {
+        dbg("%s: PHY reset failed\r\n", __FUNCTION__);
+        return 0;
+    };
+    dbg("%s: PHY reset OK\r\n", __FUNCTION__);
+    dbg("%s: PHY Enable Auto-Negotiation\r\n", __FUNCTION__);

-	if (timeout >= FEC_MII_TIMEOUT)
-	{
-		dbg("%s: Auto-negotiation failed (timeout). Set default mode (100Mbps, full duplex)\r\n", __FUNCTION__);
+    /* Enable Auto-Negotiation */
+    if (!fec_mii_write(fec_ch, phy_addr, MII_AM79C874_CR, MII_AM79C874_CR_AUTON | MII_AM79C874_CR_RST_NEG))
+        return 0;

-		/* Set the default mode (Full duplex, 100 Mbps) */
-		if (!fec_mii_write(fec_ch, phy_addr, MII_AM79C874_CR, MII_AM79C874_CR_100MB | MII_AM79C874_CR_DPLX))
-		{
-			dbg("%s: forced setting 100Mbps/full failed.\r\n", __FUNCTION__);
-			return 0;
-		}
-	}
+    dbg("%s:PHY Wait for auto-negotiation to complete\r\n", __FUNCTION__);
+
+    /* Wait for auto-negotiation to complete */
+    for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
+    {
+        settings = 0;
+        fec_mii_read(fec_ch, phy_addr, MII_AM79C874_SR, &settings);
+        if ((settings & AUTONEGLINK) == AUTONEGLINK)
+            break;
+    }
+
+    if (timeout >= FEC_MII_TIMEOUT)
+    {
+        dbg("%s: Auto-negotiation failed (timeout). Set default mode (100Mbps, full duplex)\r\n", __FUNCTION__);
+
+        /* Set the default mode (Full duplex, 100 Mbps) */
+        if (!fec_mii_write(fec_ch, phy_addr, MII_AM79C874_CR, MII_AM79C874_CR_100MB | MII_AM79C874_CR_DPLX))
+        {
+            dbg("%s: forced setting 100Mbps/full failed.\r\n", __FUNCTION__);
+            return 0;
+        }
+    }

 #ifdef DBG_AM79
-	settings = 0;
+    settings = 0;

-	fec_mii_read(fec_ch, phy_addr, MII_AM79C874_DR, &settings);
+    fec_mii_read(fec_ch, phy_addr, MII_AM79C874_DR, &settings);

-	dbg("%s: PHY Mode:\r\n", __FUNCTION__);	
-	if (settings & MII_AM79C874_DR_DATA_RATE)
-		dbg("%s: 100Mbps", __FUNCTION__);
-	else
-		dbg("%s: 10Mbps ", __FUNCTION__);
+    dbg("%s: PHY Mode:\r\n", __FUNCTION__);
+    if (settings & MII_AM79C874_DR_DATA_RATE)
+        dbg("%s: 100Mbps", __FUNCTION__);
+    else
+        dbg("%s: 10Mbps ", __FUNCTION__);

-	if (settings & MII_AM79C874_DR_DPLX)
-		dbg("%s: Full-duplex\r\n", __FUNCTION__);
-	else
-		dbg("%s: Half-duplex\r\n", __FUNCTION__);
+    if (settings & MII_AM79C874_DR_DPLX)
+        dbg("%s: Full-duplex\r\n", __FUNCTION__);
+    else
+        dbg("%s: Half-duplex\r\n", __FUNCTION__);

-	dbg("%s:PHY auto-negotiation complete\r\n", __FUNCTION__);
+    dbg("%s:PHY auto-negotiation complete\r\n", __FUNCTION__);
 #endif /* DBG_AM79 */

-	return 1;
+    return 1;
 }
--- a/net/bcm5222.c
+++ b/net/bcm5222.c
@@ -37,7 +37,7 @@
 * This function sets up the Auto-Negotiate Advertisement register
 * within the PHY and then forces the PHY to auto-negotiate for
 * it's settings.
- * 
+ *
 * Params:
 *  fec_ch      FEC channel
 *  phy_addr    Address of the PHY.
@@ -50,133 +50,133 @@
 */
 int bcm5222_init(uint8_t fec_ch, uint8_t phy_addr, uint8_t speed, uint8_t duplex)
 {
-	int timeout;
-	uint16_t settings;
+    int timeout;
+    uint16_t settings;

-	/* Initialize the MII interface */
-	fec_mii_init(fec_ch, SYSCLK / 1000);
+    /* Initialize the MII interface */
+    fec_mii_init(fec_ch, SYSCLK / 1000);
    dbg("PHY reset\r\n");

-	/* Reset the PHY */
-	if (!fec_mii_write(fec_ch, phy_addr, BCM5222_CTRL, BCM5222_CTRL_RESET | BCM5222_CTRL_ANE))
-		return 0;
+    /* Reset the PHY */
+    if (!fec_mii_write(fec_ch, phy_addr, BCM5222_CTRL, BCM5222_CTRL_RESET | BCM5222_CTRL_ANE))
+        return 0;

-	/* Wait for the PHY to reset */
-	for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
-	{
-		fec_mii_read(fec_ch, phy_addr, BCM5222_CTRL, &settings);
-		if (!(settings & BCM5222_CTRL_RESET))
-			break;
-	}
-	if(timeout >= FEC_MII_TIMEOUT)
-		return 0;
+    /* Wait for the PHY to reset */
+    for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
+    {
+        fec_mii_read(fec_ch, phy_addr, BCM5222_CTRL, &settings);
+        if (!(settings & BCM5222_CTRL_RESET))
+            break;
+    }
+    if(timeout >= FEC_MII_TIMEOUT)
+        return 0;

    dbg("PHY reset OK\r\n");

-	settings = (BCM5222_AN_ADV_NEXT_PAGE | BCM5222_AN_ADV_PAUSE);
+    settings = (BCM5222_AN_ADV_NEXT_PAGE | BCM5222_AN_ADV_PAUSE);

-	if (speed == FEC_MII_10BASE_T)
-		settings |= (uint16_t)((duplex == FEC_MII_FULL_DUPLEX) 
-				? (BCM5222_AN_ADV_10BT_FDX | BCM5222_AN_ADV_10BT) 
-				: BCM5222_AN_ADV_10BT);
-	else /* (speed == FEC_MII_100BASE_TX) */
-		settings = (uint16_t)((duplex == FEC_MII_FULL_DUPLEX)  
-				? (BCM5222_AN_ADV_100BTX_FDX | BCM5222_AN_ADV_100BTX
-					| BCM5222_AN_ADV_10BT_FDX | BCM5222_AN_ADV_10BT) 
-				: (BCM5222_AN_ADV_100BTX | BCM5222_AN_ADV_10BT));
+    if (speed == FEC_MII_10BASE_T)
+        settings |= (uint16_t)((duplex == FEC_MII_FULL_DUPLEX)
+                               ? (BCM5222_AN_ADV_10BT_FDX | BCM5222_AN_ADV_10BT)
+                               : BCM5222_AN_ADV_10BT);
+    else /* (speed == FEC_MII_100BASE_TX) */
+        settings = (uint16_t)((duplex == FEC_MII_FULL_DUPLEX)
+                              ? (BCM5222_AN_ADV_100BTX_FDX | BCM5222_AN_ADV_100BTX
+                                 | BCM5222_AN_ADV_10BT_FDX | BCM5222_AN_ADV_10BT)
+                              : (BCM5222_AN_ADV_100BTX | BCM5222_AN_ADV_10BT));

-	/* Set the Auto-Negotiation Advertisement Register */
-	if (!fec_mii_write(fec_ch, phy_addr, BCM5222_AN_ADV, settings))
-		return 0;
+    /* Set the Auto-Negotiation Advertisement Register */
+    if (!fec_mii_write(fec_ch, phy_addr, BCM5222_AN_ADV, settings))
+        return 0;

    dbg("PHY Enable Auto-Negotiation\r\n");

-	/* Enable Auto-Negotiation */
-	if (!fec_mii_write(fec_ch, phy_addr, BCM5222_CTRL, (BCM5222_CTRL_ANE | BCM5222_CTRL_RESTART_AN)))
-		return 0;
+    /* Enable Auto-Negotiation */
+    if (!fec_mii_write(fec_ch, phy_addr, BCM5222_CTRL, (BCM5222_CTRL_ANE | BCM5222_CTRL_RESTART_AN)))
+        return 0;

    dbg("PHY Wait for auto-negotiation to complete\r\n");

-	/* Wait for auto-negotiation to complete */
-	for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
-	{
-		if (!fec_mii_read(fec_ch, phy_addr, BCM5222_STAT, &settings))
-			return 0;
-		if (settings & BCM5222_STAT_AN_COMPLETE)
-			break;
-	}
+    /* Wait for auto-negotiation to complete */
+    for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
+    {
+        if (!fec_mii_read(fec_ch, phy_addr, BCM5222_STAT, &settings))
+            return 0;
+        if (settings & BCM5222_STAT_AN_COMPLETE)
+            break;
+    }

-	if (timeout < FEC_MII_TIMEOUT)
-	{
+    if (timeout < FEC_MII_TIMEOUT)
+    {
        dbg("PHY auto-negociation complete\r\n");

-		/* Read Auxiliary Control/Status Register */
-		if (!fec_mii_read(fec_ch, phy_addr, BCM5222_ACSR, &settings))
-			return 0;
-	}
-	else
-	{
+        /* Read Auxiliary Control/Status Register */
+        if (!fec_mii_read(fec_ch, phy_addr, BCM5222_ACSR, &settings))
+            return 0;
+    }
+    else
+    {
        dbg("auto negotiation failed, PHY Set the default mode\r\n");

-		/* Set the default mode (Full duplex, 100 Mbps) */
-		if (!fec_mii_write(fec_ch, phy_addr, BCM5222_ACSR, settings = (BCM5222_ACSR_100BTX | BCM5222_ACSR_FDX)))
-			return 0;
-	}
+        /* Set the default mode (Full duplex, 100 Mbps) */
+        if (!fec_mii_write(fec_ch, phy_addr, BCM5222_ACSR, settings = (BCM5222_ACSR_100BTX | BCM5222_ACSR_FDX)))
+            return 0;
+    }

-	/* Set the proper duplex in the FEC now that we have auto-negotiated */
-	if (settings & BCM5222_ACSR_FDX)
-		fec_duplex(fec_ch, FEC_MII_FULL_DUPLEX);
-	else
-		fec_duplex(fec_ch, FEC_MII_HALF_DUPLEX);
+    /* Set the proper duplex in the FEC now that we have auto-negotiated */
+    if (settings & BCM5222_ACSR_FDX)
+        fec_duplex(fec_ch, FEC_MII_FULL_DUPLEX);
+    else
+        fec_duplex(fec_ch, FEC_MII_HALF_DUPLEX);

    dbg("PHY Mode: ");

-	if (settings & BCM5222_ACSR_100BTX)
+    if (settings & BCM5222_ACSR_100BTX)
        dbg("100Mbps\r\n");
-	else
+    else
        dbg("10Mbps\r\n");

-	if (settings & BCM5222_ACSR_FDX)
+    if (settings & BCM5222_ACSR_FDX)
        dbg("Full-duplex\r\n");
-	else
+    else
        dbg("Half-duplex\r\n");

-	return 1;
+    return 1;
 }

 void bcm5222_get_reg(uint16_t* status0, uint16_t* status1)
 {
-	fec_mii_read(0, 0x00, 0x00000000, &status0[0]); 
-	fec_mii_read(0, 0x00, 0x00000001, &status0[1]); 
-	fec_mii_read(0, 0x00, 0x00000004, &status0[4]); 
-	fec_mii_read(0, 0x00, 0x00000005, &status0[5]); 
-	fec_mii_read(0, 0x00, 0x00000006, &status0[6]); 
-	fec_mii_read(0, 0x00, 0x00000007, &status0[7]); 
-	fec_mii_read(0, 0x00, 0x00000008, &status0[8]); 
-	fec_mii_read(0, 0x00, 0x00000010, &status0[16]);
-	fec_mii_read(0, 0x00, 0x00000011, &status0[17]);
-	fec_mii_read(0, 0x00, 0x00000012, &status0[18]);
-	fec_mii_read(0, 0x00, 0x00000013, &status0[19]);
-	fec_mii_read(0, 0x00, 0x00000018, &status0[24]);
-	fec_mii_read(0, 0x00, 0x00000019, &status0[25]);
-	fec_mii_read(0, 0x00, 0x0000001B, &status0[27]);
-	fec_mii_read(0, 0x00, 0x0000001C, &status0[28]);
-	fec_mii_read(0, 0x00, 0x0000001E, &status0[30]);
-	fec_mii_read(0, 0x01, 0x00000000, &status1[0]);
-	fec_mii_read(0, 0x01, 0x00000001, &status1[1]);
-	fec_mii_read(0, 0x01, 0x00000004, &status1[4]);
-	fec_mii_read(0, 0x01, 0x00000005, &status1[5]);
-	fec_mii_read(0, 0x01, 0x00000006, &status1[6]);
-	fec_mii_read(0, 0x01, 0x00000007, &status1[7]);
-	fec_mii_read(0, 0x01, 0x00000008, &status1[8]);
-	fec_mii_read(0, 0x01, 0x00000010, &status1[16]);
-	fec_mii_read(0, 0x01, 0x00000011, &status1[17]);
-	fec_mii_read(0, 0x01, 0x00000012, &status1[18]);
-	fec_mii_read(0, 0x01, 0x00000013, &status1[19]);
-	fec_mii_read(0, 0x01, 0x00000018, &status1[24]);
-	fec_mii_read(0, 0x01, 0x00000019, &status1[25]);
-	fec_mii_read(0, 0x01, 0x0000001B, &status1[27]);
-	fec_mii_read(0, 0x01, 0x0000001C, &status1[28]);
-	fec_mii_read(0, 0x01, 0x0000001E, &status1[30]);
+    fec_mii_read(0, 0x00, 0x00000000, &status0[0]);
+    fec_mii_read(0, 0x00, 0x00000001, &status0[1]);
+    fec_mii_read(0, 0x00, 0x00000004, &status0[4]);
+    fec_mii_read(0, 0x00, 0x00000005, &status0[5]);
+    fec_mii_read(0, 0x00, 0x00000006, &status0[6]);
+    fec_mii_read(0, 0x00, 0x00000007, &status0[7]);
+    fec_mii_read(0, 0x00, 0x00000008, &status0[8]);
+    fec_mii_read(0, 0x00, 0x00000010, &status0[16]);
+    fec_mii_read(0, 0x00, 0x00000011, &status0[17]);
+    fec_mii_read(0, 0x00, 0x00000012, &status0[18]);
+    fec_mii_read(0, 0x00, 0x00000013, &status0[19]);
+    fec_mii_read(0, 0x00, 0x00000018, &status0[24]);
+    fec_mii_read(0, 0x00, 0x00000019, &status0[25]);
+    fec_mii_read(0, 0x00, 0x0000001B, &status0[27]);
+    fec_mii_read(0, 0x00, 0x0000001C, &status0[28]);
+    fec_mii_read(0, 0x00, 0x0000001E, &status0[30]);
+    fec_mii_read(0, 0x01, 0x00000000, &status1[0]);
+    fec_mii_read(0, 0x01, 0x00000001, &status1[1]);
+    fec_mii_read(0, 0x01, 0x00000004, &status1[4]);
+    fec_mii_read(0, 0x01, 0x00000005, &status1[5]);
+    fec_mii_read(0, 0x01, 0x00000006, &status1[6]);
+    fec_mii_read(0, 0x01, 0x00000007, &status1[7]);
+    fec_mii_read(0, 0x01, 0x00000008, &status1[8]);
+    fec_mii_read(0, 0x01, 0x00000010, &status1[16]);
+    fec_mii_read(0, 0x01, 0x00000011, &status1[17]);
+    fec_mii_read(0, 0x01, 0x00000012, &status1[18]);
+    fec_mii_read(0, 0x01, 0x00000013, &status1[19]);
+    fec_mii_read(0, 0x01, 0x00000018, &status1[24]);
+    fec_mii_read(0, 0x01, 0x00000019, &status1[25]);
+    fec_mii_read(0, 0x01, 0x0000001B, &status1[27]);
+    fec_mii_read(0, 0x01, 0x0000001C, &status1[28]);
+    fec_mii_read(0, 0x01, 0x0000001E, &status1[30]);
 }

--- a/net/bootp.c
+++ b/net/bootp.c
@@ -18,101 +18,101 @@
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DBG_BOOTP */

-#define TIMER_NETWORK 3			/* defines GPT3 as timer for this function */
+#define TIMER_NETWORK 3         /* defines GPT3 as timer for this function */

 static struct bootp_connection connection;
-#define XID			0x1234		/* this is arbitrary */
-#define	MAX_TRIES	5			/* since UDP can fail */
+#define XID         0x1234      /* this is arbitrary */
+#define MAX_TRIES   5           /* since UDP can fail */

 void bootp_request(NIF *nif, uint8_t *pa)
 {
-	/*
-	 * This function broadcasts a BOOTP request for the protocol
-	 * address "pa"
-	 */
-	uint8_t *addr;
-	IP_ADDR broadcast = {255, 255, 255, 255};
-	NBUF *nbuf;
-	struct bootp_packet *p;
-	int i, result;
+    /*
+     * This function broadcasts a BOOTP request for the protocol
+     * address "pa"
+     */
+    uint8_t *addr;
+    IP_ADDR broadcast = {255, 255, 255, 255};
+    NBUF *nbuf;
+    struct bootp_packet *p;
+    int i, result;

-	nbuf = nbuf_alloc();
-	if (nbuf == NULL)
-	{
-		xprintf("%s: couldn't allocate Tx buffer\r\n", __FUNCTION__);
-		return;
-	}
+    nbuf = nbuf_alloc();
+    if (nbuf == NULL)
+    {
+        xprintf("%s: couldn't allocate Tx buffer\r\n", __FUNCTION__);
+        return;
+    }

-	p = (struct bootp_packet *) &nbuf->data[BOOTP_HDR_OFFSET];
+    p = (struct bootp_packet *) &nbuf->data[BOOTP_HDR_OFFSET];

-	/* Build the BOOTP request packet */
-	p->type = BOOTP_TYPE_BOOTREQUEST;
-	p->htype = BOOTP_HTYPE_ETHERNET;
-	p->hlen = BOOTP_HLEN_ETHERNET;
-	p->hops = 0;
-	p->xid = XID;
-	p->secs = 1;
-	p->flags = BOOTP_FLAGS_BROADCAST;
-	p->cl_addr = 0x0;
-	p->yi_addr = 0x0;
-	p->gi_addr = 0x0;
+    /* Build the BOOTP request packet */
+    p->type = BOOTP_TYPE_BOOTREQUEST;
+    p->htype = BOOTP_HTYPE_ETHERNET;
+    p->hlen = BOOTP_HLEN_ETHERNET;
+    p->hops = 0;
+    p->xid = XID;
+    p->secs = 1;
+    p->flags = BOOTP_FLAGS_BROADCAST;
+    p->cl_addr = 0x0;
+    p->yi_addr = 0x0;
+    p->gi_addr = 0x0;

-	connection.nif = nif;
-	addr = &nif->hwa[0];
+    connection.nif = nif;
+    addr = &nif->hwa[0];

-	for (i = 0; i < 6; i++)
-		p->ch_addr[i] = addr[i];
+    for (i = 0; i < 6; i++)
+        p->ch_addr[i] = addr[i];

-	nbuf->length = BOOTP_PACKET_LEN;
+    nbuf->length = BOOTP_PACKET_LEN;

-	/* setup reply handler */
-	udp_bind_port(BOOTP_CLIENT_PORT, bootp_handler);
+    /* setup reply handler */
+    udp_bind_port(BOOTP_CLIENT_PORT, bootp_handler);

-	for (i = 0; i < MAX_TRIES; i++)
-	{
-		/* Send the BOOTP request */
-		result = udp_send(connection.nif, broadcast, BOOTP_CLIENT_PORT,
-							BOOTP_SERVER_PORT, nbuf);
-		dbg("sent bootp request\r\n");
-		if (result == true)
-			break;
-	}
+    for (i = 0; i < MAX_TRIES; i++)
+    {
+        /* Send the BOOTP request */
+        result = udp_send(connection.nif, broadcast, BOOTP_CLIENT_PORT,
+                            BOOTP_SERVER_PORT, nbuf);
+        dbg("sent bootp request\r\n");
+        if (result == true)
+            break;
+    }

-	/* release handler */
-	udp_free_port(BOOTP_CLIENT_PORT);
+    /* release handler */
+    udp_free_port(BOOTP_CLIENT_PORT);

-	if (result == 0)
-		nbuf_free(nbuf);
+    if (result == 0)
+        nbuf_free(nbuf);
 }

 void bootp_handler(NIF *nif, NBUF *nbuf)
 {
-	/* 
-	 * BOOTP protocol handler 
-	 */
-	uint8_t *addr;
-	struct bootp_packet *rx_p;
-	udp_frame_hdr *udpframe;
+    /* 
+     * BOOTP protocol handler 
+     */
+    struct bootp_packet *rx_p;
+    udp_frame_hdr *udpframe;

+    (void) udpframe;    /* FIXME: just to avoid compiler warning */
    dbg("\r\n");

-	rx_p = (struct bootp_packet *) &nbuf->data[nbuf->offset];
-	udpframe = (udp_frame_hdr *) &nbuf->data[nbuf->offset - UDP_HDR_SIZE];
+    rx_p = (struct bootp_packet *) &nbuf->data[nbuf->offset];
+    udpframe = (udp_frame_hdr *) &nbuf->data[nbuf->offset - UDP_HDR_SIZE];

    /*
     * check packet if it is valid and if it is really intended for us
     */

-	if (rx_p->type == BOOTP_TYPE_BOOTREPLY && rx_p->xid == XID)
-	{
-		dbg("received bootp reply\r\n");
-		/* seems to be valid */
-	
-	}
-	else
-	{
+    if (rx_p->type == BOOTP_TYPE_BOOTREPLY && rx_p->xid == XID)
+    {
+        dbg("received bootp reply\r\n");
+        /* seems to be valid */
+    
+    }
+    else
+    {
        dbg("received invalid bootp reply\r\n");
-		/* not valid */
-		return;
-	}
+        /* not valid */
+        return;
+    }
 }
--- a/net/nbuf.c
+++ b/net/nbuf.c
@@ -39,46 +39,46 @@ uint8_t *unaligned_buffers[NBUF_MAX];
 */
 int nbuf_init(void)
 {
-	int i;
-	NBUF *nbuf;
+    int i;
+    NBUF *nbuf;

-	for (i = 0; i < NBUF_MAXQ; ++i)
-	{
-		/* Initialize all the queues */
-		queue_init(&nbuf_queue[i]);
-	}
+    for (i = 0; i < NBUF_MAXQ; ++i)
+    {
+        /* Initialize all the queues */
+        queue_init(&nbuf_queue[i]);
+    }

-	dbg("Creating %d net buffers of %d bytes\r\n", NBUF_MAX, NBUF_SZ);
+    dbg("Creating %d net buffers of %d bytes\r\n", NBUF_MAX, NBUF_SZ);

-	for (i = 0; i < NBUF_MAX; ++i)
-	{
-		/* Allocate memory for the network buffer structure */
-		nbuf = (NBUF *) driver_mem_alloc(sizeof(NBUF));
-		if (!nbuf)
-		{
-			xprintf("failed to allocate nbuf\r\n");
-			return 1;
-		}
+    for (i = 0; i < NBUF_MAX; ++i)
+    {
+        /* Allocate memory for the network buffer structure */
+        nbuf = (NBUF *) driver_mem_alloc(sizeof(NBUF));
+        if (!nbuf)
+        {
+            xprintf("failed to allocate nbuf\r\n");
+            return 1;
+        }

-		/* Allocate memory for the actual data */
-		unaligned_buffers[i] = driver_mem_alloc(NBUF_SZ + 16);
-		nbuf->data = (uint8_t *)((uint32_t)(unaligned_buffers[i] + 15) & 0xFFFFFFF0);
-		if (!nbuf->data)
-		{
-			return 1;
-		}
+        /* Allocate memory for the actual data */
+        unaligned_buffers[i] = driver_mem_alloc(NBUF_SZ + 16);
+        nbuf->data = (uint8_t *)((uint32_t)(unaligned_buffers[i] + 15) & 0xFFFFFFF0);
+        if (!nbuf->data)
+        {
+            return 1;
+        }

-		/* Initialize the network buffer */
-		nbuf->offset = 0;
-		nbuf->length = 0;
+        /* Initialize the network buffer */
+        nbuf->offset = 0;
+        nbuf->length = 0;

-		/* Add the network buffer to the free list */
-		queue_add(&nbuf_queue[NBUF_FREE], (QNODE *)nbuf);
-	}
+        /* Add the network buffer to the free list */
+        queue_add(&nbuf_queue[NBUF_FREE], (QNODE *)nbuf);
+    }

-	dbg("NBUF allocation complete\r\n");
+    dbg("NBUF allocation complete\r\n");

-	return 0;
+    return 0;
 }

 /*
@@ -86,23 +86,23 @@ int nbuf_init(void)
 */
 void nbuf_flush(void)
 {
-	NBUF *nbuf;
-	int i;
-	int level = set_ipl(7);
-	int n = 0;
+    NBUF *nbuf;
+    int i;
+    int level = set_ipl(7);
+    int n = 0;

-	for (i = 0; i < NBUF_MAX; ++i)
-		driver_mem_free((uint8_t *) unaligned_buffers[i]);
+    for (i = 0; i < NBUF_MAX; ++i)
+        driver_mem_free((uint8_t *) unaligned_buffers[i]);

-	for (i = 0; i < NBUF_MAXQ; ++i)
-	{
-		while ((nbuf = (NBUF *) queue_remove(&nbuf_queue[i])) != NULL)
-		{
-			driver_mem_free(nbuf);
-			++n;
-		}
-	}
-	set_ipl(level);
+    for (i = 0; i < NBUF_MAXQ; ++i)
+    {
+        while ((nbuf = (NBUF *) queue_remove(&nbuf_queue[i])) != NULL)
+        {
+            driver_mem_free(nbuf);
+            ++n;
+        }
+    }
+    set_ipl(level);
 }

 /*
@@ -114,13 +114,13 @@ void nbuf_flush(void)
 */
 NBUF *nbuf_alloc(void)
 {
-	NBUF *nbuf;
-	int level = set_ipl(7);
+    NBUF *nbuf;
+    int level = set_ipl(7);

-	nbuf = (NBUF *) queue_remove(&nbuf_queue[NBUF_FREE]);
-	set_ipl(level);
+    nbuf = (NBUF *) queue_remove(&nbuf_queue[NBUF_FREE]);
+    set_ipl(level);

-	return nbuf;
+    return nbuf;
 }

 /*
@@ -131,13 +131,13 @@ NBUF *nbuf_alloc(void)
 */
 void nbuf_free(NBUF *nbuf)
 {
-	int level = set_ipl(7);
+    int level = set_ipl(7);

-	nbuf->offset = 0;
-	nbuf->length = NBUF_SZ;
-	queue_add(&nbuf_queue[NBUF_FREE],(QNODE *) nbuf);
+    nbuf->offset = 0;
+    nbuf->length = NBUF_SZ;
+    queue_add(&nbuf_queue[NBUF_FREE],(QNODE *) nbuf);

-	set_ipl(level);
+    set_ipl(level);
 }

 /*
@@ -148,13 +148,13 @@ void nbuf_free(NBUF *nbuf)
 */
 NBUF *nbuf_remove(int q)
 {
-	NBUF *nbuf;
-	int level = set_ipl(7);
+    NBUF *nbuf;
+    int level = set_ipl(7);

-	nbuf = (NBUF *) queue_remove(&nbuf_queue[q]);
-	set_ipl(level);
+    nbuf = (NBUF *) queue_remove(&nbuf_queue[q]);
+    set_ipl(level);

-	return nbuf;
+    return nbuf;
 }

 /*
@@ -165,10 +165,10 @@ NBUF *nbuf_remove(int q)
 */
 void nbuf_add(int q, NBUF *nbuf)
 {
-	int level = set_ipl(7);
+    int level = set_ipl(7);

-	queue_add(&nbuf_queue[q], (QNODE *) nbuf);
-	set_ipl(level);
+    queue_add(&nbuf_queue[q], (QNODE *) nbuf);
+    set_ipl(level);
 }

 /*
@@ -176,16 +176,16 @@ void nbuf_add(int q, NBUF *nbuf)
 */
 void nbuf_reset(void)
 {
-	NBUF *nbuf;
-	int i;
-	int level = set_ipl(7);
+    NBUF *nbuf;
+    int i;
+    int level = set_ipl(7);

-	for (i = 1; i < NBUF_MAXQ; ++i)
-	{
-		while ((nbuf = nbuf_remove(i)) != NULL)
-			nbuf_free(nbuf);
-	}
-	set_ipl(level);
+    for (i = 1; i < NBUF_MAXQ; ++i)
+    {
+        while ((nbuf = nbuf_remove(i)) != NULL)
+            nbuf_free(nbuf);
+    }
+    set_ipl(level);
 }

 /*
@@ -194,31 +194,31 @@ void nbuf_reset(void)
 void nbuf_debug_dump(void)
 {
 #ifdef DBG_NBUF
-	NBUF *nbuf;
-	int i;
-	int j;
-	int level;
+    NBUF *nbuf;
+    int i;
+    int j;
+    int level;

-	level = set_ipl(7);
+    level = set_ipl(7);

-	for (i = 0; i < NBUF_MAXQ; ++i)
-	{
-		dbg("\r\n\r\nQueue #%d\r\n\r\n", i);
-		dbg("\tBuffer Location\tOffset\tLength\r\n");
-		dbg("--------------------------------------\r\n");
-		j = 0;
-		nbuf = (NBUF *) queue_peek(&nbuf_queue[i]);
+    for (i = 0; i < NBUF_MAXQ; ++i)
+    {
+        dbg("\r\n\r\nQueue #%d\r\n\r\n", i);
+        dbg("\tBuffer Location\tOffset\tLength\r\n");
+        dbg("--------------------------------------\r\n");
+        j = 0;
+        nbuf = (NBUF *) queue_peek(&nbuf_queue[i]);

-		while (nbuf != NULL)
-		{
-			dbg("%d\t0x%08x\t0x%04x\t0x%04x\r\n", j++, nbuf->data,
-					nbuf->offset,
-					nbuf->length);
-			nbuf = (NBUF *) nbuf->node.next;
-		}
-	}
-	dbg("\r\n");
+        while (nbuf != NULL)
+        {
+            dbg("%d\t0x%08x\t0x%04x\t0x%04x\r\n", j++, nbuf->data,
+                nbuf->offset,
+                nbuf->length);
+            nbuf = (NBUF *) nbuf->node.next;
+        }
+    }
+    dbg("\r\n");

-	set_ipl(level);
+    set_ipl(level);
 #endif /* DBG_NBUF */
 }
--- a/net/nif.c
+++ b/net/nif.c
@@ -20,111 +20,111 @@

 int nif_protocol_exist(NIF *nif, uint16_t protocol)
 {
-	/*
-	 * This function searches the list of supported protocols
-	 * on the particular NIF and if a protocol handler exists,
-	 * true is returned.  This function is useful for network cards
-	 * that needn't read in the entire frame but can discard frames
-	 * arbitrarily.
-	 */
-	int index;
+    /*
+     * This function searches the list of supported protocols
+     * on the particular NIF and if a protocol handler exists,
+     * true is returned.  This function is useful for network cards
+     * that needn't read in the entire frame but can discard frames
+     * arbitrarily.
+     */
+    int index;

-	for (index = 0; index < nif->num_protocol; ++index)
-	{
-		if (nif->protocol[index].protocol == protocol)
-		{
-			return true;
-		}
-	}
-	return false;
+    for (index = 0; index < nif->num_protocol; ++index)
+    {
+        if (nif->protocol[index].protocol == protocol)
+        {
+            return true;
+        }
+    }
+    return false;
 }

 void nif_protocol_handler(NIF *nif, uint16_t protocol, NBUF *pNbuf)
 {
-	/*
-	 * This function searches the list of supported protocols
-	 * on the particular NIF and if a protocol handler exists,
-	 * the protocol handler is invoked.  This routine called by
-	 * network device driver after receiving a frame.
-	 */
-	int index;
+    /*
+     * This function searches the list of supported protocols
+     * on the particular NIF and if a protocol handler exists,
+     * the protocol handler is invoked.  This routine called by
+     * network device driver after receiving a frame.
+     */
+    int index;

-	for (index = 0; index < nif->num_protocol; ++index)
-	{
-		if (nif->protocol[index].protocol == protocol)
-		{
-			dbg("call protocol handler for protocol %d at %p\r\n", protocol,
-						nif->protocol[index].handler);
-			nif->protocol[index].handler(nif,pNbuf);
-			return;
-		}
-	}
-	dbg("no protocol handler found for protocol %d\r\n", protocol);
+    for (index = 0; index < nif->num_protocol; ++index)
+    {
+        if (nif->protocol[index].protocol == protocol)
+        {
+            dbg("call protocol handler for protocol %d at %p\r\n", protocol,
+                nif->protocol[index].handler);
+            nif->protocol[index].handler(nif,pNbuf);
+            return;
+        }
+    }
+    dbg("no protocol handler found for protocol %d\r\n", protocol);
 }

 void *nif_get_protocol_info(NIF *nif, uint16_t protocol)
 {
-	/*
-	 * This function searches the list of supported protocols
-	 * on the particular NIF and returns a pointer to the
-	 * config info for 'protocol', otherwise NULL is returned.
-	 */
-	int index;
+    /*
+     * This function searches the list of supported protocols
+     * on the particular NIF and returns a pointer to the
+     * config info for 'protocol', otherwise NULL is returned.
+     */
+    int index;

-	for (index = 0; index < nif->num_protocol; ++index)
-	{
-		if (nif->protocol[index].protocol == protocol)
-			return (void *)nif->protocol[index].info;
-	}
-	return (void *)0;
+    for (index = 0; index < nif->num_protocol; ++index)
+    {
+        if (nif->protocol[index].protocol == protocol)
+            return (void *)nif->protocol[index].info;
+    }
+    return (void *)0;
 }

 int nif_bind_protocol(NIF *nif, uint16_t protocol, void (*handler)(NIF *,NBUF *),
-					void *info)
+                      void *info)
 {
-	/*
-	 * This function registers 'protocol' as a supported
-	 * protocol in 'nif'.
-	 */
-	if (nif->num_protocol < (MAX_SUP_PROTO - 1))
-	{
-		nif->protocol[nif->num_protocol].protocol = protocol;
-		nif->protocol[nif->num_protocol].handler = (void(*)(NIF *, NBUF *)) handler;
-		nif->protocol[nif->num_protocol].info = info;
-		++nif->num_protocol;
+    /*
+     * This function registers 'protocol' as a supported
+     * protocol in 'nif'.
+     */
+    if (nif->num_protocol < (MAX_SUP_PROTO - 1))
+    {
+        nif->protocol[nif->num_protocol].protocol = protocol;
+        nif->protocol[nif->num_protocol].handler = (void(*)(NIF *, NBUF *)) handler;
+        nif->protocol[nif->num_protocol].info = info;
+        ++nif->num_protocol;

-		return true;
-	}
-	return false;
+        return true;
+    }
+    return false;
 }

 NIF *nif_init (NIF *nif)
 {
-	int i;
+    int i;

-	for (i = 0; i < ETH_ADDR_LEN; ++i)
-	{
-		nif->hwa[i] = 0;
-		nif->broadcast[i] = 0xFF;
-	}
+    for (i = 0; i < ETH_ADDR_LEN; ++i)
+    {
+        nif->hwa[i] = 0;
+        nif->broadcast[i] = 0xFF;
+    }

-	for (i = 0; i < MAX_SUP_PROTO; ++i)
-	{
-		nif->protocol[i].protocol = 0;
-		nif->protocol[i].handler = 0;
-		nif->protocol[i].info = 0;
-	}
-	nif->num_protocol = 0;
+    for (i = 0; i < MAX_SUP_PROTO; ++i)
+    {
+        nif->protocol[i].protocol = 0;
+        nif->protocol[i].handler = 0;
+        nif->protocol[i].info = 0;
+    }
+    nif->num_protocol = 0;

-	nif->mtu = 0;
-	nif->ch = 0;
-	nif->send = 0;
+    nif->mtu = 0;
+    nif->ch = 0;
+    nif->send = 0;

-	nif->f_rx = 0;
-	nif->f_tx = 0;
-	nif->f_rx_err = 0;
-	nif->f_tx_err = 0;
-	nif->f_err = 0;
+    nif->f_rx = 0;
+    nif->f_tx = 0;
+    nif->f_rx_err = 0;
+    nif->f_tx_err = 0;
+    nif->f_err = 0;

-	return nif;
+    return nif;
 }
--- a/net/tftp.c
+++ b/net/tftp.c
--- a/nutil/s19header.c
+++ b/nutil/s19header.c
@@ -42,9 +42,9 @@
 #define SREC_COUNT(a) 		(a)[1]							/* length of valid bytes to follow */
 #define SREC_ADDR16(a) 		(256 * (a)[2] + (a)[3])			/* 2 byte address field */
 #define SREC_ADDR24(a)		(0x10000 * (a)[2] + 0x100 *  \
-							(a)[3] + (a)[4])				/* 3 byte address field */
+    (a)[3] + (a)[4])				/* 3 byte address field */
 #define SREC_ADDR32(a) 		(0x1000000 * a[2] + 0x10000 * \
-							a[3] + 0x100 * (a)[4] + (a)[5])	/* 4 byte address field */
+    a[3] + 0x100 * (a)[4] + (a)[5])	/* 4 byte address field */
 #define SREC_DATA16(a)		((uint8_t *)&((a)[4]))			/* address of first byte of data in a record */
 #define SREC_DATA24(a)		((uint8_t *)&((a)[5]))			/* address of first data byte in 24 bit record */
 #define SREC_DATA32(a)		((uint8_t *)&((a)[6]))			/* adress of first byte of a record with 32 bit address field */
@@ -67,13 +67,13 @@
 */
 static uint8_t nibble_to_byte(uint8_t nibble)
 {
-	if ((nibble >= '0') && (nibble <= '9'))
-		return nibble - '0';
-	else if ((nibble >= 'A' && nibble <= 'F'))
-		return 10 + nibble - 'A';
-	else if ((nibble >= 'a' && nibble <= 'f'))
-		return 10 + nibble - 'a';
-	return 0;
+    if ((nibble >= '0') && (nibble <= '9'))
+        return nibble - '0';
+    else if ((nibble >= 'A' && nibble <= 'F'))
+        return 10 + nibble - 'A';
+    else if ((nibble >= 'a' && nibble <= 'f'))
+        return 10 + nibble - 'a';
+    return 0;
 }

 /*
@@ -81,7 +81,7 @@ static uint8_t nibble_to_byte(uint8_t nibble)
 */
 static uint8_t hex_to_byte(uint8_t hex[2])
 {
-	return 16 * (nibble_to_byte(hex[0])) + (nibble_to_byte(hex[1]));
+    return 16 * (nibble_to_byte(hex[0])) + (nibble_to_byte(hex[1]));
 }

 #ifdef _NOT_USED_
@@ -90,7 +90,7 @@ static uint8_t hex_to_byte(uint8_t hex[2])
 */
 static uint16_t hex_to_word(uint8_t hex[4])
 {
-	return 256 * hex_to_byte(&hex[0]) + hex_to_byte(&hex[2]);
+    return 256 * hex_to_byte(&hex[0]) + hex_to_byte(&hex[2]);
 }

 /*
@@ -98,7 +98,7 @@ static uint16_t hex_to_word(uint8_t hex[4])
 */
 static uint32_t hex_to_long(uint8_t hex[8])
 {
-	return 65536 * hex_to_word(&hex[0]) + hex_to_word(&hex[4]);
+    return 65536 * hex_to_word(&hex[0]) + hex_to_word(&hex[4]);
 }
 #endif /* _NOT_USED_ */

@@ -109,46 +109,46 @@ static uint32_t hex_to_long(uint8_t hex[8])
 */
 static uint8_t checksum(uint8_t arr[])
 {
-	int i;
-	uint8_t checksum = SREC_COUNT(arr);
+    int i;
+    uint8_t checksum = SREC_COUNT(arr);

-	for (i = 0; i < SREC_COUNT(arr) - 1; i++)
-	{
-		checksum += arr[i + 2];
-	}
-	return ~checksum;
+    for (i = 0; i < SREC_COUNT(arr) - 1; i++)
+    {
+        checksum += arr[i + 2];
+    }
+    return ~checksum;
 }

 void print_record(uint8_t *arr)
 {
-	switch (SREC_TYPE(arr))
-	{
-		case 0:
-		{
-			printf("type 0x%x ", SREC_TYPE(arr));
-			printf("count 0x%x ", SREC_COUNT(arr));
-			printf("addr 0x%x ", SREC_ADDR16(arr));
-			printf("module %11.11s ", SREC_DATA16(arr));
-			printf("chk 0x%x 0x%x\r\n", SREC_CHECKSUM(arr), checksum(arr));
-		}
-		break;
+    switch (SREC_TYPE(arr))
+    {
+        case 0:
+            {
+                printf("type 0x%x ", SREC_TYPE(arr));
+                printf("count 0x%x ", SREC_COUNT(arr));
+                printf("addr 0x%x ", SREC_ADDR16(arr));
+                printf("module %11.11s ", SREC_DATA16(arr));
+                printf("chk 0x%x 0x%x\r\n", SREC_CHECKSUM(arr), checksum(arr));
+            }
+            break;

-		case 3:
-		case 7:
-		{
-			printf("type 0x%x ", SREC_TYPE(arr));
-			printf("count 0x%x ", SREC_COUNT(arr));
-			printf("addr 0x%x ", SREC_ADDR32(arr));
-			printf("data %02x,%02x,%02x,%02x,... ",
-					SREC_DATA32(arr)[0], SREC_DATA32(arr)[1], SREC_DATA32(arr)[3], SREC_DATA32(arr)[4]);
-			printf("chk 0x%x 0x%x\r\n", SREC_CHECKSUM(arr), checksum(arr));
-		}
-		break;
+        case 3:
+        case 7:
+            {
+                printf("type 0x%x ", SREC_TYPE(arr));
+                printf("count 0x%x ", SREC_COUNT(arr));
+                printf("addr 0x%x ", SREC_ADDR32(arr));
+                printf("data %02x,%02x,%02x,%02x,... ",
+                       SREC_DATA32(arr)[0], SREC_DATA32(arr)[1], SREC_DATA32(arr)[3], SREC_DATA32(arr)[4]);
+                printf("chk 0x%x 0x%x\r\n", SREC_CHECKSUM(arr), checksum(arr));
+            }
+            break;

-		default:
-			printf("unsupported report type %d in print_record\r\n", arr[0]);
-			break;
-	}
+        default:
+            printf("unsupported report type %d in print_record\r\n", arr[0]);
+            break;
+    }
 }

 /*
@@ -156,26 +156,26 @@ void print_record(uint8_t *arr)
 */
 static void line_to_vector(uint8_t *buff, uint8_t *vector)
 {
-	int i;
-	int length;
-	uint8_t *vp = vector;
+    int i;
+    int length;
+    uint8_t *vp = vector;

-	length = hex_to_byte(buff + 2);
+    length = hex_to_byte(buff + 2);

-	buff++;
-	*vp++ = nibble_to_byte(*buff); /* record type. Only one single nibble */
-	buff++;
+    buff++;
+    *vp++ = nibble_to_byte(*buff); /* record type. Only one single nibble */
+    buff++;

-	for (i = 0; i <= length; i++)
-	{
-		*vp++ = hex_to_byte(buff);
-		buff += 2;
-	}
+    for (i = 0; i <= length; i++)
+    {
+        *vp++ = hex_to_byte(buff);
+        buff += 2;
+    }
 }

 static void vector_to_line(uint8_t *vector, uint8_t *buff)
 {
-	sprintf(buff, "S");
+    sprintf(buff, "S");
 }

 /*
@@ -199,157 +199,157 @@ static void vector_to_line(uint8_t *vector, uint8_t *buff)
 */
 int main(int argc, char *argv[])
 {
-	int fres;
-	int set;
-	char *filename = NULL;
-	FILE *file;
-	int ret = OK;
-	int i;
+    int fres;
+    int set;
+    char *filename = NULL;
+    FILE *file;
+    int ret = OK;
+    int i;


-	for (i = 1; i < argc; i++)
-	{
-		if (argv[i][0] == '-')
-		{
-			/* option */
-			if (strcmp(argv[i], "-s") == 0)
-			{
-				set = 1;
-			}
-		}
-		else
-		{
-			filename = argv[i];
-		}
-	}
+    for (i = 1; i < argc; i++)
+    {
+        if (argv[i][0] == '-')
+        {
+            /* option */
+            if (strcmp(argv[i], "-s") == 0)
+            {
+                set = 1;
+            }
+        }
+        else
+        {
+            filename = argv[i];
+        }
+    }

-	if (filename == NULL)
-	{
-		fprintf(stderr, "no filename given\n");
-		exit(1);
-	}
+    if (filename == NULL)
+    {
+        fprintf(stderr, "no filename given\n");
+        exit(1);
+    }

-	if ((file = fopen(filename, "r")) != NULL)
-	{
-		uint8_t line[80];
-		int lineno = 0;
-		int data_records = 0;
-		bool found_block_header = false;
-		bool found_block_end = false;
-		bool found_block_data = false;
+    if ((file = fopen(filename, "r")) != NULL)
+    {
+        uint8_t line[80];
+        int lineno = 0;
+        int data_records = 0;
+        bool found_block_header = false;
+        bool found_block_end = false;
+        bool found_block_data = false;

-		while (ret == OK && (uint8_t *) fgets((char *) line, sizeof(line), file) != NULL)
-		{
-			lineno++;
-			uint8_t vector[80];
-			char str[255];
-			int length;
+        while (ret == OK && (uint8_t *) fgets((char *) line, sizeof(line), file) != NULL)
+        {
+            lineno++;
+            uint8_t vector[80];
+            char str[255];
+            int length;



-			line_to_vector(line, vector);	/* vector now contains the decoded contents of line, from line[1] on */
+            line_to_vector(line, vector);	/* vector now contains the decoded contents of line, from line[1] on */

-			if (line[0] == 'S')
-			{
-				char header[256];
+            if (line[0] == 'S')
+            {
+                char header[256];

-				if (SREC_CHECKSUM(vector) != checksum(vector))
-				{
-					printf("invalid checksum 0x%x (should be 0x%x) in line %d\r\n",
-							SREC_CHECKSUM(vector), checksum(vector), lineno);
-					ret = FAIL;
-				}
+                if (SREC_CHECKSUM(vector) != checksum(vector))
+                {
+                    printf("invalid checksum 0x%x (should be 0x%x) in line %d\r\n",
+                           SREC_CHECKSUM(vector), checksum(vector), lineno);
+                    ret = FAIL;
+                }

-				switch (vector[0])
-				{
-				case 0:	/* block header */
-					found_block_header = true;
-					if (found_block_data || found_block_end)
-					{
-						printf("S7 or S3 record found before S0: S-records corrupt?\r\n");
-						ret = FAIL;
-					}
-					printf("address: 0x%04x\n", SREC_ADDR16(vector));
-					printf("length of record: %d\n", SREC_COUNT(vector));
-					length = SREC_DATA16_SIZE(vector) - (SREC_DATA16(vector) - vector);
-					printf("length: %d\n", length);
-					strncpy(str, SREC_DATA16(vector), length);
-					str[length] = '\0';
-					printf("Name: %s\n", str);
-					printf("version: %d, revision %d\n",
-									* (unsigned short *)((char *) SREC_DATA16(vector) + length),
-									* (unsigned short *)((char *) SREC_DATA16(vector) + length + 1));
-					print_record(vector);
+                switch (vector[0])
+                {
+                    case 0:	/* block header */
+                        found_block_header = true;
+                        if (found_block_data || found_block_end)
+                        {
+                            printf("S7 or S3 record found before S0: S-records corrupt?\r\n");
+                            ret = FAIL;
+                        }
+                        printf("address: 0x%04x\n", SREC_ADDR16(vector));
+                        printf("length of record: %d\n", SREC_COUNT(vector));
+                        length = SREC_DATA16_SIZE(vector) - (SREC_DATA16(vector) - vector);
+                        printf("length: %d\n", length);
+                        strncpy(str, SREC_DATA16(vector), length);
+                        str[length] = '\0';
+                        printf("Name: %s\n", str);
+                        printf("version: %d, revision %d\n",
+                               * (unsigned short *)((char *) SREC_DATA16(vector) + length),
+                               * (unsigned short *)((char *) SREC_DATA16(vector) + length + 1));
+                        print_record(vector);

-					break;
+                        break;

-				case 2: /* three byte address field data record */
-					if (!found_block_header || found_block_end)
-					{
-						printf("S3 record found before S0 or after S7: S-records corrupt?\r\n");
-						ret = FAIL;
-					}
-					// ret = callback((uint8_t *) SREC_ADDR24(vector), SREC_DATA24(vector), SREC_DATA24_SIZE(vector));
-					data_records++;
-					break;
+                    case 2: /* three byte address field data record */
+                        if (!found_block_header || found_block_end)
+                        {
+                            printf("S3 record found before S0 or after S7: S-records corrupt?\r\n");
+                            ret = FAIL;
+                        }
+                        // ret = callback((uint8_t *) SREC_ADDR24(vector), SREC_DATA24(vector), SREC_DATA24_SIZE(vector));
+                        data_records++;
+                        break;

-				case 3: /* four byte address field data record */
-					if (!found_block_header || found_block_end)
-					{
-						printf("S3 record found before S0 or after S7: S-records corrupt?\r\n");
-						ret = FAIL;
-					}
-					// ret = callback((uint8_t *) SREC_ADDR32(vector), SREC_DATA32(vector), SREC_DATA32_SIZE(vector));
-					data_records++;
-					break;
+                    case 3: /* four byte address field data record */
+                        if (!found_block_header || found_block_end)
+                        {
+                            printf("S3 record found before S0 or after S7: S-records corrupt?\r\n");
+                            ret = FAIL;
+                        }
+                        // ret = callback((uint8_t *) SREC_ADDR32(vector), SREC_DATA32(vector), SREC_DATA32_SIZE(vector));
+                        data_records++;
+                        break;

-				case 7: /* four byte address field end record */
-					if (!found_block_header || found_block_end)
-					{
-						printf("S7 record found before S0 or after S7: S-records corrupt?\r\n");
-					}
-					else
-					{
-						// printf("S7 record (end) found after %d valid data blocks\r\n", data_records);
-						//*start_address = (void *) SREC_ADDR32(vector);
-					}
-					break;
+                    case 7: /* four byte address field end record */
+                        if (!found_block_header || found_block_end)
+                        {
+                            printf("S7 record found before S0 or after S7: S-records corrupt?\r\n");
+                        }
+                        else
+                        {
+                            // printf("S7 record (end) found after %d valid data blocks\r\n", data_records);
+                            //*start_address = (void *) SREC_ADDR32(vector);
+                        }
+                        break;

-				case 8: /* three byte address field end record */
-					if (!found_block_header || found_block_end)
-					{
-						printf("S8 record found before S0 or after S8: S-records corrupt?\r\n");
-					}
-					else
-					{
-						// printf("S7 record (end) found after %d valid data blocks\r\n", data_records);
-						//*start_address = (void *) SREC_ADDR24(vector);
-					}
-					break;
+                    case 8: /* three byte address field end record */
+                        if (!found_block_header || found_block_end)
+                        {
+                            printf("S8 record found before S0 or after S8: S-records corrupt?\r\n");
+                        }
+                        else
+                        {
+                            // printf("S7 record (end) found after %d valid data blocks\r\n", data_records);
+                            //*start_address = (void *) SREC_ADDR24(vector);
+                        }
+                        break;

-				default:
-					printf("unsupported record type (%d) found in line %d\r\n", vector[0], lineno);
-					printf("offending line: \r\n");
-					printf("%s\r\n", line);
-					ret = FAIL;
-					break;
-				}
-			}
-			else
-			{
-				printf("illegal character ('%c') found on line %d: S-records corrupt?\r\n", line[0], lineno);
-				ret = FAIL;
-				break;
-			}
-		}
-		fclose(file);
-	}
-	else
-	{
-		printf("could not open file %s\r\n", filename);
-		ret = FILE_OPEN;
-	}
-	return ret;
+                    default:
+                        printf("unsupported record type (%d) found in line %d\r\n", vector[0], lineno);
+                        printf("offending line: \r\n");
+                        printf("%s\r\n", line);
+                        ret = FAIL;
+                        break;
+                }
+            }
+            else
+            {
+                printf("illegal character ('%c') found on line %d: S-records corrupt?\r\n", line[0], lineno);
+                ret = FAIL;
+                break;
+            }
+        }
+        fclose(file);
+    }
+    else
+    {
+        printf("could not open file %s\r\n", filename);
+        ret = FILE_OPEN;
+    }
+    return ret;
 }

 /*
@@ -357,9 +357,9 @@ int main(int argc, char *argv[])
 */
 static err_t simulate()
 {
-	err_t ret = OK;
+    err_t ret = OK;

-	return ret;
+    return ret;
 }


@@ -368,15 +368,15 @@ static err_t simulate()
 */
 static err_t verify(uint8_t *dst, uint8_t *src, uint32_t length)
 {
-	uint8_t *end = src + length;
+    uint8_t *end = src + length;

-	do
-	{
-		if (*src++ != *dst++)
-			return FAIL;
-	} while (src < end);
+    do
+    {
+        if (*src++ != *dst++)
+            return FAIL;
+    } while (src < end);

-	return OK;
+    return OK;
 }

 void srec_execute(char *flasher_filename)
--- a/pci/ehci-hcd.c
+++ b/pci/ehci-hcd.c
--- a/pci/ohci-hcd.c
+++ b/pci/ohci-hcd.c
@@ -109,52 +109,52 @@ inline void writel(uint32_t value, uint32_t *address)

 struct pci_device_id ohci_usb_pci_table[] =
 {
-    {
-        PCI_VENDOR_ID_AL,
-        PCI_DEVICE_ID_AL_M5237,
-        PCI_ANY_ID,
-        PCI_ANY_ID,
-        PCI_CLASS_SERIAL_USB_OHCI,
-        0,
-        0
-    }, /* ULI1575 PCI OHCI module ids */
-    {
-        PCI_VENDOR_ID_NEC,
-        PCI_DEVICE_ID_NEC_USB,
-        PCI_ANY_ID,
-        PCI_ANY_ID,
-        PCI_CLASS_SERIAL_USB_OHCI,
-        0,
-        0
-    }, /* NEC PCI OHCI module ids */
-    {
-        PCI_VENDOR_ID_NEC,
-        PCI_DEVICE_ID_NEC_USB_A,
-        PCI_ANY_ID,
-        PCI_ANY_ID,
-        PCI_CLASS_SERIAL_USB_OHCI,
-        0,
-        0
-    }, /* NEC PCI OHCI module ids */
-    {
-        PCI_VENDOR_ID_PHILIPS,
-        PCI_DEVICE_ID_PHILIPS_ISP1561,
-        PCI_ANY_ID,
-        PCI_ANY_ID,
-        PCI_CLASS_SERIAL_USB_OHCI,
-        0,
-        0
-    }, /* Philips 1561 PCI OHCI module ids */
-    /* Please add supported PCI OHCI controller ids here */
-    {
-        0,
-        0,
-        0,
-        0,
-        0,
-        0,
-        0
-    }
+{
+    PCI_VENDOR_ID_AL,
+    PCI_DEVICE_ID_AL_M5237,
+    PCI_ANY_ID,
+    PCI_ANY_ID,
+    PCI_CLASS_SERIAL_USB_OHCI,
+    0,
+    0
+}, /* ULI1575 PCI OHCI module ids */
+{
+    PCI_VENDOR_ID_NEC,
+    PCI_DEVICE_ID_NEC_USB,
+    PCI_ANY_ID,
+    PCI_ANY_ID,
+    PCI_CLASS_SERIAL_USB_OHCI,
+    0,
+    0
+}, /* NEC PCI OHCI module ids */
+{
+    PCI_VENDOR_ID_NEC,
+    PCI_DEVICE_ID_NEC_USB_A,
+    PCI_ANY_ID,
+    PCI_ANY_ID,
+    PCI_CLASS_SERIAL_USB_OHCI,
+    0,
+    0
+}, /* NEC PCI OHCI module ids */
+{
+    PCI_VENDOR_ID_PHILIPS,
+    PCI_DEVICE_ID_PHILIPS_ISP1561,
+    PCI_ANY_ID,
+    PCI_ANY_ID,
+    PCI_CLASS_SERIAL_USB_OHCI,
+    0,
+    0
+}, /* Philips 1561 PCI OHCI module ids */
+/* Please add supported PCI OHCI controller ids here */
+{
+    0,
+    0,
+    0,
+    0,
+    0,
+    0,
+    0
+}
 };

 /* global ohci_t */
@@ -169,8 +169,8 @@ static inline uint32_t roothub_portstatus(ohci_t *ohci, int i) { return readl(&o
 /* forward declaration */
 static int hc_interrupt(ohci_t *ohci);
 static void td_submit_job(ohci_t *ohci, struct usb_device *dev, uint32_t pipe,
-                            void *buffer, int transfer_len, struct devrequest *setup,
-                            urb_priv_t *urb, int interval);
+                          void *buffer, int transfer_len, struct devrequest *setup,
+                          urb_priv_t *urb, int interval);


 static struct td *ptd;
@@ -231,20 +231,20 @@ static int sohci_get_current_frame_number(ohci_t *ohci, struct usb_device *dev);
 * small: 0) header + data packets 1) just header */

 static void pkt_print(ohci_t *ohci, urb_priv_t *purb, struct usb_device *dev,
-              uint32_t pipe, void *buffer, int transfer_len,
-              struct devrequest *setup, char *str, int small)
+                      uint32_t pipe, void *buffer, int transfer_len,
+                      struct devrequest *setup, char *str, int small)
 {
    dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx\r\n",
-            str,
-            sohci_get_current_frame_number(ohci, dev),
-            usb_pipedevice(pipe),
-            usb_pipeendpoint(pipe),
-            usb_pipeout(pipe)? 'O': 'I',
-            usb_pipetype(pipe) < 2 ? \
-                (usb_pipeint(pipe)? "INTR": "ISOC"): \
-                (usb_pipecontrol(pipe)? "CTRL": "BULK"),
-            (purb ? purb->actual_length : 0),
-            transfer_len, dev->status);
+        str,
+        sohci_get_current_frame_number(ohci, dev),
+        usb_pipedevice(pipe),
+        usb_pipeendpoint(pipe),
+        usb_pipeout(pipe)? 'O': 'I',
+        usb_pipetype(pipe) < 2 ? \
+            (usb_pipeint(pipe)? "INTR": "ISOC"): \
+            (usb_pipecontrol(pipe)? "CTRL": "BULK"),
+        (purb ? purb->actual_length : 0),
+        transfer_len, dev->status);
 #ifdef OHCI_VERBOSE_DEBUG
    if (!small)
    {
@@ -313,7 +313,7 @@ static void ohci_dump_intr_mask(char *label, uint32_t mask)
        (mask & OHCI_INTR_SF) ? " SF" : "",
        (mask & OHCI_INTR_WDH) ? " WDH" : "",
        (mask & OHCI_INTR_SO) ? " SO" : ""
-        );
+                                );
 }

 static void maybe_print_eds(ohci_t *controller, char *label, uint32_t value)
@@ -375,7 +375,7 @@ static void ohci_dump_status(ohci_t *controller)
        (temp & OHCI_BLF) ? " BLF" : "",
        (temp & OHCI_CLF) ? " CLF" : "",
        (temp & OHCI_HCR) ? " HCR" : ""
-        );
+                            );
    ohci_dump_intr_mask("intrstatus", readl(&regs->intrstatus));
    ohci_dump_intr_mask("intrenable", readl(&regs->intrenable));
    maybe_print_eds(controller, "ed_periodcurrent", readl(&regs->ed_periodcurrent));
@@ -395,7 +395,7 @@ static void ohci_dump_roothub(ohci_t *controller, int verbose)
    temp = roothub_a(controller);
    (void) temp;

-//	ndp = (temp & RH_A_NDP);
+    //	ndp = (temp & RH_A_NDP);
    ndp = controller->ndp;
    if (verbose)
    {
@@ -423,7 +423,7 @@ static void ohci_dump_roothub(ohci_t *controller, int verbose)
            (temp & RH_HS_DRWE) ? " DRWE" : "",
            (temp & RH_HS_OCI) ? " OCI" : "",
            (temp & RH_HS_LPS) ? " LPS" : ""
-            );
+                                 );
    }

    for (i = 0; i < ndp; i++)
@@ -446,7 +446,7 @@ static void ohci_dump_roothub(ohci_t *controller, int verbose)

            (temp & RH_PS_PES) ? " PES" : "",
            (temp & RH_PS_CCS) ? " CCS" : ""
-            );
+                                 );
    }
 }

@@ -736,8 +736,8 @@ static int ep_link(ohci_t *ohci, ed_t *edi)
            {
                inter = 1;
                for (ed_p = &(ohci->hcca->int_table[ep_rev(5, i) + int_branch]);
-                 (*ed_p != 0) && (((ed_t *)ed_p)->int_interval >= interval);
-                 ed_p = &(((ed_t *)ed_p)->hwNextED))
+                     (*ed_p != 0) && (((ed_t *)ed_p)->int_interval >= interval);
+                     ed_p = &(((ed_t *)ed_p)->hwNextED))
                    inter = ep_rev(6, ((ed_t *)ed_p)->int_interval);
                ed->hwNextED = *ed_p;
                *ed_p = swpl((uint32_t)ed - ohci->dma_offset);
@@ -869,11 +869,11 @@ static ed_t *ep_add_ed(ohci_t *ohci, struct usb_device *usb_dev, uint32_t pipe,
    }

    ed->hwINFO = swpl(usb_pipedevice(pipe)
-            | usb_pipeendpoint(pipe) << 7
-            | (usb_pipeisoc(pipe)? 0x8000: 0)
-            | (usb_pipecontrol(pipe)? 0: (usb_pipeout(pipe)? 0x800: 0x1000))
-            | usb_pipeslow(pipe) << 13
-            | usb_maxpacket(usb_dev, pipe) << 16);
+                      | usb_pipeendpoint(pipe) << 7
+                      | (usb_pipeisoc(pipe)? 0x8000: 0)
+                      | (usb_pipecontrol(pipe)? 0: (usb_pipeout(pipe)? 0x800: 0x1000))
+                      | usb_pipeslow(pipe) << 13
+                      | usb_maxpacket(usb_dev, pipe) << 16);

    if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK)
    {
@@ -943,14 +943,14 @@ static void td_fill(ohci_t *ohci, unsigned int info, void *data, int len,
    {
        int i;
        dbg("td_fill: %08x %08x %08X %08X at 0x%08X\r\n",
-         swpl(td->hwINFO), swpl(td->hwCBP), swpl(td->hwNextTD), swpl(td->hwBE), td);
+            swpl(td->hwINFO), swpl(td->hwCBP), swpl(td->hwNextTD), swpl(td->hwBE), td);
        for (i = 0; i < len; i++)
            dbg("%02X ", *(unsigned char *)(data + i) & 0xff);
        dbg("\r\n");
    }
    else
        dbg("td_fill: %08x %08x %08X %08X at 0x%08X\r\n",
-         swpl(td->hwINFO), swpl(td->hwCBP), swpl(td->hwNextTD), swpl(td->hwBE), td);
+            swpl(td->hwINFO), swpl(td->hwCBP), swpl(td->hwNextTD), swpl(td->hwBE), td);
 #endif
 }

@@ -959,8 +959,8 @@ static void td_fill(ohci_t *ohci, unsigned int info, void *data, int len,
 /* prepare all TDs of a transfer */

 static void td_submit_job(ohci_t *ohci, struct usb_device *dev, uint32_t pipe,
-                            void *buffer, int transfer_len, struct devrequest *setup,
-                            urb_priv_t *urb, int interval)
+                          void *buffer, int transfer_len, struct devrequest *setup,
+                          urb_priv_t *urb, int interval)
 {
    int data_len = transfer_len;
    void *data;
@@ -1258,7 +1258,7 @@ static uint8_t root_hub_config_des[] =
    0x01,	    /*	uint8_t  bConfigurationValue; */
    0x00,	    /*	uint8_t  iConfiguration; */
    0x40,	    /*	uint8_t  bmAttributes;
-     Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+         Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
    0x00,	    /*	uint8_t  MaxPower; */

    /* interface */
@@ -1344,7 +1344,7 @@ int rh_check_port_status(ohci_t *controller)
    uint32_t temp, ndp, i;
    int res = -1;
    temp = roothub_a(controller);
-//	ndp = (temp & RH_A_NDP);
+    //	ndp = (temp & RH_A_NDP);
    ndp = controller->ndp;
    for (i = 0; i < ndp; i++)
    {
@@ -1368,7 +1368,7 @@ int rh_check_port_status(ohci_t *controller)
 }

 static int ohci_submit_rh_msg(ohci_t *ohci, struct usb_device *dev, uint32_t pipe,
-                                void *buffer, int transfer_len, struct devrequest *cmd)
+                              void *buffer, int transfer_len, struct devrequest *cmd)
 {
    void *data = buffer;
    int leni = transfer_len;
@@ -1524,7 +1524,7 @@ static int ohci_submit_rh_msg(ohci_t *ohci, struct usb_device *dev, uint32_t pip
                uint32_t temp = roothub_a(ohci);
                data_buf[0] = 9;		/* min length; */
                data_buf[1] = 0x29;
-//      		data_buf[2] = temp & RH_A_NDP;
+                //      		data_buf[2] = temp & RH_A_NDP;
                data_buf[2] = (uint8_t)ohci->ndp;
                data_buf[3] = 0;

@@ -1607,7 +1607,7 @@ static int ohci_submit_rh_msg(ohci_t *ohci, struct usb_device *dev, uint32_t pip
 */

 static int submit_common_msg(ohci_t *ohci, struct usb_device *dev, uint32_t pipe, void *buffer,
-                                int transfer_len, struct devrequest *setup, int interval)
+                             int transfer_len, struct devrequest *setup, int interval)
 {
    int stat = 0;
    int maxsize = usb_maxpacket(dev, pipe);
@@ -1688,7 +1688,7 @@ static int submit_common_msg(ohci_t *ohci, struct usb_device *dev, uint32_t pipe
        }
        else
 #endif
-        stat = hc_interrupt(ohci);
+            stat = hc_interrupt(ohci);
        if (stat < 0)
        {
            dbg("USB CRC error\r\n");
@@ -1820,7 +1820,7 @@ static int hc_reset(ohci_t *ohci)
                uint32_t id = 0;
                id = pci_read_config_longword(handle, PCIIDR);
                if ((PCI_VENDOR_ID_PHILIPS == (id & 0xFFFF)) && (PCI_DEVICE_ID_PHILIPS_ISP1561_2 == (id >> 16)))
-                 {
+                {
                    int timeout = 1000;
                    uint32_t usb_base_addr = 0xFFFFFFFF;
                    struct pci_rd *pci_rsc_desc;
@@ -1859,7 +1859,7 @@ static int hc_reset(ohci_t *ohci)
    }

    if ((ohci->controller == 0) && (ohci->ent->vendor == PCI_VENDOR_ID_NEC)
-                                && (ohci->ent->device == PCI_DEVICE_ID_NEC_USB))
+            && (ohci->ent->device == PCI_DEVICE_ID_NEC_USB))
    {
        //if (ohci->handle == 1) /* NEC on motherboard has FPGA clock */
 #if defined(MACHINE_FIREBEE)
--- a/pci/pci.c
+++ b/pci/pci.c
@@ -26,6 +26,7 @@

 #include <MCF5475.h>
 #include "pci.h"
+#include "pci_errata.h"
 #include "bas_types.h"
 #include "bas_printf.h"
 #include "bas_string.h"
@@ -33,7 +34,7 @@
 #include "interrupts.h"
 #include "wait.h"

-//#define DEBUG_PCI
+// #define DEBUG_PCI
 #ifdef DEBUG_PCI
 #define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
@@ -77,13 +78,11 @@ static int num_pci_classes = sizeof(pci_classes) / sizeof(struct pci_class);
 #define NUM_CARDS       10
 #define NUM_RESOURCES   7
 /* holds the handle of a card at position = array index */
-static int32_t handles[NUM_CARDS];
+static int32_t handles[NUM_CARDS] = { -1 };

 /* holds the card's resource descriptors; filled in pci_device_config() */
 static struct pci_rd resource_descriptors[NUM_CARDS][NUM_RESOURCES];

-typedef int (*pci_interrupt_handler)(int param);
-
 /*
 * holds the interrupt handler addresses (see pci_hook_interrupt()
 * and pci_unhook_interrupt()) of the PCI cards
@@ -100,65 +99,6 @@ struct pci_interrupt
 #define MAX_INTERRUPTS  (NUM_CARDS * 3)
 static struct pci_interrupt interrupts[MAX_INTERRUPTS];

-static inline __attribute__((aligned(16))) void chip_errata_135(void)
-{
-    /*
-     * Errata type: Silicon
-     * Affected component: PCI
-     * Description: When core PCI transactions that involve writes to configuration or I/O space
-     * are followed by a core line access to line addresses 0x4 and 0xC, core access
-     * to the XL bus can hang.
-     * Workaround: Prevent PCI configuration and I/O writes from being followed by the described
-     * line access by the core by generating a known good XL bus transaction after
-     * the PCI transaction.
-     * Create a dummy function which is called immediately after each of the affected
-     * transactions. There are three requirements for this dummy function.
-     * 1. The function must be aligned to a 16-byte boundary.
-     * 2. The function must contain a dummy write to a location on the XL bus,
-     * preferably one with no side effects.
-     * 3. The function must be longer than 32 bytes. If it is not, the function should
-     * be padded with 16- or 48-bit TPF instructions placed after the end of
-     * the function (after the RTS instruction) such that the length is longer
-     * than 32 bytes.
-     */
-
-     __asm__ __volatile(
-        "       .extern __MBAR          \n\t"
-        "       clr.l   d0              \n\t"
-        "       move.l  d0,__MBAR+0xF0C \n\t"       /* Must use direct addressing. write to EPORT module */
-                                                    /* xlbus -> slavebus -> eport, writing '0' to register */
-                                                    /* has no effect */
-        "       rts                     \n\t"
-        "       tpf.l   #0x0            \n\t"
-        "       tpf.l   #0x0            \n\t"
-        "       tpf.l   #0x0            \n\t"
-        "       tpf.l   #0x0            \n\t"
-        "       tpf.l   #0x0            \n\t"
-        ::: "memory");
-}
-
-static inline void chip_errata_055(int32_t handle)
-{
-    uint32_t dummy;
-
-    return;     /* test */
-
-    /* initiate PCI configuration access to device */
-    MCF_PCI_PCICAR = MCF_PCI_PCICAR_E |         /* enable configuration access special cycle */
-            MCF_PCI_PCICAR_BUSNUM(3) |          /* note: invalid bus number */
-            MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | /* device number, devices 0 - 9 are reserved */
-            MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |  /* function number */
-            MCF_PCI_PCICAR_DWORD(0);
-
-    /* issue a dummy read to an unsupported bus number (will fail) */
-    dummy =  * (volatile uint32_t *) PCI_IO_OFFSET; /* access device */
-
-    /* silently clear the PCI errors we produced just now */
-    MCF_PCI_PCIISR = 0xffffffff;     /* clear all errors */
-    MCF_PCI_PCIGSCR = MCF_PCI_PCIGSCR_PE | MCF_PCI_PCIGSCR_SE;
-
-    (void) dummy;
-}

 /*
 * Although this pragma stuff should work according to the GCC docs, it doesn't seem to
@@ -175,6 +115,7 @@ int32_t pci_get_interrupt_cause(void)
    /*
     * loop through all PCI devices...
     */
+    dbg("");
    while ((handle = *hdl++) != -1)
    {
        uint16_t command_register = swpw(pci_read_config_word(handle, PCICR));
@@ -198,6 +139,7 @@ int32_t pci_call_interrupt_chain(int32_t handle, int32_t data)
 {
    int i;

+    dbg("");
    for (i = 0; i < MAX_INTERRUPTS; i++)
    {
        if (interrupts[i].handle == handle)
@@ -244,7 +186,7 @@ static char *device_class(int classcode)
            return pci_classes[i].description;
        }
    }
-    return "not found";
+    return "unknown device class";
 }

 /*
@@ -300,11 +242,6 @@ static int pci_check_status(void)

        ret = 1;
    }
-
-    if (!ret)
-    {
-        dbg("no error\r\n");
-    }
    return ret;
 }

@@ -397,6 +334,9 @@ uint8_t pci_read_config_byte(int32_t handle, int offset)
 int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t value)
 {
    /* initiate PCI configuration access to device */
+
+    dbg("initiate configuration access\r\n");
+
    MCF_PCI_PCICAR = MCF_PCI_PCICAR_E |             /* enable configuration access special cycle */
        MCF_PCI_PCICAR_BUSNUM(PCI_BUS_FROM_HANDLE(handle)) |
        MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) |     /* device number, devices 0 - 9 are reserved */
@@ -405,11 +345,15 @@ int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t value)

    NOP();

+    dbg("access device\r\n");
    * (volatile uint32_t *) PCI_IO_OFFSET = value;  /* access device */
+
+    dbg("chip errata\r\n");
    chip_errata_135();

    NOP();

+    dbg("finish config space access cycle\r\n");
    /* finish configuration space access cycle */
    MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E;

@@ -470,6 +414,7 @@ int32_t pci_write_config_byte(int32_t handle, int offset, uint8_t value)

    return PCI_SUCCESSFUL;
 }
+
 /*
 * pci_get_resource
 *
@@ -546,7 +491,7 @@ int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index)
                        if (value != 0xffffffff)    /* device found */
                        {
                            if (vendor_id == 0xffff ||
-                                (PCI_VENDOR_ID(value) == vendor_id && PCI_DEVICE_ID(value) == device_id))
+                                ((PCI_VENDOR_ID(value) == vendor_id) && (PCI_DEVICE_ID(value) == device_id)))
                            {
                                if (n == index)
                                {
@@ -567,6 +512,7 @@ int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index)
 * pci_find_classcode(uint32_t classcode, int index)
 *
 * Find the index'th pci device with a specific classcode. Bits 0-23 describe this classcode.
+ *
 * Bits 24 - 26 describe what needs to match: 24: prog interface, 25: PCI subclass, 26: PCI base class.
 * If no bits are set, there is a match for each device.
 */
@@ -586,6 +532,7 @@ int32_t pci_find_classcode(uint32_t classcode, int index)
            uint8_t htr;

            handle = PCI_HANDLE(bus, device, 0);
+            dbg("check handle %d\r\n", handle);

            value = pci_read_config_longword(handle, PCIIDR);

@@ -593,12 +540,18 @@ int32_t pci_find_classcode(uint32_t classcode, int index)
            {
                value = pci_read_config_longword(handle, PCICCR);

+                dbg("classcode to search for=%x\r\n", classcode);
+                dbg("PCI_CLASSCODE found=%02x\r\n", PCI_CLASS_CODE(value));
+                dbg("PCI_SUBCLASS found=%02x\r\n", PCI_SUBCLASS(value));
+                dbg("PCI_PROG_IF found=%02x\r\n", PCI_PROG_IF(value));
+
                if ((classcode & (1 << 26) ? ((PCI_CLASS_CODE(value) == (classcode & 0xff))) : true) &&
                    (classcode & (1 << 25) ? ((PCI_SUBCLASS(value) == ((classcode & 0xff00) >> 8))) : true) &&
                    (classcode & (1 << 24) ? ((PCI_PROG_IF(value) == ((classcode & 0xff0000) >> 16))) : true))
                {
                    if (n == index)
                    {
+                        dbg("found device at handle %d\r\n", handle);
                        return handle;
                    }
                    n++;
@@ -622,12 +575,13 @@ int32_t pci_find_classcode(uint32_t classcode, int index)
                        {
                            value = pci_read_config_longword(handle, PCICCR);

-                            if ((classcode & (1 << 26) ? ((PCI_CLASS_CODE(value) == (classcode & 0xff))) : true) &&
-                                (classcode & (1 << 25) ? ((PCI_SUBCLASS(value) == ((classcode & 0xff00) >> 8))) : true) &&
-                                (classcode & (1 << 24) ? ((PCI_PROG_IF(value) == ((classcode & 0xff0000) >> 16))) : true))
+                            if ((classcode & PCI_FIND_BASE_CLASS ? ((PCI_CLASS_CODE(value) == (classcode & 0xff))) : true) &&
+                                (classcode & PCI_FIND_SUB_CLASS ? ((PCI_SUBCLASS(value) == ((classcode & 0xff00) >> 8))) : true) &&
+                                (classcode & PCI_FIND_PROG_IF ? ((PCI_PROG_IF(value) == ((classcode & 0xff0000) >> 16))) : true))
                            {
                                if (n == index)
                                {
+                                    dbg("found device with handle %d\n", handle);
                                    return handle;
                                }
                                n++;
@@ -645,7 +599,7 @@ int32_t pci_hook_interrupt(int32_t handle, void *handler, void *parameter)
 {
    int i;

-    pci_interrupt_handler h = handler;
+    // pci_interrupt_handler h = handler;

    /*
     * find empty slot
@@ -930,7 +884,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)

                /* fill resource descriptor */
                rd->next = sizeof(struct pci_rd);
-                rd->flags = 0 | FLG_32BIT | FLG_16BIT | FLG_8BIT | 2; /* little endian, lane swapped */
+                rd->flags = 0 | FLG_32BIT | FLG_16BIT | FLG_8BIT | ORD_INTEL_LS; /* little endian, lane swapped */
                rd->start = address;
                rd->length = size;
                rd->offset = 0;
@@ -1041,12 +995,13 @@ static void pci_bridge_config(uint16_t bus, uint16_t device, uint16_t function)

    if (function != 0)
    {
-        dbg("trying to configure a multi-function bridge. Cancelled\r\n");
+        err("trying to configure a multi-function bridge. Cancelled\r\n");
        return;
    }
    handle = PCI_HANDLE(bus, device, function);
+    dbg("handle=%d\r\n", handle);

-    pci_write_config_longword(handle, PCIBAR0, 0x40000000);
+    pci_write_config_longword(handle, PCIBAR0, swpl(0x40000000));
    pci_write_config_longword(handle, PCIBAR1, 0x0);
    pci_write_config_longword(handle, PCICSR, 0x146);
 }
@@ -1069,17 +1024,21 @@ void pci_scan(void)
        uint32_t value;

        value = pci_read_config_longword(handle, PCIIDR);
-        xprintf(" %02x | %02x | %02x |%04x|%04x|%04x| %s (0x%02x)\r\n",
+
+        xprintf(" %02x | %02x | %02x |%04x|%04x|%04x| %s (0x%02x, 0x%04x)\r\n",
                PCI_BUS_FROM_HANDLE(handle),
                PCI_DEVICE_FROM_HANDLE(handle),
                PCI_FUNCTION_FROM_HANDLE(handle),
                PCI_VENDOR_ID(value), PCI_DEVICE_ID(value),
                handle,
                device_class(pci_read_config_byte(handle, PCICCR)),
-                pci_read_config_byte(handle, PCICCR));
+                pci_read_config_byte(handle, PCICCR),
+                pci_read_config_word(handle, PCICCR));

        /* save handle to index value so that we'll be able to later find our resources */
        handles[index] = handle;
+        handles[index + 1] = -1;
+
        if (PCI_VENDOR_ID(value) != 0x1057 && PCI_DEVICE_ID(value) != 0x5806) /* do not configure bridge */
        {
            /* configure memory and I/O for card */
@@ -1089,10 +1048,12 @@ void pci_scan(void)
        }
        else
        {
+            dbg("");
            pci_bridge_config(PCI_BUS_FROM_HANDLE(handle),
                        PCI_DEVICE_FROM_HANDLE(handle),
                        PCI_FUNCTION_FROM_HANDLE(handle));
        }
+        dbg("");
        handle = pci_find_device(0x0, 0xFFFF, ++index);
    }
    xprintf("\r\n...finished\r\n");
@@ -1104,15 +1065,16 @@ void init_eport(void)
    /* configure IRQ1-7 pins on EPORT falling edge triggered */
    MCF_EPORT_EPPAR = MCF_EPORT_EPPAR_EPPA7(MCF_EPORT_EPPAR_FALLING) |
            MCF_EPORT_EPPAR_EPPA6(MCF_EPORT_EPPAR_FALLING) |
-#if MACHINE_FIREBEE     /* irq5 level triggered on FireBee */
+#if defined(MACHINE_FIREBEE)     /* irq5 level triggered on FireBee */
            MCF_EPORT_EPPAR_EPPA5(MCF_EPORT_EPPAR_LEVEL) |
-#elif MACHINE_M5484LITE
+#elif defined(MACHINE_M5484LITE)
            MCF_EPORT_EPPAR_EPPA5(MCF_EPORT_EPPAR_FALLING) |
 #endif /* MACHINE_FIREBEE */
            MCF_EPORT_EPPAR_EPPA4(MCF_EPORT_EPPAR_FALLING) |
            MCF_EPORT_EPPAR_EPPA3(MCF_EPORT_EPPAR_FALLING) |
            MCF_EPORT_EPPAR_EPPA2(MCF_EPORT_EPPAR_FALLING) |
            MCF_EPORT_EPPAR_EPPA1(MCF_EPORT_EPPAR_FALLING);
+
    MCF_EPORT_EPDDR = 0;    /* clear data direction register. All pins as input */
    MCF_EPORT_EPFR = -1;    /* clear all EPORT interrupt flags */
    MCF_EPORT_EPIER = 0xfe; /* enable all EPORT interrupts (for now) */
@@ -1169,7 +1131,7 @@ void init_pci(void)
    init_eport();
    init_xlbus_arbiter();

-    MCF_PCI_PCIGSCR = 1;    /* reset PCI */
+    MCF_PCI_PCIGSCR = -1;

    /*
     * setup the PCI arbiter
@@ -1195,11 +1157,11 @@ void init_pci(void)
    MCF_PAD_PAR_PCIBR = 0x3ff;
 #endif /* MACHINE_FIREBEE */

-    MCF_PCI_PCISCR =  MCF_PCI_PCISCR_M | /* memory access control enabled */
-        MCF_PCI_PCISCR_B |      /* bus master enabled */
-        MCF_PCI_PCISCR_M |      /* mem access enable */
-        MCF_PCI_PCISCR_MA |     /* clear master abort error */
-        MCF_PCI_PCISCR_MW;      /* memory write and invalidate enabled */
+    MCF_PCI_PCISCR =  MCF_PCI_PCISCR_M |    /* memory access control enabled */
+        MCF_PCI_PCISCR_B |                  /* bus master enabled */
+        MCF_PCI_PCISCR_M |                  /* mem access enable */
+        MCF_PCI_PCISCR_MA |                 /* clear master abort error */
+        MCF_PCI_PCISCR_MW;                  /* memory write and invalidate enabled */


    /* Setup burst parameters */
@@ -1222,15 +1184,21 @@ void init_pci(void)

    /* Configure Initiator Windows */

-    /* initiator window 0 base / translation adress register */
-    MCF_PCI_PCIIW0BTAR = (PCI_MEMORY_OFFSET | (((PCI_MEMORY_SIZE - 1) >> 8) & 0xffff0000))
-                          | ((PCI_MEMORY_OFFSET >> 16) & 0xff00);
+    /*
+     * initiator window 0 base / translation adress register
+     * used for PCI memory access
+     */
+    MCF_PCI_PCIIW0BTAR = (PCI_MEMORY_OFFSET + ((PCI_MEMORY_SIZE - 1) >> 8))
+                          + (PCI_MEMORY_OFFSET >> 16);

    NOP();
    dbg("PCIIW0BTAR=0x%08x\r\n", MCF_PCI_PCIIW0BTAR);

-    /* initiator window 1 base / translation adress register */
-    MCF_PCI_PCIIW1BTAR = (PCI_IO_OFFSET | ((PCI_IO_SIZE - 1) >> 8)) & 0xffff0000;
+    /*
+     * initiator window 1 base / translation adress register
+     * used for PCI I/O access
+     */
+    MCF_PCI_PCIIW1BTAR = (PCI_IO_OFFSET + ((PCI_IO_SIZE - 1) >> 8)) & 0xffff0000;
    NOP();
    /* initiator window 2 base / translation address register */
    MCF_PCI_PCIIW2BTAR = 0L;   /* not used */
@@ -1241,6 +1209,7 @@ void init_pci(void)
                    MCF_PCI_PCIIWCR_WINCTRL0_E |
                    MCF_PCI_PCIIWCR_WINCTRL1_E;
    NOP();
+
    /*
     * Initialize target control register.
     * Used when an external bus master accesses the Coldfire PCI as target
--- a/pci/pci_errata.c
+++ b/pci/pci_errata.c
@@ -0,0 +1,64 @@
+#include "pci_errata.h"
+#include "pci.h"
+#include <MCF5475.h>
+
+__attribute__((aligned(16))) void chip_errata_135(void)
+{
+    /*
+     * Errata type: Silicon
+     * Affected component: PCI
+     * Description: When core PCI transactions that involve writes to configuration or I/O space
+     * are followed by a core line access to line addresses 0x4 and 0xC, core access
+     * to the XL bus can hang.
+     * Workaround: Prevent PCI configuration and I/O writes from being followed by the described
+     * line access by the core by generating a known good XL bus transaction after
+     * the PCI transaction.
+     * Create a dummy function which is called immediately after each of the affected
+     * transactions. There are three requirements for this dummy function.
+     * 1. The function must be aligned to a 16-byte boundary.
+     * 2. The function must contain a dummy write to a location on the XL bus,
+     * preferably one with no side effects.
+     * 3. The function must be longer than 32 bytes. If it is not, the function should
+     * be padded with 16- or 48-bit TPF instructions placed after the end of
+     * the function (after the RTS instruction) such that the length is longer
+     * than 32 bytes.
+     */
+
+     __asm__ __volatile(
+        "       .extern __MBAR          \n\t"
+        "       clr.l   d0              \n\t"
+        "       move.l  d0,__MBAR+0xF0C \n\t"       /* Must use direct addressing. write to EPORT module */
+                                                    /* xlbus -> slavebus -> eport, writing '0' to register */
+                                                    /* has no effect */
+        "       rts                     \n\t"
+        "       tpf.l   #0x0            \n\t"
+        "       tpf.l   #0x0            \n\t"
+        "       tpf.l   #0x0            \n\t"
+        "       tpf.l   #0x0            \n\t"
+        "       tpf.l   #0x0            \n\t"
+        ::: "d0", "memory");
+}
+
+void chip_errata_055(int32_t handle)
+{
+    uint32_t dummy;
+
+    return;     /* test */
+
+    /* initiate PCI configuration access to device */
+    MCF_PCI_PCICAR = MCF_PCI_PCICAR_E |         /* enable configuration access special cycle */
+            MCF_PCI_PCICAR_BUSNUM(3) |          /* note: invalid bus number */
+            MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | /* device number, devices 0 - 9 are reserved */
+            MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |  /* function number */
+            MCF_PCI_PCICAR_DWORD(0);
+
+    /* issue a dummy read to an unsupported bus number (will fail) */
+    dummy =  * (volatile uint32_t *) PCI_IO_OFFSET; /* access device */
+
+    /* silently clear the PCI errors we produced just now */
+    MCF_PCI_PCIISR = 0xffffffff;     /* clear all errors */
+    MCF_PCI_PCIGSCR = MCF_PCI_PCIGSCR_PE | MCF_PCI_PCIGSCR_SE;
+
+    (void) dummy;
+}
+
--- a/radeon/radeon_accel.c
+++ b/radeon/radeon_accel.c
--- a/radeon/radeon_base.c
+++ b/radeon/radeon_base.c
--- a/radeon/radeon_cursor.c
+++ b/radeon/radeon_cursor.c
@@ -70,41 +70,41 @@
 #define CURSOR_SWAPPING_START() \
    if (rinfo->big_endian) \
    OUTREG(SURFACE_CNTL, \
-	   ((__surface_cntl = INREG(SURFACE_CNTL)) | \
-	    NONSURF_AP0_SWP_32BPP) & \
-	   ~NONSURF_AP0_SWP_16BPP);
+    ((__surface_cntl = INREG(SURFACE_CNTL)) | \
+    NONSURF_AP0_SWP_32BPP) & \
+    ~NONSURF_AP0_SWP_16BPP);
 #define CURSOR_SWAPPING_END() \
    if (rinfo->big_endian) \
-	(OUTREG(SURFACE_CNTL, __surface_cntl));
+    (OUTREG(SURFACE_CNTL, __surface_cntl));

 /* Set cursor foreground and background colors */
 void radeon_set_cursor_colors(struct fb_info *info, int bg, int fg)
 {
-	struct radeonfb_info *rinfo = info->par;
+    struct radeonfb_info *rinfo = info->par;
    unsigned long *pixels = (unsigned long *)((unsigned long) rinfo->fb_base + rinfo->cursor_start);
-	int pixel, i;
-	CURSOR_SWAPPING_DECL_MMIO
-	CURSOR_SWAPPING_DECL
-//	DPRINTVALHEX("radeonfb: RADEONSetCursorColors: cursor_start ",rinfo->cursor_start);
-//	DPRINT("\r\n");
-	fg |= 0xff000000;
-	bg |= 0xff000000;
-	/* Don't recolour the image if we don't have to. */
+    int pixel, i;
+    CURSOR_SWAPPING_DECL_MMIO
+            CURSOR_SWAPPING_DECL
+            //	DPRINTVALHEX("radeonfb: RADEONSetCursorColors: cursor_start ",rinfo->cursor_start);
+            //	DPRINT("\r\n");
+            fg |= 0xff000000;
+    bg |= 0xff000000;
+    /* Don't recolour the image if we don't have to. */
    if (fg == rinfo->cursor_fg && bg == rinfo->cursor_bg)
-		return;
-	CURSOR_SWAPPING_START();
+        return;
+    CURSOR_SWAPPING_START();

    /*
     * Note: We assume that the pixels are either fully opaque or fully
-	 * transparent, so we won't premultiply them, and we can just
-	 * check for non-zero pixel values; those are either fg or bg
-	 */
+     * transparent, so we won't premultiply them, and we can just
+     * check for non-zero pixel values; those are either fg or bg
+     */
    for (i = 0; i < CURSOR_WIDTH * CURSOR_HEIGHT; i++, pixels++)
        if ((pixel = *pixels))
-			*pixels = (pixel == rinfo->cursor_fg) ? fg : bg;
-	CURSOR_SWAPPING_END();
-	rinfo->cursor_fg = fg;
-	rinfo->cursor_bg = bg;
+            *pixels = (pixel == rinfo->cursor_fg) ? fg : bg;
+    CURSOR_SWAPPING_END();
+    rinfo->cursor_fg = fg;
+    rinfo->cursor_bg = bg;
 }

 /* Set cursor position to (x,y) with offset into cursor bitmap at
@@ -112,29 +112,29 @@ void radeon_set_cursor_colors(struct fb_info *info, int bg, int fg)
 */
 void radeon_set_cursor_position(struct fb_info *info, int x, int y)
 {
-	struct radeonfb_info *rinfo = info->par;
-	struct fb_var_screeninfo *mode = &info->var;
-	int xorigin = 0;
-	int yorigin = 0;
+    struct radeonfb_info *rinfo = info->par;
+    struct fb_var_screeninfo *mode = &info->var;
+    int xorigin = 0;
+    int yorigin = 0;
    if (mode->vmode & FB_VMODE_DOUBLE)
-		y <<= 1;
+        y <<= 1;
    if (x < 0)
-		xorigin = 1 - x;
+        xorigin = 1 - x;
    if (y < 0)
-	  yorigin = 1 - y;
+        yorigin = 1 - y;

-//	DPRINTVALHEX("radeonfb: RADEONSetCursorPosition: cursor_start ",rinfo->cursor_start);
-//	DPRINTVAL(" x ",x);
-//	DPRINTVAL(" y ",y);
-//	DPRINT("\r\n");
+    //	DPRINTVALHEX("radeonfb: RADEONSetCursorPosition: cursor_start ",rinfo->cursor_start);
+    //	DPRINTVAL(" x ",x);
+    //	DPRINTVAL(" y ",y);
+    //	DPRINT("\r\n");

-	OUTREG(CUR_HORZ_VERT_OFF, (CUR_LOCK  | (xorigin << 16) | yorigin));
-	OUTREG(CUR_HORZ_VERT_POSN, (CUR_LOCK | ((xorigin ? 0 : x) << 16) | (yorigin ? 0 : y)));
-	OUTREG(CUR_OFFSET, rinfo->cursor_start + yorigin * 256);
-	rinfo->cursor_x = (unsigned long)x;
+    OUTREG(CUR_HORZ_VERT_OFF, (CUR_LOCK  | (xorigin << 16) | yorigin));
+    OUTREG(CUR_HORZ_VERT_POSN, (CUR_LOCK | ((xorigin ? 0 : x) << 16) | (yorigin ? 0 : y)));
+    OUTREG(CUR_OFFSET, rinfo->cursor_start + yorigin * 256);
+    rinfo->cursor_x = (unsigned long)x;
    if (mode->vmode & FB_VMODE_DOUBLE)
        rinfo->cursor_y = (unsigned long) y >> 1;
-	else
+    else
        rinfo->cursor_y = (unsigned long) y;
 }

@@ -144,192 +144,192 @@ void radeon_set_cursor_position(struct fb_info *info, int x, int y)
 */
 void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsigned short *data, int zoom)
 {
-	struct radeonfb_info *rinfo = info->par;
-	unsigned long *d = (unsigned long *)((unsigned long)rinfo->fb_base+rinfo->cursor_start);
-	unsigned long save = 0;
-	unsigned short chunk, mchunk;
-	unsigned long i, j, k;
-	CURSOR_SWAPPING_DECL
+    struct radeonfb_info *rinfo = info->par;
+    unsigned long *d = (unsigned long *)((unsigned long)rinfo->fb_base+rinfo->cursor_start);
+    unsigned long save = 0;
+    unsigned short chunk, mchunk;
+    unsigned long i, j, k;
+    CURSOR_SWAPPING_DECL

-//	DPRINTVALHEX("radeonfb: RADEONLoadCursorImage: cursor_start ",rinfo->cursor_start);
-//	DPRINT("\r\n");
+            //	DPRINTVALHEX("radeonfb: RADEONLoadCursorImage: cursor_start ",rinfo->cursor_start);
+            //	DPRINT("\r\n");

-	save = INREG(CRTC_GEN_CNTL) & ~(unsigned long) (3 << 20);
-	save |= (unsigned long) (2 << 20);
-	OUTREG(CRTC_GEN_CNTL, save & (unsigned long)~CRTC_CUR_EN);
+            save = INREG(CRTC_GEN_CNTL) & ~(unsigned long) (3 << 20);
+    save |= (unsigned long) (2 << 20);
+    OUTREG(CRTC_GEN_CNTL, save & (unsigned long)~CRTC_CUR_EN);

-	/*
-	 * Convert the bitmap to ARGB32.
-	 */
-	CURSOR_SWAPPING_START();
+    /*
+     * Convert the bitmap to ARGB32.
+     */
+    CURSOR_SWAPPING_START();
 #define ARGB_PER_CHUNK	(8 * sizeof (chunk))
-	switch(zoom)
-	{
-	case 1:
-	default:
-        for (i = 0; i < CURSOR_HEIGHT; i++)
-		{
-            if (i < 16)
-			{
-				mchunk = *mask++;
-				chunk = *data++;
-			}
-			else
-				mchunk = chunk = 0;
-            for (j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j++)
-			{
-                for (k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
-				{
-                    if (mchunk & 0x8000)
-					{
-                        if (chunk & 0x8000)
-							*d++ = 0xff000000; /* Black, fully opaque. */				
-						else
-							*d++ = 0xffffffff; /* White, fully opaque. */
-					}			
-					else
-						*d++ = 0x00000000; /* White/Black, fully transparent. */			
-				}
-			}
-		}
-		break;
-	case 2:
-        for (i = 0; i < CURSOR_HEIGHT; i++)
-		{
-            if (i < 16*2)
-			{
-				mchunk = *mask;
-				chunk = *data;
-                if ((i & 1) == 1)
-				{
-					mask++;
-					data++;
-				}		
-			}
-			else
-				mchunk = chunk = 0;
-            for (j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j+=2)
-			{
-                for (k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
-				{
-                    if (mchunk & 0x8000)
-					{
-                        if (chunk & 0x8000)
-						{
-							*d++ = 0xff000000; /* Black, fully opaque. */				
-							*d++ = 0xff000000; 
-						}
-						else
-						{
-							*d++ = 0xffffffff; /* White, fully opaque. */
-							*d++ = 0xffffffff;							
-						}
-					}			
-					else
-					{
-						*d++ = 0x00000000; /* White/Black, fully transparent. */			
-						*d++ = 0x00000000;
-					}
-				}
-			}
-		}
-		break;
-	case 4:
-        for (i = 0; i < CURSOR_HEIGHT; i++)
-		{
-            if (i < 16 * 4)
-			{
-				mchunk = *mask;
-				chunk = *data;
-                if ((i & 3) == 3)
-				{
-					mask++;
-					data++;
-				}		
-			}
-			else
-				mchunk = chunk = 0;
-            for (j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j+=4)
-			{
-                for (k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
-				{
-                    if (mchunk & 0x8000)
-					{
-                        if (chunk & 0x8000)
-						{
-							*d++ = 0xff000000; /* Black, fully opaque. */				
-							*d++ = 0xff000000; 
-							*d++ = 0xff000000;
-							*d++ = 0xff000000;
-						}
-						else
-						{
-							*d++ = 0xffffffff; /* White, fully opaque. */
-							*d++ = 0xffffffff;							
-							*d++ = 0xffffffff;
-							*d++ = 0xffffffff;				
-						}
-					}			
-					else
-					{
-						*d++ = 0x00000000; /* White/Black, fully transparent. */			
-						*d++ = 0x00000000;
-						*d++ = 0x00000000;
-						*d++ = 0x00000000;
-					}
-				}
-			}
-		}
-		break;
-	}
-	CURSOR_SWAPPING_END();
-	rinfo->cursor_bg = 0xffffffff; /* White, fully opaque. */
-	rinfo->cursor_fg = 0xff000000; /* Black, fully opaque. */		
-	OUTREG(CRTC_GEN_CNTL, save);
+    switch(zoom)
+    {
+        case 1:
+        default:
+            for (i = 0; i < CURSOR_HEIGHT; i++)
+            {
+                if (i < 16)
+                {
+                    mchunk = *mask++;
+                    chunk = *data++;
+                }
+                else
+                    mchunk = chunk = 0;
+                for (j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j++)
+                {
+                    for (k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
+                    {
+                        if (mchunk & 0x8000)
+                        {
+                            if (chunk & 0x8000)
+                                *d++ = 0xff000000; /* Black, fully opaque. */
+                            else
+                                *d++ = 0xffffffff; /* White, fully opaque. */
+                        }
+                        else
+                            *d++ = 0x00000000; /* White/Black, fully transparent. */
+                    }
+                }
+            }
+            break;
+        case 2:
+            for (i = 0; i < CURSOR_HEIGHT; i++)
+            {
+                if (i < 16*2)
+                {
+                    mchunk = *mask;
+                    chunk = *data;
+                    if ((i & 1) == 1)
+                    {
+                        mask++;
+                        data++;
+                    }
+                }
+                else
+                    mchunk = chunk = 0;
+                for (j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j+=2)
+                {
+                    for (k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
+                    {
+                        if (mchunk & 0x8000)
+                        {
+                            if (chunk & 0x8000)
+                            {
+                                *d++ = 0xff000000; /* Black, fully opaque. */
+                                *d++ = 0xff000000;
+                            }
+                            else
+                            {
+                                *d++ = 0xffffffff; /* White, fully opaque. */
+                                *d++ = 0xffffffff;
+                            }
+                        }
+                        else
+                        {
+                            *d++ = 0x00000000; /* White/Black, fully transparent. */
+                            *d++ = 0x00000000;
+                        }
+                    }
+                }
+            }
+            break;
+        case 4:
+            for (i = 0; i < CURSOR_HEIGHT; i++)
+            {
+                if (i < 16 * 4)
+                {
+                    mchunk = *mask;
+                    chunk = *data;
+                    if ((i & 3) == 3)
+                    {
+                        mask++;
+                        data++;
+                    }
+                }
+                else
+                    mchunk = chunk = 0;
+                for (j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j+=4)
+                {
+                    for (k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
+                    {
+                        if (mchunk & 0x8000)
+                        {
+                            if (chunk & 0x8000)
+                            {
+                                *d++ = 0xff000000; /* Black, fully opaque. */
+                                *d++ = 0xff000000;
+                                *d++ = 0xff000000;
+                                *d++ = 0xff000000;
+                            }
+                            else
+                            {
+                                *d++ = 0xffffffff; /* White, fully opaque. */
+                                *d++ = 0xffffffff;
+                                *d++ = 0xffffffff;
+                                *d++ = 0xffffffff;
+                            }
+                        }
+                        else
+                        {
+                            *d++ = 0x00000000; /* White/Black, fully transparent. */
+                            *d++ = 0x00000000;
+                            *d++ = 0x00000000;
+                            *d++ = 0x00000000;
+                        }
+                    }
+                }
+            }
+            break;
+    }
+    CURSOR_SWAPPING_END();
+    rinfo->cursor_bg = 0xffffffff; /* White, fully opaque. */
+    rinfo->cursor_fg = 0xff000000; /* Black, fully opaque. */
+    OUTREG(CRTC_GEN_CNTL, save);
 }

 /* Hide hardware cursor. */
 void radeon_hide_cursor(struct fb_info *info)
 {
-	struct radeonfb_info *rinfo = info->par;
+    struct radeonfb_info *rinfo = info->par;

-//	DPRINT("radeonfb: RADEONHideCursor\r\n");
-	OUTREGP(CRTC_GEN_CNTL, 0, ~CRTC_CUR_EN);
-	rinfo->cursor_show = 0;
+    //	DPRINT("radeonfb: RADEONHideCursor\r\n");
+    OUTREGP(CRTC_GEN_CNTL, 0, ~CRTC_CUR_EN);
+    rinfo->cursor_show = 0;
 }

 /* Show hardware cursor. */
 void radeon_show_cursor(struct fb_info *info)
 {
-	struct radeonfb_info *rinfo = info->par;
+    struct radeonfb_info *rinfo = info->par;

-//	DPRINT("radeonfb: RADEONShowCursor\r\n");
-	OUTREGP(CRTC_GEN_CNTL, CRTC_CUR_EN, ~CRTC_CUR_EN);
-	rinfo->cursor_show = 1;
+    //	DPRINT("radeonfb: RADEONShowCursor\r\n");
+    OUTREGP(CRTC_GEN_CNTL, CRTC_CUR_EN, ~CRTC_CUR_EN);
+    rinfo->cursor_show = 1;
 }

 /* Initialize hardware cursor support. */
 long radeon_cursor_init(struct fb_info *info)
 {
-	struct radeonfb_info *rinfo = info->par;
-	int size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT;
-	unsigned long fbarea = offscreen_alloc(rinfo->info, size_bytes + 256);
+    struct radeonfb_info *rinfo = info->par;
+    int size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT;
+    unsigned long fbarea = offscreen_alloc(rinfo->info, size_bytes + 256);

    dbg("radeonfb: %s: fbarea: %p\r\n", fbarea);

    if (!fbarea)
-		rinfo->cursor_start = 0;
-	else
-	{
-		unsigned short data[16], mask[16];
+        rinfo->cursor_start = 0;
+    else
+    {
+        unsigned short data[16], mask[16];

-		memset(data, 0, sizeof(data));
-		memset(mask, 0, sizeof(data));		
-		rinfo->cursor_start = RADEON_ALIGN(fbarea - (unsigned long) rinfo->fb_base, 256);
-		rinfo->cursor_end = rinfo->cursor_start + size_bytes;
-		radeon_load_cursor_image(info, mask, data, 1);
-	}
-	dbg("radeonfb: %s cursor_start: %p\r\n", rinfo->cursor_start);
+        memset(data, 0, sizeof(data));
+        memset(mask, 0, sizeof(data));
+        rinfo->cursor_start = RADEON_ALIGN(fbarea - (unsigned long) rinfo->fb_base, 256);
+        rinfo->cursor_end = rinfo->cursor_start + size_bytes;
+        radeon_load_cursor_image(info, mask, data, 1);
+    }
+    dbg("radeonfb: %s cursor_start: %p\r\n", rinfo->cursor_start);

-	return (rinfo->cursor_start ? fbarea : 0);
+    return (rinfo->cursor_start ? fbarea : 0);
 }
--- a/radeon/radeon_monitor.c
+++ b/radeon/radeon_monitor.c
--- a/spi/dspi.c
+++ b/spi/dspi.c
@@ -30,79 +30,79 @@

 struct baudrate
 {
-	int br_divisor;
-	int pbr_divisor;
-	int	divider;
+    int br_divisor;
+    int pbr_divisor;
+    int	divider;
 };

 static const int system_clock = 132000000;	/* System clock in Hz */

-struct baudrate baudrates[] =
+static struct baudrate baudrates[] =
 {
-	{ 0b0000, 0b00,	4 },
-	{ 0b0000, 0b01,	6 },
-	{ 0b0001, 0b00,	8 },
-	{ 0b0000, 0b10,	10 },
-	{ 0b0001, 0b01,	12 },
-	{ 0b0010, 0b00,	12 },
-	{ 0b0000, 0b11,	14 },
-	{ 0b0011, 0b00,	16 },
-	{ 0b0010, 0b01,	18 },
-	{ 0b0001, 0b10,	20 },
-	{ 0b0011, 0b01,	24 },
-	{ 0b0001, 0b11,	28 },
-	{ 0b0010, 0b10,	30 },
-	{ 0b0100, 0b00,	32 },
-	{ 0b0011, 0b10,	40 },
-	{ 0b0010, 0b11,	42 },
-	{ 0b0100, 0b01,	48 },
-	{ 0b0011, 0b11,	56 },
-	{ 0b0101, 0b00,	64 },
-	{ 0b0100, 0b10,	80 },
-	{ 0b0101, 0b01,	96 },
-	{ 0b0100, 0b11,	112 },
-	{ 0b0110, 0b00,	128 },
-	{ 0b0101, 0b10,	160 },
-	{ 0b0110, 0b01,	192 },
-	{ 0b0101, 0b11,	224 },
-	{ 0b0111, 0b00,	256 },
-	{ 0b0110, 0b10,	320 },
-	{ 0b0111, 0b01,	384 },
-	{ 0b0110, 0b11,	448 },
-	{ 0b1000, 0b00,	512 },
-	{ 0b0111, 0b10,	640 },
-	{ 0b1000, 0b01,	768 },
-	{ 0b0111, 0b11,	896 },
-	{ 0b1001, 0b00,	1024 },
-	{ 0b1000, 0b10,	1280 },
-	{ 0b1001, 0b01,	1536 },
-	{ 0b1000, 0b11,	1792 },
-	{ 0b1010, 0b00,	2048 },
-	{ 0b1001, 0b10,	2560 },
-	{ 0b1010, 0b01,	3072 },
-	{ 0b1001, 0b11,	3584 },
-	{ 0b1011, 0b00,	4096 },
-	{ 0b1010, 0b10,	5120 },
-	{ 0b1011, 0b01,	6144 },
-	{ 0b1010, 0b11,	7168 },
-	{ 0b1100, 0b00,	8192 },
-	{ 0b1011, 0b10,	10240 },
-	{ 0b1100, 0b01,	12288 },
-	{ 0b1011, 0b11,	14336 },
-	{ 0b1101, 0b00,	16384 },
-	{ 0b1100, 0b10,	20480 },
-	{ 0b1101, 0b01,	24576 },
-	{ 0b1100, 0b11,	28672 },
-	{ 0b1110, 0b00,	32768 },
-	{ 0b1101, 0b10,	40960 },
-	{ 0b1110, 0b01,	49152 },
-	{ 0b1101, 0b11,	57344 },
-	{ 0b1111, 0b00,	65536 },
-	{ 0b1110, 0b10,	81920 },
-	{ 0b1111, 0b01,	98304 },
-	{ 0b1110, 0b11,	114688 },
-	{ 0b1111, 0b10,	163840 },
-	{ 0b1111, 0b11,	229376 },
+    { 0b0000, 0b00,	4 },
+    { 0b0000, 0b01,	6 },
+    { 0b0001, 0b00,	8 },
+    { 0b0000, 0b10,	10 },
+    { 0b0001, 0b01,	12 },
+    { 0b0010, 0b00,	12 },
+    { 0b0000, 0b11,	14 },
+    { 0b0011, 0b00,	16 },
+    { 0b0010, 0b01,	18 },
+    { 0b0001, 0b10,	20 },
+    { 0b0011, 0b01,	24 },
+    { 0b0001, 0b11,	28 },
+    { 0b0010, 0b10,	30 },
+    { 0b0100, 0b00,	32 },
+    { 0b0011, 0b10,	40 },
+    { 0b0010, 0b11,	42 },
+    { 0b0100, 0b01,	48 },
+    { 0b0011, 0b11,	56 },
+    { 0b0101, 0b00,	64 },
+    { 0b0100, 0b10,	80 },
+    { 0b0101, 0b01,	96 },
+    { 0b0100, 0b11,	112 },
+    { 0b0110, 0b00,	128 },
+    { 0b0101, 0b10,	160 },
+    { 0b0110, 0b01,	192 },
+    { 0b0101, 0b11,	224 },
+    { 0b0111, 0b00,	256 },
+    { 0b0110, 0b10,	320 },
+    { 0b0111, 0b01,	384 },
+    { 0b0110, 0b11,	448 },
+    { 0b1000, 0b00,	512 },
+    { 0b0111, 0b10,	640 },
+    { 0b1000, 0b01,	768 },
+    { 0b0111, 0b11,	896 },
+    { 0b1001, 0b00,	1024 },
+    { 0b1000, 0b10,	1280 },
+    { 0b1001, 0b01,	1536 },
+    { 0b1000, 0b11,	1792 },
+    { 0b1010, 0b00,	2048 },
+    { 0b1001, 0b10,	2560 },
+    { 0b1010, 0b01,	3072 },
+    { 0b1001, 0b11,	3584 },
+    { 0b1011, 0b00,	4096 },
+    { 0b1010, 0b10,	5120 },
+    { 0b1011, 0b01,	6144 },
+    { 0b1010, 0b11,	7168 },
+    { 0b1100, 0b00,	8192 },
+    { 0b1011, 0b10,	10240 },
+    { 0b1100, 0b01,	12288 },
+    { 0b1011, 0b11,	14336 },
+    { 0b1101, 0b00,	16384 },
+    { 0b1100, 0b10,	20480 },
+    { 0b1101, 0b01,	24576 },
+    { 0b1100, 0b11,	28672 },
+    { 0b1110, 0b00,	32768 },
+    { 0b1101, 0b10,	40960 },
+    { 0b1110, 0b01,	49152 },
+    { 0b1101, 0b11,	57344 },
+    { 0b1111, 0b00,	65536 },
+    { 0b1110, 0b10,	81920 },
+    { 0b1111, 0b01,	98304 },
+    { 0b1110, 0b11,	114688 },
+    { 0b1111, 0b10,	163840 },
+    { 0b1111, 0b11,	229376 },
 };

 /*
@@ -110,28 +110,28 @@ struct baudrate baudrates[] =
 */
 int dspi_set_baudrate(int rate)
 {
-	int set_baudrate = 0;
-	int br;
-	int pbr;
-	int i;
+    int set_baudrate = 0;
+    int br;
+    int pbr;
+    int i;

-	for (i = sizeof(baudrates) / sizeof(struct baudrate) - 1; i >= 0; i--)
-	{
-		set_baudrate = system_clock / baudrates[i].divider;
+    for (i = sizeof(baudrates) / sizeof(struct baudrate) - 1; i >= 0; i--)
+    {
+        set_baudrate = system_clock / baudrates[i].divider;

-		if (set_baudrate > rate)
-		{
-			continue;
-		}
-		br = baudrates[i].br_divisor;
-		pbr = baudrates[i].pbr_divisor;
+        if (set_baudrate > rate)
+        {
+            continue;
+        }
+        br = baudrates[i].br_divisor;
+        pbr = baudrates[i].pbr_divisor;

-		/* TODO: set br and pbr here */
+        /* TODO: set br and pbr here */

-		return set_baudrate;
-	}
+        return set_baudrate;
+    }

-	return 0;
+    return 0;
 }

 static uint32_t dspi_fifo_val = MCF_DSPI_DTFR_CTCNT;
@@ -141,20 +141,20 @@ static uint32_t dspi_fifo_val = MCF_DSPI_DTFR_CTCNT;
 */
 uint8_t dspi_xchg_byte(int device, uint8_t byte, int last)
 {
-	uint32_t fifo;
-	uint8_t res;
+    uint32_t fifo;
+    uint8_t res;

-	fifo =  dspi_fifo_val | (byte & 0xff);			/* transfer bytes only */
-	fifo |= (last ? MCF_DSPI_DTFR_EOQ : 0);			/* mark last transfer */
-	MCF_DSPI_DTFR = fifo;
-	while (! (MCF_DSPI_DSR & MCF_DSPI_DSR_TCF));	/* wait until DSPI transfer complete */
-	fifo = MCF_DSPI_DRFR;							/* read transferred word */
+    fifo =  dspi_fifo_val | (byte & 0xff);			/* transfer bytes only */
+    fifo |= (last ? MCF_DSPI_DTFR_EOQ : 0);			/* mark last transfer */
+    MCF_DSPI_DTFR = fifo;
+    while (! (MCF_DSPI_DSR & MCF_DSPI_DSR_TCF));	/* wait until DSPI transfer complete */
+    fifo = MCF_DSPI_DRFR;							/* read transferred word */

-	MCF_DSPI_DSR = -1;		 						/* clear DSPI status register */
+    MCF_DSPI_DSR = -1;		 						/* clear DSPI status register */

-	res = fifo & 0xff;
+    res = fifo & 0xff;

-	return res;
+    return res;
 }

 /* Receive multiple byte with 0xff as output
@@ -164,11 +164,11 @@ uint8_t dspi_xchg_byte(int device, uint8_t byte, int last)
 */
 static void dspi_rcv_byte_multi(int device, uint8_t *buff, uint32_t count)
 {
-	int i;
+    int i;

-	for (i = 0; i < count - 1; i++)
-		*buff++ = dspi_xchg_byte(device, 0xff, 0);
-	*buff++ = dspi_xchg_byte(device, 0xff, 1); 		/* transfer last byte and stop transmission */
+    for (i = 0; i < count - 1; i++)
+        *buff++ = dspi_xchg_byte(device, 0xff, 0);
+    *buff++ = dspi_xchg_byte(device, 0xff, 1); 		/* transfer last byte and stop transmission */
 }

 /* Send multiple byte, discard input
@@ -178,10 +178,10 @@ static void dspi_rcv_byte_multi(int device, uint8_t *buff, uint32_t count)
 */
 static void dspi_xmt_byte_multi(int device, const uint8_t *buff, uint32_t btx)
 {
-	int i;
+    int i;

-	for (i = 0; i < btx - 1; i++)
-		dspi_xchg_byte(device, *buff++, 0);
-	dspi_xchg_byte(device, *buff++, 1);				/* transfer last byte and indicate end of transmission */
+    for (i = 0; i < btx - 1; i++)
+        dspi_xchg_byte(device, *buff++, 0);
+    dspi_xchg_byte(device, *buff++, 1);				/* transfer last byte and indicate end of transmission */
 }

--- a/spi/mmc.c
+++ b/spi/mmc.c
--- a/spi/sd_card.c
+++ b/spi/sd_card.c
@@ -41,81 +41,81 @@
 */
 void sd_card_init(void)
 {
-	DRESULT res;
-	FATFS fs;
-	FRESULT fres;
+    DRESULT res;
+    FATFS fs;
+    FRESULT fres;

-	disk_initialize(0);
-	res = disk_status(0);
-	xprintf("disk status of SD card is %d\r\n", res);
-	if (res == RES_OK)
-	{
-		fres = f_mount(0, &fs);
-		xprintf("mount status of SD card fs is %d\r\n", fres);
-		if (fres == FR_OK)
-		{
-			DIR directory;
-			FIL file;
+    disk_initialize(0);
+    res = disk_status(0);
+    xprintf("disk status of SD card is %d\r\n", res);
+    if (res == RES_OK)
+    {
+        fres = f_mount(0, &fs);
+        xprintf("mount status of SD card fs is %d\r\n", fres);
+        if (fres == FR_OK)
+        {
+            DIR directory;
+            FIL file;

-			fres = f_opendir(&directory, "\\");
-			if (fres == FR_OK)
-			{
-				FILINFO fi;
+            fres = f_opendir(&directory, "\\");
+            if (fres == FR_OK)
+            {
+                FILINFO fi;

-				while (((fres = f_readdir(&directory, &fi)) == FR_OK) && fi.fname[0])
-				{
-					xprintf("%13.13s %d\r\n", fi.fname, fi.fsize);
-				}
-			}
-			else
-			{
-				xprintf("could not open directory \"\\\" on SD-card! Error code: %d\r\n", fres);
-			}
+                while (((fres = f_readdir(&directory, &fi)) == FR_OK) && fi.fname[0])
+                {
+                    xprintf("%13.13s %d\r\n", fi.fname, fi.fsize);
+                }
+            }
+            else
+            {
+                xprintf("could not open directory \"\\\" on SD-card! Error code: %d\r\n", fres);
+            }

-			/*
-			 * let's see if we find our boot flashing executable on disk
-			 */
-			fres = f_open(&file, FLASHCODE_NAME, FA_READ);
-			if (fres == FR_OK)
-			{
-				/*
-				 * yes, load and execute it
-				 *
-				 * FIXME: we will need some kind of user confirmation here
-				 * to avoid unwanted flashing or "bootsector viruses" before going productive
-				 */
-				uint32_t size;	/* length of code piece read */
-				uint32_t total_size = 0L;
-				int32_t start_time = MCF_SLT_SCNT(0);
-				int32_t end_time;
-				int32_t time = 0;
+            /*
+             * let's see if we find our boot flashing executable on disk
+             */
+            fres = f_open(&file, FLASHCODE_NAME, FA_READ);
+            if (fres == FR_OK)
+            {
+                /*
+                 * yes, load and execute it
+                 *
+                 * FIXME: we will need some kind of user confirmation here
+                 * to avoid unwanted flashing or "bootsector viruses" before going productive
+                 */
+                uint32_t size;	/* length of code piece read */
+                uint32_t total_size = 0L;
+                int32_t start_time = MCF_SLT_SCNT(0);
+                int32_t end_time;
+                int32_t time = 0;

-				while ((fres = f_read(&file, (void *) FLASHCODE_ADDRESS, 1024 * 1000, &size)) == FR_OK && size > 0)
-				{
-					total_size += size / 1024;
-					xprintf("read hunk of %d bytes, total_size = %d kBytes\r\n", size, total_size);
-				}
-				end_time = MCF_SLT_SCNT(0);
-				time = (end_time - start_time) / 132L;
-				xprintf("result of f_read: %ld, %ld kbytes read\r\n", fres, total_size);
-				xprintf("time to load %s: %ld s\r\n", FLASHCODE_NAME, time / 1000 / 100);
-				xprintf("equals to about %ld kBytes/second\r\n", total_size / (time / 1000 / 100));
+                while ((fres = f_read(&file, (void *) FLASHCODE_ADDRESS, 1024 * 1000, &size)) == FR_OK && size > 0)
+                {
+                    total_size += size / 1024;
+                    xprintf("read hunk of %d bytes, total_size = %d kBytes\r\n", size, total_size);
+                }
+                end_time = MCF_SLT_SCNT(0);
+                time = (end_time - start_time) / 132L;
+                xprintf("result of f_read: %ld, %ld kbytes read\r\n", fres, total_size);
+                xprintf("time to load %s: %ld s\r\n", FLASHCODE_NAME, time / 1000 / 100);
+                xprintf("equals to about %ld kBytes/second\r\n", total_size / (time / 1000 / 100));

-			}
-			f_close(&file);
+            }
+            f_close(&file);

-			fres = f_open(&file, WELCOME_NAME, FA_READ);
-			if (fres == FR_OK)
-			{
-				char line[128];
+            fres = f_open(&file, WELCOME_NAME, FA_READ);
+            if (fres == FR_OK)
+            {
+                char line[128];

-				while (f_gets(line, sizeof(line), &file))
-				{
-					xprintf("%s", line);
-				}
-			}
-			f_close(&file);
-		}
-		f_mount(0, 0L);	/* release work area */
-	}
+                while (f_gets(line, sizeof(line), &file))
+                {
+                    xprintf("%s", line);
+                }
+            }
+            f_close(&file);
+        }
+        f_mount(0, 0L);	/* release work area */
+    }
 }
--- a/sys/BaS.c
+++ b/sys/BaS.c
@@ -31,6 +31,7 @@
 #include "bas_printf.h"
 #include "bas_string.h"
 #include "bas_types.h"
+#include "bas_utils.h"
 #include "sd_card.h"
 #include "wait.h"

@@ -179,8 +180,8 @@ void nvram_init(void)
    for (i = 0; i < 64; i++)
    {
        uint8_t data = read_pic_byte();
-        *(volatile uint8_t*)0xffff8961 = i;
-        *(volatile uint8_t*)0xffff8963 = data;
+        * (volatile uint8_t*) 0xffff8961 = i;
+        * (volatile uint8_t*) 0xffff8963 = data;
    }

    xprintf("finished\r\n");
@@ -195,13 +196,13 @@ void acia_init()
 {
    xprintf("init ACIA: ");
    /* init ACIA */
-    KBD_ACIA_CONTROL = 3;       /* master reset */
+    KBD_ACIA_CONTROL = 3;                   /* master reset */
    NOP();

-    MIDI_ACIA_CONTROL = 3;      /* master reset */
+    MIDI_ACIA_CONTROL = 3;                  /* master reset */
    NOP();

-    KBD_ACIA_CONTROL = 0x96;    /* clock div = 64, 8N1, RTS low, TX int disable, RX int enable */
+    KBD_ACIA_CONTROL = 0x96;                /* clock div = 64, 8N1, RTS low, TX int disable, RX int enable */
    NOP();

    MFP_INTR_IN_SERVICE_A = 0xff;
@@ -217,11 +218,12 @@ void enable_coldfire_interrupts()
 {
    xprintf("enable interrupts: ");
 #if defined(MACHINE_FIREBEE)
-    FBEE_INTR_CONTROL = 0L;                /* disable all interrupts */
+    FBEE_INTR_CONTROL = 0L;                 /* disable all interrupts */
 #endif /* MACHINE_FIREBEE */

    MCF_EPORT_EPPAR = 0xaaa8;               /* all interrupts on falling edge */

+#ifdef _NOT_USED_
 #if defined(MACHINE_FIREBEE)
    /*
     * TIN0 on the Coldfire is connected to the FPGA. TIN0 triggers every write
@@ -232,13 +234,20 @@ void enable_coldfire_interrupts()
            MCF_GPT_GMS_TMS(1);             /* route GPT0 interrupt on interrupt controller */
    MCF_INTC_ICR62 = MCF_INTC_ICR_IL(7) |
                     MCF_INTC_ICR_IP(6);    /* interrupt level 7, interrupt priority 7 */
+    MCF_INTC_IMRH = 0xbffffffe;             /* psc3 and timer 0 int on */
+#endif
+#endif
+    xprintf("finished\r\n");
+}

-
+void enable_pci_interrupts()
+{
+    dbg("enable PCI interrupts\r\n");
    MCF_EPORT_EPIER = 0xfe;                 /* int 1-7 on */
    MCF_EPORT_EPFR = 0xff;                  /* clear all pending interrupts */
    MCF_INTC_IMRL = 0xffffff00;             /* int 1-7 on */
-    //MCF_INTC_IMRH = 0xbffffffe;             /* psc3 and timer 0 int on */
    MCF_INTC_IMRH = 0;
+#if defined(MACHINE_FIREBEE)
    FBEE_INTR_ENABLE = FBEE_INTR_INT_IRQ7 | /* enable pseudo bus error */
            FBEE_INTR_INT_MFP_IRQ6 |        /* enable MFP interrupts */
            FBEE_INTR_INT_FPGA_IRQ5 |       /* enable Firebee (PIC, PCI, ETH PHY, DVI, DSP) interrupts */
@@ -247,15 +256,26 @@ void enable_coldfire_interrupts()
            FBEE_INTR_PCI_INTB |
            FBEE_INTR_PCI_INTC |
            FBEE_INTR_PCI_INTD;
-#endif
+            ;
+#elif defined(MACHINE_M5484LITE)
+    /*
+     * MCF 5484 interrupts are configured at the CPLD for the FireEngine
+     */

-    xprintf("finished\r\n");
+    /* TODO: enable PCI interrupts on the LITEKIT */
+#elif defined(MACHINE_M54455)
+    /* MCF 54455 interrupts are configured at the FPGA */
+
+    /* TODO: enable PCI interrupts on the MCF54455 */
+#else
+#error unknown machine!
+#endif
 }

 void disable_coldfire_interrupts()
 {
 #if defined(MACHINE_FIREBEE)
-    FBEE_INTR_ENABLE = 0;      /* disable all interrupts */
+    FBEE_INTR_ENABLE = 0;                   /* disable all interrupts */
 #endif /* MACHINE_FIREBEE */

    MCF_EPORT_EPIER = 0x0;
@@ -267,22 +287,42 @@ void disable_coldfire_interrupts()

 NIF nif1;
 #if defined(MACHINE_M5484LITE)
+    /*
+     * on the MCF 5484 LITEKIT, the second FEC interface is usable
+     */
 NIF nif2;
 #endif

+bool spurious_interrupt_handler(void *arg1, void *arg2)
+{
+    dbg("IMRH=%lx, IMRL=%lx\r\n", MCF_INTC_IMRH, MCF_INTC_IMRL);
+    dbg("IPRH=%lx, IPRL=%lx\r\n", MCF_INTC_IPRH, MCF_INTC_IPRL);
+    dbg("IRLR=%x\r\n", MCF_INTC_IRLR);
+
+    return true;
+}
+
 /*
 * initialize the interrupt handler tables to dispatch interrupt requests from Coldfire devices
 */
 void init_isr(void)
 {
-    isr_init();     /* need to call that explicitely, otherwise isr table might be full */
+    isr_init();                             /* need to call that explicitely, otherwise isr table might be full */
+
+    /*
+     * register spurious interrupt handler
+     */
+    if (!isr_register_handler(24, 6, 6, spurious_interrupt_handler, NULL, NULL))
+    {
+        dbg("unable to register spurious interrupt handler\r\n");
+    }

    /*
     * register the FEC interrupt handler
     */
    if (!isr_register_handler(64 + INT_SOURCE_FEC0, 5, 1, fec0_interrupt_handler, NULL, (void *) &nif1))
    {
-        err("unable to register isr for FEC0\r\n");
+        dbg("unable to register isr for FEC0\r\n");
    }

    /*
@@ -291,16 +331,16 @@ void init_isr(void)

    if (!isr_register_handler(64 + INT_SOURCE_DMA, 5, 3, dma_interrupt_handler, NULL, NULL))
    {
-        err("unable to register isr for DMA\r\n");
+        dbg("unable to register isr for DMA\r\n");
    }

-#ifdef MACHINE_FIREBEE
+#if defined(MACHINE_FIREBEE)
    /*
     * register GPT0 timer interrupt vector
     */
    if (!isr_register_handler(64 + INT_SOURCE_GPT0, 5, 2, gpt0_interrupt_handler, NULL, NULL))
    {
-        err("unable to register isr for GPT0 timer\r\n");
+        dbg("unable to register isr for GPT0 timer\r\n");
    }

    /*
@@ -308,7 +348,7 @@ void init_isr(void)
     */
    if (!isr_register_handler(64 + INT_SOURCE_PSC3, 5, 5, pic_interrupt_handler, NULL, NULL))
    {
-        err("Error: unable to register ISR for PSC3\r\n");
+        dbg("Error: unable to register ISR for PSC3\r\n");
    }
 #endif /* MACHINE_FIREBEE */

@@ -317,20 +357,20 @@ void init_isr(void)
     */
    if (!isr_register_handler(64 + INT_SOURCE_XLBPCI, 7, 0, xlbpci_interrupt_handler, NULL, NULL))
    {
-        err("Error: unable to register isr for XLB PCI interrupts\r\n");
+        dbg("Error: unable to register isr for XLB PCI interrupts\r\n");
    }

-    MCF_XLB_XARB_IMR = MCF_XLB_XARB_IMR_SEAE |      /* slave error acknowledge interrupt */
-                       MCF_XLB_XARB_IMR_MME |       /* multiple master at prio 0 interrupt */
-                       MCF_XLB_XARB_IMR_TTAE |      /* TT address only interrupt */
-                       MCF_XLB_XARB_IMR_TTRE |      /* TT reserved interrupt enable */
-                       MCF_XLB_XARB_IMR_ECWE |      /* external control word interrupt */
-                       MCF_XLB_XARB_IMR_TTME |      /* TBST/TSIZ mismatch interrupt */
-                       MCF_XLB_XARB_IMR_BAE;        /* bus activity tenure timeout interrupt */
+    MCF_XLB_XARB_IMR = MCF_XLB_XARB_IMR_SEAE |          /* slave error acknowledge interrupt */
+                       MCF_XLB_XARB_IMR_MME |           /* multiple master at prio 0 interrupt */
+                       MCF_XLB_XARB_IMR_TTAE |          /* TT address only interrupt */
+                       MCF_XLB_XARB_IMR_TTRE |          /* TT reserved interrupt enable */
+                       MCF_XLB_XARB_IMR_ECWE |          /* external control word interrupt */
+                       MCF_XLB_XARB_IMR_TTME |          /* TBST/TSIZ mismatch interrupt */
+                       MCF_XLB_XARB_IMR_BAE;            /* bus activity tenure timeout interrupt */

-    if (!isr_register_handler(64 + INT_SOURCE_PCIARB, 7, 1, pciarb_interrupt_handler, NULL, NULL))
+    if (!isr_register_handler(64 + INT_SOURCE_PCIARB, 5, 0, pciarb_interrupt_handler, NULL, NULL))
    {
-        err("Error: unable to register isr for PCIARB interrupts\r\n");
+        dbg("Error: unable to register isr for PCIARB interrupts\r\n");

        return;
    }
@@ -352,10 +392,11 @@ void BaS(void)
    mmu_init();
    xprintf("finished\r\n");

-    xprintf("copy EmuTOS: ");
-
+    xprintf("initialize Coldfire DMA: ");
    dma_init();
+    xprintf("finished\r\n");

+    xprintf("copy EmuTOS: ");
    /* copy EMUTOS */
    src = (uint8_t *) EMUTOS;
    dma_memcpy(dst, src, EMUTOS_SIZE);
@@ -373,7 +414,7 @@ void BaS(void)
    NOP();                                      /* force pipeline sync */
    xprintf("finished\r\n");

-    #ifdef MACHINE_FIREBEE
+#if defined(MACHINE_FIREBEE)
    xprintf("IDE reset: ");
    /* IDE reset */
    * (volatile uint8_t *) (0xffff8802 - 2) = 14;
@@ -384,16 +425,17 @@ void BaS(void)

    xprintf("finished\r\n");
    xprintf("enable video: ");
+
    /*
     * video setup (25MHz)
     */
-    * (volatile uint32_t *) (0xf0000410 + 0) = 0x032002ba;  /* horizontal 640x480 */
-    * (volatile uint32_t *) (0xf0000410 + 4) = 0x020c020a;  /* vertical 640x480 */
-    * (volatile uint32_t *) (0xf0000410 + 8) = 0x0190015d;  /* horizontal 320x240 */
-    * (volatile uint32_t *) (0xf0000410 + 12) = 0x020C020A; /* vertical 320x230 */
+    * (volatile uint32_t *) 0xf0000410 = 0x032002ba;  /* horizontal 640x480 */
+    * (volatile uint32_t *) 0xf0000414 = 0x020c020a;  /* vertical 640x480 */
+    * (volatile uint32_t *) 0xf0000418 = 0x0190015d;  /* horizontal 320x240 */
+    * (volatile uint32_t *) 0xf000041c = 0x020c020a; /* vertical 320x230 */

    /* fifo on, refresh on, ddrcs and cke on, video dac on */
-    * (volatile uint32_t *) (0xf0000410 - 0x20) = 0x01070002;
+    * (volatile uint32_t *) 0xf0000400 = 0x01070082;

    xprintf("finished\r\n");
 #endif /* MACHINE_FIREBEE */
@@ -403,7 +445,7 @@ void BaS(void)
    /*
     * memory setup
     */
-    memset((void *) 0x400, 0, 0x400);
+    // memset((void *) 0x200, 0, 0x400);

 #if defined(MACHINE_FIREBEE)
    /* set Falcon bus control register */
@@ -442,16 +484,68 @@ void BaS(void)
    init_isr();

    enable_coldfire_interrupts();
-    dma_irq_enable();
+    MCF_INTC_IMRH = 0;
+    MCF_INTC_IMRL = 0;

+    dma_irq_enable();
+    fec_irq_enable(0, 5, 1);
+
+    enable_pci_interrupts();
    init_pci();
-    // video_init();
+    video_init();

    /* initialize USB devices */
-    //init_usb();
+    init_usb();

    set_ipl(7);     /* disable interrupts */

+    /*
+     * start FireTOS if DIP switch is set accordingly
+     */
+    if (!(DIP_SWITCH & (1 << 6)))
+    {
+        extern uint8_t _FIRETOS[];
+#define FIRETOS ((uint32_t)_FIRETOS) /* where FireTOS is stored in flash */
+
+        /* make sure MMU is disabled */
+        MCF_MMU_MMUCR = 0;  /* MMU off */
+        NOP();              /* force pipeline sync */
+
+
+        /*
+         * FireTOS wants to have the TOS system variables cleared
+         */
+        memset((void *) 0x400, 0, 0x400);
+
+        /* ST RAM */
+
+        * (uint32_t *) 0x42e = STRAM_END;   /* phystop TOS system variable */
+        * (uint32_t *) 0x420 = 0x752019f3;  /* memvalid TOS system variable */
+        * (uint32_t *) 0x43a = 0x237698aa;  /* memval2 TOS system variable */
+        * (uint32_t *) 0x51a = 0x5555aaaa;  /* memval3 TOS system variable */
+
+        /* TT-RAM */
+
+        * (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */
+        * (uint32_t *) 0x5a8 = 0x1357bd13;  /* ramvalid TOS system variable */
+
+        xprintf("call FireTOS\r\n");
+        /* Jump into FireTOS */
+        typedef void void_func(void);
+        void_func* FireTOS = (void_func*) FIRETOS;
+        FireTOS();  // Should never return
+    }
+
+    /*
+     * fix initial pc/sp in ST RAM for FreeMiNT. It expects valid values there
+     * like on original STs (where these values reside in ROM) and uses them on
+     * CTRL-ALT-DELETE reboots.
+     */
+    struct rom_header *bas_header = (struct rom_header *) TARGET_ADDRESS;
+    struct rom_header *stram_header = (struct rom_header *) 0x0;
+
+    *stram_header = *bas_header;
+
    xprintf("call EmuTOS\r\n");
    struct rom_header *os_header = (struct rom_header *) TOS;
    os_header->initial_pc();
--- a/sys/cache.c
+++ b/sys/cache.c
@@ -26,60 +26,61 @@

 void cacr_set(uint32_t value)
 {
-	extern uint32_t rt_cacr;
+    extern uint32_t rt_cacr;

-	rt_cacr = value;
-	__asm__ __volatile__("movec	%0, cacr\n\t"
-						 : /* output */
-						 : "r" (rt_cacr)
-						 : "memory" /* clobbers */);
+    rt_cacr = value;
+    __asm__ __volatile__(
+        "           movec	%0, cacr\n\t"
+        : /* output */
+        : "r" (rt_cacr)
+        : "memory" /* clobbers */);
 }

 uint32_t cacr_get(void)
 {
-	extern uint32_t rt_cacr;
+    extern uint32_t rt_cacr;

-	return rt_cacr;
+    return rt_cacr;
 }

 void disable_data_cache(void)
 {
-	flush_and_invalidate_caches();
-	cacr_set((cacr_get() | CF_CACR_DCINVA) & ~CF_CACR_DEC);
+    flush_and_invalidate_caches();
+    cacr_set((cacr_get() | CF_CACR_DCINVA) & ~CF_CACR_DEC);
 }

 void disable_instruction_cache(void)
 {
-	flush_and_invalidate_caches();
-	cacr_set((cacr_get() | CF_CACR_ICINVA) & ~CF_CACR_IEC);
+    flush_and_invalidate_caches();
+    cacr_set((cacr_get() | CF_CACR_ICINVA) & ~CF_CACR_IEC);
 }

 void enable_data_cache(void)
 {
-	cacr_set(cacr_get() & ~CF_CACR_DCINVA);
+    cacr_set(cacr_get() & ~CF_CACR_DCINVA);
 }

 void flush_and_invalidate_caches(void)
 {
-	__asm__ __volatile__(
-			"	clr.l		d0                  \n\t"
-			"	clr.l		d1                  \n\t"
-			"	move.l		d0,a0               \n\t"
-			"cfa_setloop:                       \n\t"
-			"	cpushl		bc,(a0)				| flush\n\t"
-			"	lea			0x10(a0),a0			| index+1\n\t"
-			"	addq.l		#1,d1				| index+1\n\t"
-			"	cmpi.w		#512,d1				| all sets?\n\t"
-			"	bne.s		cfa_setloop			| no->\n\t"
-			"	clr.l		d1                  \n\t"
-			"	addq.l		#1,d0               \n\t"
-			"	move.l		d0,a0               \n\t"
-			"	cmpi.w		#4,d0				| all ways?\n\t"
-			"	bne.s		cfa_setloop			| no->\n\t"
-			/* input */	:
-			/* output */	:
-			/* clobber */	: "cc", "d0", "d1", "a0"
-	);
+    __asm__ __volatile__(
+            "	clr.l		d0                  \n\t"
+            "	clr.l		d1                  \n\t"
+            "	move.l		d0,a0               \n\t"
+            "cfa_setloop:                       \n\t"
+            "	cpushl		bc,(a0)				| flush\n\t"
+            "	lea			0x10(a0),a0			| index+1\n\t"
+            "	addq.l		#1,d1				| index+1\n\t"
+            "	cmpi.w		#512,d1				| all sets?\n\t"
+            "	bne.s		cfa_setloop			| no->\n\t"
+            "	clr.l		d1                  \n\t"
+            "	addq.l		#1,d0               \n\t"
+            "	move.l		d0,a0               \n\t"
+            "	cmpi.w		#4,d0				| all ways?\n\t"
+            "	bne.s		cfa_setloop			| no->\n\t"
+            /* input */	:
+            /* output */	:
+            /* clobber */	: "cc", "d0", "d1", "a0"
+    );
 }

 /*
@@ -87,48 +88,48 @@ void flush_and_invalidate_caches(void)
 */
 void flush_icache_range(void *address, size_t size)
 {
-	uint32_t set;
-	uint32_t start_set;
-	uint32_t end_set;
-	void *endaddr = address + size;
+    uint32_t set;
+    uint32_t start_set;
+    uint32_t end_set;
+    void *endaddr = address + size;

-	start_set = (uint32_t) address & _ICACHE_SET_MASK;
-	end_set = (uint32_t) endaddr & _ICACHE_SET_MASK;
+    start_set = (uint32_t) address & _ICACHE_SET_MASK;
+    end_set = (uint32_t) endaddr & _ICACHE_SET_MASK;

-	if (start_set > end_set) {
-		/* from the begining to the lowest address */
+    if (start_set > end_set) {
+        /* from the begining to the lowest address */
        for (set = 0; set <= end_set; set += (0x10 - 3))
        {
-			__asm__ __volatile__(
-						"       cpushl  ic,(%[set])         \n\t"
-						"       addq.l  #1,%[set]           \n\t"
-						"       cpushl  ic,(%[set])         \n\t"
-						"       addq.l  #1,%[set]           \n\t"
-						"       cpushl  ic,(%[set])         \n\t"
-						"       addq.l  #1,%[set]           \n\t"
-						"       cpushl  ic,(%[set])         \n\t"
-				 : /* output parameters  */
-				 : [set] "a" (set)  /* input parameters */
-				 : "cc"             /* clobbered registers */
-			);
-		}
-		/* next loop will finish the cache ie pass the hole */
-		end_set = LAST_ICACHE_ADDR;
-	}
-	for (set = start_set; set <= end_set; set += (0x10 - 3)) {
-		__asm__ __volatile__(
-					"       cpushl  ic,(%[set])             \n\t"
-					"       addq.l  #1,%[set]               \n\t"
-					"       cpushl  ic,(%[set])             \n\t"
-					"       addq.l  #1,%[set]               \n\t"
-					"       cpushl  ic,(%[set])             \n\t"
-					"       addq.l  #1,%[set]               \n\t"
-					"       cpushl  ic,(%[set])"
-					: /* output parameters */
-					: [set] "a" (set)
-					: "cc"
-		 );
-	}
+            __asm__ __volatile__(
+                        "       cpushl  ic,(%[set])         \n\t"
+                        "       addq.l  #1,%[set]           \n\t"
+                        "       cpushl  ic,(%[set])         \n\t"
+                        "       addq.l  #1,%[set]           \n\t"
+                        "       cpushl  ic,(%[set])         \n\t"
+                        "       addq.l  #1,%[set]           \n\t"
+                        "       cpushl  ic,(%[set])         \n\t"
+                 : /* output parameters  */
+                 : [set] "a" (set)  /* input parameters */
+                 : "cc"             /* clobbered registers */
+            );
+        }
+        /* next loop will finish the cache ie pass the hole */
+        end_set = LAST_ICACHE_ADDR;
+    }
+    for (set = start_set; set <= end_set; set += (0x10 - 3)) {
+        __asm__ __volatile__(
+                    "       cpushl  ic,(%[set])             \n\t"
+                    "       addq.l  #1,%[set]               \n\t"
+                    "       cpushl  ic,(%[set])             \n\t"
+                    "       addq.l  #1,%[set]               \n\t"
+                    "       cpushl  ic,(%[set])             \n\t"
+                    "       addq.l  #1,%[set]               \n\t"
+                    "       cpushl  ic,(%[set])"
+                    : /* output parameters */
+                    : [set] "a" (set)
+                    : "cc"
+         );
+    }
 }


@@ -138,52 +139,53 @@ void flush_icache_range(void *address, size_t size)
 */
 void flush_dcache_range(void *address, size_t size)
 {
-	unsigned long set;
-	unsigned long start_set;
-	unsigned long end_set;
-	void *endaddr;
+    unsigned long set;
+    unsigned long start_set;
+    unsigned long end_set;
+    void *endaddr;

-	endaddr = address + size;
-	start_set = (uint32_t) address & _DCACHE_SET_MASK;
-	end_set = (uint32_t) endaddr & _DCACHE_SET_MASK;
+    endaddr = address + size;
+    start_set = (uint32_t) address & _DCACHE_SET_MASK;
+    end_set = (uint32_t) endaddr & _DCACHE_SET_MASK;

-	if (start_set > end_set) {
-		/* from the begining to the lowest address */
-		for (set = 0; set <= end_set; set += (0x10 - 3))
-		{
-			__asm__ __volatile__(
-						"       cpushl  dc,(%[set])         \n\t"
-						"       addq.l  #1,%[set]           \n\t"
-						"       cpushl  dc,(%[set])         \n\t"
-						"       addq.l  #1,%[set]           \n\t"
-						"       cpushl  dc,(%[set])         \n\t"
-						"       addq.l  #1,%[set]           \n\t"
-						"       cpushl  dc,(%[set])         \n\t"
-						: /* output parameters */
-						: [set] "a" (set)
-						: "cc" /* clobbered registers */
-			);
-		}
-		/* next loop will finish the cache ie pass the hole */
-		end_set = LAST_DCACHE_ADDR;
-	}
-	for (set = start_set; set <= end_set; set += (0x10 - 3))
-	{
-		__asm__ __volatile__(
-					"       cpushl      dc,(%[set])     \n\t"
-					"       addq.l      #1,%[set]       \n\t"
-					"       cpushl      dc,(%[set])     \n\t"
-					"       addq%.l     #1,%[set]       \n\t"
-					"       cpushl      dc,(%[set])     \n\t"
-					"       addq.l      #1,%[set]       \n\t"
-					"       cpushl      dc,(%[set])     \n\t"
-					: /* output parameters */
-					: [set] "a" (set)
-					: "cc" /* clobbered registers */
-		);
-	}
+    if (start_set > end_set) {
+        /* from the begining to the lowest address */
+        for (set = 0; set <= end_set; set += (0x10 - 3))
+        {
+            __asm__ __volatile__(
+                        "       cpushl  dc,(%[set])         \n\t"
+                        "       addq.l  #1,%[set]           \n\t"
+                        "       cpushl  dc,(%[set])         \n\t"
+                        "       addq.l  #1,%[set]           \n\t"
+                        "       cpushl  dc,(%[set])         \n\t"
+                        "       addq.l  #1,%[set]           \n\t"
+                        "       cpushl  dc,(%[set])         \n\t"
+                        : /* output parameters */
+                        : [set] "a" (set)
+                        : "cc" /* clobbered registers */
+            );
+        }
+        /* next loop will finish the cache ie pass the hole */
+        end_set = LAST_DCACHE_ADDR;
+    }
+    for (set = start_set; set <= end_set; set += (0x10 - 3))
+    {
+        __asm__ __volatile__(
+                    "       cpushl      dc,(%[set])     \n\t"
+                    "       addq.l      #1,%[set]       \n\t"
+                    "       cpushl      dc,(%[set])     \n\t"
+                    "       addq%.l     #1,%[set]       \n\t"
+                    "       cpushl      dc,(%[set])     \n\t"
+                    "       addq.l      #1,%[set]       \n\t"
+                    "       cpushl      dc,(%[set])     \n\t"
+                    : /* output parameters */
+                    : [set] "a" (set)
+                    : "cc" /* clobbered registers */
+        );
+    }
 }

+
 /*
 * flush and invalidate a specific region from the both caches. We do not know if the area is cached
 * at all, we do not know in which of the four ways it is cached, but we know the index where they
--- a/sys/driver_mem.c
+++ b/sys/driver_mem.c
@@ -29,10 +29,11 @@

 //#define DBG_DM
 #ifdef	DBG_DM
-#define	dbg(fmt, args...)	xprintf(fmt, ##args)
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
-#define dbg(fmt, args...)
+#define dbg(format, arg...) do { ; } while (0)
 #endif
+#define err(format, arg...) do { xprintf("ERROR: %s(): " format, __FUNCTION__, ##arg); } while (0)

 extern long offscren_reserved(void);

--- a/sys/exceptions.S
+++ b/sys/exceptions.S
@@ -21,114 +21,114 @@
 */

 #include "startcf.h"
-#if MACHINE_FIREBEE
+#if defined(MACHINE_FIREBEE)
 #include "firebee.h"
-#elif MACHINE_M5484LITE
+#elif defined(MACHINE_M5484LITE)
 #include "m5484l.h"
 #endif /* MACHINE_FIREBEE */

-                .extern __SUP_SP
-                .extern _rom_entry
-                .extern __RAMBAR0
-                .extern _rt_mod
-                .extern _rt_ssp
-                .extern _rt_usp
-                .extern _rt_vbr
-                .extern _mmutr_miss
-                .extern __MBAR
-                .extern __MMUBAR
-                .extern _video_tlb
-                .extern _video_sbt
-                .extern _flush_and_invalidate_caches
-                .extern _get_bas_drivers
+        .extern __SUP_SP
+        .extern _rom_entry
+        .extern __RAMBAR0
+        .extern _rt_mod
+        .extern _rt_ssp
+        .extern _rt_usp
+        .extern _rt_vbr
+        .extern _mmutr_miss
+        .extern __MBAR
+        .extern __MMUBAR
+        .extern _video_tlb
+        .extern _video_sbt
+        .extern _flush_and_invalidate_caches
+        .extern _get_bas_drivers

-                /* PCI interrupt handlers */
-                .extern _irq5_handler
-                .extern _irq6_handler
-                .extern _irq7_handler
+        /* PCI interrupt handlers */
+        .extern _irq5_handler
+        .extern _irq6_handler
+        .extern _irq7_handler

-                .global _vec_init
-                .global _std_exc_vec        /* needed by driver_vec.c */
+        .global _vec_init
+        .global _std_exc_vec                /* needed by driver_vec.c */

 /* Register read/write equates */

-                /* MMU */
-                .equ    MCF_MMU_MMUCR, __MMUBAR
-                .equ    MCF_MMU_MMUOR, __MMUBAR+0x04
-                .equ    MCF_MMU_MMUSR, __MMUBAR+0x08
-                .equ    MCF_MMU_MMUAR, __MMUBAR+0x10
-                .equ    MCF_MMU_MMUTR, __MMUBAR+0x14
-                .equ    MCF_MMU_MMUDR, __MMUBAR+0x18
+        /* MMU */
+        .equ    MCF_MMU_MMUCR, __MMUBAR
+        .equ    MCF_MMU_MMUOR, __MMUBAR+0x04
+        .equ    MCF_MMU_MMUSR, __MMUBAR+0x08
+        .equ    MCF_MMU_MMUAR, __MMUBAR+0x10
+        .equ    MCF_MMU_MMUTR, __MMUBAR+0x14
+        .equ    MCF_MMU_MMUDR, __MMUBAR+0x18

-                /* EPORT flag register */
-                .equ    MCF_EPORT_EPFR, __MBAR+0xf0c
+        /* EPORT flag register */
+        .equ    MCF_EPORT_EPFR, __MBAR+0xf0c

-                /* FEC1 port output data direction register */
-                .equ    MCF_GPIO_PODR_FEC1L, __MBAR+0xa07
+        /* FEC1 port output data direction register */
+        .equ    MCF_GPIO_PODR_FEC1L, __MBAR+0xa07

-                /* PSC0 transmit buffer register */
-                .equ    MCF_PSC0_PSCTB_8BIT, __MBAR+0x860c
+        /* PSC0 transmit buffer register */
+        .equ    MCF_PSC0_PSCTB_8BIT, __MBAR+0x860c

-                /* GPT mode select register */
-                .equ    MCF_GPT0_GMS, __MBAR+0x800
+        /* GPT mode select register */
+        .equ    MCF_GPT0_GMS, __MBAR+0x800

-                /* Slice timer 0 count register */
-                .equ    MCF_SLT0_SCNT, __MBAR+0x908
+        /* Slice timer 0 count register */
+        .equ    MCF_SLT0_SCNT, __MBAR+0x908

-                // interrupt sources
-                .equ    INT_SOURCE_EPORT_EPF1,1     // edge port flag 1
-                .equ    INT_SOURCE_EPORT_EPF2,2     // edge port flag 2
-                .equ    INT_SOURCE_EPORT_EPF3,3     // edge port flag 3
-                .equ    INT_SOURCE_EPORT_EPF4,4     // edge port flag 4
-                .equ    INT_SOURCE_EPORT_EPF5,5     // edge port flag 5
-                .equ    INT_SOURCE_EPORT_EPF6,6     // edge port flag 6
-                .equ    INT_SOURCE_EPORT_EPF7,7     // edge port flag 7
-                .equ    INT_SOURCE_USB_EP0ISR,15    // USB endpoint 0 interrupt
-                .equ    INT_SOURCE_USB_EP1ISR,16    // USB endpoint 1 interrupt
-                .equ    INT_SOURCE_USB_EP2ISR,17    // USB endpoint 2 interrupt
-                .equ    INT_SOURCE_USB_EP3ISR,18    // USB endpoint 3 interrupt
-                .equ    INT_SOURCE_USB_EP4ISR,19    // USB endpoint 4 interrupt
-                .equ    INT_SOURCE_USB_EP5ISR,20    // USB endpoint 5 interrupt
-                .equ    INT_SOURCE_USB_EP6ISR,21    // USB endpoint 6 interrupt
-                .equ    INT_SOURCE_USB_USBISR,22    // USB general interrupt
-                .equ    INT_SOURCE_USB_USBAISR,23   // USB core interrupt
-                .equ    INT_SOURCE_USB_ANY,24       // OR of all USB interrupts
-                .equ    INT_SOURCE_USB_DSPI_OVF,25  // DSPI overflow or underflow
-                .equ    INT_SOURCE_USB_DSPI_RFOF,26 // receive FIFO overflow interrupt
-                .equ    INT_SOURCE_USB_DSPI_RFDF,27 // receive FIFO drain interrupt
-                .equ    INT_SOURCE_USB_DSPI_TFUF,28 // transmit FIFO underflow interrupt
-                .equ    INT_SOURCE_USB_DSPI_TCF,29  // transfer complete interrupt
-                .equ    INT_SOURCE_USB_DSPI_TFFF,30 // transfer FIFO fill interrupt
-                .equ    INT_SOURCE_USB_DSPI_EOQF,31 // end of queue interrupt
-                .equ    INT_SOURCE_PSC3,32          // PSC3 interrupt
-                .equ    INT_SOURCE_PSC2,33          // PSC2 interrupt
-                .equ    INT_SOURCE_PSC1,34          // PSC1 interrupt
-                .equ    INT_SOURCE_PSC0,35          // PSC0 interrupt
-                .equ    INT_SOURCE_CTIMERS,36       // combined source for comm timers
-                .equ    INT_SOURCE_SEC,37           // SEC interrupt
-                .equ    INT_SOURCE_FEC1,38          // FEC1 interrupt
-                .equ    INT_SOURCE_FEC0,39          // FEC0 interrupt
-                .equ    INT_SOURCE_I2C,40           // I2C interrupt
-                .equ    INT_SOURCE_PCIARB,41        // PCI arbiter interrupt
-                .equ    INT_SOURCE_CBPCI,42         // COMM bus PCI interrupt
-                .equ    INT_SOURCE_XLBPCI,43        // XLB PCI interrupt
-                .equ    INT_SOURCE_XLBARB,47        // XLBARB to PCI interrupt
-                .equ    INT_SOURCE_DMA,48           // multichannel DMA interrupt
-                .equ    INT_SOURCE_CAN0_ERROR,49    // FlexCAN error interrupt
-                .equ    INT_SOURCE_CAN0_BUSOFF,50   // FlexCAN bus off interrupt
-                .equ    INT_SOURCE_CAN0_MBOR,51     // message buffer ORed interrupt
-                .equ    INT_SOURCE_SLT1,53          // slice timer 1 interrupt
-                .equ    INT_SOURCE_SLT0,54          // slice timer 0 interrupt
-                .equ    INT_SOURCE_CAN1_ERROR,55    // FlexCAN error interrupt
-                .equ    INT_SOURCE_CAN1_BUSOFF,56   // FlexCAN bus off interrupt
-                .equ    INT_SOURCE_CAN1_MBOR,57     // message buffer ORed interrupt
-                .equ    INT_SOURCE_GPT3,59          // GPT3 timer interrupt
-                .equ    INT_SOURCE_GPT2,60          // GPT2 timer interrupt
-                .equ    INT_SOURCE_GPT1,61          // GPT1 timer interrupt
-                .equ    INT_SOURCE_GPT0,62          // GPT0 timer interrupt
+        // interrupt sources
+        .equ    INT_SOURCE_EPORT_EPF1,1         // edge port flag 1
+        .equ    INT_SOURCE_EPORT_EPF2,2         // edge port flag 2
+        .equ    INT_SOURCE_EPORT_EPF3,3         // edge port flag 3
+        .equ    INT_SOURCE_EPORT_EPF4,4         // edge port flag 4
+        .equ    INT_SOURCE_EPORT_EPF5,5         // edge port flag 5
+        .equ    INT_SOURCE_EPORT_EPF6,6         // edge port flag 6
+        .equ    INT_SOURCE_EPORT_EPF7,7         // edge port flag 7
+        .equ    INT_SOURCE_USB_EP0ISR,15        // USB endpoint 0 interrupt
+        .equ    INT_SOURCE_USB_EP1ISR,16        // USB endpoint 1 interrupt
+        .equ    INT_SOURCE_USB_EP2ISR,17        // USB endpoint 2 interrupt
+        .equ    INT_SOURCE_USB_EP3ISR,18        // USB endpoint 3 interrupt
+        .equ    INT_SOURCE_USB_EP4ISR,19        // USB endpoint 4 interrupt
+        .equ    INT_SOURCE_USB_EP5ISR,20        // USB endpoint 5 interrupt
+        .equ    INT_SOURCE_USB_EP6ISR,21        // USB endpoint 6 interrupt
+        .equ    INT_SOURCE_USB_USBISR,22        // USB general interrupt
+        .equ    INT_SOURCE_USB_USBAISR,23       // USB core interrupt
+        .equ    INT_SOURCE_USB_ANY,24           // OR of all USB interrupts
+        .equ    INT_SOURCE_USB_DSPI_OVF,25      // DSPI overflow or underflow
+        .equ    INT_SOURCE_USB_DSPI_RFOF,26     // receive FIFO overflow interrupt
+        .equ    INT_SOURCE_USB_DSPI_RFDF,27     // receive FIFO drain interrupt
+        .equ    INT_SOURCE_USB_DSPI_TFUF,28     // transmit FIFO underflow interrupt
+        .equ    INT_SOURCE_USB_DSPI_TCF,29      // transfer complete interrupt
+        .equ    INT_SOURCE_USB_DSPI_TFFF,30     // transfer FIFO fill interrupt
+        .equ    INT_SOURCE_USB_DSPI_EOQF,31     // end of queue interrupt
+        .equ    INT_SOURCE_PSC3,32              // PSC3 interrupt
+        .equ    INT_SOURCE_PSC2,33              // PSC2 interrupt
+        .equ    INT_SOURCE_PSC1,34              // PSC1 interrupt
+        .equ    INT_SOURCE_PSC0,35              // PSC0 interrupt
+        .equ    INT_SOURCE_CTIMERS,36           // combined source for comm timers
+        .equ    INT_SOURCE_SEC,37               // SEC interrupt
+        .equ    INT_SOURCE_FEC1,38              // FEC1 interrupt
+        .equ    INT_SOURCE_FEC0,39              // FEC0 interrupt
+        .equ    INT_SOURCE_I2C,40               // I2C interrupt
+        .equ    INT_SOURCE_PCIARB,41            // PCI arbiter interrupt
+        .equ    INT_SOURCE_CBPCI,42             // COMM bus PCI interrupt
+        .equ    INT_SOURCE_XLBPCI,43            // XLB PCI interrupt
+        .equ    INT_SOURCE_XLBARB,47            // XLBARB to PCI interrupt
+        .equ    INT_SOURCE_DMA,48               // multichannel DMA interrupt
+        .equ    INT_SOURCE_CAN0_ERROR,49        // FlexCAN error interrupt
+        .equ    INT_SOURCE_CAN0_BUSOFF,50       // FlexCAN bus off interrupt
+        .equ    INT_SOURCE_CAN0_MBOR,51         // message buffer ORed interrupt
+        .equ    INT_SOURCE_SLT1,53              // slice timer 1 interrupt
+        .equ    INT_SOURCE_SLT0,54              // slice timer 0 interrupt
+        .equ    INT_SOURCE_CAN1_ERROR,55        // FlexCAN error interrupt
+        .equ    INT_SOURCE_CAN1_BUSOFF,56       // FlexCAN bus off interrupt
+        .equ    INT_SOURCE_CAN1_MBOR,57         // message buffer ORed interrupt
+        .equ    INT_SOURCE_GPT3,59              // GPT3 timer interrupt
+        .equ    INT_SOURCE_GPT2,60              // GPT2 timer interrupt
+        .equ    INT_SOURCE_GPT1,61              // GPT1 timer interrupt
+        .equ    INT_SOURCE_GPT0,62              // GPT0 timer interrupt

 // Atari register equates (provided by FPGA)
-                .equ    vbasehi, 0xffff8201
+        .equ    vbasehi, 0xffff8201

 /*
 * macros
@@ -139,113 +139,119 @@
 * flag from the EDGE PORT flag register, set the status register to the appropriate interrupt
 * mask an jump through the corresponging vector
 */
-                .macro  irq vector,int_mask,clr_int
-                move.w  #0x2700,sr                  // disable interrupt
-                subq.l  #8,sp
-                movem.l d0/a5,(sp)                  // save registers
+        .macro  irq vector,int_mask,clr_int
+        move.w  #0x2700,sr                      // disable interrupts
+        subq.l  #8,sp
+        movem.l d0/a5,(sp)                      // save registers

-                lea MCF_EPORT_EPFR,a5
-                move.b  #\clr_int,(a5)              // clear int pending
+        lea     MCF_EPORT_EPFR,a5
+        move.b  #\clr_int,(a5)                  // clear int pending

-                movem.l (sp),d0/a5                  // restore registers
-                addq.l  #8,sp
-                move.l  \vector,-(sp)
-                move    #0x2\int_mask\()00,sr
-                rts
-                .endm
+        movem.l (sp),d0/a5                      // restore registers
+        addq.l  #8,sp
+        move.l  \vector,-(sp)
+        move    #0x2\int_mask\()00,sr
+        rts
+        .endm

-                .text
+        .text
 _vec_init:
-                move.l  a2,-(sp)                    // Backup registers
+        move.l  a2,-(sp)                        // Backup registers

-                mov3q.l #-1,_rt_mod                 // rt_mod auf super
-                clr.l   _rt_ssp
-                clr.l   _rt_usp
-                clr.l   _rt_vbr
-                move.l  #__RAMBAR0,d0               // exception vectors reside in rambar0
-                movec   d0,VBR
-                move.l  d0,a0
-                move.l  a0,a2
+        mov3q.l #-1,_rt_mod                     // rt_mod auf super
+        clr.l   _rt_ssp
+        clr.l   _rt_usp
+        clr.l   _rt_vbr
+        move.l  #__RAMBAR0,d0                   // exception vectors reside in rambar0
+        movec   d0,VBR
+        move.l  d0,a0
+        move.l  a0,a2

 /*
 * first, set standard vector for all exceptions
 */
 init_vec:
-                move.l  #256,d0
-                lea std_exc_vec(pc),a1              // standard vector
+        move.l  #256,d0
+        lea     std_exc_vec(pc),a1              // standard vector
 init_vec_loop:
-                move.l  a1,(a2)+                    // set standard vector for all exceptions
-                subq.l  #1,d0
-                bne init_vec_loop
+        move.l  a1,(a2)+                        // set standard vector for all exceptions
+        subq.l  #1,d0
+        bne     init_vec_loop

-                move.l  #__SUP_SP,(a0)              // set initial stack pointer at start of exception vector table
+// set individual interrupt handler assignments

-                lea reset_vector(pc),a1             // set reset vector
-                move.l  a1,0x04(a0)
+        move.l  #__SUP_SP,(a0)                  // set initial stack pointer at start of exception vector table

-                lea access(pc),a1                   // set illegal access exception handler
-                move.l  a1,0x08(a0)
+        lea     reset_vector(pc),a1             // set reset vector
+        move.l  a1,0x04(a0)
+
+        lea     access(pc),a1                   // set illegal access exception handler
+        move.l  a1,0x08(a0)
+
+// install spurious interrupt handler
+        lea     _lowlevel_isr_handler,a1
+        move.l	a1,0x60(a0)

 // trap #0 (without any parameters for now) is used to provide BaS' driver addresses to the OS
-                lea _get_bas_drivers(pc),a1
-                move.l  a1,0x80(a0)                 // trap #0 exception vector
+        lea     _get_bas_drivers(pc),a1
+        move.l  a1,0x80(a0)                     // trap #0 exception vector

 // MFP non-autovector interrupt handlers. Those are just rerouted to their autovector counterparts

-                lea     irq1(pc),a1
-                move.l  a1,0x104(a0)
+        lea     irq1(pc),a1
+        move.l  a1,0x104(a0)

-                lea     irq2(pc),a1
-                move.l  a1,0x108(a0)
+        lea     irq2(pc),a1
+        move.l  a1,0x108(a0)

-                lea     irq3(pc),a1
-                move.l  a1,0x10c(a0)
+        lea     irq3(pc),a1
+        move.l  a1,0x10c(a0)

-                lea     irq4(pc),a1
-                move.l  a1,0x110(a0)
+        lea     irq4(pc),a1
+        move.l  a1,0x110(a0)

-                lea     irq5(pc),a1
-                move.l  a1,0x114(a0)
+        lea     irq5(pc),a1
+        move.l  a1,0x114(a0)

-                lea     irq6(pc),a1
-                move.l  a1,0x118(a0)
+        lea     irq6(pc),a1
+        move.l  a1,0x118(a0)

-                lea     irq7(pc),a1
-                move.l  a1,0x11c(a0)
+        lea     irq7(pc),a1
+        move.l  a1,0x11c(a0)



 // install lowlevel_isr_handler for the three GPT timers
-                lea     _lowlevel_isr_handler(pc),a1
-                move.l  a1,(INT_SOURCE_GPT1 + 64) * 4(a0)
-                move.l  a1,(INT_SOURCE_GPT2 + 64) * 4(a0)
-                move.l  a1,(INT_SOURCE_GPT3 + 64) * 4(a0)
+        lea     _lowlevel_isr_handler(pc),a1
+        move.l  a1,(INT_SOURCE_GPT1 + 64) * 4(a0)
+        move.l  a1,(INT_SOURCE_GPT2 + 64) * 4(a0)
+        move.l  a1,(INT_SOURCE_GPT3 + 64) * 4(a0)

 // install lowlevel_isr_handler for the PSC3 interrupt
-                move.l  a1,(INT_SOURCE_PSC3 + 64) * 4(a0)
+        move.l  a1,(INT_SOURCE_PSC3 + 64) * 4(a0)

 // install lowlevel_isr_handler for Coldfire DMA interrupts
-                move.l  a1,(INT_SOURCE_DMA + 64) * 4(a0)
+        move.l  a1,(INT_SOURCE_DMA + 64) * 4(a0)

 // install lowlevel_isr_handler for the XLBPCI interrupt
-                move.l  a1,(INT_SOURCE_XLBPCI + 64) * 4(a0)
+        move.l  a1,(INT_SOURCE_XLBPCI + 64) * 4(a0)

 // install lowlevel_isr_handler for the FEC0  interrupt
-                move.l  a1,(INT_SOURCE_FEC0 + 64) * 4(a0)
+        move.l  a1,(INT_SOURCE_FEC0 + 64) * 4(a0)

 #ifndef MACHINE_FIREBEE
 // FEC1 not wired on the FireBee (used for FPGA as GPIO), but available on other machines
-                move.l  a1,(INT_SOURCE_FEC1 + 64) * 4(a0)
+        move.l  a1,(INT_SOURCE_FEC1 + 64) * 4(a0)
 #endif

 #ifdef MACHINE_FIREBEE

 // timer vectors (triggers when vbashi gets changed, used for video page copy)
-                move.l  a1,(INT_SOURCE_GPT0 + 64) * 4(a0)
+        // move.l  a1,(INT_SOURCE_GPT0 + 64) * 4(a0)
 #endif /* MACHINE_FIREBEE */

-                move.l  (sp)+,a2            // Restore registers
-                rts
+        move.l  (sp)+,a2                        // Restore registers
+        rts


 /*
@@ -254,281 +260,294 @@ init_vec_loop:
 vector_table_start:
 std_exc_vec:
 _std_exc_vec:
-                //move.w    #0x2700,sr              // disable interrupt
-                subq.l  #8,sp
-                movem.l d0/a5,(sp)                  // save registers
-                move.w  8(sp),d0                    // fetch vector
-                and.l   #0x3fc,d0                   // mask out vector number
-
+        move.w	#0x2700,sr                      // disable interrupt
+        subq.l  #8,sp
+        movem.l d0/a5,(sp)                      // save registers
+        move.w  8(sp),d0                        // fetch vector
+        and.l   #0x3fc,d0                       // mask out vector number
+//#define DBG_EXC
 #ifdef DBG_EXC
-                // printout vector number of exception
+        // printout vector number of exception

-                lea -4 * 4(sp),sp                   // reserve stack space
-                movem.l d0-d1/a0-a1,(sp)            // save gcc scratch registers
+        lea -4 * 4(sp),sp                       // reserve stack space
+        movem.l d0-d1/a0-a1,(sp)                // save gcc scratch registers

-                lsr.l   #2,d0                       // shift vector number in place
-                cmp.l   #33,d0
-                beq     noprint
-                cmp.l   #34,d0
-                beq n   oprint
-                cmp.l   #45,d0
-                beq     noprint
-                cmp.l   #46,d0
-                beq     noprint
-                move.l  4 * 4 + 8 + 4(sp),-(sp)     // pc at exception
-                move.l  d0,-(sp)                    // provide it to xprintf()
-                pea     exception_text
-                jsr     _xprintf                    // call xprintf()
-                add.l   #3*4,sp                     // adjust stack
+        lsr.l   #2,d0                           // shift vector number in place
+        cmp.l   #33,d0
+        beq     noprint
+        cmp.l   #34,d0
+        beq     noprint
+        cmp.l   #45,d0
+        beq     noprint
+        cmp.l   #46,d0
+        beq     noprint
+        move.l  4 * 4 + 8 + 4(sp),-(sp)         // pc at exception
+        move.l  d0,-(sp)                        // provide it to xprintf()
+        pea     exception_text
+        jsr     _xprintf                        // call xprintf()
+        add.l   #3*4,sp                         // adjust stack
 noprint:

-                movem.l (sp),d0-d1/a0-a1            // restore registers
-                lea     4 * 4(sp),sp
+        movem.l (sp),d0-d1/a0-a1                // restore registers
+        lea     4 * 4(sp),sp
 #endif /* DBG_EXC */

-                add.l   _rt_vbr,d0                  // + VBR
-                move.l  d0,a5
-                move.l  (a5),d0                     // fetch exception routine address
+        add.l   _rt_vbr,d0                      // + VBR
+        move.l  d0,a5
+        move.l  (a5),d0                         // fetch exception routine address

-                move.l  4(sp),a5                    // restore a5
-                move.l  d0,4(sp)                    // store exception routine address
+        move.l  4(sp),a5                        // restore a5
+        move.l  d0,4(sp)                        // store exception routine address

-                // FIXME: not clear why we would need the following?
-                //move.w    10(sp),d0               // restore original SR
-                //bset  #13,d0                      // set supervisor bit
-                //move.w    d0,sr                   //
-                move.l  (sp)+,d0                    // restore d0
-                rts                                 // jump to exception handler
+        move.w	10(sp),d0                       // restore original SR (irq mask)
+        bset	#13,d0                          // set supervisor bit
+        move.w	d0,sr                           //
+        move.l  (sp)+,d0                        // restore d0
+        rts                                     // jump to exception handler

 exception_text:
-                .ascii  "DEBUG: EXCEPTION %d caught at %p"
-                .byte   13, 10, 0
-                .align  4
+        .ascii  "DEBUG: EXCEPTION %d caught at %p"
+        .byte   13, 10, 0
+        .align  4

 reset_vector:
-                move.w  #0x2700,sr                  // disable interrupts
-                move.l  #0x31415926,d0
-                cmp.l   0x426,d0                    // _resvalid: reset vector valid?
-                beq     std_exc_vec                 // yes->
-                jmp     _rom_entry                  // no, cold start machine
+        move.w  #0x2700,sr                      // disable interrupts
+        move.l  #0x31415926,d0
+        cmp.l   0x426,d0                        // _resvalid: reset vector valid?
+        beq     std_exc_vec                     // yes->
+        jmp     _rom_entry                      // no, cold start machine

 access:
-                move.w  #0x2700,sr                  // disable interrupts
+        move.w  #0x2700,sr                      // disable interrupts

-                link    a6,#-4 * 4                  // make room for gcc scratch registers
-                movem.l d0-d1/a0-a1,(sp)            // save them
+        link    a6,#-4 * 4                      // make room for gcc scratch registers
+        movem.l d0-d1/a0-a1,(sp)                // save them

-                move.l  4(a6),-(sp)                 // push format_status
-                move.l  8(a6),-(sp)                 // pc at exception
-                move.l  MCF_MMU_MMUAR,-(sp)         // MMU fault address
-                move.l  MCF_MMU_MMUSR,-(sp)         // MMU status regisrter
-                move.w  #0x2300,sr                  // can lower interrupt mask now that MMU status is safe
-                jsr     _mmutr_miss                 // call C routine
-                lea     4 * 4(sp),sp                // adjust stack
+        move.l  4(a6),-(sp)                     // push format_status
+        move.l  8(a6),-(sp)                     // pc at exception
+        move.l  MCF_MMU_MMUAR,-(sp)             // MMU fault address
+        move.l  MCF_MMU_MMUSR,-(sp)             // MMU status register
+        // probably doesn't make sense since we still have a potential unmapped MMU page
+        // move.w  #0x2300,sr                      // can lower interrupt mask now that MMU status is safe
+        jsr     _mmutr_miss                     // call C routine
+        lea     4 * 4(sp),sp                    // adjust stack

-                tst.l   d0                          // exception handler signals bus error
-                bne     bus_error
+        tst.l   d0                              // exception handler signals bus error
+        bne     bus_error

-                movem.l (sp),d0-d1/a0-a1            // restore registers
-                unlk    a6
-                rte
+        movem.l (sp),d0-d1/a0-a1                // restore registers
+        unlk    a6
+        rte

 bus_error:
-                movem.l (sp),d0-d1/a0-a1            // restore registers
-                unlk    a6
-                bra     std_exc_vec                 // FIXME: this seems to be bogous...
+        movem.l (sp),d0-d1/a0-a1                // restore registers
+        unlk    a6
+        move.l  0x08,-(sp)
+        rts
+        // bra     std_exc_vec                     // FIXME: this seems to be bogous...

 zero_divide:
-                move.w  #0x2700,sr                  // disable interrupt
-                move.l  a0,-(sp)
-                move.l  d0,-(sp)
-                move.l  12(sp),a0                   // pc
-                move.w  (a0)+,d0                    // command word
-                btst    #7,d0                       // long?
-                beq     zd_word                     // nein->
-                addq.l  #2,a0
+        move.w  #0x2700,sr                      // disable interrupt
+        move.l  a0,-(sp)
+        move.l  d0,-(sp)
+        move.l  12(sp),a0                       // pc
+        move.w  (a0)+,d0                        // command word
+        btst    #7,d0                           // long?
+        beq     zd_word                         // no->
+        addq.l  #2,a0

 zd_word:
-                and.l   0x3f,d0                     // mask out ea field
-                cmp.w   #0x08,d0                    // -(ax) or less?
-                ble     zd_end
-                addq.l  #2,a0
-                cmp.w   #0x39,d0                    // xxx.L
-                bne     zd_nal
-                addq.l  #2,a0
-                bra     zd_end
+        and.l   0x3f,d0                         // mask out ea field
+        cmp.w   #0x08,d0                        // -(ax) or less?
+        ble     zd_end
+        addq.l  #2,a0
+        cmp.w   #0x39,d0                        // xxx.L
+        bne     zd_nal
+        addq.l  #2,a0
+        bra     zd_end

-zd_nal:         cmp.w   #0x3c,d0                    // immediate?
-                bne     zd_end                      // no->
-                btst    #7,d0                       // long?
-                beq     zd_end                      // no
-                addq.l  #2,a0
+zd_nal:         cmp.w   #0x3c,d0                // immediate?
+        bne     zd_end                          // no->
+        btst    #7,d0                           // long?
+        beq     zd_end                          // no
+        addq.l  #2,a0
 zd_end:
-                move.l  a0,12(sp)
-                move.l  (sp)+,d0
-                move.l  (sp)+,a0
-                rte
+        move.l  a0,12(sp)
+        move.l  (sp)+,d0
+        move.l  (sp)+,a0
+        rte

 #ifdef _NOT_USED_
 linea:
-                move.w  #0x2700,sr                  // disable interrupt
-                halt
-                nop
-                nop
+        move.w  #0x2700,sr                      // disable interrupt
+        halt
+        nop
+        nop
 linef:
-                move.w  #0x2700,sr                  // disable interrupt
-                halt
-                nop
-                nop
+        move.w  #0x2700,sr                      // disable interrupt
+        halt
+        nop
+        nop
 format:
-                move.w  #0x2700,sr                  // disable interrupt
-                halt
-                nop
-                nop
+        move.w  #0x2700,sr                      // disable interrupt
+        halt
+        nop
+        nop

 //floating point
 flpoow:
-                move.w  #0x2700,sr                  // disable interrupt
-                halt
-                nop
-                nop
+        move.w  #0x2700,sr                      // disable interrupt
+        halt
+        nop
+        nop
 #endif /* _NOT_USED */


-irq1:           irq     0x64, 1, 0x02               // Level 1 autovector interrupt (unused)
-irq2:           irq     0x68, 2, 0x04               // Level 2 autovector interrupt (horizontal blank)
-irq3:           irq     0x6c, 3, 0x08               // Level 3 autovector interrupt (unused)
-irq4:           irq     0x70, 4, 0x10               // Level 4 autovector interrupt (vertical blank)
+irq1:           irq     0x64, 1, 0x02           // Level 1 autovector interrupt (unused)
+irq2:           irq     0x68, 2, 0x04           // Level 2 autovector interrupt (horizontal blank)
+irq3:           irq     0x6c, 3, 0x08           // Level 3 autovector interrupt (unused)
+irq4:           irq     0x70, 4, 0x10           // Level 4 autovector interrupt (vertical blank)



-#if defined(MACHINE_FIREBEE)                        /* these handlers are only meaningful for the Firebee */
-irq5:           //move.w  #0x2700,sr                  // disable interrupts
-                subq.l  #4,sp                       // extra space
+#if defined(MACHINE_FIREBEE)                    /* these handlers are only meaningful for the Firebee */
+irq5:           //move.w  #0x2700,sr            // disable interrupts
+        subq.l	#4,sp                           // extra space

-                link    a6,#-4 * 4                  // save gcc scratch registers
-                movem.l d0-d1/a0-a1,(sp)
+        link	a6,#-4 * 4                      // save gcc scratch registers
+        movem.l	d0-d1/a0-a1,(sp)

-                jsr     _irq5_handler               // call C handler routine
+        jsr	_irq5_handler                       // call C handler routine

-                tst.b   d0                          // handled?
-                beq     irq5_forward
+        tst.b	d0                              // handled?
+        beq	irq5_forward

-                movem.l (sp),d0-d1/a0-a1            // restore registers
-                unlk    a6
-                addq.l  #4,sp
+        movem.l	(sp),d0-d1/a0-a1                // restore registers
+        unlk	a6
+        addq.l	#4,sp

-                rte                                 // return from exception
+        rte                                     // return from exception

-irq5_forward:   move.l  0x74,a0                     // fetch OS irq5 vector
-                add.l   _rt_vbr,a0                  // add runtime vbr
-                move.l  a0,4(a6)                    // put on stack
+irq5_forward:   move.l	0x74,a0                 // fetch OS irq5 vector
+        add.l	_rt_vbr,a0                      // add runtime vbr
+        move.l	a0,4(a6)                        // put on stack

-                movem.l (sp),d0-d1/a0-a1            // restore registers
-                unlk    a6                          //
-                move.w  #0x2500,sr                  // set interrupt level
-                rts                                 // jump through vector
+        movem.l	(sp),d0-d1/a0-a1                // restore registers
+        unlk	a6			//
+        move.w	#0x2500,sr                      // set interrupt level
+        rts                                     // jump through vector

 /*
 * irq6 needs special treatment since - because the Coldfire only supports autovector interrupts
 * - the exception vector is provided by the simulated MFP from the FPGA
 */
-irq6:           //move.w  #0x2700,sr                  // disable interrupt
-                subq.l  #4,sp                       // extra space
+irq6:		move.w	#0x2700,sr                  // disable interrupt
+        subq.l	#4,sp                           // extra space

-                link    a6,#-4 * 4                  // save gcc scratch registers
-                movem.l d0-d1/a0-a1,(sp)
+        link	a6,#-4 * 4                      // save gcc scratch registers
+        movem.l d0-d1/a0-a1,(sp)

-                move.l  8(a6),-(sp)                 // format status word
-                move.l  12(a6),-(sp)                // pc at exception
-                jsr     _irq6_handler               // call C handler
-                lea     8(sp),sp                    // fix stack
+        move.l	8(a6),-(sp)                     // format status word
+        move.l	12(a6),-(sp)                    // pc at exception
+        jsr     _irq6_handler                   // call C handler
+        lea     8(sp),sp                        // fix stack

-                tst.b   d0                          // interrupt handled?
-                beq     irq6_forward                // no, forward to TOS
+        tst.b	d0                              // interrupt handled?
+        beq	irq6_forward                        // no, forward to TOS

-                movem.l (sp),d0-d1/a0-a1            // restore registers
-                unlk    a6
-                addq.l  #4,sp                       // "extra space" not needed in this case
-                rte
+        movem.l	(sp),d0-d1/a0-a1                // restore registers
+        unlk	a6
+        addq.l	#4,sp                           // "extra space" not needed in this case
+        rte

 irq6_forward:
-                move.l  0xf0020000,a0               // fetch "MFP interrupt vector" from FPGA
-                add.l   _rt_vbr,a0                  // add runtime VBR
-                move.l  (a0),4(a6)                  // fetch handler address and put it on "extra space"
+        move.l	0xf0020000,a0                   // fetch "MFP interrupt vector" from FPGA
+        add.l	_rt_vbr,a0                      // add runtime VBR
+        move.l  (a0),4(a6)                      // fetch handler address and put it on "extra space"

-                movem.l (sp),d0-d1/a0-a1
-                unlk    a6
-                move.w  #0x2600,sr                  // set interrupt mask to MFP level
+        movem.l (sp),d0-d1/a0-a1
+        unlk	a6
+        move.w	#0x2600,sr                      // set interrupt mask to MFP level

-                rts                                 // jump through vector
+        rts                                     // jump through vector

 /*
 * irq 7 = pseudo bus error
 */
 irq7:
-                lea     -12(sp),sp
-                movem.l d0/a0,(sp)
+        lea	-12(sp),sp
+        movem.l d0/a0,(sp)

-                move.l  __RAMBAR0+0x008,a0          // real access error handler
-                move.l  a0,8(sp)                    // this will be the return address for rts
+        move.l	__RAMBAR0+0x008,a0              // real access error handler
+        move.l	a0,8(sp)                        // this will be the return address for rts

-                move.w  12(sp),d0                   // format/vector word
-                andi.l  #0xf000,d0                  // keep only the format
-                ori.l   #2*4,d0                     // simulate vector #2, no fault
-                move.w  d0,12(sp)
+        move.w	12(sp),d0                       // format/vector word
+        andi.l	#0xf000,d0                      // keep only the format
+        ori.l	#2*4,d0                         // simulate vector #2, no fault
+        move.w	d0,12(sp)

-                // TODO: Inside an interrupt handler, 16(sp) is the return address.
-                // For an Access Error, it should be the address of the fault instruction instead
+        // TODO: Inside an interrupt handler, 16(sp) is the return address.
+        // For an Access Error, it should be the address of the fault instruction instead

-                lea     MCF_EPORT_EPFR,a0
-                bset    #7,(a0)                     // clear int 7
+        lea	MCF_EPORT_EPFR,a0
+        bset	#7,(a0)                         // clear int 7

-                move.l  (sp)+,d0                    // restore registers
-                move.l  (sp)+,a0
-                rts                                 // Forward to the Access Error handler
+        move.l	(sp)+,d0                        // restore registers
+        move.l	(sp)+,a0
+        rts                                     // Forward to the Access Error handler

-#else                                               // handlers for M5484LITE
+#else                                           // handlers for M5484LITE

-irq5:                                               // irq5 is tied to PCI INTC# and PCI INTD# on the M5484LITE
-                //move.w  #0x2700,sr                  // disable interrupts
+irq5:
+        move.w	#0x2700,sr                      // disable interrupts
+        subq.l	#4,sp                           // extra space

-                lea     -4*4(sp),sp                 // save gcc scratch registers
-                movem.l d0-d1/a0-a1,(sp)
+        link	a6,#-4 * 4                      // save gcc scratch registers
+        movem.l	d0-d1/a0-a1,(sp)

-                jsr     _irq5_handler               // call C handler routine
+        jsr     _irq5_handler                   // call C handler routine

-                movem.l (sp),d0-d1/a0-a1            // restore registers
-                lea     4*4(sp),sp
+        tst.b	d0                              // handled?
+        beq     irq5_forward

-                rte                                 // return from exception
+        movem.l	(sp),d0-d1/a0-a1                // restore registers
+        unlk	a6
+        addq.l	#4,sp

-irq5text:
-                .ascii  "IRQ5!"
-                .dc.b   13,10,0
+        rte                                     // return from exception
+
+irq5_forward:
+        move.l	0x74,a0                         // fetch OS irq5 vector
+        add.l	_rt_vbr,a0                      // add runtime vbr
+        move.l	a0,4(a6)                        // put on stack
+
+        movem.l	(sp),d0-d1/a0-a1                // restore registers
+        unlk	a6                              //
+        move.w	#0x2500,sr                      // set interrupt level
+        rts                                     // jump through vector

 irq6:
-                irq 0x74,5,0x20
+        irq 0x74,5,0x20

-irq7:                                               // irq7 is tied to PCI INTA# and PCI INTB# on the M5484LITE
+irq7:                                           // irq7 is tied to PCI INTA# and PCI INTB# on the M5484LITE

-                //move.w  #0x2700,sr                  // disable interrupts
+        move.w	#0x2700,sr                      // disable interrupts

-                lea     -4*4(sp),sp                 // save gcc scratch registers
-                movem.l d0-d1/a0-a1,(sp)
+        lea	-4*4(sp),sp                         // save gcc scratch registers
+        movem.l	d0-d1/a0-a1,(sp)

-                jsr     _irq7_handler               // call C handler routine
+        jsr	_irq7_handler                       // call C handler routine

-                movem.l (sp),d0-d1/a0-a1            // restore registers
-                lea     4*4(sp),sp
+        movem.l	(sp),d0-d1/a0-a1                // restore registers
+        lea	4 * 4(sp),sp

-                rte                                 // return from exception
+        rte                                     // return from exception

 irq7text:
-                .data
-                .ascii  "IRQ7!"
-                .dc.b   13,10,0
-                .text
+        .data
+        .ascii	"IRQ7!"
+        .dc.b	13,10,0
+        .text
 #endif /* MACHINE_FIREBEE */

 /*
@@ -536,8 +555,8 @@ irq7text:
 * isr_register_handler(int vector). If the higlevel routine (isr_execute_handler())
 * returns != true, the call is forwarded to the OS (through its own vector base).
 */
-                .global _lowlevel_isr_handler
-                .extern _isr_execute_handler
+        .global _lowlevel_isr_handler
+        .extern _isr_execute_handler


 /*
@@ -553,33 +572,33 @@ irq7text:
 * (sp) ->  gcc scratch registers save area
 */
 _lowlevel_isr_handler:
-                subq.l  #4,sp                       // extra space
-                link    a6,#-4 * 4                  // make room for
-                movem.l d0-d1/a0-a1,(sp)            // gcc scratch registers and save them,
-                                                    // other registers will be taken care of by gcc itself
+        subq.l	#4,sp                           // extra space
+        link	a6,#-4 * 4                      // make room for
+        movem.l	d0-d1/a0-a1,(sp)                // gcc scratch registers and save them,
+                                                // other registers will be taken care of by gcc itself

-                move.w  8(a6),d0                    // fetch vector number from stack
-                lsr.l   #2,d0                       // move it in place
-                andi.l  #0xff,d0                    // mask it out
-                move.l  d0,-(sp)                    // push it
-                jsr     _isr_execute_handler        // call the C handler
-                addq.l  #4,sp                       // adjust stack
-                tst.b   d0                          // handled?
-                beq     lowlevel_forward            // no, forward it to TOS
+        move.w	8(a6),d0                        // fetch vector number from stack
+        lsr.l	#2,d0                           // move it in place
+        andi.l	#0xff,d0                        // mask it out
+        move.l	d0,-(sp)                        // push it
+        jsr     _isr_execute_handler            // call the C handler
+        addq.l	#4,sp                           // adjust stack
+        tst.b	d0                              // handled?
+        beq     lowlevel_forward                // no, forward it to TOS

-                movem.l (sp),d0-d1/a0-a1            // restore registers
-                unlk    a6
-                addq.l  #4,sp                       // eliminate extra space
+        movem.l	(sp),d0-d1/a0-a1                // restore registers
+        unlk	a6
+        addq.l	#4,sp                           // eliminate extra space

-                rte
+        rte

 lowlevel_forward:
-                move.l  8(a6),d0                    // fetch OS irq vector
-                lsr.l   #2,d0                       // move it in place
-                andi.l  #0xff,d0                    // mask out vector number
-                add.l   _rt_vbr,d0                  // add runtime vbr
-                move.l  d0,4(a6)                    // put on stack as return address
+        move.l	8(a6),d0                        // fetch OS irq vector
+        lsr.l	#2,d0                           // move it in place
+        andi.l	#0xff,d0                        // mask out vector number
+        add.l	_rt_vbr,d0                      // add runtime vbr
+        move.l	d0,4(a6)                        // put on stack as return address

-                movem.l (sp),d0-d1/a0-a1            // restore registers
-                unlk    a6                          //
-                rts                                 // jump through vector
+        movem.l	(sp),d0-d1/a0-a1                // restore registers
+        unlk	a6                              //
+        rts                                     // jump through vector
--- a/sys/fault_vectors.c
+++ b/sys/fault_vectors.c
@@ -52,109 +52,134 @@ void fault_handler(uint32_t pc, uint32_t format_status)
    xprintf("fault_status: %x (", fault_status);
    switch (fault_status)
    {
-    case 0:
-        xprintf("not an access or address error nor an interrupted debug service routine");
-        break;
-    case 1:
-    case 3:
-    case 11:
-        xprintf("reserved");
-        break;
-    case 2:
-        xprintf("interrupt during a debug service routine for faults other than access errors");
-        break;
-    case 4:
-        xprintf("error (for example, protection fault) on instruction fetch");
-        break;
-    case 5:
-        xprintf("TLB miss on opword or instruction fetch");
-        break;
-    case 6:
-        xprintf("TLB miss on extension word of instruction fetch");
-        break;
-    case 7:
-        xprintf("IFP access error while executing in emulator mode");
-        break;
-    case 8:
-        xprintf("error on data write");
-        break;
-    case 9:
-        xprintf("error on attempted write to write-protected space");
-        break;
-    case 10:
-        xprintf("TLB miss on data write");
-        break;
-    case 12:
-        xprintf("error on data read");
-        break;
-    case 13:
-        xprintf("attempted read, read-modify-write of protected space");
-        break;
-    case 14:
-        xprintf("TLB miss on data read or read-modify-write");
-        break;
-    case 15:
-        xprintf("OEP access error while executing in emulator mode");
+        case 0:
+            xprintf("not an access or address error nor an interrupted debug service routine");
+            break;
+
+        case 1:
+        case 3:
+        case 11:
+            xprintf("reserved");
+            break;
+
+        case 2:
+            xprintf("interrupt during a debug service routine for faults other than access errors");
+            break;
+
+        case 4:
+            xprintf("error (for example, protection fault) on instruction fetch");
+            break;
+
+        case 5:
+            xprintf("TLB miss on opword or instruction fetch");
+            break;
+
+        case 6:
+            xprintf("TLB miss on extension word of instruction fetch");
+            break;
+
+        case 7:
+            xprintf("IFP access error while executing in emulator mode");
+            break;
+
+        case 8:
+            xprintf("error on data write");
+            break;
+
+        case 9:
+            xprintf("error on attempted write to write-protected space");
+            break;
+
+        case 10:
+            xprintf("TLB miss on data write");
+            break;
+
+        case 12:
+            xprintf("error on data read");
+            break;
+
+        case 13:
+            xprintf("attempted read, read-modify-write of protected space");
+            break;
+
+        case 14:
+            xprintf("TLB miss on data read or read-modify-write");
+            break;
+
+        case 15:
+            xprintf("OEP access error while executing in emulator mode");
    }
    xprintf(")\r\n");

-    xprintf("vector = %02x (", vector);
+    xprintf("vector = %d (", vector);
    switch (vector)
    {
-    case 2:
-        xprintf("access error");
-        break;
-    case 3:
-        xprintf("address error");
-        break;
-    case 4:
-        xprintf("illegal instruction");
-        break;
-    case 5:
-        xprintf("divide by zero");
-        break;
-    case 8:
-        xprintf("privilege violation");
-        break;
-    case 9:
-        xprintf("trace");
-        break;
-    case 10:
-        xprintf("unimplemented line-a opcode");
-        break;
-    case 11:
-        xprintf("unimplemented line-f opcode");
-        break;
-    case 12:
-        xprintf("non-PC breakpoint debug interrupt");
-        break;
-    case 13:
-        xprintf("PC breakpoint debug interrupt");
-        break;
-    case 14:
-        xprintf("format error");
-        break;
-    case 24:
-        xprintf("spurious interrupt");
-        break;
-    default:
-        if ( ((vector >= 6) && (vector <= 7)) ||
-             ((vector >= 16) && (vector <= 23)))
-        {
-            xprintf("reserved");
-        }
-        else if ((vector >= 25) && (vector <= 31))
-        {
-            xprintf("level %d autovectored interrupt", fault_status - 24);
-        }
-        else if ((vector >= 32) && (vector <= 47))
-        {
-            xprintf("trap #%d", vector - 32);
-        }
-        else
-        {
-            xprintf("unknown vector\r\n");
-        }
+        case 2:
+            xprintf("access error");
+            break;
+
+        case 3:
+            xprintf("address error");
+            break;
+
+        case 4:
+            xprintf("illegal instruction");
+            break;
+
+        case 5:
+            xprintf("divide by zero");
+            break;
+
+        case 8:
+            xprintf("privilege violation");
+            break;
+
+        case 9:
+            xprintf("trace");
+            break;
+
+        case 10:
+            xprintf("unimplemented line-a opcode");
+            break;
+
+        case 11:
+            xprintf("unimplemented line-f opcode");
+            break;
+
+        case 12:
+            xprintf("non-PC breakpoint debug interrupt");
+            break;
+
+        case 13:
+            xprintf("PC breakpoint debug interrupt");
+            break;
+
+        case 14:
+            xprintf("format error");
+            break;
+
+        case 24:
+            xprintf("spurious interrupt");
+            break;
+
+        default:
+            if ( ((vector >= 6) && (vector <= 7)) ||
+                 ((vector >= 16) && (vector <= 23)))
+            {
+                xprintf("reserved");
+            }
+            else if ((vector >= 25) && (vector <= 31))
+            {
+                xprintf("level %d autovectored interrupt", fault_status - 24);
+            }
+            else if ((vector >= 32) && (vector <= 47))
+            {
+                xprintf("trap #%d", vector - 32);
+            }
+            else
+            {
+                xprintf("unknown vector\r\n");
+            }
    }
    xprintf(")\r\n");
    xprintf("sr=%4x\r\n", sr);
--- a/sys/init_fpga.c
+++ b/sys/init_fpga.c
@@ -50,8 +50,8 @@ extern uint8_t _FPGA_CONFIG_SIZE[];
 * been loaded through the onboard JTAG interface.
 * init_fpga() will honour this and not overwrite config.
 */
-extern bool _FPGA_JTAG_LOADED;
-extern int32_t _FPGA_JTAG_VALID;
+extern uint32_t _FPGA_JTAG_LOADED;
+extern uint32_t _FPGA_JTAG_VALID;
 #define VALID_JTAG 0xaffeaffe

 void config_gpio_for_fpga_config(void)
@@ -94,14 +94,16 @@ bool init_fpga(void)
    volatile int32_t time, start, end;
    int i;

-    dbg("FPGA load config\r\n(_FPGA_JTAG_LOADED = %x, _FPGA_JTAG_VALID = %x)...\r\n", _FPGA_JTAG_LOADED, _FPGA_JTAG_VALID);
-    if (_FPGA_JTAG_LOADED == true && _FPGA_JTAG_VALID == VALID_JTAG)
+    xprintf("FPGA load config...\r\n");
+    xprintf("_FPGA_JTAG_LOADED = 0x%x\r\n", _FPGA_JTAG_LOADED);
+    xprintf("_FPGA_JTAG_VALID = 0x%x\r\n", _FPGA_JTAG_VALID);
+    if (_FPGA_JTAG_LOADED == 1 && _FPGA_JTAG_VALID == VALID_JTAG)
    {
-        dbg("detected _FPGA_JTAG_LOADED flag. Not overwriting FPGA config.\r\n");
+        xprintf("detected _FPGA_JTAG_LOADED flag. FPGA config skipped.\r\n");

        /* reset the flag so that next boot will load config again from flash */
-        _FPGA_JTAG_LOADED = 0;
-        _FPGA_JTAG_VALID = 0;
+        // _FPGA_JTAG_LOADED = 0;
+        // _FPGA_JTAG_VALID = 0;

        return true;
    }
@@ -124,7 +126,7 @@ bool init_fpga(void)
     * excerpt from an Altera configuration manual:
     *
     * The low-to-high transition of nCONFIG on the FPGA begins the configuration cycle. The
-     * configuration cycle consists of 3 stages<EFBFBD>reset, configuration, and initialization.
+     * configuration cycle consists of 3 stages: reset, configuration, and initialization.
     * While nCONFIG is low, the device is in reset. When the device comes out of reset,
     * nCONFIG must be at a logic high level in order for the device to release the open-drain
     * nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the FPGA
@@ -180,6 +182,16 @@ bool init_fpga(void)

        xprintf("finished (took %f seconds).\r\n", time / 1000.0);
        config_gpio_for_jtag_config();
+
+        /*
+         * assure skipping fpga load on warm boot
+         */
+
+        _FPGA_JTAG_LOADED = 1;
+        _FPGA_JTAG_VALID = VALID_JTAG;
+
+        xprintf("SRAM now set to FPGA load skip\r\n");
+
        return true;
    }
    xprintf("FAILED!\r\n");
--- a/sys/interrupts.c
+++ b/sys/interrupts.c
@@ -37,7 +37,7 @@
 #include "dma.h"
 #include "pci.h"

-//#define IRQ_DEBUG
+// #define IRQ_DEBUG
 #if defined(IRQ_DEBUG)
 #define dbg(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
@@ -61,6 +61,7 @@ struct isrentry

 static struct isrentry isrtab[MAX_ISR_ENTRY];      /* list of interrupt service routines */

+
 /*
 * clear the table of interrupt service handlers
 */
@@ -117,7 +118,7 @@ bool isr_enable_int_source(int int_source)
    }
    else
    {
-        err("vector %d does not correspond to an internal interrupt source\r\n");
+        dbg("vector %d does not correspond to an internal interrupt source\r\n");
        return false;
    }

@@ -137,9 +138,9 @@ bool isr_register_handler(int vector, int level, int priority, bool (*handler)(v
    int index;
    int int_source;

-    if ((vector == 0) || (handler == NULL))
+    if ((vector <= 0) || (handler == NULL))
    {
-        dbg("illegal vector or handler!\r\n");
+        dbg("illegal vector or handler (vector=%x, handler=%p)!\r\n", vector, handler);

        return false;
    }
@@ -163,18 +164,20 @@ bool isr_register_handler(int vector, int level, int priority, bool (*handler)(v

            int_source = vector - 64;

-            if (!isr_enable_int_source(int_source))
+            if (int_source >= 0)
            {
-                err("failed to enable internal interrupt souce %d in IMRL/IMRH\r\n", int_source);
-                return false;
-            }
+                if (!isr_enable_int_source(int_source))
+                {
+                    dbg("failed to enable internal interrupt souce %d in IMRL/IMRH\r\n", int_source);
+                    return false;
+                }

-            if (!isr_set_prio_and_level(int_source, priority, level))
-            {
-                err("failed to set priority and level for interrupt source %d\r\n", int_source);
-                return false;
+                if (!isr_set_prio_and_level(int_source, priority, level))
+                {
+                    dbg("failed to set priority and level for interrupt source %d\r\n", int_source);
+                    return false;
+                }
            }
-
            return true;
        }
    }
@@ -233,6 +236,7 @@ bool isr_execute_handler(int vector)
    return true;
 }

+#if defined(MACHINE_FIREBEE)
 /*
 * PIC interrupt handler for Firebee
 *
@@ -243,24 +247,27 @@ bool pic_interrupt_handler(void *arg1, void *arg2)
 {
    uint8_t rcv_byte;

-    rcv_byte = MCF_PSC3_PSCRB_8BIT;
+    dbg("PIC interrupt\r\n");
+
+    rcv_byte = read_pic_byte();
    if (rcv_byte == 2)                  /* PIC requests RTC data */
    {
-        uint8_t *rtc_reg = (uint8_t *) 0xffff8961;
-        uint8_t *rtc_data = (uint8_t *) 0xffff8963;
+        volatile uint8_t *rtc_reg = (uint8_t *) 0xffff8961;
+        volatile uint8_t *rtc_data = (uint8_t *) 0xffff8963;
        int index = 0;

        err("PIC interrupt: requesting RTC data\r\n");

-        MCF_PSC3_PSCTB_8BIT = 0x82;     // header byte to PIC
+        write_pic_byte(0x82);     // header byte to PIC
        do
        {
-            *rtc_reg = 0;
-            MCF_PSC3_PSCTB_8BIT = *rtc_data;
-        } while (index++ < 64);
+            *rtc_reg = index;
+            write_pic_byte(*rtc_data);
+        } while (++index < 64);
    }
    return true;
 }
+#endif /* MACHINE_FIREBEE */

 bool xlbpci_interrupt_handler(void *arg1, void *arg2)
 {
@@ -332,6 +339,12 @@ bool irq5_handler(void *arg1, void *arg2)
        pending_interrupts & FBEE_INTR_PCI_INTC ||
        pending_interrupts & FBEE_INTR_PCI_INTD)
    {
+        int handle;
+
+        if ((handle = pci_get_interrupt_cause() != -1))
+        {
+            pci_call_interrupt_chain(handle, 0L);
+        }
        dbg("PCI interrupt IRQ5\r\n");
        FBEE_INTR_CLEAR = FBEE_INTR_PCI_INTA |
                          FBEE_INTR_PCI_INTB |
@@ -345,14 +358,6 @@ bool irq5_handler(void *arg1, void *arg2)
        FBEE_INTR_CLEAR = FBEE_INTR_DSP;
    }

-    if (pending_interrupts & FBEE_INTR_VSYNC || pending_interrupts & FBEE_INTR_HSYNC)
-    {
-        dbg("vsync or hsync interrupt!\r\n");
-        FBEE_INTR_CLEAR = FBEE_INTR_VSYNC | FBEE_INTR_HSYNC;
-        /* hsync and vsync should go to TOS unhandled */
-        return false;
-    }
-
    MCF_EPORT_EPFR |= (1 << 5);             /* clear interrupt from edge port */

    return true;
@@ -474,7 +479,7 @@ bool irq7_handler(void)
 */
 bool gpt0_interrupt_handler(void *arg0, void *arg1)
 {
-    dbg("handler called\n\r");
+    dbg("gpt0 handler called\n\r");

    MCF_GPT0_GMS &= ~1;     /* rearm trigger */
    NOP();
@@ -483,3 +488,26 @@ bool gpt0_interrupt_handler(void *arg0, void *arg1)
    return true;
 }
 #endif /* MACHINE_FIREBEE */
+
+
+uint32_t set_ipl(uint32_t ipl)
+{
+    uint32_t ret;
+
+    __asm__ __volatile__(
+        "		move.w	sr,%[ret]\r\n"			/* retrieve status register */
+        "		andi.l	#0x07,%[ipl]\n\t"		/* mask out ipl bits on new value */
+        "		lsl.l	#8,%[ipl]\n\t"			/* shift them to position */
+        "		move.l	%[ret],d0\n\t"			/* retrieve original value */
+        "		andi.l	#0x0000f8ff,d0\n\t"		/* clear ipl part */
+        "		or.l	%[ipl],d0\n\t"			/* or in new value */
+        "		move.w	d0,sr\n\t"				/* put it in place */
+        "		andi.l	#0x0700,%[ret]\r\n"		/* mask out ipl bits */
+        "		lsr.l	#8,%[ret]\r\n"			/* shift them to position */
+        : [ret] "=&d" (ret)		/* output */
+        : [ipl] "d" (ipl)		/* input */
+        : "cc"	/* clobber */
+    );
+
+    return ret;
+}
--- a/sys/mmu.c
+++ b/sys/mmu.c
@@ -1,6 +1,7 @@
 #include "mmu.h"
 #include "acia.h"
 #include "exceptions.h"
+#include "pci.h"

 #if defined(MACHINE_FIREBEE)
 #include "firebee.h"
@@ -79,7 +80,7 @@
 #else
 #define dbg(format, arg...) do {;} while (0)
 #endif /* DBG_MMU */
-#define err(format, arg...) do { xprintf("ERROR (%s()): " format, __FUNCTION__, ##arg); } while(0);
+#define err(format, arg...) do { xprintf("ERROR (%s()): " format, __FUNCTION__, ##arg); } while(0)

 /*
 * set ASID register
@@ -229,8 +230,6 @@ static struct virt_to_phys translation[] =
    { 0x00000000, 0x00e00000, 0x00000000 },     /* map first 14 MByte to first 14 Mb of SD ram */
    { 0x00e00000, 0x00100000, 0x00000000 },     /* map TOS to SDRAM */
    { 0x01000000, 0x04000000, 0x00000000 },     /* map rest of ram virt = phys */
-    { 0x60000000, 0x10000000, 0x00000000 },     /* map CPLD CF card I/O area */
-
 };
 #elif defined(MACHINE_M54455)
 /* FIXME: this is not determined yet! */
@@ -248,7 +247,7 @@ static struct virt_to_phys translation[] =

 static int num_translations = sizeof(translation) / sizeof(struct virt_to_phys);

-static inline int32_t lookup_phys(int32_t virt)
+static inline uint32_t lookup_phys(int32_t virt)
 {
    int i;

@@ -264,36 +263,27 @@ static inline int32_t lookup_phys(int32_t virt)
    return -1;
 }

-struct mmu_page_descriptor
-{
-    uint8_t cache_mode          : 2;
-    uint8_t supervisor_protect  : 1;
-    uint8_t read                : 1;
-    uint8_t write               : 1;
-    uint8_t execute             : 1;
-    uint8_t global              : 1;
-    uint8_t locked              : 1;
-};

 /*
 * page descriptors. Size depending on DEFAULT_PAGE_SIZE, either 1M (resulting in 512
 * bytes size) or 8k pages (64k descriptor array size)
 */
-static struct mmu_page_descriptor pages[SDRAM_SIZE / DEFAULT_PAGE_SIZE];
+#define NUM_PAGES    (SDRAM_SIZE / SIZE_DEFAULT)
+static struct mmu_page_descriptor pages[NUM_PAGES];


-int mmu_map_instruction_page(int32_t virt, uint8_t asid)
+int mmu_map_instruction_page(uint32_t virt, uint8_t asid)
 {
-    const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1);       /* pagesize */
-    int page_index = (virt & size_mask) / DEFAULT_PAGE_SIZE;    /* index into page_descriptor array */
-    struct mmu_page_descriptor *page = &pages[page_index];      /* attributes of page to map */
+    const uint32_t size_mask = ~ (SIZE_DEFAULT - 1);                /* pagesize */
+    int page_index = (virt & size_mask) / SIZE_DEFAULT;             /* index into page_descriptor array */
+    struct mmu_page_descriptor *page = &pages[page_index];          /* attributes of page to map */
    int ipl;
-    int32_t phys = lookup_phys(virt);                           /* virtual to physical translation of page */
+    uint32_t phys = lookup_phys(virt);                               /* virtual to physical translation of page */

-    if (phys == -1)
+    if (phys == (uint32_t) -1)
    {
        /* no valid mapping found, caller will issue a bus error in return */
-
+        dbg("no mapping found\r\n");
        return 0;
    }

@@ -316,7 +306,7 @@ int mmu_map_instruction_page(int32_t virt, uint8_t asid)
        MCF_MMU_MMUTR_V;                                            /* valid */

    MCF_MMU_MMUDR = (phys & size_mask) |                            /* physical address */
-        MCF_MMU_MMUDR_SZ(DEFAULT_PAGE_SIZE) |                       /* page size */
+        MCF_MMU_MMUDR_SZ(MMU_PAGE_SIZE_DEFAULT) |                   /* page size */
        MCF_MMU_MMUDR_CM(page->cache_mode) |                        /* cache mode */
        (page->supervisor_protect ? MCF_MMU_MMUDR_SP : 0) |         /* supervisor protect */
        (page->read ? MCF_MMU_MMUDR_R : 0) |                        /* read access enable */
@@ -337,19 +327,19 @@ int mmu_map_instruction_page(int32_t virt, uint8_t asid)
    return 1;
 }

-int mmu_map_data_page(int32_t virt, uint8_t asid)
+int mmu_map_data_page(uint32_t virt, uint8_t asid)
 {
    uint16_t ipl;
-    const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1);       /* pagesize */
-    int page_index = (virt & size_mask) / DEFAULT_PAGE_SIZE;    /* index into page_descriptor array */
+    const uint32_t size_mask = ~ (SIZE_DEFAULT - 1);            /* pagesize */
+    int page_index = (virt & size_mask) / SIZE_DEFAULT;         /* index into page_descriptor array */
    struct mmu_page_descriptor *page = &pages[page_index];      /* attributes of page to map */

-    int32_t phys = lookup_phys(virt);                           /* virtual to physical translation of page */
+    uint32_t phys = lookup_phys(virt);                           /* virtual to physical translation of page */

-    if (phys == -1)
+    if (phys == (uint32_t) -1)
    {
        /* no valid mapping found, caller will issue a bus error in return */
-
+        dbg("no mapping found\r\n");
        return 0;
    }

@@ -370,7 +360,7 @@ int mmu_map_data_page(int32_t virt, uint8_t asid)
        MCF_MMU_MMUTR_V;                                            /* valid */

    MCF_MMU_MMUDR = (phys & size_mask) |                            /* physical address */
-        MCF_MMU_MMUDR_SZ(DEFAULT_PAGE_SIZE) |                       /* page size */
+        MCF_MMU_MMUDR_SZ(MMU_PAGE_SIZE_DEFAULT) |                   /* page size */
        MCF_MMU_MMUDR_CM(page->cache_mode) |                        /* cache mode */
        (page->supervisor_protect ? MCF_MMU_MMUDR_SP : 0) |         /* supervisor protect */
        (page->read ? MCF_MMU_MMUDR_R : 0) |                        /* read access enable */
@@ -399,7 +389,7 @@ int mmu_map_data_page(int32_t virt, uint8_t asid)
 * per instruction as a minimum, more for performance. Thus locked pages (that can't be touched by the
 * LRU algorithm) should be used sparsingly.
 */
-int mmu_map_page(int32_t virt, int32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor *flags)
+uint32_t mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor *flags)
 {
    int size_mask;
    int ipl;
@@ -433,17 +423,18 @@ int mmu_map_page(int32_t virt, int32_t phys, enum mmu_page_size sz, uint8_t page

    ipl = set_ipl(7);       /* do not disturb */

-    MCF_MMU_MMUTR = ((int) virt & size_mask) |                      /* virtual address */
+    MCF_MMU_MMUTR = (virt & size_mask) |                            /* virtual address */
        MCF_MMU_MMUTR_ID(page_id) |                                 /* address space id (ASID) */
        (flags->global ? MCF_MMU_MMUTR_SG : 0) |                    /* shared global */
        MCF_MMU_MMUTR_V;                                            /* valid */

-    MCF_MMU_MMUDR = ((int) phys & size_mask) |                      /* physical address */
+    MCF_MMU_MMUDR = (phys & size_mask) |                            /* physical address */
        MCF_MMU_MMUDR_SZ(sz) |                                      /* page size */
        MCF_MMU_MMUDR_CM(flags->cache_mode) |
        (flags->read ? MCF_MMU_MMUDR_R : 0) |                       /* read access enable */
        (flags->write ? MCF_MMU_MMUDR_W : 0) |                      /* write access enable */
        (flags->execute ? MCF_MMU_MMUDR_X : 0) |                    /* execute access enable */
+        (flags->supervisor_protect ? MCF_MMU_MMUDR_SP : 0) |        /* supervisor protect */
        (flags->locked ? MCF_MMU_MMUDR_LK : 0);

    MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |     /* access TLB, data */
@@ -456,7 +447,7 @@ int mmu_map_page(int32_t virt, int32_t phys, enum mmu_page_size sz, uint8_t page

    set_ipl(ipl);

-    dbg("mapped virt=0x%08x to phys=0x%08x\r\n", virt, phys);
+    dbg("mapped virt=0x%08x to phys=0x%08x size mask 0x%lx\r\n", virt, phys, size_mask);

    return 1;
 }
@@ -477,26 +468,24 @@ void mmu_init(void)
    /*
     * prelaminary initialization of page descriptor 0 (root) table
     */
-    for (i = 0; i < sizeof(pages) / sizeof(struct mmu_page_descriptor); i++)
+    for (i = 0; i < NUM_PAGES; i++)
    {
-        uint32_t addr = i * DEFAULT_PAGE_SIZE;
+        uint32_t addr = i * SIZE_DEFAULT;

 #if defined(MACHINE_FIREBEE)
        if (addr >= 0x00f00000UL && addr < 0x00ffffffUL)        /* Falcon I/O area on the Firebee */
        {
            pages[i].cache_mode = CACHE_NOCACHE_PRECISE;
-            pages[i].execute = 0;
+            pages[i].supervisor_protect = 1;
            pages[i].read = 1;
            pages[i].write = 1;
            pages[i].execute = 0;
            pages[i].global = 1;
-            pages[i].supervisor_protect = 1;
        }
        else if (addr >= 0x0UL && addr < 0x00e00000UL)          /* ST-RAM, potential video memory */
        {
            pages[i].cache_mode = CACHE_WRITETHROUGH;
-            pages[i].execute = 1;
-            pages[i].supervisor_protect = 0;
+            pages[i].supervisor_protect = 0; // (addr == 0x0L ? 1 : 0);
            pages[i].read = 1;
            pages[i].write = 1;
            pages[i].execute = 1;
@@ -505,40 +494,45 @@ void mmu_init(void)
        else if (addr >= 0x00e00000UL && addr < 0x00f00000UL)   /* EmuTOS */
        {
            pages[i].cache_mode = CACHE_COPYBACK;
-            pages[i].execute = 1;
-            pages[i].supervisor_protect = 1;
+            pages[i].supervisor_protect = 0;
            pages[i].read = 1;
            pages[i].write = 0;
            pages[i].execute = 1;
            pages[i].global = 1;
        }
+        else if (addr >= 0x00000000 && addr <= 0x00010000)      /* first Megabyte of ST RAM */
+        {
+            pages[i].cache_mode = CACHE_COPYBACK;
+            pages[i].supervisor_protect = 0;
+            pages[i].read = 1;
+            pages[i].write = 1;
+            pages[i].execute = 1;
+            pages[i].global = 1;
+        }
        else
        {
            pages[i].cache_mode = CACHE_COPYBACK;
-            pages[i].execute = 1;
+            pages[i].supervisor_protect = 0;
            pages[i].read = 1;
            pages[i].write = 1;
-            pages[i].supervisor_protect = 0;
+            pages[i].execute = 1;
            pages[i].global = 1;
        }
        pages[i].locked = 0;                /* not locked */
-        pages[0].supervisor_protect = 0;    /* protect system vectors */

 #elif defined(MACHINE_M5484LITE)
        if (addr >= 0x60000000UL && addr < 0x70000000UL)        /* Compact Flash on the m5484lite */
        {
            pages[i].cache_mode = CACHE_NOCACHE_PRECISE;
-            pages[i].execute = 0;
+            pages[i].supervisor_protect = 0;
            pages[i].read = 1;
            pages[i].write = 1;
-            pages[i].execute = 0;
+            pages[i].execute = 1;
            pages[i].global = 1;
-            pages[i].supervisor_protect = 1;
        }
        else if (addr >= 0x0UL && addr < 0x00e00000UL)          /* ST-RAM, potential video memory */
        {
            pages[i].cache_mode = CACHE_WRITETHROUGH;
-            pages[i].execute = 1;
            pages[i].supervisor_protect = 0;
            pages[i].read = 1;
            pages[i].write = 1;
@@ -565,7 +559,6 @@ void mmu_init(void)
            pages[i].global = 1;
        }
        pages[i].locked = 0;                /* not locked */
-        pages[0].supervisor_protect = 0;    /* protect system vectors */

 #elif defined(MACHINE_M54455)
        if (addr >= 0x60000000UL && addr < 0x70000000UL)        /* Compact Flash on the m5484lite */
@@ -608,29 +601,30 @@ void mmu_init(void)
            pages[i].global = 1;
        }
        pages[i].locked = 0;                /* not locked */
-        pages[0].supervisor_protect = 0;    /* protect system vectors */
 #else
 #error Unknown machine!
 #endif /* MACHINE_FIREBEE */
    }

-    set_asid(0);            /* do not use address extension (ASID provides virtual 48 bit addresses */
+    set_asid(0);                        /* do not use address extension (ASID provides virtual 48 bit addresses */
+
+    // pages[0].supervisor_protect = 1;    /* protect system vectors */

    /* set data access attributes in ACR0 and ACR1 */

    /* map PCI address space */
    set_acr0(ACR_W(0) |                             /* read and write accesses permitted */
-            ACR_SP(1) |                             /* supervisor and user mode access permitted */
+            //ACR_SP(1) |                             /* supervisor only access permitted */
            ACR_CM(ACR_CM_CACHE_INH_PRECISE) |      /* cache inhibit, precise */
            ACR_AMM(0) |                            /* control region > 16 MB */
            ACR_S(ACR_S_SUPERVISOR_MODE) |          /* match addresses in supervisor mode only */
            ACR_E(1) |                              /* enable ACR */
 #if defined(MACHINE_FIREBEE)
            ACR_ADMSK(0x7f) |                       /* cover 2GB area from 0x80000000 to 0xffffffff */
-            ACR_BA(0x80000000));                    /* (equals area from 3 to 4 GB */
+            ACR_BA(PCI_MEMORY_OFFSET));             /* (equals area from 3 to 4 GB */
 #elif defined(MACHINE_M5484LITE)
            ACR_ADMSK(0x7f) |                       /* cover 2 GB area from 0x80000000 to 0xffffffff */
-            ACR_BA(0x80000000));
+            ACR_BA(PCI_MEMORY_OFFSET));
 #elif defined(MACHINE_M54455)
            ACR_ADMSK(0x7f) |
            ACR_BA(0x80000000));                    /* FIXME: not determined yet */
@@ -638,8 +632,6 @@ void mmu_init(void)
 #error unknown machine!
 #endif /* MACHINE_FIREBEE */

-    // set_acr1(0x601fc000);
-
    /* data access attributes for BaS in flash */

    set_acr1(ACR_W(0) |
@@ -676,47 +668,18 @@ void mmu_init(void)
            ACR_ADMSK(0x7) |
            ACR_BA(0xe0000000));

-    /* disable ACR1 - 3, essentially disabling all of the above */

+    /* disable ACR3 */
    set_acr3(0x0);

    set_mmubar(MMUBAR + 1);     /* set and enable MMUBAR */

-    /* create locked TLB entries */
-
-    flags.cache_mode = CACHE_COPYBACK;
-    flags.supervisor_protect = 0;
-    flags.read = 1;
-    flags.write = 1;
-    flags.execute = 1;
-    flags.locked = true;
-
-    /* 0x00000000 - 0x00100000 (first MB of physical memory) locked virt = phys */
-    mmu_map_page(0x0, 0x0, MMU_PAGE_SIZE_1M, 0, &flags);
-
-#ifdef _NOT_USED_
-#if defined(MACHINE_FIREBEE)
-    /*
-     * 0x00d00000 - 0x00e00000 (last megabyte of ST RAM = Falcon video memory) locked ID = 6
-     * mapped to physical address 0x60d0'0000 (FPGA video memory)
-     * video RAM: read write execute normal write true
-     */
-    flags.cache_mode = CACHE_WRITETHROUGH;
-    flags.supervisor_protect = 0;
-    flags.read = 1;
-    flags.write = 1;
-    flags.execute = 1;
-    flags.locked = true;
-    mmu_map_page(0x00d00000, 0x60d00000, MMU_PAGE_SIZE_1M, SCA_PAGE_ID, &flags);
-#endif /* MACHINE_FIREBEE */
-#endif
-
    /*
     * Make the TOS (in SDRAM) read-only
     * This maps virtual 0x00e0'0000 - 0x00ef'ffff to the same virtual address
     */
    flags.cache_mode = CACHE_COPYBACK;
-    flags.supervisor_protect = 0;
+    flags.supervisor_protect = 0;  // needs to stay like this or cf_flasher will choke */
    flags.read = 1;
    flags.write = 0;
    flags.execute = 1;
@@ -735,6 +698,17 @@ void mmu_init(void)
    flags.execute = 0;
    flags.locked = 1;
    mmu_map_page(0x00f00000, 0xfff00000, MMU_PAGE_SIZE_1M, 0, &flags);
+#elif defined(MACHINE_M5484LITE)
+    /*
+     * Map m5484LITE CPLD access
+     */
+    flags.cache_mode = CACHE_NOCACHE_PRECISE;
+    flags.supervisor_protect = 1;
+    flags.read = 1;
+    flags.write = 1;
+    flags.execute = 0;
+    flags.locked = 1;
+    mmu_map_page(0x6a000000, 0x6a000000, MMU_PAGE_SIZE_1M, 0, &flags);
 #endif /* MACHINE_FIREBEE */

    /*
@@ -742,7 +716,7 @@ void mmu_init(void)
     * virtual address. This is also used (completely) when BaS is in RAM
     */
    flags.cache_mode = CACHE_COPYBACK;
-    flags.supervisor_protect = 1;
+    flags.supervisor_protect = 0;
    flags.read = 1;
    flags.write = 1;
    flags.execute = 1;
@@ -754,7 +728,7 @@ void mmu_init(void)
     * virtual address. Used uncached for drivers.
     */
    flags.cache_mode = CACHE_NOCACHE_PRECISE;
-    flags.supervisor_protect = 1;
+    flags.supervisor_protect = 0;
    flags.read = 1;
    flags.write = 1;
    flags.execute = 0;
@@ -763,12 +737,11 @@ void mmu_init(void)
 }


-uint32_t mmutr_miss(uint32_t mmu_sr, uint32_t fault_address, uint32_t pc,
-                uint32_t format_status)
+uint32_t mmutr_miss(uint32_t mmu_sr, uint32_t fault_address, uint32_t pc, uint32_t format_status)
 {
    uint32_t fault = format_status & 0xc030000;

-    dbg("MMU TLB MISS accessing 0x%08x\r\nFS = 0x%08x\r\nPC = 0x%08x\r\n", fault_address, format_status, pc);
+    //dbg("MMU TLB MISS accessing 0x%08x\r\nFS = 0x%08x\r\nPC = 0x%08x\r\n", fault_address, format_status, pc);
    // flush_and_invalidate_caches();

    switch (fault)
@@ -786,22 +759,24 @@ uint32_t mmutr_miss(uint32_t mmu_sr, uint32_t fault_address, uint32_t pc,

            if (!mmu_map_instruction_page(pc, 0))
            {
-                dbg("bus error\r\n");
+                dbg("ITLB miss bus error\r\n");
                return 1;   /* bus error */
            }

+#ifdef _NOT_USED_
            /* due to prefetch, it makes sense to map the next adjacent page also for ITLBs */
-            if (pc + DEFAULT_PAGE_SIZE < TARGET_ADDRESS)
+            if (pc + SIZE_DEFAULT < TARGET_ADDRESS)
            {
                /*
                 * only do this if the next page is still valid RAM
                 */
-                if (!mmu_map_instruction_page(pc + DEFAULT_PAGE_SIZE, 0))
+                if (!mmu_map_instruction_page(pc + MMU_DEFAULT_PAGE_SIZE, 0))
                {
-                    dbg("bus error\r\n");
+                    dbg("ITLB next page bus error\r\n");
                    return 1;   /* bus error */
                }
            }
+#endif /* _NOT_USED_ */
            break;

        case 0x08020000:    /* TLB miss on data write */
@@ -815,14 +790,58 @@ uint32_t mmutr_miss(uint32_t mmu_sr, uint32_t fault_address, uint32_t pc,

            if (!mmu_map_data_page(fault_address, 0))
            {
-                dbg("bus error\r\n");
+                dbg("DTLB miss bus error\r\n");
                return 1;   /* bus error */
            }
            break;

+        case 0x0c010000:
+        case 0x08010000:
+            dbg("privilege violation accessing 0x%08x\r\n"
+                "FS = 0x%08x\r\n"
+                "MMUSR = 0x%08x\r\n"
+                "PC = 0x%08x\r\n",
+                fault_address, format_status, mmu_sr, pc);
+            dbg("fault = 0x%08x\r\n", fault);
+#ifdef _DOES_NOT_WORK_
+            /*
+             * check if its one of our "special cases" and map a user page on top of it if user
+             * mode access should be allowed
+             */
+            if (fault_address >= 1024 && fault_address < 0x00100000) /* ST-RAM */
+            {
+                struct mmu_page_descriptor flags =
+                {
+                    .cache_mode = CACHE_COPYBACK,
+                    .supervisor_protect = 0,
+                    .read = 1,
+                    .write = 1,
+                    .execute = 1,
+                    .global = 1,
+                    .locked = 0
+                };
+
+                uint32_t virt = fault_address & ~(SIZE_1K - 1);
+                uint32_t phys = (fault_address & (~(SIZE_1K - 1))) + 0x60000000;
+                dbg("mapping helper page virt=0x%08x to phys=0x%08x\r\n", virt, phys);
+                if (!mmu_map_page(virt, phys, MMU_PAGE_SIZE_1K, 0, &flags))
+                {
+                    dbg("privilege violation (bus error)\r\n");
+                    return 1;
+                }
+            }
+#endif
+            return 1;
+            break;
+
        /* else issue a bus error */
        default:
-            dbg("bus error\r\n");
+            dbg("bus error accessing 0x%08x\r\n"
+                "FS = 0x%08x\r\n"
+                "MMUSR = 0x%08x\r\n"
+                "PC = 0x%08x\r\n",
+                fault_address, format_status, mmu_sr, pc);
+            dbg("fault = 0x%08x\r\n", fault);
            return 1;       /* signal bus error to caller */
    }
 #ifdef DBG_MMU
@@ -858,14 +877,14 @@ uint32_t mmutr_miss(uint32_t mmu_sr, uint32_t fault_address, uint32_t pc,
 *
 * return: 0 if failed (page not in translation table), 1 otherwise
 */
-int32_t mmu_map_data_page_locked(uint32_t virt, uint32_t size, int asid)
+uint32_t mmu_map_data_page_locked(uint32_t virt, uint32_t size, int asid)
 {
-    const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1);       /* pagesize */
-    int page_index = (virt & size_mask) / DEFAULT_PAGE_SIZE;    /* index into page_descriptor array */
+    const uint32_t size_mask = ~ (SIZE_DEFAULT - 1);       /* pagesize */
+    int page_index = (virt & size_mask) / SIZE_DEFAULT;    /* index into page_descriptor array */
    struct mmu_page_descriptor *page = &pages[page_index];          /* attributes of page to map */
    int i = 0;

-    while (page_index * DEFAULT_PAGE_SIZE < virt + size)
+    while (page_index * SIZE_DEFAULT < virt + size)
    {
        if (page->locked)
        {
@@ -877,7 +896,7 @@ int32_t mmu_map_data_page_locked(uint32_t virt, uint32_t size, int asid)
            mmu_map_data_page(virt, 0);
            i++;
        }
-        virt += DEFAULT_PAGE_SIZE;
+        virt += SIZE_DEFAULT;
    }

    dbg("%d pages locked\r\n", i);
@@ -890,18 +909,18 @@ int32_t mmu_map_data_page_locked(uint32_t virt, uint32_t size, int asid)
 *
 * return: 0 if failed (page not found), 1 otherwise
 */
-int32_t mmu_unlock_data_page(uint32_t address, uint32_t size, int asid)
+uint32_t mmu_unlock_data_page(uint32_t address, uint32_t size, int asid)
 {
    int curr_asid;
-    const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1);
-    int page_index = (address & size_mask) / DEFAULT_PAGE_SIZE;     /* index into page descriptor array */
+    const uint32_t size_mask = ~ (SIZE_DEFAULT - 1);
+    int page_index = (address & size_mask) / SIZE_DEFAULT;     /* index into page descriptor array */
    struct mmu_page_descriptor *page = &pages[page_index];

    curr_asid = set_asid(asid);         /* set asid to the one to search for */

    /* TODO: check for pages[] array bounds */

-    while (page_index * DEFAULT_PAGE_SIZE < address + size)
+    while (page_index * SIZE_DEFAULT < address + size)
    {
        MCF_MMU_MMUAR = address + page->supervisor_protect;
        MCF_MMU_MMUOR = MCF_MMU_MMUOR_STLB |        /* search TLB */
@@ -930,7 +949,7 @@ int32_t mmu_unlock_data_page(uint32_t address, uint32_t size, int asid)
    return 1;   /* success */
 }

-int32_t mmu_report_locked_pages(uint32_t *num_itlb, uint32_t *num_dtlb)
+uint32_t mmu_report_locked_pages(uint32_t *num_itlb, uint32_t *num_dtlb)
 {
    int i;
    int li = 0;
@@ -979,5 +998,5 @@ int32_t mmu_report_locked_pages(uint32_t *num_itlb, uint32_t *num_dtlb)

 uint32_t mmu_report_pagesize(void)
 {
-    return DEFAULT_PAGE_SIZE;
+    return SIZE_DEFAULT;
 }
--- a/sys/startcf.S
+++ b/sys/startcf.S
@@ -4,64 +4,74 @@
 * so it will be placed at the very beginning of the ROM.
 */

-		.equ	MCF_MMU_MMUCR, __MMUBAR + 0
+        .equ	MCF_MMU_MMUCR, __MMUBAR + 0

-		.global _rom_header
-		.global _rom_entry
+        .globl	_rom_header
+        .globl	_rom_entry

-		.extern	_initialize_hardware
-		.extern _rt_mbar
+        .extern	_initialize_hardware
+        .extern	_rt_mbar

 /* ROM header */
 _rom_header:
-		/* The first long is supposed to be the initial SP.
-		 * We replace it by bra.s to allow running the ROM from the first byte.
-		 * Then we add a fake jmp instruction for pretty disassembly.
-		 */
-		bra.s	_rom_entry	// Short jump to the real entry point
-		.short	0x4ef9		// Fake jmp instruction
-		/* The second long is the initial PC */
-		.long	_rom_entry	// Real entry point
+        /* The first long is supposed to be the initial SP.
+         * We replace it by bra.s to allow running the ROM from the first byte.
+         * Then we add a fake jmp instruction for pretty disassembly.
+         */
+        bra.s	_rom_entry		// Short jump to the real entry point
+        .short	0x4ef9			// Fake jmp instruction
+        /* The second long is the initial PC */
+        .long	_rom_entry		// Real entry point

 /* ROM entry point */
 _rom_entry:
-		/* disable interrupts */
-		move.w #0x2700,SR
+        /* disable interrupts */
+        move.w #0x2700,sr

-		/* Initialize MBAR */
-		move.l	#__MBAR,d0
-		movec	d0,MBAR
-		move.l	d0,_rt_mbar
+#if !defined(MACHINE_M54455)			// MCF54455 does not have the MBAR register
+        /* Initialize MBAR */
+        move.l	#__MBAR,d0
+        movec	d0,MBAR
+        move.l	d0,_rt_mbar
+#endif

-		/* mmu off */
-		move.l	#__MMUBAR+1,d0
-		movec	d0,MMUBAR
+        /* mmu off */
+        move.l	#__MMUBAR+1,d0
+        movec	d0,MMUBAR

-		clr.l	d0
-		move.l	d0,MCF_MMU_MMUCR
+        clr.l	d0
+        move.l	d0,MCF_MMU_MMUCR
+        nop

-		/* Initialize RAMBARs: locate SRAM and validate it */
-		move.l	#__RAMBAR0 + 0x7,d0 	/* supervisor only */
-		movec	d0,RAMBAR0
-		move.l	#__RAMBAR1 + 0x1,d0
-		movec	d0,RAMBAR1
+#if !defined(MACHINE_M54455)			// MCF54455 does not have RAMBAR0 and RAMBAR1 registers */

-		/* set stack pointer to end of SRAM */
-		lea 	__SUP_SP,a7
-		move.l	#0,(sp)
+        /* Initialize RAMBARs: locate SRAM and validate it */
+        move.l	#__RAMBAR0 + 0x7,d0 	// supervisor only
+        movec	d0,RAMBAR0
+        move.l	#__RAMBAR1 + 0x1,d0
+        movec	d0,RAMBAR1
+#else
+        move.l	#__RAMBAR0 + 0x7,d0
+        movec	d0,RAMBAR
+#endif

-		/*
-		 * Initialize the processor caches.
-		 * The instruction cache is fully enabled.
-		 * The data cache is enabled, but cache-inhibited by default.
-		 * Later, the MMU will fully activate the data cache for specific areas.
-		 * It is important to enable both caches now, otherwise cpushl would hang.
-		 */
+        /* set stack pointer to end of SRAM */
+        lea 	__SUP_SP,a7
+        move.l	#0,(sp)

-		move.l	#0xa50c8120,d0
-		movec	d0,cacr
-		andi.l	#0xfefbfeff,d0			// Clear invalidate bits
-		move.l	d0,_rt_cacr
+        /*
+         * Initialize the processor caches.
+         * The instruction cache is fully enabled.
+         * The data cache is enabled, but cache-inhibited by default.
+         * Later, the MMU will fully activate the data cache for specific areas.
+         * It is important to enable both caches now, otherwise cpushl would hang.
+         */
+
+        move.l	#0xa50c8120,d0
+        movec	d0,cacr
+        andi.l	#0xfefbfeff,d0			// Clear invalidate bits
+        move.l	d0,_rt_cacr
+
+        /* initialize any hardware specific issues */
+        bra    _initialize_hardware

-		/* initialize any hardware specific issues */
-		bra    _initialize_hardware
--- a/sys/sysinit.c
+++ b/sys/sysinit.c
@@ -46,8 +46,6 @@
 #else
 #error "unknown machine"
 #endif /* MACHINE_M5484LITE */
-
-#
 #include "dma.h"
 #include "mod_devicetable.h"
 #include "pci_ids.h"
@@ -70,7 +68,7 @@ extern volatile long _VRAM; /* start address of video ram from linker script */
 * BYT3 = 7.576ns/tick = 132.00MHz offset 3
 * count down!!! 132MHz!!!
 */
-void init_slt(void)
+static void init_slt(void)
 {
    xprintf("slice timer initialization: ");
    MCF_SLT0_STCNT = 0xffffffff;
@@ -81,7 +79,7 @@ void init_slt(void)
 /*
 * init GPIO general purpose I/O module
 */
-void init_gpio(void)
+static void init_gpio(void)
 {
    /*
     * pad register P.S.:FBCTL and FBCS set correctly at reset
@@ -128,13 +126,13 @@ void init_gpio(void)
     * /PCIBG1 used as /PCIBG1
     * /PCIBG0 used as /PCIBG0
     */
-#if MACHINE_FIREBEE
+#if defined(MACHINE_FIREBEE)
    MCF_PAD_PAR_PCIBG = MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST |
            MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO |
            MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 |
            MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 |
            MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0;
-#elif MACHINE_M5484LITE
+#elif defined(MACHINE_M5484LITE)
    MCF_PAD_PAR_PCIBG = MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4 |
            MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3 |
            MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 |
@@ -214,16 +212,16 @@ void init_gpio(void)
 /*
 * init serial
 */
-void init_serial(void)
+static void init_serial(void)
 {
    /* PSC0: SER1 */
    MCF_PSC0_PSCSICR = 0;       /* PSC control register: select UART mode */
    MCF_PSC0_PSCCSR = 0xDD;     /* use TX and RX baud rate from PSC timer */
    MCF_PSC0_PSCCTUR = 0x00;    /* =\ */
-#ifdef MACHINE_FIREBEE
+#if defined(MACHINE_FIREBEE)
    MCF_PSC0_PSCCTLR = 36;      /* divide sys_clk by 36 => BAUD RATE = 115200 bps */
 #endif
-#ifdef MACHINE_M5484LITE
+#if defined(MACHINE_M5484LITE)
    MCF_PSC0_PSCCTLR = 27;      /* LITE board has 100 MHz sys_clk only */
 #endif
    MCF_PSC0_PSCCR = 0x20;      /* reset receiver and RxFIFO */
@@ -244,7 +242,7 @@ void init_serial(void)
    MCF_PSC0_PSCOPSET = 0x01;
    MCF_PSC0_PSCCR = 0x05;

-#ifdef MACHINE_FIREBEE  /* PSC3 is not connected to anything on the LITE board */
+#if defined(MACHINE_FIREBEE)  /* PSC3 is not connected to anything on the LITE board */
    /* PSC3: PIC */
    MCF_PSC3_PSCSICR = 0;   // UART
    MCF_PSC3_PSCCSR = 0xDD;
@@ -267,16 +265,13 @@ void init_serial(void)
    MCF_PSC3_PSCCR = 0x05;
 #endif /* MACHINE_FIREBEE */

-    MCF_INTC_ICR32 = MCF_INTC_ICR_IL(7) |
-                     MCF_INTC_ICR_IL(4);      /* PSC3 interrupt vector. Do we need it? */
-
    xprintf("\r\nserial interfaces initialization: finished\r\n");
 }

 /********************************************************************/
 /* Initialize DDR DIMMs on the EVB board */
 /********************************************************************/
-bool init_ddram(void)
+static bool init_ddram(void)
 {
    xprintf("SDRAM controller initialization: ");

@@ -298,7 +293,7 @@ bool init_ddram(void)
         */
        MCF_SDRAMC_SDRAMDS = 0x000002AA;/* SDRAMDS configuration */

-#if MACHINE_FIREBEE
+#if defined(MACHINE_FIREBEE)
        MCF_SDRAMC_CS0CFG = 0x0000001A; /* SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) */
        MCF_SDRAMC_CS1CFG = 0x0800001A; /* SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) */
        MCF_SDRAMC_CS2CFG = 0x1000001A; /* SDRAM CS2 configuration (128Mbytes 1000_0000 - 07FF_FFFF) */
@@ -341,7 +336,7 @@ bool init_ddram(void)
        MCF_SDRAMC_SDMR = 0x008D0000;   /* SDMR (write to LMR) */
        MCF_SDRAMC_SDCR = 0x710D0F00;   /* SDCR (lock SDMR and enable refresh) */

-#elif MACHINE_M5484LITE
+#elif defined(MACHINE_M5484LITE)
        MCF_SDRAMC_CS0CFG = 0x00000019; /* SDRAM CS0 configuration (64 Mbytes 0000_0000 - 03FF_FFFF) */
        MCF_SDRAMC_CS1CFG = 0x00000000; /* SDRAM CS1 configuration - off */
        MCF_SDRAMC_CS2CFG = 0x00000000; /* SDRAM CS2 configuration - off */
@@ -401,65 +396,58 @@ bool init_ddram(void)
 /*
 * initialize FlexBus chip select registers
 */
-void init_fbcs()
+static void init_fbcs()
 {
    xprintf("FlexBus chip select registers initialization: ");

    /* Flash */
-    MCF_FBCS0_CSAR = BOOTFLASH_BASE_ADDRESS;    /* flash base address */
-    MCF_FBCS0_CSCR = MCF_FBCS_CSCR_PS_16 |      /* 16 bit word access */
-            MCF_FBCS_CSCR_WS(6)|                        /* 6 Waitstates */
-            MCF_FBCS_CSCR_AA |
-            MCF_FBCS_CSCR_ASET(1) |
-            MCF_FBCS_CSCR_RDAH(1);              /* chip errata SECF077 */
+    MCF_FBCS0_CSAR = MCF_FBCS_CSAR_BA(BOOTFLASH_BASE_ADDRESS);    /* flash base address */
+    MCF_FBCS0_CSCR = MCF_FBCS_CSCR_PS_16 |              /* 16 bit word access */
+            MCF_FBCS_CSCR_WS(8)|                        /* 6 wait states */
+            MCF_FBCS_CSCR_AA |                          /* auto /TA acknowledge */
+            MCF_FBCS_CSCR_ASET(1) |                     /* assert chip select on second rising edge after address assertion */
+            MCF_FBCS_CSCR_RDAH(1);                      /* chip errata SECF077 */
    MCF_FBCS0_CSMR = BOOTFLASH_BAM |
            MCF_FBCS_CSMR_V;                            /* enable */


-#if MACHINE_FIREBEE /* FBC setup for FireBee */
-    MCF_FBCS1_CSAR = 0xFFF00000;                        /* ATARI I/O ADRESS */
+#if defined(MACHINE_FIREBEE) /* FBC setup for FireBee */
+    MCF_FBCS1_CSAR = MCF_FBCS_CSAR_BA(0xFFF00000);      /* ATARI I/O address range */
    MCF_FBCS1_CSCR = MCF_FBCS_CSCR_PS_16                /* 16BIT PORT */
-        | MCF_FBCS_CSCR_WS(8)                           /* DEFAULT 8WS */
-        | MCF_FBCS_CSCR_AA;                             /* AA */
+        | MCF_FBCS_CSCR_WS(32)                           /* 8 wait states */
+        | MCF_FBCS_CSCR_AA;                             /* auto /TA acknowledge */
    MCF_FBCS1_CSMR = MCF_FBCS_CSMR_BAM_1M | MCF_FBCS_CSMR_V;

-    MCF_FBCS2_CSAR = 0xF0000000;                        /* Firebee new I/O address range */
+    MCF_FBCS2_CSAR = MCF_FBCS_CSAR_BA(0xF0000000);      /* Firebee new I/O address range */
    MCF_FBCS2_CSCR = MCF_FBCS_CSCR_PS_32                /* 32BIT PORT */
-        | MCF_FBCS_CSCR_WS(8)                           /* DEFAULT 4WS */
-        | MCF_FBCS_CSCR_AA;                             /* AA */
+        | MCF_FBCS_CSCR_WS(32)                           /* 4 wait states */
+        | MCF_FBCS_CSCR_AA;                             /* auto /TA acknowledge */
    MCF_FBCS2_CSMR = (MCF_FBCS_CSMR_BAM_128M            /* F000'0000-F7FF'FFFF */
              | MCF_FBCS_CSMR_V);

-    MCF_FBCS3_CSAR = 0xF8000000;                        /* Firebee new I/O address range */
-    MCF_FBCS3_CSCR = MCF_FBCS_CSCR_PS_16                /* 16BIT PORT */
-        | MCF_FBCS_CSCR_AA; // AA
+    MCF_FBCS3_CSAR = MCF_FBCS_CSAR_BA(0xF8000000);      /* Firebee SRAM */
+    MCF_FBCS3_CSCR = MCF_FBCS_CSCR_PS_16                /* 16 bit port */
+        | MCF_FBCS_CSCR_WS(32)                          /* 0 wait states */
+        | MCF_FBCS_CSCR_AA;                             /* auto /TA acknowledge */
    MCF_FBCS3_CSMR = (MCF_FBCS_CSMR_BAM_64M             /* F800'0000-FBFF'FFFF */
              | MCF_FBCS_CSMR_V);

-    MCF_FBCS4_CSAR = 0x40000000;                        /* video ram area, FB_CS3 not used, decoded on FPGA */
-    MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32                /* 32BIT PORT */
+    /*
+     * Note: burst read/write settings of the following FBCS are purely "cosmetical".
+     * The Coldfire FlexBus only "bursts" on a smaller port size than 32 bit up to 32 bit,
+     * i.e. it can burst on an 8 bit port up to 4 burst cycles or two on a 16 bit port.
+     * Enabling burst on a 32 bit port has no effect (unfortunately).
+     */
+    MCF_FBCS4_CSAR = MCF_FBCS_CSAR_BA(0x40000000);      /* video ram area, FB_CS3 not used, decoded on FPGA */
+    MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32                /* 32 bit port */
+        | MCF_FBCS_CSCR_WS(32)                          /* 0 wait states */
+        | MCF_FBCS_CSCR_AA                              /* /TA auto acknowledge */
        | MCF_FBCS_CSCR_BSTR                            /* burst read enable */
        | MCF_FBCS_CSCR_BSTW;                           /* burst write enable */
    MCF_FBCS4_CSMR = MCF_FBCS_CSMR_BAM_1G               /* 4000'0000-7FFF'FFFF */
              | MCF_FBCS_CSMR_V;
-#elif MACHINE_M5484LITE
-    /* disable other FBCS for now */
-    MCF_FBCS1_CSMR = 0;
-    MCF_FBCS2_CSMR = 0;
-    MCF_FBCS3_CSMR = 0;
-    MCF_FBCS4_CSMR = 0;

-    MCF_FBCS5_CSAR = MCF_FBCS_CSAR_BA(0x60000000);
-    MCF_FBCS5_CSCR = MCF_FBCS_CSCR_PS_16    /* CPLD access */
-        | MCF_FBCS_CSCR_WS(32)
-        | MCF_FBCS_CSCR_ASET(1)
-        | MCF_FBCS_CSCR_AA;
-    MCF_FBCS5_CSMR = MCF_FBCS_CSMR_BAM_256M
-        | MCF_FBCS_CSMR_V;
-#endif /* MACHINE_FIREBEE */
-
-
-#ifndef MACHINE_M5484LITE
+    /* disable FBCS5 on Firebee */
    MCF_FBCS5_CSAR = 0x0;
    MCF_FBCS5_CSCR = MCF_FBCS_CSCR_PS_8
        | MCF_FBCS_CSCR_BSTR
@@ -467,12 +455,27 @@ void init_fbcs()
        | MCF_FBCS_CSCR_RDAH(1);                /* chip errata SECF077 */
    MCF_FBCS5_CSMR = MCF_FBCS_CSMR_BAM_1G;
        //| MCF_FBCS_CSMR_V;
-#endif /* MACHINE_M5484LITE */
+#elif defined(MACHINE_M5484LITE)
+    /* disable other FBCS for now */
+    MCF_FBCS1_CSMR = 0;
+    MCF_FBCS2_CSMR = 0;
+    MCF_FBCS3_CSMR = 0;
+    MCF_FBCS4_CSMR = 0;
+
+    MCF_FBCS5_CSAR = MCF_FBCS_CSAR_BA(0x60000000);
+    MCF_FBCS5_CSCR = MCF_FBCS_CSCR_PS_16 |              /* CPLD access 16 bit wide */
+                     MCF_FBCS_CSCR_WS(32) |             /* 32 wait states */
+                     MCF_FBCS_CSCR_ASET(1) |            /* chip select on second rising clock edge */
+                     MCF_FBCS_CSCR_AA;                  /* auto acknowledge */
+    MCF_FBCS5_CSMR = MCF_FBCS_CSMR_BAM_256M |           /* maps 0x60000000 to 0x68000000 */
+                     MCF_FBCS_CSMR_V;
+#endif /* MACHINE_FIREBEE */

    xprintf("finished\r\n");
 }

-void wait_pll(void)
+#ifdef MACHINE_FIREBEE
+static void wait_pll(void)
 {
    int32_t trgt = MCF_SLT0_SCNT - 100000;
    do
@@ -483,12 +486,12 @@ void wait_pll(void)

 static volatile uint8_t *pll_base = (volatile uint8_t *) 0xf0000600;

-void init_pll(void)
+static void init_pll(void)
 {
    xprintf("FPGA PLL initialization: ");

    wait_pll();
-    * (volatile uint16_t *) (pll_base + 0x48) = 27; /* loopfilter  r */
+    * (volatile uint16_t *) (pll_base + 0x48) = 27;     /* loopfilter  r */

    wait_pll();
    * (volatile uint16_t *) (pll_base + 0x08) = 1;      /* charge pump 1 */
@@ -530,13 +533,10 @@ void init_pll(void)
    xprintf("finished\r\n");
 }

-
-
 /*
 * INIT VIDEO DDR RAM
 */
-
-void init_video_ddr(void) {
+static void init_video_ddr(void) {
    xprintf("init video RAM: ");

    * (volatile uint16_t *) 0xf0000400 = 0xb;   /* set cke = 1, cs=1, config = 1 */
@@ -564,11 +564,11 @@ void init_video_ddr(void) {
    _VRAM = 0000070022; /* load MR dll on */
    NOP();

-    * (uint32_t *) 0xf0000400 = 0x01070002; /* fifo on, refresh on, ddrcs und cke on, video dac on */
+    * (uint32_t *) 0xf0000400 = 0x01070082; /* fifo on, refresh on, ddrcs und cke on, video dac on, Falcon shift mode on */

    xprintf("finished\r\n");
 }
-
+#endif /* MACHINE_FIREBEE */

 /*
 * probe for NEC compatible USB host controller and install if found
@@ -586,49 +586,46 @@ void init_usb(void)

    do
    {
-        handle = pci_find_device(0x0000, 0xffff, index++);
+        handle = pci_find_classcode(PCI_CLASS_SERIAL_USB | PCI_FIND_BASE_CLASS | PCI_FIND_SUB_CLASS, index++);
        if (handle > 0)
        {
-            uint32_t id = 0;
-            uint32_t class = 0;
+            long id;
+            long pci_class;

+            xprintf("serial USB found at bus=0x%x, dev=0x%x, fnc=0x%x (0x%x)\r\n",
+                    PCI_BUS_FROM_HANDLE(handle),
+                    PCI_DEVICE_FROM_HANDLE(handle),
+                    PCI_FUNCTION_FROM_HANDLE(handle),
+                    handle);
            id = pci_read_config_longword(handle, PCIIDR);
-            class = pci_read_config_longword(handle, PCIREV);
+            pci_class = pci_read_config_longword(handle, PCIREV);

-            if (PCI_CLASS_CODE(class) == PCI_CLASS_SERIAL_USB)
+            if (PCI_SUBCLASS(pci_class) == PCI_CLASS_SERIAL_USB_EHCI)
            {
-                xprintf("serial USB found at bus=0x%x, dev=0x%x, fnc=0x%x (0x%x)\r\n",
-                        PCI_BUS_FROM_HANDLE(handle),
-                        PCI_DEVICE_FROM_HANDLE(handle),
-                        PCI_FUNCTION_FROM_HANDLE(handle),
-                        handle);
-                if (PCI_SUBCLASS(class) == PCI_CLASS_SERIAL_USB_EHCI)
+                board = ehci_usb_pci_table;
+                while (board->vendor)
                {
-                    board = ehci_usb_pci_table;
-                    while (board->vendor)
+                    if ((board->vendor == PCI_VENDOR_ID(id)) && board->device == PCI_DEVICE_ID(id))
                    {
-                        if ((board->vendor == PCI_VENDOR_ID(id)) && board->device == PCI_DEVICE_ID(id))
+                        if (usb_init(handle, board) >= 0)
                        {
-                            if (usb_init(handle, board) >= 0)
-                            {
-                                usb_found++;
-                            }
+                            usb_found++;
                        }
-                        board++;
                    }
+                    board++;
                }
-                if (PCI_SUBCLASS(class) == PCI_CLASS_SERIAL_USB_OHCI)
+            }
+            if (PCI_SUBCLASS(pci_class) == PCI_CLASS_SERIAL_USB_OHCI)
+            {
+                board = ohci_usb_pci_table;
+                while (board->vendor)
                {
-                    board = ohci_usb_pci_table;
-                    while (board->vendor)
+                    if ((board->vendor == PCI_VENDOR_ID(id)) && board->device == PCI_DEVICE_ID(id))
                    {
-                        if ((board->vendor == PCI_VENDOR_ID(id)) && board->device == PCI_DEVICE_ID(id))
-                        {
-                            if (usb_init(handle, board) >= 0)
-                                usb_found++;
-                        }
-                        board++;
+                        if (usb_init(handle, board) >= 0)
+                            usb_found++;
                    }
+                    board++;
                }
            }
        }
@@ -637,6 +634,8 @@ void init_usb(void)
    xprintf("finished (found %d USB controller(s))\r\n", usb_found);
 }

+#if defined(MACHINE_FIREBEE)
+
 static bool i2c_transfer_finished(void)
 {
    if (MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)
@@ -659,7 +658,7 @@ static bool i2c_bus_free(void)
 /*
 * TFP410 (DVI) on
 */
-void dvi_on(void)
+static void dvi_on(void)
 {
    uint8_t receivedByte;
    uint8_t dummyByte;          /* only used for a dummy read */
@@ -808,7 +807,7 @@ try_again:
 /*
 * AC97
 */
-void init_ac97(void)
+static void init_ac97(void)
 {
    // PSC2: AC97 ----------
    int i;
@@ -902,6 +901,7 @@ livo:
    MCF_PSC2_PSCTB_AC97 = 0x00000000;   //last data
    xprintf(" finished\r\n");
 }
+#endif /* MACHINE_FIREBEE */

 /* Symbols from the linker script */

@@ -929,22 +929,20 @@ extern uint8_t _BAS_RESIDENT_TEXT[];
 extern uint8_t _BAS_RESIDENT_TEXT_SIZE[];
 #define BAS_RESIDENT_TEXT_SIZE ((uint32_t) _BAS_RESIDENT_TEXT_SIZE)

-void clear_bss_segment(void)
+static void clear_bss_segment(void)
 {
    extern uint8_t _BAS_BSS_START[];
    uint8_t * BAS_BSS_START = &_BAS_BSS_START[0];
    extern uint8_t _BAS_BSS_END[];
    uint8_t *BAS_BSS_END = &_BAS_BSS_END[0];

-    bzero(BAS_BSS_START, BAS_BSS_END - BAS_BSS_START - 1);
+    bzero(BAS_BSS_START, BAS_BSS_END - BAS_BSS_START + 1);
 }

 void initialize_hardware(void)
 {
-    bool coldboot = true;
-
    /* Test for FireTOS switch: DIP switch #5 up */
-#ifdef MACHINE_FIREBEE
+#ifdef _NOT_USED_ // #if defined(MACHINE_FIREBEE)
    if (!(DIP_SWITCH & (1 << 6))) {
        /* Minimal hardware initialization */
        init_gpio();
@@ -962,6 +960,7 @@ void initialize_hardware(void)

        /* TT-RAM */

+        xprintf("FASTRAM_END = %p\r\n", FASTRAM_END);
        * (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */
        * (uint32_t *) 0x5a8 = 0x1357bd13;  /* ramvalid TOS system variable */

@@ -977,7 +976,7 @@ void initialize_hardware(void)

    xprintf("\n\n");
    xprintf("%s BASIS system (BaS) v %d.%d (%s, %s)\r\n\r\n",
-#if MACHINE_FIREBEE
+#if defined(MACHINE_FIREBEE)
    "Firebee"
 #elif MACHINE_M5484LITE
    "m5484 LITEKIT"
@@ -1047,18 +1046,33 @@ void initialize_hardware(void)
            break;
    }

-    /* make sure MMU is disabled */
-    MCF_MMU_MMUCR = 0;  /* MMU off */
-    NOP();              /* force pipeline sync */
-
    /*
     * Determine the processor revision
     */
    xprintf(" (revision %d)\r\n", ((MCF_SIU_JTAGID & MCF_SIU_JTAGID_REV) >> 28));

+    /* make sure MMU is disabled */
+    MCF_MMU_MMUCR = 0;  /* MMU off */
+    NOP();              /* force pipeline sync */
+
    init_slt();
    init_fbcs();
-    coldboot = init_ddram();
+    init_ddram();
+
+#if defined(MACHINE_M5484LITE)
+    xprintf("Fire Engine Control register:          %02x\r\n", * (uint8_t *) 0x61000000);
+    xprintf("Fire Engine interrupt register:        %02x\r\n", * (uint8_t *) 0x62000000);
+    xprintf("Fire Engine interrupt mask register:   %02x\r\n", * (uint8_t *) 0x63000000);
+    xprintf("Fire Engine power management register: %02x\r\n", * (uint8_t *) 0x64000000);
+    xprintf("Fire Engine EEPROM SPI register:       %02x\r\n", * (uint8_t *) 0x65000000);
+    xprintf("Fire Engine Flash register:            %02x\r\n", * (uint8_t *) 0x66000000);
+    xprintf("Fire Engine CPLD revision register:    %02x\r\n", * (uint8_t *) 0x67000000);
+    xprintf("Fire Engine Hardware revision register:%02x\r\n", * (uint8_t *) 0x68000000);
+
+    xprintf("write control register 0x%02x\r\n", 1 << 7);
+    * (uint8_t *) 0x61000000 = 1 << 7;
+    xprintf("Fire Engine Control register:          %02x\r\n", * (uint8_t *) 0x61000000);
+#endif /* MACHINE_M5484LITE */

    /*
     * install (preliminary) exception vectors
@@ -1103,21 +1117,15 @@ void initialize_hardware(void)

    }

-#if MACHINE_FIREBEE
-    if (coldboot) /* does not work with BDM */
-        ;
+#if defined(MACHINE_FIREBEE)
    fpga_configured = init_fpga();

    init_pll();
    init_video_ddr();
    dvi_on();
-
-#endif /* MACHINE_FIREBEE */
-    driver_mem_init();
-
-#if MACHINE_FIREBEE
    init_ac97();
 #endif /* MACHINE_FIREBEE */
+    driver_mem_init();

    /* jump into the BaS */
    extern void BaS(void);
--- a/tos/Makefile
+++ b/tos/Makefile
@@ -2,14 +2,31 @@
 .PHONY: jtagwait
 .PHONY: bascook
 .PHONY: vmem_test
-tos: jtagwait bascook vmem_test
+.PHONY: pci_test
+.PHONY: fpga_test
+tos: jtagwait bascook vmem_test pci_test fpga_test

 jtagwait:
-	(cd $@; make)
+	$(MAKE) -C $@

 bascook:
-	(cd $@; make)
+	$(MAKE) -C $@

 vmem_test:
-	(cd $@; make)
+	$(MAKE) -C $@
+
+pci_test:
+	$(MAKE) -C $@
+
+fpga_test:
+	$(MAKE) -C $@
+
+.PHONY: clean
+clean:
+	(cd jtagwait; make clean)
+	(cd bascook; make clean)
+	(cd vmem_test; make clean)
+	(cd pci_test; make clean)
+	(cd fpga_test; make clean)
+

--- a/tos/bascook/Makefile
+++ b/tos/bascook/Makefile
@@ -23,7 +23,9 @@ TOPDIR= ../..

 BAS_INCLUDE=-I$(TOPDIR)/../BaS_gcc/include

-INCLUDE=-I$(TOPDIR)/../libcmini/include $(BAS_INCLUDE) -nostdlib
+LIBCMINI=$(TOPDIR)/../libcmini/libcmini
+
+INCLUDE=-I$(LIBCMINI)/include $(BAS_INCLUDE) -nostdlib
 LIBS=-lcmini -nostdlib -lgcc
 CC=$(PREFIX)/bin/gcc

@@ -72,7 +74,7 @@ $(1)/objs/%.o:$(SRCDIR)/%.S

 $(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
 $(1)/$(APP): $$($(1)_OBJS)
-	$(CC) $$(CFLAGS) -o $$@ $(TOPDIR)/../libcmini/m5475/startup.o $$($(1)_OBJS) -L$(TOPDIR)/../libcmini/m5475 $(LIBS)
+	$(CC) $$(CFLAGS) -o $$@ $(LIBCMINI)/m5475/startup.o $$($(1)_OBJS) -L$(LIBCMINI)/m5475 $(LIBS)
 	$(STRIP) $$@
 endef
 $(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
@@ -90,8 +92,7 @@ clean:

 .PHONY: printvars
 printvars:
-	@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
-
+	@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V)))) 
 ifneq (clean,$(MAKECMDGOALS))
 -include $(DEPEND)
 endif
--- a/tos/bascook/sources/bascook.c
+++ b/tos/bascook/sources/bascook.c
@@ -10,13 +10,13 @@ struct driver_table *get_bas_drivers(void)
    struct driver_table *ret = NULL;

    __asm__ __volatile__(
-        "			bra.s	 do_trap			\n\t"
-        "			.dc.l	0x5f424153			\n\t"	// '_BAS'
-        "do_trap:	trap	#0					\n\t"
-        "			move.l	d0,%[ret]			\n\t"
-        :	[ret] "=m" (ret)	/* output */
-        :						/* no inputs */
-        :						/* clobbered */
+        "           bra.s   do_trap             \n\t"
+        "           .dc.l   0x5f424153          \n\t"   // '_BAS'
+        "do_trap:   trap    #0                  \n\t"
+        "           move.l  d0,%[ret]           \n\t"
+        :   [ret] "=m" (ret)    /* output */
+        :                       /* no inputs */
+        :                       /* clobbered */
    );

    return ret;
@@ -28,10 +28,10 @@ struct driver_table *get_bas_drivers(void)
 * exposure call.
 * If we get here, we have a BaS version that doesn't support the trap 0 interface
 */
-static void __attribute__((interrupt)) my_own_trap0_handler(void)
+static void __attribute__((interrupt)) trap0_catcher(void)
 {
    __asm__ __volatile__(
-        "		clr.l		d0				\n\t"		// return 0 to indicate not supported
+        "       clr.l       d0              \n\t"       // return 0 to indicate not supported
        :
        :
        :
@@ -85,43 +85,42 @@ void setcookie(uint32_t cookie, uint32_t value)
        printf("cannot set cookie, cookie jar is full!\r\n");
 }

-#define COOKIE_DMAC	0x444d4143L /* FireTOS DMA API */
+#define COOKIE_DMAC 0x444d4143L /* FireTOS DMA API cookie ("DMAC") */
+#define COOKIE_BAS_ 0x4241535fL /* BAS_ cookie (points to driver table struct */

 static char *dt_to_str(enum driver_type dt)
 {
    switch (dt)
    {
-        case BLOCKDEV_DRIVER: return "generic block device driver";
-        case CHARDEV_DRIVER:  return "generic character device driver";
-        case VIDEO_DRIVER:    return "video/framebuffer driver";
-        case XHDI_DRIVER:     return "XHDI compatible hard disk driver";
-        case MCD_DRIVER:	  return "multichannel DMA driver";
-        case PCI_DRIVER:	  return "PCI interface driver";
-        case MMU_DRIVER:	  return "MMU lock/unlock pages driver";
-        default:              return "unknown driver type";
+        case BLOCKDEV_DRIVER:   return "generic block device driver";
+        case CHARDEV_DRIVER:    return "generic character device driver";
+        case VIDEO_DRIVER:      return "video/framebuffer driver";
+        case XHDI_DRIVER:       return "XHDI compatible hard disk driver";
+        case MCD_DRIVER:        return "multichannel DMA driver";
+        case PCI_DRIVER:        return "PCI interface driver";
+        case MMU_DRIVER:        return "MMU lock/unlock pages driver";
+        case PCI_NATIVE_DRIVER: return "PCI interface native driver";
+        default:                return "unknown driver type";
    }
 }

-int main(int argc, char *argv[])
+static void set_driver_cookies(void)
 {
    struct driver_table *dt;
-    void *ssp;
    void *old_vector;
    char **sysbase = (char **) 0x4f2;
    uint32_t sig;

-    (void) Cconws("retrieve BaS driver interface\r\n");
-
-    ssp = (void *) Super(0L);								/* go to supervisor mode, we are doing dirty tricks */
    sig = * (long *)((*sysbase) + 0x2c);
+
    /*
     * first check if we are on EmuTOS, FireTOS want's to do everything itself
     */
    if (sig == 0x45544f53)
    {
-        old_vector = Setexc(0x20, my_own_trap0_handler);		/* set our own temporarily */
-        dt = get_bas_drivers();									/* trap #0 */
-        (void) Setexc(0x20, old_vector);						/* restore original vector */
+        old_vector = Setexc(0x20, trap0_catcher);               /* set our own temporarily */
+        dt = get_bas_drivers();                                 /* trap #0 */
+        (void) Setexc(0x20, old_vector);                        /* restore original vector */

        if (dt)
        {
@@ -144,6 +143,12 @@ int main(int argc, char *argv[])
                }
                ifc++;
            }
+
+            /*
+             * set cookie to be able to find the driver table later on
+             */
+            setcookie(COOKIE_BAS_, (uint32_t) dt);
+            printf("BAS_ cookie set to %p\r\n", dt);
        }
        else
        {
@@ -155,9 +160,15 @@ int main(int argc, char *argv[])
        printf("not running on EmuTOS,\r\n(signature 0x%04x instead of 0x%04x\r\n",
               (uint32_t) sig, 0x45544f53);
    }
-    Super(ssp);
+}

-    while (Cconis()) Cconin();	/* eat keys */
+int main(int argc, char *argv[])
+{
+    (void) Cconws("retrieve BaS driver interface\r\n");
+
+    Supexec(set_driver_cookies);
+
+    while (Cconis()) Cconin();  /* eat keys */

    return 0;
 }
--- a/tos/fpga_test/Makefile
+++ b/tos/fpga_test/Makefile
@@ -0,0 +1,106 @@
+CROSS=Y
+
+CROSSBINDIR_IS_Y=m68k-atari-mint-
+CROSSBINDIR_IS_N=
+
+CROSSBINDIR=$(CROSSBINDIR_IS_$(CROSS))
+
+UNAME := $(shell uname)
+ifeq ($(CROSS), Y)
+ifeq ($(UNAME),Linux)
+PREFIX=m68k-atari-mint
+HATARI=hatari
+else
+PREFIX=m68k-atari-mint
+HATARI=/usr/local/bin/hatari
+endif
+else
+PREFIX=/usr
+endif
+
+DEPEND=depend
+TOPDIR = ../..
+
+LIBCMINI=$(TOPDIR)/../libcmini/libcmini
+
+INCLUDE=-I$(LIBCMINI)/include -nostdlib
+LIBS=-lcmini -nostdlib -lgcc
+CC=$(PREFIX)/bin/gcc
+
+CC=$(CROSSBINDIR)gcc
+STRIP=$(CROSSBINDIR)strip
+STACK=$(CROSSBINDIR)stack
+
+APP=fpga_test.prg
+TEST_APP=$(APP)
+
+CFLAGS=\
+	-O0\
+	-g\
+	-Wl,-Map,mapfile\
+	-Wl,--defsym -Wl,__MBAR=0xff000000\
+	-Wl,--defsym -Wl,__MMUBAR=0xff040000\
+	-Wl,--defsym -Wl,__FPGA_JTAG_LOADED=0xff101000\
+	-Wl,--defsym -Wl,__FPGA_JTAG_VALID=0xff101004\
+	-Wl,--defsym -Wl,__VRAM=0x60000000\
+	-Wall
+
+SRCDIR=sources
+INCDIR=include
+INCLUDE+=-I$(INCDIR)
+
+CSRCS=\
+	$(SRCDIR)/fpga_test.c \
+	$(SRCDIR)/bas_printf.c
+
+ASRCS=$(SRCDIR)/printf_helper.S
+
+COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS)))
+AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS)))
+OBJS=$(COBJS) $(AOBJS)
+
+TRGTDIRS=./m5475 ./m5475/mshort
+OBJDIRS=$(patsubst %,%/objs,$(TRGTDIRS))
+
+#
+# multilib flags. These must match m68k-atari-mint-gcc -print-multi-lib output
+#
+m5475/$(APP):CFLAGS += -mcpu=5475
+m5475/mshort/$(APP): CFLAGS += -mcpu=5475 -mshort
+
+all:$(patsubst %,%/$(APP),$(TRGTDIRS))
+#
+# generate pattern rules for multilib object files.
+#
+define CC_TEMPLATE
+$(1)/objs/%.o:$(SRCDIR)/%.c
+	$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
+
+$(1)/objs/%.o:$(SRCDIR)/%.S
+	$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
+
+$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
+$(1)/$(APP): $$($(1)_OBJS)
+	$(CC) $$(CFLAGS) -o $$@ $(LIBCMINI)/$(1)/startup.o $$($(1)_OBJS) -L$(LIBCMINI)/$(1) $(LIBS)
+	#$(STRIP) $$@
+endef
+$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
+
+$(DEPEND): $(ASRCS) $(CSRCS)
+	-rm -f $(DEPEND)
+	for d in $(TRGTDIRS);\
+		do $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e "s#^\(.*\).o:#$$d/objs/\1.o:#" >> $(DEPEND); \
+    done
+
+
+clean:
+	@rm -f $(patsubst %,%/objs/*.o,$(TRGTDIRS)) $(patsubst %,%/$(APP),$(TRGTDIRS))
+	@rm -f $(DEPEND) mapfile
+
+.PHONY: printvars
+printvars:
+	@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
+
+ifneq (clean,$(MAKECMDGOALS))
+-include $(DEPEND)
+endif
--- a/tos/fpga_test/include/MCF5475.h
+++ b/tos/fpga_test/include/MCF5475.h
@@ -0,0 +1,67 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_H__
+#define __MCF5475_H__
+
+#include <stdint.h>
+/***
+ * MCF5475 Derivative Memory map definitions from linker command files:
+ * __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
+ * linker symbols must be defined in the linker command file.
+ */
+
+typedef uint32_t __attribute__((__may_alias__)) uint32_t_a;	/* a type to avoid gcc's complaints about pointer aliasing */
+
+extern uint8_t _MBAR[];
+extern uint8_t _MMUBAR[];
+extern uint8_t _RAMBAR0[];
+extern uint8_t _RAMBAR0_SIZE[];
+extern uint8_t _RAMBAR1[];
+extern uint8_t _RAMBAR1_SIZE[];
+
+#define MBAR_ADDRESS    (uint32_t)_MBAR
+#define MMUBAR_ADDRESS  (uint32_t)_MMUBAR
+#define RAMBAR0_ADDRESS (uint32_t)_RAMBAR0
+#define RAMBAR0_SIZE    (uint32_t)_RAMBAR0_SIZE
+#define RAMBAR1_ADDRESS (uint32_t)_RAMBAR1
+#define RAMBAR1_SIZE    (uint32_t)_RAMBAR1_SIZE
+
+
+#include "MCF5475_SIU.h"
+#include "MCF5475_MMU.h"
+#include "MCF5475_SDRAMC.h"
+#include "MCF5475_XLB.h"
+#include "MCF5475_CLOCK.h"
+#include "MCF5475_FBCS.h"
+#include "MCF5475_INTC.h"
+#include "MCF5475_GPT.h"
+#include "MCF5475_SLT.h"
+#include "MCF5475_GPIO.h"
+#include "MCF5475_PAD.h"
+#include "MCF5475_PCI.h"
+#include "MCF5475_PCIARB.h"
+#include "MCF5475_EPORT.h"
+#include "MCF5475_CTM.h"
+#include "MCF5475_DMA.h"
+#include "MCF5475_PSC.h"
+#include "MCF5475_DSPI.h"
+#include "MCF5475_I2C.h"
+#include "MCF5475_FEC.h"
+#include "MCF5475_USB.h"
+#include "MCF5475_SRAM.h"
+#include "MCF5475_SEC.h"
+
+#endif /* __MCF5475_H__ */
--- a/tos/fpga_test/include/MCF5475_CLOCK.h
+++ b/tos/fpga_test/include/MCF5475_CLOCK.h
@@ -0,0 +1,47 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_CLOCK_H__
+#define __MCF5475_CLOCK_H__
+
+
+/*********************************************************************
+*
+* Clock Module (CLOCK)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CLOCK_SPCR                       (*(volatile uint32_t*)(&_MBAR[0x300]))
+
+
+/* Bit definitions and macros for MCF_CLOCK_SPCR */
+#define MCF_CLOCK_SPCR_MEMEN                 (0x1)
+#define MCF_CLOCK_SPCR_PCIEN                 (0x2)
+#define MCF_CLOCK_SPCR_FBEN                  (0x4)
+#define MCF_CLOCK_SPCR_CAN0EN                (0x8)
+#define MCF_CLOCK_SPCR_DMAEN                 (0x10)
+#define MCF_CLOCK_SPCR_FEC0EN                (0x20)
+#define MCF_CLOCK_SPCR_FEC1EN                (0x40)
+#define MCF_CLOCK_SPCR_USBEN                 (0x80)
+#define MCF_CLOCK_SPCR_PSCEN                 (0x200)
+#define MCF_CLOCK_SPCR_CAN1EN                (0x800)
+#define MCF_CLOCK_SPCR_CRYENA                (0x1000)
+#define MCF_CLOCK_SPCR_CRYENB                (0x2000)
+#define MCF_CLOCK_SPCR_COREN                 (0x4000)
+#define MCF_CLOCK_SPCR_PLLK                  (0x80000000)
+
+
+#endif /* __MCF5475_CLOCK_H__ */
--- a/tos/fpga_test/include/MCF5475_CTM.h
+++ b/tos/fpga_test/include/MCF5475_CTM.h
@@ -0,0 +1,76 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_CTM_H__
+#define __MCF5475_CTM_H__
+
+
+/*********************************************************************
+*
+* Comm Timer Module (CTM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CTM_CTCR0                        (*(volatile uint32_t*)(&_MBAR[0x7F00]))
+#define MCF_CTM_CTCR1                        (*(volatile uint32_t*)(&_MBAR[0x7F04]))
+#define MCF_CTM_CTCR2                        (*(volatile uint32_t*)(&_MBAR[0x7F08]))
+#define MCF_CTM_CTCR3                        (*(volatile uint32_t*)(&_MBAR[0x7F0C]))
+#define MCF_CTM_CTCR4                        (*(volatile uint32_t*)(&_MBAR[0x7F10]))
+#define MCF_CTM_CTCR5                        (*(volatile uint32_t*)(&_MBAR[0x7F14]))
+#define MCF_CTM_CTCR6                        (*(volatile uint32_t*)(&_MBAR[0x7F18]))
+#define MCF_CTM_CTCR7                        (*(volatile uint32_t*)(&_MBAR[0x7F1C]))
+#define MCF_CTM_CTCRF(x)                     (*(volatile uint32_t*)(&_MBAR[0x7F00 + ((x)*0x4)]))
+#define MCF_CTM_CTCRV(x)                     (*(volatile uint32_t*)(&_MBAR[0x7F10 + ((x-4)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_CTM_CTCRF */
+#define MCF_CTM_CTCRF_CRV(x)                 (((x)&0xFFFF)<<0)
+#define MCF_CTM_CTCRF_S(x)                   (((x)&0xF)<<0x10)
+#define MCF_CTM_CTCRF_S_CLK_1                (0)
+#define MCF_CTM_CTCRF_S_CLK_2                (0x10000)
+#define MCF_CTM_CTCRF_S_CLK_4                (0x20000)
+#define MCF_CTM_CTCRF_S_CLK_8                (0x30000)
+#define MCF_CTM_CTCRF_S_CLK_16               (0x40000)
+#define MCF_CTM_CTCRF_S_CLK_32               (0x50000)
+#define MCF_CTM_CTCRF_S_CLK_64               (0x60000)
+#define MCF_CTM_CTCRF_S_CLK_128              (0x70000)
+#define MCF_CTM_CTCRF_S_CLK_256              (0x80000)
+#define MCF_CTM_CTCRF_S_CLK_EXT              (0x90000)
+#define MCF_CTM_CTCRF_PCT(x)                 (((x)&0x7)<<0x14)
+#define MCF_CTM_CTCRF_PCT_100                (0)
+#define MCF_CTM_CTCRF_PCT_50                 (0x100000)
+#define MCF_CTM_CTCRF_PCT_25                 (0x200000)
+#define MCF_CTM_CTCRF_PCT_12p5               (0x300000)
+#define MCF_CTM_CTCRF_PCT_6p25               (0x400000)
+#define MCF_CTM_CTCRF_PCT_OFF                (0x500000)
+#define MCF_CTM_CTCRF_M                      (0x800000)
+#define MCF_CTM_CTCRF_IM                     (0x1000000)
+#define MCF_CTM_CTCRF_I                      (0x80000000)
+
+/* Bit definitions and macros for MCF_CTM_CTCRV */
+#define MCF_CTM_CTCRV_CRV(x)                 (((x)&0xFFFFFF)<<0)
+#define MCF_CTM_CTCRV_PCT(x)                 (((x)&0x7)<<0x18)
+#define MCF_CTM_CTCRV_PCT_100                (0)
+#define MCF_CTM_CTCRV_PCT_50                 (0x1000000)
+#define MCF_CTM_CTCRV_PCT_25                 (0x2000000)
+#define MCF_CTM_CTCRV_PCT_12p5               (0x3000000)
+#define MCF_CTM_CTCRV_PCT_6p25               (0x4000000)
+#define MCF_CTM_CTCRV_PCT_OFF                (0x5000000)
+#define MCF_CTM_CTCRV_M                      (0x8000000)
+#define MCF_CTM_CTCRV_S                      (0x10000000)
+
+
+#endif /* __MCF5475_CTM_H__ */
--- a/tos/fpga_test/include/MCF5475_DMA.h
+++ b/tos/fpga_test/include/MCF5475_DMA.h
@@ -0,0 +1,234 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_DMA_H__
+#define __MCF5475_DMA_H__
+
+
+/*********************************************************************
+*
+* Multichannel DMA (DMA)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_DMA_TASKBAR                      (*(volatile uint32_t*)(&_MBAR[0x8000]))
+#define MCF_DMA_CP                           (*(volatile uint32_t*)(&_MBAR[0x8004]))
+#define MCF_DMA_EP                           (*(volatile uint32_t*)(&_MBAR[0x8008]))
+#define MCF_DMA_VP                           (*(volatile uint32_t*)(&_MBAR[0x800C]))
+#define MCF_DMA_PTD                          (*(volatile uint32_t*)(&_MBAR[0x8010]))
+#define MCF_DMA_DIPR                         (*(volatile uint32_t*)(&_MBAR[0x8014]))
+#define MCF_DMA_DIMR                         (*(volatile uint32_t*)(&_MBAR[0x8018]))
+#define MCF_DMA_TCR0                         (*(volatile uint16_t*)(&_MBAR[0x801C]))
+#define MCF_DMA_TCR1                         (*(volatile uint16_t*)(&_MBAR[0x801E]))
+#define MCF_DMA_TCR2                         (*(volatile uint16_t*)(&_MBAR[0x8020]))
+#define MCF_DMA_TCR3                         (*(volatile uint16_t*)(&_MBAR[0x8022]))
+#define MCF_DMA_TCR4                         (*(volatile uint16_t*)(&_MBAR[0x8024]))
+#define MCF_DMA_TCR5                         (*(volatile uint16_t*)(&_MBAR[0x8026]))
+#define MCF_DMA_TCR6                         (*(volatile uint16_t*)(&_MBAR[0x8028]))
+#define MCF_DMA_TCR7                         (*(volatile uint16_t*)(&_MBAR[0x802A]))
+#define MCF_DMA_TCR8                         (*(volatile uint16_t*)(&_MBAR[0x802C]))
+#define MCF_DMA_TCR9                         (*(volatile uint16_t*)(&_MBAR[0x802E]))
+#define MCF_DMA_TCR10                        (*(volatile uint16_t*)(&_MBAR[0x8030]))
+#define MCF_DMA_TCR11                        (*(volatile uint16_t*)(&_MBAR[0x8032]))
+#define MCF_DMA_TCR12                        (*(volatile uint16_t*)(&_MBAR[0x8034]))
+#define MCF_DMA_TCR13                        (*(volatile uint16_t*)(&_MBAR[0x8036]))
+#define MCF_DMA_TCR14                        (*(volatile uint16_t*)(&_MBAR[0x8038]))
+#define MCF_DMA_TCR15                        (*(volatile uint16_t*)(&_MBAR[0x803A]))
+#define MCF_DMA_PRIOR0                       (*(volatile uint8_t *)(&_MBAR[0x803C]))
+#define MCF_DMA_PRIOR1                       (*(volatile uint8_t *)(&_MBAR[0x803D]))
+#define MCF_DMA_PRIOR2                       (*(volatile uint8_t *)(&_MBAR[0x803E]))
+#define MCF_DMA_PRIOR3                       (*(volatile uint8_t *)(&_MBAR[0x803F]))
+#define MCF_DMA_PRIOR4                       (*(volatile uint8_t *)(&_MBAR[0x8040]))
+#define MCF_DMA_PRIOR5                       (*(volatile uint8_t *)(&_MBAR[0x8041]))
+#define MCF_DMA_PRIOR6                       (*(volatile uint8_t *)(&_MBAR[0x8042]))
+#define MCF_DMA_PRIOR7                       (*(volatile uint8_t *)(&_MBAR[0x8043]))
+#define MCF_DMA_PRIOR8                       (*(volatile uint8_t *)(&_MBAR[0x8044]))
+#define MCF_DMA_PRIOR9                       (*(volatile uint8_t *)(&_MBAR[0x8045]))
+#define MCF_DMA_PRIOR10                      (*(volatile uint8_t *)(&_MBAR[0x8046]))
+#define MCF_DMA_PRIOR11                      (*(volatile uint8_t *)(&_MBAR[0x8047]))
+#define MCF_DMA_PRIOR12                      (*(volatile uint8_t *)(&_MBAR[0x8048]))
+#define MCF_DMA_PRIOR13                      (*(volatile uint8_t *)(&_MBAR[0x8049]))
+#define MCF_DMA_PRIOR14                      (*(volatile uint8_t *)(&_MBAR[0x804A]))
+#define MCF_DMA_PRIOR15                      (*(volatile uint8_t *)(&_MBAR[0x804B]))
+#define MCF_DMA_PRIOR16                      (*(volatile uint8_t *)(&_MBAR[0x804C]))
+#define MCF_DMA_PRIOR17                      (*(volatile uint8_t *)(&_MBAR[0x804D]))
+#define MCF_DMA_PRIOR18                      (*(volatile uint8_t *)(&_MBAR[0x804E]))
+#define MCF_DMA_PRIOR19                      (*(volatile uint8_t *)(&_MBAR[0x804F]))
+#define MCF_DMA_PRIOR20                      (*(volatile uint8_t *)(&_MBAR[0x8050]))
+#define MCF_DMA_PRIOR21                      (*(volatile uint8_t *)(&_MBAR[0x8051]))
+#define MCF_DMA_PRIOR22                      (*(volatile uint8_t *)(&_MBAR[0x8052]))
+#define MCF_DMA_PRIOR23                      (*(volatile uint8_t *)(&_MBAR[0x8053]))
+#define MCF_DMA_PRIOR24                      (*(volatile uint8_t *)(&_MBAR[0x8054]))
+#define MCF_DMA_PRIOR25                      (*(volatile uint8_t *)(&_MBAR[0x8055]))
+#define MCF_DMA_PRIOR26                      (*(volatile uint8_t *)(&_MBAR[0x8056]))
+#define MCF_DMA_PRIOR27                      (*(volatile uint8_t *)(&_MBAR[0x8057]))
+#define MCF_DMA_PRIOR28                      (*(volatile uint8_t *)(&_MBAR[0x8058]))
+#define MCF_DMA_PRIOR29                      (*(volatile uint8_t *)(&_MBAR[0x8059]))
+#define MCF_DMA_PRIOR30                      (*(volatile uint8_t *)(&_MBAR[0x805A]))
+#define MCF_DMA_PRIOR31                      (*(volatile uint8_t *)(&_MBAR[0x805B]))
+#define MCF_DMA_IMCR                         (*(volatile uint32_t*)(&_MBAR[0x805C]))
+#define MCF_DMA_TSKSZ0                       (*(volatile uint32_t*)(&_MBAR[0x8060]))
+#define MCF_DMA_TSKSZ1                       (*(volatile uint32_t*)(&_MBAR[0x8064]))
+#define MCF_DMA_DBGCOMP0                     (*(volatile uint32_t*)(&_MBAR[0x8070]))
+#define MCF_DMA_DBGCOMP2                     (*(volatile uint32_t*)(&_MBAR[0x8074]))
+#define MCF_DMA_DBGCTL                       (*(volatile uint32_t*)(&_MBAR[0x8078]))
+#define MCF_DMA_TCR(x)                       (*(volatile uint16_t*)(&_MBAR[0x801C + ((x)*0x2)]))
+#define MCF_DMA_PRIOR(x)                     (*(volatile uint8_t *)(&_MBAR[0x803C + ((x)*0x1)]))
+
+
+/* Bit definitions and macros for MCF_DMA_TASKBAR */
+#define MCF_DMA_TASKBAR_TASK_BASE_ADDRESS(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_CP */
+#define MCF_DMA_CP_DESCRIPTOR_POINTER(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_EP */
+#define MCF_DMA_EP_DESCRIPTOR_POINTER(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_VP */
+#define MCF_DMA_VP_VARIABLE_POINTER(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_PTD */
+#define MCF_DMA_PTD_PCTL0                    (0x1)
+#define MCF_DMA_PTD_PCTL1                    (0x2)
+#define MCF_DMA_PTD_PCTL13                   (0x2000)
+#define MCF_DMA_PTD_PCTL14                   (0x4000)
+#define MCF_DMA_PTD_PCTL15                   (0x8000)
+
+/* Bit definitions and macros for MCF_DMA_DIPR */
+#define MCF_DMA_DIPR_TASK(x)                 (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DIMR */
+#define MCF_DMA_DIMR_TASK(x)                 (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_TCR */
+#define MCF_DMA_TCR_ASTSKNUM(x)              (((x)&0xF)<<0)
+#define MCF_DMA_TCR_HLDINITNUM               (0x20)
+#define MCF_DMA_TCR_HIPRITSKEN               (0x40)
+#define MCF_DMA_TCR_ASTRT                    (0x80)
+#define MCF_DMA_TCR_INITNUM(x)               (((x)&0x1F)<<0x8)
+#define MCF_DMA_TCR_ALWINIT                  (0x2000)
+#define MCF_DMA_TCR_V                        (0x4000)
+#define MCF_DMA_TCR_EN                       (0x8000)
+
+/* Bit definitions and macros for MCF_DMA_PRIOR */
+#define MCF_DMA_PRIOR_PRI(x)                 (((x)&0x7)<<0)
+#define MCF_DMA_PRIOR_HLD                    (0x80)
+
+/* Bit definitions and macros for MCF_DMA_IMCR */
+#define MCF_DMA_IMCR_IMC16(x)	(((x)&0x3)<<0)
+#define MCF_DMA_IMCR_IMC17(x)	(((x)&0x3)<<0x2)
+#define MCF_DMA_IMCR_IMC18(x)	(((x)&0x3)<<0x4)
+#define MCF_DMA_IMCR_IMC19(x)	(((x)&0x3)<<0x6)
+#define MCF_DMA_IMCR_IMC20(x)	(((x)&0x3)<<0x8)
+#define MCF_DMA_IMCR_IMC21(x)	(((x)&0x3)<<0xA)
+#define MCF_DMA_IMCR_IMC22(x)	(((x)&0x3)<<0xC)
+#define MCF_DMA_IMCR_IMC23(x)	(((x)&0x3)<<0xE)
+#define MCF_DMA_IMCR_IMC24(x)	(((x)&0x3)<<0x10)
+#define MCF_DMA_IMCR_IMC25(x)	(((x)&0x3)<<0x12)
+#define MCF_DMA_IMCR_IMC26(x)	(((x)&0x3)<<0x14)
+#define MCF_DMA_IMCR_IMC27(x)	(((x)&0x3)<<0x16)
+#define MCF_DMA_IMCR_IMC28(x)	(((x)&0x3)<<0x18)
+#define MCF_DMA_IMCR_IMC29(x)	(((x)&0x3)<<0x1A)
+#define MCF_DMA_IMCR_IMC30(x)	(((x)&0x3)<<0x1C)
+#define MCF_DMA_IMCR_IMC31(x)	(((x)&0x3)<<0x1E)
+
+
+#define MCF_DMA_IMCR_IMC16_FEC0RX    (0x00000000)
+#define MCF_DMA_IMCR_IMC17_FEC0TX    (0x00000000)
+#define MCF_DMA_IMCR_IMC18_FEC0RX    (0x00000020)
+#define MCF_DMA_IMCR_IMC19_FEC0TX    (0x00000080)
+#define MCF_DMA_IMCR_IMC20_FEC1RX    (0x00000100)
+#define MCF_DMA_IMCR_IMC21_DREQ1     (0x00000000)
+#define MCF_DMA_IMCR_IMC21_FEC1TX    (0x00000400)
+#define MCF_DMA_IMCR_IMC22_FEC0RX    (0x00001000)
+#define MCF_DMA_IMCR_IMC23_FEC0TX    (0x00004000)
+#define MCF_DMA_IMCR_IMC24_CTM0      (0x00010000)
+#define MCF_DMA_IMCR_IMC24_FEC1RX    (0x00020000)
+#define MCF_DMA_IMCR_IMC25_CTM1      (0x00040000)
+#define MCF_DMA_IMCR_IMC25_FEC1TX    (0x00080000)
+#define MCF_DMA_IMCR_IMC26_USBEP4    (0x00000000)
+#define MCF_DMA_IMCR_IMC26_CTM2      (0x00200000)
+#define MCF_DMA_IMCR_IMC27_USBEP5    (0x00000000)
+#define MCF_DMA_IMCR_IMC27_CTM3      (0x00800000)
+#define MCF_DMA_IMCR_IMC28_USBEP6    (0x00000000)
+#define MCF_DMA_IMCR_IMC28_CTM4      (0x01000000)
+#define MCF_DMA_IMCR_IMC28_DREQ1     (0x02000000)
+#define MCF_DMA_IMCR_IMC28_PSC2RX    (0x03000000)
+#define MCF_DMA_IMCR_IMC29_DREQ1     (0x04000000)
+#define MCF_DMA_IMCR_IMC29_CTM5      (0x08000000)
+#define MCF_DMA_IMCR_IMC29_PSC2TX    (0x0C000000)
+#define MCF_DMA_IMCR_IMC30_FEC1RX    (0x00000000)
+#define MCF_DMA_IMCR_IMC30_CTM6      (0x10000000)
+#define MCF_DMA_IMCR_IMC30_PSC3RX    (0x30000000)
+#define MCF_DMA_IMCR_IMC31_FEC1TX    (0x00000000)
+#define MCF_DMA_IMCR_IMC31_CTM7      (0x80000000)
+#define MCF_DMA_IMCR_IMC31_PSC3TX    (0xC0000000)
+
+/* Bit definitions and macros for MCF_DMA_TSKSZ0 */
+#define MCF_DMA_TSKSZ0_DSTSZ7(x)             (((x)&0x3)<<0)
+#define MCF_DMA_TSKSZ0_SRCSZ7(x)             (((x)&0x3)<<0x2)
+#define MCF_DMA_TSKSZ0_DSTSZ6(x)             (((x)&0x3)<<0x4)
+#define MCF_DMA_TSKSZ0_SRCSZ6(x)             (((x)&0x3)<<0x6)
+#define MCF_DMA_TSKSZ0_DSTSZ5(x)             (((x)&0x3)<<0x8)
+#define MCF_DMA_TSKSZ0_SRCSZ5(x)             (((x)&0x3)<<0xA)
+#define MCF_DMA_TSKSZ0_DSTSZ4(x)             (((x)&0x3)<<0xC)
+#define MCF_DMA_TSKSZ0_SRCSZ4(x)             (((x)&0x3)<<0xE)
+#define MCF_DMA_TSKSZ0_DSTSZ3(x)             (((x)&0x3)<<0x10)
+#define MCF_DMA_TSKSZ0_SRCSZ3(x)             (((x)&0x3)<<0x12)
+#define MCF_DMA_TSKSZ0_DSTSZ2(x)             (((x)&0x3)<<0x14)
+#define MCF_DMA_TSKSZ0_SRCSZ2(x)             (((x)&0x3)<<0x16)
+#define MCF_DMA_TSKSZ0_DSTSZ1(x)             (((x)&0x3)<<0x18)
+#define MCF_DMA_TSKSZ0_SRCSZ1(x)             (((x)&0x3)<<0x1A)
+#define MCF_DMA_TSKSZ0_DSTSZ0(x)             (((x)&0x3)<<0x1C)
+#define MCF_DMA_TSKSZ0_SRCSZ0(x)             (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_DMA_TSKSZ1 */
+#define MCF_DMA_TSKSZ1_DSTSZ15(x)            (((x)&0x3)<<0)
+#define MCF_DMA_TSKSZ1_SRCSZ15(x)            (((x)&0x3)<<0x2)
+#define MCF_DMA_TSKSZ1_DSTSZ14(x)            (((x)&0x3)<<0x4)
+#define MCF_DMA_TSKSZ1_SRCSZ14(x)            (((x)&0x3)<<0x6)
+#define MCF_DMA_TSKSZ1_DSTSZ13(x)            (((x)&0x3)<<0x8)
+#define MCF_DMA_TSKSZ1_SRCSZ13(x)            (((x)&0x3)<<0xA)
+#define MCF_DMA_TSKSZ1_DSTSZ12(x)            (((x)&0x3)<<0xC)
+#define MCF_DMA_TSKSZ1_SRCSZ12(x)            (((x)&0x3)<<0xE)
+#define MCF_DMA_TSKSZ1_DSTSZ11(x)            (((x)&0x3)<<0x10)
+#define MCF_DMA_TSKSZ1_SRCSZ11(x)            (((x)&0x3)<<0x12)
+#define MCF_DMA_TSKSZ1_DSTSZ10(x)            (((x)&0x3)<<0x14)
+#define MCF_DMA_TSKSZ1_SRCSZ10(x)            (((x)&0x3)<<0x16)
+#define MCF_DMA_TSKSZ1_DSTSZ9(x)             (((x)&0x3)<<0x18)
+#define MCF_DMA_TSKSZ1_SRCSZ9(x)             (((x)&0x3)<<0x1A)
+#define MCF_DMA_TSKSZ1_DSTSZ8(x)             (((x)&0x3)<<0x1C)
+#define MCF_DMA_TSKSZ1_SRCSZ8(x)             (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_DMA_DBGCOMP0 */
+#define MCF_DMA_DBGCOMP0_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DBGCOMP2 */
+#define MCF_DMA_DBGCOMP2_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DBGCTL */
+#define MCF_DMA_DBGCTL_I                     (0x2)
+#define MCF_DMA_DBGCTL_E                     (0x4)
+#define MCF_DMA_DBGCTL_AND_OR                (0x80)
+#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_2(x)  (((x)&0x7)<<0x8)
+#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_1(x)  (((x)&0x7)<<0xB)
+#define MCF_DMA_DBGCTL_B                     (0x4000)
+#define MCF_DMA_DBGCTL_AA                    (0x8000)
+#define MCF_DMA_DBGCTL_BLOCK_TASKS(x)        (((x)&0xFFFF)<<0x10)
+
+
+#endif /* __MCF5475_DMA_H__ */
--- a/tos/fpga_test/include/MCF5475_DSPI.h
+++ b/tos/fpga_test/include/MCF5475_DSPI.h
@@ -0,0 +1,150 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_DSPI_H__
+#define __MCF5475_DSPI_H__
+
+
+/*********************************************************************
+*
+* DMA Serial Peripheral Interface (DSPI)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_DSPI_DMCR                        (*(volatile uint32_t*)(&_MBAR[0x8A00]))
+#define MCF_DSPI_DTCR                        (*(volatile uint32_t*)(&_MBAR[0x8A08]))
+#define MCF_DSPI_DCTAR0                      (*(volatile uint32_t*)(&_MBAR[0x8A0C]))
+#define MCF_DSPI_DCTAR1                      (*(volatile uint32_t*)(&_MBAR[0x8A10]))
+#define MCF_DSPI_DCTAR2                      (*(volatile uint32_t*)(&_MBAR[0x8A14]))
+#define MCF_DSPI_DCTAR3                      (*(volatile uint32_t*)(&_MBAR[0x8A18]))
+#define MCF_DSPI_DCTAR4                      (*(volatile uint32_t*)(&_MBAR[0x8A1C]))
+#define MCF_DSPI_DCTAR5                      (*(volatile uint32_t*)(&_MBAR[0x8A20]))
+#define MCF_DSPI_DCTAR6                      (*(volatile uint32_t*)(&_MBAR[0x8A24]))
+#define MCF_DSPI_DCTAR7                      (*(volatile uint32_t*)(&_MBAR[0x8A28]))
+#define MCF_DSPI_DSR                         (*(volatile uint32_t*)(&_MBAR[0x8A2C]))
+#define MCF_DSPI_DIRSR                       (*(volatile uint32_t*)(&_MBAR[0x8A30]))
+#define MCF_DSPI_DTFR                        (*(volatile uint32_t*)(&_MBAR[0x8A34]))
+#define MCF_DSPI_DRFR                        (*(volatile uint32_t*)(&_MBAR[0x8A38]))
+#define MCF_DSPI_DTFDR0                      (*(volatile uint32_t*)(&_MBAR[0x8A3C]))
+#define MCF_DSPI_DTFDR1                      (*(volatile uint32_t*)(&_MBAR[0x8A40]))
+#define MCF_DSPI_DTFDR2                      (*(volatile uint32_t*)(&_MBAR[0x8A44]))
+#define MCF_DSPI_DTFDR3                      (*(volatile uint32_t*)(&_MBAR[0x8A48]))
+#define MCF_DSPI_DRFDR0                      (*(volatile uint32_t*)(&_MBAR[0x8A7C]))
+#define MCF_DSPI_DRFDR1                      (*(volatile uint32_t*)(&_MBAR[0x8A80]))
+#define MCF_DSPI_DRFDR2                      (*(volatile uint32_t*)(&_MBAR[0x8A84]))
+#define MCF_DSPI_DRFDR3                      (*(volatile uint32_t*)(&_MBAR[0x8A88]))
+#define MCF_DSPI_DCTAR(x)                    (*(volatile uint32_t*)(&_MBAR[0x8A0C + ((x)*0x4)]))
+#define MCF_DSPI_DTFDR(x)                    (*(volatile uint32_t*)(&_MBAR[0x8A3C + ((x)*0x4)]))
+#define MCF_DSPI_DRFDR(x)                    (*(volatile uint32_t*)(&_MBAR[0x8A7C + ((x)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_DSPI_DMCR */
+#define MCF_DSPI_DMCR_HALT                   (0x1)
+#define MCF_DSPI_DMCR_SMPL_PT(x)             (((x)&0x3)<<0x8)
+#define MCF_DSPI_DMCR_SMPL_PT_0CLK           (0)
+#define MCF_DSPI_DMCR_SMPL_PT_1CLK           (0x100)
+#define MCF_DSPI_DMCR_SMPL_PT_2CLK           (0x200)
+#define MCF_DSPI_DMCR_CRXF                   (0x400)
+#define MCF_DSPI_DMCR_CTXF                   (0x800)
+#define MCF_DSPI_DMCR_DRXF                   (0x1000)
+#define MCF_DSPI_DMCR_DTXF                   (0x2000)
+#define MCF_DSPI_DMCR_CSIS0                  (0x10000)
+#define MCF_DSPI_DMCR_CSIS2                  (0x40000)
+#define MCF_DSPI_DMCR_CSIS3                  (0x80000)
+#define MCF_DSPI_DMCR_CSIS5                  (0x200000)
+#define MCF_DSPI_DMCR_ROOE                   (0x1000000)
+#define MCF_DSPI_DMCR_PCSSE                  (0x2000000)
+#define MCF_DSPI_DMCR_MTFE                   (0x4000000)
+#define MCF_DSPI_DMCR_FRZ                    (0x8000000)
+#define MCF_DSPI_DMCR_DCONF(x)               (((x)&0x3)<<0x1C)
+#define MCF_DSPI_DMCR_CSCK                   (0x40000000)
+#define MCF_DSPI_DMCR_MSTR                   (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DTCR */
+#define MCF_DSPI_DTCR_SPI_TCNT(x)            (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_DSPI_DCTAR */
+#define MCF_DSPI_DCTAR_BR(x)                 (((x)&0xF)<<0)
+#define MCF_DSPI_DCTAR_DT(x)                 (((x)&0xF)<<0x4)
+#define MCF_DSPI_DCTAR_ASC(x)                (((x)&0xF)<<0x8)
+#define MCF_DSPI_DCTAR_CSSCK(x)              (((x)&0xF)<<0xC)
+#define MCF_DSPI_DCTAR_PBR(x)                (((x)&0x3)<<0x10)
+#define MCF_DSPI_DCTAR_PBR_1CLK              (0)
+#define MCF_DSPI_DCTAR_PBR_3CLK              (0x10000)
+#define MCF_DSPI_DCTAR_PBR_5CLK              (0x20000)
+#define MCF_DSPI_DCTAR_PBR_7CLK              (0x30000)
+#define MCF_DSPI_DCTAR_PDT(x)                (((x)&0x3)<<0x12)
+#define MCF_DSPI_DCTAR_PDT_1CLK              (0)
+#define MCF_DSPI_DCTAR_PDT_3CLK              (0x40000)
+#define MCF_DSPI_DCTAR_PDT_5CLK              (0x80000)
+#define MCF_DSPI_DCTAR_PDT_7CLK              (0xC0000)
+#define MCF_DSPI_DCTAR_PASC(x)               (((x)&0x3)<<0x14)
+#define MCF_DSPI_DCTAR_PASC_1CLK             (0)
+#define MCF_DSPI_DCTAR_PASC_3CLK             (0x100000)
+#define MCF_DSPI_DCTAR_PASC_5CLK             (0x200000)
+#define MCF_DSPI_DCTAR_PASC_7CLK             (0x300000)
+#define MCF_DSPI_DCTAR_PCSSCK(x)             (((x)&0x3)<<0x16)
+#define MCF_DSPI_DCTAR_LSBFE                 (0x1000000)
+#define MCF_DSPI_DCTAR_CPHA                  (0x2000000)
+#define MCF_DSPI_DCTAR_CPOL                  (0x4000000)
+#define MCF_DSPI_DCTAR_TRSZ(x)               (((x)&0xF)<<0x1B)
+
+/* Bit definitions and macros for MCF_DSPI_DSR */
+#define MCF_DSPI_DSR_RXPTR(x)                (((x)&0xF)<<0)
+#define MCF_DSPI_DSR_RXCTR(x)                (((x)&0xF)<<0x4)
+#define MCF_DSPI_DSR_TXPTR(x)                (((x)&0xF)<<0x8)
+#define MCF_DSPI_DSR_TXCTR(x)                (((x)&0xF)<<0xC)
+#define MCF_DSPI_DSR_RFDF                    (0x20000)
+#define MCF_DSPI_DSR_RFOF                    (0x80000)
+#define MCF_DSPI_DSR_TFFF                    (0x2000000)
+#define MCF_DSPI_DSR_TFUF                    (0x8000000)
+#define MCF_DSPI_DSR_EOQF                    (0x10000000)
+#define MCF_DSPI_DSR_TXRXS                   (0x40000000)
+#define MCF_DSPI_DSR_TCF                     (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DIRSR */
+#define MCF_DSPI_DIRSR_RFDFS                 (0x10000)
+#define MCF_DSPI_DIRSR_RFDFE                 (0x20000)
+#define MCF_DSPI_DIRSR_RFOFE                 (0x80000)
+#define MCF_DSPI_DIRSR_TFFFS                 (0x1000000)
+#define MCF_DSPI_DIRSR_TFFFE                 (0x2000000)
+#define MCF_DSPI_DIRSR_TFUFE                 (0x8000000)
+#define MCF_DSPI_DIRSR_EOQFE                 (0x10000000)
+#define MCF_DSPI_DIRSR_TCFE                  (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DTFR */
+#define MCF_DSPI_DTFR_TXDATA(x)              (((x)&0xFFFF)<<0)
+#define MCF_DSPI_DTFR_CS0                    (0x10000)
+#define MCF_DSPI_DTFR_CS2                    (0x40000)
+#define MCF_DSPI_DTFR_CS3                    (0x80000)
+#define MCF_DSPI_DTFR_CS5                    (0x200000)
+#define MCF_DSPI_DTFR_CTCNT                  (0x4000000)
+#define MCF_DSPI_DTFR_EOQ                    (0x8000000)
+#define MCF_DSPI_DTFR_CTAS(x)                (((x)&0x7)<<0x1C)
+#define MCF_DSPI_DTFR_CONT                   (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DRFR */
+#define MCF_DSPI_DRFR_RXDATA(x)              (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DSPI_DTFDR */
+#define MCF_DSPI_DTFDR_TXDATA(x)             (((x)&0xFFFF)<<0)
+#define MCF_DSPI_DTFDR_TXCMD(x)              (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_DSPI_DRFDR */
+#define MCF_DSPI_DRFDR_RXDATA(x)             (((x)&0xFFFF)<<0)
+
+
+#endif /* __MCF5475_DSPI_H__ */
--- a/tos/fpga_test/include/MCF5475_EPORT.h
+++ b/tos/fpga_test/include/MCF5475_EPORT.h
@@ -0,0 +1,123 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_EPORT_H__
+#define __MCF5475_EPORT_H__
+
+
+/*********************************************************************
+*
+* Edge Port Module (EPORT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_EPORT_EPPAR                      (*(volatile uint16_t*)(&_MBAR[0xF00]))
+#define MCF_EPORT_EPDDR                      (*(volatile uint8_t *)(&_MBAR[0xF04]))
+#define MCF_EPORT_EPIER                      (*(volatile uint8_t *)(&_MBAR[0xF05]))
+#define MCF_EPORT_EPDR                       (*(volatile uint8_t *)(&_MBAR[0xF08]))
+#define MCF_EPORT_EPPDR                      (*(volatile uint8_t *)(&_MBAR[0xF09]))
+#define MCF_EPORT_EPFR                       (*(volatile uint8_t *)(&_MBAR[0xF0C]))
+
+
+
+/* Bit definitions and macros for MCF_EPORT_EPPAR */
+#define MCF_EPORT_EPPAR_EPPA1(x)             (((x)&0x3)<<0x2)
+#define MCF_EPORT_EPPAR_EPPA1_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA1_RISING         (0x4)
+#define MCF_EPORT_EPPAR_EPPA1_FALLING        (0x8)
+#define MCF_EPORT_EPPAR_EPPA1_BOTH           (0xC)
+#define MCF_EPORT_EPPAR_EPPA2(x)             (((x)&0x3)<<0x4)
+#define MCF_EPORT_EPPAR_EPPA2_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA2_RISING         (0x10)
+#define MCF_EPORT_EPPAR_EPPA2_FALLING        (0x20)
+#define MCF_EPORT_EPPAR_EPPA2_BOTH           (0x30)
+#define MCF_EPORT_EPPAR_EPPA3(x)             (((x)&0x3)<<0x6)
+#define MCF_EPORT_EPPAR_EPPA3_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA3_RISING         (0x40)
+#define MCF_EPORT_EPPAR_EPPA3_FALLING        (0x80)
+#define MCF_EPORT_EPPAR_EPPA3_BOTH           (0xC0)
+#define MCF_EPORT_EPPAR_EPPA4(x)             (((x)&0x3)<<0x8)
+#define MCF_EPORT_EPPAR_EPPA4_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA4_RISING         (0x100)
+#define MCF_EPORT_EPPAR_EPPA4_FALLING        (0x200)
+#define MCF_EPORT_EPPAR_EPPA4_BOTH           (0x300)
+#define MCF_EPORT_EPPAR_EPPA5(x)             (((x)&0x3)<<0xA)
+#define MCF_EPORT_EPPAR_EPPA5_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA5_RISING         (0x400)
+#define MCF_EPORT_EPPAR_EPPA5_FALLING        (0x800)
+#define MCF_EPORT_EPPAR_EPPA5_BOTH           (0xC00)
+#define MCF_EPORT_EPPAR_EPPA6(x)             (((x)&0x3)<<0xC)
+#define MCF_EPORT_EPPAR_EPPA6_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA6_RISING         (0x1000)
+#define MCF_EPORT_EPPAR_EPPA6_FALLING        (0x2000)
+#define MCF_EPORT_EPPAR_EPPA6_BOTH           (0x3000)
+#define MCF_EPORT_EPPAR_EPPA7(x)             (((x)&0x3)<<0xE)
+#define MCF_EPORT_EPPAR_EPPA7_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA7_RISING         (0x4000)
+#define MCF_EPORT_EPPAR_EPPA7_FALLING        (0x8000)
+#define MCF_EPORT_EPPAR_EPPA7_BOTH           (0xC000)
+#define MCF_EPORT_EPPAR_LEVEL                (0)
+#define MCF_EPORT_EPPAR_RISING               (0x1)
+#define MCF_EPORT_EPPAR_FALLING              (0x2)
+#define MCF_EPORT_EPPAR_BOTH                 (0x3)
+
+/* Bit definitions and macros for MCF_EPORT_EPDDR */
+#define MCF_EPORT_EPDDR_EPDD1                (0x2)
+#define MCF_EPORT_EPDDR_EPDD2                (0x4)
+#define MCF_EPORT_EPDDR_EPDD3                (0x8)
+#define MCF_EPORT_EPDDR_EPDD4                (0x10)
+#define MCF_EPORT_EPDDR_EPDD5                (0x20)
+#define MCF_EPORT_EPDDR_EPDD6                (0x40)
+#define MCF_EPORT_EPDDR_EPDD7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPIER */
+#define MCF_EPORT_EPIER_EPIE1                (0x2)
+#define MCF_EPORT_EPIER_EPIE2                (0x4)
+#define MCF_EPORT_EPIER_EPIE3                (0x8)
+#define MCF_EPORT_EPIER_EPIE4                (0x10)
+#define MCF_EPORT_EPIER_EPIE5                (0x20)
+#define MCF_EPORT_EPIER_EPIE6                (0x40)
+#define MCF_EPORT_EPIER_EPIE7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPDR */
+#define MCF_EPORT_EPDR_EPD1                  (0x2)
+#define MCF_EPORT_EPDR_EPD2                  (0x4)
+#define MCF_EPORT_EPDR_EPD3                  (0x8)
+#define MCF_EPORT_EPDR_EPD4                  (0x10)
+#define MCF_EPORT_EPDR_EPD5                  (0x20)
+#define MCF_EPORT_EPDR_EPD6                  (0x40)
+#define MCF_EPORT_EPDR_EPD7                  (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPPDR */
+#define MCF_EPORT_EPPDR_EPPD1                (0x2)
+#define MCF_EPORT_EPPDR_EPPD2                (0x4)
+#define MCF_EPORT_EPPDR_EPPD3                (0x8)
+#define MCF_EPORT_EPPDR_EPPD4                (0x10)
+#define MCF_EPORT_EPPDR_EPPD5                (0x20)
+#define MCF_EPORT_EPPDR_EPPD6                (0x40)
+#define MCF_EPORT_EPPDR_EPPD7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPFR */
+#define MCF_EPORT_EPFR_EPF1                  (0x2)
+#define MCF_EPORT_EPFR_EPF2                  (0x4)
+#define MCF_EPORT_EPFR_EPF3                  (0x8)
+#define MCF_EPORT_EPFR_EPF4                  (0x10)
+#define MCF_EPORT_EPFR_EPF5                  (0x20)
+#define MCF_EPORT_EPFR_EPF6                  (0x40)
+#define MCF_EPORT_EPFR_EPF7                  (0x80)
+
+
+#endif /* __MCF5475_EPORT_H__ */
--- a/tos/fpga_test/include/MCF5475_FBCS.h
+++ b/tos/fpga_test/include/MCF5475_FBCS.h
@@ -0,0 +1,100 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_FBCS_H__
+#define __MCF5475_FBCS_H__
+
+
+/*********************************************************************
+*
+* FlexBus Chip Select Module (FBCS)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FBCS0_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x500]))
+#define MCF_FBCS0_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x504]))
+#define MCF_FBCS0_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x508]))
+
+#define MCF_FBCS1_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x50C]))
+#define MCF_FBCS1_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x510]))
+#define MCF_FBCS1_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x514]))
+
+#define MCF_FBCS2_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x518]))
+#define MCF_FBCS2_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x51C]))
+#define MCF_FBCS2_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x520]))
+
+#define MCF_FBCS3_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x524]))
+#define MCF_FBCS3_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x528]))
+#define MCF_FBCS3_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x52C]))
+
+#define MCF_FBCS4_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x530]))
+#define MCF_FBCS4_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x534]))
+#define MCF_FBCS4_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x538]))
+
+#define MCF_FBCS5_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x53C]))
+#define MCF_FBCS5_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x540]))
+#define MCF_FBCS5_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x544]))
+
+#define MCF_FBCS_CSAR(x)                     (*(volatile uint32_t*)(&_MBAR[0x500 + ((x)*0xC)]))
+#define MCF_FBCS_CSMR(x)                     (*(volatile uint32_t*)(&_MBAR[0x504 + ((x)*0xC)]))
+#define MCF_FBCS_CSCR(x)                     (*(volatile uint32_t*)(&_MBAR[0x508 + ((x)*0xC)]))
+
+
+/* Bit definitions and macros for MCF_FBCS_CSAR */
+#define MCF_FBCS_CSAR_BA(x)                  ((x)&0xFFFF0000)
+
+/* Bit definitions and macros for MCF_FBCS_CSMR */
+#define MCF_FBCS_CSMR_V                      (0x1)
+#define MCF_FBCS_CSMR_WP                     (0x100)
+#define MCF_FBCS_CSMR_BAM(x)                 (((x)&0xFFFF)<<0x10)
+#define MCF_FBCS_CSMR_BAM_4G                 (0xFFFF0000)
+#define MCF_FBCS_CSMR_BAM_2G                 (0x7FFF0000)
+#define MCF_FBCS_CSMR_BAM_1G                 (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_1024M              (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_512M               (0x1FFF0000)
+#define MCF_FBCS_CSMR_BAM_256M               (0xFFF0000)
+#define MCF_FBCS_CSMR_BAM_128M               (0x7FF0000)
+#define MCF_FBCS_CSMR_BAM_64M                (0x3FF0000)
+#define MCF_FBCS_CSMR_BAM_32M                (0x1FF0000)
+#define MCF_FBCS_CSMR_BAM_16M                (0xFF0000)
+#define MCF_FBCS_CSMR_BAM_8M                 (0x7F0000)
+#define MCF_FBCS_CSMR_BAM_4M                 (0x3F0000)
+#define MCF_FBCS_CSMR_BAM_2M                 (0x1F0000)
+#define MCF_FBCS_CSMR_BAM_1M                 (0xF0000)
+#define MCF_FBCS_CSMR_BAM_1024K              (0xF0000)
+#define MCF_FBCS_CSMR_BAM_512K               (0x70000)
+#define MCF_FBCS_CSMR_BAM_256K               (0x30000)
+#define MCF_FBCS_CSMR_BAM_128K               (0x10000)
+#define MCF_FBCS_CSMR_BAM_64K                (0)
+
+/* Bit definitions and macros for MCF_FBCS_CSCR */
+#define MCF_FBCS_CSCR_BSTW                   (0x8)
+#define MCF_FBCS_CSCR_BSTR                   (0x10)
+#define MCF_FBCS_CSCR_BEM                    (0x20)
+#define MCF_FBCS_CSCR_PS(x)                  (((x)&0x3)<<0x6)
+#define MCF_FBCS_CSCR_PS_32                  (0)
+#define MCF_FBCS_CSCR_PS_8                   (0x40)
+#define MCF_FBCS_CSCR_PS_16                  (0x80)
+#define MCF_FBCS_CSCR_AA                     (0x100)
+#define MCF_FBCS_CSCR_WS(x)                  (((x)&0x3F)<<0xA)
+#define MCF_FBCS_CSCR_WRAH(x)                (((x)&0x3)<<0x10)
+#define MCF_FBCS_CSCR_RDAH(x)                (((x)&0x3)<<0x12)
+#define MCF_FBCS_CSCR_ASET(x)                (((x)&0x3)<<0x14)
+#define MCF_FBCS_CSCR_SWSEN                  (0x800000)
+#define MCF_FBCS_CSCR_SWS(x)                 (((x)&0x3F)<<0x1A)
+
+
+#endif /* __MCF5475_FBCS_H__ */
--- a/tos/fpga_test/include/MCF5475_FEC.h
+++ b/tos/fpga_test/include/MCF5475_FEC.h
@@ -0,0 +1,680 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_FEC_H__
+#define __MCF5475_FEC_H__
+
+
+/*********************************************************************
+*
+* Fast Ethernet Controller(FEC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FEC0_EIR                         (*(volatile uint32_t*)(&_MBAR[0x9004]))
+#define MCF_FEC0_EIMR                        (*(volatile uint32_t*)(&_MBAR[0x9008]))
+#define MCF_FEC0_ECR                         (*(volatile uint32_t*)(&_MBAR[0x9024]))
+#define MCF_FEC0_MMFR                        (*(volatile uint32_t*)(&_MBAR[0x9040]))
+#define MCF_FEC0_MSCR                        (*(volatile uint32_t*)(&_MBAR[0x9044]))
+#define MCF_FEC0_MIBC                        (*(volatile uint32_t*)(&_MBAR[0x9064]))
+#define MCF_FEC0_RCR                         (*(volatile uint32_t*)(&_MBAR[0x9084]))
+#define MCF_FEC0_RHR                         (*(volatile uint32_t*)(&_MBAR[0x9088]))
+#define MCF_FEC0_TCR                         (*(volatile uint32_t*)(&_MBAR[0x90C4]))
+#define MCF_FEC0_PALR                        (*(volatile uint32_t*)(&_MBAR[0x90E4]))
+#define MCF_FEC0_PAHR                        (*(volatile uint32_t*)(&_MBAR[0x90E8]))
+#define MCF_FEC0_OPD                         (*(volatile uint32_t*)(&_MBAR[0x90EC]))
+#define MCF_FEC0_IAUR                        (*(volatile uint32_t*)(&_MBAR[0x9118]))
+#define MCF_FEC0_IALR                        (*(volatile uint32_t*)(&_MBAR[0x911C]))
+#define MCF_FEC0_GAUR                        (*(volatile uint32_t*)(&_MBAR[0x9120]))
+#define MCF_FEC0_GALR                        (*(volatile uint32_t*)(&_MBAR[0x9124]))
+#define MCF_FEC0_FECTFWR                     (*(volatile uint32_t*)(&_MBAR[0x9144]))
+#define MCF_FEC0_FECRFDR                     (*(volatile uint32_t*)(&_MBAR[0x9184]))
+#define MCF_FEC0_FECRFSR                     (*(volatile uint32_t*)(&_MBAR[0x9188]))
+#define MCF_FEC0_FECRFCR                     (*(volatile uint32_t*)(&_MBAR[0x918C]))
+#define MCF_FEC0_FECRLRFP                    (*(volatile uint32_t*)(&_MBAR[0x9190]))
+#define MCF_FEC0_FECRLWFP                    (*(volatile uint32_t*)(&_MBAR[0x9194]))
+#define MCF_FEC0_FECRFAR                     (*(volatile uint32_t*)(&_MBAR[0x9198]))
+#define MCF_FEC0_FECRFRP                     (*(volatile uint32_t*)(&_MBAR[0x919C]))
+#define MCF_FEC0_FECRFWP                     (*(volatile uint32_t*)(&_MBAR[0x91A0]))
+#define MCF_FEC0_FECTFDR                     (*(volatile uint32_t*)(&_MBAR[0x91A4]))
+#define MCF_FEC0_FECTFSR                     (*(volatile uint32_t*)(&_MBAR[0x91A8]))
+#define MCF_FEC0_FECTFCR                     (*(volatile uint32_t*)(&_MBAR[0x91AC]))
+#define MCF_FEC0_FECTLRFP                    (*(volatile uint32_t*)(&_MBAR[0x91B0]))
+#define MCF_FEC0_FECTLWFP                    (*(volatile uint32_t*)(&_MBAR[0x91B4]))
+#define MCF_FEC0_FECTFAR                     (*(volatile uint32_t*)(&_MBAR[0x91B8]))
+#define MCF_FEC0_FECTFRP                     (*(volatile uint32_t*)(&_MBAR[0x91BC]))
+#define MCF_FEC0_FECTFWP                     (*(volatile uint32_t*)(&_MBAR[0x91C0]))
+#define MCF_FEC0_FECFRST                     (*(volatile uint32_t*)(&_MBAR[0x91C4]))
+#define MCF_FEC0_FECCTCWR                    (*(volatile uint32_t*)(&_MBAR[0x91C8]))
+#define MCF_FEC0_RMON_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9200]))
+#define MCF_FEC0_RMON_T_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9204]))
+#define MCF_FEC0_RMON_T_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9208]))
+#define MCF_FEC0_RMON_T_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x920C]))
+#define MCF_FEC0_RMON_T_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9210]))
+#define MCF_FEC0_RMON_T_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9214]))
+#define MCF_FEC0_RMON_T_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9218]))
+#define MCF_FEC0_RMON_T_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x921C]))
+#define MCF_FEC0_RMON_T_JAB                  (*(volatile uint32_t*)(&_MBAR[0x9220]))
+#define MCF_FEC0_RMON_T_COL                  (*(volatile uint32_t*)(&_MBAR[0x9224]))
+#define MCF_FEC0_RMON_T_P64                  (*(volatile uint32_t*)(&_MBAR[0x9228]))
+#define MCF_FEC0_RMON_T_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x922C]))
+#define MCF_FEC0_RMON_T_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x9230]))
+#define MCF_FEC0_RMON_T_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x9234]))
+#define MCF_FEC0_RMON_T_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x9238]))
+#define MCF_FEC0_RMON_T_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x923C]))
+#define MCF_FEC0_RMON_T_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x9240]))
+#define MCF_FEC0_RMON_T_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x9244]))
+#define MCF_FEC0_IEEE_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9248]))
+#define MCF_FEC0_IEEE_T_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x924C]))
+#define MCF_FEC0_IEEE_T_1COL                 (*(volatile uint32_t*)(&_MBAR[0x9250]))
+#define MCF_FEC0_IEEE_T_MCOL                 (*(volatile uint32_t*)(&_MBAR[0x9254]))
+#define MCF_FEC0_IEEE_T_DEF                  (*(volatile uint32_t*)(&_MBAR[0x9258]))
+#define MCF_FEC0_IEEE_T_LCOL                 (*(volatile uint32_t*)(&_MBAR[0x925C]))
+#define MCF_FEC0_IEEE_T_EXCOL                (*(volatile uint32_t*)(&_MBAR[0x9260]))
+#define MCF_FEC0_IEEE_T_MACERR               (*(volatile uint32_t*)(&_MBAR[0x9264]))
+#define MCF_FEC0_IEEE_T_CSERR                (*(volatile uint32_t*)(&_MBAR[0x9268]))
+#define MCF_FEC0_IEEE_T_SQE                  (*(volatile uint32_t*)(&_MBAR[0x926C]))
+#define MCF_FEC0_IEEE_T_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x9270]))
+#define MCF_FEC0_IEEE_T_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x9274]))
+#define MCF_FEC0_RMON_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9280]))
+#define MCF_FEC0_RMON_R_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9284]))
+#define MCF_FEC0_RMON_R_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9288]))
+#define MCF_FEC0_RMON_R_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x928C]))
+#define MCF_FEC0_RMON_R_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9290]))
+#define MCF_FEC0_RMON_R_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9294]))
+#define MCF_FEC0_RMON_R_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9298]))
+#define MCF_FEC0_RMON_R_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x929C]))
+#define MCF_FEC0_RMON_R_JAB                  (*(volatile uint32_t*)(&_MBAR[0x92A0]))
+#define MCF_FEC0_RMON_R_RESVD_0              (*(volatile uint32_t*)(&_MBAR[0x92A4]))
+#define MCF_FEC0_RMON_R_P64                  (*(volatile uint32_t*)(&_MBAR[0x92A8]))
+#define MCF_FEC0_RMON_R_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x92AC]))
+#define MCF_FEC0_RMON_R_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x92B0]))
+#define MCF_FEC0_RMON_R_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x92B4]))
+#define MCF_FEC0_RMON_R_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x92B8]))
+#define MCF_FEC0_RMON_R_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x92BC]))
+#define MCF_FEC0_RMON_R_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x92C0]))
+#define MCF_FEC0_RMON_R_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x92C4]))
+#define MCF_FEC0_IEEE_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x92C8]))
+#define MCF_FEC0_IEEE_R_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x92CC]))
+#define MCF_FEC0_IEEE_R_CRC                  (*(volatile uint32_t*)(&_MBAR[0x92D0]))
+#define MCF_FEC0_IEEE_R_ALIGN                (*(volatile uint32_t*)(&_MBAR[0x92D4]))
+#define MCF_FEC0_IEEE_R_MACERR               (*(volatile uint32_t*)(&_MBAR[0x92D8]))
+#define MCF_FEC0_IEEE_R_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x92DC]))
+#define MCF_FEC0_IEEE_R_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x92E0]))
+
+#define MCF_FEC1_EIR                         (*(volatile uint32_t*)(&_MBAR[0x9804]))
+#define MCF_FEC1_EIMR                        (*(volatile uint32_t*)(&_MBAR[0x9808]))
+#define MCF_FEC1_ECR                         (*(volatile uint32_t*)(&_MBAR[0x9824]))
+#define MCF_FEC1_MMFR                        (*(volatile uint32_t*)(&_MBAR[0x9840]))
+#define MCF_FEC1_MSCR                        (*(volatile uint32_t*)(&_MBAR[0x9844]))
+#define MCF_FEC1_MIBC                        (*(volatile uint32_t*)(&_MBAR[0x9864]))
+#define MCF_FEC1_RCR                         (*(volatile uint32_t*)(&_MBAR[0x9884]))
+#define MCF_FEC1_RHR                         (*(volatile uint32_t*)(&_MBAR[0x9888]))
+#define MCF_FEC1_TCR                         (*(volatile uint32_t*)(&_MBAR[0x98C4]))
+#define MCF_FEC1_PALR                        (*(volatile uint32_t*)(&_MBAR[0x98E4]))
+#define MCF_FEC1_PAHR                        (*(volatile uint32_t*)(&_MBAR[0x98E8]))
+#define MCF_FEC1_OPD                         (*(volatile uint32_t*)(&_MBAR[0x98EC]))
+#define MCF_FEC1_IAUR                        (*(volatile uint32_t*)(&_MBAR[0x9918]))
+#define MCF_FEC1_IALR                        (*(volatile uint32_t*)(&_MBAR[0x991C]))
+#define MCF_FEC1_GAUR                        (*(volatile uint32_t*)(&_MBAR[0x9920]))
+#define MCF_FEC1_GALR                        (*(volatile uint32_t*)(&_MBAR[0x9924]))
+#define MCF_FEC1_FECTFWR                     (*(volatile uint32_t*)(&_MBAR[0x9944]))
+#define MCF_FEC1_FECRFDR                     (*(volatile uint32_t*)(&_MBAR[0x9984]))
+#define MCF_FEC1_FECRFSR                     (*(volatile uint32_t*)(&_MBAR[0x9988]))
+#define MCF_FEC1_FECRFCR                     (*(volatile uint32_t*)(&_MBAR[0x998C]))
+#define MCF_FEC1_FECRLRFP                    (*(volatile uint32_t*)(&_MBAR[0x9990]))
+#define MCF_FEC1_FECRLWFP                    (*(volatile uint32_t*)(&_MBAR[0x9994]))
+#define MCF_FEC1_FECRFAR                     (*(volatile uint32_t*)(&_MBAR[0x9998]))
+#define MCF_FEC1_FECRFRP                     (*(volatile uint32_t*)(&_MBAR[0x999C]))
+#define MCF_FEC1_FECRFWP                     (*(volatile uint32_t*)(&_MBAR[0x99A0]))
+#define MCF_FEC1_FECTFDR                     (*(volatile uint32_t*)(&_MBAR[0x99A4]))
+#define MCF_FEC1_FECTFSR                     (*(volatile uint32_t*)(&_MBAR[0x99A8]))
+#define MCF_FEC1_FECTFCR                     (*(volatile uint32_t*)(&_MBAR[0x99AC]))
+#define MCF_FEC1_FECTLRFP                    (*(volatile uint32_t*)(&_MBAR[0x99B0]))
+#define MCF_FEC1_FECTLWFP                    (*(volatile uint32_t*)(&_MBAR[0x99B4]))
+#define MCF_FEC1_FECTFAR                     (*(volatile uint32_t*)(&_MBAR[0x99B8]))
+#define MCF_FEC1_FECTFRP                     (*(volatile uint32_t*)(&_MBAR[0x99BC]))
+#define MCF_FEC1_FECTFWP                     (*(volatile uint32_t*)(&_MBAR[0x99C0]))
+#define MCF_FEC1_FECFRST                     (*(volatile uint32_t*)(&_MBAR[0x99C4]))
+#define MCF_FEC1_FECCTCWR                    (*(volatile uint32_t*)(&_MBAR[0x99C8]))
+#define MCF_FEC1_RMON_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9A00]))
+#define MCF_FEC1_RMON_T_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9A04]))
+#define MCF_FEC1_RMON_T_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A08]))
+#define MCF_FEC1_RMON_T_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A0C]))
+#define MCF_FEC1_RMON_T_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9A10]))
+#define MCF_FEC1_RMON_T_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9A14]))
+#define MCF_FEC1_RMON_T_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9A18]))
+#define MCF_FEC1_RMON_T_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x9A1C]))
+#define MCF_FEC1_RMON_T_JAB                  (*(volatile uint32_t*)(&_MBAR[0x9A20]))
+#define MCF_FEC1_RMON_T_COL                  (*(volatile uint32_t*)(&_MBAR[0x9A24]))
+#define MCF_FEC1_RMON_T_P64                  (*(volatile uint32_t*)(&_MBAR[0x9A28]))
+#define MCF_FEC1_RMON_T_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x9A2C]))
+#define MCF_FEC1_RMON_T_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x9A30]))
+#define MCF_FEC1_RMON_T_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x9A34]))
+#define MCF_FEC1_RMON_T_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x9A38]))
+#define MCF_FEC1_RMON_T_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x9A3C]))
+#define MCF_FEC1_RMON_T_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x9A40]))
+#define MCF_FEC1_RMON_T_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x9A44]))
+#define MCF_FEC1_IEEE_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9A48]))
+#define MCF_FEC1_IEEE_T_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x9A4C]))
+#define MCF_FEC1_IEEE_T_1COL                 (*(volatile uint32_t*)(&_MBAR[0x9A50]))
+#define MCF_FEC1_IEEE_T_MCOL                 (*(volatile uint32_t*)(&_MBAR[0x9A54]))
+#define MCF_FEC1_IEEE_T_DEF                  (*(volatile uint32_t*)(&_MBAR[0x9A58]))
+#define MCF_FEC1_IEEE_T_LCOL                 (*(volatile uint32_t*)(&_MBAR[0x9A5C]))
+#define MCF_FEC1_IEEE_T_EXCOL                (*(volatile uint32_t*)(&_MBAR[0x9A60]))
+#define MCF_FEC1_IEEE_T_MACERR               (*(volatile uint32_t*)(&_MBAR[0x9A64]))
+#define MCF_FEC1_IEEE_T_CSERR                (*(volatile uint32_t*)(&_MBAR[0x9A68]))
+#define MCF_FEC1_IEEE_T_SQE                  (*(volatile uint32_t*)(&_MBAR[0x9A6C]))
+#define MCF_FEC1_IEEE_T_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x9A70]))
+#define MCF_FEC1_IEEE_T_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x9A74]))
+#define MCF_FEC1_RMON_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9A80]))
+#define MCF_FEC1_RMON_R_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9A84]))
+#define MCF_FEC1_RMON_R_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A88]))
+#define MCF_FEC1_RMON_R_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A8C]))
+#define MCF_FEC1_RMON_R_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9A90]))
+#define MCF_FEC1_RMON_R_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9A94]))
+#define MCF_FEC1_RMON_R_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9A98]))
+#define MCF_FEC1_RMON_R_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x9A9C]))
+#define MCF_FEC1_RMON_R_JAB                  (*(volatile uint32_t*)(&_MBAR[0x9AA0]))
+#define MCF_FEC1_RMON_R_RESVD_0              (*(volatile uint32_t*)(&_MBAR[0x9AA4]))
+#define MCF_FEC1_RMON_R_P64                  (*(volatile uint32_t*)(&_MBAR[0x9AA8]))
+#define MCF_FEC1_RMON_R_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x9AAC]))
+#define MCF_FEC1_RMON_R_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x9AB0]))
+#define MCF_FEC1_RMON_R_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x9AB4]))
+#define MCF_FEC1_RMON_R_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x9AB8]))
+#define MCF_FEC1_RMON_R_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x9ABC]))
+#define MCF_FEC1_RMON_R_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x9AC0]))
+#define MCF_FEC1_RMON_R_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x9AC4]))
+#define MCF_FEC1_IEEE_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9AC8]))
+#define MCF_FEC1_IEEE_R_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x9ACC]))
+#define MCF_FEC1_IEEE_R_CRC                  (*(volatile uint32_t*)(&_MBAR[0x9AD0]))
+#define MCF_FEC1_IEEE_R_ALIGN                (*(volatile uint32_t*)(&_MBAR[0x9AD4]))
+#define MCF_FEC1_IEEE_R_MACERR               (*(volatile uint32_t*)(&_MBAR[0x9AD8]))
+#define MCF_FEC1_IEEE_R_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x9ADC]))
+#define MCF_FEC1_IEEE_R_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x9AE0]))
+
+#define MCF_FEC_EIR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9004 + ((x)*0x800)]))
+#define MCF_FEC_EIMR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9008 + ((x)*0x800)]))
+#define MCF_FEC_ECR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9024 + ((x)*0x800)]))
+#define MCF_FEC_MMFR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9040 + ((x)*0x800)]))
+#define MCF_FEC_MSCR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9044 + ((x)*0x800)]))
+#define MCF_FEC_MIBC(x)                      (*(volatile uint32_t*)(&_MBAR[0x9064 + ((x)*0x800)]))
+#define MCF_FEC_RCR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9084 + ((x)*0x800)]))
+#define MCF_FEC_RHR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9088 + ((x)*0x800)]))
+#define MCF_FEC_TCR(x)                       (*(volatile uint32_t*)(&_MBAR[0x90C4 + ((x)*0x800)]))
+#define MCF_FEC_PALR(x)                      (*(volatile uint32_t*)(&_MBAR[0x90E4 + ((x)*0x800)]))
+#define MCF_FEC_PAHR(x)                      (*(volatile uint32_t*)(&_MBAR[0x90E8 + ((x)*0x800)]))
+#define MCF_FEC_OPD(x)                       (*(volatile uint32_t*)(&_MBAR[0x90EC + ((x)*0x800)]))
+#define MCF_FEC_IAUR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9118 + ((x)*0x800)]))
+#define MCF_FEC_IALR(x)                      (*(volatile uint32_t*)(&_MBAR[0x911C + ((x)*0x800)]))
+#define MCF_FEC_GAUR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9120 + ((x)*0x800)]))
+#define MCF_FEC_GALR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9124 + ((x)*0x800)]))
+#define MCF_FEC_FECTFWR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9144 + ((x)*0x800)]))
+#define MCF_FEC_FECRFDR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9184 + ((x)*0x800)]))
+#define MCF_FEC_FECRFSR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9188 + ((x)*0x800)]))
+#define MCF_FEC_FECRFCR(x)                   (*(volatile uint32_t*)(&_MBAR[0x918C + ((x)*0x800)]))
+#define MCF_FEC_FECRLRFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x9190 + ((x)*0x800)]))
+#define MCF_FEC_FECRLWFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x9194 + ((x)*0x800)]))
+#define MCF_FEC_FECRFAR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9198 + ((x)*0x800)]))
+#define MCF_FEC_FECRFRP(x)                   (*(volatile uint32_t*)(&_MBAR[0x919C + ((x)*0x800)]))
+#define MCF_FEC_FECRFWP(x)                   (*(volatile uint32_t*)(&_MBAR[0x91A0 + ((x)*0x800)]))
+#define MCF_FEC_FECTFDR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91A4 + ((x)*0x800)]))
+#define MCF_FEC_FECTFSR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91A8 + ((x)*0x800)]))
+#define MCF_FEC_FECTFCR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91AC + ((x)*0x800)]))
+#define MCF_FEC_FECTLRFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x91B0 + ((x)*0x800)]))
+#define MCF_FEC_FECTLWFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x91B4 + ((x)*0x800)]))
+#define MCF_FEC_FECTFAR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91B8 + ((x)*0x800)]))
+#define MCF_FEC_FECTFRP(x)                   (*(volatile uint32_t*)(&_MBAR[0x91BC + ((x)*0x800)]))
+#define MCF_FEC_FECTFWP(x)                   (*(volatile uint32_t*)(&_MBAR[0x91C0 + ((x)*0x800)]))
+#define MCF_FEC_FECFRST(x)                   (*(volatile uint32_t*)(&_MBAR[0x91C4 + ((x)*0x800)]))
+#define MCF_FEC_FECCTCWR(x)                  (*(volatile uint32_t*)(&_MBAR[0x91C8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x9200 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_PACKETS(x)            (*(volatile uint32_t*)(&_MBAR[0x9204 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_BC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x9208 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_MC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x920C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_CRC_ALIGN(x)          (*(volatile uint32_t*)(&_MBAR[0x9210 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_UNDERSIZE(x)          (*(volatile uint32_t*)(&_MBAR[0x9214 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_OVERSIZE(x)           (*(volatile uint32_t*)(&_MBAR[0x9218 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_FRAG(x)               (*(volatile uint32_t*)(&_MBAR[0x921C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_JAB(x)                (*(volatile uint32_t*)(&_MBAR[0x9220 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_COL(x)                (*(volatile uint32_t*)(&_MBAR[0x9224 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P64(x)                (*(volatile uint32_t*)(&_MBAR[0x9228 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P65TO127(x)           (*(volatile uint32_t*)(&_MBAR[0x922C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P128TO255(x)          (*(volatile uint32_t*)(&_MBAR[0x9230 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P256TO511(x)          (*(volatile uint32_t*)(&_MBAR[0x9234 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P512TO1023(x)         (*(volatile uint32_t*)(&_MBAR[0x9238 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P1024TO2047(x)        (*(volatile uint32_t*)(&_MBAR[0x923C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P_GTE2048(x)          (*(volatile uint32_t*)(&_MBAR[0x9240 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_OCTETS(x)             (*(volatile uint32_t*)(&_MBAR[0x9244 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x9248 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_FRAME_OK(x)           (*(volatile uint32_t*)(&_MBAR[0x924C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_1COL(x)               (*(volatile uint32_t*)(&_MBAR[0x9250 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_MCOL(x)               (*(volatile uint32_t*)(&_MBAR[0x9254 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_DEF(x)                (*(volatile uint32_t*)(&_MBAR[0x9258 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_LCOL(x)               (*(volatile uint32_t*)(&_MBAR[0x925C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_EXCOL(x)              (*(volatile uint32_t*)(&_MBAR[0x9260 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_MACERR(x)             (*(volatile uint32_t*)(&_MBAR[0x9264 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_CSERR(x)              (*(volatile uint32_t*)(&_MBAR[0x9268 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_SQE(x)                (*(volatile uint32_t*)(&_MBAR[0x926C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_FDXFC(x)              (*(volatile uint32_t*)(&_MBAR[0x9270 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_OCTETS_OK(x)          (*(volatile uint32_t*)(&_MBAR[0x9274 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x9280 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_PACKETS(x)            (*(volatile uint32_t*)(&_MBAR[0x9284 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_BC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x9288 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_MC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x928C + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_CRC_ALIGN(x)          (*(volatile uint32_t*)(&_MBAR[0x9290 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_UNDERSIZE(x)          (*(volatile uint32_t*)(&_MBAR[0x9294 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_OVERSIZE(x)           (*(volatile uint32_t*)(&_MBAR[0x9298 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_FRAG(x)               (*(volatile uint32_t*)(&_MBAR[0x929C + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_JAB(x)                (*(volatile uint32_t*)(&_MBAR[0x92A0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_RESVD_0(x)            (*(volatile uint32_t*)(&_MBAR[0x92A4 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P64(x)                (*(volatile uint32_t*)(&_MBAR[0x92A8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P65TO127(x)           (*(volatile uint32_t*)(&_MBAR[0x92AC + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P128TO255(x)          (*(volatile uint32_t*)(&_MBAR[0x92B0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P256TO511(x)          (*(volatile uint32_t*)(&_MBAR[0x92B4 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P512TO1023(x)         (*(volatile uint32_t*)(&_MBAR[0x92B8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P1024TO2047(x)        (*(volatile uint32_t*)(&_MBAR[0x92BC + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P_GTE2048(x)          (*(volatile uint32_t*)(&_MBAR[0x92C0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_OCTETS(x)             (*(volatile uint32_t*)(&_MBAR[0x92C4 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x92C8 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_FRAME_OK(x)           (*(volatile uint32_t*)(&_MBAR[0x92CC + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_CRC(x)                (*(volatile uint32_t*)(&_MBAR[0x92D0 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_ALIGN(x)              (*(volatile uint32_t*)(&_MBAR[0x92D4 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_MACERR(x)             (*(volatile uint32_t*)(&_MBAR[0x92D8 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_FDXFC(x)              (*(volatile uint32_t*)(&_MBAR[0x92DC + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_OCTETS_OK(x)          (*(volatile uint32_t*)(&_MBAR[0x92E0 + ((x)*0x800)]))
+
+
+/* Bit definitions and macros for MCF_FEC_EIR */
+#define MCF_FEC_EIR_RFERR                    (0x20000)
+#define MCF_FEC_EIR_XFERR                    (0x40000)
+#define MCF_FEC_EIR_XFUN                     (0x80000)
+#define MCF_FEC_EIR_RL                       (0x100000)
+#define MCF_FEC_EIR_LC                       (0x200000)
+#define MCF_FEC_EIR_MII                      (0x800000)
+#define MCF_FEC_EIR_TXF                      (0x8000000)
+#define MCF_FEC_EIR_GRA                      (0x10000000)
+#define MCF_FEC_EIR_BABT                     (0x20000000)
+#define MCF_FEC_EIR_BABR                     (0x40000000)
+#define MCF_FEC_EIR_HBERR                    (0x80000000)
+#define MCF_FEC_EIR_CLEAR_ALL                (0xFFFFFFFF)
+
+/* Bit definitions and macros for MCF_FEC_EIMR */
+#define MCF_FEC_EIMR_RFERR                   (0x20000)
+#define MCF_FEC_EIMR_XFERR                   (0x40000)
+#define MCF_FEC_EIMR_XFUN                    (0x80000)
+#define MCF_FEC_EIMR_RL                      (0x100000)
+#define MCF_FEC_EIMR_LC                      (0x200000)
+#define MCF_FEC_EIMR_MII                     (0x800000)
+#define MCF_FEC_EIMR_TXF                     (0x8000000)
+#define MCF_FEC_EIMR_GRA                     (0x10000000)
+#define MCF_FEC_EIMR_BABT                    (0x20000000)
+#define MCF_FEC_EIMR_BABR                    (0x40000000)
+#define MCF_FEC_EIMR_HBERR                   (0x80000000)
+#define MCF_FEC_EIMR_MASK_ALL                (0)
+#define MCF_FEC_EIMR_UNMASK_ALL              (0xFFFFFFFF)
+
+/* Bit definitions and macros for MCF_FEC_ECR */
+#define MCF_FEC_ECR_RESET                    (0x1)
+#define MCF_FEC_ECR_ETHER_EN                 (0x2)
+
+/* Bit definitions and macros for MCF_FEC_MMFR */
+#define MCF_FEC_MMFR_DATA(x)                 (((x)&0xFFFF)<<0)
+#define MCF_FEC_MMFR_TA(x)                   (((x)&0x3)<<0x10)
+#define MCF_FEC_MMFR_TA_10                   (0x20000)
+#define MCF_FEC_MMFR_RA(x)                   (((x)&0x1F)<<0x12)
+#define MCF_FEC_MMFR_PA(x)                   (((x)&0x1F)<<0x17)
+#define MCF_FEC_MMFR_OP(x)                   (((x)&0x3)<<0x1C)
+#define MCF_FEC_MMFR_OP_READ                 (0x20000000)
+#define MCF_FEC_MMFR_OP_WRITE                (0x10000000)
+#define MCF_FEC_MMFR_ST(x)                   (((x)&0x3)<<0x1E)
+#define MCF_FEC_MMFR_ST_01                   (0x40000000)
+
+/* Bit definitions and macros for MCF_FEC_MSCR */
+#define MCF_FEC_MSCR_MII_SPEED(x)            (((x)&0x3F)<<0x1)
+#define MCF_FEC_MSCR_DIS_PREAMBLE            (0x80)
+#define MCF_FEC_MSCR_MII_SPEED_133           (0x1B<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_120           (0x18<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_66            (0xE<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_60            (0xC<<0x1)
+
+/* Bit definitions and macros for MCF_FEC_MIBC */
+#define MCF_FEC_MIBC_MIB_IDLE                (0x40000000)
+#define MCF_FEC_MIBC_MIB_DISABLE             (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_RCR */
+#define MCF_FEC_RCR_LOOP                     (0x1)
+#define MCF_FEC_RCR_DRT                      (0x2)
+#define MCF_FEC_RCR_MII_MODE                 (0x4)
+#define MCF_FEC_RCR_PROM                     (0x8)
+#define MCF_FEC_RCR_BC_REJ                   (0x10)
+#define MCF_FEC_RCR_FCE                      (0x20)
+#define MCF_FEC_RCR_MAX_FL(x)                (((x)&0x7FF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_RHR */
+#define MCF_FEC_RHR_HASH(x)                  (((x)&0x3F)<<0x18)
+#define MCF_FEC_RHR_MULTCAST                 (0x40000000)
+#define MCF_FEC_RHR_FCE                      (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_TCR */
+#define MCF_FEC_TCR_GTS                      (0x1)
+#define MCF_FEC_TCR_HBC                      (0x2)
+#define MCF_FEC_TCR_FDEN                     (0x4)
+#define MCF_FEC_TCR_TFC_PAUSE                (0x8)
+#define MCF_FEC_TCR_RFC_PAUSE                (0x10)
+
+/* Bit definitions and macros for MCF_FEC_PALR */
+#define MCF_FEC_PALR_PADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_PAHR */
+#define MCF_FEC_PAHR_TYPE(x)                 (((x)&0xFFFF)<<0)
+#define MCF_FEC_PAHR_PADDR2(x)               (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_OPD */
+#define MCF_FEC_OPD_PAUSE_DUR(x)             (((x)&0xFFFF)<<0)
+#define MCF_FEC_OPD_OPCODE(x)                (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_IAUR */
+#define MCF_FEC_IAUR_IADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IALR */
+#define MCF_FEC_IALR_IADDR2(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_GAUR */
+#define MCF_FEC_GAUR_GADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_GALR */
+#define MCF_FEC_GALR_GADDR2(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFWR */
+#define MCF_FEC_FECTFWR_X_WMRK(x)            (((x)&0xF)<<0)
+#define MCF_FEC_FECTFWR_X_WMRK_64            (0)
+#define MCF_FEC_FECTFWR_X_WMRK_128           (0x1)
+#define MCF_FEC_FECTFWR_X_WMRK_192           (0x2)
+#define MCF_FEC_FECTFWR_X_WMRK_256           (0x3)
+#define MCF_FEC_FECTFWR_X_WMRK_320           (0x4)
+#define MCF_FEC_FECTFWR_X_WMRK_384           (0x5)
+#define MCF_FEC_FECTFWR_X_WMRK_448           (0x6)
+#define MCF_FEC_FECTFWR_X_WMRK_512           (0x7)
+#define MCF_FEC_FECTFWR_X_WMRK_576           (0x8)
+#define MCF_FEC_FECTFWR_X_WMRK_640           (0x9)
+#define MCF_FEC_FECTFWR_X_WMRK_704           (0xA)
+#define MCF_FEC_FECTFWR_X_WMRK_768           (0xB)
+#define MCF_FEC_FECTFWR_X_WMRK_832           (0xC)
+#define MCF_FEC_FECTFWR_X_WMRK_896           (0xD)
+#define MCF_FEC_FECTFWR_X_WMRK_960           (0xE)
+#define MCF_FEC_FECTFWR_X_WMRK_1024          (0xF)
+
+/* Bit definitions and macros for MCF_FEC_FECRFDR */
+#define MCF_FEC_FECRFDR_FIFO_DATA(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFSR */
+#define MCF_FEC_FECRFSR_EMT                  (0x10000)
+#define MCF_FEC_FECRFSR_ALARM                (0x20000)
+#define MCF_FEC_FECRFSR_FU                   (0x40000)
+#define MCF_FEC_FECRFSR_FRMRDY               (0x80000)
+#define MCF_FEC_FECRFSR_OF                   (0x100000)
+#define MCF_FEC_FECRFSR_UF                   (0x200000)
+#define MCF_FEC_FECRFSR_RXW                  (0x400000)
+#define MCF_FEC_FECRFSR_FAE                  (0x800000)
+#define MCF_FEC_FECRFSR_FRM(x)               (((x)&0xF)<<0x18)
+#define MCF_FEC_FECRFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_FECRFCR */
+#define MCF_FEC_FECRFCR_COUNTER(x)           (((x)&0xFFFF)<<0)
+#define MCF_FEC_FECRFCR_OF_MSK               (0x80000)
+#define MCF_FEC_FECRFCR_UF_MSK               (0x100000)
+#define MCF_FEC_FECRFCR_RXW_MSK              (0x200000)
+#define MCF_FEC_FECRFCR_FAE_MSK              (0x400000)
+#define MCF_FEC_FECRFCR_IP_MSK               (0x800000)
+#define MCF_FEC_FECRFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_FEC_FECRFCR_FRMEN                (0x8000000)
+#define MCF_FEC_FECRFCR_TIMER                (0x10000000)
+
+/* Bit definitions and macros for MCF_FEC_FECRLRFP */
+#define MCF_FEC_FECRLRFP_LRFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRLWFP */
+#define MCF_FEC_FECRLWFP_LWFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFAR */
+#define MCF_FEC_FECRFAR_ALARM(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFRP */
+#define MCF_FEC_FECRFRP_READ(x)              (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFWP */
+#define MCF_FEC_FECRFWP_WRITE(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFDR */
+#define MCF_FEC_FECTFDR_FIFO_DATA(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFSR */
+#define MCF_FEC_FECTFSR_EMT                  (0x10000)
+#define MCF_FEC_FECTFSR_ALARM                (0x20000)
+#define MCF_FEC_FECTFSR_FU                   (0x40000)
+#define MCF_FEC_FECTFSR_FRMRDY               (0x80000)
+#define MCF_FEC_FECTFSR_OF                   (0x100000)
+#define MCF_FEC_FECTFSR_UF                   (0x200000)
+#define MCF_FEC_FECTFSR_FAE                  (0x800000)
+#define MCF_FEC_FECTFSR_FRM(x)               (((x)&0xF)<<0x18)
+#define MCF_FEC_FECTFSR_TXW                  (0x40000000)
+#define MCF_FEC_FECTFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_FECTFCR */
+#define MCF_FEC_FECTFCR_RESERVED             (0x200000)
+#define MCF_FEC_FECTFCR_COUNTER(x)           (((x)&0xFFFF)<<0|0x200000)
+#define MCF_FEC_FECTFCR_TXW_MASK             (0x240000)
+#define MCF_FEC_FECTFCR_OF_MSK               (0x280000)
+#define MCF_FEC_FECTFCR_UF_MSK               (0x300000)
+#define MCF_FEC_FECTFCR_FAE_MSK              (0x600000)
+#define MCF_FEC_FECTFCR_IP_MSK               (0xA00000)
+#define MCF_FEC_FECTFCR_GR(x)                (((x)&0x7)<<0x18|0x200000)
+#define MCF_FEC_FECTFCR_FRMEN                (0x8200000)
+#define MCF_FEC_FECTFCR_TIMER                (0x10200000)
+#define MCF_FEC_FECTFCR_WFR                  (0x20200000)
+#define MCF_FEC_FECTFCR_WCTL                 (0x40200000)
+
+/* Bit definitions and macros for MCF_FEC_FECTLRFP */
+#define MCF_FEC_FECTLRFP_LRFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTLWFP */
+#define MCF_FEC_FECTLWFP_LWFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFAR */
+#define MCF_FEC_FECTFAR_ALARM(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFRP */
+#define MCF_FEC_FECTFRP_READ(x)              (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFWP */
+#define MCF_FEC_FECTFWP_WRITE(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECFRST */
+#define MCF_FEC_FECFRST_RST_CTL              (0x1000000)
+#define MCF_FEC_FECFRST_SW_RST               (0x2000000)
+
+/* Bit definitions and macros for MCF_FEC_FECCTCWR */
+#define MCF_FEC_FECCTCWR_TFCW                (0x1000000)
+#define MCF_FEC_FECCTCWR_CRC                 (0x2000000)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */
+#define MCF_FEC_RMON_T_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */
+#define MCF_FEC_RMON_T_PACKETS_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */
+#define MCF_FEC_RMON_T_BC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */
+#define MCF_FEC_RMON_T_MC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */
+#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */
+#define MCF_FEC_RMON_T_UNDERSIZE_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */
+#define MCF_FEC_RMON_T_OVERSIZE_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */
+#define MCF_FEC_RMON_T_FRAG_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */
+#define MCF_FEC_RMON_T_JAB_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_COL */
+#define MCF_FEC_RMON_T_COL_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */
+#define MCF_FEC_RMON_T_P64_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */
+#define MCF_FEC_RMON_T_P65TO127_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */
+#define MCF_FEC_RMON_T_P128TO255_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */
+#define MCF_FEC_RMON_T_P256TO511_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */
+#define MCF_FEC_RMON_T_P512TO1023_Value(x)   (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */
+#define MCF_FEC_RMON_T_P1024TO2047_Value(x)  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */
+#define MCF_FEC_RMON_T_P_GTE2048_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */
+#define MCF_FEC_RMON_T_OCTETS_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */
+#define MCF_FEC_IEEE_T_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */
+#define MCF_FEC_IEEE_T_FRAME_OK_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */
+#define MCF_FEC_IEEE_T_1COL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */
+#define MCF_FEC_IEEE_T_MCOL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */
+#define MCF_FEC_IEEE_T_DEF_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */
+#define MCF_FEC_IEEE_T_LCOL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */
+#define MCF_FEC_IEEE_T_EXCOL_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */
+#define MCF_FEC_IEEE_T_MACERR_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */
+#define MCF_FEC_IEEE_T_CSERR_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */
+#define MCF_FEC_IEEE_T_SQE_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */
+#define MCF_FEC_IEEE_T_FDXFC_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */
+#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_DROP */
+#define MCF_FEC_RMON_R_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */
+#define MCF_FEC_RMON_R_PACKETS_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */
+#define MCF_FEC_RMON_R_BC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */
+#define MCF_FEC_RMON_R_MC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */
+#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */
+#define MCF_FEC_RMON_R_UNDERSIZE_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */
+#define MCF_FEC_RMON_R_OVERSIZE_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */
+#define MCF_FEC_RMON_R_FRAG_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */
+#define MCF_FEC_RMON_R_JAB_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */
+#define MCF_FEC_RMON_R_RESVD_0_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */
+#define MCF_FEC_RMON_R_P64_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */
+#define MCF_FEC_RMON_R_P65TO127_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */
+#define MCF_FEC_RMON_R_P128TO255_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */
+#define MCF_FEC_RMON_R_P256TO511_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */
+#define MCF_FEC_RMON_R_P512TO1023_Value(x)   (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */
+#define MCF_FEC_RMON_R_P1024TO2047_Value(x)  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */
+#define MCF_FEC_RMON_R_P_GTE2048_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */
+#define MCF_FEC_RMON_R_OCTETS_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */
+#define MCF_FEC_IEEE_R_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */
+#define MCF_FEC_IEEE_R_FRAME_OK_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */
+#define MCF_FEC_IEEE_R_CRC_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */
+#define MCF_FEC_IEEE_R_ALIGN_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */
+#define MCF_FEC_IEEE_R_MACERR_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */
+#define MCF_FEC_IEEE_R_FDXFC_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */
+#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+
+#endif /* __MCF5475_FEC_H__ */
--- a/tos/fpga_test/include/MCF5475_GPIO.h
+++ b/tos/fpga_test/include/MCF5475_GPIO.h
@@ -0,0 +1,543 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_GPIO_H__
+#define __MCF5475_GPIO_H__
+
+
+/*********************************************************************
+*
+* General Purpose I/O (GPIO)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPIO_PODR_FBCTL                  (*(volatile uint8_t *)(&_MBAR[0xA00]))
+#define MCF_GPIO_PDDR_FBCTL                  (*(volatile uint8_t *)(&_MBAR[0xA10]))
+#define MCF_GPIO_PPDSDR_FBCTL                (*(volatile uint8_t *)(&_MBAR[0xA20]))
+#define MCF_GPIO_PCLRR_FBCTL                 (*(volatile uint8_t *)(&_MBAR[0xA30]))
+
+#define MCF_GPIO_PODR_FBCS                   (*(volatile uint8_t *)(&_MBAR[0xA01]))
+#define MCF_GPIO_PDDR_FBCS                   (*(volatile uint8_t *)(&_MBAR[0xA11]))
+#define MCF_GPIO_PPDSDR_FBCS                 (*(volatile uint8_t *)(&_MBAR[0xA21]))
+#define MCF_GPIO_PCLRR_FBCS                  (*(volatile uint8_t *)(&_MBAR[0xA31]))
+
+#define MCF_GPIO_PODR_DMA                    (*(volatile uint8_t *)(&_MBAR[0xA02]))
+#define MCF_GPIO_PDDR_DMA                    (*(volatile uint8_t *)(&_MBAR[0xA12]))
+#define MCF_GPIO_PPDSDR_DMA                  (*(volatile uint8_t *)(&_MBAR[0xA22]))
+#define MCF_GPIO_PCLRR_DMA                   (*(volatile uint8_t *)(&_MBAR[0xA32]))
+
+#define MCF_GPIO_PODR_FEC0H                  (*(volatile uint8_t *)(&_MBAR[0xA04]))
+#define MCF_GPIO_PDDR_FEC0H                  (*(volatile uint8_t *)(&_MBAR[0xA14]))
+#define MCF_GPIO_PPDSDR_FEC0H                (*(volatile uint8_t *)(&_MBAR[0xA24]))
+#define MCF_GPIO_PCLRR_FEC0H                 (*(volatile uint8_t *)(&_MBAR[0xA34]))
+
+#define MCF_GPIO_PODR_FEC0L                  (*(volatile uint8_t *)(&_MBAR[0xA05]))
+#define MCF_GPIO_PDDR_FEC0L                  (*(volatile uint8_t *)(&_MBAR[0xA15]))
+#define MCF_GPIO_PPDSDR_FEC0L                (*(volatile uint8_t *)(&_MBAR[0xA25]))
+#define MCF_GPIO_PCLRR_FEC0L                 (*(volatile uint8_t *)(&_MBAR[0xA35]))
+
+#define MCF_GPIO_PODR_FEC1H                  (*(volatile uint8_t *)(&_MBAR[0xA06]))
+#define MCF_GPIO_PDDR_FEC1H                  (*(volatile uint8_t *)(&_MBAR[0xA16]))
+#define MCF_GPIO_PPDSDR_FEC1H                (*(volatile uint8_t *)(&_MBAR[0xA26]))
+#define MCF_GPIO_PCLRR_FEC1H                 (*(volatile uint8_t *)(&_MBAR[0xA36]))
+
+#define MCF_GPIO_PODR_FEC1L                  (*(volatile uint8_t *)(&_MBAR[0xA07]))
+#define MCF_GPIO_PDDR_FEC1L                  (*(volatile uint8_t *)(&_MBAR[0xA17]))
+#define MCF_GPIO_PPDSDR_FEC1L                (*(volatile uint8_t *)(&_MBAR[0xA27]))
+#define MCF_GPIO_PCLRR_FEC1L                 (*(volatile uint8_t *)(&_MBAR[0xA37]))
+
+#define MCF_GPIO_PODR_FECI2C                 (*(volatile uint8_t *)(&_MBAR[0xA08]))
+#define MCF_GPIO_PDDR_FECI2C                 (*(volatile uint8_t *)(&_MBAR[0xA18]))
+#define MCF_GPIO_PPDSDR_FECI2C               (*(volatile uint8_t *)(&_MBAR[0xA28]))
+#define MCF_GPIO_PCLRR_FECI2C                (*(volatile uint8_t *)(&_MBAR[0xA38]))
+
+#define MCF_GPIO_PODR_PCIBG                  (*(volatile uint8_t *)(&_MBAR[0xA09]))
+#define MCF_GPIO_PDDR_PCIBG                  (*(volatile uint8_t *)(&_MBAR[0xA19]))
+#define MCF_GPIO_PPDSDR_PCIBG                (*(volatile uint8_t *)(&_MBAR[0xA29]))
+#define MCF_GPIO_PCLRR_PCIBG                 (*(volatile uint8_t *)(&_MBAR[0xA39]))
+
+#define MCF_GPIO_PODR_PCIBR                  (*(volatile uint8_t *)(&_MBAR[0xA0A]))
+#define MCF_GPIO_PDDR_PCIBR                  (*(volatile uint8_t *)(&_MBAR[0xA1A]))
+#define MCF_GPIO_PPDSDR_PCIBR                (*(volatile uint8_t *)(&_MBAR[0xA2A]))
+#define MCF_GPIO_PCLRR_PCIBR                 (*(volatile uint8_t *)(&_MBAR[0xA3A]))
+
+#define MCF_GPIO2_PODR_PSC3PSC               (*(volatile uint8_t *)(&_MBAR[0xA0C]))
+#define MCF_GPIO2_PDDR_PSC3PSC               (*(volatile uint8_t *)(&_MBAR[0xA1C]))
+#define MCF_GPIO2_PPDSDR_PSC3PSC             (*(volatile uint8_t *)(&_MBAR[0xA2C]))
+#define MCF_GPIO2_PCLRR_PSC3PSC              (*(volatile uint8_t *)(&_MBAR[0xA3C]))
+
+#define MCF_GPIO0_PODR_PSC1PSC               (*(volatile uint8_t *)(&_MBAR[0xA0D]))
+#define MCF_GPIO0_PDDR_PSC1PSC               (*(volatile uint8_t *)(&_MBAR[0xA1D]))
+#define MCF_GPIO0_PPDSDR_PSC1PSC             (*(volatile uint8_t *)(&_MBAR[0xA2D]))
+#define MCF_GPIO0_PCLRR_PSC1PSC              (*(volatile uint8_t *)(&_MBAR[0xA3D]))
+
+#define MCF_GPIO_PODR_DSPI                   (*(volatile uint8_t *)(&_MBAR[0xA0E]))
+#define MCF_GPIO_PDDR_DSPI                   (*(volatile uint8_t *)(&_MBAR[0xA1E]))
+#define MCF_GPIO_PPDSDR_DSPI                 (*(volatile uint8_t *)(&_MBAR[0xA2E]))
+#define MCF_GPIO_PCLRR_DSPI                  (*(volatile uint8_t *)(&_MBAR[0xA3E]))
+
+
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0      (0x1)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1      (0x2)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2      (0x4)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3      (0x8)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4      (0x10)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5      (0x20)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6      (0x40)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0      (0x1)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1      (0x2)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2      (0x4)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3      (0x8)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4      (0x10)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5      (0x20)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6      (0x40)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0  (0x1)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1  (0x2)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2  (0x4)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3  (0x8)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4  (0x10)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5  (0x20)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6  (0x40)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0    (0x1)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1    (0x2)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2    (0x4)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3    (0x8)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4    (0x10)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5    (0x20)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6    (0x40)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS1        (0x2)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS2        (0x4)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS3        (0x8)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS4        (0x10)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS5        (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1        (0x2)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2        (0x4)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3        (0x8)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4        (0x10)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5        (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1    (0x2)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2    (0x4)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3    (0x8)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4    (0x10)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5    (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1      (0x2)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2      (0x4)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3      (0x8)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4      (0x10)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5      (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_DMA */
+#define MCF_GPIO_PODR_DMA_PODR_DMA0          (0x1)
+#define MCF_GPIO_PODR_DMA_PODR_DMA1          (0x2)
+#define MCF_GPIO_PODR_DMA_PODR_DMA2          (0x4)
+#define MCF_GPIO_PODR_DMA_PODR_DMA3          (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA0          (0x1)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA1          (0x2)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA2          (0x4)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA3          (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0      (0x1)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1      (0x2)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2      (0x4)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3      (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0        (0x1)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1        (0x2)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2        (0x4)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3        (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0      (0x1)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1      (0x2)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2      (0x4)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3      (0x8)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4      (0x10)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5      (0x20)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6      (0x40)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0      (0x1)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1      (0x2)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2      (0x4)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3      (0x8)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4      (0x10)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5      (0x20)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6      (0x40)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0    (0x1)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1    (0x2)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2    (0x4)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3    (0x8)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4    (0x10)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5    (0x20)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6    (0x40)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0      (0x1)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1      (0x2)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2      (0x4)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3      (0x8)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4      (0x10)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5      (0x20)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6      (0x40)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0      (0x1)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1      (0x2)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2      (0x4)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3      (0x8)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4      (0x10)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5      (0x20)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6      (0x40)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0    (0x1)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1    (0x2)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2    (0x4)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3    (0x8)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4    (0x10)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5    (0x20)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6    (0x40)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0      (0x1)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1      (0x2)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2      (0x4)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3      (0x8)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4      (0x10)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5      (0x20)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6      (0x40)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0      (0x1)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1      (0x2)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2      (0x4)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3      (0x8)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4      (0x10)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5      (0x20)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6      (0x40)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0    (0x1)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1    (0x2)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2    (0x4)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3    (0x8)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4    (0x10)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5    (0x20)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6    (0x40)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0      (0x1)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1      (0x2)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2      (0x4)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3      (0x8)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4      (0x10)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5      (0x20)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6      (0x40)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0      (0x1)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1      (0x2)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2      (0x4)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3      (0x8)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4      (0x10)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5      (0x20)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6      (0x40)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0    (0x1)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1    (0x2)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2    (0x4)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3    (0x8)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4    (0x10)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5    (0x20)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6    (0x40)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0    (0x1)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1    (0x2)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2    (0x4)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3    (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0    (0x1)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1    (0x2)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2    (0x4)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3    (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0  (0x1)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1  (0x2)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2  (0x4)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3  (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0      (0x1)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1      (0x2)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2      (0x4)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3      (0x8)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0      (0x1)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1      (0x2)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2      (0x4)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3      (0x8)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0  (0x1)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1  (0x2)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2  (0x4)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3  (0x8)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4  (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0    (0x1)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1    (0x2)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2    (0x4)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3    (0x8)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4    (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0      (0x1)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1      (0x2)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2      (0x4)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3      (0x8)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0      (0x1)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1      (0x2)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2      (0x4)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3      (0x8)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0  (0x1)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1  (0x2)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2  (0x4)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3  (0x8)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4  (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0    (0x1)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1    (0x2)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2    (0x4)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3    (0x8)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4    (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI0        (0x1)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI1        (0x2)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI2        (0x4)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI3        (0x8)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI4        (0x10)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI5        (0x20)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI6        (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0        (0x1)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1        (0x2)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2        (0x4)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3        (0x8)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4        (0x10)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5        (0x20)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6        (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0    (0x1)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1    (0x2)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2    (0x4)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3    (0x8)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4    (0x10)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5    (0x20)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6    (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0      (0x1)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1      (0x2)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2      (0x4)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3      (0x8)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4      (0x10)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5      (0x20)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6      (0x40)
+
+
+#endif /* __MCF5475_GPIO_H__ */
--- a/tos/fpga_test/include/MCF5475_GPT.h
+++ b/tos/fpga_test/include/MCF5475_GPT.h
@@ -0,0 +1,100 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_GPT_H__
+#define __MCF5475_GPT_H__
+
+
+/*********************************************************************
+*
+* General Purpose Timers (GPT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPT0_GMS                         (*(volatile uint32_t*)(&_MBAR[0x800]))
+#define MCF_GPT0_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x804]))
+#define MCF_GPT0_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x808]))
+#define MCF_GPT0_GSR                         (*(volatile uint32_t*)(&_MBAR[0x80C]))
+
+#define MCF_GPT1_GMS                         (*(volatile uint32_t*)(&_MBAR[0x810]))
+#define MCF_GPT1_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x814]))
+#define MCF_GPT1_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x818]))
+#define MCF_GPT1_GSR                         (*(volatile uint32_t*)(&_MBAR[0x81C]))
+
+#define MCF_GPT2_GMS                         (*(volatile uint32_t*)(&_MBAR[0x820]))
+#define MCF_GPT2_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x824]))
+#define MCF_GPT2_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x828]))
+#define MCF_GPT2_GSR                         (*(volatile uint32_t*)(&_MBAR[0x82C]))
+
+#define MCF_GPT3_GMS                         (*(volatile uint32_t*)(&_MBAR[0x830]))
+#define MCF_GPT3_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x834]))
+#define MCF_GPT3_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x838]))
+#define MCF_GPT3_GSR                         (*(volatile uint32_t*)(&_MBAR[0x83C]))
+
+#define MCF_GPT_GMS(x)                       (*(volatile uint32_t*)(&_MBAR[0x800 + ((x)*0x10)]))
+#define MCF_GPT_GCIR(x)                      (*(volatile uint32_t*)(&_MBAR[0x804 + ((x)*0x10)]))
+#define MCF_GPT_GPWM(x)                      (*(volatile uint32_t*)(&_MBAR[0x808 + ((x)*0x10)]))
+#define MCF_GPT_GSR(x)                       (*(volatile uint32_t*)(&_MBAR[0x80C + ((x)*0x10)]))
+
+
+/* Bit definitions and macros for MCF_GPT_GMS */
+#define MCF_GPT_GMS_TMS(x)                   (((x)&0x7)<<0)
+#define MCF_GPT_GMS_TMS_DISABLE              (0)
+#define MCF_GPT_GMS_TMS_INCAPT               (0x1)
+#define MCF_GPT_GMS_TMS_OUTCAPT              (0x2)
+#define MCF_GPT_GMS_TMS_PWM                  (0x3)
+#define MCF_GPT_GMS_TMS_GPIO                 (0x4)
+#define MCF_GPT_GMS_GPIO(x)                  (((x)&0x3)<<0x4)
+#define MCF_GPT_GMS_GPIO_INPUT               (0)
+#define MCF_GPT_GMS_GPIO_OUTLO               (0x20)
+#define MCF_GPT_GMS_GPIO_OUTHI               (0x30)
+#define MCF_GPT_GMS_IEN                      (0x100)
+#define MCF_GPT_GMS_OD                       (0x200)
+#define MCF_GPT_GMS_SC                       (0x400)
+#define MCF_GPT_GMS_CE                       (0x1000)
+#define MCF_GPT_GMS_WDEN                     (0x8000)
+#define MCF_GPT_GMS_ICT(x)                   (((x)&0x3)<<0x10)
+#define MCF_GPT_GMS_ICT_ANY                  (0)
+#define MCF_GPT_GMS_ICT_RISE                 (0x10000)
+#define MCF_GPT_GMS_ICT_FALL                 (0x20000)
+#define MCF_GPT_GMS_ICT_PULSE                (0x30000)
+#define MCF_GPT_GMS_OCT(x)                   (((x)&0x3)<<0x14)
+#define MCF_GPT_GMS_OCT_FRCLOW               (0)
+#define MCF_GPT_GMS_OCT_PULSEHI              (0x100000)
+#define MCF_GPT_GMS_OCT_PULSELO              (0x200000)
+#define MCF_GPT_GMS_OCT_TOGGLE               (0x300000)
+#define MCF_GPT_GMS_OCPW(x)                  (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_GPT_GCIR */
+#define MCF_GPT_GCIR_CNT(x)                  (((x)&0xFFFF)<<0)
+#define MCF_GPT_GCIR_PRE(x)                  (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_GPT_GPWM */
+#define MCF_GPT_GPWM_LOAD                    (0x1)
+#define MCF_GPT_GPWM_PWMOP                   (0x100)
+#define MCF_GPT_GPWM_WIDTH(x)                (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_GPT_GSR */
+#define MCF_GPT_GSR_CAPT                     (0x1)
+#define MCF_GPT_GSR_COMP                     (0x2)
+#define MCF_GPT_GSR_PWMP                     (0x4)
+#define MCF_GPT_GSR_TEXP                     (0x8)
+#define MCF_GPT_GSR_PIN                      (0x100)
+#define MCF_GPT_GSR_OVF(x)                   (((x)&0x7)<<0xC)
+#define MCF_GPT_GSR_CAPTURE(x)               (((x)&0xFFFF)<<0x10)
+
+
+#endif /* __MCF5475_GPT_H__ */
--- a/tos/fpga_test/include/MCF5475_I2C.h
+++ b/tos/fpga_test/include/MCF5475_I2C.h
@@ -0,0 +1,69 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_I2C_H__
+#define __MCF5475_I2C_H__
+
+
+/*********************************************************************
+*
+* I2C Module (I2C)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_I2C_I2ADR                        (*(volatile uint8_t *)(&_MBAR[0x8F00]))
+#define MCF_I2C_I2FDR                        (*(volatile uint8_t *)(&_MBAR[0x8F04]))
+#define MCF_I2C_I2CR                         (*(volatile uint8_t *)(&_MBAR[0x8F08]))
+#define MCF_I2C_I2SR                         (*(volatile uint8_t *)(&_MBAR[0x8F0C]))
+#define MCF_I2C_I2DR                         (*(volatile uint8_t *)(&_MBAR[0x8F10]))
+#define MCF_I2C_I2ICR                        (*(volatile uint8_t *)(&_MBAR[0x8F20]))
+
+
+
+/* Bit definitions and macros for MCF_I2C_I2ADR */
+#define MCF_I2C_I2ADR_ADR(x)                 (((x)&0x7F)<<0x1)
+
+/* Bit definitions and macros for MCF_I2C_I2FDR */
+#define MCF_I2C_I2FDR_IC(x)                  (((x)&0x3F)<<0)
+
+/* Bit definitions and macros for MCF_I2C_I2CR */
+#define MCF_I2C_I2CR_RSTA                    (0x4)
+#define MCF_I2C_I2CR_TXAK                    (0x8)
+#define MCF_I2C_I2CR_MTX                     (0x10)
+#define MCF_I2C_I2CR_MSTA                    (0x20)
+#define MCF_I2C_I2CR_IIEN                    (0x40)
+#define MCF_I2C_I2CR_IEN                     (0x80)
+
+/* Bit definitions and macros for MCF_I2C_I2SR */
+#define MCF_I2C_I2SR_RXAK                    (0x1)
+#define MCF_I2C_I2SR_IIF                     (0x2)
+#define MCF_I2C_I2SR_SRW                     (0x4)
+#define MCF_I2C_I2SR_IAL                     (0x10)
+#define MCF_I2C_I2SR_IBB                     (0x20)
+#define MCF_I2C_I2SR_IAAS                    (0x40)
+#define MCF_I2C_I2SR_ICF                     (0x80)
+
+/* Bit definitions and macros for MCF_I2C_I2DR */
+#define MCF_I2C_I2DR_DATA(x)                 (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_I2C_I2ICR */
+#define MCF_I2C_I2ICR_IE                     (0x1)
+#define MCF_I2C_I2ICR_RE                     (0x2)
+#define MCF_I2C_I2ICR_TE                     (0x4)
+#define MCF_I2C_I2ICR_BNBE                   (0x8)
+
+
+#endif /* __MCF5475_I2C_H__ */
--- a/tos/fpga_test/include/MCF5475_INTC.h
+++ b/tos/fpga_test/include/MCF5475_INTC.h
@@ -0,0 +1,331 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_INTC_H__
+#define __MCF5475_INTC_H__
+
+
+/*********************************************************************
+*
+* Interrupt Controller (INTC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_INTC_IPRH                        (*(volatile uint32_t*)(&_MBAR[0x700]))
+#define MCF_INTC_IPRL                        (*(volatile uint32_t*)(&_MBAR[0x704]))
+#define MCF_INTC_IMRH                        (*(volatile uint32_t*)(&_MBAR[0x708]))
+#define MCF_INTC_IMRL                        (*(volatile uint32_t*)(&_MBAR[0x70C]))
+#define MCF_INTC_INTFRCH                     (*(volatile uint32_t*)(&_MBAR[0x710]))
+#define MCF_INTC_INTFRCL                     (*(volatile uint32_t*)(&_MBAR[0x714]))
+#define MCF_INTC_IRLR                        (*(volatile uint8_t *)(&_MBAR[0x718]))
+#define MCF_INTC_IACKLPR                     (*(volatile uint8_t *)(&_MBAR[0x719]))
+#define MCF_INTC_ICR01                       (*(volatile uint8_t *)(&_MBAR[0x741]))
+#define MCF_INTC_ICR02                       (*(volatile uint8_t *)(&_MBAR[0x742]))
+#define MCF_INTC_ICR03                       (*(volatile uint8_t *)(&_MBAR[0x743]))
+#define MCF_INTC_ICR04                       (*(volatile uint8_t *)(&_MBAR[0x744]))
+#define MCF_INTC_ICR05                       (*(volatile uint8_t *)(&_MBAR[0x745]))
+#define MCF_INTC_ICR06                       (*(volatile uint8_t *)(&_MBAR[0x746]))
+#define MCF_INTC_ICR07                       (*(volatile uint8_t *)(&_MBAR[0x747]))
+#define MCF_INTC_ICR08                       (*(volatile uint8_t *)(&_MBAR[0x748]))
+#define MCF_INTC_ICR09                       (*(volatile uint8_t *)(&_MBAR[0x749]))
+#define MCF_INTC_ICR10                       (*(volatile uint8_t *)(&_MBAR[0x74A]))
+#define MCF_INTC_ICR11                       (*(volatile uint8_t *)(&_MBAR[0x74B]))
+#define MCF_INTC_ICR12                       (*(volatile uint8_t *)(&_MBAR[0x74C]))
+#define MCF_INTC_ICR13                       (*(volatile uint8_t *)(&_MBAR[0x74D]))
+#define MCF_INTC_ICR14                       (*(volatile uint8_t *)(&_MBAR[0x74E]))
+#define MCF_INTC_ICR15                       (*(volatile uint8_t *)(&_MBAR[0x74F]))
+#define MCF_INTC_ICR16                       (*(volatile uint8_t *)(&_MBAR[0x750]))
+#define MCF_INTC_ICR17                       (*(volatile uint8_t *)(&_MBAR[0x751]))
+#define MCF_INTC_ICR18                       (*(volatile uint8_t *)(&_MBAR[0x752]))
+#define MCF_INTC_ICR19                       (*(volatile uint8_t *)(&_MBAR[0x753]))
+#define MCF_INTC_ICR20                       (*(volatile uint8_t *)(&_MBAR[0x754]))
+#define MCF_INTC_ICR21                       (*(volatile uint8_t *)(&_MBAR[0x755]))
+#define MCF_INTC_ICR22                       (*(volatile uint8_t *)(&_MBAR[0x756]))
+#define MCF_INTC_ICR23                       (*(volatile uint8_t *)(&_MBAR[0x757]))
+#define MCF_INTC_ICR24                       (*(volatile uint8_t *)(&_MBAR[0x758]))
+#define MCF_INTC_ICR25                       (*(volatile uint8_t *)(&_MBAR[0x759]))
+#define MCF_INTC_ICR26                       (*(volatile uint8_t *)(&_MBAR[0x75A]))
+#define MCF_INTC_ICR27                       (*(volatile uint8_t *)(&_MBAR[0x75B]))
+#define MCF_INTC_ICR28                       (*(volatile uint8_t *)(&_MBAR[0x75C]))
+#define MCF_INTC_ICR29                       (*(volatile uint8_t *)(&_MBAR[0x75D]))
+#define MCF_INTC_ICR30                       (*(volatile uint8_t *)(&_MBAR[0x75E]))
+#define MCF_INTC_ICR31                       (*(volatile uint8_t *)(&_MBAR[0x75F]))
+#define MCF_INTC_ICR32                       (*(volatile uint8_t *)(&_MBAR[0x760]))
+#define MCF_INTC_ICR33                       (*(volatile uint8_t *)(&_MBAR[0x761]))
+#define MCF_INTC_ICR34                       (*(volatile uint8_t *)(&_MBAR[0x762]))
+#define MCF_INTC_ICR35                       (*(volatile uint8_t *)(&_MBAR[0x763]))
+#define MCF_INTC_ICR36                       (*(volatile uint8_t *)(&_MBAR[0x764]))
+#define MCF_INTC_ICR37                       (*(volatile uint8_t *)(&_MBAR[0x765]))
+#define MCF_INTC_ICR38                       (*(volatile uint8_t *)(&_MBAR[0x766]))
+#define MCF_INTC_ICR39                       (*(volatile uint8_t *)(&_MBAR[0x767]))
+#define MCF_INTC_ICR40                       (*(volatile uint8_t *)(&_MBAR[0x768]))
+#define MCF_INTC_ICR41                       (*(volatile uint8_t *)(&_MBAR[0x769]))
+#define MCF_INTC_ICR42                       (*(volatile uint8_t *)(&_MBAR[0x76A]))
+#define MCF_INTC_ICR43                       (*(volatile uint8_t *)(&_MBAR[0x76B]))
+#define MCF_INTC_ICR44                       (*(volatile uint8_t *)(&_MBAR[0x76C]))
+#define MCF_INTC_ICR45                       (*(volatile uint8_t *)(&_MBAR[0x76D]))
+#define MCF_INTC_ICR46                       (*(volatile uint8_t *)(&_MBAR[0x76E]))
+#define MCF_INTC_ICR47                       (*(volatile uint8_t *)(&_MBAR[0x76F]))
+#define MCF_INTC_ICR48                       (*(volatile uint8_t *)(&_MBAR[0x770]))
+#define MCF_INTC_ICR49                       (*(volatile uint8_t *)(&_MBAR[0x771]))
+#define MCF_INTC_ICR50                       (*(volatile uint8_t *)(&_MBAR[0x772]))
+#define MCF_INTC_ICR51                       (*(volatile uint8_t *)(&_MBAR[0x773]))
+#define MCF_INTC_ICR52                       (*(volatile uint8_t *)(&_MBAR[0x774]))
+#define MCF_INTC_ICR53                       (*(volatile uint8_t *)(&_MBAR[0x775]))
+#define MCF_INTC_ICR54                       (*(volatile uint8_t *)(&_MBAR[0x776]))
+#define MCF_INTC_ICR55                       (*(volatile uint8_t *)(&_MBAR[0x777]))
+#define MCF_INTC_ICR56                       (*(volatile uint8_t *)(&_MBAR[0x778]))
+#define MCF_INTC_ICR57                       (*(volatile uint8_t *)(&_MBAR[0x779]))
+#define MCF_INTC_ICR58                       (*(volatile uint8_t *)(&_MBAR[0x77A]))
+#define MCF_INTC_ICR59                       (*(volatile uint8_t *)(&_MBAR[0x77B]))
+#define MCF_INTC_ICR60                       (*(volatile uint8_t *)(&_MBAR[0x77C]))
+#define MCF_INTC_ICR61                       (*(volatile uint8_t *)(&_MBAR[0x77D]))
+#define MCF_INTC_ICR62                       (*(volatile uint8_t *)(&_MBAR[0x77E]))
+#define MCF_INTC_ICR63                       (*(volatile uint8_t *)(&_MBAR[0x77F]))
+#define MCF_INTC_SWIACK                      (*(volatile uint8_t *)(&_MBAR[0x7E0]))
+#define MCF_INTC_L1IACK                      (*(volatile uint8_t *)(&_MBAR[0x7E4]))
+#define MCF_INTC_L2IACK                      (*(volatile uint8_t *)(&_MBAR[0x7E8]))
+#define MCF_INTC_L3IACK                      (*(volatile uint8_t *)(&_MBAR[0x7EC]))
+#define MCF_INTC_L4IACK                      (*(volatile uint8_t *)(&_MBAR[0x7F0]))
+#define MCF_INTC_L5IACK                      (*(volatile uint8_t *)(&_MBAR[0x7F4]))
+#define MCF_INTC_L6IACK                      (*(volatile uint8_t *)(&_MBAR[0x7F8]))
+#define MCF_INTC_L7IACK                      (*(volatile uint8_t *)(&_MBAR[0x7FC]))
+#define MCF_INTC_ICR(x)                      (*(volatile uint8_t *)(&_MBAR[0x741 + ((x-1)*0x1)]))
+#define MCF_INTC_LIACK(x)                    (*(volatile uint8_t *)(&_MBAR[0x7E4 + ((x-1)*0x4)]))
+
+
+
+/* Bit definitions and macros for MCF_INTC_IPRH */
+#define MCF_INTC_IPRH_INT32                  (0x1)
+#define MCF_INTC_IPRH_INT33                  (0x2)
+#define MCF_INTC_IPRH_INT34                  (0x4)
+#define MCF_INTC_IPRH_INT35                  (0x8)
+#define MCF_INTC_IPRH_INT36                  (0x10)
+#define MCF_INTC_IPRH_INT37                  (0x20)
+#define MCF_INTC_IPRH_INT38                  (0x40)
+#define MCF_INTC_IPRH_INT39                  (0x80)
+#define MCF_INTC_IPRH_INT40                  (0x100)
+#define MCF_INTC_IPRH_INT41                  (0x200)
+#define MCF_INTC_IPRH_INT42                  (0x400)
+#define MCF_INTC_IPRH_INT43                  (0x800)
+#define MCF_INTC_IPRH_INT44                  (0x1000)
+#define MCF_INTC_IPRH_INT45                  (0x2000)
+#define MCF_INTC_IPRH_INT46                  (0x4000)
+#define MCF_INTC_IPRH_INT47                  (0x8000)
+#define MCF_INTC_IPRH_INT48                  (0x10000)
+#define MCF_INTC_IPRH_INT49                  (0x20000)
+#define MCF_INTC_IPRH_INT50                  (0x40000)
+#define MCF_INTC_IPRH_INT51                  (0x80000)
+#define MCF_INTC_IPRH_INT52                  (0x100000)
+#define MCF_INTC_IPRH_INT53                  (0x200000)
+#define MCF_INTC_IPRH_INT54                  (0x400000)
+#define MCF_INTC_IPRH_INT55                  (0x800000)
+#define MCF_INTC_IPRH_INT56                  (0x1000000)
+#define MCF_INTC_IPRH_INT57                  (0x2000000)
+#define MCF_INTC_IPRH_INT58                  (0x4000000)
+#define MCF_INTC_IPRH_INT59                  (0x8000000)
+#define MCF_INTC_IPRH_INT60                  (0x10000000)
+#define MCF_INTC_IPRH_INT61                  (0x20000000)
+#define MCF_INTC_IPRH_INT62                  (0x40000000)
+#define MCF_INTC_IPRH_INT63                  (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IPRL */
+#define MCF_INTC_IPRL_INT1                   (0x2)
+#define MCF_INTC_IPRL_INT2                   (0x4)
+#define MCF_INTC_IPRL_INT3                   (0x8)
+#define MCF_INTC_IPRL_INT4                   (0x10)
+#define MCF_INTC_IPRL_INT5                   (0x20)
+#define MCF_INTC_IPRL_INT6                   (0x40)
+#define MCF_INTC_IPRL_INT7                   (0x80)
+#define MCF_INTC_IPRL_INT8                   (0x100)
+#define MCF_INTC_IPRL_INT9                   (0x200)
+#define MCF_INTC_IPRL_INT10                  (0x400)
+#define MCF_INTC_IPRL_INT11                  (0x800)
+#define MCF_INTC_IPRL_INT12                  (0x1000)
+#define MCF_INTC_IPRL_INT13                  (0x2000)
+#define MCF_INTC_IPRL_INT14                  (0x4000)
+#define MCF_INTC_IPRL_INT15                  (0x8000)
+#define MCF_INTC_IPRL_INT16                  (0x10000)
+#define MCF_INTC_IPRL_INT17                  (0x20000)
+#define MCF_INTC_IPRL_INT18                  (0x40000)
+#define MCF_INTC_IPRL_INT19                  (0x80000)
+#define MCF_INTC_IPRL_INT20                  (0x100000)
+#define MCF_INTC_IPRL_INT21                  (0x200000)
+#define MCF_INTC_IPRL_INT22                  (0x400000)
+#define MCF_INTC_IPRL_INT23                  (0x800000)
+#define MCF_INTC_IPRL_INT24                  (0x1000000)
+#define MCF_INTC_IPRL_INT25                  (0x2000000)
+#define MCF_INTC_IPRL_INT26                  (0x4000000)
+#define MCF_INTC_IPRL_INT27                  (0x8000000)
+#define MCF_INTC_IPRL_INT28                  (0x10000000)
+#define MCF_INTC_IPRL_INT29                  (0x20000000)
+#define MCF_INTC_IPRL_INT30                  (0x40000000)
+#define MCF_INTC_IPRL_INT31                  (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IMRH */
+#define MCF_INTC_IMRH_INT_MASK32             (0x1)
+#define MCF_INTC_IMRH_INT_MASK33             (0x2)
+#define MCF_INTC_IMRH_INT_MASK34             (0x4)
+#define MCF_INTC_IMRH_INT_MASK35             (0x8)
+#define MCF_INTC_IMRH_INT_MASK36             (0x10)
+#define MCF_INTC_IMRH_INT_MASK37             (0x20)
+#define MCF_INTC_IMRH_INT_MASK38             (0x40)
+#define MCF_INTC_IMRH_INT_MASK39             (0x80)
+#define MCF_INTC_IMRH_INT_MASK40             (0x100)
+#define MCF_INTC_IMRH_INT_MASK41             (0x200)
+#define MCF_INTC_IMRH_INT_MASK42             (0x400)
+#define MCF_INTC_IMRH_INT_MASK43             (0x800)
+#define MCF_INTC_IMRH_INT_MASK44             (0x1000)
+#define MCF_INTC_IMRH_INT_MASK45             (0x2000)
+#define MCF_INTC_IMRH_INT_MASK46             (0x4000)
+#define MCF_INTC_IMRH_INT_MASK47             (0x8000)
+#define MCF_INTC_IMRH_INT_MASK48             (0x10000)
+#define MCF_INTC_IMRH_INT_MASK49             (0x20000)
+#define MCF_INTC_IMRH_INT_MASK50             (0x40000)
+#define MCF_INTC_IMRH_INT_MASK51             (0x80000)
+#define MCF_INTC_IMRH_INT_MASK52             (0x100000)
+#define MCF_INTC_IMRH_INT_MASK53             (0x200000)
+#define MCF_INTC_IMRH_INT_MASK54             (0x400000)
+#define MCF_INTC_IMRH_INT_MASK55             (0x800000)
+#define MCF_INTC_IMRH_INT_MASK56             (0x1000000)
+#define MCF_INTC_IMRH_INT_MASK57             (0x2000000)
+#define MCF_INTC_IMRH_INT_MASK58             (0x4000000)
+#define MCF_INTC_IMRH_INT_MASK59             (0x8000000)
+#define MCF_INTC_IMRH_INT_MASK60             (0x10000000)
+#define MCF_INTC_IMRH_INT_MASK61             (0x20000000)
+#define MCF_INTC_IMRH_INT_MASK62             (0x40000000)
+#define MCF_INTC_IMRH_INT_MASK63             (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IMRL */
+#define MCF_INTC_IMRL_MASKALL                (0x1)
+#define MCF_INTC_IMRL_INT_MASK1              (0x2)
+#define MCF_INTC_IMRL_INT_MASK2              (0x4)
+#define MCF_INTC_IMRL_INT_MASK3              (0x8)
+#define MCF_INTC_IMRL_INT_MASK4              (0x10)
+#define MCF_INTC_IMRL_INT_MASK5              (0x20)
+#define MCF_INTC_IMRL_INT_MASK6              (0x40)
+#define MCF_INTC_IMRL_INT_MASK7              (0x80)
+#define MCF_INTC_IMRL_INT_MASK8              (0x100)
+#define MCF_INTC_IMRL_INT_MASK9              (0x200)
+#define MCF_INTC_IMRL_INT_MASK10             (0x400)
+#define MCF_INTC_IMRL_INT_MASK11             (0x800)
+#define MCF_INTC_IMRL_INT_MASK12             (0x1000)
+#define MCF_INTC_IMRL_INT_MASK13             (0x2000)
+#define MCF_INTC_IMRL_INT_MASK14             (0x4000)
+#define MCF_INTC_IMRL_INT_MASK15             (0x8000)
+#define MCF_INTC_IMRL_INT_MASK16             (0x10000)
+#define MCF_INTC_IMRL_INT_MASK17             (0x20000)
+#define MCF_INTC_IMRL_INT_MASK18             (0x40000)
+#define MCF_INTC_IMRL_INT_MASK19             (0x80000)
+#define MCF_INTC_IMRL_INT_MASK20             (0x100000)
+#define MCF_INTC_IMRL_INT_MASK21             (0x200000)
+#define MCF_INTC_IMRL_INT_MASK22             (0x400000)
+#define MCF_INTC_IMRL_INT_MASK23             (0x800000)
+#define MCF_INTC_IMRL_INT_MASK24             (0x1000000)
+#define MCF_INTC_IMRL_INT_MASK25             (0x2000000)
+#define MCF_INTC_IMRL_INT_MASK26             (0x4000000)
+#define MCF_INTC_IMRL_INT_MASK27             (0x8000000)
+#define MCF_INTC_IMRL_INT_MASK28             (0x10000000)
+#define MCF_INTC_IMRL_INT_MASK29             (0x20000000)
+#define MCF_INTC_IMRL_INT_MASK30             (0x40000000)
+#define MCF_INTC_IMRL_INT_MASK31             (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_INTFRCH */
+#define MCF_INTC_INTFRCH_INTFRC32            (0x1)
+#define MCF_INTC_INTFRCH_INTFRC33            (0x2)
+#define MCF_INTC_INTFRCH_INTFRC34            (0x4)
+#define MCF_INTC_INTFRCH_INTFRC35            (0x8)
+#define MCF_INTC_INTFRCH_INTFRC36            (0x10)
+#define MCF_INTC_INTFRCH_INTFRC37            (0x20)
+#define MCF_INTC_INTFRCH_INTFRC38            (0x40)
+#define MCF_INTC_INTFRCH_INTFRC39            (0x80)
+#define MCF_INTC_INTFRCH_INTFRC40            (0x100)
+#define MCF_INTC_INTFRCH_INTFRC41            (0x200)
+#define MCF_INTC_INTFRCH_INTFRC42            (0x400)
+#define MCF_INTC_INTFRCH_INTFRC43            (0x800)
+#define MCF_INTC_INTFRCH_INTFRC44            (0x1000)
+#define MCF_INTC_INTFRCH_INTFRC45            (0x2000)
+#define MCF_INTC_INTFRCH_INTFRC46            (0x4000)
+#define MCF_INTC_INTFRCH_INTFRC47            (0x8000)
+#define MCF_INTC_INTFRCH_INTFRC48            (0x10000)
+#define MCF_INTC_INTFRCH_INTFRC49            (0x20000)
+#define MCF_INTC_INTFRCH_INTFRC50            (0x40000)
+#define MCF_INTC_INTFRCH_INTFRC51            (0x80000)
+#define MCF_INTC_INTFRCH_INTFRC52            (0x100000)
+#define MCF_INTC_INTFRCH_INTFRC53            (0x200000)
+#define MCF_INTC_INTFRCH_INTFRC54            (0x400000)
+#define MCF_INTC_INTFRCH_INTFRC55            (0x800000)
+#define MCF_INTC_INTFRCH_INTFRC56            (0x1000000)
+#define MCF_INTC_INTFRCH_INTFRC57            (0x2000000)
+#define MCF_INTC_INTFRCH_INTFRC58            (0x4000000)
+#define MCF_INTC_INTFRCH_INTFRC59            (0x8000000)
+#define MCF_INTC_INTFRCH_INTFRC60            (0x10000000)
+#define MCF_INTC_INTFRCH_INTFRC61            (0x20000000)
+#define MCF_INTC_INTFRCH_INTFRC62            (0x40000000)
+#define MCF_INTC_INTFRCH_INTFRC63            (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_INTFRCL */
+#define MCF_INTC_INTFRCL_INTFRC1             (0x2)
+#define MCF_INTC_INTFRCL_INTFRC2             (0x4)
+#define MCF_INTC_INTFRCL_INTFRC3             (0x8)
+#define MCF_INTC_INTFRCL_INTFRC4             (0x10)
+#define MCF_INTC_INTFRCL_INTFRC5             (0x20)
+#define MCF_INTC_INTFRCL_INTFRC6             (0x40)
+#define MCF_INTC_INTFRCL_INTFRC7             (0x80)
+#define MCF_INTC_INTFRCL_INTFRC8             (0x100)
+#define MCF_INTC_INTFRCL_INTFRC9             (0x200)
+#define MCF_INTC_INTFRCL_INTFRC10            (0x400)
+#define MCF_INTC_INTFRCL_INTFRC11            (0x800)
+#define MCF_INTC_INTFRCL_INTFRC12            (0x1000)
+#define MCF_INTC_INTFRCL_INTFRC13            (0x2000)
+#define MCF_INTC_INTFRCL_INTFRC14            (0x4000)
+#define MCF_INTC_INTFRCL_INTFRC15            (0x8000)
+#define MCF_INTC_INTFRCL_INTFRC16            (0x10000)
+#define MCF_INTC_INTFRCL_INTFRC17            (0x20000)
+#define MCF_INTC_INTFRCL_INTFRC18            (0x40000)
+#define MCF_INTC_INTFRCL_INTFRC19            (0x80000)
+#define MCF_INTC_INTFRCL_INTFRC20            (0x100000)
+#define MCF_INTC_INTFRCL_INTFRC21            (0x200000)
+#define MCF_INTC_INTFRCL_INTFRC22            (0x400000)
+#define MCF_INTC_INTFRCL_INTFRC23            (0x800000)
+#define MCF_INTC_INTFRCL_INTFRC24            (0x1000000)
+#define MCF_INTC_INTFRCL_INTFRC25            (0x2000000)
+#define MCF_INTC_INTFRCL_INTFRC26            (0x4000000)
+#define MCF_INTC_INTFRCL_INTFRC27            (0x8000000)
+#define MCF_INTC_INTFRCL_INTFRC28            (0x10000000)
+#define MCF_INTC_INTFRCL_INTFRC29            (0x20000000)
+#define MCF_INTC_INTFRCL_INTFRC30            (0x40000000)
+#define MCF_INTC_INTFRCL_INTFRC31            (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IRLR */
+#define MCF_INTC_IRLR_IRQ(x)                 (((x)&0x7F)<<0x1)
+
+/* Bit definitions and macros for MCF_INTC_IACKLPR */
+#define MCF_INTC_IACKLPR_PRI(x)              (((x)&0xF)<<0)
+#define MCF_INTC_IACKLPR_LEVEL(x)            (((x)&0x7)<<0x4)
+
+/* Bit definitions and macros for MCF_INTC_ICR */
+#define MCF_INTC_ICR_IP(x)                   (((x)&0x7)<<0)
+#define MCF_INTC_ICR_IL(x)                   (((x)&0x7)<<0x3)
+
+/* Bit definitions and macros for MCF_INTC_SWIACK */
+#define MCF_INTC_SWIACK_VECTOR(x)            (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_INTC_LIACK */
+#define MCF_INTC_LIACK_VECTOR(x)             (((x)&0xFF)<<0)
+
+
+#endif /* __MCF5475_INTC_H__ */
--- a/tos/fpga_test/include/MCF5475_MMU.h
+++ b/tos/fpga_test/include/MCF5475_MMU.h
@@ -0,0 +1,79 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_MMU_H__
+#define __MCF5475_MMU_H__
+
+
+/*********************************************************************
+*
+* Memory Management Unit (MMU)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+
+/* note the uint32_t_a - this is to avoid gcc warnings about pointer aliasing */
+#define MCF_MMU_MMUCR                        (*(volatile uint32_t_a*)(&_MMUBAR[0]))
+#define MCF_MMU_MMUOR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x4]))
+#define MCF_MMU_MMUSR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x8]))
+#define MCF_MMU_MMUAR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x10]))
+#define MCF_MMU_MMUTR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x14]))
+#define MCF_MMU_MMUDR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x18]))
+
+
+/* Bit definitions and macros for MCF_MMU_MMUCR */
+#define MCF_MMU_MMUCR_EN                     (0x1)
+#define MCF_MMU_MMUCR_ASM                    (0x2)
+
+/* Bit definitions and macros for MCF_MMU_MMUOR */
+#define MCF_MMU_MMUOR_UAA                    (0x1)
+#define MCF_MMU_MMUOR_ACC                    (0x2)
+#define MCF_MMU_MMUOR_RW                     (0x4)
+#define MCF_MMU_MMUOR_ADR                    (0x8)
+#define MCF_MMU_MMUOR_ITLB                   (0x10)
+#define MCF_MMU_MMUOR_CAS                    (0x20)
+#define MCF_MMU_MMUOR_CNL                    (0x40)
+#define MCF_MMU_MMUOR_CA                     (0x80)
+#define MCF_MMU_MMUOR_STLB                   (0x100)
+#define MCF_MMU_MMUOR_AA(x)                  (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_MMU_MMUSR */
+#define MCF_MMU_MMUSR_HIT                    (0x2)
+#define MCF_MMU_MMUSR_WF                     (0x8)
+#define MCF_MMU_MMUSR_RF                     (0x10)
+#define MCF_MMU_MMUSR_SPF                    (0x20)
+
+/* Bit definitions and macros for MCF_MMU_MMUAR */
+#define MCF_MMU_MMUAR_FA(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_MMU_MMUTR */
+#define MCF_MMU_MMUTR_V                      (0x1)
+#define MCF_MMU_MMUTR_SG                     (0x2)
+#define MCF_MMU_MMUTR_ID(x)                  (((x)&0xFF)<<0x2)
+#define MCF_MMU_MMUTR_VA(x)                  (((x)&0x3FFFFF)<<0xA)
+
+/* Bit definitions and macros for MCF_MMU_MMUDR */
+#define MCF_MMU_MMUDR_LK                     (0x2)
+#define MCF_MMU_MMUDR_X                      (0x4)
+#define MCF_MMU_MMUDR_W                      (0x8)
+#define MCF_MMU_MMUDR_R                      (0x10)
+#define MCF_MMU_MMUDR_SP                     (0x20)
+#define MCF_MMU_MMUDR_CM(x)                  (((x)&0x3)<<0x6)
+#define MCF_MMU_MMUDR_SZ(x)                  (((x)&0x3)<<0x8)
+#define MCF_MMU_MMUDR_PA(x)                  (((x)&0x3FFFFF)<<0xA)
+
+
+#endif /* __MCF5475_MMU_H__ */
--- a/tos/fpga_test/include/MCF5475_PAD.h
+++ b/tos/fpga_test/include/MCF5475_PAD.h
@@ -0,0 +1,233 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PAD_H__
+#define __MCF5475_PAD_H__
+
+
+/*********************************************************************
+*
+* Common GPIO
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PAD_PAR_FBCTL                    (*(volatile uint16_t*)(&_MBAR[0xA40]))
+#define MCF_PAD_PAR_FBCS                     (*(volatile uint8_t *)(&_MBAR[0xA42]))
+#define MCF_PAD_PAR_DMA                      (*(volatile uint8_t *)(&_MBAR[0xA43]))
+#define MCF_PAD_PAR_FECI2CIRQ                (*(volatile uint16_t*)(&_MBAR[0xA44]))
+#define MCF_PAD_PAR_PCIBG                    (*(volatile uint16_t*)(&_MBAR[0xA48]))
+#define MCF_PAD_PAR_PCIBR                    (*(volatile uint16_t*)(&_MBAR[0xA4A]))
+#define MCF_PAD_PAR_PSC3                     (*(volatile uint8_t *)(&_MBAR[0xA4C]))
+#define MCF_PAD_PAR_PSC2                     (*(volatile uint8_t *)(&_MBAR[0xA4D]))
+#define MCF_PAD_PAR_PSC1                     (*(volatile uint8_t *)(&_MBAR[0xA4E]))
+#define MCF_PAD_PAR_PSC0                     (*(volatile uint8_t *)(&_MBAR[0xA4F]))
+#define MCF_PAD_PAR_DSPI                     (*(volatile uint16_t*)(&_MBAR[0xA50]))
+#define MCF_PAD_PAR_TIMER                    (*(volatile uint8_t *)(&_MBAR[0xA52]))
+
+
+/* Bit definitions and macros for MCF_PAD_PAR_FBCTL */
+#define MCF_PAD_PAR_FBCTL_PAR_ALE(x)         (((x)&0x3)<<0)
+#define MCF_PAD_PAR_FBCTL_PAR_ALE_GPIO       (0)
+#define MCF_PAD_PAR_FBCTL_PAR_ALE_TBST       (0x2)
+#define MCF_PAD_PAR_FBCTL_PAR_ALE_ALE        (0x3)
+#define MCF_PAD_PAR_FBCTL_PAR_TA             (0x4)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB_GPIO       (0)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB_TBST       (0x20)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB_RW         (0x30)
+#define MCF_PAD_PAR_FBCTL_PAR_OE             (0x40)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE0           (0x100)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE1           (0x400)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE2           (0x1000)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE3           (0x4000)
+
+/* Bit definitions and macros for MCF_PAD_PAR_FBCS */
+#define MCF_PAD_PAR_FBCS_PAR_CS1             (0x2)
+#define MCF_PAD_PAR_FBCS_PAR_CS2             (0x4)
+#define MCF_PAD_PAR_FBCS_PAR_CS3             (0x8)
+#define MCF_PAD_PAR_FBCS_PAR_CS4             (0x10)
+#define MCF_PAD_PAR_FBCS_PAR_CS5             (0x20)
+
+/* Bit definitions and macros for MCF_PAD_PAR_DMA */
+#define MCF_PAD_PAR_DMA_PAR_DREQ0(x)         (((x)&0x3)<<0)
+#define MCF_PAD_PAR_DMA_PAR_DREQ0_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DREQ0_TIN0       (0x2)
+#define MCF_PAD_PAR_DMA_PAR_DREQ0_DREQ0      (0x3)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1(x)         (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_IRQ1       (0x4)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_TIN1       (0x8)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_DREQ1      (0xC)
+#define MCF_PAD_PAR_DMA_PAR_DACK0(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_DMA_PAR_DACK0_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DACK0_TOUT0      (0x20)
+#define MCF_PAD_PAR_DMA_PAR_DACK0_DACK0      (0x30)
+#define MCF_PAD_PAR_DMA_PAR_DACK1(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_DMA_PAR_DACK1_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DACK1_TOUT1      (0x80)
+#define MCF_PAD_PAR_DMA_PAR_DACK1_DACK1      (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_FECI2CIRQ */
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ5       (0x1)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ6       (0x2)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_SCL        (0x4)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_SDA        (0x8)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC(x)   (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_SCL  (0x80)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC (0xC0)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO(x)  (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x200)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO (0x300)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MII      (0x400)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E17        (0x800)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC      (0x1000)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO     (0x2000)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII      (0x4000)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E07        (0x8000)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PCIBG */
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0(x)      (((x)&0x3)<<0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_TOUT0   (0x2)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0  (0x3)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1(x)      (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_TOUT1   (0x8)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1  (0xC)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2(x)      (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_TOUT2   (0x20)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2  (0x30)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3(x)      (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_TOUT3   (0x80)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3  (0xC0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4(x)      (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST    (0x200)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4  (0x300)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PCIBR */
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0(x)      (((x)&0x3)<<0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_TIN0    (0x2)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0  (0x3)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1(x)      (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_TIN1    (0x8)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1  (0xC)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2(x)      (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_TIN2    (0x20)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2  (0x30)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3(x)      (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_TIN3    (0x80)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3  (0xC0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4(x)      (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4    (0x200)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4  (0x300)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC3 */
+#define MCF_PAD_PAR_PSC3_PAR_TXD3            (0x4)
+#define MCF_PAD_PAR_PSC3_PAR_RXD3            (0x8)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3_GPIO       (0)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3_RTS        (0x30)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3_GPIO       (0)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC2 */
+#define MCF_PAD_PAR_PSC2_PAR_TXD2            (0x4)
+#define MCF_PAD_PAR_PSC2_PAR_RXD2            (0x8)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2_GPIO       (0)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2_RTS        (0x30)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2_GPIO       (0)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC1 */
+#define MCF_PAD_PAR_PSC1_PAR_TXD1            (0x4)
+#define MCF_PAD_PAR_PSC1_PAR_RXD1            (0x8)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1_GPIO       (0)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1_RTS        (0x30)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1_GPIO       (0)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC0 */
+#define MCF_PAD_PAR_PSC0_PAR_TXD0            (0x4)
+#define MCF_PAD_PAR_PSC0_PAR_RXD0            (0x8)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0_GPIO       (0)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0_RTS        (0x30)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0_GPIO       (0)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_DSPI */
+#define MCF_PAD_PAR_DSPI_PAR_SOUT(x)         (((x)&0x3)<<0)
+#define MCF_PAD_PAR_DSPI_PAR_SOUT_GPIO       (0)
+#define MCF_PAD_PAR_DSPI_PAR_SOUT_TXD        (0x2)
+#define MCF_PAD_PAR_DSPI_PAR_SOUT_SOUT       (0x3)
+#define MCF_PAD_PAR_DSPI_PAR_SIN(x)          (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_DSPI_PAR_SIN_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_SIN_RXD         (0x8)
+#define MCF_PAD_PAR_DSPI_PAR_SIN_SIN         (0xC)
+#define MCF_PAD_PAR_DSPI_PAR_SCK(x)          (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_BCLK        (0x10)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_CTS         (0x20)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_SCK         (0x30)
+#define MCF_PAD_PAR_DSPI_PAR_CS0(x)          (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_FSYNC       (0x40)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_RTS         (0x80)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_DSPICS0     (0xC0)
+#define MCF_PAD_PAR_DSPI_PAR_CS2(x)          (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_DSPI_PAR_CS2_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_CS2_TOUT2       (0x200)
+#define MCF_PAD_PAR_DSPI_PAR_CS2_DSPICS2     (0x300)
+#define MCF_PAD_PAR_DSPI_PAR_CS3(x)          (((x)&0x3)<<0xA)
+#define MCF_PAD_PAR_DSPI_PAR_CS3_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_CS3_TOUT3       (0x800)
+#define MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3     (0xC00)
+#define MCF_PAD_PAR_DSPI_PAR_CS5             (0x1000)
+
+/* Bit definitions and macros for MCF_PAD_PAR_TIMER */
+#define MCF_PAD_PAR_TIMER_PAR_TOUT2          (0x1)
+#define MCF_PAD_PAR_TIMER_PAR_TIN2(x)        (((x)&0x3)<<0x1)
+#define MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2      (0x4)
+#define MCF_PAD_PAR_TIMER_PAR_TIN2_TIN2      (0x6)
+#define MCF_PAD_PAR_TIMER_PAR_TOUT3          (0x8)
+#define MCF_PAD_PAR_TIMER_PAR_TIN3(x)        (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_TIMER_PAR_TIN3_IRQ3      (0x20)
+#define MCF_PAD_PAR_TIMER_PAR_TIN3_TIN3      (0x30)
+
+
+#endif /* __MCF5475_PAD_H__ */
--- a/tos/fpga_test/include/MCF5475_PCI.h
+++ b/tos/fpga_test/include/MCF5475_PCI.h
@@ -0,0 +1,376 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PCI_H__
+#define __MCF5475_PCI_H__
+
+
+/*********************************************************************
+*
+* PCI Bus Controller (PCI)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PCI_PCIIDR                       (*(volatile uint32_t*)(&_MBAR[0xB00]))
+#define MCF_PCI_PCISCR                       (*(volatile uint32_t*)(&_MBAR[0xB04]))
+#define MCF_PCI_PCICCRIR                     (*(volatile uint32_t*)(&_MBAR[0xB08]))
+#define MCF_PCI_PCICR1                       (*(volatile uint32_t*)(&_MBAR[0xB0C]))
+#define MCF_PCI_PCIBAR0                      (*(volatile uint32_t*)(&_MBAR[0xB10]))
+#define MCF_PCI_PCIBAR1                      (*(volatile uint32_t*)(&_MBAR[0xB14]))
+#define MCF_PCI_PCICCPR                      (*(volatile uint32_t*)(&_MBAR[0xB28]))
+#define MCF_PCI_PCISID                       (*(volatile uint32_t*)(&_MBAR[0xB2C]))
+#define MCF_PCI_PCICR2                       (*(volatile uint32_t*)(&_MBAR[0xB3C]))
+#define MCF_PCI_PCIGSCR                      (*(volatile uint32_t*)(&_MBAR[0xB60]))
+#define MCF_PCI_PCITBATR0                    (*(volatile uint32_t*)(&_MBAR[0xB64]))
+#define MCF_PCI_PCITBATR1                    (*(volatile uint32_t*)(&_MBAR[0xB68]))
+#define MCF_PCI_PCITCR                       (*(volatile uint32_t*)(&_MBAR[0xB6C]))
+#define MCF_PCI_PCIIW0BTAR                   (*(volatile uint32_t*)(&_MBAR[0xB70]))
+#define MCF_PCI_PCIIW1BTAR                   (*(volatile uint32_t*)(&_MBAR[0xB74]))
+#define MCF_PCI_PCIIW2BTAR                   (*(volatile uint32_t*)(&_MBAR[0xB78]))
+#define MCF_PCI_PCIIWCR                      (*(volatile uint32_t*)(&_MBAR[0xB80]))
+#define MCF_PCI_PCIICR                       (*(volatile uint32_t*)(&_MBAR[0xB84]))
+#define MCF_PCI_PCIISR                       (*(volatile uint32_t*)(&_MBAR[0xB88]))
+#define MCF_PCI_PCICAR                       (*(volatile uint32_t*)(&_MBAR[0xBF8]))
+#define MCF_PCI_PCITPSR                      (*(volatile uint32_t*)(&_MBAR[0x8400]))
+#define MCF_PCI_PCITSAR                      (*(volatile uint32_t*)(&_MBAR[0x8404]))
+#define MCF_PCI_PCITTCR                      (*(volatile uint32_t*)(&_MBAR[0x8408]))
+#define MCF_PCI_PCITER                       (*(volatile uint32_t*)(&_MBAR[0x840C]))
+#define MCF_PCI_PCITNAR                      (*(volatile uint32_t*)(&_MBAR[0x8410]))
+#define MCF_PCI_PCITLWR                      (*(volatile uint32_t*)(&_MBAR[0x8414]))
+#define MCF_PCI_PCITDCR                      (*(volatile uint32_t*)(&_MBAR[0x8418]))
+#define MCF_PCI_PCITSR                       (*(volatile uint32_t*)(&_MBAR[0x841C]))
+#define MCF_PCI_PCITFDR                      (*(volatile uint32_t*)(&_MBAR[0x8440]))
+#define MCF_PCI_PCITFSR                      (*(volatile uint32_t*)(&_MBAR[0x8444]))
+#define MCF_PCI_PCITFCR                      (*(volatile uint32_t*)(&_MBAR[0x8448]))
+#define MCF_PCI_PCITFAR                      (*(volatile uint32_t*)(&_MBAR[0x844C]))
+#define MCF_PCI_PCITFRPR                     (*(volatile uint32_t*)(&_MBAR[0x8450]))
+#define MCF_PCI_PCITFWPR                     (*(volatile uint32_t*)(&_MBAR[0x8454]))
+#define MCF_PCI_PCIRPSR                      (*(volatile uint32_t*)(&_MBAR[0x8480]))
+#define MCF_PCI_PCIRSAR                      (*(volatile uint32_t*)(&_MBAR[0x8484]))
+#define MCF_PCI_PCIRTCR                      (*(volatile uint32_t*)(&_MBAR[0x8488]))
+#define MCF_PCI_PCIRER                       (*(volatile uint32_t*)(&_MBAR[0x848C]))
+#define MCF_PCI_PCIRNAR                      (*(volatile uint32_t*)(&_MBAR[0x8490]))
+#define MCF_PCI_PCIRDCR                      (*(volatile uint32_t*)(&_MBAR[0x8498]))
+#define MCF_PCI_PCIRSR                       (*(volatile uint32_t*)(&_MBAR[0x849C]))
+#define MCF_PCI_PCIRFDR                      (*(volatile uint32_t*)(&_MBAR[0x84C0]))
+#define MCF_PCI_PCIRFSR                      (*(volatile uint32_t*)(&_MBAR[0x84C4]))
+#define MCF_PCI_PCIRFCR                      (*(volatile uint32_t*)(&_MBAR[0x84C8]))
+#define MCF_PCI_PCIRFAR                      (*(volatile uint32_t*)(&_MBAR[0x84CC]))
+#define MCF_PCI_PCIRFRPR                     (*(volatile uint32_t*)(&_MBAR[0x84D0]))
+#define MCF_PCI_PCIRFWPR                     (*(volatile uint32_t*)(&_MBAR[0x84D4]))
+
+
+/* Bit definitions and macros for MCF_PCI_PCIIDR */
+#define MCF_PCI_PCIIDR_VENDORID(x)           (((x)&0xFFFF)<<0)
+#define MCF_PCI_PCIIDR_DEVICEID(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCISCR */
+#define MCF_PCI_PCISCR_IO                    (0x1)
+#define MCF_PCI_PCISCR_M                     (0x2)
+#define MCF_PCI_PCISCR_B                     (0x4)
+#define MCF_PCI_PCISCR_SP                    (0x8)
+#define MCF_PCI_PCISCR_MW                    (0x10)
+#define MCF_PCI_PCISCR_V                     (0x20)
+#define MCF_PCI_PCISCR_PER                   (0x40)
+#define MCF_PCI_PCISCR_ST                    (0x80)
+#define MCF_PCI_PCISCR_S                     (0x100)
+#define MCF_PCI_PCISCR_F                     (0x200)
+#define MCF_PCI_PCISCR_C                     (0x100000)
+#define MCF_PCI_PCISCR_66M                   (0x200000)
+#define MCF_PCI_PCISCR_R                     (0x400000)
+#define MCF_PCI_PCISCR_FC                    (0x800000)
+#define MCF_PCI_PCISCR_DP                    (0x1000000)
+#define MCF_PCI_PCISCR_DT(x)                 (((x)&0x3)<<0x19)
+#define MCF_PCI_PCISCR_TS                    (0x8000000)
+#define MCF_PCI_PCISCR_TR                    (0x10000000)
+#define MCF_PCI_PCISCR_MA                    (0x20000000)
+#define MCF_PCI_PCISCR_SE                    (0x40000000)
+#define MCF_PCI_PCISCR_PE                    (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCICCRIR */
+#define MCF_PCI_PCICCRIR_REVISIONID(x)       (((x)&0xFF)<<0)
+#define MCF_PCI_PCICCRIR_CLASSCODE(x)        (((x)&0xFFFFFF)<<0x8)
+
+/* Bit definitions and macros for MCF_PCI_PCICR1 */
+#define MCF_PCI_PCICR1_CACHELINESIZE(x)      (((x)&0xFF)<<0)
+#define MCF_PCI_PCICR1_LATTIMER(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCICR1_HEADERTYPE(x)         (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCICR1_BIST(x)               (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIBAR0 */
+#define MCF_PCI_PCIBAR0_IOM                  (0x1)
+#define MCF_PCI_PCIBAR0_RANGE(x)             (((x)&0x3)<<0x1)
+#define MCF_PCI_PCIBAR0_PREF                 (0x8)
+#define MCF_PCI_PCIBAR0_BAR0(x)              (((x)&0x3FFF)<<0x12)
+
+/* Bit definitions and macros for MCF_PCI_PCIBAR1 */
+#define MCF_PCI_PCIBAR1_IOM                  (0x1)
+#define MCF_PCI_PCIBAR1_RANGE(x)             (((x)&0x3)<<0x1)
+#define MCF_PCI_PCIBAR1_PREF                 (0x8)
+#define MCF_PCI_PCIBAR1_BAR1(x)              (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_PCI_PCICCPR */
+#define MCF_PCI_PCICCPR_PCICCP(x)            (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCISID */
+#define MCF_PCI_PCISID_VENDORID(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCICR2 */
+#define MCF_PCI_PCICR2_INTLINE(x)            (((x)&0xFF)<<0)
+#define MCF_PCI_PCICR2_INTPIN(x)             (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCICR2_MINGNT(x)             (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCICR2_MAXLAT(x)             (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIGSCR */
+#define MCF_PCI_PCIGSCR_PR                   (0x1)
+#define MCF_PCI_PCIGSCR_SEE                  (0x1000)
+#define MCF_PCI_PCIGSCR_PEE                  (0x2000)
+#define MCF_PCI_PCIGSCR_CLKINRESERVED(x)     (((x)&0x7)<<0x10)
+#define MCF_PCI_PCIGSCR_XLB2CLKIN(x)         (((x)&0x7)<<0x18)
+#define MCF_PCI_PCIGSCR_SE                   (0x10000000)
+#define MCF_PCI_PCIGSCR_PE                   (0x20000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITBATR0 */
+#define MCF_PCI_PCITBATR0_EN                 (0x1)
+#define MCF_PCI_PCITBATR0_BAT0(x)            (((x)&0x3FFF)<<0x12)
+
+/* Bit definitions and macros for MCF_PCI_PCITBATR1 */
+#define MCF_PCI_PCITBATR1_EN                 (0x1)
+#define MCF_PCI_PCITBATR1_BAT1(x)            (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_PCI_PCITCR */
+#define MCF_PCI_PCITCR_P                     (0x10000)
+#define MCF_PCI_PCITCR_LD                    (0x1000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */
+#define MCF_PCI_PCIIW0BTAR_WTA0(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCIIW0BTAR_WAM0(x)           (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIIW0BTAR_WBA0(x)           (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */
+#define MCF_PCI_PCIIW1BTAR_WTA1(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCIIW1BTAR_WAM1(x)           (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIIW1BTAR_WBA1(x)           (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */
+#define MCF_PCI_PCIIW2BTAR_WTA2(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCIIW2BTAR_WAM2(x)           (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIIW2BTAR_WBA2(x)           (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIIWCR */
+#define MCF_PCI_PCIIWCR_WINCTRL2_E           (0x100)
+#define MCF_PCI_PCIIWCR_WINCTRL2_PRC(x)      (((x)&0x3)<<0x9)
+#define MCF_PCI_PCIIWCR_WINCTRL2_IOM         (0x800)
+#define MCF_PCI_PCIIWCR_WINCTRL1_E           (0x10000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_PRC(x)      (((x)&0x3)<<0x11)
+#define MCF_PCI_PCIIWCR_WINCTRL1_IOM         (0x80000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_E           (0x1000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_PRC(x)      (((x)&0x3)<<0x19)
+#define MCF_PCI_PCIIWCR_WINCTRL0_IOM         (0x8000000)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD     (0x100)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE   (0x300)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL    (0x500)
+#define MCF_PCI_PCIIWCR_WINCTRL2_IO          (0x900)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD     (0x10000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE   (0x30000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL    (0x50000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_IO          (0x90000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD     (0x1000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE   (0x3000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL    (0x5000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_IO          (0x9000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIICR */
+#define MCF_PCI_PCIICR_MAXRETRY(x)           (((x)&0xFF)<<0)
+#define MCF_PCI_PCIICR_TAE                   (0x1000000)
+#define MCF_PCI_PCIICR_IAE                   (0x2000000)
+#define MCF_PCI_PCIICR_REE                   (0x4000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIISR */
+#define MCF_PCI_PCIISR_TA                    (0x1000000)
+#define MCF_PCI_PCIISR_IA                    (0x2000000)
+#define MCF_PCI_PCIISR_RE                    (0x4000000)
+
+/* Bit definitions and macros for MCF_PCI_PCICAR */
+#define MCF_PCI_PCICAR_DWORD(x)              (((x)&0x3F)<<0x2)
+#define MCF_PCI_PCICAR_FUNCNUM(x)            (((x)&0x7)<<0x8)
+#define MCF_PCI_PCICAR_DEVNUM(x)             (((x)&0x1F)<<0xB)
+#define MCF_PCI_PCICAR_BUSNUM(x)             (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCICAR_E                     (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITPSR */
+#define MCF_PCI_PCITPSR_PKTSIZE(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCITSAR */
+#define MCF_PCI_PCITSAR_STARTADD(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITTCR */
+#define MCF_PCI_PCITTCR_DI                   (0x1)
+#define MCF_PCI_PCITTCR_W                    (0x10)
+#define MCF_PCI_PCITTCR_MAXBEATS(x)          (((x)&0x7)<<0x8)
+#define MCF_PCI_PCITTCR_MAXRETRY(x)          (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCITTCR_PCICMD(x)            (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCITER */
+#define MCF_PCI_PCITER_NE                    (0x10000)
+#define MCF_PCI_PCITER_IAE                   (0x20000)
+#define MCF_PCI_PCITER_TAE                   (0x40000)
+#define MCF_PCI_PCITER_RE                    (0x80000)
+#define MCF_PCI_PCITER_SE                    (0x100000)
+#define MCF_PCI_PCITER_FEE                   (0x200000)
+#define MCF_PCI_PCITER_ME                    (0x1000000)
+#define MCF_PCI_PCITER_BE                    (0x8000000)
+#define MCF_PCI_PCITER_CM                    (0x10000000)
+#define MCF_PCI_PCITER_RF                    (0x40000000)
+#define MCF_PCI_PCITER_RC                    (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITNAR */
+#define MCF_PCI_PCITNAR_NEXTADDRESS(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITLWR */
+#define MCF_PCI_PCITLWR_LASTWORD(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITDCR */
+#define MCF_PCI_PCITDCR_PKTSDONE(x)          (((x)&0xFFFF)<<0)
+#define MCF_PCI_PCITDCR_BYTESDONE(x)         (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCITSR */
+#define MCF_PCI_PCITSR_IA                    (0x10000)
+#define MCF_PCI_PCITSR_TA                    (0x20000)
+#define MCF_PCI_PCITSR_RE                    (0x40000)
+#define MCF_PCI_PCITSR_SE                    (0x80000)
+#define MCF_PCI_PCITSR_FE                    (0x100000)
+#define MCF_PCI_PCITSR_BE1                   (0x200000)
+#define MCF_PCI_PCITSR_BE2                   (0x400000)
+#define MCF_PCI_PCITSR_BE3                   (0x800000)
+#define MCF_PCI_PCITSR_NT                    (0x1000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITFDR */
+#define MCF_PCI_PCITFDR_FIFODATAWORD(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITFSR */
+#define MCF_PCI_PCITFSR_EMPTY                (0x10000)
+#define MCF_PCI_PCITFSR_ALARM                (0x20000)
+#define MCF_PCI_PCITFSR_FULL                 (0x40000)
+#define MCF_PCI_PCITFSR_FR                   (0x80000)
+#define MCF_PCI_PCITFSR_OF                   (0x100000)
+#define MCF_PCI_PCITFSR_UF                   (0x200000)
+#define MCF_PCI_PCITFSR_RXW                  (0x400000)
+#define MCF_PCI_PCITFSR_FAE                  (0x800000)
+#define MCF_PCI_PCITFSR_TXW                  (0x40000000)
+#define MCF_PCI_PCITFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITFCR */
+#define MCF_PCI_PCITFCR_TXW_MASK             (0x40000)
+#define MCF_PCI_PCITFCR_OF_MASK              (0x80000)
+#define MCF_PCI_PCITFCR_UF_MASK              (0x100000)
+#define MCF_PCI_PCITFCR_RXW_MASK             (0x200000)
+#define MCF_PCI_PCITFCR_FAE_MASK             (0x400000)
+#define MCF_PCI_PCITFCR_IP_MASK              (0x800000)
+#define MCF_PCI_PCITFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PCI_PCITFCR_WFR                  (0x20000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITFAR */
+#define MCF_PCI_PCITFAR_ALARM(x)             (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITFRPR */
+#define MCF_PCI_PCITFRPR_READPTR(x)          (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITFWPR */
+#define MCF_PCI_PCITFWPR_WRITEPTR(x)         (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRPSR */
+#define MCF_PCI_PCIRPSR_PKTSIZE(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCIRSAR */
+#define MCF_PCI_PCIRSAR_STARTADD(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRTCR */
+#define MCF_PCI_PCIRTCR_DI                   (0x1)
+#define MCF_PCI_PCIRTCR_W                    (0x10)
+#define MCF_PCI_PCIRTCR_MAXBEATS(x)          (((x)&0x7)<<0x8)
+#define MCF_PCI_PCIRTCR_FB                   (0x1000)
+#define MCF_PCI_PCIRTCR_MAXRETRY(x)          (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIRTCR_PCICMD(x)            (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIRER */
+#define MCF_PCI_PCIRER_NE                    (0x10000)
+#define MCF_PCI_PCIRER_IAE                   (0x20000)
+#define MCF_PCI_PCIRER_TAE                   (0x40000)
+#define MCF_PCI_PCIRER_RE                    (0x80000)
+#define MCF_PCI_PCIRER_SE                    (0x100000)
+#define MCF_PCI_PCIRER_FEE                   (0x200000)
+#define MCF_PCI_PCIRER_ME                    (0x1000000)
+#define MCF_PCI_PCIRER_BE                    (0x8000000)
+#define MCF_PCI_PCIRER_CM                    (0x10000000)
+#define MCF_PCI_PCIRER_FE                    (0x20000000)
+#define MCF_PCI_PCIRER_RF                    (0x40000000)
+#define MCF_PCI_PCIRER_RC                    (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRNAR */
+#define MCF_PCI_PCIRNAR_NEXTADDRESS(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRDCR */
+#define MCF_PCI_PCIRDCR_PKTSDONE(x)          (((x)&0xFFFF)<<0)
+#define MCF_PCI_PCIRDCR_BYTESDONE(x)         (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCIRSR */
+#define MCF_PCI_PCIRSR_IA                    (0x10000)
+#define MCF_PCI_PCIRSR_TA                    (0x20000)
+#define MCF_PCI_PCIRSR_RE                    (0x40000)
+#define MCF_PCI_PCIRSR_SE                    (0x80000)
+#define MCF_PCI_PCIRSR_FE                    (0x100000)
+#define MCF_PCI_PCIRSR_BE1                   (0x200000)
+#define MCF_PCI_PCIRSR_BE2                   (0x400000)
+#define MCF_PCI_PCIRSR_BE3                   (0x800000)
+#define MCF_PCI_PCIRSR_NT                    (0x1000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFDR */
+#define MCF_PCI_PCIRFDR_FIFODATAWORD(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFSR */
+#define MCF_PCI_PCIRFSR_EMPTY                (0x10000)
+#define MCF_PCI_PCIRFSR_ALARM                (0x20000)
+#define MCF_PCI_PCIRFSR_FULL                 (0x40000)
+#define MCF_PCI_PCIRFSR_FR                   (0x80000)
+#define MCF_PCI_PCIRFSR_OF                   (0x100000)
+#define MCF_PCI_PCIRFSR_UF                   (0x200000)
+#define MCF_PCI_PCIRFSR_RXW                  (0x400000)
+#define MCF_PCI_PCIRFSR_FAE                  (0x800000)
+#define MCF_PCI_PCIRFSR_TXW                  (0x40000000)
+#define MCF_PCI_PCIRFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFCR */
+#define MCF_PCI_PCIRFCR_TXW_MASK             (0x40000)
+#define MCF_PCI_PCIRFCR_OF_MASK              (0x80000)
+#define MCF_PCI_PCIRFCR_UF_MASK              (0x100000)
+#define MCF_PCI_PCIRFCR_RXW_MASK             (0x200000)
+#define MCF_PCI_PCIRFCR_FAE_MASK             (0x400000)
+#define MCF_PCI_PCIRFCR_IP_MASK              (0x800000)
+#define MCF_PCI_PCIRFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PCI_PCIRFCR_WFR                  (0x20000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFAR */
+#define MCF_PCI_PCIRFAR_ALARM(x)             (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFRPR */
+#define MCF_PCI_PCIRFRPR_READPTR(x)          (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFWPR */
+#define MCF_PCI_PCIRFWPR_WRITEPTR(x)         (((x)&0x7F)<<0)
+
+
+#endif /* __MCF5475_PCI_H__ */
--- a/tos/fpga_test/include/MCF5475_PCIARB.h
+++ b/tos/fpga_test/include/MCF5475_PCIARB.h
@@ -0,0 +1,43 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PCIARB_H__
+#define __MCF5475_PCIARB_H__
+
+
+/*********************************************************************
+*
+* PCI Bus Arbiter Module (PCIARB)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PCIARB_PACR                      (*(volatile uint32_t*)(&_MBAR[0xC00]))
+#define MCF_PCIARB_PASR                      (*(volatile uint32_t*)(&_MBAR[0xC04]))
+
+
+/* Bit definitions and macros for MCF_PCIARB_PACR */
+#define MCF_PCIARB_PACR_INTMPRI              (0x1)
+#define MCF_PCIARB_PACR_EXTMPRI(x)           (((x)&0x1F)<<0x1)
+#define MCF_PCIARB_PACR_INTMINTEN            (0x10000)
+#define MCF_PCIARB_PACR_EXTMINTEN(x)         (((x)&0x1F)<<0x11)
+#define MCF_PCIARB_PACR_DS                   (0x80000000)
+
+/* Bit definitions and macros for MCF_PCIARB_PASR */
+#define MCF_PCIARB_PASR_ITLMBK               (0x10000)
+#define MCF_PCIARB_PASR_EXTMBK(x)            (((x)&0x1F)<<0x11)
+
+
+#endif /* __MCF5475_PCIARB_H__ */
--- a/tos/fpga_test/include/MCF5475_PSC.h
+++ b/tos/fpga_test/include/MCF5475_PSC.h
@@ -0,0 +1,527 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PSC_H__
+#define __MCF5475_PSC_H__
+
+
+/*********************************************************************
+*
+* Programmable Serial Controller (PSC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PSC0_PSCMR2                      (*(volatile uint8_t *)(&_MBAR[0x8600]))
+#define MCF_PSC0_PSCMR1                      (*(volatile uint8_t *)(&_MBAR[0x8600]))
+#define MCF_PSC0_PSCCSR                      (*(volatile uint8_t *)(&_MBAR[0x8604]))
+#define MCF_PSC0_PSCSR                       (*(volatile uint16_t*)(&_MBAR[0x8604]))
+#define MCF_PSC0_PSCCR                       (*(volatile uint8_t *)(&_MBAR[0x8608]))
+#define MCF_PSC0_PSCRB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCTB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCRB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCTB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCRB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCTB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCIPCR                     (*(volatile uint8_t *)(&_MBAR[0x8610]))
+#define MCF_PSC0_PSCACR                      (*(volatile uint8_t *)(&_MBAR[0x8610]))
+#define MCF_PSC0_PSCIMR                      (*(volatile uint16_t*)(&_MBAR[0x8614]))
+#define MCF_PSC0_PSCISR                      (*(volatile uint16_t*)(&_MBAR[0x8614]))
+#define MCF_PSC0_PSCCTUR                     (*(volatile uint8_t *)(&_MBAR[0x8618]))
+#define MCF_PSC0_PSCCTLR                     (*(volatile uint8_t *)(&_MBAR[0x861C]))
+#define MCF_PSC0_PSCIP                       (*(volatile uint8_t *)(&_MBAR[0x8634]))
+#define MCF_PSC0_PSCOPSET                    (*(volatile uint8_t *)(&_MBAR[0x8638]))
+#define MCF_PSC0_PSCOPRESET                  (*(volatile uint8_t *)(&_MBAR[0x863C]))
+#define MCF_PSC0_PSCSICR                     (*(volatile uint8_t *)(&_MBAR[0x8640]))
+#define MCF_PSC0_PSCIRCR1                    (*(volatile uint8_t *)(&_MBAR[0x8644]))
+#define MCF_PSC0_PSCIRCR2                    (*(volatile uint8_t *)(&_MBAR[0x8648]))
+#define MCF_PSC0_PSCIRSDR                    (*(volatile uint8_t *)(&_MBAR[0x864C]))
+#define MCF_PSC0_PSCIRMDR                    (*(volatile uint8_t *)(&_MBAR[0x8650]))
+#define MCF_PSC0_PSCIRFDR                    (*(volatile uint8_t *)(&_MBAR[0x8654]))
+#define MCF_PSC0_PSCRFCNT                    (*(volatile uint16_t*)(&_MBAR[0x8658]))
+#define MCF_PSC0_PSCTFCNT                    (*(volatile uint16_t*)(&_MBAR[0x865C]))
+#define MCF_PSC0_PSCRFDR                     (*(volatile uint32_t*)(&_MBAR[0x8660]))
+#define MCF_PSC0_PSCRFSR                     (*(volatile uint16_t*)(&_MBAR[0x8664]))
+#define MCF_PSC0_PSCRFCR                     (*(volatile uint32_t*)(&_MBAR[0x8668]))
+#define MCF_PSC0_PSCRFAR                     (*(volatile uint16_t*)(&_MBAR[0x866E]))
+#define MCF_PSC0_PSCRFRP                     (*(volatile uint16_t*)(&_MBAR[0x8672]))
+#define MCF_PSC0_PSCRFWP                     (*(volatile uint16_t*)(&_MBAR[0x8676]))
+#define MCF_PSC0_PSCRLRFP                    (*(volatile uint16_t*)(&_MBAR[0x867A]))
+#define MCF_PSC0_PSCRLWFP                    (*(volatile uint16_t*)(&_MBAR[0x867E]))
+#define MCF_PSC0_PSCTFDR                     (*(volatile uint32_t*)(&_MBAR[0x8680]))
+#define MCF_PSC0_PSCTFSR                     (*(volatile uint16_t*)(&_MBAR[0x8684]))
+#define MCF_PSC0_PSCTFCR                     (*(volatile uint32_t*)(&_MBAR[0x8688]))
+#define MCF_PSC0_PSCTFAR                     (*(volatile uint16_t*)(&_MBAR[0x868E]))
+#define MCF_PSC0_PSCTFRP                     (*(volatile uint16_t*)(&_MBAR[0x8692]))
+#define MCF_PSC0_PSCTFWP                     (*(volatile uint16_t*)(&_MBAR[0x8696]))
+#define MCF_PSC0_PSCTLRFP                    (*(volatile uint16_t*)(&_MBAR[0x869A]))
+#define MCF_PSC0_PSCTLWFP                    (*(volatile uint16_t*)(&_MBAR[0x869E]))
+
+#define MCF_PSC1_PSCMR2                      (*(volatile uint8_t *)(&_MBAR[0x8700]))
+#define MCF_PSC1_PSCMR1                      (*(volatile uint8_t *)(&_MBAR[0x8700]))
+#define MCF_PSC1_PSCCSR                      (*(volatile uint8_t *)(&_MBAR[0x8704]))
+#define MCF_PSC1_PSCSR                       (*(volatile uint16_t*)(&_MBAR[0x8704]))
+#define MCF_PSC1_PSCCR                       (*(volatile uint8_t *)(&_MBAR[0x8708]))
+#define MCF_PSC1_PSCRB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCTB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCRB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCTB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCRB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCTB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCIPCR                     (*(volatile uint8_t *)(&_MBAR[0x8710]))
+#define MCF_PSC1_PSCACR                      (*(volatile uint8_t *)(&_MBAR[0x8710]))
+#define MCF_PSC1_PSCIMR                      (*(volatile uint16_t*)(&_MBAR[0x8714]))
+#define MCF_PSC1_PSCISR                      (*(volatile uint16_t*)(&_MBAR[0x8714]))
+#define MCF_PSC1_PSCCTUR                     (*(volatile uint8_t *)(&_MBAR[0x8718]))
+#define MCF_PSC1_PSCCTLR                     (*(volatile uint8_t *)(&_MBAR[0x871C]))
+#define MCF_PSC1_PSCIP                       (*(volatile uint8_t *)(&_MBAR[0x8734]))
+#define MCF_PSC1_PSCOPSET                    (*(volatile uint8_t *)(&_MBAR[0x8738]))
+#define MCF_PSC1_PSCOPRESET                  (*(volatile uint8_t *)(&_MBAR[0x873C]))
+#define MCF_PSC1_PSCSICR                     (*(volatile uint8_t *)(&_MBAR[0x8740]))
+#define MCF_PSC1_PSCIRCR1                    (*(volatile uint8_t *)(&_MBAR[0x8744]))
+#define MCF_PSC1_PSCIRCR2                    (*(volatile uint8_t *)(&_MBAR[0x8748]))
+#define MCF_PSC1_PSCIRSDR                    (*(volatile uint8_t *)(&_MBAR[0x874C]))
+#define MCF_PSC1_PSCIRMDR                    (*(volatile uint8_t *)(&_MBAR[0x8750]))
+#define MCF_PSC1_PSCIRFDR                    (*(volatile uint8_t *)(&_MBAR[0x8754]))
+#define MCF_PSC1_PSCRFCNT                    (*(volatile uint16_t*)(&_MBAR[0x8758]))
+#define MCF_PSC1_PSCTFCNT                    (*(volatile uint16_t*)(&_MBAR[0x875C]))
+#define MCF_PSC1_PSCRFDR                     (*(volatile uint32_t*)(&_MBAR[0x8760]))
+#define MCF_PSC1_PSCRFSR                     (*(volatile uint16_t*)(&_MBAR[0x8764]))
+#define MCF_PSC1_PSCRFCR                     (*(volatile uint32_t*)(&_MBAR[0x8768]))
+#define MCF_PSC1_PSCRFAR                     (*(volatile uint16_t*)(&_MBAR[0x876E]))
+#define MCF_PSC1_PSCRFRP                     (*(volatile uint16_t*)(&_MBAR[0x8772]))
+#define MCF_PSC1_PSCRFWP                     (*(volatile uint16_t*)(&_MBAR[0x8776]))
+#define MCF_PSC1_PSCRLRFP                    (*(volatile uint16_t*)(&_MBAR[0x877A]))
+#define MCF_PSC1_PSCRLWFP                    (*(volatile uint16_t*)(&_MBAR[0x877E]))
+#define MCF_PSC1_PSCTFDR                     (*(volatile uint32_t*)(&_MBAR[0x8780]))
+#define MCF_PSC1_PSCTFSR                     (*(volatile uint16_t*)(&_MBAR[0x8784]))
+#define MCF_PSC1_PSCTFCR                     (*(volatile uint32_t*)(&_MBAR[0x8788]))
+#define MCF_PSC1_PSCTFAR                     (*(volatile uint16_t*)(&_MBAR[0x878E]))
+#define MCF_PSC1_PSCTFRP                     (*(volatile uint16_t*)(&_MBAR[0x8792]))
+#define MCF_PSC1_PSCTFWP                     (*(volatile uint16_t*)(&_MBAR[0x8796]))
+#define MCF_PSC1_PSCTLRFP                    (*(volatile uint16_t*)(&_MBAR[0x879A]))
+#define MCF_PSC1_PSCTLWFP                    (*(volatile uint16_t*)(&_MBAR[0x879E]))
+
+#define MCF_PSC2_PSCMR2                      (*(volatile uint8_t *)(&_MBAR[0x8800]))
+#define MCF_PSC2_PSCMR1                      (*(volatile uint8_t *)(&_MBAR[0x8800]))
+#define MCF_PSC2_PSCCSR                      (*(volatile uint8_t *)(&_MBAR[0x8804]))
+#define MCF_PSC2_PSCSR                       (*(volatile uint16_t*)(&_MBAR[0x8804]))
+#define MCF_PSC2_PSCCR                       (*(volatile uint8_t *)(&_MBAR[0x8808]))
+#define MCF_PSC2_PSCRB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCTB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCRB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCTB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCRB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCTB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCIPCR                     (*(volatile uint8_t *)(&_MBAR[0x8810]))
+#define MCF_PSC2_PSCACR                      (*(volatile uint8_t *)(&_MBAR[0x8810]))
+#define MCF_PSC2_PSCIMR                      (*(volatile uint16_t*)(&_MBAR[0x8814]))
+#define MCF_PSC2_PSCISR                      (*(volatile uint16_t*)(&_MBAR[0x8814]))
+#define MCF_PSC2_PSCCTUR                     (*(volatile uint8_t *)(&_MBAR[0x8818]))
+#define MCF_PSC2_PSCCTLR                     (*(volatile uint8_t *)(&_MBAR[0x881C]))
+#define MCF_PSC2_PSCIP                       (*(volatile uint8_t *)(&_MBAR[0x8834]))
+#define MCF_PSC2_PSCOPSET                    (*(volatile uint8_t *)(&_MBAR[0x8838]))
+#define MCF_PSC2_PSCOPRESET                  (*(volatile uint8_t *)(&_MBAR[0x883C]))
+#define MCF_PSC2_PSCSICR                     (*(volatile uint8_t *)(&_MBAR[0x8840]))
+#define MCF_PSC2_PSCIRCR1                    (*(volatile uint8_t *)(&_MBAR[0x8844]))
+#define MCF_PSC2_PSCIRCR2                    (*(volatile uint8_t *)(&_MBAR[0x8848]))
+#define MCF_PSC2_PSCIRSDR                    (*(volatile uint8_t *)(&_MBAR[0x884C]))
+#define MCF_PSC2_PSCIRMDR                    (*(volatile uint8_t *)(&_MBAR[0x8850]))
+#define MCF_PSC2_PSCIRFDR                    (*(volatile uint8_t *)(&_MBAR[0x8854]))
+#define MCF_PSC2_PSCRFCNT                    (*(volatile uint16_t*)(&_MBAR[0x8858]))
+#define MCF_PSC2_PSCTFCNT                    (*(volatile uint16_t*)(&_MBAR[0x885C]))
+#define MCF_PSC2_PSCRFDR                     (*(volatile uint32_t*)(&_MBAR[0x8860]))
+#define MCF_PSC2_PSCRFSR                     (*(volatile uint16_t*)(&_MBAR[0x8864]))
+#define MCF_PSC2_PSCRFCR                     (*(volatile uint32_t*)(&_MBAR[0x8868]))
+#define MCF_PSC2_PSCRFAR                     (*(volatile uint16_t*)(&_MBAR[0x886E]))
+#define MCF_PSC2_PSCRFRP                     (*(volatile uint16_t*)(&_MBAR[0x8872]))
+#define MCF_PSC2_PSCRFWP                     (*(volatile uint16_t*)(&_MBAR[0x8876]))
+#define MCF_PSC2_PSCRLRFP                    (*(volatile uint16_t*)(&_MBAR[0x887A]))
+#define MCF_PSC2_PSCRLWFP                    (*(volatile uint16_t*)(&_MBAR[0x887E]))
+#define MCF_PSC2_PSCTFDR                     (*(volatile uint32_t*)(&_MBAR[0x8880]))
+#define MCF_PSC2_PSCTFSR                     (*(volatile uint16_t*)(&_MBAR[0x8884]))
+#define MCF_PSC2_PSCTFCR                     (*(volatile uint32_t*)(&_MBAR[0x8888]))
+#define MCF_PSC2_PSCTFAR                     (*(volatile uint16_t*)(&_MBAR[0x888E]))
+#define MCF_PSC2_PSCTFRP                     (*(volatile uint16_t*)(&_MBAR[0x8892]))
+#define MCF_PSC2_PSCTFWP                     (*(volatile uint16_t*)(&_MBAR[0x8896]))
+#define MCF_PSC2_PSCTLRFP                    (*(volatile uint16_t*)(&_MBAR[0x889A]))
+#define MCF_PSC2_PSCTLWFP                    (*(volatile uint16_t*)(&_MBAR[0x889E]))
+
+#define MCF_PSC3_PSCMR2                      (*(volatile uint8_t *)(&_MBAR[0x8900]))
+#define MCF_PSC3_PSCMR1                      (*(volatile uint8_t *)(&_MBAR[0x8900]))
+#define MCF_PSC3_PSCCSR                      (*(volatile uint8_t *)(&_MBAR[0x8904]))
+#define MCF_PSC3_PSCSR                       (*(volatile uint16_t*)(&_MBAR[0x8904]))
+#define MCF_PSC3_PSCCR                       (*(volatile uint8_t *)(&_MBAR[0x8908]))
+#define MCF_PSC3_PSCRB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCTB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCRB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCTB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCRB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCTB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCIPCR                     (*(volatile uint8_t *)(&_MBAR[0x8910]))
+#define MCF_PSC3_PSCACR                      (*(volatile uint8_t *)(&_MBAR[0x8910]))
+#define MCF_PSC3_PSCIMR                      (*(volatile uint16_t*)(&_MBAR[0x8914]))
+#define MCF_PSC3_PSCISR                      (*(volatile uint16_t*)(&_MBAR[0x8914]))
+#define MCF_PSC3_PSCCTUR                     (*(volatile uint8_t *)(&_MBAR[0x8918]))
+#define MCF_PSC3_PSCCTLR                     (*(volatile uint8_t *)(&_MBAR[0x891C]))
+#define MCF_PSC3_PSCIP                       (*(volatile uint8_t *)(&_MBAR[0x8934]))
+#define MCF_PSC3_PSCOPSET                    (*(volatile uint8_t *)(&_MBAR[0x8938]))
+#define MCF_PSC3_PSCOPRESET                  (*(volatile uint8_t *)(&_MBAR[0x893C]))
+#define MCF_PSC3_PSCSICR                     (*(volatile uint8_t *)(&_MBAR[0x8940]))
+#define MCF_PSC3_PSCIRCR1                    (*(volatile uint8_t *)(&_MBAR[0x8944]))
+#define MCF_PSC3_PSCIRCR2                    (*(volatile uint8_t *)(&_MBAR[0x8948]))
+#define MCF_PSC3_PSCIRSDR                    (*(volatile uint8_t *)(&_MBAR[0x894C]))
+#define MCF_PSC3_PSCIRMDR                    (*(volatile uint8_t *)(&_MBAR[0x8950]))
+#define MCF_PSC3_PSCIRFDR                    (*(volatile uint8_t *)(&_MBAR[0x8954]))
+#define MCF_PSC3_PSCRFCNT                    (*(volatile uint16_t*)(&_MBAR[0x8958]))
+#define MCF_PSC3_PSCTFCNT                    (*(volatile uint16_t*)(&_MBAR[0x895C]))
+#define MCF_PSC3_PSCRFDR                     (*(volatile uint32_t*)(&_MBAR[0x8960]))
+#define MCF_PSC3_PSCRFSR                     (*(volatile uint16_t*)(&_MBAR[0x8964]))
+#define MCF_PSC3_PSCRFCR                     (*(volatile uint32_t*)(&_MBAR[0x8968]))
+#define MCF_PSC3_PSCRFAR                     (*(volatile uint16_t*)(&_MBAR[0x896E]))
+#define MCF_PSC3_PSCRFRP                     (*(volatile uint16_t*)(&_MBAR[0x8972]))
+#define MCF_PSC3_PSCRFWP                     (*(volatile uint16_t*)(&_MBAR[0x8976]))
+#define MCF_PSC3_PSCRLRFP                    (*(volatile uint16_t*)(&_MBAR[0x897A]))
+#define MCF_PSC3_PSCRLWFP                    (*(volatile uint16_t*)(&_MBAR[0x897E]))
+#define MCF_PSC3_PSCTFDR                     (*(volatile uint32_t*)(&_MBAR[0x8980]))
+#define MCF_PSC3_PSCTFSR                     (*(volatile uint16_t*)(&_MBAR[0x8984]))
+#define MCF_PSC3_PSCTFCR                     (*(volatile uint32_t*)(&_MBAR[0x8988]))
+#define MCF_PSC3_PSCTFAR                     (*(volatile uint16_t*)(&_MBAR[0x898E]))
+#define MCF_PSC3_PSCTFRP                     (*(volatile uint16_t*)(&_MBAR[0x8992]))
+#define MCF_PSC3_PSCTFWP                     (*(volatile uint16_t*)(&_MBAR[0x8996]))
+#define MCF_PSC3_PSCTLRFP                    (*(volatile uint16_t*)(&_MBAR[0x899A]))
+#define MCF_PSC3_PSCTLWFP                    (*(volatile uint16_t*)(&_MBAR[0x899E]))
+
+#define MCF_PSC_PSCMR(x)                     (*(volatile uint8_t *)(&_MBAR[0x8600 + ((x)*0x100)]))
+#define MCF_PSC_PSCCSR(x)                    (*(volatile uint8_t *)(&_MBAR[0x8604 + ((x)*0x100)]))
+#define MCF_PSC_PSCSR(x)                     (*(volatile uint16_t*)(&_MBAR[0x8604 + ((x)*0x100)]))
+#define MCF_PSC_PSCCR(x)                     (*(volatile uint8_t *)(&_MBAR[0x8608 + ((x)*0x100)]))
+#define MCF_PSC_PSCRB_8BIT(x)                (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCTB_8BIT(x)                (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCRB_16BIT(x)               (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCTB_16BIT(x)               (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCRB_AC97(x)                (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCTB_AC97(x)                (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCIPCR(x)                   (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)]))
+#define MCF_PSC_PSCACR(x)                    (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)]))
+#define MCF_PSC_PSCIMR(x)                    (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)]))
+#define MCF_PSC_PSCISR(x)                    (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)]))
+#define MCF_PSC_PSCCTUR(x)                   (*(volatile uint8_t *)(&_MBAR[0x8618 + ((x)*0x100)]))
+#define MCF_PSC_PSCCTLR(x)                   (*(volatile uint8_t *)(&_MBAR[0x861C + ((x)*0x100)]))
+#define MCF_PSC_PSCIP(x)                     (*(volatile uint8_t *)(&_MBAR[0x8634 + ((x)*0x100)]))
+#define MCF_PSC_PSCOPSET(x)                  (*(volatile uint8_t *)(&_MBAR[0x8638 + ((x)*0x100)]))
+#define MCF_PSC_PSCOPRESET(x)                (*(volatile uint8_t *)(&_MBAR[0x863C + ((x)*0x100)]))
+#define MCF_PSC_PSCSICR(x)                   (*(volatile uint8_t *)(&_MBAR[0x8640 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRCR1(x)                  (*(volatile uint8_t *)(&_MBAR[0x8644 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRCR2(x)                  (*(volatile uint8_t *)(&_MBAR[0x8648 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRSDR(x)                  (*(volatile uint8_t *)(&_MBAR[0x864C + ((x)*0x100)]))
+#define MCF_PSC_PSCIRMDR(x)                  (*(volatile uint8_t *)(&_MBAR[0x8650 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRFDR(x)                  (*(volatile uint8_t *)(&_MBAR[0x8654 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFCNT(x)                  (*(volatile uint16_t*)(&_MBAR[0x8658 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFCNT(x)                  (*(volatile uint16_t*)(&_MBAR[0x865C + ((x)*0x100)]))
+#define MCF_PSC_PSCRFDR(x)                   (*(volatile uint32_t*)(&_MBAR[0x8660 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFSR(x)                   (*(volatile uint16_t*)(&_MBAR[0x8664 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFCR(x)                   (*(volatile uint32_t*)(&_MBAR[0x8668 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFAR(x)                   (*(volatile uint16_t*)(&_MBAR[0x866E + ((x)*0x100)]))
+#define MCF_PSC_PSCRFRP(x)                   (*(volatile uint16_t*)(&_MBAR[0x8672 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFWP(x)                   (*(volatile uint16_t*)(&_MBAR[0x8676 + ((x)*0x100)]))
+#define MCF_PSC_PSCRLRFP(x)                  (*(volatile uint16_t*)(&_MBAR[0x867A + ((x)*0x100)]))
+#define MCF_PSC_PSCRLWFP(x)                  (*(volatile uint16_t*)(&_MBAR[0x867E + ((x)*0x100)]))
+#define MCF_PSC_PSCTFDR(x)                   (*(volatile uint32_t*)(&_MBAR[0x8680 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFSR(x)                   (*(volatile uint16_t*)(&_MBAR[0x8684 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFCR(x)                   (*(volatile uint32_t*)(&_MBAR[0x8688 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFAR(x)                   (*(volatile uint16_t*)(&_MBAR[0x868E + ((x)*0x100)]))
+#define MCF_PSC_PSCTFRP(x)                   (*(volatile uint16_t*)(&_MBAR[0x8692 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFWP(x)                   (*(volatile uint16_t*)(&_MBAR[0x8696 + ((x)*0x100)]))
+#define MCF_PSC_PSCTLRFP(x)                  (*(volatile uint16_t*)(&_MBAR[0x869A + ((x)*0x100)]))
+#define MCF_PSC_PSCTLWFP(x)                  (*(volatile uint16_t*)(&_MBAR[0x869E + ((x)*0x100)]))
+
+/* Bit definitions and macros for MCF_PSC_PSCMR */
+#define MCF_PSC_PSCMR_SB(x)                  (((x)&0xF)<<0)
+#define MCF_PSC_PSCMR_TXCTS                  (0x10)
+#define MCF_PSC_PSCMR_TXRTS                  (0x20)
+#define MCF_PSC_PSCMR_CM(x)                  (((x)&0x3)<<0x6)
+#define MCF_PSC_PSCMR_CM_NORMAL              (0)
+#define MCF_PSC_PSCMR_CM_ECHO                (0x40)
+#define MCF_PSC_PSCMR_CM_LOCAL_LOOP          (0x80)
+#define MCF_PSC_PSCMR_CM_REMOTE_LOOP         (0xC0)
+#define MCF_PSC_PSCMR_SB_STOP_BITS_1         (0x7)
+#define MCF_PSC_PSCMR_SB_STOP_BITS_15        (0x8)
+#define MCF_PSC_PSCMR_SB_STOP_BITS_2         (0xF)
+#define MCF_PSC_PSCMR_PM_MULTI_ADDR          (0x1C)
+#define MCF_PSC_PSCMR_PM_MULTI_DATA          (0x18)
+#define MCF_PSC_PSCMR_PM_NONE                (0x10)
+#define MCF_PSC_PSCMR_PM_FORCE_HI            (0xC)
+#define MCF_PSC_PSCMR_PM_FORCE_LO            (0x8)
+#define MCF_PSC_PSCMR_PM_ODD                 (0x4)
+#define MCF_PSC_PSCMR_PM_EVEN                (0)
+#define MCF_PSC_PSCMR_BC(x)                  (((x)&0x3)<<0)
+#define MCF_PSC_PSCMR_BC_5                   (0)
+#define MCF_PSC_PSCMR_BC_6                   (0x1)
+#define MCF_PSC_PSCMR_BC_7                   (0x2)
+#define MCF_PSC_PSCMR_BC_8                   (0x3)
+#define MCF_PSC_PSCMR_PT                     (0x4)
+#define MCF_PSC_PSCMR_PM(x)                  (((x)&0x3)<<0x3)
+#define MCF_PSC_PSCMR_ERR                    (0x20)
+#define MCF_PSC_PSCMR_RXIRQ_FU               (0x40)
+#define MCF_PSC_PSCMR_RXRTS                  (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCCSR */
+#define MCF_PSC_PSCCSR_TCSEL(x)              (((x)&0xF)<<0)
+#define MCF_PSC_PSCCSR_RCSEL(x)              (((x)&0xF)<<0x4)
+#define MCF_PSC_PSCCSR_TCSEL_SYS_CLK         (0x0D)
+#define MCF_PSC_PSCCSR_TCSEL_CTM16           (0x0E)
+#define MCF_PSC_PSCCSR_TCSEL_CTM             (0x0F)
+#define MCF_PSC_PSCCSR_RCSEL_SYS_CLK         (0xD0)
+#define MCF_PSC_PSCCSR_RCSEL_CTM16           (0xE0)
+#define MCF_PSC_PSCCSR_RCSEL_CTM             (0xF0)
+
+/* Bit definitions and macros for MCF_PSC_PSCSR */
+#define MCF_PSC_PSCSR_ERR                    (0x40)
+#define MCF_PSC_PSCSR_CDE_DEOF               (0x80)
+#define MCF_PSC_PSCSR_RXRDY                  (0x100)
+#define MCF_PSC_PSCSR_FU                     (0x200)
+#define MCF_PSC_PSCSR_TXRDY                  (0x400)
+#define MCF_PSC_PSCSR_TXEMP_URERR            (0x800)
+#define MCF_PSC_PSCSR_OE                     (0x1000)
+#define MCF_PSC_PSCSR_PE_CRCERR              (0x2000)
+#define MCF_PSC_PSCSR_FE_PHYERR              (0x4000)
+#define MCF_PSC_PSCSR_RB_NEOF                (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCCR */
+#define MCF_PSC_PSCCR_RXC(x)                 (((x)&0x3)<<0)
+#define MCF_PSC_PSCCR_RX_ENABLED             (0x1)
+#define MCF_PSC_PSCCR_RX_DISABLED            (0x2)
+#define MCF_PSC_PSCCR_TXC(x)                 (((x)&0x3)<<0x2)
+#define MCF_PSC_PSCCR_TX_ENABLED             (0x4)
+#define MCF_PSC_PSCCR_TX_DISABLED            (0x8)
+#define MCF_PSC_PSCCR_MISC(x)                (((x)&0x7)<<0x4)
+#define MCF_PSC_PSCCR_NONE                   (0)
+#define MCF_PSC_PSCCR_RESET_MR               (0x10)
+#define MCF_PSC_PSCCR_RESET_RX               (0x20)
+#define MCF_PSC_PSCCR_RESET_TX               (0x30)
+#define MCF_PSC_PSCCR_RESET_ERROR            (0x40)
+#define MCF_PSC_PSCCR_RESET_BKCHGINT         (0x50)
+#define MCF_PSC_PSCCR_START_BREAK            (0x60)
+#define MCF_PSC_PSCCR_STOP_BREAK             (0x70)
+
+/* Bit definitions and macros for MCF_PSC_PSCRB_8BIT */
+#define MCF_PSC_PSCRB_8BIT_RB3(x)            (((x)&0xFF)<<0)
+#define MCF_PSC_PSCRB_8BIT_RB2(x)            (((x)&0xFF)<<0x8)
+#define MCF_PSC_PSCRB_8BIT_RB1(x)            (((x)&0xFF)<<0x10)
+#define MCF_PSC_PSCRB_8BIT_RB0(x)            (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PSC_PSCTB_8BIT */
+#define MCF_PSC_PSCTB_8BIT_TB3(x)            (((x)&0xFF)<<0)
+#define MCF_PSC_PSCTB_8BIT_TB2(x)            (((x)&0xFF)<<0x8)
+#define MCF_PSC_PSCTB_8BIT_TB1(x)            (((x)&0xFF)<<0x10)
+#define MCF_PSC_PSCTB_8BIT_TB0(x)            (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PSC_PSCRB_16BIT */
+#define MCF_PSC_PSCRB_16BIT_RB1(x)           (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCRB_16BIT_RB0(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PSC_PSCTB_16BIT */
+#define MCF_PSC_PSCTB_16BIT_TB1(x)           (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCTB_16BIT_TB0(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PSC_PSCRB_AC97 */
+#define MCF_PSC_PSCRB_AC97_SOF               (0x800)
+#define MCF_PSC_PSCRB_AC97_RB(x)             (((x)&0xFFFFF)<<0xC)
+
+/* Bit definitions and macros for MCF_PSC_PSCTB_AC97 */
+#define MCF_PSC_PSCTB_AC97_TB(x)             (((x)&0xFFFFF)<<0xC)
+
+/* Bit definitions and macros for MCF_PSC_PSCIPCR */
+#define MCF_PSC_PSCIPCR_RESERVED             (0xC)
+#define MCF_PSC_PSCIPCR_CTS                  (0xD)
+#define MCF_PSC_PSCIPCR_D_CTS                (0x1C)
+#define MCF_PSC_PSCIPCR_SYNC                 (0x8C)
+
+/* Bit definitions and macros for MCF_PSC_PSCACR */
+#define MCF_PSC_PSCACR_IEC0                  (0x1)
+
+/* Bit definitions and macros for MCF_PSC_PSCIMR */
+#define MCF_PSC_PSCIMR_ERR                   (0x40)
+#define MCF_PSC_PSCIMR_DEOF                  (0x80)
+#define MCF_PSC_PSCIMR_TXRDY                 (0x100)
+#define MCF_PSC_PSCIMR_RXRDY_FU              (0x200)
+#define MCF_PSC_PSCIMR_DB                    (0x400)
+#define MCF_PSC_PSCIMR_IPC                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCISR */
+#define MCF_PSC_PSCISR_ERR                   (0x40)
+#define MCF_PSC_PSCISR_DEOF                  (0x80)
+#define MCF_PSC_PSCISR_TXRDY                 (0x100)
+#define MCF_PSC_PSCISR_RXRDY_FU              (0x200)
+#define MCF_PSC_PSCISR_DB                    (0x400)
+#define MCF_PSC_PSCISR_IPC                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCCTUR */
+#define MCF_PSC_PSCCTUR_CT(x)                (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCCTLR */
+#define MCF_PSC_PSCCTLR_CT(x)                (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCIP */
+#define MCF_PSC_PSCIP_CTS                    (0x1)
+#define MCF_PSC_PSCIP_TGL                    (0x40)
+#define MCF_PSC_PSCIP_LPWR_B                 (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCOPSET */
+#define MCF_PSC_PSCOPSET_RTS                 (0x1)
+
+/* Bit definitions and macros for MCF_PSC_PSCOPRESET */
+#define MCF_PSC_PSCOPRESET_RTS               (0x1)
+
+/* Bit definitions and macros for MCF_PSC_PSCSICR */
+#define MCF_PSC_PSCSICR_SIM(x)               (((x)&0x7)<<0)
+#define MCF_PSC_PSCSICR_SIM_UART             (0)
+#define MCF_PSC_PSCSICR_SIM_MODEM8           (0x1)
+#define MCF_PSC_PSCSICR_SIM_MODEM16          (0x2)
+#define MCF_PSC_PSCSICR_SIM_AC97             (0x3)
+#define MCF_PSC_PSCSICR_SIM_SIR              (0x4)
+#define MCF_PSC_PSCSICR_SIM_MIR              (0x5)
+#define MCF_PSC_PSCSICR_SIM_FIR              (0x6)
+#define MCF_PSC_PSCSICR_SHDIR                (0x10)
+#define MCF_PSC_PSCSICR_DTS1                 (0x20)
+#define MCF_PSC_PSCSICR_AWR                  (0x40)
+#define MCF_PSC_PSCSICR_ACRB                 (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRCR1 */
+#define MCF_PSC_PSCIRCR1_SPUL                (0x1)
+#define MCF_PSC_PSCIRCR1_SIPEN               (0x2)
+#define MCF_PSC_PSCIRCR1_FD                  (0x4)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRCR2 */
+#define MCF_PSC_PSCIRCR2_NXTEOF              (0x1)
+#define MCF_PSC_PSCIRCR2_ABORT               (0x2)
+#define MCF_PSC_PSCIRCR2_SIPREQ              (0x4)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRSDR */
+#define MCF_PSC_PSCIRSDR_IRSTIM(x)           (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRMDR */
+#define MCF_PSC_PSCIRMDR_M_FDIV(x)           (((x)&0x7F)<<0)
+#define MCF_PSC_PSCIRMDR_FREQ                (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRFDR */
+#define MCF_PSC_PSCIRFDR_F_FDIV(x)           (((x)&0xF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFCNT */
+#define MCF_PSC_PSCRFCNT_CNT(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFCNT */
+#define MCF_PSC_PSCTFCNT_CNT(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFDR */
+#define MCF_PSC_PSCRFDR_DATA(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFSR */
+#define MCF_PSC_PSCRFSR_EMT                  (0x1)
+#define MCF_PSC_PSCRFSR_ALARM                (0x2)
+#define MCF_PSC_PSCRFSR_FU                   (0x4)
+#define MCF_PSC_PSCRFSR_FRMRDY               (0x8)
+#define MCF_PSC_PSCRFSR_OF                   (0x10)
+#define MCF_PSC_PSCRFSR_UF                   (0x20)
+#define MCF_PSC_PSCRFSR_RXW                  (0x40)
+#define MCF_PSC_PSCRFSR_FAE                  (0x80)
+#define MCF_PSC_PSCRFSR_FRM(x)               (((x)&0xF)<<0x8)
+#define MCF_PSC_PSCRFSR_FRM_BYTE0            (0x800)
+#define MCF_PSC_PSCRFSR_FRM_BYTE1            (0x400)
+#define MCF_PSC_PSCRFSR_FRM_BYTE2            (0x200)
+#define MCF_PSC_PSCRFSR_FRM_BYTE3            (0x100)
+#define MCF_PSC_PSCRFSR_TAG(x)               (((x)&0x3)<<0xC)
+#define MCF_PSC_PSCRFSR_TXW                  (0x4000)
+#define MCF_PSC_PSCRFSR_IP                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFCR */
+#define MCF_PSC_PSCRFCR_CNTR(x)              (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCRFCR_TXW_MSK              (0x40000)
+#define MCF_PSC_PSCRFCR_OF_MSK               (0x80000)
+#define MCF_PSC_PSCRFCR_UF_MSK               (0x100000)
+#define MCF_PSC_PSCRFCR_RXW_MSK              (0x200000)
+#define MCF_PSC_PSCRFCR_FAE_MSK              (0x400000)
+#define MCF_PSC_PSCRFCR_IP_MSK               (0x800000)
+#define MCF_PSC_PSCRFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PSC_PSCRFCR_FRMEN                (0x8000000)
+#define MCF_PSC_PSCRFCR_TIMER                (0x10000000)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFAR */
+#define MCF_PSC_PSCRFAR_ALARM(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFRP */
+#define MCF_PSC_PSCRFRP_READ(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFWP */
+#define MCF_PSC_PSCRFWP_WRITE(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRLRFP */
+#define MCF_PSC_PSCRLRFP_LRFP(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRLWFP */
+#define MCF_PSC_PSCRLWFP_LWFP(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFDR */
+#define MCF_PSC_PSCTFDR_DATA(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFSR */
+#define MCF_PSC_PSCTFSR_EMT                  (0x1)
+#define MCF_PSC_PSCTFSR_ALARM                (0x2)
+#define MCF_PSC_PSCTFSR_FU                   (0x4)
+#define MCF_PSC_PSCTFSR_FRMRDY               (0x8)
+#define MCF_PSC_PSCTFSR_OF                   (0x10)
+#define MCF_PSC_PSCTFSR_UF                   (0x20)
+#define MCF_PSC_PSCTFSR_RXW                  (0x40)
+#define MCF_PSC_PSCTFSR_FAE                  (0x80)
+#define MCF_PSC_PSCTFSR_FRM(x)               (((x)&0xF)<<0x8)
+#define MCF_PSC_PSCTFSR_FRM_BYTE0            (0x800)
+#define MCF_PSC_PSCTFSR_FRM_BYTE1            (0x400)
+#define MCF_PSC_PSCTFSR_FRM_BYTE2            (0x200)
+#define MCF_PSC_PSCTFSR_FRM_BYTE3            (0x100)
+#define MCF_PSC_PSCTFSR_TAG(x)               (((x)&0x3)<<0xC)
+#define MCF_PSC_PSCTFSR_TXW                  (0x4000)
+#define MCF_PSC_PSCTFSR_IP                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFCR */
+#define MCF_PSC_PSCTFCR_CNTR(x)              (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCTFCR_TXW_MSK              (0x40000)
+#define MCF_PSC_PSCTFCR_OF_MSK               (0x80000)
+#define MCF_PSC_PSCTFCR_UF_MSK               (0x100000)
+#define MCF_PSC_PSCTFCR_RXW_MSK              (0x200000)
+#define MCF_PSC_PSCTFCR_FAE_MSK              (0x400000)
+#define MCF_PSC_PSCTFCR_IP_MSK               (0x800000)
+#define MCF_PSC_PSCTFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PSC_PSCTFCR_FRMEN                (0x8000000)
+#define MCF_PSC_PSCTFCR_TIMER                (0x10000000)
+#define MCF_PSC_PSCTFCR_WFR                  (0x20000000)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFAR */
+#define MCF_PSC_PSCTFAR_ALARM(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFRP */
+#define MCF_PSC_PSCTFRP_READ(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFWP */
+#define MCF_PSC_PSCTFWP_WRITE(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTLRFP */
+#define MCF_PSC_PSCTLRFP_LRFP(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTLWFP */
+#define MCF_PSC_PSCTLWFP_LWFP(x)             (((x)&0x1FF)<<0)
+
+
+#endif /* __MCF5475_PSC_H__ */
--- a/tos/fpga_test/include/MCF5475_SDRAMC.h
+++ b/tos/fpga_test/include/MCF5475_SDRAMC.h
@@ -0,0 +1,106 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SDRAMC_H__
+#define __MCF5475_SDRAMC_H__
+
+
+/*********************************************************************
+*
+* Synchronous DRAM Controller (SDRAMC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SDRAMC_SDRAMDS                   (*(volatile uint32_t*)(&_MBAR[0x4]))
+#define MCF_SDRAMC_CS0CFG                    (*(volatile uint32_t*)(&_MBAR[0x20]))
+#define MCF_SDRAMC_CS1CFG                    (*(volatile uint32_t*)(&_MBAR[0x24]))
+#define MCF_SDRAMC_CS2CFG                    (*(volatile uint32_t*)(&_MBAR[0x28]))
+#define MCF_SDRAMC_CS3CFG                    (*(volatile uint32_t*)(&_MBAR[0x2C]))
+#define MCF_SDRAMC_SDMR                      (*(volatile uint32_t*)(&_MBAR[0x100]))
+#define MCF_SDRAMC_SDCR                      (*(volatile uint32_t*)(&_MBAR[0x104]))
+#define MCF_SDRAMC_SDCFG1                    (*(volatile uint32_t*)(&_MBAR[0x108]))
+#define MCF_SDRAMC_SDCFG2                    (*(volatile uint32_t*)(&_MBAR[0x10C]))
+#define MCF_SDRAMC_CSCFG(x)                  (*(volatile uint32_t*)(&_MBAR[0x20 + ((x)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */
+#define MCF_SDRAMC_SDRAMDS_SB_D(x)           (((x)&0x3)<<0)
+#define MCF_SDRAMC_SDRAMDS_SB_S(x)           (((x)&0x3)<<0x2)
+#define MCF_SDRAMC_SDRAMDS_SB_A(x)           (((x)&0x3)<<0x4)
+#define MCF_SDRAMC_SDRAMDS_SB_C(x)           (((x)&0x3)<<0x6)
+#define MCF_SDRAMC_SDRAMDS_SB_E(x)           (((x)&0x3)<<0x8)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA        (0)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA        (0x1)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA         (0x2)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE        (0x3)
+
+/* Bit definitions and macros for MCF_SDRAMC_CSCFG */
+#define MCF_SDRAMC_CSCFG_CSSZ(x)             (((x)&0x1F)<<0)
+#define MCF_SDRAMC_CSCFG_CSSZ_DISABLED       (0)
+#define MCF_SDRAMC_CSCFG_CSSZ_1MBYTE         (0x13)
+#define MCF_SDRAMC_CSCFG_CSSZ_2MBYTE         (0x14)
+#define MCF_SDRAMC_CSCFG_CSSZ_4MBYTE         (0x15)
+#define MCF_SDRAMC_CSCFG_CSSZ_8MBYTE         (0x16)
+#define MCF_SDRAMC_CSCFG_CSSZ_16MBYTE        (0x17)
+#define MCF_SDRAMC_CSCFG_CSSZ_32MBYTE        (0x18)
+#define MCF_SDRAMC_CSCFG_CSSZ_64MBYTE        (0x19)
+#define MCF_SDRAMC_CSCFG_CSSZ_128MBYTE       (0x1A)
+#define MCF_SDRAMC_CSCFG_CSSZ_256MBYTE       (0x1B)
+#define MCF_SDRAMC_CSCFG_CSSZ_512MBYTE       (0x1C)
+#define MCF_SDRAMC_CSCFG_CSSZ_1GBYTE         (0x1D)
+#define MCF_SDRAMC_CSCFG_CSSZ_2GBYTE         (0x1E)
+#define MCF_SDRAMC_CSCFG_CSSZ_4GBYTE         (0x1F)
+#define MCF_SDRAMC_CSCFG_CSBA(x)             (((x)&0xFFF)<<0x14)
+#define MCF_SDRAMC_CSCFG_BA(x)               ((x)&0xFFF00000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDMR */
+#define MCF_SDRAMC_SDMR_CMD                  (0x10000)
+#define MCF_SDRAMC_SDMR_AD(x)                (((x)&0xFFF)<<0x12)
+#define MCF_SDRAMC_SDMR_BNKAD(x)             (((x)&0x3)<<0x1E)
+#define MCF_SDRAMC_SDMR_BK_LMR               (0)
+#define MCF_SDRAMC_SDMR_BK_LEMR              (0x40000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCR */
+#define MCF_SDRAMC_SDCR_IPALL                (0x2)
+#define MCF_SDRAMC_SDCR_IREF                 (0x4)
+#define MCF_SDRAMC_SDCR_BUFF                 (0x10)
+#define MCF_SDRAMC_SDCR_DQS_OE(x)            (((x)&0xF)<<0x8)
+#define MCF_SDRAMC_SDCR_RCNT(x)              (((x)&0x3F)<<0x10)
+#define MCF_SDRAMC_SDCR_DRIVE                (0x400000)
+#define MCF_SDRAMC_SDCR_AP                   (0x800000)
+#define MCF_SDRAMC_SDCR_MUX(x)               (((x)&0x3)<<0x18)
+#define MCF_SDRAMC_SDCR_REF                  (0x10000000)
+#define MCF_SDRAMC_SDCR_DDR                  (0x20000000)
+#define MCF_SDRAMC_SDCR_CKE                  (0x40000000)
+#define MCF_SDRAMC_SDCR_MODE_EN              (0x80000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
+#define MCF_SDRAMC_SDCFG1_WTLAT(x)           (((x)&0x7)<<0x4)
+#define MCF_SDRAMC_SDCFG1_REF2ACT(x)         (((x)&0xF)<<0x8)
+#define MCF_SDRAMC_SDCFG1_PRE2ACT(x)         (((x)&0x7)<<0xC)
+#define MCF_SDRAMC_SDCFG1_ACT2RW(x)          (((x)&0x7)<<0x10)
+#define MCF_SDRAMC_SDCFG1_RDLAT(x)           (((x)&0xF)<<0x14)
+#define MCF_SDRAMC_SDCFG1_SWT2RD(x)          (((x)&0x7)<<0x18)
+#define MCF_SDRAMC_SDCFG1_SRD2RW(x)          (((x)&0xF)<<0x1C)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
+#define MCF_SDRAMC_SDCFG2_BL(x)              (((x)&0xF)<<0x10)
+#define MCF_SDRAMC_SDCFG2_BRD2WT(x)          (((x)&0xF)<<0x14)
+#define MCF_SDRAMC_SDCFG2_BWT2RW(x)          (((x)&0xF)<<0x18)
+#define MCF_SDRAMC_SDCFG2_BRD2PRE(x)         (((x)&0xF)<<0x1C)
+
+
+#endif /* __MCF5475_SDRAMC_H__ */
--- a/tos/fpga_test/include/MCF5475_SEC.h
+++ b/tos/fpga_test/include/MCF5475_SEC.h
@@ -0,0 +1,398 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SEC_H__
+#define __MCF5475_SEC_H__
+
+
+/*********************************************************************
+*
+* Integrated Security Engine (SEC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SEC_EUACRH                       (*(volatile uint32_t*)(&_MBAR[0x21000]))
+#define MCF_SEC_EUACRL                       (*(volatile uint32_t*)(&_MBAR[0x21004]))
+#define MCF_SEC_SIMRH                        (*(volatile uint32_t*)(&_MBAR[0x21008]))
+#define MCF_SEC_SIMRL                        (*(volatile uint32_t*)(&_MBAR[0x2100C]))
+#define MCF_SEC_SISRH                        (*(volatile uint32_t*)(&_MBAR[0x21010]))
+#define MCF_SEC_SISRL                        (*(volatile uint32_t*)(&_MBAR[0x21014]))
+#define MCF_SEC_SICRH                        (*(volatile uint32_t*)(&_MBAR[0x21018]))
+#define MCF_SEC_SICRL                        (*(volatile uint32_t*)(&_MBAR[0x2101C]))
+#define MCF_SEC_SIDR                         (*(volatile uint32_t*)(&_MBAR[0x21020]))
+#define MCF_SEC_EUASRH                       (*(volatile uint32_t*)(&_MBAR[0x21028]))
+#define MCF_SEC_EUASRL                       (*(volatile uint32_t*)(&_MBAR[0x2102C]))
+#define MCF_SEC_SMCR                         (*(volatile uint32_t*)(&_MBAR[0x21030]))
+#define MCF_SEC_MEAR                         (*(volatile uint32_t*)(&_MBAR[0x21038]))
+#define MCF_SEC_CCCR0                        (*(volatile uint32_t*)(&_MBAR[0x2200C]))
+#define MCF_SEC_CCPSRH0                      (*(volatile uint32_t*)(&_MBAR[0x22010]))
+#define MCF_SEC_CCPSRL0                      (*(volatile uint32_t*)(&_MBAR[0x22014]))
+#define MCF_SEC_CDPR0                        (*(volatile uint32_t*)(&_MBAR[0x22044]))
+#define MCF_SEC_FR0                          (*(volatile uint32_t*)(&_MBAR[0x2204C]))
+#define MCF_SEC_CCCR1                        (*(volatile uint32_t*)(&_MBAR[0x2300C]))
+#define MCF_SEC_CCPSRH1                      (*(volatile uint32_t*)(&_MBAR[0x23010]))
+#define MCF_SEC_CCPSRL1                      (*(volatile uint32_t*)(&_MBAR[0x23014]))
+#define MCF_SEC_CDPR1                        (*(volatile uint32_t*)(&_MBAR[0x23044]))
+#define MCF_SEC_FR1                          (*(volatile uint32_t*)(&_MBAR[0x2304C]))
+#define MCF_SEC_AFRCR                        (*(volatile uint32_t*)(&_MBAR[0x28018]))
+#define MCF_SEC_AFSR                         (*(volatile uint32_t*)(&_MBAR[0x28028]))
+#define MCF_SEC_AFISR                        (*(volatile uint32_t*)(&_MBAR[0x28030]))
+#define MCF_SEC_AFIMR                        (*(volatile uint32_t*)(&_MBAR[0x28038]))
+#define MCF_SEC_DRCR                         (*(volatile uint32_t*)(&_MBAR[0x2A018]))
+#define MCF_SEC_DSR                          (*(volatile uint32_t*)(&_MBAR[0x2A028]))
+#define MCF_SEC_DISR                         (*(volatile uint32_t*)(&_MBAR[0x2A030]))
+#define MCF_SEC_DIMR                         (*(volatile uint32_t*)(&_MBAR[0x2A038]))
+#define MCF_SEC_MDRCR                        (*(volatile uint32_t*)(&_MBAR[0x2C018]))
+#define MCF_SEC_MDSR                         (*(volatile uint32_t*)(&_MBAR[0x2C028]))
+#define MCF_SEC_MDISR                        (*(volatile uint32_t*)(&_MBAR[0x2C030]))
+#define MCF_SEC_MDIMR                        (*(volatile uint32_t*)(&_MBAR[0x2C038]))
+#define MCF_SEC_RNGRCR                       (*(volatile uint32_t*)(&_MBAR[0x2E018]))
+#define MCF_SEC_RNGSR                        (*(volatile uint32_t*)(&_MBAR[0x2E028]))
+#define MCF_SEC_RNGISR                       (*(volatile uint32_t*)(&_MBAR[0x2E030]))
+#define MCF_SEC_RNGIMR                       (*(volatile uint32_t*)(&_MBAR[0x2E038]))
+#define MCF_SEC_AESRCR                       (*(volatile uint32_t*)(&_MBAR[0x32018]))
+#define MCF_SEC_AESSR                        (*(volatile uint32_t*)(&_MBAR[0x32028]))
+#define MCF_SEC_AESISR                       (*(volatile uint32_t*)(&_MBAR[0x32030]))
+#define MCF_SEC_AESIMR                       (*(volatile uint32_t*)(&_MBAR[0x32038]))
+#define MCF_SEC_CCCRn(x)                     (*(volatile uint32_t*)(&_MBAR[0x2200C + ((x)*0x1000)]))
+#define MCF_SEC_CCPSRHn(x)                   (*(volatile uint32_t*)(&_MBAR[0x22010 + ((x)*0x1000)]))
+#define MCF_SEC_CCPSRLn(x)                   (*(volatile uint32_t*)(&_MBAR[0x22014 + ((x)*0x1000)]))
+#define MCF_SEC_CDPRn(x)                     (*(volatile uint32_t*)(&_MBAR[0x22044 + ((x)*0x1000)]))
+#define MCF_SEC_FRn(x)                       (*(volatile uint32_t*)(&_MBAR[0x2204C + ((x)*0x1000)]))
+
+
+/* Bit definitions and macros for MCF_SEC_EUACRH */
+#define MCF_SEC_EUACRH_AFEU(x)               (((x)&0xF)<<0)
+#define MCF_SEC_EUACRH_AFFEU_NOASSIGN        (0)
+#define MCF_SEC_EUACRH_AFFEU_CHA0            (0x1)
+#define MCF_SEC_EUACRH_AFFEU_CHA1            (0x2)
+#define MCF_SEC_EUACRH_MDEU(x)               (((x)&0xF)<<0x8)
+#define MCF_SEC_EUACRH_MDEU_NOASSIGN         (0)
+#define MCF_SEC_EUACRH_MDEU_CHA0             (0x100)
+#define MCF_SEC_EUACRH_MDEU_CHA1             (0x200)
+#define MCF_SEC_EUACRH_RNG(x)                (((x)&0xF)<<0x18)
+#define MCF_SEC_EUACRH_RNG_NOASSIGN          (0)
+#define MCF_SEC_EUACRH_RNG_CHA0              (0x1000000)
+#define MCF_SEC_EUACRH_RNG_CHA1              (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_EUACRL */
+#define MCF_SEC_EUACRL_AESU(x)               (((x)&0xF)<<0x10)
+#define MCF_SEC_EUACRL_AESU_NOASSIGN         (0)
+#define MCF_SEC_EUACRL_AESU_CHA0             (0x10000)
+#define MCF_SEC_EUACRL_AESU_CHA1             (0x20000)
+#define MCF_SEC_EUACRL_DEU(x)                (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SEC_SIMRH */
+#define MCF_SEC_SIMRH_AERR                   (0x8000000)
+#define MCF_SEC_SIMRH_CHA_0_DN               (0x10000000)
+#define MCF_SEC_SIMRH_CHA_0_ERR              (0x20000000)
+#define MCF_SEC_SIMRH_CHA_1_DN               (0x40000000)
+#define MCF_SEC_SIMRH_CHA_1_ERR              (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_SIMRL */
+#define MCF_SEC_SIMRL_TEA                    (0x40)
+#define MCF_SEC_SIMRL_DEU_DN                 (0x100)
+#define MCF_SEC_SIMRL_DEU_ERR                (0x200)
+#define MCF_SEC_SIMRL_AESU_DN                (0x1000)
+#define MCF_SEC_SIMRL_AESU_ERR               (0x2000)
+#define MCF_SEC_SIMRL_MDEU_DN                (0x10000)
+#define MCF_SEC_SIMRL_MDEU_ERR               (0x20000)
+#define MCF_SEC_SIMRL_AFEU_DN                (0x100000)
+#define MCF_SEC_SIMRL_AFEU_ERR               (0x200000)
+#define MCF_SEC_SIMRL_RNG_DN                 (0x1000000)
+#define MCF_SEC_SIMRL_RNG_ERR                (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_SISRH */
+#define MCF_SEC_SISRH_AERR                   (0x8000000)
+#define MCF_SEC_SISRH_CHA_0_DN               (0x10000000)
+#define MCF_SEC_SISRH_CHA_0_ERR              (0x20000000)
+#define MCF_SEC_SISRH_CHA_1_DN               (0x40000000)
+#define MCF_SEC_SISRH_CHA_1_ERR              (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_SISRL */
+#define MCF_SEC_SISRL_TEA                    (0x40)
+#define MCF_SEC_SISRL_DEU_DN                 (0x100)
+#define MCF_SEC_SISRL_DEU_ERR                (0x200)
+#define MCF_SEC_SISRL_AESU_DN                (0x1000)
+#define MCF_SEC_SISRL_AESU_ERR               (0x2000)
+#define MCF_SEC_SISRL_MDEU_DN                (0x10000)
+#define MCF_SEC_SISRL_MDEU_ERR               (0x20000)
+#define MCF_SEC_SISRL_AFEU_DN                (0x100000)
+#define MCF_SEC_SISRL_AFEU_ERR               (0x200000)
+#define MCF_SEC_SISRL_RNG_DN                 (0x1000000)
+#define MCF_SEC_SISRL_RNG_ERR                (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_SICRH */
+#define MCF_SEC_SICRH_AERR                   (0x8000000)
+#define MCF_SEC_SICRH_CHA_0_DN               (0x10000000)
+#define MCF_SEC_SICRH_CHA_0_ERR              (0x20000000)
+#define MCF_SEC_SICRH_CHA_1_DN               (0x40000000)
+#define MCF_SEC_SICRH_CHA_1_ERR              (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_SICRL */
+#define MCF_SEC_SICRL_TEA                    (0x40)
+#define MCF_SEC_SICRL_DEU_DN                 (0x100)
+#define MCF_SEC_SICRL_DEU_ERR                (0x200)
+#define MCF_SEC_SICRL_AESU_DN                (0x1000)
+#define MCF_SEC_SICRL_AESU_ERR               (0x2000)
+#define MCF_SEC_SICRL_MDEU_DN                (0x10000)
+#define MCF_SEC_SICRL_MDEU_ERR               (0x20000)
+#define MCF_SEC_SICRL_AFEU_DN                (0x100000)
+#define MCF_SEC_SICRL_AFEU_ERR               (0x200000)
+#define MCF_SEC_SICRL_RNG_DN                 (0x1000000)
+#define MCF_SEC_SICRL_RNG_ERR                (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_SIDR */
+#define MCF_SEC_SIDR_VERSION(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_EUASRH */
+#define MCF_SEC_EUASRH_AFEU(x)               (((x)&0xF)<<0)
+#define MCF_SEC_EUASRH_MDEU(x)               (((x)&0xF)<<0x8)
+#define MCF_SEC_EUASRH_RNG(x)                (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SEC_EUASRL */
+#define MCF_SEC_EUASRL_AESU(x)               (((x)&0xF)<<0x10)
+#define MCF_SEC_EUASRL_DEU(x)                (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SEC_SMCR */
+#define MCF_SEC_SMCR_CURR_CHAN(x)            (((x)&0xF)<<0x4)
+#define MCF_SEC_SMCR_CURR_CHAN_1             (0x10)
+#define MCF_SEC_SMCR_CURR_CHAN_2             (0x20)
+#define MCF_SEC_SMCR_SWR                     (0x1000000)
+
+/* Bit definitions and macros for MCF_SEC_MEAR */
+#define MCF_SEC_MEAR_ADDRESS(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_CCCRn */
+#define MCF_SEC_CCCRn_RST                    (0x1)
+#define MCF_SEC_CCCRn_CDIE                   (0x2)
+#define MCF_SEC_CCCRn_NT                     (0x4)
+#define MCF_SEC_CCCRn_NE                     (0x8)
+#define MCF_SEC_CCCRn_WE                     (0x10)
+#define MCF_SEC_CCCRn_BURST_SIZE(x)          (((x)&0x7)<<0x8)
+#define MCF_SEC_CCCRn_BURST_SIZE_2           (0)
+#define MCF_SEC_CCCRn_BURST_SIZE_8           (0x100)
+#define MCF_SEC_CCCRn_BURST_SIZE_16          (0x200)
+#define MCF_SEC_CCCRn_BURST_SIZE_24          (0x300)
+#define MCF_SEC_CCCRn_BURST_SIZE_32          (0x400)
+#define MCF_SEC_CCCRn_BURST_SIZE_40          (0x500)
+#define MCF_SEC_CCCRn_BURST_SIZE_48          (0x600)
+#define MCF_SEC_CCCRn_BURST_SIZE_56          (0x700)
+
+/* Bit definitions and macros for MCF_SEC_CCPSRHn */
+#define MCF_SEC_CCPSRHn_STATE(x)             (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_CCPSRLn */
+#define MCF_SEC_CCPSRLn_PAIR_PTR(x)          (((x)&0xFF)<<0)
+#define MCF_SEC_CCPSRLn_EUERR                (0x100)
+#define MCF_SEC_CCPSRLn_SERR                 (0x200)
+#define MCF_SEC_CCPSRLn_DERR                 (0x400)
+#define MCF_SEC_CCPSRLn_PERR                 (0x1000)
+#define MCF_SEC_CCPSRLn_TEA                  (0x2000)
+#define MCF_SEC_CCPSRLn_SD                   (0x10000)
+#define MCF_SEC_CCPSRLn_PD                   (0x20000)
+#define MCF_SEC_CCPSRLn_SRD                  (0x40000)
+#define MCF_SEC_CCPSRLn_PRD                  (0x80000)
+#define MCF_SEC_CCPSRLn_SG                   (0x100000)
+#define MCF_SEC_CCPSRLn_PG                   (0x200000)
+#define MCF_SEC_CCPSRLn_SR                   (0x400000)
+#define MCF_SEC_CCPSRLn_PR                   (0x800000)
+#define MCF_SEC_CCPSRLn_MO                   (0x1000000)
+#define MCF_SEC_CCPSRLn_MI                   (0x2000000)
+#define MCF_SEC_CCPSRLn_STAT                 (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_CDPRn */
+#define MCF_SEC_CDPRn_CDP(x)                 (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_FRn */
+#define MCF_SEC_FRn_FETCH_ADDR(x)            (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_AFRCR */
+#define MCF_SEC_AFRCR_SR                     (0x1000000)
+#define MCF_SEC_AFRCR_MI                     (0x2000000)
+#define MCF_SEC_AFRCR_RI                     (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_AFSR */
+#define MCF_SEC_AFSR_RD                      (0x1000000)
+#define MCF_SEC_AFSR_ID                      (0x2000000)
+#define MCF_SEC_AFSR_IE                      (0x4000000)
+#define MCF_SEC_AFSR_OFR                     (0x8000000)
+#define MCF_SEC_AFSR_IFW                     (0x10000000)
+#define MCF_SEC_AFSR_HALT                    (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_AFISR */
+#define MCF_SEC_AFISR_DSE                    (0x10000)
+#define MCF_SEC_AFISR_KSE                    (0x20000)
+#define MCF_SEC_AFISR_CE                     (0x40000)
+#define MCF_SEC_AFISR_ERE                    (0x80000)
+#define MCF_SEC_AFISR_IE                     (0x100000)
+#define MCF_SEC_AFISR_OFU                    (0x2000000)
+#define MCF_SEC_AFISR_IFO                    (0x4000000)
+#define MCF_SEC_AFISR_IFE                    (0x10000000)
+#define MCF_SEC_AFISR_OFE                    (0x20000000)
+#define MCF_SEC_AFISR_AE                     (0x40000000)
+#define MCF_SEC_AFISR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_AFIMR */
+#define MCF_SEC_AFIMR_DSE                    (0x10000)
+#define MCF_SEC_AFIMR_KSE                    (0x20000)
+#define MCF_SEC_AFIMR_CE                     (0x40000)
+#define MCF_SEC_AFIMR_ERE                    (0x80000)
+#define MCF_SEC_AFIMR_IE                     (0x100000)
+#define MCF_SEC_AFIMR_OFU                    (0x2000000)
+#define MCF_SEC_AFIMR_IFO                    (0x4000000)
+#define MCF_SEC_AFIMR_IFE                    (0x10000000)
+#define MCF_SEC_AFIMR_OFE                    (0x20000000)
+#define MCF_SEC_AFIMR_AE                     (0x40000000)
+#define MCF_SEC_AFIMR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_DRCR */
+#define MCF_SEC_DRCR_SR                      (0x1000000)
+#define MCF_SEC_DRCR_MI                      (0x2000000)
+#define MCF_SEC_DRCR_RI                      (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_DSR */
+#define MCF_SEC_DSR_RD                       (0x1000000)
+#define MCF_SEC_DSR_ID                       (0x2000000)
+#define MCF_SEC_DSR_IE                       (0x4000000)
+#define MCF_SEC_DSR_OFR                      (0x8000000)
+#define MCF_SEC_DSR_IFW                      (0x10000000)
+#define MCF_SEC_DSR_HALT                     (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_DISR */
+#define MCF_SEC_DISR_DSE                     (0x10000)
+#define MCF_SEC_DISR_KSE                     (0x20000)
+#define MCF_SEC_DISR_CE                      (0x40000)
+#define MCF_SEC_DISR_ERE                     (0x80000)
+#define MCF_SEC_DISR_IE                      (0x100000)
+#define MCF_SEC_DISR_KPE                     (0x200000)
+#define MCF_SEC_DISR_OFU                     (0x2000000)
+#define MCF_SEC_DISR_IFO                     (0x4000000)
+#define MCF_SEC_DISR_IFE                     (0x10000000)
+#define MCF_SEC_DISR_OFE                     (0x20000000)
+#define MCF_SEC_DISR_AE                      (0x40000000)
+#define MCF_SEC_DISR_ME                      (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_DIMR */
+#define MCF_SEC_DIMR_DSE                     (0x10000)
+#define MCF_SEC_DIMR_KSE                     (0x20000)
+#define MCF_SEC_DIMR_CE                      (0x40000)
+#define MCF_SEC_DIMR_ERE                     (0x80000)
+#define MCF_SEC_DIMR_IE                      (0x100000)
+#define MCF_SEC_DIMR_KPE                     (0x200000)
+#define MCF_SEC_DIMR_OFU                     (0x2000000)
+#define MCF_SEC_DIMR_IFO                     (0x4000000)
+#define MCF_SEC_DIMR_IFE                     (0x10000000)
+#define MCF_SEC_DIMR_OFE                     (0x20000000)
+#define MCF_SEC_DIMR_AE                      (0x40000000)
+#define MCF_SEC_DIMR_ME                      (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_MDRCR */
+#define MCF_SEC_MDRCR_SR                     (0x1000000)
+#define MCF_SEC_MDRCR_MI                     (0x2000000)
+#define MCF_SEC_MDRCR_RI                     (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_MDSR */
+#define MCF_SEC_MDSR_RD                      (0x1000000)
+#define MCF_SEC_MDSR_ID                      (0x2000000)
+#define MCF_SEC_MDSR_IE                      (0x4000000)
+#define MCF_SEC_MDSR_IFW                     (0x10000000)
+#define MCF_SEC_MDSR_HALT                    (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_MDISR */
+#define MCF_SEC_MDISR_DSE                    (0x10000)
+#define MCF_SEC_MDISR_KSE                    (0x20000)
+#define MCF_SEC_MDISR_CE                     (0x40000)
+#define MCF_SEC_MDISR_ERE                    (0x80000)
+#define MCF_SEC_MDISR_IE                     (0x100000)
+#define MCF_SEC_MDISR_IFO                    (0x4000000)
+#define MCF_SEC_MDISR_AE                     (0x40000000)
+#define MCF_SEC_MDISR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_MDIMR */
+#define MCF_SEC_MDIMR_DSE                    (0x10000)
+#define MCF_SEC_MDIMR_KSE                    (0x20000)
+#define MCF_SEC_MDIMR_CE                     (0x40000)
+#define MCF_SEC_MDIMR_ERE                    (0x80000)
+#define MCF_SEC_MDIMR_IE                     (0x100000)
+#define MCF_SEC_MDIMR_IFO                    (0x4000000)
+#define MCF_SEC_MDIMR_AE                     (0x40000000)
+#define MCF_SEC_MDIMR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGRCR */
+#define MCF_SEC_RNGRCR_SR                    (0x1000000)
+#define MCF_SEC_RNGRCR_MI                    (0x2000000)
+#define MCF_SEC_RNGRCR_RI                    (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGSR */
+#define MCF_SEC_RNGSR_RD                     (0x1000000)
+#define MCF_SEC_RNGSR_IE                     (0x4000000)
+#define MCF_SEC_RNGSR_OFR                    (0x8000000)
+#define MCF_SEC_RNGSR_HALT                   (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGISR */
+#define MCF_SEC_RNGISR_IE                    (0x100000)
+#define MCF_SEC_RNGISR_OFU                   (0x2000000)
+#define MCF_SEC_RNGISR_AE                    (0x40000000)
+#define MCF_SEC_RNGISR_ME                    (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGIMR */
+#define MCF_SEC_RNGIMR_IE                    (0x100000)
+#define MCF_SEC_RNGIMR_OFU                   (0x2000000)
+#define MCF_SEC_RNGIMR_AE                    (0x40000000)
+#define MCF_SEC_RNGIMR_ME                    (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_AESRCR */
+#define MCF_SEC_AESRCR_SR                    (0x1000000)
+#define MCF_SEC_AESRCR_MI                    (0x2000000)
+#define MCF_SEC_AESRCR_RI                    (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_AESSR */
+#define MCF_SEC_AESSR_RD                     (0x1000000)
+#define MCF_SEC_AESSR_ID                     (0x2000000)
+#define MCF_SEC_AESSR_IE                     (0x4000000)
+#define MCF_SEC_AESSR_OFR                    (0x8000000)
+#define MCF_SEC_AESSR_IFW                    (0x10000000)
+#define MCF_SEC_AESSR_HALT                   (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_AESISR */
+#define MCF_SEC_AESISR_DSE                   (0x10000)
+#define MCF_SEC_AESISR_KSE                   (0x20000)
+#define MCF_SEC_AESISR_CE                    (0x40000)
+#define MCF_SEC_AESISR_ERE                   (0x80000)
+#define MCF_SEC_AESISR_IE                    (0x100000)
+#define MCF_SEC_AESISR_OFU                   (0x2000000)
+#define MCF_SEC_AESISR_IFO                   (0x4000000)
+#define MCF_SEC_AESISR_IFE                   (0x10000000)
+#define MCF_SEC_AESISR_OFE                   (0x20000000)
+#define MCF_SEC_AESISR_AE                    (0x40000000)
+#define MCF_SEC_AESISR_ME                    (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_AESIMR */
+#define MCF_SEC_AESIMR_DSE                   (0x10000)
+#define MCF_SEC_AESIMR_KSE                   (0x20000)
+#define MCF_SEC_AESIMR_CE                    (0x40000)
+#define MCF_SEC_AESIMR_ERE                   (0x80000)
+#define MCF_SEC_AESIMR_IE                    (0x100000)
+#define MCF_SEC_AESIMR_OFU                   (0x2000000)
+#define MCF_SEC_AESIMR_IFO                   (0x4000000)
+#define MCF_SEC_AESIMR_IFE                   (0x10000000)
+#define MCF_SEC_AESIMR_OFE                   (0x20000000)
+#define MCF_SEC_AESIMR_AE                    (0x40000000)
+#define MCF_SEC_AESIMR_ME                    (0x80000000)
+
+
+#endif /* __MCF5475_SEC_H__ */
--- a/tos/fpga_test/include/MCF5475_SIU.h
+++ b/tos/fpga_test/include/MCF5475_SIU.h
@@ -0,0 +1,67 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SIU_H__
+#define __MCF5475_SIU_H__
+
+
+/*********************************************************************
+*
+* System Integration Unit (SIU)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SIU_SBCR                         (*(volatile uint32_t*)(&_MBAR[0x10]))
+#define MCF_SIU_SECSACR                      (*(volatile uint32_t*)(&_MBAR[0x38]))
+#define MCF_SIU_RSR                          (*(volatile uint32_t*)(&_MBAR[0x44]))
+#define MCF_SIU_JTAGID                       (*(volatile uint32_t*)(&_MBAR[0x50]))
+
+
+/* Bit definitions and macros for MCF_SIU_SBCR */
+#define MCF_SIU_SBCR_PIN2DSPI                (0x8000000)
+#define MCF_SIU_SBCR_DMA2CPU                 (0x10000000)
+#define MCF_SIU_SBCR_CPU2DMA                 (0x20000000)
+#define MCF_SIU_SBCR_PIN2DMA                 (0x40000000)
+#define MCF_SIU_SBCR_PIN2CPU                 (0x80000000)
+
+/* Bit definitions and macros for MCF_SIU_SECSACR */
+#define MCF_SIU_SECSACR_SEQEN                (0x1)
+
+/* Bit definitions and macros for MCF_SIU_RSR */
+#define MCF_SIU_RSR_RST                      (0x1)
+#define MCF_SIU_RSR_RSTWD                    (0x2)
+#define MCF_SIU_RSR_RSTJTG                   (0x8)
+
+/* Bit definitions and macros for MCF_SIU_JTAGID */
+#define MCF_SIU_JTAGID_JTAGID(x)             (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SIU_JTAGID */
+#define MCF_SIU_JTAGID_REV          (0xF0000000)
+#define MCF_SIU_JTAGID_PROCESSOR    (0x0FFFFFFF)
+#define MCF_SIU_JTAGID_MCF5485      (0x0800C01D)
+#define MCF_SIU_JTAGID_MCF5484      (0x0800D01D)
+#define MCF_SIU_JTAGID_MCF5483      (0x0800E01D)
+#define MCF_SIU_JTAGID_MCF5482      (0x0800F01D)
+#define MCF_SIU_JTAGID_MCF5481      (0x0801001D)
+#define MCF_SIU_JTAGID_MCF5480      (0x0801101D)
+#define MCF_SIU_JTAGID_MCF5475      (0x0801201D)
+#define MCF_SIU_JTAGID_MCF5474      (0x0801301D)
+#define MCF_SIU_JTAGID_MCF5473      (0x0801401D)
+#define MCF_SIU_JTAGID_MCF5472      (0x0801501D)
+#define MCF_SIU_JTAGID_MCF5471      (0x0801601D)
+#define MCF_SIU_JTAGID_MCF5470      (0x0801701D)
+
+#endif /* __MCF5475_SIU_H__ */
--- a/tos/fpga_test/include/MCF5475_SLT.h
+++ b/tos/fpga_test/include/MCF5475_SLT.h
@@ -0,0 +1,59 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SLT_H__
+#define __MCF5475_SLT_H__
+
+
+/*********************************************************************
+*
+* Slice Timers (SLT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SLT0_STCNT                       (*(volatile uint32_t*)(&_MBAR[0x900]))
+#define MCF_SLT0_SCR                         (*(volatile uint32_t*)(&_MBAR[0x904]))
+#define MCF_SLT0_SCNT                        (*(volatile uint32_t*)(&_MBAR[0x908]))
+#define MCF_SLT0_SSR                         (*(volatile uint32_t*)(&_MBAR[0x90C]))
+
+#define MCF_SLT1_STCNT                       (*(volatile uint32_t*)(&_MBAR[0x910]))
+#define MCF_SLT1_SCR                         (*(volatile uint32_t*)(&_MBAR[0x914]))
+#define MCF_SLT1_SCNT                        (*(volatile uint32_t*)(&_MBAR[0x918]))
+#define MCF_SLT1_SSR                         (*(volatile uint32_t*)(&_MBAR[0x91C]))
+
+#define MCF_SLT_STCNT(x)                     (*(volatile uint32_t*)(&_MBAR[0x900 + ((x)*0x10)]))
+#define MCF_SLT_SCR(x)                       (*(volatile uint32_t*)(&_MBAR[0x904 + ((x)*0x10)]))
+#define MCF_SLT_SCNT(x)                      (*(volatile int32_t*)(&_MBAR[0x908 + ((x)*0x10)]))
+#define MCF_SLT_SSR(x)                       (*(volatile uint32_t*)(&_MBAR[0x90C + ((x)*0x10)]))
+
+
+/* Bit definitions and macros for MCF_SLT_STCNT */
+#define MCF_SLT_STCNT_TC(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SLT_SCR */
+#define MCF_SLT_SCR_TEN                      (0x1000000)
+#define MCF_SLT_SCR_IEN                      (0x2000000)
+#define MCF_SLT_SCR_RUN                      (0x4000000)
+
+/* Bit definitions and macros for MCF_SLT_SCNT */
+#define MCF_SLT_SCNT_CNT(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SLT_SSR */
+#define MCF_SLT_SSR_ST                       (0x1000000)
+#define MCF_SLT_SSR_BE                       (0x2000000)
+
+
+#endif /* __MCF5475_SLT_H__ */
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Markus Fröschle	a0a6a36e0c	make FireTOS always cold boot (clear sys vars)	2016-08-14 09:55:28 +00:00
Markus Fröschle	d28c05918e	bump version	2016-08-14 09:09:12 +00:00
Markus Fröschle	9653fa601e	disabled debug output. This is version 0.88, "official" release	2016-08-14 08:16:20 +00:00
Markus Fröschle	b2015265e2	Fixed comments (that were obviously copy/pasted wrongly long ago)	2016-08-02 08:45:26 +00:00
Markus Fröschle	bc4a45aba4	did some beautifying on the code	2016-07-31 19:13:16 +00:00
Markus Fröschle	1c64feb4cb	add fpga_test	2016-07-30 09:55:11 +00:00
Markus Fröschle	2fbbbcc072	add fpga_test tos prg	2016-07-30 09:54:42 +00:00
Markus Fröschle	78b0f1133f	back to original VRAM address	2016-06-09 20:57:59 +00:00
Markus Fröschle	1feb4f2c7a	do more FPGA register tests	2016-06-09 18:04:17 +00:00
Markus Fröschle	bac9e62074	cleanup vmem_test	2016-06-06 05:19:25 +00:00
Markus Fröschle	eb7009ccfc	added memory test for VHDL config	2016-06-04 21:16:01 +00:00
Markus Fröschle	5edc91aa9f	general overhaul. Prepare for smaller pagesize	2016-04-17 19:37:19 +00:00
Markus Fröschle	98b9803ddf	make set_ipl() a true function (was inlined before)	2016-04-17 18:21:09 +00:00
Markus Fröschle	9a46235b91	experimental: directly jump through bus error vector on bus error	2016-04-17 18:20:28 +00:00
Markus Fröschle	a280a8f901	introduce SIZE_DEFAULT and MMU_PAGESIZE_DEFAULT to make experiments with smaller pagesize more versatile	2016-04-17 18:19:21 +00:00
Markus Fröschle	bff912704e	modify to _not_ inline set_ipl()	2016-04-17 18:17:55 +00:00
Markus Fröschle	3cc79212a3	changed return type to uint32_t instead of int32_t	2016-04-17 18:16:48 +00:00
Markus Fröschle	478563479a	activate m68k-elf compile again	2016-04-17 18:15:13 +00:00
Markus Fröschle	d2271ca7d9	fix wrong variable for ram target mapfile generation	2016-04-16 12:01:26 +00:00
Markus Fröschle	f06bf5fe8e	add missing include of pci_errata.h enable -O2 optimization	2016-04-04 19:04:15 +00:00
Markus Fröschle	a409f40593	fix failed alignment of pci_errata_xxx() functions which caused the code to hang when compiled with m68k-atari-mint-gcc	2016-04-04 09:31:25 +00:00
Markus Fröschle	e73333d893	put libcmini dependencies into a variable, cleanup clean target	2016-04-03 19:04:18 +00:00
Markus Fröschle	627aa0c2c4	modify 1st page to cache mode PASSTHROUGH	2016-04-02 18:56:20 +00:00
Markus Fröschle	181a83db5a	fix ST RAM values for initial SP & PC to allow FreeMint reboots on CTRL-ALT-DELETE	2016-04-02 10:39:26 +00:00
Markus Fröschle	11628b7167	skip FPGA config load at reset ("warm start")	2016-04-02 08:04:26 +00:00
David Gálvez	a97cebe140	Post increment makes that we send 65 bytes. Reported by Daroou.	2016-02-16 15:21:30 +00:00
David Gálvez	4c765b2512	Move functions declaration to header file	2016-02-07 18:35:04 +00:00
David Gálvez	0658bde430	Fix date and time saving to PIC process. Use wrapped functions to acces PIC registers.	2016-02-07 14:20:22 +00:00
Markus Fröschle	fe2e85b984	fix PSC3 interrupt level and prio fix PIC communication in PSC3 interrupt handler	2016-02-07 12:28:13 +00:00
Markus Fröschle	88e9fe0007	fix wrong IRQ priority for PCI arbiter interrupt (was identical to DMA interrupt)	2016-02-07 10:27:42 +00:00
Markus Fröschle	7d59124531	avoid FireTOS hang on boot	2016-01-30 16:00:02 +00:00
Markus Fröschle	640126b42e	fix comments	2015-11-21 07:39:49 +00:00
Markus Fröschle	a1572c4aed	fix crash on FireTOS	2015-11-20 21:45:59 +00:00
Markus Fröschle	7536b088e8	fix comment	2015-11-20 21:35:46 +00:00
Markus Fröschle	e9c21377d8	new revision of BaS native PCI driver that supports find_pci_device() and find_pci_classcode() functions from TOS	2015-11-20 21:25:07 +00:00
Markus Fröschle	54cd5c8151	add PCI driver interface enumeration routine	2015-11-20 19:25:57 +00:00
Markus Fröschle	3fc79b9c84	make pci_test skeleton compile	2015-11-20 18:17:35 +00:00
Markus Fröschle	4e6fa096f7	add pci_test TOS program build directory	2015-11-20 18:13:11 +00:00
Markus Fröschle	23badbe934	add pci_test TOS application	2015-11-20 18:12:11 +00:00
Markus Fröschle	e65a36765b	make separate section to enable external interrupts on the MCF54455	2015-11-20 12:43:04 +00:00
Markus Fröschle	ff7af9b57b	initialize handles array	2015-11-20 12:35:15 +00:00
Markus Fröschle	7fcb150791	fix __MBAR and __RAMBAR for MCF54455	2015-11-20 12:34:17 +00:00
Markus Fröschle	64e994e440	make specific -mcpu settings for the three supported platforms	2015-11-20 12:32:18 +00:00
Markus Fröschle	cbee753127	add diagnostics messages to find cause of hang	2015-11-20 07:08:09 +00:00
Markus Fröschle	dd5fb8ab2e	fix consistency #if and #if defined()	2015-11-19 20:27:49 +00:00
Markus Fröschle	46c940ea2e	fix consistancy (#ifdef, #if defined(), #if)	2015-11-19 19:00:44 +00:00
Markus Fröschle	af3bd32d41	reformat	2015-11-16 15:20:43 +00:00
Markus Fröschle	ca2e65ad49	more tests	2015-10-31 20:53:59 +00:00
Markus Fröschle	ccd044c7d0	fix Atari specific special character codes	2015-10-17 11:30:09 +00:00
Markus Fröschle	6445903e1b	use Supexec() instead of Super() to retrieve driver interface in supervisor mode	2015-10-13 06:00:23 +00:00
Markus Fröschle	87bf20c6bd	clarify comment	2015-10-13 05:21:53 +00:00
Markus Fröschle	d118796306	reformat	2015-10-13 05:14:06 +00:00
Markus Fröschle	35d879b698	reformat	2015-10-11 19:39:49 +00:00
Markus Fröschle	a14f3a8b59	reformatted	2015-10-11 19:13:02 +00:00
Markus Fröschle	479dd69eb6	reformatted	2015-10-11 18:47:48 +00:00
Markus Fröschle	0e5491d973	new function enable_pci_interrupts() (defer PCI interrupt activation until after PCI scan)	2015-10-11 18:31:07 +00:00
Markus Fröschle	352bf75f85	fix to only reprogram the interrupt controller if neccessary	2015-10-11 18:27:41 +00:00
Markus Fröschle	7058762c28	reformatting	2015-10-11 10:45:26 +00:00
Markus Fröschle	c23d4b76bf	fix a problem where enabling the spurious interrupt handler screwed up interrupt controller registers	2015-10-11 05:54:45 +00:00
Markus Fröschle	e46516fad9	fix a problem where nested interrupts caused networking to hang	2015-10-11 05:52:58 +00:00
Markus Fröschle	4f8943ff0b	disable debugging output in release version	2015-10-11 05:52:07 +00:00
Markus Fröschle	34488eabae	fix invalid parameter type	2015-10-03 16:21:50 +00:00
Markus Fröschle	bd6141f7b3	fix discrepancies and disable PCI interrupts (temporarily) seems to increase stability	2015-10-03 16:12:17 +00:00
Markus Fröschle	b13413e60e	temporary disabled PCI interrupts	2015-10-03 08:31:58 +00:00
Markus Fröschle	dad6a94b5e	modified for new doxygen version	2015-04-07 10:24:20 +00:00
Markus Fröschle	c77dac9a26	fixed wrong function prototype	2015-04-07 10:23:46 +00:00
Markus Fröschle	c67323540c	fixed tabs	2015-04-07 10:16:55 +00:00
Markus Fröschle	f8a3699c11	make unsigned/signed usage more consistent	2015-04-07 10:06:14 +00:00
Markus Fröschle	6ed85c93c4	suppress compiler warning when doing non-debug build	2015-04-07 10:04:31 +00:00
Markus Fröschle	f5b6b0cdb1	removed non-UTF8 char that made it into the file somehow	2015-04-07 10:03:20 +00:00
Markus Fröschle	9f03b891fd	modified Makefiles in tos subdir stripped down vmem_test to be able to test a DDR controller only FPGA config	2015-04-05 09:05:11 +00:00
Markus Fröschle	0de57bc247	repaired jtagwait magic type conflict added "native PCI" driver interface	2015-04-03 14:28:41 +00:00
Markus Fröschle	383b42ee4c	removed hardcoded path to libgcc	2015-02-28 15:54:05 +00:00
Markus Fröschle	f9d48faf9a	removed doubly defined typedef	2015-02-28 15:35:02 +00:00
Markus Fröschle	73e0703a13	modified PCI configuration, RADEON card does not configure correctly (MMIO space not accessible)	2015-02-22 19:46:16 +00:00
Markus Fröschle	c609defb84	reformatted	2015-02-18 21:36:16 +00:00
Markus Fröschle	769194aa45	compiles again, pci bios emulator not tested	2015-02-18 15:59:52 +00:00
Markus Fröschle	0dae8b8d48	fixed emulator "struct emu"-dependent calls	2015-02-18 15:54:14 +00:00
Markus Fröschle	27cdc3bf25	fixed remaining errors except one	2015-02-17 19:57:58 +00:00
Markus Fröschle	cb8eb08d86	modified to support NetBSD x86emu	2015-02-17 19:29:20 +00:00
Markus Fröschle	27951d68c4	included setjmp()/longjump() into emulator	2015-02-17 16:35:30 +00:00
Markus Fröschle	13209134c3	added setjmp()/longjmp() (used by NetBSD x86 emulator) modified x86pcibios.c to work with NetBSD x86 emulator	2015-02-17 14:43:11 +00:00
Markus Fröschle	5cf48838c6	fixed to work for COMPILE_ELF=N again	2015-02-17 11:21:41 +00:00
Markus Fröschle	ed5f1fb64c	added libgcc_helper.S to retarget libgcc calls for 64 bit multiplication/division	2015-02-17 11:12:29 +00:00
Markus Fröschle	910f34f48e	added comments about FPGA_JTAG_LOADED	2015-02-17 07:27:20 +00:00
Markus Fröschle	f2f182c493	still problems with libgcc.a long long symbols	2015-02-17 07:22:02 +00:00
Markus Fröschle	a7eea51b60	replaced Firetos x86 emulator with the optimised NetBSD version	2015-02-16 22:14:44 +00:00
Markus Fröschle	69e6becb2a	fixed formatting	2015-02-15 10:33:22 +00:00
Markus Fröschle	168e1f439c	modified to expose the PCI "native" driver interface (this is different from the PCIBIOS) to TOS	2015-02-14 08:45:59 +00:00
Markus Fröschle	64b46fd15d	fixed (wrong) comment	2015-01-31 06:32:41 +00:00
Markus Fröschle	e1fce476c0	made m548xLITE board run again	2015-01-24 10:14:39 +00:00
Markus Fröschle	e2bc61b85b	removed vsync and hsync interrupt handling from fbee interrupt handler	2015-01-19 12:32:22 +00:00
Markus Fröschle	400f28ef2f	reformatted	2015-01-18 21:05:05 +00:00
Markus Fröschle	62d68ec12e	Networking finally works stable, although not really clean. Something causes spurious interrupts and a handler for this fixed it for now.	2015-01-18 19:47:31 +00:00
Markus Fröschle	a5c06bf765	modified to load the correct emutos	2015-01-17 21:48:50 +00:00
Markus Fröschle	95a6d3067f	modified debug print	2015-01-17 21:47:56 +00:00
Markus Fröschle	9b382ead25	modified for m548x irq5	2015-01-17 21:47:12 +00:00
Markus Fröschle	b88351c464	modified FBC for m5484x CPLD CompactFlash access	2015-01-17 21:46:04 +00:00
Markus Fröschle	14f0b58d2d	enabled m548x debugging	2015-01-17 21:44:56 +00:00