add missing project file

makes it basically working, but still some pixel errors

DSP/DSP.vhd

@@ -1,18 +1,18 @@
--- WARNING: Do NOT edit the input and output ports in this file in a text
+-- WARNING: Do NOT edit the input AND output ports in this file in a text
 -- editor if you plan to continue editing the block that represents it in
 -- the Block Editor! File corruption is VERY likely to occur.
 
 -- Copyright (C) 1991-2008 Altera Corporation
 -- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
+-- AND other software AND tools, AND its AMPP partner logic 
+-- functions, AND any output files from any of the foregoing 
+-- (including device programming or simulation files), AND any 
 -- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
+-- to the terms AND conditions of the Altera Program License 
 -- Subscription Agreement, Altera MegaCore Function License 
 -- Agreement, or other applicable license agreement, including, 
 -- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
+-- programming logic devices manufactured by Altera AND sold by 
 -- Altera or its authorized distributors.  Please refer to the 
 -- applicable agreement for further details.
 
@@ -21,59 +21,57 @@
 -- Created on Tue Sep 08 16:24:57 2009
 
 LIBRARY ieee;
-USE ieee.std_logic_1164.all;
+    USE ieee.std_logic_1164.all;
 
 
 --  Entity Declaration
 
-ENTITY DSP IS
+ENTITY dsp IS
 	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
 	PORT
 	(
-		CLK33M : IN STD_LOGIC;
-		MAIN_CLK : IN STD_LOGIC;
-		nFB_OE : IN STD_LOGIC;
-		nFB_WR : IN STD_LOGIC;
-		nFB_CS1 : IN STD_LOGIC;
-		nFB_CS2 : IN STD_LOGIC;
-		FB_SIZE0 : IN STD_LOGIC;
-		FB_SIZE1 : IN STD_LOGIC;
-		nFB_BURST : IN STD_LOGIC;
-		FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
-		nRSTO : IN STD_LOGIC;
-		nFB_CS3 : IN STD_LOGIC;
-		nSRCS : INOUT STD_LOGIC;
-		nSRBLE : OUT STD_LOGIC;
-		nSRBHE : OUT STD_LOGIC;
-		nSRWE : OUT STD_LOGIC;
-		nSROE : OUT STD_LOGIC;
-		DSP_INT : OUT STD_LOGIC;
-		DSP_TA : OUT STD_LOGIC;
-		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
-		IO : INOUT STD_LOGIC_VECTOR(17 downto 0);
-		SRD : INOUT STD_LOGIC_VECTOR(15 downto 0)
+		CLK33M      : IN std_logic;
+		MAIN_CLK    : IN std_logic;
+		nFB_OE      : IN std_logic;
+		nFB_WR      : IN std_logic;
+		nFB_CS1     : IN std_logic;
+		nFB_CS2     : IN std_logic;
+		FB_SIZE0    : IN std_logic;
+		FB_SIZE1    : IN std_logic;
+		nFB_BURST   : IN std_logic;
+		FB_ADR      : IN std_logic_vector(31 DOWNTO 0);
+		nRSTO       : IN std_logic;
+		nFB_CS3     : IN std_logic;
+		nSRCS       : INOUT std_logic;
+		nSRBLE      : OUT std_logic;
+		nSRBHE      : OUT std_logic;
+		nSRWE       : OUT std_logic;
+		nSROE       : OUT std_logic;
+		DSP_INT     : OUT std_logic;
+		DSP_TA      : OUT std_logic;
+		FB_AD       : INOUT std_logic_vector(31 DOWNTO 0);
+		IO          : INOUT std_logic_vector(17 DOWNTO 0);
+		SRD         : INOUT std_logic_vector(15 DOWNTO 0)
 	);
 	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
 	
-END DSP;
+END dsp;
 
 
 --  Architecture Body
 
-ARCHITECTURE DSP_architecture OF DSP IS
+ARCHITECTURE rtl OF dsp IS
 
 	
 BEGIN
-	nSRCS  <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1';	--nFB_CS3;
-	nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1';
-	nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; 
-	nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1';
-	nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1';
+	nSRCS  <= '0' WHEN nFB_CS2 = '0' AND FB_ADR(27 DOWNTO 24) = x"4" ELSE '1';	--nFB_CS3;
+	nSRBHE <= '0' WHEN FB_ADR(0 DOWNTO 0) = "0" ELSE '1';
+	nSRBLE <= '1' WHEN FB_ADR(0 DOWNTO 0) = "0" AND FB_SIZE1 = '0' AND FB_SIZE0 = '1' ELSE '0'; 
+	nSRWE <= '0' WHEN nFB_WR = '0' AND nSRCS = '0' AND MAIN_CLK = '0' ELSE '1';
+	nSROE <= '0' WHEN nFB_OE = '0' AND nSRCS = '0' ELSE '1';
 	DSP_INT <= '0';
 	DSP_TA <= '0';
-	IO(17 downto 0) <= FB_ADR(18 downto 1);
-	SRD(15 downto 0) <= FB_AD(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
-	FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
-	
-	
-END DSP_architecture;
+	IO(17 DOWNTO 0) <= FB_ADR(18 DOWNTO 1);
+	SRD(15 DOWNTO 0) <= FB_AD(31 DOWNTO 16) WHEN nFB_WR = '0' AND nSRCS = '0' ELSE "ZZZZZZZZZZZZZZZZ";
+	FB_AD(31 DOWNTO 16) <= SRD(15 DOWNTO 0) WHEN nFB_OE = '0' AND nSRCS = '0' ELSE "ZZZZZZZZZZZZZZZZ";
+END rtl;

FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak

@@ -1,971 +0,0 @@
--- WARNING: Do NOT edit the input and output ports in this file in a text
--- editor if you plan to continue editing the block that represents it in
--- the Block Editor! File corruption is VERY likely to occur.
-
--- Copyright (C) 1991-2008 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
-
--- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
--- Created on Tue Sep 08 16:24:20 2009
-
-library work;
-use work.FalconIO_SDCard_IDE_CF_pkg.all;
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-
---  Entity Declaration
-
-
---  Entity Declaration
-
-ENTITY FalconIO_SDCard_IDE_CF IS
-	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
-	PORT
-	(
-		CLK33M : IN STD_LOGIC;
-		MAIN_CLK : IN STD_LOGIC;
-		CLK2M : IN STD_LOGIC;
-		CLK500k : IN STD_LOGIC;
-		nFB_CS1 : IN STD_LOGIC;
-		FB_SIZE0 : IN STD_LOGIC;
-		FB_SIZE1 : IN STD_LOGIC;
-		nFB_BURST : IN STD_LOGIC;
-		FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
-		LP_BUSY : IN STD_LOGIC;
-		nACSI_DRQ : IN STD_LOGIC;
-		nACSI_INT : IN STD_LOGIC;
-		nSCSI_DRQ : IN STD_LOGIC;
-		nSCSI_MSG : IN STD_LOGIC;
-		MIDI_IN : IN STD_LOGIC;
-		RxD : IN STD_LOGIC;
-		CTS : IN STD_LOGIC;
-		RI : IN STD_LOGIC;
-		DCD : IN STD_LOGIC;
-		AMKB_RX : IN STD_LOGIC;
-		PIC_AMKB_RX : IN STD_LOGIC;
-		IDE_RDY : IN STD_LOGIC;
-		IDE_INT : IN STD_LOGIC;
-		WP_CS_CARD : IN STD_LOGIC;
-		nINDEX : IN STD_LOGIC;
-		TRACK00 : IN STD_LOGIC;
-		nRD_DATA : IN STD_LOGIC;
-		nDCHG : IN STD_LOGIC;
-		SD_DATA0 : IN STD_LOGIC;
-		SD_DATA1 : IN STD_LOGIC;
-		SD_DATA2 : IN STD_LOGIC;
-		SD_CARD_DEDECT : IN STD_LOGIC;
-		SD_WP : IN STD_LOGIC;
-		nDACK0 : IN STD_LOGIC;
-		nFB_WR : INOUT STD_LOGIC;
-		WP_CF_CARD : IN STD_LOGIC;
-		nWP : IN STD_LOGIC;
-		nFB_CS2 : IN STD_LOGIC;
-		nRSTO : IN STD_LOGIC;
-		HD_DD : IN STD_LOGIC;
-		nSCSI_C_D : IN STD_LOGIC;
-		nSCSI_I_O : IN STD_LOGIC;
-		CLK2M4576 : IN STD_LOGIC;
-		nFB_OE : IN STD_LOGIC;
-		VSYNC : IN STD_LOGIC;
-		HSYNC : IN STD_LOGIC;
-		DSP_INT : IN STD_LOGIC;
-		nBLANK : IN STD_LOGIC;
-		FDC_CLK : IN STD_LOGIC;
-		FB_ALE : IN STD_LOGIC;
-		ACP_CONF : IN STD_LOGIC_VECTOR(31 downto 24);
-		nIDE_CS1 : OUT STD_LOGIC;
-		nIDE_CS0 : OUT STD_LOGIC;
-		LP_STR : OUT STD_LOGIC;
-		LP_DIR : OUT STD_LOGIC;
-		nACSI_ACK : OUT STD_LOGIC;
-		nACSI_RESET : OUT STD_LOGIC;
-		nACSI_CS : OUT STD_LOGIC;
-		ACSI_DIR : OUT STD_LOGIC;
-		ACSI_A1 : OUT STD_LOGIC;
-		nSCSI_ACK : OUT STD_LOGIC;
-		nSCSI_ATN : OUT STD_LOGIC;
-		SCSI_DIR : OUT STD_LOGIC;
-		SD_CLK : OUT STD_LOGIC;
-		YM_QA : OUT STD_LOGIC;
-		YM_QC : OUT STD_LOGIC;
-		YM_QB : OUT STD_LOGIC;
-		nSDSEL : OUT STD_LOGIC;
-		STEP : OUT STD_LOGIC;
-		MOT_ON : OUT STD_LOGIC;
-		nRP_LDS : OUT STD_LOGIC;
-		nRP_UDS : OUT STD_LOGIC;
-		nROM4 : OUT STD_LOGIC;
-		nROM3 : OUT STD_LOGIC;
-		nCF_CS1 : OUT STD_LOGIC;
-		nCF_CS0 : OUT STD_LOGIC;
-		nIDE_RD : INOUT STD_LOGIC;
-		nIDE_WR : INOUT STD_LOGIC;
-		AMKB_TX : OUT STD_LOGIC;
-		IDE_RES : OUT STD_LOGIC;
-		DTR : OUT STD_LOGIC;
-		RTS : OUT STD_LOGIC;
-		TxD : OUT STD_LOGIC;
-		MIDI_OLR : OUT STD_LOGIC;
-		MIDI_TLR : OUT STD_LOGIC;
-		nDREQ0 : OUT STD_LOGIC;
-		DSA_D : OUT STD_LOGIC;
-		nMFP_INT : OUT STD_LOGIC;
-		FALCON_IO_TA : OUT STD_LOGIC;
-		STEP_DIR : OUT STD_LOGIC;
-		WR_DATA : OUT STD_LOGIC;
-		WR_GATE : OUT STD_LOGIC;
-		DMA_DRQ : OUT STD_LOGIC;
-		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
-		LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
-		ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
-		SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
-		SCSI_PAR : INOUT STD_LOGIC;
-		nSCSI_SEL : INOUT STD_LOGIC;
-		nSCSI_BUSY : INOUT STD_LOGIC;
-		nSCSI_RST : INOUT STD_LOGIC;
-		SD_CD_DATA3 : INOUT STD_LOGIC;
-		SD_CDM_D1 : INOUT STD_LOGIC
-	);
-	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
-	
-END FalconIO_SDCard_IDE_CF;
-
-
---  Architecture Body
-
-ARCHITECTURE FalconIO_SDCard_IDE_CF_architecture OF FalconIO_SDCard_IDE_CF IS
--- system
-signal SYS_CLK					: STD_LOGIC;
-signal RESETn					: STD_LOGIC;
-signal FB_B0					: STD_LOGIC;	-- UPPER BYT BEI 16BIT BUS
-signal FB_B1					: STD_LOGIC;	-- LOWER BYT BEI 16BIT BUS
-signal BYT						: STD_LOGIC;	-- WENN BYT -> 1
-signal LONG						: STD_LOGIC;	-- WENN  -> 1
--- KEYBOARD MIDI
-signal ACIA_CS_I				: STD_LOGIC;
-signal IRQ_KEYBDn				: STD_LOGIC;
-signal IRQ_MIDIn				: STD_LOGIC;
-signal KEYB_RxD					: STD_LOGIC;
-signal AMKB_REG					: STD_LOGIC_VECTOR(4 downto 0);
-signal MIDI_OUT					: STD_LOGIC;
-signal DATA_OUT_ACIA_I			: STD_LOGIC_VECTOR(7 downto 0);
-signal DATA_OUT_ACIA_II			: STD_LOGIC_VECTOR(7 downto 0);
--- MFP
-signal MFP_CS					: STD_LOGIC;
-signal MFP_INTACK				: STD_LOGIC;
-signal LDS						: STD_LOGIC;
-signal DTACK_OUT_MFPn			: STD_LOGIC;
-signal IRQ_ACIAn				: STD_LOGIC;
-signal DINTn					: STD_LOGIC;
-signal DATA_OUT_MFP				: STD_LOGIC_VECTOR(7 downto 0);
-signal TDO						: STD_LOGIC;
--- SOUND
-signal SNDCS					: STD_LOGIC;
-signal SNDCS_I					: STD_LOGIC;
-signal SNDIR_I					: STD_LOGIC;
-signal LP_DIR_X					: STD_LOGIC;
-signal DA_OUT_X					: STD_LOGIC_VECTOR(7 downto 0);
-signal LP_D_X					: STD_LOGIC_VECTOR(7 downto 0);
--- DIV
-signal SUB_BUS					: STD_LOGIC;	-- SUB BUS MIT ROM-PORT, CF UND IDE
-signal ROM_CS					: STD_LOGIC;
--- DMA UND FLOPPY
-signal DMA_DATEN_CS				: STD_LOGIC;
-signal DMA_MODUS_CS				: STD_LOGIC;
-signal DMA_MODUS				: STD_LOGIC_VECTOR(15 downto 0);
-signal WDC_BSL_CS				: STD_LOGIC;
-signal WDC_BSL					: STD_LOGIC_VECTOR(1 DOWNTO 0);
-signal HD_DD_OUT				: STD_LOGIC;
-signal FDCS_In					: STD_LOGIC;
-signal CA0						: STD_LOGIC;
-signal CA1						: STD_LOGIC;
-signal CA2						: STD_LOGIC;
-signal FDINT					: STD_LOGIC;
-signal FDRQ						: STD_LOGIC;
-signal CD_OUT_FDC				: STD_LOGIC_VECTOR(7 downto 0);
-signal CD_IN_FDC				: STD_LOGIC_VECTOR(7 downto 0);
-signal DMA_TOP_CS				: STD_LOGIC;
-signal DMA_TOP					: STD_LOGIC_VECTOR(7 downto 0);
-signal DMA_HIGH_CS				: STD_LOGIC;
-signal DMA_HIGH					: STD_LOGIC_VECTOR(7 downto 0);
-signal DMA_MID_CS				: STD_LOGIC;
-signal DMA_MID					: STD_LOGIC_VECTOR(7 downto 0);
-signal DMA_LOW_CS				: STD_LOGIC;
-signal DMA_LOW					: STD_LOGIC_VECTOR(7 downto 0);
-signal DMA_DIRM_CS				: STD_LOGIC;
-signal DMA_ADR_CS				: STD_LOGIC;
-signal DMA_STATUS				: STD_LOGIC_VECTOR(2 downto 0);
-signal DMA_DIR_OLD				: STD_LOGIC;
-signal DMA_BYT_CNT_CS			: STD_LOGIC;
-signal DMA_BYT_CNT				: STD_LOGIC_VECTOR(31 downto 0);
-signal CLR_FIFO					: STD_LOGIC;
-signal DMA_DRQ_I				: STD_LOGIC;
-signal DMA_DRQ_REG				: STD_LOGIC_VECTOR(1 downto 0);
-signal DMA_DRQQ					: STD_LOGIC;
-signal DMA_DRQ_Q				: STD_LOGIC;
-signal RDF_DOUT					: STD_LOGIC_VECTOR(31 downto 0);
-signal RDF_AZ					: STD_LOGIC_VECTOR(9 downto 0);
-signal RDF_RDE					: STD_LOGIC;
-signal RDF_WRE					: STD_LOGIC;
-signal RDF_DIN					: STD_LOGIC_VECTOR(7 downto 0);
-signal WRF_DOUT					: STD_LOGIC_VECTOR(7 downto 0);
-signal WRF_AZ					: STD_LOGIC_VECTOR(9 downto 0);
-signal WRF_RDE					: STD_LOGIC;
-signal WRF_WRE					: STD_LOGIC;
-signal nFDC_WR					: STD_LOGIC;
-type FCF_STATES is(	FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7);
-signal FCF_STATE				: FCF_STATES;
-signal NEXT_FCF_STATE			: FCF_STATES;
-signal DMA_REQ					: STD_LOGIC;
-signal FDC_CS					: STD_LOGIC;
-signal FCF_CS					: STD_LOGIC;
-signal FCF_APH					: STD_LOGIC;
-signal DMA_AZ_CS				: STD_LOGIC;
-signal DMA_ACTIV				: STD_LOGIC;
-signal DMA_ACTIV_NEW			: STD_LOGIC;
-signal FDC_OUT					: STD_LOGIC_VECTOR(7 downto 0);
--- SCSI
-signal SCSI_CS					: STD_LOGIC;
-signal SCSI_CSn					: STD_LOGIC;
-signal SCSI_DOUT				: STD_LOGIC_VECTOR(7 downto 0);
-signal nSCSI_DACK				: STD_LOGIC;
-signal SCSI_DRQ					: STD_LOGIC;
-signal SCSI_INT					: STD_LOGIC;
-signal DB_OUTn					: STD_LOGIC_VECTOR(7 downto 0);
-signal DB_EN					: STD_LOGIC;
-signal DBP_OUTn					: STD_LOGIC;
-signal DBP_EN					: STD_LOGIC;
-signal RST_OUTn					: STD_LOGIC;
-signal RST_EN					: STD_LOGIC;
-signal BSY_OUTn					: STD_LOGIC;
-signal BSY_EN					: STD_LOGIC;
-signal SEL_OUTn					: STD_LOGIC;
-signal SEL_EN					: STD_LOGIC;
--- IDE
-signal nnIDE_RES				: STD_LOGIC;
-signal IDE_CF_CS				: STD_LOGIC;
-signal IDE_CF_TA				: STD_LOGIC;
-signal NEXT_nIDE_RD				: STD_LOGIC;
-signal NEXT_nIDE_WR				: STD_LOGIC;
-type CMD_STATES is(	IDLE, T1, T6, T7);
-signal CMD_STATE				: CMD_STATES;
-signal NEXT_CMD_STATE			: CMD_STATES;
-
-	
-BEGIN
-LONG  <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else '0';
-BYT   <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0';
-FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0';
-FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0';
-
-FALCON_IO_TA <= '1' when SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1' 
-				 or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';
-SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1'    ELSE
-           '1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE
-           '1' when nFB_WR = '0' and nIDE_WR = '0'   ELSE '0';
-nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1'; 
-nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1'; 
-nDREQ0 <= '0';
-----------------------------------------------------------------------------
--- SD
-----------------------------------------------------------------------------
-SD_CLK <= 'Z';
-SD_CD_DATA3 <= 'Z';
-SD_CDM_D1 <= 'Z';
-----------------------------------------------------------------------------
--- IDE
-----------------------------------------------------------------------------
-CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE)
-	begin
-		if nRSTO = '0' then
-			CMD_STATE <= IDLE;
-		elsif rising_edge(MAIN_CLK) then
-				CMD_STATE <= NEXT_CMD_STATE; 	-- go to next
-				nIDE_RD   <= NEXT_nIDE_RD; 		-- go to next
-				nIDE_WR   <= NEXT_nIDE_WR; 		-- go to next
-			else
-				CMD_STATE <= CMD_STATE; 		-- halten
-				nIDE_RD   <= nIDE_RD;			-- halten
-				nIDE_WR   <= nIDE_WR;			-- halten
-			end if;
-	end process CMD_REG;
-
-	CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA)
-	begin
-		case CMD_STATE is
-			when IDLE =>
-				IDE_CF_TA <= '0';
-				if  IDE_CF_CS = '1' then
-					NEXT_nIDE_RD <= not nFB_WR;
-					NEXT_nIDE_WR <=     nFB_WR;
-					NEXT_CMD_STATE <= T1;
-				else
-					NEXT_nIDE_RD <= '1';
-					NEXT_nIDE_WR <= '1';
-					NEXT_CMD_STATE <= IDLE; 		 
-				end if;
-			when T1 =>
-				IDE_CF_TA <= '0';
-				NEXT_nIDE_RD <= not nFB_WR;
-				NEXT_nIDE_WR <=     nFB_WR;
-				NEXT_CMD_STATE <= T6;
-			when T6 =>
-				IF IDE_RDY = '1' then
-					IDE_CF_TA <= '1';
-					NEXT_nIDE_RD <= '1';
-					NEXT_nIDE_WR <= '1';
-					NEXT_CMD_STATE <= T7;
-				else
-					IDE_CF_TA <= '0';
-					NEXT_nIDE_RD <= not nFB_WR;
-					NEXT_nIDE_WR <=     nFB_WR;
-					NEXT_CMD_STATE <= T6;
-				end if;
-			when T7 => 
-				IDE_CF_TA <= '0';
-				NEXT_nIDE_RD <= '1';
-				NEXT_nIDE_WR <= '1';
-				NEXT_CMD_STATE <= IDLE;
-		end case;
-	end process CMD_DECODER;
-	
-IDE_RES <= not nnIDE_RES and nRSTO;
-IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0';				-- FFF0'0000/80
-nCF_CS0   <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else 				-- FFFO'0000-FFF0'001F
-			 '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; 			-- FFFO'0040-FFF0'005F
-nCF_CS1   <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else	 			-- FFF0'0020-FFF0'003F
-			 '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; 			-- FFFO'0060-FFF0'007F
-nIDE_CS0  <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else				-- FFF0'0040-FFF0'005F 
-			 '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; 			-- FFFO'0000-FFF0'001F
-nIDE_CS1  <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else				-- FFF0'0060-FFF0'007F 
-			 '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; 			-- FFFO'0020-FFF0'003F
------------------------------------------------------------------------------------------------------------------------------------------
--- ACSI, SCSI UND FLOPPY WD1772 
--------------------------------------------------------------------------------------------------------------------------------------------
--- daten read fifo
-	RDF: dcfifo0
-		port map(
-			aclr				=> CLR_FIFO,
-			data				=> RDF_DIN,
-			rdclk				=> MAIN_CLK,
-			rdreq				=> RDF_RDE,
-			wrclk				=> FDC_CLK,
-			wrreq				=> RDF_WRE,
-			q					=> RDF_DOUT,
-			wrusedw				=> RDF_AZ
-	);
-FCF_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"0020110" and LONG = '1' else '0';		-- F002'0110 LONG ONLY
-FCF_APH <= '1' when FB_ALE = '1' and FB_AD(31 downto 0)  = x"F0020110" and LONG = '1' else '0';		-- ADRESSPHASE F0020110 LONG ONLY
-RDF_RDE <= '1' when FCF_APH = '1' and nFB_WR = '1' else '0';										-- AKTIVIEREN IN ADRESSPHASE
-FB_AD <= RDF_DOUT(7 downto 0) & RDF_DOUT(15 downto 8) & RDF_DOUT(23 downto 16) & RDF_DOUT(31 downto 24) when FCF_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";	 
-RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT;
--- daten write fifo
-	WRF: dcfifo1
-		port map(
-			aclr				=> CLR_FIFO,
-			data				=> FB_AD(7 downto 0) & FB_AD(15 downto 8) & FB_AD(23 downto 16) & FB_AD(31 downto 24),
-			rdclk				=> FDC_CLK,
-			rdreq				=> WRF_RDE,
-			wrclk				=> MAIN_CLK,
-			wrreq				=> WRF_WRE,
-			q					=> WRF_DOUT,
-			rdusedw				=> WRF_AZ
-	);
-CD_IN_FDC <=  WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_AD(23 downto 16); 							-- BEI DMA WRITE <-FIFO SONST <-FB
-DMA_AZ_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"002010C" else '0';										-- F002'010C LONG
-FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ when DMA_AZ_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
-DMA_DRQ_Q <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0';
--- FIFO WRITE: GENAU 1 MAIN_CLK  -------------------------------------------------------------------------
-	process(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH)
-	begin
-		if nRSTO = '0' THEN
-			WRF_WRE <= '0';
-		elsif rising_edge(MAIN_CLK) then
-				IF FCF_APH = '1' and nFB_WR = '0' then
-					WRF_WRE <= '1';
-				else
-					WRF_WRE <= '0';
-				end if;
-			else
-				WRF_WRE <= WRF_WRE;
-			end if;
-	END PROCESS;
- 
-FCF_REG: process(nRSTO, FDC_CLK, FCF_STATE, NEXT_FCF_STATE, DMA_ACTIV)
-	begin
-		if nRSTO = '0' then
-			FCF_STATE <= FCF_IDLE;
-			DMA_ACTIV <= '0';
-		elsif rising_edge(FDC_CLK) then
-				FCF_STATE <= NEXT_FCF_STATE; 			-- go to next
-				DMA_ACTIV <= DMA_ACTIV_NEW;
-			else
-				FCF_STATE <= FCF_STATE; 					-- halten
-				DMA_ACTIV <= DMA_ACTIV;
-			end if;
-	end process FCF_REG;
-
-FDC_REG: process(nRSTO, FDC_CLK, FDC_OUT, FDCS_In, CD_OUT_FDC)
-	begin
-		if nRSTO = '0' then
-			FDC_OUT <= x"00";
-		elsif rising_edge(FDC_CLK) and FDCS_In = '0' then
-				FDC_OUT <= CD_OUT_FDC; 						-- set
-			else
-				FDC_OUT <= FDC_OUT; 						-- halten
-			end if;
-	end process FDC_REG;
-
-DMA_REQ <= '1' when ((DMA_DRQ_I = '1' and DMA_MODUS(7) = '1') or (SCSI_DRQ = '1' and DMA_MODUS(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODUS(6) = '0' and CLR_FIFO = '0' else '0';
-FDC_CS   <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and FB_B1 = '1' else '0';
-SCSI_CS  <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_B1 = '1' else '0';
-
-	FCF_DECODER: process(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn)
-	begin
-		case FCF_STATE is
-			when FCF_IDLE =>
-				SCSI_CSn <= '1';
-				FDCS_In <= '1';
-				RDF_WRE <= '0';
-				WRF_RDE <= '0';
-				nSCSI_DACK <= '1';
-				if DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS = '1' then 	 
-					DMA_ACTIV_NEW <= DMA_REQ;
-					NEXT_FCF_STATE <= FCF_T0;
-				else
-					DMA_ACTIV_NEW <= '0';
-					NEXT_FCF_STATE <= FCF_IDLE; 		 
-				end if;
-			when FCF_T0 =>
-				SCSI_CSn <= '1';
-				FDCS_In <= '1';
-				RDF_WRE <= '0';
-				nSCSI_DACK <= '1';
-				DMA_ACTIV_NEW <= DMA_REQ;
-				WRF_RDE <= DMA_MODUS(8) and DMA_REQ;				-- WRITE -> READ FROM FIFO
-				if 	DMA_REQ = '0' and DMA_ACTIV = '1' THEN			-- spike?
-					NEXT_FCF_STATE <= FCF_IDLE;						-- ja -> zum start
-				else
-					NEXT_FCF_STATE <= FCF_T1;
-				end if;
-			when FCF_T1 =>
-				RDF_WRE <= '0';
-				WRF_RDE <= '0';
-				DMA_ACTIV_NEW <= DMA_ACTIV;
-				SCSI_CSn <= not SCSI_CS;
-				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
-				nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
-				NEXT_FCF_STATE <= FCF_T2;
-			when FCF_T2 =>
-				RDF_WRE <= '0';
-				WRF_RDE <= '0';
-				DMA_ACTIV_NEW <= DMA_ACTIV;
-				SCSI_CSn <= not SCSI_CS;
-				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
-				nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
-				NEXT_FCF_STATE <= FCF_T3;
-			when FCF_T3 =>
-				RDF_WRE <= '0';
-				WRF_RDE <= '0';
-				DMA_ACTIV_NEW <= DMA_ACTIV;
-				SCSI_CSn <= not SCSI_CS;
-				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
-				nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
-				NEXT_FCF_STATE <= FCF_T6;
-			when FCF_T6 =>
-				WRF_RDE <= '0';
-				DMA_ACTIV_NEW <= DMA_ACTIV;
-				SCSI_CSn <= not SCSI_CS;
-				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
-				nSCSI_DACK <= DMA_MODUS(7)  and DMA_ACTIV;
-				RDF_WRE <= not DMA_MODUS(8) and DMA_ACTIV;		-- READ -> WRITE IN FIFO
-				NEXT_FCF_STATE <= FCF_T7;
-			when FCF_T7 =>
-				SCSI_CSn <= '1';
-				FDCS_In <= '1';
-				RDF_WRE <= '0';
-				WRF_RDE <= '0';
-				nSCSI_DACK <= '1';
-				DMA_ACTIV_NEW <= '0';
-				if FDC_CS = '1' and DMA_REQ = '0'  then 	 
-					NEXT_FCF_STATE <= FCF_T7;
-				else
-					NEXT_FCF_STATE <= FCF_IDLE; 		 
-				end if;
-		end case;
-	end process FCF_DECODER;
-
-	I_FDC: WF1772IP_TOP_SOC
-		port map(
-            CLK					=> FDC_CLK,
-			RESETn				=> nRSTO,
-			CSn					=> FDCS_In,
-			RWn					=> nFDC_WR,
-			A1					=> CA2,
-			A0					=> CA1,
-			DATA_IN				=> CD_IN_FDC,
-			DATA_OUT			=> CD_OUT_FDC,
---			DATA_EN				=> CD_EN_FDC,
-			RDn					=> nRD_DATA,
-			TR00n				=> TRACK00,
-			IPn					=> nINDEX,
-			WPRTn				=> nWP,
-			DDEn				=> '0', -- Fixed to MFM.
-			HDTYPE				=> HD_DD_OUT,  
-			MO					=> MOT_ON,
-			WG					=> WR_GATE,
-			WD					=> WR_DATA,
-			STEP				=> STEP,
-			DIRC				=> STEP_DIR,
-			DRQ					=> DMA_DRQ_I,
-			INTRQ				=> FDINT 
-		);
-DMA_DATEN_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C302" else '0';						-- F8604/2 
-DMA_MODUS_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C303" else '0';						-- F8606/2
-WDC_BSL_CS   <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C307" else '0';						-- F860E/2
-HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0);
-nFDC_WR <= (not DMA_MODUS(8)) when DMA_ACTIV = '1' else nFB_WR;
-CA0 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(0);
-CA1 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(1);
-CA2 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(2);
-FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
-FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1'                               and nFB_OE = '0' else "ZZZZZZZZ";
-FB_AD(23 downto 16) <= FDC_OUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and nFB_OE = '0' else
-                     SCSI_DOUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and nFB_OE = '0' else 
-      DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1'           and nFB_OE = '0' else "ZZZZZZZZ";
---- WDC BSL REGISTER -------------------------------------------------------
-	process(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1)
-	begin
-		if nRSTO = '0' THEN
-			WDC_BSL <= "00";
-		elsif rising_edge(MAIN_CLK) and WDC_BSL_CS = '1' and nFB_WR = '0' then
-			IF FB_B0 = '1' THEN
-				WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24);
-			else
-				WDC_BSL(1 DOWNTO 0) <= WDC_BSL(1 DOWNTO 0);
-			end if;
-		end if;
-	END PROCESS;
---- DMA MODUS REGISTER -------------------------------------------------------
-	process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1)
-	begin
-		if nRSTO = '0' THEN
-			DMA_MODUS <= x"0000";
-		elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '1' and nFB_WR = '0' then
-			IF FB_B0 = '1' THEN
-				DMA_MODUS(15 downto 8) <= FB_AD(31 downto 24);
-			else
-				DMA_MODUS(15 downto 8) <= DMA_MODUS(15 downto 8);
-			end if;
-			IF FB_B1 = '1' THEN
-				DMA_MODUS(7 downto 0) <= FB_AD(23 downto 16);
-			else
-				DMA_MODUS(7 downto 0) <= DMA_MODUS(7 downto 0);
-			end if;
-		else
-			DMA_MODUS <= DMA_MODUS;
-		end if;
-	END PROCESS;
--- BYT COUNTER, SECTOR COUNTER ----------------------------------------------------
-	process(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO)
-	begin
-		if nRSTO = '0' or CLR_FIFO = '1' THEN
-			DMA_BYT_CNT <= x"00000000";													 
-		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_DATEN_CS = '1' and nFB_WR = '0' and DMA_MODUS(4) = '1' and FB_B1 = '1' then
-				DMA_BYT_CNT(31 downto 17) <= "000000000000000";
-				DMA_BYT_CNT(16 downto 9) <= FB_AD(23 downto 16);
-				DMA_BYT_CNT(8 downto 0) <= "000000000";
-			elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_BYT_CNT_CS = '1' then
-					DMA_BYT_CNT <= FB_AD;
-				else
-					DMA_BYT_CNT <= DMA_BYT_CNT;
-				end if;
-	END PROCESS;
---------------------------------------------------------------------
-FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
-DMA_STATUS(0) <= '1';													-- DMA OK
-DMA_STATUS(1) <= '1' when DMA_BYT_CNT /= 0 and DMA_BYT_CNT(31) = '0' else '0';					-- WENN byts UND NICHT MINUS
-DMA_STATUS(2) <= '0' when DMA_DRQ_I = '1' or SCSI_DRQ = '1' else '0'; 
-DMA_DRQQ <= '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '0' and RDF_AZ >  15 and DMA_MODUS(6) = '0' else 
-            '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '1' and WRF_AZ < 512 and DMA_MODUS(6) = '0' else '0';
-DMA_DRQ <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0';
--- DMA REQUEST: SPIKES AUSFILTERN  ------------------------------------------
-	process(FDC_CLK, nRSTO, DMA_DRQ_REG)
-	begin
-		if nRSTO = '0' THEN
-			DMA_DRQ_REG <= "00";
-		elsif rising_edge(FDC_CLK) then
-				DMA_DRQ_REG(0) <= DMA_DRQQ;
-				DMA_DRQ_REG(1) <= DMA_DRQ_REG(0) and DMA_DRQQ;
-			else
-				DMA_DRQ_REG <= DMA_DRQ_REG;
-			end if;
-	END PROCESS;
--- DMA ADRESSE ------------------------------------------------------
-	process(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS)
-	begin
-		if nRSTO = '0' THEN
-			DMA_TOP <= x"00";
-		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') then
-				DMA_TOP <= FB_AD(31 downto 24);
-			else 
-				DMA_TOP <= DMA_TOP;
-			end if;
-	END PROCESS;
-	process(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS)
-	begin
-		if nRSTO = '0' THEN
-			DMA_HIGH <= x"00";
-		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') then
-				DMA_HIGH <= FB_AD(23 downto 16);
-			else
-				DMA_HIGH <= DMA_HIGH;
-			end if;
-	END PROCESS;
-	process(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR)
-	begin
-		DMA_MID <= DMA_MID;
-		if nRSTO = '0' THEN
-			DMA_MID <= x"00";
-		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then
-				if DMA_MID_CS = '1' then
-					DMA_MID <= FB_AD(23 downto 16);
-				elsif DMA_ADR_CS = '1' then
-						DMA_MID <= FB_AD(15 downto 8);
-					end if;
-			end if;
-	END PROCESS;
-	process(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR)
-	begin
-		DMA_LOW <= DMA_LOW;
-		if nRSTO = '0' THEN
-			DMA_LOW <= x"00";
-		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then
-				if DMA_LOW_CS = '1'then
-					DMA_LOW <= FB_AD(23 downto 16);
-				elsif DMA_ADR_CS = '1' then
-						DMA_LOW <= FB_AD(7 downto 0);
-					end if;
-			end if;
-	END PROCESS;
---------------------------------------------------------------------------------------------
-DMA_TOP_CS <= '1' when nFB_CS1 = '0'  and FB_ADR(19 downto 1) = x"7C304" and FB_B0 = '1' else '0';			-- F8608/2
-DMA_HIGH_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B1 = '1' else '0';			-- F8609/2		
-DMA_MID_CS <= '1' when nFB_CS1 = '0'  and FB_ADR(19 downto 1) = x"7C305" and FB_B1 = '1' else '0';			-- F860B/2		
-DMA_LOW_CS <= '1' when nFB_CS1 = '0'  and FB_ADR(19 downto 1) = x"7C306" and FB_B1 = '1' else '0';			-- F860D/2	
-FB_AD(31 downto 24) <= DMA_TOP  when DMA_TOP_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZ";
-FB_AD(23 downto 16) <= DMA_HIGH when DMA_HIGH_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
-FB_AD(23 downto 16) <= DMA_MID  when DMA_MID_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZ";
-FB_AD(23 downto 16) <= DMA_LOW  when DMA_LOW_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZ";
--- DIRECTZUGRIFF
-DMA_DIRM_CS <= '1' when nFB_CS2 = '0' and     FB_ADR(26 downto 0) = x"20100" else '0';						-- F002'0100 WORD 
-DMA_ADR_CS  <= '1' when nFB_CS2 = '0' and     FB_ADR(26 downto 0) = x"20104" else '0';						-- F002'0104 LONG 
-DMA_BYT_CNT_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20108" else '0';						-- F002'0108 LONG 
-FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
-FB_AD(31 downto 16) <= DMA_MODUS when DMA_DIRM_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
-FB_AD <= DMA_BYT_CNT when DMA_BYT_CNT_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
--- DMA RW TOGGLE ------------------------------------------
-	process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD)
-	begin
-		if nRSTO = '0' THEN
-			DMA_DIR_OLD <= '0';
-		elsif rising_edge(MAIN_CLK) and  DMA_MODUS_CS = '0' then
-				DMA_DIR_OLD <= DMA_MODUS(8);
-			else
-				DMA_DIR_OLD <= DMA_DIR_OLD;
-			end if;
-	END PROCESS;
-CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD;	
--- SCSI ----------------------------------------------------------------------------------
-    I_SCSI: WF5380_TOP_SOC
-        port map(
-            CLK					=> FDC_CLK,
-            RESETn				=> nRSTO,
-			ADR			        => CA2 & CA1 & CA0,
-			DATA_IN		        => CD_IN_FDC,	
-			DATA_OUT			=> SCSI_DOUT,
-			--DATA_EN			: out bit;
-            -- Bus and DMA controls:
-			CSn			        => '1',			--SCSI_CSn,  ABGESCHALTET
-			RDn		            => (not nFDC_WR) or (not SCSI_CS),
-			WRn	                =>      nFDC_WR  or (not SCSI_CS),
-            EOPn                => '1',
-			DACKn	            => nSCSI_DACK,
-			DRQ		            => SCSI_DRQ,
-			INT		            => SCSI_INT,
---            READY                	=> 
-            -- SCSI bus:
-            DB_INn		        => SCSI_D,
-            DB_OUTn		        => DB_OUTn,
-            DB_EN               => DB_EN,
-            DBP_INn		        => SCSI_PAR,
-            DBP_OUTn	        => DBP_OUTn,
-            DBP_EN              => DBP_EN,				-- wenn 1 dann output
-            RST_INn             => nSCSI_RST,
-            RST_OUTn            => RST_OUTn,
-            RST_EN              => RST_EN,
-            BSY_INn             => nSCSI_BUSY,
-            BSY_OUTn            => BSY_OUTn,
-            BSY_EN              => BSY_EN,
-            SEL_INn             => nSCSI_SEL,
-            SEL_OUTn            => SEL_OUTn,
-            SEL_EN              => SEL_EN,
-            ACK_INn             => '1',
-            ACK_OUTn            => nSCSI_ACK,
---            ACK_EN              => ACK_EN,
-            ATN_INn             => '1',
-            ATN_OUTn            => nSCSI_ATN,
---            ATN_EN              => ATN_EN,
-            REQ_INn             => nSCSI_DRQ,
---            REQ_OUTn            => REQ_OUTn,
---            REQ_EN              => REQ_EN,
-            IOn_IN              => nSCSI_I_O,
---            IOn_OUT             => IOn_OUT,
---            IO_EN               => IO_EN,
-            CDn_IN              => nSCSI_C_D,
---            CDn_OUT             => CDn_OUT,
---            CD_EN               => CD_EN,
-            MSG_INn             => nSCSI_MSG
---            MSG_OUTn            => MSG_OUTn,
---            MSG_EN              => MSG_EN
-        );              
--- SCSI ACSI ---------------------------------------------------------------
-SCSI_D <= DB_OUTn when DB_EN = '1' else "ZZZZZZZZ";
-SCSI_DIR <= '1'; --'0' when DB_EN = '1' else '1';	--ABGESCHALTET
-SCSI_PAR <= DBP_OUTn when DBP_EN = '1' else 'Z';
-nSCSI_RST <= RST_OUTn when RST_EN = '1' else 'Z';
-nSCSI_BUSY <= BSY_OUTn when BSY_EN = '1' else 'Z';
-nSCSI_SEL <= SEL_OUTn when SEL_EN = '1' else 'Z';
-ACSI_DIR <= '0';
-ACSI_D <= "ZZZZZZZZ";
-nACSI_CS <= '1';
-ACSI_A1 <= CA1;
-nACSI_RESET <= nRSTO;
-nACSI_ACK <= '1';
-----------------------------------------------------------------------------
--- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns
-----------------------------------------------------------------------------
-ROM_CS <= '1' when nFB_CS1 = '0' and nFB_WR = '1' and FB_ADR(19 downto 17) = x"5" else '0';		-- FFF A'0000/2'0000
-nROM4 <= '0' when ROM_CS = '1' and FB_ADR(16) = '0' else '1';
-nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1';
-----------------------------------------------------------------------------
--- ACIA KEYBOARD
-----------------------------------------------------------------------------
-	I_ACIA_KEYBOARD: WF6850IP_TOP_SOC
-	  port map(
-			CLK					=> MAIN_CLK,
-			RESETn				=> nRSTO,
-
-			CS2n				=> FB_ADR(2),
-			CS1					=> '1',
-			CS0					=> ACIA_CS_I,
-            E					=> ACIA_CS_I,
-			RWn					=> nFB_WR,
-			RS					=> FB_ADR(1),
-
-			DATA_IN				=> FB_AD(31 downto 24),
-			DATA_OUT			=> DATA_OUT_ACIA_I,
---			DATA_EN				=> DATA_EN_ACIA_I,
-
-			TXCLK				=> CLK500k,
-			RXCLK				=> CLK500k,
-			RXDATA				=> KEYB_RxD,
-
-			CTSn				=> '0',
-			DCDn				=> '0',
-        
-			IRQn				=> IRQ_KEYBDn,
-			TXDATA				=> AMKB_TX
-			--RTSn				=> -- Not used.
-		);                                              
-ACIA_CS_I <= '1' when nFB_CS1 = '0'and FB_ADR(19 downto 3) = x"1FF80" else '0';		-- FFC00-FFC07 FFC00/8
-KEYB_RxD <= '1' when AMKB_REG(3) = '1' or PIC_AMKB_RX = '0' else '0';				-- TASTATUR DATEN VOM PIC(PS2) OR NORMAL
-FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else "ZZZZZZZZ";
--- AMKB_TX: SPIKES AUSFILTERN  ------------------------------------------
-	process(CLK2M, AMKB_RX, AMKB_REG)
-	begin
-		if rising_edge(CLK2M) then
-			IF AMKB_RX = '0' THEN
-				IF AMKB_REG < 16 THEN
-					AMKB_REG <= "00000";
-				ELSE
-					AMKB_REG <= AMKB_REG - 1;
-				END IF;
-			ELSE
-				IF AMKB_REG > 15 THEN
-					AMKB_REG <= "11111";
-				ELSE
-					AMKB_REG <= AMKB_REG + 1;
-				END IF;
-			END IF;
-		ELSE
-			AMKB_REG <= AMKB_REG;
-		end if;
-	END PROCESS;
-----------------------------------------------------------------------------
--- ACIA MIDI
-----------------------------------------------------------------------------
-	I_ACIA_MIDI: WF6850IP_TOP_SOC
-		port map(
-			CLK					=> MAIN_CLK,
-			RESETn				=> nRSTO,
-
-			CS2n				=> '0',
-			CS1					=> FB_ADR(2),
-			CS0					=> ACIA_CS_I,
-            E					=> ACIA_CS_I,
-			RWn					=> nFB_WR,
-			RS					=> FB_ADR(1),
-
-			DATA_IN				=> FB_AD(31 downto 24),
-			DATA_OUT			=> DATA_OUT_ACIA_II,
---			DATA_EN				=> DATA_EN_ACIA_II,
-
-			TXCLK				=> CLK500k,
-			RXCLK				=> CLK500k,
-			RXDATA				=> MIDI_IN,
-			CTSn				=> '0',
-			DCDn				=> '0',
-        
-			IRQn				=> IRQ_MIDIn,
-			TXDATA				=> MIDI_OUT
-			--RTSn				=> -- Not used.
-	    );                                              
-MIDI_TLR <= MIDI_OUT;
-MIDI_OLR <= MIDI_OUT;
-FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
-----------------------------------------------------------------------------
--- MFP
-----------------------------------------------------------------------------
-	I_MFP: WF68901IP_TOP_SOC
-		port map(  
-			-- System control:
-			CLK					=> MAIN_CLK,
-			RESETn				=> nRSTO,
-			-- Asynchronous bus control:
-			DSn					=> not LDS,
-			CSn					=> not MFP_CS,
-			RWn					=> nFB_WR,
- 			DTACKn				=> DTACK_OUT_MFPn,
-			-- Data and Adresses:
-			RS					=> FB_ADR(5 downto 1),
-			DATA_IN				=> FB_AD(23 downto 16),
-			DATA_OUT			=> DATA_OUT_MFP,
---			DATA_EN				=> DATA_EN_MFP,
-            GPIP_IN(7)			=> not DMA_DRQ_Q,
-            GPIP_IN(6)			=> not RI,
-			GPIP_IN(5)			=> DINTn,
-			GPIP_IN(4)			=> IRQ_ACIAn,
-			GPIP_IN(3)			=> DSP_INT,
-            GPIP_IN(2)			=> not CTS,
-            GPIP_IN(1)			=> not DCD,
-            GPIP_IN(0)			=> LP_BUSY,
-			-- GPIP_OUT			=>, -- Not used; all GPIPs are direction input.
-			-- GPIP_EN			=>, -- Not used; all GPIPs are direction input.
-			-- Interrupt control:
-			IACKn				=> not MFP_INTACK,
-			IEIn				=> '0',
-			-- IEOn				=>, -- Not used.
-			IRQn				=> nMFP_INT,
-			-- Timers and timer control:
-			XTAL1				=> CLK2M4576,
-            TAI					=> '0',
-			TBI				    => nBLANK,
-            -- TAO				=>,
-			-- TBO				=>,
-            -- TCO				=>,
-			TDO					=> TDO,
-			-- Serial I/O control:
-			RC					=> TDO,
-			TC					=> TDO,
-			SI					=> RxD, 
-			SO					=> TxD
-			-- SO_EN			=> MFP_SO_EN
-			-- DMA control:
-			-- RRn				=>,
-			-- TRn				=>
-		);
-
-MFP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3FE8" else '0';		-- FFA00/40
-MFP_INTACK <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20000" else '0'; 	--F002'0000
-LDS <= '1' when MFP_CS = '1' or MFP_INTACK = '1' else '0';
-FB_AD(23 downto 16) <= DATA_OUT_MFP when MFP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
-FB_AD(31 downto 10) <= "0000000000000000000000" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZ";
-FB_AD(9 downto 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZ";
-FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ";
-DINTn <= '0' when IDE_INT = '1' AND ACP_CONFIG[28] = '1' else
-         '0' when FDINT = '1' else
-         '0' when SCSI_INT = '1' AND ACP_CONFIG[28] = '1' else '1';
--- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN  ------------------------------------------
-	process(MAIN_CLK,nRSTO,IRQ_ACIAn,IRQ_KEYBDn,IRQ_MIDIn)
-	begin
-		if nRSTO = '0' THEN
-			IRQ_ACIAn <= '1';
-		elsif rising_edge(MAIN_CLK) then
-				IRQ_ACIAn <= IRQ_KEYBDn and IRQ_MIDIn;
-			else
-				IRQ_ACIAn <= IRQ_ACIAn;
-			end if;
-	END PROCESS;
-----------------------------------------------------------------------------
--- Sound
-----------------------------------------------------------------------------
- 	I_SOUND: WF2149IP_TOP_SOC
-		port map(
-			SYS_CLK				=> MAIN_CLK,
-			RESETn				=> nRSTO,
-
-			WAV_CLK				=> CLK2M,
-			SELn				=> '1',
-
-			BDIR				=> SNDIR_I,
-			BC2					=> '1',
-			BC1					=> SNDCS_I,
-
-			A9n					=> '0',
-			A8					=> '1',
-			DA_IN				=> FB_AD(31 downto 24),
-			DA_OUT 				=> DA_OUT_X,
-
-			IO_A_IN				=> x"00", -- All port pins are dedicated outputs.
-			IO_A_OUT(7)			=> nnIDE_RES,
-            IO_A_OUT(6)			=> LP_DIR_X,
-			IO_A_OUT(5)			=> LP_STR,
-			IO_A_OUT(4)			=> DTR,
-			IO_A_OUT(3)			=> RTS,
---			IO_A_OUT(2)			=> FDD_D1SEL,
-			IO_A_OUT(1)			=> DSA_D,
-			IO_A_OUT(0)			=> nSDSEL,
-			-- IO_A_EN			=>, -- Not required.
-			IO_B_IN				=> LP_D,
-			IO_B_OUT			=> LP_D_X,
- --			IO_B_EN				=> IO_B_EN,
-
-			OUT_A				=> YM_QA,
-			OUT_B				=> YM_QB,
-			OUT_C				=> YM_QC
-		);
-
-SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0';		-- 8800-8803 F8800/4
-SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0';
-SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0';
-FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ";
-LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ";
-LP_DIR <= LP_DIR_X;
-
-END FalconIO_SDCard_IDE_CF_architecture;

FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd

@@ -64,7 +64,7 @@ type BUSCYCLES is (INACTIVE, R_READ, R_WRITE, ADDRESS);
 component WF2149IP_WAVE
 	port(
 		RESETn		: in bit;
-		SYS_CLK		: in bit;
+		SYS_CLK		: in std_logic;
 
 		WAV_STRB	: in bit;
 

FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd

@@ -76,129 +76,130 @@
 --   Minor changes.
 --
 
-library ieee;
-use ieee.std_logic_1164.all;
-use work.wf2149ip_pkg.all;
+LIBRARY ieee;
+    USE ieee.std_logic_1164.ALL;
+    USE work.wf2149ip_pkg.ALL;
 
-entity WF2149IP_TOP_SOC is
-	port(
+ENTITY WF2149IP_TOP_SOC IS
+	PORT(
 		
-		SYS_CLK		: in bit; -- Read the inforation in the header!
-		RESETn   	: in bit;
+		SYS_CLK		: IN std_logic; -- Read the inforation in the header!
+		RESETn   	: IN bit;
 
-		WAV_CLK		: in bit; -- Read the inforation in the header!
-		SELn		: in bit;
+		WAV_CLK		: IN bit; -- Read the inforation in the header!
+		SELn		: IN bit;
 		
-		BDIR		: in bit;
-		BC2, BC1	: in bit;
+		BDIR		: IN bit;
+		BC2, BC1	: IN bit;
 
-		A9n, A8		: in bit;
-		DA_IN		: in std_logic_vector(7 downto 0);
-		DA_OUT		: out std_logic_vector(7 downto 0);
-		DA_EN		: out bit;
+		A9n, A8		: IN bit;
+		DA_IN		: IN std_logic_vector(7 DOWNTO 0);
+		DA_OUT		: OUT std_logic_vector(7 DOWNTO 0);
+		DA_EN		: OUT bit;
 		
-		IO_A_IN		: in bit_vector(7 downto 0);
-		IO_A_OUT	: out bit_vector(7 downto 0);
-		IO_A_EN		: out bit;
-		IO_B_IN		: in bit_vector(7 downto 0);
-		IO_B_OUT	: out bit_vector(7 downto 0);
-		IO_B_EN		: out bit;
+		IO_A_IN		: IN bit_vector(7 DOWNTO 0);
+		IO_A_OUT	: OUT bit_vector(7 DOWNTO 0);
+		IO_A_EN		: OUT bit;
+		IO_B_IN		: IN bit_vector(7 DOWNTO 0);
+		IO_B_OUT	: OUT bit_vector(7 DOWNTO 0);
+		IO_B_EN		: OUT bit;
 
-		OUT_A		: out bit; -- Analog (PWM) outputs.
-		OUT_B		: out bit;
-		OUT_C		: out bit
+		OUT_A		: OUT bit; -- Analog (PWM) outputs.
+		OUT_B		: OUT bit;
+		OUT_C		: OUT bit
 	);
-end WF2149IP_TOP_SOC;
+END WF2149IP_TOP_SOC;
 
-architecture STRUCTURE of WF2149IP_TOP_SOC is
-signal BUSCYCLE		: BUSCYCLES;
-signal DATA_OUT_I	: std_logic_vector(7 downto 0);
-signal DATA_EN_I	: bit;
-signal WAV_STRB		: bit;
-signal ADR_I		: bit_vector(3 downto 0);
-signal CTRL_REG		: bit_vector(7 downto 0);
-signal PORT_A		: bit_vector(7 downto 0);
-signal PORT_B		: bit_vector(7 downto 0);
-begin
-	P_WAVSTRB: process(RESETn, SYS_CLK)
-	variable LOCK	: boolean;
-	variable TMP	: bit;
-	begin
-		if RESETn = '0' then
+ARCHITECTURE rtl OF WF2149IP_TOP_SOC IS
+    SIGNAL BUSCYCLE		: BUSCYCLES;
+    SIGNAL DATA_OUT_I	: std_logic_vector(7 DOWNTO 0);
+    SIGNAL DATA_EN_I	: bit;
+    SIGNAL WAV_STRB		: bit;
+    SIGNAL ADR_I		: bit_vector(3 DOWNTO 0);
+    SIGNAL CTRL_REG		: bit_vector(7 DOWNTO 0);
+    SIGNAL PORT_A		: bit_vector(7 DOWNTO 0);
+    SIGNAL PORT_B		: bit_vector(7 DOWNTO 0);
+BEGIN
+	P_WAVSTRB: PROCESS(RESETn, SYS_CLK)
+        VARIABLE LOCK	: boolean;
+        VARIABLE TMP	: bit;
+	BEGIN
+		IF RESETn = '0' THEN
 			LOCK := false;
 			TMP := '0';
-		elsif SYS_CLK = '1' and SYS_CLK' event then
-			if WAV_CLK = '1' and LOCK = false then
+		ELSIF rising_edge(SYS_CLK) THEN
+			IF WAV_CLK = '1' and LOCK = false THEN
 				LOCK := true;
 				TMP := not TMP; -- Divider by 2.
-				case SELn is
-					when '1' 	=> WAV_STRB <= '1';
-					when others => WAV_STRB <= TMP;
-				end case;
-			elsif WAV_CLK = '0' then
+				
+                CASE SELn IS
+					WHEN '1' 	=> WAV_STRB <= '1';
+					WHEN OTHERS => WAV_STRB <= TMP;
+				END CASE;
+			ELSIF WAV_CLK = '0' THEN
 				LOCK := false;
 				WAV_STRB <= '0';
-			else
+			ELSE
 				WAV_STRB <= '0';
-			end if;
-		end if;
-	end process P_WAVSTRB;		
+			END IF;
+		END IF;
+	END PROCESS P_WAVSTRB;		
 
-	with BDIR & BC2 & BC1 select
-		BUSCYCLE <= INACTIVE	when "000" | "010" | "101",
-					ADDRESS 	when "001" | "100" | "111",
-					R_READ 		when "011",
-					R_WRITE 	when "110";
+	WITH BDIR & BC2 & BC1 SELECT
+		BUSCYCLE <= INACTIVE	WHEN "000" | "010" | "101",
+					ADDRESS 	WHEN "001" | "100" | "111",
+					R_READ 		WHEN "011",
+					R_WRITE 	WHEN "110";
 
-	ADDRESSLATCH: process(RESETn, SYS_CLK)
+	ADDRESSLATCH: PROCESS(RESETn, SYS_CLK)
 	-- This process is responsible to store the desired register
 	-- address. The default (after reset) is channel A fine tone 
 	-- adjustment.
-	begin
-		if RESETn = '0' then
-			ADR_I <= (others => '0');
-        elsif SYS_CLK = '1' and SYS_CLK' event then
-			if BUSCYCLE = ADDRESS and A9n = '0' and A8 = '1' and DA_IN(7 downto 4) = x"0" then
-				ADR_I <= To_BitVector(DA_IN(3 downto 0));
-			end if;
-		end if;
-	end process ADDRESSLATCH;	
+	BEGIN
+		IF RESETn = '0' THEN
+			ADR_I <= (OTHERS => '0');
+        ELSIF rising_edge(SYS_CLK) THEN
+			IF BUSCYCLE = ADDRESS AND A9n = '0' AND A8 = '1' AND DA_IN(7 DOWNTO 4) = x"0" THEN
+				ADR_I <= To_BitVector(DA_IN(3 DOWNTO 0));
+			END IF;
+		END IF;
+	END PROCESS ADDRESSLATCH;	
 
-	P_CTRL_REG: process(RESETn, SYS_CLK)
+	P_CTRL_REG: PROCESS(RESETn, SYS_CLK)
 	-- THIS is the Control register for the mixer and for the I/O ports.
-	begin
-		if RESETn = '0' then
+	BEGIN
+		IF RESETn = '0' THEN
 			CTRL_REG <= x"00";
-		elsif SYS_CLK = '1' and SYS_CLK' event then
-			if BUSCYCLE = R_WRITE and ADR_I = x"7" then
+		ELSIF rising_edge(SYS_CLK) THEN
+			IF BUSCYCLE = R_WRITE AND ADR_I = x"7" THEN
 				CTRL_REG <= To_BitVector(DA_IN);
-			end if;
-		end if;
-	end process P_CTRL_REG;
+			END IF;
+		END IF;
+	END PROCESS P_CTRL_REG;
 	
-	DIG_PORTS: process(RESETn, SYS_CLK)
-	begin
-		if RESETn = '0' then
+	DIG_PORTS: PROCESS(RESETn, SYS_CLK)
+	BEGIN
+		IF RESETn = '0' THEN
 			PORT_A <= x"00";
 			PORT_B <= x"00";
-		elsif SYS_CLK = '1' and SYS_CLK' event then
-			if BUSCYCLE = R_WRITE and ADR_I = x"E" then
+		ELSIF rising_edge(SYS_CLK) THEN
+			IF BUSCYCLE = R_WRITE AND ADR_I = x"E" THEN
 				PORT_A <= To_BitVector(DA_IN);
-			elsif BUSCYCLE = R_WRITE and ADR_I = x"F" then
+			ELSIF BUSCYCLE = R_WRITE and ADR_I = x"F" THEN
 				PORT_B <= To_BitVector(DA_IN);
-			end if;
-		end if;	
-	end process DIG_PORTS;
+			END IF;
+		END IF;	
+	END PROCESS DIG_PORTS;
 	-- Set port direction to input or to output:
-	IO_A_EN	<= '1' when CTRL_REG(6) = '1' else '0';
-	IO_B_EN <= '1' when CTRL_REG(7) = '1' else '0';
+	IO_A_EN	<= '1' WHEN CTRL_REG(6) = '1' ELSE '0';
+	IO_B_EN <= '1' WHEN CTRL_REG(7) = '1' ELSE '0';
 	IO_A_OUT <= PORT_A;
 	IO_B_OUT <= PORT_B;
 
 	I_PSG_WAVE: WF2149IP_WAVE
-		port map(
+		PORT MAP(
 			RESETn		=> RESETn,
-			SYS_CLK	=> SYS_CLK,
+			SYS_CLK	    => SYS_CLK,
 
 			WAV_STRB	=> WAV_STRB,
 
@@ -208,7 +209,7 @@ begin
 			DATA_EN		=> DATA_EN_I,
 			
 			BUSCYCLE	=> BUSCYCLE,
-			CTRL_REG	=> CTRL_REG(5 downto 0),
+			CTRL_REG	=> CTRL_REG(5 DOWNTO 0),
 						
 			OUT_A		=> OUT_A,
 			OUT_B		=> OUT_B,
@@ -216,14 +217,14 @@ begin
 		);
 
 	-- Read the ports and registers:
-	DA_EN <= 	'1' when DATA_EN_I = '1' else
-				'1' when BUSCYCLE = R_READ and ADR_I = x"7" else
-				'1' when BUSCYCLE = R_READ and ADR_I = x"E" else
-				'1' when BUSCYCLE = R_READ and ADR_I = x"F" else '0';
+	DA_EN <= 	'1' WHEN DATA_EN_I = '1' ELSE
+				'1' WHEN BUSCYCLE = R_READ and ADR_I = x"7" ELSE
+				'1' WHEN BUSCYCLE = R_READ and ADR_I = x"E" ELSE
+				'1' WHEN BUSCYCLE = R_READ and ADR_I = x"F" ELSE '0';
 				
-	DA_OUT <= 	DATA_OUT_I when DATA_EN_I = '1' else -- WAV stuff.
-				To_StdLogicVector(IO_A_IN) when BUSCYCLE = R_READ and ADR_I = x"E" else
-				To_StdLogicVector(IO_B_IN) when BUSCYCLE = R_READ and ADR_I = x"F" else
-				To_StdLogicVector(CTRL_REG) when BUSCYCLE = R_READ and ADR_I = x"7" else (others => '0');
+	DA_OUT <= 	DATA_OUT_I WHEN DATA_EN_I = '1' ELSE -- WAV stuff.
+				To_StdLogicVector(IO_A_IN) WHEN BUSCYCLE = R_READ and ADR_I = x"E" ELSE
+				To_StdLogicVector(IO_B_IN) WHEN BUSCYCLE = R_READ and ADR_I = x"F" ELSE
+				To_StdLogicVector(CTRL_REG) WHEN BUSCYCLE = R_READ and ADR_I = x"7" ELSE (OTHERS => '0');
 
-end STRUCTURE;
+END rtl;

FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd

@@ -65,7 +65,7 @@ use work.wf2149ip_pkg.all;
 entity WF2149IP_WAVE is
 	port(
 		RESETn		: in bit;
-		SYS_CLK		: in bit;
+		SYS_CLK		: in std_logic;
 
 		WAV_STRB	: in bit;
 

FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd

@@ -60,8 +60,8 @@
 --
 
 library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
+    use ieee.std_logic_1164.all;
+    use ieee.std_logic_unsigned.all;
 
 entity WF6850IP_TOP_SOC is
   port (

Interrupt_Handler/interrupt_handler.tdf

@@ -17,64 +17,64 @@ INCLUDE "lpm_bustri_BYT.inc";
 SUBDESIGN interrupt_handler
 (
 	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
-	MAIN_CLK : INPUT;
-	nFB_WR : INPUT;
-	nFB_CS1 : INPUT;
-	nFB_CS2 : INPUT;
-	FB_SIZE0 : INPUT;
-	FB_SIZE1 : INPUT;
-	FB_ADR[31..0] : INPUT;
-	PIC_INT : INPUT;
-	E0_INT : INPUT;
-	DVI_INT : INPUT;
-	nPCI_INTA : INPUT;
-	nPCI_INTB : INPUT;
-	nPCI_INTC : INPUT;
-	nPCI_INTD : INPUT;
-	nMFP_INT : INPUT;
-	nFB_OE : INPUT;
-	DSP_INT : INPUT;
-	VSYNC : INPUT;
-	HSYNC : INPUT;
-	DMA_DRQ : INPUT;
-	nIRQ[7..2] : OUTPUT;
-	INT_HANDLER_TA : OUTPUT;
-	ACP_CONF[31..0] : OUTPUT;
-	TIN0 : OUTPUT;
-	FB_AD[31..0] : BIDIR;
+	MAIN_CLK            : INPUT;
+	nFB_WR              : INPUT;
+	nFB_CS1             : INPUT;
+	nFB_CS2             : INPUT;
+	FB_SIZE0            : INPUT;
+	FB_SIZE1            : INPUT;
+	FB_ADR[31..0]       : INPUT;
+	PIC_INT             : INPUT;
+	E0_INT              : INPUT;
+	DVI_INT             : INPUT;
+	nPCI_INTA           : INPUT;
+	nPCI_INTB           : INPUT;
+	nPCI_INTC           : INPUT;
+	nPCI_INTD           : INPUT;
+	nMFP_INT            : INPUT;
+	nFB_OE              : INPUT;
+	DSP_INT             : INPUT;
+	VSYNC               : INPUT;
+	HSYNC               : INPUT;
+	DMA_DRQ             : INPUT;
+	nIRQ[7..2]          : OUTPUT;
+	INT_HANDLER_TA      : OUTPUT;
+	ACP_CONF[31..0]     : OUTPUT;
+	TIN0                : OUTPUT;
+	FB_AD[31..0]        : BIDIR;
 	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
 )
 
 VARIABLE
-	FB_B[3..0]				:NODE;
-	INT_CTR[31..0]			:DFFE;
-	INT_CTR_CS				:NODE;
-	INT_LATCH[31..0]		:DFF;
-	INT_LATCH_CS			:NODE;
-	INT_CLEAR[31..0]		:DFF;
-	INT_CLEAR_CS			:NODE;
-	INT_IN[31..0]			:NODE;
-	INT_ENA[31..0]			:DFFE;
-	INT_ENA_CS				:NODE;
-	ACP_CONF[31..0]			:DFFE;
-	ACP_CONF_CS				:NODE;
-	PSEUDO_BUS_ERROR		:NODE;
-	UHR_AS					:NODE;
-	UHR_DS					:NODE;
-	RTC_ADR[5..0]			:DFFE;
-	ACHTELSEKUNDEN[2..0]	:DFFE;
-	WERTE[7..0][63..0]		:DFFE;			-- WERTE REGISTER 0-63
-	PIC_INT_SYNC[2..0]		:DFF;
-	INC_SEC					:NODE;
-	INC_MIN					:NODE;
-	INC_STD					:NODE;
-	INC_TAG					:NODE;
+	FB_B[3..0]				    :NODE;
+	INT_CTR[31..0]			    :DFFE;
+	INT_CTR_CS				    :NODE;
+	INT_LATCH[31..0]		    :DFF;
+	INT_LATCH_CS			    :NODE;
+	INT_CLEAR[31..0]		    :DFF;
+	INT_CLEAR_CS			    :NODE;
+	INT_IN[31..0]			    :NODE;
+	INT_ENA[31..0]			    :DFFE;
+	INT_ENA_CS				    :NODE;
+	ACP_CONF[31..0]			    :DFFE;
+	ACP_CONF_CS				    :NODE;
+	PSEUDO_BUS_ERROR		    :NODE;
+	UHR_AS					    :NODE;
+	UHR_DS					    :NODE;
+	RTC_ADR[5..0]			    :DFFE;
+	ACHTELSEKUNDEN[2..0]	    :DFFE;
+	WERTE[7..0][63..0]		    :DFFE;			-- WERTE REGISTER 0-63
+	PIC_INT_SYNC[2..0]		    :DFF;
+	INC_SEC					    :NODE;
+	INC_MIN					    :NODE;
+	INC_STD					    :NODE;
+	INC_TAG					    :NODE;
 	ANZAHL_TAGE_DES_MONATS[7..0]:NODE;
-	WINTERZEIT				:NODE;
-	SOMMERZEIT				:NODE;
-	INC_MONAT				:NODE;
-	INC_JAHR				:NODE;
-	UPDATE_ON				:NODE;
+	WINTERZEIT				    :NODE;
+	SOMMERZEIT				    :NODE;
+	INC_MONAT				    :NODE;
+	INC_JAHR				    :NODE;
+	UPDATE_ON				    :NODE;
 	
 BEGIN
 -- BYT SELECT
@@ -91,7 +91,7 @@ BEGIN
 		# !FB_SIZE1 &  FB_SIZE0 &  FB_ADR1 &  FB_ADR0	-- LLBYT
 		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
 
--- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSL<53>SEN, 1=INT7 AUSL<53>SEN
+-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSL<53>SEN, 1=INT7 AUSL<53>SEN
 	INT_CTR[].CLK = MAIN_CLK;
 	INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000";						-- $10000/4
 	INT_CTR[] = FB_AD[];
@@ -99,6 +99,7 @@ BEGIN
 	INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR;
 	INT_CTR[15..8].ENA  = INT_CTR_CS & FB_B2 & !nFB_WR;
 	INT_CTR[7..0].ENA   = INT_CTR_CS & FB_B3 & !nFB_WR;
+    
 -- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
 	INT_ENA[].CLK = MAIN_CLK;
 	INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001";						-- $10004/4
@@ -107,6 +108,7 @@ BEGIN
 	INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR;
 	INT_ENA[15..8].ENA  = INT_ENA_CS & FB_B2 & !nFB_WR;
 	INT_ENA[7..0].ENA   = INT_ENA_CS & FB_B3 & !nFB_WR;
+    
 -- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR
 	INT_CLEAR[].CLK = MAIN_CLK;
 	INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002";						-- $10008/4
@@ -114,8 +116,10 @@ BEGIN
 	INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR;
 	INT_CLEAR[15..8]  = FB_AD[15..8]  & INT_CLEAR_CS & FB_B2 & !nFB_WR;
 	INT_CLEAR[7..0]   = FB_AD[7..0]   & INT_CLEAR_CS & FB_B3 & !nFB_WR;
+    
 -- INTERRUPT LATCH REGISTER READ ONLY
 	INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003";						-- $1000C/4
+    
 -- INTERRUPT
 	!nIRQ2 = HSYNC 						& INT_ENA[26];
 	!nIRQ3 = INT_CTR0 					& INT_ENA[27];
@@ -139,6 +143,7 @@ PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8"			-- SCC
 							#  FB_ADR[19..4]==H"F890"			-- DMA SOUND
 							#  FB_ADR[19..4]==H"F891"			-- DMA SOUND
 							#  FB_ADR[19..4]==H"F892");			-- DMA SOUND
+                            
 -- IF VIDEO ADR CHANGE
 TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2
 
@@ -176,6 +181,7 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR H
 	INT_IN29 = INT_LATCH[]!=H"00000000";
 	INT_IN30 = !nMFP_INT; 
 	INT_IN31 = DMA_DRQ; 
+    
 --***************************************************************************************
 -- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE 
 	ACP_CONF[].CLK = MAIN_CLK;
@@ -324,9 +330,12 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR H
 	WERTE[][61].ENA = RTC_ADR[]==61 & UHR_DS & !nFB_WR;
 	WERTE[][62].ENA = RTC_ADR[]==62 & UHR_DS & !nFB_WR;
 	WERTE[][63].ENA = RTC_ADR[]==63 & UHR_DS & !nFB_WR;
-	PIC_INT_SYNC[].CLK = MAIN_CLK;	PIC_INT_SYNC[0] = PIC_INT;
+	
+    PIC_INT_SYNC[].CLK = MAIN_CLK;
+    PIC_INT_SYNC[0] = PIC_INT;
 	PIC_INT_SYNC[1] = PIC_INT_SYNC[0];
 	PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0];
+    
 	UPDATE_ON = !WERTE[7][11];		
 	WERTE[6][10].CLRN = GND;	-- KEIN UIP
 	UPDATE_ON = !WERTE[7][11];	-- UPDATE ON OFF
@@ -334,48 +343,57 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR H
 	WERTE[1][11] = VCC;	-- IMMER 24H FORMAT
 	WERTE[0][11] = VCC;	-- IMMER SOMMERZEITKORREKTUR
 	WERTE[7][13] = VCC;	-- IMMER RICHTIG
--- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN F<>R R<>CKSCHALTUNG)
+    
+-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN F<>R R<>CKSCHALTUNG)
 	SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4  & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL
 	WERTE[0][13] = SOMMERZEIT;
 	WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT);
 	WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13];  --LETZTER SONNTAG IM OKTOBER
+    
 -- ACHTELSEKUNDEN
 	ACHTELSEKUNDEN[].CLK = MAIN_CLK;
 	ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1;
 	ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON;
+    
 -- SEKUNDEN
 	INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON;   
-	WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);			-- SEKUNDEN Z<>HLEN BIS 59
+	WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);			-- SEKUNDEN Z<>HLEN BIS 59
 	WERTE[][0].ENA  = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);	
+    
 -- MINUTEN
 	INC_MIN = INC_SEC & WERTE[][0]==59;							--  
-	WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR);			-- MINUTEN Z<>HLEN BIS 59
+	WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR);			-- MINUTEN Z<>HLEN BIS 59
 	WERTE[][2].ENA  = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR);								--  
+    
 -- STUNDEN
 	INC_STD = INC_MIN & WERTE[][2]==59;							  
-	WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR);  -- STUNDEN Z<>HLEN BIS 23
+	WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR);  -- STUNDEN Z<>HLEN BIS 23
 	WERTE[][4].ENA  = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR);		-- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT	 
 -- WOCHENTAG UND TAG 
+
 	INC_TAG = INC_STD & WERTE[][2]==23;						
-	WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR)				-- WOCHENTAG Z<>HLEN BIS 7
+	WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR)				-- WOCHENTAG Z<>HLEN BIS 7
 			   # 1              & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);			-- DANN BEI 1 WEITER
 	WERTE[][6].ENA  = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);
 	ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12)
 							 # 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11)  
 							 # 29 &  WERTE[][8]==2 & WERTE[1..0][9]==0  
 							 # 28 &  WERTE[][8]==2 & WERTE[1..0][9]!=0;  
-	WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR)  	-- TAG Z<>HLEN BIS MONATSENDE
+	WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR)  	-- TAG Z<>HLEN BIS MONATSENDE
 			   # 1              & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR);		-- DANN BEI 1 WEITER
 	WERTE[][7].ENA  = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR);								--  
+
 -- MONATE
 	INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[];							--  
-	WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR)					-- MONATE Z<>HLEN BIS 12
+	WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR)					-- MONATE Z<>HLEN BIS 12
 			   # 1              & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);					-- DANN BEI 1 WEITER
 	WERTE[][8].ENA  = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);
+    
 -- JAHR		   
 	INC_JAHR = INC_MONAT & WERTE[][8]==12;							--  
-	WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);					-- JAHRE Z<>HLEN BIS 99
+	WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);					-- JAHRE Z<>HLEN BIS 99
 	WERTE[][9].ENA  = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);
+    
 -- TRISTATE OUTPUT
 
 	FB_AD[31..24] = lpm_bustri_BYT(
@@ -457,6 +475,7 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR H
 				 # INT_CLEAR_CS & INT_IN[23..16]
 				 # ACP_CONF_CS  & ACP_CONF[23..16]
 				  ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+                  
 	FB_AD[15..8] = lpm_bustri_BYT(
 					INT_CTR_CS   & INT_CTR[15..8] 
 				  #	INT_ENA_CS   & INT_ENA[15..8]
@@ -464,6 +483,7 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR H
 				  # INT_CLEAR_CS & INT_IN[15..8]
 				  # ACP_CONF_CS  & ACP_CONF[15..8]
 				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+                  
 	FB_AD[7..0] = lpm_bustri_BYT(
 					INT_CTR_CS   & INT_CTR[7..0] 
 				  #	INT_ENA_CS   & INT_ENA[7..0]

Video/BLITTER/BLITTER.vhd

@@ -26,7 +26,7 @@ USE ieee.std_logic_1164.all;
 
 --  Entity Declaration
 
-ENTITY BLITTER IS
+ENTITY blitter IS
 	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
 	PORT
 	(
@@ -61,7 +61,7 @@ END BLITTER;
 
 --  Architecture Body
 
-ARCHITECTURE BLITTER_architecture OF BLITTER IS
+ARCHITECTURE BLITTER_architecture OF blitter IS
 
 	
 BEGIN

Video/DDR_CTR.tdf

@@ -58,9 +58,9 @@ SUBDESIGN DDR_CTR
 )
 
 VARIABLE
-	FB_REGDDR				:MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);	
-	DDR_SM					:MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8,					-- START (NORMAL 8 CYCLES TOTAL = 60ns)
-													   DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, 		 					-- CONFIG 
+	FB_REGDDR				:MACHINE WITH STATES(FR_WAIT, FR_S0, FR_S1, FR_S2, FR_S3);	
+	DDR_SM					:MACHINE WITH STATES(DS_T1, DS_T2A, DS_T2B, DS_T3, DS_N5, DS_N6, DS_N7, DS_N8,				-- START (NORMAL 8 CYCLES TOTAL = 60ns)
+													    DS_C2, DS_C3, DS_C4, DS_C5, DS_C6, DS_C7, 	 					-- CONFIG 
 												                   DS_T4R,DS_T5R,										-- READ CPU UND BLITTER,  
 												                   DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W,		 	-- WRITE CPU UND BLITTER
 												                   DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, 	-- READ FIFO
@@ -129,7 +129,8 @@ VARIABLE
 	
 BEGIN
 	LINE =  FB_SIZE0 &  FB_SIZE1;
--- BYT SELECT
+
+    -- BYT SELECT
 	FB_B0 = FB_ADR[1..0]==0 								-- ADR==0
 		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
 	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
@@ -140,7 +141,8 @@ BEGIN
 	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
 		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
 		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
--- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR)  --------------------------------------------------
+
+    -- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR)  --------------------------------------------------
 	FB_REGDDR.CLK = MAIN_CLK;
 	CASE FB_REGDDR IS
 		WHEN FR_WAIT => 
@@ -198,7 +200,8 @@ BEGIN
 				FB_REGDDR = FR_WAIT;
 			END IF;
 	END CASE;
--- DDR STEUERUNG -----------------------------------------------------
+
+    -- DDR STEUERUNG -----------------------------------------------------
 -- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; 
 	VCKE = VIDEO_RAM_CTR0;
 	nVCS = !VIDEO_RAM_CTR1;
@@ -220,34 +223,39 @@ BEGIN
 	FIFO_AC.CLK = DDRCLK0;
 	BLITTER_AC.CLK = DDRCLK0;
 	DDRWR_D_SEL1 = BLITTER_AC;
--- SELECT LOGIC
+
+    -- SELECT LOGIC
 	DDR_SEL  = FB_ALE & FB_AD[31..30]==B"01";
 	DDR_CS.CLK = MAIN_CLK;
 	DDR_CS.ENA = FB_ALE;
 	DDR_CS	 = DDR_SEL;
--- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP<53>TER
+
+    -- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP<53>TER
 	CPU_SIG = DDR_SEL & (nFB_WR # !LINE)  & !DDR_CONFIG					-- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
 			# DDR_SEL          			  &  DDR_CONFIG					-- CONFIG SOFORT LOS
-			# FB_REGDDR==FR_S1 & !nFB_WR; 								-- LINE WRITE SP<53>TER
+			# FB_REGDDR==FR_S1 & !nFB_WR; 								-- LINE WRITE SP<53>TER
 	CPU_REQ.CLK = DDR_SYNC_66M;
 	CPU_REQ = CPU_SIG 
 			# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC;		-- HALTEN BUS CYC BEGONNEN ODER FERTIG
 	BUS_CYC.CLK = DDRCLK0;
 	BUS_CYC = BUS_CYC & !BUS_CYC_END;
+    
 	-- STATE MACHINE SYNCHRONISIEREN -----------------
 	MCS[].CLK = DDRCLK0;
 	MCS0 = MAIN_CLK;
 	MCS1 = MCS0;		
 	CPU_DDR_SYNC.CLK = DDRCLK0;
 	CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS;				-- NUR 1 WENN EIN
-	---------------------------------------------------
+	
+    ---------------------------------------------------
 	VA_S[].CLK = DDRCLK0;
 	BA_S[].CLK = DDRCLK0;
 	VA[] =  VA_S[];
 	BA[] =  BA_S[];
 	VA_P[].CLK = DDRCLK0;
 	BA_P[].CLK = DDRCLK0;
--- DDR STATE MACHINE  -----------------------------------------------
+
+    -- DDR STATE MACHINE  -----------------------------------------------
 	DDR_SM.CLK = DDRCLK0;
 	CASE DDR_SM IS
 		WHEN DS_T1 =>
@@ -336,12 +344,13 @@ BEGIN
 					END IF;
 				END IF;
 			END IF;
--- READ			
+
+        -- READ			
 		WHEN DS_T4R =>
 			CPU_AC = CPU_AC;
 			BLITTER_AC = BLITTER_AC;
 			VCAS = VCC;															
-			SR_DDR_FB = CPU_AC;										-- READ DATEN F<>R CPU
+			SR_DDR_FB = CPU_AC;										-- READ DATEN F<>R CPU
 			SR_BLITTER_DACK = BLITTER_AC;							-- BLITTER DACK AND BLITTER LATCH DATEN
 			DDR_SM = DS_T5R;	
 			
@@ -357,7 +366,8 @@ BEGIN
 				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
 				DDR_SM = DS_CB6;
 			END IF;
--- WRITE			
+
+        -- WRITE			
 		WHEN DS_T4W =>
 			CPU_AC = CPU_AC;
 			BLITTER_AC = BLITTER_AC;
@@ -383,7 +393,7 @@ BEGIN
 			VCAS = VCC;															
 			VWE  = VCC;
 			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITER
-			SR_DDRWR_D_SEL = VCC;									-- 2. H<>LFTE WRITE DATEN SELEKTIEREN
+			SR_DDRWR_D_SEL = VCC;									-- 2. H<>LFTE WRITE DATEN SELEKTIEREN
 			SR_VDMP[] = LINE & B"11111111";							-- WENN LINE DANN ACTIV 
 			DDR_SM = DS_T7W;
 
@@ -391,7 +401,7 @@ BEGIN
 			CPU_AC = CPU_AC;
 			BLITTER_AC = BLITTER_AC;
 			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITE
-			SR_DDRWR_D_SEL = VCC;									-- 2. H<>LFTE WRITE DATEN SELEKTIEREN
+			SR_DDRWR_D_SEL = VCC;									-- 2. H<>LFTE WRITE DATEN SELEKTIEREN
 			DDR_SM = DS_T8W;
 
 		WHEN DS_T8W =>								 
@@ -407,7 +417,8 @@ BEGIN
 				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
 				DDR_SM = DS_CB6;
 			END IF;
--- FIFO READ 
+
+        -- FIFO READ 
 		WHEN DS_T4F =>
 			VCAS = VCC;															
 			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
@@ -497,7 +508,8 @@ BEGIN
 				DDR_SM = DS_T7F;
 			END IF;	
 
--- CONFIG CYCLUS
+
+        -- CONFIG CYCLUS
 		WHEN DS_C2 =>
 			DDR_SM = DS_C3;
 		WHEN DS_C3 =>
@@ -520,18 +532,20 @@ BEGIN
 			VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
 			VWE	 = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
 			DDR_SM = DS_N8;
--- CLOSE FIFO BANK
+
+        -- CLOSE FIFO BANK
 		WHEN DS_CB6 =>
 			FIFO_BANK_NOT_OK = VCC;						-- AUF NOT OK 
-			VRAS = VCC;									-- B<>NKE SCHLIESSEN
+			VRAS = VCC;									-- B<>NKE SCHLIESSEN
 			VWE = VCC;
 			DDR_SM = DS_N7;
 		WHEN DS_CB8 =>
 			FIFO_BANK_NOT_OK = VCC;						-- AUF NOT OK 
-			VRAS = VCC;									-- B<>NKE SCHLIESSEN
+			VRAS = VCC;									-- B<>NKE SCHLIESSEN
 			VWE = VCC;
 			DDR_SM = DS_T1;
--- REFRESH 70NS = 10 ZYCLEN
+
+        -- REFRESH 70NS = 10 ZYCLEN
 		WHEN DS_R2 =>
 			IF DDR_REFRESH_SIG[]==9 THEN				-- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN
 				VRAS = VCC;								-- ALLE BANKS SCHLIESSEN
@@ -552,7 +566,8 @@ BEGIN
 			DDR_SM = DS_R6;
 		WHEN DS_R6 =>
 			DDR_SM = DS_N5;
--- LEERSCHLAUFE			
+
+        -- LEERSCHLAUFE			
 		WHEN DS_N5 =>
 			DDR_SM = DS_N6;
 		WHEN DS_N6 =>
@@ -584,14 +599,14 @@ BEGIN
 	FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00");
 	FIFO_BANK_OK.CLK = DDRCLK0;
 	FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK;
-	-- Z<>HLER R<>CKSETZEN WENN CLR FIFO ----------------
+	-- Z<>HLER R<>CKSETZEN WENN CLR FIFO ----------------
 	CLR_FIFO_SYNC.CLK =DDRCLK0;
 	CLR_FIFO_SYNC = CLR_FIFO;				-- SYNCHRONISIEREN
 	CLEAR_FIFO_CNT.CLK  = DDRCLK0;
 	CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE;
 	STOP.CLK = DDRCLK0;
 	STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT;
-	-- Z<>HLEN -----------------------------------------------
+	-- Z<>HLEN -----------------------------------------------
 	VIDEO_ADR_CNT[].CLK = DDRCLK0;
 	VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT;
 	VIDEO_ADR_CNT[] =  CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]
@@ -608,12 +623,12 @@ BEGIN
 -- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
 -----------------------------------------------------------------------------------------
 	DDR_REFRESH_CNT[].CLK = CLK33M;
-	DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1;													-- Z<>HLEN 0-2047 
+	DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1;													-- Z<>HLEN 0-2047 
 	REFRESH_TIME.CLK = DDRCLK0;
 	REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK;											-- SYNC
 	DDR_REFRESH_SIG[].CLK = DDRCLK0;												
 	DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6;				
-	DDR_REFRESH_SIG[] =  REFRESH_TIME & 9                     & DDR_REFRESH_ON & !DDR_CONFIG	-- 9 ST<53>CK (8 REFRESH UND 1 ALS VORLAUF)
+	DDR_REFRESH_SIG[] =  REFRESH_TIME & 9                     & DDR_REFRESH_ON & !DDR_CONFIG	-- 9 ST<53>CK (8 REFRESH UND 1 ALS VORLAUF)
 					  # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; 	-- MINUS 1 WENN GEMACHT
 	DDR_REFRESH_REQ.CLK = DDRCLK0;
 	DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG;

Video/VIDEO_MOD_MUX_CLUTCTR.tdf

@@ -1,4 +1,4 @@
-TITLE "VIDEO MODUSE UND CLUT CONTROL";
+TITLE "VIDEO MODI AND CLUT CONTROL";
 
 -- CREATED BY FREDI ASCHWANDEN
 
@@ -8,58 +8,58 @@ INCLUDE "lpm_bustri_BYT.inc";
 -- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
 -- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
 
-SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
+SUBDESIGN video_mod_mux_clutctr
 (
 	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
-	nRSTO : INPUT;
-	MAIN_CLK : INPUT;
-	nFB_CS1 : INPUT;
-	nFB_CS2 : INPUT;
-	nFB_CS3 : INPUT;
-	nFB_WR : INPUT;
-	nFB_OE : INPUT;
-	FB_SIZE0 : INPUT;
-	FB_SIZE1 : INPUT;
-	nFB_BURST : INPUT;
-	FB_ADR[31..0] : INPUT;
-	CLK33M : INPUT;
-	CLK25M : INPUT;
-	BLITTER_RUN : INPUT;
-	CLK_VIDEO : INPUT;
-	VR_D[8..0] : INPUT;
-	VR_BUSY : INPUT;
-	COLOR8 : OUTPUT;
-	ACP_CLUT_RD : OUTPUT;
-	COLOR1 : OUTPUT;
-	FALCON_CLUT_RDH : OUTPUT;
-	FALCON_CLUT_RDL : OUTPUT;
-	FALCON_CLUT_WR[3..0] : OUTPUT;
-	ST_CLUT_RD : OUTPUT;
-	ST_CLUT_WR[1..0] : OUTPUT;
-	CLUT_MUX_ADR[3..0] : OUTPUT;
-	HSYNC : OUTPUT;
-	VSYNC : OUTPUT;
-	nBLANK : OUTPUT;
-	nSYNC : OUTPUT;
-	nPD_VGA : OUTPUT;
-	FIFO_RDE : OUTPUT;
-	COLOR2 : OUTPUT;
-	COLOR4 : OUTPUT;
-	PIXEL_CLK : OUTPUT;
-	CLUT_OFF[3..0] : OUTPUT;
-	BLITTER_ON : OUTPUT;
-	VIDEO_RAM_CTR[15..0] : OUTPUT;
-	VIDEO_MOD_TA : OUTPUT;
-	CCR[23..0] : OUTPUT;
-	CCSEL[2..0] : OUTPUT;
-	ACP_CLUT_WR[3..0] : OUTPUT;
-	INTER_ZEI : OUTPUT;
-	DOP_FIFO_CLR : OUTPUT;
-	VIDEO_RECONFIG : OUTPUT;
-	VR_WR : OUTPUT;
-	VR_RD : OUTPUT;
-	CLR_FIFO : OUTPUT;
-	FB_AD[31..0] : BIDIR;
+	nRSTO                   : INPUT;
+	MAIN_CLK                : INPUT;
+	nFB_CS1                 : INPUT;
+	nFB_CS2                 : INPUT;
+	nFB_CS3                 : INPUT;
+	nFB_WR                  : INPUT;
+	nFB_OE                  : INPUT;
+	FB_SIZE0                : INPUT;
+	FB_SIZE1                : INPUT;
+	nFB_BURST               : INPUT;
+	FB_ADR[31..0]           : INPUT;
+	CLK33M                  : INPUT;
+	CLK25M                  : INPUT;
+	BLITTER_RUN             : INPUT;
+	CLK_VIDEO               : INPUT;
+	VR_D[8..0]              : INPUT;
+	VR_BUSY                 : INPUT;
+	COLOR8                  : OUTPUT;
+	ACP_CLUT_RD             : OUTPUT;
+	COLOR1                  : OUTPUT;
+	FALCON_CLUT_RDH         : OUTPUT;
+	FALCON_CLUT_RDL         : OUTPUT;
+	FALCON_CLUT_WR[3..0]    : OUTPUT;
+	ST_CLUT_RD              : OUTPUT;
+	ST_CLUT_WR[1..0]        : OUTPUT;
+	CLUT_MUX_ADR[3..0]      : OUTPUT;
+	HSYNC                   : OUTPUT;
+	VSYNC                   : OUTPUT;
+	nBLANK                  : OUTPUT;
+	nSYNC                   : OUTPUT;
+	nPD_VGA                 : OUTPUT;
+	FIFO_RDE                : OUTPUT;
+	COLOR2                  : OUTPUT;
+	COLOR4                  : OUTPUT;
+	PIXEL_CLK               : OUTPUT;
+	CLUT_OFF[3..0]          : OUTPUT;
+	BLITTER_ON              : OUTPUT;
+	VIDEO_RAM_CTR[15..0]    : OUTPUT;
+	VIDEO_MOD_TA            : OUTPUT;
+	CCR[23..0]              : OUTPUT;
+	CCSEL[2..0]             : OUTPUT;
+	ACP_CLUT_WR[3..0]       : OUTPUT;
+	INTER_ZEI               : OUTPUT;
+	DOP_FIFO_CLR            : OUTPUT;
+	VIDEO_RECONFIG          : OUTPUT;
+	VR_WR                   : OUTPUT;
+	VR_RD                   : OUTPUT;
+	CLR_FIFO                : OUTPUT;
+	FB_AD[31..0]            : BIDIR;
 	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
 )
 
@@ -98,12 +98,12 @@ VARIABLE
 	VDL_LWD[15..0]				:DFFE;
 	VDL_LWD_CS					:NODE;
 -- DIV. CONTROL REGISTER
-	CLUT_TA						:DFF;  			-- BRAUCHT EIN WAITSTAT
+	CLUT_TA						:DFF;  			-- needs one wait state
 	HSYNC						:DFF;
 	HSYNC_I[7..0]				:DFF;
-	HSY_LEN[7..0]				:DFF;			-- L<EFBFBD>NGE HSYNC PULS IN PIXEL_CLK
+	HSY_LEN[7..0]				:DFF;			-- length of hsync pulse in pixel_clk
 	HSYNC_START					:DFF;
-	LAST						:DFF;			-- LETZTES PIXEL EINER ZEILE ERREICHT
+	LAST						:DFF;			-- reached last pixel of a line
 	VSYNC						:DFF;
 	VSYNC_START					:DFFE;
 	VSYNC_I[2..0]				:DFFE;
@@ -191,60 +191,90 @@ VARIABLE
 	VDL_VCT_CS					:NODE;
 	VDL_VMD[3..0]				:DFFE;
 	VDL_VMD_CS					:NODE;
+    ACP_VCTR6_DUP               : NODE;
 
 BEGIN
--- BYT SELECT 32 BIT
-	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
-	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
+    -- BYT SELECT 32 BIT
+	FB_B0 = FB_ADR[1..0] == 0;								-- ADR==0
+	FB_B1 = FB_ADR[1..0] == 1								-- ADR==1
 		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
 		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
+	FB_B2 = FB_ADR[1..0] == 2								-- ADR==2
 		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
+	FB_B3 = FB_ADR[1..0] == 3								-- ADR==3
 		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
 		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
--- BYT SELECT 16 BIT
-	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
-	FB_16B1 = FB_ADR[0]==1									-- ADR==1
+
+    -- BYT SELECT 16 BIT
+	FB_16B0 = FB_ADR[0] == 0;								-- ADR==0
+	FB_16B1 = FB_ADR[0] == 1								-- ADR==1
 		    # !(!FB_SIZE1 & FB_SIZE0);						-- NOT BYT
--- ACP CLUT --
-	ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0";						-- 0-3FF/1024
+
+    -- ACP CLUT --
+	ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10] == H"0";		-- 0-3FF/1024
 	ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
 	ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR;
-	CLUT_TA.CLK = MAIN_CLK;
+	
+    CLUT_TA.CLK = MAIN_CLK;
 	CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA;
---FALCON CLUT --
-	FALCON_CLUT_CS  = !nFB_CS1 & FB_ADR[19..10]==H"3E6";				-- $F9800/$400
+
+    
+    --FALCON CLUT --
+	FALCON_CLUT_CS  = !nFB_CS1 & FB_ADR[19..10] == H"3E6";				-- $F9800/$400
 	FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1;				-- HIGH WORD
 	FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE &  FB_ADR1;				-- LOW WORD
 	FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
 	FALCON_CLUT_WR[3..2] = FB_16B[] &  FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
--- ST CLUT --
-	ST_CLUT_CS  = !nFB_CS1 & FB_ADR[19..5]==H"7C12";					-- $F8240/$20
+
+    
+    -- ST CLUT --
+	ST_CLUT_CS  = !nFB_CS1 & FB_ADR[19..5] == H"7C12";					-- $F8240/$20
 	ST_CLUT_RD  = ST_CLUT_CS & !nFB_OE;
 	ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR;
--- ST SHIFT MODE
+
+    
+    -- ST SHIFT MODE
 	ST_SHIFT_MODE[].CLK = MAIN_CLK;
-	ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130";				-- $F8260/2
+	ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C130";			-- $F8260/2
 	ST_SHIFT_MODE[] = FB_AD[25..24];
 	ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
-	COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- MONO
-	COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 4 FARBEN
-	COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 16 FARBEN
--- FALCON SHIFT MODE
+	
+    COLOR1 = ST_SHIFT_MODE[] == B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- MONO
+	COLOR2 = ST_SHIFT_MODE[] == B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 4 FARBEN
+	COLOR4 = ST_SHIFT_MODE[] == B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 16 FARBEN
+
+    
+    -- FALCON SHIFT MODE
 	FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
-	FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133";			-- $F8266/2
+	FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C133";			-- $F8266/2
 	FALCON_SHIFT_MODE[] = FB_AD[26..16];
 	FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
 	FALCON_SHIFT_MODE[7..0].ENA  = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
-	CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
-	COLOR1  = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
+	
+    CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
+	
+    COLOR1  = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
 	COLOR8  = FALCON_SHIFT_MODE4  & !COLOR16           & FALCON_VIDEO & !ACP_VIDEO_ON;
 	COLOR16 = FALCON_SHIFT_MODE8                       & FALCON_VIDEO & !ACP_VIDEO_ON;
 	COLOR4  = !COLOR1             & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
--- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
+
+    
+    -- ACP VIDEO CONTROL
+    -- BIT 0=ACP VIDEO ON,
+    --     1=POWER ON VIDEO DAC,
+    --     2=ACP 24BIT,
+    --     3=ACP 16BIT,
+    --     4=ACP 8BIT,
+    --     5=ACP 1BIT,
+    --     6=FALCON SHIFT MODE,
+    --     7=ST SHIFT MODE,
+    --     9..8= VCLK FREQUENZ,
+    --     15=-SYNC ALLOWED,
+    --     31..16=VIDEO_RAM_CTR,
+    --     25=RANDFARBE EINSCHALTEN,
+    --     26=STANDARD ATARI SYNCS
 	ACP_VCTR[].CLK = MAIN_CLK;
-	ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100";						-- $400/4
+	ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2] == H"100";						-- $400/4
 	ACP_VCTR[31..8] = FB_AD[31..8];
 	ACP_VCTR[5..0] = FB_AD[5..0];
 	ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
@@ -253,9 +283,11 @@ BEGIN
 	ACP_VCTR[5..0].ENA   = ACP_VCTR_CS & FB_B3 & !nFB_WR;
 	ACP_VIDEO_ON = ACP_VCTR0;
 	nPD_VGA = ACP_VCTR1;
-	-- ATARI MODUS
-	ATARI_SYNC = ACP_VCTR26;			-- WENN 1 AUTOMATISCHE AUFL<46>SUNG
-	-- HORIZONTAL TIMING 640x480
+	
+    -- ATARI MODUS
+	ATARI_SYNC = ACP_VCTR26;			-- WENN 1 AUTOMATISCHE AUFL<46>SUNG
+	
+    -- HORIZONTAL TIMING 640x480
 	ATARI_HH[].CLK = MAIN_CLK;
 	ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104";						-- $410/4
 	ATARI_HH[] = FB_AD[];
@@ -263,7 +295,8 @@ BEGIN
 	ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
 	ATARI_HH[15..8].ENA  = ATARI_HH_CS & FB_B2 & !nFB_WR;
 	ATARI_HH[7..0].ENA   = ATARI_HH_CS & FB_B3 & !nFB_WR;
-	-- VERTIKAL TIMING 640x480
+	
+    -- VERTIKAL TIMING 640x480
 	ATARI_VH[].CLK = MAIN_CLK;
 	ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105";						-- $414/4
 	ATARI_VH[] = FB_AD[];
@@ -271,7 +304,8 @@ BEGIN
 	ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
 	ATARI_VH[15..8].ENA  = ATARI_VH_CS & FB_B2 & !nFB_WR;
 	ATARI_VH[7..0].ENA   = ATARI_VH_CS & FB_B3 & !nFB_WR;
-	-- HORIZONTAL TIMING 320x240
+	
+    -- HORIZONTAL TIMING 320x240
 	ATARI_HL[].CLK = MAIN_CLK;
 	ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106";						-- $418/4
 	ATARI_HL[] = FB_AD[];
@@ -279,7 +313,8 @@ BEGIN
 	ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
 	ATARI_HL[15..8].ENA  = ATARI_HL_CS & FB_B2 & !nFB_WR;
 	ATARI_HL[7..0].ENA   = ATARI_HL_CS & FB_B3 & !nFB_WR;
-	-- VERTIKAL TIMING 320x240
+	
+    -- VERTIKAL TIMING 320x240
 	ATARI_VL[].CLK = MAIN_CLK;
 	ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107";						-- $41C/4
 	ATARI_VL[] = FB_AD[];
@@ -287,7 +322,9 @@ BEGIN
 	ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
 	ATARI_VL[15..8].ENA  = ATARI_VL_CS & FB_B2 & !nFB_WR;
 	ATARI_VL[7..0].ENA   = ATARI_VL_CS & FB_B3 & !nFB_WR;
--- VIDEO PLL CONFIG
+
+    
+    -- VIDEO PLL CONFIG
 	VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1;	-- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
 	VR_WR.CLK = MAIN_CLK;
 	VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
@@ -298,21 +335,28 @@ BEGIN
 	VR_FRQ[].CLK = MAIN_CLK;
 	VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
 	VR_FRQ[] = FB_AD[23..16];
--- VIDEO PLL RECONFIG
+
+    -- VIDEO PLL RECONFIG
 	VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0;		-- $(F)000'0800 
 	VIDEO_RECONFIG.CLK = MAIN_CLK;
 	VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
-------------------------------------------------------------------------------------------------------------------------
+
+    ------------------------------------------------------------------------------------------------------------------------
 	VIDEO_RAM_CTR[] = ACP_VCTR[31..16];
--------------- COLOR MODE IM ACP SETZEN	
+
+    -------------- COLOR MODE IM ACP SETZEN	
 	COLOR1   = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
 	COLOR8   = 			    ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
 	COLOR16  = 				   		     ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
 	COLOR24  = 										  ACP_VCTR2 & ACP_VIDEO_ON;
 	ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1;
--- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
+
+    -- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
 	ACP_VCTR7          = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
-	ACP_VCTR6          = ST_SHIFT_MODE_CS     & !nFB_WR & !ACP_VIDEO_ON;
+    
+    -- duplicate ACP_VCTR6 according to TimeQuest recommendations
+    ACP_VCTR6_DUP      = ST_SHIFT_MODE_CS     & !nFB_WR & !ACP_VIDEO_ON;
+	ACP_VCTR6          = ACP_VCTR6_DUP;
 	ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
 	FALCON_VIDEO	   = ACP_VCTR7;
 	FALCON_CLUT        = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
@@ -325,118 +369,140 @@ BEGIN
 			# B"101" & COLOR16
 			# B"110" & COLOR24
 			# B"111" & RAND_ON;
--- DIVERSE (VIDEO)-REGISTER ----------------------------
--- RANDFARBE
+
+    -- DIVERSE (VIDEO)-REGISTER ----------------------------
+
+    -- RANDFARBE
 	CCR[].CLK = MAIN_CLK;
 	CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101";						-- $404/4
 	CCR[] = FB_AD[23..0];
 	CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
 	CCR[15..8].ENA  = CCR_CS & FB_B2 & !nFB_WR;
 	CCR[7..0].ENA   = CCR_CS & FB_B3 & !nFB_WR;
---SYS CTR
+
+    --SYS CTR
 	SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003";						-- $8006/2
 	SYS_CTR[].CLK = MAIN_CLK;
 	SYS_CTR[6..0] = FB_AD[22..16];
 	SYS_CTR[6..0].ENA  = SYS_CTR_CS & !nFB_WR & FB_B3;
 	BLITTER_ON = !SYS_CTR3;
---VDL_LOF
+
+    --VDL_LOF
 	VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107";						-- $820E/2
 	VDL_LOF[].CLK = MAIN_CLK;
 	VDL_LOF[] = FB_AD[31..16];
 	VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
 	VDL_LOF[7..0].ENA  = VDL_LOF_CS & !nFB_WR & FB_B3;
---VDL_LWD
+
+    --VDL_LWD
 	VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108";						-- $8210/2
 	VDL_LWD[].CLK = MAIN_CLK;
 	VDL_LWD[] = FB_AD[31..16];
 	VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
 	VDL_LWD[7..0].ENA  = VDL_LWD_CS & !nFB_WR & FB_B1;
--- HORIZONTAL
--- VDL_HHT
+
+    -- HORIZONTAL
+
+    -- VDL_HHT
 	VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141";						-- $8282/2
 	VDL_HHT[].CLK = MAIN_CLK;
 	VDL_HHT[] = FB_AD[27..16];
 	VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
 	VDL_HHT[7..0].ENA  = VDL_HHT_CS & !nFB_WR & FB_B3;
--- VDL_HBE
+
+    -- VDL_HBE
 	VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143";						-- $8286/2
 	VDL_HBE[].CLK = MAIN_CLK;
 	VDL_HBE[] = FB_AD[27..16];
 	VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
 	VDL_HBE[7..0].ENA  = VDL_HBE_CS & !nFB_WR & FB_B3;
--- VDL_HDB
+
+    -- VDL_HDB
 	VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144";						-- $8288/2
 	VDL_HDB[].CLK = MAIN_CLK;
 	VDL_HDB[] = FB_AD[27..16];
 	VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
 	VDL_HDB[7..0].ENA  = VDL_HDB_CS & !nFB_WR & FB_B1;
--- VDL_HDE
+
+    -- VDL_HDE
 	VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145";						-- $828A/2
 	VDL_HDE[].CLK = MAIN_CLK;
 	VDL_HDE[] = FB_AD[27..16];
 	VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
 	VDL_HDE[7..0].ENA  = VDL_HDE_CS & !nFB_WR & FB_B3;
--- VDL_HBB
+
+    -- VDL_HBB
 	VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142";						-- $8284/2
 	VDL_HBB[].CLK = MAIN_CLK;
 	VDL_HBB[] = FB_AD[27..16];
 	VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
 	VDL_HBB[7..0].ENA  = VDL_HBB_CS & !nFB_WR & FB_B1;
--- VDL_HSS
+
+    -- VDL_HSS
 	VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146";						-- $828C/2
 	VDL_HSS[].CLK = MAIN_CLK;
 	VDL_HSS[] = FB_AD[27..16];
 	VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
 	VDL_HSS[7..0].ENA  = VDL_HSS_CS & !nFB_WR & FB_B1;
--- VERTIKAL
--- VDL_VBE
+
+    -- VERTIKAL
+
+    -- VDL_VBE
 	VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153";						-- $82A6/2
 	VDL_VBE[].CLK = MAIN_CLK;
 	VDL_VBE[] = FB_AD[26..16];
 	VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
 	VDL_VBE[7..0].ENA  = VDL_VBE_CS & !nFB_WR & FB_B3;
--- VDL_VDB
+
+    -- VDL_VDB
 	VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154";						-- $82A8/2
 	VDL_VDB[].CLK = MAIN_CLK;
 	VDL_VDB[] = FB_AD[26..16];
 	VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
 	VDL_VDB[7..0].ENA  = VDL_VDB_CS & !nFB_WR & FB_B1;
--- VDL_VDE
+
+    -- VDL_VDE
 	VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155";						-- $82AA/2
 	VDL_VDE[].CLK = MAIN_CLK;
 	VDL_VDE[] = FB_AD[26..16];
 	VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
 	VDL_VDE[7..0].ENA  = VDL_VDE_CS & !nFB_WR & FB_B3;
--- VDL_VBB
+
+    -- VDL_VBB
 	VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152";						-- $82A4/2
 	VDL_VBB[].CLK = MAIN_CLK;
 	VDL_VBB[] = FB_AD[26..16];
 	VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
 	VDL_VBB[7..0].ENA  = VDL_VBB_CS & !nFB_WR & FB_B1;
--- VDL_VSS
+
+    -- VDL_VSS
 	VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156";						-- $82AC/2
 	VDL_VSS[].CLK = MAIN_CLK;
 	VDL_VSS[] = FB_AD[26..16];
 	VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
 	VDL_VSS[7..0].ENA  = VDL_VSS_CS & !nFB_WR & FB_B1;
--- VDL_VFT
+
+    -- VDL_VFT
 	VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151";						-- $82A2/2
 	VDL_VFT[].CLK = MAIN_CLK;
 	VDL_VFT[] = FB_AD[26..16];
 	VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
 	VDL_VFT[7..0].ENA  = VDL_VFT_CS & !nFB_WR & FB_B3;
--- VDL_VCT
+
+    -- VDL_VCT
 	VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160";						-- $82C0/2
 	VDL_VCT[].CLK = MAIN_CLK;
 	VDL_VCT[] = FB_AD[24..16];
 	VDL_VCT[8].ENA 		= VDL_VCT_CS & !nFB_WR & FB_B0;
 	VDL_VCT[7..0].ENA  	= VDL_VCT_CS & !nFB_WR & FB_B1;
--- VDL_VMD
+
+    -- VDL_VMD
 	VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161";						-- $82C2/2
 	VDL_VMD[].CLK = MAIN_CLK;
 	VDL_VMD[] = FB_AD[19..16];
 	VDL_VMD[3..0].ENA  	= VDL_VMD_CS & !nFB_WR & FB_B3;
---- REGISTER OUT
+
+    --- REGISTER OUT
 	FB_AD[31..16] = lpm_bustri_WORD(
 						ST_SHIFT_MODE_CS 		& (0,ST_SHIFT_MODE[],B"00000000") 
 					  #	FALCON_SHIFT_MODE_CS 	& (0,FALCON_SHIFT_MODE[])
@@ -484,8 +550,9 @@ BEGIN
 				 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
 				 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS;
 	
--- VIDEO AUSGABE SETZEN
-	CLK17M.CLK = CLK33M;
+
+    -- VIDEO AUSGABE SETZEN
+	CLK17M.CLK = MAIN_CLK;
 	CLK17M = !CLK17M;
 	CLK13M.CLK = CLK25M;
 	CLK13M = !CLK13M;
@@ -496,9 +563,10 @@ BEGIN
 			#	CLK25M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
 			#	CLK33M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
 			#	CLK_VIDEO  & ACP_VIDEO_ON & ACP_VCTR[9];
---------------------------------------------------------------
--- HORIZONTALE SYNC L<>NGE in PIXEL_CLK
-----------------------------------------------------------------
+
+    --------------------------------------------------------------
+    -- HORIZONTALE SYNC L<>NGE in PIXEL_CLK
+    ----------------------------------------------------------------
 	HSY_LEN[].CLK = MAIN_CLK;		
 	HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0)
 			#	16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
@@ -517,14 +585,15 @@ BEGIN
 	HDIS_LEN[] =  320 &  VDL_VMD2								-- BREITE IN PIXELN
 			   #  640 & !VDL_VMD2;
 					
--- DOPPELZEILENMODUS
+
+    -- DOPPELZEILENMODUS
 	DOP_ZEI.CLK = MAIN_CLK;
 	DOP_ZEI = VDL_VMD0 & ST_VIDEO;								-- ZEILENVERDOPPELUNG EIN AUS
 	INTER_ZEI.CLK = PIXEL_CLK;
 	INTER_ZEI =  DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) 	    -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
 	          #  DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); 		-- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
 	DOP_FIFO_CLR.CLK = PIXEL_CLK;
-	DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX;				-- DOPPELZEILENFIFO L<>SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
+	DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX;				-- DOPPELZEILENFIFO L<>SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
 					
 	RAND_LINKS[] 	=  VDL_HBE[] 									&  ACP_VIDEO_ON
 					#  21											& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
@@ -566,7 +635,8 @@ BEGIN
 					#  ATARI_VL[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
 					#  ATARI_VH[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
 					# (0,VDL_VFT[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
--- Z<>HLER
+
+    -- Z<>HLER
 	LAST.CLK = PIXEL_CLK;
 	LAST = VHCNT[]==(H_TOTAL[]-2);
 	VHCNT[].CLK = PIXEL_CLK;
@@ -574,10 +644,11 @@ BEGIN
 	VVCNT[].CLK = PIXEL_CLK;
 	VVCNT[].ENA = LAST;
 	VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1);
--- DISPLAY ON OFF
+
+    -- DISPLAY ON OFF
 	DPO_ZL.CLK = PIXEL_CLK;
 	DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1);	-- 1 ZEILE DAVOR ON OFF
-	DPO_ZL.ENA = LAST;												-- AM ZEILENENDE <20>BERNEHMEN
+	DPO_ZL.ENA = LAST;												-- AM ZEILENENDE <20>BERNEHMEN
 	DPO_ON.CLK = PIXEL_CLK;
 	DPO_ON = VHCNT[]==RAND_LINKS[];									-- BESSER EINZELN WEGEN TIMING
 	DPO_OFF.CLK = PIXEL_CLK;
@@ -585,31 +656,35 @@ BEGIN
 	DISP_ON.CLK = PIXEL_CLK;
 	DISP_ON = DISP_ON & !DPO_OFF 
 			# DPO_ON & DPO_ZL;
--- DATENTRANSFER ON OFF
+
+    -- DATENTRANSFER ON OFF
 	VDO_ON.CLK = PIXEL_CLK;
 	VDO_ON = VHCNT[]==(HDIS_START[]-1);								-- BESSER EINZELN WEGEN TIMING
 	VDO_OFF.CLK = PIXEL_CLK;
 	VDO_OFF = VHCNT[]==HDIS_END[];
 	VDO_ZL.CLK = PIXEL_CLK;
-	VDO_ZL.ENA = LAST;												-- AM ZEILENENDE <20>BERNEHMEN
+	VDO_ZL.ENA = LAST;												-- AM ZEILENENDE <20>BERNEHMEN
 	VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]);	-- 1 ZEILE DAVOR ON OFF
 	VDTRON.CLK = PIXEL_CLK;
 	VDTRON = VDTRON & !VDO_OFF
 		   # VDO_ON & VDO_ZL;
--- VERZ<52>GERUNG UND SYNC	
+
+    -- VERZ<52>GERUNG UND SYNC	
 	HSYNC_START.CLK = PIXEL_CLK;
 	HSYNC_START = VHCNT[]==HS_START[]-3;
 	HSYNC_I[].CLK = PIXEL_CLK;
 	HSYNC_I[] = HSY_LEN[]    &  HSYNC_START
 			 # (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
-	VSYNC_START.CLK = PIXEL_CLK;
+	
+    VSYNC_START.CLK = PIXEL_CLK;
 	VSYNC_START.ENA = LAST;
 	VSYNC_START = VVCNT[]==(VS_START[]-3);						-- start am ende der Zeile vor dem vsync		
 	VSYNC_I[].CLK = PIXEL_CLK;
 	VSYNC_I[].ENA = LAST;										-- start am ende der Zeile vor dem vsync
 	VSYNC_I[] =   3 	    &  VSYNC_START						-- 3 zeilen vsync length
-			# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0;		-- runterz<72>hlen bis 0
-	VERZ[][].CLK = PIXEL_CLK;
+			# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0;		-- runterz<72>hlen bis 0
+	
+    VERZ[][].CLK = PIXEL_CLK;
 	VERZ[][1] = VERZ[][0];
 	VERZ[][2] = VERZ[][1];
 	VERZ[][3] = VERZ[][2];
@@ -619,20 +694,25 @@ BEGIN
 	VERZ[][7] = VERZ[][6];
 	VERZ[][8] = VERZ[][7];
 	VERZ[][9] = VERZ[][8];
-	VERZ[0][0] = DISP_ON;
+	
+    VERZ[0][0] = DISP_ON;
 	VERZ[1][0] = HSYNC_I[]!=0;
 	VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
-				#  ACP_VCTR15 &  VDL_VCT6  & HSYNC_I[]==0;		-- NUR M<>GLICH WENN BEIDE
+				#  ACP_VCTR15 &  VDL_VCT6  & HSYNC_I[]==0;		-- NUR M<>GLICH WENN BEIDE
 	VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
-				#  ACP_VCTR15 &  VDL_VCT5  & VSYNC_I[]==0;		-- NUR M<>GLICH WENN BEIDE
-	nBLANK.CLK = PIXEL_CLK;
+				#  ACP_VCTR15 &  VDL_VCT5  & VSYNC_I[]==0;		-- NUR M<>GLICH WENN BEIDE
+	
+    nBLANK.CLK = PIXEL_CLK;
 	nBLANK =  VERZ[0][8];
-	HSYNC.CLK = PIXEL_CLK;
+	
+    HSYNC.CLK = PIXEL_CLK;
 	HSYNC  =  VERZ[1][9];
 	VSYNC.CLK = PIXEL_CLK;
 	VSYNC  =  VERZ[2][9];
-	nSYNC  = GND;
--- RANDFARBE MACHEN ------------------------------------
+	
+    nSYNC  = GND;
+
+    -- RANDFARBE MACHEN ------------------------------------
 	RAND[].CLK = PIXEL_CLK;
 	RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25;
 	RAND[1] = RAND[0];
@@ -642,19 +722,20 @@ BEGIN
 	RAND[5] = RAND[4];
 	RAND[6] = RAND[5];
 	RAND_ON = RAND[6];
-----------------------------------------------------------
+
+    ----------------------------------------------------------
 	CLR_FIFO.CLK = PIXEL_CLK;
 	CLR_FIFO.ENA = LAST;
-	CLR_FIFO = VVCNT[]==V_TOTAL[]-2;								-- IN LETZTER ZEILE L<>SCHEN
+	CLR_FIFO = VVCNT[]==V_TOTAL[]-2;								-- IN LETZTER ZEILE L<>SCHEN
 	START_ZEILE.CLK = PIXEL_CLK;
 	START_ZEILE.ENA = LAST;
 	START_ZEILE = VVCNT[]==0;										-- ZEILE 1
 	SYNC_PIX.CLK = PIXEL_CLK;
-	SYNC_PIX  = VHCNT[]==3 & START_ZEILE;							-- SUB PIXEL Z<>HLER SYNCHRONISIEREN
+	SYNC_PIX  = VHCNT[]==3 & START_ZEILE;							-- SUB PIXEL Z<>HLER SYNCHRONISIEREN
 	SYNC_PIX1.CLK = PIXEL_CLK;
-	SYNC_PIX1 = VHCNT[]==5 & START_ZEILE;							-- SUB PIXEL Z<>HLER SYNCHRONISIEREN
+	SYNC_PIX1 = VHCNT[]==5 & START_ZEILE;							-- SUB PIXEL Z<>HLER SYNCHRONISIEREN
 	SYNC_PIX2.CLK = PIXEL_CLK;
-	SYNC_PIX2 = VHCNT[]==7 & START_ZEILE;							-- SUB PIXEL Z<>HLER SYNCHRONISIEREN
+	SYNC_PIX2 = VHCNT[]==7 & START_ZEILE;							-- SUB PIXEL Z<>HLER SYNCHRONISIEREN
 	SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
 	SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
 	SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX;			--count up if display on sonst clear bei sync pix		
@@ -665,7 +746,7 @@ BEGIN
 			  # SUB_PIXEL_CNT[3..0]==1 & COLOR8 
 			  # SUB_PIXEL_CNT[2..0]==1 & COLOR16 
 			  # SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON
-			  # SYNC_PIX # SYNC_PIX1 # SYNC_PIX2;				-- 3 CLOCK ZUS<55>TZLICH F<>R FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
+			  # SYNC_PIX # SYNC_PIX1 # SYNC_PIX2;				-- 3 CLOCK ZUS<55>TZLICH F<>R FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
 	
 	CLUT_MUX_ADR[].CLK = PIXEL_CLK;
 	CLUT_MUX_AV[][].CLK = PIXEL_CLK; 

altpll1.bsf

@@ -1,100 +1,100 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
-	(rect 0 0 328 216)
-	(text "altpll1" (rect 144 1 191 20)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 197 31 212)(font "Arial" ))
-	(port
-		(pt 0 72)
-		(input)
-		(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
-		(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 48 72)(line_width 1))
-	)
-	(port
-		(pt 328 72)
-		(output)
-		(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c0" (rect 311 56 325 72)(font "Arial" (font_size 8)))
-		(line (pt 328 72)(pt 272 72)(line_width 1))
-	)
-	(port
-		(pt 328 96)
-		(output)
-		(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c1" (rect 311 80 325 96)(font "Arial" (font_size 8)))
-		(line (pt 328 96)(pt 272 96)(line_width 1))
-	)
-	(port
-		(pt 328 120)
-		(output)
-		(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c2" (rect 311 104 325 120)(font "Arial" (font_size 8)))
-		(line (pt 328 120)(pt 272 120)(line_width 1))
-	)
-	(port
-		(pt 328 144)
-		(output)
-		(text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8)))
-		(text "locked" (rect 287 128 325 144)(font "Arial" (font_size 8)))
-		(line (pt 328 144)(pt 272 144)(line_width 1))
-	)
-	(drawing
-		(text "Cyclone III" (rect 253 198 301 212)(font "Arial" ))
-		(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
-		(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
-		(text "Clk " (rect 59 111 76 125)(font "Arial" ))
-		(text "Ratio" (rect 90 111 114 125)(font "Arial" ))
-		(text "Ph (dg)" (rect 128 111 163 125)(font "Arial" ))
-		(text "DC (%)" (rect 173 111 208 125)(font "Arial" ))
-		(text "c0" (rect 63 129 75 143)(font "Arial" ))
-		(text "1/66" (rect 92 129 113 143)(font "Arial" ))
-		(text "0.00" (rect 136 129 157 143)(font "Arial" ))
-		(text "50.00" (rect 178 129 205 143)(font "Arial" ))
-		(text "c1" (rect 63 147 75 161)(font "Arial" ))
-		(text "67/900" (rect 85 147 118 161)(font "Arial" ))
-		(text "0.00" (rect 136 147 157 161)(font "Arial" ))
-		(text "50.00" (rect 178 147 205 161)(font "Arial" ))
-		(text "c2" (rect 63 165 75 179)(font "Arial" ))
-		(text "67/90" (rect 89 165 116 179)(font "Arial" ))
-		(text "0.00" (rect 136 165 157 179)(font "Arial" ))
-		(text "50.00" (rect 178 165 205 179)(font "Arial" ))
-		(line (pt 0 0)(pt 329 0)(line_width 1))
-		(line (pt 329 0)(pt 329 217)(line_width 1))
-		(line (pt 0 217)(pt 329 217)(line_width 1))
-		(line (pt 0 0)(pt 0 217)(line_width 1))
-		(line (pt 56 108)(pt 215 108)(line_width 1))
-		(line (pt 56 125)(pt 215 125)(line_width 1))
-		(line (pt 56 143)(pt 215 143)(line_width 1))
-		(line (pt 56 161)(pt 215 161)(line_width 1))
-		(line (pt 56 179)(pt 215 179)(line_width 1))
-		(line (pt 56 108)(pt 56 179)(line_width 1))
-		(line (pt 82 108)(pt 82 179)(line_width 3))
-		(line (pt 125 108)(pt 125 179)(line_width 3))
-		(line (pt 170 108)(pt 170 179)(line_width 3))
-		(line (pt 214 108)(pt 214 179)(line_width 1))
-		(line (pt 48 56)(pt 272 56)(line_width 1))
-		(line (pt 272 56)(pt 272 200)(line_width 1))
-		(line (pt 48 200)(pt 272 200)(line_width 1))
-		(line (pt 48 56)(pt 48 200)(line_width 1))
-	)
-)
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2014 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 272 176)
+	(text "altpll1" (rect 119 0 160 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 161 26 172)(font "Arial" ))
+	(port
+		(pt 0 64)
+		(input)
+		(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 40 64))
+	)
+	(port
+		(pt 272 64)
+		(output)
+		(text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
+		(text "c0" (rect 257 51 269 63)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 272 80)
+		(output)
+		(text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8)))
+		(text "c1" (rect 257 67 267 79)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 272 96)
+		(output)
+		(text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8)))
+		(text "c2" (rect 257 83 269 95)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 272 112)
+		(output)
+		(text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8)))
+		(text "locked" (rect 237 99 268 111)(font "Arial" (font_size 8)))
+	)
+	(drawing
+		(text "Cyclone III" (rect 214 162 474 334)(font "Arial" ))
+		(text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" ))
+		(text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" ))
+		(text "Clk " (rect 51 91 117 192)(font "Arial" ))
+		(text "Ratio" (rect 82 91 187 192)(font "Arial" ))
+		(text "Ph (dg)" (rect 119 91 269 192)(font "Arial" ))
+		(text "DC (%)" (rect 154 91 340 192)(font "Arial" ))
+		(text "c0" (rect 54 104 119 218)(font "Arial" ))
+		(text "1/66" (rect 84 104 186 218)(font "Arial" ))
+		(text "0.00" (rect 125 104 269 218)(font "Arial" ))
+		(text "50.00" (rect 158 104 340 218)(font "Arial" ))
+		(text "c1" (rect 54 117 118 244)(font "Arial" ))
+		(text "512/6875" (rect 74 117 187 244)(font "Arial" ))
+		(text "0.00" (rect 125 117 269 244)(font "Arial" ))
+		(text "50.00" (rect 158 117 340 244)(font "Arial" ))
+		(text "c2" (rect 54 130 119 270)(font "Arial" ))
+		(text "1024/1375" (rect 71 130 185 270)(font "Arial" ))
+		(text "0.00" (rect 125 130 269 270)(font "Arial" ))
+		(text "50.00" (rect 158 130 340 270)(font "Arial" ))
+		(line (pt 0 0)(pt 273 0))
+		(line (pt 273 0)(pt 273 177))
+		(line (pt 0 177)(pt 273 177))
+		(line (pt 0 0)(pt 0 177))
+		(line (pt 48 89)(pt 186 89))
+		(line (pt 48 101)(pt 186 101))
+		(line (pt 48 114)(pt 186 114))
+		(line (pt 48 127)(pt 186 127))
+		(line (pt 48 140)(pt 186 140))
+		(line (pt 48 89)(pt 48 140))
+		(line (pt 68 89)(pt 68 140)(line_width 3))
+		(line (pt 116 89)(pt 116 140)(line_width 3))
+		(line (pt 151 89)(pt 151 140)(line_width 3))
+		(line (pt 185 89)(pt 185 140))
+		(line (pt 40 48)(pt 223 48))
+		(line (pt 223 48)(pt 223 159))
+		(line (pt 40 159)(pt 223 159))
+		(line (pt 40 48)(pt 40 159))
+		(line (pt 271 64)(pt 223 64))
+		(line (pt 271 80)(pt 223 80))
+		(line (pt 271 96)(pt 223 96))
+		(line (pt 271 112)(pt 223 112))
+	)
+)

altpll1.cmp

@@ -1,25 +1,25 @@
---Copyright (C) 1991-2010 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-component altpll1
-	PORT
-	(
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		locked		: OUT STD_LOGIC 
-	);
-end component;
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altpll1
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;

altpll1.inc

@@ -1,26 +1,26 @@
---Copyright (C) 1991-2010 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-FUNCTION altpll1 
-(
-	inclk0
-)
-
-RETURNS (
-	c0,
-	c1,
-	c2,
-	locked
-);
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altpll1 
+(
+	inclk0
+)
+
+RETURNS (
+	c0,
+	c1,
+	c2,
+	locked
+);

altpll1.ppf

@@ -1,12 +1,12 @@
-<?xml version="1.0" encoding="UTF-8" ?>
-<!DOCTYPE pinplan>
-<pinplan intended_family="Cyclone III" variation_name="altpll1" megafunction_name="ALTPLL" specifies="all_ports">
-<global>
-<pin name="inclk0" direction="input" scope="external" source="clock"  />
-<pin name="c0" direction="output" scope="external" source="clock"  />
-<pin name="c1" direction="output" scope="external" source="clock"  />
-<pin name="c2" direction="output" scope="external" source="clock"  />
-<pin name="locked" direction="output" scope="external"  />
-
-</global>
-</pinplan>
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altpll1" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>

altpll1.qip

@@ -1,7 +1,7 @@
-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "9.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.cmp"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.ppf"]
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.ppf"]

altpll1.vhd

@@ -1,423 +1,423 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: altpll1.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2010 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY altpll1 IS
-	PORT
-	(
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		locked		: OUT STD_LOGIC 
-	);
-END altpll1;
-
-
-ARCHITECTURE SYN OF altpll1 IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		self_reset_on_loss_lock		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-			locked	: OUT STD_LOGIC ;
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire3    <= sub_wire0(2);
-	sub_wire2    <= sub_wire0(1);
-	sub_wire1    <= sub_wire0(0);
-	c0    <= sub_wire1;
-	c1    <= sub_wire2;
-	c2    <= sub_wire3;
-	locked    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 66,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 1,
-		clk0_phase_shift => "0",
-		clk1_divide_by => 900,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 67,
-		clk1_phase_shift => "0",
-		clk2_divide_by => 90,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 67,
-		clk2_phase_shift => "0",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 30303,
-		intended_device_family => "Cyclone III",
-		lpm_type => "altpll",
-		operation_mode => "SOURCE_SYNCHRONOUS",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_UNUSED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_USED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
-		port_clk3 => "PORT_UNUSED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		self_reset_on_loss_lock => "OFF",
-		width_clock => 5
-	)
-	PORT MAP (
-		inclk => sub_wire6,
-		clk => sub_wire0,
-		locked => sub_wire4
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "90"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "90"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.500000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.456667"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.566668"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "67"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "67"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.50000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.45760000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll1.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "66"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "900"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "67"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "90"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "67"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
--- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE
--- Retrieval info: LIB_FILE: altera_mf
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: altpll1.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altpll1 IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END altpll1;
+
+
+ARCHITECTURE SYN OF altpll1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire4    <= sub_wire0(2);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	locked    <= sub_wire2;
+	c0    <= sub_wire3;
+	c2    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 66,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 1,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 6875,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 512,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 1375,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 1024,
+		clk2_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 30303,
+		intended_device_family => "Cyclone III",
+		lpm_type => "altpll",
+		operation_mode => "SOURCE_SYNCHRONOUS",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire6,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "90"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "90"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.457600"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.576000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "67"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "67"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.45760000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll1.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "66"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "6875"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "512"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1375"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1024"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf

altpll2.bsf

@@ -1,117 +1,117 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
-	(rect 0 0 304 248)
-	(text "altpll2" (rect 132 1 179 20)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 229 31 244)(font "Arial" ))
-	(port
-		(pt 0 72)
-		(input)
-		(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
-		(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 48 72)(line_width 1))
-	)
-	(port
-		(pt 304 72)
-		(output)
-		(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8)))
-		(line (pt 304 72)(pt 272 72)(line_width 1))
-	)
-	(port
-		(pt 304 96)
-		(output)
-		(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c1" (rect 287 80 301 96)(font "Arial" (font_size 8)))
-		(line (pt 304 96)(pt 272 96)(line_width 1))
-	)
-	(port
-		(pt 304 120)
-		(output)
-		(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8)))
-		(line (pt 304 120)(pt 272 120)(line_width 1))
-	)
-	(port
-		(pt 304 144)
-		(output)
-		(text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c3" (rect 287 128 301 144)(font "Arial" (font_size 8)))
-		(line (pt 304 144)(pt 272 144)(line_width 1))
-	)
-	(port
-		(pt 304 168)
-		(output)
-		(text "c4" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c4" (rect 287 152 301 168)(font "Arial" (font_size 8)))
-		(line (pt 304 168)(pt 272 168)(line_width 1))
-	)
-	(drawing
-		(text "Cyclone III" (rect 229 230 277 244)(font "Arial" ))
-		(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
-		(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
-		(text "Clk " (rect 59 111 76 125)(font "Arial" ))
-		(text "Ratio" (rect 85 111 109 125)(font "Arial" ))
-		(text "Ph (dg)" (rect 119 111 154 125)(font "Arial" ))
-		(text "DC (%)" (rect 164 111 199 125)(font "Arial" ))
-		(text "c0" (rect 63 129 75 143)(font "Arial" ))
-		(text "4/1" (rect 91 129 106 143)(font "Arial" ))
-		(text "240.00" (rect 120 129 153 143)(font "Arial" ))
-		(text "50.00" (rect 169 129 196 143)(font "Arial" ))
-		(text "c1" (rect 63 147 75 161)(font "Arial" ))
-		(text "4/1" (rect 91 147 106 161)(font "Arial" ))
-		(text "0.00" (rect 127 147 148 161)(font "Arial" ))
-		(text "50.00" (rect 169 147 196 161)(font "Arial" ))
-		(text "c2" (rect 63 165 75 179)(font "Arial" ))
-		(text "4/1" (rect 91 165 106 179)(font "Arial" ))
-		(text "180.00" (rect 120 165 153 179)(font "Arial" ))
-		(text "50.00" (rect 169 165 196 179)(font "Arial" ))
-		(text "c3" (rect 63 183 75 197)(font "Arial" ))
-		(text "4/1" (rect 91 183 106 197)(font "Arial" ))
-		(text "105.00" (rect 120 183 153 197)(font "Arial" ))
-		(text "50.00" (rect 169 183 196 197)(font "Arial" ))
-		(text "c4" (rect 63 201 75 215)(font "Arial" ))
-		(text "2/1" (rect 91 201 106 215)(font "Arial" ))
-		(text "270.00" (rect 120 201 153 215)(font "Arial" ))
-		(text "50.00" (rect 169 201 196 215)(font "Arial" ))
-		(line (pt 0 0)(pt 305 0)(line_width 1))
-		(line (pt 305 0)(pt 305 249)(line_width 1))
-		(line (pt 0 249)(pt 305 249)(line_width 1))
-		(line (pt 0 0)(pt 0 249)(line_width 1))
-		(line (pt 56 108)(pt 206 108)(line_width 1))
-		(line (pt 56 125)(pt 206 125)(line_width 1))
-		(line (pt 56 143)(pt 206 143)(line_width 1))
-		(line (pt 56 161)(pt 206 161)(line_width 1))
-		(line (pt 56 179)(pt 206 179)(line_width 1))
-		(line (pt 56 197)(pt 206 197)(line_width 1))
-		(line (pt 56 215)(pt 206 215)(line_width 1))
-		(line (pt 56 108)(pt 56 215)(line_width 1))
-		(line (pt 82 108)(pt 82 215)(line_width 3))
-		(line (pt 116 108)(pt 116 215)(line_width 3))
-		(line (pt 161 108)(pt 161 215)(line_width 3))
-		(line (pt 205 108)(pt 205 215)(line_width 1))
-		(line (pt 48 56)(pt 272 56)(line_width 1))
-		(line (pt 272 56)(pt 272 232)(line_width 1))
-		(line (pt 48 232)(pt 272 232)(line_width 1))
-		(line (pt 48 56)(pt 48 232)(line_width 1))
-	)
-)
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2014 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 256 200)
+	(text "altpll2" (rect 111 0 153 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 185 26 196)(font "Arial" ))
+	(port
+		(pt 0 64)
+		(input)
+		(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 40 64))
+	)
+	(port
+		(pt 256 64)
+		(output)
+		(text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
+		(text "c0" (rect 241 51 253 63)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 256 80)
+		(output)
+		(text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8)))
+		(text "c1" (rect 241 67 251 79)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 256 96)
+		(output)
+		(text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8)))
+		(text "c2" (rect 241 83 253 95)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 256 112)
+		(output)
+		(text "c3" (rect 0 0 15 13)(font "Arial" (font_size 8)))
+		(text "c3" (rect 241 99 253 111)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 256 128)
+		(output)
+		(text "c4" (rect 0 0 15 13)(font "Arial" (font_size 8)))
+		(text "c4" (rect 241 115 253 127)(font "Arial" (font_size 8)))
+	)
+	(drawing
+		(text "Cyclone III" (rect 198 186 442 382)(font "Arial" ))
+		(text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" ))
+		(text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" ))
+		(text "Clk " (rect 51 91 117 192)(font "Arial" ))
+		(text "Ratio" (rect 71 91 165 192)(font "Arial" ))
+		(text "Ph (dg)" (rect 97 91 225 192)(font "Arial" ))
+		(text "DC (%)" (rect 132 91 296 192)(font "Arial" ))
+		(text "c0" (rect 54 104 119 218)(font "Arial" ))
+		(text "4/1" (rect 76 104 165 218)(font "Arial" ))
+		(text "240.00" (rect 98 104 225 218)(font "Arial" ))
+		(text "50.00" (rect 136 104 296 218)(font "Arial" ))
+		(text "c1" (rect 54 117 118 244)(font "Arial" ))
+		(text "4/1" (rect 76 117 165 244)(font "Arial" ))
+		(text "0.00" (rect 103 117 225 244)(font "Arial" ))
+		(text "50.00" (rect 136 117 296 244)(font "Arial" ))
+		(text "c2" (rect 54 130 119 270)(font "Arial" ))
+		(text "4/1" (rect 76 130 165 270)(font "Arial" ))
+		(text "180.00" (rect 98 130 224 270)(font "Arial" ))
+		(text "50.00" (rect 136 130 296 270)(font "Arial" ))
+		(text "c3" (rect 54 143 119 296)(font "Arial" ))
+		(text "4/1" (rect 76 143 165 296)(font "Arial" ))
+		(text "105.00" (rect 98 143 224 296)(font "Arial" ))
+		(text "50.00" (rect 136 143 296 296)(font "Arial" ))
+		(text "c4" (rect 54 156 119 322)(font "Arial" ))
+		(text "2/1" (rect 76 156 165 322)(font "Arial" ))
+		(text "270.00" (rect 98 156 225 322)(font "Arial" ))
+		(text "50.00" (rect 136 156 296 322)(font "Arial" ))
+		(line (pt 0 0)(pt 257 0))
+		(line (pt 257 0)(pt 257 201))
+		(line (pt 0 201)(pt 257 201))
+		(line (pt 0 0)(pt 0 201))
+		(line (pt 48 89)(pt 164 89))
+		(line (pt 48 101)(pt 164 101))
+		(line (pt 48 114)(pt 164 114))
+		(line (pt 48 127)(pt 164 127))
+		(line (pt 48 140)(pt 164 140))
+		(line (pt 48 153)(pt 164 153))
+		(line (pt 48 166)(pt 164 166))
+		(line (pt 48 89)(pt 48 166))
+		(line (pt 68 89)(pt 68 166)(line_width 3))
+		(line (pt 94 89)(pt 94 166)(line_width 3))
+		(line (pt 129 89)(pt 129 166)(line_width 3))
+		(line (pt 163 89)(pt 163 166))
+		(line (pt 40 48)(pt 223 48))
+		(line (pt 223 48)(pt 223 183))
+		(line (pt 40 183)(pt 223 183))
+		(line (pt 40 48)(pt 40 183))
+		(line (pt 255 64)(pt 223 64))
+		(line (pt 255 80)(pt 223 80))
+		(line (pt 255 96)(pt 223 96))
+		(line (pt 255 112)(pt 223 112))
+		(line (pt 255 128)(pt 223 128))
+	)
+)

altpll2.cmp

@@ -1,26 +1,26 @@
---Copyright (C) 1991-2010 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-component altpll2
-	PORT
-	(
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC ;
-		c4		: OUT STD_LOGIC 
-	);
-end component;
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altpll2
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		c4		: OUT STD_LOGIC 
+	);
+end component;

altpll2.inc

@@ -1,27 +1,27 @@
---Copyright (C) 1991-2010 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-FUNCTION altpll2 
-(
-	inclk0
-)
-
-RETURNS (
-	c0,
-	c1,
-	c2,
-	c3,
-	c4
-);
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altpll2 
+(
+	inclk0
+)
+
+RETURNS (
+	c0,
+	c1,
+	c2,
+	c3,
+	c4
+);

altpll2.ppf

@@ -1,13 +1,13 @@
-<?xml version="1.0" encoding="UTF-8" ?>
-<!DOCTYPE pinplan>
-<pinplan intended_family="Cyclone III" variation_name="altpll2" megafunction_name="ALTPLL" specifies="all_ports">
-<global>
-<pin name="inclk0" direction="input" scope="external" source="clock"  />
-<pin name="c0" direction="output" scope="external" source="clock"  />
-<pin name="c1" direction="output" scope="external" source="clock"  />
-<pin name="c2" direction="output" scope="external" source="clock"  />
-<pin name="c3" direction="output" scope="external" source="clock"  />
-<pin name="c4" direction="output" scope="external" source="clock"  />
-
-</global>
-</pinplan>
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altpll2" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="c3" direction="output" scope="external" source="clock"  />
+<pin name="c4" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>

altpll2.qip

@@ -1,7 +1,7 @@
-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "9.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll2.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.inc"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.cmp"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.ppf"]
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll2.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.ppf"]

altpll2.vhd

@@ -1,477 +1,477 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: altpll2.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2010 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY altpll2 IS
-	PORT
-	(
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC ;
-		c4		: OUT STD_LOGIC 
-	);
-END altpll2;
-
-
-ARCHITECTURE SYN OF altpll2 IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC ;
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire8_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
-		clk3_divide_by		: NATURAL;
-		clk3_duty_cycle		: NATURAL;
-		clk3_multiply_by		: NATURAL;
-		clk3_phase_shift		: STRING;
-		clk4_divide_by		: NATURAL;
-		clk4_duty_cycle		: NATURAL;
-		clk4_multiply_by		: NATURAL;
-		clk4_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire8_bv(0 DOWNTO 0) <= "0";
-	sub_wire8    <= To_stdlogicvector(sub_wire8_bv);
-	sub_wire5    <= sub_wire0(4);
-	sub_wire4    <= sub_wire0(3);
-	sub_wire3    <= sub_wire0(2);
-	sub_wire2    <= sub_wire0(1);
-	sub_wire1    <= sub_wire0(0);
-	c0    <= sub_wire1;
-	c1    <= sub_wire2;
-	c2    <= sub_wire3;
-	c3    <= sub_wire4;
-	c4    <= sub_wire5;
-	sub_wire6    <= inclk0;
-	sub_wire7    <= sub_wire8(0 DOWNTO 0) & sub_wire6;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 1,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 4,
-		clk0_phase_shift => "5051",
-		clk1_divide_by => 1,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 4,
-		clk1_phase_shift => "0",
-		clk2_divide_by => 1,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 4,
-		clk2_phase_shift => "3788",
-		clk3_divide_by => 1,
-		clk3_duty_cycle => 50,
-		clk3_multiply_by => 4,
-		clk3_phase_shift => "2210",
-		clk4_divide_by => 1,
-		clk4_duty_cycle => 50,
-		clk4_multiply_by => 2,
-		clk4_phase_shift => "11364",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 30303,
-		intended_device_family => "Cyclone III",
-		lpm_type => "altpll",
-		operation_mode => "SOURCE_SYNCHRONOUS",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_UNUSED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_UNUSED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
-		port_clk3 => "PORT_USED",
-		port_clk4 => "PORT_USED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		width_clock => 5
-	)
-	PORT MAP (
-		inclk => sub_wire7,
-		clk => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
--- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "132.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "132.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "132.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "132.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "66.000000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "133.33333000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "133.33330000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "133.33330000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "133.33330000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "240.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "180.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "105.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "270.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll2.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "5051"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "3788"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
--- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4"
--- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "2210"
--- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
--- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "11364"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
--- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
--- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_waveforms.html TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_wave*.jpg FALSE
--- Retrieval info: LIB_FILE: altera_mf
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: altpll2.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altpll2 IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		c4		: OUT STD_LOGIC 
+	);
+END altpll2;
+
+
+ARCHITECTURE SYN OF altpll2 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire8_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		clk4_divide_by		: NATURAL;
+		clk4_duty_cycle		: NATURAL;
+		clk4_multiply_by		: NATURAL;
+		clk4_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire8_bv(0 DOWNTO 0) <= "0";
+	sub_wire8    <= To_stdlogicvector(sub_wire8_bv);
+	sub_wire5    <= sub_wire0(4);
+	sub_wire4    <= sub_wire0(2);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire2    <= sub_wire0(3);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	c3    <= sub_wire2;
+	c0    <= sub_wire3;
+	c2    <= sub_wire4;
+	c4    <= sub_wire5;
+	sub_wire6    <= inclk0;
+	sub_wire7    <= sub_wire8(0 DOWNTO 0) & sub_wire6;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 1,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 4,
+		clk0_phase_shift => "5051",
+		clk1_divide_by => 1,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 4,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 1,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 4,
+		clk2_phase_shift => "3788",
+		clk3_divide_by => 1,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 4,
+		clk3_phase_shift => "2210",
+		clk4_divide_by => 1,
+		clk4_duty_cycle => 50,
+		clk4_multiply_by => 2,
+		clk4_phase_shift => "11364",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 30303,
+		intended_device_family => "Cyclone III",
+		lpm_type => "altpll",
+		operation_mode => "SOURCE_SYNCHRONOUS",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_USED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire7,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "132.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "132.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "132.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "132.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "66.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "133.33333000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "133.33330000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "133.33330000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "133.33330000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "240.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "180.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "105.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "270.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll2.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "5051"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "3788"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "2210"
+-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "11364"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf

altpll3.bsf

@@ -1,105 +1,105 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
-	(rect 0 0 304 232)
-	(text "altpll3" (rect 132 1 179 20)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 213 31 228)(font "Arial" ))
-	(port
-		(pt 0 72)
-		(input)
-		(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
-		(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 48 72)(line_width 1))
-	)
-	(port
-		(pt 304 72)
-		(output)
-		(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8)))
-		(line (pt 304 72)(pt 272 72)(line_width 1))
-	)
-	(port
-		(pt 304 96)
-		(output)
-		(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c1" (rect 287 80 301 96)(font "Arial" (font_size 8)))
-		(line (pt 304 96)(pt 272 96)(line_width 1))
-	)
-	(port
-		(pt 304 120)
-		(output)
-		(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8)))
-		(line (pt 304 120)(pt 272 120)(line_width 1))
-	)
-	(port
-		(pt 304 144)
-		(output)
-		(text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c3" (rect 287 128 301 144)(font "Arial" (font_size 8)))
-		(line (pt 304 144)(pt 272 144)(line_width 1))
-	)
-	(drawing
-		(text "Cyclone III" (rect 229 214 277 228)(font "Arial" ))
-		(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
-		(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
-		(text "Clk " (rect 59 111 76 125)(font "Arial" ))
-		(text "Ratio" (rect 86 111 110 125)(font "Arial" ))
-		(text "Ph (dg)" (rect 121 111 156 125)(font "Arial" ))
-		(text "DC (%)" (rect 166 111 201 125)(font "Arial" ))
-		(text "c0" (rect 63 129 75 143)(font "Arial" ))
-		(text "2/33" (rect 88 129 109 143)(font "Arial" ))
-		(text "0.00" (rect 129 129 150 143)(font "Arial" ))
-		(text "50.00" (rect 171 129 198 143)(font "Arial" ))
-		(text "c1" (rect 63 147 75 161)(font "Arial" ))
-		(text "16/33" (rect 85 147 112 161)(font "Arial" ))
-		(text "0.00" (rect 129 147 150 161)(font "Arial" ))
-		(text "50.00" (rect 171 147 198 161)(font "Arial" ))
-		(text "c2" (rect 63 165 75 179)(font "Arial" ))
-		(text "25/33" (rect 85 165 112 179)(font "Arial" ))
-		(text "0.00" (rect 129 165 150 179)(font "Arial" ))
-		(text "50.00" (rect 171 165 198 179)(font "Arial" ))
-		(text "c3" (rect 63 183 75 197)(font "Arial" ))
-		(text "16/11" (rect 85 183 112 197)(font "Arial" ))
-		(text "0.00" (rect 129 183 150 197)(font "Arial" ))
-		(text "50.00" (rect 171 183 198 197)(font "Arial" ))
-		(line (pt 0 0)(pt 305 0)(line_width 1))
-		(line (pt 305 0)(pt 305 233)(line_width 1))
-		(line (pt 0 233)(pt 305 233)(line_width 1))
-		(line (pt 0 0)(pt 0 233)(line_width 1))
-		(line (pt 56 108)(pt 208 108)(line_width 1))
-		(line (pt 56 125)(pt 208 125)(line_width 1))
-		(line (pt 56 143)(pt 208 143)(line_width 1))
-		(line (pt 56 161)(pt 208 161)(line_width 1))
-		(line (pt 56 179)(pt 208 179)(line_width 1))
-		(line (pt 56 197)(pt 208 197)(line_width 1))
-		(line (pt 56 108)(pt 56 197)(line_width 1))
-		(line (pt 82 108)(pt 82 197)(line_width 3))
-		(line (pt 118 108)(pt 118 197)(line_width 3))
-		(line (pt 163 108)(pt 163 197)(line_width 3))
-		(line (pt 207 108)(pt 207 197)(line_width 1))
-		(line (pt 48 56)(pt 272 56)(line_width 1))
-		(line (pt 272 56)(pt 272 216)(line_width 1))
-		(line (pt 48 216)(pt 272 216)(line_width 1))
-		(line (pt 48 56)(pt 48 216)(line_width 1))
-	)
-)
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2014 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 256 184)
+	(text "altpll3" (rect 111 0 153 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 169 26 180)(font "Arial" ))
+	(port
+		(pt 0 64)
+		(input)
+		(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 40 64))
+	)
+	(port
+		(pt 256 64)
+		(output)
+		(text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
+		(text "c0" (rect 241 51 253 63)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 256 80)
+		(output)
+		(text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8)))
+		(text "c1" (rect 241 67 251 79)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 256 96)
+		(output)
+		(text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8)))
+		(text "c2" (rect 241 83 253 95)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 256 112)
+		(output)
+		(text "c3" (rect 0 0 15 13)(font "Arial" (font_size 8)))
+		(text "c3" (rect 241 99 253 111)(font "Arial" (font_size 8)))
+	)
+	(drawing
+		(text "Cyclone III" (rect 198 170 442 350)(font "Arial" ))
+		(text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" ))
+		(text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" ))
+		(text "Clk " (rect 51 91 117 192)(font "Arial" ))
+		(text "Ratio" (rect 77 91 177 192)(font "Arial" ))
+		(text "Ph (dg)" (rect 109 91 249 192)(font "Arial" ))
+		(text "DC (%)" (rect 144 91 320 192)(font "Arial" ))
+		(text "c0" (rect 54 104 119 218)(font "Arial" ))
+		(text "2/33" (rect 79 104 177 218)(font "Arial" ))
+		(text "0.00" (rect 115 104 249 218)(font "Arial" ))
+		(text "50.00" (rect 148 104 320 218)(font "Arial" ))
+		(text "c1" (rect 54 117 118 244)(font "Arial" ))
+		(text "16/33" (rect 77 117 177 244)(font "Arial" ))
+		(text "0.00" (rect 115 117 249 244)(font "Arial" ))
+		(text "50.00" (rect 148 117 320 244)(font "Arial" ))
+		(text "c2" (rect 54 130 119 270)(font "Arial" ))
+		(text "227/300" (rect 71 130 176 270)(font "Arial" ))
+		(text "0.00" (rect 115 130 249 270)(font "Arial" ))
+		(text "50.00" (rect 148 130 320 270)(font "Arial" ))
+		(text "c3" (rect 54 143 119 296)(font "Arial" ))
+		(text "227/156" (rect 71 143 176 296)(font "Arial" ))
+		(text "0.00" (rect 115 143 249 296)(font "Arial" ))
+		(text "50.00" (rect 148 143 320 296)(font "Arial" ))
+		(line (pt 0 0)(pt 257 0))
+		(line (pt 257 0)(pt 257 185))
+		(line (pt 0 185)(pt 257 185))
+		(line (pt 0 0)(pt 0 185))
+		(line (pt 48 89)(pt 176 89))
+		(line (pt 48 101)(pt 176 101))
+		(line (pt 48 114)(pt 176 114))
+		(line (pt 48 127)(pt 176 127))
+		(line (pt 48 140)(pt 176 140))
+		(line (pt 48 153)(pt 176 153))
+		(line (pt 48 89)(pt 48 153))
+		(line (pt 68 89)(pt 68 153)(line_width 3))
+		(line (pt 106 89)(pt 106 153)(line_width 3))
+		(line (pt 141 89)(pt 141 153)(line_width 3))
+		(line (pt 175 89)(pt 175 153))
+		(line (pt 40 48)(pt 223 48))
+		(line (pt 223 48)(pt 223 167))
+		(line (pt 40 167)(pt 223 167))
+		(line (pt 40 48)(pt 40 167))
+		(line (pt 255 64)(pt 223 64))
+		(line (pt 255 80)(pt 223 80))
+		(line (pt 255 96)(pt 223 96))
+		(line (pt 255 112)(pt 223 112))
+	)
+)

altpll3.cmp

@@ -1,25 +1,25 @@
---Copyright (C) 1991-2010 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-component altpll3
-	PORT
-	(
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC 
-	);
-end component;
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altpll3
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC 
+	);
+end component;

altpll3.inc

@@ -1,26 +1,26 @@
---Copyright (C) 1991-2010 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-FUNCTION altpll3 
-(
-	inclk0
-)
-
-RETURNS (
-	c0,
-	c1,
-	c2,
-	c3
-);
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altpll3 
+(
+	inclk0
+)
+
+RETURNS (
+	c0,
+	c1,
+	c2,
+	c3
+);

altpll3.ppf

@@ -1,12 +1,12 @@
-<?xml version="1.0" encoding="UTF-8" ?>
-<!DOCTYPE pinplan>
-<pinplan intended_family="Cyclone III" variation_name="altpll3" megafunction_name="ALTPLL" specifies="all_ports">
-<global>
-<pin name="inclk0" direction="input" scope="external" source="clock"  />
-<pin name="c0" direction="output" scope="external" source="clock"  />
-<pin name="c1" direction="output" scope="external" source="clock"  />
-<pin name="c2" direction="output" scope="external" source="clock"  />
-<pin name="c3" direction="output" scope="external" source="clock"  />
-
-</global>
-</pinplan>
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altpll3" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="c3" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>

altpll3.qip

@@ -1,7 +1,7 @@
-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "9.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll3.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.inc"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.cmp"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.ppf"]
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll3.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.ppf"]

altpll3.vhd

@@ -1,445 +1,445 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: altpll3.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2010 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY altpll3 IS
-	PORT
-	(
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC 
-	);
-END altpll3;
-
-
-ARCHITECTURE SYN OF altpll3 IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
-		clk3_divide_by		: NATURAL;
-		clk3_duty_cycle		: NATURAL;
-		clk3_multiply_by		: NATURAL;
-		clk3_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire4    <= sub_wire0(3);
-	sub_wire3    <= sub_wire0(2);
-	sub_wire2    <= sub_wire0(1);
-	sub_wire1    <= sub_wire0(0);
-	c0    <= sub_wire1;
-	c1    <= sub_wire2;
-	c2    <= sub_wire3;
-	c3    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 33,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 2,
-		clk0_phase_shift => "0",
-		clk1_divide_by => 33,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 16,
-		clk1_phase_shift => "0",
-		clk2_divide_by => 33,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 25,
-		clk2_phase_shift => "0",
-		clk3_divide_by => 11,
-		clk3_duty_cycle => 50,
-		clk3_multiply_by => 16,
-		clk3_phase_shift => "0",
-		compensate_clock => "CLK1",
-		inclk0_input_frequency => 30303,
-		intended_device_family => "Cyclone III",
-		lpm_type => "altpll",
-		operation_mode => "SOURCE_SYNCHRONOUS",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_UNUSED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_UNUSED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
-		port_clk3 => "PORT_USED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		width_clock => 5
-	)
-	PORT MAP (
-		inclk => sub_wire6,
-		clk => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "33"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "33"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "33"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.000000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "25"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "48"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "160.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll3.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "33"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "25"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "11"
--- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "16"
--- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
--- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.inc TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_wave*.jpg FALSE
--- Retrieval info: LIB_FILE: altera_mf
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: altpll3.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altpll3 IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC 
+	);
+END altpll3;
+
+
+ARCHITECTURE SYN OF altpll3 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire4    <= sub_wire0(2);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire2    <= sub_wire0(3);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	c3    <= sub_wire2;
+	c0    <= sub_wire3;
+	c2    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 33,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 2,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 33,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 16,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 300,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 227,
+		clk2_phase_shift => "0",
+		clk3_divide_by => 156,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 227,
+		clk3_phase_shift => "0",
+		compensate_clock => "CLK1",
+		inclk0_input_frequency => 30303,
+		intended_device_family => "Cyclone III",
+		lpm_type => "altpll",
+		operation_mode => "SOURCE_SYNCHRONOUS",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire6,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3744"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "300"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "156"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.969999"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.019230"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "227"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "227"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "227"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "48.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll3.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "300"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "227"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "156"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "227"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf

altpll4.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2010 Altera Corporation
+Copyright (C) 1991-2014 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,108 +18,108 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
 (symbol
-	(rect 0 0 376 232)
-	(text "altpll4" (rect 168 1 215 20)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 213 31 228)(font "Arial" ))
+	(rect 0 0 312 184)
+	(text "altpll4" (rect 139 0 179 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 168 25 180)(font "Arial" ))
 	(port
-		(pt 0 72)
+		(pt 0 64)
 		(input)
-		(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
-		(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 88 72)(line_width 1))
+		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 72 64))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "areset" (rect 0 0 36 14)(font "Arial" (font_size 8)))
+		(text "areset" (rect 4 66 33 79)(font "Arial" (font_size 8)))
+		(line (pt 0 80)(pt 72 80))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "areset" (rect 0 0 42 16)(font "Arial" (font_size 8)))
-		(text "areset" (rect 4 80 40 96)(font "Arial" (font_size 8)))
-		(line (pt 0 96)(pt 88 96)(line_width 1))
+		(text "scanclk" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "scanclk" (rect 4 82 39 95)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 72 96))
 	)
 	(port
-		(pt 0 120)
+		(pt 0 112)
 		(input)
-		(text "scanclk" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "scanclk" (rect 4 104 49 120)(font "Arial" (font_size 8)))
-		(line (pt 0 120)(pt 88 120)(line_width 1))
+		(text "scandata" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "scandata" (rect 4 98 47 111)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 72 112))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "scanclkena" (rect 0 0 64 14)(font "Arial" (font_size 8)))
+		(text "scanclkena" (rect 4 114 57 127)(font "Arial" (font_size 8)))
+		(line (pt 0 128)(pt 72 128))
 	)
 	(port
 		(pt 0 144)
 		(input)
-		(text "scandata" (rect 0 0 62 16)(font "Arial" (font_size 8)))
-		(text "scandata" (rect 4 128 57 144)(font "Arial" (font_size 8)))
-		(line (pt 0 144)(pt 88 144)(line_width 1))
+		(text "configupdate" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "configupdate" (rect 4 130 65 143)(font "Arial" (font_size 8)))
+		(line (pt 0 144)(pt 72 144))
 	)
 	(port
-		(pt 0 168)
-		(input)
-		(text "scanclkena" (rect 0 0 77 16)(font "Arial" (font_size 8)))
-		(text "scanclkena" (rect 4 152 70 168)(font "Arial" (font_size 8)))
-		(line (pt 0 168)(pt 88 168)(line_width 1))
-	)
-	(port
-		(pt 0 192)
-		(input)
-		(text "configupdate" (rect 0 0 86 16)(font "Arial" (font_size 8)))
-		(text "configupdate" (rect 4 176 77 192)(font "Arial" (font_size 8)))
-		(line (pt 0 192)(pt 88 192)(line_width 1))
-	)
-	(port
-		(pt 376 72)
+		(pt 312 64)
 		(output)
-		(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c0" (rect 359 56 373 72)(font "Arial" (font_size 8)))
-		(line (pt 376 72)(pt 288 72)(line_width 1))
+		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c0" (rect 296 50 306 63)(font "Arial" (font_size 8)))
 	)
 	(port
-		(pt 376 96)
+		(pt 312 80)
 		(output)
-		(text "scandataout" (rect 0 0 83 16)(font "Arial" (font_size 8)))
-		(text "scandataout" (rect 302 80 373 96)(font "Arial" (font_size 8)))
-		(line (pt 376 96)(pt 288 96)(line_width 1))
+		(text "scandataout" (rect 0 0 70 14)(font "Arial" (font_size 8)))
+		(text "scandataout" (rect 248 66 306 79)(font "Arial" (font_size 8)))
 	)
 	(port
-		(pt 376 120)
+		(pt 312 96)
 		(output)
-		(text "scandone" (rect 0 0 66 16)(font "Arial" (font_size 8)))
-		(text "scandone" (rect 317 104 373 120)(font "Arial" (font_size 8)))
-		(line (pt 376 120)(pt 288 120)(line_width 1))
+		(text "scandone" (rect 0 0 56 14)(font "Arial" (font_size 8)))
+		(text "scandone" (rect 260 82 306 95)(font "Arial" (font_size 8)))
 	)
 	(port
-		(pt 376 144)
+		(pt 312 112)
 		(output)
-		(text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8)))
-		(text "locked" (rect 335 128 373 144)(font "Arial" (font_size 8)))
-		(line (pt 376 144)(pt 288 144)(line_width 1))
+		(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
+		(text "locked" (rect 277 98 306 111)(font "Arial" (font_size 8)))
 	)
 	(drawing
-		(text "Cyclone III" (rect 301 214 349 228)(font "Arial" ))
-		(text "inclk0 frequency: 48.000 MHz" (rect 98 123 241 137)(font "Arial" ))
-		(text "Operation Mode: Normal" (rect 98 140 213 154)(font "Arial" ))
-		(text "Clk " (rect 99 167 116 181)(font "Arial" ))
-		(text "Ratio" (rect 125 167 149 181)(font "Arial" ))
-		(text "Ph (dg)" (rect 159 167 194 181)(font "Arial" ))
-		(text "DC (%)" (rect 204 167 239 181)(font "Arial" ))
-		(text "c0" (rect 103 185 115 199)(font "Arial" ))
-		(text "2/1" (rect 131 185 146 199)(font "Arial" ))
-		(text "0.00" (rect 167 185 188 199)(font "Arial" ))
-		(text "50.00" (rect 209 185 236 199)(font "Arial" ))
-		(line (pt 0 0)(pt 377 0)(line_width 1))
-		(line (pt 377 0)(pt 377 233)(line_width 1))
-		(line (pt 0 233)(pt 377 233)(line_width 1))
-		(line (pt 0 0)(pt 0 233)(line_width 1))
-		(line (pt 96 164)(pt 246 164)(line_width 1))
-		(line (pt 96 181)(pt 246 181)(line_width 1))
-		(line (pt 96 199)(pt 246 199)(line_width 1))
-		(line (pt 96 164)(pt 96 199)(line_width 1))
-		(line (pt 122 164)(pt 122 199)(line_width 3))
-		(line (pt 156 164)(pt 156 199)(line_width 3))
-		(line (pt 201 164)(pt 201 199)(line_width 3))
-		(line (pt 245 164)(pt 245 199)(line_width 1))
-		(line (pt 88 56)(pt 288 56)(line_width 1))
-		(line (pt 288 56)(pt 288 216)(line_width 1))
-		(line (pt 88 216)(pt 288 216)(line_width 1))
-		(line (pt 88 56)(pt 88 216)(line_width 1))
+		(text "Cyclone III" (rect 250 169 545 349)(font "Arial" ))
+		(text "inclk0 frequency: 48.019 MHz" (rect 82 92 287 195)(font "Arial" ))
+		(text "Operation Mode: Normal" (rect 82 105 263 221)(font "Arial" ))
+		(text "Clk " (rect 83 126 180 263)(font "Arial" ))
+		(text "Ratio" (rect 104 126 228 263)(font "Arial" ))
+		(text "Ph (dg)" (rect 130 126 289 263)(font "Arial" ))
+		(text "DC (%)" (rect 164 126 358 263)(font "Arial" ))
+		(text "c0" (rect 86 140 180 291)(font "Arial" ))
+		(text "2/1" (rect 109 140 228 291)(font "Arial" ))
+		(text "0.00" (rect 136 140 288 291)(font "Arial" ))
+		(text "50.00" (rect 168 140 357 291)(font "Arial" ))
+		(line (pt 0 0)(pt 313 0))
+		(line (pt 313 0)(pt 313 186))
+		(line (pt 0 186)(pt 313 186))
+		(line (pt 0 0)(pt 0 186))
+		(line (pt 80 124)(pt 196 124))
+		(line (pt 80 137)(pt 196 137))
+		(line (pt 80 151)(pt 196 151))
+		(line (pt 80 124)(pt 80 151))
+		(line (pt 101 124)(pt 101 151)(line_width 3))
+		(line (pt 127 124)(pt 127 151)(line_width 3))
+		(line (pt 161 124)(pt 161 151)(line_width 3))
+		(line (pt 195 124)(pt 195 151))
+		(line (pt 72 48)(pt 239 48))
+		(line (pt 239 48)(pt 239 168))
+		(line (pt 72 168)(pt 239 168))
+		(line (pt 72 48)(pt 72 168))
+		(line (pt 311 64)(pt 239 64))
+		(line (pt 311 80)(pt 239 80))
+		(line (pt 311 96)(pt 239 96))
+		(line (pt 311 112)(pt 239 112))
 	)
 )

altpll4.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2010 Altera Corporation
+--Copyright (C) 1991-2014 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

altpll4.inc

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2010 Altera Corporation
+--Copyright (C) 1991-2014 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

altpll4.mif

@@ -1,4 +1,4 @@
--- Copyright (C) 1991-2010 Altera Corporation
+-- Copyright (C) 1991-2014 Altera Corporation
 -- Your use of Altera Corporation's design tools, logic functions 
 -- and other software and tools, and its AMPP partner logic 
 -- functions, and any output files from any of the foregoing 
@@ -17,8 +17,8 @@
 --    Device Part: -
 --    Device Speed Grade: 8
 --    PLL Scan Chain: Fast PLL (144 bits)
---    File Name: C:\FireBee\FPGA\altpll4.mif
---    Generated: Mon Dec 06 01:47:24 2010
+--    File Name: C:/Users/froesm1/Documents/Development/FPGA_quartus//altpll4.mif
+--    Generated: Mon Sep 21 17:50:54 2015
 
 WIDTH=1;
 DEPTH=144;

altpll4.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.tdf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.inc"]

altpll4.tdf

@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2010 Altera Corporation
+--Copyright (C) 1991-2014 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -59,7 +59,7 @@ VARIABLE
 			CLK0_MULTIPLY_BY = 2,
 			CLK0_PHASE_SHIFT = "0",
 			COMPENSATE_CLOCK = "CLK0",
-			INCLK0_INPUT_FREQUENCY = 20833,
+			INCLK0_INPUT_FREQUENCY = 20824,
 			INTENDED_DEVICE_FAMILY = "Cyclone III",
 			LPM_TYPE = "altpll",
 			OPERATION_MODE = "NORMAL",
@@ -113,16 +113,16 @@ VARIABLE
 BEGIN
 
 	c0 = altpll_component.clk[0..0];
-	scandone = altpll_component.scandone;
 	scandataout = altpll_component.scandataout;
+	scandone = altpll_component.scandone;
 	locked = altpll_component.locked;
-	altpll_component.scanclkena = scanclkena;
+	altpll_component.areset = areset;
+	altpll_component.configupdate = configupdate;
 	altpll_component.inclk[0..0] = inclk0;
 	altpll_component.inclk[1..1] = GND;
-	altpll_component.scandata = scandata;
-	altpll_component.areset = areset;
 	altpll_component.scanclk = scanclk;
-	altpll_component.configupdate = configupdate;
+	altpll_component.scanclkena = scanclkena;
+	altpll_component.scandata = scandata;
 END;
 
 
@@ -148,7 +148,7 @@ END;
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
 -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.038460"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -156,7 +156,7 @@ END;
 -- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
 -- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
 -- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.019"
 -- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
 -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
 -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
@@ -166,7 +166,7 @@ END;
 -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
 -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
 -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "336.000"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
 -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
@@ -217,7 +217,7 @@ END;
 -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20824"
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
 -- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
@@ -277,22 +277,22 @@ END;
 -- Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
 -- Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
 -- Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
--- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
--- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
--- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
--- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
--- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
 -- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
+-- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
+-- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
+-- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.tdf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.ppf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.inc TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4_inst.tdf FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.mif TRUE
 -- Retrieval info: LIB_FILE: altera_mf

firebee1.asm.rpt

@@ -1,128 +0,0 @@
-Assembler report for firebee1
-Wed Dec 15 02:25:13 2010
-Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Assembler Summary
-  3. Assembler Settings
-  4. Assembler Generated Files
-  5. Assembler Device Options: C:/FireBee/FPGA/firebee1.sof
-  6. Assembler Device Options: C:/FireBee/FPGA/firebee1.rbf
-  7. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary                                             ;
-+-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Wed Dec 15 02:25:13 2010 ;
-; Revision Name         ; firebee1                              ;
-; Top-level Entity Name ; firebee1                              ;
-; Family                ; Cyclone III                           ;
-; Device                ; EP3C40F484C6                          ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------+
-; Assembler Settings                                                                                       ;
-+-----------------------------------------------------------------------------+------------+---------------+
-; Option                                                                      ; Setting    ; Default Value ;
-+-----------------------------------------------------------------------------+------------+---------------+
-; Generate Raw Binary File (.rbf) For Target Device                           ; On         ; Off           ;
-; Hexadecimal Output File start address                                       ; 0XE0700000 ; 0             ;
-; Use smart compilation                                                       ; Off        ; Off           ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On         ; On            ;
-; Enable compact report table                                                 ; Off        ; Off           ;
-; Generate compressed bitstreams                                              ; On         ; On            ;
-; Compression mode                                                            ; Off        ; Off           ;
-; Clock source for configuration device                                       ; Internal   ; Internal      ;
-; Clock frequency of the configuration device                                 ; 10 MHZ     ; 10 MHz        ;
-; Divide clock frequency by                                                   ; 1          ; 1             ;
-; Auto user code                                                              ; Off        ; Off           ;
-; Use configuration device                                                    ; Off        ; Off           ;
-; Configuration device                                                        ; Auto       ; Auto          ;
-; Configuration device auto user code                                         ; Off        ; Off           ;
-; Generate Tabular Text File (.ttf) For Target Device                         ; Off        ; Off           ;
-; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off        ; Off           ;
-; Hexadecimal Output File count direction                                     ; Up         ; Up            ;
-; Release clears before tri-states                                            ; Off        ; Off           ;
-; Auto-restart configuration after error                                      ; On         ; On            ;
-; Enable OCT_DONE                                                             ; Off        ; Off           ;
-; Generate Serial Vector Format File (.svf) for Target Device                 ; Off        ; Off           ;
-; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off        ; Off           ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off        ; Off           ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On         ; On            ;
-+-----------------------------------------------------------------------------+------------+---------------+
-
-
-+------------------------------+
-; Assembler Generated Files    ;
-+------------------------------+
-; File Name                    ;
-+------------------------------+
-; C:/FireBee/FPGA/firebee1.sof ;
-; C:/FireBee/FPGA/firebee1.rbf ;
-+------------------------------+
-
-
-+--------------------------------------------------------+
-; Assembler Device Options: C:/FireBee/FPGA/firebee1.sof ;
-+----------------+---------------------------------------+
-; Option         ; Setting                               ;
-+----------------+---------------------------------------+
-; Device         ; EP3C40F484C6                          ;
-; JTAG usercode  ; 0xFFFFFFFF                            ;
-; Checksum       ; 0x0085E8C6                            ;
-+----------------+---------------------------------------+
-
-
-+--------------------------------------------------------+
-; Assembler Device Options: C:/FireBee/FPGA/firebee1.rbf ;
-+---------------------+----------------------------------+
-; Option              ; Setting                          ;
-+---------------------+----------------------------------+
-; Raw Binary File     ;                                  ;
-;  Compression Ratio  ; 2                                ;
-+---------------------+----------------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus II Assembler
-    Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
-    Info: Processing started: Wed Dec 15 02:25:08 2010
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1
-Info: Writing out detailed assembly data for power analysis
-Info: Assembler is generating device programming files
-Info: Quartus II Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 291 megabytes
-    Info: Processing ended: Wed Dec 15 02:25:13 2010
-    Info: Elapsed time: 00:00:05
-    Info: Total CPU time (on all processors): 00:00:05
-
-

firebee1.done

@@ -1 +0,0 @@
-Wed Dec 15 02:25:24 2010

firebee1.fit.summary

@@ -1,16 +0,0 @@
-Fitter Status : Successful - Wed Dec 15 02:25:02 2010
-Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-Revision Name : firebee1
-Top-level Entity Name : firebee1
-Family : Cyclone III
-Device : EP3C40F484C6
-Timing Models : Final
-Total logic elements : 9,526 / 39,600 ( 24 % )
-    Total combinational functions : 8,061 / 39,600 ( 20 % )
-    Dedicated logic registers : 4,563 / 39,600 ( 12 % )
-Total registers : 4749
-Total pins : 295 / 332 ( 89 % )
-Total virtual pins : 0
-Total memory bits : 109,344 / 1,161,216 ( 9 % )
-Embedded Multiplier 9-bit elements : 6 / 252 ( 2 % )
-Total PLLs : 4 / 4 ( 100 % )

firebee1.flow.rpt

@@ -1,380 +0,0 @@
-Flow report for firebee1
-Wed Dec 15 02:25:22 2010
-Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Flow Summary
-  3. Flow Settings
-  4. Flow Non-Default Global Settings
-  5. Flow Elapsed Time
-  6. Flow OS Summary
-  7. Flow Log
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------------+
-; Flow Summary                                                                      ;
-+------------------------------------+----------------------------------------------+
-; Flow Status                        ; Successful - Wed Dec 15 02:25:21 2010        ;
-; Quartus II Version                 ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
-; Revision Name                      ; firebee1                                     ;
-; Top-level Entity Name              ; firebee1                                     ;
-; Family                             ; Cyclone III                                  ;
-; Device                             ; EP3C40F484C6                                 ;
-; Timing Models                      ; Final                                        ;
-; Met timing requirements            ; No                                           ;
-; Total logic elements               ; 9,526 / 39,600 ( 24 % )                      ;
-;     Total combinational functions  ; 8,061 / 39,600 ( 20 % )                      ;
-;     Dedicated logic registers      ; 4,563 / 39,600 ( 12 % )                      ;
-; Total registers                    ; 4749                                         ;
-; Total pins                         ; 295 / 332 ( 89 % )                           ;
-; Total virtual pins                 ; 0                                            ;
-; Total memory bits                  ; 109,344 / 1,161,216 ( 9 % )                  ;
-; Embedded Multiplier 9-bit elements ; 6 / 252 ( 2 % )                              ;
-; Total PLLs                         ; 4 / 4 ( 100 % )                              ;
-+------------------------------------+----------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings                           ;
-+-------------------+---------------------+
-; Option            ; Setting             ;
-+-------------------+---------------------+
-; Start date & time ; 12/15/2010 02:20:37 ;
-; Main task         ; Compilation         ;
-; Revision Name     ; firebee1            ;
-+-------------------+---------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings                                                                                            ;
-+-----------------------------------------+------------------------------------+---------------+-------------+----------------+
-; Assignment Name                         ; Value                              ; Default Value ; Entity Name ; Section Id     ;
-+-----------------------------------------+------------------------------------+---------------+-------------+----------------+
-; COMPILER_SIGNATURE_ID                   ; 150661768621.129237603704664       ; --            ; --          ; --             ;
-; CYCLONEII_OPTIMIZATION_TECHNIQUE        ; Speed                              ; Balanced      ; --          ; --             ;
-; FMAX_REQUIREMENT                        ; 30 ns                              ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_COUNTER                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_RAM_DP+                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_RAM_DP+                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_RAM_DP+                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_LATCH                          ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_COMPARE                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_FF                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_FF                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_FF                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTDDIO_BIDIR                      ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTDDIO_OUT                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTDDIO_OUT                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTDDIO_OUT                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTDDIO_OUT                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_FIFO+                          ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_FIFO+                          ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTPLL_RECONFIG                    ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; MAX_CORE_JUNCTION_TEMP                  ; 85                                 ; --            ; --          ; --             ;
-; MIN_CORE_JUNCTION_TEMP                  ; 0                                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; C:/firebee/FPGA/firebee1.dpf       ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll1.bsf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll1.inc                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll1.cmp                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll1.ppf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll2.bsf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll2.inc                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll2.cmp                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll2.ppf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll3.bsf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll3.inc                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll3.cmp                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll3.ppf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll0.bsf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll0.inc                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll0.cmp                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll0.ppf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_counter0.bsf                   ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_counter0.cmp                   ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg0.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg0.inc            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg0.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram0.bsf                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram0.inc                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram0.cmp                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri1.bsf              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri1.cmp              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram1.bsf                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram1.inc                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram1.cmp                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri2.bsf              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri2.cmp              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri4.bsf              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri4.cmp              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant0.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant0.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant1.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant1.inc            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant1.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux0.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux0.inc                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux0.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux1.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux1.inc                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux1.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux2.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux2.inc                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux2.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant2.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant2.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram2.bsf                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram2.inc                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram2.cmp                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri6.bsf              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri6.cmp              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux3.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux3.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux4.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux4.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant3.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant3.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg1.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg1.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_latch1.bsf               ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_latch1.cmp               ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant4.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant4.inc            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant4.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg2.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg2.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_compare1.bsf             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_compare1.inc             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_compare1.cmp             ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_LONG.bsf                ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_LONG.inc                ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_LONG.cmp                ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_BYT.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_BYT.inc                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_BYT.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_WORD.bsf                ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_WORD.inc                ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_WORD.cmp                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff4.bsf                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff4.inc                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff4.cmp                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff5.bsf                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff5.inc                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff5.cmp                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff6.bsf                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff6.inc                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff6.cmp                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg3.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg3.inc            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg3.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_bidir0.bsf           ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_bidir0.inc           ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_bidir0.cmp           ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_bidir0.ppf           ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out0.bsf             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out0.inc             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out0.cmp             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out0.ppf             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux5.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux5.inc                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux5.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg5.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg5.inc            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg5.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg6.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg6.inc            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg6.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg4.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg4.inc            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg4.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out1.bsf             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out1.inc             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out1.cmp             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out1.ppf             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out2.bsf             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out2.inc             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out2.cmp             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out2.ppf             ; --            ; --          ; --             ;
-; MISC_FILE                               ; altddio_out3.bsf                   ; --            ; --          ; --             ;
-; MISC_FILE                               ; altddio_out3.inc                   ; --            ; --          ; --             ;
-; MISC_FILE                               ; altddio_out3.cmp                   ; --            ; --          ; --             ;
-; MISC_FILE                               ; altddio_out3.ppf                   ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux6.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux6.inc                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux6.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; FalconIO_SDCard_IDE_CF/dcfifo0.bsf ; --            ; --          ; --             ;
-; MISC_FILE                               ; FalconIO_SDCard_IDE_CF/dcfifo0.cmp ; --            ; --          ; --             ;
-; MISC_FILE                               ; FalconIO_SDCard_IDE_CF/dcfifo1.bsf ; --            ; --          ; --             ;
-; MISC_FILE                               ; FalconIO_SDCard_IDE_CF/dcfifo1.cmp ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_muxDZ.bsf                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_muxDZ.cmp                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_muxVDM.bsf               ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_muxVDM.cmp               ; --            ; --          ; --             ;
-; MISC_FILE                               ; C:/FireBee/FPGA/firebee1.dpf       ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll_reconfig1.tdf               ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll_reconfig1.bsf               ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll_reconfig1.inc               ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll_reconfig1.cmp               ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll4.tdf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll4.bsf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll4.inc                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll4.cmp                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll4.ppf                        ; --            ; --          ; --             ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE             ; 1.2V                               ; --            ; --          ; --             ;
-; PARTITION_COLOR                         ; 16764057                           ; --            ; --          ; Top            ;
-; PARTITION_NETLIST_TYPE                  ; SOURCE                             ; --            ; --          ; Top            ;
-; PHYSICAL_SYNTHESIS_COMBO_LOGIC          ; On                                 ; Off           ; --          ; --             ;
-; PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ; On                                 ; Off           ; --          ; --             ;
-; PHYSICAL_SYNTHESIS_EFFORT               ; Fast                               ; Normal        ; --          ; --             ;
-; PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ; On                                 ; Off           ; --          ; --             ;
-; STATE_MACHINE_PROCESSING                ; One-Hot                            ; Auto          ; --          ; --             ;
-; TCO_REQUIREMENT                         ; 1 ns                               ; --            ; --          ; --             ;
-; TH_REQUIREMENT                          ; 1 ns                               ; --            ; --          ; --             ;
-; TPD_REQUIREMENT                         ; 1 ns                               ; --            ; --          ; --             ;
-; TSU_REQUIREMENT                         ; 1 ns                               ; --            ; --          ; --             ;
-; USE_GENERATED_PHYSICAL_CONSTRAINTS      ; Off                                ; --            ; --          ; eda_blast_fpga ;
-; USE_TIMEQUEST_TIMING_ANALYZER           ; Off                                ; On            ; --          ; --             ;
-+-----------------------------------------+------------------------------------+---------------+-------------+----------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time                                                                                                           ;
-+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name             ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis    ; 00:01:16     ; 1.0                     ; 347 MB              ; 00:01:17                           ;
-; Fitter                  ; 00:03:05     ; 1.0                     ; 334 MB              ; 00:03:07                           ;
-; Assembler               ; 00:00:05     ; 1.0                     ; 291 MB              ; 00:00:04                           ;
-; Classic Timing Analyzer ; 00:00:07     ; 1.0                     ; 227 MB              ; 00:00:09                           ;
-; Total                   ; 00:04:33     ; --                      ; --                  ; 00:04:37                           ;
-+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+------------------------------------------------------------------------------------------+
-; Flow OS Summary                                                                          ;
-+-------------------------+------------------+---------------+------------+----------------+
-; Module Name             ; Machine Hostname ; OS Name       ; OS Version ; Processor type ;
-+-------------------------+------------------+---------------+------------+----------------+
-; Analysis & Synthesis    ; envy15           ; Windows Vista ; 6.1        ; x86_64         ;
-; Fitter                  ; envy15           ; Windows Vista ; 6.1        ; x86_64         ;
-; Assembler               ; envy15           ; Windows Vista ; 6.1        ; x86_64         ;
-; Classic Timing Analyzer ; envy15           ; Windows Vista ; 6.1        ; x86_64         ;
-+-------------------------+------------------+---------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off firebeei1 -c firebee1
-quartus_fit --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1
-quartus_asm --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1
-quartus_tan --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 --timing_analysis_only
-
-
-

firebee1.map.summary

@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Wed Dec 15 02:21:55 2010
-Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-Revision Name : firebee1
-Top-level Entity Name : firebee1
-Family : Cyclone III
-Total logic elements : 10,706
-    Total combinational functions : 8,060
-    Dedicated logic registers : 4,612
-Total registers : 4740
-Total pins : 295
-Total virtual pins : 0
-Total memory bits : 109,344
-Embedded Multiplier 9-bit elements : 6
-Total PLLs : 4

firebee1.pin

@@ -1,557 +0,0 @@
- -- Copyright (C) 1991-2010 Altera Corporation
- -- Your use of Altera Corporation's design tools, logic functions 
- -- and other software and tools, and its AMPP partner logic 
- -- functions, and any output files from any of the foregoing 
- -- (including device programming or simulation files), and any 
- -- associated documentation or information are expressly subject 
- -- to the terms and conditions of the Altera Program License 
- -- Subscription Agreement, Altera MegaCore Function License 
- -- Agreement, or other applicable license agreement, including, 
- -- without limitation, that your use is for the sole purpose of 
- -- programming logic devices manufactured by Altera and sold by 
- -- Altera or its authorized distributors.  Please refer to the 
- -- applicable agreement for further details.
- -- 
- -- This is a Quartus II output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus II input file. This file cannot be used
- -- to make Quartus II pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus II help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC            : No Connect. This pin has no internal connection to the device.
- -- DNU           : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
- -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
- --                 of its bank.
- --					Bank 1:		3.3V
- --					Bank 2:		3.3V
- --					Bank 3:		3.3V
- --					Bank 4:		2.5V
- --					Bank 5:		2.5V
- --					Bank 6:		3.0V
- --					Bank 7:		3.3V
- --					Bank 8:		3.3V
- -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- --					It can also be used to report unused dedicated pins. The connection
- --					on the board for unused dedicated pins depends on whether this will
- --					be used in a future design. One example is device migration. When
- --					using device migration, refer to the device pin-tables. If it is a
- --					GND pin in the pin table or if it will not be used in a future design
- --					for another purpose the it MUST be connected to GND. If it is an unused
- --					dedicated pin, then it can be connected to a valid signal on the board
- --					(low, high, or toggling) if that signal is required for a different
- --					revision of the design.
- -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
- --					This pin should be connected to GND. It may also be connected  to a
- --					valid signal  on the board  (low, high, or toggling)  if that signal
- --					is required for a different revision of the design.
- -- GND*          : Unused  I/O  pin.   For transceiver I/O banks, connect each pin marked GND*
- --           	    either individually through a 10k Ohm resistor to GND or tie all pins
- --           	    together and connect through a single 10k Ohm resistor to GND.
- --           	    For non-transceiver I/O banks, connect each pin marked GND* directly to GND
- --           	    or leave it unconnected.
- -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
-CHIP  "firebee1"  ASSIGNED TO AN: EP3C40F484C6
-
-Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
--------------------------------------------------------------------------------------------------------------
-GND                          : A1        : gnd    :                   :         :           :                
-VCCIO8                       : A2        : power  :                   : 3.3V    : 8         :                
-LP_D[6]                      : A3        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-nSRBLE                       : A4        : output : 3.3-V LVTTL       :         : 8         : Y              
-SRD[1]                       : A5        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-IO[3]                        : A6        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-IO[1]                        : A7        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-IO[0]                        : A8        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-SRD[10]                      : A9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-SRD[9]                       : A10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-DVI_INT                      : A11       : input  : 3.3-V LVTTL       :         : 8         : Y              
-nDACK1                       : A12       : input  : 3.3-V LVTTL       :         : 7         : Y              
-IO[16]                       : A13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-IO[14]                       : A14       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-IO[9]                        : A15       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-SD_DATA1                     : A16       : input  : 3.3-V LVTTL       :         : 7         : Y              
-YM_QA                        : A17       : output : 3.3-V LVTTL       :         : 7         : Y              
-TxD                          : A18       : output : 3.3-V LVTTL       :         : 7         : Y              
-DCD                          : A19       : input  : 3.3-V LVTTL       :         : 7         : Y              
-nRD_DATA                     : A20       : input  : 3.3-V LVTTL       :         : 7         : Y              
-VCCIO7                       : A21       : power  :                   : 3.3V    : 7         :                
-GND                          : A22       : gnd    :                   :         :           :                
-nPCI_INTA                    : AA1       : input  : 3.3-V LVTTL       :         : 2         : Y              
-PIC_INT                      : AA2       : input  : 3.3-V LVTTL       :         : 2         : Y              
-FB_AD[2]                     : AA3       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[6]                     : AA4       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[8]                     : AA5       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-VCCIO3                       : AA6       : power  :                   : 3.3V    : 3         :                
-FB_AD[15]                    : AA7       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[22]                    : AA8       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[25]                    : AA9       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[31]                    : AA10      : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-GND+                         : AA11      :        :                   :         : 3         :                
-GND+                         : AA12      :        :                   :         : 4         :                
-VD[18]                       : AA13      : bidir  : 2.5 V             :         : 4         : Y              
-VD[25]                       : AA14      : bidir  : 2.5 V             :         : 4         : Y              
-VDQS[0]                      : AA15      : bidir  : 2.5 V             :         : 4         : Y              
-VDM[0]                       : AA16      : output : 2.5 V             :         : 4         : Y              
-nDDR_CLK                     : AA17      : output : 2.5 V             :         : 4         : Y              
-VA[12]                       : AA18      : output : 2.5 V             :         : 4         : Y              
-BA[1]                        : AA19      : output : 2.5 V             :         : 4         : Y              
-VA[7]                        : AA20      : output : 2.5 V             :         : 4         : Y              
-VA[6]                        : AA21      : output : 2.5 V             :         : 5         : Y              
-VA[4]                        : AA22      : output : 2.5 V             :         : 5         : Y              
-GND                          : AB1       : gnd    :                   :         :           :                
-VCCIO3                       : AB2       : power  :                   : 3.3V    : 3         :                
-FB_AD[3]                     : AB3       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[7]                     : AB4       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[9]                     : AB5       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-GND                          : AB6       : gnd    :                   :         :           :                
-FB_AD[16]                    : AB7       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[23]                    : AB8       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[26]                    : AB9       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-CLK24M576                    : AB10      : output : 3.3-V LVTTL       :         : 3         : Y              
-GND+                         : AB11      :        :                   :         : 3         :                
-CLK33M                       : AB12      : input  : 3.3-V LVTTL       :         : 4         : Y              
-VD[29]                       : AB13      : bidir  : 2.5 V             :         : 4         : Y              
-VD[26]                       : AB14      : bidir  : 2.5 V             :         : 4         : Y              
-VD[24]                       : AB15      : bidir  : 2.5 V             :         : 4         : Y              
-VD[23]                       : AB16      : bidir  : 2.5 V             :         : 4         : Y              
-DDR_CLK                      : AB17      : output : 2.5 V             :         : 4         : Y              
-nVCAS                        : AB18      : output : 2.5 V             :         : 4         : Y              
-VA[9]                        : AB19      : output : 2.5 V             :         : 4         : Y              
-VA[8]                        : AB20      : output : 2.5 V             :         : 4         : Y              
-VCCIO4                       : AB21      : power  :                   : 2.5V    : 4         :                
-GND                          : AB22      : gnd    :                   :         :           :                
-ACSI_D[0]                    : B1        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-MIDI_TLR                     : B2        : output : 3.3-V LVTTL       :         : 1         : Y              
-LP_D[5]                      : B3        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-nSRBHE                       : B4        : output : 3.3-V LVTTL       :         : 8         : Y              
-SRD[0]                       : B5        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-IO[4]                        : B6        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-IO[2]                        : B7        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-nSRCS                        : B8        : output : 3.3-V LVTTL       :         : 8         : Y              
-SRD[8]                       : B9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-SRD[11]                      : B10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-nRSTO_MCF                    : B11       : input  : 3.3-V LVTTL       :         : 8         : Y              
-nDACK0                       : B12       : input  : 3.3-V LVTTL       :         : 7         : Y              
-IO[17]                       : B13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-IO[15]                       : B14       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-IO[10]                       : B15       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-SD_DATA0                     : B16       : input  : 3.3-V LVTTL       :         : 7         : Y              
-SD_DATA2                     : B17       : input  : 3.3-V LVTTL       :         : 7         : Y              
-RTS                          : B18       : output : 3.3-V LVTTL       :         : 7         : Y              
-RI                           : B19       : input  : 3.3-V LVTTL       :         : 7         : Y              
-nSDSEL                       : B20       : output : 3.3-V LVTTL       :         : 7         : Y              
-VB[5]                        : B21       : output : 3.0-V LVTTL       :         : 6         : Y              
-VB[4]                        : B22       : output : 3.0-V LVTTL       :         : 6         : Y              
-ACSI_D[4]                    : C1        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-ACSI_D[3]                    : C2        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-LP_D[2]                      : C3        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-LP_D[1]                      : C4        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-GND                          : C5        : gnd    :                   :         :           :                
-SRD[2]                       : C6        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-IO[7]                        : C7        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-IO[6]                        : C8        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-GND                          : C9        : gnd    :                   :         :           :                
-SRD[4]                       : C10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-GND                          : C11       : gnd    :                   :         :           :                
-GND                          : C12       : gnd    :                   :         :           :                
-IO[11]                       : C13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-GND                          : C14       : gnd    :                   :         :           :                
-SD_CLK                       : C15       : output : 3.3-V LVTTL       :         : 7         : Y              
-GND                          : C16       : gnd    :                   :         :           :                
-nDCHG                        : C17       : input  : 3.3-V LVTTL       :         : 7         : Y              
-GND                          : C18       : gnd    :                   :         :           :                
-TRACK00                      : C19       : input  : 3.3-V LVTTL       :         : 7         : Y              
-VB[6]                        : C20       : output : 3.0-V LVTTL       :         : 6         : Y              
-VB[3]                        : C21       : output : 3.0-V LVTTL       :         : 6         : Y              
-VB[2]                        : C22       : output : 3.0-V LVTTL       :         : 6         : Y              
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT : D1        : input  : 3.3-V LVTTL       :         : 1         : N              
-ACSI_D[5]                    : D2        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-GND                          : D3        : gnd    :                   :         :           :                
-VCCIO1                       : D4        : power  :                   : 3.3V    : 1         :                
-VCCIO8                       : D5        : power  :                   : 3.3V    : 8         :                
-LP_D[4]                      : D6        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8         :                
-GND                          : D8        : gnd    :                   :         :           :                
-VCCIO8                       : D9        : power  :                   : 3.3V    : 8         :                
-SRD[12]                      : D10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-VCCIO8                       : D11       : power  :                   : 3.3V    : 8         :                
-VCCIO7                       : D12       : power  :                   : 3.3V    : 7         :                
-IO[12]                       : D13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-VCCIO7                       : D14       : power  :                   : 3.3V    : 7         :                
-DTR                          : D15       : output : 3.3-V LVTTL       :         : 7         : Y              
-VCCIO7                       : D16       : power  :                   : 3.3V    : 7         :                
-nWR_GATE                     : D17       : output : 3.3-V LVTTL       :         : 7         : Y              
-VCCIO7                       : D18       : power  :                   : 3.3V    : 7         :                
-nWP                          : D19       : input  : 3.3-V LVTTL       :         : 7         : Y              
-VB[7]                        : D20       : output : 3.0-V LVTTL       :         : 6         : Y              
-VG[7]                        : D21       : output : 3.0-V LVTTL       :         : 6         : Y              
-VG[6]                        : D22       : output : 3.0-V LVTTL       :         : 6         : Y              
-SCSI_D[1]                    : E1        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT : E2        : input  : 3.3-V LVTTL       :         : 1         : N              
-ACSI_D[2]                    : E3        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 1         :                
-LPDIR                        : E5        : output : 3.3-V LVTTL       :         : 8         : Y              
-LP_STR                       : E6        : output : 3.3-V LVTTL       :         : 8         : Y              
-LP_D[3]                      : E7        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-VCCIO8                       : E8        : power  :                   : 3.3V    : 8         :                
-IO[5]                        : E9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-SRD[6]                       : E10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-nDREQ1                       : E11       : output : 3.3-V LVTTL       :         : 7         : Y              
-MIDI_IN                      : E12       : input  : 3.3-V LVTTL       :         : 7         : Y              
-IO[13]                       : E13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-SD_CMD_D1                    : E14       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-YM_QC                        : E15       : output : 3.3-V LVTTL       :         : 7         : Y              
-nINDEX                       : E16       : input  : 3.3-V LVTTL       :         : 7         : Y              
-VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
-GNDA2                        : E18       : gnd    :                   :         :           :                
-VCCIO6                       : E19       : power  :                   : 3.0V    : 6         :                
-GND                          : E20       : gnd    :                   :         :           :                
-VG[2]                        : E21       : output : 3.0-V LVTTL       :         : 6         : Y              
-VG[1]                        : E22       : output : 3.0-V LVTTL       :         : 6         : Y              
-SCSI_D[3]                    : F1        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-SCSI_D[2]                    : F2        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-GND                          : F3        : gnd    :                   :         :           :                
-VCCIO1                       : F4        : power  :                   : 3.3V    : 1         :                
-GNDA3                        : F5        : gnd    :                   :         :           :                
-VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
-LP_D[0]                      : F7        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-nSRWE                        : F8        : output : 3.3-V LVTTL       :         : 8         : Y              
-SRD[5]                       : F9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-SRD[13]                      : F10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-nSROE                        : F11       : output : 3.3-V LVTTL       :         : 7         : Y              
-GND                          : F12       : gnd    :                   :         :           :                
-SD_CD_DATA3                  : F13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-nSTEP                        : F14       : output : 3.3-V LVTTL       :         : 7         : Y              
-DSA_D                        : F15       : output : 3.3-V LVTTL       :         : 7         : Y              
-HD_DD                        : F16       : input  : 3.3-V LVTTL       :         : 7         : Y              
-nSYNC                        : F17       : output : 3.0-V LVCMOS      :         : 6         : Y              
-VCCA2                        : F18       : power  :                   : 2.5V    :           :                
-PIXEL_CLK_PAD                : F19       : output : 3.0-V LVTTL       :         : 6         : Y              
-nIRQ[4]                      : F20       : output : 3.0-V LVCMOS      :         : 6         : Y              
-nIRQ[2]                      : F21       : output : 3.0-V LVCMOS      :         : 6         : Y              
-VR[7]                        : F22       : output : 3.0-V LVTTL       :         : 6         : Y              
-GND+                         : G1        :        :                   :         : 1         :                
-MAIN_CLK                     : G2        : input  : 3.3-V LVTTL       :         : 1         : Y              
-SCSI_D[5]                    : G3        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-SCSI_D[4]                    : G4        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-ACSI_D[1]                    : G5        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-VCCA3                        : G6        : power  :                   : 2.5V    :           :                
-LP_BUSY                      : G7        : input  : 3.3-V LVTTL       :         : 8         : Y              
-LP_D[7]                      : G8        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-SRD[14]                      : G9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-IO[8]                        : G10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-SRD[3]                       : G11       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-VCCINT                       : G12       : power  :                   : 1.2V    :           :                
-YM_QB                        : G13       : output : 3.3-V LVTTL       :         : 7         : Y              
-nWR                          : G14       : output : 3.3-V LVTTL       :         : 7         : Y              
-nSTEP_DIR                    : G15       : output : 3.3-V LVTTL       :         : 7         : Y              
-nMOT_ON                      : G16       : output : 3.3-V LVTTL       :         : 7         : Y              
-nBLANK_PAD                   : G17       : output : 3.0-V LVTTL       :         : 6         : Y              
-VB[0]                        : G18       : output : 3.0-V LVTTL       :         : 6         : Y              
-VCCIO6                       : G19       : power  :                   : 3.0V    : 6         :                
-GND                          : G20       : gnd    :                   :         :           :                
-E0_INT                       : G21       : input  : 3.3-V LVTTL       :         : 6         : Y              
-IDE_INT                      : G22       : input  : 3.3-V LVTTL       :         : 6         : Y              
-nSCSI_C_D                    : H1        : input  : 3.3-V LVTTL       :         : 1         : Y              
-nSCSI_MSG                    : H2        : input  : 3.3-V LVTTL       :         : 1         : Y              
-GND                          : H3        : gnd    :                   :         :           :                
-VCCIO1                       : H4        : power  :                   : 3.3V    : 1         :                
-MIDI_OLR                     : H5        : output : 3.3-V LVTTL       :         : 1         : Y              
-ACSI_D[7]                    : H6        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-ACSI_D[6]                    : H7        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 1         :                
-VCCINT                       : H9        : power  :                   : 1.2V    :           :                
-SRD[15]                      : H10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-SRD[7]                       : H11       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-GND                          : H12       : gnd    :                   :         :           :                
-GND                          : H13       : gnd    :                   :         :           :                
-CTS                          : H14       : input  : 3.3-V LVTTL       :         : 7         : Y              
-RxD                          : H15       : input  : 3.3-V LVTTL       :         : 7         : Y              
-VG[5]                        : H16       : output : 3.0-V LVTTL       :         : 6         : Y              
-VB[1]                        : H17       : output : 3.0-V LVTTL       :         : 6         : Y              
-VG[3]                        : H18       : output : 3.0-V LVTTL       :         : 6         : Y              
-VG[0]                        : H19       : output : 3.0-V LVTTL       :         : 6         : Y              
-nIRQ[3]                      : H20       : output : 3.0-V LVCMOS      :         : 6         : Y              
-VR[3]                        : H21       : output : 3.0-V LVTTL       :         : 6         : Y              
-VR[2]                        : H22       : output : 3.0-V LVTTL       :         : 6         : Y              
-CLKUSB                       : J1        : output : 3.3-V LVTTL       :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : J2        :        :                   :         : 1         :                
-nSCSI_I_O                    : J3        : input  : 3.3-V LVTTL       :         : 1         : Y              
-nACSI_INT                    : J4        : input  : 3.3-V LVTTL       :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : J5        :        :                   :         : 1         :                
-SCSI_D[0]                    : J6        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-SCSI_DIR                     : J7        : output : 3.3-V LVTTL       :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : J8        :        :                   :         : 1         :                
-GND                          : J9        : gnd    :                   :         :           :                
-VCCINT                       : J10       : power  :                   : 1.2V    :           :                
-VCCINT                       : J11       : power  :                   : 1.2V    :           :                
-VCCINT                       : J12       : power  :                   : 1.2V    :           :                
-VCCINT                       : J13       : power  :                   : 1.2V    :           :                
-VCCINT                       : J14       : power  :                   : 1.2V    :           :                
-GND                          : J15       : gnd    :                   :         :           :                
-VCCINT                       : J16       : power  :                   : 1.2V    :           :                
-VG[4]                        : J17       : output : 3.0-V LVTTL       :         : 6         : Y              
-VR[6]                        : J18       : output : 3.0-V LVTTL       :         : 6         : Y              
-GND                          : J19       : gnd    :                   :         :           :                
-VCCIO6                       : J20       : power  :                   : 3.0V    : 6         :                
-VR[1]                        : J21       : output : 3.0-V LVTTL       :         : 6         : Y              
-VR[0]                        : J22       : output : 3.0-V LVTTL       :         : 6         : Y              
-~ALTERA_DATA0~ / RESERVED_INPUT : K1        : input  : 3.3-V LVTTL       :         : 1         : N              
-~ALTERA_DCLK~ / RESERVED_INPUT : K2        : input  : 3.3-V LVTTL       :         : 1         : N              
-GND                          : K3        : gnd    :                   :         :           :                
-VCCIO1                       : K4        : power  :                   : 3.3V    : 1         :                
-nCONFIG                      : K5        :        :                   :         : 1         :                
-nSTATUS                      : K6        :        :                   :         : 1         :                
-nACSI_DRQ                    : K7        : input  : 3.3-V LVTTL       :         : 1         : Y              
-SCSI_D[7]                    : K8        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-VCCINT                       : K9        : power  :                   : 1.2V    :           :                
-GND                          : K10       : gnd    :                   :         :           :                
-GND                          : K11       : gnd    :                   :         :           :                
-GND                          : K12       : gnd    :                   :         :           :                
-GND                          : K13       : gnd    :                   :         :           :                
-VCCINT                       : K14       : power  :                   : 1.2V    :           :                
-VCCINT                       : K15       : power  :                   : 1.2V    :           :                
-GND                          : K16       : gnd    :                   :         :           :                
-VR[4]                        : K17       : output : 3.0-V LVTTL       :         : 6         : Y              
-VR[5]                        : K18       : output : 3.0-V LVTTL       :         : 6         : Y              
-VSYNC_PAD                    : K19       : output : 3.0-V LVTTL       :         : 6         : Y              
-MSEL3                        : K20       :        :                   :         : 6         :                
-HSYNC_PAD                    : K21       : output : 3.0-V LVTTL       :         : 6         : Y              
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22       : output : 3.0-V LVTTL       :         : 6         : N              
-TMS                          : L1        : input  :                   :         : 1         :                
-TCK                          : L2        : input  :                   :         : 1         :                
-nCE                          : L3        :        :                   :         : 1         :                
-TDO                          : L4        : output :                   :         : 1         :                
-TDI                          : L5        : input  :                   :         : 1         :                
-ACSI_DIR                     : L6        : output : 3.3-V LVTTL       :         : 2         : Y              
-PIC_AMKB_RX                  : L7        : input  : 3.3-V LVTTL       :         : 2         : Y              
-SCSI_D[6]                    : L8        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-VCCINT                       : L9        : power  :                   : 1.2V    :           :                
-GND                          : L10       : gnd    :                   :         :           :                
-GND                          : L11       : gnd    :                   :         :           :                
-GND                          : L12       : gnd    :                   :         :           :                
-GND                          : L13       : gnd    :                   :         :           :                
-VCCINT                       : L14       : power  :                   : 1.2V    :           :                
-GND                          : L15       : gnd    :                   :         :           :                
-VCCINT                       : L16       : power  :                   : 1.2V    :           :                
-MSEL2                        : L17       :        :                   :         : 6         :                
-MSEL1                        : L18       :        :                   :         : 6         :                
-VCCIO6                       : L19       : power  :                   : 3.0V    : 6         :                
-GND                          : L20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22       :        :                   :         : 6         :                
-nACSI_RESET                  : M1        : output : 3.3-V LVTTL       :         : 2         : Y              
-nACSI_CS                     : M2        : output : 3.3-V LVTTL       :         : 2         : Y              
-nSCSI_ATN                    : M3        : output : 3.3-V LVTTL       :         : 2         : Y              
-nACSI_ACK                    : M4        : output : 3.3-V LVTTL       :         : 2         : Y              
-IDE_RES                      : M5        : output : 3.3-V LVTTL       :         : 2         : Y              
-ACSI_A1                      : M6        : output : 3.3-V LVTTL       :         : 2         : Y              
-SCSI_PAR                     : M7        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
-nSCSI_SEL                    : M8        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
-VCCINT                       : M9        : power  :                   : 1.2V    :           :                
-GND                          : M10       : gnd    :                   :         :           :                
-GND                          : M11       : gnd    :                   :         :           :                
-GND                          : M12       : gnd    :                   :         :           :                
-GND                          : M13       : gnd    :                   :         :           :                
-VCCINT                       : M14       : power  :                   : 1.2V    :           :                
-VCCINT                       : M15       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
-MSEL0                        : M17       :        :                   :         : 6         :                
-CONF_DONE                    : M18       :        :                   :         : 6         :                
-SD_WP                        : M19       : input  : 3.3-V LVTTL       :         : 5         : Y              
-SD_CARD_DEDECT               : M20       : input  : 3.3-V LVTTL       :         : 5         : Y              
-VD[1]                        : M21       : bidir  : 2.5 V             :         : 5         : Y              
-VD[0]                        : M22       : bidir  : 2.5 V             :         : 5         : Y              
-AMKB_TX                      : N1        : output : 3.3-V LVCMOS      :         : 2         : Y              
-nSCSI_ACK                    : N2        : output : 3.3-V LVTTL       :         : 2         : Y              
-GND                          : N3        : gnd    :                   :         :           :                
-VCCIO2                       : N4        : power  :                   : 3.3V    : 2         :                
-nRP_LDS                      : N5        : output : 3.3-V LVTTL       :         : 2         : Y              
-nSCSI_RST                    : N6        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
-nIRQ[7]                      : N7        : output : 3.3-V LVTTL       :         : 2         : Y              
-nSCSI_BUSY                   : N8        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
-VCCINT                       : N9        : power  :                   : 1.2V    :           :                
-GND                          : N10       : gnd    :                   :         :           :                
-GND                          : N11       : gnd    :                   :         :           :                
-GND                          : N12       : gnd    :                   :         :           :                
-GND                          : N13       : gnd    :                   :         :           :                
-VCCINT                       : N14       : power  :                   : 1.2V    :           :                
-GND                          : N15       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
-VD[12]                       : N17       : bidir  : 2.5 V             :         : 5         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
-LED_FPGA_OK                  : N19       : output : 2.5 V             :         : 5         : Y              
-VD[15]                       : N20       : bidir  : 2.5 V             :         : 5         : Y              
-~ALTERA_DEV_CLRn~ / RESERVED_INPUT : N21       : input  : 2.5 V             :         : 5         : N              
-~ALTERA_DEV_OE~ / RESERVED_INPUT : N22       : input  : 2.5 V             :         : 5         : N              
-nIDE_RD                      : P1        : output : 3.3-V LVTTL       :         : 2         : Y              
-nIDE_WR                      : P2        : output : 3.3-V LVTTL       :         : 2         : Y              
-nROM3                        : P3        : output : 3.3-V LVTTL       :         : 2         : Y              
-nRP_UDS                      : P4        : output : 3.3-V LVTTL       :         : 2         : Y              
-nIRQ[5]                      : P5        : output : 3.3-V LVTTL       :         : 2         : Y              
-nPCI_INTD                    : P6        : input  : 3.3-V LVTTL       :         : 2         : Y              
-nIRQ[6]                      : P7        : output : 3.3-V LVTTL       :         : 2         : Y              
-GND                          : P8        : gnd    :                   :         :           :                
-VCCINT                       : P9        : power  :                   : 1.2V    :           :                
-VCCINT                       : P10       : power  :                   : 1.2V    :           :                
-VCCINT                       : P11       : power  :                   : 1.2V    :           :                
-VCCINT                       : P12       : power  :                   : 1.2V    :           :                
-VCCINT                       : P13       : power  :                   : 1.2V    :           :                
-VCCINT                       : P14       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
-VD[10]                       : P17       : bidir  : 2.5 V             :         : 5         : Y              
-VCCIO5                       : P18       : power  :                   : 2.5V    : 5         :                
-GND                          : P19       : gnd    :                   :         :           :                
-VD[13]                       : P20       : bidir  : 2.5 V             :         : 5         : Y              
-VD[4]                        : P21       : bidir  : 2.5 V             :         : 5         : Y              
-VD[2]                        : P22       : bidir  : 2.5 V             :         : 5         : Y              
-nIDE_CS1                     : R1        : output : 3.3-V LVTTL       :         : 2         : Y              
-nIDE_CS0                     : R2        : output : 3.3-V LVTTL       :         : 2         : Y              
-GND                          : R3        : gnd    :                   :         :           :                
-VCCIO2                       : R4        : power  :                   : 3.3V    : 2         :                
-TIN0                         : R5        : output : 3.3-V LVTTL       :         : 2         : Y              
-nFB_OE                       : R6        : input  : 3.3-V LVTTL       :         : 2         : Y              
-FB_ALE                       : R7        : input  : 3.3-V LVTTL       :         : 2         : Y              
-VCCINT                       : R8        : power  :                   : 1.2V    :           :                
-GND                          : R9        : gnd    :                   :         :           :                
-VCCINT                       : R10       : power  :                   : 1.2V    :           :                
-GND                          : R11       : gnd    :                   :         :           :                
-VCCINT                       : R12       : power  :                   : 1.2V    :           :                
-GND                          : R13       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 4         :                
-VD[5]                        : R17       : bidir  : 2.5 V             :         : 5         : Y              
-VD[9]                        : R18       : bidir  : 2.5 V             :         : 5         : Y              
-VD[6]                        : R19       : bidir  : 2.5 V             :         : 5         : Y              
-VD[3]                        : R20       : bidir  : 2.5 V             :         : 5         : Y              
-VD[11]                       : R21       : bidir  : 2.5 V             :         : 5         : Y              
-VD[14]                       : R22       : bidir  : 2.5 V             :         : 5         : Y              
-WP_CF_CARD                   : T1        : input  : 3.3-V LVTTL       :         : 2         : Y              
-GND+                         : T2        :        :                   :         : 2         :                
-nFB_BURST                    : T3        : input  : 3.3-V LVTTL       :         : 2         : Y              
-CLK25M                       : T4        : output : 3.3-V LVTTL       :         : 2         : Y              
-nFB_WR                       : T5        : input  : 3.3-V LVTTL       :         : 2         : Y              
-VCCA1                        : T6        : power  :                   : 2.5V    :           :                
-nFB_TA                       : T7        : output : 3.3-V LVTTL       :         : 2         : Y              
-nFB_CS1                      : T8        : input  : 3.3-V LVTTL       :         : 3         : Y              
-nFB_CS2                      : T9        : input  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[20]                    : T10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[24]                    : T11       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-VD[16]                       : T12       : bidir  : 2.5 V             :         : 4         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : T13       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
-VDQS[3]                      : T16       : bidir  : 2.5 V             :         : 4         : Y              
-VDM[3]                       : T17       : output : 2.5 V             :         : 5         : Y              
-nVCS                         : T18       : output : 2.5 V             :         : 5         : Y              
-VCCIO5                       : T19       : power  :                   : 2.5V    : 5         :                
-GND                          : T20       : gnd    :                   :         :           :                
-nMASTER                      : T21       : input  : 3.3-V LVTTL       :         : 5         : Y              
-TOUT0                        : T22       : input  : 3.3-V LVTTL       :         : 5         : Y              
-nSCSI_DRQ                    : U1        : input  : 3.3-V LVTTL       :         : 2         : Y              
-nROM4                        : U2        : output : 3.3-V LVTTL       :         : 2         : Y              
-GND                          : U3        : gnd    :                   :         :           :                
-VCCIO2                       : U4        : power  :                   : 3.3V    : 2         :                
-GNDA1                        : U5        : gnd    :                   :         :           :                
-VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
-FB_SIZE0                     : U8        : input  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[12]                    : U9        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[21]                    : U10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[27]                    : U11       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-VD[31]                       : U12       : bidir  : 2.5 V             :         : 4         : Y              
-VD[20]                       : U13       : bidir  : 2.5 V             :         : 4         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
-VCKE                         : U15       : output : 2.5 V             :         : 4         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : U16       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U17       :        :                   :         : 4         :                
-VCCA4                        : U18       : power  :                   : 2.5V    :           :                
-VA[11]                       : U19       : output : 2.5 V             :         : 5         : Y              
-VDM[2]                       : U20       : output : 2.5 V             :         : 5         : Y              
-VD[7]                        : U21       : bidir  : 2.5 V             :         : 5         : Y              
-VDQS[2]                      : U22       : bidir  : 2.5 V             :         : 5         : Y              
-nPD_VGA                      : V1        : output : 3.3-V LVTTL       :         : 2         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
-nPCI_INTC                    : V3        : input  : 3.3-V LVTTL       :         : 2         : Y              
-nPCI_INTB                    : V4        : input  : 3.3-V LVTTL       :         : 2         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
-nFB_CS3                      : V6        : input  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[5]                     : V7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[13]                    : V8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[18]                    : V9        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[19]                    : V10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[28]                    : V11       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-VD[30]                       : V12       : bidir  : 2.5 V             :         : 4         : Y              
-VD[27]                       : V13       : bidir  : 2.5 V             :         : 4         : Y              
-VD[19]                       : V14       : bidir  : 2.5 V             :         : 4         : Y              
-VD[21]                       : V15       : bidir  : 2.5 V             :         : 4         : Y              
-VDM[1]                       : V16       : output : 2.5 V             :         : 4         : Y              
-VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
-GNDA4                        : V18       : gnd    :                   :         :           :                
-VCCIO5                       : V19       : power  :                   : 2.5V    : 5         :                
-GND                          : V20       : gnd    :                   :         :           :                
-VA[10]                       : V21       : output : 2.5 V             :         : 5         : Y              
-VD[8]                        : V22       : bidir  : 2.5 V             :         : 5         : Y              
-nCF_CS1                      : W1        : output : 3.3-V LVTTL       :         : 2         : Y              
-nCF_CS0                      : W2        : output : 3.3-V LVTTL       :         : 2         : Y              
-GND                          : W3        : gnd    :                   :         :           :                
-VCCIO2                       : W4        : power  :                   : 3.3V    : 2         :                
-VCCIO3                       : W5        : power  :                   : 3.3V    : 3         :                
-FB_AD[4]                     : W6        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[10]                    : W7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[14]                    : W8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-VCCIO3                       : W9        : power  :                   : 3.3V    : 3         :                
-FB_AD[29]                    : W10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-VCCIO3                       : W11       : power  :                   : 3.3V    : 3         :                
-VCCIO4                       : W12       : power  :                   : 2.5V    : 4         :                
-VD[28]                       : W13       : bidir  : 2.5 V             :         : 4         : Y              
-VD[22]                       : W14       : bidir  : 2.5 V             :         : 4         : Y              
-VDQS[1]                      : W15       : bidir  : 2.5 V             :         : 4         : Y              
-VCCIO4                       : W16       : power  :                   : 2.5V    : 4         :                
-nVRAS                        : W17       : output : 2.5 V             :         : 4         : Y              
-VCCIO4                       : W18       : power  :                   : 2.5V    : 4         :                
-BA[0]                        : W19       : output : 2.5 V             :         : 5         : Y              
-VA[0]                        : W20       : output : 2.5 V             :         : 5         : Y              
-VA[2]                        : W21       : output : 2.5 V             :         : 5         : Y              
-VA[1]                        : W22       : output : 2.5 V             :         : 5         : Y              
-IDE_RDY                      : Y1        : input  : 3.3-V LVTTL       :         : 2         : Y              
-AMKB_RX                      : Y2        : input  : 3.3-V LVTTL       :         : 2         : Y              
-FB_AD[0]                     : Y3        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_SIZE1                     : Y4        : input  : 3.3-V LVTTL       :         : 3         : Y              
-GND                          : Y5        : gnd    :                   :         :           :                
-FB_AD[1]                     : Y6        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[11]                    : Y7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[17]                    : Y8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-GND                          : Y9        : gnd    :                   :         :           :                
-FB_AD[30]                    : Y10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-GND                          : Y11       : gnd    :                   :         :           :                
-GND                          : Y12       : gnd    :                   :         :           :                
-VD[17]                       : Y13       : bidir  : 2.5 V             :         : 4         : Y              
-VCCIO4                       : Y14       : power  :                   : 2.5V    : 4         :                
-GND                          : Y15       : gnd    :                   :         :           :                
-GND                          : Y16       : gnd    :                   :         :           :                
-nVWE                         : Y17       : output : 2.5 V             :         : 4         : Y              
-GND                          : Y18       : gnd    :                   :         :           :                
-VCCIO5                       : Y19       : power  :                   : 2.5V    : 5         :                
-GND                          : Y20       : gnd    :                   :         :           :                
-VA[5]                        : Y21       : output : 2.5 V             :         : 5         : Y              
-VA[3]                        : Y22       : output : 2.5 V             :         : 5         : Y              

firebee1.qws

@@ -1,4 +0,0 @@
-[ProjectWorkspace]
-ptn_Child1=Frames
-[ProjectWorkspace.Frames]
-ptn_Child1=ChildFrames

firebee1.sdc

@@ -0,0 +1,224 @@
+#--------------------------------------------------------------#
+#                                                              #
+# Synopsis design constraints for the Firebee project          #
+#                                                              #
+# This file is part of the Firebee ACP project.                #
+# http://www.experiment-s.de                                   #
+#                                                              #
+# Description:                                                 #
+#   timing constraints for the Firebee VHDL config             #
+#                                                              #
+#                                                              #
+#                                                              #
+# To Do:                                                       #
+# -                                                            #
+#                                                              #
+# Author(s):                                                   #
+# Markus Fröschle, mfro@mubf.de                                #
+#                                                              #
+#--------------------------------------------------------------#
+#                                                              #
+# Copyright (C) 2015 Markus Fröschle & the ACP project         #
+#                                                              #
+# This source file may be used and distributed without         #
+# restriction provided that this copyright statement is not    #
+# removed from the file and that any derivative work contains  #
+# the original copyright notice and the associated disclaimer. #
+#                                                              #
+# This source file is free software; you can redistribute it   #
+# and/or modify it under the terms of the GNU Lesser General   #
+# Public License as published by the Free Software Foundation; #
+# either version 2.1 of the License, or (at your option) any   #
+# later version.                                               #
+#                                                              #
+# This source is distributed in the hope that it will be       #
+# useful, but WITHOUT ANY WARRANTY; without even the implied   #
+# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      #
+# PURPOSE. See the GNU Lesser General Public License for more  #
+# details.                                                     #
+#                                                              #
+# You should have received a copy of the GNU Lesser General    #
+# Public License along with this source; if not, download it   #
+# from http://www.gnu.org/licenses/lgpl.html                   #
+#                                                              #
+################################################################
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_ports {MAIN_CLK}]
+
+# Clocks used:
+# MAIN_CLK          33MHz
+# 
+# PLL1: i_mfp_acia_clk_pll
+# input: MAIN_CLK
+# c0: 500 kHz
+# c1: 2.4576 MHz
+# c2: 24.576 MHz
+# 
+# PLL2: i_ddr_clock_pll
+# input: MAIN_CLK
+# c0: 132 MHz   190°
+# c1: 132 MHz   0°
+# c2: 132 MHz   180°
+# c3: 132 MHz   105°
+# c4: 66 MHz    270°
+#
+# PLL3: i_atari_clk_pll
+# input: MAIN_CLK
+# c0: 2 MHz
+# c1: 16 MHz
+# c2: 25 MHz
+# c3: 48 MHz
+# 
+# PLL4_ i_video_clk_pll
+# input: USB_CLK (48 MHz, PLL3 c3)
+# c0: 96 MHz, programmable in 1MHz steps
+#
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+derive_pll_clocks
+
+# PIXEL_CLK is either
+# CLK13M, CLK17M, CLK25M, CLK33M or CLK_VIDEO
+# where CLK13M is half of CLK25M,
+# CLK17M is half of CLK33M and CLK_VIDEO is the freely programmable
+# clock of i_video_clk_pll
+#
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}]  2.00  
+set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}]  2.00  
+derive_clock_uncertainty
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.000 [all_inputs]
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock [get_clocks {MAIN_CLK}]  -max 1.000 [all_outputs]
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+#
+# i_video_clk is freely programmable
+#
+set_false_path  -from  [get_clocks {MAIN_CLK}]  -to  [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
+
+# MAIN_CLK to 16 MHz clk -> false_path
+set_false_path  -from  [get_clocks {MAIN_CLK}]  -to  [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
+set_false_path  -from  [get_clocks {MAIN_CLK}]  -to  [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]
+
+# MAIN_CLK to DDR clk and v.v.
+set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
+set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
+
+set_false_path  -from  [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}]  -to  [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
+set_false_path  -from  [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}]  -to  [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
+set_false_path  -from  [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {MAIN_CLK}]
+set_false_path  -from  [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]  -to  [get_clocks {MAIN_CLK}]
+
+# 2 MHz to 33 MHz
+set_false_path  -from  [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {MAIN_CLK}]
+
+# 16 MHz to 33 MHz
+set_false_path  -from  [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]  -to  [get_clocks {MAIN_CLK}]
+set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
+
+# 25 MHz to 33 MHz
+set_false_path  -from  [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]  -to  [get_clocks {MAIN_CLK}]
+set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]
+
+set_false_path  -from  [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]  -to  [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
+set_false_path  -from  [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]  -to  [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
+
+set_false_path  -from  [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]
+
+set_false_path  -from  [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {MAIN_CLK}]
+set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
+
+set_false_path  -from  [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
+
+set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}]
+set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}]
+set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}]
+set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*}]
+set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe19|dffe20a*}]
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+# from here to the end of the file statements are just an experiment
+
+#set_max_delay 25 -from [get_ports {*}]
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+#set_min_delay 0.5 -from [get_ports {*}]
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+#set_input_delay -max -clock [get_clocks {MAIN_CLK}] [get_pins {*}] 25
+#set_input_delay -min -clock [get_clocks {MAIN_CLK}] [get_pins {*}] .5
+#set_output_delay -max -clock [get_clocks {MAIN_CLK}] [get_pins {*}] 25
+#set_output_delay -min -clock [get_clocks {MAIN_CLK}] [get_pins {*}] .5
+
+# restrict timing of video controller
+
+#set_output_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {VA[*]}]
+#set_output_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {VA[*]}]
+
+#set_output_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {BA[*]}]
+#set_output_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {BA[*]}]
+
+#set_output_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {VD[*]}]
+#set_output_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {VD[*]}]
+#set_input_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {VD[*]}]
+#set_input_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {VD[*]}]

firebee1.tan.summary

@@ -1,296 +0,0 @@
---------------------------------------------------------------------------------------
-Timing Analyzer Summary
---------------------------------------------------------------------------------------
-
-Type           : Worst-case tsu
-Slack          : -4.528 ns
-Required Time  : 1.000 ns
-Actual Time    : 5.528 ns
-From           : MAIN_CLK
-To             : altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state
-From Clock     : --
-To Clock       : MAIN_CLK
-Failed Paths   : 6867
-
-Type           : Worst-case tco
-Slack          : -14.840 ns
-Required Time  : 1.000 ns
-Actual Time    : 15.840 ns
-From           : interrupt_handler:nobody|INT_LATCH[8]
-To             : nIRQ[5]
-From Clock     : MAIN_CLK
-To Clock       : --
-Failed Paths   : 4976
-
-Type           : Worst-case tpd
-Slack          : -11.944 ns
-Required Time  : 1.000 ns
-Actual Time    : 12.944 ns
-From           : nFB_CS1
-To             : FB_AD[18]
-From Clock     : --
-To Clock       : --
-Failed Paths   : 514
-
-Type           : Worst-case th
-Slack          : -0.401 ns
-Required Time  : 1.000 ns
-Actual Time    : 1.401 ns
-From           : FB_AD[25]
-To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]
-From Clock     : --
-To Clock       : MAIN_CLK
-Failed Paths   : 117
-
-Type           : Clock Setup: 'CLK33M'
-Slack          : -5.966 ns
-Required Time  : 33.00 MHz ( period = 30.303 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0
-To             : Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]
-To Clock       : CLK33M
-Failed Paths   : 3741
-
-Type           : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'
-Slack          : -4.615 ns
-Required Time  : 24.98 MHz ( period = 40.033 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0
-To             : Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]
-From Clock     : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
-To Clock       : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]
-Failed Paths   : 3741
-
-Type           : Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
-Slack          : -4.294 ns
-Required Time  : 95.92 MHz ( period = 10.425 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0
-To             : Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]
-To Clock       : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
-Failed Paths   : 3741
-
-Type           : Clock Setup: 'MAIN_CLK'
-Slack          : -4.261 ns
-Required Time  : 33.00 MHz ( period = 30.303 ns )
-Actual Time    : N/A
-From           : FB_ALE
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
-To Clock       : MAIN_CLK
-Failed Paths   : 27347
-
-Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
-Slack          : -2.673 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : FB_ALE
-To             : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
-Failed Paths   : 86
-
-Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
-Slack          : -1.712 ns
-Required Time  : 66.00 MHz ( period = 15.151 ns )
-Actual Time    : N/A
-From           : FB_ALE
-To             : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
-Failed Paths   : 29
-
-Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
-Slack          : 1.672 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]
-To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
-Failed Paths   : 0
-
-Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
-Slack          : 2.965 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : Restricted to 500.00 MHz ( period = 2.000 ns )
-From           : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]
-To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
-Failed Paths   : 0
-
-Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
-Slack          : 5.299 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]
-To             : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
-Failed Paths   : 0
-
-Type           : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'
-Slack          : 28.590 ns
-Required Time  : 15.99 MHz ( period = 62.552 ns )
-Actual Time    : 186.15 MHz ( period = 5.372 ns )
-From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]
-To Clock       : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]
-Failed Paths   : 0
-
-Type           : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'
-Slack          : 498.663 ns
-Required Time  : 2.00 MHz ( period = 500.416 ns )
-Actual Time    : Restricted to 500.00 MHz ( period = 2.000 ns )
-From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]
-To Clock       : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]
-Failed Paths   : 0
-
-Type           : Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'
-Slack          : 1997.239 ns
-Required Time  : 0.50 MHz ( period = 1999.998 ns )
-Actual Time    : 362.45 MHz ( period = 2.759 ns )
-From           : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]
-To             : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]
-From Clock     : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]
-To Clock       : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'MAIN_CLK'
-Slack          : -3.786 ns
-Required Time  : 33.00 MHz ( period = 30.303 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]
-To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]
-From Clock     : MAIN_CLK
-To Clock       : MAIN_CLK
-Failed Paths   : 108
-
-Type           : Clock Hold: 'CLK33M'
-Slack          : -0.687 ns
-Required Time  : 33.00 MHz ( period = 30.303 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
-To             : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
-From Clock     : CLK33M
-To Clock       : CLK33M
-Failed Paths   : 26
-
-Type           : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'
-Slack          : -0.454 ns
-Required Time  : 24.98 MHz ( period = 40.033 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
-To             : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]
-To Clock       : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]
-Failed Paths   : 26
-
-Type           : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'
-Slack          : 0.502 ns
-Required Time  : 15.99 MHz ( period = 62.552 ns )
-Actual Time    : N/A
-From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]
-To Clock       : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
-Slack          : 0.502 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]
-To             : Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
-Slack          : 0.502 ns
-Required Time  : 95.92 MHz ( period = 10.425 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
-To             : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
-From Clock     : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
-To Clock       : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'
-Slack          : 0.564 ns
-Required Time  : 2.00 MHz ( period = 500.416 ns )
-Actual Time    : N/A
-From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]
-To Clock       : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'
-Slack          : 0.825 ns
-Required Time  : 0.50 MHz ( period = 1999.998 ns )
-Actual Time    : N/A
-From           : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]
-To             : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]
-From Clock     : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]
-To Clock       : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
-Slack          : 1.825 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]
-To             : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
-Slack          : 2.664 ns
-Required Time  : 66.00 MHz ( period = 15.151 ns )
-Actual Time    : N/A
-From           : FB_ALE
-To             : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
-Slack          : 3.263 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]
-To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
-Slack          : 4.336 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]
-To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
-Failed Paths   : 0
-
-Type           : Total number of failed paths
-Slack          : 
-Required Time  : 
-Actual Time    : 
-From           : 
-To             : 
-From Clock     : 
-To Clock       : 
-Failed Paths   : 51319
-
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-