Markus Fröschle
|
b22e83e8b7
|
more constraints
|
2014-12-30 15:26:27 +00:00 |
|
Markus Fröschle
|
17b17a2263
|
further constrained
|
2014-12-30 14:05:49 +00:00 |
|
Markus Fröschle
|
7ef61bd397
|
added sdc file and upgraded IP components
|
2014-12-30 12:57:22 +00:00 |
|
Markus Fröschle
|
7f5ab992fc
|
is a generated file
|
2014-12-30 08:15:54 +00:00 |
|
Markus Fröschle
|
f511b1e324
|
removed more generated files
|
2014-12-30 08:15:10 +00:00 |
|
Markus Fröschle
|
978a642ce7
|
removed more generated files
|
2014-12-30 08:12:59 +00:00 |
|
Markus Fröschle
|
6e4e180e96
|
removed generated files
|
2014-12-30 07:37:08 +00:00 |
|
Markus Fröschle
|
1f39271768
|
latest release
|
2014-06-09 21:09:41 +00:00 |
|
Markus Fröschle
|
1a6b187a68
|
new run of quartus
FPGA_quartus@1000
|
2012-11-16 19:32:30 +00:00 |
|
David Gálvez
|
d2e1a3ccc7
|
Moved source_fa into trunk
|
2011-01-03 08:10:50 +00:00 |
|
aschi54
|
92c2ab95fc
|
FPGA_quartus@11
|
2010-12-27 13:20:36 +00:00 |
|