Markus Fröschle
8081df42a6
merged fixes from 0.8.6.1 (errornous skip of FPGA load)
2014-12-26 09:36:45 +00:00
Markus Fröschle
b1c7851f34
start merging R_0.8.6.1 (jtag load bug fix)
2014-12-26 09:07:22 +00:00
Markus Fröschle
8706322f96
added to the DDR RAM model
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reformatted (converted tabs to spaces)
2014-12-25 15:20:14 +00:00
Markus Fröschle
a7eb46e158
used design assistant to force the fitter to put more effort into getting the timing right which removed negative slack
2014-12-25 10:08:53 +00:00
Markus Fröschle
674406e4d3
formatting
2014-12-24 17:54:51 +00:00
Markus Fröschle
06688a9a02
got rid of BIT signal types
2014-12-24 17:07:51 +00:00
Markus Fröschle
5a923ddada
fixed formatting
2014-12-24 16:24:21 +00:00
Markus Fröschle
ef1807665e
removed UNSIGNED() conversions that are not needed anymore
2014-12-24 16:17:17 +00:00
Markus Fröschle
517599bc33
reenabled all modules
2014-12-24 16:11:12 +00:00
Markus Fröschle
e7e4fa4e75
added a little bus toggling to the test bench
2014-12-24 09:42:57 +00:00
Markus Fröschle
766d75a5d3
fixed pin assignments for renamed pins fb_cs_n[..]
2014-12-23 22:35:03 +00:00
Markus Fröschle
71db27849b
started implementing SAMSUNG's Verilog DDR model in VHDL
2014-12-23 22:30:23 +00:00
Markus Fröschle
63c0a2f167
added testbench files
2014-12-23 18:25:15 +00:00
Markus Fröschle
5eac75430e
renamed files, fixed testbench
2014-12-23 18:20:11 +00:00
Markus Fröschle
5cc8c3bbbf
fixed type inconistencies
2014-12-23 16:44:21 +00:00
Markus Fröschle
c197609be6
started "full fledged" testbench to analyze where fb_ta_n gets lost
2014-12-23 14:56:53 +00:00
Markus Fröschle
5c9253c6a9
implemented video_control_register as ALIAS
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fb_ta_n stuck at GND?
2014-12-23 11:21:56 +00:00
Markus Fröschle
a4835a305c
experimental
2014-12-23 08:59:40 +00:00
Markus Fröschle
1f50d16cfc
got rid of several unnecessary UNSIGNED() type conversions
2014-12-23 08:33:59 +00:00
Markus Fröschle
85ec4c726c
added io_register.vhd
2014-12-22 22:14:33 +00:00
Markus Fröschle
1612d52010
more formatting
2014-12-22 21:09:46 +00:00
Markus Fröschle
0f55615b45
converted more STD_LOGIC_VECTORs to UNSIGNED
2014-12-22 19:58:01 +00:00
Markus Fröschle
822f5a64d2
finished fixing formatting
2014-12-22 12:36:35 +00:00
Markus Fröschle
e2c69a75f6
changed all STD_LOGIC_VECTOR signals to UNSIGNED to ease calculations
2014-12-22 12:09:53 +00:00
Markus Fröschle
e0a1dfedcf
enabled flow analysis
2014-12-22 10:05:59 +00:00
Markus Fröschle
7963f9c8ae
fixed formatting
2014-12-22 08:50:22 +00:00
Markus Fröschle
7d98e35c50
fixed fifo_mw initialization
2014-12-22 08:40:35 +00:00
Markus Fröschle
4bb0527539
fifo_mw never got a value assigned - fixed for testbench, but still open for toplevel
2014-12-22 08:31:07 +00:00
Markus Fröschle
89f75bd4e8
fixed IRQn[x] to IRQ_n[x]
2014-12-22 06:42:16 +00:00
Markus Fröschle
2de4cceb00
fixed assignment to the new postfixed names
2014-12-22 06:37:25 +00:00
Markus Fröschle
5b64c3d6cf
fixed CLOCK_TICK generic
2014-12-22 06:09:10 +00:00
Markus Fröschle
3e769ceeb4
DDR2 simulation compiles in ModelSim
2014-12-22 05:57:17 +00:00
Markus Fröschle
1aab3c25d2
further extended testbench.
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Need to fix difference between clock ticks and TIME in original code
2014-12-21 20:40:51 +00:00
Markus Fröschle
9d7858a144
fixed missing data_in
2014-12-21 11:13:58 +00:00
Markus Fröschle
ff7faf4395
more formatting and corrections of testbench code
2014-12-21 10:55:49 +00:00
Markus Fröschle
04c32593cf
renamed RAM model
2014-12-21 08:33:17 +00:00
Markus Fröschle
db93ec6026
updated testbench (not functional yet)
2014-12-21 08:32:20 +00:00
Markus Fröschle
132f136d3a
relaxed timing and uncommented unneeded components in toplevel until timing issues are solved
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added lots of set_false_path statements to sort out timing problems
2014-12-20 12:26:32 +00:00
Markus Fröschle
9f288fc3d0
fixed formatting
2014-12-20 10:13:32 +00:00
Markus Fröschle
0c95b41b15
commented everything which is not needed to debug video system/DDR controller for now
2014-12-20 09:12:56 +00:00
Markus Fröschle
6d3b09f87b
fixed formatting
2014-12-20 09:05:03 +00:00
Markus Fröschle
fe27ee2e22
fixed formatting errors
2014-12-20 08:48:21 +00:00
Markus Fröschle
599b23bdcf
renamed directory hierarchy and toplevel entity
2014-12-20 08:34:53 +00:00
Markus Fröschle
e5f37977e1
renamed files
2014-12-20 08:26:37 +00:00
Markus Fröschle
c51e6c6098
reformatted
2014-12-20 08:25:53 +00:00
Markus Fröschle
cbff11f5d8
renamed files
2014-12-20 08:22:10 +00:00
Markus Fröschle
91ea8fc622
reformatted
2014-12-20 01:21:36 +00:00
Markus Fröschle
c81fc7e7e9
fixed comments
2014-12-16 20:33:51 +00:00
David Gálvez
a40831e6b7
Delete USB directories and the sorce code from the repository.
...
Here is not the place for this source code, it's not related directly with
the project. They were my firsts experiments with USB, it's very outdated too.
2014-11-28 10:25:52 +00:00
Markus Fröschle
798c5b839d
improved error handling
2014-11-24 16:12:35 +00:00
