fixed a few more problems resulting from changing libraries

vhdl/backend/Altera/Firebee/firebee.qsf

@@ -673,4 +673,6 @@ set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/Firebee_V1_pk
 set_global_assignment -name QIP_FILE ../../../rtl/vhdl/Firebee_V1/altpll_reconfig1.qip
 set_global_assignment -name VHDL_FILE ../../../testbenches/ddr_ram_model.vhd
 set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS OFF
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC OFF
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd

@@ -65,19 +65,23 @@ entity DDR_CTRL_V1 is
 		DDRCLK0         : in std_logic;
 		CLK_33M         : in std_logic;
 		FIFO_MW         : in std_logic_vector(8 downto 0);
-		VA              : out std_logic_vector(12 downto 0);
+		
-		VWEn            : out std_logic;
+		VA              : out std_logic_vector(12 downto 0);		-- video Adress bus at the DDR chips
-		VRASn           : out std_logic;
+		VWEn            : out std_logic;									-- video memory write enable
-		VCSn            : out std_logic;
+		VRASn           : out std_logic;									-- video memory RAS
-		VCKE            : out std_logic;
+		VCSn            : out std_logic;									-- video memory chip select
-		VCASn           : out std_logic;
+		VCKE            : out std_logic;									-- video memory clock enable
+		VCASn           : out std_logic;									-- video memory CAS
+		
 		FB_LE           : out std_logic_vector(3 downto 0);
 		FB_VDOE         : out std_logic_vector(3 downto 0);
+		
 		SR_FIFO_WRE     : out std_logic;
 		SR_DDR_FB       : out std_logic;
 		SR_DDR_WR       : out std_logic;
 		SR_DDRWR_D_SEL  : out std_logic;
 		SR_VDMP         : out std_logic_vector(7 downto 0);
+		
 		VIDEO_DDR_TA    : out std_logic;
 		SR_BLITTER_DACK : out std_logic;
 		BA              : out std_logic_vector(1 downto 0);
@@ -92,9 +96,9 @@ end entity DDR_CTRL_V1;
 
 architecture BEHAVIOUR of DDR_CTRL_V1 is
 	-- FIFO WATER MARK:
-	constant FIFO_LWM : std_logic_vector(8 downto 0) := "000000000";
+	constant FIFO_LWM : integer := 0;		-- low water mark
-	constant FIFO_MWM : std_logic_vector(8 downto 0) := "011001000"; -- 200.
+	constant FIFO_MWM : integer := 200;		-- medium water mark
-	constant FIFO_HWM : std_logic_vector(8 downto 0) := "111110100"; -- 500.
+	constant FIFO_HWM : integer := 500;		-- high water mark
 	
 	type ACCESS_WIDTH_TYPE is (LONG, WORD, BYTE);
 	type DDR_ACCESS_TYPE is (CPU, FIFO, BLITTER, NONE);
@@ -146,7 +150,7 @@ architecture BEHAVIOUR of DDR_CTRL_V1 is
 	signal STOP             : std_logic;
 	signal FIFO_BANK_OK     : std_logic;
 	signal DDR_REFRESH_ON   : std_logic;
-	signal DDR_REFRESH_CNT  : unsigned(10 downto 0);
+	signal DDR_REFRESH_CNT  : unsigned(10 downto 0) := "00000000000";
 	signal DDR_REFRESH_REQ  : std_logic;
 	signal DDR_REFRESH_SIG  : unsigned(3 downto 0);
 	signal REFRESH_TIME     : std_logic;
@@ -197,7 +201,7 @@ begin
 	------------------------------------ CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) ---------------------------------------------------------------------
 	FBCTRL_REG: process
 	begin
-		wait until CLK_MAIN = '1' and CLK_MAIN' event;
+		wait until rising_edge(CLK_MAIN);
 		FB_REGDDR <= FB_REGDDR_NEXT;
 	end process FBCTRL_REG;
     
@@ -212,18 +216,21 @@ begin
 				else
 					FB_REGDDR_NEXT <= FR_WAIT;
 				end if;
+			
 			when FR_S0 =>
 				if DDR_CS = '1' and ACCESS_WIDTH = LONG then
 					FB_REGDDR_NEXT <= FR_S1;
 				else
 					FB_REGDDR_NEXT <= FR_WAIT; 
 				end if;
+			
 			when FR_S1 => 
 				if DDR_CS = '1' then
 					FB_REGDDR_NEXT <= FR_S2;
 				else
 					FB_REGDDR_NEXT <= FR_WAIT; 
 				end if;
+			
 			when FR_S2 => 
 				if DDR_CS = '1' and BUS_CYC = '0' and ACCESS_WIDTH = LONG and FB_WRn = '0' then -- Eventually wait during long word access.
 					FB_REGDDR_NEXT <= FR_S2;
@@ -232,6 +239,7 @@ begin
 				else
 					FB_REGDDR_NEXT <= FR_WAIT;
 				end if;
+	
 			when FR_S3 => 
 				FB_REGDDR_NEXT <= FR_WAIT;
 		end case;
@@ -251,6 +259,7 @@ begin
 						'1' when FB_REGDDR = FR_S3 and DDR_CS = '1' else '0';
 
 	-- FB_VDOE # VIDEO_OE.
+
 	-- Write access for video data:
 	FB_VDOE(0) <= '1' when FB_REGDDR = FR_S0 and DDR_CS = '1' and FB_OEn = '0' and DDR_CONFIG = '0' and ACCESS_WIDTH = LONG else
 						'1' when FB_REGDDR = FR_S0 and DDR_CS = '1' and FB_OEn = '0' and DDR_CONFIG = '0' and ACCESS_WIDTH /= LONG and CLK_MAIN = '0' else '0';
@@ -265,7 +274,7 @@ begin
 	------------------------------------------------------ DDR State Machine --------------------------------------------------------------------------------------
 	DDR_STATE_REG: process
 	begin
-        wait until DDRCLK0 = '1' and DDRCLK0' event;
+		wait until rising_edge(DDRCLK0);
 		DDR_STATE <= DDR_NEXT_STATE;
 	end process DDR_STATE_REG;
 
@@ -285,10 +294,13 @@ begin
 				else
 					DDR_NEXT_STATE <= DS_T1; -- Synchronize.
 				end if;
+			
 			when DS_T2A => -- Fast access, in this case page is always not ok.
 				DDR_NEXT_STATE <= DS_T3;
+	
 			when DS_T2B =>
 				DDR_NEXT_STATE <= DS_T3;
+
 			when DS_T3 =>
 				if DDR_ACCESS = CPU and FB_WRn = '0' then
 					DDR_NEXT_STATE <= DS_T4W;
@@ -303,45 +315,57 @@ begin
 				else
 					DDR_NEXT_STATE <= DS_N8;
 				end if;
+            
 			-- Read:
 			when DS_T4R =>
 				DDR_NEXT_STATE <= DS_T5R;                
+
 			when DS_T5R =>
 				if FIFO_REQ = '1' and FIFO_BANK_OK = '1' then -- Insert FIFO read, when bank ok.
 					DDR_NEXT_STATE <= DS_T6F;
 				else    
 					DDR_NEXT_STATE <= DS_CB6;
 				end if;
+            
 			-- Write:            
 			when DS_T4W =>
 				DDR_NEXT_STATE <= DS_T5W;
+
 			when DS_T5W =>
 				DDR_NEXT_STATE <= DS_T6W;
+
 			when DS_T6W =>                               
 				DDR_NEXT_STATE <= DS_T7W;
+
 			when DS_T7W =>                               
 				DDR_NEXT_STATE <= DS_T8W;
+            
 			when DS_T8W =>                               
 				DDR_NEXT_STATE <= DS_T9W;
+            
 			when DS_T9W =>                               
 				if FIFO_REQ = '1' and FIFO_BANK_OK = '1' then
 					DDR_NEXT_STATE <= DS_T6F;
 				else
 					DDR_NEXT_STATE <= DS_CB6;
 				end if;
+            
 			-- FIFO read:
 			when DS_T4F =>
 				DDR_NEXT_STATE <= DS_T5F;                
+
 			when DS_T5F =>
 				if FIFO_REQ = '1' then
 					DDR_NEXT_STATE <= DS_T6F;
 				else
 					DDR_NEXT_STATE <= DS_CB6; -- Leave open.
 				end if;
+
 			when DS_T6F =>
 				DDR_NEXT_STATE <= DS_T7F;                                                                      
+            
 			when DS_T7F =>
-                if CPU_REQ = '1' and FIFO_MW > FIFO_LWM then    
+				if CPU_REQ = '1' and FIFO_MW > std_logic_vector(to_unsigned(FIFO_LWM, FIFO_MW'length)) then    
 					DDR_NEXT_STATE <= DS_CB8; -- Close bank.
 				elsif FIFO_REQ = '1' and VIDEO_ADR_CNT(7 downto 0) = x"FF" then -- New page?
 					DDR_NEXT_STATE <= DS_CB8; -- Close bank.
@@ -350,12 +374,14 @@ begin
 				else
 					DDR_NEXT_STATE <= DS_CB8; -- Close bank.
 				end if;
+
 			when DS_T8F =>
-                if FIFO_MW < FIFO_LWM then -- Emergency?
+				if FIFO_MW < std_logic_vector(to_unsigned(FIFO_LWM, FIFO_MW'length)) then -- Emergency?
 					DDR_NEXT_STATE <= DS_T5F; -- Yes!
 				else
 					DDR_NEXT_STATE <= DS_T9F;
 				end if;
+
 			when DS_T9F =>
 				if FIFO_REQ = '1' and VIDEO_ADR_CNT(7 downto 0) = x"FF"  then -- New page?
 					DDR_NEXT_STATE <= DS_CB6; -- Close bank.
@@ -364,34 +390,44 @@ begin
 				else
 					DDR_NEXT_STATE <= DS_CB6; -- Close bank.
 				end if;
+
 			when DS_T10F =>
 				if DDR_SEL = '1' and (FB_WRn = '1' or (FB_SIZE0 and  FB_SIZE1) = '0') and DATA_IN(13 downto 12) /= FIFO_BA then
 					DDR_NEXT_STATE <= DS_T3;
 				else
 					DDR_NEXT_STATE <= DS_T7F;
 				end if; 
+
 			-- Configuration cycles:
 			when DS_C2 =>
 				DDR_NEXT_STATE <= DS_C3;
+			
 			when DS_C3 =>
 				DDR_NEXT_STATE <= DS_C4;
+            
 			when DS_C4 =>
 				if CPU_REQ = '1' then
 					DDR_NEXT_STATE <= DS_C5;
 				else
 					DDR_NEXT_STATE <= DS_T1;
 				end if; 
+
 			when DS_C5 =>
 				DDR_NEXT_STATE <= DS_C6;
+			
 			when DS_C6 =>
 				DDR_NEXT_STATE <= DS_C7;
+            
 			when DS_C7 =>
 				DDR_NEXT_STATE <= DS_N8;
+
 			-- Close FIFO bank.
 			when DS_CB6 =>
 				DDR_NEXT_STATE <= DS_N7;
+            
 			when DS_CB8 =>
 				DDR_NEXT_STATE <= DS_T1;
+			
 			-- Refresh 70ns = ten cycles.
 			when DS_R2 =>
 				if DDR_REFRESH_SIG = x"9" then -- One cycle delay to close all banks.
@@ -399,21 +435,29 @@ begin
 				else
 					DDR_NEXT_STATE <= DS_R3;
 				end if;
+
 			when DS_R3 =>
 				DDR_NEXT_STATE <= DS_R4;
+
 			when DS_R4 =>
 				DDR_NEXT_STATE <= DS_R5;
+            
 			when DS_R5 =>
 				DDR_NEXT_STATE <= DS_R6;
+            
 			when DS_R6 =>
 				DDR_NEXT_STATE <= DS_N5;
+            
 			-- Loop:
 			when DS_N5 =>
 				DDR_NEXT_STATE <= DS_N6;
+
 			when DS_N6 =>
 				DDR_NEXT_STATE <= DS_N7;
+
 			when DS_N7 =>
 				DDR_NEXT_STATE <= DS_N8;
+            
 			when DS_N8 =>
 				DDR_NEXT_STATE <= DS_T1;
 		end case;
@@ -421,7 +465,8 @@ begin
 
     P_CLK0: process
     begin
-        wait until DDRCLK0 = '1' and DDRCLK0' event;
+		wait until rising_edge(DDRCLK0);
+		
 		-- Default assignments;
 		DDR_ACCESS <= NONE;
 		SR_FIFO_WRE_I <= '0';
@@ -429,15 +474,16 @@ begin
 		SR_DDR_WR <= '0';
 		SR_DDRWR_D_SEL <= '0';
 
-        MCS <= MCS(0) & CLK_MAIN;
+		MCS <= MCS(0) & CLK_MAIN;		-- sync on CLK_MAIN
+		
 		BLITTER_REQ <= BLITTER_SIG and not DDR_CONFIG and VCKE_I and not VCS_In;
 		FIFO_CLR_SYNC <= FIFO_CLR;
 		CLEAR_FIFO_CNT <= FIFO_CLR_SYNC or not FIFO_ACTIVE;
 		STOP <= FIFO_CLR_SYNC or CLEAR_FIFO_CNT;
 
-        if FIFO_MW < FIFO_MWM then
+		if FIFO_MW < std_logic_vector(to_unsigned(FIFO_MWM, FIFO_MW'length)) then
 			FIFO_REQ <= '1';
-        elsif FIFO_MW < FIFO_HWM and FIFO_REQ = '1' then
+		elsif FIFO_MW < std_logic_vector(to_unsigned(FIFO_HWM, FIFO_MW'length)) and FIFO_REQ = '1' then
 			FIFO_REQ <= '1';
 		elsif FIFO_ACTIVE = '1' and CLEAR_FIFO_CNT = '0' and STOP = '0' and DDR_CONFIG = '0' and VCKE_I = '1' and VCS_In = '0' then
 			FIFO_REQ <= '1';
@@ -534,8 +580,8 @@ begin
 				BA_S <= BLITTER_BA;
 			end if;
 		elsif DDR_STATE = DS_T4R then
--- mfro SR_DDR_FB <= CPU_AC;
+		-- mfro SR_DDR_FB <= CPU_AC;
--- mfro SR_BLITTER_DACK <= BLITTER_AC;
+		-- mfro SR_BLITTER_DACK <= BLITTER_AC;
 		elsif DDR_STATE = DS_T5R and FIFO_REQ = '1' and FIFO_BANK_OK = '1' then
 			VA_S(10) <= '0';
 			VA_S(9 downto 0) <= std_logic_vector(FIFO_COL_ADR);
@@ -544,7 +590,7 @@ begin
 			VA_S(10) <= '1';
 		elsif DDR_STATE = DS_T4W then
 			VA_S(10) <= VA_S(10);
--- mfro SR_BLITTER_DACK <= BLITTER_AC;
+			-- mfro ??? SR_BLITTER_DACK <= BLITTER_AC;
 		elsif DDR_STATE = DS_T5W then
 			VA_S(10) <= VA_S(10);
 			if DDR_ACCESS = CPU then
@@ -590,7 +636,7 @@ begin
 			VA_S(10) <= '0';
 		elsif DDR_STATE = DS_T6F then
 			SR_FIFO_WRE_I <= '1';
-        elsif DDR_STATE = DS_T7F and CPU_REQ = '1' and FIFO_MW > FIFO_LWM then
+		elsif DDR_STATE = DS_T7F and CPU_REQ = '1' and FIFO_MW > std_logic_vector(to_unsigned(FIFO_LWM, FIFO_MW'length)) then
 			VA_S(10) <= '1';
 		elsif DDR_STATE = DS_T7F and FIFO_REQ = '1' and VIDEO_ADR_CNT(7 downto 0) = x"FF" then
 			VA_S(10) <= '1';
@@ -633,7 +679,7 @@ begin
 
 	P_DDR_CS: process
 	begin
-        wait until CLK_MAIN = '1' and CLK_MAIN' event;
+		wait until rising_edge(CLK_MAIN);
 		if FB_ALE = '1' then
 			DDR_CS <= DDR_SEL;
 		end if;
@@ -641,7 +687,8 @@ begin
     
 	P_CPU_REQ: process
 	begin
-        wait until DDR_SYNC_66M = '1' and DDR_SYNC_66M' event;
+		wait until rising_edge(DDR_SYNC_66M);
+
 		if DDR_SEL = '1' and FB_WRn = '1' and DDR_CONFIG = '0' then
 			CPU_REQ <= '1';
 		elsif DDR_SEL = '1' and FB_SIZE1 = '0' and FB_SIZE1 = '0' and DDR_CONFIG = '0' then -- Start when not config and not long word access.
@@ -663,7 +710,7 @@ begin
 		-- Refresh: Always 8 at a time every 7.8us.
 		-- 7.8us x 8 = 62.4us = 2059 -> 2048 @ 33MHz.
 	begin
-        wait until CLK_33M = '1' and CLK_33M' event;
+		wait until rising_edge(CLK_33M);
 		DDR_REFRESH_CNT <= DDR_REFRESH_CNT + 1; -- Count 0 to 2047.
 	end process P_REFRESH;
 

vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd

@@ -569,10 +569,10 @@ begin
 	FALCON_IO_TA <= ACIA_CS or SNDCS or not DTACK_OUT_MFPn or PADDLE_CS or IDE_CF_TA or DMA_CS;
 	FB_TAn <= '0' when (BLITTER_TA or VIDEO_DDR_TA or VIDEO_MOD_TA or FALCON_IO_TA or DSP_TA or INT_HANDLER_TA)= '1' else '1';
 
-	ACIA_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 3) = x"1FF80" else '0'; -- FFC00-FFC07 FFC00/8
+	ACIA_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 3) & "000" = x"FFFC00" else '0';			-- FFFC00 - FFFC07
-	MFP_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 6) = x"3FE8" else '0'; -- FFA00/40
+	MFP_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 6) & "000000" = x"FFFA00" else '0';		-- FFFA00/40
-	PADDLE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 6) = x"3E48" else '0'; -- F9200-F923F
+	PADDLE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 6) & "000000"= x"FF9200" else '0';	-- FF9200-FF923F
-	SNDCS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 2) = x"3E200" else '0'; -- 8800-8803 F8800/4
+	SNDCS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 2) & "00" = x"FF8800" else '0'; 			-- FF8800-FF8803
 	SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1) = '0' else '0';
 	SNDIR_I <= '1' when SNDCS = '1' and FB_WRn = '0' else '0';
 
@@ -599,7 +599,7 @@ begin
 	HD_DD_OUT <= FDD_HD_DD when FBEE_CONF(29) = '0' else WDC_BSL0;
 	LDS <= '1' when MFP_CS = '1' or MFP_INTACK = '1' else '0';
 	ACIA_IRQn <= IRQ_KEYBDn and IRQ_MIDIn;
-	MFP_INTACK <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = x"20000" else '0'; 	--F002'0000
+	MFP_INTACK <= '1' when FB_CSn(2) = '0' and FB_ADR(19 downto 0) = x"20000" else '0'; 	--F002'0000
 	DINTn <= '0' when IDE_INT = '1' and FBEE_CONF(28) = '1' else
 				'0' when FD_INT = '1' else
 				'0' when SCSI_INT = '1' and FBEE_CONF(28) = '1' else '1';

vhdl/rtl/vhdl/Peripherals/ide_cf_sd_rom.vhd

@@ -91,17 +91,16 @@ entity IDE_CF_SD_ROM is
 end entity IDE_CF_SD_ROM;
 
 architecture BEHAVIOUR of IDE_CF_SD_ROM is
-type CMD_STATES is(	IDLE, T1, T6, T7);
+	type CMD_STATES is (IDLE, T1, T6, T7);
-signal CMD_STATE				: CMD_STATES;
-signal NEXT_CMD_STATE			: CMD_STATES;
 	
-signal ROM_CS					: STD_LOGIC;
+	signal CMD_STATE				: CMD_STATES;
-
+	signal NEXT_CMD_STATE		: CMD_STATES;
-signal IDE_CF_CS				: std_logic;
+	signal ROM_CS					: STD_LOGIC;
-signal NEXT_IDE_RDn				: std_logic;
+	signal IDE_CF_CS				: std_logic;
-signal NEXT_IDE_WRn				: std_logic;
+	signal NEXT_IDE_RDn			: std_logic;
+	signal NEXT_IDE_WRn			: std_logic;
 begin
-    ROM_CS <= '1' when FB_CS1n = '0' and FB_WRn = '1' and FB_ADR(19 downto 17) = x"5" else '0'; -- FFF A'0000/2'0000
+	ROM_CS <= '1' when FB_CS1n = '0' and FB_WRn = '1' and FB_ADR(19 downto 17) = "101" else '0'; -- FFF A'0000/2'0000
 
     RP_UDSn <= '0' when FB_WRn = '1' and FB_B0 = '1' and (ROM_CS = '1' or IDE_CF_CS = '1' or IDE_WRn = '0') else '1'; 
     RP_LDSn <= '0' when FB_WRn = '1' and FB_B1 = '1' and (ROM_CS = '1' or IDE_CF_CS = '1' or IDE_WRn = '0') else '1'; 

vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd

@@ -464,15 +464,15 @@ begin
     ST_CLUT <= '1' when ST_VIDEO = '1' and FBEE_VIDEO_ON = '0' and FALCON_CLUT = '0' and COLOR1_I = '0' else '0';
 
     -- Several (video)-registers:
-    CCR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "000000000000000000100000001" else '0';-- $404/4.
+    CCR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR = x"f0000404" else '0';	-- $F0000404 - Firebee video border color
-    SYS_CTR_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000000000011" else '0'; -- $8006/2.
+    SYS_CTR_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8008" else '0';	-- $FF8006 - Falcon monitor type register
-    VDL_LOF_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000100000111" else '0'; -- $820E/2.
+    VDL_LOF_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff820e" else '0'; -- $FF820E/F - line-width hi/lo.
-    VDL_LWD_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000100001000" else '0'; -- $8210/2.
+    VDL_LWD_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8210" else '0'; -- $FF8210/1 - vertical wrap hi/lo.
-    VDL_HHT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101000001" else '0'; -- $8282/2.
+    VDL_HHT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8282" else '0'; -- $FF8282/3 - horizontal hold timer hi/lo.
-    VDL_HBE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101000011" else '0'; -- $8286/2.
+    VDL_HBE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8286" else '0'; -- $FF8286/7 - horizontal border end hi/lo.
-    VDL_HDB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101000100" else '0'; -- $8288/2.
+    VDL_HDB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8288" else '0'; -- $FF8288/9 - horizontal display begin hi/lo.
-    VDL_HDE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101000101" else '0'; -- $828A/2.
+    VDL_HDE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff828a" else '0'; -- $FF828A/B - horizontal display end hi/lo.
-    VDL_HBB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101000010" else '0'; -- $8284/2.
+    VDL_HBB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8284" else '0'; -- $FF8284/5 - horizontal border begin hi/lo.
     VDL_HSS_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101000110" else '0'; -- $828C/2.
     VDL_VBE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101010011" else '0'; -- $82A6/2.
     VDL_VDB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101010100" else '0'; -- $82A8/2.

vhdl/rtl/vhdl/Video/Video_Top.vhd

@@ -284,7 +284,7 @@ begin
 	P_VIDEO_OUT: process
 	variable VIDEO_OUT  : std_logic_vector(23 downto 0);
 	begin
-        wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event;
+		wait until rising_edge(CLK_PIXEL_I);
 		case CC_SEL is
 			when "111" => VIDEO_OUT := CCR; -- Register type video.
 			when "110" => VIDEO_OUT := CC_24(23 downto 0); -- 3 byte FIFO type video.
@@ -364,7 +364,7 @@ begin
 
 	FIFO_DMUX: process
 	begin
-        wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event;
+		wait until rising_edge(CLK_PIXEL_I);
 		if FIFO_RDE = '1' and INTER_ZEI = '1' then
 			FIFO_D <= FIFO_D_OUT_128;
 		elsif FIFO_RDE = '1' then
@@ -375,11 +375,11 @@ begin
 	CLUT_SHIFTREGS: process
 		variable CLUT_SHIFTREG   : CLUT_SHIFTREG_TYPE;
 	begin
-        wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event;
+		wait until rising_edge(CLK_PIXEL_I);
 		CLUT_SHIFT_LOAD <= FIFO_RDE;
 		if CLUT_SHIFT_LOAD = '1' then
 			for i in 0 to 7 loop
-                CLUT_SHIFTREG(7 - i) := FIFO_D((i+1)*16 -1 downto i*16);
+				CLUT_SHIFTREG(7 - i) := FIFO_D((i + 1) * 16 - 1 downto i * 16);
 			end loop;
 		else
 			CLUT_SHIFTREG(7) := CLUT_SHIFTREG(7)(14 downto 0) & CLUT_ADR_A(0);
@@ -425,9 +425,9 @@ begin
     
 	DFF_CLK0: process
 	begin
-        wait until CLK_DDR0 = '1' and CLK_DDR0' event;
+		wait until rising_edge(CLK_DDR0);
 		VD_VZ_I <= VD_VZ_I(63 downto 0) & VDP_IN(63 downto 0);
-        --
+
 		if FIFO_WRE = '1' then
 			VDM_A <= VD_VZ_I;
 			VDM_B <= VDM_A;
@@ -442,7 +442,7 @@ begin
 
 	DFF_CLK3: process
 	begin
-        wait until CLK_DDR3 = '1' and CLK_DDR3' event;
+		wait until rising_edge(CLK_DDR3);
 		VDMP_I <= VDMP;
 	end process DFF_CLK3;
 
@@ -451,7 +451,7 @@ begin
 	SHIFT_CLK0: process
 		variable TMP : std_logic_vector(4 downto 0);
 	begin
-        wait until CLK_DDR0 = '1' and CLK_DDR0' event;
+		wait until rising_edge(CLK_DDR0);
 		TMP := SR_FIFO_WRE & TMP(4 downto 1);
 		FIFO_WRE <= TMP(0);
 	end process SHIFT_CLK0;