181 lines
7.6 KiB
VHDL
181 lines
7.6 KiB
VHDL
----------------------------------------------------------------------
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---- ----
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---- This file is part of the 'Firebee' project. ----
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---- http://acp.atari.org ----
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---- ----
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---- Description: ----
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---- This design unit provides peripheral logic for the 'Firebee' ----
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---- computer. It is optimized for the use of an Altera Cyclone ----
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---- FPGA (EP3C40F484). This IP-Core is based on the first edi- ----
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---- tion of the Firebee configware originally provided by Fredi ----
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---- Ashwanden and Wolfgang Förster. This release is in compa- ----
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---- rision to the first edition completely written in VHDL. ----
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---- ----
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---- Author(s): ----
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---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2012 Fredi Aschwanden, Wolfgang Förster ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU General Public ----
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---- License as published by the Free Software Foundation; either ----
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---- version 2 of the License, or (at your option) any later ----
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---- version. ----
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---- ----
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---- This program is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU General Public ----
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---- License along with this program; if not, write to the Free ----
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---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ----
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---- Boston, MA 02110-1301, USA. ----
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---- ----
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----------------------------------------------------------------------
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--
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-- Revision History
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--
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-- Revision 2K12B 20120801 WF
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-- Initial Release of the second edition.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity IDE_CF_SD_ROM is
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port(
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RESET : in std_logic;
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CLK_MAIN : in std_logic;
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FB_ADR : in std_logic_vector(19 downto 5);
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FB_CS1n : in std_logic;
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FB_WRn : in std_logic;
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FB_B0 : in std_logic;
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FB_B1 : in std_logic;
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FBEE_CONF : in std_logic_vector(31 downto 30);
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RP_UDSn : out std_logic;
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RP_LDSn : out std_logic;
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SD_CLK : out std_logic;
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SD_D0 : in std_logic;
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SD_D1 : in std_logic;
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SD_D2 : in std_logic;
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SD_CD_D3_IN : in std_logic;
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SD_CD_D3_OUT : out std_logic;
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SD_CD_D3_EN : out std_logic;
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SD_CMD_D1_IN : in std_logic;
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SD_CMD_D1_OUT : out std_logic;
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SD_CMD_D1_EN : out std_logic;
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SD_CARD_DETECT : in std_logic;
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SD_WP : in std_logic;
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IDE_RDY : in std_logic;
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IDE_WRn : buffer std_logic;
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IDE_RDn : out std_logic;
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IDE_CSn : out std_logic_vector(1 downto 0);
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IDE_DRQn : out std_logic;
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IDE_CF_TA : out std_logic;
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ROM4n : out std_logic;
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ROM3n : out std_logic;
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CF_WP : in std_logic;
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CF_CSn : out std_logic_vector(1 downto 0)
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);
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end entity IDE_CF_SD_ROM;
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architecture BEHAVIOUR of IDE_CF_SD_ROM is
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type CMD_STATES is (IDLE, T1, T6, T7);
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signal CMD_STATE : CMD_STATES;
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signal NEXT_CMD_STATE : CMD_STATES;
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signal ROM_CS : STD_LOGIC;
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signal IDE_CF_CS : std_logic;
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signal NEXT_IDE_RDn : std_logic;
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signal NEXT_IDE_WRn : std_logic;
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begin
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ROM_CS <= '1' when FB_CS1n = '0' and FB_WRn = '1' and FB_ADR(19 downto 17) = "101" else '0'; -- FFF A'0000/2'0000
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RP_UDSn <= '0' when FB_WRn = '1' and FB_B0 = '1' and (ROM_CS = '1' or IDE_CF_CS = '1' or IDE_WRn = '0') else '1';
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RP_LDSn <= '0' when FB_WRn = '1' and FB_B1 = '1' and (ROM_CS = '1' or IDE_CF_CS = '1' or IDE_WRn = '0') else '1';
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IDE_CF_CS <= '1' when FB_CS1n = '0' and FB_ADR(19 downto 7) = x"0" else '0'; -- FFF0'0000/80
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IDE_CSn(0) <= '0' when FBEE_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else -- FFF0'0040-FFF0'005F
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'0' when FBEE_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; -- FFFO'0000-FFF0'001F
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IDE_CSn(1) <= '0' when FBEE_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else -- FFF0'0060-FFF0'007F
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'0' when FBEE_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; -- FFFO'0020-FFF0'003F
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CF_CSn(0) <= '0' when FBEE_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else -- FFFO'0000-FFF0'001F
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'0' when FBEE_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; -- FFFO'0040-FFF0'005F
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CF_CSn(1) <= '0' when FBEE_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else -- FFF0'0020-FFF0'003F
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'0' when FBEE_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; -- FFFO'0060-FFF0'007F
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IDE_DRQn <= '0';
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IDE_CMD_REG: process(RESET, CLK_MAIN)
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begin
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if RESET = '1' then
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CMD_STATE <= IDLE;
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elsif rising_edge(CLK_MAIN) then
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CMD_STATE <= NEXT_CMD_STATE;
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IDE_RDn <= NEXT_IDE_RDn;
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IDE_WRn <= NEXT_IDE_WRn;
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end if;
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end process IDE_CMD_REG;
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IDE_CMD_DECODER: process(CMD_STATE, IDE_CF_CS, FB_WRn, IDE_RDY)
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begin
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case CMD_STATE is
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when IDLE =>
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IDE_CF_TA <= '0';
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if IDE_CF_CS = '1' then
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NEXT_IDE_RDn <= not FB_WRn;
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NEXT_IDE_WRn <= FB_WRn;
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NEXT_CMD_STATE <= T1;
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else
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NEXT_IDE_RDn <= '1';
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NEXT_IDE_WRn <= '1';
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NEXT_CMD_STATE <= IDLE;
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end if;
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when T1 =>
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IDE_CF_TA <= '0';
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NEXT_IDE_RDn <= not FB_WRn;
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NEXT_IDE_WRn <= FB_WRn;
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NEXT_CMD_STATE <= T6;
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when T6 =>
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IF IDE_RDY = '1' then
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IDE_CF_TA <= '1';
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NEXT_IDE_RDn <= '1';
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NEXT_IDE_WRn <= '1';
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NEXT_CMD_STATE <= T7;
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else
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IDE_CF_TA <= '0';
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NEXT_IDE_RDn <= not FB_WRn;
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NEXT_IDE_WRn <= FB_WRn;
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NEXT_CMD_STATE <= T6;
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end if;
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when T7 =>
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IDE_CF_TA <= '0';
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NEXT_IDE_RDn <= '1';
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NEXT_IDE_WRn <= '1';
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NEXT_CMD_STATE <= IDLE;
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end case;
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end process IDE_CMD_DECODER;
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SD_CLK <= '0';
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SD_CD_D3_OUT <= '0';
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SD_CD_D3_EN <= '0';
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SD_CMD_D1_OUT <= '0';
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SD_CMD_D1_EN <= '0';
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ROM4n <= '0' when FB_CS1n = '0' and FB_WRn = '1' and FB_ADR(19 downto 17) = x"5" and FB_ADR(16) = '0' else '1'; -- FFF A'0000/2'0000
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ROM3n <= '0' when FB_CS1n = '0' and FB_WRn = '1' and FB_ADR(19 downto 17) = x"5" and FB_ADR(16) = '1' else '1'; -- FFF A'0000/2'0000
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end architecture BEHAVIOUR;
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