From cf56eece6735b3b9a57aede378210d728f32c40b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 6 Aug 2014 19:49:32 +0000 Subject: [PATCH] fixed a few more problems resulting from changing libraries --- vhdl/backend/Altera/Firebee/firebee.qsf | 2 + vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd | 941 ++++++++++---------- vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd | 10 +- vhdl/rtl/vhdl/Peripherals/ide_cf_sd_rom.vhd | 19 +- vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd | 18 +- vhdl/rtl/vhdl/Video/Video_Top.vhd | 276 +++--- 6 files changed, 657 insertions(+), 609 deletions(-) diff --git a/vhdl/backend/Altera/Firebee/firebee.qsf b/vhdl/backend/Altera/Firebee/firebee.qsf index d7e7793..90e7ce2 100755 --- a/vhdl/backend/Altera/Firebee/firebee.qsf +++ b/vhdl/backend/Altera/Firebee/firebee.qsf @@ -673,4 +673,6 @@ set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/Firebee_V1_pk set_global_assignment -name QIP_FILE ../../../rtl/vhdl/Firebee_V1/altpll_reconfig1.qip set_global_assignment -name VHDL_FILE ../../../testbenches/ddr_ram_model.vhd set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS OFF +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC OFF set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd b/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd index 6878153..7b838a3 100644 --- a/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd +++ b/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd @@ -65,19 +65,23 @@ entity DDR_CTRL_V1 is DDRCLK0 : in std_logic; CLK_33M : in std_logic; FIFO_MW : in std_logic_vector(8 downto 0); - VA : out std_logic_vector(12 downto 0); - VWEn : out std_logic; - VRASn : out std_logic; - VCSn : out std_logic; - VCKE : out std_logic; - VCASn : out std_logic; + + VA : out std_logic_vector(12 downto 0); -- video Adress bus at the DDR chips + VWEn : out std_logic; -- video memory write enable + VRASn : out std_logic; -- video memory RAS + VCSn : out std_logic; -- video memory chip select + VCKE : out std_logic; -- video memory clock enable + VCASn : out std_logic; -- video memory CAS + FB_LE : out std_logic_vector(3 downto 0); FB_VDOE : out std_logic_vector(3 downto 0); + SR_FIFO_WRE : out std_logic; SR_DDR_FB : out std_logic; SR_DDR_WR : out std_logic; SR_DDRWR_D_SEL : out std_logic; SR_VDMP : out std_logic_vector(7 downto 0); + VIDEO_DDR_TA : out std_logic; SR_BLITTER_DACK : out std_logic; BA : out std_logic_vector(1 downto 0); @@ -92,9 +96,9 @@ end entity DDR_CTRL_V1; architecture BEHAVIOUR of DDR_CTRL_V1 is -- FIFO WATER MARK: - constant FIFO_LWM : std_logic_vector(8 downto 0) := "000000000"; - constant FIFO_MWM : std_logic_vector(8 downto 0) := "011001000"; -- 200. - constant FIFO_HWM : std_logic_vector(8 downto 0) := "111110100"; -- 500. + constant FIFO_LWM : integer := 0; -- low water mark + constant FIFO_MWM : integer := 200; -- medium water mark + constant FIFO_HWM : integer := 500; -- high water mark type ACCESS_WIDTH_TYPE is (LONG, WORD, BYTE); type DDR_ACCESS_TYPE is (CPU, FIFO, BLITTER, NONE); @@ -146,7 +150,7 @@ architecture BEHAVIOUR of DDR_CTRL_V1 is signal STOP : std_logic; signal FIFO_BANK_OK : std_logic; signal DDR_REFRESH_ON : std_logic; - signal DDR_REFRESH_CNT : unsigned(10 downto 0); + signal DDR_REFRESH_CNT : unsigned(10 downto 0) := "00000000000"; signal DDR_REFRESH_REQ : std_logic; signal DDR_REFRESH_SIG : unsigned(3 downto 0); signal REFRESH_TIME : std_logic; @@ -197,475 +201,518 @@ begin ------------------------------------ CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) --------------------------------------------------------------------- FBCTRL_REG: process begin - wait until CLK_MAIN = '1' and CLK_MAIN' event; + wait until rising_edge(CLK_MAIN); FB_REGDDR <= FB_REGDDR_NEXT; end process FBCTRL_REG; FBCTRL_DEC: process(FB_REGDDR, BUS_CYC, DDR_SEL, ACCESS_WIDTH, FB_WRn, DDR_CS) begin - case FB_REGDDR is - when FR_WAIT => - if BUS_CYC = '1' then - FB_REGDDR_NEXT <= FR_S0; - elsif DDR_SEL = '1' and ACCESS_WIDTH = LONG and FB_WRn = '0' then - FB_REGDDR_NEXT <= FR_S0; - else - FB_REGDDR_NEXT <= FR_WAIT; - end if; - when FR_S0 => - if DDR_CS = '1' and ACCESS_WIDTH = LONG then - FB_REGDDR_NEXT <= FR_S1; - else - FB_REGDDR_NEXT <= FR_WAIT; - end if; - when FR_S1 => - if DDR_CS = '1' then - FB_REGDDR_NEXT <= FR_S2; - else - FB_REGDDR_NEXT <= FR_WAIT; - end if; - when FR_S2 => - if DDR_CS = '1' and BUS_CYC = '0' and ACCESS_WIDTH = LONG and FB_WRn = '0' then -- Eventually wait during long word access. - FB_REGDDR_NEXT <= FR_S2; - elsif DDR_CS = '1' then - FB_REGDDR_NEXT <= FR_S3; - else - FB_REGDDR_NEXT <= FR_WAIT; - end if; - when FR_S3 => - FB_REGDDR_NEXT <= FR_WAIT; - end case; - end process FBCTRL_DEC; + case FB_REGDDR is + when FR_WAIT => + if BUS_CYC = '1' then + FB_REGDDR_NEXT <= FR_S0; + elsif DDR_SEL = '1' and ACCESS_WIDTH = LONG and FB_WRn = '0' then + FB_REGDDR_NEXT <= FR_S0; + else + FB_REGDDR_NEXT <= FR_WAIT; + end if; + + when FR_S0 => + if DDR_CS = '1' and ACCESS_WIDTH = LONG then + FB_REGDDR_NEXT <= FR_S1; + else + FB_REGDDR_NEXT <= FR_WAIT; + end if; + + when FR_S1 => + if DDR_CS = '1' then + FB_REGDDR_NEXT <= FR_S2; + else + FB_REGDDR_NEXT <= FR_WAIT; + end if; + + when FR_S2 => + if DDR_CS = '1' and BUS_CYC = '0' and ACCESS_WIDTH = LONG and FB_WRn = '0' then -- Eventually wait during long word access. + FB_REGDDR_NEXT <= FR_S2; + elsif DDR_CS = '1' then + FB_REGDDR_NEXT <= FR_S3; + else + FB_REGDDR_NEXT <= FR_WAIT; + end if; + + when FR_S3 => + FB_REGDDR_NEXT <= FR_WAIT; + end case; + end process FBCTRL_DEC; - -- Coldfire CPU access: - FB_LE(0) <= not FB_WRn when FB_REGDDR = FR_WAIT else - not FB_WRn when FB_REGDDR = FR_S0 and DDR_CS = '1' else '0'; - FB_LE(1) <= not FB_WRn when FB_REGDDR = FR_S1 and DDR_CS = '1' else '0'; - FB_LE(2) <= not FB_WRn when FB_REGDDR = FR_S2 and DDR_CS = '1' else '0'; - FB_LE(3) <= not FB_WRn when FB_REGDDR = FR_S3 and DDR_CS = '1' else '0'; + -- Coldfire CPU access: + FB_LE(0) <= not FB_WRn when FB_REGDDR = FR_WAIT else + not FB_WRn when FB_REGDDR = FR_S0 and DDR_CS = '1' else '0'; + FB_LE(1) <= not FB_WRn when FB_REGDDR = FR_S1 and DDR_CS = '1' else '0'; + FB_LE(2) <= not FB_WRn when FB_REGDDR = FR_S2 and DDR_CS = '1' else '0'; + FB_LE(3) <= not FB_WRn when FB_REGDDR = FR_S3 and DDR_CS = '1' else '0'; - -- Video data access: - VIDEO_DDR_TA <= '1' when FB_REGDDR = FR_S0 and DDR_CS = '1' else - '1' when FB_REGDDR = FR_S1 and DDR_CS = '1' else - '1' when FB_REGDDR = FR_S2 and FB_REGDDR_NEXT = FR_S3 else - '1' when FB_REGDDR = FR_S3 and DDR_CS = '1' else '0'; + -- Video data access: + VIDEO_DDR_TA <= '1' when FB_REGDDR = FR_S0 and DDR_CS = '1' else + '1' when FB_REGDDR = FR_S1 and DDR_CS = '1' else + '1' when FB_REGDDR = FR_S2 and FB_REGDDR_NEXT = FR_S3 else + '1' when FB_REGDDR = FR_S3 and DDR_CS = '1' else '0'; -- FB_VDOE # VIDEO_OE. - -- Write access for video data: - FB_VDOE(0) <= '1' when FB_REGDDR = FR_S0 and DDR_CS = '1' and FB_OEn = '0' and DDR_CONFIG = '0' and ACCESS_WIDTH = LONG else - '1' when FB_REGDDR = FR_S0 and DDR_CS = '1' and FB_OEn = '0' and DDR_CONFIG = '0' and ACCESS_WIDTH /= LONG and CLK_MAIN = '0' else '0'; - FB_VDOE(1) <= '1' when FB_REGDDR = FR_S1 and DDR_CS = '1' and FB_OEn = '0' and DDR_CONFIG = '0' else '0'; - FB_VDOE(2) <= '1' when FB_REGDDR = FR_S2 and DDR_CS = '1' and FB_OEn = '0' and DDR_CONFIG = '0' else '0'; - FB_VDOE(3) <= '1' when FB_REGDDR = FR_S3 and DDR_CS = '1' and FB_OEn = '0' and DDR_CONFIG = '0' and CLK_MAIN = '0' else '0'; - BUS_CYC_END <= '1' when FB_REGDDR = FR_S0 and DDR_CS = '1' and ACCESS_WIDTH /= LONG else - '1' when FB_REGDDR = FR_S3 and DDR_CS = '1' else '0'; + -- Write access for video data: + FB_VDOE(0) <= '1' when FB_REGDDR = FR_S0 and DDR_CS = '1' and FB_OEn = '0' and DDR_CONFIG = '0' and ACCESS_WIDTH = LONG else + '1' when FB_REGDDR = FR_S0 and DDR_CS = '1' and FB_OEn = '0' and DDR_CONFIG = '0' and ACCESS_WIDTH /= LONG and CLK_MAIN = '0' else '0'; + FB_VDOE(1) <= '1' when FB_REGDDR = FR_S1 and DDR_CS = '1' and FB_OEn = '0' and DDR_CONFIG = '0' else '0'; + FB_VDOE(2) <= '1' when FB_REGDDR = FR_S2 and DDR_CS = '1' and FB_OEn = '0' and DDR_CONFIG = '0' else '0'; + FB_VDOE(3) <= '1' when FB_REGDDR = FR_S3 and DDR_CS = '1' and FB_OEn = '0' and DDR_CONFIG = '0' and CLK_MAIN = '0' else '0'; - --------------------------------------------------------------------------------------------------------------------------------------------------------------- - ------------------------------------------------------ DDR State Machine -------------------------------------------------------------------------------------- - DDR_STATE_REG: process - begin - wait until DDRCLK0 = '1' and DDRCLK0' event; - DDR_STATE <= DDR_NEXT_STATE; - end process DDR_STATE_REG; + BUS_CYC_END <= '1' when FB_REGDDR = FR_S0 and DDR_CS = '1' and ACCESS_WIDTH /= LONG else + '1' when FB_REGDDR = FR_S3 and DDR_CS = '1' else '0'; - DDR_STATE_DEC: process(DDR_STATE, DDR_REFRESH_REQ, CPU_DDR_SYNC, DDR_CONFIG, FB_WRn, DDR_ACCESS, BLITTER_WR, FIFO_REQ, FIFO_BANK_OK, - FIFO_MW, CPU_REQ, VIDEO_ADR_CNT, DDR_SEL, FB_SIZE1, FB_SIZE0, DATA_IN, FIFO_BA, DDR_REFRESH_SIG) - begin - case DDR_STATE is - when DS_T1 => - if DDR_REFRESH_REQ = '1' then - DDR_NEXT_STATE <= DS_R2; - elsif CPU_DDR_SYNC = '1' and DDR_CONFIG = '1' then -- Synchronous start. - DDR_NEXT_STATE <= DS_C2; - elsif CPU_DDR_SYNC = '1' and CPU_REQ = '1' then -- Synchronous start. - DDR_NEXT_STATE <= DS_T2B; - elsif CPU_DDR_SYNC = '1' then - DDR_NEXT_STATE <= DS_T2A; - else - DDR_NEXT_STATE <= DS_T1; -- Synchronize. - end if; - when DS_T2A => -- Fast access, in this case page is always not ok. - DDR_NEXT_STATE <= DS_T3; - when DS_T2B => - DDR_NEXT_STATE <= DS_T3; - when DS_T3 => - if DDR_ACCESS = CPU and FB_WRn = '0' then - DDR_NEXT_STATE <= DS_T4W; - elsif DDR_ACCESS = BLITTER and BLITTER_WR = '1' then - DDR_NEXT_STATE <= DS_T4W; - elsif DDR_ACCESS = CPU then -- CPU? - DDR_NEXT_STATE <= DS_T4R; - elsif DDR_ACCESS = FIFO then -- FIFO? - DDR_NEXT_STATE <= DS_T4F; - elsif DDR_ACCESS = BLITTER then - DDR_NEXT_STATE <= DS_T4R; - else - DDR_NEXT_STATE <= DS_N8; - end if; - -- Read: - when DS_T4R => - DDR_NEXT_STATE <= DS_T5R; - when DS_T5R => - if FIFO_REQ = '1' and FIFO_BANK_OK = '1' then -- Insert FIFO read, when bank ok. - DDR_NEXT_STATE <= DS_T6F; - else - DDR_NEXT_STATE <= DS_CB6; - end if; - -- Write: - when DS_T4W => - DDR_NEXT_STATE <= DS_T5W; - when DS_T5W => - DDR_NEXT_STATE <= DS_T6W; - when DS_T6W => - DDR_NEXT_STATE <= DS_T7W; - when DS_T7W => - DDR_NEXT_STATE <= DS_T8W; - when DS_T8W => - DDR_NEXT_STATE <= DS_T9W; - when DS_T9W => - if FIFO_REQ = '1' and FIFO_BANK_OK = '1' then - DDR_NEXT_STATE <= DS_T6F; - else - DDR_NEXT_STATE <= DS_CB6; - end if; - -- FIFO read: - when DS_T4F => - DDR_NEXT_STATE <= DS_T5F; - when DS_T5F => - if FIFO_REQ = '1' then - DDR_NEXT_STATE <= DS_T6F; - else - DDR_NEXT_STATE <= DS_CB6; -- Leave open. - end if; - when DS_T6F => - DDR_NEXT_STATE <= DS_T7F; - when DS_T7F => - if CPU_REQ = '1' and FIFO_MW > FIFO_LWM then - DDR_NEXT_STATE <= DS_CB8; -- Close bank. - elsif FIFO_REQ = '1' and VIDEO_ADR_CNT(7 downto 0) = x"FF" then -- New page? - DDR_NEXT_STATE <= DS_CB8; -- Close bank. - elsif FIFO_REQ = '1' then - DDR_NEXT_STATE <= DS_T8F; - else - DDR_NEXT_STATE <= DS_CB8; -- Close bank. - end if; - when DS_T8F => - if FIFO_MW < FIFO_LWM then -- Emergency? - DDR_NEXT_STATE <= DS_T5F; -- Yes! - else - DDR_NEXT_STATE <= DS_T9F; - end if; - when DS_T9F => - if FIFO_REQ = '1' and VIDEO_ADR_CNT(7 downto 0) = x"FF" then -- New page? - DDR_NEXT_STATE <= DS_CB6; -- Close bank. - elsif FIFO_REQ = '1' then - DDR_NEXT_STATE <= DS_T10F; - else - DDR_NEXT_STATE <= DS_CB6; -- Close bank. - end if; - when DS_T10F => - if DDR_SEL = '1' and (FB_WRn = '1' or (FB_SIZE0 and FB_SIZE1) = '0') and DATA_IN(13 downto 12) /= FIFO_BA then - DDR_NEXT_STATE <= DS_T3; - else - DDR_NEXT_STATE <= DS_T7F; - end if; - -- Configuration cycles: - when DS_C2 => - DDR_NEXT_STATE <= DS_C3; - when DS_C3 => - DDR_NEXT_STATE <= DS_C4; - when DS_C4 => - if CPU_REQ = '1' then - DDR_NEXT_STATE <= DS_C5; - else - DDR_NEXT_STATE <= DS_T1; - end if; - when DS_C5 => - DDR_NEXT_STATE <= DS_C6; - when DS_C6 => - DDR_NEXT_STATE <= DS_C7; - when DS_C7 => - DDR_NEXT_STATE <= DS_N8; - -- Close FIFO bank. - when DS_CB6 => - DDR_NEXT_STATE <= DS_N7; - when DS_CB8 => - DDR_NEXT_STATE <= DS_T1; - -- Refresh 70ns = ten cycles. - when DS_R2 => - if DDR_REFRESH_SIG = x"9" then -- One cycle delay to close all banks. - DDR_NEXT_STATE <= DS_R4; - else - DDR_NEXT_STATE <= DS_R3; - end if; - when DS_R3 => - DDR_NEXT_STATE <= DS_R4; - when DS_R4 => - DDR_NEXT_STATE <= DS_R5; - when DS_R5 => - DDR_NEXT_STATE <= DS_R6; - when DS_R6 => - DDR_NEXT_STATE <= DS_N5; - -- Loop: - when DS_N5 => - DDR_NEXT_STATE <= DS_N6; - when DS_N6 => - DDR_NEXT_STATE <= DS_N7; - when DS_N7 => - DDR_NEXT_STATE <= DS_N8; - when DS_N8 => - DDR_NEXT_STATE <= DS_T1; - end case; - end process DDR_STATE_DEC; + --------------------------------------------------------------------------------------------------------------------------------------------------------------- + ------------------------------------------------------ DDR State Machine -------------------------------------------------------------------------------------- + DDR_STATE_REG: process + begin + wait until rising_edge(DDRCLK0); + DDR_STATE <= DDR_NEXT_STATE; + end process DDR_STATE_REG; + + DDR_STATE_DEC: process(DDR_STATE, DDR_REFRESH_REQ, CPU_DDR_SYNC, DDR_CONFIG, FB_WRn, DDR_ACCESS, BLITTER_WR, FIFO_REQ, FIFO_BANK_OK, + FIFO_MW, CPU_REQ, VIDEO_ADR_CNT, DDR_SEL, FB_SIZE1, FB_SIZE0, DATA_IN, FIFO_BA, DDR_REFRESH_SIG) + begin + case DDR_STATE is + when DS_T1 => + if DDR_REFRESH_REQ = '1' then + DDR_NEXT_STATE <= DS_R2; + elsif CPU_DDR_SYNC = '1' and DDR_CONFIG = '1' then -- Synchronous start. + DDR_NEXT_STATE <= DS_C2; + elsif CPU_DDR_SYNC = '1' and CPU_REQ = '1' then -- Synchronous start. + DDR_NEXT_STATE <= DS_T2B; + elsif CPU_DDR_SYNC = '1' then + DDR_NEXT_STATE <= DS_T2A; + else + DDR_NEXT_STATE <= DS_T1; -- Synchronize. + end if; + + when DS_T2A => -- Fast access, in this case page is always not ok. + DDR_NEXT_STATE <= DS_T3; + + when DS_T2B => + DDR_NEXT_STATE <= DS_T3; + + when DS_T3 => + if DDR_ACCESS = CPU and FB_WRn = '0' then + DDR_NEXT_STATE <= DS_T4W; + elsif DDR_ACCESS = BLITTER and BLITTER_WR = '1' then + DDR_NEXT_STATE <= DS_T4W; + elsif DDR_ACCESS = CPU then -- CPU? + DDR_NEXT_STATE <= DS_T4R; + elsif DDR_ACCESS = FIFO then -- FIFO? + DDR_NEXT_STATE <= DS_T4F; + elsif DDR_ACCESS = BLITTER then + DDR_NEXT_STATE <= DS_T4R; + else + DDR_NEXT_STATE <= DS_N8; + end if; + + -- Read: + when DS_T4R => + DDR_NEXT_STATE <= DS_T5R; + + when DS_T5R => + if FIFO_REQ = '1' and FIFO_BANK_OK = '1' then -- Insert FIFO read, when bank ok. + DDR_NEXT_STATE <= DS_T6F; + else + DDR_NEXT_STATE <= DS_CB6; + end if; + + -- Write: + when DS_T4W => + DDR_NEXT_STATE <= DS_T5W; + + when DS_T5W => + DDR_NEXT_STATE <= DS_T6W; + + when DS_T6W => + DDR_NEXT_STATE <= DS_T7W; + + when DS_T7W => + DDR_NEXT_STATE <= DS_T8W; + + when DS_T8W => + DDR_NEXT_STATE <= DS_T9W; + + when DS_T9W => + if FIFO_REQ = '1' and FIFO_BANK_OK = '1' then + DDR_NEXT_STATE <= DS_T6F; + else + DDR_NEXT_STATE <= DS_CB6; + end if; + + -- FIFO read: + when DS_T4F => + DDR_NEXT_STATE <= DS_T5F; + + when DS_T5F => + if FIFO_REQ = '1' then + DDR_NEXT_STATE <= DS_T6F; + else + DDR_NEXT_STATE <= DS_CB6; -- Leave open. + end if; + + when DS_T6F => + DDR_NEXT_STATE <= DS_T7F; + + when DS_T7F => + if CPU_REQ = '1' and FIFO_MW > std_logic_vector(to_unsigned(FIFO_LWM, FIFO_MW'length)) then + DDR_NEXT_STATE <= DS_CB8; -- Close bank. + elsif FIFO_REQ = '1' and VIDEO_ADR_CNT(7 downto 0) = x"FF" then -- New page? + DDR_NEXT_STATE <= DS_CB8; -- Close bank. + elsif FIFO_REQ = '1' then + DDR_NEXT_STATE <= DS_T8F; + else + DDR_NEXT_STATE <= DS_CB8; -- Close bank. + end if; + + when DS_T8F => + if FIFO_MW < std_logic_vector(to_unsigned(FIFO_LWM, FIFO_MW'length)) then -- Emergency? + DDR_NEXT_STATE <= DS_T5F; -- Yes! + else + DDR_NEXT_STATE <= DS_T9F; + end if; + + when DS_T9F => + if FIFO_REQ = '1' and VIDEO_ADR_CNT(7 downto 0) = x"FF" then -- New page? + DDR_NEXT_STATE <= DS_CB6; -- Close bank. + elsif FIFO_REQ = '1' then + DDR_NEXT_STATE <= DS_T10F; + else + DDR_NEXT_STATE <= DS_CB6; -- Close bank. + end if; + + when DS_T10F => + if DDR_SEL = '1' and (FB_WRn = '1' or (FB_SIZE0 and FB_SIZE1) = '0') and DATA_IN(13 downto 12) /= FIFO_BA then + DDR_NEXT_STATE <= DS_T3; + else + DDR_NEXT_STATE <= DS_T7F; + end if; + + -- Configuration cycles: + when DS_C2 => + DDR_NEXT_STATE <= DS_C3; + + when DS_C3 => + DDR_NEXT_STATE <= DS_C4; + + when DS_C4 => + if CPU_REQ = '1' then + DDR_NEXT_STATE <= DS_C5; + else + DDR_NEXT_STATE <= DS_T1; + end if; + + when DS_C5 => + DDR_NEXT_STATE <= DS_C6; + + when DS_C6 => + DDR_NEXT_STATE <= DS_C7; + + when DS_C7 => + DDR_NEXT_STATE <= DS_N8; + + -- Close FIFO bank. + when DS_CB6 => + DDR_NEXT_STATE <= DS_N7; + + when DS_CB8 => + DDR_NEXT_STATE <= DS_T1; + + -- Refresh 70ns = ten cycles. + when DS_R2 => + if DDR_REFRESH_SIG = x"9" then -- One cycle delay to close all banks. + DDR_NEXT_STATE <= DS_R4; + else + DDR_NEXT_STATE <= DS_R3; + end if; + + when DS_R3 => + DDR_NEXT_STATE <= DS_R4; + + when DS_R4 => + DDR_NEXT_STATE <= DS_R5; + + when DS_R5 => + DDR_NEXT_STATE <= DS_R6; + + when DS_R6 => + DDR_NEXT_STATE <= DS_N5; + + -- Loop: + when DS_N5 => + DDR_NEXT_STATE <= DS_N6; + + when DS_N6 => + DDR_NEXT_STATE <= DS_N7; + + when DS_N7 => + DDR_NEXT_STATE <= DS_N8; + + when DS_N8 => + DDR_NEXT_STATE <= DS_T1; + end case; + end process DDR_STATE_DEC; P_CLK0: process begin - wait until DDRCLK0 = '1' and DDRCLK0' event; - -- Default assignments; - DDR_ACCESS <= NONE; - SR_FIFO_WRE_I <= '0'; - SR_VDMP <= x"00"; - SR_DDR_WR <= '0'; - SR_DDRWR_D_SEL <= '0'; + wait until rising_edge(DDRCLK0); + + -- Default assignments; + DDR_ACCESS <= NONE; + SR_FIFO_WRE_I <= '0'; + SR_VDMP <= x"00"; + SR_DDR_WR <= '0'; + SR_DDRWR_D_SEL <= '0'; - MCS <= MCS(0) & CLK_MAIN; - BLITTER_REQ <= BLITTER_SIG and not DDR_CONFIG and VCKE_I and not VCS_In; - FIFO_CLR_SYNC <= FIFO_CLR; - CLEAR_FIFO_CNT <= FIFO_CLR_SYNC or not FIFO_ACTIVE; - STOP <= FIFO_CLR_SYNC or CLEAR_FIFO_CNT; + MCS <= MCS(0) & CLK_MAIN; -- sync on CLK_MAIN + + BLITTER_REQ <= BLITTER_SIG and not DDR_CONFIG and VCKE_I and not VCS_In; + FIFO_CLR_SYNC <= FIFO_CLR; + CLEAR_FIFO_CNT <= FIFO_CLR_SYNC or not FIFO_ACTIVE; + STOP <= FIFO_CLR_SYNC or CLEAR_FIFO_CNT; - if FIFO_MW < FIFO_MWM then - FIFO_REQ <= '1'; - elsif FIFO_MW < FIFO_HWM and FIFO_REQ = '1' then - FIFO_REQ <= '1'; - elsif FIFO_ACTIVE = '1' and CLEAR_FIFO_CNT = '0' and STOP = '0' and DDR_CONFIG = '0' and VCKE_I = '1' and VCS_In = '0' then - FIFO_REQ <= '1'; - else - FIFO_REQ <= '1'; - end if; + if FIFO_MW < std_logic_vector(to_unsigned(FIFO_MWM, FIFO_MW'length)) then + FIFO_REQ <= '1'; + elsif FIFO_MW < std_logic_vector(to_unsigned(FIFO_HWM, FIFO_MW'length)) and FIFO_REQ = '1' then + FIFO_REQ <= '1'; + elsif FIFO_ACTIVE = '1' and CLEAR_FIFO_CNT = '0' and STOP = '0' and DDR_CONFIG = '0' and VCKE_I = '1' and VCS_In = '0' then + FIFO_REQ <= '1'; + else + FIFO_REQ <= '1'; + end if; - if CLEAR_FIFO_CNT = '1' then - VIDEO_ADR_CNT <= unsigned(VIDEO_BASE_ADR); - elsif SR_FIFO_WRE_I = '1' then - VIDEO_ADR_CNT <= VIDEO_ADR_CNT + 1; - end if; + if CLEAR_FIFO_CNT = '1' then + VIDEO_ADR_CNT <= unsigned(VIDEO_BASE_ADR); + elsif SR_FIFO_WRE_I = '1' then + VIDEO_ADR_CNT <= VIDEO_ADR_CNT + 1; + end if; - if MCS = "10" and VCKE_I = '1' and VCS_In = '0' then - CPU_DDR_SYNC <= '1'; - else - CPU_DDR_SYNC <= '0'; - end if; + if MCS = "10" and VCKE_I = '1' and VCS_In = '0' then + CPU_DDR_SYNC <= '1'; + else + CPU_DDR_SYNC <= '0'; + end if; - if DDR_REFRESH_SIG /= x"0" and DDR_REFRESH_ON = '1' and DDR_CONFIG = '0' and REFRESH_TIME = '1' then - DDR_REFRESH_REQ <= '1'; - else - DDR_REFRESH_REQ <= '0'; - end if; + if DDR_REFRESH_SIG /= x"0" and DDR_REFRESH_ON = '1' and DDR_CONFIG = '0' and REFRESH_TIME = '1' then + DDR_REFRESH_REQ <= '1'; + else + DDR_REFRESH_REQ <= '0'; + end if; - if DDR_REFRESH_CNT = "00000000000" and CLK_MAIN = '0' then - REFRESH_TIME <= '1'; - else - REFRESH_TIME <= '0'; - end if; + if DDR_REFRESH_CNT = "00000000000" and CLK_MAIN = '0' then + REFRESH_TIME <= '1'; + else + REFRESH_TIME <= '0'; + end if; - if REFRESH_TIME = '1' and DDR_REFRESH_ON = '1' and DDR_CONFIG = '0' then - DDR_REFRESH_SIG <= x"9"; - elsif DDR_STATE = DS_R6 and DDR_REFRESH_ON = '1' and DDR_CONFIG = '0' then - DDR_REFRESH_SIG <= DDR_REFRESH_SIG - 1; - else - DDR_REFRESH_SIG <= x"0"; - end if; + if REFRESH_TIME = '1' and DDR_REFRESH_ON = '1' and DDR_CONFIG = '0' then + DDR_REFRESH_SIG <= x"9"; + elsif DDR_STATE = DS_R6 and DDR_REFRESH_ON = '1' and DDR_CONFIG = '0' then + DDR_REFRESH_SIG <= DDR_REFRESH_SIG - 1; + else + DDR_REFRESH_SIG <= x"0"; + end if; - if BUS_CYC_END = '1' then - BUS_CYC <= '0'; - elsif DDR_STATE = DS_T1 and CPU_DDR_SYNC = '1' and CPU_REQ = '1' then - BUS_CYC <= '1'; - elsif DDR_STATE = DS_T2A and DDR_SEL = '1' and FB_WRn = '0' then - BUS_CYC <= '1'; - elsif DDR_STATE = DS_T2A and DDR_SEL = '1' and (FB_SIZE0 = '0' or FB_SIZE1= '0') then - BUS_CYC <= '1'; - elsif DDR_STATE = DS_T2B then - BUS_CYC <= '1'; - elsif DDR_STATE = DS_T10F and FB_WRn = '0' and DATA_IN(13 downto 12) = FIFO_BA then - BUS_CYC <= '1'; - elsif DDR_STATE = DS_T10F and (FB_SIZE0 = '0' or FB_SIZE1= '0') and DATA_IN(13 downto 12) = FIFO_BA then - BUS_CYC <= '1'; - elsif DDR_STATE = DS_C3 then - BUS_CYC <= CPU_REQ; - end if; + if BUS_CYC_END = '1' then + BUS_CYC <= '0'; + elsif DDR_STATE = DS_T1 and CPU_DDR_SYNC = '1' and CPU_REQ = '1' then + BUS_CYC <= '1'; + elsif DDR_STATE = DS_T2A and DDR_SEL = '1' and FB_WRn = '0' then + BUS_CYC <= '1'; + elsif DDR_STATE = DS_T2A and DDR_SEL = '1' and (FB_SIZE0 = '0' or FB_SIZE1= '0') then + BUS_CYC <= '1'; + elsif DDR_STATE = DS_T2B then + BUS_CYC <= '1'; + elsif DDR_STATE = DS_T10F and FB_WRn = '0' and DATA_IN(13 downto 12) = FIFO_BA then + BUS_CYC <= '1'; + elsif DDR_STATE = DS_T10F and (FB_SIZE0 = '0' or FB_SIZE1= '0') and DATA_IN(13 downto 12) = FIFO_BA then + BUS_CYC <= '1'; + elsif DDR_STATE = DS_C3 then + BUS_CYC <= CPU_REQ; + end if; - if DDR_STATE = DS_T1 and CPU_DDR_SYNC = '1' and CPU_REQ = '1' then - VA_S <= CPU_ROW_ADR; - BA_S <= CPU_BA; - DDR_ACCESS <= CPU; - elsif DDR_STATE = DS_T1 and CPU_DDR_SYNC = '1' and FIFO_REQ = '1' then - VA_P <= FIFO_ROW_ADR; - BA_P <= FIFO_BA; - DDR_ACCESS <= FIFO; - elsif DDR_STATE = DS_T1 and CPU_DDR_SYNC = '1' and BLITTER_REQ = '0' then - VA_P <= BLITTER_ROW_ADR; - BA_P <= BLITTER_BA; - DDR_ACCESS <= BLITTER; - elsif DDR_STATE = DS_T2A and DDR_SEL = '1' and FB_WRn = '0' then - VA_S(10) <= '1'; - DDR_ACCESS <= CPU; - elsif DDR_STATE = DS_T2A and DDR_SEL = '1' and (FB_SIZE0 = '0' or FB_SIZE1= '0') then - VA_S(10) <= '1'; - DDR_ACCESS <= CPU; - elsif DDR_STATE = DS_T2A then - -- ?? mfro - VA_S(10) <= not (FIFO_ACTIVE and FIFO_REQ); - DDR_ACCESS <= FIFO; - FIFO_BANK_OK <= FIFO_ACTIVE and FIFO_REQ; - -- ?? mfro BLITTER_AC <= BLITTER_ACTIVE and BLITTER_REQ; - elsif DDR_STATE = DS_T2B then - FIFO_BANK_OK <= '0'; - elsif DDR_STATE = DS_T3 then - VA_S(10) <= VA_S(10); - if (FB_WRn = '0' and DDR_ACCESS = CPU) or (BLITTER_WR = '1' and DDR_ACCESS = BLITTER) then - VA_S(9 downto 0) <= CPU_COL_ADR; - BA_S <= CPU_BA; + if DDR_STATE = DS_T1 and CPU_DDR_SYNC = '1' and CPU_REQ = '1' then + VA_S <= CPU_ROW_ADR; + BA_S <= CPU_BA; + DDR_ACCESS <= CPU; + elsif DDR_STATE = DS_T1 and CPU_DDR_SYNC = '1' and FIFO_REQ = '1' then + VA_P <= FIFO_ROW_ADR; + BA_P <= FIFO_BA; + DDR_ACCESS <= FIFO; + elsif DDR_STATE = DS_T1 and CPU_DDR_SYNC = '1' and BLITTER_REQ = '0' then + VA_P <= BLITTER_ROW_ADR; + BA_P <= BLITTER_BA; + DDR_ACCESS <= BLITTER; + elsif DDR_STATE = DS_T2A and DDR_SEL = '1' and FB_WRn = '0' then + VA_S(10) <= '1'; + DDR_ACCESS <= CPU; + elsif DDR_STATE = DS_T2A and DDR_SEL = '1' and (FB_SIZE0 = '0' or FB_SIZE1= '0') then + VA_S(10) <= '1'; + DDR_ACCESS <= CPU; + elsif DDR_STATE = DS_T2A then + -- ?? mfro + VA_S(10) <= not (FIFO_ACTIVE and FIFO_REQ); + DDR_ACCESS <= FIFO; + FIFO_BANK_OK <= FIFO_ACTIVE and FIFO_REQ; + -- ?? mfro BLITTER_AC <= BLITTER_ACTIVE and BLITTER_REQ; + elsif DDR_STATE = DS_T2B then + FIFO_BANK_OK <= '0'; + elsif DDR_STATE = DS_T3 then + VA_S(10) <= VA_S(10); + if (FB_WRn = '0' and DDR_ACCESS = CPU) or (BLITTER_WR = '1' and DDR_ACCESS = BLITTER) then + VA_S(9 downto 0) <= CPU_COL_ADR; + BA_S <= CPU_BA; elsif FIFO_ACTIVE = '1' then VA_S(9 downto 0) <= std_logic_vector(FIFO_COL_ADR); BA_S <= FIFO_BA; elsif DDR_ACCESS = BLITTER then - VA_S(9 downto 0) <= BLITTER_COL_ADR; - BA_S <= BLITTER_BA; - end if; - elsif DDR_STATE = DS_T4R then --- mfro SR_DDR_FB <= CPU_AC; --- mfro SR_BLITTER_DACK <= BLITTER_AC; - elsif DDR_STATE = DS_T5R and FIFO_REQ = '1' and FIFO_BANK_OK = '1' then - VA_S(10) <= '0'; - VA_S(9 downto 0) <= std_logic_vector(FIFO_COL_ADR); - BA_S <= FIFO_BA; - elsif DDR_STATE = DS_T5R then - VA_S(10) <= '1'; - elsif DDR_STATE = DS_T4W then - VA_S(10) <= VA_S(10); --- mfro SR_BLITTER_DACK <= BLITTER_AC; - elsif DDR_STATE = DS_T5W then - VA_S(10) <= VA_S(10); - if DDR_ACCESS = CPU then - VA_S(9 downto 0) <= CPU_COL_ADR; - BA_S <= CPU_BA; - elsif DDR_ACCESS = BLITTER then - VA_S(9 downto 0) <= BLITTER_COL_ADR; - BA_S <= BLITTER_BA; - end if; - if DDR_ACCESS = BLITTER and FB_SIZE1 = '1' and FB_SIZE0 = '1' then - SR_VDMP <= BYTE_SEL & x"F"; - elsif DDR_ACCESS = BLITTER then - SR_VDMP <= BYTE_SEL & x"0"; - else - SR_VDMP <= BYTE_SEL & x"0"; - end if; - elsif DDR_STATE = DS_T6W then - SR_DDR_WR <= '1'; - SR_DDRWR_D_SEL <= '1'; - if DDR_ACCESS = BLITTER or (FB_SIZE1 = '1' and FB_SIZE0 = '1') then - SR_VDMP <= x"FF"; - else - SR_VDMP <= x"00"; - end if; - elsif DDR_STATE = DS_T7W then - SR_DDR_WR <= '1'; - SR_DDRWR_D_SEL <= '1'; - elsif DDR_STATE = DS_T9W and FIFO_REQ = '1' and FIFO_BANK_OK = '1' then - VA_S(10) <= '0'; - VA_S(9 downto 0) <= std_logic_vector(FIFO_COL_ADR); - BA_S <= FIFO_BA; - elsif DDR_STATE = DS_T9W then - VA_S(10) <= '0'; - elsif DDR_STATE = DS_T4F then - SR_FIFO_WRE_I <= '1'; - elsif DDR_STATE = DS_T5F and FIFO_REQ = '1' and VIDEO_ADR_CNT(7 downto 0) = x"FF" then - VA_S(10) <= '1'; - elsif DDR_STATE = DS_T5F and FIFO_REQ = '1' then - VA_S(10) <= '0'; - VA_S(9 downto 0) <= std_logic_vector(FIFO_COL_ADR + "100"); - BA_S <= FIFO_BA; - elsif DDR_STATE = DS_T5F then - VA_S(10) <= '0'; - elsif DDR_STATE = DS_T6F then - SR_FIFO_WRE_I <= '1'; - elsif DDR_STATE = DS_T7F and CPU_REQ = '1' and FIFO_MW > FIFO_LWM then - VA_S(10) <= '1'; - elsif DDR_STATE = DS_T7F and FIFO_REQ = '1' and VIDEO_ADR_CNT(7 downto 0) = x"FF" then - VA_S(10) <= '1'; - elsif DDR_STATE = DS_T7F and FIFO_REQ = '1' then - VA_S(10) <= '0'; - VA_S(9 downto 0) <= std_logic_vector(FIFO_COL_ADR + "100"); - BA_S <= FIFO_BA; - elsif DDR_STATE = DS_T7F then - VA_S(10) <= '1'; - elsif DDR_STATE = DS_T9F and FIFO_REQ = '1' and VIDEO_ADR_CNT(7 downto 0) = x"FF" then - VA_S(10) <= '1'; - elsif DDR_STATE = DS_T9F and FIFO_REQ = '1' then - VA_P(10) <= '0'; - VA_P(9 downto 0) <= std_logic_vector(FIFO_COL_ADR + "100"); - BA_P <= FIFO_BA; - elsif DDR_STATE = DS_T9F then - VA_S(10) <= '1'; - elsif DDR_STATE = DS_T10F and FB_WRn = '0' and DATA_IN(13 downto 12) = FIFO_BA then - VA_S(10) <= '1'; - DDR_ACCESS <= CPU; - elsif DDR_STATE = DS_T10F and (FB_SIZE0 = '0' or FB_SIZE1= '0') and DATA_IN(13 downto 12) = FIFO_BA then - VA_S(10) <= '1'; - DDR_ACCESS <= CPU; - elsif DDR_STATE = DS_T10F then - SR_FIFO_WRE_I <= '1'; - elsif DDR_STATE = DS_C6 then - VA_S <= DATA_IN(12 downto 0); - BA_S <= DATA_IN(14 downto 13); - elsif DDR_STATE = DS_CB6 then - FIFO_BANK_OK <= '0'; - elsif DDR_STATE = DS_CB8 then - FIFO_BANK_OK <= '0'; - elsif DDR_STATE = DS_R2 then - FIFO_BANK_OK <= '0'; - else - end if; - end process P_CLK0; + VA_S(9 downto 0) <= BLITTER_COL_ADR; + BA_S <= BLITTER_BA; + end if; + elsif DDR_STATE = DS_T4R then + -- mfro SR_DDR_FB <= CPU_AC; + -- mfro SR_BLITTER_DACK <= BLITTER_AC; + elsif DDR_STATE = DS_T5R and FIFO_REQ = '1' and FIFO_BANK_OK = '1' then + VA_S(10) <= '0'; + VA_S(9 downto 0) <= std_logic_vector(FIFO_COL_ADR); + BA_S <= FIFO_BA; + elsif DDR_STATE = DS_T5R then + VA_S(10) <= '1'; + elsif DDR_STATE = DS_T4W then + VA_S(10) <= VA_S(10); + -- mfro ??? SR_BLITTER_DACK <= BLITTER_AC; + elsif DDR_STATE = DS_T5W then + VA_S(10) <= VA_S(10); + if DDR_ACCESS = CPU then + VA_S(9 downto 0) <= CPU_COL_ADR; + BA_S <= CPU_BA; + elsif DDR_ACCESS = BLITTER then + VA_S(9 downto 0) <= BLITTER_COL_ADR; + BA_S <= BLITTER_BA; + end if; + if DDR_ACCESS = BLITTER and FB_SIZE1 = '1' and FB_SIZE0 = '1' then + SR_VDMP <= BYTE_SEL & x"F"; + elsif DDR_ACCESS = BLITTER then + SR_VDMP <= BYTE_SEL & x"0"; + else + SR_VDMP <= BYTE_SEL & x"0"; + end if; + elsif DDR_STATE = DS_T6W then + SR_DDR_WR <= '1'; + SR_DDRWR_D_SEL <= '1'; + if DDR_ACCESS = BLITTER or (FB_SIZE1 = '1' and FB_SIZE0 = '1') then + SR_VDMP <= x"FF"; + else + SR_VDMP <= x"00"; + end if; + elsif DDR_STATE = DS_T7W then + SR_DDR_WR <= '1'; + SR_DDRWR_D_SEL <= '1'; + elsif DDR_STATE = DS_T9W and FIFO_REQ = '1' and FIFO_BANK_OK = '1' then + VA_S(10) <= '0'; + VA_S(9 downto 0) <= std_logic_vector(FIFO_COL_ADR); + BA_S <= FIFO_BA; + elsif DDR_STATE = DS_T9W then + VA_S(10) <= '0'; + elsif DDR_STATE = DS_T4F then + SR_FIFO_WRE_I <= '1'; + elsif DDR_STATE = DS_T5F and FIFO_REQ = '1' and VIDEO_ADR_CNT(7 downto 0) = x"FF" then + VA_S(10) <= '1'; + elsif DDR_STATE = DS_T5F and FIFO_REQ = '1' then + VA_S(10) <= '0'; + VA_S(9 downto 0) <= std_logic_vector(FIFO_COL_ADR + "100"); + BA_S <= FIFO_BA; + elsif DDR_STATE = DS_T5F then + VA_S(10) <= '0'; + elsif DDR_STATE = DS_T6F then + SR_FIFO_WRE_I <= '1'; + elsif DDR_STATE = DS_T7F and CPU_REQ = '1' and FIFO_MW > std_logic_vector(to_unsigned(FIFO_LWM, FIFO_MW'length)) then + VA_S(10) <= '1'; + elsif DDR_STATE = DS_T7F and FIFO_REQ = '1' and VIDEO_ADR_CNT(7 downto 0) = x"FF" then + VA_S(10) <= '1'; + elsif DDR_STATE = DS_T7F and FIFO_REQ = '1' then + VA_S(10) <= '0'; + VA_S(9 downto 0) <= std_logic_vector(FIFO_COL_ADR + "100"); + BA_S <= FIFO_BA; + elsif DDR_STATE = DS_T7F then + VA_S(10) <= '1'; + elsif DDR_STATE = DS_T9F and FIFO_REQ = '1' and VIDEO_ADR_CNT(7 downto 0) = x"FF" then + VA_S(10) <= '1'; + elsif DDR_STATE = DS_T9F and FIFO_REQ = '1' then + VA_P(10) <= '0'; + VA_P(9 downto 0) <= std_logic_vector(FIFO_COL_ADR + "100"); + BA_P <= FIFO_BA; + elsif DDR_STATE = DS_T9F then + VA_S(10) <= '1'; + elsif DDR_STATE = DS_T10F and FB_WRn = '0' and DATA_IN(13 downto 12) = FIFO_BA then + VA_S(10) <= '1'; + DDR_ACCESS <= CPU; + elsif DDR_STATE = DS_T10F and (FB_SIZE0 = '0' or FB_SIZE1= '0') and DATA_IN(13 downto 12) = FIFO_BA then + VA_S(10) <= '1'; + DDR_ACCESS <= CPU; + elsif DDR_STATE = DS_T10F then + SR_FIFO_WRE_I <= '1'; + elsif DDR_STATE = DS_C6 then + VA_S <= DATA_IN(12 downto 0); + BA_S <= DATA_IN(14 downto 13); + elsif DDR_STATE = DS_CB6 then + FIFO_BANK_OK <= '0'; + elsif DDR_STATE = DS_CB8 then + FIFO_BANK_OK <= '0'; + elsif DDR_STATE = DS_R2 then + FIFO_BANK_OK <= '0'; + else + end if; + end process P_CLK0; - DDR_SEL <= '1' when FB_ALE = '1' and DATA_IN(31 downto 30) = "01" else '0'; + DDR_SEL <= '1' when FB_ALE = '1' and DATA_IN(31 downto 30) = "01" else '0'; - P_DDR_CS: process - begin - wait until CLK_MAIN = '1' and CLK_MAIN' event; - if FB_ALE = '1' then - DDR_CS <= DDR_SEL; - end if; - end process P_DDR_CS; + P_DDR_CS: process + begin + wait until rising_edge(CLK_MAIN); + if FB_ALE = '1' then + DDR_CS <= DDR_SEL; + end if; + end process P_DDR_CS; - P_CPU_REQ: process - begin - wait until DDR_SYNC_66M = '1' and DDR_SYNC_66M' event; - if DDR_SEL = '1' and FB_WRn = '1' and DDR_CONFIG = '0' then - CPU_REQ <= '1'; - elsif DDR_SEL = '1' and FB_SIZE1 = '0' and FB_SIZE1 = '0' and DDR_CONFIG = '0' then -- Start when not config and not long word access. - CPU_REQ <= '1'; - elsif DDR_SEL = '1' and FB_SIZE1 = '0' and FB_SIZE1 = '1' and DDR_CONFIG = '0' then -- Start when not config and not long word access. - CPU_REQ <= '1'; - elsif DDR_SEL = '1' and FB_SIZE1 = '1' and FB_SIZE1 = '0' and DDR_CONFIG = '0' then -- Start when not config and not long word access. - CPU_REQ <= '1'; - elsif DDR_SEL = '1' and DDR_CONFIG = '1' then -- Config, start immediately. - CPU_REQ <= '1'; - elsif FB_REGDDR = FR_S1 and FB_WRn = '0' then -- Long word write later. - CPU_REQ <= '1'; - elsif FB_REGDDR /= FR_S1 and FB_REGDDR /= FR_S3 and BUS_CYC_END = '0' and BUS_CYC = '0' then -- Halt, bus cycle in progress or ready. - CPU_REQ <= '0'; - end if; - end process P_CPU_REQ; + P_CPU_REQ: process + begin + wait until rising_edge(DDR_SYNC_66M); + + if DDR_SEL = '1' and FB_WRn = '1' and DDR_CONFIG = '0' then + CPU_REQ <= '1'; + elsif DDR_SEL = '1' and FB_SIZE1 = '0' and FB_SIZE1 = '0' and DDR_CONFIG = '0' then -- Start when not config and not long word access. + CPU_REQ <= '1'; + elsif DDR_SEL = '1' and FB_SIZE1 = '0' and FB_SIZE1 = '1' and DDR_CONFIG = '0' then -- Start when not config and not long word access. + CPU_REQ <= '1'; + elsif DDR_SEL = '1' and FB_SIZE1 = '1' and FB_SIZE1 = '0' and DDR_CONFIG = '0' then -- Start when not config and not long word access. + CPU_REQ <= '1'; + elsif DDR_SEL = '1' and DDR_CONFIG = '1' then -- Config, start immediately. + CPU_REQ <= '1'; + elsif FB_REGDDR = FR_S1 and FB_WRn = '0' then -- Long word write later. + CPU_REQ <= '1'; + elsif FB_REGDDR /= FR_S1 and FB_REGDDR /= FR_S3 and BUS_CYC_END = '0' and BUS_CYC = '0' then -- Halt, bus cycle in progress or ready. + CPU_REQ <= '0'; + end if; + end process P_CPU_REQ; - P_REFRESH: process - -- Refresh: Always 8 at a time every 7.8us. - -- 7.8us x 8 = 62.4us = 2059 -> 2048 @ 33MHz. - begin - wait until CLK_33M = '1' and CLK_33M' event; - DDR_REFRESH_CNT <= DDR_REFRESH_CNT + 1; -- Count 0 to 2047. - end process P_REFRESH; + P_REFRESH: process + -- Refresh: Always 8 at a time every 7.8us. + -- 7.8us x 8 = 62.4us = 2059 -> 2048 @ 33MHz. + begin + wait until rising_edge(CLK_33M); + DDR_REFRESH_CNT <= DDR_REFRESH_CNT + 1; -- Count 0 to 2047. + end process P_REFRESH; SR_FIFO_WRE <= SR_FIFO_WRE_I; diff --git a/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd b/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd index 432c3f7..b315202 100644 --- a/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd +++ b/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd @@ -569,10 +569,10 @@ begin FALCON_IO_TA <= ACIA_CS or SNDCS or not DTACK_OUT_MFPn or PADDLE_CS or IDE_CF_TA or DMA_CS; FB_TAn <= '0' when (BLITTER_TA or VIDEO_DDR_TA or VIDEO_MOD_TA or FALCON_IO_TA or DSP_TA or INT_HANDLER_TA)= '1' else '1'; - ACIA_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 3) = x"1FF80" else '0'; -- FFC00-FFC07 FFC00/8 - MFP_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 6) = x"3FE8" else '0'; -- FFA00/40 - PADDLE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 6) = x"3E48" else '0'; -- F9200-F923F - SNDCS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 2) = x"3E200" else '0'; -- 8800-8803 F8800/4 + ACIA_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 3) & "000" = x"FFFC00" else '0'; -- FFFC00 - FFFC07 + MFP_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 6) & "000000" = x"FFFA00" else '0'; -- FFFA00/40 + PADDLE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 6) & "000000"= x"FF9200" else '0'; -- FF9200-FF923F + SNDCS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 2) & "00" = x"FF8800" else '0'; -- FF8800-FF8803 SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1) = '0' else '0'; SNDIR_I <= '1' when SNDCS = '1' and FB_WRn = '0' else '0'; @@ -599,7 +599,7 @@ begin HD_DD_OUT <= FDD_HD_DD when FBEE_CONF(29) = '0' else WDC_BSL0; LDS <= '1' when MFP_CS = '1' or MFP_INTACK = '1' else '0'; ACIA_IRQn <= IRQ_KEYBDn and IRQ_MIDIn; - MFP_INTACK <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = x"20000" else '0'; --F002'0000 + MFP_INTACK <= '1' when FB_CSn(2) = '0' and FB_ADR(19 downto 0) = x"20000" else '0'; --F002'0000 DINTn <= '0' when IDE_INT = '1' and FBEE_CONF(28) = '1' else '0' when FD_INT = '1' else '0' when SCSI_INT = '1' and FBEE_CONF(28) = '1' else '1'; diff --git a/vhdl/rtl/vhdl/Peripherals/ide_cf_sd_rom.vhd b/vhdl/rtl/vhdl/Peripherals/ide_cf_sd_rom.vhd index 73a8beb..e642fcd 100644 --- a/vhdl/rtl/vhdl/Peripherals/ide_cf_sd_rom.vhd +++ b/vhdl/rtl/vhdl/Peripherals/ide_cf_sd_rom.vhd @@ -91,17 +91,16 @@ entity IDE_CF_SD_ROM is end entity IDE_CF_SD_ROM; architecture BEHAVIOUR of IDE_CF_SD_ROM is -type CMD_STATES is( IDLE, T1, T6, T7); -signal CMD_STATE : CMD_STATES; -signal NEXT_CMD_STATE : CMD_STATES; - -signal ROM_CS : STD_LOGIC; - -signal IDE_CF_CS : std_logic; -signal NEXT_IDE_RDn : std_logic; -signal NEXT_IDE_WRn : std_logic; + type CMD_STATES is (IDLE, T1, T6, T7); + + signal CMD_STATE : CMD_STATES; + signal NEXT_CMD_STATE : CMD_STATES; + signal ROM_CS : STD_LOGIC; + signal IDE_CF_CS : std_logic; + signal NEXT_IDE_RDn : std_logic; + signal NEXT_IDE_WRn : std_logic; begin - ROM_CS <= '1' when FB_CS1n = '0' and FB_WRn = '1' and FB_ADR(19 downto 17) = x"5" else '0'; -- FFF A'0000/2'0000 + ROM_CS <= '1' when FB_CS1n = '0' and FB_WRn = '1' and FB_ADR(19 downto 17) = "101" else '0'; -- FFF A'0000/2'0000 RP_UDSn <= '0' when FB_WRn = '1' and FB_B0 = '1' and (ROM_CS = '1' or IDE_CF_CS = '1' or IDE_WRn = '0') else '1'; RP_LDSn <= '0' when FB_WRn = '1' and FB_B1 = '1' and (ROM_CS = '1' or IDE_CF_CS = '1' or IDE_WRn = '0') else '1'; diff --git a/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd b/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd index 6fcac09..e02861e 100644 --- a/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd +++ b/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd @@ -464,15 +464,15 @@ begin ST_CLUT <= '1' when ST_VIDEO = '1' and FBEE_VIDEO_ON = '0' and FALCON_CLUT = '0' and COLOR1_I = '0' else '0'; -- Several (video)-registers: - CCR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "000000000000000000100000001" else '0';-- $404/4. - SYS_CTR_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000000000011" else '0'; -- $8006/2. - VDL_LOF_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000100000111" else '0'; -- $820E/2. - VDL_LWD_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000100001000" else '0'; -- $8210/2. - VDL_HHT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101000001" else '0'; -- $8282/2. - VDL_HBE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101000011" else '0'; -- $8286/2. - VDL_HDB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101000100" else '0'; -- $8288/2. - VDL_HDE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101000101" else '0'; -- $828A/2. - VDL_HBB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101000010" else '0'; -- $8284/2. + CCR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR = x"f0000404" else '0'; -- $F0000404 - Firebee video border color + SYS_CTR_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8008" else '0'; -- $FF8006 - Falcon monitor type register + VDL_LOF_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff820e" else '0'; -- $FF820E/F - line-width hi/lo. + VDL_LWD_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8210" else '0'; -- $FF8210/1 - vertical wrap hi/lo. + VDL_HHT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8282" else '0'; -- $FF8282/3 - horizontal hold timer hi/lo. + VDL_HBE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8286" else '0'; -- $FF8286/7 - horizontal border end hi/lo. + VDL_HDB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8288" else '0'; -- $FF8288/9 - horizontal display begin hi/lo. + VDL_HDE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff828a" else '0'; -- $FF828A/B - horizontal display end hi/lo. + VDL_HBB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 1) & '0' = x"ff8284" else '0'; -- $FF8284/5 - horizontal border begin hi/lo. VDL_HSS_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101000110" else '0'; -- $828C/2. VDL_VBE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101010011" else '0'; -- $82A6/2. VDL_VDB_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000101010100" else '0'; -- $82A8/2. diff --git a/vhdl/rtl/vhdl/Video/Video_Top.vhd b/vhdl/rtl/vhdl/Video/Video_Top.vhd index 8f14e61..0ab805e 100644 --- a/vhdl/rtl/vhdl/Video/Video_Top.vhd +++ b/vhdl/rtl/vhdl/Video/Video_Top.vhd @@ -281,23 +281,23 @@ begin CLUT_FBEE_B <= CLUT_FI(clut_fi_index)(7 downto 0); end process P_CLUT_ST_PX; - P_VIDEO_OUT: process - variable VIDEO_OUT : std_logic_vector(23 downto 0); - begin - wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event; - case CC_SEL is - when "111" => VIDEO_OUT := CCR; -- Register type video. - when "110" => VIDEO_OUT := CC_24(23 downto 0); -- 3 byte FIFO type video. - when "101" => VIDEO_OUT := CC_16; -- 2 byte FIFO type video. - when "100" => VIDEO_OUT := CLUT_FBEE_R & CLUT_FBEE_G & CLUT_FBEE_B; -- Firebee type video. - when "001" => VIDEO_OUT := CLUT_FA_R & "00" & CLUT_FA_G & "00" & CLUT_FA_B & "00"; -- Falcon type video. - when "000" => VIDEO_OUT := CLUT_ST_R & x"0" & CLUT_ST_G & x"0" & CLUT_ST_B & x"0"; -- ST type video. - when others => VIDEO_OUT := (others => '0'); - end case; - RED <= VIDEO_OUT(23 downto 16); - GREEN <= VIDEO_OUT(15 downto 8); - BLUE <= VIDEO_OUT(7 downto 0); - end process P_VIDEO_OUT; + P_VIDEO_OUT: process + variable VIDEO_OUT : std_logic_vector(23 downto 0); + begin + wait until rising_edge(CLK_PIXEL_I); + case CC_SEL is + when "111" => VIDEO_OUT := CCR; -- Register type video. + when "110" => VIDEO_OUT := CC_24(23 downto 0); -- 3 byte FIFO type video. + when "101" => VIDEO_OUT := CC_16; -- 2 byte FIFO type video. + when "100" => VIDEO_OUT := CLUT_FBEE_R & CLUT_FBEE_G & CLUT_FBEE_B; -- Firebee type video. + when "001" => VIDEO_OUT := CLUT_FA_R & "00" & CLUT_FA_G & "00" & CLUT_FA_B & "00"; -- Falcon type video. + when "000" => VIDEO_OUT := CLUT_ST_R & x"0" & CLUT_ST_G & x"0" & CLUT_ST_B & x"0"; -- ST type video. + when others => VIDEO_OUT := (others => '0'); + end case; + RED <= VIDEO_OUT(23 downto 16); + GREEN <= VIDEO_OUT(15 downto 8); + BLUE <= VIDEO_OUT(7 downto 0); + end process P_VIDEO_OUT; P_CC: process variable CC24_I : std_logic_vector(31 downto 0); @@ -307,10 +307,10 @@ begin wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event; case CLUT_ADR_MUX(1 downto 0) is when "11" => CC24_I := FIFO_D(31 downto 0); - when "10" => CC24_I := FIFO_D(63 downto 32); - when "01" => CC24_I := FIFO_D(95 downto 64); - when "00" => CC24_I := FIFO_D(127 downto 96); - when others => CC24_I := (others => 'Z'); + when "10" => CC24_I := FIFO_D(63 downto 32); + when "01" => CC24_I := FIFO_D(95 downto 64); + when "00" => CC24_I := FIFO_D(127 downto 96); + when others => CC24_I := (others => 'Z'); end case; -- CC_24 <= CC24_I; @@ -355,138 +355,138 @@ begin end case; end process P_CC; - CLUT_SHIFT_IN <= CLUT_ADR_A(6 downto 1) when COLOR4 = '0' and COLOR2 = '0' else - CLUT_ADR_A(7 downto 2) when COLOR4 = '0' and COLOR2 = '1' else - "00" & CLUT_ADR_A(7 downto 4) when COLOR4 = '1' and COLOR2 = '0' else "000000"; + CLUT_SHIFT_IN <= CLUT_ADR_A(6 downto 1) when COLOR4 = '0' and COLOR2 = '0' else + CLUT_ADR_A(7 downto 2) when COLOR4 = '0' and COLOR2 = '1' else + "00" & CLUT_ADR_A(7 downto 4) when COLOR4 = '1' and COLOR2 = '0' else "000000"; - FIFO_RD_REQ_128 <= '1' when FIFO_RDE = '1' and INTER_ZEI = '1' else '0'; - FIFO_RD_REQ_512 <= '1' when FIFO_RDE = '1' and INTER_ZEI = '0' else '0'; + FIFO_RD_REQ_128 <= '1' when FIFO_RDE = '1' and INTER_ZEI = '1' else '0'; + FIFO_RD_REQ_512 <= '1' when FIFO_RDE = '1' and INTER_ZEI = '0' else '0'; - FIFO_DMUX: process - begin - wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event; - if FIFO_RDE = '1' and INTER_ZEI = '1' then - FIFO_D <= FIFO_D_OUT_128; - elsif FIFO_RDE = '1' then - FIFO_D <= FIFO_D_OUT_512; - end if; - end process FIFO_DMUX; + FIFO_DMUX: process + begin + wait until rising_edge(CLK_PIXEL_I); + if FIFO_RDE = '1' and INTER_ZEI = '1' then + FIFO_D <= FIFO_D_OUT_128; + elsif FIFO_RDE = '1' then + FIFO_D <= FIFO_D_OUT_512; + end if; + end process FIFO_DMUX; - CLUT_SHIFTREGS: process - variable CLUT_SHIFTREG : CLUT_SHIFTREG_TYPE; - begin - wait until CLK_PIXEL_I = '1' and CLK_PIXEL_I' event; - CLUT_SHIFT_LOAD <= FIFO_RDE; - if CLUT_SHIFT_LOAD = '1' then - for i in 0 to 7 loop - CLUT_SHIFTREG(7 - i) := FIFO_D((i+1)*16 -1 downto i*16); - end loop; - else - CLUT_SHIFTREG(7) := CLUT_SHIFTREG(7)(14 downto 0) & CLUT_ADR_A(0); - CLUT_SHIFTREG(6) := CLUT_SHIFTREG(6)(14 downto 0) & CLUT_ADR_A(7); - CLUT_SHIFTREG(5) := CLUT_SHIFTREG(5)(14 downto 0) & CLUT_SHIFT_IN(5); - CLUT_SHIFTREG(4) := CLUT_SHIFTREG(4)(14 downto 0) & CLUT_SHIFT_IN(4); - CLUT_SHIFTREG(3) := CLUT_SHIFTREG(3)(14 downto 0) & CLUT_SHIFT_IN(3); - CLUT_SHIFTREG(2) := CLUT_SHIFTREG(2)(14 downto 0) & CLUT_SHIFT_IN(2); - CLUT_SHIFTREG(1) := CLUT_SHIFTREG(1)(14 downto 0) & CLUT_SHIFT_IN(1); - CLUT_SHIFTREG(0) := CLUT_SHIFTREG(0)(14 downto 0) & CLUT_SHIFT_IN(0); - end if; - -- - for i in 0 to 7 loop - CLUT_ADR_A(i) <= CLUT_SHIFTREG(i)(15); - end loop; - end process CLUT_SHIFTREGS; + CLUT_SHIFTREGS: process + variable CLUT_SHIFTREG : CLUT_SHIFTREG_TYPE; + begin + wait until rising_edge(CLK_PIXEL_I); + CLUT_SHIFT_LOAD <= FIFO_RDE; + if CLUT_SHIFT_LOAD = '1' then + for i in 0 to 7 loop + CLUT_SHIFTREG(7 - i) := FIFO_D((i + 1) * 16 - 1 downto i * 16); + end loop; + else + CLUT_SHIFTREG(7) := CLUT_SHIFTREG(7)(14 downto 0) & CLUT_ADR_A(0); + CLUT_SHIFTREG(6) := CLUT_SHIFTREG(6)(14 downto 0) & CLUT_ADR_A(7); + CLUT_SHIFTREG(5) := CLUT_SHIFTREG(5)(14 downto 0) & CLUT_SHIFT_IN(5); + CLUT_SHIFTREG(4) := CLUT_SHIFTREG(4)(14 downto 0) & CLUT_SHIFT_IN(4); + CLUT_SHIFTREG(3) := CLUT_SHIFTREG(3)(14 downto 0) & CLUT_SHIFT_IN(3); + CLUT_SHIFTREG(2) := CLUT_SHIFTREG(2)(14 downto 0) & CLUT_SHIFT_IN(2); + CLUT_SHIFTREG(1) := CLUT_SHIFTREG(1)(14 downto 0) & CLUT_SHIFT_IN(1); + CLUT_SHIFTREG(0) := CLUT_SHIFTREG(0)(14 downto 0) & CLUT_SHIFT_IN(0); + end if; + -- + for i in 0 to 7 loop + CLUT_ADR_A(i) <= CLUT_SHIFTREG(i)(15); + end loop; + end process CLUT_SHIFTREGS; - CLUT_ADR(7) <= CLUT_OFF(3) or (CLUT_ADR_A(7) and COLOR8); - CLUT_ADR(6) <= CLUT_OFF(2) or (CLUT_ADR_A(6) and COLOR8); - CLUT_ADR(5) <= CLUT_OFF(1) or (CLUT_ADR_A(5) and COLOR8); - CLUT_ADR(4) <= CLUT_OFF(0) or (CLUT_ADR_A(4) and COLOR8); - CLUT_ADR(3) <= CLUT_ADR_A(3) and (COLOR8 or COLOR4); - CLUT_ADR(2) <= CLUT_ADR_A(2) and (COLOR8 or COLOR4); - CLUT_ADR(1) <= CLUT_ADR_A(1) and (COLOR8 or COLOR4 or COLOR2); - CLUT_ADR(0) <= CLUT_ADR_A(0); + CLUT_ADR(7) <= CLUT_OFF(3) or (CLUT_ADR_A(7) and COLOR8); + CLUT_ADR(6) <= CLUT_OFF(2) or (CLUT_ADR_A(6) and COLOR8); + CLUT_ADR(5) <= CLUT_OFF(1) or (CLUT_ADR_A(5) and COLOR8); + CLUT_ADR(4) <= CLUT_OFF(0) or (CLUT_ADR_A(4) and COLOR8); + CLUT_ADR(3) <= CLUT_ADR_A(3) and (COLOR8 or COLOR4); + CLUT_ADR(2) <= CLUT_ADR_A(2) and (COLOR8 or COLOR4); + CLUT_ADR(1) <= CLUT_ADR_A(1) and (COLOR8 or COLOR4 or COLOR2); + CLUT_ADR(0) <= CLUT_ADR_A(0); - FB_AD_OUT <= x"0" & CLUT_ST_OUT & x"0000" when CLUT_ST_RD = '1' else - CLUT_FA_OUT(17 downto 12) & "00" & CLUT_FA_OUT(11 downto 6) & "00" & x"0000" when CLUT_FA_RDH = '1' else - x"00" & CLUT_FA_OUT(5 downto 0) & "00" & x"0000" when CLUT_FA_RDL = '1' else - x"00" & CLUT_FBEE_OUT when CLUT_FBEE_RD = '1' else - DATA_OUT_VIDEO_CTRL when DATA_EN_H_VIDEO_CTRL = '1' else -- Use upper word. - DATA_OUT_VIDEO_CTRL when DATA_EN_L_VIDEO_CTRL = '1' else (others => '0'); -- Use lower word. + FB_AD_OUT <= x"0" & CLUT_ST_OUT & x"0000" when CLUT_ST_RD = '1' else + CLUT_FA_OUT(17 downto 12) & "00" & CLUT_FA_OUT(11 downto 6) & "00" & x"0000" when CLUT_FA_RDH = '1' else + x"00" & CLUT_FA_OUT(5 downto 0) & "00" & x"0000" when CLUT_FA_RDL = '1' else + x"00" & CLUT_FBEE_OUT when CLUT_FBEE_RD = '1' else + DATA_OUT_VIDEO_CTRL when DATA_EN_H_VIDEO_CTRL = '1' else -- Use upper word. + DATA_OUT_VIDEO_CTRL when DATA_EN_L_VIDEO_CTRL = '1' else (others => '0'); -- Use lower word. - FB_AD_EN_31_16 <= '1' when CLUT_FBEE_RD = '1' else - '1' when CLUT_FA_RDH = '1' else - '1' when DATA_EN_H_VIDEO_CTRL = '1' else '0'; + FB_AD_EN_31_16 <= '1' when CLUT_FBEE_RD = '1' else + '1' when CLUT_FA_RDH = '1' else + '1' when DATA_EN_H_VIDEO_CTRL = '1' else '0'; - FB_AD_EN_15_0 <= '1' when CLUT_FBEE_RD = '1' else - '1' when CLUT_FA_RDL = '1' else - '1' when DATA_EN_L_VIDEO_CTRL = '1' else '0'; + FB_AD_EN_15_0 <= '1' when CLUT_FBEE_RD = '1' else + '1' when CLUT_FA_RDL = '1' else + '1' when DATA_EN_L_VIDEO_CTRL = '1' else '0'; - VD_VZ <= VD_VZ_I; + VD_VZ <= VD_VZ_I; - DFF_CLK0: process - begin - wait until CLK_DDR0 = '1' and CLK_DDR0' event; - VD_VZ_I <= VD_VZ_I(63 downto 0) & VDP_IN(63 downto 0); - -- - if FIFO_WRE = '1' then - VDM_A <= VD_VZ_I; - VDM_B <= VDM_A; - end if; - end process DFF_CLK0; + DFF_CLK0: process + begin + wait until rising_edge(CLK_DDR0); + VD_VZ_I <= VD_VZ_I(63 downto 0) & VDP_IN(63 downto 0); - DFF_CLK2: process - begin - wait until CLK_DDR2 = '1' and CLK_DDR2' event; - VDMP <= SR_VDMP; - end process DFF_CLK2; + if FIFO_WRE = '1' then + VDM_A <= VD_VZ_I; + VDM_B <= VDM_A; + end if; + end process DFF_CLK0; - DFF_CLK3: process - begin - wait until CLK_DDR3 = '1' and CLK_DDR3' event; - VDMP_I <= VDMP; - end process DFF_CLK3; + DFF_CLK2: process + begin + wait until CLK_DDR2 = '1' and CLK_DDR2' event; + VDMP <= SR_VDMP; + end process DFF_CLK2; - VDM <= VDMP_I(7 downto 4) when CLK_DDR3 = '1' else VDMP_I(3 downto 0); + DFF_CLK3: process + begin + wait until rising_edge(CLK_DDR3); + VDMP_I <= VDMP; + end process DFF_CLK3; + + VDM <= VDMP_I(7 downto 4) when CLK_DDR3 = '1' else VDMP_I(3 downto 0); - SHIFT_CLK0: process - variable TMP : std_logic_vector(4 downto 0); - begin - wait until CLK_DDR0 = '1' and CLK_DDR0' event; - TMP := SR_FIFO_WRE & TMP(4 downto 1); - FIFO_WRE <= TMP(0); - end process SHIFT_CLK0; + SHIFT_CLK0: process + variable TMP : std_logic_vector(4 downto 0); + begin + wait until rising_edge(CLK_DDR0); + TMP := SR_FIFO_WRE & TMP(4 downto 1); + FIFO_WRE <= TMP(0); + end process SHIFT_CLK0; - with VDM_SEL select - VDM_C <= VDM_B when x"0", - VDM_B(119 downto 0) & VDM_A(127 downto 120) when x"1", - VDM_B(111 downto 0) & VDM_A(127 downto 112) when x"2", - VDM_B(103 downto 0) & VDM_A(127 downto 104) when x"3", - VDM_B(95 downto 0) & VDM_A(127 downto 96) when x"4", - VDM_B(87 downto 0) & VDM_A(127 downto 88) when x"5", - VDM_B(79 downto 0) & VDM_A(127 downto 80) when x"6", - VDM_B(71 downto 0) & VDM_A(127 downto 72) when x"7", - VDM_B(63 downto 0) & VDM_A(127 downto 64) when x"8", - VDM_B(55 downto 0) & VDM_A(127 downto 56) when x"9", - VDM_B(47 downto 0) & VDM_A(127 downto 48) when x"A", - VDM_B(39 downto 0) & VDM_A(127 downto 40) when x"B", - VDM_B(31 downto 0) & VDM_A(127 downto 32) when x"C", - VDM_B(23 downto 0) & VDM_A(127 downto 24) when x"D", - VDM_B(15 downto 0) & VDM_A(127 downto 16) when x"E", - VDM_B(7 downto 0) & VDM_A(127 downto 8) when x"F", - (others => 'X') when others; + with VDM_SEL select + VDM_C <= VDM_B when x"0", + VDM_B(119 downto 0) & VDM_A(127 downto 120) when x"1", + VDM_B(111 downto 0) & VDM_A(127 downto 112) when x"2", + VDM_B(103 downto 0) & VDM_A(127 downto 104) when x"3", + VDM_B(95 downto 0) & VDM_A(127 downto 96) when x"4", + VDM_B(87 downto 0) & VDM_A(127 downto 88) when x"5", + VDM_B(79 downto 0) & VDM_A(127 downto 80) when x"6", + VDM_B(71 downto 0) & VDM_A(127 downto 72) when x"7", + VDM_B(63 downto 0) & VDM_A(127 downto 64) when x"8", + VDM_B(55 downto 0) & VDM_A(127 downto 56) when x"9", + VDM_B(47 downto 0) & VDM_A(127 downto 48) when x"A", + VDM_B(39 downto 0) & VDM_A(127 downto 40) when x"B", + VDM_B(31 downto 0) & VDM_A(127 downto 32) when x"C", + VDM_B(23 downto 0) & VDM_A(127 downto 24) when x"D", + VDM_B(15 downto 0) & VDM_A(127 downto 16) when x"E", + VDM_B(7 downto 0) & VDM_A(127 downto 8) when x"F", + (others => 'X') when others; - I_FIFO_DC0: lpm_fifo_dc0 - port map( - aclr => FIFO_CLR_I, - data => VDM_C, - rdclk => CLK_PIXEL_I, - rdreq => FIFO_RD_REQ_512, - wrclk => CLK_DDR0, - wrreq => FIFO_WRE, - q => FIFO_D_OUT_512, - --rdempty =>, -- Not used. - wrusedw => FIFO_MW - ); + I_FIFO_DC0: lpm_fifo_dc0 + port map( + aclr => FIFO_CLR_I, + data => VDM_C, + rdclk => CLK_PIXEL_I, + rdreq => FIFO_RD_REQ_512, + wrclk => CLK_DDR0, + wrreq => FIFO_WRE, + q => FIFO_D_OUT_512, + --rdempty =>, -- Not used. + wrusedw => FIFO_MW + ); I_FIFO_DZ: lpm_fifoDZ port map(