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more constraints

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This commit is contained in:
Markus Fröschle
2014-12-30 15:26:27 +00:00
parent 17b17a2263
commit b22e83e8b7
2 changed files with 22 additions and 5 deletions
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16
firebee1.qsf
View File

@@ -369,12 +369,12 @@ set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT FAST
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK
@@ -686,4 +686,14 @@ set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip
set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
set_global_assignment -name QIP_FILE altddio_out3.qip
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name ENABLE_DRC_SETTINGS ON
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk33m
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to main_clk
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

11
firebee1.sdc
View File

@@ -64,10 +64,16 @@ derive_clock_uncertainty
# Set Input Delay
#**************************************************************
# constrain DDR RAM
set_input_delay -clock [get_clocks {inst12|altpll_component|auto_generated|pll1|*}] 5ps [get_ports {VD*}]
#**************************************************************
# Set Output Delay
#**************************************************************
# constrain DDR RAM
set_output_delay -clock [get_clocks {inst12|altpll_component|auto_generated|pll1|*}] 5ps [get_ports {VD*}]
#**************************************************************
# Set Clock Groups
#**************************************************************
@@ -93,10 +99,11 @@ set_false_path -from [get_clocks {inst13|altpll_component|auto_generated|pll1|cl
set_false_path -from [get_clocks {main_clk}] -to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}]
set_false_path -from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {main_clk}]
set_false_path -from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {main_clk}]
set_false_path -from [get_clocks {main_clk}] -to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path -from [get_clocks {inst12|altpll_component|auto_generated|pll1|*}] -to [get_clocks {main_clk}]
set_false_path -from [get_clocks {main_clk}] -to [get_clocks {inst12|altpll_component|auto_generated|pll1|*}]
set_false_path -from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}]
set_false_path -from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path -from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}]