From b22e83e8b7e043cd438a23b22d467bf0cbd3111f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 30 Dec 2014 15:26:27 +0000 Subject: [PATCH] more constraints --- firebee1.qsf | 16 +++++++++++++--- firebee1.sdc | 11 +++++++++-- 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/firebee1.qsf b/firebee1.qsf index 0d07fc0..4e8dc73 100644 --- a/firebee1.qsf +++ b/firebee1.qsf @@ -369,12 +369,12 @@ set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "AUTO FIT" +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT FAST +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK @@ -686,4 +686,14 @@ set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name ENABLE_DRC_SETTINGS ON +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk33m +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to main_clk +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/firebee1.sdc b/firebee1.sdc index 84d5c06..2f6e864 100644 --- a/firebee1.sdc +++ b/firebee1.sdc @@ -64,10 +64,16 @@ derive_clock_uncertainty # Set Input Delay #************************************************************** +# constrain DDR RAM +set_input_delay -clock [get_clocks {inst12|altpll_component|auto_generated|pll1|*}] 5ps [get_ports {VD*}] + #************************************************************** # Set Output Delay #************************************************************** +# constrain DDR RAM +set_output_delay -clock [get_clocks {inst12|altpll_component|auto_generated|pll1|*}] 5ps [get_ports {VD*}] + #************************************************************** # Set Clock Groups #************************************************************** @@ -93,10 +99,11 @@ set_false_path -from [get_clocks {inst13|altpll_component|auto_generated|pll1|cl set_false_path -from [get_clocks {main_clk}] -to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] set_false_path -from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {main_clk}] -set_false_path -from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {main_clk}] -set_false_path -from [get_clocks {main_clk}] -to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] +set_false_path -from [get_clocks {inst12|altpll_component|auto_generated|pll1|*}] -to [get_clocks {main_clk}] +set_false_path -from [get_clocks {main_clk}] -to [get_clocks {inst12|altpll_component|auto_generated|pll1|*}] set_false_path -from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] + set_false_path -from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] set_false_path -from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}]