fixed fifo_mw initialization

2014-12-22 08:40:35 +00:00
parent 4bb0527539
commit 7d98e35c50
3 changed files with 3 additions and 3 deletions
--- a/vhdl/testbenches/ddr_ctlr_tb.vhd
+++ b/vhdl/testbenches/ddr_ctlr_tb.vhd
@@ -32,7 +32,7 @@ ARCHITECTURE beh OF ddr_ctlr_tb IS
    SIGNAL blitter_wr       : STD_LOGIC;
    SIGNAL ddrclk0          : STD_LOGIC;
    SIGNAL clk_33m          : STD_LOGIC := '0';
-    SIGNAL fifo_mw          : UNSIGNED (8 DOWNTO 0) := TO_UNSIGNED(300, 9);
+    SIGNAL fifo_mw          : UNSIGNED (8 DOWNTO 0) := (OTHERS => '0');
    SIGNAL va               : STD_LOGIC_VECTOR(12 DOWNTO 0);
    SIGNAL vwe_n            : STD_LOGIC;
    SIGNAL vras_n           : STD_LOGIC;