diff --git a/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd b/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd
index d9ad824..e0a14e5 100644
--- a/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd
+++ b/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd
@@ -70,7 +70,7 @@ ENTITY DDR_CTRL IS
         va              : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);               -- video Adress bus at the DDR chips
         vwe_n           : OUT STD_LOGIC;                                    -- video memory write enable
         vras_n          : OUT STD_LOGIC;                                    -- video memory RAS
-        vcs_n            : OUT STD_LOGIC;                                    -- video memory chip SELECT
+        vcs_n           : OUT STD_LOGIC;                                    -- video memory chip SELECT
         vcke            : OUT STD_LOGIC;                                    -- video memory clock enable
         vcas_n          : OUT STD_LOGIC;                                    -- video memory CAS
         
diff --git a/vhdl/rtl/vhdl/Firebee/Firebee.vhd b/vhdl/rtl/vhdl/Firebee/Firebee.vhd
index 6dc1961..c6f594d 100644
--- a/vhdl/rtl/vhdl/Firebee/Firebee.vhd
+++ b/vhdl/rtl/vhdl/Firebee/Firebee.vhd
@@ -407,7 +407,7 @@ ARCHITECTURE Structure of firebee is
     SIGNAL fdc_cs_n             : STD_LOGIC;
     SIGNAL fdc_wr_n             : STD_LOGIC;
     SIGNAL fifo_clr             : STD_LOGIC;
-    SIGNAL fifo_mw              : UNSIGNED (8 DOWNTO 0);
+    SIGNAL fifo_mw              : UNSIGNED (8 DOWNTO 0) := (OTHERS => '0');
     SIGNAL hd_dd_out            : STD_LOGIC;
     SIGNAL hsync_i              : STD_LOGIC;
     SIGNAL ide_cf_ta            : STD_LOGIC;
diff --git a/vhdl/testbenches/ddr_ctlr_tb.vhd b/vhdl/testbenches/ddr_ctlr_tb.vhd
index 546c1ab..d38eb0d 100644
--- a/vhdl/testbenches/ddr_ctlr_tb.vhd
+++ b/vhdl/testbenches/ddr_ctlr_tb.vhd
@@ -32,7 +32,7 @@ ARCHITECTURE beh OF ddr_ctlr_tb IS
     SIGNAL blitter_wr       : STD_LOGIC;
     SIGNAL ddrclk0          : STD_LOGIC;
     SIGNAL clk_33m          : STD_LOGIC := '0';
-    SIGNAL fifo_mw          : UNSIGNED (8 DOWNTO 0) := TO_UNSIGNED(300, 9);
+    SIGNAL fifo_mw          : UNSIGNED (8 DOWNTO 0) := (OTHERS => '0');
     SIGNAL va               : STD_LOGIC_VECTOR(12 DOWNTO 0);
     SIGNAL vwe_n            : STD_LOGIC;
     SIGNAL vras_n           : STD_LOGIC;