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fixed fifo_mw initialization

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This commit is contained in:
Markus Fröschle
2014-12-22 08:40:35 +00:00
parent 4bb0527539
commit 7d98e35c50
3 changed files with 3 additions and 3 deletions
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2
vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd
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@@ -70,7 +70,7 @@ ENTITY DDR_CTRL IS
va : OUT STD_LOGIC_VECTOR (12 DOWNTO 0); -- video Adress bus at the DDR chips
vwe_n : OUT STD_LOGIC; -- video memory write enable
vras_n : OUT STD_LOGIC; -- video memory RAS
vcs_n : OUT STD_LOGIC; -- video memory chip SELECT
vcs_n : OUT STD_LOGIC; -- video memory chip SELECT
vcke : OUT STD_LOGIC; -- video memory clock enable
vcas_n : OUT STD_LOGIC; -- video memory CAS

2
vhdl/rtl/vhdl/Firebee/Firebee.vhd
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@@ -407,7 +407,7 @@ ARCHITECTURE Structure of firebee is
SIGNAL fdc_cs_n : STD_LOGIC;
SIGNAL fdc_wr_n : STD_LOGIC;
SIGNAL fifo_clr : STD_LOGIC;
SIGNAL fifo_mw : UNSIGNED (8 DOWNTO 0);
SIGNAL fifo_mw : UNSIGNED (8 DOWNTO 0) := (OTHERS => '0');
SIGNAL hd_dd_out : STD_LOGIC;
SIGNAL hsync_i : STD_LOGIC;
SIGNAL ide_cf_ta : STD_LOGIC;