Firebee/FireBee_SVN
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

swapped out pci initialization into separate source file (still needs some testing bevore removing the original)

Browse Source
This commit is contained in:
Markus Fröschle
2013-10-21 10:03:00 +00:00
parent 33240aa13d
commit 22ee5f01c1
5 changed files with 45 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

41
BaS_gcc/sources/pci.c
View File

@@ -1,6 +1,25 @@
/*
* pci.c
*
* * Purpose: PCI configuration for the Coldfire builtin PCI bridge.
*
* Notes:
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* Created on: 08.01.2013
* Author: Markus Froeschle
*/
@@ -8,6 +27,7 @@
#include <MCF5475.h>
#include "pci.h"
#include "stdint.h"
#include "bas_printf.h"
void init_eport(void)
{
@@ -30,6 +50,7 @@ void init_xlbus_arbiter(void)
/* setup XL bus arbiter */
clock_ratio = (MCF_PCI_PCIGSCR >> 24) & 0x07;
if (clock_ratio == 4)
{
/* device errata 26: Flexbus hang up in 4:1 clock ratio */
@@ -40,6 +61,8 @@ void init_xlbus_arbiter(void)
void init_pci(void)
{
xprintf("initializing PCI bridge:");
/*
* assert /PCIRESET (reset cards on bus). FIXME: According to documentation,
* this should be done last during PCI initialization
@@ -65,7 +88,7 @@ void init_pci(void)
+ MCF_PCI_PCISCR_B /* bus master enable for controller */
+ MCF_PCI_PCISCR_MW; /* controller can generate memory write and invalidate command */
/* Configuration 1 Register PCICR1 */
/* Configuration 1 Register PCICR1, setup burst parameters */
MCF_PCI_PCICR1 = MCF_PCI_PCICR1_CACHELINESIZE(8) /* cache line size in units of DWORDs */
+ MCF_PCI_PCICR1_LATTIMER(32); /* 256 PCI clocks (?) latency */
/* Configuration 2 Register PCICR2 */
@@ -84,9 +107,10 @@ void init_pci(void)
/* Initiator Window 0 Base / Translation Address Register */
#ifdef SAME_CPU_PCI_MEM_ADDR
MCF_PCI_PCIIW0BTAR = (PCI_MEMORY_OFFSET + ((PCI_MEMORY_SIZE - 1) >> 8) & 0xFFFF0000) | (PCI_MEMORY_OFFSET >> 16 & 0xFFFF)
MCF_PCI_PCIIW0BTAR = (PCI_MEMORY_OFFSET + ((PCI_MEMORY_SIZE - 1) >> 8) & 0xFFFF0000) |
(PCI_MEMORY_OFFSET >> 16 & 0xFFFF)
#else
MCF_PCI_PCIIW0BTAR = PCI_MEMORY_OFFSET + ((PCI_MEMORY_SIZE - 1) >> 8) & 0xFFFF0000;
MCF_PCI_PCIIW0BTAR = PCI_MEMORY_OFFSET + (((PCI_MEMORY_SIZE - 1) >> 8) & 0xFFFF0000);
#endif /* SAME_CPU_PCI_MEM_ADDR */
/* Initiator Window 1 Base / Translation Address Register */
@@ -98,12 +122,11 @@ void init_pci(void)
MCF_PCI_PCIIWCR = MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE
+ MCF_PCI_PCIIWCR_WINCTRL1_IO;
/* reset PCI devices */
MCF_PCI_PCIGSCR &= ~MCF_PCI_PCIGSCR_PR;
xprintf("finished\r\n");
/* target zones */
}
void init(void)
{
init_eport();
init_xlbus_arbiter();
init_pci();
}