diff --git a/BaS_gcc/bas.lk.in b/BaS_gcc/bas.lk.in
index e733401..5693e76 100644
--- a/BaS_gcc/bas.lk.in
+++ b/BaS_gcc/bas.lk.in
@@ -21,6 +21,7 @@ SECTIONS
 		objs/illegal_instruction.o(.text)
 		objs/supervisor.o(.text)
 		objs/mmu.o(.text)		
+		objs/pci.o(.text)
 		
 		objs/BaS.o(.text)
 		objs/wait.o(.text)
diff --git a/BaS_gcc/include/pci.h b/BaS_gcc/include/pci.h
index 2a9b28f..6a42b98 100644
--- a/BaS_gcc/include/pci.h
+++ b/BaS_gcc/include/pci.h
@@ -1,10 +1,13 @@
 #ifndef _PCI_H_
 #define _PCI_H_
 
-#define PCI_MEMORY_OFFSET	0x80000000
-#define PCI_MEMORY_SIZE		0x40000000
-#define PCI_IO_OFFSET		0xB0000000
-#define PCI_IO_SIZE			0x10000000
+#define	 PCI_MEMORY_OFFSET	(0x80000000)
+#define	 PCI_MEMORY_SIZE	(0x40000000)
+#define	 PCI_IO_OFFSET		(0xD0000000)
+#define	 PCI_IO_SIZE		(0x10000000)
 
+extern void init_eport(void);
+extern void init_xlbus_arbiter(void);
+extern void init_pci(void);
 
 #endif /* _PCI_H_ */
diff --git a/BaS_gcc/sources/basflash.c b/BaS_gcc/sources/basflash.c
index 2c0bd51..db85e74 100644
--- a/BaS_gcc/sources/basflash.c
+++ b/BaS_gcc/sources/basflash.c
@@ -526,7 +526,7 @@ err_t srec_load(char *flash_filename)
 		{
 			/* next pass: copy data to destination */
 			xprintf("OK.\r\ncopy/flash data: ");
-			err = read_srecords(flash_filename, &start_address, &length, memcpy);
+			err = read_srecords(flash_filename, &start_address, &length, flash);
 			if (err == OK)
 			{
 				/* next pass: verify data */
diff --git a/BaS_gcc/sources/pci.c b/BaS_gcc/sources/pci.c
index 473387c..6007352 100644
--- a/BaS_gcc/sources/pci.c
+++ b/BaS_gcc/sources/pci.c
@@ -1,6 +1,25 @@
 /*
  * pci.c
  *
+ * * Purpose:		PCI configuration for the Coldfire builtin PCI bridge.
+ *
+ * Notes:
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
  *  Created on: 08.01.2013
  *      Author: Markus Froeschle
  */
@@ -8,6 +27,7 @@
 #include <MCF5475.h>
 #include "pci.h"
 #include "stdint.h"
+#include "bas_printf.h"
 
 void init_eport(void)
 {
@@ -30,6 +50,7 @@ void init_xlbus_arbiter(void)
 
 	/* setup XL bus arbiter */
 	clock_ratio = (MCF_PCI_PCIGSCR >> 24) & 0x07;
+
 	if (clock_ratio == 4)
 	{
 		/* device errata 26: Flexbus hang up in 4:1 clock ratio */
@@ -40,6 +61,8 @@ void init_xlbus_arbiter(void)
 
 void init_pci(void)
 {
+	xprintf("initializing PCI bridge:");
+
 	/*
 	 * assert /PCIRESET (reset cards on bus). FIXME: According to documentation,
 	 * this should be done last during PCI initialization
@@ -65,7 +88,7 @@ void init_pci(void)
 				+ MCF_PCI_PCISCR_B			/* bus master enable for controller */
 				+ MCF_PCI_PCISCR_MW;		/* controller can generate memory write and invalidate command */
 
-	/* Configuration 1 Register PCICR1 */
+	/* Configuration 1 Register PCICR1, setup burst parameters */
 	MCF_PCI_PCICR1 = MCF_PCI_PCICR1_CACHELINESIZE(8)	/* cache line size in units of DWORDs */
 				+ MCF_PCI_PCICR1_LATTIMER(32);			/* 256 PCI clocks (?) latency */
 	/* Configuration 2 Register PCICR2 */
@@ -84,9 +107,10 @@ void init_pci(void)
 
 	/* Initiator Window 0 Base / Translation Address Register */
 #ifdef SAME_CPU_PCI_MEM_ADDR
-	MCF_PCI_PCIIW0BTAR = (PCI_MEMORY_OFFSET + ((PCI_MEMORY_SIZE - 1) >> 8) & 0xFFFF0000) | (PCI_MEMORY_OFFSET >> 16 & 0xFFFF)
+	MCF_PCI_PCIIW0BTAR = (PCI_MEMORY_OFFSET + ((PCI_MEMORY_SIZE - 1) >> 8) & 0xFFFF0000) |
+							(PCI_MEMORY_OFFSET >> 16 & 0xFFFF)
 #else
-	MCF_PCI_PCIIW0BTAR = PCI_MEMORY_OFFSET + ((PCI_MEMORY_SIZE - 1) >> 8)	& 0xFFFF0000;
+	MCF_PCI_PCIIW0BTAR = PCI_MEMORY_OFFSET + (((PCI_MEMORY_SIZE - 1) >> 8) & 0xFFFF0000);
 #endif /* SAME_CPU_PCI_MEM_ADDR */
 
 	/* Initiator Window 1 Base / Translation Address Register */
@@ -98,12 +122,11 @@ void init_pci(void)
 	MCF_PCI_PCIIWCR = MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE
 			+ MCF_PCI_PCIIWCR_WINCTRL1_IO;
 
+	/* reset PCI devices */
+		MCF_PCI_PCIGSCR &= ~MCF_PCI_PCIGSCR_PR;
+
+		xprintf("finished\r\n");
+
 	/* target zones */
 }
 
-void init(void)
-{
-	init_eport();
-	init_xlbus_arbiter();
-	init_pci();
-}
diff --git a/BaS_gcc/sources/sysinit.c b/BaS_gcc/sources/sysinit.c
index b864b18..cbaffe1 100644
--- a/BaS_gcc/sources/sysinit.c
+++ b/BaS_gcc/sources/sysinit.c
@@ -30,6 +30,7 @@
 #include "startcf.h"
 #include "cache.h"
 #include "sysinit.h"
+#include "pci.h"
 #include "bas_printf.h"
 #include "bas_string.h"
 #include "bas_types.h"
@@ -481,12 +482,6 @@ void init_video_ddr(void) {
 	xprintf("finished\r\n");
 }
 
-
-#define	 PCI_MEMORY_OFFSET	(0x80000000)
-#define	 PCI_MEMORY_SIZE	(0x40000000)
-#define	 PCI_IO_OFFSET		(0xD0000000)
-#define	 PCI_IO_SIZE		(0x10000000)
-
 /*
  * INIT PCI
  */
@@ -990,7 +985,9 @@ void initialize_hardware(void) {
 	init_slt();
 	init_fbcs();
 	init_ddram();
-	init_PCI();
+	init_pci();
+	init_eport();
+	init_xlbus_arbiter();
 	init_fpga();
 	init_pll();
 	init_video_ddr();