133 lines
4.8 KiB
C
133 lines
4.8 KiB
C
/*
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* pci.c
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*
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* * Purpose: PCI configuration for the Coldfire builtin PCI bridge.
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*
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* Notes:
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*
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* This file is part of BaS_gcc.
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*
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* BaS_gcc is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* BaS_gcc is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
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*
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* Created on: 08.01.2013
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* Author: Markus Froeschle
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*/
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#include <MCF5475.h>
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#include "pci.h"
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#include "stdint.h"
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#include "bas_printf.h"
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void init_eport(void)
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{
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/* concigure IRQ1-7 pins on EPORT falling edge triggered */
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MCF_EPORT_EPPAR = MCF_EPORT_EPPAR_EPPA7(MCF_EPORT_EPPAR_FALLING) +
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MCF_EPORT_EPPAR_EPPA6(MCF_EPORT_EPPAR_FALLING) +
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MCF_EPORT_EPPAR_EPPA5(MCF_EPORT_EPPAR_FALLING) +
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MCF_EPORT_EPPAR_EPPA4(MCF_EPORT_EPPAR_FALLING) +
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MCF_EPORT_EPPAR_EPPA3(MCF_EPORT_EPPAR_FALLING) +
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MCF_EPORT_EPPAR_EPPA2(MCF_EPORT_EPPAR_FALLING) +
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MCF_EPORT_EPPAR_EPPA1(MCF_EPORT_EPPAR_FALLING);
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MCF_EPORT_EPDDR = 0; /* clear data direction register. All pins as input */
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MCF_EPORT_EPFR = 0; /* clear all EPORT interrupt flags */
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MCF_EPORT_EPIER = 0; /* disable all EPORT interrupts (for now) */
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}
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void init_xlbus_arbiter(void)
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{
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uint8_t clock_ratio;
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/* setup XL bus arbiter */
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clock_ratio = (MCF_PCI_PCIGSCR >> 24) & 0x07;
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if (clock_ratio == 4)
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{
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/* device errata 26: Flexbus hang up in 4:1 clock ratio */
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MCF_PCI_PCIGSCR |= 0x80000000; /* disable pipeline */
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}
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/* FIXME: Firetos (boot2.S, l. 719) looks pretty strange at this place - is this a typo? */
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}
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void init_pci(void)
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{
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xprintf("initializing PCI bridge:");
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/*
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* assert /PCIRESET (reset cards on bus). FIXME: According to documentation,
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* this should be done last during PCI initialization
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*/
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MCF_PCI_PCIGSCR = MCF_PCI_PCIGSCR_PR;
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/*
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* setup the PCI arbiter.
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*/
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/* PCI Arbiter Control Register (PACR) */
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MCF_PCIARB_PACR = MCF_PCIARB_PACR_INTMPRI /* internal master priority level high */
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+ MCF_PCIARB_PACR_EXTMPRI(0x1f) /* external master priority levels all high */
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+ MCF_PCIARB_PACR_INTMINTEN /* generate interrupt if internal master timeout */
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+ MCF_PCIARB_PACR_EXTMINTEN(0x1f); /* generate interrupt if external master timeout */
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/* configure all 5 PCI Bus Grant pins for PCI */
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MCF_PAD_PAR_PCIBG = 0x3ff;
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/* configure all 5 PCI Bus Request pins for PCI */
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MCF_PAD_PAR_PCIBR = 0x3ff;
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/* PCI Status/Command Register PCISCR */
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MCF_PCI_PCISCR = MCF_PCI_PCISCR_M /* recognize memory accesses */
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+ MCF_PCI_PCISCR_B /* bus master enable for controller */
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+ MCF_PCI_PCISCR_MW; /* controller can generate memory write and invalidate command */
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/* Configuration 1 Register PCICR1, setup burst parameters */
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MCF_PCI_PCICR1 = MCF_PCI_PCICR1_CACHELINESIZE(8) /* cache line size in units of DWORDs */
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+ MCF_PCI_PCICR1_LATTIMER(32); /* 256 PCI clocks (?) latency */
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/* Configuration 2 Register PCICR2 */
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MCF_PCI_PCICR2 = MCF_PCI_PCICR2_MINGNT(1) /* specifies how long the Coldfire processor retains bus ownership as master */
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+ MCF_PCI_PCICR2_MAXLAT(1); /* specifies (in units of 1/4 microseconds) how often the Coldfire */
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/* processor needs access to the bus as PCI master */
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/* Initiator Control Register: turn on error signaling */
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MCF_PCI_PCIICR = MCF_PCI_PCIICR_TAE + /* target abort enable: CPU generates an interrupt if target terminates a transaction */
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MCF_PCI_PCIICR_IAE /* the same for the initiator */
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/* + MCF_PCI_PCIICR_REE */ ; /* the same for retry errors */
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/* Global Status/Control Register */
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MCF_PCI_PCIGSCR |= MCF_PCI_PCIGSCR_SEE; /* generate interrupt if /PCISERR is asserted (PCI system error) */
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/* configure initiator windows */
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/* Initiator Window 0 Base / Translation Address Register */
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#ifdef SAME_CPU_PCI_MEM_ADDR
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MCF_PCI_PCIIW0BTAR = (PCI_MEMORY_OFFSET + ((PCI_MEMORY_SIZE - 1) >> 8) & 0xFFFF0000) |
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(PCI_MEMORY_OFFSET >> 16 & 0xFFFF)
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#else
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MCF_PCI_PCIIW0BTAR = PCI_MEMORY_OFFSET + (((PCI_MEMORY_SIZE - 1) >> 8) & 0xFFFF0000);
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#endif /* SAME_CPU_PCI_MEM_ADDR */
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/* Initiator Window 1 Base / Translation Address Register */
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MCF_PCI_PCIIW1BTAR = (PCI_IO_OFFSET + ((PCI_IO_SIZE - 1) >> 8)) & 0xFFFF0000;
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/* Initiator Window 2 Base / Translation Address Register */
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MCF_PCI_PCIIW2BTAR = 0L; /* not used */
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MCF_PCI_PCIIWCR = MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE
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+ MCF_PCI_PCIIWCR_WINCTRL1_IO;
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/* reset PCI devices */
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MCF_PCI_PCIGSCR &= ~MCF_PCI_PCIGSCR_PR;
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xprintf("finished\r\n");
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/* target zones */
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}
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