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finally fixed multiple drivers problem

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This commit is contained in:
Markus Fröschle
2016-07-28 11:48:10 +00:00
parent c6f8a7d4e8
commit f1a038e3a5
9 changed files with 760 additions and 907 deletions
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8
FPGA_Quartus_13.1/DSP/DSP.vhd
View File

@@ -49,7 +49,8 @@ ENTITY dsp IS
nSROE : OUT std_logic;
DSP_INT : OUT std_logic;
DSP_TA : OUT std_logic;
FB_AD : INOUT std_logic_vector(31 DOWNTO 0);
fb_ad_in : in std_logic_vector(31 downto 0);
fb_ad_out : out std_logic_vector(31 downto 0);
IO : INOUT std_logic_vector(17 DOWNTO 0);
SRD : INOUT std_logic_vector(15 DOWNTO 0)
);
@@ -72,6 +73,7 @@ BEGIN
DSP_INT <= '0';
DSP_TA <= '0';
IO(17 DOWNTO 0) <= FB_ADR(18 DOWNTO 1);
SRD(15 DOWNTO 0) <= FB_AD(31 DOWNTO 16) WHEN nFB_WR = '0' AND nSRCS = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= SRD(15 DOWNTO 0) WHEN nFB_OE = '0' AND nSRCS = '0' ELSE "ZZZZZZZZZZZZZZZZ";
SRD(15 DOWNTO 0) <= fb_ad_in(31 DOWNTO 16) WHEN nFB_WR = '0' AND nSRCS = '0' ELSE (others => 'Z');
-- fb_ad_out(31 DOWNTO 16) <= SRD(15 DOWNTO 0) WHEN nFB_OE = '0' AND nSRCS = '0' ELSE (others => 'Z');
fb_ad_out(31 downto 0) <= (others => 'Z'); -- otherwise we get a constant driver error
END rtl;

137
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
View File

@@ -130,7 +130,8 @@ ENTITY falconio_sdcard_ide_cf IS
WR_DATA : OUT std_logic;
WR_GATE : OUT std_logic;
DMA_DRQ : OUT std_logic;
FB_AD : INOUT std_logic_vector(31 DOWNTO 0);
fb_ad_in : in std_logic_vector(31 downto 0);
fb_ad_out : out std_logic_vector(31 downto 0);
LP_D : INOUT std_logic_vector(7 DOWNTO 0);
SND_A : INOUT std_logic_vector(7 downto 0);
ACSI_D : INOUT std_logic_vector(7 DOWNTO 0);
@@ -302,11 +303,11 @@ BEGIN
nDREQ0 <= '0';
-- input daten halten
p_hold_input_data : PROCESS(MAIN_CLK, nFB_WR, FB_AD(31 DOWNTO 16), FB_ADI(15 DOWNTO 0))
p_hold_input_data : PROCESS(MAIN_CLK, nFB_WR, fb_ad_in(31 DOWNTO 16), FB_ADI(15 DOWNTO 0))
BEGIN
IF rising_edge(MAIN_CLK) THEN
IF nFB_WR = '0' THEN
FB_ADI <= FB_AD(31 downto 16);
FB_ADI <= fb_ad_in(31 downto 16);
ELSE
FB_ADI <= FB_ADI;
END IF;
@@ -403,9 +404,9 @@ BEGIN
wrusedw => RDF_AZ
);
FCF_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"0020110" AND LONG = '1' ELSE '0'; -- F002'0110 LONG ONLY
FCF_APH <= '1' WHEN FB_ALE = '1' AND FB_AD(31 DOWNTO 0) = x"F0020110" AND LONG = '1' ELSE '0'; -- ADRESSPHASE F0020110 LONG ONLY
FCF_APH <= '1' WHEN FB_ALE = '1' AND fb_ad_in(31 DOWNTO 0) = x"F0020110" AND LONG = '1' ELSE '0'; -- ADRESSPHASE F0020110 LONG ONLY
RDF_RDE <= '1' WHEN FCF_APH = '1' AND nFB_WR = '1' ELSE '0'; -- AKTIVIEREN IN ADRESSPHASE
FB_AD <= RDF_DOUT(7 DOWNTO 0) & RDF_DOUT(15 DOWNTO 8) & RDF_DOUT(23 DOWNTO 16) & RDF_DOUT(31 DOWNTO 24) WHEN FCF_CS = '1' and nFB_OE = '0'
fb_ad_out <= RDF_DOUT(7 DOWNTO 0) & RDF_DOUT(15 DOWNTO 8) & RDF_DOUT(23 DOWNTO 16) & RDF_DOUT(31 DOWNTO 24) WHEN FCF_CS = '1' and nFB_OE = '0'
ELSE (OTHERS => 'Z');
RDF_DIN <= CD_OUT_FDC WHEN DMA_MODUS(7) = '1' ELSE SCSI_DOUT;
@@ -413,7 +414,7 @@ BEGIN
WRF: dcfifo1
PORT MAP(
aclr => CLR_FIFO,
data => FB_AD(7 DOWNTO 0) & FB_AD(15 DOWNTO 8) & FB_AD(23 DOWNTO 16) & FB_AD(31 DOWNTO 24),
data => fb_ad_in(7 DOWNTO 0) & fb_ad_in(15 DOWNTO 8) & fb_ad_in(23 DOWNTO 16) & fb_ad_in(31 DOWNTO 24),
rdclk => FDC_CLK,
rdreq => WRF_RDE,
wrclk => MAIN_CLK,
@@ -423,7 +424,7 @@ BEGIN
);
CD_IN_FDC <= WRF_DOUT WHEN DMA_ACTIV = '1' and DMA_MODUS(8) = '1' ELSE FB_ADI(7 DOWNTO 0); -- BEI DMA WRITE <-FIFO SONST <-FB
DMA_AZ_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"002010C" ELSE '0'; -- F002'010C LONG
FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ WHEN DMA_AZ_CS = '1' and nFB_OE = '0'
fb_ad_out <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ WHEN DMA_AZ_CS = '1' and nFB_OE = '0'
ELSE (OTHERS => 'Z');
DMA_DRQ_Q <= '1' WHEN DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' ELSE '0';
@@ -581,9 +582,9 @@ BEGIN
CA1 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(1);
CA2 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(2);
FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else (OTHERS => 'Z');
FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
FB_AD(23 DOWNTO 16) <= FDC_OUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "00" AND nFB_OE = '0' ELSE
fb_ad_out(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else (OTHERS => 'Z');
fb_ad_out(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
fb_ad_out(23 DOWNTO 16) <= FDC_OUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "00" AND nFB_OE = '0' ELSE
SCSI_DOUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "01" AND nFB_OE = '0' ELSE
DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
--- WDC BSL REGISTER -------------------------------------------------------
@@ -593,7 +594,7 @@ BEGIN
WDC_BSL <= "00";
ELSIF rising_edge(MAIN_CLK) AND WDC_BSL_CS = '1' AND nFB_WR = '0' THEN
IF FB_B0 = '1' THEN
WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24);
WDC_BSL(1 DOWNTO 0) <= fb_ad_in(25 DOWNTO 24);
ELSE
WDC_BSL(1 DOWNTO 0) <= WDC_BSL(1 DOWNTO 0);
END IF;
@@ -606,12 +607,12 @@ BEGIN
DMA_MODUS <= x"0000";
ELSIF rising_edge(MAIN_CLK) AND DMA_MODUS_CS = '1' AND nFB_WR = '0' THEN
IF FB_B0 = '1' THEN
DMA_MODUS(15 DOWNTO 8) <= FB_AD(31 DOWNTO 24);
DMA_MODUS(15 DOWNTO 8) <= fb_ad_in(31 DOWNTO 24);
ELSE
DMA_MODUS(15 DOWNTO 8) <= DMA_MODUS(15 DOWNTO 8);
END IF;
IF FB_B1 = '1' THEN
DMA_MODUS(7 DOWNTO 0) <= FB_AD(23 DOWNTO 16);
DMA_MODUS(7 DOWNTO 0) <= fb_ad_in(23 DOWNTO 16);
ELSE
DMA_MODUS(7 DOWNTO 0) <= DMA_MODUS(7 DOWNTO 0);
END IF;
@@ -626,16 +627,16 @@ BEGIN
DMA_BYT_CNT <= x"00000000";
ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND DMA_DATEN_CS = '1' AND nFB_WR = '0' AND DMA_MODUS(4) = '1' AND FB_B1 = '1' THEN
DMA_BYT_CNT(31 downto 17) <= "000000000000000";
DMA_BYT_CNT(16 DOWNTO 9) <= FB_AD(23 DOWNTO 16);
DMA_BYT_CNT(16 DOWNTO 9) <= fb_ad_in(23 DOWNTO 16);
DMA_BYT_CNT(8 downto 0) <= "000000000";
ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND DMA_BYT_CNT_CS = '1' THEN
DMA_BYT_CNT <= FB_AD;
DMA_BYT_CNT <= fb_ad_in;
ELSE
DMA_BYT_CNT <= DMA_BYT_CNT;
END IF;
END PROCESS;
--------------------------------------------------------------------
FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
fb_ad_out(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
DMA_STATUS(0) <= '1'; -- DMA OK
DMA_STATUS(1) <= '1' WHEN DMA_BYT_CNT /= 0 AND DMA_BYT_CNT(31) = '0' ELSE '0'; -- WENN byts UND NICHT MINUS
DMA_STATUS(2) <= '0' WHEN DMA_DRQ_I = '1' OR SCSI_DRQ = '1' ELSE '0';
@@ -660,7 +661,7 @@ BEGIN
IF nRSTO = '0' THEN
DMA_TOP <= x"00";
ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND (DMA_TOP_CS = '1' OR DMA_ADR_CS = '1') THEN
DMA_TOP <= FB_AD(31 DOWNTO 24);
DMA_TOP <= fb_ad_in(31 DOWNTO 24);
ELSE
DMA_TOP <= DMA_TOP;
END IF;
@@ -670,7 +671,7 @@ BEGIN
IF nRSTO = '0' THEN
DMA_HIGH <= x"00";
ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND (DMA_HIGH_CS = '1' OR DMA_ADR_CS = '1') THEN
DMA_HIGH <= FB_AD(23 DOWNTO 16);
DMA_HIGH <= fb_ad_in(23 DOWNTO 16);
ELSE
DMA_HIGH <= DMA_HIGH;
END IF;
@@ -682,9 +683,9 @@ BEGIN
DMA_MID <= x"00";
ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' THEN
IF DMA_MID_CS = '1' THEN
DMA_MID <= FB_AD(23 DOWNTO 16);
DMA_MID <= fb_ad_in(23 DOWNTO 16);
ELSIF DMA_ADR_CS = '1' THEN
DMA_MID <= FB_AD(15 DOWNTO 8);
DMA_MID <= fb_ad_in(15 DOWNTO 8);
END IF;
END IF;
END PROCESS;
@@ -695,9 +696,9 @@ BEGIN
DMA_LOW <= x"00";
ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' THEN
IF DMA_LOW_CS = '1'THEN
DMA_LOW <= FB_AD(23 DOWNTO 16);
DMA_LOW <= fb_ad_in(23 DOWNTO 16);
ELSIF DMA_ADR_CS = '1' THEN
DMA_LOW <= FB_AD(7 DOWNTO 0);
DMA_LOW <= fb_ad_in(7 DOWNTO 0);
END IF;
END IF;
END PROCESS;
@@ -707,18 +708,18 @@ BEGIN
DMA_MID_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C305" AND FB_B1 = '1' ELSE '0'; -- F860B/2
DMA_LOW_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C306" AND FB_B1 = '1' ELSE '0'; -- F860D/2
FB_AD(31 DOWNTO 24) <= DMA_TOP WHEN DMA_TOP_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
FB_AD(23 DOWNTO 16) <= DMA_HIGH WHEN DMA_HIGH_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
FB_AD(23 DOWNTO 16) <= DMA_MID WHEN DMA_MID_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
FB_AD(23 DOWNTO 16) <= DMA_LOW WHEN DMA_LOW_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
fb_ad_out(31 DOWNTO 24) <= DMA_TOP WHEN DMA_TOP_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
fb_ad_out(23 DOWNTO 16) <= DMA_HIGH WHEN DMA_HIGH_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
fb_ad_out(23 DOWNTO 16) <= DMA_MID WHEN DMA_MID_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
fb_ad_out(23 DOWNTO 16) <= DMA_LOW WHEN DMA_LOW_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
-- DIRECTZUGRIFF
DMA_DIRM_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20100" ELSE '0'; -- F002'0100 WORD
DMA_ADR_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20104" ELSE '0'; -- F002'0104 LONG
DMA_BYT_CNT_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20108" ELSE '0'; -- F002'0108 LONG
FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= DMA_MODUS WHEN DMA_DIRM_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD <= DMA_BYT_CNT WHEN DMA_BYT_CNT_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
fb_ad_out <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
fb_ad_out(31 DOWNTO 16) <= DMA_MODUS WHEN DMA_DIRM_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
fb_ad_out <= DMA_BYT_CNT WHEN DMA_BYT_CNT_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
-- DMA RW TOGGLE ------------------------------------------
PROCESS(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD)
@@ -840,8 +841,8 @@ BEGIN
);
ACIA_CS_I <= '1' WHEN nFB_CS1 = '0'AND FB_ADR(19 DOWNTO 3) = x"1FF80" ELSE '0'; -- FFC00-FFC07 FFC00/8
KEYB_RxD <= '0' WHEN AMKB_REG(3) = '0' or PIC_AMKB_RX = '0' ELSE '1'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL //
FB_AD(31 DOWNTO 24) <= DATA_OUT_ACIA_I WHEN ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' ELSE
DATA_OUT_ACIA_II WHEN ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
fb_ad_out(31 DOWNTO 24) <= DATA_OUT_ACIA_I WHEN ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' ELSE
DATA_OUT_ACIA_II WHEN ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' ELSE (others => 'Z');
-- AMKB_TX: SPIKES AUSFILTERN und sychronisieren ------------------------------------------
PROCESS(CLK2M, AMKB_RX, AMKB_REG)
@@ -916,7 +917,7 @@ BEGIN
DTACKn => DTACK_OUT_MFPn,
-- Data and Adresses:
RS => FB_ADR(5 DOWNTO 1),
DATA_IN => FB_AD(23 DOWNTO 16),
DATA_IN => fb_ad_in(23 DOWNTO 16),
DATA_OUT => DATA_OUT_MFP,
-- DATA_EN => DATA_EN_MFP,
GPIP_IN(7) => NOT DMA_DRQ_Q,
@@ -957,10 +958,10 @@ BEGIN
MFP_INTACK <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20000" ELSE '0'; --F002'0000
LDS <= '1' WHEN MFP_CS = '1' OR MFP_INTACK = '1' ELSE '0';
FB_AD(23 DOWNTO 16) <= DATA_OUT_MFP WHEN MFP_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
FB_AD(31 DOWNTO 10) <= "0000000000000000000000" WHEN MFP_INTACK = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZ";
FB_AD(9 DOWNTO 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
FB_AD(1 DOWNTO 0) <= "00" WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE "ZZ";
fb_ad_out(23 DOWNTO 16) <= DATA_OUT_MFP WHEN MFP_CS = '1' and nFB_OE = '0' ELSE (others => 'Z');
fb_ad_out(31 DOWNTO 10) <= "0000000000000000000000" WHEN MFP_INTACK = '1' and nFB_OE = '0' ELSE (others => 'Z');
fb_ad_out(9 DOWNTO 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' ELSE (others => 'Z');
fb_ad_out(1 DOWNTO 0) <= "00" WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE (others => 'Z');
DINTn <= '0' WHEN IDE_INT = '1' AND ACP_CONF(28) = '1' ELSE
'0' WHEN FDINT = '1' ELSE
'0' WHEN SCSI_INT = '1' AND ACP_CONF(28) = '1' ELSE '1';
@@ -1000,7 +1001,7 @@ BEGIN
SNDCS_I <= '1' WHEN SNDCS = '1' AND FB_ADR (1 DOWNTO 1) = "0" ELSE '0';
SNDIR_I <= '1' WHEN SNDCS = '1' AND nFB_WR = '0' ELSE '0';
FB_AD(31 DOWNTO 24) <= DA_OUT_X WHEN SNDCS_I = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
fb_ad_out(31 DOWNTO 24) <= DA_OUT_X WHEN SNDCS_I = '1' and nFB_OE = '0' ELSE (others => 'Z');
nnIDE_RES <= SND_A_X(7);
LP_DIR_X <= SND_A_X(6);
@@ -1012,7 +1013,7 @@ BEGIN
DSA_D <= SND_A_X(1);
nSDSEL <= SND_A_X(0);
SND_A <= SND_A_X;
LP_D <= LP_D_X WHEN LP_DIR_X = '0' ELSE "ZZZZZZZZ";
LP_D <= LP_D_X WHEN LP_DIR_X = '0' ELSE (others => 'Z');
LP_DIR <= LP_DIR_X;
@@ -1027,143 +1028,143 @@ BEGIN
IF nRSTO = '0' THEN
sndmactl <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_WR = '0' and FB_B1 ='1' THEN
sndmactl <= FB_AD(23 DOWNTO 16);
sndmactl <= fb_ad_in(23 DOWNTO 16);
ELSE
sndmactl <= sndmactl;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndmactl WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_OE = '0' ELSE "ZZZZZZZZ";
fb_ad_out(23 DOWNTO 16) <= sndmactl WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_OE = '0' ELSE (others => 'Z');
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
begin
IF nRSTO = '0' THEN
sndbashi <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_WR = '0' and FB_B1 ='1' THEN
sndbashi <= FB_AD(23 DOWNTO 16);
sndbashi <= fb_ad_in(23 DOWNTO 16);
ELSE
sndbashi <= sndbashi;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndbashi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_OE = '0' ELSE "ZZZZZZZZ";
fb_ad_out(23 DOWNTO 16) <= sndbashi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_OE = '0' ELSE (others => 'Z');
PROCESS(nRSTO,MAIN_CLK,FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndbasmi <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"2" and nFB_WR = '0' and FB_B1 ='1' THEN
sndbasmi <= FB_AD(23 DOWNTO 16);
sndbasmi <= fb_ad_in(23 DOWNTO 16);
ELSE
sndbasmi <= sndbasmi;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndbasmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"2" and nFB_OE = '0' ELSE "ZZZZZZZZ";
fb_ad_out(23 DOWNTO 16) <= sndbasmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"2" and nFB_OE = '0' ELSE (others => 'Z');
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndbaslo <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"3" and nFB_WR = '0' and FB_B1 ='1' THEN
sndbaslo <= FB_AD(23 DOWNTO 16);
sndbaslo <= fb_ad_in(23 DOWNTO 16);
ELSE
sndbaslo <= sndbaslo;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndbaslo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"3" and nFB_OE = '0' ELSE "ZZZZZZZZ";
fb_ad_out(23 DOWNTO 16) <= sndbaslo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"3" and nFB_OE = '0' ELSE (others => 'Z');
PROCESS(nRSTO,MAIN_CLK,FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndadrhi <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"4" and nFB_WR = '0' and FB_B1 ='1' THEN
sndadrhi <= FB_AD(23 DOWNTO 16);
sndadrhi <= fb_ad_in(23 DOWNTO 16);
ELSE
sndadrhi <= sndadrhi;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndadrhi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"4" and nFB_OE = '0' ELSE "ZZZZZZZZ";
fb_ad_out(23 DOWNTO 16) <= sndadrhi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"4" and nFB_OE = '0' ELSE (others => 'Z');
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndadrmi <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"5" and nFB_WR = '0' and FB_B1 ='1' THEN
sndadrmi <= FB_AD(23 DOWNTO 16);
sndadrmi <= fb_ad_in(23 DOWNTO 16);
ELSE
sndadrmi <= sndadrmi;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndadrmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"5" and nFB_OE = '0' else "ZZZZZZZZ";
fb_ad_out(23 DOWNTO 16) <= sndadrmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"5" and nFB_OE = '0' else (others => 'Z');
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndadrlo <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"6" and nFB_WR = '0' and FB_B1 ='1' THEN
sndadrlo <= FB_AD(23 DOWNTO 16);
sndadrlo <= fb_ad_in(23 DOWNTO 16);
ELSE
sndadrlo <= sndadrlo;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndadrlo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"6" and nFB_OE = '0' ELSE "ZZZZZZZZ";
fb_ad_out(23 DOWNTO 16) <= sndadrlo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"6" and nFB_OE = '0' ELSE (others => 'Z');
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndendhi <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"7" and nFB_WR = '0' and FB_B1 ='1' THEN
sndendhi <= FB_AD(23 DOWNTO 16);
sndendhi <= fb_ad_in(23 DOWNTO 16);
ELSE
sndendhi <= sndendhi;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndendhi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"7" and nFB_OE = '0' ELSE "ZZZZZZZZ";
fb_ad_out(23 DOWNTO 16) <= sndendhi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"7" and nFB_OE = '0' ELSE (others => 'Z');
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndendmi <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_WR = '0' and FB_B1 ='1' THEN
sndendmi <= FB_AD(23 DOWNTO 16);
sndendmi <= fb_ad_in(23 DOWNTO 16);
ELSE
sndendmi <= sndendmi;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndendmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_OE = '0' ELSE "ZZZZZZZZ";
fb_ad_out(23 DOWNTO 16) <= sndendmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_OE = '0' ELSE (others => 'Z');
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndendlo <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_WR = '0' and FB_B1 ='1' THEN
sndendlo <= FB_AD(23 DOWNTO 16);
sndendlo <= fb_ad_in(23 DOWNTO 16);
ELSE
sndendlo <= sndendlo;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndendlo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_OE = '0' ELSE "ZZZZZZZZ";
fb_ad_out(23 DOWNTO 16) <= sndendlo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_OE = '0' ELSE (others => 'Z');
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndmode <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_WR = '0' and FB_B1 ='1' THEN
sndmode <= FB_AD(23 DOWNTO 16);
sndmode <= fb_ad_in(23 DOWNTO 16);
ELSE
sndmode <= sndmode;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndmode WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_OE = '0' ELSE "ZZZZZZZZ";
fb_ad_out(23 DOWNTO 16) <= sndmode WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_OE = '0' ELSE (others => 'Z');
----------------------------------------------------------------------------
-- Paddle
@@ -1171,13 +1172,13 @@ BEGIN
paddle_cs <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 6) = x"3E48" ELSE '0'; -- F9200-F923F
FB_AD(31 DOWNTO 16) <= x"bfff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"A" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"B" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= x"0000" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= x"0000" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"11" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
fb_ad_out(31 DOWNTO 16) <= x"bfff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_OE = '0' ELSE (others => 'Z');
fb_ad_out(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_OE = '0' ELSE (others => 'Z');
fb_ad_out(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_OE = '0' ELSE (others => 'Z');
fb_ad_out(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_OE = '0' ELSE (others => 'Z');
fb_ad_out(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"A" and nFB_OE = '0' ELSE (others => 'Z');
fb_ad_out(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"B" and nFB_OE = '0' ELSE (others => 'Z');
fb_ad_out(31 DOWNTO 16) <= x"0000" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_OE = '0' ELSE (others => 'Z');
fb_ad_out(31 DOWNTO 16) <= x"0000" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"11" and nFB_OE = '0' ELSE (others => 'Z');
END rtl;

155
FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd
View File

@@ -174,7 +174,8 @@ ENTITY interrupt_handler IS
INT_HANDLER_TA : BUFFER std_logic;
ACP_CONF : BUFFER std_logic_vector(31 DOWNTO 0);
TIN0 : BUFFER std_logic;
FB_AD : INOUT std_logic_vector(31 DOWNTO 0)
fb_ad_in : in std_logic_vector(31 downto 0);
fb_ad_out : out std_logic_vector(31 downto 0)
);
END interrupt_handler;
@@ -5100,7 +5101,7 @@ BEGIN
-- $10000/4
INT_CTR_CS <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4000" else '0';
INT_CTR_d <= FB_AD;
INT_CTR_d <= fb_ad_in;
INT_CTR24_ena_ctrl <= INT_CTR_CS and FB_B(0) and (not nFB_WR);
INT_CTR16_ena_ctrl <= INT_CTR_CS and FB_B(1) and (not nFB_WR);
INT_CTR8_ena_ctrl <= INT_CTR_CS and FB_B(2) and (not nFB_WR);
@@ -5115,7 +5116,7 @@ BEGIN
-- INT_ENA_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) =
-- "00000000000100000000000001");
INT_ENA_d <= FB_AD;
INT_ENA_d <= fb_ad_in;
INT_ENA24_ena_ctrl <= INT_ENA_CS and FB_B(0) and (not nFB_WR);
INT_ENA16_ena_ctrl <= INT_ENA_CS and FB_B(1) and (not nFB_WR);
INT_ENA8_ena_ctrl <= INT_ENA_CS and FB_B(2) and (not nFB_WR);
@@ -5127,13 +5128,13 @@ BEGIN
-- $10008/4
int_clear_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4002" else '0';
-- INT_CLEAR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000100000000000010");
INT_CLEAR_d(31 DOWNTO 24) <= FB_AD(31 DOWNTO 24) and sizeIt(INT_CLEAR_CS,8)
INT_CLEAR_d(31 DOWNTO 24) <= fb_ad_in(31 DOWNTO 24) and sizeIt(INT_CLEAR_CS,8)
and sizeIt(FB_B(0),8) and sizeIt(not nFB_WR,8);
INT_CLEAR_d(23 DOWNTO 16) <= FB_AD(23 DOWNTO 16) and sizeIt(INT_CLEAR_CS,8)
INT_CLEAR_d(23 DOWNTO 16) <= fb_ad_in(23 DOWNTO 16) and sizeIt(INT_CLEAR_CS,8)
and sizeIt(FB_B(1),8) and sizeIt(not nFB_WR,8);
INT_CLEAR_d(15 DOWNTO 8) <= FB_AD(15 DOWNTO 8) and sizeIt(INT_CLEAR_CS,8)
INT_CLEAR_d(15 DOWNTO 8) <= fb_ad_in(15 DOWNTO 8) and sizeIt(INT_CLEAR_CS,8)
and sizeIt(FB_B(2),8) and sizeIt(not nFB_WR,8);
INT_CLEAR_d(7 DOWNTO 0) <= FB_AD(7 DOWNTO 0) and sizeIt(INT_CLEAR_CS,8) and
INT_CLEAR_d(7 DOWNTO 0) <= fb_ad_in(7 DOWNTO 0) and sizeIt(INT_CLEAR_CS,8) and
sizeIt(FB_B(3),8) and sizeIt(not nFB_WR,8);
-- INTERRUPT LATCH REGISTER READ ONLY
@@ -5341,7 +5342,7 @@ BEGIN
-- $4'0000/4
ACP_CONF_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000010000000000000000");
ACP_CONF_d <= FB_AD;
ACP_CONF_d <= fb_ad_in;
ACP_CONF24_ena_ctrl <= ACP_CONF_CS and FB_B(0) and (not nFB_WR);
ACP_CONF16_ena_ctrl <= ACP_CONF_CS and FB_B(1) and (not nFB_WR);
ACP_CONF8_ena_ctrl <= ACP_CONF_CS and FB_B(2) and (not nFB_WR);
@@ -5352,7 +5353,7 @@ BEGIN
-- C1287 0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR
-- --------------------------------------------------------
RTC_ADR0_clk_ctrl <= MAIN_CLK;
RTC_ADR_d <= FB_AD(21 DOWNTO 16);
RTC_ADR_d <= fb_ad_in(21 DOWNTO 16);
-- FFFF8961
UHR_AS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100010010110000") and FB_B(1);
@@ -5370,210 +5371,210 @@ BEGIN
WERTE0_0_clk_ctrl <= MAIN_CLK;
(WERTE7_0_d_1, WERTE6_0_d_1, WERTE5_0_d_1, WERTE4_0_d_1, WERTE3_0_d_1,
WERTE2_0_d_1, WERTE1_0_d_1, WERTE0_0_d_1) <= FB_AD(23 DOWNTO 16) and
WERTE2_0_d_1, WERTE1_0_d_1, WERTE0_0_d_1) <= fb_ad_in(23 DOWNTO 16) and
sizeIt(to_std_logic(RTC_ADR_q = "000000"),8) and sizeIt(UHR_DS,8) and
sizeIt(not nFB_WR,8);
(WERTE7_d(1), WERTE6_d(1), WERTE5_d(1), WERTE4_d(1), WERTE3_d(1),
WERTE2_d(1), WERTE1_d(1), WERTE0_d(1)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(1), WERTE1_d(1), WERTE0_d(1)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_2_d_1, WERTE6_2_d_1, WERTE5_2_d_1, WERTE4_2_d_1, WERTE3_2_d_1,
WERTE2_2_d_1, WERTE1_2_d_1, WERTE0_2_d_1) <= FB_AD(23 DOWNTO 16) and
WERTE2_2_d_1, WERTE1_2_d_1, WERTE0_2_d_1) <= fb_ad_in(23 DOWNTO 16) and
sizeIt(to_std_logic(RTC_ADR_q = "000010"),8) and sizeIt(UHR_DS,8) and
sizeIt(not nFB_WR,8);
(WERTE7_d(3), WERTE6_d(3), WERTE5_d(3), WERTE4_d(3), WERTE3_d(3),
WERTE2_d(3), WERTE1_d(3), WERTE0_d(3)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(3), WERTE1_d(3), WERTE0_d(3)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_4_d_1, WERTE6_4_d_1, WERTE5_4_d_1, WERTE4_4_d_1, WERTE3_4_d_1,
WERTE2_4_d_1, WERTE1_4_d_1, WERTE0_4_d_1) <= FB_AD(23 DOWNTO 16) and
WERTE2_4_d_1, WERTE1_4_d_1, WERTE0_4_d_1) <= fb_ad_in(23 DOWNTO 16) and
sizeIt(to_std_logic(RTC_ADR_q = "000100"),8) and sizeIt(UHR_DS,8) and
sizeIt(not nFB_WR,8);
(WERTE7_d(5), WERTE6_d(5), WERTE5_d(5), WERTE4_d(5), WERTE3_d(5),
WERTE2_d(5), WERTE1_d(5), WERTE0_d(5)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(5), WERTE1_d(5), WERTE0_d(5)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_6_d_1, WERTE6_6_d_1, WERTE5_6_d_1, WERTE4_6_d_1, WERTE3_6_d_1,
WERTE2_6_d_1, WERTE1_6_d_1, WERTE0_6_d_1) <= FB_AD(23 DOWNTO 16) and
WERTE2_6_d_1, WERTE1_6_d_1, WERTE0_6_d_1) <= fb_ad_in(23 DOWNTO 16) and
sizeIt(to_std_logic(RTC_ADR_q = "000110"),8) and sizeIt(UHR_DS,8) and
sizeIt(not nFB_WR,8);
(WERTE7_7_d_1, WERTE6_7_d_1, WERTE5_7_d_1, WERTE4_7_d_1, WERTE3_7_d_1,
WERTE2_7_d_1, WERTE1_7_d_1, WERTE0_7_d_1) <= FB_AD(23 DOWNTO 16) and
WERTE2_7_d_1, WERTE1_7_d_1, WERTE0_7_d_1) <= fb_ad_in(23 DOWNTO 16) and
sizeIt(to_std_logic(RTC_ADR_q = "000111"),8) and sizeIt(UHR_DS,8) and
sizeIt(not nFB_WR,8);
(WERTE7_8_d_1, WERTE6_8_d_1, WERTE5_8_d_1, WERTE4_8_d_1, WERTE3_8_d_1,
WERTE2_8_d_1, WERTE1_8_d_1, WERTE0_8_d_1) <= FB_AD(23 DOWNTO 16) and
WERTE2_8_d_1, WERTE1_8_d_1, WERTE0_8_d_1) <= fb_ad_in(23 DOWNTO 16) and
sizeIt(to_std_logic(RTC_ADR_q = "001000"),8) and sizeIt(UHR_DS,8) and
sizeIt(not nFB_WR,8);
(WERTE7_9_d_1, WERTE6_9_d_1, WERTE5_9_d_1, WERTE4_9_d_1, WERTE3_9_d_1,
WERTE2_9_d_1, WERTE1_9_d_1, WERTE0_9_d_1) <= FB_AD(23 DOWNTO 16) and
WERTE2_9_d_1, WERTE1_9_d_1, WERTE0_9_d_1) <= fb_ad_in(23 DOWNTO 16) and
sizeIt(to_std_logic(RTC_ADR_q = "001001"),8) and sizeIt(UHR_DS,8) and
sizeIt(not nFB_WR,8);
(WERTE7_d(10), WERTE6_d(10), WERTE5_d(10), WERTE4_d(10), WERTE3_d(10),
WERTE2_d(10), WERTE1_d(10), WERTE0_d(10)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(10), WERTE1_d(10), WERTE0_d(10)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(11), WERTE6_d(11), WERTE5_d(11), WERTE4_d(11), WERTE3_d(11),
WERTE2_11_d_1, WERTE1_11_d_1, WERTE0_11_d_1) <= FB_AD(23 DOWNTO 16);
WERTE2_11_d_1, WERTE1_11_d_1, WERTE0_11_d_1) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(12), WERTE6_d(12), WERTE5_d(12), WERTE4_d(12), WERTE3_d(12),
WERTE2_d(12), WERTE1_d(12), WERTE0_d(12)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(12), WERTE1_d(12), WERTE0_d(12)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_13_d_1, WERTE6_d(13), WERTE5_d(13), WERTE4_d(13), WERTE3_d(13),
WERTE2_d(13), WERTE1_d(13), WERTE0_13_d_1) <= FB_AD(23 DOWNTO 16);
WERTE2_d(13), WERTE1_d(13), WERTE0_13_d_1) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(14), WERTE6_d(14), WERTE5_d(14), WERTE4_d(14), WERTE3_d(14),
WERTE2_d(14), WERTE1_d(14), WERTE0_d(14)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(14), WERTE1_d(14), WERTE0_d(14)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(15), WERTE6_d(15), WERTE5_d(15), WERTE4_d(15), WERTE3_d(15),
WERTE2_d(15), WERTE1_d(15), WERTE0_d(15)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(15), WERTE1_d(15), WERTE0_d(15)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(16), WERTE6_d(16), WERTE5_d(16), WERTE4_d(16), WERTE3_d(16),
WERTE2_d(16), WERTE1_d(16), WERTE0_d(16)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(16), WERTE1_d(16), WERTE0_d(16)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(17), WERTE6_d(17), WERTE5_d(17), WERTE4_d(17), WERTE3_d(17),
WERTE2_d(17), WERTE1_d(17), WERTE0_d(17)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(17), WERTE1_d(17), WERTE0_d(17)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(18), WERTE6_d(18), WERTE5_d(18), WERTE4_d(18), WERTE3_d(18),
WERTE2_d(18), WERTE1_d(18), WERTE0_d(18)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(18), WERTE1_d(18), WERTE0_d(18)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(19), WERTE6_d(19), WERTE5_d(19), WERTE4_d(19), WERTE3_d(19),
WERTE2_d(19), WERTE1_d(19), WERTE0_d(19)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(19), WERTE1_d(19), WERTE0_d(19)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(20), WERTE6_d(20), WERTE5_d(20), WERTE4_d(20), WERTE3_d(20),
WERTE2_d(20), WERTE1_d(20), WERTE0_d(20)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(20), WERTE1_d(20), WERTE0_d(20)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(21), WERTE6_d(21), WERTE5_d(21), WERTE4_d(21), WERTE3_d(21),
WERTE2_d(21), WERTE1_d(21), WERTE0_d(21)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(21), WERTE1_d(21), WERTE0_d(21)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(22), WERTE6_d(22), WERTE5_d(22), WERTE4_d(22), WERTE3_d(22),
WERTE2_d(22), WERTE1_d(22), WERTE0_d(22)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(22), WERTE1_d(22), WERTE0_d(22)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(23), WERTE6_d(23), WERTE5_d(23), WERTE4_d(23), WERTE3_d(23),
WERTE2_d(23), WERTE1_d(23), WERTE0_d(23)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(23), WERTE1_d(23), WERTE0_d(23)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(24), WERTE6_d(24), WERTE5_d(24), WERTE4_d(24), WERTE3_d(24),
WERTE2_d(24), WERTE1_d(24), WERTE0_d(24)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(24), WERTE1_d(24), WERTE0_d(24)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(25), WERTE6_d(25), WERTE5_d(25), WERTE4_d(25), WERTE3_d(25),
WERTE2_d(25), WERTE1_d(25), WERTE0_d(25)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(25), WERTE1_d(25), WERTE0_d(25)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(26), WERTE6_d(26), WERTE5_d(26), WERTE4_d(26), WERTE3_d(26),
WERTE2_d(26), WERTE1_d(26), WERTE0_d(26)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(26), WERTE1_d(26), WERTE0_d(26)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(27), WERTE6_d(27), WERTE5_d(27), WERTE4_d(27), WERTE3_d(27),
WERTE2_d(27), WERTE1_d(27), WERTE0_d(27)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(27), WERTE1_d(27), WERTE0_d(27)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(28), WERTE6_d(28), WERTE5_d(28), WERTE4_d(28), WERTE3_d(28),
WERTE2_d(28), WERTE1_d(28), WERTE0_d(28)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(28), WERTE1_d(28), WERTE0_d(28)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(29), WERTE6_d(29), WERTE5_d(29), WERTE4_d(29), WERTE3_d(29),
WERTE2_d(29), WERTE1_d(29), WERTE0_d(29)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(29), WERTE1_d(29), WERTE0_d(29)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(30), WERTE6_d(30), WERTE5_d(30), WERTE4_d(30), WERTE3_d(30),
WERTE2_d(30), WERTE1_d(30), WERTE0_d(30)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(30), WERTE1_d(30), WERTE0_d(30)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(31), WERTE6_d(31), WERTE5_d(31), WERTE4_d(31), WERTE3_d(31),
WERTE2_d(31), WERTE1_d(31), WERTE0_d(31)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(31), WERTE1_d(31), WERTE0_d(31)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(32), WERTE6_d(32), WERTE5_d(32), WERTE4_d(32), WERTE3_d(32),
WERTE2_d(32), WERTE1_d(32), WERTE0_d(32)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(32), WERTE1_d(32), WERTE0_d(32)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(33), WERTE6_d(33), WERTE5_d(33), WERTE4_d(33), WERTE3_d(33),
WERTE2_d(33), WERTE1_d(33), WERTE0_d(33)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(33), WERTE1_d(33), WERTE0_d(33)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(34), WERTE6_d(34), WERTE5_d(34), WERTE4_d(34), WERTE3_d(34),
WERTE2_d(34), WERTE1_d(34), WERTE0_d(34)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(34), WERTE1_d(34), WERTE0_d(34)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(35), WERTE6_d(35), WERTE5_d(35), WERTE4_d(35), WERTE3_d(35),
WERTE2_d(35), WERTE1_d(35), WERTE0_d(35)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(35), WERTE1_d(35), WERTE0_d(35)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(36), WERTE6_d(36), WERTE5_d(36), WERTE4_d(36), WERTE3_d(36),
WERTE2_d(36), WERTE1_d(36), WERTE0_d(36)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(36), WERTE1_d(36), WERTE0_d(36)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(37), WERTE6_d(37), WERTE5_d(37), WERTE4_d(37), WERTE3_d(37),
WERTE2_d(37), WERTE1_d(37), WERTE0_d(37)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(37), WERTE1_d(37), WERTE0_d(37)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(38), WERTE6_d(38), WERTE5_d(38), WERTE4_d(38), WERTE3_d(38),
WERTE2_d(38), WERTE1_d(38), WERTE0_d(38)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(38), WERTE1_d(38), WERTE0_d(38)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(39), WERTE6_d(39), WERTE5_d(39), WERTE4_d(39), WERTE3_d(39),
WERTE2_d(39), WERTE1_d(39), WERTE0_d(39)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(39), WERTE1_d(39), WERTE0_d(39)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(40), WERTE6_d(40), WERTE5_d(40), WERTE4_d(40), WERTE3_d(40),
WERTE2_d(40), WERTE1_d(40), WERTE0_d(40)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(40), WERTE1_d(40), WERTE0_d(40)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(41), WERTE6_d(41), WERTE5_d(41), WERTE4_d(41), WERTE3_d(41),
WERTE2_d(41), WERTE1_d(41), WERTE0_d(41)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(41), WERTE1_d(41), WERTE0_d(41)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(42), WERTE6_d(42), WERTE5_d(42), WERTE4_d(42), WERTE3_d(42),
WERTE2_d(42), WERTE1_d(42), WERTE0_d(42)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(42), WERTE1_d(42), WERTE0_d(42)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(43), WERTE6_d(43), WERTE5_d(43), WERTE4_d(43), WERTE3_d(43),
WERTE2_d(43), WERTE1_d(43), WERTE0_d(43)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(43), WERTE1_d(43), WERTE0_d(43)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(44), WERTE6_d(44), WERTE5_d(44), WERTE4_d(44), WERTE3_d(44),
WERTE2_d(44), WERTE1_d(44), WERTE0_d(44)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(44), WERTE1_d(44), WERTE0_d(44)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(45), WERTE6_d(45), WERTE5_d(45), WERTE4_d(45), WERTE3_d(45),
WERTE2_d(45), WERTE1_d(45), WERTE0_d(45)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(45), WERTE1_d(45), WERTE0_d(45)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(46), WERTE6_d(46), WERTE5_d(46), WERTE4_d(46), WERTE3_d(46),
WERTE2_d(46), WERTE1_d(46), WERTE0_d(46)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(46), WERTE1_d(46), WERTE0_d(46)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(47), WERTE6_d(47), WERTE5_d(47), WERTE4_d(47), WERTE3_d(47),
WERTE2_d(47), WERTE1_d(47), WERTE0_d(47)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(47), WERTE1_d(47), WERTE0_d(47)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(48), WERTE6_d(48), WERTE5_d(48), WERTE4_d(48), WERTE3_d(48),
WERTE2_d(48), WERTE1_d(48), WERTE0_d(48)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(48), WERTE1_d(48), WERTE0_d(48)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(49), WERTE6_d(49), WERTE5_d(49), WERTE4_d(49), WERTE3_d(49),
WERTE2_d(49), WERTE1_d(49), WERTE0_d(49)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(49), WERTE1_d(49), WERTE0_d(49)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(50), WERTE6_d(50), WERTE5_d(50), WERTE4_d(50), WERTE3_d(50),
WERTE2_d(50), WERTE1_d(50), WERTE0_d(50)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(50), WERTE1_d(50), WERTE0_d(50)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(51), WERTE6_d(51), WERTE5_d(51), WERTE4_d(51), WERTE3_d(51),
WERTE2_d(51), WERTE1_d(51), WERTE0_d(51)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(51), WERTE1_d(51), WERTE0_d(51)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(52), WERTE6_d(52), WERTE5_d(52), WERTE4_d(52), WERTE3_d(52),
WERTE2_d(52), WERTE1_d(52), WERTE0_d(52)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(52), WERTE1_d(52), WERTE0_d(52)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(53), WERTE6_d(53), WERTE5_d(53), WERTE4_d(53), WERTE3_d(53),
WERTE2_d(53), WERTE1_d(53), WERTE0_d(53)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(53), WERTE1_d(53), WERTE0_d(53)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(54), WERTE6_d(54), WERTE5_d(54), WERTE4_d(54), WERTE3_d(54),
WERTE2_d(54), WERTE1_d(54), WERTE0_d(54)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(54), WERTE1_d(54), WERTE0_d(54)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(55), WERTE6_d(55), WERTE5_d(55), WERTE4_d(55), WERTE3_d(55),
WERTE2_d(55), WERTE1_d(55), WERTE0_d(55)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(55), WERTE1_d(55), WERTE0_d(55)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(56), WERTE6_d(56), WERTE5_d(56), WERTE4_d(56), WERTE3_d(56),
WERTE2_d(56), WERTE1_d(56), WERTE0_d(56)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(56), WERTE1_d(56), WERTE0_d(56)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(57), WERTE6_d(57), WERTE5_d(57), WERTE4_d(57), WERTE3_d(57),
WERTE2_d(57), WERTE1_d(57), WERTE0_d(57)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(57), WERTE1_d(57), WERTE0_d(57)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(58), WERTE6_d(58), WERTE5_d(58), WERTE4_d(58), WERTE3_d(58),
WERTE2_d(58), WERTE1_d(58), WERTE0_d(58)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(58), WERTE1_d(58), WERTE0_d(58)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(59), WERTE6_d(59), WERTE5_d(59), WERTE4_d(59), WERTE3_d(59),
WERTE2_d(59), WERTE1_d(59), WERTE0_d(59)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(59), WERTE1_d(59), WERTE0_d(59)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(60), WERTE6_d(60), WERTE5_d(60), WERTE4_d(60), WERTE3_d(60),
WERTE2_d(60), WERTE1_d(60), WERTE0_d(60)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(60), WERTE1_d(60), WERTE0_d(60)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(61), WERTE6_d(61), WERTE5_d(61), WERTE4_d(61), WERTE3_d(61),
WERTE2_d(61), WERTE1_d(61), WERTE0_d(61)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(61), WERTE1_d(61), WERTE0_d(61)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(62), WERTE6_d(62), WERTE5_d(62), WERTE4_d(62), WERTE3_d(62),
WERTE2_d(62), WERTE1_d(62), WERTE0_d(62)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(62), WERTE1_d(62), WERTE0_d(62)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_d(63), WERTE6_d(63), WERTE5_d(63), WERTE4_d(63), WERTE3_d(63),
WERTE2_d(63), WERTE1_d(63), WERTE0_d(63)) <= FB_AD(23 DOWNTO 16);
WERTE2_d(63), WERTE1_d(63), WERTE0_d(63)) <= fb_ad_in(23 DOWNTO 16);
(WERTE7_0_ena_1, WERTE6_0_ena_1, WERTE5_0_ena_1, WERTE4_0_ena_1,
WERTE3_0_ena_1, WERTE2_0_ena_1, WERTE1_0_ena_1, WERTE0_0_ena_1) <=
@@ -6008,7 +6009,7 @@ BEGIN
(sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(31 DOWNTO 24));
u0_enabledt <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or
ACP_CONF_CS) and (not nFB_OE);
FB_AD(31 DOWNTO 24) <= u0_tridata;
fb_ad_out(31 DOWNTO 24) <= u0_tridata;
u1_data <= (std_logic_vector'(WERTE7_q(0) & WERTE6_q(0) & WERTE5_q(0) &
WERTE4_q(0) & WERTE3_q(0) & WERTE2_q(0) & WERTE1_q(0) & WERTE0_q(0))
and sizeIt(to_std_logic(RTC_ADR_q = "000000"),8) and sizeIt(UHR_DS,8))
@@ -6227,7 +6228,7 @@ BEGIN
(sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(23 DOWNTO 16));
u1_enabledt <= (UHR_DS or UHR_AS or INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS
or INT_CLEAR_CS or ACP_CONF_CS) and (not nFB_OE);
FB_AD(23 DOWNTO 16) <= u1_tridata;
fb_ad_out(23 DOWNTO 16) <= u1_tridata;
u2_data <= (sizeIt(INT_CTR_CS,8) and INT_CTR_q(15 DOWNTO 8)) or
(sizeIt(INT_ENA_CS,8) and INT_ENA_q(15 DOWNTO 8)) or
(sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(15 DOWNTO 8)) or
@@ -6235,7 +6236,7 @@ BEGIN
(sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(15 DOWNTO 8));
u2_enabledt <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or
ACP_CONF_CS) and (not nFB_OE);
FB_AD(15 DOWNTO 8) <= u2_tridata;
fb_ad_out(15 DOWNTO 8) <= u2_tridata;
u3_data <= (sizeIt(INT_CTR_CS,8) and INT_CTR_q(7 DOWNTO 0)) or
(sizeIt(INT_ENA_CS,8) and INT_ENA_q(7 DOWNTO 0)) or
(sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(7 DOWNTO 0)) or
@@ -6243,7 +6244,7 @@ BEGIN
(sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(7 DOWNTO 0));
u3_enabledt <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or
ACP_CONF_CS) and (not nFB_OE);
FB_AD(7 DOWNTO 0) <= u3_tridata;
fb_ad_out(7 DOWNTO 0) <= u3_tridata;
INT_HANDLER_TA <= int_ctr_cs or int_ena_cs or int_latch_cs or int_clear_cs;

100
FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd
View File

@@ -1,73 +1,47 @@
-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
-- Created on Fri Oct 16 15:40:59 2009
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity blitter is
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
port
(
nRSTO : IN std_logic;
MAIN_CLK : IN std_logic;
FB_ALE : IN std_logic;
nFB_WR : IN std_logic;
nFB_OE : IN std_logic;
FB_SIZE0 : IN std_logic;
FB_SIZE1 : IN std_logic;
VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0);
BLITTER_ON : IN std_logic;
FB_ADR : IN std_logic_vector(31 DOWNTO 0);
nFB_CS1 : IN std_logic;
nFB_CS2 : IN std_logic;
nFB_CS3 : IN std_logic;
DDRCLK0 : IN std_logic;
BLITTER_DIN : IN std_logic_vector(127 DOWNTO 0);
BLITTER_DACK : IN std_logic_vector(4 DOWNTO 0);
SR_BLITTER_DACK : IN std_logic;
BLITTER_RUN : OUT std_logic;
BLITTER_DOUT : OUT std_logic_vector(127 DOWNTO 0);
BLITTER_ADR : OUT std_logic_vector(31 DOWNTO 0);
BLITTER_SIG : OUT std_logic;
BLITTER_WR : OUT std_logic;
blitter_ta : OUT std_logic;
fb_ad_in : in std_logic_vector(31 DOWNTO 0);
nRSTO : in std_logic;
MAIN_CLK : in std_logic;
FB_ALE : in std_logic;
nFB_WR : in std_logic;
nFB_OE : in std_logic;
FB_SIZE0 : in std_logic;
FB_SIZE1 : in std_logic;
VIDEO_RAM_CTR : in std_logic_vector(15 downto 0);
BLITTER_ON : in std_logic;
FB_ADR : in std_logic_vector(31 downto 0);
nFB_CS1 : in std_logic;
nFB_CS2 : in std_logic;
nFB_CS3 : in std_logic;
DDRCLK0 : in std_logic;
BLITTER_DIN : in std_logic_vector(127 downto 0);
BLITTER_DACK : in std_logic_vector(4 downto 0);
SR_BLITTER_DACK : in std_logic;
blitter_run : out std_logic;
blitter_dout : out std_logic_vector(127 downto 0);
blitter_adr : out std_logic_vector(31 downto 0);
blitter_sig : out std_logic;
blitter_wr : out std_logic;
blitter_ta : out std_logic;
fb_ad_in : in std_logic_vector(31 downto 0);
fb_ad_out : out std_logic_vector(31 downto 0)
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END BLITTER;
end BLITTER;
ARCHITECTURE rtl OF blitter IS
architecture rtl of blitter is
BEGIN
BLITTER_RUN <= '0';
BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0";
BLITTER_ADR <= x"76543210";
BLITTER_SIG <= '0';
BLITTER_WR <= '0';
begin
blitter_run <= '0';
blitter_dout <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0";
blitter_adr <= x"76543210";
blitter_sig <= '0';
blitter_wr <= '0';
blitter_ta <= '0';
END rtl;
fb_ad_out <= (others => 'Z');
end rtl;

26
FPGA_Quartus_13.1/Video/DDR_CTR.vhd
View File

@@ -1384,16 +1384,24 @@ begin
"00000" & video_act_adr(26 downto 24) when video_cnt_h and not nfb_oe else
(others => 'Z');
u0_data <= (sizeIt(VIDEO_BASE_L,8) and VIDEO_BASE_L_D_q) or
(sizeIt(VIDEO_BASE_M,8) and VIDEO_BASE_M_D_q) or
(sizeIt(VIDEO_BASE_H,8) and VIDEO_BASE_H_D_q) or
(sizeIt(VIDEO_CNT_L,8) and VIDEO_ACT_ADR(7 downto 0)) or
(sizeIt(VIDEO_CNT_M,8) and VIDEO_ACT_ADR(15 downto 8)) or
(sizeIt(VIDEO_CNT_H,8) and VIDEO_ACT_ADR(23 downto 16));
u0_enabledt <= (VIDEO_BASE_L or VIDEO_BASE_M or VIDEO_BASE_H or VIDEO_CNT_L
or VIDEO_CNT_M or VIDEO_CNT_H) and (not nFB_OE);
fb_ad_out(23 downto 16) <= u0_tridata when u0_enabledt;
-- u0_data <= (sizeIt(VIDEO_BASE_L,8) and VIDEO_BASE_L_D_q) or
-- (sizeIt(VIDEO_BASE_M,8) and VIDEO_BASE_M_D_q) or
-- (sizeIt(VIDEO_BASE_H,8) and VIDEO_BASE_H_D_q) or
-- (sizeIt(VIDEO_CNT_L,8) and VIDEO_ACT_ADR(7 downto 0)) or
-- (sizeIt(VIDEO_CNT_M,8) and VIDEO_ACT_ADR(15 downto 8)) or
-- (sizeIt(VIDEO_CNT_H,8) and VIDEO_ACT_ADR(23 downto 16));
-- u0_enabledt <= (VIDEO_BASE_L or VIDEO_BASE_M or VIDEO_BASE_H or VIDEO_CNT_L
-- or VIDEO_CNT_M or VIDEO_CNT_H) and (not nFB_OE);
-- fb_ad_out(23 downto 16) <= u0_tridata when u0_enabledt else (others => 'Z');
fb_ad_out(23 downto 16) <= video_base_l_d_q when video_base_l and not nfb_oe else
video_base_m_d_q when video_base_m and not nfb_oe else
video_base_h_d_q when video_base_h and not nfb_oe else
video_act_adr(7 downto 0) when video_cnt_l and not nfb_oe else
video_act_adr(15 downto 8) when video_cnt_m and not nfb_oe else
video_act_adr(23 downto 16) when video_cnt_h and not nfb_oe else
(others => 'Z');
fb_ad_out(15 downto 0) <= (others => 'Z');
-- Assignments added to explicitly combine the
-- effects of multiple drivers in the source

918
FPGA_Quartus_13.1/Video/video.vhd
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File diff suppressed because it is too large Load Diff

92
FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd
View File

@@ -1131,7 +1131,7 @@ begin
-- 10 VGA
-- 11 TV
-- $8006/2
sys_ctr_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp_w(fb_adR, 20x"f8006") = '1';
sys_ctr_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp_w(fb_adR, 20x"f8006") = '1' else '0';
-- fb_adR(19 downto 1) = std_logic_vector'(20x"f8006")(19 downto 1) else '0';
-- sys_ctr_CS <= to_std_logic(((not nFB_CS1) = '1') and fb_adR(19 downto 1) = "1111100000000000011");
@@ -1284,31 +1284,31 @@ begin
-- (sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010"));
fb_ad_out(31 downto 16) <= "000000" & st_shift_mode_q & "00000000" when st_shift_mode_cs = '1' else
"100000000" & sys_ctr_q(6 downto 4) & (not blitter_run) & sys_ctr_q(2 downto 0) when sys_ctr_cs = '1' else
lwd_q when lof_cs = '1' and lwd_cs = '1' else
"0000" & hbe_q when hbe_cs = '1' else
"0000" & hdb_q when hdb_cs = '1' else
"0000" & hde_q when hde_cs = '1' else
"0000" & hbb_q when hbb_cs = '1' else
"0000" & hss_q when hss_cs = '1' else
"0000" & hht_q when hht_cs = '1' else
"00000" & vbe_q when vbe_cs = '1' else
"00000" & vdb_q when vdb_cs = '1' else
"00000" & vde_q when vde_cs = '1' else
"00000" & vbb_q when vbb_cs = '1' else
"00000" & vss_q when vss_cs = '1' else
"00000" & vft_q when vft_cs = '1' else
"0000000" & vco_q when vco_cs = '1' else
"000000000000" & vcntrl_q when vcntrl_cs = '1' else
acp_vctr_q(31 downto 16) when acp_vctr_cs = '1' else
atari_hh_q(31 downto 16) when atari_hh_cs = '1' else
atari_vh_q(31 downto 16) when atari_vh_cs = '1' else
atari_hl_q(31 downto 16) when atari_hl_cs = '1' else
atari_vl_q(31 downto 16) when atari_vl_cs = '1' else
"00000000" & border_color_q(23 downto 16) when border_color_cs = '1' else
"0000000" & vr_dout_q when video_pll_config_cs = '1' else
vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010" when video_pll_reconfig_cs = '1' else
(others => 'Z');
"100000000" & sys_ctr_q(6 downto 4) & (not blitter_run) & sys_ctr_q(2 downto 0) when sys_ctr_cs = '1' else
lwd_q when lof_cs = '1' and lwd_cs = '1' else
"0000" & hbe_q when hbe_cs = '1' else
"0000" & hdb_q when hdb_cs = '1' else
"0000" & hde_q when hde_cs = '1' else
"0000" & hbb_q when hbb_cs = '1' else
"0000" & hss_q when hss_cs = '1' else
"0000" & hht_q when hht_cs = '1' else
"00000" & vbe_q when vbe_cs = '1' else
"00000" & vdb_q when vdb_cs = '1' else
"00000" & vde_q when vde_cs = '1' else
"00000" & vbb_q when vbb_cs = '1' else
"00000" & vss_q when vss_cs = '1' else
"00000" & vft_q when vft_cs = '1' else
"0000000" & vco_q when vco_cs = '1' else
"000000000000" & vcntrl_q when vcntrl_cs = '1' else
acp_vctr_q(31 downto 16) when acp_vctr_cs = '1' else
atari_hh_q(31 downto 16) when atari_hh_cs = '1' else
atari_vh_q(31 downto 16) when atari_vh_cs = '1' else
atari_hl_q(31 downto 16) when atari_hl_cs = '1' else
atari_vl_q(31 downto 16) when atari_vl_cs = '1' else
"00000000" & border_color_q(23 downto 16) when border_color_cs = '1' else
"0000000" & vr_dout_q when video_pll_config_cs = '1' else
vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010" when video_pll_reconfig_cs = '1' else
(others => 'Z');
-- u0_enabledt <= (st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_CS or border_color_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or
-- hde_CS or HBB_CS or HSS_CS or HHT_CS or atari_hh_CS or atari_vh_CS or atari_hl_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or
@@ -1326,16 +1326,38 @@ begin
-- fb_ad(15 downto 0) <= u1_tridata;
fb_ad_out(15 downto 0) <= acp_vctr_q(15 downto 0) when acp_vctr_cs = '1' else
atari_hh_q(15 downto 0) when atari_hh_cs = '1' else
atari_vh_q(15 downto 0) when atari_vh_cs = '1' else
atari_hl_q(15 downto 0) when atari_hl_cs = '1' else
atari_vl_q(15 downto 0) when atari_vl_cs = '1' else
border_color_q(15 downto 0) when border_color_cs = '1' else
(others => 'Z');
atari_hh_q(15 downto 0) when atari_hh_cs = '1' else
atari_vh_q(15 downto 0) when atari_vh_cs = '1' else
atari_hl_q(15 downto 0) when atari_hl_cs = '1' else
atari_vl_q(15 downto 0) when atari_vl_cs = '1' else
border_color_q(15 downto 0) when border_color_cs = '1' else
(others => 'Z');
video_mod_ta <= clut_ta_q or st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or
hde_CS or HBB_CS or HSS_CS or HHT_CS or atari_hh_CS or atari_vh_CS or atari_hl_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or
VSS_CS or VFT_CS or VCO_CS or vcntrl_cs;
video_mod_ta <= clut_ta_q or
st_shift_mode_cs or
falcon_shift_mode_cs or
acp_vctr_cs or
sys_ctr_cs or
lof_cs or
lwd_cs or
hbe_cs or
hdb_cs or
hde_cs or
hbb_cs or
hss_cs or
hht_cs or
atari_hh_cs or
atari_vh_cs or
atari_hl_cs or
atari_vl_cs or
vbe_cs or
vdb_cs or
vde_cs or
vbb_cs or
vss_cs or
vft_cs or
vco_cs or
vcntrl_cs;
-- VIDEO AUSGABE SETZEN
CLK17M_d <= not CLK17M_q;

30
FPGA_Quartus_13.1/firebee1.vhd
View File

@@ -1,12 +1,12 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_1164.all;
LIBRARY altera;
USE altera.altera_primitives_components.all;
library altera;
use altera.altera_primitives_components.all;
LIBRARY work;
library work;
ENTITY firebee1 IS
entity firebee1 is
port
(
FB_ALE : in std_logic;
@@ -147,7 +147,7 @@ ENTITY firebee1 IS
);
end firebee1;
architecture rtl OF firebee1 IS
architecture rtl of firebee1 is
signal ACP_CONF : std_logic_vector(31 downto 0);
signal clk25m_i : std_logic;
signal CLK2M : std_logic;
@@ -270,7 +270,6 @@ begin
c4 => DDR_SYNC_66M
);
i_dsp : work.dsp
port map
(
@@ -285,7 +284,8 @@ begin
nFB_BURST => nFB_BURST,
nRSTO => nRSTO,
nFB_CS3 => nFB_CS3,
FB_AD => FB_AD,
fb_ad_in => fb_ad_in,
fb_ad_out => fb_ad_out,
FB_ADR => FB_ADR,
IO => IO,
SRD => SRD,
@@ -298,7 +298,6 @@ begin
DSP_TA => DSP_TA
);
i_falconio_sdcard_ide_cf : work.falconio_sdcard_ide_cf
port map
(
@@ -359,7 +358,8 @@ begin
SD_CDM_D1 => SD_CDM_D1,
ACP_CONF => ACP_CONF(31 downto 24),
ACSI_D => ACSI_D,
FB_AD => FB_AD,
fb_ad_in => fb_ad_in,
fb_ad_out => fb_ad_out,
FB_ADR => FB_ADR,
LP_D => LP_D,
SCSI_D => SCSI_D,
@@ -430,7 +430,8 @@ begin
HSYNC => HSYNC,
DMA_DRQ => DMA_DRQ,
nRSTO => nRSTO,
FB_AD => FB_AD,
fb_ad_in => fb_ad_in,
fb_ad_out => fb_ad_out,
FB_ADR => FB_ADR,
INT_HANDLER_TA => INT_HANDLER_TA,
TIN0 => TIN0,
@@ -438,7 +439,6 @@ begin
nIRQ => nIRQ
);
i_mfp_acia_clk_pll : work.altpll1
port map
(
@@ -473,7 +473,6 @@ begin
data_out => VR_D
);
i_video : entity work.video
port map
(
@@ -522,7 +521,6 @@ begin
VR => VR
);
i_video_clk_pll : altpll4
port map
(
@@ -563,6 +561,8 @@ begin
nWR_GATE <= not(WR_GATE);
nFB_TA <= not(video_ta or int_handler_ta or dsp_ta or falcon_io_ta);
fb_ad_in <= fb_ad;
fb_ad <= fb_ad_out when (video_ta or int_handler_ta or dsp_ta or falcon_io_ta) else (others => 'Z');
CLK33M <= MAIN_CLK;

171
FPGA_Quartus_13.1/firebee_utils_pkg.vhd
View File

@@ -1,171 +0,0 @@
----------------------------------------------------------------------
---- ----
---- This file is part of the 'Firebee' project. ----
---- http://acp.atari.org ----
---- ----
---- Description: ----
---- This package contains utility functions, procedures and constants
---- for the Firebee project.
----
---- Author(s): ----
---- - Markus Fröschle, mfro@mubf.de
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2015 Markus Fröschle
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU General Public ----
---- License as published by the Free Software Foundation; either ----
---- version 2 of the License, or (at your option) any later ----
---- version. ----
---- ----
---- This program is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, write to the Free ----
---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ----
---- Boston, MA 02110-1301, USA. ----
---- ----
----------------------------------------------------------------------
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
PACKAGE firebee_utils_pkg IS
FUNCTION f_addr_cmp_l(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic;
FUNCTION f_addr_cmp_w(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic;
FUNCTION f_addr_cmp_b(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic;
FUNCTION f_addr_cmp_mask(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector; CONSTANT num_ignore : integer) RETURN std_logic;
COMPONENT synchronizer IS
PORT
(
-- Input ports
source_signal : IN std_logic;
target_clock : IN std_logic;
target_signal : OUT std_logic
);
END COMPONENT synchronizer;
END firebee_utils_pkg;
PACKAGE BODY firebee_utils_pkg IS
FUNCTION f_addr_cmp_l(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic IS
VARIABLE ret : std_logic := '1';
VARIABLE c_low : integer;
VARIABLE c_hi : integer;
BEGIN
c_hi := addr_const'HIGH;
c_low := addr_const'LOW;
-- synthesis translate_off
REPORT("addr_const'HIGH = " & integer'IMAGE(c_hi) & " addr_const'LOW = " & integer'IMAGE(c_low)) SEVERITY WARNING;
REPORT("addr'HIGH = " & integer'IMAGE(addr'HIGH) & " addr'LOW = " & integer'IMAGE(addr'LOW)) SEVERITY WARNING;
-- synthesis translate_on
FOR i IN c_hi DOWNTO c_low + 2 LOOP
IF addr(i) /= addr_const(c_hi - i) THEN
-- synthesis translate_off
REPORT("f_addr_cmp_l(): addr = " & to_hstring(unsigned(addr)) & " differs from addr_const = " & to_hstring(unsigned(addr_const)) &
" at bit = " & integer'IMAGE(i)) SEVERITY WARNING;
REPORT("addr(" & integer'IMAGE(i) & ") (" & to_string(addr) & ") = " & to_string(addr(i)) &
" addr_const(" & integer'IMAGE(i) & ") ( " & to_string(addr_const) & ") = " & to_string(addr_const(i)));
-- synthesis translate_on
ret := '0';
EXIT;
END IF;
END LOOP;
RETURN ret;
END FUNCTION f_addr_cmp_l;
FUNCTION f_addr_cmp_w(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic IS
VARIABLE ret : std_logic := '1';
VARIABLE c_hi : integer;
VARIABLE c_low : integer;
BEGIN
REPORT("f_addr_cmp_w(): addr_const'HIGH = " & integer'IMAGE(addr_const'HIGH) & " addr_const'LOW = " & integer'IMAGE(addr_const'LOW)) SEVERITY WARNING;
REPORT("f_addr_cmp_w(): addr'HIGH = " & integer'IMAGE(addr'HIGH) & " addr'LOW = " & integer'IMAGE(addr'LOW)) SEVERITY WARNING;
c_hi := addr_const'HIGH;
c_low := addr_const'LOW;
FOR i IN c_hi DOWNTO c_low + 1 LOOP
IF addr(i) /= addr_const(c_hi - i) THEN
-- synthesis translate_off
REPORT("f_addr_cmp_w(): addr = " & to_hstring(unsigned(addr)) & " differs from addr_const = " & to_hstring(unsigned(addr_const)) &
" at bit = " & integer'IMAGE(i)) SEVERITY WARNING;
REPORT("f_addr_cmp_w(): addr(" & integer'IMAGE(i) & ") (" & to_string(addr) & ") = " & to_string(addr(i)) &
" addr_const(" & integer'IMAGE(i) & ") ( " & to_string(addr_const) & ") = " & to_string(addr_const(i)));
-- synthesis translate_on
ret := '0';
EXIT;
END IF;
END LOOP;
RETURN ret;
END FUNCTION f_addr_cmp_w;
-- this is just for completeness
FUNCTION f_addr_cmp_b(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic IS
VARIABLE ret : std_logic := '1';
VARIABLE c_hi : integer;
VARIABLE c_low : integer;
BEGIN
c_hi := addr_const'HIGH;
c_low := addr_const'LOW;
FOR i IN c_hi DOWNTO c_low LOOP
IF addr(i) /= addr_const(c_hi - i) THEN
-- synthesis translate_off
REPORT("f_addr_cmp_l(): addr = " & to_hstring(unsigned(addr)) & " differs from addr_const = " & to_hstring(unsigned(addr_const)) &
" at bit = " & integer'IMAGE(i)) SEVERITY WARNING;
REPORT("addr(" & integer'IMAGE(i) & ") (" & to_string(addr) & ") = " & to_string(addr(i)) &
" addr_const(" & integer'IMAGE(i) & ") ( " & to_string(addr_const) & ") = " & to_string(addr_const(i)));
-- synthesis translate_on
ret := '0';
EXIT;
END IF;
END LOOP;
RETURN ret;
END FUNCTION f_addr_cmp_b;
-- this is for arbitrary sized address compares. It compares from the highest bit of addr_const to the lowest - num_ignore
-- bit, thus allowing any size of comparision.
FUNCTION f_addr_cmp_mask(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector; CONSTANT num_ignore : integer) RETURN std_logic IS
VARIABLE ret : std_logic := '1';
VARIABLE c_hi : integer;
VARIABLE c_low : integer;
BEGIN
c_hi := addr_const'HIGH;
c_low := addr_const'LOW;
FOR i IN addr_const'HIGH DOWNTO addr_const'LOW + num_ignore LOOP
IF addr(i) /= addr_const(c_hi - i) THEN
-- synthesis translate_off
REPORT("f_addr_cmp_l(): addr = " & to_hstring(unsigned(addr)) & " differs from addr_const = " & to_hstring(unsigned(addr_const)) &
" at bit = " & integer'IMAGE(i)) SEVERITY WARNING;
REPORT("addr(" & integer'IMAGE(i) & ") (" & to_string(addr) & ") = " & to_string(addr(i)) &
" addr_const(" & integer'IMAGE(i) & ") ( " & to_string(addr_const) & ") = " & to_string(addr_const(i)));
-- synthesis translate_on
ret := '0';
EXIT;
END IF;
END LOOP;
RETURN ret;
END FUNCTION f_addr_cmp_mask;
END PACKAGE BODY firebee_utils_pkg;