80 lines
3.0 KiB
VHDL
80 lines
3.0 KiB
VHDL
-- WARNING: Do NOT edit the input AND output ports in this file in a text
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-- editor if you plan to continue editing the block that represents it in
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-- the Block Editor! File corruption is VERY likely to occur.
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-- Copyright (C) 1991-2008 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- AND other software AND tools, AND its AMPP partner logic
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-- functions, AND any output files from any of the foregoing
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-- (including device programming or simulation files), AND any
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-- associated documentation or information are expressly subject
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-- to the terms AND conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera AND sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
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-- Created on Tue Sep 08 16:24:57 2009
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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-- Entity Declaration
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ENTITY dsp IS
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-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
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PORT
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(
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CLK33M : IN std_logic;
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MAIN_CLK : IN std_logic;
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nFB_OE : IN std_logic;
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nFB_WR : IN std_logic;
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nFB_CS1 : IN std_logic;
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nFB_CS2 : IN std_logic;
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FB_SIZE0 : IN std_logic;
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FB_SIZE1 : IN std_logic;
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nFB_BURST : IN std_logic;
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FB_ADR : IN std_logic_vector(31 DOWNTO 0);
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nRSTO : IN std_logic;
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nFB_CS3 : IN std_logic;
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nSRCS : INOUT std_logic;
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nSRBLE : OUT std_logic;
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nSRBHE : OUT std_logic;
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nSRWE : OUT std_logic;
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nSROE : OUT std_logic;
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DSP_INT : OUT std_logic;
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DSP_TA : OUT std_logic;
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fb_ad_in : in std_logic_vector(31 downto 0);
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fb_ad_out : out std_logic_vector(31 downto 0);
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IO : INOUT std_logic_vector(17 DOWNTO 0);
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SRD : INOUT std_logic_vector(15 DOWNTO 0)
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);
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-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
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END dsp;
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-- Architecture Body
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ARCHITECTURE rtl OF dsp IS
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BEGIN
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nSRCS <= '0' WHEN nFB_CS2 = '0' AND FB_ADR(27 DOWNTO 24) = x"4" ELSE '1'; --nFB_CS3;
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nSRBHE <= '0' WHEN FB_ADR(0 DOWNTO 0) = "0" ELSE '1';
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nSRBLE <= '1' WHEN FB_ADR(0 DOWNTO 0) = "0" AND FB_SIZE1 = '0' AND FB_SIZE0 = '1' ELSE '0';
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nSRWE <= '0' WHEN nFB_WR = '0' AND nSRCS = '0' AND MAIN_CLK = '0' ELSE '1';
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nSROE <= '0' WHEN nFB_OE = '0' AND nSRCS = '0' ELSE '1';
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DSP_INT <= '0';
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DSP_TA <= '0';
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IO(17 DOWNTO 0) <= FB_ADR(18 DOWNTO 1);
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SRD(15 DOWNTO 0) <= fb_ad_in(31 DOWNTO 16) WHEN nFB_WR = '0' AND nSRCS = '0' ELSE (others => 'Z');
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-- fb_ad_out(31 DOWNTO 16) <= SRD(15 DOWNTO 0) WHEN nFB_OE = '0' AND nSRCS = '0' ELSE (others => 'Z');
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fb_ad_out(31 downto 0) <= (others => 'Z'); -- otherwise we get a constant driver error
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END rtl;
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