48 lines
1.4 KiB
VHDL
48 lines
1.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity blitter is
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port
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(
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nRSTO : in std_logic;
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MAIN_CLK : in std_logic;
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FB_ALE : in std_logic;
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nFB_WR : in std_logic;
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nFB_OE : in std_logic;
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FB_SIZE0 : in std_logic;
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FB_SIZE1 : in std_logic;
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VIDEO_RAM_CTR : in std_logic_vector(15 downto 0);
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BLITTER_ON : in std_logic;
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FB_ADR : in std_logic_vector(31 downto 0);
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nFB_CS1 : in std_logic;
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nFB_CS2 : in std_logic;
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nFB_CS3 : in std_logic;
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DDRCLK0 : in std_logic;
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BLITTER_DIN : in std_logic_vector(127 downto 0);
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BLITTER_DACK : in std_logic_vector(4 downto 0);
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SR_BLITTER_DACK : in std_logic;
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blitter_run : out std_logic;
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blitter_dout : out std_logic_vector(127 downto 0);
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blitter_adr : out std_logic_vector(31 downto 0);
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blitter_sig : out std_logic;
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blitter_wr : out std_logic;
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blitter_ta : out std_logic;
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fb_ad_in : in std_logic_vector(31 downto 0);
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fb_ad_out : out std_logic_vector(31 downto 0)
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);
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end BLITTER;
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architecture rtl of blitter is
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begin
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blitter_run <= '0';
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blitter_dout <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0";
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blitter_adr <= x"76543210";
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blitter_sig <= '0';
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blitter_wr <= '0';
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blitter_ta <= '0';
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fb_ad_out <= (others => 'Z');
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end rtl;
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