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Sync with Fredi's source tree 15/04/2017

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IDE and Blitter work.
This commit is contained in:
David Gálvez
2018-04-09 17:21:35 +02:00
parent 68129dbe57
commit b2d17efff1
97 changed files with 9395 additions and 9114 deletions
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2
FPGA_by_Fredi/.sopc_builder/filters.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<filters version="9.1sp2" />

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FPGA_by_Fredi/.sopc_builder/preferences.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<preferences>
<systemtable>
<columns>
<connections preferredWidth="30" />
<export visible="0" />
<irq preferredWidth="34" />
</columns>
</systemtable>
<clocktable>
<columns>
<clockname preferredWidth="138" />
<clocksource preferredWidth="138" />
<frequency preferredWidth="119" />
</columns>
</clocktable>
<window width="900" height="600" x="0" y="0" />
</preferences>

314
FPGA_by_Fredi/BLITTER.tdf
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-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2010 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
-- Created on Sat Jan 15 11:06:17 2011
INCLUDE "lpm_bustri_WORD.inc";
INCLUDE "VIDEO/BLITTER/lpm_clshift0.INC";
INCLUDE "VIDEO/BLITTER/altsyncram0.INC";
CONSTANT BL_SKEW_LF = 255;
-- Title Statement (optional)
TITLE "Blitter";
-- Parameters Statement (optional)
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-- Subdesign Section
SUBDESIGN BLITTER
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
nRSTO : INPUT;
MAIN_CLK : INPUT;
FB_ALE : INPUT;
nFB_WR : INPUT;
nFB_OE : INPUT;
FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT;
VIDEO_RAM_CTR[15..0] : INPUT;
BLITTER_ON : INPUT;
FB_ADR[31..0] : INPUT;
nFB_CS1 : INPUT;
nFB_CS2 : INPUT;
nFB_CS3 : INPUT;
DDRCLK0 : INPUT;
BLITTER_DIN[127..0] : INPUT;
BLITTER_DACK[4..0] : INPUT;
SR_BLITTER_DACK : INPUT;
BLITTER_RUN : OUTPUT;
BLITTER_DOUT[127..0] : OUTPUT;
BLITTER_ADR[31..0] : OUTPUT;
BLITTER_SIG : OUTPUT;
BLITTER_WR : OUTPUT;
BLITTER_TA : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
VARIABLE
FB_B[3..0] :NODE;
FB_16B[1..0] :NODE;
BLITTER_CS :NODE;
BL_BUSY :NODE;
BL_HRAM_CS :NODE;
BL_HRAM_ADR[3..0] :NODE;
BL_HRAM_OUT[15..0] :NODE;
BL_HRAM_BE[1..0] :NODE;
BL_SRC_X_INC_CS :NODE;
BL_SRC_X_INC[15..0] :DFFE;
BL_SRC_Y_INC_CS :NODE;
BL_SRC_Y_INC[15..0] :DFFE;
BL_ENDMASK1_CS :NODE;
BL_ENDMASK1[15..0] :DFFE;
BL_ENDMASK2_CS :NODE;
BL_ENDMASK2[15..0] :DFFE;
BL_ENDMASK3_CS :NODE;
BL_ENDMASK3[15..0] :DFFE;
BL_SRC_ADRH_CS :NODE;
BL_SRC_ADRL_CS :NODE;
BL_SRC_ADR[31..0] :DFFE;
BL_DST_X_INC_CS :NODE;
BL_DST_X_INC[15..0] :DFFE;
BL_DST_Y_INC_CS :NODE;
BL_DST_Y_INC[15..0] :DFFE;
BL_DST_ADRH_CS :NODE;
BL_DST_ADRL_CS :NODE;
BL_DST_ADR[31..0] :DFFE;
BL_X_CNT_CS :NODE;
BL_X_CNT[15..0] :DFFE;
BL_Y_CNT_CS :NODE;
BL_Y_CNT[15..0] :DFFE;
BL_HT_OP_CS :NODE;
BL_HT_OP[7..0] :DFFE;
BL_LC_OP[7..0] :DFFE;
BL_LN_CS :NODE;
BL_LN[7..0] :DFFE;
BL_SKEW[7..0] :DFFE;
BL_SKEW_EXT[6..0] :NODE;
BL_SKEW_IN[255..0] :DFFE;
BL_SKEW_OUT[255..0] :NODE;
BL_DATA_DDR_READY :DFF; -- 1 WENN DATEN GESCHRIEBEN ODER LESBAR
BL_READ_SRC :DFFE;
BL_DST_BUFFER[127..0] :DFFE;
BL_READ_DST :DFFE;
HOP_OUT[127..0] :NODE;
COUNT[18..0] :DFF;
BEGIN
-- BYT SELECT 32 BIT
FB_B0 = FB_ADR[1..0]==0; -- ADR==0
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- BYT SELECT 16 BIT
FB_16B0 = FB_ADR[0]==0; -- ADR==0
FB_16B1 = FB_ADR[0]==1 -- ADR==1
# !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT
-- BLITTER CS
BLITTER_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..6]==H"3E28"; -- FFFF8A00-3F/40
BLITTER_TA = BLITTER_CS;
-- REGISTER
-- HALFTON RAM
BL_HRAM_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..5]==H"7C50"; -- $F8A00/20
BL_HRAM_BE1 = BL_HRAM_CS & FB_16B0 # !BL_HRAM_CS;
BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1 # !BL_HRAM_CS;
BL_HRAM_ADR[] = BL_HRAM_CS & FB_ADR[4..1]
# !BL_HRAM_CS & BL_LN[3..0];
BL_HRAM_OUT[] = altsyncram0(BL_HRAM_ADR[],BL_HRAM_BE[],DDRCLK0,FB_AD[31..16],BL_HRAM_CS & !nFB_WR);
-- SRC X INC
BL_SRC_X_INC[].CLK = MAIN_CLK;
BL_SRC_X_INC[] = !BL_BUSY & FB_AD[31..16];
BL_SRC_X_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C510"; -- $F8A20/2
BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_X_INC[7..0].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
-- SRC Y INC
BL_SRC_Y_INC[].CLK = MAIN_CLK;
BL_SRC_Y_INC[] = !BL_BUSY & FB_AD[31..16];
BL_SRC_Y_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C511"; -- $F8A22/2
BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_Y_INC[7..0].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
-- SRC ADR HIGH
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[31..16] = !BL_BUSY & FB_AD[31..16];
BL_SRC_ADRH_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C512"; -- $F8A24/2
BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
-- SRC ADR LOW
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[15..0] = !BL_BUSY & FB_AD[31..16];
BL_SRC_ADRL_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C513"; -- $F8A26/2
BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[7..0].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
-- ENDMASK 1
BL_ENDMASK1[].CLK = MAIN_CLK;
BL_ENDMASK1[] = FB_AD[31..16];
BL_ENDMASK1_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C514"; -- $F8A28/2
BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
BL_ENDMASK1[7..0].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
-- ENDMASK 2
BL_ENDMASK2[].CLK = MAIN_CLK;
BL_ENDMASK2[] = FB_AD[31..16];
BL_ENDMASK2_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C515"; -- $F8A2A/2
BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
BL_ENDMASK2[7..0].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
-- ENDMASK 3
BL_ENDMASK3[].CLK = MAIN_CLK;
BL_ENDMASK3[] = FB_AD[31..16];
BL_ENDMASK3_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C516"; -- $F8A2C/2
BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
BL_ENDMASK3[7..0].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
-- DST X INC
BL_DST_X_INC[].CLK = MAIN_CLK;
BL_DST_X_INC[] = !BL_BUSY & FB_AD[31..16];
BL_DST_X_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C517"; -- $F8A2E/2
BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
BL_DST_X_INC[7..0].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
-- DST Y INC
BL_DST_Y_INC[].CLK = MAIN_CLK;
BL_DST_Y_INC[] = !BL_BUSY & FB_AD[31..16];
BL_DST_Y_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C518"; -- $F8A30/2
BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
BL_DST_Y_INC[7..0].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
-- DST ADR HIGH
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[31..16] = !BL_BUSY & FB_AD[31..16];
BL_DST_ADRH_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C512"; -- $F8A24/2
BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
-- DST ADR LOW
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[15..0] = !BL_BUSY & FB_AD[31..16];
BL_DST_ADRL_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C513"; -- $F8A26/2
BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[7..0].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
-- X COUNT
BL_X_CNT[].CLK = MAIN_CLK;
BL_X_CNT[] = !BL_BUSY & FB_AD[31..16];
BL_X_CNT_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51B"; -- $F8A36/2
BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
BL_X_CNT[7..0].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B1;
-- Y COUNT
BL_Y_CNT[].CLK = MAIN_CLK;
BL_Y_CNT[] = !BL_BUSY & FB_AD[31..16];
BL_Y_CNT_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51C"; -- $F8A38/2
BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
BL_Y_CNT[7..0].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
-- HALFTONE OP BYT
BL_HT_OP[].CLK = MAIN_CLK;
BL_HT_OP[] = FB_AD[31..24];
BL_HT_OP_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51D"; -- $F8A3A/2
BL_HT_OP[7..0].ENA = BL_HT_OP_CS & !nFB_WR & FB_16B0;
-- LOGIC OP BYT
BL_LC_OP[].CLK = MAIN_CLK;
BL_LC_OP[] = FB_AD[23..16];
BL_LC_OP[7..0].ENA = BL_HT_OP_CS & !nFB_WR & FB_16B1; -- $F8A3B
-- LINE NUMBER BYT
BL_LN[].CLK = MAIN_CLK;
BL_LN[] = !BL_BUSY & FB_AD[31..24];
BL_LN_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51E"; -- $F8A3C/2
BL_LN[7..0].ENA = BL_LN_CS & !nFB_WR & FB_16B0;
-- SKEW BYT
BL_SKEW[].CLK = MAIN_CLK;
BL_SKEW[] = FB_AD[31..24];
BL_SKEW[7..0].ENA = BL_LN_CS & !nFB_WR & FB_16B1; -- $F8A3D
--- REGISTER OUT
FB_AD[31..16] = lpm_bustri_WORD(
BL_HRAM_CS & BL_HRAM_OUT[]
# BL_SRC_X_INC_CS & BL_SRC_X_INC[]
# BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
# BL_SRC_ADRH_CS & BL_SRC_ADR[31..16]
# BL_SRC_ADRL_CS & BL_SRC_ADR[15..0]
# BL_ENDMASK1_CS & BL_ENDMASK1[]
# BL_ENDMASK2_CS & BL_ENDMASK2[]
# BL_ENDMASK3_CS & BL_ENDMASK3[]
# BL_DST_X_INC_CS & BL_DST_X_INC[]
# BL_DST_Y_INC_CS & BL_DST_Y_INC[]
# BL_DST_ADRH_CS & BL_DST_ADR[31..16]
# BL_DST_ADRL_CS & BL_DST_ADR[15..0]
# BL_X_CNT_CS & BL_X_CNT[]
# BL_Y_CNT_CS & BL_Y_CNT[]
# BL_HT_OP_CS & (BL_HT_OP[],BL_LC_OP[])
# BL_LN_CS & (BL_LN[],BL_SKEW[])
,BLITTER_CS & !nFB_OE); -- FFFF8A00-3F/40
-----------------------------------------
--
BL_READ_SRC.CLK = DDRCLK0;
BL_READ_DST.CLK = DDRCLK0;
-- READY SIGNAL 1 CLOCK SP<53>TER
BL_DATA_DDR_READY.CLK = DDRCLK0;
BL_DATA_DDR_READY = BL_DATA_DDR_READY & BLITTER_DACK0;
-- SRC BUFFER LADEN
BL_SKEW_IN[].CLK = DDRCLK0;
BL_SKEW_IN[].ENA = BL_DATA_DDR_READY & BL_READ_SRC;
BL_SKEW_IN[255..128] = BLITTER_DIN[];
BL_SKEW_IN[127..0] = BL_SKEW_IN[255..128];
-- DST BUFFER LADEN
BL_DST_BUFFER[].CLK = DDRCLK0;
BL_DST_BUFFER[].ENA = BL_DATA_DDR_READY & BL_READ_DST;
BL_DST_BUFFER[] = BLITTER_DIN[];
-- SKEW EXTENDET
BL_SKEW_EXT[6..4] = BL_SRC_ADR[3..1];
BL_SKEW_EXT[3..0] = BL_SKEW[3..0];
-- SKEW EXT MUX
BL_SKEW_OUT[] = lpm_clshift0(BL_SKEW_IN[],BL_SKEW_EXT[]); -- BIT 127..0 SIND RELEVANT
-- HOP
IF BL_HT_OP[1..0]==B"00" THEN
HOP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
ELSE
IF BL_HT_OP[1..0]==B"01" THEN
HOP_OUT[] = (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]);
ELSE
IF BL_HT_OP[1..0]==B"10" THEN
HOP_OUT[] = BL_SKEW_OUT[127..0];
ELSE
HOP_OUT[] = BL_SKEW_OUT[127..0] & (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]);
END IF;
END IF;
END IF;
BLITTER_RUN = GND; --VCC;
BLITTER_SIG = GND; --VCC;
BLITTER_WR = GND; --VCC;
BL_BUSY = GND;
COUNT[] = COUNT[] + 16;
COUNT[].CLK = BLITTER_DACK0;
BLITTER_DOUT[] = H"112233445566778899AABBCCDDEEFF00";
BLITTER_ADR[] = (0, COUNT[]) + 400000;
END;

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FPGA_by_Fredi/BLITTER.tdf.bak
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@@ -1,313 +0,0 @@
-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2010 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
-- Created on Sat Jan 15 11:06:17 2011
INCLUDE "lpm_bustri_WORD.inc";
INCLUDE "VIDEO/BLITTER/lpm_clshift0.INC";
INCLUDE "VIDEO/BLITTER/altsyncram0.INC";
CONSTANT BL_SKEW_LF = 255;
-- Title Statement (optional)
TITLE "Blitter";
-- Parameters Statement (optional)
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-- Subdesign Section
SUBDESIGN BLITTER
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
nRSTO : INPUT;
MAIN_CLK : INPUT;
FB_ALE : INPUT;
nFB_WR : INPUT;
nFB_OE : INPUT;
FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT;
VIDEO_RAM_CTR[15..0] : INPUT;
BLITTER_ON : INPUT;
FB_ADR[31..0] : INPUT;
nFB_CS1 : INPUT;
nFB_CS2 : INPUT;
nFB_CS3 : INPUT;
DDRCLK0 : INPUT;
BLITTER_DIN[127..0] : INPUT;
BLITTER_DACK[4..0] : INPUT;
SR_BLITTER_DACK : INPUT;
BLITTER_RUN : OUTPUT;
BLITTER_DOUT[127..0] : OUTPUT;
BLITTER_ADR[31..0] : OUTPUT;
BLITTER_SIG : OUTPUT;
BLITTER_WR : OUTPUT;
BLITTER_TA : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
VARIABLE
FB_B[3..0] :NODE;
FB_16B[1..0] :NODE;
BLITTER_CS :NODE;
BL_BUSY :NODE;
BL_HRAM_CS :NODE;
BL_HRAM_ADR[3..0] :NODE;
BL_HRAM_OUT[15..0] :NODE;
BL_HRAM_BE[1..0] :NODE;
BL_SRC_X_INC_CS :NODE;
BL_SRC_X_INC[15..0] :DFFE;
BL_SRC_Y_INC_CS :NODE;
BL_SRC_Y_INC[15..0] :DFFE;
BL_ENDMASK1_CS :NODE;
BL_ENDMASK1[15..0] :DFFE;
BL_ENDMASK2_CS :NODE;
BL_ENDMASK2[15..0] :DFFE;
BL_ENDMASK3_CS :NODE;
BL_ENDMASK3[15..0] :DFFE;
BL_SRC_ADRH_CS :NODE;
BL_SRC_ADRL_CS :NODE;
BL_SRC_ADR[31..0] :DFFE;
BL_DST_X_INC_CS :NODE;
BL_DST_X_INC[15..0] :DFFE;
BL_DST_Y_INC_CS :NODE;
BL_DST_Y_INC[15..0] :DFFE;
BL_DST_ADRH_CS :NODE;
BL_DST_ADRL_CS :NODE;
BL_DST_ADR[31..0] :DFFE;
BL_X_CNT_CS :NODE;
BL_X_CNT[15..0] :DFFE;
BL_Y_CNT_CS :NODE;
BL_Y_CNT[15..0] :DFFE;
BL_HT_OP_CS :NODE;
BL_HT_OP[7..0] :DFFE;
BL_LC_OP[7..0] :DFFE;
BL_LN_CS :NODE;
BL_LN[7..0] :DFFE;
BL_SKEW[7..0] :DFFE;
BL_SKEW_EXT[6..0] :NODE;
BL_SKEW_IN[255..0] :DFFE;
BL_SKEW_OUT[255..0] :NODE;
BL_DATA_DDR_READY :DFF; -- 1 WENN DATEN GESCHRIEBEN ODER LESBAR
BL_READ_SRC :DFFE;
BL_DST_BUFFER[127..0] :DFFE;
BL_READ_DST :DFFE;
HOP_OUT[127..0] :NODE;
COUNT[18..0] :DFF;
BEGIN
-- BYT SELECT 32 BIT
FB_B0 = FB_ADR[1..0]==0; -- ADR==0
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- BYT SELECT 16 BIT
FB_16B0 = FB_ADR[0]==0; -- ADR==0
FB_16B1 = FB_ADR[0]==1 -- ADR==1
# !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT
-- BLITTER CS
BLITTER_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..6]==H"3E28"; -- FFFF8A00-3F/40
BLITTER_TA = BLITTER_CS;
-- REGISTER
-- HALFTON RAM
BL_HRAM_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..5]==H"7C50"; -- $F8A00/20
BL_HRAM_BE1 = BL_HRAM_CS & FB_16B0 # !BL_HRAM_CS;
BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1 # !BL_HRAM_CS;
BL_HRAM_ADR[] = BL_HRAM_CS & FB_ADR[4..1]
# !BL_HRAM_CS & BL_LN[3..0];
BL_HRAM_OUT[] = altsyncram0(BL_HRAM_ADR[],BL_HRAM_BE[],DDRCLK0,FB_AD[31..16],BL_HRAM_CS & !nFB_WR);
-- SRC X INC
BL_SRC_X_INC[].CLK = MAIN_CLK;
BL_SRC_X_INC[] = !BL_BUSY & FB_AD[31..16];
BL_SRC_X_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C510"; -- $F8A20/2
BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_X_INC[7..0].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
-- SRC Y INC
BL_SRC_Y_INC[].CLK = MAIN_CLK;
BL_SRC_Y_INC[] = !BL_BUSY & FB_AD[31..16];
BL_SRC_Y_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C511"; -- $F8A22/2
BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_Y_INC[7..0].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
-- SRC ADR HIGH
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[31..16] = !BL_BUSY & FB_AD[31..16];
BL_SRC_ADRH_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C512"; -- $F8A24/2
BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
-- SRC ADR LOW
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[15..0] = !BL_BUSY & FB_AD[31..16];
BL_SRC_ADRL_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C513"; -- $F8A26/2
BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[7..0].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
-- ENDMASK 1
BL_ENDMASK1[].CLK = MAIN_CLK;
BL_ENDMASK1[] = FB_AD[31..16];
BL_ENDMASK1_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C514"; -- $F8A28/2
BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
BL_ENDMASK1[7..0].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
-- ENDMASK 2
BL_ENDMASK2[].CLK = MAIN_CLK;
BL_ENDMASK2[] = FB_AD[31..16];
BL_ENDMASK2_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C515"; -- $F8A2A/2
BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
BL_ENDMASK2[7..0].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
-- ENDMASK 3
BL_ENDMASK3[].CLK = MAIN_CLK;
BL_ENDMASK3[] = FB_AD[31..16];
BL_ENDMASK3_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C516"; -- $F8A2C/2
BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
BL_ENDMASK3[7..0].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
-- DST X INC
BL_DST_X_INC[].CLK = MAIN_CLK;
BL_DST_X_INC[] = !BL_BUSY & FB_AD[31..16];
BL_DST_X_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C517"; -- $F8A2E/2
BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
BL_DST_X_INC[7..0].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
-- DST Y INC
BL_DST_Y_INC[].CLK = MAIN_CLK;
BL_DST_Y_INC[] = !BL_BUSY & FB_AD[31..16];
BL_DST_Y_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C518"; -- $F8A30/2
BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
BL_DST_Y_INC[7..0].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
-- DST ADR HIGH
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[31..16] = !BL_BUSY & FB_AD[31..16];
BL_DST_ADRH_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C512"; -- $F8A24/2
BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
-- DST ADR LOW
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[15..0] = !BL_BUSY & FB_AD[31..16];
BL_DST_ADRL_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C513"; -- $F8A26/2
BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[7..0].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
-- X COUNT
BL_X_CNT[].CLK = MAIN_CLK;
BL_X_CNT[] = !BL_BUSY & FB_AD[31..16];
BL_X_CNT_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51B"; -- $F8A36/2
BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
BL_X_CNT[7..0].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B1;
-- Y COUNT
BL_Y_CNT[].CLK = MAIN_CLK;
BL_Y_CNT[] = !BL_BUSY & FB_AD[31..16];
BL_Y_CNT_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51C"; -- $F8A38/2
BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
BL_Y_CNT[7..0].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
-- HALFTONE OP BYT
BL_HT_OP[].CLK = MAIN_CLK;
BL_HT_OP[] = FB_AD[31..24];
BL_HT_OP_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51D"; -- $F8A3A/2
BL_HT_OP[7..0].ENA = BL_HT_OP_CS & !nFB_WR & FB_16B0;
-- LOGIC OP BYT
BL_LC_OP[].CLK = MAIN_CLK;
BL_LC_OP[] = FB_AD[23..16];
BL_LC_OP[7..0].ENA = BL_HT_OP_CS & !nFB_WR & FB_16B1; -- $F8A3B
-- LINE NUMBER BYT
BL_LN[].CLK = MAIN_CLK;
BL_LN[] = !BL_BUSY & FB_AD[31..24];
BL_LN_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51E"; -- $F8A3C/2
BL_LN[7..0].ENA = BL_LN_CS & !nFB_WR & FB_16B0;
-- SKEW BYT
BL_SKEW[].CLK = MAIN_CLK;
BL_SKEW[] = FB_AD[31..24];
BL_SKEW[7..0].ENA = BL_LN_CS & !nFB_WR & FB_16B1; -- $F8A3D
--- REGISTER OUT
FB_AD[31..16] = lpm_bustri_WORD(
BL_HRAM_CS & BL_HRAM_OUT[]
# BL_SRC_X_INC_CS & BL_SRC_X_INC[]
# BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
# BL_SRC_ADRH_CS & BL_SRC_ADR[31..16]
# BL_SRC_ADRL_CS & BL_SRC_ADR[15..0]
# BL_ENDMASK1_CS & BL_ENDMASK1[]
# BL_ENDMASK2_CS & BL_ENDMASK2[]
# BL_ENDMASK3_CS & BL_ENDMASK3[]
# BL_DST_X_INC_CS & BL_DST_X_INC[]
# BL_DST_Y_INC_CS & BL_DST_Y_INC[]
# BL_DST_ADRH_CS & BL_DST_ADR[31..16]
# BL_DST_ADRL_CS & BL_DST_ADR[15..0]
# BL_X_CNT_CS & BL_X_CNT[]
# BL_Y_CNT_CS & BL_Y_CNT[]
# BL_HT_OP_CS & (BL_HT_OP[],BL_LC_OP[])
# BL_LN_CS & (BL_LN[],BL_SKEW[])
,BLITTER_CS & !nFB_OE); -- FFFF8A00-3F/40
-----------------------------------------
--
BL_READ_SRC.CLK = DDRCLK0;
BL_READ_DST.CLK = DDRCLK0;
-- READY SIGNAL 1 CLOCK SP<53>TER
BL_DATA_DDR_READY.CLK = DDRCLK0;
BL_DATA_DDR_READY = BL_DATA_DDR_READY & BLITTER_DACK0;
-- SRC BUFFER LADEN
BL_SKEW_IN[].CLK = DDRCLK0;
BL_SKEW_IN[].ENA = BL_DATA_DDR_READY & BL_READ_SRC;
BL_SKEW_IN[255..128] = BLITTER_DIN[];
BL_SKEW_IN[127..0] = BL_SKEW_IN[255..128];
-- DST BUFFER LADEN
BL_DST_BUFFER[].CLK = DDRCLK0;
BL_DST_BUFFER[].ENA = BL_DATA_DDR_READY & BL_READ_DST;
BL_DST_BUFFER[] = BLITTER_DIN[];
-- SKEW EXTENDET
BL_SKEW_EXT[6..4] = BL_SRC_ADR[3..1];
BL_SKEW_EXT[3..0] = BL_SKEW[3..0];
-- SKEW EXT MUX
BL_SKEW_OUT[] = lpm_clshift0(BL_SKEW_IN[],BL_SKEW_EXT[]); -- BIT 127..0 SIND RELEVANT
-- HOP
IF BL_HT_OP[1..0]==B"00" THEN
HOP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
ELSE
IF BL_HT_OP[1..0]==B"01" THEN
HOP_OUT[] = (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]);
ELSE
IF BL_HT_OP[1..0]==B"10" THEN
HOP_OUT[] = BL_SKEW_OUT[127..0];
ELSE
HOP_OUT[] = BL_SKEW_OUT[127..0] & (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]);
END IF;
END IF;
END IF;
BLITTER_RUN = gnd; --VCC;
BLITTER_SIG = gnd; --VCC;
BLITTER_WR = gnd; --VCC;
COUNT[] = COUNT[] + 16;
COUNT[].CLK = BLITTER_DACK0;
BLITTER_DOUT[] = H"112233445566778899AABBCCDDEEFF00";
BLITTER_ADR[] = (0, COUNT[]) + 400000;
END;

42
FPGA_by_Fredi/FPGA_DATE.bsf Normal file
View File

@@ -0,0 +1,42 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 88 48)
(text "FPGA_DATE" (rect 6 1 96 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 32 25 44)(font "Arial" ))
(port
(pt 88 24)
(output)
(text "result[31..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "result[31..0]" (rect 85 -31 98 24)(font "Arial" (font_size 8))(invisible))
(line (pt 88 24)(pt 72 24)(line_width 3))
)
(drawing
(text "319037463" (rect 27 18 72 30)(font "Arial" ))
(text "32" (rect 77 25 87 37)(font "Arial" ))
(line (pt 16 16)(pt 72 16)(line_width 1))
(line (pt 72 16)(pt 72 32)(line_width 1))
(line (pt 72 32)(pt 16 32)(line_width 1))
(line (pt 16 32)(pt 16 16)(line_width 1))
(line (pt 72 28)(pt 80 20)(line_width 1))
)
)

7
FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.inc → FPGA_by_Fredi/FPGA_DATE.inc
View File

@@ -13,12 +13,11 @@
--applicable agreement for further details. --applicable agreement for further details.
FUNCTION lpm_clshift0 FUNCTION FPGA_DATE
( (
data[255..0],
distance[6..0]
) )
RETURNS ( RETURNS (
result[255..0] result[31..0]
); );

5
FPGA_by_Fredi/FPGA_DATE.qip Normal file
View File

@@ -0,0 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "FPGA_DATE.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "FPGA_DATE.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "FPGA_DATE.inc"]

79
FPGA_by_Fredi/FPGA_DATE.tdf Normal file
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@@ -0,0 +1,79 @@
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_constant
-- ============================================================
-- File Name: FPGA_DATE.tdf
-- Megafunction Name(s):
-- lpm_constant
--
-- Simulation Library Files(s):
--
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
-- Clearbox generated function header
FUNCTION FPGA_DATE_lpm_constant_d19 ()
RETURNS ( result[31..0]);
SUBDESIGN FPGA_DATE
(
result[31..0] : OUTPUT;
)
VARIABLE
FPGA_DATE_lpm_constant_d19_component : FPGA_DATE_lpm_constant_d19;
BEGIN
result[31..0] = FPGA_DATE_lpm_constant_d19_component.result[31..0];
END;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: Radix NUMERIC "16"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "319037463"
-- Retrieval info: PRIVATE: nBit NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "319037463"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL FPGA_DATE.tdf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FPGA_DATE.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FPGA_DATE.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FPGA_DATE.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FPGA_DATE_inst.tdf FALSE

30
FPGA_by_Fredi/FPGA_DATE_lpm_constant_d19.tdf Normal file
View File

@@ -0,0 +1,30 @@
--lpm_constant CBX_AUTO_BLACKBOX="ALL" ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=13042017 LPM_WIDTH=32 result
--VERSION_BEGIN 9.1SP2 cbx_lpm_constant 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ VERSION_END
-- Copyright (C) 1991-2010 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources =
SUBDESIGN FPGA_DATE_lpm_constant_d19
(
result[31..0] : output;
)
BEGIN
result[] = B"00010011000001000010000000010111";
END;
--VALID FILE

221
FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
View File

@@ -42,6 +42,7 @@ ENTITY FalconIO_SDCard_IDE_CF IS
CLK2M : IN STD_LOGIC; CLK2M : IN STD_LOGIC;
CLK500k : IN STD_LOGIC; CLK500k : IN STD_LOGIC;
nFB_CS1 : IN STD_LOGIC; nFB_CS1 : IN STD_LOGIC;
nFB_CS3 : IN STD_LOGIC;
FB_SIZE0 : IN STD_LOGIC; FB_SIZE0 : IN STD_LOGIC;
FB_SIZE1 : IN STD_LOGIC; FB_SIZE1 : IN STD_LOGIC;
nFB_BURST : IN STD_LOGIC; nFB_BURST : IN STD_LOGIC;
@@ -83,11 +84,12 @@ ENTITY FalconIO_SDCard_IDE_CF IS
nFB_OE : IN STD_LOGIC; nFB_OE : IN STD_LOGIC;
VSYNC : IN STD_LOGIC; VSYNC : IN STD_LOGIC;
HSYNC : IN STD_LOGIC; HSYNC : IN STD_LOGIC;
BLITTER_INT : IN STD_LOGIC;
DSP_INT : IN STD_LOGIC; DSP_INT : IN STD_LOGIC;
nBLANK : IN STD_LOGIC; nBLANK : IN STD_LOGIC;
FDC_CLK : IN STD_LOGIC; FDC_CLK : IN STD_LOGIC;
FB_ALE : IN STD_LOGIC; FB_ALE : IN STD_LOGIC;
ACP_CONF : IN STD_LOGIC_VECTOR(31 downto 24); ACP_CONF : IN STD_LOGIC_VECTOR(31 downto 0);
nIDE_CS1 : OUT STD_LOGIC; nIDE_CS1 : OUT STD_LOGIC;
nIDE_CS0 : OUT STD_LOGIC; nIDE_CS0 : OUT STD_LOGIC;
LP_STR : OUT STD_LOGIC; LP_STR : OUT STD_LOGIC;
@@ -132,7 +134,6 @@ ENTITY FalconIO_SDCard_IDE_CF IS
DMA_DRQ : OUT STD_LOGIC; DMA_DRQ : OUT STD_LOGIC;
FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0); FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0); LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
SND_A : INOUT STD_LOGIC_VECTOR(7 downto 0);
ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0); ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0); SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
SCSI_PAR : INOUT STD_LOGIC; SCSI_PAR : INOUT STD_LOGIC;
@@ -140,7 +141,8 @@ ENTITY FalconIO_SDCard_IDE_CF IS
nSCSI_BUSY : INOUT STD_LOGIC; nSCSI_BUSY : INOUT STD_LOGIC;
nSCSI_RST : INOUT STD_LOGIC; nSCSI_RST : INOUT STD_LOGIC;
SD_CD_DATA3 : INOUT STD_LOGIC; SD_CD_DATA3 : INOUT STD_LOGIC;
SD_CDM_D1 : INOUT STD_LOGIC SD_CDM_D1 : INOUT STD_LOGIC;
VIDEO_TA : IN STD_LOGIC
); );
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
@@ -156,7 +158,7 @@ signal RESETn : STD_LOGIC;
signal FB_B0 : STD_LOGIC; -- UPPER BYT BEI 16BIT BUS signal FB_B0 : STD_LOGIC; -- UPPER BYT BEI 16BIT BUS
signal FB_B1 : STD_LOGIC; -- LOWER BYT BEI 16BIT BUS signal FB_B1 : STD_LOGIC; -- LOWER BYT BEI 16BIT BUS
signal BYT : STD_LOGIC; -- WENN BYT -> 1 signal BYT : STD_LOGIC; -- WENN BYT -> 1
signal LONG : STD_LOGIC; -- WENN -> 1 signal LONG : STD_LOGIC; -- WENN Long -> 1
signal FB_ADI : STD_LOGIC_VECTOR(15 downto 0); -- gespeicherte writedaten signal FB_ADI : STD_LOGIC_VECTOR(15 downto 0); -- gespeicherte writedaten
signal nResetatio : STD_LOGIC; -- reset atari bausteine signal nResetatio : STD_LOGIC; -- reset atari bausteine
-- KEYBOARD MIDI -- KEYBOARD MIDI
@@ -184,7 +186,6 @@ signal SNDCS_I : STD_LOGIC;
signal SNDIR_I : STD_LOGIC; signal SNDIR_I : STD_LOGIC;
signal LP_DIR_X : STD_LOGIC; signal LP_DIR_X : STD_LOGIC;
signal DA_OUT_X : STD_LOGIC_VECTOR(7 downto 0); signal DA_OUT_X : STD_LOGIC_VECTOR(7 downto 0);
signal SND_A_X : STD_LOGIC_VECTOR(7 downto 0);
signal LP_D_X : STD_LOGIC_VECTOR(7 downto 0); signal LP_D_X : STD_LOGIC_VECTOR(7 downto 0);
signal nLP_STR : STD_LOGIC; signal nLP_STR : STD_LOGIC;
-- DMA SOUND -- DMA SOUND
@@ -278,10 +279,11 @@ signal SEL_EN : STD_LOGIC;
-- IDE -- IDE
signal nnIDE_RES : STD_LOGIC; signal nnIDE_RES : STD_LOGIC;
signal IDE_CF_CS : STD_LOGIC; signal IDE_CF_CS : STD_LOGIC;
signal IDE_CF_TA : STD_LOGIC; signal IDE_DRIVE0 : STD_LOGIC;
signal NEXT_nIDE_RD : STD_LOGIC; signal IDE_DRIVE1 : STD_LOGIC;
signal NEXT_nIDE_WR : STD_LOGIC; signal IDE_DCS : STD_LOGIC;
type CMD_STATES is( IDLE, T1, T6, T7); signal IDE_TA : STD_LOGIC;
type CMD_STATES is(IDLE,T1,T2,T3,T4,T5,T6,T7,T8,T9);
signal CMD_STATE : CMD_STATES; signal CMD_STATE : CMD_STATES;
signal NEXT_CMD_STATE : CMD_STATES; signal NEXT_CMD_STATE : CMD_STATES;
-- Paddle -- Paddle
@@ -294,13 +296,13 @@ FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0';
FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0'; FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0';
FALCON_IO_TA <= '1' when ACIA_CS_I = '1' or DTACK_OUT_MFPn = '0' or DMA_MODUS_CS ='1' or dma_snd_cs = '1' or paddle_cs = '1' FALCON_IO_TA <= '1' when ACIA_CS_I = '1' or DTACK_OUT_MFPn = '0' or DMA_MODUS_CS ='1' or dma_snd_cs = '1' or paddle_cs = '1'
or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';--SNDCS = '1' or or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_TA = '1' else '0'; --SNDCS = '1' or
SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE
'1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE '1' when IDE_CF_CS = '1' ELSE
'1' when nFB_WR = '0' and nIDE_WR = '0' ELSE '0'; '1' when nFB_CS3 = '0' ELSE '0';
nRP_UDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B0 = '1' else '1'; nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1';
nRP_LDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B1 = '1' else '1'; nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1';
nDREQ0 <= '0';
-- input daten halten -- input daten halten
process(MAIN_CLK, nFB_WR, FB_AD(31 downto 16), FB_ADI(15 downto 0)) process(MAIN_CLK, nFB_WR, FB_AD(31 downto 16), FB_ADI(15 downto 0))
begin begin
@@ -329,64 +331,145 @@ CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE)
CMD_STATE <= IDLE; CMD_STATE <= IDLE;
elsif rising_edge(MAIN_CLK) then elsif rising_edge(MAIN_CLK) then
CMD_STATE <= NEXT_CMD_STATE; -- go to next CMD_STATE <= NEXT_CMD_STATE; -- go to next
nIDE_RD <= NEXT_nIDE_RD; -- go to next
nIDE_WR <= NEXT_nIDE_WR; -- go to next
else else
CMD_STATE <= CMD_STATE; -- halten CMD_STATE <= CMD_STATE; -- halten
nIDE_RD <= nIDE_RD; -- halten
nIDE_WR <= nIDE_WR; -- halten
end if; end if;
end process CMD_REG; end process CMD_REG;
CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA) CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, nIDE_RD, nIDE_WR, IDE_RDY)
begin begin
case CMD_STATE is case CMD_STATE is
when IDLE => when IDLE =>
IDE_CF_TA <= '0'; IDE_TA <= '0';
if IDE_CF_CS = '1' then nIDE_RD <= '1';
NEXT_nIDE_RD <= not nFB_WR; nIDE_WR <= '1';
NEXT_nIDE_WR <= nFB_WR; if IDE_DCS = '1' then
NEXT_CMD_STATE <= T1; if FB_ADR(6) = '0' then
if ACP_CONF(18 downto 16) = x"1" then
NEXT_CMD_STATE <= T3;
else
if ACP_CONF(18 downto 16) = x"2" then
NEXT_CMD_STATE <= T2;
else
NEXT_CMD_STATE <= T1;
end if;
end if;
else
if ACP_CONF(22 downto 20) = x"1" then
NEXT_CMD_STATE <= T3;
else
if ACP_CONF(22 downto 20) = x"2" then
NEXT_CMD_STATE <= T2;
else
NEXT_CMD_STATE <= T1;
end if;
end if;
end if;
else else
NEXT_nIDE_RD <= '1'; if IDE_CF_CS = '1' then
NEXT_nIDE_WR <= '1'; NEXT_CMD_STATE <= T1;
NEXT_CMD_STATE <= IDLE; else
NEXT_CMD_STATE <= IDLE;
end if;
end if; end if;
when T1 => when T1 =>
IDE_CF_TA <= '0'; IDE_TA <= '0';
NEXT_nIDE_RD <= not nFB_WR; nIDE_RD <= not nFB_WR;
NEXT_nIDE_WR <= nFB_WR; nIDE_WR <= nFB_WR;
NEXT_CMD_STATE <= T6; NEXT_CMD_STATE <= T2;
when T6 => when T2 =>
IF IDE_RDY = '1' then IDE_TA <= '0';
IDE_CF_TA <= '1'; nIDE_RD <= not nFB_WR;
NEXT_nIDE_RD <= '1'; nIDE_WR <= nFB_WR;
NEXT_nIDE_WR <= '1'; NEXT_CMD_STATE <= T3;
NEXT_CMD_STATE <= T7; when T3 =>
nIDE_RD <= not nFB_WR;
nIDE_WR <= nFB_WR;
IF IDE_RDY = '0' then
IDE_TA <= '0';
NEXT_CMD_STATE <= T3;
else else
IDE_CF_TA <= '0'; IDE_TA <= '1';
NEXT_nIDE_RD <= not nFB_WR; NEXT_CMD_STATE <= T5;
NEXT_nIDE_WR <= nFB_WR;
NEXT_CMD_STATE <= T6;
end if; end if;
when T7 => when T4 =>
IDE_CF_TA <= '0'; IDE_TA <= '0';
NEXT_nIDE_RD <= '1'; nIDE_RD <= '1';
NEXT_nIDE_WR <= '1'; nIDE_WR <= '1';
NEXT_CMD_STATE <= IDLE; NEXT_CMD_STATE <= IDLE;
when T5 =>
IDE_TA <= '0';
nIDE_RD <= '1';
nIDE_WR <= '1';
if IDE_DCS = '0' or FB_SIZE0 = '1' or FB_SIZE1 = '1' then -- wenn kein cs oder nicht long ->> fertig
NEXT_CMD_STATE <= T4;
else
if FB_ADR(6) = '0' then
if ACP_CONF(18 downto 16) = x"1" then
NEXT_CMD_STATE <= T9;
else
if ACP_CONF(18 downto 16) = x"2" then
NEXT_CMD_STATE <= T8;
else
NEXT_CMD_STATE <= T6;
end if;
end if;
else
if ACP_CONF(22 downto 20) = x"1" then
NEXT_CMD_STATE <= T9;
else
if ACP_CONF(22 downto 20) = x"2" then
NEXT_CMD_STATE <= T8;
else
NEXT_CMD_STATE <= T6;
end if;
end if;
end if;
end if;
when T6 =>
IDE_TA <= '0';
nIDE_RD <= '1';
nIDE_WR <= '1';
NEXT_CMD_STATE <= T7;
when T7 =>
IDE_TA <= '0';
nIDE_RD <= not nFB_WR;
nIDE_WR <= nFB_WR;
NEXT_CMD_STATE <= T8;
when T8 =>
IDE_TA <= '0';
nIDE_RD <= not nFB_WR;
nIDE_WR <= nFB_WR;
NEXT_CMD_STATE <= T9;
when T9 =>
nIDE_RD <= not nFB_WR;
nIDE_WR <= nFB_WR;
IF IDE_RDY = '0' then
IDE_TA <= '0';
NEXT_CMD_STATE <= T9;
else
IDE_TA <= '1';
NEXT_CMD_STATE <= T4;
end if;
end case; end case;
end process CMD_DECODER; end process CMD_DECODER;
IDE_RES <= not nnIDE_RES and nRSTO; IDE_RES <= not ACP_CONF(25) and nRSTO; -- !!!!ACHTUNG: RESET wenn 0!!!!!!!!!!!!!!! -- IDE_RES manuel oder weil nRSTO
IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0'; -- FFF0'0000/80 IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0'; -- FFF0'0000-FFF0'007F
nCF_CS0 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else -- FFFO'0000-FFF0'001F IDE_DRIVE0 <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 0) = x"99" else '0'; -- FFF0'0099 (19+80!)
'0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; -- FFFO'0040-FFF0'005F IDE_DRIVE1 <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 0) = x"D9" else '0'; -- FFF0'00D9 (19+40+80!)
nCF_CS1 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else -- FFF0'0020-FFF0'003F IDE_DCS <= '1' when FB_ALE = '1' and FB_ADR(31 downto 2) = x"3FFC0000" else -- FFF0'000x 0-3
'0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; -- FFFO'0060-FFF0'007F '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"0" else -- FFF0'000x 0-3
nIDE_CS0 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else -- FFF0'0040-FFF0'005F '1' when FB_ALE = '1' and FB_ADR(31 downto 2) = x"3FFC0010" else -- FFF0'004x 0-3
'0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; -- FFFO'0000-FFF0'001F '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"10" else '0'; -- FFF0'004x 0-3
nIDE_CS1 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else -- FFF0'0060-FFF0'007F nCF_CS0 <= FB_ADR(5) or (FB_ADR(6) xor (ACP_CONF(31) xnor HD_DD)); -- xxxx'xx00-1F
'0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; -- FFFO'0020-FFF0'003F nCF_CS1 <= not FB_ADR(5) or (FB_ADR(6) xor (ACP_CONF(31) xnor HD_DD)); -- xxxx'xx20-3F
nIDE_CS0 <= FB_ADR(5) or (FB_ADR(6) xnor (ACP_CONF(30) xnor HD_DD)); -- xxxx'xx40-5F
nIDE_CS1 <= not FB_ADR(5) or (FB_ADR(6) xnor (ACP_CONF(30) xnor HD_DD)); -- xxxx'xx60-7F
nDREQ0 <= '1';
FB_AD(23 downto 20) <= ACP_CONF(19 downto 16) when IDE_DRIVE0 = '1' and nFB_OE = '0' else "ZZZZ";
FB_AD(23 downto 20) <= ACP_CONF(23 downto 20) when IDE_DRIVE1 = '1' and nFB_OE = '0' else "ZZZZ";
----------------------------------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------------------------------------
-- ACSI, SCSI UND FLOPPY WD1772 -- ACSI, SCSI UND FLOPPY WD1772
------------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------------
@@ -909,7 +992,7 @@ MIDI_OLR <= MIDI_OUT;
GPIP_IN(6) => not RI, GPIP_IN(6) => not RI,
GPIP_IN(5) => DINTn, GPIP_IN(5) => DINTn,
GPIP_IN(4) => acia_irq, GPIP_IN(4) => acia_irq,
GPIP_IN(3) => DSP_INT, GPIP_IN(3) => BLITTER_INT OR DSP_INT,
GPIP_IN(2) => not CTS, GPIP_IN(2) => not CTS,
GPIP_IN(1) => not DCD, GPIP_IN(1) => not DCD,
GPIP_IN(0) => LP_BUSY, GPIP_IN(0) => LP_BUSY,
@@ -948,7 +1031,7 @@ FB_AD(9 downto 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' else "Z
FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ"; FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ";
DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else
'0' when FDINT = '1' else '0' when FDINT = '1' else
'0' when SCSI_INT = '1' AND ACP_CONF(28) = '1' else '1'; '0' when SCSI_INT = '1' AND ACP_CONF(27) = '1' else '1';
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Sound -- Sound
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
@@ -969,8 +1052,15 @@ DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else
DA_IN => FB_ADI(15 downto 8), DA_IN => FB_ADI(15 downto 8),
DA_OUT => DA_OUT_X, DA_OUT => DA_OUT_X,
IO_A_IN => SND_A, IO_A_IN => x"00", -- All port pins are dedicated outputs.
IO_A_OUT => SND_A_X, IO_A_OUT(7) => nnIDE_RES,
IO_A_OUT(6) => LP_DIR_X,
IO_A_OUT(5) => nLP_STR,
IO_A_OUT(4) => DTR,
IO_A_OUT(3) => RTS,
-- IO_A_OUT(2) => FDD_D1SEL,
IO_A_OUT(1) => DSA_D,
IO_A_OUT(0) => nSDSEL,
-- IO_A_EN =>, -- Not required. -- IO_A_EN =>, -- Not required.
IO_B_IN => LP_D, IO_B_IN => LP_D,
IO_B_OUT => LP_D_X, IO_B_OUT => LP_D_X,
@@ -985,18 +1075,9 @@ SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0'; --
SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0'; SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0';
SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0'; SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0';
FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ"; FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ";
nnIDE_RES <= SND_A_X(7);
LP_DIR_X <= SND_A_X(6);
LP_STR <= SND_A_X(5);
DTR <= SND_A_X(4);
RTS <= SND_A_X(3);
-- FDD_D1SEL <= SND_A_X(2)
DSA_D <= SND_A_X(1);
nSDSEL <= SND_A_X(0);
SND_A <= SND_A_X;
LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ"; LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ";
LP_DIR <= LP_DIR_X; LP_DIR <= LP_DIR_X;
LP_STR <= not nLP_STR;
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- DMA Sound register -- DMA Sound register

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@@ -1,406 +0,0 @@
----------------------------------------------------------------------
---- ----
---- Atari Coldfire IP Core ----
---- ----
---- This file is part of the Atari Coldfire project. ----
---- http://www.experiment-s.de ----
---- ----
---- Description: ----
---- ----
---- ----
---- ----
---- ----
---- ----
---- Author(s): ----
---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Wolfgang Foerster ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.gnu.org/licenses/lgpl.html ----
---- ----
----------------------------------------------------------------------
--
-- Revision History
-- 1.0 Initial Release, 20090925.
--
library ieee;
use ieee.std_logic_1164.all;
package FalconIO_SDCard_IDE_CF_PKG is
component WF25915IP_TOP_V1_SOC -- GLUE.
port (
-- Clock system:
GL_CLK : in std_logic; -- Originally 8MHz.
GL_CLK_016 : in std_logic; -- One sixteenth of GL_CLK.
-- Core address select:
GL_ROMSEL_FC_E0n : in std_logic;
EN_RAM_14MB : in std_logic;
-- Adress decoder outputs:
GL_ROM_6n : out std_logic; -- STE.
GL_ROM_5n : out std_logic; -- STE.
GL_ROM_4n : out std_logic; -- ST.
GL_ROM_3n : out std_logic; -- ST.
GL_ROM_2n : out std_logic;
GL_ROM_1n : out std_logic;
GL_ROM_0n : out std_logic;
GL_ACIACS : out std_logic;
GL_MFPCSn : out std_logic;
GL_SNDCSn : out std_logic;
GL_FCSn : out std_logic;
GL_STE_SNDCS : out std_logic; -- STE: Sound chip select.
GL_STE_SNDIR : out std_logic; -- STE: Data flow direction control.
GL_STE_RTCCSn : out std_logic; --STE only.
GL_STE_RTC_WRn : out std_logic; --STE only.
GL_STE_RTC_RDn : out std_logic; --STE only.
-- 6800 peripheral control,
GL_VPAn : out std_logic;
GL_VMAn : in std_logic;
GL_DMA_SYNC : in std_logic;
GL_DEVn : out std_logic;
GL_RAMn : out std_logic;
GL_DMAn : out std_logic;
-- Interrupt system:
-- Comment out GL_AVECn for CPUs which do not provide the VMAn signal.
GL_AVECn : out std_logic;
GL_STE_FDINT : in std_logic; -- Floppy disk interrupt; STE only.
GL_STE_HDINTn : in std_logic; -- Hard disk interrupt; STE only.
GL_MFPINTn : in std_logic; -- ST.
GL_STE_EINT3n : in std_logic; --STE only.
GL_STE_EINT5n : in std_logic; --STE only.
GL_STE_EINT7n : in std_logic; --STE only.
GL_STE_DINTn : out std_logic; -- Disk interrupt (floppy or hard disk); STE only.
GL_IACKn : out std_logic; -- ST.
GL_STE_IPL2n : out std_logic; --STE only.
GL_STE_IPL1n : out std_logic; --STE only.
GL_STE_IPL0n : out std_logic; --STE only.
-- Video timing:
GL_BLANKn : out std_logic;
GL_DE : out std_logic;
GL_MULTISYNC : in std_logic_vector(3 downto 2);
GL_VIDEO_HIMODE : out std_logic;
GL_HSYNC_INn : in std_logic;
GL_HSYNC_OUTn : out std_logic;
GL_VSYNC_INn : in std_logic;
GL_VSYNC_OUTn : out std_logic;
GL_SYNC_OUT_EN : out std_logic;
-- Bus arstd_logicration control:
GL_RDY_INn : in std_logic;
GL_RDY_OUTn : out std_logic;
GL_BRn : out std_logic;
GL_BGIn : in std_logic;
GL_BGOn : out std_logic;
GL_BGACK_INn : in std_logic;
GL_BGACK_OUTn : out std_logic;
-- Adress and data bus:
GL_ADDRESS : in std_logic_vector(23 downto 1);
-- ST: put the data bus to 1 downto 0.
-- STE: put the data out bus to 15 downto 0.
GL_DATA_IN : in std_logic_vector(7 downto 0);
GL_DATA_OUT : out std_logic_vector(15 downto 0);
GL_DATA_EN : out std_logic;
-- Asynchronous bus control:
GL_RWn_IN : in std_logic;
GL_RWn_OUT : out std_logic;
GL_AS_INn : in std_logic;
GL_AS_OUTn : out std_logic;
GL_UDS_INn : in std_logic;
GL_UDS_OUTn : out std_logic;
GL_LDS_INn : in std_logic;
GL_LDS_OUTn : out std_logic;
GL_DTACK_INn : in std_logic;
GL_DTACK_OUTn : out std_logic;
GL_CTRL_EN : out std_logic;
-- System control:
GL_RESETn : in std_logic;
GL_BERRn : out std_logic;
-- Processor function codes:
GL_FC : in std_logic_vector(2 downto 0);
-- STE enhancements:
GL_STE_FDDS : out std_logic; -- Floppy type select (HD or DD).
GL_STE_FCCLK : out std_logic; -- Floppy controller clock select.
GL_STE_JOY_RHn : out std_logic; -- Read only FF9202 high byte.
GL_STE_JOY_RLn : out std_logic; -- Read only FF9202 low byte.
GL_STE_JOY_WL : out std_logic; -- Write only FF9202 low byte.
GL_STE_JOY_WEn : out std_logic; -- Write only FF9202 output enable.
GL_STE_BUTTONn : out std_logic; -- Read only FF9000 low byte.
GL_STE_PAD0Xn : in std_logic; -- Counter input for the Paddle 0X.
GL_STE_PAD0Yn : in std_logic; -- Counter input for the Paddle 0Y.
GL_STE_PAD1Xn : in std_logic; -- Counter input for the Paddle 1X.
GL_STE_PAD1Yn : in std_logic; -- Counter input for the Paddle 1Y.
GL_STE_PADRSTn : out std_logic; -- Paddle monoflops reset.
GL_STE_PENn : in std_logic; -- Input of the light pen.
GL_STE_SCCn : out std_logic; -- Select signal for the STE or TT SCC chip.
GL_STE_CPROGn : out std_logic -- Select signal for the STE's cache processor.
);
end component WF25915IP_TOP_V1_SOC;
component WF5380_TOP_SOC
port (
CLK : in std_logic;
RESETn : in std_logic;
ADR : in std_logic_vector(2 downto 0);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
CSn : in std_logic;
RDn : in std_logic;
WRn : in std_logic;
EOPn : in std_logic;
DACKn : in std_logic;
DRQ : out std_logic;
INT : out std_logic;
READY : out std_logic;
DB_INn : in std_logic_vector(7 downto 0);
DB_OUTn : out std_logic_vector(7 downto 0);
DB_EN : out std_logic;
DBP_INn : in std_logic;
DBP_OUTn : out std_logic;
DBP_EN : out std_logic;
RST_INn : in std_logic;
RST_OUTn : out std_logic;
RST_EN : out std_logic;
BSY_INn : in std_logic;
BSY_OUTn : out std_logic;
BSY_EN : out std_logic;
SEL_INn : in std_logic;
SEL_OUTn : out std_logic;
SEL_EN : out std_logic;
ACK_INn : in std_logic;
ACK_OUTn : out std_logic;
ACK_EN : out std_logic;
ATN_INn : in std_logic;
ATN_OUTn : out std_logic;
ATN_EN : out std_logic;
REQ_INn : in std_logic;
REQ_OUTn : out std_logic;
REQ_EN : out std_logic;
IOn_IN : in std_logic;
IOn_OUT : out std_logic;
IO_EN : out std_logic;
CDn_IN : in std_logic;
CDn_OUT : out std_logic;
CD_EN : out std_logic;
MSG_INn : in std_logic;
MSG_OUTn : out std_logic;
MSG_EN : out std_logic
);
end component WF5380_TOP_SOC;
component WF1772IP_TOP_SOC -- FDC.
port (
CLK : in std_logic; -- 16MHz clock!
RESETn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
A1, A0 : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
RDn : in std_logic;
TR00n : in std_logic;
IPn : in std_logic;
WPRTn : in std_logic;
DDEn : in std_logic;
HDTYPE : in std_logic; -- '0' = DD disks, '1' = HD disks.
MO : out std_logic;
WG : out std_logic;
WD : out std_logic;
STEP : out std_logic;
DIRC : out std_logic;
DRQ : out std_logic;
INTRQ : out std_logic
);
end component WF1772IP_TOP_SOC;
component WF68901IP_TOP_SOC -- MFP.
port ( -- System control:
CLK : in std_logic;
RESETn : in std_logic;
-- Asynchronous bus control:
DSn : in std_logic;
CSn : in std_logic;
RWn : in std_logic;
DTACKn : out std_logic;
-- Data and Adresses:
RS : in std_logic_vector(5 downto 1);
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
GPIP_IN : in std_logic_vector(7 downto 0);
GPIP_OUT : out std_logic_vector(7 downto 0);
GPIP_EN : out std_logic_vector(7 downto 0);
-- Interrupt control:
IACKn : in std_logic;
IEIn : in std_logic;
IEOn : out std_logic;
IRQn : out std_logic;
-- Timers and timer control:
XTAL1 : in std_logic; -- Use an oszillator instead of a quartz.
TAI : in std_logic;
TBI : in std_logic;
TAO : out std_logic;
TBO : out std_logic;
TCO : out std_logic;
TDO : out std_logic;
-- Serial I/O control:
RC : in std_logic;
TC : in std_logic;
SI : in std_logic;
SO : out std_logic;
SO_EN : out std_logic;
-- DMA control:
RRn : out std_logic;
TRn : out std_logic
);
end component WF68901IP_TOP_SOC;
component WF2149IP_TOP_SOC -- Sound.
port(
SYS_CLK : in std_logic; -- Read the inforation in the header!
RESETn : in std_logic;
WAV_CLK : in std_logic; -- Read the inforation in the header!
SELn : in std_logic;
BDIR : in std_logic;
BC2, BC1 : in std_logic;
A9n, A8 : in std_logic;
DA_IN : in std_logic_vector(7 downto 0);
DA_OUT : out std_logic_vector(7 downto 0);
DA_EN : out std_logic;
IO_A_IN : in std_logic_vector(7 downto 0);
IO_A_OUT : out std_logic_vector(7 downto 0);
IO_A_EN : out std_logic;
IO_B_IN : in std_logic_vector(7 downto 0);
IO_B_OUT : out std_logic_vector(7 downto 0);
IO_B_EN : out std_logic;
OUT_A : out std_logic; -- Analog (PWM) outputs.
OUT_B : out std_logic;
OUT_C : out std_logic
);
end component WF2149IP_TOP_SOC;
component WF6850IP_TOP_SOC -- ACIA.
port (
CLK : in std_logic;
RESETn : in std_logic;
CS2n, CS1, CS0 : in std_logic;
E : in std_logic;
RWn : in std_logic;
RS : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
TXCLK : in std_logic;
RXCLK : in std_logic;
RXDATA : in std_logic;
CTSn : in std_logic;
DCDn : in std_logic;
IRQn : out std_logic;
TXDATA : out std_logic;
RTSn : out std_logic
);
end component WF6850IP_TOP_SOC;
component WF_SD_CARD
port (
RESETn : in std_logic;
CLK : in std_logic;
ACSI_A1 : in std_logic;
ACSI_CSn : in std_logic;
ACSI_ACKn : in std_logic;
ACSI_INTn : out std_logic;
ACSI_DRQn : out std_logic;
ACSI_D_IN : in std_logic_vector(7 downto 0);
ACSI_D_OUT : out std_logic_vector(7 downto 0);
ACSI_D_EN : out std_logic;
MC_DO : in std_logic;
MC_PIO_DMAn : in std_logic;
MC_RWn : in std_logic;
MC_CLR_CMD : in std_logic;
MC_DONE : out std_logic;
MC_GOT_CMD : out std_logic;
MC_D_IN : in std_logic_vector(7 downto 0);
MC_D_OUT : out std_logic_vector(7 downto 0);
MC_D_EN : out std_logic
);
end component WF_SD_CARD;
component dcfifo0
PORT (
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
wrusedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end component dcfifo0;
component dcfifo1
PORT (
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end component;
end FalconIO_SDCard_IDE_CF_PKG;

4
FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
View File

@@ -190,8 +190,8 @@ begin
end if; end if;
end process DIG_PORTS; end process DIG_PORTS;
-- Set port direction to input or to output: -- Set port direction to input or to output:
IO_A_EN <= '1' when CTRL_REG(6) = '1' else '0'; IO_A_EN <= '1' when CTRL_REG(6) = '1' else '0';
IO_B_EN <= '1' when CTRL_REG(7) = '1' else '0'; IO_B_EN <= '1' when CTRL_REG(7) = '1' else '0';
IO_A_OUT <= PORT_A; IO_A_OUT <= PORT_A;
IO_B_OUT <= PORT_B; IO_B_OUT <= PORT_B;

229
FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd.bak
View File

@@ -1,229 +0,0 @@
----------------------------------------------------------------------
---- ----
---- YM2149 compatible sound generator. ----
---- ----
---- This file is part of the SUSKA ATARI clone project. ----
---- http://www.experiment-s.de ----
---- ----
---- Description: ----
---- Model of the ST or STE's YM2149 sound generator. ----
---- This IP core of the sound generator differs slightly from ----
---- the original. Firstly it is a synchronous design without any ----
---- latches (like assumed in the original chip). This required ----
---- the introduction of a system adequate clock. In detail this ----
---- SYS_CLK should on the one hand be fast enough to meet the ----
---- timing requirements of the system's bus cycle and should one ----
---- the other hand drive the PWM modules correctly. To meet both ----
---- a SYS_CLK of 16MHz or above is recommended. ----
---- Secondly, the original chip has an implemented DA converter. ----
---- This feature is not possible in today's FPGAs. Therefore the ----
---- converter is replaced by pulse width modulators. This solu- ----
---- tion is very simple in comparison to other approaches like ----
---- external DA converters with wave tables etc. The soltution ----
---- with the pulse width modulators is probably not as accurate ----
---- DAs with wavetables. For a detailed descrition of the hard- ----
---- ware PWM filter look at the end of the wave file, where the ----
---- pulse width modulators can be found. ----
---- For a proper operation it is required, that the wave clock ----
---- is lower than the system clock. A good choice is for example ----
---- 2MHz for the wave clock and 16MHz for the system clock. ----
---- ----
---- Main module file. ----
---- Top level file for use in systems on programmable chips. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2006 - 2008 Wolfgang Foerster ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.gnu.org/licenses/lgpl.html ----
---- ----
----------------------------------------------------------------------
--
-- Revision History
--
-- Revision 2K6A 2006/06/03 WF
-- Initial Release.
-- Revision 2K6B 2006/11/07 WF
-- Modified Source to compile with the Xilinx ISE.
-- Top level file provided for SOC (systems on programmable chips).
-- Revision 2K8A 2008/07/14 WF
-- Minor changes.
--
library ieee;
use ieee.std_logic_1164.all;
use work.wf2149ip_pkg.all;
entity WF2149IP_TOP_SOC is
port(
SYS_CLK : in bit; -- Read the inforation in the header!
RESETn : in bit;
WAV_CLK : in bit; -- Read the inforation in the header!
SELn : in bit;
BDIR : in bit;
BC2, BC1 : in bit;
A9n, A8 : in bit;
DA_IN : in std_logic_vector(7 downto 0);
DA_OUT : out std_logic_vector(7 downto 0);
DA_EN : out bit;
IO_A_IN : in bit_vector(7 downto 0);
IO_A_OUT : out bit_vector(7 downto 0);
IO_A_EN : out bit;
IO_B_IN : in bit_vector(7 downto 0);
IO_B_OUT : out bit_vector(7 downto 0);
IO_B_EN : out bit;
OUT_A : out bit; -- Analog (PWM) outputs.
OUT_B : out bit;
OUT_C : out bit
);
end WF2149IP_TOP_SOC;
architecture STRUCTURE of WF2149IP_TOP_SOC is
signal BUSCYCLE : BUSCYCLES;
signal DATA_OUT_I : std_logic_vector(7 downto 0);
signal DATA_EN_I : bit;
signal WAV_STRB : bit;
signal ADR_I : bit_vector(3 downto 0);
signal CTRL_REG : bit_vector(7 downto 0);
signal PORT_A : bit_vector(7 downto 0);
signal PORT_B : bit_vector(7 downto 0);
begin
P_WAVSTRB: process(RESETn, SYS_CLK)
variable LOCK : boolean;
variable TMP : bit;
begin
if RESETn = '0' then
LOCK := false;
TMP := '0';
elsif SYS_CLK = '1' and SYS_CLK' event then
if WAV_CLK = '1' and LOCK = false then
LOCK := true;
TMP := not TMP; -- Divider by 2.
case SELn is
when '1' => WAV_STRB <= '1';
when others => WAV_STRB <= TMP;
end case;
elsif WAV_CLK = '0' then
LOCK := false;
WAV_STRB <= '0';
else
WAV_STRB <= '0';
end if;
end if;
end process P_WAVSTRB;
with BDIR & BC2 & BC1 select
BUSCYCLE <= INACTIVE when "000" | "010" | "101",
ADDRESS when "001" | "100" | "111",
R_READ when "011",
R_WRITE when "110";
ADDRESSLATCH: process(RESETn, SYS_CLK)
-- This process is responsible to store the desired register
-- address. The default (after reset) is channel A fine tone
-- adjustment.
begin
if RESETn = '0' then
ADR_I <= (others => '0');
elsif SYS_CLK = '1' and SYS_CLK' event then
if BUSCYCLE = ADDRESS and A9n = '0' and A8 = '1' and DA_IN(7 downto 4) = x"0" then
ADR_I <= To_BitVector(DA_IN(3 downto 0));
end if;
end if;
end process ADDRESSLATCH;
P_CTRL_REG: process(RESETn, SYS_CLK)
-- THIS is the Control register for the mixer and for the I/O ports.
begin
if RESETn = '0' then
CTRL_REG <= x"00";
elsif SYS_CLK = '1' and SYS_CLK' event then
if BUSCYCLE = R_WRITE and ADR_I = x"7" then
CTRL_REG <= To_BitVector(DA_IN);
end if;
end if;
end process P_CTRL_REG;
DIG_PORTS: process(RESETn, SYS_CLK)
begin
if RESETn = '0' then
PORT_A <= x"00";
PORT_B <= x"00";
elsif SYS_CLK = '1' and SYS_CLK' event then
if BUSCYCLE = R_WRITE and ADR_I = x"E" then
PORT_A <= To_BitVector(DA_IN);
elsif BUSCYCLE = R_WRITE and ADR_I = x"F" then
PORT_B <= To_BitVector(DA_IN);
end if;
end if;
end process DIG_PORTS;
-- Set port direction to input or to output:
IO_A_EN <= '1' when CTRL_REG(6) = '1' else '1'; --0
IO_B_EN <= '1' when CTRL_REG(7) = '1' else '1'; --0
IO_A_OUT <= PORT_A;
IO_B_OUT <= PORT_B;
I_PSG_WAVE: WF2149IP_WAVE
port map(
RESETn => RESETn,
SYS_CLK => SYS_CLK,
WAV_STRB => WAV_STRB,
ADR => ADR_I,
DATA_IN => DA_IN,
DATA_OUT => DATA_OUT_I,
DATA_EN => DATA_EN_I,
BUSCYCLE => BUSCYCLE,
CTRL_REG => CTRL_REG(5 downto 0),
OUT_A => OUT_A,
OUT_B => OUT_B,
OUT_C => OUT_C
);
-- Read the ports and registers:
DA_EN <= '1' when DATA_EN_I = '1' else
'1' when BUSCYCLE = R_READ and ADR_I = x"7" else
'1' when BUSCYCLE = R_READ and ADR_I = x"E" else
'1' when BUSCYCLE = R_READ and ADR_I = x"F" else '0';
DA_OUT <= DATA_OUT_I when DATA_EN_I = '1' else -- WAV stuff.
To_StdLogicVector(IO_A_IN) when BUSCYCLE = R_READ and ADR_I = x"E" else
To_StdLogicVector(IO_B_IN) when BUSCYCLE = R_READ and ADR_I = x"F" else
To_StdLogicVector(CTRL_REG) when BUSCYCLE = R_READ and ADR_I = x"7" else (others => '0');
end STRUCTURE;

202
FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak
View File

@@ -1,202 +0,0 @@
-- megafunction wizard: %LPM_FIFO+%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo_mixed_widths
-- ============================================================
-- File Name: dcfifo0.vhd
-- Megafunction Name(s):
-- dcfifo_mixed_widths
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dcfifo0 IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
wrusedw : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END dcfifo0;
ARCHITECTURE SYN OF dcfifo0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
COMPONENT dcfifo_mixed_widths
GENERIC (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
lpm_widthu_r : NATURAL;
lpm_width_r : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
wrclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
aclr : IN STD_LOGIC ;
rdclk : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
wrreq : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
wrusedw <= sub_wire0(4 DOWNTO 0);
q <= sub_wire1(15 DOWNTO 0);
dcfifo_mixed_widths_component : dcfifo_mixed_widths
GENERIC MAP (
intended_device_family => "Cyclone III",
lpm_numwords => 32,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => 8,
lpm_widthu => 5,
lpm_widthu_r => 4,
lpm_width_r => 16,
overflow_checking => "ON",
rdsync_delaypipe => 5,
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 5
)
PORT MAP (
wrclk => wrclk,
rdreq => rdreq,
aclr => aclr,
rdclk => rdclk,
wrreq => wrreq,
data => data,
wrusedw => sub_wire0,
q => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "32"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "8"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "16"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-- Retrieval info: USED_PORT: wrusedw 0 0 5 0 OUTPUT NODEFVAL wrusedw[4..0]
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: wrusedw 0 0 5 0 @wrusedw 0 0 5 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf

202
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View File

@@ -1,202 +0,0 @@
-- megafunction wizard: %LPM_FIFO+%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo_mixed_widths
-- ============================================================
-- File Name: dcfifo1.vhd
-- Megafunction Name(s):
-- dcfifo_mixed_widths
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dcfifo1 IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END dcfifo1;
ARCHITECTURE SYN OF dcfifo1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT dcfifo_mixed_widths
GENERIC (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
lpm_widthu_r : NATURAL;
lpm_width_r : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
wrclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
aclr : IN STD_LOGIC ;
rdclk : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wrreq : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
wrusedw <= sub_wire0(3 DOWNTO 0);
q <= sub_wire1(7 DOWNTO 0);
dcfifo_mixed_widths_component : dcfifo_mixed_widths
GENERIC MAP (
intended_device_family => "Cyclone III",
lpm_numwords => 16,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => 16,
lpm_widthu => 4,
lpm_widthu_r => 5,
lpm_width_r => 8,
overflow_checking => "ON",
rdsync_delaypipe => 5,
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 5
)
PORT MAP (
wrclk => wrclk,
rdreq => rdreq,
aclr => aclr,
rdclk => rdclk,
wrreq => wrreq,
data => data,
wrusedw => sub_wire0,
q => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "16"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "16"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "8"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-- Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL wrusedw[3..0]
-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf

17
FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf
View File

@@ -24,6 +24,7 @@ SUBDESIGN interrupt_handler
FB_SIZE0 : INPUT; FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT; FB_SIZE1 : INPUT;
FB_ADR[31..0] : INPUT; FB_ADR[31..0] : INPUT;
FPGA_DATE[31..0] : INPUT;
PIC_INT : INPUT; PIC_INT : INPUT;
E0_INT : INPUT; E0_INT : INPUT;
DVI_INT : INPUT; DVI_INT : INPUT;
@@ -61,6 +62,7 @@ VARIABLE
INT_LA[9..0][3..0] :DFF; INT_LA[9..0][3..0] :DFF;
ACP_CONF[31..0] :DFFE; ACP_CONF[31..0] :DFFE;
ACP_CONF_CS :NODE; ACP_CONF_CS :NODE;
FPGA_DATE_CS :NODE;
PSEUDO_BUS_ERROR :NODE; PSEUDO_BUS_ERROR :NODE;
UHR_AS :NODE; UHR_AS :NODE;
UHR_DS :NODE; UHR_DS :NODE;
@@ -201,6 +203,9 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H
ACP_CONF[15..8].ENA = ACP_CONF_CS & FB_B2 & !nFB_WR; ACP_CONF[15..8].ENA = ACP_CONF_CS & FB_B2 & !nFB_WR;
ACP_CONF[7..0].ENA = ACP_CONF_CS & FB_B3 & !nFB_WR; ACP_CONF[7..0].ENA = ACP_CONF_CS & FB_B3 & !nFB_WR;
--*************************************************************************************** --***************************************************************************************
-- FPGA DATE HEX (ddmmyyyy)
FPGA_DATE_CS = !nFB_CS2 & FB_ADR[27..2]==H"10040"; -- $4'0000/4
--***************************************************************************************
-------------------------------------------------------------- --------------------------------------------------------------
-- C1287 0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR -- C1287 0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR
@@ -288,7 +293,8 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H
# INT_LATCH_CS & INT_LATCH[31..24] # INT_LATCH_CS & INT_LATCH[31..24]
# INT_CLEAR_CS & INT_IN[31..24] # INT_CLEAR_CS & INT_IN[31..24]
# ACP_CONF_CS & ACP_CONF[31..24] # ACP_CONF_CS & ACP_CONF[31..24]
,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); # FPGA_DATE_CS & FPGA_DATE[31..24]
,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS # FPGA_DATE_CS) & !nFB_OE);
FB_AD[23..16] = lpm_bustri_BYT( FB_AD[23..16] = lpm_bustri_BYT(
WERTE[][0] & RTC_ADR[]==0 & UHR_DS WERTE[][0] & RTC_ADR[]==0 & UHR_DS
# WERTE[][1] & RTC_ADR[]==1 & UHR_DS # WERTE[][1] & RTC_ADR[]==1 & UHR_DS
@@ -360,21 +366,24 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H
# INT_LATCH_CS & INT_LATCH[23..16] # INT_LATCH_CS & INT_LATCH[23..16]
# INT_CLEAR_CS & INT_IN[23..16] # INT_CLEAR_CS & INT_IN[23..16]
# ACP_CONF_CS & ACP_CONF[23..16] # ACP_CONF_CS & ACP_CONF[23..16]
,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); # FPGA_DATE_CS & FPGA_DATE[23..16]
,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS # FPGA_DATE_CS) & !nFB_OE);
FB_AD[15..8] = lpm_bustri_BYT( FB_AD[15..8] = lpm_bustri_BYT(
INT_CTR_CS & INT_CTR[15..8] INT_CTR_CS & INT_CTR[15..8]
# INT_ENA_CS & INT_ENA[15..8] # INT_ENA_CS & INT_ENA[15..8]
# INT_LATCH_CS & INT_LATCH[15..8] # INT_LATCH_CS & INT_LATCH[15..8]
# INT_CLEAR_CS & INT_IN[15..8] # INT_CLEAR_CS & INT_IN[15..8]
# ACP_CONF_CS & ACP_CONF[15..8] # ACP_CONF_CS & ACP_CONF[15..8]
,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); # FPGA_DATE_CS & FPGA_DATE[15..8]
,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS # FPGA_DATE_CS) & !nFB_OE);
FB_AD[7..0] = lpm_bustri_BYT( FB_AD[7..0] = lpm_bustri_BYT(
INT_CTR_CS & INT_CTR[7..0] INT_CTR_CS & INT_CTR[7..0]
# INT_ENA_CS & INT_ENA[7..0] # INT_ENA_CS & INT_ENA[7..0]
# INT_LATCH_CS & INT_LATCH[7..0] # INT_LATCH_CS & INT_LATCH[7..0]
# INT_CLEAR_CS & INT_IN[7..0] # INT_CLEAR_CS & INT_IN[7..0]
# ACP_CONF_CS & ACP_CONF[7..0] # ACP_CONF_CS & ACP_CONF[7..0]
,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); # FPGA_DATE_CS & FPGA_DATE[7..0]
,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS # FPGA_DATE_CS) & !nFB_OE);
INT_HANDLER_TA = INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS; INT_HANDLER_TA = INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS;
END; END;

382
FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak
View File

@@ -1,382 +0,0 @@
TITLE "INTERRUPT HANDLER UND C1287";
-- CREATED BY FREDI ASCHWANDEN
INCLUDE "lpm_bustri_LONG.inc";
INCLUDE "lpm_bustri_BYT.inc";
-- Parameters Statement (optional)
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-- Subdesign Section
SUBDESIGN interrupt_handler
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
MAIN_CLK : INPUT;
nFB_WR : INPUT;
nFB_CS1 : INPUT;
nFB_CS2 : INPUT;
FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT;
FB_ADR[31..0] : INPUT;
PIC_INT : INPUT;
E0_INT : INPUT;
DVI_INT : INPUT;
nPCI_INTA : INPUT;
nPCI_INTB : INPUT;
nPCI_INTC : INPUT;
nPCI_INTD : INPUT;
nMFP_INT : INPUT;
nFB_OE : INPUT;
DSP_INT : INPUT;
VSYNC : INPUT;
HSYNC : INPUT;
DMA_DRQ : INPUT;
nRSTO : INPUT;
nIRQ[7..2] : OUTPUT;
INT_HANDLER_TA : OUTPUT;
ACP_CONF[31..0] : OUTPUT;
TIN0 : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
VARIABLE
FB_B[3..0] :NODE;
INT_CTR[31..0] :DFFE;
INT_CTR_CS :NODE;
INT_LATCH[31..0] :DFF;
INT_LATCH_CS :NODE;
INT_CLEAR[31..0] :DFF;
INT_CLEAR_CS :NODE;
INT_IN[31..0] :NODE;
INT_ENA[31..0] :DFFE;
INT_ENA_CS :NODE;
INT_L[9..0] :DFF;
INT_LA[9..0][3..0] :DFF;
ACP_CONF[31..0] :DFFE;
ACP_CONF_CS :NODE;
PSEUDO_BUS_ERROR :NODE;
UHR_AS :NODE;
UHR_DS :NODE;
RTC_ADR[5..0] :DFFE;
ACHTELSEKUNDEN[2..0] :DFFE;
WERTE[7..0][63..0] :DFFE; -- WERTE REGISTER 0-63
PIC_INT_SYNC[2..0] :DFF;
INC_SEC :NODE;
INC_MIN :NODE;
INC_STD :NODE;
INC_TAG :NODE;
ANZAHL_TAGE_DES_MONATS[7..0]:NODE;
WINTERZEIT :NODE;
SOMMERZEIT :NODE;
INC_MONAT :NODE;
INC_JAHR :NODE;
UPDATE_ON :NODE;
BEGIN
-- BYT SELECT
FB_B0 = FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HWORD
# !FB_SIZE1 & FB_SIZE0 & !FB_ADR1 & !FB_ADR0 -- HHBYT
# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE
FB_B1 = FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HWORD
# !FB_SIZE1 & FB_SIZE0 & !FB_ADR1 & FB_ADR0 -- HLBYT
# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LWORD
# !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & !FB_ADR0 -- LHBYT
# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LWORD
# !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & FB_ADR0 -- LLBYT
# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE
-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSL<53>SEN, 1=INT7 AUSL<53>SEN
INT_CTR[].CLK = MAIN_CLK;
INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000"; -- $10000/4
INT_CTR[] = FB_AD[];
INT_CTR[31..24].ENA = INT_CTR_CS & FB_B0 & !nFB_WR;
INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR;
INT_CTR[15..8].ENA = INT_CTR_CS & FB_B2 & !nFB_WR;
INT_CTR[7..0].ENA = INT_CTR_CS & FB_B3 & !nFB_WR;
-- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
INT_ENA[].CLK = MAIN_CLK;
INT_ENA[].CLRN = nRSTO;
INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001"; -- $10004/4
INT_ENA[] = FB_AD[];
INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR;
INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR;
INT_ENA[15..8].ENA = INT_ENA_CS & FB_B2 & !nFB_WR;
INT_ENA[7..0].ENA = INT_ENA_CS & FB_B3 & !nFB_WR;
-- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR
INT_CLEAR[].CLK = MAIN_CLK;
INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002"; -- $10008/4
INT_CLEAR[31..24] = FB_AD[31..24] & INT_CLEAR_CS & FB_B0 & !nFB_WR;
INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR;
INT_CLEAR[15..8] = FB_AD[15..8] & INT_CLEAR_CS & FB_B2 & !nFB_WR;
INT_CLEAR[7..0] = FB_AD[7..0] & INT_CLEAR_CS & FB_B3 & !nFB_WR;
-- INTERRUPT LATCH REGISTER READ ONLY
INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003"; -- $1000C/4
-- INTERRUPT
!nIRQ2 = HSYNC & INT_ENA[26];
!nIRQ3 = INT_CTR0 & INT_ENA[27];
!nIRQ4 = VSYNC & INT_ENA[28];
nIRQ5 = INT_LATCH[]==H"00000000" & INT_ENA[29];
!nIRQ6 = !nMFP_INT & INT_ENA[30];
!nIRQ7 = PSEUDO_BUS_ERROR & INT_ENA[31];
PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC
# FB_ADR[19..4]==H"F8E0" -- VME
-- # FB_ADR[19..4]==H"F920" -- PADDLE
-- # FB_ADR[19..4]==H"F921" -- PADDLE
-- # FB_ADR[19..4]==H"F922" -- PADDLE
# FB_ADR[19..4]==H"FFA8" -- MFP2
# FB_ADR[19..4]==H"FFA9" -- MFP2
# FB_ADR[19..4]==H"FFAA" -- MFP2
# FB_ADR[19..4]==H"FFA8" -- MFP2
# FB_ADR[19..8]==H"F87" -- TT SCSI
# FB_ADR[19..4]==H"FFC2" -- ST UHR
# FB_ADR[19..4]==H"FFC3" -- ST UHR
-- # FB_ADR[19..4]==H"F890" -- DMA SOUND
-- # FB_ADR[19..4]==H"F891" -- DMA SOUND
-- # FB_ADR[19..4]==H"F892" -- DMA SOUND
);
-- IF VIDEO ADR CHANGE
TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2
-- INTERRUPT LATCH
INT_L[].CLK = MAIN_CLK;
INT_L[].CLRN = nRSTO;
INT_L0 = PIC_INT & INT_ENA[0];
INT_L1 = E0_INT & INT_ENA[1];
INT_L2 = DVI_INT & INT_ENA[2];
INT_L3 = !nPCI_INTA & INT_ENA[3];
INT_L4 = !nPCI_INTB & INT_ENA[4];
INT_L5 = !nPCI_INTC & INT_ENA[5];
INT_L6 = !nPCI_INTD & INT_ENA[6];
INT_L7 = DSP_INT & INT_ENA[7];
INT_L8 = VSYNC & INT_ENA[8];
INT_L9 = HSYNC & INT_ENA[9];
INT_LA[][].CLK = MAIN_CLK;
INT_LATCH[] = H"FFFFFFFF";
INT_LATCH[].CLRN = !INT_CLEAR[] & nRSTO;
FOR I IN 0 TO 9 GENERATE
INT_LA[I][].CLRN = INT_ENA[I] & nRSTO;
INT_LA[I][] = INT_LA[I][]+1 & INT_L[I] & INT_LA[I][]<7
# INT_LA[I][]-1 & !INT_L[I] & INT_LA[I][]>8
# 15 & INT_L[I] & INT_LA[I][]>6
# 0 & !INT_L[I] & INT_LA[I][]<9;
INT_LATCH[I].CLK = INT_LA[I][3];
END GENERATE;
-- INT_IN
INT_IN0 = PIC_INT;
INT_IN1 = E0_INT;
INT_IN2 = DVI_INT;
INT_IN3 = !nPCI_INTA;
INT_IN4 = !nPCI_INTB;
INT_IN5 = !nPCI_INTC;
INT_IN6 = !nPCI_INTD;
INT_IN7 = DSP_INT;
INT_IN8 = VSYNC;
INT_IN9 = HSYNC;
INT_IN[25..10] = H"0";
INT_IN26 = HSYNC;
INT_IN27 = INT_CTR0;
INT_IN28 = VSYNC;
INT_IN29 = INT_LATCH[]!=H"00000000";
INT_IN30 = !nMFP_INT;
INT_IN31 = DMA_DRQ;
--***************************************************************************************
-- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE
ACP_CONF[].CLK = MAIN_CLK;
ACP_CONF_CS = !nFB_CS2 & FB_ADR[27..2]==H"10000"; -- $4'0000/4
ACP_CONF[] = FB_AD[];
ACP_CONF[31..24].ENA = ACP_CONF_CS & FB_B0 & !nFB_WR;
ACP_CONF[23..16].ENA = ACP_CONF_CS & FB_B1 & !nFB_WR;
ACP_CONF[15..8].ENA = ACP_CONF_CS & FB_B2 & !nFB_WR;
ACP_CONF[7..0].ENA = ACP_CONF_CS & FB_B3 & !nFB_WR;
--***************************************************************************************
--------------------------------------------------------------
-- C1287 0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR
----------------------------------------------------------
RTC_ADR[].CLK = MAIN_CLK;
RTC_ADR[] = FB_AD[21..16];
UHR_AS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B0" & FB_B1; -- FFFF8961
UHR_DS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B1" & FB_B3; -- FFFF8963
RTC_ADR[].ENA = UHR_AS & !nFB_WR;
WERTE[][].CLK = MAIN_CLK;
WERTE[7..0][0] = FB_AD[23..16] & RTC_ADR[]==0 & UHR_DS & !nFB_WR;
WERTE[7..0][1] = FB_AD[23..16];
WERTE[7..0][2] = FB_AD[23..16] & RTC_ADR[]==2 & UHR_DS & !nFB_WR;
WERTE[7..0][3] = FB_AD[23..16];
WERTE[7..0][4] = FB_AD[23..16] & RTC_ADR[]==4 & UHR_DS & !nFB_WR;
WERTE[7..0][5] = FB_AD[23..16];
WERTE[7..0][6] = FB_AD[23..16] & RTC_ADR[]==6 & UHR_DS & !nFB_WR;
WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR;
WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR;
WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR;
FOR I IN 10 TO 63 GENERATE
WERTE[7..0][I] = FB_AD[23..16];
END GENERATE;
FOR I IN 0 TO 63 GENERATE
WERTE[][I].ENA = RTC_ADR[]==I & UHR_DS & !nFB_WR;
END GENERATE;
PIC_INT_SYNC[].CLK = MAIN_CLK;
PIC_INT_SYNC[0] = PIC_INT;
PIC_INT_SYNC[1] = PIC_INT_SYNC[0];
PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0];
UPDATE_ON = !WERTE[7][11];
WERTE[6][10].CLRN = GND; -- KEIN UIP
UPDATE_ON = !WERTE[7][11]; -- UPDATE ON OFF
WERTE[2][11] = VCC; -- IMMER BINARY
WERTE[1][11] = VCC; -- IMMER 24H FORMAT
WERTE[0][11] = VCC; -- IMMER SOMMERZEITKORREKTUR
WERTE[7][13] = VCC; -- IMMER RICHTIG
-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN F<>R R<>CKSCHALTUNG)
SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4 & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL
WERTE[0][13] = SOMMERZEIT;
WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT);
WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13]; --LETZTER SONNTAG IM OKTOBER
-- ACHTELSEKUNDEN
ACHTELSEKUNDEN[].CLK = MAIN_CLK;
ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1;
ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON;
-- SEKUNDEN
INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON;
WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN Z<>HLEN BIS 59
WERTE[][0].ENA = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);
-- MINUTEN
INC_MIN = INC_SEC & WERTE[][0]==59; --
WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN Z<>HLEN BIS 59
WERTE[][2].ENA = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); --
-- STUNDEN
INC_STD = INC_MIN & WERTE[][2]==59;
WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN Z<>HLEN BIS 23
WERTE[][4].ENA = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT
-- WOCHENTAG UND TAG
INC_TAG = INC_STD & WERTE[][2]==23;
WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG Z<>HLEN BIS 7
# 1 & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER
WERTE[][6].ENA = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);
ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12)
# 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11)
# 29 & WERTE[][8]==2 & WERTE[1..0][9]==0
# 28 & WERTE[][8]==2 & WERTE[1..0][9]!=0;
WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG Z<>HLEN BIS MONATSENDE
# 1 & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER
WERTE[][7].ENA = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); --
-- MONATE
INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[]; --
WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE Z<>HLEN BIS 12
# 1 & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER
WERTE[][8].ENA = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);
-- JAHR
INC_JAHR = INC_MONAT & WERTE[][8]==12; --
WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE Z<>HLEN BIS 99
WERTE[][9].ENA = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);
-- TRISTATE OUTPUT
FB_AD[31..24] = lpm_bustri_BYT(
INT_CTR_CS & INT_CTR[31..24]
# INT_ENA_CS & INT_ENA[31..24]
# INT_LATCH_CS & INT_LATCH[31..24]
# INT_CLEAR_CS & INT_IN[31..24]
# ACP_CONF_CS & ACP_CONF[31..24]
,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
FB_AD[23..16] = lpm_bustri_BYT(
WERTE[][0] & RTC_ADR[]==0 & UHR_DS
# WERTE[][1] & RTC_ADR[]==1 & UHR_DS
# WERTE[][2] & RTC_ADR[]==2 & UHR_DS
# WERTE[][3] & RTC_ADR[]==3 & UHR_DS
# WERTE[][4] & RTC_ADR[]==4 & UHR_DS
# WERTE[][5] & RTC_ADR[]==5 & UHR_DS
# WERTE[][6] & RTC_ADR[]==6 & UHR_DS
# WERTE[][7] & RTC_ADR[]==7 & UHR_DS
# WERTE[][8] & RTC_ADR[]==8 & UHR_DS
# WERTE[][9] & RTC_ADR[]==9 & UHR_DS
# WERTE[][10] & RTC_ADR[]==10 & UHR_DS
# WERTE[][11] & RTC_ADR[]==11 & UHR_DS
# WERTE[][12] & RTC_ADR[]==12 & UHR_DS
# WERTE[][13] & RTC_ADR[]==13 & UHR_DS
# WERTE[][14] & RTC_ADR[]==14 & UHR_DS
# WERTE[][15] & RTC_ADR[]==15 & UHR_DS
# WERTE[][16] & RTC_ADR[]==16 & UHR_DS
# WERTE[][17] & RTC_ADR[]==17 & UHR_DS
# WERTE[][18] & RTC_ADR[]==18 & UHR_DS
# WERTE[][19] & RTC_ADR[]==19 & UHR_DS
# WERTE[][20] & RTC_ADR[]==20 & UHR_DS
# WERTE[][21] & RTC_ADR[]==21 & UHR_DS
# WERTE[][22] & RTC_ADR[]==22 & UHR_DS
# WERTE[][23] & RTC_ADR[]==23 & UHR_DS
# WERTE[][24] & RTC_ADR[]==24 & UHR_DS
# WERTE[][25] & RTC_ADR[]==25 & UHR_DS
# WERTE[][26] & RTC_ADR[]==26 & UHR_DS
# WERTE[][27] & RTC_ADR[]==27 & UHR_DS
# WERTE[][28] & RTC_ADR[]==28 & UHR_DS
# WERTE[][29] & RTC_ADR[]==29 & UHR_DS
# WERTE[][30] & RTC_ADR[]==30 & UHR_DS
# WERTE[][31] & RTC_ADR[]==31 & UHR_DS
# WERTE[][32] & RTC_ADR[]==32 & UHR_DS
# WERTE[][33] & RTC_ADR[]==33 & UHR_DS
# WERTE[][34] & RTC_ADR[]==34 & UHR_DS
# WERTE[][35] & RTC_ADR[]==35 & UHR_DS
# WERTE[][36] & RTC_ADR[]==36 & UHR_DS
# WERTE[][37] & RTC_ADR[]==37 & UHR_DS
# WERTE[][38] & RTC_ADR[]==38 & UHR_DS
# WERTE[][39] & RTC_ADR[]==39 & UHR_DS
# WERTE[][40] & RTC_ADR[]==40 & UHR_DS
# WERTE[][41] & RTC_ADR[]==41 & UHR_DS
# WERTE[][42] & RTC_ADR[]==42 & UHR_DS
# WERTE[][43] & RTC_ADR[]==43 & UHR_DS
# WERTE[][44] & RTC_ADR[]==44 & UHR_DS
# WERTE[][45] & RTC_ADR[]==45 & UHR_DS
# WERTE[][46] & RTC_ADR[]==46 & UHR_DS
# WERTE[][47] & RTC_ADR[]==47 & UHR_DS
# WERTE[][48] & RTC_ADR[]==48 & UHR_DS
# WERTE[][49] & RTC_ADR[]==49 & UHR_DS
# WERTE[][50] & RTC_ADR[]==50 & UHR_DS
# WERTE[][51] & RTC_ADR[]==51 & UHR_DS
# WERTE[][52] & RTC_ADR[]==52 & UHR_DS
# WERTE[][53] & RTC_ADR[]==53 & UHR_DS
# WERTE[][54] & RTC_ADR[]==54 & UHR_DS
# WERTE[][55] & RTC_ADR[]==55 & UHR_DS
# WERTE[][56] & RTC_ADR[]==56 & UHR_DS
# WERTE[][57] & RTC_ADR[]==57 & UHR_DS
# WERTE[][58] & RTC_ADR[]==58 & UHR_DS
# WERTE[][59] & RTC_ADR[]==59 & UHR_DS
# WERTE[][60] & RTC_ADR[]==60 & UHR_DS
# WERTE[][61] & RTC_ADR[]==61 & UHR_DS
# WERTE[][62] & RTC_ADR[]==62 & UHR_DS
# WERTE[][63] & RTC_ADR[]==63 & UHR_DS
# (0,RTC_ADR[]) & UHR_AS
# INT_CTR_CS & INT_CTR[23..16]
# INT_ENA_CS & INT_ENA[23..16]
# INT_LATCH_CS & INT_LATCH[23..16]
# INT_CLEAR_CS & INT_IN[23..16]
# ACP_CONF_CS & ACP_CONF[23..16]
,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
FB_AD[15..8] = lpm_bustri_BYT(
INT_CTR_CS & INT_CTR[15..8]
# INT_ENA_CS & INT_ENA[15..8]
# INT_LATCH_CS & INT_LATCH[15..8]
# INT_CLEAR_CS & INT_IN[15..8]
# ACP_CONF_CS & ACP_CONF[15..8]
,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
FB_AD[7..0] = lpm_bustri_BYT(
INT_CTR_CS & INT_CTR[7..0]
# INT_ENA_CS & INT_ENA[7..0]
# INT_LATCH_CS & INT_LATCH[7..0]
# INT_CLEAR_CS & INT_IN[7..0]
# ACP_CONF_CS & ACP_CONF[7..0]
,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
INT_HANDLER_TA = INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS;
END;

20
FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt
View File

@@ -1,20 +0,0 @@
PLL_Name altpll1:inst|altpll:altpll_component|altpll_3vp2:auto_generated|pll1
PLLJITTER 36
PLLSPEmax 84
PLLSPEmin -53
PLL_Name altpll2:inst12|altpll:altpll_component|altpll_1r33:auto_generated|pll1
PLLJITTER 43
PLLSPEmax 84
PLLSPEmin -53
PLL_Name altpll3:inst13|altpll:altpll_component|altpll_aus2:auto_generated|pll1
PLLJITTER NA
PLLSPEmax 84
PLLSPEmin -53
PLL_Name altpll4:inst22|altpll:altpll_component|altpll_r4n2:auto_generated|pll1
PLLJITTER 31
PLLSPEmax 84
PLLSPEmin -53

27
FPGA_by_Fredi/UNUSED
View File

@@ -1,27 +0,0 @@
-- Clearbox generated Memory Initialization File (.mif)
WIDTH=3;
DEPTH=16;
ADDRESS_RADIX=HEX;
DATA_RADIX=HEX;
CONTENT BEGIN
00 : 7;
01 : 6;
02 : 5;
03 : 4;
04 : 3;
05 : 2;
06 : 1;
07 : 0;
08 : 7;
09 : 6;
0a : 5;
0b : 4;
0c : 3;
0d : 2;
0e : 1;
0f : 0;
END;

110
FPGA_by_Fredi/Video/BLITTER/altsyncram0.bsf
View File

@@ -1,110 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 256 128)
(text "altsyncram0" (rect 84 2 187 21)(font "Arial" (font_size 10)))
(text "inst" (rect 8 109 31 124)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "data[15..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
(text "data[15..0]" (rect 4 16 66 32)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 112 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "address[3..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
(text "address[3..0]" (rect 4 32 80 48)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 112 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "wren" (rect 0 0 31 16)(font "Arial" (font_size 8)))
(text "wren" (rect 4 48 31 64)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 112 64)(line_width 1))
)
(port
(pt 0 88)
(input)
(text "byteena_a[1..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
(text "byteena_a[1..0]" (rect 4 72 94 88)(font "Arial" (font_size 8)))
(line (pt 0 88)(pt 112 88)(line_width 3))
)
(port
(pt 0 104)
(input)
(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
(text "clock" (rect 4 88 35 104)(font "Arial" (font_size 8)))
(line (pt 0 104)(pt 104 104)(line_width 1))
)
(port
(pt 256 32)
(output)
(text "q[15..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
(text "q[15..0]" (rect 209 16 253 32)(font "Arial" (font_size 8)))
(line (pt 256 32)(pt 168 32)(line_width 3))
)
(drawing
(text "16 Word(s)" (rect 133 35 147 90)(font "Arial" )(vertical))
(text "RAM" (rect 149 49 163 72)(font "Arial" )(vertical))
(text "Block Type: AUTO" (rect 41 106 129 120)(font "Arial" ))
(line (pt 128 24)(pt 168 24)(line_width 1))
(line (pt 168 24)(pt 168 96)(line_width 1))
(line (pt 168 96)(pt 128 96)(line_width 1))
(line (pt 128 96)(pt 128 24)(line_width 1))
(line (pt 112 27)(pt 120 27)(line_width 1))
(line (pt 120 27)(pt 120 39)(line_width 1))
(line (pt 120 39)(pt 112 39)(line_width 1))
(line (pt 112 39)(pt 112 27)(line_width 1))
(line (pt 112 34)(pt 114 36)(line_width 1))
(line (pt 114 36)(pt 112 38)(line_width 1))
(line (pt 104 36)(pt 112 36)(line_width 1))
(line (pt 120 32)(pt 128 32)(line_width 3))
(line (pt 112 43)(pt 120 43)(line_width 1))
(line (pt 120 43)(pt 120 55)(line_width 1))
(line (pt 120 55)(pt 112 55)(line_width 1))
(line (pt 112 55)(pt 112 43)(line_width 1))
(line (pt 112 50)(pt 114 52)(line_width 1))
(line (pt 114 52)(pt 112 54)(line_width 1))
(line (pt 104 52)(pt 112 52)(line_width 1))
(line (pt 120 48)(pt 128 48)(line_width 3))
(line (pt 112 59)(pt 120 59)(line_width 1))
(line (pt 120 59)(pt 120 71)(line_width 1))
(line (pt 120 71)(pt 112 71)(line_width 1))
(line (pt 112 71)(pt 112 59)(line_width 1))
(line (pt 112 66)(pt 114 68)(line_width 1))
(line (pt 114 68)(pt 112 70)(line_width 1))
(line (pt 104 68)(pt 112 68)(line_width 1))
(line (pt 120 64)(pt 128 64)(line_width 1))
(line (pt 112 83)(pt 120 83)(line_width 1))
(line (pt 120 83)(pt 120 95)(line_width 1))
(line (pt 120 95)(pt 112 95)(line_width 1))
(line (pt 112 95)(pt 112 83)(line_width 1))
(line (pt 112 90)(pt 114 92)(line_width 1))
(line (pt 114 92)(pt 112 94)(line_width 1))
(line (pt 104 92)(pt 112 92)(line_width 1))
(line (pt 120 88)(pt 128 88)(line_width 3))
(line (pt 104 36)(pt 104 105)(line_width 1))
)
)

15
FPGA_by_Fredi/Video/BLITTER/altsyncram0.inc
View File

@@ -15,13 +15,18 @@
FUNCTION altsyncram0 FUNCTION altsyncram0
( (
address[3..0], address_a[3..0],
address_b[3..0],
byteena_a[1..0], byteena_a[1..0],
clock, clock_a,
data[15..0], clock_b,
wren data_a[15..0],
data_b[15..0],
wren_a,
wren_b
) )
RETURNS ( RETURNS (
q[15..0] q_a[15..0],
q_b[15..0]
); );

2
FPGA_by_Fredi/Video/BLITTER/altsyncram0.qip
View File

@@ -1,6 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "ALTSYNCRAM" set_global_assignment -name IP_TOOL_NAME "ALTSYNCRAM"
set_global_assignment -name IP_TOOL_VERSION "9.1" set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.tdf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.inc"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.cmp"]

110
FPGA_by_Fredi/Video/BLITTER/altsyncram0.tdf
View File

@@ -38,43 +38,63 @@ INCLUDE "altsyncram.inc";
SUBDESIGN altsyncram0 SUBDESIGN altsyncram0
( (
address[3..0] : INPUT; address_a[3..0] : INPUT;
address_b[3..0] : INPUT;
byteena_a[1..0] : INPUT = VCC; byteena_a[1..0] : INPUT = VCC;
clock : INPUT = VCC; clock_a : INPUT = VCC;
data[15..0] : INPUT; clock_b : INPUT;
wren : INPUT = GND; data_a[15..0] : INPUT;
q[15..0] : OUTPUT; data_b[15..0] : INPUT;
wren_a : INPUT = GND;
wren_b : INPUT = GND;
q_a[15..0] : OUTPUT;
q_b[15..0] : OUTPUT;
) )
VARIABLE VARIABLE
altsyncram_component : altsyncram WITH ( altsyncram_component : altsyncram WITH (
ADDRESS_REG_B = "CLOCK1",
BYTE_SIZE = 8, BYTE_SIZE = 8,
CLOCK_ENABLE_INPUT_A = "BYPASS", CLOCK_ENABLE_INPUT_A = "BYPASS",
CLOCK_ENABLE_INPUT_B = "BYPASS",
CLOCK_ENABLE_OUTPUT_A = "BYPASS", CLOCK_ENABLE_OUTPUT_A = "BYPASS",
CLOCK_ENABLE_OUTPUT_B = "BYPASS",
INDATA_REG_B = "CLOCK1",
INTENDED_DEVICE_FAMILY = "Cyclone III", INTENDED_DEVICE_FAMILY = "Cyclone III",
LPM_HINT = "ENABLE_RUNTIME_MOD=NO",
LPM_TYPE = "altsyncram", LPM_TYPE = "altsyncram",
NUMWORDS_A = 16, NUMWORDS_A = 16,
OPERATION_MODE = "SINGLE_PORT", NUMWORDS_B = 16,
OPERATION_MODE = "BIDIR_DUAL_PORT",
OUTDATA_ACLR_A = "NONE", OUTDATA_ACLR_A = "NONE",
OUTDATA_ACLR_B = "NONE",
OUTDATA_REG_A = "UNREGISTERED", OUTDATA_REG_A = "UNREGISTERED",
OUTDATA_REG_B = "UNREGISTERED",
POWER_UP_UNINITIALIZED = "FALSE", POWER_UP_UNINITIALIZED = "FALSE",
READ_DURING_WRITE_MODE_PORT_A = "NEW_DATA_WITH_NBE_READ", READ_DURING_WRITE_MODE_PORT_A = "NEW_DATA_WITH_NBE_READ",
READ_DURING_WRITE_MODE_PORT_B = "NEW_DATA_WITH_NBE_READ", READ_DURING_WRITE_MODE_PORT_B = "NEW_DATA_WITH_NBE_READ",
WIDTHAD_A = 4, WIDTHAD_A = 4,
WIDTHAD_B = 4,
WIDTH_A = 16, WIDTH_A = 16,
WIDTH_BYTEENA_A = 2 WIDTH_B = 16,
WIDTH_BYTEENA_A = 2,
WIDTH_BYTEENA_B = 1,
WRCONTROL_WRADDRESS_REG_B = "CLOCK1"
); );
BEGIN BEGIN
q[15..0] = altsyncram_component.q_a[15..0]; q_a[15..0] = altsyncram_component.q_a[15..0];
altsyncram_component.wren_a = wren; q_b[15..0] = altsyncram_component.q_b[15..0];
altsyncram_component.clock0 = clock; altsyncram_component.wren_a = wren_a;
altsyncram_component.clock0 = clock_a;
altsyncram_component.wren_b = wren_b;
altsyncram_component.clock1 = clock_b;
altsyncram_component.byteena_a[1..0] = byteena_a[1..0]; altsyncram_component.byteena_a[1..0] = byteena_a[1..0];
altsyncram_component.address_a[3..0] = address[3..0]; altsyncram_component.address_a[3..0] = address_a[3..0];
altsyncram_component.data_a[15..0] = data[15..0]; altsyncram_component.address_b[3..0] = address_b[3..0];
altsyncram_component.data_a[15..0] = data_a[15..0];
altsyncram_component.data_b[15..0] = data_b[15..0];
END; END;
@@ -100,13 +120,13 @@ END;
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0" -- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" -- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0" -- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0" -- Retrieval info: PRIVATE: Clock NUMERIC "5"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0" -- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0" -- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0" -- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" -- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -116,17 +136,17 @@ END;
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "256" -- Retrieval info: PRIVATE: MEMSIZE NUMERIC "256"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" -- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "" -- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "1" -- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" -- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1" -- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0" -- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" -- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1" -- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" -- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1" -- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
@@ -138,44 +158,64 @@ END;
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16" -- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16" -- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" -- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0" -- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" -- Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_WITH_NBE_READ" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_WITH_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_WITH_NBE_READ" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_WITH_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
-- Retrieval info: USED_PORT: address 0 0 4 0 INPUT NODEFVAL address[3..0] -- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: USED_PORT: address_a 0 0 4 0 INPUT NODEFVAL address_a[3..0]
-- Retrieval info: USED_PORT: address_b 0 0 4 0 INPUT NODEFVAL address_b[3..0]
-- Retrieval info: USED_PORT: byteena_a 0 0 2 0 INPUT VCC byteena_a[1..0] -- Retrieval info: USED_PORT: byteena_a 0 0 2 0 INPUT VCC byteena_a[1..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock -- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC clock_a
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] -- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] -- Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL data_a[15..0]
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND wren -- Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL data_b[15..0]
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 -- Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL q_a[15..0]
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -- Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL q_b[15..0]
-- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 -- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND wren_a
-- Retrieval info: CONNECT: @address_a 0 0 4 0 address 0 0 4 0 -- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND wren_b
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
-- Retrieval info: CONNECT: @address_a 0 0 4 0 address_a 0 0 4 0
-- Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
-- Retrieval info: CONNECT: @address_b 0 0 4 0 address_b 0 0 4 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena_a 0 0 2 0 -- Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena_a 0 0 2 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.tdf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.tdf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_inst.tdf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_inst.tdf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_wave*.jpg FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf -- Retrieval info: LIB_FILE: altera_mf

BIN
FPGA_by_Fredi/Video/BLITTER/altsyncram0_wave0.jpg
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13
FPGA_by_Fredi/Video/BLITTER/altsyncram0_waveforms.html
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@@ -1,13 +0,0 @@
<html>
<head>
<title>Sample Waveforms for "altsyncram0.tdf" </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file "altsyncram0.tdf" </CENTER></h2>
<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design "altsyncram0.tdf". For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( FFF0, FFF1, FFF2, FFF3, ...). The design "altsyncram0.tdf" has </P>
<CENTER><img src=altsyncram0_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. </P>
<P></P>
</body>
</html>

427
FPGA_by_Fredi/Video/BLITTER/blitter.tdf.ALT
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@@ -1,427 +0,0 @@
-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2010 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
-- Created on Sat Jan 15 11:06:17 2011
INCLUDE "lpm_bustri_WORD.inc";
INCLUDE "VIDEO/BLITTER/lpm_clshift0.INC";
CONSTANT BL_SKEW_LF = 255;
-- Title Statement (optional)
TITLE "Blitter";
-- Parameters Statement (optional)
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-- Subdesign Section
SUBDESIGN BLITTER
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
nRSTO : INPUT;
MAIN_CLK : INPUT;
FB_ALE : INPUT;
nFB_WR : INPUT;
nFB_OE : INPUT;
FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT;
VIDEO_RAM_CTR[15..0] : INPUT;
BLITTER_ON : INPUT;
FB_ADR[31..0] : INPUT;
nFB_CS1 : INPUT;
nFB_CS2 : INPUT;
nFB_CS3 : INPUT;
DDRCLK0 : INPUT;
BLITTER_DIN[127..0] : INPUT;
BLITTER_DACK[4..0] : INPUT;
SR_BLITTER_DACK : INPUT;
BLITTER_RUN : OUTPUT;
BLITTER_DOUT[127..0] : OUTPUT;
BLITTER_ADR[31..0] : OUTPUT;
BLITTER_SIG : OUTPUT;
BLITTER_WR : OUTPUT;
BLITTER_TA : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
VARIABLE
FB_B[3..0] :NODE;
FB_16B[1..0] :NODE;
BLITTER_CS :NODE;
BL_HRAM0_CS :NODE;
BL_HRAM0[15..0] :DFFE;
BL_HRAM1_CS :NODE;
BL_HRAM1[15..0] :DFFE;
BL_HRAM2_CS :NODE;
BL_HRAM2[15..0] :DFFE;
BL_HRAM3_CS :NODE;
BL_HRAM3[15..0] :DFFE;
BL_HRAM4_CS :NODE;
BL_HRAM4[15..0] :DFFE;
BL_HRAM5_CS :NODE;
BL_HRAM5[15..0] :DFFE;
BL_HRAM6_CS :NODE;
BL_HRAM6[15..0] :DFFE;
BL_HRAM7_CS :NODE;
BL_HRAM7[15..0] :DFFE;
BL_HRAM8_CS :NODE;
BL_HRAM8[15..0] :DFFE;
BL_HRAM9_CS :NODE;
BL_HRAM9[15..0] :DFFE;
BL_HRAMA_CS :NODE;
BL_HRAMA[15..0] :DFFE;
BL_HRAMB_CS :NODE;
BL_HRAMB[15..0] :DFFE;
BL_HRAMC_CS :NODE;
BL_HRAMC[15..0] :DFFE;
BL_HRAMD_CS :NODE;
BL_HRAMD[15..0] :DFFE;
BL_HRAME_CS :NODE;
BL_HRAME[15..0] :DFFE;
BL_HRAMF_CS :NODE;
BL_HRAMF[15..0] :DFFE;
BL_SRC_X_INC_CS :NODE;
BL_SRC_X_INC[15..0] :DFFE;
BL_SRC_Y_INC_CS :NODE;
BL_SRC_Y_INC[15..0] :DFFE;
BL_ENDMASK1_CS :NODE;
BL_ENDMASK1[15..0] :DFFE;
BL_ENDMASK2_CS :NODE;
BL_ENDMASK2[15..0] :DFFE;
BL_ENDMASK3_CS :NODE;
BL_ENDMASK3[15..0] :DFFE;
BL_SRC_ADRH_CS :NODE;
BL_SRC_ADRL_CS :NODE;
BL_SRC_ADR[31..0] :DFFE;
BL_DST_X_INC_CS :NODE;
BL_DST_X_INC[15..0] :DFFE;
BL_DST_Y_INC_CS :NODE;
BL_DST_Y_INC[15..0] :DFFE;
BL_DST_ADRH_CS :NODE;
BL_DST_ADRL_CS :NODE;
BL_DST_ADR[31..0] :DFFE;
BL_X_CNT_CS :NODE;
BL_X_CNT[15..0] :DFFE;
BL_Y_CNT_CS :NODE;
BL_Y_CNT[15..0] :DFFE;
BL_HT_OP_CS :NODE;
BL_HT_OP[7..0] :DFFE;
BL_LC_OP[7..0] :DFFE;
BL_LN_CS :NODE;
BL_LN[7..0] :DFFE;
BL_SKEW[7..0] :DFFE;
BL_SKEW_EXT[6..0] :NODE;
BL_SKEW_IN[255..0] :DFFE;
BL_SKEW_OUT[255..0] :DFFE;
BL_DATA_DDR_READY :DFF; -- 1 WENN DATEN GESCHRIEBEN ODER LESBAR
BL_READ_SRC :DFFE;
BL_DST_BUFFER[127..0] :DFFE;
BL_READ_DST :DFFE;
COUNT[18..0] :DFF;
BEGIN
-- BYT SELECT 32 BIT
FB_B0 = FB_ADR[1..0]==0; -- ADR==0
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- BYT SELECT 16 BIT
FB_16B0 = FB_ADR[0]==0; -- ADR==0
FB_16B1 = FB_ADR[0]==1 -- ADR==1
# !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT
-- BLITTER CS
BLITTER_CS = !nFB_CS1 & FB_ADR[19..6]==H"3E28"; -- FFFF8A00-3F/40
BLITTER_TA = BLITTER_CS;
-- REGISTER
-- HALFTON RAM 0
BL_HRAM0[].CLK = MAIN_CLK;
BL_HRAM0[15..0] = FB_AD[31..16];
BL_HRAM0_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C500"; -- $F8A00/2
BL_HRAM0[15..8].ENA = BL_HRAM0_CS & !nFB_WR & FB_16B0;
BL_HRAM0[7..0].ENA = BL_HRAM0_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 1
BL_HRAM1[].CLK = MAIN_CLK;
BL_HRAM1[15..0] = FB_AD[31..16];
BL_HRAM1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C501"; -- $F8A02/2
BL_HRAM1[15..8].ENA = BL_HRAM1_CS & !nFB_WR & FB_16B0;
BL_HRAM1[7..0].ENA = BL_HRAM1_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 2
BL_HRAM2[].CLK = MAIN_CLK;
BL_HRAM2[15..0] = FB_AD[31..16];
BL_HRAM2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C502"; -- $F8A04/2
BL_HRAM2[15..8].ENA = BL_HRAM2_CS & !nFB_WR & FB_16B0;
BL_HRAM2[7..0].ENA = BL_HRAM2_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 3
BL_HRAM3[].CLK = MAIN_CLK;
BL_HRAM3[15..0] = FB_AD[31..16];
BL_HRAM3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C503"; -- $F8A06/2
BL_HRAM3[15..8].ENA = BL_HRAM3_CS & !nFB_WR & FB_16B0;
BL_HRAM3[7..0].ENA = BL_HRAM3_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 4
BL_HRAM4[].CLK = MAIN_CLK;
BL_HRAM4[15..0] = FB_AD[31..16];
BL_HRAM4_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C504"; -- $F8A08/2
BL_HRAM4[15..8].ENA = BL_HRAM4_CS & !nFB_WR & FB_16B0;
BL_HRAM4[7..0].ENA = BL_HRAM4_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 5
BL_HRAM5[].CLK = MAIN_CLK;
BL_HRAM5[15..0] = FB_AD[31..16];
BL_HRAM5_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C505"; -- $F8A08/2
BL_HRAM5[15..8].ENA = BL_HRAM5_CS & !nFB_WR & FB_16B0;
BL_HRAM5[7..0].ENA = BL_HRAM5_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 6
BL_HRAM6[].CLK = MAIN_CLK;
BL_HRAM6[15..0] = FB_AD[31..16];
BL_HRAM6_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C506"; -- $F8A08/2
BL_HRAM6[15..8].ENA = BL_HRAM6_CS & !nFB_WR & FB_16B0;
BL_HRAM6[7..0].ENA = BL_HRAM6_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 7
BL_HRAM7[].CLK = MAIN_CLK;
BL_HRAM7[15..0] = FB_AD[31..16];
BL_HRAM7_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C507"; -- $F8A08/2
BL_HRAM7[15..8].ENA = BL_HRAM7_CS & !nFB_WR & FB_16B0;
BL_HRAM7[7..0].ENA = BL_HRAM7_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 8
BL_HRAM8[].CLK = MAIN_CLK;
BL_HRAM8[15..0] = FB_AD[31..16];
BL_HRAM8_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C508"; -- $F8A10/2
BL_HRAM8[15..8].ENA = BL_HRAM8_CS & !nFB_WR & FB_16B0;
BL_HRAM8[7..0].ENA = BL_HRAM8_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 9
BL_HRAM9[].CLK = MAIN_CLK;
BL_HRAM9[15..0] = FB_AD[31..16];
BL_HRAM9_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C509"; -- $F8A12/2
BL_HRAM9[15..8].ENA = BL_HRAM9_CS & !nFB_WR & FB_16B0;
BL_HRAM9[7..0].ENA = BL_HRAM9_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 10
BL_HRAMA[].CLK = MAIN_CLK;
BL_HRAMA[15..0] = FB_AD[31..16];
BL_HRAMA_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50A"; -- $F8A4/2
BL_HRAMA[15..8].ENA = BL_HRAMA_CS & !nFB_WR & FB_16B0;
BL_HRAMA[7..0].ENA = BL_HRAMA_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 11
BL_HRAMB[].CLK = MAIN_CLK;
BL_HRAMB[15..0] = FB_AD[31..16];
BL_HRAMB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50B"; -- $F8A16/2
BL_HRAMB[15..8].ENA = BL_HRAMB_CS & !nFB_WR & FB_16B0;
BL_HRAMB[7..0].ENA = BL_HRAMB_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 12
BL_HRAMC[].CLK = MAIN_CLK;
BL_HRAMC[15..0] = FB_AD[31..16];
BL_HRAMC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50C"; -- $F8A18/2
BL_HRAMC[15..8].ENA = BL_HRAMC_CS & !nFB_WR & FB_16B0;
BL_HRAMC[7..0].ENA = BL_HRAMC_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 13
BL_HRAMD[].CLK = MAIN_CLK;
BL_HRAMD[15..0] = FB_AD[31..16];
BL_HRAMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50D"; -- $F8A1A/2
BL_HRAMD[15..8].ENA = BL_HRAMD_CS & !nFB_WR & FB_16B0;
BL_HRAMD[7..0].ENA = BL_HRAMD_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 14
BL_HRAME[].CLK = MAIN_CLK;
BL_HRAME[15..0] = FB_AD[31..16];
BL_HRAME_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50E"; -- $F8A1C/2
BL_HRAME[15..8].ENA = BL_HRAME_CS & !nFB_WR & FB_16B0;
BL_HRAME[7..0].ENA = BL_HRAME_CS & !nFB_WR & FB_16B1;
-- HALFTON RAM 15
BL_HRAMF[].CLK = MAIN_CLK;
BL_HRAMF[15..0] = FB_AD[31..16];
BL_HRAMF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50F"; -- $F8A1E/2
BL_HRAMF[15..8].ENA = BL_HRAMF_CS & !nFB_WR & FB_16B0;
BL_HRAMF[7..0].ENA = BL_HRAMF_CS & !nFB_WR & FB_16B1;
-- SRC X INC
BL_SRC_X_INC[].CLK = MAIN_CLK;
BL_SRC_X_INC[] = FB_AD[31..16];
BL_SRC_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C510"; -- $F8A20/2
BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_X_INC[7..0].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
-- SRC Y INC
BL_SRC_Y_INC[].CLK = MAIN_CLK;
BL_SRC_Y_INC[] = FB_AD[31..16];
BL_SRC_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C511"; -- $F8A22/2
BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_Y_INC[7..0].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
-- SRC ADR HIGH
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[31..16] = FB_AD[31..16];
BL_SRC_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512"; -- $F8A24/2
BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
-- SRC ADR LOW
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[15..0] = FB_AD[31..16];
BL_SRC_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513"; -- $F8A26/2
BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[7..0].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
-- ENDMASK 1
BL_ENDMASK1[].CLK = MAIN_CLK;
BL_ENDMASK1[] = FB_AD[31..16];
BL_ENDMASK1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C514"; -- $F8A28/2
BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
BL_ENDMASK1[7..0].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
-- ENDMASK 2
BL_ENDMASK2[].CLK = MAIN_CLK;
BL_ENDMASK2[] = FB_AD[31..16];
BL_ENDMASK2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C515"; -- $F8A2A/2
BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
BL_ENDMASK2[7..0].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
-- ENDMASK 3
BL_ENDMASK3[].CLK = MAIN_CLK;
BL_ENDMASK3[] = FB_AD[31..16];
BL_ENDMASK3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C516"; -- $F8A2C/2
BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
BL_ENDMASK3[7..0].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
-- DST X INC
BL_DST_X_INC[].CLK = MAIN_CLK;
BL_DST_X_INC[] = FB_AD[31..16];
BL_DST_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C517"; -- $F8A2E/2
BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
BL_DST_X_INC[7..0].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
-- DST Y INC
BL_DST_Y_INC[].CLK = MAIN_CLK;
BL_DST_Y_INC[] = FB_AD[31..16];
BL_DST_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C518"; -- $F8A30/2
BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
BL_DST_Y_INC[7..0].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
-- DST ADR HIGH
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[31..16] = FB_AD[31..16];
BL_DST_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512"; -- $F8A24/2
BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
-- DST ADR LOW
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[15..0] = FB_AD[31..16];
BL_DST_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513"; -- $F8A26/2
BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[7..0].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
-- X COUNT
BL_X_CNT[].CLK = MAIN_CLK;
BL_X_CNT[] = FB_AD[31..16];
BL_X_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51B"; -- $F8A36/2
BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
BL_X_CNT[7..0].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B1;
-- Y COUNT
BL_Y_CNT[].CLK = MAIN_CLK;
BL_Y_CNT[] = FB_AD[31..16];
BL_Y_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51C"; -- $F8A38/2
BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
BL_Y_CNT[7..0].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
-- HALFTONE OP BYT
BL_HT_OP[].CLK = MAIN_CLK;
BL_HT_OP[] = FB_AD[31..24];
BL_HT_OP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51D"; -- $F8A3A/2
BL_HT_OP[7..0].ENA = BL_HT_OP_CS & !nFB_WR & FB_16B0;
-- LOGIC OP BYT
BL_LC_OP[].CLK = MAIN_CLK;
BL_LC_OP[] = FB_AD[23..16];
BL_LC_OP[7..0].ENA = BL_HT_OP_CS & !nFB_WR & FB_16B1; -- $F8A3B
-- LINE NUMBER BYT
BL_LN[].CLK = MAIN_CLK;
BL_LN[] = FB_AD[31..24];
BL_LN_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51E"; -- $F8A3C/2
BL_LN[7..0].ENA = BL_LN_CS & !nFB_WR & FB_16B0;
-- SKEW BYT
BL_SKEW[].CLK = MAIN_CLK;
BL_SKEW[] = FB_AD[31..24];
BL_SKEW[7..0].ENA = BL_LN_CS & !nFB_WR & FB_16B1; -- $F8A3D
--- REGISTER OUT
FB_AD[31..16] = lpm_bustri_WORD(
BL_HRAM0_CS & BL_HRAM0[15..0]
# BL_HRAM1_CS & BL_HRAM1[15..0]
# BL_HRAM2_CS & BL_HRAM2[15..0]
# BL_HRAM3_CS & BL_HRAM3[15..0]
# BL_HRAM4_CS & BL_HRAM4[15..0]
# BL_HRAM5_CS & BL_HRAM5[15..0]
# BL_HRAM6_CS & BL_HRAM6[15..0]
# BL_HRAM7_CS & BL_HRAM7[15..0]
# BL_HRAM8_CS & BL_HRAM8[15..0]
# BL_HRAM9_CS & BL_HRAM9[15..0]
# BL_HRAMA_CS & BL_HRAMA[15..0]
# BL_HRAMB_CS & BL_HRAMB[15..0]
# BL_HRAMC_CS & BL_HRAMC[15..0]
# BL_HRAMD_CS & BL_HRAMD[15..0]
# BL_HRAME_CS & BL_HRAME[15..0]
# BL_HRAMF_CS & BL_HRAMF[15..0]
# BL_SRC_X_INC_CS & BL_SRC_X_INC[]
# BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
# BL_SRC_ADRH_CS & BL_SRC_ADR[31..16]
# BL_SRC_ADRL_CS & BL_SRC_ADR[15..0]
# BL_ENDMASK1_CS & BL_ENDMASK1[]
# BL_ENDMASK2_CS & BL_ENDMASK2[]
# BL_ENDMASK3_CS & BL_ENDMASK3[]
# BL_DST_X_INC_CS & BL_DST_X_INC[]
# BL_DST_Y_INC_CS & BL_DST_Y_INC[]
# BL_DST_ADRH_CS & BL_DST_ADR[31..16]
# BL_DST_ADRL_CS & BL_DST_ADR[15..0]
# BL_X_CNT_CS & BL_X_CNT[]
# BL_Y_CNT_CS & BL_Y_CNT[]
# BL_HT_OP_CS & (BL_HT_OP[],BL_LC_OP[])
# BL_LN_CS & (BL_LN[],BL_SKEW[])
,!nFB_CS1 & FB_ADR[19..6]==H"3E28" & !nFB_OE); -- FFFF8A00-3F/40
-----------------------------------------
--
BL_READ_SRC.CLK = DDRCLK0;
BL_READ_DST.CLK = DDRCLK0;
BLITTER_RUN = VCC;
BLITTER_SIG = VCC;
BLITTER_WR = VCC;
-- READY SIGNAL 1 CLOCK SP<53>TER
BL_DATA_DDR_READY.CLK = DDRCLK0;
BL_DATA_DDR_READY = BL_DATA_DDR_READY & BLITTER_DACK0;
-- SRC BUFFER LADEN
BL_SKEW_IN[].CLK = DDRCLK0;
BL_SKEW_IN[].ENA = BL_DATA_DDR_READY & BL_READ_SRC;
BL_SKEW_IN[255..128] = BLITTER_DIN[];
BL_SKEW_IN[127..0] = BL_SKEW_IN[255..128];
-- DST BUFFER LADEN
BL_DST_BUFFER[].CLK = DDRCLK0;
BL_DST_BUFFER[].ENA = BL_DATA_DDR_READY & BL_READ_DST;
BL_DST_BUFFER[] = BLITTER_DIN[];
-- SKEW EXTENDET
BL_SKEW_EXT[6..4] = BL_SRC_ADR[3..1];
BL_SKEW_EXT[3..0] = BL_SKEW[3..0];
-- SKEW EXT MUX
BL_SKEW_OUT[].CLK = DDRCLK0;
BL_SKEW_OUT[].ENA = BL_DATA_DDR_READY & BL_READ_DST;
BL_SKEW_OUT[] = lpm_clshift0(BL_SKEW_IN[],BL_SKEW_EXT[]); -- BIT 127..0 SIND RELEVANT
COUNT[] = COUNT[] + 16;
COUNT[].CLK = BLITTER_DACK0;
BLITTER_DOUT[] = H"112233445566778899AABBCCDDEEFF00";
BLITTER_ADR[] = (0, COUNT[]) + 400000;
END;

54
FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.bsf
View File

@@ -1,54 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 208 80)
(text "lpm_clshift0" (rect 62 3 162 22)(font "Arial" (font_size 10)))
(text "inst" (rect 8 61 31 76)(font "Arial" ))
(port
(pt 0 24)
(input)
(text "data[255..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
(text "data[255..0]" (rect 20 16 89 32)(font "Arial" (font_size 8)))
(line (pt 0 24)(pt 16 24)(line_width 3))
)
(port
(pt 0 40)
(input)
(text "distance[6..0]" (rect 0 0 93 16)(font "Arial" (font_size 8)))
(text "distance[6..0]" (rect 20 32 99 48)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 16 40)(line_width 3))
)
(port
(pt 208 24)
(output)
(text "result[255..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
(text "result[255..0]" (rect 113 16 189 32)(font "Arial" (font_size 8)))
(line (pt 208 24)(pt 192 24)(line_width 3))
)
(drawing
(text "LOGICAL right shift" (rect 21 50 114 64)(font "Arial" ))
(line (pt 16 16)(pt 16 64)(line_width 1))
(line (pt 192 16)(pt 192 64)(line_width 1))
(line (pt 16 16)(pt 192 16)(line_width 1))
(line (pt 16 64)(pt 192 64)(line_width 1))
)
)

21
FPGA_by_Fredi/Video/BLITTER/altsyncram0.cmp → FPGA_by_Fredi/Video/BLITTER/lpm_clshift144.inc
View File

@@ -13,14 +13,13 @@
--applicable agreement for further details. --applicable agreement for further details.
component altsyncram0 FUNCTION lpm_clshift144
PORT (
( data[143..0],
address : IN STD_LOGIC_VECTOR (3 DOWNTO 0); direction,
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '1'); distance[7..0]
clock : IN STD_LOGIC := '1'; )
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren : IN STD_LOGIC := '0'; RETURNS (
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) result[143..0]
); );
end component;

4
FPGA_by_Fredi/Video/BLITTER/lpm_clshift144.qip Normal file
View File

@@ -0,0 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "LPM_CLSHIFT"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift144.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift144.inc"]

94
FPGA_by_Fredi/Video/BLITTER/lpm_clshift144.tdf Normal file
View File

@@ -0,0 +1,94 @@
-- megafunction wizard: %LPM_CLSHIFT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_clshift
-- ============================================================
-- File Name: lpm_clshift144.tdf
-- Megafunction Name(s):
-- lpm_clshift
--
-- Simulation Library Files(s):
--
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
INCLUDE "lpm_clshift.inc";
SUBDESIGN lpm_clshift144
(
data[143..0] : INPUT;
direction : INPUT;
distance[7..0] : INPUT;
result[143..0] : OUTPUT;
)
VARIABLE
lpm_clshift_component : lpm_clshift WITH (
LPM_SHIFTTYPE = "LOGICAL",
LPM_TYPE = "LPM_CLSHIFT",
LPM_WIDTH = 144,
LPM_WIDTHDIST = 8
);
BEGIN
result[143..0] = lpm_clshift_component.result[143..0];
lpm_clshift_component.distance[7..0] = distance[7..0];
lpm_clshift_component.direction = direction;
lpm_clshift_component.data[143..0] = data[143..0];
END;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_SHIFTTYPE NUMERIC "0"
-- Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "144"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: lpm_width_varies NUMERIC "0"
-- Retrieval info: PRIVATE: lpm_widthdist NUMERIC "8"
-- Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "0"
-- Retrieval info: PRIVATE: port_direction NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_SHIFTTYPE STRING "LOGICAL"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CLSHIFT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "144"
-- Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "8"
-- Retrieval info: USED_PORT: data 0 0 144 0 INPUT NODEFVAL data[143..0]
-- Retrieval info: USED_PORT: direction 0 0 0 0 INPUT NODEFVAL direction
-- Retrieval info: USED_PORT: distance 0 0 8 0 INPUT NODEFVAL distance[7..0]
-- Retrieval info: USED_PORT: result 0 0 144 0 OUTPUT NODEFVAL result[143..0]
-- Retrieval info: CONNECT: @distance 0 0 8 0 distance 0 0 8 0
-- Retrieval info: CONNECT: @data 0 0 144 0 data 0 0 144 0
-- Retrieval info: CONNECT: result 0 0 144 0 @result 0 0 144 0
-- Retrieval info: CONNECT: @direction 0 0 0 0 direction 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift144.tdf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift144.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift144.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift144.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift144_inst.tdf FALSE

25
FPGA_by_Fredi/Video/BLITTER/lpm_clshift384.inc Normal file
View File

@@ -0,0 +1,25 @@
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION lpm_clshift384
(
data[383..0],
direction,
distance[7..0]
)
RETURNS (
result[383..0]
);

5
FPGA_by_Fredi/Video/BLITTER/lpm_clshift384.qip Normal file
View File

@@ -0,0 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "LPM_CLSHIFT"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift384.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift384.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift384.cmp"]

50
FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.tdf → FPGA_by_Fredi/Video/BLITTER/lpm_clshift384.tdf
View File

@@ -36,11 +36,12 @@ INCLUDE "lpm_clshift.inc";
SUBDESIGN lpm_clshift0 SUBDESIGN lpm_clshift384
( (
data[255..0] : INPUT; data[383..0] : INPUT;
distance[6..0] : INPUT; direction : INPUT;
result[255..0] : OUTPUT; distance[7..0] : INPUT;
result[383..0] : OUTPUT;
) )
VARIABLE VARIABLE
@@ -48,16 +49,16 @@ VARIABLE
lpm_clshift_component : lpm_clshift WITH ( lpm_clshift_component : lpm_clshift WITH (
LPM_SHIFTTYPE = "LOGICAL", LPM_SHIFTTYPE = "LOGICAL",
LPM_TYPE = "LPM_CLSHIFT", LPM_TYPE = "LPM_CLSHIFT",
LPM_WIDTH = 256, LPM_WIDTH = 384,
LPM_WIDTHDIST = 7 LPM_WIDTHDIST = 8
); );
BEGIN BEGIN
result[255..0] = lpm_clshift_component.result[255..0]; result[383..0] = lpm_clshift_component.result[383..0];
lpm_clshift_component.distance[6..0] = distance[6..0]; lpm_clshift_component.distance[7..0] = distance[7..0];
lpm_clshift_component.direction = VCC; lpm_clshift_component.direction = direction;
lpm_clshift_component.data[255..0] = data[255..0]; lpm_clshift_component.data[383..0] = data[383..0];
END; END;
@@ -67,26 +68,27 @@ END;
-- ============================================================ -- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_SHIFTTYPE NUMERIC "0" -- Retrieval info: PRIVATE: LPM_SHIFTTYPE NUMERIC "0"
-- Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "256" -- Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "384"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: lpm_width_varies NUMERIC "0" -- Retrieval info: PRIVATE: lpm_width_varies NUMERIC "0"
-- Retrieval info: PRIVATE: lpm_widthdist NUMERIC "7" -- Retrieval info: PRIVATE: lpm_widthdist NUMERIC "8"
-- Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "1" -- Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "0"
-- Retrieval info: PRIVATE: port_direction NUMERIC "1" -- Retrieval info: PRIVATE: port_direction NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_SHIFTTYPE STRING "LOGICAL" -- Retrieval info: CONSTANT: LPM_SHIFTTYPE STRING "LOGICAL"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CLSHIFT" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CLSHIFT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "256" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "384"
-- Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "7" -- Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "8"
-- Retrieval info: USED_PORT: data 0 0 256 0 INPUT NODEFVAL data[255..0] -- Retrieval info: USED_PORT: data 0 0 384 0 INPUT NODEFVAL data[383..0]
-- Retrieval info: USED_PORT: distance 0 0 7 0 INPUT NODEFVAL distance[6..0] -- Retrieval info: USED_PORT: direction 0 0 0 0 INPUT NODEFVAL direction
-- Retrieval info: USED_PORT: result 0 0 256 0 OUTPUT NODEFVAL result[255..0] -- Retrieval info: USED_PORT: distance 0 0 8 0 INPUT NODEFVAL distance[7..0]
-- Retrieval info: CONNECT: @distance 0 0 7 0 distance 0 0 7 0 -- Retrieval info: USED_PORT: result 0 0 384 0 OUTPUT NODEFVAL result[383..0]
-- Retrieval info: CONNECT: @data 0 0 256 0 data 0 0 256 0 -- Retrieval info: CONNECT: @distance 0 0 8 0 distance 0 0 8 0
-- Retrieval info: CONNECT: result 0 0 256 0 @result 0 0 256 0 -- Retrieval info: CONNECT: @data 0 0 384 0 data 0 0 384 0
-- Retrieval info: CONNECT: @direction 0 0 0 0 VCC 0 0 0 0 -- Retrieval info: CONNECT: result 0 0 384 0 @result 0 0 384 0
-- Retrieval info: CONNECT: @direction 0 0 0 0 direction 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.tdf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.tdf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0_inst.tdf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0_inst.tdf FALSE

58
FPGA_by_Fredi/Video/DDR_CTR.tdf
View File

@@ -6,8 +6,8 @@ INCLUDE "lpm_bustri_BYT.inc";
-- FIFO WATER MARK -- FIFO WATER MARK
CONSTANT FIFO_LWM = 0; CONSTANT FIFO_LWM = 0;
CONSTANT FIFO_MWM = 200; CONSTANT FIFO_MWM = 1000;
CONSTANT FIFO_HWM = 500; CONSTANT FIFO_HWM = 2000;
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! -- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! -- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
@@ -34,7 +34,7 @@ SUBDESIGN DDR_CTR
BLITTER_WR : INPUT; BLITTER_WR : INPUT;
DDRCLK0 : INPUT; DDRCLK0 : INPUT;
CLK33M : INPUT; CLK33M : INPUT;
FIFO_MW[8..0] : INPUT; FIFO_MW[10..0] : INPUT;
VA[12..0] : OUTPUT; VA[12..0] : OUTPUT;
nVWE : OUTPUT; nVWE : OUTPUT;
nVRAS : OUTPUT; nVRAS : OUTPUT;
@@ -205,26 +205,13 @@ BEGIN
DDR_REFRESH_ON = VIDEO_RAM_CTR2; DDR_REFRESH_ON = VIDEO_RAM_CTR2;
DDR_CONFIG = VIDEO_RAM_CTR3; DDR_CONFIG = VIDEO_RAM_CTR3;
FIFO_ACTIVE = VIDEO_RAM_CTR8; FIFO_ACTIVE = VIDEO_RAM_CTR8;
-------------------------------- ----------------------------------------------------------------
-- CPU ---------------------------
--------------------------------------------------------
CPU_ROW_ADR[] = FB_ADR[26..14]; CPU_ROW_ADR[] = FB_ADR[26..14];
CPU_BA[] = FB_ADR[13..12]; CPU_BA[] = FB_ADR[13..12];
CPU_COL_ADR[] = FB_ADR[11..2]; CPU_COL_ADR[] = FB_ADR[11..2];
nVRAS = !VRAS;
nVCAS = !VCAS;
nVWE = !VWE;
SR_DDR_WR.CLK = DDRCLK0;
SR_DDRWR_D_SEL.CLK = DDRCLK0;
SR_VDMP[7..0].CLK = DDRCLK0;
SR_FIFO_WRE.CLK = DDRCLK0;
CPU_AC.CLK = DDRCLK0; CPU_AC.CLK = DDRCLK0;
FIFO_AC.CLK = DDRCLK0;
BLITTER_AC.CLK = DDRCLK0;
DDRWR_D_SEL1 = BLITTER_AC;
-- SELECT LOGIC
DDR_SEL = FB_ALE & FB_AD[31..30]==B"01";
DDR_CS.CLK = MAIN_CLK;
DDR_CS.ENA = FB_ALE;
DDR_CS = DDR_SEL;
-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP<53>TER -- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP<53>TER
CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
# DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS # DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS
@@ -234,6 +221,30 @@ BEGIN
# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG # CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG
BUS_CYC.CLK = DDRCLK0; BUS_CYC.CLK = DDRCLK0;
BUS_CYC = BUS_CYC & !BUS_CYC_END; BUS_CYC = BUS_CYC & !BUS_CYC_END;
-- SELECT LOGIC
DDR_SEL = FB_ALE & FB_AD[31..30]==B"01";
DDR_CS.CLK = MAIN_CLK;
DDR_CS.ENA = FB_ALE;
DDR_CS = DDR_SEL;
---------------------------------------------------------------
-- BLITTER ----------------------
-----------------------------------------
BLITTER_REQ.CLK = DDRCLK0;
BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS;
BLITTER_ROW_ADR[] = BLITTER_ADR[26..14];
BLITTER_BA[] = BLITTER_ADR[13..12];
BLITTER_COL_ADR[] = BLITTER_ADR[11..2];
BLITTER_AC.CLK = DDRCLK0;
DDRWR_D_SEL1 = BLITTER_AC;
---------------------------------------------------
nVRAS = !VRAS;
nVCAS = !VCAS;
nVWE = !VWE;
SR_DDR_WR.CLK = DDRCLK0;
SR_DDRWR_D_SEL.CLK = DDRCLK0;
SR_VDMP[7..0].CLK = DDRCLK0;
SR_FIFO_WRE.CLK = DDRCLK0;
FIFO_AC.CLK = DDRCLK0;
-- STATE MACHINE SYNCHRONISIEREN ----------------- -- STATE MACHINE SYNCHRONISIEREN -----------------
MCS[].CLK = DDRCLK0; MCS[].CLK = DDRCLK0;
MCS0 = MAIN_CLK; MCS0 = MAIN_CLK;
@@ -563,15 +574,6 @@ BEGIN
DDR_SM = DS_T1; DDR_SM = DS_T1;
END CASE; END CASE;
---------------------------------------------------------------
-- BLITTER ----------------------
-----------------------------------------
BLITTER_REQ.CLK = DDRCLK0;
BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS;
BLITTER_ROW_ADR[] = BLITTER_ADR[26..14];
BLITTER_BA1 = BLITTER_ADR13;
BLITTER_BA0 = BLITTER_ADR12;
BLITTER_COL_ADR[] = BLITTER_ADR[11..2];
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- FIFO --------------------------------- -- FIFO ---------------------------------
-------------------------------------------------------- --------------------------------------------------------

659
FPGA_by_Fredi/Video/DDR_CTR.tdf.bak
View File

@@ -1,659 +0,0 @@
TITLE "DDR_CTR";
-- CREATED BY FREDI ASCHWANDEN
INCLUDE "lpm_bustri_BYT.inc";
-- FIFO WATER MARK
CONSTANT FIFO_LWM = 0;
CONSTANT FIFO_MWM = 200;
CONSTANT FIFO_HWM = 500;
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
SUBDESIGN DDR_CTR
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
FB_ADR[31..0] : INPUT;
nFB_CS1 : INPUT;
nFB_CS2 : INPUT;
nFB_CS3 : INPUT;
nFB_OE : INPUT;
FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT;
nRSTO : INPUT;
MAIN_CLK : INPUT;
FB_ALE : INPUT;
nFB_WR : INPUT;
DDR_SYNC_66M : INPUT;
CLR_FIFO : INPUT;
VIDEO_RAM_CTR[15..0] : INPUT;
BLITTER_ADR[31..0] : INPUT;
BLITTER_SIG : INPUT;
BLITTER_WR : INPUT;
DDRCLK0 : INPUT;
CLK33M : INPUT;
FIFO_MW[8..0] : INPUT;
VA[12..0] : OUTPUT;
nVWE : OUTPUT;
nVRAS : OUTPUT;
nVCS : OUTPUT;
VCKE : OUTPUT;
nVCAS : OUTPUT;
FB_LE[3..0] : OUTPUT;
FB_VDOE[3..0] : OUTPUT;
SR_FIFO_WRE : OUTPUT;
SR_DDR_FB : OUTPUT;
SR_DDR_WR : OUTPUT;
SR_DDRWR_D_SEL : OUTPUT;
SR_VDMP[7..0] : OUTPUT;
VIDEO_DDR_TA : OUTPUT;
SR_BLITTER_DACK : OUTPUT;
BA[1..0] : OUTPUT;
DDRWR_D_SEL1 : OUTPUT;
VDM_SEL[3..0] : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
VARIABLE
FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);
DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8, -- START (NORMAL 8 CYCLES TOTAL = 60ns)
DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, -- CONFIG
DS_T4R,DS_T5R, -- READ CPU UND BLITTER,
DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W, -- WRITE CPU UND BLITTER
DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, -- READ FIFO
DS_CB6, DS_CB8, -- CLOSE FIFO BANK
DS_R2,DS_R3,DS_R4, DS_R5, DS_R6); -- REFRESH 10X7.5NS=75NS
LINE :NODE;
FB_B[3..0] :NODE;
VCAS :NODE;
VRAS :NODE;
VWE :NODE;
VA_P[12..0] :DFF;
BA_P[1..0] :DFF;
VA_S[12..0] :DFF;
BA_S[1..0] :DFF;
MCS[1..0] :DFF;
CPU_DDR_SYNC :DFF;
DDR_SEL :NODE;
DDR_CS :DFFE;
DDR_CONFIG :NODE;
SR_DDR_WR :DFF;
SR_DDRWR_D_SEL :DFF;
SR_VDMP[7..0] :DFF;
CPU_ROW_ADR[12..0] :NODE;
CPU_BA[1..0] :NODE;
CPU_COL_ADR[9..0] :NODE;
CPU_SIG :NODE;
CPU_REQ :DFF;
CPU_AC :DFF;
BUS_CYC :DFF;
BUS_CYC_END :NODE;
BLITTER_REQ :DFF;
BLITTER_AC :DFF;
BLITTER_ROW_ADR[12..0] :NODE;
BLITTER_BA[1..0] :NODE;
BLITTER_COL_ADR[9..0] :NODE;
FIFO_REQ :DFF;
FIFO_AC :DFF;
FIFO_ROW_ADR[12..0] :NODE;
FIFO_BA[1..0] :NODE;
FIFO_COL_ADR[9..0] :NODE;
FIFO_ACTIVE :NODE;
CLR_FIFO_SYNC :DFF;
CLEAR_FIFO_CNT :DFF;
STOP :DFF;
SR_FIFO_WRE :DFF;
FIFO_BANK_OK :DFF;
FIFO_BANK_NOT_OK :NODE;
DDR_REFRESH_ON :NODE;
DDR_REFRESH_CNT[10..0] :DFF;
DDR_REFRESH_REQ :DFF;
DDR_REFRESH_SIG[3..0] :DFFE;
REFRESH_TIME :DFF;
VIDEO_BASE_L_D[7..0] :DFFE;
VIDEO_BASE_L :NODE;
VIDEO_BASE_M_D[7..0] :DFFE;
VIDEO_BASE_M :NODE;
VIDEO_BASE_H_D[7..0] :DFFE;
VIDEO_BASE_H :NODE;
VIDEO_BASE_X_D[2..0] :DFFE;
VIDEO_ADR_CNT[22..0] :DFFE;
VIDEO_CNT_L :NODE;
VIDEO_CNT_M :NODE;
VIDEO_CNT_H :NODE;
VIDEO_BASE_ADR[22..0] :NODE;
VIDEO_ACT_ADR[26..0] :NODE;
BEGIN
LINE = FB_SIZE0 & FB_SIZE1;
-- BYT SELECT
FB_B0 = FB_ADR[1..0]==0 -- ADR==0
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) --------------------------------------------------
FB_REGDDR.CLK = MAIN_CLK;
CASE FB_REGDDR IS
WHEN FR_WAIT =>
FB_LE0 = !nFB_WR;
IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE
FB_REGDDR = FR_S0;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S0 =>
IF DDR_CS THEN
FB_LE0 = !nFB_WR;
VIDEO_DDR_TA = VCC;
IF LINE THEN
FB_VDOE0 = !nFB_OE & !DDR_CONFIG;
FB_REGDDR = FR_S1;
ELSE
BUS_CYC_END = VCC;
FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
FB_REGDDR = FR_WAIT;
END IF;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S1 =>
IF DDR_CS THEN
FB_VDOE1 = !nFB_OE & !DDR_CONFIG;
FB_LE1 = !nFB_WR;
VIDEO_DDR_TA = VCC;
FB_REGDDR = FR_S2;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S2 =>
IF DDR_CS THEN
FB_VDOE2 = !nFB_OE & !DDR_CONFIG;
FB_LE2 = !nFB_WR;
IF !BUS_CYC & LINE & !nFB_WR THEN -- BEI LINE WRITE EVT. WARTEN
FB_REGDDR = FR_S2;
ELSE
VIDEO_DDR_TA = VCC;
FB_REGDDR = FR_S3;
END IF;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S3 =>
IF DDR_CS THEN
FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
FB_LE3 = !nFB_WR;
VIDEO_DDR_TA = VCC;
BUS_CYC_END = VCC;
FB_REGDDR = FR_WAIT;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
END CASE;
-- DDR STEUERUNG -----------------------------------------------------
-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE;
VCKE = VIDEO_RAM_CTR0;
nVCS = !VIDEO_RAM_CTR1;
DDR_REFRESH_ON = VIDEO_RAM_CTR2;
DDR_CONFIG = VIDEO_RAM_CTR3;
FIFO_ACTIVE = VIDEO_RAM_CTR8;
--------------------------------
CPU_ROW_ADR[] = FB_ADR[26..14];
CPU_BA[] = FB_ADR[13..12];
CPU_COL_ADR[] = FB_ADR[11..2];
nVRAS = !VRAS;
nVCAS = !VCAS;
nVWE = !VWE;
SR_DDR_WR.CLK = DDRCLK0;
SR_DDRWR_D_SEL.CLK = DDRCLK0;
SR_VDMP[7..0].CLK = DDRCLK0;
SR_FIFO_WRE.CLK = DDRCLK0;
CPU_AC.CLK = DDRCLK0;
FIFO_AC.CLK = DDRCLK0;
BLITTER_AC.CLK = DDRCLK0;
DDRWR_D_SEL1 = BLITTER_AC;
-- SELECT LOGIC
DDR_SEL = FB_ALE & FB_AD[31..30]==B"01";
DDR_CS.CLK = MAIN_CLK;
DDR_CS.ENA = FB_ALE;
DDR_CS = DDR_SEL;
-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP<53>TER
CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
# DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS
# FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SP<53>TER
CPU_REQ.CLK = DDR_SYNC_66M;
CPU_REQ = CPU_SIG
# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG
BUS_CYC.CLK = DDRCLK0;
BUS_CYC = BUS_CYC & !BUS_CYC_END;
-- STATE MACHINE SYNCHRONISIEREN -----------------
MCS[].CLK = DDRCLK0;
MCS0 = MAIN_CLK;
MCS1 = MCS0;
CPU_DDR_SYNC.CLK = DDRCLK0;
CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS; -- NUR 1 WENN EIN
---------------------------------------------------
VA_S[].CLK = DDRCLK0;
BA_S[].CLK = DDRCLK0;
VA[] = VA_S[];
BA[] = BA_S[];
VA_P[].CLK = DDRCLK0;
BA_P[].CLK = DDRCLK0;
-- DDR STATE MACHINE -----------------------------------------------
DDR_SM.CLK = DDRCLK0;
CASE DDR_SM IS
WHEN DS_T1 =>
IF DDR_REFRESH_REQ THEN
DDR_SM = DS_R2;
ELSE
IF CPU_DDR_SYNC THEN -- SYNCHRON UND EIN?
IF DDR_CONFIG THEN -- JA
DDR_SM = DS_C2;
ELSE
IF CPU_REQ THEN -- BEI WAIT UND LINE WRITE
VA_S[] = CPU_ROW_ADR[];
BA_S[] = CPU_BA[];
CPU_AC = VCC;
BUS_CYC = VCC;
DDR_SM = DS_T2B;
ELSE
IF FIFO_REQ # !BLITTER_REQ THEN -- FIFO IST DEFAULT
VA_P[] = FIFO_ROW_ADR[];
BA_P[] = FIFO_BA[];
FIFO_AC = VCC; -- VORBESETZEN
ELSE
VA_P[] = BLITTER_ROW_ADR[];
BA_P[] = BLITTER_BA[];
BLITTER_AC = VCC; -- VORBESETZEN
END IF;
DDR_SM = DS_T2A;
END IF;
END IF;
ELSE
DDR_SM = DS_T1; -- NEIN ->SYNCHRONISIEREN
END IF;
END IF;
WHEN DS_T2A => -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK ***
IF DDR_SEL & (nFB_WR # !LINE) THEN
VRAS = VCC;
VA[] = FB_AD[26..14];
BA[] = FB_AD[13..12];
VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO PAGE
CPU_AC = VCC;
BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN
ELSE
VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ;
VA[] = VA_P[];
BA[] = BA_P[];
VA_S[10] = !(FIFO_AC & FIFO_REQ);
FIFO_BANK_OK = FIFO_AC & FIFO_REQ;
FIFO_AC = FIFO_AC & FIFO_REQ;
BLITTER_AC = BLITTER_AC & BLITTER_REQ;
END IF;
DDR_SM = DS_T3;
WHEN DS_T2B =>
VRAS = VCC;
FIFO_BANK_NOT_OK = VCC;
CPU_AC = VCC;
BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN
DDR_SM = DS_T3;
WHEN DS_T3 =>
CPU_AC = CPU_AC;
FIFO_AC = FIFO_AC;
BLITTER_AC = BLITTER_AC;
VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN
DDR_SM = DS_T4W;
ELSE
IF CPU_AC THEN -- CPU?
VA_S[9..0] = CPU_COL_ADR[];
BA_S[] = CPU_BA[];
DDR_SM = DS_T4R;
ELSE
IF FIFO_AC THEN -- FIFO?
VA_S[9..0] = FIFO_COL_ADR[];
BA_S[] = FIFO_BA[];
DDR_SM = DS_T4F;
ELSE
IF BLITTER_AC THEN
VA_S[9..0] = BLITTER_COL_ADR[];
BA_S[] = BLITTER_BA[];
DDR_SM = DS_T4R;
ELSE
DDR_SM = DS_N8;
END IF;
END IF;
END IF;
END IF;
-- READ
WHEN DS_T4R =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
VCAS = VCC;
SR_DDR_FB = CPU_AC; -- READ DATEN F<>R CPU
SR_BLITTER_DACK = BLITTER_AC; -- BLITTER DACK AND BLITTER LATCH DATEN
DDR_SM = DS_T5R;
WHEN DS_T5R =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
IF FIFO_REQ & FIFO_BANK_OK THEN -- FIFO READ EINSCHIEBEN WENN BANK OK
VA_S[9..0] = FIFO_COL_ADR[];
VA_S[10] = GND; -- MANUEL PRECHARGE
BA_S[] = FIFO_BA[];
DDR_SM = DS_T6F;
ELSE
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB6;
END IF;
-- WRITE
WHEN DS_T4W =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
SR_BLITTER_DACK = BLITTER_AC; -- BLITTER ACK AND BLITTER LATCH DATEN
VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
DDR_SM = DS_T5W;
WHEN DS_T5W =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
VA_S[9..0] = CPU_AC & CPU_COL_ADR[]
# BLITTER_AC & BLITTER_COL_ADR[];
VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
BA_S[] = CPU_AC & CPU_BA[]
# BLITTER_AC & BLITTER_BA[];
SR_VDMP[7..4] = FB_B[]; -- BYTE ENABLE WRITE
SR_VDMP[3..0] = LINE & B"1111"; -- LINE ENABLE WRITE
DDR_SM = DS_T6W;
WHEN DS_T6W =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
VCAS = VCC;
VWE = VCC;
SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV
DDR_SM = DS_T7W;
WHEN DS_T7W =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITE
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
DDR_SM = DS_T8W;
WHEN DS_T8W =>
DDR_SM = DS_T9W;
WHEN DS_T9W =>
IF FIFO_REQ & FIFO_BANK_OK THEN
VA_S[9..0] = FIFO_COL_ADR[];
VA_S[10] = GND; -- NON AUTO PRECHARGE
BA_S[] = FIFO_BA[];
DDR_SM = DS_T6F;
ELSE
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB6;
END IF;
-- FIFO READ
WHEN DS_T4F =>
VCAS = VCC;
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
DDR_SM = DS_T5F;
WHEN DS_T5F =>
IF FIFO_REQ THEN
IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE?
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB6; -- BANK SCHLIESSEN
ELSE
VA_S[9..0] = FIFO_COL_ADR[]+4;
VA_S[10] = GND; -- NON AUTO PRECHARGE
BA_S[] = FIFO_BA[];
DDR_SM = DS_T6F;
END IF;
ELSE
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB6; -- NOCH OFFEN LASSEN
END IF;
WHEN DS_T6F =>
VCAS = VCC;
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
DDR_SM = DS_T7F;
WHEN DS_T7F =>
IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN
VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN
DDR_SM = DS_CB8; -- BANK SCHLIESSEN
ELSE
IF FIFO_REQ THEN
IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE?
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB8; -- BANK SCHLIESSEN
ELSE
VA_S[9..0] = FIFO_COL_ADR[]+4;
VA_S[10] = GND; -- NON AUTO PRECHARGE
BA_S[] = FIFO_BA[];
DDR_SM = DS_T8F;
END IF;
ELSE
VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN
DDR_SM = DS_CB8; -- BANK SCHLIESSEN
END IF;
END IF;
WHEN DS_T8F =>
VCAS = VCC;
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
IF FIFO_MW[]<FIFO_LWM THEN -- NOTFALL?
DDR_SM = DS_T5F; -- JA->
ELSE
DDR_SM = DS_T9F;
END IF;
WHEN DS_T9F =>
IF FIFO_REQ THEN
IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE?
VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN
DDR_SM = DS_CB6; -- BANK SCHLIESSEN
ELSE
VA_P[9..0] = FIFO_COL_ADR[]+4;
VA_P[10] = GND; -- NON AUTO PRECHARGE
BA_P[] = FIFO_BA[];
DDR_SM = DS_T10F;
END IF;
ELSE
VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN
DDR_SM = DS_CB6; -- BANK SCHLIESSEN
END IF;
WHEN DS_T10F =>
IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN
VRAS = VCC;
VA[] = FB_AD[26..14];
BA[] = FB_AD[13..12];
CPU_AC = VCC;
BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN
VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO BANK
DDR_SM = DS_T3;
ELSE
VCAS = VCC;
VA[] = VA_P[];
BA[] = BA_P[];
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
DDR_SM = DS_T7F;
END IF;
-- CONFIG CYCLUS
WHEN DS_C2 =>
DDR_SM = DS_C3;
WHEN DS_C3 =>
BUS_CYC = CPU_REQ;
DDR_SM = DS_C4;
WHEN DS_C4 =>
IF CPU_REQ THEN
DDR_SM = DS_C5;
ELSE
DDR_SM = DS_T1;
END IF;
WHEN DS_C5 =>
DDR_SM = DS_C6;
WHEN DS_C6 =>
VA_S[] = FB_AD[12..0];
BA_S[] = FB_AD[14..13];
DDR_SM = DS_C7;
WHEN DS_C7 =>
VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE
VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE
VWE = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE
DDR_SM = DS_N8;
-- CLOSE FIFO BANK
WHEN DS_CB6 =>
FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK
VRAS = VCC; -- B<>NKE SCHLIESSEN
VWE = VCC;
DDR_SM = DS_N7;
WHEN DS_CB8 =>
FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK
VRAS = VCC; -- B<>NKE SCHLIESSEN
VWE = VCC;
DDR_SM = DS_T1;
-- REFRESH 70NS = 10 ZYCLEN
WHEN DS_R2 =>
IF DDR_REFRESH_SIG[]==9 THEN -- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN
VRAS = VCC; -- ALLE BANKS SCHLIESSEN
VWE = VCC;
VA[10] = VCC;
FIFO_BANK_NOT_OK = VCC;
DDR_SM = DS_R4;
ELSE
VCAS = VCC;
VRAS = VCC;
DDR_SM = DS_R3;
END IF;
WHEN DS_R3 =>
DDR_SM = DS_R4;
WHEN DS_R4 =>
DDR_SM = DS_R5;
WHEN DS_R5 =>
DDR_SM = DS_R6;
WHEN DS_R6 =>
DDR_SM = DS_N5;
-- LEERSCHLAUFE
WHEN DS_N5 =>
DDR_SM = DS_N6;
WHEN DS_N6 =>
DDR_SM = DS_N7;
WHEN DS_N7 =>
DDR_SM = DS_N8;
WHEN DS_N8 =>
DDR_SM = DS_T1;
END CASE;
---------------------------------------------------------------
-- BLITTER ----------------------
-----------------------------------------
BLITTER_REQ.CLK = DDRCLK0;
BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS;
BLITTER_ROW_ADR[] = BLITTER_ADR[26..14];
BLITTER_BA1 = BLITTER_ADR13;
BLITTER_BA0 = BLITTER_ADR12;
BLITTER_COL_ADR[] = BLITTER_ADR[11..2];
------------------------------------------------------------------------------
-- FIFO ---------------------------------
--------------------------------------------------------
FIFO_REQ.CLK = DDRCLK0;
FIFO_REQ = (FIFO_MW[]<FIFO_MWM
# FIFO_MW[]<FIFO_HWM & FIFO_REQ) & FIFO_ACTIVE & !CLEAR_FIFO_CNT & !STOP & !DDR_CONFIG & VCKE & !nVCS;
FIFO_ROW_ADR[] = VIDEO_ADR_CNT[22..10];
FIFO_BA1 = VIDEO_ADR_CNT9;
FIFO_BA0 = VIDEO_ADR_CNT8;
FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00");
FIFO_BANK_OK.CLK = DDRCLK0;
FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK;
-- Z<>HLER R<>CKSETZEN WENN CLR FIFO ----------------
CLR_FIFO_SYNC.CLK =DDRCLK0;
CLR_FIFO_SYNC = CLR_FIFO; -- SYNCHRONISIEREN
CLEAR_FIFO_CNT.CLK = DDRCLK0;
CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE;
STOP.CLK = DDRCLK0;
STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT;
-- Z<>HLEN -----------------------------------------------
VIDEO_ADR_CNT[].CLK = DDRCLK0;
VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT;
VIDEO_ADR_CNT[] = CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]
# !CLEAR_FIFO_CNT & VIDEO_ADR_CNT[]+1;
VIDEO_BASE_ADR[22..20] = VIDEO_BASE_X_D[];
VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[];
VIDEO_BASE_ADR[11..4] = VIDEO_BASE_M_D[];
VIDEO_BASE_ADR[3..0] = VIDEO_BASE_L_D[7..4];
VDM_SEL[] = VIDEO_BASE_L_D[3..0];
-- AKTUELLE VIDEO ADRESSE
VIDEO_ACT_ADR[26..4] = VIDEO_ADR_CNT[] - (0,FIFO_MW[]);
VIDEO_ACT_ADR[3..0] = VDM_SEL[];
-----------------------------------------------------------------------------------------
-- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
-----------------------------------------------------------------------------------------
DDR_REFRESH_CNT[].CLK = CLK33M;
DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- Z<>HLEN 0-2047
REFRESH_TIME.CLK = DDRCLK0;
REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK; -- SYNC
DDR_REFRESH_SIG[].CLK = DDRCLK0;
DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6;
DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 ST<53>CK (8 REFRESH UND 1 ALS VORLAUF)
# !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; -- MINUS 1 WENN GEMACHT
DDR_REFRESH_REQ.CLK = DDRCLK0;
DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG;
-----------------------------------------------------------
-- VIDEO REGISTER -----------------------
---------------------------------------------------------------------------------------------------------------------
VIDEO_BASE_L_D[].CLK = MAIN_CLK;
VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; -- 820D/2
VIDEO_BASE_L_D[] = FB_AD[23..16]; -- SORRY, NUR 16 BYT GRENZEN
VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1;
VIDEO_BASE_M_D[].CLK = MAIN_CLK;
VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; -- 8203/2
VIDEO_BASE_M_D[] = FB_AD[23..16];
VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3;
VIDEO_BASE_H_D[].CLK = MAIN_CLK;
VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100"; -- 8200-1/2
VIDEO_BASE_H_D[] = FB_AD[23..16];
VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1;
VIDEO_BASE_X_D[].CLK = MAIN_CLK;
VIDEO_BASE_X_D[] = FB_AD[26..24];
VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0;
VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; -- 8209/2
VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2
VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2
FB_AD[31..24] = lpm_bustri_BYT(
VIDEO_BASE_H & (0,VIDEO_BASE_X_D[])
# VIDEO_CNT_H & (0,VIDEO_ACT_ADR[26..24])
,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
FB_AD[23..16] = lpm_bustri_BYT(
VIDEO_BASE_L & VIDEO_BASE_L_D[]
# VIDEO_BASE_M & VIDEO_BASE_M_D[]
# VIDEO_BASE_H & VIDEO_BASE_H_D[]
# VIDEO_CNT_L & VIDEO_ACT_ADR[7..0]
# VIDEO_CNT_M & VIDEO_ACT_ADR[15..8]
# VIDEO_CNT_H & VIDEO_ACT_ADR[23..16]
,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE);
END;

352
FPGA_by_Fredi/Video/DDR_CTR_BLITTER.tdf.bak
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@@ -1,352 +0,0 @@
TITLE "DDR_CTR_BLITTER";
-- CREATED BY FREDI ASCHWANDEN
INCLUDE "lpm_bustri_BYT.inc";
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
SUBDESIGN DDR_CTR_BLITTER
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
FB_ADR[31..0] : INPUT;
nFB_CS1 : INPUT;
nFB_CS2 : INPUT;
nFB_CS3 : INPUT;
nFB_OE : INPUT;
FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT;
nRSTO : INPUT;
MAIN_CLK : INPUT;
FIFO_FULL : INPUT;
FB_ALE : INPUT;
nFB_WR : INPUT;
DDR_SYNC_66M : INPUT;
VSYNC : INPUT;
BLITTER_ON : INPUT;
VIDEO_RAM_CTR[15..0] : INPUT;
VDVZ[127..0] : INPUT;
DDRCLK[3..0] : INPUT;
BA0 : OUTPUT;
BA1 : OUTPUT;
VA[12..0] : OUTPUT;
nVWE : OUTPUT;
nVRAS : OUTPUT;
nVCS : OUTPUT;
VCKE : OUTPUT;
nVCAS : OUTPUT;
FIFO_WRE : OUTPUT;
FB_LE[3..0] : OUTPUT;
FB_VDOE[3..0] : OUTPUT;
START_CYC_RDWR : OUTPUT;
DDR_WR : OUTPUT;
CLEAR_FIFO_CNT : OUTPUT;
BLITTER_RUN : OUTPUT;
BLITTER_DOUT[127..0] : OUTPUT;
BLITTER_LE[3..0] : OUTPUT;
BLITTER_RDE : OUTPUT;
DDRWR_D_SEL[1..0] : OUTPUT;
VDMP[7..0] : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
VARIABLE
FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);
DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2,DS_T3,DS_T4,DS_T5,DS_T6,DS_T7,DS_T8,DS_LS);
LINE :NODE;
FB_B[3..0] :NODE;
VCAS :NODE;
VRAS :NODE;
VWE :NODE;
VA[12..0] :NODE;
BA0 :NODE;
BA1 :NODE;
DDR_WR :DFF;
DDR_SEL :NODE;
DDR_CONFIG :NODE;
DDRWR_D_SEL[1..0] :DFF;
CPU_ROW_ADR[12..0] :NODE;
CPU_BA0 :NODE;
CPU_BA1 :NODE;
CPU_COL_ADR[9..0] :NODE;
CPU_SIG :NODE;
CPU_REQ :DFF;
BLITTER_SIG :NODE;
BLITTER_REQ :DFF;
BLITTER_RUN :DFF;
BLITTER_WR :DFF;
BLITTER_ROW_ADR[12..0] :NODE;
BLITTER_BA0 :NODE;
BLITTER_BA1 :NODE;
BLITTER_COL_ADR[9..0] :NODE;
FIFO_SIG :NODE;
FIFO_REQ :DFF;
FIFO_ROW_ADR[12..0] :NODE;
FIFO_BA0 :NODE;
FIFO_BA1 :NODE;
FIFO_COL_ADR[9..0] :NODE;
FIFO_WRE :DFF;
FIFO_ACTIVE :NODE;
CLEAR_FIFO_CNT :DFF;
STOP :DFF;
DDR_REFRESH_ON :NODE;
VIDEO_BASE_L_D[3..0] :DFFE;
VIDEO_BASE_L :NODE;
VIDEO_BASE_M_D[7..0] :DFFE;
VIDEO_BASE_M :NODE;
VIDEO_BASE_H_D[7..0] :DFFE;
VIDEO_BASE_H :NODE;
VIDEO_BASE_X_D[7..0] :DFFE;
VIDEO_ADR_CNT[27..0] :DFFE;
VIDEO_CNT_L :NODE;
VIDEO_CNT_M :NODE;
VIDEO_CNT_H :NODE;
VIDEO_BASE_ADR[27..0] :NODE;
BEGIN
LINE = FB_SIZE0 & FB_SIZE1;
-- BYT SELECT
FB_B0 = FB_ADR[1..0]==0; -- ADR==0
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) --------------------------------------------------
FB_REGDDR.CLK = MAIN_CLK;
CASE FB_REGDDR IS
WHEN FR_WAIT =>
IF DDR_SEL THEN
FB_REGDDR = FR_S0;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S0 =>
FB_VDOE0 = !nFB_OE & !DDR_CONFIG;
FB_LE0 = !nFB_WR;
IF LINE THEN
FB_REGDDR = FR_S1;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S1 =>
FB_VDOE1 = !nFB_OE & !DDR_CONFIG;
FB_LE1 = !nFB_WR;
FB_REGDDR = FR_S2;
WHEN FR_S2 =>
FB_VDOE2 = !nFB_OE & !DDR_CONFIG;
FB_LE2 = !nFB_WR;
FB_REGDDR = FR_S3;
WHEN FR_S3 =>
FB_VDOE3 = !nFB_OE & !DDR_CONFIG;
FB_LE3 = !nFB_WR;
FB_REGDDR = FR_WAIT;
END CASE;
-- DDR STEUERUNG -----------------------------------------------------
-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0=VCKE,1=!nVCS,2=FIFO_ACTIVE,3=FIFO UND CNT CLEAR,15..11=VIDEO RAM BASE
VCKE = VIDEO_RAM_CTR0;
nVCS = !VIDEO_RAM_CTR1;
FIFO_ACTIVE = VIDEO_RAM_CTR2;
DDR_CONFIG = VIDEO_RAM_CTR3;
DDR_REFRESH_ON = VIDEO_RAM_CTR4;
--------------------------------
CPU_ROW_ADR[] = FB_ADR[26..14];
CPU_BA1 = FB_ADR13;
CPU_BA0 = FB_ADR12;
CPU_COL_ADR[] = FB_ADR[11..2];
nVRAS = !VRAS;
nVCAS = !VCAS;
nVWE = !VWE;
DDR_WR.CLK = DDRCLK0;
-- SELECT LOGIC
DDR_SEL = FB_ALE & FB_AD[31..29]==B"011";
-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP<53>TER
CPU_SIG = DDR_SEL & nFB_WR & !DDR_CONFIG -- READ SOFORT LOS
# FR_S0 & !nFB_WR -- WRITE SP<53>TER AUCH CONFIG
# FR_S3 & !nFB_WR & LINE & !DDR_CONFIG; -- LINE WRITE
CPU_REQ = CPU_SIG;
CPU_REQ.CLK = DDR_SYNC_66M;
DDR_D_SEL[].CLK = DDRCLK3;
-- DDR STATE MACHINE -----------------------------------------------
DDR_SM.CLK = DDRCLK0;
CASE DDR_SM IS
WHEN DS_T1 =>
IF MAIN_CLK THEN
DDR_WR = DDR_WR; -- WRITE HALTEN (VON T4)
DDR_SM = DS_T2;
ELSE
DDR_SM = DS_LS; -- SYNCHRONISIEREN
END IF;
WHEN DS_T2 =>
IF !DDR_CONFIG THEN
VRAS = CPU_SIG # BLITTER_SIG # FIFO_SIG # DDR_REFRESH_ON;
VA[] = CPU_SIG & CPU_ROW_ADR[]
# BLITTER_SIG & BLITTER_ROW_ADR[]
# FIFO_SIG & FIFO_ROW_ADR[];
BA0 = CPU_SIG & CPU_BA0
# BLITTER_SIG & BLITTER_BA0
# FIFO_SIG & FIFO_BA0;
BA1 = CPU_SIG & CPU_BA1
# BLITTER_SIG & BLITTER_BA1
# FIFO_SIG & FIFO_BA1;
VCAS = !CPU_SIG & !BLITTER_SIG & !FIFO_SIG & DDR_REFRESH_ON; -- AUTO REFRESH WENN SONST NICHTS
BLITTER_REQ = BLITTER_SIG;
FIFO_REQ = FIFO_SIG;
END IF;
IF MAIN_CLK THEN
DDR_SM = DS_T3;
ELSE
DDR_SM = DS_LS;
END IF;
WHEN DS_T3 =>
IF DDR_CONFIG & CPU_REQ THEN
VRAS = FB_AD18;
VCAS = FB_AD17;
VWE = FB_AD16;
BA1 = FB_AD14;
BA0 = FB_AD13;
VA[] = FB_AD[12..0];
END IF;
IF !CPU_REQ & !BLITTER_REQ & !FIFO_REQ # DDR_CONFIG THEN
DDR_SM = DS_LS;
ELSE
BLITTER_REQ = BLITTER_SIG;
FIFO_REQ = FIFO_SIG;
DDR_SM = DS_T4;
END IF;
WHEN DS_T4 =>
FIFO_REQ = FIFO_SIG;
VCAS = VCC;
VWE = !nFB_WR & CPU_REQ # BLITTER_WR & BLITTER_REQ;
VA[9..0] = CPU_REQ & CPU_COL_ADR[]
# BLITTER_REQ & BLITTER_COL_ADR[]
# FIFO_REQ & FIFO_COL_ADR[];
VA10 = VCC; -- AUTO PRECHARGE
BA0 = CPU_REQ & CPU_BA0
# BLITTER_REQ & BLITTER_BA0
# FIFO_REQ & FIFO_BA0;
BA1 = CPU_REQ & CPU_BA1
# BLITTER_REQ & BLITTER_BA1
# FIFO_REQ & FIFO_BA1;
DDR_WR = !nFB_WR & CPU_REQ # BLITTER_WR & BLITTER_REQ;
FIFO_REQ = FIFO_SIG;
IF FIFO_REQ & FIFO_COL_ADR[]!= H"3FF" THEN -- GLEICHE PAGE?
DDR_SM = DS_T5; -- JA->
ELSE
DDR_SM = DS_T1; -- SONST NEUE PAGE AUFMACHEN
END IF;
WHEN DS_T5 =>
FIFO_REQ = FIFO_SIG;
DDR_SM = DS_T6;
WHEN DS_T6 =>
IF CPU_SIG THEN -- SOFORT UMSCHALTEN WENN CPU REQ
VRAS = VCC;
VA[] = CPU_ROW_ADR[];
BA1 = CPU_BA1;
BA0 = CPU_BA0;
DDR_SM = DS_T3;
ELSE
FIFO_REQ = FIFO_SIG;
VCAS = VCC;
VA[9..0] = FIFO_COL_ADR[];
VA10 = VCC; -- AUTO PRECHARGE
BA0 = FIFO_BA0;
BA1 = FIFO_BA1;
FIFO_WRE = FIFO_REQ; -- ODER FIFO LATCH IN 5 CYC 133
IF FIFO_REQ & FIFO_COL_ADR[]!= H"3FF" THEN -- GLEICHE PAGE?
DDR_SM = DS_T5; -- JA->
ELSE
DDR_SM = DS_T1; -- SONST NEUE PAGE AUFMACHEN
END IF;
END IF;
WHEN DS_LS =>
IF !MAIN_CLK THEN -- LEERSTATE UND SYNC
DDR_SM = DS_T1;
ELSE
DDR_SM = DS_LS;
END IF;
END CASE;
------------------------------------------------------------------------------
-- FIFO ---------------------------------
FIFO_SIG = FIFO_ACTIVE & !FIFO_FULL & !BLITTER_SIG & !CPU_SIG;
FIFO_REQ.CLK = DDR_SYNC_66M;
FIFO_ROW_ADR[] = VIDEO_ADR_CNT[24..12];
FIFO_BA1 = VIDEO_ADR_CNT11;
FIFO_BA0 = VIDEO_ADR_CNT10;
FIFO_COL_ADR[] = VIDEO_ADR_CNT[9..0];
-- Z<>HLER R<>CKSETZEN WENN VSYNC ----------------
CLEAR_FIFO_CNT.CLK = DDRCLK0;
CLEAR_FIFO_CNT = VSYNC # !FIFO_ACTIVE;
STOP.CLK = DDRCLK0;
STOP = VSYNC # CLEAR_FIFO_CNT;
VIDEO_ADR_CNT[].CLK = DDRCLK0;
VIDEO_ADR_CNT[] = CLEAR_FIFO_CNT & VIDEO_BASE_ADR[] -- SET
# !CLEAR_FIFO_CNT & (VIDEO_ADR_CNT[]+1); -- NEXT 16 BYTS
VIDEO_ADR_CNT[].ENA = CLEAR_FIFO_CNT # FIFO_WRE;
FIFO_WRE.CLK = DDRCLK0;
---------------------------------------------------------------
-- BLITTER BUS IST 128 BIT BREIT ------
BLITTER_SIG = GND & !CPU_SIG;
BLITTER_REQ.CLK = DDR_SYNC_66M;
BLITTER_RUN.CLK = DDRCLK0;
BLITTER_RUN = GND;
BLITTER_WR.CLK = DDRCLK0;
BLITTER_WR = GND;
DDRWR_D_SEL1 = BLITTER_WR;
BLITTER_ROW_ADR[] = H"0";
BLITTER_BA1 = GND;
BLITTER_BA0 = GND;
BLITTER_COL_ADR[] = H"0";
BLITTER_DOUT[] = H"0";
BLITTER_LE[] = H"0";
-----------------------------------------------------------
-- VIDEO REGISTER -----------------------
---------------------------------------------------------------------------------------------------------------------
VIDEO_BASE_L_D[].CLK = MAIN_CLK;
VIDEO_BASE_L = !nFB_CS1 & FB_ADR[15..1]==H"4106"; -- 820D/2
VIDEO_BASE_L_D[] = FB_AD[23..20]; -- SORRY, NUR 16 BYT GRENZEN
VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1;
VIDEO_BASE_M_D[].CLK = MAIN_CLK;
VIDEO_BASE_M = !nFB_CS1 & FB_ADR[15..1]==H"4101"; -- 8203/2
VIDEO_BASE_M_D[] = FB_AD[23..16];
VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3;
VIDEO_BASE_H_D[].CLK = MAIN_CLK;
VIDEO_BASE_H = !nFB_CS1 & FB_ADR[15..1]==H"4100"; -- 8200-1/2
VIDEO_BASE_H_D[] = FB_AD[23..16];
VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1;
VIDEO_BASE_X_D[].CLK = MAIN_CLK;
VIDEO_BASE_X_D[] = FB_AD[31..24];
VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0;
VIDEO_CNT_L = !nFB_CS1 & FB_ADR[15..1]==H"4104"; -- 8209/2
VIDEO_CNT_M = !nFB_CS1 & FB_ADR[15..1]==H"4103"; -- 8207/2
VIDEO_CNT_H = !nFB_CS1 & FB_ADR[15..1]==H"4102"; -- 8205/2
FB_AD[31..24] = lpm_bustri_BYT(
VIDEO_BASE_H & VIDEO_BASE_X_D[]
# VIDEO_CNT_H & VIDEO_ADR_CNT[27..20]
,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
FB_AD[23..16] = lpm_bustri_BYT(
VIDEO_BASE_L & (VIDEO_BASE_L_D[],B"0000")
# VIDEO_BASE_M & VIDEO_BASE_M_D[]
# VIDEO_BASE_H & VIDEO_BASE_H_D[]
# VIDEO_CNT_L & (VIDEO_ADR_CNT[3..0],B"0000")
# VIDEO_CNT_M & VIDEO_ADR_CNT[11..4]
# VIDEO_CNT_H & VIDEO_ADR_CNT[19..12]
,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE);
VIDEO_BASE_ADR[27..20] = VIDEO_BASE_X_D[];
VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[];
VIDEO_BASE_ADR[11..4] = VIDEO_BASE_M_D[];
VIDEO_BASE_ADR[3..0] = VIDEO_BASE_L_D[];
END;

267
FPGA_by_Fredi/Video/UNUSED
View File

@@ -1,267 +0,0 @@
-- Clearbox generated Memory Initialization File (.mif)
WIDTH=6;
DEPTH=256;
ADDRESS_RADIX=HEX;
DATA_RADIX=HEX;
CONTENT BEGIN
000 : 0F;
001 : 0E;
002 : 0D;
003 : 0C;
004 : 0B;
005 : 0A;
006 : 09;
007 : 08;
008 : 07;
009 : 06;
00a : 05;
00b : 04;
00c : 03;
00d : 02;
00e : 01;
00f : 00;
010 : 0F;
011 : 0E;
012 : 0D;
013 : 0C;
014 : 0B;
015 : 0A;
016 : 09;
017 : 08;
018 : 07;
019 : 06;
01a : 05;
01b : 04;
01c : 03;
01d : 02;
01e : 01;
01f : 00;
020 : 0F;
021 : 0E;
022 : 0D;
023 : 0C;
024 : 0B;
025 : 0A;
026 : 09;
027 : 08;
028 : 07;
029 : 06;
02a : 05;
02b : 04;
02c : 03;
02d : 02;
02e : 01;
02f : 00;
030 : 0F;
031 : 0E;
032 : 0D;
033 : 0C;
034 : 0B;
035 : 0A;
036 : 09;
037 : 08;
038 : 07;
039 : 06;
03a : 05;
03b : 04;
03c : 03;
03d : 02;
03e : 01;
03f : 00;
040 : 0F;
041 : 0E;
042 : 0D;
043 : 0C;
044 : 0B;
045 : 0A;
046 : 09;
047 : 08;
048 : 07;
049 : 06;
04a : 05;
04b : 04;
04c : 03;
04d : 02;
04e : 01;
04f : 00;
050 : 0F;
051 : 0E;
052 : 0D;
053 : 0C;
054 : 0B;
055 : 0A;
056 : 09;
057 : 08;
058 : 07;
059 : 06;
05a : 05;
05b : 04;
05c : 03;
05d : 02;
05e : 01;
05f : 00;
060 : 0F;
061 : 0E;
062 : 0D;
063 : 0C;
064 : 0B;
065 : 0A;
066 : 09;
067 : 08;
068 : 07;
069 : 06;
06a : 05;
06b : 04;
06c : 03;
06d : 02;
06e : 01;
06f : 00;
070 : 0F;
071 : 0E;
072 : 0D;
073 : 0C;
074 : 0B;
075 : 0A;
076 : 09;
077 : 08;
078 : 07;
079 : 06;
07a : 05;
07b : 04;
07c : 03;
07d : 02;
07e : 01;
07f : 00;
080 : 0F;
081 : 0E;
082 : 0D;
083 : 0C;
084 : 0B;
085 : 0A;
086 : 09;
087 : 08;
088 : 07;
089 : 06;
08a : 05;
08b : 04;
08c : 03;
08d : 02;
08e : 01;
08f : 00;
090 : 0F;
091 : 0E;
092 : 0D;
093 : 0C;
094 : 0B;
095 : 0A;
096 : 09;
097 : 08;
098 : 07;
099 : 06;
09a : 05;
09b : 04;
09c : 03;
09d : 02;
09e : 01;
09f : 00;
0a0 : 0F;
0a1 : 0E;
0a2 : 0D;
0a3 : 0C;
0a4 : 0B;
0a5 : 0A;
0a6 : 09;
0a7 : 08;
0a8 : 07;
0a9 : 06;
0aa : 05;
0ab : 04;
0ac : 03;
0ad : 02;
0ae : 01;
0af : 00;
0b0 : 0F;
0b1 : 0E;
0b2 : 0D;
0b3 : 0C;
0b4 : 0B;
0b5 : 0A;
0b6 : 09;
0b7 : 08;
0b8 : 07;
0b9 : 06;
0ba : 05;
0bb : 04;
0bc : 03;
0bd : 02;
0be : 01;
0bf : 00;
0c0 : 0F;
0c1 : 0E;
0c2 : 0D;
0c3 : 0C;
0c4 : 0B;
0c5 : 0A;
0c6 : 09;
0c7 : 08;
0c8 : 07;
0c9 : 06;
0ca : 05;
0cb : 04;
0cc : 03;
0cd : 02;
0ce : 01;
0cf : 00;
0d0 : 0F;
0d1 : 0E;
0d2 : 0D;
0d3 : 0C;
0d4 : 0B;
0d5 : 0A;
0d6 : 09;
0d7 : 08;
0d8 : 07;
0d9 : 06;
0da : 05;
0db : 04;
0dc : 03;
0dd : 02;
0de : 01;
0df : 00;
0e0 : 0F;
0e1 : 0E;
0e2 : 0D;
0e3 : 0C;
0e4 : 0B;
0e5 : 0A;
0e6 : 09;
0e7 : 08;
0e8 : 07;
0e9 : 06;
0ea : 05;
0eb : 04;
0ec : 03;
0ed : 02;
0ee : 01;
0ef : 00;
0f0 : 0F;
0f1 : 0E;
0f2 : 0D;
0f3 : 0C;
0f4 : 0B;
0f5 : 0A;
0f6 : 09;
0f7 : 08;
0f8 : 07;
0f9 : 06;
0fa : 05;
0fb : 04;
0fc : 03;
0fd : 02;
0fe : 01;
0ff : 00;
END;

4
FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
View File

@@ -338,7 +338,7 @@ BEGIN
SYS_CTR[].CLK = MAIN_CLK; SYS_CTR[].CLK = MAIN_CLK;
SYS_CTR[6..0] = FB_AD[22..16]; SYS_CTR[6..0] = FB_AD[22..16];
SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3; SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3;
BLITTER_ON = !SYS_CTR3; BLITTER_ON = SYS_CTR3;
--VDL_LOF --VDL_LOF
VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2 VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2
VDL_LOF[].CLK = MAIN_CLK; VDL_LOF[].CLK = MAIN_CLK;
@@ -440,7 +440,7 @@ BEGIN
FB_AD[31..16] = lpm_bustri_WORD( FB_AD[31..16] = lpm_bustri_WORD(
ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000") ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000")
# FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[]) # FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[])
# SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],!BLITTER_RUN,SYS_CTR[2..0]) # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],BLITTER_RUN,SYS_CTR[2..0])
# VDL_LOF_CS & VDL_LOF[] # VDL_LOF_CS & VDL_LOF[]
# VDL_LWD_CS & VDL_LWD[] # VDL_LWD_CS & VDL_LWD[]
# VDL_HBE_CS & (0,VDL_HBE[]) # VDL_HBE_CS & (0,VDL_HBE[])

675
FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
View File

@@ -1,675 +0,0 @@
TITLE "VIDEO MODUSE UND CLUT CONTROL";
-- CREATED BY FREDI ASCHWANDEN
INCLUDE "lpm_bustri_WORD.inc";
INCLUDE "lpm_bustri_BYT.inc";
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
nRSTO : INPUT;
MAIN_CLK : INPUT;
nFB_CS1 : INPUT;
nFB_CS2 : INPUT;
nFB_CS3 : INPUT;
nFB_WR : INPUT;
nFB_OE : INPUT;
FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT;
nFB_BURST : INPUT;
FB_ADR[31..0] : INPUT;
CLK33M : INPUT;
CLK25M : INPUT;
BLITTER_RUN : INPUT;
CLK_VIDEO : INPUT;
VR_D[8..0] : INPUT;
VR_BUSY : INPUT;
COLOR8 : OUTPUT;
ACP_CLUT_RD : OUTPUT;
COLOR1 : OUTPUT;
FALCON_CLUT_RDH : OUTPUT;
FALCON_CLUT_RDL : OUTPUT;
FALCON_CLUT_WR[3..0] : OUTPUT;
ST_CLUT_RD : OUTPUT;
ST_CLUT_WR[1..0] : OUTPUT;
CLUT_MUX_ADR[3..0] : OUTPUT;
HSYNC : OUTPUT;
VSYNC : OUTPUT;
nBLANK : OUTPUT;
nSYNC : OUTPUT;
nPD_VGA : OUTPUT;
FIFO_RDE : OUTPUT;
COLOR2 : OUTPUT;
COLOR4 : OUTPUT;
PIXEL_CLK : OUTPUT;
CLUT_OFF[3..0] : OUTPUT;
BLITTER_ON : OUTPUT;
VIDEO_RAM_CTR[15..0] : OUTPUT;
VIDEO_MOD_TA : OUTPUT;
CCR[23..0] : OUTPUT;
CCSEL[2..0] : OUTPUT;
ACP_CLUT_WR[3..0] : OUTPUT;
INTER_ZEI : OUTPUT;
DOP_FIFO_CLR : OUTPUT;
VIDEO_RECONFIG : OUTPUT;
VR_WR : OUTPUT;
VR_RD : OUTPUT;
CLR_FIFO : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
VARIABLE
CLK17M :DFF;
CLK13M :DFF;
ACP_CLUT_CS :NODE;
ACP_CLUT :NODE;
VIDEO_PLL_CONFIG_CS :NODE;
VR_WR :DFF;
VR_DOUT[8..0] :DFFE;
VR_FRQ[7..0] :DFFE;
VIDEO_PLL_RECONFIG_CS :NODE;
VIDEO_RECONFIG :DFF;
FALCON_CLUT_CS :NODE;
FALCON_CLUT :NODE;
ST_CLUT_CS :NODE;
ST_CLUT :NODE;
FB_B[3..0] :NODE;
FB_16B[1..0] :NODE;
ST_SHIFT_MODE[1..0] :DFFE;
ST_SHIFT_MODE_CS :NODE;
FALCON_SHIFT_MODE[10..0] :DFFE;
FALCON_SHIFT_MODE_CS :NODE;
CLUT_MUX_ADR[3..0] :DFF;
CLUT_MUX_AV[1..0][3..0] :DFF;
ACP_VCTR_CS :NODE;
ACP_VCTR[31..0] :DFFE;
CCR_CS :NODE;
CCR[23..0] :DFFE;
ACP_VIDEO_ON :NODE;
SYS_CTR[6..0] :DFFE;
SYS_CTR_CS :NODE;
VDL_LOF[15..0] :DFFE;
VDL_LOF_CS :NODE;
VDL_LWD[15..0] :DFFE;
VDL_LWD_CS :NODE;
-- DIV. CONTROL REGISTER
CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT
HSYNC :DFF;
HSYNC_I[7..0] :DFF;
HSY_LEN[7..0] :DFF; -- L<>NGE HSYNC PULS IN PIXEL_CLK
HSYNC_START :DFF;
LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT
VSYNC :DFF;
VSYNC_START :DFFE;
VSYNC_I[2..0] :DFFE;
nBLANK :DFF;
DISP_ON :DFF;
DPO_ZL :DFFE;
DPO_ON :DFF;
DPO_OFF :DFF;
VDTRON :DFF;
VDO_ZL :DFFE;
VDO_ON :DFF;
VDO_OFF :DFF;
VHCNT[11..0] :DFF;
SUB_PIXEL_CNT[6..0] :DFFE;
VVCNT[10..0] :DFFE;
VERZ[2..0][9..0] :DFF;
RAND[6..0] :DFF;
RAND_ON :NODE;
FIFO_RDE :DFF;
CLR_FIFO :DFFE;
START_ZEILE :DFFE;
SYNC_PIX :DFF;
SYNC_PIX1 :DFF;
SYNC_PIX2 :DFF;
CCSEL[2..0] :DFF;
COLOR16 :NODE;
COLOR24 :NODE;
-- ATARI RESOLUTION
ATARI_SYNC :NODE;
ATARI_HH[31..0] :DFFE; -- HORIZONTAL TIMING 640x480
ATARI_HH_CS :NODE;
ATARI_VH[31..0] :DFFE; -- VERTIKAL TIMING 640x480
ATARI_VH_CS :NODE;
ATARI_HL[31..0] :DFFE; -- HORIZONTAL TIMING 320x240
ATARI_HL_CS :NODE;
ATARI_VL[31..0] :DFFE; -- VERTIKAL TIMING 320x240
ATARI_VL_CS :NODE;
-- HORIZONTAL
RAND_LINKS[11..0] :NODE;
HDIS_START[11..0] :NODE;
HDIS_END[11..0] :NODE;
RAND_RECHTS[11..0] :NODE;
HS_START[11..0] :NODE;
H_TOTAL[11..0] :NODE;
HDIS_LEN[11..0] :NODE;
MULF[5..0] :NODE;
VDL_HHT[11..0] :DFFE;
VDL_HHT_CS :NODE;
VDL_HBE[11..0] :DFFE;
VDL_HBE_CS :NODE;
VDL_HDB[11..0] :DFFE;
VDL_HDB_CS :NODE;
VDL_HDE[11..0] :DFFE;
VDL_HDE_CS :NODE;
VDL_HBB[11..0] :DFFE;
VDL_HBB_CS :NODE;
VDL_HSS[11..0] :DFFE;
VDL_HSS_CS :NODE;
-- VERTIKAL
RAND_OBEN[10..0] :NODE;
VDIS_START[10..0] :NODE;
VDIS_END[10..0] :NODE;
RAND_UNTEN[10..0] :NODE;
VS_START[10..0] :NODE;
V_TOTAL[10..0] :NODE;
FALCON_VIDEO :NODE;
ST_VIDEO :NODE;
INTER_ZEI :DFF;
DOP_ZEI :DFF;
DOP_FIFO_CLR :DFF;
VDL_VBE[10..0] :DFFE;
VDL_VBE_CS :NODE;
VDL_VDB[10..0] :DFFE;
VDL_VDB_CS :NODE;
VDL_VDE[10..0] :DFFE;
VDL_VDE_CS :NODE;
VDL_VBB[10..0] :DFFE;
VDL_VBB_CS :NODE;
VDL_VSS[10..0] :DFFE;
VDL_VSS_CS :NODE;
VDL_VFT[10..0] :DFFE;
VDL_VFT_CS :NODE;
VDL_VCT[8..0] :DFFE;
VDL_VCT_CS :NODE;
VDL_VMD[3..0] :DFFE;
VDL_VMD_CS :NODE;
BEGIN
-- BYT SELECT 32 BIT
FB_B0 = FB_ADR[1..0]==0; -- ADR==0
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- BYT SELECT 16 BIT
FB_16B0 = FB_ADR[0]==0; -- ADR==0
FB_16B1 = FB_ADR[0]==1 -- ADR==1
# !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT
-- ACP CLUT --
ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0"; -- 0-3FF/1024
ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR;
CLUT_TA.CLK = MAIN_CLK;
CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA;
--FALCON CLUT --
FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10]==H"3E6"; -- $F9800/$400
FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD
FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD
FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
FALCON_CLUT_WR[3..2] = FB_16B[] & FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
-- ST CLUT --
ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5]==H"7C12"; -- $F8240/$20
ST_CLUT_RD = ST_CLUT_CS & !nFB_OE;
ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR;
-- ST SHIFT MODE
ST_SHIFT_MODE[].CLK = MAIN_CLK;
ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130"; -- $F8260/2
ST_SHIFT_MODE[] = FB_AD[25..24];
ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO
COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN
COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN
-- FALCON SHIFT MODE
FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133"; -- $F8266/2
FALCON_SHIFT_MODE[] = FB_AD[26..16];
FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
FALCON_SHIFT_MODE[7..0].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
ACP_VCTR[].CLK = MAIN_CLK;
ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100"; -- $400/4
ACP_VCTR[31..8] = FB_AD[31..8];
ACP_VCTR[5..0] = FB_AD[5..0];
ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
ACP_VCTR[23..16].ENA = ACP_VCTR_CS & FB_B1 & !nFB_WR;
ACP_VCTR[15..8].ENA = ACP_VCTR_CS & FB_B2 & !nFB_WR;
ACP_VCTR[5..0].ENA = ACP_VCTR_CS & FB_B3 & !nFB_WR;
ACP_VIDEO_ON = ACP_VCTR0;
nPD_VGA = ACP_VCTR1;
-- ATARI MODUS
ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFL<46>SUNG
-- HORIZONTAL TIMING 640x480
ATARI_HH[].CLK = MAIN_CLK;
ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4
ATARI_HH[] = FB_AD[];
ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR;
ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR;
ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR;
-- VERTIKAL TIMING 640x480
ATARI_VH[].CLK = MAIN_CLK;
ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105"; -- $414/4
ATARI_VH[] = FB_AD[];
ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR;
ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR;
ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR;
-- HORIZONTAL TIMING 320x240
ATARI_HL[].CLK = MAIN_CLK;
ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106"; -- $418/4
ATARI_HL[] = FB_AD[];
ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR;
ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR;
ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR;
-- VERTIKAL TIMING 320x240
ATARI_VL[].CLK = MAIN_CLK;
ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107"; -- $41C/4
ATARI_VL[] = FB_AD[];
ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR;
ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR;
ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR;
-- VIDEO PLL CONFIG
VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
VR_WR.CLK = MAIN_CLK;
VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & !VR_BUSY;
VR_DOUT[].CLK = MAIN_CLK;
VR_DOUT[].ENA = !VR_BUSY;
VR_DOUT[] = VR_D[];
VR_FRQ[].CLK = MAIN_CLK;
VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
VR_FRQ[] = FB_AD[23..16];
-- VIDEO PLL RECONFIG
VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800
VIDEO_RECONFIG.CLK = MAIN_CLK;
VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
------------------------------------------------------------------------------------------------------------------------
VIDEO_RAM_CTR[] = ACP_VCTR[31..16];
-------------- COLOR MODE IM ACP SETZEN
COLOR1 = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
COLOR8 = ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON;
ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1;
-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
FALCON_VIDEO = ACP_VCTR7;
FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
ST_VIDEO = ACP_VCTR6;
ST_CLUT = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1;
CCSEL[].CLK = PIXEL_CLK;
CCSEL[] = B"000" & ST_CLUT -- ONLY FOR INFORMATION
# B"001" & FALCON_CLUT
# B"100" & ACP_CLUT
# B"101" & COLOR16
# B"110" & COLOR24
# B"111" & RAND_ON;
-- DIVERSE (VIDEO)-REGISTER ----------------------------
-- RANDFARBE
CCR[].CLK = MAIN_CLK;
CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4
CCR[] = FB_AD[23..0];
CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR;
CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR;
--SYS CTR
SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2
SYS_CTR[].CLK = MAIN_CLK;
SYS_CTR[6..0] = FB_AD[22..16];
SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3;
BLITTER_ON = !SYS_CTR3;
--VDL_LOF
VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2
VDL_LOF[].CLK = MAIN_CLK;
VDL_LOF[] = FB_AD[31..16];
VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3;
--VDL_LWD
VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2
VDL_LWD[].CLK = MAIN_CLK;
VDL_LWD[] = FB_AD[31..16];
VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1;
-- HORIZONTAL
-- VDL_HHT
VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2
VDL_HHT[].CLK = MAIN_CLK;
VDL_HHT[] = FB_AD[27..16];
VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3;
-- VDL_HBE
VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2
VDL_HBE[].CLK = MAIN_CLK;
VDL_HBE[] = FB_AD[27..16];
VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3;
-- VDL_HDB
VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2
VDL_HDB[].CLK = MAIN_CLK;
VDL_HDB[] = FB_AD[27..16];
VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1;
-- VDL_HDE
VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2
VDL_HDE[].CLK = MAIN_CLK;
VDL_HDE[] = FB_AD[27..16];
VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3;
-- VDL_HBB
VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2
VDL_HBB[].CLK = MAIN_CLK;
VDL_HBB[] = FB_AD[27..16];
VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1;
-- VDL_HSS
VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2
VDL_HSS[].CLK = MAIN_CLK;
VDL_HSS[] = FB_AD[27..16];
VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1;
-- VERTIKAL
-- VDL_VBE
VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2
VDL_VBE[].CLK = MAIN_CLK;
VDL_VBE[] = FB_AD[26..16];
VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3;
-- VDL_VDB
VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2
VDL_VDB[].CLK = MAIN_CLK;
VDL_VDB[] = FB_AD[26..16];
VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1;
-- VDL_VDE
VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2
VDL_VDE[].CLK = MAIN_CLK;
VDL_VDE[] = FB_AD[26..16];
VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3;
-- VDL_VBB
VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2
VDL_VBB[].CLK = MAIN_CLK;
VDL_VBB[] = FB_AD[26..16];
VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1;
-- VDL_VSS
VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2
VDL_VSS[].CLK = MAIN_CLK;
VDL_VSS[] = FB_AD[26..16];
VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1;
-- VDL_VFT
VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2
VDL_VFT[].CLK = MAIN_CLK;
VDL_VFT[] = FB_AD[26..16];
VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3;
-- VDL_VCT
VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2
VDL_VCT[].CLK = MAIN_CLK;
VDL_VCT[] = FB_AD[24..16];
VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0;
VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1;
-- VDL_VMD
VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2
VDL_VMD[].CLK = MAIN_CLK;
VDL_VMD[] = FB_AD[19..16];
VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3;
--- REGISTER OUT
FB_AD[31..16] = lpm_bustri_WORD(
ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000")
# FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[])
# SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],!BLITTER_RUN,SYS_CTR[2..0])
# VDL_LOF_CS & VDL_LOF[]
# VDL_LWD_CS & VDL_LWD[]
# VDL_HBE_CS & (0,VDL_HBE[])
# VDL_HDB_CS & (0,VDL_HDB[])
# VDL_HDE_CS & (0,VDL_HDE[])
# VDL_HBB_CS & (0,VDL_HBB[])
# VDL_HSS_CS & (0,VDL_HSS[])
# VDL_HHT_CS & (0,VDL_HHT[])
# VDL_VBE_CS & (0,VDL_VBE[])
# VDL_VDB_CS & (0,VDL_VDB[])
# VDL_VDE_CS & (0,VDL_VDE[])
# VDL_VBB_CS & (0,VDL_VBB[])
# VDL_VSS_CS & (0,VDL_VSS[])
# VDL_VFT_CS & (0,VDL_VFT[])
# VDL_VCT_CS & (0,VDL_VCT[])
# VDL_VMD_CS & (0,VDL_VMD[])
# ACP_VCTR_CS & ACP_VCTR[31..16]
# ATARI_HH_CS & ATARI_HH[31..16]
# ATARI_VH_CS & ATARI_VH[31..16]
# ATARI_HL_CS & ATARI_HL[31..16]
# ATARI_VL_CS & ATARI_VL[31..16]
# CCR_CS & (0,CCR[23..16])
# VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
# VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
# VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
# ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS
# VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE);
FB_AD[15..0] = lpm_bustri_WORD(
ACP_VCTR_CS & ACP_VCTR[15..0]
# ATARI_HH_CS & ATARI_HH[15..0]
# ATARI_VH_CS & ATARI_VH[15..0]
# ATARI_HL_CS & ATARI_HL[15..0]
# ATARI_VL_CS & ATARI_VL[15..0]
# CCR_CS & CCR[15..0]
,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE);
VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
# VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
# ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
# VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS;
-- VIDEO AUSGABE SETZEN
CLK17M.CLK = CLK33M;
CLK17M = !CLK17M;
CLK13M.CLK = CLK25M;
CLK13M = !CLK13M;
PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0)
# CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0)
# CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0
# CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
# CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
# CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
# CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9];
--------------------------------------------------------------
-- HORIZONTALE SYNC L<>NGE in PIXEL_CLK
----------------------------------------------------------------
HSY_LEN[].CLK = MAIN_CLK;
HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0)
# 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0)
# 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0
# 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
# 28 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
# 32 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
# 16 + (0,VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync puls length in pixeln=frequenz/ = 500ns
MULF[] = 2 & !ST_VIDEO & VDL_VMD2 -- MULTIPLIKATIONS FAKTOR
# 4 & !ST_VIDEO & !VDL_VMD2
# 16 & ST_VIDEO & VDL_VMD2
# 32 & ST_VIDEO & !VDL_VMD2;
HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN
# 640 & !VDL_VMD2;
-- DOPPELZEILENMODUS
DOP_ZEI.CLK = MAIN_CLK;
DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS
INTER_ZEI.CLK = PIXEL_CLK;
INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
# DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
DOP_FIFO_CLR.CLK = PIXEL_CLK;
DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO L<>SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON
# 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# VDL_HBE[] * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
HDIS_START[] = VDL_HDB[] & ACP_VIDEO_ON
# RAND_LINKS[]+1 & !ACP_VIDEO_ON; --
HDIS_END[] = VDL_HDE[] & ACP_VIDEO_ON
# RAND_LINKS[]+HDIS_LEN[] & !ACP_VIDEO_ON; --
RAND_RECHTS[] = VDL_HBB[] & ACP_VIDEO_ON
# HDIS_END[]+1 & !ACP_VIDEO_ON; --
HS_START[] = VDL_HSS[] & ACP_VIDEO_ON
# ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
H_TOTAL[] = VDL_HHT[] & ACP_VIDEO_ON
# ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (VDL_HHT[]+2) * (0,MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
RAND_OBEN[] = VDL_VBE[] & ACP_VIDEO_ON
# 31 & !ACP_VIDEO_ON & ATARI_SYNC
# (0,VDL_VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
VDIS_START[] = VDL_VDB[] & ACP_VIDEO_ON
# 32 & !ACP_VIDEO_ON & ATARI_SYNC
# (0,VDL_VDB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC;
VDIS_END[] = VDL_VDE[] & ACP_VIDEO_ON
# 431 & !ACP_VIDEO_ON & ATARI_SYNC & ST_VIDEO
# 511 & !ACP_VIDEO_ON & ATARI_SYNC & !ST_VIDEO
# (0,VDL_VDE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
RAND_UNTEN[] = VDL_VBB[] & ACP_VIDEO_ON
# VDIS_END[]+1 & !ACP_VIDEO_ON & ATARI_SYNC
# (0,VDL_VBB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC;
VS_START[] = VDL_VSS[] & ACP_VIDEO_ON
# ATARI_VL[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_VH[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (0,VDL_VSS[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
V_TOTAL[] = VDL_VFT[] & ACP_VIDEO_ON
# ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
-- Z<>HLER
LAST.CLK = PIXEL_CLK;
LAST = VHCNT[]==(H_TOTAL[]-2);
VHCNT[].CLK = PIXEL_CLK;
VHCNT[] = (VHCNT[] + 1) & !LAST;
VVCNT[].CLK = PIXEL_CLK;
VVCNT[].ENA = LAST;
VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1);
-- DISPLAY ON OFF
DPO_ZL.CLK = PIXEL_CLK;
DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1); -- 1 ZEILE DAVOR ON OFF
DPO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN
DPO_ON.CLK = PIXEL_CLK;
DPO_ON = VHCNT[]==RAND_LINKS[]; -- BESSER EINZELN WEGEN TIMING
DPO_OFF.CLK = PIXEL_CLK;
DPO_OFF = VHCNT[]==(RAND_RECHTS[]-1);
DISP_ON.CLK = PIXEL_CLK;
DISP_ON = DISP_ON & !DPO_OFF
# DPO_ON & DPO_ZL;
-- DATENTRANSFER ON OFF
VDO_ON.CLK = PIXEL_CLK;
VDO_ON = VHCNT[]==(HDIS_START[]-1); -- BESSER EINZELN WEGEN TIMING
VDO_OFF.CLK = PIXEL_CLK;
VDO_OFF = VHCNT[]==HDIS_END[];
VDO_ZL.CLK = PIXEL_CLK;
VDO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN
VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]); -- 1 ZEILE DAVOR ON OFF
VDTRON.CLK = PIXEL_CLK;
VDTRON = VDTRON & !VDO_OFF
# VDO_ON & VDO_ZL;
-- VERZ<52>GERUNG UND SYNC
HSYNC_START.CLK = PIXEL_CLK;
HSYNC_START = VHCNT[]==HS_START[]-3;
HSYNC_I[].CLK = PIXEL_CLK;
HSYNC_I[] = HSY_LEN[] & HSYNC_START
# (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
VSYNC_START.CLK = PIXEL_CLK;
VSYNC_START.ENA = LAST;
VSYNC_START = VVCNT[]==(VS_START[]-3); -- start am ende der Zeile vor dem vsync
VSYNC_I[].CLK = PIXEL_CLK;
VSYNC_I[].ENA = LAST; -- start am ende der Zeile vor dem vsync
VSYNC_I[] = 3 & VSYNC_START -- 3 zeilen vsync length
# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0; -- runterz<72>hlen bis 0
VERZ[][].CLK = PIXEL_CLK;
VERZ[][1] = VERZ[][0];
VERZ[][2] = VERZ[][1];
VERZ[][3] = VERZ[][2];
VERZ[][4] = VERZ[][3];
VERZ[][5] = VERZ[][4];
VERZ[][6] = VERZ[][5];
VERZ[][7] = VERZ[][6];
VERZ[][8] = VERZ[][7];
VERZ[][9] = VERZ[][8];
VERZ[0][0] = DISP_ON;
VERZ[1][0] = HSYNC_I[]!=0;
VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
# ACP_VCTR15 & VDL_VCT6 & HSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE
VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
# ACP_VCTR15 & VDL_VCT5 & VSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE
nBLANK.CLK = PIXEL_CLK;
nBLANK = VERZ[0][8];
HSYNC.CLK = PIXEL_CLK;
HSYNC = VERZ[1][9];
VSYNC.CLK = PIXEL_CLK;
VSYNC = VERZ[2][9];
nSYNC = GND;
-- RANDFARBE MACHEN ------------------------------------
RAND[].CLK = PIXEL_CLK;
RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25;
RAND[1] = RAND[0];
RAND[2] = RAND[1];
RAND[3] = RAND[2];
RAND[4] = RAND[3];
RAND[5] = RAND[4];
RAND[6] = RAND[5];
RAND_ON = RAND[6];
----------------------------------------------------------
CLR_FIFO.CLK = PIXEL_CLK;
CLR_FIFO.ENA = LAST;
CLR_FIFO = VVCNT[]==V_TOTAL[]-2; -- IN LETZTER ZEILE L<>SCHEN
START_ZEILE.CLK = PIXEL_CLK;
START_ZEILE.ENA = LAST;
START_ZEILE = VVCNT[]==0; -- ZEILE 1
SYNC_PIX.CLK = PIXEL_CLK;
SYNC_PIX = VHCNT[]==3 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX1.CLK = PIXEL_CLK;
SYNC_PIX1 = VHCNT[]==5 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX2.CLK = PIXEL_CLK;
SYNC_PIX2 = VHCNT[]==7 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX; --count up if display on sonst clear bei sync pix
FIFO_RDE.CLK = PIXEL_CLK;
FIFO_RDE = (SUB_PIXEL_CNT[6..0]==1 & COLOR1
# SUB_PIXEL_CNT[5..0]==1 & COLOR2
# SUB_PIXEL_CNT[4..0]==1 & COLOR4
# SUB_PIXEL_CNT[3..0]==1 & COLOR8
# SUB_PIXEL_CNT[2..0]==1 & COLOR16
# SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON
# SYNC_PIX # SYNC_PIX1 # SYNC_PIX2; -- 3 CLOCK ZUS<55>TZLICH F<>R FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
CLUT_MUX_ADR[].CLK = PIXEL_CLK;
CLUT_MUX_AV[][].CLK = PIXEL_CLK;
CLUT_MUX_AV[0][] = SUB_PIXEL_CNT[3..0];
CLUT_MUX_AV[1][] = CLUT_MUX_AV[0][];
CLUT_MUX_ADR[] = CLUT_MUX_AV[1][];
END;

4450
FPGA_by_Fredi/Video/Video.bdf
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File diff suppressed because it is too large Load Diff

16
FPGA_by_Fredi/Video/altdpram0_waveforms.html
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@@ -1,16 +0,0 @@
<html>
<head>
<title>Sample Waveforms for altdpram0.vhd </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file altdpram0.vhd </CENTER></h2>
<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram0.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 7, 6, 5, 4, ...). The design altdpram0.vhd has two read/write ports. Read/write port A has 16 words of 3 bits each and Read/write port B has 16 words of 3 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
<CENTER><img src=altdpram0_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
<CENTER><img src=altdpram0_wave1.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
<P></P>
</body>
</html>

16
FPGA_by_Fredi/Video/altdpram1_waveforms.html
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@@ -1,16 +0,0 @@
<html>
<head>
<title>Sample Waveforms for altdpram1.vhd </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file altdpram1.vhd </CENTER></h2>
<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram1.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 0F, 0E, 0D, 0C, ...). The design altdpram1.vhd has two read/write ports. Read/write port A has 256 words of 6 bits each and Read/write port B has 256 words of 6 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
<CENTER><img src=altdpram1_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
<CENTER><img src=altdpram1_wave1.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
<P></P>
</body>
</html>

16
FPGA_by_Fredi/Video/altdpram2_waveforms.html
View File

@@ -1,16 +0,0 @@
<html>
<head>
<title>Sample Waveforms for altdpram2.vhd </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file altdpram2.vhd </CENTER></h2>
<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram2.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( F0, F1, F2, F3, ...). The design altdpram2.vhd has two read/write ports. Read/write port A has 256 words of 8 bits each and Read/write port B has 256 words of 8 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
<CENTER><img src=altdpram2_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
<CENTER><img src=altdpram2_wave1.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
<P></P>
</body>
</html>

63
FPGA_by_Fredi/Video/lpm_blitter.bsf Normal file
View File

@@ -0,0 +1,63 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 144 96)
(text "lpm_blitter" (rect 42 1 112 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 80 25 92)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "data[63..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "data[63..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8)))
(text "enable" (rect 20 58 53 71)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 144 56)
(output)
(text "q[63..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "q[63..0]" (rect 89 50 125 63)(font "Arial" (font_size 8)))
(line (pt 144 56)(pt 128 56)(line_width 3))
)
(drawing
(text "DFF" (rect 109 17 128 29)(font "Arial" ))
(line (pt 16 16)(pt 128 16)(line_width 1))
(line (pt 128 16)(pt 128 80)(line_width 1))
(line (pt 128 80)(pt 16 80)(line_width 1))
(line (pt 16 80)(pt 16 16)(line_width 1))
(line (pt 16 42)(pt 22 48)(line_width 1))
(line (pt 22 48)(pt 16 54)(line_width 1))
)
)

9
FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.cmp → FPGA_by_Fredi/Video/lpm_blitter.cmp
View File

@@ -13,11 +13,12 @@
--applicable agreement for further details. --applicable agreement for further details.
component lpm_clshift0 component lpm_blitter
PORT PORT
( (
data : IN STD_LOGIC_VECTOR (255 DOWNTO 0); clock : IN STD_LOGIC ;
distance : IN STD_LOGIC_VECTOR (6 DOWNTO 0); data : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (255 DOWNTO 0) enable : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
); );
end component; end component;

25
FPGA_by_Fredi/Video/lpm_blitter.inc Normal file
View File

@@ -0,0 +1,25 @@
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION lpm_blitter
(
clock,
data[63..0],
enable
)
RETURNS (
q[63..0]
);

6
FPGA_by_Fredi/Video/lpm_blitter.qip Normal file
View File

@@ -0,0 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "LPM_FF"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_blitter.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_blitter.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_blitter.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_blitter.cmp"]

127
FPGA_by_Fredi/Video/lpm_blitter.vhd Normal file
View File

@@ -0,0 +1,127 @@
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: lpm_blitter.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_blitter IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
enable : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END lpm_blitter;
ARCHITECTURE SYN OF lpm_blitter IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (63 DOWNTO 0);
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enable : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(63 DOWNTO 0);
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "DFF",
lpm_type => "LPM_FF",
lpm_width => 64
)
PORT MAP (
enable => enable,
clock => clock,
data => data,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "1"
-- Retrieval info: PRIVATE: DFF NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "64"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL data[63..0]
-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT NODEFVAL enable
-- Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL q[63..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
-- Retrieval info: CONNECT: @enable 0 0 0 0 enable 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_blitter.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_blitter.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_blitter.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_blitter.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_blitter_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

13
FPGA_by_Fredi/Video/lpm_compare1_waveforms.html
View File

@@ -1,13 +0,0 @@
<html>
<head>
<title>Sample Waveforms for lpm_compare1.vhd </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file lpm_compare1.vhd </CENTER></h2>
<P>The following waveforms show the behavior of lpm_comparator megafunction for the chosen set of parameters in design lpm_compare1.vhd. The design lpm_compare1.vhd is 11 bit UNSIGNED comparator. </P>
<CENTER><img src=lpm_compare1_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing comparator operation. </CENTER></P>
<P><FONT size=3></P>
<P></P>
</body>
</html>

32
FPGA_by_Fredi/Video/lpm_fifoDZ.bsf
View File

@@ -21,53 +21,53 @@ applicable agreement for further details.
(header "symbol" (version "1.1")) (header "symbol" (version "1.1"))
(symbol (symbol
(rect 0 0 160 144) (rect 0 0 160 144)
(text "lpm_fifoDZ" (rect 41 2 133 21)(font "Arial" (font_size 10))) (text "lpm_fifoDZ" (rect 50 1 120 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 125 31 140)(font "Arial" )) (text "inst" (rect 8 128 25 140)(font "Arial" ))
(port (port
(pt 0 32) (pt 0 32)
(input) (input)
(text "data[127..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) (text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "data[127..0]" (rect 20 24 89 40)(font "Arial" (font_size 8))) (text "data[127..0]" (rect 20 26 77 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3)) (line (pt 0 32)(pt 16 32)(line_width 3))
) )
(port (port
(pt 0 56) (pt 0 56)
(input) (input)
(text "wrreq" (rect 0 0 36 16)(font "Arial" (font_size 8))) (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
(text "wrreq" (rect 20 48 51 64)(font "Arial" (font_size 8))) (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 16 56)(line_width 1)) (line (pt 0 56)(pt 16 56)(line_width 1))
) )
(port (port
(pt 0 72) (pt 0 72)
(input) (input)
(text "rdreq" (rect 0 0 34 16)(font "Arial" (font_size 8))) (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
(text "rdreq" (rect 20 64 49 80)(font "Arial" (font_size 8))) (text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 16 72)(line_width 1)) (line (pt 0 72)(pt 16 72)(line_width 1))
) )
(port (port
(pt 0 96) (pt 0 96)
(input) (input)
(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8))) (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 26 88 57 104)(font "Arial" (font_size 8))) (text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96)(line_width 1)) (line (pt 0 96)(pt 16 96)(line_width 1))
) )
(port (port
(pt 0 120) (pt 0 120)
(input) (input)
(text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8))) (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
(text "aclr" (rect 20 112 41 128)(font "Arial" (font_size 8))) (text "aclr" (rect 20 114 37 127)(font "Arial" (font_size 8)))
(line (pt 0 120)(pt 16 120)(line_width 1)) (line (pt 0 120)(pt 16 120)(line_width 1))
) )
(port (port
(pt 160 32) (pt 160 32)
(output) (output)
(text "q[127..0]" (rect 0 0 60 16)(font "Arial" (font_size 8))) (text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
(text "q[127..0]" (rect 90 24 141 40)(font "Arial" (font_size 8))) (text "q[127..0]" (rect 99 26 141 39)(font "Arial" (font_size 8)))
(line (pt 160 32)(pt 144 32)(line_width 3)) (line (pt 160 32)(pt 144 32)(line_width 3))
) )
(drawing (drawing
(text "(ack)" (rect 51 67 76 81)(font "Arial" )) (text "(ack)" (rect 51 67 72 79)(font "Arial" ))
(text "128 bits x 128 words" (rect 31 114 134 128)(font "Arial" )) (text "128 bits x 512 words" (rect 58 116 144 128)(font "Arial" ))
(line (pt 16 16)(pt 144 16)(line_width 1)) (line (pt 16 16)(pt 144 16)(line_width 1))
(line (pt 144 16)(pt 144 128)(line_width 1)) (line (pt 144 16)(pt 144 128)(line_width 1))
(line (pt 144 128)(pt 16 128)(line_width 1)) (line (pt 144 128)(pt 16 128)(line_width 1))

10
FPGA_by_Fredi/Video/lpm_fifoDZ.vhd
View File

@@ -88,11 +88,11 @@ BEGIN
GENERIC MAP ( GENERIC MAP (
add_ram_output_register => "OFF", add_ram_output_register => "OFF",
intended_device_family => "Cyclone III", intended_device_family => "Cyclone III",
lpm_numwords => 128, lpm_numwords => 512,
lpm_showahead => "ON", lpm_showahead => "ON",
lpm_type => "scfifo", lpm_type => "scfifo",
lpm_width => 128, lpm_width => 128,
lpm_widthu => 7, lpm_widthu => 9,
overflow_checking => "OFF", overflow_checking => "OFF",
underflow_checking => "OFF", underflow_checking => "OFF",
use_eab => "ON" use_eab => "ON"
@@ -119,7 +119,7 @@ END SYN;
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1" -- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
-- Retrieval info: PRIVATE: Clock NUMERIC "0" -- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "128" -- Retrieval info: PRIVATE: Depth NUMERIC "512"
-- Retrieval info: PRIVATE: Empty NUMERIC "0" -- Retrieval info: PRIVATE: Empty NUMERIC "0"
-- Retrieval info: PRIVATE: Full NUMERIC "0" -- Retrieval info: PRIVATE: Full NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -147,11 +147,11 @@ END SYN;
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0" -- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128" -- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" -- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" -- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7" -- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" -- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" -- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON" -- Retrieval info: CONSTANT: USE_EAB STRING "ON"

13
FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html
View File

@@ -1,13 +0,0 @@
<html>
<head>
<title>Sample Waveforms for "lpm_fifoDZ.vhd" </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file "lpm_fifoDZ.vhd" </CENTER></h2>
<P>The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design "lpm_fifoDZ.vhd". The design "lpm_fifoDZ.vhd" has a depth of 128 words of 128 bits each. The fifo is in show-ahead synchronous mode. The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge. </P>
<CENTER><img src=lpm_fifoDZ_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P>
<P></P>
</body>
</html>

15
FPGA_by_Fredi/Video/lpm_fifo_dc0.bsf
View File

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur. the Block Editor! File corruption is VERY likely to occur.
*/ */
/* /*
Copyright (C) 1991-2008 Altera Corporation Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing functions, and any output files from any of the foregoing
@@ -68,8 +68,8 @@ applicable agreement for further details.
(port (port
(pt 160 72) (pt 160 72)
(output) (output)
(text "wrusedw[8..0]" (rect 0 0 84 14)(font "Arial" (font_size 8))) (text "wrusedw[10..0]" (rect 0 0 92 14)(font "Arial" (font_size 8)))
(text "wrusedw[8..0]" (rect 69 66 132 79)(font "Arial" (font_size 8))) (text "wrusedw[10..0]" (rect 63 66 132 79)(font "Arial" (font_size 8)))
(line (pt 160 72)(pt 144 72)(line_width 3)) (line (pt 160 72)(pt 144 72)(line_width 3))
) )
(port (port
@@ -79,15 +79,8 @@ applicable agreement for further details.
(text "q[127..0]" (rect 99 90 141 103)(font "Arial" (font_size 8))) (text "q[127..0]" (rect 99 90 141 103)(font "Arial" (font_size 8)))
(line (pt 160 96)(pt 144 96)(line_width 3)) (line (pt 160 96)(pt 144 96)(line_width 3))
) )
(port
(pt 160 120)
(output)
(text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8)))
(text "rdempty" (rect 102 114 140 127)(font "Arial" (font_size 8)))
(line (pt 160 120)(pt 144 120)(line_width 1))
)
(drawing (drawing
(text "128 bits x 512 words" (rect 58 140 144 152)(font "Arial" )) (text "128 bits x 2048 words" (rect 53 140 144 152)(font "Arial" ))
(line (pt 16 16)(pt 144 16)(line_width 1)) (line (pt 16 16)(pt 144 16)(line_width 1))
(line (pt 144 16)(pt 144 152)(line_width 1)) (line (pt 144 16)(pt 144 152)(line_width 1))
(line (pt 144 152)(pt 16 152)(line_width 1)) (line (pt 144 152)(pt 16 152)(line_width 1))

5
FPGA_by_Fredi/Video/lpm_fifo_dc0.cmp
View File

@@ -1,4 +1,4 @@
--Copyright (C) 1991-2008 Altera Corporation --Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing
@@ -23,7 +23,6 @@ component lpm_fifo_dc0
wrclk : IN STD_LOGIC ; wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ; wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0); q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0);
rdempty : OUT STD_LOGIC ; wrusedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
wrusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
); );
end component; end component;

5
FPGA_by_Fredi/Video/lpm_fifo_dc0.inc
View File

@@ -1,4 +1,4 @@
--Copyright (C) 1991-2008 Altera Corporation --Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing
@@ -25,6 +25,5 @@ FUNCTION lpm_fifo_dc0
RETURNS ( RETURNS (
q[127..0], q[127..0],
rdempty, wrusedw[10..0]
wrusedw[8..0]
); );

2
FPGA_by_Fredi/Video/lpm_fifo_dc0.qip
View File

@@ -1,5 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+" set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+"
set_global_assignment -name IP_TOOL_VERSION "8.1" set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.vhd"] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.bsf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.inc"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.inc"]

43
FPGA_by_Fredi/Video/lpm_fifo_dc0.vhd
View File

@@ -14,11 +14,11 @@
-- ************************************************************ -- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- --
-- 8.1 Build 163 10/28/2008 SJ Web Edition -- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************ -- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation --Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing
@@ -49,17 +49,15 @@ ENTITY lpm_fifo_dc0 IS
wrclk : IN STD_LOGIC ; wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ; wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0); q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0);
rdempty : OUT STD_LOGIC ; wrusedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
wrusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
); );
END lpm_fifo_dc0; END lpm_fifo_dc0;
ARCHITECTURE SYN OF lpm_fifo_dc0 IS ARCHITECTURE SYN OF lpm_fifo_dc0 IS
SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire0 : STD_LOGIC_VECTOR (10 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (8 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC_VECTOR (127 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (127 DOWNTO 0);
@@ -80,9 +78,8 @@ ARCHITECTURE SYN OF lpm_fifo_dc0 IS
); );
PORT ( PORT (
wrclk : IN STD_LOGIC ; wrclk : IN STD_LOGIC ;
rdempty : OUT STD_LOGIC ;
rdreq : IN STD_LOGIC ; rdreq : IN STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); wrusedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0);
aclr : IN STD_LOGIC ; aclr : IN STD_LOGIC ;
rdclk : IN STD_LOGIC ; rdclk : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0); q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0);
@@ -92,18 +89,17 @@ ARCHITECTURE SYN OF lpm_fifo_dc0 IS
END COMPONENT; END COMPONENT;
BEGIN BEGIN
rdempty <= sub_wire0; wrusedw <= sub_wire0(10 DOWNTO 0);
wrusedw <= sub_wire1(8 DOWNTO 0); q <= sub_wire1(127 DOWNTO 0);
q <= sub_wire2(127 DOWNTO 0);
dcfifo_component : dcfifo dcfifo_component : dcfifo
GENERIC MAP ( GENERIC MAP (
intended_device_family => "Cyclone III", intended_device_family => "Cyclone III",
lpm_numwords => 512, lpm_numwords => 2048,
lpm_showahead => "OFF", lpm_showahead => "OFF",
lpm_type => "dcfifo", lpm_type => "dcfifo",
lpm_width => 128, lpm_width => 128,
lpm_widthu => 9, lpm_widthu => 11,
overflow_checking => "OFF", overflow_checking => "OFF",
rdsync_delaypipe => 6, rdsync_delaypipe => 6,
underflow_checking => "OFF", underflow_checking => "OFF",
@@ -118,9 +114,8 @@ BEGIN
rdclk => rdclk, rdclk => rdclk,
wrreq => wrreq, wrreq => wrreq,
data => data, data => data,
rdempty => sub_wire0, wrusedw => sub_wire0,
wrusedw => sub_wire1, q => sub_wire1
q => sub_wire2
); );
@@ -136,7 +131,7 @@ END SYN;
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4" -- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "512" -- Retrieval info: PRIVATE: Depth NUMERIC "2048"
-- Retrieval info: PRIVATE: Empty NUMERIC "1" -- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1" -- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -154,7 +149,7 @@ END SYN;
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0" -- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" -- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "128" -- Retrieval info: PRIVATE: output_width NUMERIC "128"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0" -- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" -- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0" -- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
@@ -163,11 +158,11 @@ END SYN;
-- Retrieval info: PRIVATE: wsFull NUMERIC "0" -- Retrieval info: PRIVATE: wsFull NUMERIC "0"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1" -- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512" -- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" -- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" -- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9" -- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" -- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "6" -- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "6"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" -- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
@@ -178,19 +173,17 @@ END SYN;
-- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0] -- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0]
-- Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0] -- Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0]
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk -- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk -- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-- Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL wrusedw[8..0] -- Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0]
-- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0 -- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
-- Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0 -- Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 -- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 -- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 -- Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
-- Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0.vhd TRUE

13
FPGA_by_Fredi/Video/lpm_fifo_dc0_waveforms.html
View File

@@ -1,13 +0,0 @@
<html>
<head>
<title>Sample Waveforms for lpm_fifo_dc0.vhd </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file lpm_fifo_dc0.vhd </CENTER></h2>
<P>The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design lpm_fifo_dc0.vhd. The design lpm_fifo_dc0.vhd has a depth of 512 words of 128 bits each. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request. </P>
<CENTER><img src=lpm_fifo_dc0_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P>
<P></P>
</body>
</html>

64
FPGA_by_Fredi/altddio_out0.bsf
View File

@@ -1,64 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 232 120)
(text "altddio_out0" (rect 81 1 163 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 104 25 116)(font "Arial" ))
(port
(pt 0 24)
(input)
(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8)))
(line (pt 0 24)(pt 88 24)(line_width 1))
)
(port
(pt 0 40)
(input)
(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 88 40)(line_width 1))
)
(port
(pt 0 56)
(input)
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 88 56)(line_width 1))
)
(port
(pt 232 24)
(output)
(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8)))
(line (pt 232 24)(pt 152 24)(line_width 1))
)
(drawing
(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
(text "power up" (rect 92 74 129 86)(font "Arial" ))
(text "low" (rect 92 84 105 96)(font "Arial" ))
(line (pt 88 16)(pt 152 16)(line_width 1))
(line (pt 152 16)(pt 152 96)(line_width 1))
(line (pt 152 96)(pt 88 96)(line_width 1))
(line (pt 88 96)(pt 88 16)(line_width 1))
)
)

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-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2010 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
-- Created on Sat Jan 15 11:06:17 2011
INCLUDE "lpm_bustri_WORD.inc";
INCLUDE "VIDEO/BLITTER/lpm_clshift384.INC";
INCLUDE "VIDEO/BLITTER/altsyncram0.INC";
INCLUDE "VIDEO/BLITTER/lpm_clshift144.inc";
--CONSTANT BL_SKEW_LF = 255;
-- Title Statement (optional)
TITLE "Blitter";
-- Parameters Statement (optional)
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-- Subdesign Section
SUBDESIGN BLITTER
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
nRSTO : INPUT;
MAIN_CLK : INPUT;
FB_ALE : INPUT;
nFB_WR : INPUT;
nFB_OE : INPUT;
FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT;
VIDEO_RAM_CTR[15..0] : INPUT;
BLITTER_ON : INPUT;
FB_ADR[31..0] : INPUT;
nFB_CS1 : INPUT;
nFB_CS2 : INPUT;
nFB_CS3 : INPUT;
DDRCLK0 : INPUT;
VDP_IN[63..0] : INPUT;
BLITTER_DACK[4..0] : INPUT;
SR_BLITTER_DACK : INPUT;
BLITTER_RUN : OUTPUT;
BLITTER_INT : OUTPUT;
BLITTER_DOUT[127..0] : OUTPUT;
BLITTER_ADR[31..0] : OUTPUT;
BLITTER_SIG : OUTPUT;
BLITTER_WR : OUTPUT;
BLITTER_TA : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
VARIABLE
FB_B[3..0] :NODE;
FB_16B[1..0] :NODE;
BLITTER_CS :NODE;
BL_HRAM_CS :NODE;
BL_HRAM_BE[1..0] :NODE;
BL_HRAM_OUT[15..0] :NODE;
BL_DPRAM_OUT[15..0] :NODE;
BL_SRC_X_INC_CS :NODE;
BL_SRC_X_INC[15..0] :DFFE;
SRC_XINC_NODE[31..0] :NODE;
BL_SRC_Y_INC_CS :NODE;
BL_SRC_Y_INC[15..0] :DFFE;
SRC_YINC_NODE[31..0] :NODE;
BL_ENDMASK1_CS :NODE;
BL_ENDMASK1[15..0] :DFFE;
BL_ENDMASK2_CS :NODE;
BL_ENDMASK2[15..0] :DFFE;
BL_ENDMASK3_CS :NODE;
BL_ENDMASK3[15..0] :DFFE;
BL_SRC_ADRH_CS :NODE;
BL_SRC_ADRL_CS :NODE;
BL_SRC_ADR[31..0] :DFFE;
SRC_IADRH_CS :NODE;
SRC_IADRL_CS :NODE;
SRC_IADR[31..0] :DFF;
SRC_IADR_CLR :NODE;
SIINC :NODE;
SRC_ADR_NODE[31..0] :NODE;
BL_DST_X_INC_CS :NODE;
BL_DST_X_INC[15..0] :DFFE;
DST_XINC_NODE[31..0] :NODE;
BL_DST_Y_INC_CS :NODE;
BL_DST_Y_INC[15..0] :DFFE;
DST_YINC_NODE[31..0] :NODE;
BL_DST_ADRH_CS :NODE;
BL_DST_ADRL_CS :NODE;
BL_DST_ADR[31..0] :DFFE;
DST_IADRH_CS :NODE;
DST_IADRL_CS :NODE;
DST_IADR[31..0] :DFF;
DST_IADR_CLR :NODE;
DST_ADR_NODE[31..0] :NODE;
DIINC :NODE;
BL_X_CNT_CS :NODE;
BL_X_CNT[15..0] :DFFE;
X_CNT_NODE[15..0] :NODE;
BL_Y_CNT_CS :NODE;
BL_Y_CNT[15..0] :DFFE;
BL_HOP_CS :NODE;
BL_HOP[7..0] :DFFE;
BL_OP[7..0] :DFFE;
BL_LN_CS :NODE;
LN7CLR :NODE;
BL_LN[7..0] :DFFE;
BL_SKEW[7..0] :DFFE;
-- barell shifter
DIST_RIGHT[8..0] :NODE;
BL_BS_SKEW[7..0] :NODE;
BL_BSIN[383..0] :NODE;
BL_BSOUT[383..0] :NODE;
SHIFT_DIR :NODE;
BL_SRC_BUF1[127..0] :DFFE;
BL_SRC_BUF2[127..0] :DFFE;
BL_SRC_BUF3[127..0] :DFFE;
BL_DST_BUFRD[127..0] :DFFE;
BL_READ_DST :NODE; -- LATCH SIGNAL DST BUF RD
BL_READ_SRC :NODE; -- LATCH SIGNAL SRC BUF
SRC_READ :NODE; -- FREIGABE LATCH SIGNAL
NOT_DST_READ :NODE;
WREN_B :NODE; -- WR ENA HALFTONE RAM
X_INDEX_CS :NODE;
X_INDEX[15..0] :DFF; -- LAUFZEIGER X COUNT
X_INDEX_CLR :NODE;
Y_INDEX_CS :NODE;
Y_INDEX[15..0] :DFF; -- LAUFZEIGER Y COUNT
Y_INDEX_CLR :NODE;
LINE_NR[3..0] :NODE;
XIINC :NODE; -- INC INDEX SPALTE
YIINC :NODE; -- INC INDEX ZEILE
ZIINC :NODE; -- INC ADRESSEN ZEILENUMBRUCH
ZYINC :NODE; -- KORREKTUR ADRESSEN WENN FERTIG
HOP_OUT[127..0] :NODE;
OP_OUT[127..0] :NODE;
ENDMASK1_SHIFT[7..0] :NODE;
ENDMASK2_SHIFT[7..0] :NODE;
ENDMASK12_IN[143..0] :NODE;
ENDMASK12_OUT[143..0] :NODE;
ENDMASK23_IN[143..0] :NODE;
ENDMASK23_OUT[143..0] :NODE;
ENDMASK123[127..0] :NODE;
DDR_RAM_FREE :NODE;
SRC_DDR_ADR[31..0] :NODE;
DST_DDR_ADR[31..0] :NODE;
-- MAIN STATE MACHINE
BL_SM :MACHINE WITH STATES(START,NEW_LINE,NEW_LINEW,RDSRC1,RDSRC2,RDDST,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG);
BEGIN
-- BYT SELECT 32 BIT
FB_B0 = FB_ADR[1..0]==0; -- ADR==0
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- BYT SELECT 16 BIT
FB_16B0 = FB_ADR[0]==0; -- ADR==0
FB_16B1 = FB_ADR[0]==1 -- wenn ADR==1
# !(!FB_SIZE1 & FB_SIZE0); -- or NOT BYT
-- BLITTER CS
BLITTER_CS = !nFB_CS1 & FB_ADR[19..7]==H"1F14"; -- FFFF8A00-7F
BLITTER_TA = BLITTER_CS;
-- REGISTER
-- HALFTON RAM
BL_HRAM_CS = !nFB_CS1 & FB_ADR[19..5]==H"7C50"; -- $F8A00-1F.w
BL_HRAM_BE1 = BL_HRAM_CS & FB_16B0;
BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1;
WREN_B = B"0";
LINE_NR[] = ((Y_INDEX[3..0] & !BL_DST_Y_INC15) # (!Y_INDEX[3..0] & BL_DST_Y_INC15));
(BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(FB_ADR[4..1],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B);
-- SRC X INC
BL_SRC_X_INC[].CLK = MAIN_CLK;
BL_SRC_X_INC[] = FB_AD[31..16];
BL_SRC_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C510"; -- $F8A20.w
BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_X_INC[7..0].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
SRC_XINC_NODE[] = (H"FFFF0000" & BL_SRC_X_INC15) # (H"0000",BL_SRC_X_INC[]); -- ERWEITERN AUF 32 BIT
-- SRC Y INC
BL_SRC_Y_INC[].CLK = MAIN_CLK;
BL_SRC_Y_INC[] = FB_AD[31..16];
BL_SRC_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C511"; -- $F8A22.w
BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_Y_INC[7..0].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
SRC_YINC_NODE[] = (H"FFFF0000" & BL_SRC_Y_INC15) # (H"0000",BL_SRC_Y_INC[]); -- ERWEITERN AUF 32 BIT
-- SRC ADR HIGH
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[31..16] = FB_AD[31..16];
BL_SRC_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512"; -- $F8A24.w
BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
-- SRC ADR LOW
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[15..0] = FB_AD[31..16];
BL_SRC_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513"; -- $F8A26.w
BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[7..0].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
SRC_IADR[].CLK = DDRCLK0;
SRC_IADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C520"; -- $F8A40.w
SRC_IADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C521"; -- $F8A42.w
SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR; -- L<>SCHEN BEI WRITE
SRC_IADR[] = (SRC_IADR[] + (((8 * SRC_XINC_NODE[]) & SIINC) + (SRC_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[]) - 8) * SRC_XINC_NODE[]) & ZIINC)) & SRC_READ) & !SRC_IADR_CLR;
SRC_ADR_NODE[] = BL_SRC_ADR[] + SRC_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH
-- ENDMASK 1
BL_ENDMASK1[].CLK = MAIN_CLK;
BL_ENDMASK1[] = FB_AD[31..16];
BL_ENDMASK1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C514"; -- $F8A28.w
BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
BL_ENDMASK1[7..0].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
-- ENDMASK 2
BL_ENDMASK2[].CLK = MAIN_CLK;
BL_ENDMASK2[] = FB_AD[31..16];
BL_ENDMASK2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C515"; -- $F8A2A.w
BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
BL_ENDMASK2[7..0].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
-- ENDMASK 3
BL_ENDMASK3[].CLK = MAIN_CLK;
BL_ENDMASK3[] = FB_AD[31..16];
BL_ENDMASK3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C516"; -- $F8A2C.w
BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
BL_ENDMASK3[7..0].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
-- DST X INC
BL_DST_X_INC[].CLK = MAIN_CLK;
BL_DST_X_INC[] = FB_AD[31..16];
BL_DST_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C517"; -- $F8A2E.w
BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
BL_DST_X_INC[7..0].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
DST_XINC_NODE[] = (H"FFFF0000" & BL_DST_X_INC15) # (H"0000",BL_DST_X_INC[]); -- ERWEITERN AUF 32 BIT
-- DST Y INC
BL_DST_Y_INC[].CLK = MAIN_CLK;
BL_DST_Y_INC[] = FB_AD[31..16];
BL_DST_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C518"; -- $F8A30.w
BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
BL_DST_Y_INC[7..0].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
DST_YINC_NODE[] = (H"FFFF0000" & BL_DST_Y_INC15) # (H"0000",BL_DST_Y_INC[]); -- ERWEITERN AUF 32 BIT
-- DST ADR HIGH
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[31..16] = FB_AD[31..16];
BL_DST_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C519"; -- $F8A32.w
BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
-- DST ADR LOW
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[15..0] = FB_AD[31..16];
BL_DST_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51A"; -- $F8A34.w
BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[7..0].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
DST_IADR[].CLK = DDRCLK0;
DST_IADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C522"; -- $F8A44.w
DST_IADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C523"; -- $F8A46.w
DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR; -- L<>SCHEN BEI WRITE
DST_IADR[] = (DST_IADR[] + ((8 * DST_XINC_NODE[]) & DIINC) + (DST_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[])) * DST_XINC_NODE[]) & ZIINC)) & !DST_IADR_CLR;
DST_ADR_NODE[] = BL_DST_ADR[] + DST_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH
-- X COUNT
BL_X_CNT[].CLK = MAIN_CLK;
BL_X_CNT[] = FB_AD[31..16];
BL_X_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51B"; -- $F8A36.w
BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
BL_X_CNT[7..0].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B1;
X_INDEX[].CLK = DDRCLK0;
X_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C524"; -- $F8A48.w
X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR; -- L<>SCHEN BEI WRITE
X_INDEX[] = (X_INDEX[] + (8 & XIINC) + ((BL_X_CNT[] - X_INDEX[]) & ZIINC)) & !X_INDEX_CLR;
X_CNT_NODE[] = X_INDEX[] - ((0,DST_ADR_NODE[3..1]) & (X_INDEX[]!=0));-- EFFEKTIV GELESENE
-- Y COUNT
BL_Y_CNT[].CLK = MAIN_CLK;
BL_Y_CNT[] = FB_AD[31..16];
BL_Y_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51C"; -- $F8A38.w
BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
BL_Y_CNT[7..0].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
Y_INDEX[].CLK = DDRCLK0;
Y_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C525"; -- $F8A4A.w
Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR; -- L<>SCHEN BEI WRITE
Y_INDEX[] = (Y_INDEX[] + (1 & YIINC)) & !Y_INDEX_CLR;
-- HOP LOGIC
BL_HOP[].CLK = MAIN_CLK;
BL_HOP[] = FB_AD[31..24];
BL_HOP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51D"; -- $F8A3A.w
BL_HOP[7..0].ENA = BL_HOP_CS & !nFB_WR & FB_16B0; -- $F8A3A
-- OP LOGIC
BL_OP[].CLK = MAIN_CLK;
BL_OP[] = FB_AD[23..16];
BL_OP[7..0].ENA = BL_HOP_CS & !nFB_WR & FB_16B1; -- $F8A3B
-- LINE NUMBER BYT
BL_LN[].CLK = MAIN_CLK;
BL_LN[6..0] = FB_AD[30..24];
BL_LN7 = FB_AD31 & !LN7CLR; -- BUSY HOG UND SMUDGE
BL_LN_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51E"; -- $F8A3C.w
BL_LN[].ENA = BL_LN_CS & !nFB_WR & FB_16B0; -- $F8A3C
BL_LN7.ENA = LN7CLR;
-- SKEW BYT
BL_SKEW[].CLK = MAIN_CLK;
BL_SKEW[] = FB_AD[23..16];
BL_SKEW[].ENA = BL_LN_CS & !nFB_WR & FB_16B1; -- $F8A3D
--- REGISTER OUT
FB_AD[31..16] = lpm_bustri_WORD(
BL_HRAM_CS & BL_DPRAM_OUT[]
# BL_SRC_X_INC_CS & BL_SRC_X_INC[]
# BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
# BL_SRC_ADRH_CS & SRC_ADR_NODE[31..16]
# BL_SRC_ADRL_CS & SRC_ADR_NODE[15..0]
# BL_ENDMASK1_CS & BL_ENDMASK1[]
# BL_ENDMASK2_CS & BL_ENDMASK2[]
# BL_ENDMASK3_CS & BL_ENDMASK3[]
# BL_DST_X_INC_CS & BL_DST_X_INC[]
# BL_DST_Y_INC_CS & BL_DST_Y_INC[]
# BL_DST_ADRH_CS & DST_ADR_NODE[31..16]
# BL_DST_ADRL_CS & DST_ADR_NODE[15..0]
# BL_X_CNT_CS & (BL_X_CNT[]-X_INDEX[])
# BL_Y_CNT_CS & (BL_Y_CNT[]-Y_INDEX[])
# BL_HOP_CS & (BL_HOP[],BL_OP[])
# BL_LN_CS & (BL_LN[7..4],Y_INDEX[3..0],BL_SKEW[])
# SRC_IADRH_CS & SRC_IADR[31..16]
# SRC_IADRL_CS & SRC_IADR[15..0]
# DST_IADRH_CS & DST_IADR[31..16]
# DST_IADRL_CS & DST_IADR[15..0]
# X_INDEX_CS & X_INDEX[]
# Y_INDEX_CS & Y_INDEX[]
,BLITTER_CS & !nFB_OE); -- FFFF8A00-7F
-----------------------------------------
-- SRC BUFFER LADEN
BL_SRC_BUF1[].CLK = DDRCLK0;
BL_SRC_BUF1[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC;
BL_SRC_BUF1[63..0].ENA = BLITTER_DACK0 & BL_READ_SRC;
BL_SRC_BUF1[] = (VDP_IN[],VDP_IN[]);
BL_SRC_BUF2[].CLK = DDRCLK0;
BL_SRC_BUF2[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC;
BL_SRC_BUF2[63..0].ENA = BLITTER_DACK0 & BL_READ_SRC;
BL_SRC_BUF2[] = BL_SRC_BUF1[];
BL_SRC_BUF3[].CLK = DDRCLK0;
BL_SRC_BUF3[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC;
BL_SRC_BUF3[63..0].ENA = BLITTER_DACK0 & BL_READ_SRC;
BL_SRC_BUF3[] = BL_SRC_BUF2[];
-- ZUORDNUNG ---------
IF BL_SRC_X_INC15 THEN -- WENN NEGATIV -> REIHENFOLGE KEHREN
CASE BL_HOP[7..4] IS -- SPIEGELN?
WHEN H"0" => -- LINE WEISE
BL_BSIN[127..0] = BL_SRC_BUF3[];
BL_BSIN[255..128] = BL_SRC_BUF2[];
BL_BSIN[383..256] = BL_SRC_BUF1[];
WHEN H"1" => --- BIT WEISE
BL_BSIN[0..127] = BL_SRC_BUF3[];
BL_BSIN[128..255] = BL_SRC_BUF2[];
BL_BSIN[256..383] = BL_SRC_BUF1[];
WHEN H"2" => -- BYT WEISE
BL_BSIN[127..0] = (BL_SRC_BUF3[7..0],BL_SRC_BUF3[15..8],BL_SRC_BUF3[23..16],BL_SRC_BUF3[31..24],BL_SRC_BUF3[39..32],BL_SRC_BUF3[47..40],BL_SRC_BUF3[55..48],BL_SRC_BUF3[63..56],BL_SRC_BUF3[71..64],BL_SRC_BUF3[79..72],BL_SRC_BUF3[87..80],BL_SRC_BUF3[95..88],BL_SRC_BUF3[103..96],BL_SRC_BUF3[111..104],BL_SRC_BUF3[119..112],BL_SRC_BUF3[127..120]);
BL_BSIN[255..128] = (BL_SRC_BUF2[7..0],BL_SRC_BUF2[15..8],BL_SRC_BUF2[23..16],BL_SRC_BUF2[31..24],BL_SRC_BUF2[39..32],BL_SRC_BUF2[47..40],BL_SRC_BUF2[55..48],BL_SRC_BUF2[63..56],BL_SRC_BUF2[71..64],BL_SRC_BUF2[79..72],BL_SRC_BUF2[87..80],BL_SRC_BUF2[95..88],BL_SRC_BUF2[103..96],BL_SRC_BUF2[111..104],BL_SRC_BUF2[119..112],BL_SRC_BUF2[127..120]);
BL_BSIN[383..256] = (BL_SRC_BUF1[7..0],BL_SRC_BUF1[15..8],BL_SRC_BUF1[23..16],BL_SRC_BUF1[31..24],BL_SRC_BUF1[39..32],BL_SRC_BUF1[47..40],BL_SRC_BUF1[55..48],BL_SRC_BUF1[63..56],BL_SRC_BUF1[71..64],BL_SRC_BUF1[79..72],BL_SRC_BUF1[87..80],BL_SRC_BUF1[95..88],BL_SRC_BUF1[103..96],BL_SRC_BUF1[111..104],BL_SRC_BUF1[119..112],BL_SRC_BUF1[127..120]);
WHEN H"3" => -- WORD WEISE
BL_BSIN[127..0] = (BL_SRC_BUF3[15..0],BL_SRC_BUF3[31..16],BL_SRC_BUF3[47..32],BL_SRC_BUF3[63..48],BL_SRC_BUF3[79..64],BL_SRC_BUF3[95..80],BL_SRC_BUF3[111..96],BL_SRC_BUF3[127..112]);
BL_BSIN[255..128] = (BL_SRC_BUF2[15..0],BL_SRC_BUF2[31..16],BL_SRC_BUF2[47..32],BL_SRC_BUF2[63..48],BL_SRC_BUF2[79..64],BL_SRC_BUF2[95..80],BL_SRC_BUF2[111..96],BL_SRC_BUF2[127..112]);
BL_BSIN[383..256] = (BL_SRC_BUF1[15..0],BL_SRC_BUF1[31..16],BL_SRC_BUF1[47..32],BL_SRC_BUF1[63..48],BL_SRC_BUF1[79..64],BL_SRC_BUF1[95..80],BL_SRC_BUF1[111..96],BL_SRC_BUF1[127..112]);
WHEN H"4" => -- LONG WEISE
BL_BSIN[127..0] = (BL_SRC_BUF3[31..0],BL_SRC_BUF3[63..32],BL_SRC_BUF3[95..64],BL_SRC_BUF3[127..96]);
BL_BSIN[255..128] = (BL_SRC_BUF2[31..0],BL_SRC_BUF2[63..32],BL_SRC_BUF2[95..64],BL_SRC_BUF2[127..96]);
BL_BSIN[383..256] = (BL_SRC_BUF1[31..0],BL_SRC_BUF1[63..32],BL_SRC_BUF1[95..64],BL_SRC_BUF1[127..96]);
WHEN OTHERS => -- LINE WEISE
BL_BSIN[127..0] = BL_SRC_BUF3[];
BL_BSIN[255..128] = BL_SRC_BUF2[];
BL_BSIN[383..256] = BL_SRC_BUF1[];
END CASE;
ELSE -- SONST NORMAL BEI VORW<52>RTS
BL_BSIN[127..0] = BL_SRC_BUF1[];
BL_BSIN[255..128] = BL_SRC_BUF2[];
BL_BSIN[383..256] = BL_SRC_BUF3[];
END IF;
-- DST BUFFER READ
BL_DST_BUFRD[].CLK = DDRCLK0;
BL_DST_BUFRD[127..64].ENA = BLITTER_DACK1 & BL_READ_DST;
BL_DST_BUFRD[63..0].ENA = BLITTER_DACK0 & BL_READ_DST;
BL_DST_BUFRD[] = (VDP_IN[],VDP_IN[]);
-- barell shift *****************************************************************************
-- SOURCE SHIFT RIGHT = LPM_CSHIFT RIGTH ;SKEW SHIFT: IF FXRS==0 THEN RIGHT ELSE LEFT
DIST_RIGHT[] = (16 * ((0,DST_ADR_NODE[3..1]) - (0,SRC_ADR_NODE[3..1]))) + (!BL_SKEW7 & (0,BL_SKEW[3..0])) - (BL_SKEW7 & (0,BL_SKEW[3..0]));
IF DIST_RIGHT8 == 0 THEN
BL_BS_SKEW[] = DIST_RIGHT[7..0]; -- LPM SHIFT RIGHT
SHIFT_DIR = VCC; -- DIR = RIGHT
else
BL_BS_SKEW[] = !DIST_RIGHT[3..0] + 1; -- LPM SHIFT LEFT
SHIFT_DIR = GND; -- DIR = LEFT
end if;
-- barell shifter: direction 0=links 1=rechts IN BEZUG AUF ausgabewert!
BL_BSOUT[] = lpm_clshift384(BL_BSIN[], SHIFT_DIR , BL_BS_SKEW[]); -- wir brauchen 128bit
-- HOP ***************************************************************************************
CASE BL_HOP[1..0] IS
WHEN H"0" =>
-- 12345678901234567890123456789012
HOP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
WHEN H"1" =>
HOP_OUT[] = (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]);
WHEN H"2" =>
HOP_OUT[] = BL_BSOUT[255..128];
WHEN OTHERS =>
HOP_OUT[] = (BL_BSOUT[255..128] & (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]));
END CASE;
-- OP *****************************************************************************************
CASE BL_OP[3..0] IS
WHEN H"0" =>
OP_OUT[] = H"0";
SRC_READ = B"0";
WHEN H"1" =>
OP_OUT[] = HOP_OUT[] & BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN H"2" =>
OP_OUT[] = HOP_OUT[] & !BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN H"3" =>
OP_OUT[] = HOP_OUT[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN H"4" =>
OP_OUT[] = !HOP_OUT[] & BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN H"5" =>
OP_OUT[] = BL_DST_BUFRD[];
SRC_READ = B"0";
WHEN H"6" =>
OP_OUT[] = HOP_OUT[] $ BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN H"7" =>
OP_OUT[] = HOP_OUT[] # BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN H"8" =>
OP_OUT[] = !HOP_OUT[] & !BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN H"9" =>
OP_OUT[] = !HOP_OUT[] $ BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN H"A" =>
OP_OUT[] = !BL_DST_BUFRD[];
SRC_READ = B"0";
WHEN H"B" =>
OP_OUT[] = HOP_OUT[] # !BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN H"C" =>
OP_OUT[] = !HOP_OUT[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN H"D" =>
OP_OUT[] = !HOP_OUT[] # BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN H"E" =>
OP_OUT[] = !HOP_OUT[] # !BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN OTHERS =>
-- 12345678901234567890123456789012
OP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
SRC_READ = B"0";
END CASE;
------------ ENDMASKEN SETZEN ******************************************************************************
ENDMASK1_SHIFT[3..0] = 0;
ENDMASK2_SHIFT[3..0] = 0;
IF BL_DST_X_INC15 THEN ---------------------------- R<>CKW<4B>RTS X_INC NEGATIV
IF X_INDEX[]==0 THEN -- ENDE?
ENDMASK2_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); -- JA ENDMASK 3 SETZEN
ELSE
ENDMASK2_SHIFT[7..4] = 0; -- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN
END IF;
IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN -- SCHON ZEILENANFANG?
ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); -- JA ENDMASK 3 SETZEN
ELSE
ENDMASK1_SHIFT[7..4] = 0; -- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN
END IF;
ELSE ------------------------------------------- VORW<52>RTS X_INC POSITIV
IF X_INDEX[]==0 THEN -- ANFANG?
ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); -- JA -> ENDMASK 1 SETZEN
ELSE
ENDMASK1_SHIFT[7..4] = 0; -- NEIN->ENDMASK1 AUF ENDMASK2 SETZEN
END IF;
IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN -- SCHON ZEILENENDE?
ENDMASK2_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); -- JA ENDMASK 3 SETZEN
ELSE
ENDMASK2_SHIFT[7..4] = 0; -- NOCH NICHT AKTIV->ENDMASK 3 AUF ENDMASK2 SETZEN
END IF;
END IF;
-- ENDMASKEN -- barell shifter 144 bit, direction 0 = links 1 = rechts
-- 1234567890123456789012345678
ENDMASK12_IN[] = (BL_ENDMASK1[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
ENDMASK12_OUT[] = lpm_clshift144(ENDMASK12_IN[],1,ENDMASK1_SHIFT[]); -- IMMER rechts SCHIEBEN
ENDMASK23_IN[] = (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK3[]);
ENDMASK23_OUT[] = lpm_clshift144(ENDMASK23_IN[],0,ENDMASK2_SHIFT[]); -- IMMER LINKS SCHIEBEN
ENDMASK123[] = ENDMASK12_OUT[127..0] & ENDMASK23_OUT[143..16];
BLITTER_DOUT[] = ((ENDMASK123[] & OP_OUT[]) # (!ENDMASK123[] & BL_DST_BUFRD[]));
NOT_DST_READ = BL_OP[3..0]==(H"0" # H"3" # H"C" # H"F") & (ENDMASK123[]==-1);
-- STATE MACHINE ****************************************************************************************************
BLITTER_RUN = BLITTER_ON; -- BLITTER IST DA!
DDR_RAM_FREE = BLITTER_DACK[]==H"0"; -- 0 WENN FREI
BLITTER_ADR[3..0] = H"0"; -- IMMER LINE
SRC_DDR_ADR[] = (SRC_ADR_NODE[] - (0,(16 & BL_SRC_X_INC15))); -- WENN R<>CKW<4B>RTS NEXT ADRESS SRC
DST_DDR_ADR[] = (DST_ADR_NODE[] - (0,(16 & BL_DST_X_INC15))); -- WENN R<>CKW<4B>RTS NEXT ADRESS DST
-- BLITTER MAIN STATE MACHINE -----------------------------------------------
BL_SM.CLK = DDRCLK0;
CASE BL_SM IS
WHEN START => ------------------------- START
IF BLITTER_ON & BL_LN7 & ((BL_X_CNT[] - X_CNT_NODE[])>0) & ((BL_Y_CNT[] - Y_INDEX[]) > 0) THEN
BL_SM = NEW_LINE;
ELSE
BL_SM = START;
END IF;
WHEN NEW_LINE => ----------------------- NEU LINIE
X_INDEX_CLR = VCC; -- L<>SCHEN
BL_SM = RDSRC1;
WHEN RDSRC1 => ------------------------ READ SRC1
IF SRC_READ THEN
BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4];
BLITTER_SIG = DDR_RAM_FREE;
BL_READ_SRC = VCC; -- LATCH UND SB1->SB2
IF BLITTER_DACK0 THEN
SIINC = VCC; -- INC SRC ADR
BL_SM = RDSRC2;
ELSE
BL_SM = RDSRC1;
END IF;
ELSE
BL_SM = RDDST;
END IF;
WHEN RDSRC2 => ------------------------ READ SRC2
IF SRC_READ THEN
BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4];
BLITTER_SIG = DDR_RAM_FREE;
BL_READ_SRC = VCC; -- LATCH UND SB1->SB2
IF BLITTER_DACK0 THEN
SIINC = VCC; -- INC SRC ADR
BL_SM = RDDST;
ELSE
BL_SM = RDSRC2;
END IF;
ELSE
BL_SM = RDDST;
END IF;
WHEN RDDST => ----------------------- READ DEST
IF NOT_DST_READ THEN
BL_SM = WRDST;
ELSE
BLITTER_ADR[31..4] = DST_DDR_ADR[31..4];
BLITTER_SIG = DDR_RAM_FREE;
BL_READ_DST = VCC;
IF BLITTER_DACK0 THEN
BL_SM = WRDST;
ELSE
BL_SM = RDDST;
END IF;
END IF;
WHEN WRDST => ------------------- WRITE DEST
BLITTER_ADR[31..4] = DST_DDR_ADR[31..4];
BLITTER_WR = DDR_RAM_FREE;
BLITTER_SIG = DDR_RAM_FREE;
IF BLITTER_DACK0 THEN
XIINC = VCC; -- INC X_INDEX
DIINC = VCC; -- INC DEST ADR
BL_SM = TESTZEILENENDE;
ELSE
BL_SM = WRDST;
END IF;
WHEN TESTZEILENENDE => ----------------- ZEILENDE?
IF BL_X_CNT[]<=(X_CNT_NODE[]) THEN -- SCHON ZEILENENDE?
YIINC = VCC; -- JA -> INC Y-INDEX UND ZEILE SRC UND DEST
BL_SM = TESTFERTIG; -- ->
ELSE
BL_SM = RDSRC2; -- NEIN NEXT
END IF;
WHEN TESTFERTIG => --------------------- TEST AUF FERTIG
ZIINC = VCC; -- INC ADRESSEN ZEILENUMBRUCH
IF Y_INDEX[]>=BL_Y_CNT[] THEN -- LETZTE ZEILE?
BL_SM = FERTIG; -- JA -->
ELSE
ZYINC = VCC; -- YINC ADDIEREN ZEILENENDE
BL_SM = NEW_LINE; -- NEIN NEXT ->
END IF;
WHEN FERTIG => -------------------------- FERTIG
BLITTER_INT = VCC; -- BLITTER INTERRUPT
LN7CLR = VCC; -- BUSY BIT L<>SCHEN
IF BL_LN7==0 THEN -- WARTEN BIS GEL<45>SCHT (GEHT NUR MIT 33MHz)
BL_SM = START;
ELSE
BL_SM = FERTIG;
END IF;
WHEN OTHERS =>
BL_SM = FERTIG;
END CASE;
END;

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-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2010 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
-- Created on Sat Jan 15 11:06:17 2011
INCLUDE "lpm_bustri_WORD.inc";
INCLUDE "VIDEO/BLITTER/lpm_clshift384.INC";
INCLUDE "VIDEO/BLITTER/altsyncram0.INC";
INCLUDE "VIDEO/BLITTER/lpm_clshift144.inc";
--CONSTANT BL_SKEW_LF = 255;
-- Title Statement (optional)
TITLE "Blitter";
-- Parameters Statement (optional)
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-- Subdesign Section
SUBDESIGN BLITTER
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
nRSTO : INPUT;
MAIN_CLK : INPUT;
FB_ALE : INPUT;
nFB_WR : INPUT;
nFB_OE : INPUT;
FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT;
VIDEO_RAM_CTR[15..0] : INPUT;
BLITTER_ON : INPUT;
FB_ADR[31..0] : INPUT;
nFB_CS1 : INPUT;
nFB_CS2 : INPUT;
nFB_CS3 : INPUT;
DDRCLK0 : INPUT;
VDP_IN[63..0] : INPUT;
BLITTER_DACK[4..0] : INPUT;
SR_BLITTER_DACK : INPUT;
BLITTER_RUN : OUTPUT;
BLITTER_INT : OUTPUT;
BLITTER_DOUT[127..0] : OUTPUT;
BLITTER_ADR[31..0] : OUTPUT;
BLITTER_SIG : OUTPUT;
BLITTER_WR : OUTPUT;
BLITTER_TA : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
VARIABLE
FB_B[3..0] :NODE;
FB_16B[1..0] :NODE;
BLITTER_CS :NODE;
BL_HRAM_CS :NODE;
BL_HRAM_BE[1..0] :NODE;
BL_HRAM_OUT[15..0] :NODE;
BL_DPRAM_OUT[15..0] :NODE;
BL_SRC_X_INC_CS :NODE;
BL_SRC_X_INC[15..0] :DFFE;
SRC_XINC_NODE[31..0] :NODE;
BL_SRC_Y_INC_CS :NODE;
BL_SRC_Y_INC[15..0] :DFFE;
SRC_YINC_NODE[31..0] :NODE;
BL_ENDMASK1_CS :NODE;
BL_ENDMASK1[15..0] :DFFE;
BL_ENDMASK2_CS :NODE;
BL_ENDMASK2[15..0] :DFFE;
BL_ENDMASK3_CS :NODE;
BL_ENDMASK3[15..0] :DFFE;
BL_SRC_ADRH_CS :NODE;
BL_SRC_ADRL_CS :NODE;
BL_SRC_ADR[31..0] :DFFE;
SRC_IADRH_CS :NODE;
SRC_IADRL_CS :NODE;
SRC_IADR[31..0] :DFF;
SRC_IADR_CLR :NODE;
SIINC :NODE;
SRC_ADR_NODE[31..0] :NODE;
BL_DST_X_INC_CS :NODE;
BL_DST_X_INC[15..0] :DFFE;
DST_XINC_NODE[31..0] :NODE;
BL_DST_Y_INC_CS :NODE;
BL_DST_Y_INC[15..0] :DFFE;
DST_YINC_NODE[31..0] :NODE;
BL_DST_ADRH_CS :NODE;
BL_DST_ADRL_CS :NODE;
BL_DST_ADR[31..0] :DFFE;
DST_IADRH_CS :NODE;
DST_IADRL_CS :NODE;
DST_IADR[31..0] :DFF;
DST_IADR_CLR :NODE;
DST_ADR_NODE[31..0] :NODE;
DIINC :NODE;
BL_X_CNT_CS :NODE;
BL_X_CNT[15..0] :DFFE;
X_CNT_NODE[15..0] :NODE;
BL_Y_CNT_CS :NODE;
BL_Y_CNT[15..0] :DFFE;
BL_HOP_CS :NODE;
BL_HOP[7..0] :DFFE;
BL_OP[7..0] :DFFE;
BL_LN_CS :NODE;
LN7CLR :NODE;
BL_LN[7..0] :DFFE;
BL_SKEW[7..0] :DFFE;
-- barell shifter
DIST_RIGHT[8..0] :NODE;
BL_BS_SKEW[7..0] :NODE;
BL_BSIN[383..0] :NODE;
BL_BSOUT[383..0] :NODE;
SHIFT_DIR :NODE;
BL_SRC_BUF1[127..0] :DFFE;
BL_SRC_BUF2[127..0] :DFFE;
BL_SRC_BUF3[127..0] :DFFE;
BL_DST_BUFRD[127..0] :DFFE;
BL_READ_DST :NODE; -- LATCH SIGNAL DST BUF RD
BL_READ_SRC :NODE; -- LATCH SIGNAL SRC BUF
SRC_READ :NODE; -- FREIGABE LATCH SIGNAL
NOT_DST_READ :NODE;
WREN_B :NODE; -- WR ENA HALFTONE RAM
X_INDEX_CS :NODE;
X_INDEX[15..0] :DFF; -- LAUFZEIGER X COUNT
X_INDEX_CLR :NODE;
Y_INDEX_CS :NODE;
Y_INDEX[15..0] :DFF; -- LAUFZEIGER Y COUNT
Y_INDEX_CLR :NODE;
LINE_NR[3..0] :NODE;
XIINC :NODE; -- INC INDEX SPALTE
YIINC :NODE; -- INC INDEX ZEILE
ZIINC :NODE; -- INC ADRESSEN ZEILENUMBRUCH
ZYINC :NODE; -- KORREKTUR ADRESSEN WENN FERTIG
HOP_OUT[127..0] :NODE;
OP_OUT[127..0] :NODE;
ENDMASK1_SHIFT[7..0] :NODE;
ENDMASK2_SHIFT[7..0] :NODE;
ENDMASK12_IN[143..0] :NODE;
ENDMASK12_OUT[143..0] :NODE;
ENDMASK23_IN[143..0] :NODE;
ENDMASK23_OUT[143..0] :NODE;
ENDMASK123[127..0] :NODE;
DDR_RAM_FREE :NODE;
SRC_DDR_ADR[31..0] :NODE;
DST_DDR_ADR[31..0] :NODE;
-- MAIN STATE MACHINE
BL_SM :MACHINE WITH STATES(START,NEW_LINE,NEW_LINEW,RDSRC1,RDSRC2,RDDST,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG);
BEGIN
-- BYT SELECT 32 BIT
FB_B0 = FB_ADR[1..0]==0; -- ADR==0
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- BYT SELECT 16 BIT
FB_16B0 = FB_ADR[0]==0; -- ADR==0
FB_16B1 = FB_ADR[0]==1 -- wenn ADR==1
# !(!FB_SIZE1 & FB_SIZE0); -- or NOT BYT
-- BLITTER CS
BLITTER_CS = !nFB_CS1 & FB_ADR[19..7]==H"1F14"; -- FFFF8A00-7F
BLITTER_TA = BLITTER_CS;
-- REGISTER
-- HALFTON RAM
BL_HRAM_CS = !nFB_CS1 & FB_ADR[19..5]==H"7C50"; -- $F8A00-1F.w
BL_HRAM_BE1 = BL_HRAM_CS & FB_16B0;
BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1;
WREN_B = B"0";
LINE_NR[] = ((Y_INDEX[3..0] & !BL_DST_Y_INC15) # (!Y_INDEX[3..0] & BL_DST_Y_INC15));
(BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(FB_ADR[4..1],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B);
-- SRC X INC
BL_SRC_X_INC[].CLK = MAIN_CLK;
BL_SRC_X_INC[] = FB_AD[31..16];
BL_SRC_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C510"; -- $F8A20.w
BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_X_INC[7..0].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
SRC_XINC_NODE[] = (H"FFFF0000" & BL_SRC_X_INC15) # (H"0000",BL_SRC_X_INC[]); -- ERWEITERN AUF 32 BIT
-- SRC Y INC
BL_SRC_Y_INC[].CLK = MAIN_CLK;
BL_SRC_Y_INC[] = FB_AD[31..16];
BL_SRC_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C511"; -- $F8A22.w
BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
BL_SRC_Y_INC[7..0].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
SRC_YINC_NODE[] = (H"FFFF0000" & BL_SRC_Y_INC15) # (H"0000",BL_SRC_Y_INC[]); -- ERWEITERN AUF 32 BIT
-- SRC ADR HIGH
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[31..16] = FB_AD[31..16];
BL_SRC_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512"; -- $F8A24.w
BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
-- SRC ADR LOW
BL_SRC_ADR[].CLK = MAIN_CLK;
BL_SRC_ADR[15..0] = FB_AD[31..16];
BL_SRC_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513"; -- $F8A26.w
BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
BL_SRC_ADR[7..0].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
SRC_IADR[].CLK = DDRCLK0;
SRC_IADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C520"; -- $F8A40.w
SRC_IADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C521"; -- $F8A42.w
SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR; -- L<>SCHEN BEI WRITE
SRC_IADR[] = (SRC_IADR[] + (((8 * SRC_XINC_NODE[]) & SIINC) + (SRC_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[]) - 8) * SRC_XINC_NODE[]) & ZIINC)) & SRC_READ) & !SRC_IADR_CLR;
SRC_ADR_NODE[] = BL_SRC_ADR[] + SRC_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH
-- ENDMASK 1
BL_ENDMASK1[].CLK = MAIN_CLK;
BL_ENDMASK1[] = FB_AD[31..16];
BL_ENDMASK1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C514"; -- $F8A28.w
BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
BL_ENDMASK1[7..0].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
-- ENDMASK 2
BL_ENDMASK2[].CLK = MAIN_CLK;
BL_ENDMASK2[] = FB_AD[31..16];
BL_ENDMASK2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C515"; -- $F8A2A.w
BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
BL_ENDMASK2[7..0].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
-- ENDMASK 3
BL_ENDMASK3[].CLK = MAIN_CLK;
BL_ENDMASK3[] = FB_AD[31..16];
BL_ENDMASK3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C516"; -- $F8A2C.w
BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
BL_ENDMASK3[7..0].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
-- DST X INC
BL_DST_X_INC[].CLK = MAIN_CLK;
BL_DST_X_INC[] = FB_AD[31..16];
BL_DST_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C517"; -- $F8A2E.w
BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
BL_DST_X_INC[7..0].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
DST_XINC_NODE[] = (H"FFFF0000" & BL_DST_X_INC15) # (H"0000",BL_DST_X_INC[]); -- ERWEITERN AUF 32 BIT
-- DST Y INC
BL_DST_Y_INC[].CLK = MAIN_CLK;
BL_DST_Y_INC[] = FB_AD[31..16];
BL_DST_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C518"; -- $F8A30.w
BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
BL_DST_Y_INC[7..0].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
DST_YINC_NODE[] = (H"FFFF0000" & BL_DST_Y_INC15) # (H"0000",BL_DST_Y_INC[]); -- ERWEITERN AUF 32 BIT
-- DST ADR HIGH
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[31..16] = FB_AD[31..16];
BL_DST_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C519"; -- $F8A32.w
BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
-- DST ADR LOW
BL_DST_ADR[].CLK = MAIN_CLK;
BL_DST_ADR[15..0] = FB_AD[31..16];
BL_DST_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51A"; -- $F8A34.w
BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
BL_DST_ADR[7..0].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
DST_IADR[].CLK = DDRCLK0;
DST_IADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C522"; -- $F8A44.w
DST_IADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C523"; -- $F8A46.w
DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR; -- L<>SCHEN BEI WRITE
DST_IADR[] = (DST_IADR[] + ((8 * DST_XINC_NODE[]) & DIINC) + (DST_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[])) * DST_XINC_NODE[]) & ZIINC)) & !DST_IADR_CLR;
DST_ADR_NODE[] = BL_DST_ADR[] + DST_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH
-- X COUNT
BL_X_CNT[].CLK = MAIN_CLK;
BL_X_CNT[] = FB_AD[31..16];
BL_X_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51B"; -- $F8A36.w
BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
BL_X_CNT[7..0].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B1;
X_INDEX[].CLK = DDRCLK0;
X_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C524"; -- $F8A48.w
X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR; -- L<>SCHEN BEI WRITE
X_INDEX[] = (X_INDEX[] + (8 & XIINC) + ((BL_X_CNT[] - X_INDEX[]) & ZIINC)) & !X_INDEX_CLR;
X_CNT_NODE[] = X_INDEX[] - ((0,DST_ADR_NODE[3..1]) & (X_INDEX[]!=0));-- EFFEKTIV GELESENE
-- Y COUNT
BL_Y_CNT[].CLK = MAIN_CLK;
BL_Y_CNT[] = FB_AD[31..16];
BL_Y_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51C"; -- $F8A38.w
BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
BL_Y_CNT[7..0].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
Y_INDEX[].CLK = DDRCLK0;
Y_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C525"; -- $F8A4A.w
Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR; -- L<>SCHEN BEI WRITE
Y_INDEX[] = (Y_INDEX[] + (1 & YIINC)) & !Y_INDEX_CLR;
-- HOP LOGIC
BL_HOP[].CLK = MAIN_CLK;
BL_HOP[] = FB_AD[31..24];
BL_HOP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51D"; -- $F8A3A.w
BL_HOP[7..0].ENA = BL_HOP_CS & !nFB_WR & FB_16B0; -- $F8A3A
-- OP LOGIC
BL_OP[].CLK = MAIN_CLK;
BL_OP[] = FB_AD[23..16];
BL_OP[7..0].ENA = BL_HOP_CS & !nFB_WR & FB_16B1; -- $F8A3B
-- LINE NUMBER BYT
BL_LN[].CLK = MAIN_CLK;
BL_LN[6..0] = FB_AD[30..24];
BL_LN7 = FB_AD31 & !LN7CLR; -- BUSY HOG UND SMUDGE
BL_LN_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51E"; -- $F8A3C.w
BL_LN[].ENA = BL_LN_CS & !nFB_WR & FB_16B0; -- $F8A3C
BL_LN7.ENA = LN7CLR;
-- SKEW BYT
BL_SKEW[].CLK = MAIN_CLK;
BL_SKEW[] = FB_AD[23..16];
BL_SKEW[].ENA = BL_LN_CS & !nFB_WR & FB_16B1; -- $F8A3D
--- REGISTER OUT
FB_AD[31..16] = lpm_bustri_WORD(
BL_HRAM_CS & BL_DPRAM_OUT[]
# BL_SRC_X_INC_CS & BL_SRC_X_INC[]
# BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
# BL_SRC_ADRH_CS & SRC_ADR_NODE[31..16]
# BL_SRC_ADRL_CS & SRC_ADR_NODE[15..0]
# BL_ENDMASK1_CS & BL_ENDMASK1[]
# BL_ENDMASK2_CS & BL_ENDMASK2[]
# BL_ENDMASK3_CS & BL_ENDMASK3[]
# BL_DST_X_INC_CS & BL_DST_X_INC[]
# BL_DST_Y_INC_CS & BL_DST_Y_INC[]
# BL_DST_ADRH_CS & DST_ADR_NODE[31..16]
# BL_DST_ADRL_CS & DST_ADR_NODE[15..0]
# BL_X_CNT_CS & (BL_X_CNT[]-X_INDEX[])
# BL_Y_CNT_CS & (BL_Y_CNT[]-Y_INDEX[])
# BL_HOP_CS & (BL_HOP[],BL_OP[])
# BL_LN_CS & (BL_LN[7..4],Y_INDEX[3..0],BL_SKEW[])
# SRC_IADRH_CS & SRC_IADR[31..16]
# SRC_IADRL_CS & SRC_IADR[15..0]
# DST_IADRH_CS & DST_IADR[31..16]
# DST_IADRL_CS & DST_IADR[15..0]
# X_INDEX_CS & X_INDEX[]
# Y_INDEX_CS & Y_INDEX[]
,BLITTER_CS & !nFB_OE); -- FFFF8A00-7F
-----------------------------------------
-- SRC BUFFER LADEN
BL_SRC_BUF1[].CLK = DDRCLK0;
BL_SRC_BUF1[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC;
BL_SRC_BUF1[63..0].ENA = BLITTER_DACK0 & BL_READ_SRC;
BL_SRC_BUF1[] = (VDP_IN[],VDP_IN[]);
BL_SRC_BUF2[].CLK = DDRCLK0;
BL_SRC_BUF2[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC;
BL_SRC_BUF2[63..0].ENA = BLITTER_DACK0 & BL_READ_SRC;
BL_SRC_BUF2[] = BL_SRC_BUF1[];
BL_SRC_BUF3[].CLK = DDRCLK0;
BL_SRC_BUF3[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC;
BL_SRC_BUF3[63..0].ENA = BLITTER_DACK0 & BL_READ_SRC;
BL_SRC_BUF3[] = BL_SRC_BUF2[];
-- ZUORDNUNG ---------
IF BL_SRC_X_INC15 THEN -- WENN NEGATIV -> REIHENFOLGE KEHREN
CASE BL_HOP[7..4] IS -- SPIEGELN?
WHEN H"0" => -- LINE WEISE
BL_BSIN[127..0] = BL_SRC_BUF3[];
BL_BSIN[255..128] = BL_SRC_BUF2[];
BL_BSIN[383..256] = BL_SRC_BUF1[];
WHEN H"1" => --- BIT WEISE
BL_BSIN[0..127] = BL_SRC_BUF3[];
BL_BSIN[128..255] = BL_SRC_BUF2[];
BL_BSIN[256..383] = BL_SRC_BUF1[];
WHEN H"2" => -- BYT WEISE
BL_BSIN[127..0] = (BL_SRC_BUF3[7..0],BL_SRC_BUF3[15..8],BL_SRC_BUF3[23..16],BL_SRC_BUF3[31..24],BL_SRC_BUF3[39..32],BL_SRC_BUF3[47..40],BL_SRC_BUF3[55..48],BL_SRC_BUF3[63..56],BL_SRC_BUF3[71..64],BL_SRC_BUF3[79..72],BL_SRC_BUF3[87..80],BL_SRC_BUF3[95..88],BL_SRC_BUF3[103..96],BL_SRC_BUF3[111..104],BL_SRC_BUF3[119..112],BL_SRC_BUF3[127..120]);
BL_BSIN[255..128] = (BL_SRC_BUF2[7..0],BL_SRC_BUF2[15..8],BL_SRC_BUF2[23..16],BL_SRC_BUF2[31..24],BL_SRC_BUF2[39..32],BL_SRC_BUF2[47..40],BL_SRC_BUF2[55..48],BL_SRC_BUF2[63..56],BL_SRC_BUF2[71..64],BL_SRC_BUF2[79..72],BL_SRC_BUF2[87..80],BL_SRC_BUF2[95..88],BL_SRC_BUF2[103..96],BL_SRC_BUF2[111..104],BL_SRC_BUF2[119..112],BL_SRC_BUF2[127..120]);
BL_BSIN[383..256] = (BL_SRC_BUF1[7..0],BL_SRC_BUF1[15..8],BL_SRC_BUF1[23..16],BL_SRC_BUF1[31..24],BL_SRC_BUF1[39..32],BL_SRC_BUF1[47..40],BL_SRC_BUF1[55..48],BL_SRC_BUF1[63..56],BL_SRC_BUF1[71..64],BL_SRC_BUF1[79..72],BL_SRC_BUF1[87..80],BL_SRC_BUF1[95..88],BL_SRC_BUF1[103..96],BL_SRC_BUF1[111..104],BL_SRC_BUF1[119..112],BL_SRC_BUF1[127..120]);
WHEN H"3" => -- WORD WEISE
BL_BSIN[127..0] = (BL_SRC_BUF3[15..0],BL_SRC_BUF3[31..16],BL_SRC_BUF3[47..32],BL_SRC_BUF3[63..48],BL_SRC_BUF3[79..64],BL_SRC_BUF3[95..80],BL_SRC_BUF3[111..96],BL_SRC_BUF3[127..112]);
BL_BSIN[255..128] = (BL_SRC_BUF2[15..0],BL_SRC_BUF2[31..16],BL_SRC_BUF2[47..32],BL_SRC_BUF2[63..48],BL_SRC_BUF2[79..64],BL_SRC_BUF2[95..80],BL_SRC_BUF2[111..96],BL_SRC_BUF2[127..112]);
BL_BSIN[383..256] = (BL_SRC_BUF1[15..0],BL_SRC_BUF1[31..16],BL_SRC_BUF1[47..32],BL_SRC_BUF1[63..48],BL_SRC_BUF1[79..64],BL_SRC_BUF1[95..80],BL_SRC_BUF1[111..96],BL_SRC_BUF1[127..112]);
WHEN H"4" => -- LONG WEISE
BL_BSIN[127..0] = (BL_SRC_BUF3[31..0],BL_SRC_BUF3[63..32],BL_SRC_BUF3[95..64],BL_SRC_BUF3[127..96]);
BL_BSIN[255..128] = (BL_SRC_BUF2[31..0],BL_SRC_BUF2[63..32],BL_SRC_BUF2[95..64],BL_SRC_BUF2[127..96]);
BL_BSIN[383..256] = (BL_SRC_BUF1[31..0],BL_SRC_BUF1[63..32],BL_SRC_BUF1[95..64],BL_SRC_BUF1[127..96]);
WHEN OTHERS => -- LINE WEISE
BL_BSIN[127..0] = BL_SRC_BUF3[];
BL_BSIN[255..128] = BL_SRC_BUF2[];
BL_BSIN[383..256] = BL_SRC_BUF1[];
END CASE;
ELSE -- SONST NORMAL BEI VORW<52>RTS
BL_BSIN[127..0] = BL_SRC_BUF1[];
BL_BSIN[255..128] = BL_SRC_BUF2[];
BL_BSIN[383..256] = BL_SRC_BUF3[];
END IF;
-- DST BUFFER READ
BL_DST_BUFRD[].CLK = DDRCLK0;
BL_DST_BUFRD[127..64].ENA = BLITTER_DACK1 & BL_READ_DST;
BL_DST_BUFRD[63..0].ENA = BLITTER_DACK0 & BL_READ_DST;
BL_DST_BUFRD[] = (VDP_IN[],VDP_IN[]);
-- barell shift *****************************************************************************
-- SOURCE SHIFT RIGHT = LPM_CSHIFT RIGTH ;SKEW SHIFT: IF FXRS==0 THEN RIGHT ELSE LEFT
DIST_RIGHT[] = (16 * ((0,DST_ADR_NODE[3..1]) - (0,SRC_ADR_NODE[3..1]))) + (!BL_SKEW7 & (0,BL_SKEW[3..0])) - (BL_SKEW7 & (0,BL_SKEW[3..0]));
IF DIST_RIGHT8 == 0 THEN
BL_BS_SKEW[] = DIST_RIGHT[7..0]; -- LPM SHIFT RIGHT
SHIFT_DIR = VCC; -- DIR = RIGHT
else
BL_BS_SKEW[] = !DIST_RIGHT[3..0] + 1; -- LPM SHIFT LEFT
SHIFT_DIR = GND; -- DIR = LEFT
end if;
-- barell shifter: direction 0=links 1=rechts IN BEZUG AUF ausgabewert!
BL_BSOUT[] = lpm_clshift384(BL_BSIN[], SHIFT_DIR , BL_BS_SKEW[]); -- wir brauchen 128bit
-- HOP ***************************************************************************************
CASE BL_HOP[1..0] IS
WHEN H"0" =>
-- 12345678901234567890123456789012
HOP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
WHEN H"1" =>
HOP_OUT[] = (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]);
WHEN H"2" =>
HOP_OUT[] = BL_BSOUT[255..128];
WHEN OTHERS =>
HOP_OUT[] = (BL_BSOUT[255..128] & (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]));
END CASE;
-- OP *****************************************************************************************
CASE BL_OP[3..0] IS
WHEN H"0" =>
OP_OUT[] = H"0";
SRC_READ = B"0";
WHEN H"1" =>
OP_OUT[] = HOP_OUT[] & BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN H"2" =>
OP_OUT[] = HOP_OUT[] & !BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN H"3" =>
OP_OUT[] = HOP_OUT[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN H"4" =>
OP_OUT[] = !HOP_OUT[] & BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN H"5" =>
OP_OUT[] = BL_DST_BUFRD[];
SRC_READ = B"0";
WHEN H"6" =>
OP_OUT[] = HOP_OUT[] $ BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN H"7" =>
OP_OUT[] = HOP_OUT[] # BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN H"8" =>
OP_OUT[] = !HOP_OUT[] & !BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN H"9" =>
OP_OUT[] = !HOP_OUT[] $ BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN H"A" =>
OP_OUT[] = !BL_DST_BUFRD[];
SRC_READ = B"0";
WHEN H"B" =>
OP_OUT[] = HOP_OUT[] # !BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN H"C" =>
OP_OUT[] = !HOP_OUT[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN H"D" =>
OP_OUT[] = !HOP_OUT[] # BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN H"E" =>
OP_OUT[] = !HOP_OUT[] # !BL_DST_BUFRD[];
SRC_READ = BL_HOP1 # BL_HOP0;
WHEN OTHERS =>
-- 12345678901234567890123456789012
OP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
SRC_READ = B"0";
END CASE;
------------ ENDMASKEN SETZEN ******************************************************************************
ENDMASK1_SHIFT[3..0] = 0;
ENDMASK2_SHIFT[3..0] = 0;
IF BL_DST_X_INC15 THEN ---------------------------- R<>CKW<4B>RTS X_INC NEGATIV
IF X_INDEX[]==0 THEN -- ENDE?
ENDMASK2_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); -- JA ENDMASK 3 SETZEN
ELSE
ENDMASK2_SHIFT[7..4] = 0; -- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN
END IF;
IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN -- SCHON ZEILENANFANG?
ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); -- JA ENDMASK 3 SETZEN
ELSE
ENDMASK1_SHIFT[7..4] = 0; -- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN
END IF;
ELSE ------------------------------------------- VORW<52>RTS X_INC POSITIV
IF X_INDEX[]==0 THEN -- ANFANG?
ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); -- JA -> ENDMASK 1 SETZEN
ELSE
ENDMASK1_SHIFT[7..4] = 0; -- NEIN->ENDMASK1 AUF ENDMASK2 SETZEN
END IF;
IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN -- SCHON ZEILENENDE?
ENDMASK2_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); -- JA ENDMASK 3 SETZEN
ELSE
ENDMASK2_SHIFT[7..4] = 0; -- NOCH NICHT AKTIV->ENDMASK 3 AUF ENDMASK2 SETZEN
END IF;
END IF;
-- ENDMASKEN -- barell shifter 144 bit, direction 0 = links 1 = rechts
-- 1234567890123456789012345678
ENDMASK12_IN[] = (BL_ENDMASK1[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
ENDMASK12_OUT[] = lpm_clshift144(ENDMASK12_IN[],1,ENDMASK1_SHIFT[]); -- IMMER rechts SCHIEBEN
ENDMASK23_IN[] = (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK3[]);
ENDMASK23_OUT[] = lpm_clshift144(ENDMASK23_IN[],0,ENDMASK2_SHIFT[]); -- IMMER LINKS SCHIEBEN
ENDMASK123[] = ENDMASK12_OUT[127..0] & ENDMASK23_OUT[143..16];
BLITTER_DOUT[] = ((ENDMASK123[] & OP_OUT[]) # (!ENDMASK123[] & BL_DST_BUFRD[]));
NOT_DST_READ = BL_OP[3..0]==(H"0" # H"3" # H"C" # H"F") & (ENDMASK123[]==-1);
-- STATE MACHINE ****************************************************************************************************
BLITTER_RUN = BLITTER_ON; -- BLITTER IST DA!
DDR_RAM_FREE = BLITTER_DACK[]==H"0"; -- 0 WENN FREI
BLITTER_ADR[3..0] = H"0"; -- IMMER LINE
SRC_DDR_ADR[] = (SRC_ADR_NODE[] - (0,(16 & BL_SRC_X_INC15))); -- WENN R<>CKW<4B>RTS NEXT ADRESS SRC
DST_DDR_ADR[] = (DST_ADR_NODE[] - (0,(16 & BL_DST_X_INC15))); -- WENN R<>CKW<4B>RTS NEXT ADRESS DST
-- BLITTER MAIN STATE MACHINE -----------------------------------------------
BL_SM.CLK = DDRCLK0;
CASE BL_SM IS
WHEN START => ------------------------- START
IF BLITTER_ON & BL_LN7 & ((BL_X_CNT[] - X_CNT_NODE[])>0) & ((BL_Y_CNT[] - Y_INDEX[]) > 0) THEN
BL_SM = NEW_LINE;
ELSE
BL_SM = START;
END IF;
WHEN NEW_LINE => ----------------------- NEU LINIE
X_INDEX_CLR = VCC; -- L<>SCHEN
BL_SM = RDSRC1;
WHEN RDSRC1 => ------------------------ READ SRC1
IF SRC_READ THEN
BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4];
BLITTER_SIG = DDR_RAM_FREE;
BL_READ_SRC = VCC; -- LATCH UND SB1->SB2
IF BLITTER_DACK0 THEN
SIINC = VCC; -- INC SRC ADR
BL_SM = RDSRC2;
ELSE
BL_SM = RDSRC1;
END IF;
ELSE
BL_SM = RDDST;
END IF;
WHEN RDSRC2 => ------------------------ READ SRC2
IF SRC_READ THEN
BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4];
BLITTER_SIG = DDR_RAM_FREE;
BL_READ_SRC = VCC; -- LATCH UND SB1->SB2
IF BLITTER_DACK0 THEN
SIINC = VCC; -- INC SRC ADR
BL_SM = RDDST;
ELSE
BL_SM = RDSRC2;
END IF;
ELSE
BL_SM = RDDST;
END IF;
WHEN RDDST => ----------------------- READ DEST
IF NOT_READ_DST THEN
BL_SM = WRDST;
ELSE
BLITTER_ADR[31..4] = DST_DDR_ADR[31..4];
BLITTER_SIG = DDR_RAM_FREE;
BL_READ_DST = VCC;
IF BLITTER_DACK0 THEN
BL_SM = WRDST;
ELSE
BL_SM = RDDST;
END IF;
END IF;
WHEN WRDST => ------------------- WRITE DEST
BLITTER_ADR[31..4] = DST_DDR_ADR[31..4];
BLITTER_WR = DDR_RAM_FREE;
BLITTER_SIG = DDR_RAM_FREE;
IF BLITTER_DACK0 THEN
XIINC = VCC; -- INC X_INDEX
DIINC = VCC; -- INC DEST ADR
BL_SM = TESTZEILENENDE;
ELSE
BL_SM = WRDST;
END IF;
WHEN TESTZEILENENDE => ----------------- ZEILENDE?
IF BL_X_CNT[]<=(X_CNT_NODE[]) THEN -- SCHON ZEILENENDE?
YIINC = VCC; -- JA -> INC Y-INDEX UND ZEILE SRC UND DEST
BL_SM = TESTFERTIG; -- ->
ELSE
BL_SM = RDSRC2; -- NEIN NEXT
END IF;
WHEN TESTFERTIG => --------------------- TEST AUF FERTIG
ZIINC = VCC; -- INC ADRESSEN ZEILENUMBRUCH
IF Y_INDEX[]>=BL_Y_CNT[] THEN -- LETZTE ZEILE?
BL_SM = FERTIG; -- JA -->
ELSE
ZYINC = VCC; -- YINC ADDIEREN ZEILENENDE
BL_SM = NEW_LINE; -- NEIN NEXT ->
END IF;
WHEN FERTIG => -------------------------- FERTIG
BLITTER_INT = VCC; -- BLITTER INTERRUPT
LN7CLR = VCC; -- BUSY BIT L<>SCHEN
IF BL_LN7==0 THEN -- WARTEN BIS GEL<45>SCHT (GEHT NUR MIT 33MHz)
BL_SM = START;
ELSE
BL_SM = FERTIG;
END IF;
WHEN OTHERS =>
BL_SM = FERTIG;
END CASE;
END;

BIN
FPGA_by_Fredi/blitter.tdf.pdf Normal file
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Binary file not shown.

128
FPGA_by_Fredi/firebee1.asm.rpt Normal file
View File

@@ -0,0 +1,128 @@
Assembler report for firebee1
Thu Apr 13 11:08:24 2017
Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: C:/FireBee/FPGA/firebee1.sof
6. Assembler Device Options: C:/FireBee/FPGA/firebee1.rbf
7. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Thu Apr 13 11:08:24 2017 ;
; Revision Name ; firebee1 ;
; Top-level Entity Name ; firebee1 ;
; Family ; Cyclone III ;
; Device ; EP3C40F484C6 ;
+-----------------------+---------------------------------------+
+----------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+-----------------------------------------------------------------------------+------------+---------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------------+------------+---------------+
; Generate Raw Binary File (.rbf) For Target Device ; On ; Off ;
; Hexadecimal Output File start address ; 0XE0700000 ; 0 ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Generate compressed bitstreams ; On ; On ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; Auto user code ; Off ; Off ;
; Use configuration device ; Off ; Off ;
; Configuration device ; Auto ; Auto ;
; Configuration device auto user code ; Off ; Off ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Release clears before tri-states ; Off ; Off ;
; Auto-restart configuration after error ; On ; On ;
; Enable OCT_DONE ; Off ; Off ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
+-----------------------------------------------------------------------------+------------+---------------+
+------------------------------+
; Assembler Generated Files ;
+------------------------------+
; File Name ;
+------------------------------+
; C:/FireBee/FPGA/firebee1.sof ;
; C:/FireBee/FPGA/firebee1.rbf ;
+------------------------------+
+--------------------------------------------------------+
; Assembler Device Options: C:/FireBee/FPGA/firebee1.sof ;
+----------------+---------------------------------------+
; Option ; Setting ;
+----------------+---------------------------------------+
; Device ; EP3C40F484C6 ;
; JTAG usercode ; 0xFFFFFFFF ;
; Checksum ; 0x01072C3E ;
+----------------+---------------------------------------+
+--------------------------------------------------------+
; Assembler Device Options: C:/FireBee/FPGA/firebee1.rbf ;
+---------------------+----------------------------------+
; Option ; Setting ;
+---------------------+----------------------------------+
; Raw Binary File ; ;
; Compression Ratio ; 2 ;
+---------------------+----------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
Info: Processing started: Thu Apr 13 11:08:20 2017
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 310 megabytes
Info: Processing ended: Thu Apr 13 11:08:24 2017
Info: Elapsed time: 00:00:04
Info: Total CPU time (on all processors): 00:00:05

622
FPGA_by_Fredi/firebee1.bdf
View File

@@ -293,7 +293,7 @@ applicable agreement for further details.
(line (pt 117 12)(pt 121 8)(line_width 1)) (line (pt 117 12)(pt 121 8)(line_width 1))
) )
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 560 1504 648 1536)) (annotation_block (location)(rect 520 1472 608 1504))
) )
(pin (pin
(input) (input)
@@ -2063,6 +2063,23 @@ applicable agreement for further details.
) )
(annotation_block (location)(rect 992 272 1056 288)) (annotation_block (location)(rect 992 272 1056 288))
) )
(pin
(output)
(rect 1848 2128 2024 2144)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "nDREQ0" (rect 90 0 133 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8)(line_width 1))
(line (pt 52 4)(pt 78 4)(line_width 1))
(line (pt 52 12)(pt 78 12)(line_width 1))
(line (pt 52 12)(pt 52 4)(line_width 1))
(line (pt 78 4)(pt 82 8)(line_width 1))
(line (pt 82 8)(pt 78 12)(line_width 1))
(line (pt 78 12)(pt 82 8)(line_width 1))
)
(annotation_block (location)(rect 2024 2112 2072 2128))
)
(pin (pin
(bidir) (bidir)
(rect 1840 1088 2016 1104) (rect 1840 1088 2016 1104)
@@ -2242,7 +2259,7 @@ applicable agreement for further details.
) )
(flipy) (flipy)
(text "VCC" (rect 152 7 172 17)(font "Arial" (font_size 6))) (text "VCC" (rect 152 7 172 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 352 1376 416 1824)) (annotation_block (location)(rect 112 928 176 1376))
) )
(pin (pin
(bidir) (bidir)
@@ -3477,118 +3494,26 @@ applicable agreement for further details.
(line (pt 40 48)(pt 40 168)(line_width 1)) (line (pt 40 48)(pt 40 168)(line_width 1))
) )
) )
(block (symbol
(rect 1264 2944 1672 3560) (rect 840 2872 928 2920)
(text "DSP" (rect 5 5 28 19)(font "Arial" (font_size 8))) (text "Mathias_Alles" (rect 5 602 72 614)(font "Arial" )) (block_io "CLK33M" (input)) (text "FPGA_DATE" (rect 6 1 96 17)(font "Arial" (font_size 10)))
(block_io "MAIN_CLK" (input)) (text "inst26" (rect 8 32 37 44)(font "Arial" ))
(block_io "nFB_OE" (input)) (port
(block_io "nFB_WR" (input)) (pt 88 24)
(block_io "nFB_CS1" (input)) (output)
(block_io "nFB_CS2" (input)) (text "result[31..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(block_io "FB_SIZE0" (input)) (text "result[31..0]" (rect 85 -31 152 -17)(font "Arial" (font_size 8))(invisible))
(block_io "FB_SIZE1" (input)) (line (pt 88 24)(pt 72 24)(line_width 3))
(block_io "nFB_BURST" (input)) )
(block_io "FB_ADR[31..0]" (input)) (drawing
(block_io "nRSTO" (input)) (text "319037463" (rect 27 18 80 30)(font "Arial" ))
(block_io "nFB_CS3" (input)) (text "32" (rect 77 25 88 37)(font "Arial" ))
(block_io "nSRCS" (output)) (line (pt 16 16)(pt 72 16)(line_width 1))
(block_io "nSRBLE" (output)) (line (pt 72 16)(pt 72 32)(line_width 1))
(block_io "nSRBHE" (output)) (line (pt 72 32)(pt 16 32)(line_width 1))
(block_io "nSRWE" (output)) (line (pt 16 32)(pt 16 16)(line_width 1))
(block_io "nSROE" (output)) (line (pt 72 28)(pt 80 20)(line_width 1))
(block_io "DSP_INT" (output)) )
(block_io "DSP_TA" (output))
(block_io "FB_AD[31..0]" (bidir))
(block_io "IO[17..0]" (bidir))
(block_io "SRD[15..0]" (bidir))
(mapper
(pt 408 416)
(bidir)
)
(mapper
(pt 408 392)
(bidir)
)
(mapper
(pt 408 368)
(bidir)
)
(mapper
(pt 408 320)
(bidir)
)
(mapper
(pt 408 440)
(bidir)
)
(mapper
(pt 408 344)
(bidir)
)
(mapper
(pt 408 296)
(bidir)
)
(mapper
(pt 408 40)
(bidir)
)
(mapper
(pt 0 56)
(bidir)
)
(mapper
(pt 0 80)
(bidir)
)
(mapper
(pt 0 104)
(bidir)
)
(mapper
(pt 0 128)
(bidir)
)
(mapper
(pt 0 152)
(bidir)
)
(mapper
(pt 0 176)
(bidir)
)
(mapper
(pt 0 248)
(bidir)
)
(mapper
(pt 0 224)
(bidir)
)
(mapper
(pt 0 272)
(bidir)
)
(mapper
(pt 0 296)
(bidir)
)
(mapper
(pt 408 72)
(bidir)
)
(mapper
(pt 408 576)
(bidir)
)
(mapper
(pt 0 320)
(bidir)
)
(mapper
(pt 0 200)
(bidir)
)
) )
(block (block
(rect 1264 -48 1672 728) (rect 1264 -48 1672 728)
@@ -3631,6 +3556,7 @@ applicable agreement for further details.
(block_io "BA[1..0]" (output)) (block_io "BA[1..0]" (output))
(block_io "VIDEO_RECONFIG" (output)) (block_io "VIDEO_RECONFIG" (output))
(block_io "VR_WR" (output)) (block_io "VR_WR" (output))
(block_io "BLITTER_INT" (output))
(block_io "VDQS[3..0]" (bidir)) (block_io "VDQS[3..0]" (bidir))
(block_io "FB_AD[31..0]" (bidir)) (block_io "FB_AD[31..0]" (bidir))
(block_io "VD[31..0]" (bidir)) (block_io "VD[31..0]" (bidir))
@@ -3802,137 +3728,8 @@ applicable agreement for further details.
(pt 0 512) (pt 0 512)
(bidir) (bidir)
) )
)
(block
(rect 1264 2344 1672 2904)
(text "interrupt_handler" (rect 5 5 101 19)(font "Arial" (font_size 8))) (text "nobody" (rect 5 546 41 558)(font "Arial" )) (block_io "MAIN_CLK" (input))
(block_io "nFB_WR" (input))
(block_io "nFB_CS1" (input))
(block_io "nFB_CS2" (input))
(block_io "FB_SIZE0" (input))
(block_io "FB_SIZE1" (input))
(block_io "FB_ADR[31..0]" (input))
(block_io "PIC_INT" (input))
(block_io "E0_INT" (input))
(block_io "DVI_INT" (input))
(block_io "nPCI_INTA" (input))
(block_io "nPCI_INTB" (input))
(block_io "nPCI_INTC" (input))
(block_io "nPCI_INTD" (input))
(block_io "nMFP_INT" (input))
(block_io "nFB_OE" (input))
(block_io "DSP_INT" (input))
(block_io "VSYNC" (input))
(block_io "HSYNC" (input))
(block_io "DMA_DRQ" (input))
(block_io "nRSTO" (input))
(block_io "nIRQ[7..2]" (output))
(block_io "INT_HANDLER_TA" (output))
(block_io "ACP_CONF[31..0]" (output))
(block_io "TIN0" (output))
(block_io "FB_AD[31..0]" (bidir))
(mapper (mapper
(pt 408 56) (pt 408 704)
(bidir)
)
(mapper
(pt 408 80)
(bidir)
)
(mapper
(pt 0 256)
(bidir)
)
(mapper
(pt 0 280)
(bidir)
)
(mapper
(pt 0 304)
(bidir)
)
(mapper
(pt 0 376)
(bidir)
)
(mapper
(pt 0 400)
(bidir)
)
(mapper
(pt 0 328)
(bidir)
)
(mapper
(pt 0 352)
(bidir)
)
(mapper
(pt 0 432)
(bidir)
)
(mapper
(pt 0 456)
(bidir)
)
(mapper
(pt 0 480)
(bidir)
)
(mapper
(pt 0 504)
(bidir)
)
(mapper
(pt 408 504)
(bidir)
)
(mapper
(pt 0 528)
(bidir)
)
(mapper
(pt 408 240)
(bidir)
)
(mapper
(pt 408 296)
(bidir)
)
(mapper
(pt 0 224)
(bidir)
)
(mapper
(pt 0 104)
(bidir)
)
(mapper
(pt 0 128)
(bidir)
)
(mapper
(pt 0 176)
(bidir)
)
(mapper
(pt 0 200)
(bidir)
)
(mapper
(pt 0 56)
(bidir)
)
(mapper
(pt 0 152)
(bidir)
)
(mapper
(pt 0 80)
(bidir)
)
(mapper
(pt 0 32)
(bidir) (bidir)
) )
) )
@@ -3983,12 +3780,15 @@ applicable agreement for further details.
(block_io "nFB_OE" (input)) (block_io "nFB_OE" (input))
(block_io "VSYNC" (input)) (block_io "VSYNC" (input))
(block_io "HSYNC" (input)) (block_io "HSYNC" (input))
(block_io "DSP_INT" (input))
(block_io "nBLANK" (input)) (block_io "nBLANK" (input))
(block_io "FDC_CLK" (input)) (block_io "FDC_CLK" (input))
(block_io "FB_ALE" (input)) (block_io "FB_ALE" (input))
(block_io "ACP_CONF[31..24]" (input))
(block_io "HD_DD" (input)) (block_io "HD_DD" (input))
(block_io "nFB_CS3" (input))
(block_io "VIDEO_TA" (input))
(block_io "ACP_CONF[31..0]" (input))
(block_io "BLITTER_INT" (input))
(block_io "DSP_INT" (input))
(block_io "nIDE_CS1" (output)) (block_io "nIDE_CS1" (output))
(block_io "nIDE_CS0" (output)) (block_io "nIDE_CS0" (output))
(block_io "LP_STR" (output)) (block_io "LP_STR" (output))
@@ -4361,10 +4161,6 @@ applicable agreement for further details.
(pt 0 176) (pt 0 176)
(bidir) (bidir)
) )
(mapper
(pt 0 1216)
(bidir)
)
(mapper (mapper
(pt 408 48) (pt 408 48)
(bidir) (bidir)
@@ -4449,6 +4245,274 @@ applicable agreement for further details.
(pt 408 1544) (pt 408 1544)
(bidir) (bidir)
) )
(mapper
(pt 0 1408)
(bidir)
)
(mapper
(pt 0 1488)
(bidir)
)
(mapper
(pt 0 1440)
(bidir)
)
(mapper
(pt 0 1464)
(bidir)
)
)
(block
(rect 1264 2944 1672 3560)
(text "DSP" (rect 5 5 28 19)(font "Arial" (font_size 8))) (text "Mathias_Alles" (rect 5 602 72 614)(font "Arial" )) (block_io "CLK33M" (input))
(block_io "MAIN_CLK" (input))
(block_io "nFB_OE" (input))
(block_io "nFB_WR" (input))
(block_io "nFB_CS1" (input))
(block_io "nFB_CS2" (input))
(block_io "FB_SIZE0" (input))
(block_io "FB_SIZE1" (input))
(block_io "nFB_BURST" (input))
(block_io "FB_ADR[31..0]" (input))
(block_io "nRSTO" (input))
(block_io "nFB_CS3" (input))
(block_io "nSRCS" (output))
(block_io "nSRBLE" (output))
(block_io "nSRBHE" (output))
(block_io "nSRWE" (output))
(block_io "nSROE" (output))
(block_io "DSP_INT" (output))
(block_io "DSP_TA" (output))
(block_io "FB_AD[31..0]" (bidir))
(block_io "IO[17..0]" (bidir))
(block_io "SRD[15..0]" (bidir))
(mapper
(pt 408 416)
(bidir)
)
(mapper
(pt 408 392)
(bidir)
)
(mapper
(pt 408 368)
(bidir)
)
(mapper
(pt 408 320)
(bidir)
)
(mapper
(pt 408 440)
(bidir)
)
(mapper
(pt 408 344)
(bidir)
)
(mapper
(pt 408 296)
(bidir)
)
(mapper
(pt 408 40)
(bidir)
)
(mapper
(pt 0 56)
(bidir)
)
(mapper
(pt 0 80)
(bidir)
)
(mapper
(pt 0 104)
(bidir)
)
(mapper
(pt 0 128)
(bidir)
)
(mapper
(pt 0 152)
(bidir)
)
(mapper
(pt 0 176)
(bidir)
)
(mapper
(pt 0 248)
(bidir)
)
(mapper
(pt 0 224)
(bidir)
)
(mapper
(pt 0 272)
(bidir)
)
(mapper
(pt 0 296)
(bidir)
)
(mapper
(pt 408 72)
(bidir)
)
(mapper
(pt 408 576)
(bidir)
)
(mapper
(pt 0 320)
(bidir)
)
(mapper
(pt 0 200)
(bidir)
)
)
(block
(rect 1264 2344 1672 2920)
(text "interrupt_handler" (rect 5 5 101 19)(font "Arial" (font_size 8))) (text "nobody" (rect 5 562 41 574)(font "Arial" )) (block_io "MAIN_CLK" (input))
(block_io "nFB_WR" (input))
(block_io "nFB_CS1" (input))
(block_io "nFB_CS2" (input))
(block_io "FB_SIZE0" (input))
(block_io "FB_SIZE1" (input))
(block_io "FB_ADR[31..0]" (input))
(block_io "PIC_INT" (input))
(block_io "E0_INT" (input))
(block_io "DVI_INT" (input))
(block_io "nPCI_INTA" (input))
(block_io "nPCI_INTB" (input))
(block_io "nPCI_INTC" (input))
(block_io "nPCI_INTD" (input))
(block_io "nMFP_INT" (input))
(block_io "nFB_OE" (input))
(block_io "DSP_INT" (input))
(block_io "VSYNC" (input))
(block_io "HSYNC" (input))
(block_io "DMA_DRQ" (input))
(block_io "nRSTO" (input))
(block_io "VIDEO_TA" (input))
(block_io "FPGA_DATE[31..0]" (input))
(block_io "nIRQ[7..2]" (output))
(block_io "INT_HANDLER_TA" (output))
(block_io "ACP_CONF[31..0]" (output))
(block_io "TIN0" (output))
(block_io "FB_AD[31..0]" (bidir))
(mapper
(pt 408 56)
(bidir)
)
(mapper
(pt 408 80)
(bidir)
)
(mapper
(pt 0 256)
(bidir)
)
(mapper
(pt 0 280)
(bidir)
)
(mapper
(pt 0 304)
(bidir)
)
(mapper
(pt 0 376)
(bidir)
)
(mapper
(pt 0 400)
(bidir)
)
(mapper
(pt 0 328)
(bidir)
)
(mapper
(pt 0 352)
(bidir)
)
(mapper
(pt 0 432)
(bidir)
)
(mapper
(pt 0 456)
(bidir)
)
(mapper
(pt 0 480)
(bidir)
)
(mapper
(pt 0 504)
(bidir)
)
(mapper
(pt 408 504)
(bidir)
)
(mapper
(pt 0 528)
(bidir)
)
(mapper
(pt 408 240)
(bidir)
)
(mapper
(pt 408 296)
(bidir)
)
(mapper
(pt 0 224)
(bidir)
)
(mapper
(pt 0 104)
(bidir)
)
(mapper
(pt 0 128)
(bidir)
)
(mapper
(pt 0 176)
(bidir)
)
(mapper
(pt 0 200)
(bidir)
)
(mapper
(pt 0 56)
(bidir)
)
(mapper
(pt 0 152)
(bidir)
)
(mapper
(pt 0 80)
(bidir)
)
(mapper
(pt 0 32)
(bidir)
)
(mapper
(pt 0 552)
(bidir)
)
) )
(connector (connector
(text "FB_AD[31..0]" (rect 1682 2384 1749 2396)(font "Arial" )) (text "FB_AD[31..0]" (rect 1682 2384 1749 2396)(font "Arial" ))
@@ -5365,11 +5429,6 @@ applicable agreement for further details.
(pt 1264 1984) (pt 1264 1984)
(pt 1144 1984) (pt 1144 1984)
) )
(connector
(text "DSP_INT" (rect 1154 1944 1200 1956)(font "Arial" ))
(pt 1264 1960)
(pt 1144 1960)
)
(connector (connector
(text "DMA_DRQ" (rect 1682 2096 1736 2108)(font "Arial" )) (text "DMA_DRQ" (rect 1682 2096 1736 2108)(font "Arial" ))
(pt 1784 2112) (pt 1784 2112)
@@ -5385,12 +5444,6 @@ applicable agreement for further details.
(pt 1144 2008) (pt 1144 2008)
(pt 1264 2008) (pt 1264 2008)
) )
(connector
(text "ACP_CONF[31..24]" (rect 1146 2064 1243 2076)(font "Arial" ))
(pt 1136 2080)
(pt 1264 2080)
(bus)
)
(connector (connector
(text "LP_STR" (rect 1682 824 1722 836)(font "Arial" )) (text "LP_STR" (rect 1682 824 1722 836)(font "Arial" ))
(pt 1672 840) (pt 1672 840)
@@ -5908,11 +5961,6 @@ applicable agreement for further details.
(pt 1672 2224) (pt 1672 2224)
(pt 1864 2224) (pt 1864 2224)
) )
(connector
(text "nDREQ0" (rect 1674 2120 1717 2132)(font "Arial" ))
(pt 1672 2136)
(pt 1800 2136)
)
(connector (connector
(text "MIDI_OLR" (rect 1682 2272 1733 2284)(font "Arial" )) (text "MIDI_OLR" (rect 1682 2272 1733 2284)(font "Arial" ))
(pt 1672 2288) (pt 1672 2288)
@@ -5990,6 +6038,48 @@ applicable agreement for further details.
(pt 816 280) (pt 816 280)
(pt 712 280) (pt 712 280)
) )
(connector
(text "nFB_CS3" (rect 1162 2136 1209 2148)(font "Arial" ))
(pt 1152 2152)
(pt 1264 2152)
)
(connector
(text "nDREQ0" (rect 1722 2120 1765 2132)(font "Arial" ))
(pt 1672 2136)
(pt 1848 2136)
)
(connector
(text "Video_TA" (rect 1178 2216 1224 2228)(font "Arial" ))
(pt 1168 2232)
(pt 1264 2232)
)
(connector
(text "ACP_CONF[31..0]" (rect 1146 2064 1238 2076)(font "Arial" ))
(pt 1136 2080)
(pt 1264 2080)
(bus)
)
(connector
(text "BLITTER_INT" (rect 1698 640 1765 652)(font "Arial" ))
(pt 1672 656)
(pt 1792 656)
)
(connector
(text "BLITTER_INT" (rect 1154 2168 1221 2180)(font "Arial" ))
(pt 1264 2184)
(pt 1144 2184)
)
(connector
(text "DSP_INT" (rect 1154 2192 1200 2204)(font "Arial" ))
(pt 1264 2208)
(pt 1144 2208)
)
(connector
(text "FPGA_DATE[31..0]" (rect 938 2880 1033 2892)(font "Arial" ))
(pt 928 2896)
(pt 1264 2896)
(bus)
)
(junction (pt 2504 760)) (junction (pt 2504 760))
(junction (pt 1856 -64)) (junction (pt 1856 -64))
(junction (pt 2424 -80)) (junction (pt 2424 -80))

2
FPGA_by_Fredi/firebee1.done
View File

@@ -1 +1 @@
Fri Aug 28 13:39:52 2015 Thu Apr 13 11:08:39 2017

16
FPGA_by_Fredi/firebee1.fit.summary
View File

@@ -1,16 +1,16 @@
Fitter Status : Successful - Fri Aug 28 13:39:32 2015 Fitter Status : Successful - Thu Apr 13 11:08:12 2017
Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
Revision Name : firebee1 Revision Name : firebee1
Top-level Entity Name : firebee1 Top-level Entity Name : firebee1
Family : Cyclone III Family : Cyclone III
Device : EP3C40F484C6 Device : EP3C40F484C6
Timing Models : Final Timing Models : Final
Total logic elements : 10,207 / 39,600 ( 26 % ) Total logic elements : 20,945 / 39,600 ( 53 % )
Total combinational functions : 8,661 / 39,600 ( 22 % ) Total combinational functions : 19,059 / 39,600 ( 48 % )
Dedicated logic registers : 5,025 / 39,600 ( 13 % ) Dedicated logic registers : 5,696 / 39,600 ( 14 % )
Total registers : 5162 Total registers : 5845
Total pins : 295 / 332 ( 89 % ) Total pins : 296 / 332 ( 89 % )
Total virtual pins : 0 Total virtual pins : 0
Total memory bits : 109,600 / 1,161,216 ( 9 % ) Total memory bits : 355,360 / 1,161,216 ( 31 % )
Embedded Multiplier 9-bit elements : 6 / 252 ( 2 % ) Embedded Multiplier 9-bit elements : 12 / 252 ( 5 % )
Total PLLs : 4 / 4 ( 100 % ) Total PLLs : 4 / 4 ( 100 % )

428
FPGA_by_Fredi/firebee1.flow.rpt Normal file
View File

@@ -0,0 +1,428 @@
Flow report for firebee1
Sat Apr 15 23:46:36 2017
Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+----------------------------------------------+
; Flow Status ; Successful - Sat Apr 15 23:46:35 2017 ;
; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
; Revision Name ; firebee1 ;
; Top-level Entity Name ; firebee1 ;
; Family ; Cyclone III ;
; Device ; EP3C40F484C6 ;
; Timing Models ; Final ;
; Met timing requirements ; N/A ;
; Total logic elements ; 22,593 ;
; Total combinational functions ; 19,050 ;
; Dedicated logic registers ; 5,711 ;
; Total registers ; 5839 ;
; Total pins ; 296 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 355,360 ;
; Embedded Multiplier 9-bit elements ; 12 ;
; Total PLLs ; 4 ;
+------------------------------------+----------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 04/15/2017 23:43:13 ;
; Main task ; Compilation ;
; Revision Name ; firebee1 ;
+-------------------+---------------------+
+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-----------------------------------------+------------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-----------------------------------------+------------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 1098263457634.149229259302120 ; -- ; -- ; -- ;
; CYCLONEII_OPTIMIZATION_TECHNIQUE ; Speed ; Balanced ; -- ; -- ;
; FMAX_REQUIREMENT ; 30 ns ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_COUNTER ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_RAM_DP+ ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_RAM_DP+ ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_RAM_DP+ ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_LATCH ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_COMPARE ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_FF ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_FF ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_FF ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTDDIO_BIDIR ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_FIFO+ ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_FIFO+ ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTPLL_RECONFIG ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTSYNCRAM ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_COUNTER ; -- ; -- ; -- ;
; IP_TOOL_NAME ; ALTIOBUF ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_FF ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_CLSHIFT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_CLSHIFT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; MISC_FILE ; C:/firebee/FPGA/firebee1.dpf ; -- ; -- ; -- ;
; MISC_FILE ; C:/FireBee/FPGA/firebee1.dpf ; -- ; -- ; -- ;
; MISC_FILE ; altpll1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; altpll1.inc ; -- ; -- ; -- ;
; MISC_FILE ; altpll1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; altpll1.ppf ; -- ; -- ; -- ;
; MISC_FILE ; altpll2.bsf ; -- ; -- ; -- ;
; MISC_FILE ; altpll2.inc ; -- ; -- ; -- ;
; MISC_FILE ; altpll2.cmp ; -- ; -- ; -- ;
; MISC_FILE ; altpll2.ppf ; -- ; -- ; -- ;
; MISC_FILE ; altpll3.bsf ; -- ; -- ; -- ;
; MISC_FILE ; altpll3.inc ; -- ; -- ; -- ;
; MISC_FILE ; altpll3.cmp ; -- ; -- ; -- ;
; MISC_FILE ; altpll3.ppf ; -- ; -- ; -- ;
; MISC_FILE ; altpll0.bsf ; -- ; -- ; -- ;
; MISC_FILE ; altpll0.inc ; -- ; -- ; -- ;
; MISC_FILE ; altpll0.cmp ; -- ; -- ; -- ;
; MISC_FILE ; altpll0.ppf ; -- ; -- ; -- ;
; MISC_FILE ; lpm_counter0.bsf ; -- ; -- ; -- ;
; MISC_FILE ; lpm_counter0.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg0.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg0.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg0.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/altdpram0.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/altdpram0.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/altdpram0.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_bustri1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_bustri1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/altdpram1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/altdpram1.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/altdpram1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_bustri2.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_bustri2.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_bustri4.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_bustri4.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant0.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant0.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant1.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux0.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux0.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux0.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux1.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux2.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux2.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux2.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant2.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant2.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/altdpram2.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/altdpram2.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/altdpram2.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_bustri6.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_bustri6.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux3.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux3.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux4.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux4.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant3.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant3.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_latch1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_latch1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant4.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant4.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_constant4.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg2.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg2.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_compare1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_compare1.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_compare1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; lpm_bustri_LONG.bsf ; -- ; -- ; -- ;
; MISC_FILE ; lpm_bustri_LONG.inc ; -- ; -- ; -- ;
; MISC_FILE ; lpm_bustri_LONG.cmp ; -- ; -- ; -- ;
; MISC_FILE ; lpm_bustri_BYT.bsf ; -- ; -- ; -- ;
; MISC_FILE ; lpm_bustri_BYT.inc ; -- ; -- ; -- ;
; MISC_FILE ; lpm_bustri_BYT.cmp ; -- ; -- ; -- ;
; MISC_FILE ; lpm_bustri_WORD.bsf ; -- ; -- ; -- ;
; MISC_FILE ; lpm_bustri_WORD.inc ; -- ; -- ; -- ;
; MISC_FILE ; lpm_bustri_WORD.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_ff4.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_ff4.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_ff4.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_ff5.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_ff5.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_ff5.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_ff6.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_ff6.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_ff6.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg3.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg3.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg3.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_bidir0.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_bidir0.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_bidir0.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_bidir0.ppf ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out0.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out0.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out0.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out0.ppf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux5.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux5.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux5.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg5.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg5.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg5.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg6.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg6.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg6.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg4.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg4.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_shiftreg4.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out1.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out1.ppf ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out2.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out2.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out2.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/altddio_out2.ppf ; -- ; -- ; -- ;
; MISC_FILE ; altddio_out3.bsf ; -- ; -- ; -- ;
; MISC_FILE ; altddio_out3.inc ; -- ; -- ; -- ;
; MISC_FILE ; altddio_out3.cmp ; -- ; -- ; -- ;
; MISC_FILE ; altddio_out3.ppf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux6.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux6.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_mux6.cmp ; -- ; -- ; -- ;
; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo0.bsf ; -- ; -- ; -- ;
; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo0.cmp ; -- ; -- ; -- ;
; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_muxDZ.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_muxDZ.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_muxVDM.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_muxVDM.cmp ; -- ; -- ; -- ;
; MISC_FILE ; altpll_reconfig1.tdf ; -- ; -- ; -- ;
; MISC_FILE ; altpll_reconfig1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; altpll_reconfig1.inc ; -- ; -- ; -- ;
; MISC_FILE ; altpll_reconfig1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; altpll4.tdf ; -- ; -- ; -- ;
; MISC_FILE ; altpll4.bsf ; -- ; -- ; -- ;
; MISC_FILE ; altpll4.inc ; -- ; -- ; -- ;
; MISC_FILE ; altpll4.cmp ; -- ; -- ; -- ;
; MISC_FILE ; altpll4.ppf ; -- ; -- ; -- ;
; MISC_FILE ; lpm_mux0.tdf ; -- ; -- ; -- ;
; MISC_FILE ; lpm_mux0.bsf ; -- ; -- ; -- ;
; MISC_FILE ; lpm_mux0.inc ; -- ; -- ; -- ;
; MISC_FILE ; lpm_mux0.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/BLITTER/altsyncram0.tdf ; -- ; -- ; -- ;
; MISC_FILE ; Video/BLITTER/altsyncram0.inc ; -- ; -- ; -- ;
; MISC_FILE ; lpm_shiftreg0.tdf ; -- ; -- ; -- ;
; MISC_FILE ; lpm_shiftreg0.bsf ; -- ; -- ; -- ;
; MISC_FILE ; lpm_shiftreg0.inc ; -- ; -- ; -- ;
; MISC_FILE ; lpm_shiftreg0.cmp ; -- ; -- ; -- ;
; MISC_FILE ; lpm_counter1.tdf ; -- ; -- ; -- ;
; MISC_FILE ; lpm_counter1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; lpm_counter1.inc ; -- ; -- ; -- ;
; MISC_FILE ; lpm_counter1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; altiobuf_bidir0.tdf ; -- ; -- ; -- ;
; MISC_FILE ; altiobuf_bidir0.bsf ; -- ; -- ; -- ;
; MISC_FILE ; altiobuf_bidir0.inc ; -- ; -- ; -- ;
; MISC_FILE ; altiobuf_bidir0.cmp ; -- ; -- ; -- ;
; MISC_FILE ; lpm_mux1.tdf ; -- ; -- ; -- ;
; MISC_FILE ; lpm_mux1.bsf ; -- ; -- ; -- ;
; MISC_FILE ; lpm_mux1.inc ; -- ; -- ; -- ;
; MISC_FILE ; lpm_mux1.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_blitter.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_blitter.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/lpm_blitter.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/BLITTER/lpm_clshift384.tdf ; -- ; -- ; -- ;
; MISC_FILE ; Video/BLITTER/lpm_clshift384.inc ; -- ; -- ; -- ;
; MISC_FILE ; Video/BLITTER/lpm_clshift384.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Video/BLITTER/lpm_clshift144.tdf ; -- ; -- ; -- ;
; MISC_FILE ; Video/BLITTER/lpm_clshift144.inc ; -- ; -- ; -- ;
; MISC_FILE ; FPGA_DATE.tdf ; -- ; -- ; -- ;
; MISC_FILE ; FPGA_DATE.bsf ; -- ; -- ; -- ;
; MISC_FILE ; FPGA_DATE.inc ; -- ; -- ; -- ;
; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; PHYSICAL_SYNTHESIS_COMBO_LOGIC ; On ; Off ; -- ; -- ;
; PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ; On ; Off ; -- ; -- ;
; PHYSICAL_SYNTHESIS_EFFORT ; Fast ; Normal ; -- ; -- ;
; PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ; On ; Off ; -- ; -- ;
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ;
; POWER_USE_TA_VALUE ; 35 ; 25 ; -- ; -- ;
; STATE_MACHINE_PROCESSING ; One-Hot ; Auto ; -- ; -- ;
; TCO_REQUIREMENT ; 1 ns ; -- ; -- ; -- ;
; TH_REQUIREMENT ; 1 ns ; -- ; -- ; -- ;
; TPD_REQUIREMENT ; 1 ns ; -- ; -- ; -- ;
; TSU_REQUIREMENT ; 1 ns ; -- ; -- ; -- ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
; USE_TIMEQUEST_TIMING_ANALYZER ; Off ; On ; -- ; -- ;
+-----------------------------------------+------------------------------------+---------------+-------------+----------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:03:20 ; 1.0 ; 355 MB ; 00:03:21 ;
; Total ; 00:03:20 ; -- ; -- ; 00:03:21 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
+---------------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+------------------+---------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+------------------+---------------+------------+----------------+
; Analysis & Synthesis ; Vaio ; Windows Vista ; 6.1 ; x86_64 ;
+----------------------+------------------+---------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off firebeei1 -c firebee1

16
FPGA_by_Fredi/firebee1.map.summary
View File

@@ -1,14 +1,14 @@
Analysis & Synthesis Status : Successful - Fri Aug 28 13:35:56 2015 Analysis & Synthesis Status : Successful - Sat Apr 15 23:46:35 2017
Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
Revision Name : firebee1 Revision Name : firebee1
Top-level Entity Name : firebee1 Top-level Entity Name : firebee1
Family : Cyclone III Family : Cyclone III
Total logic elements : 11,642 Total logic elements : 22,593
Total combinational functions : 8,656 Total combinational functions : 19,050
Dedicated logic registers : 5,028 Dedicated logic registers : 5,711
Total registers : 5156 Total registers : 5839
Total pins : 295 Total pins : 296
Total virtual pins : 0 Total virtual pins : 0
Total memory bits : 109,600 Total memory bits : 355,360
Embedded Multiplier 9-bit elements : 6 Embedded Multiplier 9-bit elements : 12
Total PLLs : 4 Total PLLs : 4

2
FPGA_by_Fredi/firebee1.pin
View File

@@ -490,7 +490,7 @@ VDM[2] : U20 : output : 2.5 V :
VD[7] : U21 : bidir : 2.5 V : : 5 : Y VD[7] : U21 : bidir : 2.5 V : : 5 : Y
VDQS[2] : U22 : bidir : 2.5 V : : 5 : Y VDQS[2] : U22 : bidir : 2.5 V : : 5 : Y
nPD_VGA : V1 : output : 3.3-V LVTTL : : 2 : Y nPD_VGA : V1 : output : 3.3-V LVTTL : : 2 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 : nDREQ0 : V2 : output : 3.3-V LVTTL : : 2 : Y
nPCI_INTC : V3 : input : 3.3-V LVTTL : : 2 : Y nPCI_INTC : V3 : input : 3.3-V LVTTL : : 2 : Y
nPCI_INTB : V4 : input : 3.3-V LVTTL : : 2 : Y nPCI_INTB : V4 : input : 3.3-V LVTTL : : 2 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 : RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 :

183
FPGA_by_Fredi/firebee1.qsf
View File

@@ -567,8 +567,93 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf" set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf"
set_location_assignment PIN_E5 -to LPDIR set_location_assignment PIN_E5 -to LPDIR
set_location_assignment PIN_B11 -to nRSTO_MCF set_location_assignment PIN_B11 -to nRSTO_MCF
set_global_assignment -name SOURCE_FILE Video/BLITTER/lpm_clshift0.cmp set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT
set_global_assignment -name AHDL_FILE Video/BLITTER/lpm_clshift0.tdf set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD
set_location_assignment PIN_AB12 -to CLK33MDIR
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_location_assignment PIN_E12 -to MIDI_IN_PIN
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN
set_instance_assignment -name PCI_IO ON -to nPCI_INTA
set_instance_assignment -name PCI_IO ON -to nPCI_INTB
set_instance_assignment -name PCI_IO ON -to nPCI_INTC
set_instance_assignment -name PCI_IO ON -to nPCI_INTD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2]
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4]
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4]
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5]
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3]
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2]
set_global_assignment -name POWER_USE_TA_VALUE 35
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX
set_location_assignment PIN_V2 -to nDREQ0
set_global_assignment -name AHDL_FILE Video/BLITTER/lpm_clshift144.tdf
set_global_assignment -name SOURCE_FILE Video/BLITTER/altsyncram0.cmp set_global_assignment -name SOURCE_FILE Video/BLITTER/altsyncram0.cmp
set_global_assignment -name AHDL_FILE Video/BLITTER/altsyncram0.tdf set_global_assignment -name AHDL_FILE Video/BLITTER/altsyncram0.tdf
set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp
@@ -738,95 +823,15 @@ set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt
set_global_assignment -name QIP_FILE altpll_reconfig1.qip set_global_assignment -name QIP_FILE altpll_reconfig1.qip
set_global_assignment -name QIP_FILE altpll4.qip set_global_assignment -name QIP_FILE altpll4.qip
set_global_assignment -name QIP_FILE lpm_mux0.qip set_global_assignment -name QIP_FILE lpm_mux0.qip
set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip
set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT
set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD
set_location_assignment PIN_AB12 -to CLK33MDIR
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name QIP_FILE lpm_shiftreg0.qip set_global_assignment -name QIP_FILE lpm_shiftreg0.qip
set_global_assignment -name QIP_FILE lpm_counter1.qip set_global_assignment -name QIP_FILE lpm_counter1.qip
set_global_assignment -name QIP_FILE altiobuf_bidir0.qip set_global_assignment -name QIP_FILE altiobuf_bidir0.qip
set_location_assignment PIN_E12 -to MIDI_IN_PIN set_global_assignment -name QIP_FILE lpm_mux1.qip
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN set_global_assignment -name QIP_FILE Video/lpm_blitter.qip
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN set_global_assignment -name AHDL_FILE Video/BLITTER/lpm_clshift384.tdf
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN set_global_assignment -name INCLUDE_FILE Video/BLITTER/lpm_clshift383.inc
set_instance_assignment -name PCI_IO ON -to nPCI_INTA set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift384.qip
set_instance_assignment -name PCI_IO ON -to nPCI_INTB set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift144.qip
set_instance_assignment -name PCI_IO ON -to nPCI_INTC set_global_assignment -name QIP_FILE FPGA_DATE.qip
set_instance_assignment -name PCI_IO ON -to nPCI_INTD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2]
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4]
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4]
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5]
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3]
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2]
set_global_assignment -name POWER_USE_TA_VALUE 35
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

247
FPGA_by_Fredi/firebee1.sim.rpt Normal file
View File

@@ -0,0 +1,247 @@
Simulator report for firebee1
Fri Mar 10 13:17:46 2017
Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Simulator Summary
3. Simulator Settings
4. Simulation Waveforms
5. |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ALTSYNCRAM
6. |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM
7. |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM
8. |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM
9. |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ALTSYNCRAM
10. |firebee1|Video:Fredi_Aschwanden|BLITTER:BLITTER|altsyncram0:$00000|altsyncram:altsyncram_component|altsyncram_3on1:auto_generated|ALTSYNCRAM
11. |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM
12. |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM
13. |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM
14. |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM
15. |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM
16. |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM
17. |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated|ALTSYNCRAM
18. |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ALTSYNCRAM
19. |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ALTSYNCRAM
20. Coverage Summary
21. Complete 1/0-Value Coverage
22. Missing 1-Value Coverage
23. Missing 0-Value Coverage
24. Simulator INI Usage
25. Simulator Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------+
; Simulator Summary ;
+------+------------+
; Type ; Value ;
+------+------------+
+---------------------------------------------------------------------------------------------------------------------------+
; Simulator Settings ;
+--------------------------------------------------------------------------------------------+--------------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------------------------------+--------------+---------------+
; Simulation mode ; Timing ; Timing ;
; Start time ; 0 ns ; 0 ns ;
; End time ; 2 us ; ;
; Simulation results format ; CVWF ; ;
; Vector input source ; firebee1.vwf ; ;
; Add pins automatically to simulation output waveforms ; Off ; On ;
; Check outputs ; Off ; Off ;
; Report simulation coverage ; On ; On ;
; Display complete 1/0 value coverage report ; On ; On ;
; Display missing 1-value coverage report ; On ; On ;
; Display missing 0-value coverage report ; On ; On ;
; Detect setup and hold time violations ; Off ; Off ;
; Detect glitches ; Off ; Off ;
; Disable timing delays in Timing Simulation ; Off ; Off ;
; Generate Signal Activity File ; Off ; Off ;
; Generate VCD File for PowerPlay Power Analyzer ; Off ; Off ;
; Group bus channels in simulation results ; Off ; Off ;
; Preserve fewer signal transitions to reduce memory requirements ; On ; On ;
; Trigger vector comparison with the specified mode ; INPUT_EDGE ; INPUT_EDGE ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ; Off ;
; Overwrite Waveform Inputs With Simulation Outputs ; Off ; ;
; Perform Glitch Filtering in Timing Simulation ; Auto ; Auto ;
; Interconnect Delay Model Type ; Transport ; Transport ;
; Cell Delay Model Type ; Transport ; Transport ;
+--------------------------------------------------------------------------------------------+--------------+---------------+
+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ALTSYNCRAM ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+-----------------------------------------------------------------------------------------------------------------------------------+
; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ;
+-----------------------------------------------------------------------------------------------------------------------------------+
Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+------------------------------------------------------------------------------------------------------------------------------------+
; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ;
+------------------------------------------------------------------------------------------------------------------------------------+
Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+-------------------------------------------------------------------------------------------------------------------------------------+
; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ;
+-------------------------------------------------------------------------------------------------------------------------------------+
Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ALTSYNCRAM ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+-----------------------------------------------------------------------------------------------------------------------------------------------+
; |firebee1|Video:Fredi_Aschwanden|BLITTER:BLITTER|altsyncram0:$00000|altsyncram:altsyncram_component|altsyncram_3on1:auto_generated|ALTSYNCRAM ;
+-----------------------------------------------------------------------------------------------------------------------------------------------+
Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+----------------------------------------------------------------------------------------------------------------------------------------+
; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ;
+----------------------------------------------------------------------------------------------------------------------------------------+
Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+---------------------------------------------------------------------------------------------------------------------------------------+
; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ;
+---------------------------------------------------------------------------------------------------------------------------------------+
Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+--------------------------------------------------------------------------------------------------------------------------------------+
; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ;
+--------------------------------------------------------------------------------------------------------------------------------------+
Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+----------------------------------------------------------------------------------------------------------------------------------+
; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ;
+----------------------------------------------------------------------------------------------------------------------------------+
Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+-------------------------------------------------------------------------------------------------------------------------------------+
; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ;
+-------------------------------------------------------------------------------------------------------------------------------------+
Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+-----------------------------------------------------------------------------------------------------------------------------------+
; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ;
+-----------------------------------------------------------------------------------------------------------------------------------+
Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated|ALTSYNCRAM ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+-------------------------------------------------------------------------------------------------------------------------------------------+
; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ALTSYNCRAM ;
+-------------------------------------------------------------------------------------------------------------------------------------------+
Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ALTSYNCRAM ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+------------------+
; Coverage Summary ;
+------+-----------+
; Type ; Value ;
+------+-----------+
The following table displays output ports that toggle between 1 and 0 during simulation.
+-------------------------------------------------+
; Complete 1/0-Value Coverage ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------+
; Missing 1-Value Coverage ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+-------------------------------------------------+
; Missing 0-Value Coverage ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
Info: Processing started: Fri Mar 10 13:17:43 2017
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off firebeei1 -c firebee1
Info: Can't find specified vector source file "C:/FireBee/FPGA/firebee1.vwf"
Warning: Can't display state machine states -- register holding state machine bit "|firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.A_00" was synthesized away
Error: No valid vector source file specified and default file "C:/FireBee/FPGA/firebee1.cvwf" does not exist
Error: Quartus II Simulator was unsuccessful. 1 error, 1 warning
Error: Peak virtual memory: 241 megabytes
Error: Processing ended: Fri Mar 10 13:17:46 2017
Error: Elapsed time: 00:00:03
Error: Total CPU time (on all processors): 00:00:03

214
FPGA_by_Fredi/firebee1.tan.summary
View File

@@ -3,170 +3,180 @@ Timing Analyzer Summary
-------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------
Type : Worst-case tsu Type : Worst-case tsu
Slack : -10.339 ns Slack : -10.689 ns
Required Time : 1.000 ns Required Time : 1.000 ns
Actual Time : 11.339 ns Actual Time : 11.689 ns
From : FB_SIZE1 From : nFB_CS1
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[2] To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|SER[2]
From Clock : -- From Clock : --
To Clock : MAIN_CLK To Clock : MAIN_CLK
Failed Paths : 10192 Failed Paths : 9930
Type : Worst-case tco Type : Worst-case tco
Slack : -14.371 ns Slack : -14.089 ns
Required Time : 1.000 ns Required Time : 1.000 ns
Actual Time : 15.371 ns Actual Time : 15.089 ns
From : interrupt_handler:nobody|RTC_ADR[0] From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]
To : FB_AD[18] To : FB_AD[27]
From Clock : MAIN_CLK From Clock : MAIN_CLK
To Clock : -- To Clock : --
Failed Paths : 5354 Failed Paths : 7401
Type : Worst-case tpd Type : Worst-case tpd
Slack : -13.264 ns Slack : -14.015 ns
Required Time : 1.000 ns Required Time : 1.000 ns
Actual Time : 14.264 ns Actual Time : 15.015 ns
From : nFB_CS1 From : nFB_CS1
To : FB_AD[18] To : FB_AD[27]
From Clock : -- From Clock : --
To Clock : -- To Clock : --
Failed Paths : 538 Failed Paths : 546
Type : Worst-case th Type : Worst-case th
Slack : -0.110 ns Slack : -0.258 ns
Required Time : 1.000 ns Required Time : 1.000 ns
Actual Time : 1.110 ns Actual Time : 1.258 ns
From : VD[31] From : FB_AD[20]
To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31] To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0~porta_datain_reg0
From Clock : -- From Clock : --
To Clock : MAIN_CLK To Clock : MAIN_CLK
Failed Paths : 2 Failed Paths : 16
Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
Slack : -17.845 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|BLITTER:BLITTER|BL_DST_ADR[0]
To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO
From Clock : MAIN_CLK
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
Failed Paths : 29183
Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
Slack : -11.412 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|BLITTER:BLITTER|BL_DST_ADR[0]
To : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[4]
From Clock : MAIN_CLK
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
Failed Paths : 25165
Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]' Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]'
Slack : -7.918 ns Slack : -6.848 ns
Required Time : 25.00 MHz ( period = 39.999 ns ) Required Time : 25.00 MHz ( period = 39.999 ns )
Actual Time : N/A Actual Time : N/A
From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6] From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]
To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI
From Clock : MAIN_CLK From Clock : MAIN_CLK
To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0] To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
Failed Paths : 4748 Failed Paths : 5329
Type : Clock Setup: 'MAIN_CLK'
Slack : -6.482 ns
Required Time : 33.00 MHz ( period = 30.303 ns )
Actual Time : N/A
From : FB_ALE
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CMD_STATE.T8
From Clock : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[0]
To Clock : MAIN_CLK
Failed Paths : 43303
Type : Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' Type : Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
Slack : -6.799 ns Slack : -6.153 ns
Required Time : 96.01 MHz ( period = 10.416 ns ) Required Time : 96.01 MHz ( period = 10.416 ns )
Actual Time : N/A Actual Time : N/A
From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6] From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]
To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI
From Clock : MAIN_CLK From Clock : MAIN_CLK
To Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] To Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
Failed Paths : 4694 Failed Paths : 5302
Type : Clock Setup: 'MAIN_CLK'
Slack : -5.955 ns
Required Time : 33.00 MHz ( period = 30.303 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|nBLANK
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[3]
From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
To Clock : MAIN_CLK
Failed Paths : 41276
Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
Slack : -5.567 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO
To : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLR_FIFO_SYNC
From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
Failed Paths : 129
Type : Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]' Type : Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]'
Slack : -4.614 ns Slack : -4.613 ns
Required Time : 16.00 MHz ( period = 62.499 ns ) Required Time : 16.00 MHz ( period = 62.499 ns )
Actual Time : N/A Actual Time : N/A
From : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] From : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16]
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[4] To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|SER[2]
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
To Clock : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1] To Clock : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
Failed Paths : 2882 Failed Paths : 2876
Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
Slack : -3.520 ns Slack : -3.386 ns
Required Time : 66.00 MHz ( period = 15.151 ns ) Required Time : 66.00 MHz ( period = 15.151 ns )
Actual Time : N/A Actual Time : N/A
From : FB_ALE From : FB_ALE
To : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] To : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14]
From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0] From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
Failed Paths : 29 Failed Paths : 33
Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
Slack : 2.410 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR
To : Video:Fredi_Aschwanden|inst90~_Duplicate_2
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
Failed Paths : 0
Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
Slack : 2.966 ns Slack : 2.966 ns
Required Time : 132.01 MHz ( period = 7.575 ns ) Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : Restricted to 500.00 MHz ( period = 2.000 ns ) Actual Time : Restricted to 500.00 MHz ( period = 2.000 ns )
From : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29] From : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8]
To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29] To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8]
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
Failed Paths : 0 Failed Paths : 0
Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
Slack : 5.144 ns Slack : 5.489 ns
Required Time : 132.01 MHz ( period = 7.575 ns ) Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A Actual Time : N/A
From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4] From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]
To : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4] To : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
Failed Paths : 0 Failed Paths : 0
Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]' Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]'
Slack : 26.171 ns Slack : 27.221 ns
Required Time : 0.50 MHz ( period = 1999.998 ns ) Required Time : 0.50 MHz ( period = 1999.998 ns )
Actual Time : N/A Actual Time : N/A
From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[0] From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE.PARITY
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_TX To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_TX
From Clock : MAIN_CLK From Clock : MAIN_CLK
To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2] To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]
Failed Paths : 0 Failed Paths : 0
Type : Clock Hold: 'MAIN_CLK' Type : Clock Hold: 'MAIN_CLK'
Slack : -3.299 ns Slack : -4.871 ns
Required Time : 33.00 MHz ( period = 30.303 ns ) Required Time : 33.00 MHz ( period = 30.303 ns )
Actual Time : N/A Actual Time : N/A
From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6] From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4]
To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[2] To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[4]
From Clock : MAIN_CLK From Clock : MAIN_CLK
To Clock : MAIN_CLK To Clock : MAIN_CLK
Failed Paths : 529 Failed Paths : 764
Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]' Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]'
Slack : -0.640 ns Slack : -0.116 ns
Required Time : 25.00 MHz ( period = 39.999 ns ) Required Time : 25.00 MHz ( period = 39.999 ns )
Actual Time : N/A Actual Time : N/A
From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
To : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] To : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0] From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0] To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
Failed Paths : 33 Failed Paths : 136
Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
Slack : 0.491 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_bqh1:auto_generated|a_graycounter_pjc:wrptr_gp|counter11a[0]
To : Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_bqh1:auto_generated|altsyncram_fo31:fifo_ram|ram_block12a79~porta_address_reg0
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
Failed Paths : 0
Type : Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]' Type : Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]'
Slack : 0.453 ns Slack : 0.500 ns
Required Time : 16.00 MHz ( period = 62.499 ns ) Required Time : 16.00 MHz ( period = 62.499 ns )
Actual Time : N/A Actual Time : N/A
From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[6] From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[8]
To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_address_reg0 To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_address_reg0
From Clock : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1] From Clock : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
To Clock : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1] To Clock : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
@@ -182,28 +192,28 @@ From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generat
To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2] To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]
Failed Paths : 0 Failed Paths : 0
Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
Slack : 0.502 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]
To : Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
Failed Paths : 0
Type : Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' Type : Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
Slack : 0.502 ns Slack : 0.502 ns
Required Time : 96.01 MHz ( period = 10.416 ns ) Required Time : 96.01 MHz ( period = 10.416 ns )
Actual Time : N/A Actual Time : N/A
From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
To : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] To : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
From Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] From Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
To Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] To Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
Failed Paths : 0 Failed Paths : 0
Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
Slack : 1.812 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4]
To : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4]
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
Failed Paths : 0
Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
Slack : 1.775 ns Slack : 2.489 ns
Required Time : 66.00 MHz ( period = 15.151 ns ) Required Time : 66.00 MHz ( period = 15.151 ns )
Actual Time : N/A Actual Time : N/A
From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ
@@ -212,22 +222,12 @@ From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generat
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
Failed Paths : 0 Failed Paths : 0
Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
Slack : 1.829 ns
Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A
From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7]
To : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7]
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
Failed Paths : 0
Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
Slack : 2.585 ns Slack : 3.193 ns
Required Time : 132.01 MHz ( period = 7.575 ns ) Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A Actual Time : N/A
From : Video:Fredi_Aschwanden|inst90~_Duplicate_4 From : Video:Fredi_Aschwanden|inst90~_Duplicate_4
To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
Failed Paths : 0 Failed Paths : 0
@@ -236,8 +236,8 @@ Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2
Slack : 4.335 ns Slack : 4.335 ns
Required Time : 132.01 MHz ( period = 7.575 ns ) Required Time : 132.01 MHz ( period = 7.575 ns )
Actual Time : N/A Actual Time : N/A
From : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12] From : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16]
To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12] To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16]
From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
Failed Paths : 0 Failed Paths : 0
@@ -250,7 +250,7 @@ From :
To : To :
From Clock : From Clock :
To Clock : To Clock :
Failed Paths : 70406 Failed Paths : 129984
-------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------

16
FPGA_by_Fredi/firebeei1.qws Normal file
View File

@@ -0,0 +1,16 @@
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
ptn_Child3=Document-2
[ProjectWorkspace.Frames.ChildFrames.Document-0]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
DocPathName=firebee1.bdf
DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
IsChildFrameDetached=False
IsActiveChildFrame=False
ptn_Child1=StateMap

11
FPGA_by_Fredi/incremental_db/README
View File

@@ -1,11 +0,0 @@
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.

BIN
FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.cdb
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BIN
FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.dfp
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BIN
FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.hdb
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BIN
FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.kpt
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5
FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.logdb
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@@ -1,5 +0,0 @@
v1
DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12|mult_aat:auto_generated|mac_out2,
DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6|mult_aat:auto_generated|mac_out2,
DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated|mac_out2,
PORT_SWAPPING,PORT_SWAPPING_FINISHED,Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated|mac_mult1,

BIN
FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.rcfdb
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BIN
FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.re.rcfdb
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BIN
FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.map.cdb
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BIN
FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.map.dpi
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BIN
FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.map.hdb
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BIN
FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.map.kpt
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BIN
FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.merge_hb.atm
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BIN
FPGA_by_Fredi/lpm_counter0_wave0.jpg
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Width:  |  Height:  |  Size: 55 KiB

13
FPGA_by_Fredi/lpm_counter0_waveforms.html
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@@ -1,13 +0,0 @@
<html>
<head>
<title>Sample Waveforms for lpm_counter0.vhd </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file lpm_counter0.vhd </CENTER></h2>
<P>The following waveforms show the behavior of lpm_counter megafunction for the chosen set of parameters in design lpm_counter0.vhd. The design lpm_counter0.vhd is a 18 bit up counter. </P>
<CENTER><img src=lpm_counter0_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing counter operation. </CENTER></P>
<P><FONT size=3></P>
<P></P>
</body>
</html>

185
FPGA_by_Fredi/lpm_mux0.s19 Normal file
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@@ -0,0 +1,185 @@
S12300002D2D436F707972696768742028432920313939312D3230313020416C74657261DB
S123002020436F72706F726174696F6E0D0A2D2D596F757220757365206F6620416C746527
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S9030000FC

1838
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@@ -0,0 +1,278 @@
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_mux1
PORT
(
data0x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data100x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data101x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data102x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data103x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data104x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data105x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data106x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data107x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data108x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data109x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data10x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data110x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data111x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data112x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data113x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data114x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data115x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data116x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data117x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data118x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data119x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data11x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data120x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data121x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data122x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data123x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data124x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data125x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data126x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data127x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data128x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data129x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data12x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data130x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data131x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data132x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data133x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data134x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data135x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data136x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data137x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data138x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data139x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data13x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data140x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data141x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data142x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data143x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data144x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data145x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data146x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data147x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data148x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data149x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data14x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data150x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data151x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data152x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data153x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data154x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data155x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data156x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data157x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data158x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data159x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data15x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data160x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data161x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data162x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data163x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data164x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data165x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data166x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data167x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data168x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data169x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data16x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data170x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data171x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data172x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data173x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data174x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data175x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data176x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data177x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data178x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data179x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data17x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data180x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data181x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data182x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data183x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data184x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data185x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data186x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data187x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data188x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data189x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data18x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data190x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data191x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data192x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data193x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data194x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data195x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data196x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data197x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data198x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data199x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data19x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data200x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data201x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data202x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data203x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data204x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data205x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data206x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data207x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data208x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data209x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data20x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data210x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data211x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data212x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data213x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data214x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data215x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data216x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data217x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data218x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data219x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data21x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data220x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data221x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data222x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data223x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data224x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data225x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data226x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data227x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data228x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data229x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data22x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data230x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data231x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data232x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data233x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data234x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data235x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data236x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data237x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data238x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data239x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data23x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data240x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data241x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data242x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data243x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data244x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data245x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data246x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data247x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data248x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data249x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data24x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data250x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data251x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data252x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data253x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data254x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data255x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data25x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data26x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data27x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data28x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data29x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data2x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data30x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data31x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data32x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data33x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data34x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data35x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data36x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data37x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data38x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data39x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data3x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data40x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data41x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data42x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data43x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data44x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data45x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data46x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data47x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data48x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data49x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data4x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data50x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data51x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data52x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data53x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data54x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data55x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data56x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data57x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data58x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data59x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data5x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data60x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data61x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data62x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data63x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data64x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data65x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data66x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data67x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data68x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data69x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data6x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data70x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data71x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data72x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data73x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data74x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data75x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data76x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data77x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data78x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data79x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data7x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data80x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data81x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data82x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data83x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data84x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data85x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data86x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data87x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data88x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data89x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data8x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data90x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data91x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data92x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data93x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data94x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data95x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data96x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data97x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data98x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data99x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
data9x : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
);
end component;

279
FPGA_by_Fredi/lpm_mux1.inc Normal file
View File

@@ -0,0 +1,279 @@
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION lpm_mux1
(
data0x[127..0],
data100x[127..0],
data101x[127..0],
data102x[127..0],
data103x[127..0],
data104x[127..0],
data105x[127..0],
data106x[127..0],
data107x[127..0],
data108x[127..0],
data109x[127..0],
data10x[127..0],
data110x[127..0],
data111x[127..0],
data112x[127..0],
data113x[127..0],
data114x[127..0],
data115x[127..0],
data116x[127..0],
data117x[127..0],
data118x[127..0],
data119x[127..0],
data11x[127..0],
data120x[127..0],
data121x[127..0],
data122x[127..0],
data123x[127..0],
data124x[127..0],
data125x[127..0],
data126x[127..0],
data127x[127..0],
data128x[127..0],
data129x[127..0],
data12x[127..0],
data130x[127..0],
data131x[127..0],
data132x[127..0],
data133x[127..0],
data134x[127..0],
data135x[127..0],
data136x[127..0],
data137x[127..0],
data138x[127..0],
data139x[127..0],
data13x[127..0],
data140x[127..0],
data141x[127..0],
data142x[127..0],
data143x[127..0],
data144x[127..0],
data145x[127..0],
data146x[127..0],
data147x[127..0],
data148x[127..0],
data149x[127..0],
data14x[127..0],
data150x[127..0],
data151x[127..0],
data152x[127..0],
data153x[127..0],
data154x[127..0],
data155x[127..0],
data156x[127..0],
data157x[127..0],
data158x[127..0],
data159x[127..0],
data15x[127..0],
data160x[127..0],
data161x[127..0],
data162x[127..0],
data163x[127..0],
data164x[127..0],
data165x[127..0],
data166x[127..0],
data167x[127..0],
data168x[127..0],
data169x[127..0],
data16x[127..0],
data170x[127..0],
data171x[127..0],
data172x[127..0],
data173x[127..0],
data174x[127..0],
data175x[127..0],
data176x[127..0],
data177x[127..0],
data178x[127..0],
data179x[127..0],
data17x[127..0],
data180x[127..0],
data181x[127..0],
data182x[127..0],
data183x[127..0],
data184x[127..0],
data185x[127..0],
data186x[127..0],
data187x[127..0],
data188x[127..0],
data189x[127..0],
data18x[127..0],
data190x[127..0],
data191x[127..0],
data192x[127..0],
data193x[127..0],
data194x[127..0],
data195x[127..0],
data196x[127..0],
data197x[127..0],
data198x[127..0],
data199x[127..0],
data19x[127..0],
data1x[127..0],
data200x[127..0],
data201x[127..0],
data202x[127..0],
data203x[127..0],
data204x[127..0],
data205x[127..0],
data206x[127..0],
data207x[127..0],
data208x[127..0],
data209x[127..0],
data20x[127..0],
data210x[127..0],
data211x[127..0],
data212x[127..0],
data213x[127..0],
data214x[127..0],
data215x[127..0],
data216x[127..0],
data217x[127..0],
data218x[127..0],
data219x[127..0],
data21x[127..0],
data220x[127..0],
data221x[127..0],
data222x[127..0],
data223x[127..0],
data224x[127..0],
data225x[127..0],
data226x[127..0],
data227x[127..0],
data228x[127..0],
data229x[127..0],
data22x[127..0],
data230x[127..0],
data231x[127..0],
data232x[127..0],
data233x[127..0],
data234x[127..0],
data235x[127..0],
data236x[127..0],
data237x[127..0],
data238x[127..0],
data239x[127..0],
data23x[127..0],
data240x[127..0],
data241x[127..0],
data242x[127..0],
data243x[127..0],
data244x[127..0],
data245x[127..0],
data246x[127..0],
data247x[127..0],
data248x[127..0],
data249x[127..0],
data24x[127..0],
data250x[127..0],
data251x[127..0],
data252x[127..0],
data253x[127..0],
data254x[127..0],
data255x[127..0],
data25x[127..0],
data26x[127..0],
data27x[127..0],
data28x[127..0],
data29x[127..0],
data2x[127..0],
data30x[127..0],
data31x[127..0],
data32x[127..0],
data33x[127..0],
data34x[127..0],
data35x[127..0],
data36x[127..0],
data37x[127..0],
data38x[127..0],
data39x[127..0],
data3x[127..0],
data40x[127..0],
data41x[127..0],
data42x[127..0],
data43x[127..0],
data44x[127..0],
data45x[127..0],
data46x[127..0],
data47x[127..0],
data48x[127..0],
data49x[127..0],
data4x[127..0],
data50x[127..0],
data51x[127..0],
data52x[127..0],
data53x[127..0],
data54x[127..0],
data55x[127..0],
data56x[127..0],
data57x[127..0],
data58x[127..0],
data59x[127..0],
data5x[127..0],
data60x[127..0],
data61x[127..0],
data62x[127..0],
data63x[127..0],
data64x[127..0],
data65x[127..0],
data66x[127..0],
data67x[127..0],
data68x[127..0],
data69x[127..0],
data6x[127..0],
data70x[127..0],
data71x[127..0],
data72x[127..0],
data73x[127..0],
data74x[127..0],
data75x[127..0],
data76x[127..0],
data77x[127..0],
data78x[127..0],
data79x[127..0],
data7x[127..0],
data80x[127..0],
data81x[127..0],
data82x[127..0],
data83x[127..0],
data84x[127..0],
data85x[127..0],
data86x[127..0],
data87x[127..0],
data88x[127..0],
data89x[127..0],
data8x[127..0],
data90x[127..0],
data91x[127..0],
data92x[127..0],
data93x[127..0],
data94x[127..0],
data95x[127..0],
data96x[127..0],
data97x[127..0],
data98x[127..0],
data99x[127..0],
data9x[127..0],
sel[7..0]
)
RETURNS (
result[127..0]
);

10
FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.qip → FPGA_by_Fredi/lpm_mux1.qip
View File

@@ -1,6 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "LPM_CLSHIFT" set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
set_global_assignment -name IP_TOOL_VERSION "9.1" set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.tdf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.bsf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.inc"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.cmp"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.cmp"]

1105
FPGA_by_Fredi/lpm_mux1.tdf Normal file
View File

File diff suppressed because it is too large Load Diff

115
FPGA_by_Fredi/serv_req_info.txt
View File

@@ -1,115 +0,0 @@
<internal_error>
<executable>quartus.exe</executable>
<sub_system>VDB</sub_system>
<file>/quartus/db/vdb/vdb_value_bus.cpp</file>
<line>4101</line>
<callstack>
0x0382cb44: db_vdb + 0x5cb44 (?get_element@VDB_VALUE_BUS@@QBIPAVVDB_VALUE@@I@Z + 0x54)
</callstack>
<error>loc &lt; m_value-&gt;size()</error>
<date>Tue Oct 13 17:01:46 2009</date>
<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
<full_error>loc &lt; m_value-&gt;size()
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
</internal_error>
<internal_error>
<executable>quartus.exe</executable>
<sub_system>VDB</sub_system>
<file>/quartus/db/vdb/vdb_value_bus.cpp</file>
<line>4101</line>
<callstack>
0x0382cb44: db_vdb + 0x5cb44 (?get_element@VDB_VALUE_BUS@@QBIPAVVDB_VALUE@@I@Z + 0x54)
</callstack>
<error>loc &lt; m_value-&gt;size()</error>
<date>Tue Oct 13 17:11:00 2009</date>
<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
<full_error>loc &lt; m_value-&gt;size()
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
</internal_error>
<internal_error>
<executable>quartus.exe</executable>
<sub_system>unknown</sub_system>
<file>unknown</file>
<line>0</line>
<error>Current editor: GED</error>
<date>Wed Oct 14 23:17:06 2009</date>
<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
<full_error>Access Violation at 00000000
Current editor: GED
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
</internal_error>
<internal_error>
<executable>quartus.exe</executable>
<sub_system>unknown</sub_system>
<file>unknown</file>
<line>0</line>
<error>Current editor: SFW, STED</error>
<date>Thu Oct 15 19:23:19 2009</date>
<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
<full_error>Access Violation at 00000000
Current editor: SFW, STED
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
</internal_error>
<internal_error>
<executable>quartus.exe</executable>
<sub_system>unknown</sub_system>
<file>unknown</file>
<line>0</line>
<callstack>
0x1002d196: GCL_AFC + 0x2d196 (?open_document_file@AFC_TEMPLATE_MANAGER@@UAIPAVCDocument@@PBDPBVAFC_DOC_INFO@@PAVAFC_PROJECT_STATE_MAP@@_N33@Z + 0x7b6)
</callstack>
<error>Current editor: RPW, SFW
Current dockable window: PJN</error>
<date>Fri Oct 16 00:14:03 2009</date>
<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
<full_error>Access Violation at 0X1002D196
Current editor: RPW, SFW
Current dockable window: PJN
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
</internal_error>
<internal_error>
<executable>quartus.exe</executable>
<sub_system>unknown</sub_system>
<file>unknown</file>
<line>0</line>
<error>Current editor: SFW</error>
<date>Sat Oct 17 19:01:54 2009</date>
<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
<full_error>Access Violation at 00000000
Current editor: SFW
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
</internal_error>
<internal_error>
<executable>quartus.exe</executable>
<sub_system>AFC</sub_system>
<file>/quartus/gcl/afc/afc_child_frame.cpp</file>
<line>1940</line>
<callstack>
0x100084fa: GCL_AFC + 0x84fa (?enable_docking@AFC_CHILD_FRAME@@QAIXK@Z + 0x7a)
</callstack>
<error>(bar != NULL) &amp;&amp; bar-&gt;Create(this, WS_CLIPSIBLINGS | WS_CLIPCHILDREN | WS_CHILD | WS_VISIBLE | m_s_dock_bar_map[i][1], 0, m_s_dock_bar_map[i][0])</error>
<date>Mon Oct 19 21:58:36 2009</date>
<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
<full_error>(bar != NULL) &amp;&amp; bar-&gt;Create(this, WS_CLIPSIBLINGS | WS_CLIPCHILDREN | WS_CHILD | WS_VISIBLE | m_s_dock_bar_map[i][1], 0, m_s_dock_bar_map[i][0])
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
</internal_error>
<internal_error>
<executable>quartus.exe</executable>
<sub_system>unknown</sub_system>
<file>unknown</file>
<line>0</line>
<error>Current editor: RPW, GED</error>
<date>Tue Oct 20 00:53:11 2009</date>
<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
<full_error>Access Violation at 00000000
Current editor: RPW, GED
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
</internal_error>

27
FPGA_by_Fredi/undo_redo.txt
View File

@@ -1,27 +0,0 @@
GED
Undo Commands
1. Properties
2. Move
3. Delete
4. Delete
5. Insert Node
6. Insert Symbol
7. Delete
8. Move
9. Move
10. Paste
11. Delete
12. Insert Symbol
13. Move
14. Paste
15. Delete
16. Delete
RPW
Undo Commands
1. ||Compilation Report||Flow Summary