Firebee/BaS_gcc
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

add missing files not taken with github import

Browse Source
This commit is contained in:
Markus Fröschle
2017-12-25 10:21:08 +01:00
parent c6de494f33
commit d6a9aa14e3
260 changed files with 75195 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

436
x86emu/x86biosemu.c Normal file
View File

@@ -0,0 +1,436 @@
#define RINFO_ONLY
#include "radeonfb.h"
#include "bas_printf.h"
#include "bas_string.h"
#include "util.h"
#include "driver_mem.h"
#include "x86emu.h"
#include "x86emu_regs.h"
#include "pci.h"
#include "pci_ids.h"
#include "x86pcibios.h"
// #define DEBUG
#include "debug.h"
struct rom_header
{
uint16_t signature;
uint8_t size;
uint8_t init[3];
uint8_t reserved[0x12];
uint16_t data;
};
struct pci_data
{
uint32_t signature;
uint16_t vendor;
uint16_t device;
uint16_t reserved_1;
uint16_t dlen;
uint8_t drevision;
uint8_t class_lo;
uint16_t class_hi;
uint16_t ilen;
uint16_t irevision;
uint8_t type;
uint8_t indicator;
uint16_t reserved_2;
};
static struct radeonfb_info *rinfo_biosemu;
uint16_t offset_port;
uint32_t offset_mem;
static uint32_t offset_io;
static uint32_t config_address_reg;
/* general software interrupt handler */
static uint32_t getIntVect(struct X86EMU *emu, int num)
{
return MEM_RW(num << 2) + (MEM_RW((num << 2) + 2) << 4);
}
/* FixME: There is already a push_word() in the emulator */
static void pushw(struct X86EMU *emu, uint16_t val)
{
emu->x86.R_ESP -= 2;
MEM_WW(((uint32_t) emu->x86.R_SS << 4) + emu->x86.R_SP, val);
}
static int run_bios_int(struct X86EMU *emu, int num)
{
uint32_t eflags;
eflags = emu->x86.R_EFLG;
pushw(emu, eflags);
pushw(emu, emu->x86.R_CS);
pushw(emu, emu->x86.R_IP);
emu->x86.R_CS = MEM_RW((num << 2) + 2);
emu->x86.R_IP = MEM_RW(num << 2);
return 1;
}
static uint8_t inb(struct X86EMU *emu, uint16_t port)
{
uint8_t val = 0;
if ((port >= offset_port) && (port <= offset_port + 0xff))
{
val = * (volatile uint8_t *) (offset_io + (uint32_t) port);
}
else
dbg("illegal port 0x%x\r\n", port);
return val;
}
static uint16_t inw(struct X86EMU *emu, uint16_t port)
{
uint16_t val = 0;
if ((port >= offset_port) && (port <= offset_port + 0xFF))
{
val = swpw(*(volatile uint16_t *)(offset_io + (uint32_t) port));
}
else
dbg("illegal port 0x%x\r\n", port);
return val;
}
#define PC_PCI_INDEX_PORT 0xcf8
#define PC_PCI_DATA_PORT 0xcfc
static uint32_t inl(struct X86EMU *emu, uint16_t port)
{
uint32_t val = 0;
if ((port >= offset_port) && (port <= offset_port + 0xFF))
{
val = swpl(*(volatile uint32_t *)(offset_io + (uint32_t) port));
}
else if (port == PC_PCI_INDEX_PORT)
{
val = config_address_reg;
}
else if ((port == PC_PCI_DATA_PORT) && ((config_address_reg & 0x80000000) != 0))
{
switch (config_address_reg & 0xFC)
{
case PCIIDR:
val = ((uint32_t) rinfo_biosemu->chipset << 16) + PCI_VENDOR_ID_ATI;
break;
case PCIBAR1:
val = (uint32_t) offset_port + 1;
break;
default:
val = pci_read_config_longword(rinfo_biosemu->handle, config_address_reg & 0xFC);
break;
}
}
else
dbg("illegal port 0x%x\r\n", port);
return val;
}
static void outb(struct X86EMU *emu, uint16_t port, uint8_t val)
{
if ((port >= offset_port) && (port <= offset_port + 0xFF))
{
*(volatile uint8_t *)(offset_io + (uint32_t) port) = val;
}
else
dbg("illegal port 0x%x\r\n", port);
}
static void outw(struct X86EMU *emu, uint16_t port, uint16_t val)
{
if ((port >= offset_port) && (port <= offset_port + 0xFF))
{
*(volatile uint16_t *)(offset_io + (uint32_t) port) = swpw(val);
}
else
dbg("illegal port 0x%x\r\n", port);
}
static void outl(struct X86EMU *emu, uint16_t port, uint32_t val)
{
if ((port >= offset_port) && (port <= offset_port + 0xFF))
{
*(volatile uint32_t *)(offset_io + (uint32_t) port) = swpl(val);
}
else if (port == PC_PCI_INDEX_PORT)
{
config_address_reg = val;
}
else if ((port == PC_PCI_DATA_PORT) && ((config_address_reg & 0x80000000) !=0))
{
dbg("(0x%x, 0x%x) to PCI config space\r\n", port, val);
if ((config_address_reg & 0xFC) == PCIBAR1)
{
offset_port = (uint16_t) val & 0xFFFC;
}
else
{
pci_write_config_longword(rinfo_biosemu->handle, config_address_reg & 0xFC, val);
}
}
else
dbg("illegal port 0x%x\r\n", port);
}
/*
* Interrupt multiplexer
*/
static void do_int(struct X86EMU *emu, int num)
{
int ret = 0;
switch (num)
{
case 0x10:
/* video interrupt */
/* fall through intentional */
case 0x42:
/* video interrupt */
/* fall through intentional */
case 0x6d:
/* VGA internal interrupt */
dbg("int %02xh, AH=0x%02x, AL=0x%02x\r\n", num,
emu->x86.register_a.I8_reg.h_reg,
emu->x86.register_a.I8_reg.l_reg);
if (emu->x86.register_a.I8_reg.h_reg == 0x13) /* VGA write string */
{
int num_chars = emu->x86.register_c.I16_reg.x_reg;
int seg = emu->x86.register_es;
int off = emu->x86.register_bp.I16_reg.x_reg;
int str = (seg << 4) + off;
int i;
dbg("string to output at 0x%04x:0x%04x length=0x%04x\r\n", seg, off, num_chars);
/*
* output VGA BIOS version string
*/
for (i = 0; i < num_chars; i++)
xprintf("%c", * (char *)(BIOS_MEM + str + i));
}
if (getIntVect(emu, num) == 0x0000)
err("uninitialised int vector\r\n");
if (getIntVect(emu, num) == 0xFF065)
{
ret = 1;
}
break;
case 0x15:
ret = 1;
break;
case 0x16:
ret = 0;
break;
case 0x1a:
ret = x86_pcibios_handler(emu);
ret = 1;
break;
case 0xe6:
ret = 0;
break;
default:
dbg("unhandled interrupt 0x%x\r\n", num);
break;
}
if (!ret)
{
ret = run_bios_int(emu, num);
}
}
static int setup_system_bios(void *base_addr)
{
char *base = (char *) base_addr;
int i;
/*
* we trap the "industry standard entry points" to the BIOS
* and all other locations by filling them with "hlt"
* TODO: implement hlt-handler for these
*/
for (i = 0; i < SIZE_EMU + 4; base[i++] = 0xf4);
return 1;
}
void run_bios(struct radeonfb_info *rinfo)
{
long i;
long j;
unsigned char *ptr;
struct rom_header *rom_header;
struct pci_data *rom_data;
unsigned long rom_size = 0;
unsigned long image_size = 0;
unsigned long addr;
unsigned short initialcs;
unsigned short initialip;
unsigned short devfn = (unsigned short) rinfo->handle;
struct X86EMU emu = { 0 };
X86EMU_init_default(&emu);
emu.emu_inb = inb;
emu.emu_inw = inw;
emu.emu_inl = inl;
emu.emu_outb = outb;
emu.emu_outw = outw;
emu.emu_outl = outl;
if ((rinfo->mmio_base == NULL) || (rinfo->io_base == NULL))
{
dbg("rinfo->mmio_base = %p, rinfo->io_base = %p\r\n", rinfo->mmio_base, rinfo->io_base);
return;
}
rinfo_biosemu = rinfo;
config_address_reg = 0;
offset_port = 0x300;
offset_io = (uint32_t) rinfo->io_base - (uint32_t) offset_port;
offset_mem = (uint32_t) rinfo->fb_base - 0xa0000;
rom_header = NULL;
do
{
rom_header = (struct rom_header *) ((uintptr_t) rom_header + image_size); // get next image
rom_data = (struct pci_data *) ((uintptr_t) rom_header + (uintptr_t) BIOS_IN16((long) &rom_header->data));
image_size = (size_t) BIOS_IN16((long) &rom_data->ilen) * 512;
} while ((BIOS_IN8((long) &rom_data->type) != 0) && (BIOS_IN8((long) &rom_data->indicator) != 0)); // make sure we got x86 version
if (BIOS_IN8((long) &rom_data->type) != 0)
{
dbg("unknown ROM data type = 0x%x\r\n", BIOS_IN8((long) &rom_data->type));
return;
}
rom_size = (size_t) BIOS_IN8((uintptr_t) &rom_header->size) * 512;
dbg("ROM size = 0x%lx\r\n", rom_size);
if (PCI_CLASS_DISPLAY_VGA == BIOS_IN16((long) &rom_data->class_hi))
{
memset((char *) BIOS_MEM, 0, SIZE_EMU);
setup_system_bios((char *) BIOS_MEM);
dbg("Copy VGA ROM Image from %p to %p (0x%lx bytes)\r\n",
(uintptr_t) rinfo->bios_seg + (uintptr_t) rom_header,
BIOS_MEM + PCI_VGA_RAM_IMAGE_START, rom_size);
{
long bytes_align = (uintptr_t) rom_header & 3;
ptr = (uint8_t *) BIOS_MEM;
i = (long) rom_header;
j = PCI_VGA_RAM_IMAGE_START;
if (bytes_align)
{
for (; i < 4 - bytes_align; ptr[j++] = BIOS_IN8(i++));
}
for (; i < (long) rom_header + rom_size; i += 4, j += 4)
{
*((uintptr_t *) &ptr[j]) = swpl(BIOS_IN32(i));
}
}
addr = PCI_VGA_RAM_IMAGE_START;
}
else
{
memset((uint8_t *) BIOS_MEM, 0, SIZE_EMU);
setup_system_bios((char *) BIOS_MEM);
dbg("Copy non-VGA ROM Image from %p to %p (0x%lx bytes)\r\n",
(uintptr_t) rinfo->bios_seg + (uintptr_t) rom_header,
BIOS_MEM + PCI_RAM_IMAGE_START,
rom_size);
ptr = (uint8_t *) BIOS_MEM;
for (i = (long) rom_header, j = PCI_RAM_IMAGE_START; i < (long) rom_header + rom_size; ptr[j++] = BIOS_IN8(i++));
addr = PCI_RAM_IMAGE_START;
}
initialcs = (addr & 0xf0000) >> 4;
initialip = (addr + 3) & 0xffff;
dbg("initial CS=0x%x, initial IP=0x%x\r\n", initialcs, initialip);
/*
* set emulator memory
*/
emu.mem_base = (void *) BIOS_MEM;
emu.mem_size = SIZE_EMU;
for (i = 0; i < 256; i++)
{
emu._X86EMU_intrTab[i] = do_int;
}
char *date = "01/01/99";
for (i = 0; date[i]; i++)
{
emu.emu_wrb(&emu, 0xffff5 + i, date[i]);
}
emu.emu_wrb(&emu, 0xffff7, '/');
emu.emu_wrb(&emu, 0xffffa, '/');
/* cpu setup */
emu.x86.R_AX = devfn ? devfn : 0xff;
emu.x86.R_DX = 0x80;
emu.x86.R_IP = initialip;
emu.x86.R_CS = initialcs;
/* Initialize stack and data segment */
emu.x86.R_SS = initialcs;
emu.x86.R_SP = 0xfffe;
emu.x86.R_DS = 0x0040;
emu.x86.R_ES = 0x0000;
/*
* We need a sane way to return from bios
* execution. A hlt instruction and a pointer
* to it, both kept on the stack, will do.
*/
pushw(&emu, 0xf4f4); /* hlt; hlt */
pushw(&emu, emu.x86.R_SS);
pushw(&emu, emu.x86.R_SP + 2);
dbg("X86EMU entering emulator\r\n");
X86EMU_exec(&emu);
dbg("X86EMU halted\r\n");
/*
* clear emulator memory once we are finished
*/
memset((char *) BIOS_MEM, 0, SIZE_EMU);
}

8164
x86emu/x86emu.c Normal file
View File

File diff suppressed because it is too large Load Diff

201
x86emu/x86emu_util.c Normal file
View File

@@ -0,0 +1,201 @@
/* $NetBSD: x86emu_util.c,v 1.1 2007/11/30 20:02:50 joerg Exp $ */
/****************************************************************************
*
* Realmode X86 Emulator Library
*
* Copyright (C) 1996-1999 SciTech Software, Inc.
* Copyright (C) David Mosberger-Tang
* Copyright (C) 1999 Egbert Eich
* Copyright (C) 2007 Joerg Sonnenberger
*
* ========================================================================
*
* Permission to use, copy, modify, distribute, and sell this software and
* its documentation for any purpose is hereby granted without fee,
* provided that the above copyright notice appear in all copies and that
* both that copyright notice and this permission notice appear in
* supporting documentation, and that the name of the authors not be used
* in advertising or publicity pertaining to distribution of the software
* without specific, written prior permission. The authors makes no
* representations about the suitability of this software for any purpose.
* It is provided "as is" without express or implied warranty.
*
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*
****************************************************************************/
#include "x86emu.h"
#include "x86emu_regs.h"
// #define DEBUG
#include "debug.h"
static __inline uint16_t le16dec(const void *buf)
{
const uint8_t *p = (uint8_t *) buf;
return ((p[1] << 8) | p[0]);
}
static __inline uint32_t le32dec(const void *buf)
{
const uint8_t *p = (uint8_t *) buf;
return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]);
}
static __inline void le16enc(void *buf, uint16_t u)
{
uint8_t *p = buf;
p[0] = u & 0xff;
p[1] = ((unsigned) u >> 8) & 0xff;
}
static __inline void le32enc(void *buf, uint32_t u)
{
uint8_t *p = buf;
p[0] = u & 0xff;
p[1] = (u >> 8) & 0xff;
p[2] = (u >> 16) & 0xff;
p[3] = (u >> 24) & 0xff;
}
/****************************************************************************
PARAMETERS:
addr - Emulator memory address to read
RETURNS:
Byte value read from emulator memory.
REMARKS:
Reads a byte value from the emulator memory.
****************************************************************************/
static uint8_t rdb(struct X86EMU *emu, uint32_t addr)
{
if (addr > emu->mem_size - 1)
{
dbg("attempted read outside system memory: 0x%lx. Halt emulator.\r\n", addr);
X86EMU_halt_sys(emu);
}
return emu->mem_base[addr];
}
/****************************************************************************
PARAMETERS:
addr - Emulator memory address to read
RETURNS:
Word value read from emulator memory.
REMARKS:
Reads a word value from the emulator memory.
****************************************************************************/
static uint16_t rdw(struct X86EMU *emu, uint32_t addr)
{
if (addr > emu->mem_size - 2)
{
dbg("attempted read outside system memory: 0x%lx. Halt emulator.\r\n", addr);
X86EMU_halt_sys(emu);
}
return le16dec(emu->mem_base + addr);
}
/****************************************************************************
PARAMETERS:
addr - Emulator memory address to read
RETURNS:
Long value read from emulator memory.
REMARKS:
Reads a long value from the emulator memory.
****************************************************************************/
static uint32_t rdl(struct X86EMU *emu, uint32_t addr)
{
if (addr > emu->mem_size - 4)
{
dbg("attempted read outside system memory: 0x%lx. Halt emulator.\r\n", addr);
X86EMU_halt_sys(emu);
}
return le32dec(emu->mem_base + addr);
}
/****************************************************************************
PARAMETERS:
addr - Emulator memory address to read
val - Value to store
REMARKS:
Writes a byte value to emulator memory.
****************************************************************************/
static void wrb(struct X86EMU *emu, uint32_t addr, uint8_t val)
{
if (addr > emu->mem_size - 1)
{
dbg("attempted write outside system memory: 0x%lx (0x%02x). Halt emulator.\r\n", addr, val);
X86EMU_halt_sys(emu);
}
emu->mem_base[addr] = val;
}
/****************************************************************************
PARAMETERS:
addr - Emulator memory address to read
val - Value to store
REMARKS:
Writes a word value to emulator memory.
****************************************************************************/
static void wrw(struct X86EMU *emu, uint32_t addr, uint16_t val)
{
if (addr > emu->mem_size - 2)
{
dbg("attempted write outside system memory: 0x%lx (0x%04x). Halt emulator\r\n", addr, val);
X86EMU_halt_sys(emu);
}
le16enc(emu->mem_base + addr, val);
}
/****************************************************************************
PARAMETERS:
addr - Emulator memory address to write
val - Value to store
REMARKS:
Writes a long value to emulator memory.
****************************************************************************/
static void wrl(struct X86EMU *emu, uint32_t addr, uint32_t val)
{
if (addr > emu->mem_size - 4)
{
dbg("attempted write outside system memory: 0x%lx (0x%08x)\r\n", addr, val);
X86EMU_halt_sys(emu);
}
le32enc(emu->mem_base + addr, val);
}
/*----------------------------- Setup -------------------------------------*/
void X86EMU_init_default(struct X86EMU *emu)
{
int i;
emu->emu_rdb = rdb;
emu->emu_rdw = rdw;
emu->emu_rdl = rdl;
emu->emu_wrb = wrb;
emu->emu_wrw = wrw;
emu->emu_wrl = wrl;
for (i = 0; i < 256; i++)
{
emu->_X86EMU_intrTab[i] = NULL;
}
}

171
x86emu/x86pcibios.c Normal file
View File

@@ -0,0 +1,171 @@
#include "radeonfb.h"
#include "pci.h"
#include "x86emu.h"
#include "x86pcibios.h"
#include "x86emu_regs.h"
#include "bas_printf.h"
extern unsigned short offset_port;
// #define DEBUG
#include "debug.h"
int x86_pcibios_handler(struct X86EMU *emu)
{
int ret = 0;
unsigned long dev;
switch (emu->x86.R_AX)
{
case PCI_BIOS_PRESENT:
dbg("PCI_BIOS_PRESENT\r\n");
emu->x86.R_AH = 0x00; /* no config space/special cycle support */
emu->x86.R_AL = 0x01; /* config mechanism 1 */
emu->x86.R_EDX = 'P' | 'C' << 8 | 'I' << 16 | ' ' << 24;
emu->x86.R_EBX = 0x0210; /* Version 2.10 */
emu->x86.R_ECX = 0xFF00; /* FixME: Max bus number */
emu->x86.R_EFLG &= ~FB_CF; /* clear carry flag */
ret = 1;
break;
case FIND_PCI_DEVICE:
dbg("FIND_PCI_DEVICE vendor = %04x, device = %04x\r\n", emu->x86.R_DX, emu->x86.R_CX);
dev = pci_find_device((uintptr_t) emu->x86.R_DX, ((unsigned long) emu->x86.R_CX), 0);
if (dev != 0)
{
dbg("dev = %d\r\n", dev);
emu->x86.R_BH = PCI_BUS_FROM_HANDLE(dev);
//X86_BH = (char)(dev >> 16) / PCI_MAX_FUNCTION); // dev->bus->secondary;
emu->x86.R_BL = PCI_DEVICE_FROM_HANDLE(dev) << 3 | PCI_FUNCTION_FROM_HANDLE(dev);
//X86_BL = (char)dev; // dev->path.u.pci.devfn;
emu->x86.R_AH = SUCCESSFUL;
emu->x86.R_EFLG &= ~FB_CF; /* clear carry flag */
ret = 1;
}
else
{
dbg("device not found\r\n");
emu->x86.R_AH = DEVICE_NOT_FOUND;
emu->x86.R_EFLG |= FB_CF; /* set carry flag */
ret = 0;
}
break;
case FIND_PCI_CLASS_CODE:
/* FixME: support SI != 0 */
dbg("FIND_PCI_CLASS_CODE %x", emu->x86.R_ECX);
dev = pci_find_classcode(emu->x86.R_ECX, 0);
if (dev != 0) {
dbg(" ...OK\r\n");
emu->x86.R_BH = PCI_BUS_FROM_HANDLE(dev);
emu->x86.R_BL = PCI_DEVICE_FROM_HANDLE(dev) << 3 | PCI_FUNCTION_FROM_HANDLE(dev);
emu->x86.R_AH = SUCCESSFUL;
emu->x86.R_EFLG &= ~FB_CF; /* clear carry flag */
ret = 1;
}
else
{
dbg(" ... error\r\n");
emu->x86.R_AH = DEVICE_NOT_FOUND;
emu->x86.R_EFLG |= FB_CF; /* set carry flag */
ret = 0;
}
break;
case READ_CONFIG_BYTE:
// bus, devfn
dbg("READ_CONFIG_BYTE bus = %x, devfn = %x, reg = %x\r\n", emu->x86.R_BH, emu->x86.R_BL, emu->x86.R_DI);
dev = PCI_HANDLE(emu->x86.R_BH, emu->x86.R_BL >> 3, emu->x86.R_BL & 7);
emu->x86.R_CL = pci_read_config_byte(dev, emu->x86.R_DI);
dbg("dev=0x%04x value = 0x%04x\r\n", emu->x86.R_CL);
emu->x86.R_AH = SUCCESSFUL;
emu->x86.R_EFLG &= ~FB_CF; /* clear carry flag */
ret = 1;
break;
case READ_CONFIG_WORD:
// bus, devfn
dbg("READ_CONFIG_WORD bus = %x, devfn = %x, reg = %x\r\n", emu->x86.R_BH, emu->x86.R_BL, emu->x86.R_DI);
dev = PCI_HANDLE(emu->x86.R_BH, emu->x86.R_BL >> 3, emu->x86.R_BL & 7);
if (emu->x86.R_DI == PCIBAR1)
emu->x86.R_CX = offset_port + 1;
else
emu->x86.R_CX = pci_read_config_word(dev, emu->x86.R_DI);
dbg("offset_port=0x%04x dev=0x%04x, value = %x\r\n", offset_port, dev, emu->x86.R_CX);
emu->x86.R_AH = SUCCESSFUL;
emu->x86.R_EFLG &= ~FB_CF; /* clear carry flag */
ret = 1;
break;
case READ_CONFIG_DWORD:
// bus, devfn
dbg("READ_CONFIG_DWORD bus = %x, devfn = %x, reg = %x\r\n", emu->x86.R_BH, emu->x86.R_BL, emu->x86.R_DI);
dev = PCI_HANDLE(emu->x86.R_BH, emu->x86.R_BL >> 3, emu->x86.R_BL & 7);
if (emu->x86.R_DI == PCIBAR1)
emu->x86.R_CX = (unsigned long) offset_port + 1;
else
emu->x86.R_ECX = pci_read_config_longword(dev, emu->x86.R_DI);
dbg("value = %x\r\n", emu->x86.R_ECX);
emu->x86.R_AH = SUCCESSFUL;
emu->x86.R_EFLG &= ~FB_CF; /* clear carry flag */
ret = 1;
break;
case WRITE_CONFIG_BYTE:
// bus, devfn
dbg("READ_CONFIG_BYTE bus = %x, devfn = %x, reg = %x, value = %x\r\n",
emu->x86.R_BH, emu->x86.R_BL, emu->x86.R_DI, emu->x86.R_CL);
dev = PCI_HANDLE(emu->x86.R_BH, emu->x86.R_BL >> 3, emu->x86.R_BL & 7);
pci_write_config_byte(dev, emu->x86.R_DI, emu->x86.R_CL);
emu->x86.R_AH = SUCCESSFUL;
emu->x86.R_EFLG &= ~FB_CF; /* clear carry flag */
ret = 1;
break;
case WRITE_CONFIG_WORD:
// bus, devfn
dev = PCI_HANDLE(emu->x86.R_BH, emu->x86.R_BL >> 3, emu->x86.R_BL & 7);
dbg("WRITE_CONFIG_WORD bus = %x, devfn = %x, reg = %x, value = %x\r\n", emu->x86.R_BH, emu->x86.R_BL, emu->x86.R_DI, emu->x86.R_CX);
if (emu->x86.R_DI == PCIBAR1)
{
offset_port = emu->x86.R_CX;
emu->x86.R_AH = SUCCESSFUL;
emu->x86.R_EFLG &= ~FB_CF; /* clear carry flag */
ret = 1;
break;
}
pci_write_config_word(dev, emu->x86.R_DI, emu->x86.R_CX);
emu->x86.R_AH = SUCCESSFUL;
emu->x86.R_EFLG &= ~FB_CF; /* clear carry flag */
ret = 1;
break;
case WRITE_CONFIG_DWORD:
// bus, devfn
dev = PCI_HANDLE(emu->x86.R_BH, emu->x86.R_BL >> 3, emu->x86.R_BL & 7);
dbg("WRITE_CONFIG_DWORD bus = %x, devfn = %x, value = %x\r\n",
emu->x86.R_BH, emu->x86.R_BL, emu->x86.R_DI, emu->x86.R_ECX);
if (emu->x86.R_DI == PCIBAR1)
{
offset_port = (unsigned short) emu->x86.R_ECX & 0xFFFC;
emu->x86.R_AH = SUCCESSFUL;
emu->x86.R_EFLG &= ~FB_CF; /* clear carry flag */
ret = 1;
break;
}
pci_write_config_longword(dev, emu->x86.R_DI, emu->x86.R_ECX);
emu->x86.R_AH = SUCCESSFUL;
emu->x86.R_EFLG &= ~FB_CF; /* clear carry flag */
ret = 1;
break;
default:
dbg("PCI_BIOS FUNC_NOT_SUPPORTED\r\n");
emu->x86.R_AH = FUNC_NOT_SUPPORTED;
emu->x86.R_EFLG |= FB_CF;
break;
}
return ret;
}