add missing files not taken with github import
This commit is contained in:
Markus Fröschle
3
BaS_gcc.config
Normal file
3
BaS_gcc.config
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@@ -0,0 +1,3 @@
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// Add predefined macros for your project here. For example:
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// #define THE_ANSWER 42
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#define MACHINE_FIREBEE
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1
BaS_gcc.creator
Normal file
1
BaS_gcc.creator
Normal file
@@ -0,0 +1 @@
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[General]
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397
BaS_gcc.files
Normal file
397
BaS_gcc.files
Normal file
@@ -0,0 +1,397 @@
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dma/dma.c
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dma/MCD_dmaApi.c
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dma/MCD_tasks.c
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dma/MCD_tasksInit.c
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exe/basflash.c
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exe/basflash_start.c
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firebee/bas.elf
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firebee/bas.lk
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firebee/bas.map
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firebee/bas.s19
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firebee/basflash.elf
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firebee/basflash.lk
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firebee/basflash.map
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firebee/basflash.s19
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firebee/depend
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firebee/libbas.a
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firebee/ram.elf
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firebee/ram.lk
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firebee/ram.map
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firebee/ram.s19
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flash/flash.c
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flash/s19reader.c
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flash_scripts/flash_firebee_bas.bdm
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flash_scripts/flash_firebee_etos.bdm
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flash_scripts/flash_firebee_firetos.bdm
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flash_scripts/flash_firebee_fpga.bdm
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flash_scripts/flash_m548x_bas.bdm
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flash_scripts/flash_m548x_dbug.bdm
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flash_scripts/flash_m548x_etos.bdm
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flash_scripts/m548xlite_dbug_ram.elf
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flash_scripts/m548xlite_dbug_ram.s19
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flash_scripts/run_m548x_dbug.bdm
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fs/cc932.c
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fs/cc936.c
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fs/cc949.c
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fs/cc950.c
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fs/ccsbcs.c
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fs/ff.c
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fs/unicode.c
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i2c/i2c.c
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if/driver_vec.c
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include/acia.h
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include/am79c874.h
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include/arp.h
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include/ati_ids.h
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include/bas_printf.h
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include/bas_string.h
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include/bas_types.h
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include/bas_utils.h
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include/bcm5222.h
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include/bootp.h
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include/cache.h
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include/conout.h
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include/debug.h
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include/diskio.h
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include/dma.h
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include/driver_mem.h
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include/driver_vec.h
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include/edid.h
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include/ehci.h
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include/eth.h
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include/exceptions.h
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include/fb.h
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include/fec.h
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include/fecbd.h
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include/ff.h
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include/ffconf.h
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include/firebee.h
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include/font.h
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include/i2c-algo-bit.h
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include/i2c.h
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include/icmp.h
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include/ikbd.h
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include/interrupts.h
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include/ip.h
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include/m54455.h
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include/m5484l.h
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include/MCD_dma.h
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include/mcd_initiators.h
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include/MCD_progCheck.h
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include/MCD_tasksInit.h
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include/MCF5475.h
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include/MCF5475_CLOCK.h
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include/MCF5475_CTM.h
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include/MCF5475_DMA.h
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include/MCF5475_DSPI.h
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include/MCF5475_EPORT.h
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include/MCF5475_FBCS.h
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include/MCF5475_FEC.h
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include/MCF5475_GPIO.h
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include/MCF5475_GPT.h
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include/MCF5475_I2C.h
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include/MCF5475_INTC.h
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include/MCF5475_MMU.h
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include/MCF5475_PAD.h
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include/MCF5475_PCI.h
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include/MCF5475_PCIARB.h
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include/MCF5475_PSC.h
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include/MCF5475_SDRAMC.h
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include/MCF5475_SEC.h
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include/MCF5475_SIU.h
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include/MCF5475_SLT.h
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include/MCF5475_SRAM.h
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include/MCF5475_USB.h
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include/MCF5475_XLB.h
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include/mmu.h
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include/mod_devicetable.h
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include/nbuf.h
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include/net.h
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include/net_timer.h
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include/nif.h
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include/ohci.h
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include/part.h
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include/pci.h
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include/pci_errata.h
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include/pci_ids.h
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include/queue.h
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include/radeon_reg.h
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include/radeonfb.h
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include/s19reader.h
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include/screen.h
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include/sd_card.h
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include/setjmp.h
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include/startcf.h
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include/sysinit.h
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include/tftp.h
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include/udp.h
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include/usb.h
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include/usb_defs.h
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include/usb_hub.h
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include/user_io.h
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include/util.h
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include/version.h
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include/videl.h
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include/video.h
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include/wait.h
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include/x86emu.h
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include/x86emu_regs.h
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include/x86pcibios.h
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include/xhdi_sd.h
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kbd/ikbd.c
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m54455/bas.elf
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m54455/bas.lk
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m54455/bas.map
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m54455/bas.s19
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m54455/basflash.elf
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m54455/basflash.lk
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m54455/basflash.map
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m54455/basflash.s19
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m54455/depend
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m54455/libbas.a
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m54455/ram.elf
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m54455/ram.lk
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m54455/ram.map
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m54455/ram.s19
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m5484lite/bas.elf
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m5484lite/bas.lk
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m5484lite/bas.map
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m5484lite/bas.s19
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m5484lite/basflash.elf
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m5484lite/basflash.lk
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m5484lite/basflash.map
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m5484lite/basflash.s19
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m5484lite/depend
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m5484lite/libbas.a
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m5484lite/ram.elf
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m5484lite/ram.lk
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m5484lite/ram.map
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m5484lite/ram.s19
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net/am79c874.c
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net/arp.c
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net/bcm5222.c
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net/bootp.c
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net/fec.c
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net/fecbd.c
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net/ip.c
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net/nbuf.c
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net/net_timer.c
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net/nif.c
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net/queue.c
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net/tftp.c
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net/udp.c
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nutil/s19header.c
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pci/ehci-hcd.c
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pci/ohci-hcd.c
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pci/pci.c
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pci/pci_errata.c
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pci/pci_wrappers.S
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radeon/i2c-algo-bit.c
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radeon/radeon_accel.c
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radeon/radeon_base.c
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radeon/radeon_cursor.c
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radeon/radeon_i2c.c
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radeon/radeon_monitor.c
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release/firebee/bas.s19
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release/m5484lite/bas.s19
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release/bascook.prg
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release/readme.txt
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spi/dspi.c
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spi/mmc.c
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spi/sd_card.c
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sys/BaS.c
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sys/cache.c
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sys/driver_mem.c
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sys/exceptions.S
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sys/fault_vectors.c
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sys/init_fpga.c
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sys/interrupts.c
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sys/mmu.c
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sys/startcf.S
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sys/sysinit.c
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tos/bascook/sources/bascook.c
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tos/bascook/bascook.prg
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tos/bascook/depend
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tos/bascook/mapfile
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tos/fpga_test/m5475/mshort/fpga_test.prg
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tos/fpga_test/m5475/fpga_test.prg
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tos/fpga_test/sources/fpga_test.c
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tos/fpga_test/sources/ser_printf.c
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tos/fpga_test/sources/vmem_test.c
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tos/fpga_test/depend
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tos/fpga_test/mapfile
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tos/jtagwait/include/bas_printf.h
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tos/jtagwait/include/bas_string.h
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tos/jtagwait/include/driver_vec.h
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tos/jtagwait/include/MCF5475.h
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tos/jtagwait/include/MCF5475_CLOCK.h
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tos/jtagwait/include/MCF5475_CTM.h
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tos/jtagwait/include/MCF5475_DMA.h
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tos/jtagwait/include/MCF5475_DSPI.h
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tos/jtagwait/include/MCF5475_EPORT.h
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tos/jtagwait/include/MCF5475_FBCS.h
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tos/jtagwait/include/MCF5475_FEC.h
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tos/jtagwait/include/MCF5475_GPIO.h
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tos/jtagwait/include/MCF5475_GPT.h
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tos/jtagwait/include/MCF5475_I2C.h
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tos/jtagwait/include/MCF5475_INTC.h
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tos/jtagwait/include/MCF5475_MMU.h
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tos/jtagwait/include/MCF5475_PAD.h
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tos/jtagwait/include/MCF5475_PCI.h
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tos/jtagwait/include/MCF5475_PCIARB.h
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tos/jtagwait/include/MCF5475_PSC.h
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tos/jtagwait/include/MCF5475_SDRAMC.h
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tos/jtagwait/include/MCF5475_SEC.h
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tos/jtagwait/include/MCF5475_SIU.h
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tos/jtagwait/include/MCF5475_SLT.h
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tos/jtagwait/include/MCF5475_SRAM.h
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tos/jtagwait/include/MCF5475_USB.h
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tos/jtagwait/include/MCF5475_XLB.h
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tos/jtagwait/m5475/mshort/jtagwait.prg
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tos/jtagwait/m5475/jtagwait.prg
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tos/jtagwait/sources/bas_printf.c
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tos/jtagwait/sources/bas_string.c
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tos/jtagwait/sources/jtagwait.c
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tos/jtagwait/sources/printf_helper.S
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tos/jtagwait/depend
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tos/jtagwait/mapfile
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tos/pci_mem/include/bas_string.h
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tos/pci_mem/include/bas_types.h
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tos/pci_mem/include/driver_vec.h
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tos/pci_mem/include/MCF5475.h
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tos/pci_mem/include/MCF5475_CLOCK.h
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tos/pci_mem/include/MCF5475_CTM.h
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tos/pci_mem/include/MCF5475_DMA.h
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tos/pci_mem/include/MCF5475_DSPI.h
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tos/pci_mem/include/MCF5475_EPORT.h
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tos/pci_mem/include/MCF5475_FBCS.h
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tos/pci_mem/include/MCF5475_FEC.h
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tos/pci_mem/include/MCF5475_GPIO.h
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tos/pci_mem/include/MCF5475_GPT.h
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tos/pci_mem/include/MCF5475_I2C.h
|
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tos/pci_mem/include/MCF5475_INTC.h
|
||||
tos/pci_mem/include/MCF5475_MMU.h
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tos/pci_mem/include/MCF5475_PAD.h
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||||
tos/pci_mem/include/MCF5475_PCI.h
|
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tos/pci_mem/include/MCF5475_PCIARB.h
|
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tos/pci_mem/include/MCF5475_PSC.h
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tos/pci_mem/include/MCF5475_SDRAMC.h
|
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tos/pci_mem/include/MCF5475_SEC.h
|
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tos/pci_mem/include/MCF5475_SIU.h
|
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tos/pci_mem/include/MCF5475_SLT.h
|
||||
tos/pci_mem/include/MCF5475_SRAM.h
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tos/pci_mem/include/MCF5475_USB.h
|
||||
tos/pci_mem/include/MCF5475_XLB.h
|
||||
tos/pci_mem/include/pci.h
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||||
tos/pci_mem/include/util.h
|
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tos/pci_mem/m5475/mshort/pci_mem.prg
|
||||
tos/pci_mem/m5475/pci_mem.prg
|
||||
tos/pci_mem/sources/pci_mem.c
|
||||
tos/pci_mem/depend
|
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tos/pci_mem/mapfile
|
||||
tos/pci_test/include/bas_string.h
|
||||
tos/pci_test/include/bas_types.h
|
||||
tos/pci_test/include/driver_vec.h
|
||||
tos/pci_test/include/MCF5475.h
|
||||
tos/pci_test/include/MCF5475_CLOCK.h
|
||||
tos/pci_test/include/MCF5475_CTM.h
|
||||
tos/pci_test/include/MCF5475_DMA.h
|
||||
tos/pci_test/include/MCF5475_DSPI.h
|
||||
tos/pci_test/include/MCF5475_EPORT.h
|
||||
tos/pci_test/include/MCF5475_FBCS.h
|
||||
tos/pci_test/include/MCF5475_FEC.h
|
||||
tos/pci_test/include/MCF5475_GPIO.h
|
||||
tos/pci_test/include/MCF5475_GPT.h
|
||||
tos/pci_test/include/MCF5475_I2C.h
|
||||
tos/pci_test/include/MCF5475_INTC.h
|
||||
tos/pci_test/include/MCF5475_MMU.h
|
||||
tos/pci_test/include/MCF5475_PAD.h
|
||||
tos/pci_test/include/MCF5475_PCI.h
|
||||
tos/pci_test/include/MCF5475_PCIARB.h
|
||||
tos/pci_test/include/MCF5475_PSC.h
|
||||
tos/pci_test/include/MCF5475_SDRAMC.h
|
||||
tos/pci_test/include/MCF5475_SEC.h
|
||||
tos/pci_test/include/MCF5475_SIU.h
|
||||
tos/pci_test/include/MCF5475_SLT.h
|
||||
tos/pci_test/include/MCF5475_SRAM.h
|
||||
tos/pci_test/include/MCF5475_USB.h
|
||||
tos/pci_test/include/MCF5475_XLB.h
|
||||
tos/pci_test/include/pci.h
|
||||
tos/pci_test/include/util.h
|
||||
tos/pci_test/m5475/mshort/pci_test.prg
|
||||
tos/pci_test/m5475/pci_test.prg
|
||||
tos/pci_test/sources/pci_test.c
|
||||
tos/pci_test/sources/printf_helper.S
|
||||
tos/pci_test/depend
|
||||
tos/pci_test/mapfile
|
||||
tos/vmem_test/include/bas_printf.h
|
||||
tos/vmem_test/include/bas_string.h
|
||||
tos/vmem_test/include/driver_vec.h
|
||||
tos/vmem_test/include/MCF5475.h
|
||||
tos/vmem_test/include/MCF5475_CLOCK.h
|
||||
tos/vmem_test/include/MCF5475_CTM.h
|
||||
tos/vmem_test/include/MCF5475_DMA.h
|
||||
tos/vmem_test/include/MCF5475_DSPI.h
|
||||
tos/vmem_test/include/MCF5475_EPORT.h
|
||||
tos/vmem_test/include/MCF5475_FBCS.h
|
||||
tos/vmem_test/include/MCF5475_FEC.h
|
||||
tos/vmem_test/include/MCF5475_GPIO.h
|
||||
tos/vmem_test/include/MCF5475_GPT.h
|
||||
tos/vmem_test/include/MCF5475_I2C.h
|
||||
tos/vmem_test/include/MCF5475_INTC.h
|
||||
tos/vmem_test/include/MCF5475_MMU.h
|
||||
tos/vmem_test/include/MCF5475_PAD.h
|
||||
tos/vmem_test/include/MCF5475_PCI.h
|
||||
tos/vmem_test/include/MCF5475_PCIARB.h
|
||||
tos/vmem_test/include/MCF5475_PSC.h
|
||||
tos/vmem_test/include/MCF5475_SDRAMC.h
|
||||
tos/vmem_test/include/MCF5475_SEC.h
|
||||
tos/vmem_test/include/MCF5475_SIU.h
|
||||
tos/vmem_test/include/MCF5475_SLT.h
|
||||
tos/vmem_test/include/MCF5475_SRAM.h
|
||||
tos/vmem_test/include/MCF5475_USB.h
|
||||
tos/vmem_test/include/MCF5475_XLB.h
|
||||
tos/vmem_test/m5475/mshort/vmem_test.prg
|
||||
tos/vmem_test/m5475/vmem_test.prg
|
||||
tos/vmem_test/sources/bas_printf.c
|
||||
tos/vmem_test/sources/bas_string.c
|
||||
tos/vmem_test/sources/printf_helper.S
|
||||
tos/vmem_test/sources/vmem_test.c
|
||||
tos/vmem_test/depend
|
||||
tos/vmem_test/mapfile
|
||||
usb/usb.c
|
||||
usb/usb_hub.c
|
||||
usb/usb_kbd.c
|
||||
usb/usb_mouse.c
|
||||
util/bas_printf.c
|
||||
util/bas_string.c
|
||||
util/conout.c
|
||||
util/libgcc_helper.S
|
||||
util/setjmp.S
|
||||
util/wait.c
|
||||
video/fbmem.c
|
||||
video/fbmodedb.c
|
||||
video/fbmon.c
|
||||
video/fnt_st_8x16.c
|
||||
video/offscreen.c
|
||||
video/vdi_fill.c
|
||||
video/videl.c
|
||||
video/video.c
|
||||
x86emu/x86biosemu.c
|
||||
x86emu/x86emu.c
|
||||
x86emu/x86emu_util.c
|
||||
x86emu/x86pcibios.c
|
||||
xhdi/xhdi_interface.c
|
||||
xhdi/xhdi_sd.c
|
||||
xhdi/xhdi_vec.S
|
||||
bas.lk.in
|
||||
bas_firebee.bdm
|
||||
bas_m5484.bdm
|
||||
basflash.lk.in
|
||||
check.bdm
|
||||
COPYING
|
||||
COPYING.LESSER
|
||||
Doxyfile
|
||||
dump.bdm
|
||||
mcf5474.gdb
|
||||
memory_map.txt
|
||||
5
BaS_gcc.includes
Normal file
5
BaS_gcc.includes
Normal file
@@ -0,0 +1,5 @@
|
||||
include
|
||||
tos/jtagwait/include
|
||||
tos/pci_mem/include
|
||||
tos/pci_test/include
|
||||
tos/vmem_test/include
|
||||
674
COPYING
Normal file
674
COPYING
Normal file
@@ -0,0 +1,674 @@
|
||||
GNU GENERAL PUBLIC LICENSE
|
||||
Version 3, 29 June 2007
|
||||
|
||||
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
|
||||
Everyone is permitted to copy and distribute verbatim copies
|
||||
of this license document, but changing it is not allowed.
|
||||
|
||||
Preamble
|
||||
|
||||
The GNU General Public License is a free, copyleft license for
|
||||
software and other kinds of works.
|
||||
|
||||
The licenses for most software and other practical works are designed
|
||||
to take away your freedom to share and change the works. By contrast,
|
||||
the GNU General Public License is intended to guarantee your freedom to
|
||||
share and change all versions of a program--to make sure it remains free
|
||||
software for all its users. We, the Free Software Foundation, use the
|
||||
GNU General Public License for most of our software; it applies also to
|
||||
any other work released this way by its authors. You can apply it to
|
||||
your programs, too.
|
||||
|
||||
When we speak of free software, we are referring to freedom, not
|
||||
price. Our General Public Licenses are designed to make sure that you
|
||||
have the freedom to distribute copies of free software (and charge for
|
||||
them if you wish), that you receive source code or can get it if you
|
||||
want it, that you can change the software or use pieces of it in new
|
||||
free programs, and that you know you can do these things.
|
||||
|
||||
To protect your rights, we need to prevent others from denying you
|
||||
these rights or asking you to surrender the rights. Therefore, you have
|
||||
certain responsibilities if you distribute copies of the software, or if
|
||||
you modify it: responsibilities to respect the freedom of others.
|
||||
|
||||
For example, if you distribute copies of such a program, whether
|
||||
gratis or for a fee, you must pass on to the recipients the same
|
||||
freedoms that you received. You must make sure that they, too, receive
|
||||
or can get the source code. And you must show them these terms so they
|
||||
know their rights.
|
||||
|
||||
Developers that use the GNU GPL protect your rights with two steps:
|
||||
(1) assert copyright on the software, and (2) offer you this License
|
||||
giving you legal permission to copy, distribute and/or modify it.
|
||||
|
||||
For the developers' and authors' protection, the GPL clearly explains
|
||||
that there is no warranty for this free software. For both users' and
|
||||
authors' sake, the GPL requires that modified versions be marked as
|
||||
changed, so that their problems will not be attributed erroneously to
|
||||
authors of previous versions.
|
||||
|
||||
Some devices are designed to deny users access to install or run
|
||||
modified versions of the software inside them, although the manufacturer
|
||||
can do so. This is fundamentally incompatible with the aim of
|
||||
protecting users' freedom to change the software. The systematic
|
||||
pattern of such abuse occurs in the area of products for individuals to
|
||||
use, which is precisely where it is most unacceptable. Therefore, we
|
||||
have designed this version of the GPL to prohibit the practice for those
|
||||
products. If such problems arise substantially in other domains, we
|
||||
stand ready to extend this provision to those domains in future versions
|
||||
of the GPL, as needed to protect the freedom of users.
|
||||
|
||||
Finally, every program is threatened constantly by software patents.
|
||||
States should not allow patents to restrict development and use of
|
||||
software on general-purpose computers, but in those that do, we wish to
|
||||
avoid the special danger that patents applied to a free program could
|
||||
make it effectively proprietary. To prevent this, the GPL assures that
|
||||
patents cannot be used to render the program non-free.
|
||||
|
||||
The precise terms and conditions for copying, distribution and
|
||||
modification follow.
|
||||
|
||||
TERMS AND CONDITIONS
|
||||
|
||||
0. Definitions.
|
||||
|
||||
"This License" refers to version 3 of the GNU General Public License.
|
||||
|
||||
"Copyright" also means copyright-like laws that apply to other kinds of
|
||||
works, such as semiconductor masks.
|
||||
|
||||
"The Program" refers to any copyrightable work licensed under this
|
||||
License. Each licensee is addressed as "you". "Licensees" and
|
||||
"recipients" may be individuals or organizations.
|
||||
|
||||
To "modify" a work means to copy from or adapt all or part of the work
|
||||
in a fashion requiring copyright permission, other than the making of an
|
||||
exact copy. The resulting work is called a "modified version" of the
|
||||
earlier work or a work "based on" the earlier work.
|
||||
|
||||
A "covered work" means either the unmodified Program or a work based
|
||||
on the Program.
|
||||
|
||||
To "propagate" a work means to do anything with it that, without
|
||||
permission, would make you directly or secondarily liable for
|
||||
infringement under applicable copyright law, except executing it on a
|
||||
computer or modifying a private copy. Propagation includes copying,
|
||||
distribution (with or without modification), making available to the
|
||||
public, and in some countries other activities as well.
|
||||
|
||||
To "convey" a work means any kind of propagation that enables other
|
||||
parties to make or receive copies. Mere interaction with a user through
|
||||
a computer network, with no transfer of a copy, is not conveying.
|
||||
|
||||
An interactive user interface displays "Appropriate Legal Notices"
|
||||
to the extent that it includes a convenient and prominently visible
|
||||
feature that (1) displays an appropriate copyright notice, and (2)
|
||||
tells the user that there is no warranty for the work (except to the
|
||||
extent that warranties are provided), that licensees may convey the
|
||||
work under this License, and how to view a copy of this License. If
|
||||
the interface presents a list of user commands or options, such as a
|
||||
menu, a prominent item in the list meets this criterion.
|
||||
|
||||
1. Source Code.
|
||||
|
||||
The "source code" for a work means the preferred form of the work
|
||||
for making modifications to it. "Object code" means any non-source
|
||||
form of a work.
|
||||
|
||||
A "Standard Interface" means an interface that either is an official
|
||||
standard defined by a recognized standards body, or, in the case of
|
||||
interfaces specified for a particular programming language, one that
|
||||
is widely used among developers working in that language.
|
||||
|
||||
The "System Libraries" of an executable work include anything, other
|
||||
than the work as a whole, that (a) is included in the normal form of
|
||||
packaging a Major Component, but which is not part of that Major
|
||||
Component, and (b) serves only to enable use of the work with that
|
||||
Major Component, or to implement a Standard Interface for which an
|
||||
implementation is available to the public in source code form. A
|
||||
"Major Component", in this context, means a major essential component
|
||||
(kernel, window system, and so on) of the specific operating system
|
||||
(if any) on which the executable work runs, or a compiler used to
|
||||
produce the work, or an object code interpreter used to run it.
|
||||
|
||||
The "Corresponding Source" for a work in object code form means all
|
||||
the source code needed to generate, install, and (for an executable
|
||||
work) run the object code and to modify the work, including scripts to
|
||||
control those activities. However, it does not include the work's
|
||||
System Libraries, or general-purpose tools or generally available free
|
||||
programs which are used unmodified in performing those activities but
|
||||
which are not part of the work. For example, Corresponding Source
|
||||
includes interface definition files associated with source files for
|
||||
the work, and the source code for shared libraries and dynamically
|
||||
linked subprograms that the work is specifically designed to require,
|
||||
such as by intimate data communication or control flow between those
|
||||
subprograms and other parts of the work.
|
||||
|
||||
The Corresponding Source need not include anything that users
|
||||
can regenerate automatically from other parts of the Corresponding
|
||||
Source.
|
||||
|
||||
The Corresponding Source for a work in source code form is that
|
||||
same work.
|
||||
|
||||
2. Basic Permissions.
|
||||
|
||||
All rights granted under this License are granted for the term of
|
||||
copyright on the Program, and are irrevocable provided the stated
|
||||
conditions are met. This License explicitly affirms your unlimited
|
||||
permission to run the unmodified Program. The output from running a
|
||||
covered work is covered by this License only if the output, given its
|
||||
content, constitutes a covered work. This License acknowledges your
|
||||
rights of fair use or other equivalent, as provided by copyright law.
|
||||
|
||||
You may make, run and propagate covered works that you do not
|
||||
convey, without conditions so long as your license otherwise remains
|
||||
in force. You may convey covered works to others for the sole purpose
|
||||
of having them make modifications exclusively for you, or provide you
|
||||
with facilities for running those works, provided that you comply with
|
||||
the terms of this License in conveying all material for which you do
|
||||
not control copyright. Those thus making or running the covered works
|
||||
for you must do so exclusively on your behalf, under your direction
|
||||
and control, on terms that prohibit them from making any copies of
|
||||
your copyrighted material outside their relationship with you.
|
||||
|
||||
Conveying under any other circumstances is permitted solely under
|
||||
the conditions stated below. Sublicensing is not allowed; section 10
|
||||
makes it unnecessary.
|
||||
|
||||
3. Protecting Users' Legal Rights From Anti-Circumvention Law.
|
||||
|
||||
No covered work shall be deemed part of an effective technological
|
||||
measure under any applicable law fulfilling obligations under article
|
||||
11 of the WIPO copyright treaty adopted on 20 December 1996, or
|
||||
similar laws prohibiting or restricting circumvention of such
|
||||
measures.
|
||||
|
||||
When you convey a covered work, you waive any legal power to forbid
|
||||
circumvention of technological measures to the extent such circumvention
|
||||
is effected by exercising rights under this License with respect to
|
||||
the covered work, and you disclaim any intention to limit operation or
|
||||
modification of the work as a means of enforcing, against the work's
|
||||
users, your or third parties' legal rights to forbid circumvention of
|
||||
technological measures.
|
||||
|
||||
4. Conveying Verbatim Copies.
|
||||
|
||||
You may convey verbatim copies of the Program's source code as you
|
||||
receive it, in any medium, provided that you conspicuously and
|
||||
appropriately publish on each copy an appropriate copyright notice;
|
||||
keep intact all notices stating that this License and any
|
||||
non-permissive terms added in accord with section 7 apply to the code;
|
||||
keep intact all notices of the absence of any warranty; and give all
|
||||
recipients a copy of this License along with the Program.
|
||||
|
||||
You may charge any price or no price for each copy that you convey,
|
||||
and you may offer support or warranty protection for a fee.
|
||||
|
||||
5. Conveying Modified Source Versions.
|
||||
|
||||
You may convey a work based on the Program, or the modifications to
|
||||
produce it from the Program, in the form of source code under the
|
||||
terms of section 4, provided that you also meet all of these conditions:
|
||||
|
||||
a) The work must carry prominent notices stating that you modified
|
||||
it, and giving a relevant date.
|
||||
|
||||
b) The work must carry prominent notices stating that it is
|
||||
released under this License and any conditions added under section
|
||||
7. This requirement modifies the requirement in section 4 to
|
||||
"keep intact all notices".
|
||||
|
||||
c) You must license the entire work, as a whole, under this
|
||||
License to anyone who comes into possession of a copy. This
|
||||
License will therefore apply, along with any applicable section 7
|
||||
additional terms, to the whole of the work, and all its parts,
|
||||
regardless of how they are packaged. This License gives no
|
||||
permission to license the work in any other way, but it does not
|
||||
invalidate such permission if you have separately received it.
|
||||
|
||||
d) If the work has interactive user interfaces, each must display
|
||||
Appropriate Legal Notices; however, if the Program has interactive
|
||||
interfaces that do not display Appropriate Legal Notices, your
|
||||
work need not make them do so.
|
||||
|
||||
A compilation of a covered work with other separate and independent
|
||||
works, which are not by their nature extensions of the covered work,
|
||||
and which are not combined with it such as to form a larger program,
|
||||
in or on a volume of a storage or distribution medium, is called an
|
||||
"aggregate" if the compilation and its resulting copyright are not
|
||||
used to limit the access or legal rights of the compilation's users
|
||||
beyond what the individual works permit. Inclusion of a covered work
|
||||
in an aggregate does not cause this License to apply to the other
|
||||
parts of the aggregate.
|
||||
|
||||
6. Conveying Non-Source Forms.
|
||||
|
||||
You may convey a covered work in object code form under the terms
|
||||
of sections 4 and 5, provided that you also convey the
|
||||
machine-readable Corresponding Source under the terms of this License,
|
||||
in one of these ways:
|
||||
|
||||
a) Convey the object code in, or embodied in, a physical product
|
||||
(including a physical distribution medium), accompanied by the
|
||||
Corresponding Source fixed on a durable physical medium
|
||||
customarily used for software interchange.
|
||||
|
||||
b) Convey the object code in, or embodied in, a physical product
|
||||
(including a physical distribution medium), accompanied by a
|
||||
written offer, valid for at least three years and valid for as
|
||||
long as you offer spare parts or customer support for that product
|
||||
model, to give anyone who possesses the object code either (1) a
|
||||
copy of the Corresponding Source for all the software in the
|
||||
product that is covered by this License, on a durable physical
|
||||
medium customarily used for software interchange, for a price no
|
||||
more than your reasonable cost of physically performing this
|
||||
conveying of source, or (2) access to copy the
|
||||
Corresponding Source from a network server at no charge.
|
||||
|
||||
c) Convey individual copies of the object code with a copy of the
|
||||
written offer to provide the Corresponding Source. This
|
||||
alternative is allowed only occasionally and noncommercially, and
|
||||
only if you received the object code with such an offer, in accord
|
||||
with subsection 6b.
|
||||
|
||||
d) Convey the object code by offering access from a designated
|
||||
place (gratis or for a charge), and offer equivalent access to the
|
||||
Corresponding Source in the same way through the same place at no
|
||||
further charge. You need not require recipients to copy the
|
||||
Corresponding Source along with the object code. If the place to
|
||||
copy the object code is a network server, the Corresponding Source
|
||||
may be on a different server (operated by you or a third party)
|
||||
that supports equivalent copying facilities, provided you maintain
|
||||
clear directions next to the object code saying where to find the
|
||||
Corresponding Source. Regardless of what server hosts the
|
||||
Corresponding Source, you remain obligated to ensure that it is
|
||||
available for as long as needed to satisfy these requirements.
|
||||
|
||||
e) Convey the object code using peer-to-peer transmission, provided
|
||||
you inform other peers where the object code and Corresponding
|
||||
Source of the work are being offered to the general public at no
|
||||
charge under subsection 6d.
|
||||
|
||||
A separable portion of the object code, whose source code is excluded
|
||||
from the Corresponding Source as a System Library, need not be
|
||||
included in conveying the object code work.
|
||||
|
||||
A "User Product" is either (1) a "consumer product", which means any
|
||||
tangible personal property which is normally used for personal, family,
|
||||
or household purposes, or (2) anything designed or sold for incorporation
|
||||
into a dwelling. In determining whether a product is a consumer product,
|
||||
doubtful cases shall be resolved in favor of coverage. For a particular
|
||||
product received by a particular user, "normally used" refers to a
|
||||
typical or common use of that class of product, regardless of the status
|
||||
of the particular user or of the way in which the particular user
|
||||
actually uses, or expects or is expected to use, the product. A product
|
||||
is a consumer product regardless of whether the product has substantial
|
||||
commercial, industrial or non-consumer uses, unless such uses represent
|
||||
the only significant mode of use of the product.
|
||||
|
||||
"Installation Information" for a User Product means any methods,
|
||||
procedures, authorization keys, or other information required to install
|
||||
and execute modified versions of a covered work in that User Product from
|
||||
a modified version of its Corresponding Source. The information must
|
||||
suffice to ensure that the continued functioning of the modified object
|
||||
code is in no case prevented or interfered with solely because
|
||||
modification has been made.
|
||||
|
||||
If you convey an object code work under this section in, or with, or
|
||||
specifically for use in, a User Product, and the conveying occurs as
|
||||
part of a transaction in which the right of possession and use of the
|
||||
User Product is transferred to the recipient in perpetuity or for a
|
||||
fixed term (regardless of how the transaction is characterized), the
|
||||
Corresponding Source conveyed under this section must be accompanied
|
||||
by the Installation Information. But this requirement does not apply
|
||||
if neither you nor any third party retains the ability to install
|
||||
modified object code on the User Product (for example, the work has
|
||||
been installed in ROM).
|
||||
|
||||
The requirement to provide Installation Information does not include a
|
||||
requirement to continue to provide support service, warranty, or updates
|
||||
for a work that has been modified or installed by the recipient, or for
|
||||
the User Product in which it has been modified or installed. Access to a
|
||||
network may be denied when the modification itself materially and
|
||||
adversely affects the operation of the network or violates the rules and
|
||||
protocols for communication across the network.
|
||||
|
||||
Corresponding Source conveyed, and Installation Information provided,
|
||||
in accord with this section must be in a format that is publicly
|
||||
documented (and with an implementation available to the public in
|
||||
source code form), and must require no special password or key for
|
||||
unpacking, reading or copying.
|
||||
|
||||
7. Additional Terms.
|
||||
|
||||
"Additional permissions" are terms that supplement the terms of this
|
||||
License by making exceptions from one or more of its conditions.
|
||||
Additional permissions that are applicable to the entire Program shall
|
||||
be treated as though they were included in this License, to the extent
|
||||
that they are valid under applicable law. If additional permissions
|
||||
apply only to part of the Program, that part may be used separately
|
||||
under those permissions, but the entire Program remains governed by
|
||||
this License without regard to the additional permissions.
|
||||
|
||||
When you convey a copy of a covered work, you may at your option
|
||||
remove any additional permissions from that copy, or from any part of
|
||||
it. (Additional permissions may be written to require their own
|
||||
removal in certain cases when you modify the work.) You may place
|
||||
additional permissions on material, added by you to a covered work,
|
||||
for which you have or can give appropriate copyright permission.
|
||||
|
||||
Notwithstanding any other provision of this License, for material you
|
||||
add to a covered work, you may (if authorized by the copyright holders of
|
||||
that material) supplement the terms of this License with terms:
|
||||
|
||||
a) Disclaiming warranty or limiting liability differently from the
|
||||
terms of sections 15 and 16 of this License; or
|
||||
|
||||
b) Requiring preservation of specified reasonable legal notices or
|
||||
author attributions in that material or in the Appropriate Legal
|
||||
Notices displayed by works containing it; or
|
||||
|
||||
c) Prohibiting misrepresentation of the origin of that material, or
|
||||
requiring that modified versions of such material be marked in
|
||||
reasonable ways as different from the original version; or
|
||||
|
||||
d) Limiting the use for publicity purposes of names of licensors or
|
||||
authors of the material; or
|
||||
|
||||
e) Declining to grant rights under trademark law for use of some
|
||||
trade names, trademarks, or service marks; or
|
||||
|
||||
f) Requiring indemnification of licensors and authors of that
|
||||
material by anyone who conveys the material (or modified versions of
|
||||
it) with contractual assumptions of liability to the recipient, for
|
||||
any liability that these contractual assumptions directly impose on
|
||||
those licensors and authors.
|
||||
|
||||
All other non-permissive additional terms are considered "further
|
||||
restrictions" within the meaning of section 10. If the Program as you
|
||||
received it, or any part of it, contains a notice stating that it is
|
||||
governed by this License along with a term that is a further
|
||||
restriction, you may remove that term. If a license document contains
|
||||
a further restriction but permits relicensing or conveying under this
|
||||
License, you may add to a covered work material governed by the terms
|
||||
of that license document, provided that the further restriction does
|
||||
not survive such relicensing or conveying.
|
||||
|
||||
If you add terms to a covered work in accord with this section, you
|
||||
must place, in the relevant source files, a statement of the
|
||||
additional terms that apply to those files, or a notice indicating
|
||||
where to find the applicable terms.
|
||||
|
||||
Additional terms, permissive or non-permissive, may be stated in the
|
||||
form of a separately written license, or stated as exceptions;
|
||||
the above requirements apply either way.
|
||||
|
||||
8. Termination.
|
||||
|
||||
You may not propagate or modify a covered work except as expressly
|
||||
provided under this License. Any attempt otherwise to propagate or
|
||||
modify it is void, and will automatically terminate your rights under
|
||||
this License (including any patent licenses granted under the third
|
||||
paragraph of section 11).
|
||||
|
||||
However, if you cease all violation of this License, then your
|
||||
license from a particular copyright holder is reinstated (a)
|
||||
provisionally, unless and until the copyright holder explicitly and
|
||||
finally terminates your license, and (b) permanently, if the copyright
|
||||
holder fails to notify you of the violation by some reasonable means
|
||||
prior to 60 days after the cessation.
|
||||
|
||||
Moreover, your license from a particular copyright holder is
|
||||
reinstated permanently if the copyright holder notifies you of the
|
||||
violation by some reasonable means, this is the first time you have
|
||||
received notice of violation of this License (for any work) from that
|
||||
copyright holder, and you cure the violation prior to 30 days after
|
||||
your receipt of the notice.
|
||||
|
||||
Termination of your rights under this section does not terminate the
|
||||
licenses of parties who have received copies or rights from you under
|
||||
this License. If your rights have been terminated and not permanently
|
||||
reinstated, you do not qualify to receive new licenses for the same
|
||||
material under section 10.
|
||||
|
||||
9. Acceptance Not Required for Having Copies.
|
||||
|
||||
You are not required to accept this License in order to receive or
|
||||
run a copy of the Program. Ancillary propagation of a covered work
|
||||
occurring solely as a consequence of using peer-to-peer transmission
|
||||
to receive a copy likewise does not require acceptance. However,
|
||||
nothing other than this License grants you permission to propagate or
|
||||
modify any covered work. These actions infringe copyright if you do
|
||||
not accept this License. Therefore, by modifying or propagating a
|
||||
covered work, you indicate your acceptance of this License to do so.
|
||||
|
||||
10. Automatic Licensing of Downstream Recipients.
|
||||
|
||||
Each time you convey a covered work, the recipient automatically
|
||||
receives a license from the original licensors, to run, modify and
|
||||
propagate that work, subject to this License. You are not responsible
|
||||
for enforcing compliance by third parties with this License.
|
||||
|
||||
An "entity transaction" is a transaction transferring control of an
|
||||
organization, or substantially all assets of one, or subdividing an
|
||||
organization, or merging organizations. If propagation of a covered
|
||||
work results from an entity transaction, each party to that
|
||||
transaction who receives a copy of the work also receives whatever
|
||||
licenses to the work the party's predecessor in interest had or could
|
||||
give under the previous paragraph, plus a right to possession of the
|
||||
Corresponding Source of the work from the predecessor in interest, if
|
||||
the predecessor has it or can get it with reasonable efforts.
|
||||
|
||||
You may not impose any further restrictions on the exercise of the
|
||||
rights granted or affirmed under this License. For example, you may
|
||||
not impose a license fee, royalty, or other charge for exercise of
|
||||
rights granted under this License, and you may not initiate litigation
|
||||
(including a cross-claim or counterclaim in a lawsuit) alleging that
|
||||
any patent claim is infringed by making, using, selling, offering for
|
||||
sale, or importing the Program or any portion of it.
|
||||
|
||||
11. Patents.
|
||||
|
||||
A "contributor" is a copyright holder who authorizes use under this
|
||||
License of the Program or a work on which the Program is based. The
|
||||
work thus licensed is called the contributor's "contributor version".
|
||||
|
||||
A contributor's "essential patent claims" are all patent claims
|
||||
owned or controlled by the contributor, whether already acquired or
|
||||
hereafter acquired, that would be infringed by some manner, permitted
|
||||
by this License, of making, using, or selling its contributor version,
|
||||
but do not include claims that would be infringed only as a
|
||||
consequence of further modification of the contributor version. For
|
||||
purposes of this definition, "control" includes the right to grant
|
||||
patent sublicenses in a manner consistent with the requirements of
|
||||
this License.
|
||||
|
||||
Each contributor grants you a non-exclusive, worldwide, royalty-free
|
||||
patent license under the contributor's essential patent claims, to
|
||||
make, use, sell, offer for sale, import and otherwise run, modify and
|
||||
propagate the contents of its contributor version.
|
||||
|
||||
In the following three paragraphs, a "patent license" is any express
|
||||
agreement or commitment, however denominated, not to enforce a patent
|
||||
(such as an express permission to practice a patent or covenant not to
|
||||
sue for patent infringement). To "grant" such a patent license to a
|
||||
party means to make such an agreement or commitment not to enforce a
|
||||
patent against the party.
|
||||
|
||||
If you convey a covered work, knowingly relying on a patent license,
|
||||
and the Corresponding Source of the work is not available for anyone
|
||||
to copy, free of charge and under the terms of this License, through a
|
||||
publicly available network server or other readily accessible means,
|
||||
then you must either (1) cause the Corresponding Source to be so
|
||||
available, or (2) arrange to deprive yourself of the benefit of the
|
||||
patent license for this particular work, or (3) arrange, in a manner
|
||||
consistent with the requirements of this License, to extend the patent
|
||||
license to downstream recipients. "Knowingly relying" means you have
|
||||
actual knowledge that, but for the patent license, your conveying the
|
||||
covered work in a country, or your recipient's use of the covered work
|
||||
in a country, would infringe one or more identifiable patents in that
|
||||
country that you have reason to believe are valid.
|
||||
|
||||
If, pursuant to or in connection with a single transaction or
|
||||
arrangement, you convey, or propagate by procuring conveyance of, a
|
||||
covered work, and grant a patent license to some of the parties
|
||||
receiving the covered work authorizing them to use, propagate, modify
|
||||
or convey a specific copy of the covered work, then the patent license
|
||||
you grant is automatically extended to all recipients of the covered
|
||||
work and works based on it.
|
||||
|
||||
A patent license is "discriminatory" if it does not include within
|
||||
the scope of its coverage, prohibits the exercise of, or is
|
||||
conditioned on the non-exercise of one or more of the rights that are
|
||||
specifically granted under this License. You may not convey a covered
|
||||
work if you are a party to an arrangement with a third party that is
|
||||
in the business of distributing software, under which you make payment
|
||||
to the third party based on the extent of your activity of conveying
|
||||
the work, and under which the third party grants, to any of the
|
||||
parties who would receive the covered work from you, a discriminatory
|
||||
patent license (a) in connection with copies of the covered work
|
||||
conveyed by you (or copies made from those copies), or (b) primarily
|
||||
for and in connection with specific products or compilations that
|
||||
contain the covered work, unless you entered into that arrangement,
|
||||
or that patent license was granted, prior to 28 March 2007.
|
||||
|
||||
Nothing in this License shall be construed as excluding or limiting
|
||||
any implied license or other defenses to infringement that may
|
||||
otherwise be available to you under applicable patent law.
|
||||
|
||||
12. No Surrender of Others' Freedom.
|
||||
|
||||
If conditions are imposed on you (whether by court order, agreement or
|
||||
otherwise) that contradict the conditions of this License, they do not
|
||||
excuse you from the conditions of this License. If you cannot convey a
|
||||
covered work so as to satisfy simultaneously your obligations under this
|
||||
License and any other pertinent obligations, then as a consequence you may
|
||||
not convey it at all. For example, if you agree to terms that obligate you
|
||||
to collect a royalty for further conveying from those to whom you convey
|
||||
the Program, the only way you could satisfy both those terms and this
|
||||
License would be to refrain entirely from conveying the Program.
|
||||
|
||||
13. Use with the GNU Affero General Public License.
|
||||
|
||||
Notwithstanding any other provision of this License, you have
|
||||
permission to link or combine any covered work with a work licensed
|
||||
under version 3 of the GNU Affero General Public License into a single
|
||||
combined work, and to convey the resulting work. The terms of this
|
||||
License will continue to apply to the part which is the covered work,
|
||||
but the special requirements of the GNU Affero General Public License,
|
||||
section 13, concerning interaction through a network will apply to the
|
||||
combination as such.
|
||||
|
||||
14. Revised Versions of this License.
|
||||
|
||||
The Free Software Foundation may publish revised and/or new versions of
|
||||
the GNU General Public License from time to time. Such new versions will
|
||||
be similar in spirit to the present version, but may differ in detail to
|
||||
address new problems or concerns.
|
||||
|
||||
Each version is given a distinguishing version number. If the
|
||||
Program specifies that a certain numbered version of the GNU General
|
||||
Public License "or any later version" applies to it, you have the
|
||||
option of following the terms and conditions either of that numbered
|
||||
version or of any later version published by the Free Software
|
||||
Foundation. If the Program does not specify a version number of the
|
||||
GNU General Public License, you may choose any version ever published
|
||||
by the Free Software Foundation.
|
||||
|
||||
If the Program specifies that a proxy can decide which future
|
||||
versions of the GNU General Public License can be used, that proxy's
|
||||
public statement of acceptance of a version permanently authorizes you
|
||||
to choose that version for the Program.
|
||||
|
||||
Later license versions may give you additional or different
|
||||
permissions. However, no additional obligations are imposed on any
|
||||
author or copyright holder as a result of your choosing to follow a
|
||||
later version.
|
||||
|
||||
15. Disclaimer of Warranty.
|
||||
|
||||
THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
|
||||
APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
|
||||
HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
|
||||
OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
|
||||
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
|
||||
IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
|
||||
ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
|
||||
|
||||
16. Limitation of Liability.
|
||||
|
||||
IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
|
||||
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
|
||||
THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
|
||||
GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
|
||||
USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
|
||||
DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
|
||||
PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
|
||||
EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
|
||||
SUCH DAMAGES.
|
||||
|
||||
17. Interpretation of Sections 15 and 16.
|
||||
|
||||
If the disclaimer of warranty and limitation of liability provided
|
||||
above cannot be given local legal effect according to their terms,
|
||||
reviewing courts shall apply local law that most closely approximates
|
||||
an absolute waiver of all civil liability in connection with the
|
||||
Program, unless a warranty or assumption of liability accompanies a
|
||||
copy of the Program in return for a fee.
|
||||
|
||||
END OF TERMS AND CONDITIONS
|
||||
|
||||
How to Apply These Terms to Your New Programs
|
||||
|
||||
If you develop a new program, and you want it to be of the greatest
|
||||
possible use to the public, the best way to achieve this is to make it
|
||||
free software which everyone can redistribute and change under these terms.
|
||||
|
||||
To do so, attach the following notices to the program. It is safest
|
||||
to attach them to the start of each source file to most effectively
|
||||
state the exclusion of warranty; and each file should have at least
|
||||
the "copyright" line and a pointer to where the full notice is found.
|
||||
|
||||
<one line to give the program's name and a brief idea of what it does.>
|
||||
Copyright (C) <year> <name of author>
|
||||
|
||||
This program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
Also add information on how to contact you by electronic and paper mail.
|
||||
|
||||
If the program does terminal interaction, make it output a short
|
||||
notice like this when it starts in an interactive mode:
|
||||
|
||||
<program> Copyright (C) <year> <name of author>
|
||||
This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
|
||||
This is free software, and you are welcome to redistribute it
|
||||
under certain conditions; type `show c' for details.
|
||||
|
||||
The hypothetical commands `show w' and `show c' should show the appropriate
|
||||
parts of the General Public License. Of course, your program's commands
|
||||
might be different; for a GUI interface, you would use an "about box".
|
||||
|
||||
You should also get your employer (if you work as a programmer) or school,
|
||||
if any, to sign a "copyright disclaimer" for the program, if necessary.
|
||||
For more information on this, and how to apply and follow the GNU GPL, see
|
||||
<http://www.gnu.org/licenses/>.
|
||||
|
||||
The GNU General Public License does not permit incorporating your program
|
||||
into proprietary programs. If your program is a subroutine library, you
|
||||
may consider it more useful to permit linking proprietary applications with
|
||||
the library. If this is what you want to do, use the GNU Lesser General
|
||||
Public License instead of this License. But first, please read
|
||||
<http://www.gnu.org/philosophy/why-not-lgpl.html>.
|
||||
330
COPYING.LESSER
Normal file
330
COPYING.LESSER
Normal file
@@ -0,0 +1,330 @@
|
||||
GNU LESSER GENERAL PUBLIC LICENSE
|
||||
Version 3, 29 June 2007
|
||||
|
||||
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
|
||||
Everyone is permitted to copy and distribute verbatim copies
|
||||
of this license document, but changing it is not allowed.
|
||||
|
||||
|
||||
This version of the GNU Lesser General Public License incorporates
|
||||
the terms and conditions of version 3 of the GNU General Public
|
||||
License, supplemented by the additional permissions listed below.
|
||||
|
||||
0. Additional Definitions.
|
||||
|
||||
As used herein, "this License" refers to version 3 of the GNU Lesser
|
||||
General Public License, and the "GNU GPL" refers to version 3 of the GNU
|
||||
General Public License.
|
||||
|
||||
"The Library" refers to a covered work governed by this License,
|
||||
other than an Application or a Combined Work as defined below.
|
||||
|
||||
An "Application" is any work that makes use of an interface provided
|
||||
by the Library, but which is not otherwise based on the Library.
|
||||
Defining a subclass of a class defined by the Library is deemed a mode
|
||||
of using an interface provided by the Library.
|
||||
|
||||
A "Combined Work" is a work produced by combining or linking an
|
||||
Application with the Library. The particular version of the Library
|
||||
with which the Combined Work was made is also called the "Linked
|
||||
Version".
|
||||
|
||||
The "Minimal Corresponding Source" for a Combined Work means the
|
||||
Corresponding Source for the Combined Work, excluding any source code
|
||||
for portions of the Combined Work that, considered in isolation, are
|
||||
based on the Application, and not on the Linked Version.
|
||||
|
||||
The "Corresponding Application Code" for a Combined Work means the
|
||||
object code and/or source code for the Application, including any data
|
||||
and utility programs needed for reproducing the Combined Work from the
|
||||
Application, but excluding the System Libraries of the Combined Work.
|
||||
|
||||
1. Exception to Section 3 of the GNU GPL.
|
||||
|
||||
You may convey a covered work under sections 3 and 4 of this License
|
||||
without being bound by section 3 of the GNU GPL.
|
||||
|
||||
2. Conveying Modified Versions.
|
||||
|
||||
If you modify a copy of the Library, and, in your modifications, a
|
||||
facility refers to a function or data to be supplied by an Application
|
||||
that uses the facility (other than as an argument passed when the
|
||||
facility is invoked), then you may convey a copy of the modified
|
||||
version:
|
||||
|
||||
a) under this License, provided that you make a good faith effort to
|
||||
ensure that, in the event an Application does not supply the
|
||||
function or data, the facility still operates, and performs
|
||||
whatever part of its purpose remains meaningful, or
|
||||
|
||||
b) under the GNU GPL, with none of the additional permissions of
|
||||
this License applicable to that copy.
|
||||
|
||||
3. Object Code Incorporating Material from Library Header Files.
|
||||
|
||||
The object code form of an Application may incorporate material from
|
||||
a header file that is part of the Library. You may convey such object
|
||||
code under terms of your choice, provided that, if the incorporated
|
||||
material is not limited to numerical parameters, data structure
|
||||
layouts and accessors, or small macros, inline functions and templates
|
||||
(ten or fewer lines in length), you do both of the following:
|
||||
|
||||
a) Give prominent notice with each copy of the object code that the
|
||||
Library is used in it and that the Library and its use are
|
||||
covered by this License.
|
||||
|
||||
b) Accompany the object code with a copy of the GNU GPL and this license
|
||||
document.
|
||||
|
||||
4. Combined Works.
|
||||
|
||||
You may convey a Combined Work under terms of your choice that,
|
||||
taken together, effectively do not restrict modification of the
|
||||
portions of the Library contained in the Combined Work and reverse
|
||||
engineering for debugging such modifications, if you also do each of
|
||||
the following:
|
||||
|
||||
a) Give prominent notice with each copy of the Combined Work that
|
||||
the Library is used in it and that the Library and its use are
|
||||
covered by this License.
|
||||
|
||||
b) Accompany the Combined Work with a copy of the GNU GPL and this license
|
||||
document.
|
||||
|
||||
c) For a Combined Work that displays copyright notices during
|
||||
execution, include the copyright notice for the Library among
|
||||
these notices, as well as a reference directing the user to the
|
||||
copies of the GNU GPL and this license document.
|
||||
|
||||
d) Do one of the following:
|
||||
|
||||
0) Convey the Minimal Corresponding Source under the terms of this
|
||||
License, and the Corresponding Application Code in a form
|
||||
suitable for, and under terms that permit, the user to
|
||||
recombine or relink the Application with a modified version of
|
||||
the Linked Version to produce a modified Combined Work, in the
|
||||
manner specified by section 6 of the GNU GPL for conveying
|
||||
Corresponding Source.
|
||||
|
||||
1) Use a suitable shared library mechanism for linking with the
|
||||
Library. A suitable mechanism is one that (a) uses at run time
|
||||
a copy of the Library already present on the user's computer
|
||||
system, and (b) will operate properly with a modified version
|
||||
of the Library that is interface-compatible with the Linked
|
||||
Version.
|
||||
|
||||
e) Provide Installation Information, but only if you would otherwise
|
||||
be required to provide such information under section 6 of the
|
||||
GNU GPL, and only to the extent that such information is
|
||||
necessary to install and execute a modified version of the
|
||||
Combined Work produced by recombining or relinking the
|
||||
Application with a modified version of the Linked Version. (If
|
||||
you use option 4d0, the Installation Information must accompany
|
||||
the Minimal Corresponding Source and Corresponding Application
|
||||
Code. If you use option 4d1, you must provide the Installation
|
||||
Information in the manner specified by section 6 of the GNU GPL
|
||||
for conveying Corresponding Source.)
|
||||
|
||||
5. Combined Libraries.
|
||||
|
||||
You may place library facilities that are a work based on the
|
||||
Library side by side in a single library together with other library
|
||||
facilities that are not Applications and are not covered by this
|
||||
License, and convey such a combined library under terms of your
|
||||
choice, if you do both of the following:
|
||||
|
||||
a) Accompany the combined library with a copy of the same work based
|
||||
on the Library, uncombined with any other library facilities,
|
||||
conveyed under the terms of this License.
|
||||
|
||||
b) Give prominent notice with the combined library that part of it
|
||||
is a work based on the Library, and explaining where to find the
|
||||
accompanying uncombined form of the same work.
|
||||
|
||||
6. Revised Versions of the GNU Lesser General Public License.
|
||||
|
||||
The Free Software Foundation may publish revised and/or new versions
|
||||
of the GNU Lesser General Public License from time to time. Such new
|
||||
versions will be similar in spirit to the present version, but may
|
||||
differ in detail to address new problems or concerns.
|
||||
|
||||
Each version is given a distinguishing version number. If the
|
||||
Library as you received it specifies that a certain numbered version
|
||||
of the GNU Lesser General Public License "or any later version"
|
||||
applies to it, you have the option of following the terms and
|
||||
conditions either of that published version or of any later version
|
||||
published by the Free Software Foundation. If the Library as you
|
||||
received it does not specify a version number of the GNU Lesser
|
||||
General Public License, you may choose any version of the GNU Lesser
|
||||
General Public License ever published by the Free Software Foundation.
|
||||
|
||||
If the Library as you received it specifies that a proxy can decide
|
||||
whether future versions of the GNU Lesser General Public License shall
|
||||
apply, that proxy's public statement of acceptance of any version is
|
||||
permanent authorization for you to choose that version for the
|
||||
Library.
|
||||
GNU LESSER GENERAL PUBLIC LICENSE
|
||||
Version 3, 29 June 2007
|
||||
|
||||
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
|
||||
Everyone is permitted to copy and distribute verbatim copies
|
||||
of this license document, but changing it is not allowed.
|
||||
|
||||
|
||||
This version of the GNU Lesser General Public License incorporates
|
||||
the terms and conditions of version 3 of the GNU General Public
|
||||
License, supplemented by the additional permissions listed below.
|
||||
|
||||
0. Additional Definitions.
|
||||
|
||||
As used herein, "this License" refers to version 3 of the GNU Lesser
|
||||
General Public License, and the "GNU GPL" refers to version 3 of the GNU
|
||||
General Public License.
|
||||
|
||||
"The Library" refers to a covered work governed by this License,
|
||||
other than an Application or a Combined Work as defined below.
|
||||
|
||||
An "Application" is any work that makes use of an interface provided
|
||||
by the Library, but which is not otherwise based on the Library.
|
||||
Defining a subclass of a class defined by the Library is deemed a mode
|
||||
of using an interface provided by the Library.
|
||||
|
||||
A "Combined Work" is a work produced by combining or linking an
|
||||
Application with the Library. The particular version of the Library
|
||||
with which the Combined Work was made is also called the "Linked
|
||||
Version".
|
||||
|
||||
The "Minimal Corresponding Source" for a Combined Work means the
|
||||
Corresponding Source for the Combined Work, excluding any source code
|
||||
for portions of the Combined Work that, considered in isolation, are
|
||||
based on the Application, and not on the Linked Version.
|
||||
|
||||
The "Corresponding Application Code" for a Combined Work means the
|
||||
object code and/or source code for the Application, including any data
|
||||
and utility programs needed for reproducing the Combined Work from the
|
||||
Application, but excluding the System Libraries of the Combined Work.
|
||||
|
||||
1. Exception to Section 3 of the GNU GPL.
|
||||
|
||||
You may convey a covered work under sections 3 and 4 of this License
|
||||
without being bound by section 3 of the GNU GPL.
|
||||
|
||||
2. Conveying Modified Versions.
|
||||
|
||||
If you modify a copy of the Library, and, in your modifications, a
|
||||
facility refers to a function or data to be supplied by an Application
|
||||
that uses the facility (other than as an argument passed when the
|
||||
facility is invoked), then you may convey a copy of the modified
|
||||
version:
|
||||
|
||||
a) under this License, provided that you make a good faith effort to
|
||||
ensure that, in the event an Application does not supply the
|
||||
function or data, the facility still operates, and performs
|
||||
whatever part of its purpose remains meaningful, or
|
||||
|
||||
b) under the GNU GPL, with none of the additional permissions of
|
||||
this License applicable to that copy.
|
||||
|
||||
3. Object Code Incorporating Material from Library Header Files.
|
||||
|
||||
The object code form of an Application may incorporate material from
|
||||
a header file that is part of the Library. You may convey such object
|
||||
code under terms of your choice, provided that, if the incorporated
|
||||
material is not limited to numerical parameters, data structure
|
||||
layouts and accessors, or small macros, inline functions and templates
|
||||
(ten or fewer lines in length), you do both of the following:
|
||||
|
||||
a) Give prominent notice with each copy of the object code that the
|
||||
Library is used in it and that the Library and its use are
|
||||
covered by this License.
|
||||
|
||||
b) Accompany the object code with a copy of the GNU GPL and this license
|
||||
document.
|
||||
|
||||
4. Combined Works.
|
||||
|
||||
You may convey a Combined Work under terms of your choice that,
|
||||
taken together, effectively do not restrict modification of the
|
||||
portions of the Library contained in the Combined Work and reverse
|
||||
engineering for debugging such modifications, if you also do each of
|
||||
the following:
|
||||
|
||||
a) Give prominent notice with each copy of the Combined Work that
|
||||
the Library is used in it and that the Library and its use are
|
||||
covered by this License.
|
||||
|
||||
b) Accompany the Combined Work with a copy of the GNU GPL and this license
|
||||
document.
|
||||
|
||||
c) For a Combined Work that displays copyright notices during
|
||||
execution, include the copyright notice for the Library among
|
||||
these notices, as well as a reference directing the user to the
|
||||
copies of the GNU GPL and this license document.
|
||||
|
||||
d) Do one of the following:
|
||||
|
||||
0) Convey the Minimal Corresponding Source under the terms of this
|
||||
License, and the Corresponding Application Code in a form
|
||||
suitable for, and under terms that permit, the user to
|
||||
recombine or relink the Application with a modified version of
|
||||
the Linked Version to produce a modified Combined Work, in the
|
||||
manner specified by section 6 of the GNU GPL for conveying
|
||||
Corresponding Source.
|
||||
|
||||
1) Use a suitable shared library mechanism for linking with the
|
||||
Library. A suitable mechanism is one that (a) uses at run time
|
||||
a copy of the Library already present on the user's computer
|
||||
system, and (b) will operate properly with a modified version
|
||||
of the Library that is interface-compatible with the Linked
|
||||
Version.
|
||||
|
||||
e) Provide Installation Information, but only if you would otherwise
|
||||
be required to provide such information under section 6 of the
|
||||
GNU GPL, and only to the extent that such information is
|
||||
necessary to install and execute a modified version of the
|
||||
Combined Work produced by recombining or relinking the
|
||||
Application with a modified version of the Linked Version. (If
|
||||
you use option 4d0, the Installation Information must accompany
|
||||
the Minimal Corresponding Source and Corresponding Application
|
||||
Code. If you use option 4d1, you must provide the Installation
|
||||
Information in the manner specified by section 6 of the GNU GPL
|
||||
for conveying Corresponding Source.)
|
||||
|
||||
5. Combined Libraries.
|
||||
|
||||
You may place library facilities that are a work based on the
|
||||
Library side by side in a single library together with other library
|
||||
facilities that are not Applications and are not covered by this
|
||||
License, and convey such a combined library under terms of your
|
||||
choice, if you do both of the following:
|
||||
|
||||
a) Accompany the combined library with a copy of the same work based
|
||||
on the Library, uncombined with any other library facilities,
|
||||
conveyed under the terms of this License.
|
||||
|
||||
b) Give prominent notice with the combined library that part of it
|
||||
is a work based on the Library, and explaining where to find the
|
||||
accompanying uncombined form of the same work.
|
||||
|
||||
6. Revised Versions of the GNU Lesser General Public License.
|
||||
|
||||
The Free Software Foundation may publish revised and/or new versions
|
||||
of the GNU Lesser General Public License from time to time. Such new
|
||||
versions will be similar in spirit to the present version, but may
|
||||
differ in detail to address new problems or concerns.
|
||||
|
||||
Each version is given a distinguishing version number. If the
|
||||
Library as you received it specifies that a certain numbered version
|
||||
of the GNU Lesser General Public License "or any later version"
|
||||
applies to it, you have the option of following the terms and
|
||||
conditions either of that published version or of any later version
|
||||
published by the Free Software Foundation. If the Library as you
|
||||
received it does not specify a version number of the GNU Lesser
|
||||
General Public License, you may choose any version of the GNU Lesser
|
||||
General Public License ever published by the Free Software Foundation.
|
||||
|
||||
If the Library as you received it specifies that a proxy can decide
|
||||
whether future versions of the GNU Lesser General Public License shall
|
||||
apply, that proxy's public statement of acceptance of any version is
|
||||
permanent authorization for you to choose that version for the
|
||||
Library.
|
||||
361
Makefile
Normal file
361
Makefile
Normal file
@@ -0,0 +1,361 @@
|
||||
# Makefile for Firebee BaS
|
||||
#
|
||||
# This Makefile is meant for cross compiling the BaS with Vincent Riviere's cross compilers.
|
||||
# If you want to compile native on an Atari (you will need at least GCC 4.6.3), set
|
||||
# TCPREFIX to be empty.
|
||||
#
|
||||
# If you want to compile with the m68k-elf- toolchain, set TCPREFIX accordingly. Requires an extra
|
||||
# installation, but allows source level debugging over BDM with a recent gdb (tested with 7.5),
|
||||
# the m68k BDM tools from sourceforge (http://bdm.sourceforge.net) and a BDM pod (TBLCF and P&E tested).
|
||||
|
||||
|
||||
ifneq (yes,$(VERBOSE))
|
||||
Q=@
|
||||
else
|
||||
Q=
|
||||
endif
|
||||
|
||||
# can be either "Y" or "N" (without quotes). "Y" for using the m68k-elf-, "N" for using the m68k-atari-mint
|
||||
# toolchain
|
||||
COMPILE_ELF=Y
|
||||
|
||||
ifeq (Y,$(COMPILE_ELF))
|
||||
TCPREFIX=m68k-elf-
|
||||
EXE=elf
|
||||
FORMAT=elf32-m68k
|
||||
else
|
||||
TCPREFIX=m68k-atari-mint-
|
||||
EXE=s19
|
||||
FORMAT=srec
|
||||
endif
|
||||
|
||||
CC=$(TCPREFIX)gcc
|
||||
LD=$(TCPREFIX)ld
|
||||
CPP=$(TCPREFIX)cpp
|
||||
OBJCOPY=$(TCPREFIX)objcopy
|
||||
AR=$(TCPREFIX)ar
|
||||
RANLIB=$(TCPREFIX)ranlib
|
||||
NATIVECC=gcc
|
||||
|
||||
ifeq (Y,$(COMPILE_ELF))
|
||||
LDLIBS=-lgcc
|
||||
else
|
||||
LDLIBS=-lgcc
|
||||
endif
|
||||
|
||||
INCLUDE=-Iinclude
|
||||
CFLAGS= -Wall \
|
||||
-O2 \
|
||||
-fomit-frame-pointer \
|
||||
-ffreestanding \
|
||||
-fno-strict-aliasing \
|
||||
-fleading-underscore \
|
||||
-Winline \
|
||||
-Wa,--register-prefix-optional
|
||||
|
||||
CFLAGS_OPTIMIZED = -mcpu=5474 \
|
||||
-Wall \
|
||||
-O2 \
|
||||
-fomit-frame-pointer \
|
||||
-ffreestanding \
|
||||
-fleading-underscore \
|
||||
-Wa,--register-prefix-optional
|
||||
LDFLAGS=
|
||||
|
||||
TRGTDIRS= ./firebee ./m54455 ./m5484lite
|
||||
OBJDIRS=$(patsubst %, %/objs,$(TRGTDIRS))
|
||||
TOOLDIR=util
|
||||
|
||||
VPATH=dma exe flash fs i2c if kbd pci spi sys usb net util video radeon x86emu xhdi
|
||||
|
||||
# Linker control file. The final $(LDCFILE) is intermediate only (preprocessed version of $(LDCSRC)
|
||||
LDCFILE=bas.lk
|
||||
LDRFILE=ram.lk
|
||||
LDCSRC=bas.lk.in
|
||||
LDCBSRC=basflash.lk.in
|
||||
LDCBFS=basflash.lk
|
||||
|
||||
# this Makefile can create the BaS to flash or an arbitrary ram address (for BDM debugging). See
|
||||
# below for the definition of TARGET_ADDRESS
|
||||
FLASH_EXEC=bas.$(EXE)
|
||||
RAM_EXEC=ram.$(EXE)
|
||||
BASFLASH_EXEC=basflash.$(EXE)
|
||||
|
||||
CSRCS= \
|
||||
sysinit.c \
|
||||
init_fpga.c \
|
||||
fault_vectors.c \
|
||||
interrupts.c \
|
||||
\
|
||||
bas_printf.c \
|
||||
bas_string.c \
|
||||
conout.c \
|
||||
\
|
||||
BaS.c \
|
||||
cache.c \
|
||||
mmu.c \
|
||||
mmc.c \
|
||||
unicode.c \
|
||||
ff.c \
|
||||
sd_card.c \
|
||||
wait.c \
|
||||
s19reader.c \
|
||||
flash.c \
|
||||
dma.c \
|
||||
i2c.c \
|
||||
xhdi_sd.c \
|
||||
xhdi_interface.c \
|
||||
pci.c \
|
||||
pci_errata.c \
|
||||
dspi.c \
|
||||
driver_vec.c \
|
||||
driver_mem.c \
|
||||
\
|
||||
MCD_dmaApi.c \
|
||||
MCD_tasks.c \
|
||||
MCD_tasksInit.c \
|
||||
\
|
||||
usb.c \
|
||||
ohci-hcd.c \
|
||||
ehci-hcd.c \
|
||||
usb_hub.c \
|
||||
usb_mouse.c \
|
||||
usb_kbd.c \
|
||||
ikbd.c \
|
||||
\
|
||||
nbuf.c \
|
||||
queue.c \
|
||||
net_timer.c \
|
||||
am79c874.c \
|
||||
bcm5222.c \
|
||||
nif.c \
|
||||
fecbd.c \
|
||||
fec.c \
|
||||
ip.c \
|
||||
udp.c \
|
||||
arp.c \
|
||||
bootp.c \
|
||||
tftp.c \
|
||||
\
|
||||
fbmem.c \
|
||||
fbmon.c \
|
||||
fbmodedb.c \
|
||||
offscreen.c \
|
||||
\
|
||||
videl.c \
|
||||
video.c \
|
||||
\
|
||||
i2c-algo-bit.c \
|
||||
\
|
||||
radeon_base.c \
|
||||
radeon_accel.c \
|
||||
radeon_cursor.c \
|
||||
radeon_monitor.c \
|
||||
radeon_i2c.c \
|
||||
fnt_st_8x16.c \
|
||||
\
|
||||
x86emu.c \
|
||||
x86pcibios.c \
|
||||
x86biosemu.c \
|
||||
x86emu_util.c \
|
||||
\
|
||||
basflash.c \
|
||||
basflash_start.c
|
||||
|
||||
|
||||
ASRCS= \
|
||||
startcf.S \
|
||||
exceptions.S \
|
||||
setjmp.S \
|
||||
xhdi_vec.S \
|
||||
pci_wrappers.S
|
||||
|
||||
ifeq (Y,$(COMPILE_ELF)) # needed for __ vs ___ kludge
|
||||
ASRCS += libgcc_helper.S
|
||||
endif
|
||||
|
||||
SRCS=$(ASRCS) $(CSRCS)
|
||||
COBJS=$(patsubst %.c,%.o,$(CSRCS))
|
||||
AOBJS=$(patsubst %.S,%.o,$(ASRCS))
|
||||
|
||||
OBJS=$(COBJS) $(AOBJS)
|
||||
LIBBAS=libbas.a
|
||||
|
||||
LIBS=$(patsubst %,%/$(LIBBAS),$(TRGTDIRS))
|
||||
|
||||
all: ver fls ram bfl lib tos
|
||||
fls: $(patsubst %,%/$(FLASH_EXEC),$(TRGTDIRS))
|
||||
ram: $(patsubst %,%/$(RAM_EXEC),$(TRGTDIRS))
|
||||
bfl: $(patsubst %,%/$(BASFLASH_EXEC),$(TRGTDIRS))
|
||||
lib: $(LIBS)
|
||||
|
||||
.PHONY: ver
|
||||
ver:
|
||||
touch include/version.h
|
||||
|
||||
.PHONY: tos
|
||||
tos:
|
||||
$(Q)(cd tos; $(MAKE) -s)
|
||||
|
||||
.PHONY: clean
|
||||
clean:
|
||||
$(Q)for d in $(TRGTDIRS);\
|
||||
do rm -f $$d/*.map $$d/*.s19 $$d/*.elf $$d/*.lk $$d/*.a $$d/objs/* $$d/depend;\
|
||||
done
|
||||
$(Q)rm -f tags
|
||||
$(Q)(cd tos; make -s clean)
|
||||
|
||||
|
||||
|
||||
# flags for targets
|
||||
m5484lite/bas.$(EXE): MACHINE=MACHINE_M5484LITE
|
||||
m54455/bas.$(EXE): MACHINE=MACHINE_M54455
|
||||
firebee/bas.$(EXE): MACHINE=MACHINE_FIREBEE
|
||||
|
||||
m5484lite/ram.$(EXE): MACHINE=MACHINE_M5484LITE
|
||||
m54455/ram.$(EXE): MACHINE=MACHINE_M54455
|
||||
firebee/ram.$(EXE): MACHINE=MACHINE_FIREBEE
|
||||
|
||||
m5484lite/basflash.$(EXE): MACHINE=MACHINE_M5484LITE
|
||||
m54455/basflash.$(EXE): MACHINE=MACHINE_M54455
|
||||
firebee/basflash.$(EXE): MACHINE=MACHINE_FIREBEE
|
||||
|
||||
m5484lite/bas.$(EXE): CFLAGS += -mcpu=5484
|
||||
m54455/bas.$(EXE): CFLAGS += -mcpu=54455 -msoft-float
|
||||
firebee/bas.$(EXE): CFLAGS += -mcpu=5474
|
||||
|
||||
m5484lite/ram.$(EXE): CFLAGS += -mcpu=5484
|
||||
m54455/ram.$(EXE): CFLAGS += -mcpu=54455 -msoft-float
|
||||
firebee/ram.$(EXE): CFLAGS += -mcpu=5474
|
||||
|
||||
m5484lite/basflash.$(EXE): CFLAGS += -mcpu=5484
|
||||
m54455/basflash.$(EXE): CFLAGS += -mcpu=54455 -msoft-float
|
||||
firebee/basflash.$(EXE): CFLAGS += -mcpu=5474
|
||||
|
||||
#
|
||||
# generate pattern rules for different object files
|
||||
#
|
||||
define CC_TEMPLATE
|
||||
$(1)/objs/%.o:%.c
|
||||
$(Q)echo CC $$<
|
||||
$(Q)$(CC) $$(CFLAGS) -D$$(MACHINE) $(INCLUDE) -c $$< -o $$@
|
||||
|
||||
$(1)/objs/%.o:%.S
|
||||
$(Q)echo CC $$<
|
||||
$(Q)$(CC) $$(CFLAGS) -Wa,--bitwise-or -D$$(MACHINE) $(INCLUDE) -c $$< -o $$@
|
||||
endef
|
||||
$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
|
||||
|
||||
# rules for depend
|
||||
define DEP_TEMPLATE
|
||||
ifneq (clean,$$(MAKECMDGOALS))
|
||||
include $(1)/depend
|
||||
endif
|
||||
|
||||
ifeq (firebee,$(1))
|
||||
MACHINE=MACHINE_FIREBEE
|
||||
else
|
||||
MACHINE=MACHINE_M5484LITE
|
||||
endif
|
||||
$(1)/depend:$(SRCS)
|
||||
$(Q)echo DEPEND
|
||||
$(Q)$(CC) $$(CFLAGS) -D$$(MACHINE) $(INCLUDE) -M $$^ | sed -e "s#^\(.*\).o:#"$(1)"/objs/\1.o:#" > $$@
|
||||
endef
|
||||
$(foreach DIR,$(TRGTDIRS),$(eval $(call DEP_TEMPLATE,$(DIR))))
|
||||
|
||||
|
||||
#
|
||||
# generate pattern rules for libraries
|
||||
#
|
||||
define AR_TEMPLATE
|
||||
$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
|
||||
$(1)/$(LIBBAS): $$($(1)_OBJS)
|
||||
$(Q)echo AR $$@
|
||||
$(Q)$(AR) r $$@ $$?
|
||||
$(Q)$(RANLIB) $$@
|
||||
endef
|
||||
$(foreach DIR,$(TRGTDIRS),$(eval $(call AR_TEMPLATE,$(DIR))))
|
||||
|
||||
ifeq ($(COMPILE_ELF),Y)
|
||||
FORMAT_ELF=1
|
||||
else
|
||||
FORMAT_ELF=0
|
||||
endif
|
||||
|
||||
define LK_TEMPLATE
|
||||
$(1)/$$(LDCFILE): $(LDCSRC)
|
||||
$(Q)echo CPP $$<
|
||||
$(Q)$(CPP) $(INCLUDE) -DOBJDIR=$(1)/objs -P -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $$< -o $$@
|
||||
endef
|
||||
$(foreach DIR,$(TRGTDIRS),$(eval $(call LK_TEMPLATE,$(DIR))))
|
||||
|
||||
#
|
||||
# define pattern rules for binaries
|
||||
#
|
||||
define EX_TEMPLATE
|
||||
# pattern rule for flash
|
||||
$(1)_MAPFILE=$(1)/$$(basename $$(FLASH_EXEC)).map
|
||||
$(1)/$$(FLASH_EXEC): $(1)/$(LIBBAS) $(1)/$$(LDCFILE)
|
||||
$(Q)echo CC $$@
|
||||
$(Q)$(CC) $$(CFLAGS) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDCFILE) $(LDLIBS) -o $$@
|
||||
ifeq ($(COMPILE_ELF),Y)
|
||||
$(Q)echo OBJCOPY $$@
|
||||
$(Q)$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
|
||||
else
|
||||
$(Q)echo OBJCOPY $$@
|
||||
$(Q)objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf
|
||||
endif
|
||||
|
||||
# pattern rule for RAM
|
||||
$(1)_MAPFILE_RAM=$(1)/$$(basename $$(RAM_EXEC)).map
|
||||
$(1)/$$(RAM_EXEC): $(1)/$(LIBBAS) $(1)/$$(LDCFILE)
|
||||
$(Q)echo CPP $$@
|
||||
$(Q)$(CPP) $(INCLUDE) -DCOMPILE_RAM -DOBJDIR=$(1)/objs -P -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCSRC) -o $(1)/$$(LDRFILE)
|
||||
$(Q)echo CC $$@
|
||||
$(Q)$(CC) $$(CFLAGS) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE_RAM) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDRFILE) $(LDLIBS) -o $$@
|
||||
ifeq ($(COMPILE_ELF),Y)
|
||||
$(Q)echo OBJCOPY $$@
|
||||
$(Q)$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
|
||||
else
|
||||
$(Q)echo OBJCOPY $$<
|
||||
$(Q)objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf
|
||||
endif
|
||||
|
||||
# pattern rule for basflash
|
||||
$(1)_MAPFILE_BFL=$(1)/$$(basename $$(BASFLASH_EXEC)).map
|
||||
$(1)/$$(BASFLASH_EXEC): $(1)/objs/basflash.o $(1)/objs/basflash_start.o $(1)/$(LIBBAS) $(LDCBFL)
|
||||
$(Q)echo CPP $$<
|
||||
$(CPP) $(INCLUDE) -P -DOBJDIR=$(1)/objs -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCBSRC) -o $(1)/$$(LDCBFS)
|
||||
$(Q)echo CC $$<
|
||||
$(Q)$(CC) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE_BFL) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDCBFS) -L$(1) -lbas $(LDLIBS) -o $$@
|
||||
ifeq ($(COMPILE_ELF),Y)
|
||||
$(Q)echo OBJCOPY $$<
|
||||
$(Q)$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
|
||||
else
|
||||
$(Q)echo OBJCOPY $$<
|
||||
$(Q)objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf
|
||||
endif
|
||||
endef
|
||||
$(foreach DIR,$(TRGTDIRS),$(eval $(call EX_TEMPLATE,$(DIR))))
|
||||
|
||||
|
||||
indent: $(CSRCS)
|
||||
indent $<
|
||||
|
||||
.PHONY: tags
|
||||
tags:
|
||||
ctags $(patsubst %,%/*,$(VPATH))
|
||||
|
||||
.PHONY: printvars
|
||||
printvars:
|
||||
$(Q)$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
|
||||
ifeq (MACHINE_M5484LITE,$$(MACHINE))
|
||||
MNAME=m5484lite
|
||||
else ifeq (MACHINE_FIREBEE,$(MACHINE))
|
||||
MNAME=firebee
|
||||
endif
|
||||
|
||||
tools:
|
||||
$(NATIVECC) $(INCLUDE) -c $(TOOLDIR)/s19header.c -o $(TOOLDIR)/s19header.o
|
||||
$(NATIVECC) -o $(TOOLDIR)/s19header $(TOOLDIR)/s19header.o
|
||||
|
||||
68
bas_firebee.bdm
Executable file
68
bas_firebee.bdm
Executable file
@@ -0,0 +1,68 @@
|
||||
#!/usr/local/bin/bdmctrl -D2 -v9 -d9
|
||||
#
|
||||
# firebee board initialization for bdmctrl
|
||||
#
|
||||
open $1
|
||||
reset
|
||||
sleep 10
|
||||
|
||||
# Turn on MBAR at 0xFF00_0000
|
||||
write-ctrl 0x0C0F 0xFF000000
|
||||
|
||||
# set VBR
|
||||
write-ctrl 0x0801 0x00000000
|
||||
|
||||
# Turn on RAMBAR0 at address FF10_0000
|
||||
write-ctrl 0x0C04 0xFF100007
|
||||
|
||||
# Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently)
|
||||
write-ctrl 0x0C05 0xFF101001
|
||||
|
||||
# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
|
||||
write 0xFF000500 0xE0000000 4
|
||||
write 0xFF000508 0x00041180 4
|
||||
write 0xFF000504 0x007F0001 4
|
||||
wait
|
||||
|
||||
# Init CS1 (Atari I/O address range)
|
||||
write 0xFF00050C 0xFFF00000 4
|
||||
write 0xFF000514 0x00002180 4
|
||||
write 0xFF000510 0x000F0001 4
|
||||
# Init CS2 (FireBee 32 bit I/O address range)
|
||||
write 0xFF000518 0xF0000000 4
|
||||
write 0xFF000520 0x00002100 4
|
||||
write 0xFF00051C 0x07FF0001 4
|
||||
# Init CS3 (FireBee 16 bit I/O address range)
|
||||
write 0xFF000524 0xF8000000 4
|
||||
write 0xFF00052C 0x00000180 4
|
||||
write 0xFF000528 0x03FF0001 4
|
||||
# Init CS4 (FireBee video address range)
|
||||
write 0xFF000530 0x40000000 4
|
||||
write 0xFF000538 0x00000018 4
|
||||
write 0xFF000534 0x003F0001 4
|
||||
|
||||
|
||||
# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
|
||||
write 0xFF000004 0x000002AA 4 # SDRAMDS configuration
|
||||
write 0xFF000020 0x0000001A 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
|
||||
write 0xFF000024 0x0800001A 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
|
||||
write 0xFF000028 0x1000001A 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
|
||||
write 0xFF00002C 0x1800001A 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
|
||||
write 0xFF000108 0x73622830 4 # SDCFG1
|
||||
write 0xFF00010C 0x46770000 4 # SDCFG2
|
||||
|
||||
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
|
||||
write 0xFF000100 0x40010000 4 # SDMR (write to LEMR)
|
||||
write 0xFF000100 0x048D0000 4 # SDMR (write to LMR)
|
||||
sleep 100
|
||||
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
|
||||
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
|
||||
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
|
||||
write 0xFF000100 0x008D0000 4 # SDMR (write to LMR)
|
||||
write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
|
||||
sleep 100
|
||||
|
||||
load -v firebee/ram.elf
|
||||
|
||||
execute
|
||||
wait
|
||||
56
bas_m5484.bdm
Executable file
56
bas_m5484.bdm
Executable file
@@ -0,0 +1,56 @@
|
||||
#!/usr/local/bin/bdmctrl -D2 -v9 -d9
|
||||
#
|
||||
# firebee board initialization for bdmctrl
|
||||
#
|
||||
open $1
|
||||
reset
|
||||
sleep 10
|
||||
|
||||
wait
|
||||
|
||||
# set VBR
|
||||
write-ctrl 0x0801 0x00000000
|
||||
dump-register VBR
|
||||
|
||||
# Turn on MBAR at 0xFF00_0000
|
||||
write-ctrl 0x0C0F 0xFF000000
|
||||
dump-register MBAR
|
||||
|
||||
# Turn on RAMBAR0 at address FF10_0000
|
||||
write-ctrl 0x0C04 0xFF100007
|
||||
|
||||
# Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently)
|
||||
write-ctrl 0x0C05 0xFF101001
|
||||
|
||||
# Init CS0 (BootFLASH @ E000_0000 - E03F_FFFF 8Mbytes)
|
||||
write 0xFF000500 0xE0000000 4
|
||||
write 0xFF000508 0x00041180 4
|
||||
write 0xFF000504 0x003F0001 4
|
||||
wait
|
||||
|
||||
# SDRAM Initialization @ 0000_0000 - 0400_0000 64 MBytes
|
||||
write 0xFF000004 0x000002AA 4 # SDRAMDS configuration
|
||||
write 0xFF000020 0x00000019 4 # SDRAM CS0 configuration (64Mbytes 0000_0000 - 07FF_FFFF)
|
||||
write 0xFF000024 0x00000000 4 # SDRAM CS1 configuration
|
||||
write 0xFF000028 0x00000000 4 # SDRAM CS2 configuration
|
||||
write 0xFF00002C 0x00000000 4 # SDRAM CS3 configuration
|
||||
|
||||
write 0xFF000108 0x73711630 4 # SDCFG1
|
||||
write 0xFF00010C 0x46370000 4 # SDCFG2
|
||||
|
||||
write 0xFF000104 0xE10B0002 4 # SDCR + IPALL
|
||||
write 0xFF000100 0x40010000 4 # SDMR (write to LEMR)
|
||||
write 0xFF000100 0x058D0000 4 # SDMR (write to LMR)
|
||||
sleep 100
|
||||
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
|
||||
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
|
||||
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
|
||||
write 0xFF000100 0x018D0000 4 # SDMR (write to LMR)
|
||||
write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
|
||||
sleep 100
|
||||
|
||||
load -v m5484lite/ram.elf
|
||||
execute
|
||||
# wait is _needed_ here if using the P&E BDM interface. Otherwise
|
||||
# the Coldfire resets after some time!
|
||||
wait
|
||||
115
basflash.lk.in
Normal file
115
basflash.lk.in
Normal file
@@ -0,0 +1,115 @@
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
#include "firebee.h"
|
||||
#elif defined(MACHINE_M5484LITE)
|
||||
#include "m5484l.h"
|
||||
#elif defined(MACHINE_M54455)
|
||||
#include "m54455.h"
|
||||
#else
|
||||
#error unknown machine
|
||||
#endif
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flasher (WX) : ORIGIN = BFL_TARGET_ADDRESS, LENGTH = 0x00100000 /* target to load basflash */
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
OBJDIR/basflash_start.o(.text)
|
||||
OBJDIR/basflash.o(.text)
|
||||
|
||||
*(.data)
|
||||
*(.bss)
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
} > flasher
|
||||
|
||||
.bas :
|
||||
{
|
||||
}
|
||||
|
||||
#define BAS_LABEL_LMA(x) ((x))
|
||||
/* _xprintf_before_copy = BAS_LABEL_LMA(_xprintf); */
|
||||
/* _display_progress_before_copy = BAS_LABEL_LMA(_display_progress); */
|
||||
/* _flush_and_invalidate_caches_before_copy = BAS_LABEL_LMA(_flush_and_invalidate_caches); */
|
||||
|
||||
/*
|
||||
* Global memory map
|
||||
*/
|
||||
|
||||
/* SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes */
|
||||
___SDRAM = 0x00000000;
|
||||
___SDRAM_SIZE = 0x20000000;
|
||||
|
||||
/* ST-RAM */
|
||||
__STRAM = ___SDRAM;
|
||||
__STRAM_END = __TOS;
|
||||
|
||||
/* TOS */
|
||||
__TOS = 0x00e00000;
|
||||
|
||||
/* FastRAM */
|
||||
__FASTRAM = 0x10000000;
|
||||
__FASTRAM_END = 0x1FFFFFFF;
|
||||
|
||||
/* Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) */
|
||||
___BOOT_FLASH = 0xe0000000;
|
||||
___BOOT_FLASH_SIZE = 0x00800000;
|
||||
|
||||
/* BaS */
|
||||
__BAS_LMA = LOADADDR(.bas);
|
||||
__BAS_IN_RAM = ADDR(.bas);
|
||||
__BAS_SIZE = SIZEOF(.bas);
|
||||
|
||||
/* Other flash components */
|
||||
__FIRETOS = 0xe0400000;
|
||||
__EMUTOS = 0xe0600000;
|
||||
__EMUTOS_SIZE = 0x00100000;
|
||||
|
||||
/* VIDEO RAM BASIS */
|
||||
__VRAM = 0x60000000;
|
||||
|
||||
/* Memory mapped registers */
|
||||
__MBAR = 0xFF000000;
|
||||
|
||||
/* 32KB on-chip System SRAM */
|
||||
__SYS_SRAM = 0xFF010000;
|
||||
__SYS_SRAM_SIZE = 0x00008000;
|
||||
|
||||
/* MMU memory mapped registers */
|
||||
__MMUBAR = 0xFF040000;
|
||||
|
||||
/*
|
||||
* 4KB on-chip Core SRAM0: -> exception table and exception stack
|
||||
*/
|
||||
__RAMBAR0 = 0xFF100000;
|
||||
__RAMBAR0_SIZE = 0x00001000;
|
||||
__SUP_SP = __RAMBAR0 + __RAMBAR0_SIZE - 4;
|
||||
|
||||
/* system variables */
|
||||
|
||||
/* RAMBAR0 0 to 0x7FF -> exception vectors */
|
||||
_rt_mod = __RAMBAR0 + 0x800;
|
||||
_rt_ssp = __RAMBAR0 + 0x804;
|
||||
_rt_usp = __RAMBAR0 + 0x808;
|
||||
_rt_vbr = __RAMBAR0 + 0x80C; /* (8)01 */
|
||||
_rt_cacr = __RAMBAR0 + 0x810; /* 002 */
|
||||
_rt_asid = __RAMBAR0 + 0x814; /* 003 */
|
||||
_rt_acr0 = __RAMBAR0 + 0x818; /* 004 */
|
||||
_rt_acr1 = __RAMBAR0 + 0x81c; /* 005 */
|
||||
_rt_acr2 = __RAMBAR0 + 0x820; /* 006 */
|
||||
_rt_acr3 = __RAMBAR0 + 0x824; /* 007 */
|
||||
_rt_mmubar = __RAMBAR0 + 0x828; /* 008 */
|
||||
_rt_sr = __RAMBAR0 + 0x82c;
|
||||
_d0_save = __RAMBAR0 + 0x830;
|
||||
_a7_save = __RAMBAR0 + 0x834;
|
||||
_video_tlb = __RAMBAR0 + 0x838;
|
||||
_video_sbt = __RAMBAR0 + 0x83C;
|
||||
_rt_mbar = __RAMBAR0 + 0x844; /* (c)0f */
|
||||
|
||||
/* 4KB on-chip Core SRAM1: -> modified code */
|
||||
__RAMBAR1 = 0xFF101000;
|
||||
__RAMBAR1_SIZE = 0x00001000;
|
||||
}
|
||||
76
check.bdm
Executable file
76
check.bdm
Executable file
@@ -0,0 +1,76 @@
|
||||
#!/usr/local/bin/bdmctrl -D2 -v9 -d9
|
||||
#
|
||||
# firebee board initialization for bdmctrl
|
||||
#
|
||||
open $1
|
||||
reset
|
||||
|
||||
# set VBR
|
||||
write-ctrl 0x0801 0x00000000
|
||||
# Turn on MBAR at 0xFF00_0000
|
||||
write-ctrl 0x0C0F 0xFF000000
|
||||
|
||||
# Turn on RAMBAR0 at address FF10_0000
|
||||
write-ctrl 0x0C04 0xFF100007
|
||||
|
||||
# Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently)
|
||||
write-ctrl 0x0C05 0xFF101001
|
||||
|
||||
# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
|
||||
write 0xFF000500 0xE0000000 4
|
||||
write 0xFF000508 0x00041180 4
|
||||
write 0xFF000504 0x007F0001 4
|
||||
wait
|
||||
|
||||
# Init CS1 (Atari I/O address range)
|
||||
write 0xFF00050C 0xFFF00000 4
|
||||
write 0xFF000514 0x00002180 4
|
||||
write 0xFF000510 0x000F0001 4
|
||||
# Init CS2 (FireBee 32 bit I/O address range)
|
||||
write 0xFF000518 0xF0000000 4
|
||||
write 0xFF000520 0x00002100 4
|
||||
write 0xFF00051C 0x07FF0001 4
|
||||
# Init CS3 (FireBee 16 bit I/O address range)
|
||||
write 0xFF000524 0xF8000000 4
|
||||
write 0xFF00052C 0x00000180 4
|
||||
write 0xFF000528 0x03FF0001 4
|
||||
# Init CS4 (FireBee video address range)
|
||||
write 0xFF000530 0x40000000 4
|
||||
write 0xFF000538 0x00000018 4
|
||||
write 0xFF000534 0x003F0001 4
|
||||
|
||||
|
||||
# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
|
||||
write 0xFF000004 0x000002AA 4 # SDRAMDS configuration
|
||||
write 0xFF000020 0x0000001A 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
|
||||
write 0xFF000024 0x0800001A 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
|
||||
write 0xFF000028 0x1000001A 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
|
||||
write 0xFF00002C 0x1800001A 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
|
||||
write 0xFF000108 0x73622830 4 # SDCFG1
|
||||
write 0xFF00010C 0x46770000 4 # SDCFG2
|
||||
|
||||
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
|
||||
write 0xFF000100 0x40010000 4 # SDMR (write to LEMR)
|
||||
write 0xFF000100 0x048D0000 4 # SDMR (write to LMR)
|
||||
|
||||
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
|
||||
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
|
||||
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
|
||||
write 0xFF000100 0x008D0000 4 # SDMR (write to LMR)
|
||||
write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
|
||||
|
||||
dump-register SR
|
||||
write-ctrl 0x80e 0x2700
|
||||
write-ctrl 0x2 0xa50c8120
|
||||
dump-register D0
|
||||
dump-register ASID
|
||||
dump-register ACR0
|
||||
dump-register ACR1
|
||||
dump-register ACR2
|
||||
dump-register ACR3
|
||||
dump-register SR
|
||||
dump-register CACR
|
||||
dump-register RAMBAR1
|
||||
dump-register RAMBAR2
|
||||
dump-register MBAR
|
||||
dump-register 0xc05
|
||||
17
dump.bdm
Executable file
17
dump.bdm
Executable file
@@ -0,0 +1,17 @@
|
||||
#!/usr/local/bin/bdmctrl -D2 -v9 -d9
|
||||
#
|
||||
# firebee board initialization for bdmctrl
|
||||
#
|
||||
open $1
|
||||
|
||||
dump-register D0
|
||||
#dump-register ASID
|
||||
dump-register ACR0
|
||||
dump-register ACR1
|
||||
#dump-register ACR2
|
||||
#dump-register ACR3
|
||||
dump-register SR
|
||||
dump-register CACR
|
||||
# dump-register RAMBAR1
|
||||
# dump-register RAMBAR2
|
||||
dump-register MBAR
|
||||
150
include/MCF5475_DSPI.h
Normal file
150
include/MCF5475_DSPI.h
Normal file
@@ -0,0 +1,150 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_DSPI_H__
|
||||
#define __MCF5475_DSPI_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* DMA Serial Peripheral Interface (DSPI)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_DSPI_DMCR (*(volatile uint32_t*)(&_MBAR[0x8A00]))
|
||||
#define MCF_DSPI_DTCR (*(volatile uint32_t*)(&_MBAR[0x8A08]))
|
||||
#define MCF_DSPI_DCTAR0 (*(volatile uint32_t*)(&_MBAR[0x8A0C]))
|
||||
#define MCF_DSPI_DCTAR1 (*(volatile uint32_t*)(&_MBAR[0x8A10]))
|
||||
#define MCF_DSPI_DCTAR2 (*(volatile uint32_t*)(&_MBAR[0x8A14]))
|
||||
#define MCF_DSPI_DCTAR3 (*(volatile uint32_t*)(&_MBAR[0x8A18]))
|
||||
#define MCF_DSPI_DCTAR4 (*(volatile uint32_t*)(&_MBAR[0x8A1C]))
|
||||
#define MCF_DSPI_DCTAR5 (*(volatile uint32_t*)(&_MBAR[0x8A20]))
|
||||
#define MCF_DSPI_DCTAR6 (*(volatile uint32_t*)(&_MBAR[0x8A24]))
|
||||
#define MCF_DSPI_DCTAR7 (*(volatile uint32_t*)(&_MBAR[0x8A28]))
|
||||
#define MCF_DSPI_DSR (*(volatile uint32_t*)(&_MBAR[0x8A2C]))
|
||||
#define MCF_DSPI_DIRSR (*(volatile uint32_t*)(&_MBAR[0x8A30]))
|
||||
#define MCF_DSPI_DTFR (*(volatile uint32_t*)(&_MBAR[0x8A34]))
|
||||
#define MCF_DSPI_DRFR (*(volatile uint32_t*)(&_MBAR[0x8A38]))
|
||||
#define MCF_DSPI_DTFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A3C]))
|
||||
#define MCF_DSPI_DTFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A40]))
|
||||
#define MCF_DSPI_DTFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A44]))
|
||||
#define MCF_DSPI_DTFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A48]))
|
||||
#define MCF_DSPI_DRFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A7C]))
|
||||
#define MCF_DSPI_DRFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A80]))
|
||||
#define MCF_DSPI_DRFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A84]))
|
||||
#define MCF_DSPI_DRFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A88]))
|
||||
#define MCF_DSPI_DCTAR(x) (*(volatile uint32_t*)(&_MBAR[0x8A0C + ((x)*0x4)]))
|
||||
#define MCF_DSPI_DTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A3C + ((x)*0x4)]))
|
||||
#define MCF_DSPI_DRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A7C + ((x)*0x4)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DMCR */
|
||||
#define MCF_DSPI_DMCR_HALT (0x1)
|
||||
#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_DSPI_DMCR_SMPL_PT_0CLK (0)
|
||||
#define MCF_DSPI_DMCR_SMPL_PT_1CLK (0x100)
|
||||
#define MCF_DSPI_DMCR_SMPL_PT_2CLK (0x200)
|
||||
#define MCF_DSPI_DMCR_CRXF (0x400)
|
||||
#define MCF_DSPI_DMCR_CTXF (0x800)
|
||||
#define MCF_DSPI_DMCR_DRXF (0x1000)
|
||||
#define MCF_DSPI_DMCR_DTXF (0x2000)
|
||||
#define MCF_DSPI_DMCR_CSIS0 (0x10000)
|
||||
#define MCF_DSPI_DMCR_CSIS2 (0x40000)
|
||||
#define MCF_DSPI_DMCR_CSIS3 (0x80000)
|
||||
#define MCF_DSPI_DMCR_CSIS5 (0x200000)
|
||||
#define MCF_DSPI_DMCR_ROOE (0x1000000)
|
||||
#define MCF_DSPI_DMCR_PCSSE (0x2000000)
|
||||
#define MCF_DSPI_DMCR_MTFE (0x4000000)
|
||||
#define MCF_DSPI_DMCR_FRZ (0x8000000)
|
||||
#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x3)<<0x1C)
|
||||
#define MCF_DSPI_DMCR_CSCK (0x40000000)
|
||||
#define MCF_DSPI_DMCR_MSTR (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DTCR */
|
||||
#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DCTAR */
|
||||
#define MCF_DSPI_DCTAR_BR(x) (((x)&0xF)<<0)
|
||||
#define MCF_DSPI_DCTAR_DT(x) (((x)&0xF)<<0x4)
|
||||
#define MCF_DSPI_DCTAR_ASC(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0xF)<<0xC)
|
||||
#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_DSPI_DCTAR_PBR_1CLK (0)
|
||||
#define MCF_DSPI_DCTAR_PBR_3CLK (0x10000)
|
||||
#define MCF_DSPI_DCTAR_PBR_5CLK (0x20000)
|
||||
#define MCF_DSPI_DCTAR_PBR_7CLK (0x30000)
|
||||
#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x3)<<0x12)
|
||||
#define MCF_DSPI_DCTAR_PDT_1CLK (0)
|
||||
#define MCF_DSPI_DCTAR_PDT_3CLK (0x40000)
|
||||
#define MCF_DSPI_DCTAR_PDT_5CLK (0x80000)
|
||||
#define MCF_DSPI_DCTAR_PDT_7CLK (0xC0000)
|
||||
#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x3)<<0x14)
|
||||
#define MCF_DSPI_DCTAR_PASC_1CLK (0)
|
||||
#define MCF_DSPI_DCTAR_PASC_3CLK (0x100000)
|
||||
#define MCF_DSPI_DCTAR_PASC_5CLK (0x200000)
|
||||
#define MCF_DSPI_DCTAR_PASC_7CLK (0x300000)
|
||||
#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x3)<<0x16)
|
||||
#define MCF_DSPI_DCTAR_LSBFE (0x1000000)
|
||||
#define MCF_DSPI_DCTAR_CPHA (0x2000000)
|
||||
#define MCF_DSPI_DCTAR_CPOL (0x4000000)
|
||||
#define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0xF)<<0x1B)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DSR */
|
||||
#define MCF_DSPI_DSR_RXPTR(x) (((x)&0xF)<<0)
|
||||
#define MCF_DSPI_DSR_RXCTR(x) (((x)&0xF)<<0x4)
|
||||
#define MCF_DSPI_DSR_TXPTR(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_DSPI_DSR_TXCTR(x) (((x)&0xF)<<0xC)
|
||||
#define MCF_DSPI_DSR_RFDF (0x20000)
|
||||
#define MCF_DSPI_DSR_RFOF (0x80000)
|
||||
#define MCF_DSPI_DSR_TFFF (0x2000000)
|
||||
#define MCF_DSPI_DSR_TFUF (0x8000000)
|
||||
#define MCF_DSPI_DSR_EOQF (0x10000000)
|
||||
#define MCF_DSPI_DSR_TXRXS (0x40000000)
|
||||
#define MCF_DSPI_DSR_TCF (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DIRSR */
|
||||
#define MCF_DSPI_DIRSR_RFDFS (0x10000)
|
||||
#define MCF_DSPI_DIRSR_RFDFE (0x20000)
|
||||
#define MCF_DSPI_DIRSR_RFOFE (0x80000)
|
||||
#define MCF_DSPI_DIRSR_TFFFS (0x1000000)
|
||||
#define MCF_DSPI_DIRSR_TFFFE (0x2000000)
|
||||
#define MCF_DSPI_DIRSR_TFUFE (0x8000000)
|
||||
#define MCF_DSPI_DIRSR_EOQFE (0x10000000)
|
||||
#define MCF_DSPI_DIRSR_TCFE (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DTFR */
|
||||
#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_DSPI_DTFR_CS0 (0x10000)
|
||||
#define MCF_DSPI_DTFR_CS2 (0x40000)
|
||||
#define MCF_DSPI_DTFR_CS3 (0x80000)
|
||||
#define MCF_DSPI_DTFR_CS5 (0x200000)
|
||||
#define MCF_DSPI_DTFR_CTCNT (0x4000000)
|
||||
#define MCF_DSPI_DTFR_EOQ (0x8000000)
|
||||
#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x7)<<0x1C)
|
||||
#define MCF_DSPI_DTFR_CONT (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DRFR */
|
||||
#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DTFDR */
|
||||
#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_DSPI_DTFDR_TXCMD(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DRFDR */
|
||||
#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF5475_DSPI_H__ */
|
||||
543
include/MCF5475_GPIO.h
Normal file
543
include/MCF5475_GPIO.h
Normal file
@@ -0,0 +1,543 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_GPIO_H__
|
||||
#define __MCF5475_GPIO_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* General Purpose I/O (GPIO)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_GPIO_PODR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA00]))
|
||||
#define MCF_GPIO_PDDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA10]))
|
||||
#define MCF_GPIO_PPDSDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA20]))
|
||||
#define MCF_GPIO_PCLRR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA30]))
|
||||
|
||||
#define MCF_GPIO_PODR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA01]))
|
||||
#define MCF_GPIO_PDDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA11]))
|
||||
#define MCF_GPIO_PPDSDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA21]))
|
||||
#define MCF_GPIO_PCLRR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA31]))
|
||||
|
||||
#define MCF_GPIO_PODR_DMA (*(volatile uint8_t *)(&_MBAR[0xA02]))
|
||||
#define MCF_GPIO_PDDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA12]))
|
||||
#define MCF_GPIO_PPDSDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA22]))
|
||||
#define MCF_GPIO_PCLRR_DMA (*(volatile uint8_t *)(&_MBAR[0xA32]))
|
||||
|
||||
#define MCF_GPIO_PODR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA04]))
|
||||
#define MCF_GPIO_PDDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA14]))
|
||||
#define MCF_GPIO_PPDSDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA24]))
|
||||
#define MCF_GPIO_PCLRR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA34]))
|
||||
|
||||
#define MCF_GPIO_PODR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA05]))
|
||||
#define MCF_GPIO_PDDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA15]))
|
||||
#define MCF_GPIO_PPDSDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA25]))
|
||||
#define MCF_GPIO_PCLRR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA35]))
|
||||
|
||||
#define MCF_GPIO_PODR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA06]))
|
||||
#define MCF_GPIO_PDDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA16]))
|
||||
#define MCF_GPIO_PPDSDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA26]))
|
||||
#define MCF_GPIO_PCLRR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA36]))
|
||||
|
||||
#define MCF_GPIO_PODR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA07]))
|
||||
#define MCF_GPIO_PDDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA17]))
|
||||
#define MCF_GPIO_PPDSDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA27]))
|
||||
#define MCF_GPIO_PCLRR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA37]))
|
||||
|
||||
#define MCF_GPIO_PODR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA08]))
|
||||
#define MCF_GPIO_PDDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA18]))
|
||||
#define MCF_GPIO_PPDSDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA28]))
|
||||
#define MCF_GPIO_PCLRR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA38]))
|
||||
|
||||
#define MCF_GPIO_PODR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA09]))
|
||||
#define MCF_GPIO_PDDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA19]))
|
||||
#define MCF_GPIO_PPDSDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA29]))
|
||||
#define MCF_GPIO_PCLRR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA39]))
|
||||
|
||||
#define MCF_GPIO_PODR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA0A]))
|
||||
#define MCF_GPIO_PDDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA1A]))
|
||||
#define MCF_GPIO_PPDSDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA2A]))
|
||||
#define MCF_GPIO_PCLRR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA3A]))
|
||||
|
||||
#define MCF_GPIO2_PODR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA0C]))
|
||||
#define MCF_GPIO2_PDDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA1C]))
|
||||
#define MCF_GPIO2_PPDSDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA2C]))
|
||||
#define MCF_GPIO2_PCLRR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA3C]))
|
||||
|
||||
#define MCF_GPIO0_PODR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA0D]))
|
||||
#define MCF_GPIO0_PDDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA1D]))
|
||||
#define MCF_GPIO0_PPDSDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA2D]))
|
||||
#define MCF_GPIO0_PCLRR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA3D]))
|
||||
|
||||
#define MCF_GPIO_PODR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA0E]))
|
||||
#define MCF_GPIO_PDDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA1E]))
|
||||
#define MCF_GPIO_PPDSDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA2E]))
|
||||
#define MCF_GPIO_PCLRR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA3E]))
|
||||
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x1)
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x2)
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x4)
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x8)
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10)
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20)
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40)
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x1)
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x2)
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x4)
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x8)
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10)
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20)
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40)
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */
|
||||
#define MCF_GPIO_PODR_FBCS_PODR_FBCS1 (0x2)
|
||||
#define MCF_GPIO_PODR_FBCS_PODR_FBCS2 (0x4)
|
||||
#define MCF_GPIO_PODR_FBCS_PODR_FBCS3 (0x8)
|
||||
#define MCF_GPIO_PODR_FBCS_PODR_FBCS4 (0x10)
|
||||
#define MCF_GPIO_PODR_FBCS_PODR_FBCS5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */
|
||||
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x2)
|
||||
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x4)
|
||||
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x8)
|
||||
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10)
|
||||
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */
|
||||
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */
|
||||
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_DMA */
|
||||
#define MCF_GPIO_PODR_DMA_PODR_DMA0 (0x1)
|
||||
#define MCF_GPIO_PODR_DMA_PODR_DMA1 (0x2)
|
||||
#define MCF_GPIO_PODR_DMA_PODR_DMA2 (0x4)
|
||||
#define MCF_GPIO_PODR_DMA_PODR_DMA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */
|
||||
#define MCF_GPIO_PDDR_DMA_PDDR_DMA0 (0x1)
|
||||
#define MCF_GPIO_PDDR_DMA_PDDR_DMA1 (0x2)
|
||||
#define MCF_GPIO_PDDR_DMA_PDDR_DMA2 (0x4)
|
||||
#define MCF_GPIO_PDDR_DMA_PDDR_DMA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */
|
||||
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */
|
||||
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x1)
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x2)
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x4)
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x8)
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10)
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20)
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40)
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x1)
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x2)
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x4)
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x8)
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10)
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20)
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40)
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x1)
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x2)
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x4)
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x8)
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10)
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20)
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40)
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x1)
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x2)
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x4)
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x8)
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10)
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20)
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40)
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x1)
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x2)
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x4)
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x8)
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10)
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20)
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40)
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x1)
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x2)
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x4)
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x8)
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10)
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20)
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40)
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x1)
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x2)
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x4)
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x8)
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10)
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20)
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40)
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x1)
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x2)
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x4)
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x8)
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10)
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20)
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40)
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
|
||||
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x1)
|
||||
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x2)
|
||||
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x4)
|
||||
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
|
||||
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x1)
|
||||
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x2)
|
||||
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x4)
|
||||
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
|
||||
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
|
||||
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */
|
||||
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x1)
|
||||
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x2)
|
||||
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x4)
|
||||
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x8)
|
||||
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */
|
||||
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x1)
|
||||
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x2)
|
||||
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x4)
|
||||
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x8)
|
||||
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */
|
||||
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */
|
||||
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */
|
||||
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x1)
|
||||
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x2)
|
||||
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x4)
|
||||
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x8)
|
||||
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */
|
||||
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x1)
|
||||
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x2)
|
||||
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x4)
|
||||
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x8)
|
||||
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */
|
||||
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */
|
||||
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1)
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2)
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4)
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8)
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10)
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20)
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40)
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1)
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2)
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4)
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8)
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10)
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20)
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40)
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1)
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2)
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4)
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8)
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10)
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20)
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40)
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1)
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2)
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4)
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8)
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10)
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20)
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40)
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1)
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2)
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4)
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8)
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10)
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20)
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40)
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1)
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2)
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4)
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8)
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10)
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20)
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40)
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */
|
||||
#define MCF_GPIO_PODR_DSPI_PODR_DSPI0 (0x1)
|
||||
#define MCF_GPIO_PODR_DSPI_PODR_DSPI1 (0x2)
|
||||
#define MCF_GPIO_PODR_DSPI_PODR_DSPI2 (0x4)
|
||||
#define MCF_GPIO_PODR_DSPI_PODR_DSPI3 (0x8)
|
||||
#define MCF_GPIO_PODR_DSPI_PODR_DSPI4 (0x10)
|
||||
#define MCF_GPIO_PODR_DSPI_PODR_DSPI5 (0x20)
|
||||
#define MCF_GPIO_PODR_DSPI_PODR_DSPI6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */
|
||||
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x1)
|
||||
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x2)
|
||||
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x4)
|
||||
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x8)
|
||||
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10)
|
||||
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20)
|
||||
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */
|
||||
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */
|
||||
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40)
|
||||
|
||||
|
||||
#endif /* __MCF5475_GPIO_H__ */
|
||||
100
include/MCF5475_GPT.h
Normal file
100
include/MCF5475_GPT.h
Normal file
@@ -0,0 +1,100 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_GPT_H__
|
||||
#define __MCF5475_GPT_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* General Purpose Timers (GPT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_GPT0_GMS (*(volatile uint32_t*)(&_MBAR[0x800]))
|
||||
#define MCF_GPT0_GCIR (*(volatile uint32_t*)(&_MBAR[0x804]))
|
||||
#define MCF_GPT0_GPWM (*(volatile uint32_t*)(&_MBAR[0x808]))
|
||||
#define MCF_GPT0_GSR (*(volatile uint32_t*)(&_MBAR[0x80C]))
|
||||
|
||||
#define MCF_GPT1_GMS (*(volatile uint32_t*)(&_MBAR[0x810]))
|
||||
#define MCF_GPT1_GCIR (*(volatile uint32_t*)(&_MBAR[0x814]))
|
||||
#define MCF_GPT1_GPWM (*(volatile uint32_t*)(&_MBAR[0x818]))
|
||||
#define MCF_GPT1_GSR (*(volatile uint32_t*)(&_MBAR[0x81C]))
|
||||
|
||||
#define MCF_GPT2_GMS (*(volatile uint32_t*)(&_MBAR[0x820]))
|
||||
#define MCF_GPT2_GCIR (*(volatile uint32_t*)(&_MBAR[0x824]))
|
||||
#define MCF_GPT2_GPWM (*(volatile uint32_t*)(&_MBAR[0x828]))
|
||||
#define MCF_GPT2_GSR (*(volatile uint32_t*)(&_MBAR[0x82C]))
|
||||
|
||||
#define MCF_GPT3_GMS (*(volatile uint32_t*)(&_MBAR[0x830]))
|
||||
#define MCF_GPT3_GCIR (*(volatile uint32_t*)(&_MBAR[0x834]))
|
||||
#define MCF_GPT3_GPWM (*(volatile uint32_t*)(&_MBAR[0x838]))
|
||||
#define MCF_GPT3_GSR (*(volatile uint32_t*)(&_MBAR[0x83C]))
|
||||
|
||||
#define MCF_GPT_GMS(x) (*(volatile uint32_t*)(&_MBAR[0x800 + ((x)*0x10)]))
|
||||
#define MCF_GPT_GCIR(x) (*(volatile uint32_t*)(&_MBAR[0x804 + ((x)*0x10)]))
|
||||
#define MCF_GPT_GPWM(x) (*(volatile uint32_t*)(&_MBAR[0x808 + ((x)*0x10)]))
|
||||
#define MCF_GPT_GSR(x) (*(volatile uint32_t*)(&_MBAR[0x80C + ((x)*0x10)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_GPT_GMS */
|
||||
#define MCF_GPT_GMS_TMS(x) (((x)&0x7)<<0)
|
||||
#define MCF_GPT_GMS_TMS_DISABLE (0)
|
||||
#define MCF_GPT_GMS_TMS_INCAPT (0x1)
|
||||
#define MCF_GPT_GMS_TMS_OUTCAPT (0x2)
|
||||
#define MCF_GPT_GMS_TMS_PWM (0x3)
|
||||
#define MCF_GPT_GMS_TMS_GPIO (0x4)
|
||||
#define MCF_GPT_GMS_GPIO(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_GPT_GMS_GPIO_INPUT (0)
|
||||
#define MCF_GPT_GMS_GPIO_OUTLO (0x20)
|
||||
#define MCF_GPT_GMS_GPIO_OUTHI (0x30)
|
||||
#define MCF_GPT_GMS_IEN (0x100)
|
||||
#define MCF_GPT_GMS_OD (0x200)
|
||||
#define MCF_GPT_GMS_SC (0x400)
|
||||
#define MCF_GPT_GMS_CE (0x1000)
|
||||
#define MCF_GPT_GMS_WDEN (0x8000)
|
||||
#define MCF_GPT_GMS_ICT(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_GPT_GMS_ICT_ANY (0)
|
||||
#define MCF_GPT_GMS_ICT_RISE (0x10000)
|
||||
#define MCF_GPT_GMS_ICT_FALL (0x20000)
|
||||
#define MCF_GPT_GMS_ICT_PULSE (0x30000)
|
||||
#define MCF_GPT_GMS_OCT(x) (((x)&0x3)<<0x14)
|
||||
#define MCF_GPT_GMS_OCT_FRCLOW (0)
|
||||
#define MCF_GPT_GMS_OCT_PULSEHI (0x100000)
|
||||
#define MCF_GPT_GMS_OCT_PULSELO (0x200000)
|
||||
#define MCF_GPT_GMS_OCT_TOGGLE (0x300000)
|
||||
#define MCF_GPT_GMS_OCPW(x) (((x)&0xFF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPT_GCIR */
|
||||
#define MCF_GPT_GCIR_CNT(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_GPT_GCIR_PRE(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPT_GPWM */
|
||||
#define MCF_GPT_GPWM_LOAD (0x1)
|
||||
#define MCF_GPT_GPWM_PWMOP (0x100)
|
||||
#define MCF_GPT_GPWM_WIDTH(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPT_GSR */
|
||||
#define MCF_GPT_GSR_CAPT (0x1)
|
||||
#define MCF_GPT_GSR_COMP (0x2)
|
||||
#define MCF_GPT_GSR_PWMP (0x4)
|
||||
#define MCF_GPT_GSR_TEXP (0x8)
|
||||
#define MCF_GPT_GSR_PIN (0x100)
|
||||
#define MCF_GPT_GSR_OVF(x) (((x)&0x7)<<0xC)
|
||||
#define MCF_GPT_GSR_CAPTURE(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
|
||||
#endif /* __MCF5475_GPT_H__ */
|
||||
330
include/MCF5475_INTC.h
Normal file
330
include/MCF5475_INTC.h
Normal file
@@ -0,0 +1,330 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_INTC_H__
|
||||
#define __MCF5475_INTC_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Interrupt Controller (INTC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_INTC_IPRH (*(volatile uint32_t*)(&_MBAR[0x700]))
|
||||
#define MCF_INTC_IPRL (*(volatile uint32_t*)(&_MBAR[0x704]))
|
||||
#define MCF_INTC_IMRH (*(volatile uint32_t*)(&_MBAR[0x708]))
|
||||
#define MCF_INTC_IMRL (*(volatile uint32_t*)(&_MBAR[0x70C]))
|
||||
#define MCF_INTC_INTFRCH (*(volatile uint32_t*)(&_MBAR[0x710]))
|
||||
#define MCF_INTC_INTFRCL (*(volatile uint32_t*)(&_MBAR[0x714]))
|
||||
#define MCF_INTC_IRLR (*(volatile uint8_t *)(&_MBAR[0x718]))
|
||||
#define MCF_INTC_IACKLPR (*(volatile uint8_t *)(&_MBAR[0x719]))
|
||||
#define MCF_INTC_ICR01 (*(volatile uint8_t *)(&_MBAR[0x741]))
|
||||
#define MCF_INTC_ICR02 (*(volatile uint8_t *)(&_MBAR[0x742]))
|
||||
#define MCF_INTC_ICR03 (*(volatile uint8_t *)(&_MBAR[0x743]))
|
||||
#define MCF_INTC_ICR04 (*(volatile uint8_t *)(&_MBAR[0x744]))
|
||||
#define MCF_INTC_ICR05 (*(volatile uint8_t *)(&_MBAR[0x745]))
|
||||
#define MCF_INTC_ICR06 (*(volatile uint8_t *)(&_MBAR[0x746]))
|
||||
#define MCF_INTC_ICR07 (*(volatile uint8_t *)(&_MBAR[0x747]))
|
||||
#define MCF_INTC_ICR08 (*(volatile uint8_t *)(&_MBAR[0x748]))
|
||||
#define MCF_INTC_ICR09 (*(volatile uint8_t *)(&_MBAR[0x749]))
|
||||
#define MCF_INTC_ICR10 (*(volatile uint8_t *)(&_MBAR[0x74A]))
|
||||
#define MCF_INTC_ICR11 (*(volatile uint8_t *)(&_MBAR[0x74B]))
|
||||
#define MCF_INTC_ICR12 (*(volatile uint8_t *)(&_MBAR[0x74C]))
|
||||
#define MCF_INTC_ICR13 (*(volatile uint8_t *)(&_MBAR[0x74D]))
|
||||
#define MCF_INTC_ICR14 (*(volatile uint8_t *)(&_MBAR[0x74E]))
|
||||
#define MCF_INTC_ICR15 (*(volatile uint8_t *)(&_MBAR[0x74F]))
|
||||
#define MCF_INTC_ICR16 (*(volatile uint8_t *)(&_MBAR[0x750]))
|
||||
#define MCF_INTC_ICR17 (*(volatile uint8_t *)(&_MBAR[0x751]))
|
||||
#define MCF_INTC_ICR18 (*(volatile uint8_t *)(&_MBAR[0x752]))
|
||||
#define MCF_INTC_ICR19 (*(volatile uint8_t *)(&_MBAR[0x753]))
|
||||
#define MCF_INTC_ICR20 (*(volatile uint8_t *)(&_MBAR[0x754]))
|
||||
#define MCF_INTC_ICR21 (*(volatile uint8_t *)(&_MBAR[0x755]))
|
||||
#define MCF_INTC_ICR22 (*(volatile uint8_t *)(&_MBAR[0x756]))
|
||||
#define MCF_INTC_ICR23 (*(volatile uint8_t *)(&_MBAR[0x757]))
|
||||
#define MCF_INTC_ICR24 (*(volatile uint8_t *)(&_MBAR[0x758]))
|
||||
#define MCF_INTC_ICR25 (*(volatile uint8_t *)(&_MBAR[0x759]))
|
||||
#define MCF_INTC_ICR26 (*(volatile uint8_t *)(&_MBAR[0x75A]))
|
||||
#define MCF_INTC_ICR27 (*(volatile uint8_t *)(&_MBAR[0x75B]))
|
||||
#define MCF_INTC_ICR28 (*(volatile uint8_t *)(&_MBAR[0x75C]))
|
||||
#define MCF_INTC_ICR29 (*(volatile uint8_t *)(&_MBAR[0x75D]))
|
||||
#define MCF_INTC_ICR30 (*(volatile uint8_t *)(&_MBAR[0x75E]))
|
||||
#define MCF_INTC_ICR31 (*(volatile uint8_t *)(&_MBAR[0x75F]))
|
||||
#define MCF_INTC_ICR32 (*(volatile uint8_t *)(&_MBAR[0x760]))
|
||||
#define MCF_INTC_ICR33 (*(volatile uint8_t *)(&_MBAR[0x761]))
|
||||
#define MCF_INTC_ICR34 (*(volatile uint8_t *)(&_MBAR[0x762]))
|
||||
#define MCF_INTC_ICR35 (*(volatile uint8_t *)(&_MBAR[0x763]))
|
||||
#define MCF_INTC_ICR36 (*(volatile uint8_t *)(&_MBAR[0x764]))
|
||||
#define MCF_INTC_ICR37 (*(volatile uint8_t *)(&_MBAR[0x765]))
|
||||
#define MCF_INTC_ICR38 (*(volatile uint8_t *)(&_MBAR[0x766]))
|
||||
#define MCF_INTC_ICR39 (*(volatile uint8_t *)(&_MBAR[0x767]))
|
||||
#define MCF_INTC_ICR40 (*(volatile uint8_t *)(&_MBAR[0x768]))
|
||||
#define MCF_INTC_ICR41 (*(volatile uint8_t *)(&_MBAR[0x769]))
|
||||
#define MCF_INTC_ICR42 (*(volatile uint8_t *)(&_MBAR[0x76A]))
|
||||
#define MCF_INTC_ICR43 (*(volatile uint8_t *)(&_MBAR[0x76B]))
|
||||
#define MCF_INTC_ICR44 (*(volatile uint8_t *)(&_MBAR[0x76C]))
|
||||
#define MCF_INTC_ICR45 (*(volatile uint8_t *)(&_MBAR[0x76D]))
|
||||
#define MCF_INTC_ICR46 (*(volatile uint8_t *)(&_MBAR[0x76E]))
|
||||
#define MCF_INTC_ICR47 (*(volatile uint8_t *)(&_MBAR[0x76F]))
|
||||
#define MCF_INTC_ICR48 (*(volatile uint8_t *)(&_MBAR[0x770]))
|
||||
#define MCF_INTC_ICR49 (*(volatile uint8_t *)(&_MBAR[0x771]))
|
||||
#define MCF_INTC_ICR50 (*(volatile uint8_t *)(&_MBAR[0x772]))
|
||||
#define MCF_INTC_ICR51 (*(volatile uint8_t *)(&_MBAR[0x773]))
|
||||
#define MCF_INTC_ICR52 (*(volatile uint8_t *)(&_MBAR[0x774]))
|
||||
#define MCF_INTC_ICR53 (*(volatile uint8_t *)(&_MBAR[0x775]))
|
||||
#define MCF_INTC_ICR54 (*(volatile uint8_t *)(&_MBAR[0x776]))
|
||||
#define MCF_INTC_ICR55 (*(volatile uint8_t *)(&_MBAR[0x777]))
|
||||
#define MCF_INTC_ICR56 (*(volatile uint8_t *)(&_MBAR[0x778]))
|
||||
#define MCF_INTC_ICR57 (*(volatile uint8_t *)(&_MBAR[0x779]))
|
||||
#define MCF_INTC_ICR58 (*(volatile uint8_t *)(&_MBAR[0x77A]))
|
||||
#define MCF_INTC_ICR59 (*(volatile uint8_t *)(&_MBAR[0x77B]))
|
||||
#define MCF_INTC_ICR60 (*(volatile uint8_t *)(&_MBAR[0x77C]))
|
||||
#define MCF_INTC_ICR61 (*(volatile uint8_t *)(&_MBAR[0x77D]))
|
||||
#define MCF_INTC_ICR62 (*(volatile uint8_t *)(&_MBAR[0x77E]))
|
||||
#define MCF_INTC_ICR63 (*(volatile uint8_t *)(&_MBAR[0x77F]))
|
||||
#define MCF_INTC_SWIACK (*(volatile uint8_t *)(&_MBAR[0x7E0]))
|
||||
#define MCF_INTC_L1IACK (*(volatile uint8_t *)(&_MBAR[0x7E4]))
|
||||
#define MCF_INTC_L2IACK (*(volatile uint8_t *)(&_MBAR[0x7E8]))
|
||||
#define MCF_INTC_L3IACK (*(volatile uint8_t *)(&_MBAR[0x7EC]))
|
||||
#define MCF_INTC_L4IACK (*(volatile uint8_t *)(&_MBAR[0x7F0]))
|
||||
#define MCF_INTC_L5IACK (*(volatile uint8_t *)(&_MBAR[0x7F4]))
|
||||
#define MCF_INTC_L6IACK (*(volatile uint8_t *)(&_MBAR[0x7F8]))
|
||||
#define MCF_INTC_L7IACK (*(volatile uint8_t *)(&_MBAR[0x7FC]))
|
||||
#define MCF_INTC_ICR(x) (*(volatile uint8_t *)(&_MBAR[0x741 + ((x-1)*0x1)]))
|
||||
#define MCF_INTC_LIACK(x) (*(volatile uint8_t *)(&_MBAR[0x7E4 + ((x-1)*0x4)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IPRH */
|
||||
#define MCF_INTC_IPRH_INT32 (0x1)
|
||||
#define MCF_INTC_IPRH_INT33 (0x2)
|
||||
#define MCF_INTC_IPRH_INT34 (0x4)
|
||||
#define MCF_INTC_IPRH_INT35 (0x8)
|
||||
#define MCF_INTC_IPRH_INT36 (0x10)
|
||||
#define MCF_INTC_IPRH_INT37 (0x20)
|
||||
#define MCF_INTC_IPRH_INT38 (0x40)
|
||||
#define MCF_INTC_IPRH_INT39 (0x80)
|
||||
#define MCF_INTC_IPRH_INT40 (0x100)
|
||||
#define MCF_INTC_IPRH_INT41 (0x200)
|
||||
#define MCF_INTC_IPRH_INT42 (0x400)
|
||||
#define MCF_INTC_IPRH_INT43 (0x800)
|
||||
#define MCF_INTC_IPRH_INT44 (0x1000)
|
||||
#define MCF_INTC_IPRH_INT45 (0x2000)
|
||||
#define MCF_INTC_IPRH_INT46 (0x4000)
|
||||
#define MCF_INTC_IPRH_INT47 (0x8000)
|
||||
#define MCF_INTC_IPRH_INT48 (0x10000)
|
||||
#define MCF_INTC_IPRH_INT49 (0x20000)
|
||||
#define MCF_INTC_IPRH_INT50 (0x40000)
|
||||
#define MCF_INTC_IPRH_INT51 (0x80000)
|
||||
#define MCF_INTC_IPRH_INT52 (0x100000)
|
||||
#define MCF_INTC_IPRH_INT53 (0x200000)
|
||||
#define MCF_INTC_IPRH_INT54 (0x400000)
|
||||
#define MCF_INTC_IPRH_INT55 (0x800000)
|
||||
#define MCF_INTC_IPRH_INT56 (0x1000000)
|
||||
#define MCF_INTC_IPRH_INT57 (0x2000000)
|
||||
#define MCF_INTC_IPRH_INT58 (0x4000000)
|
||||
#define MCF_INTC_IPRH_INT59 (0x8000000)
|
||||
#define MCF_INTC_IPRH_INT60 (0x10000000)
|
||||
#define MCF_INTC_IPRH_INT61 (0x20000000)
|
||||
#define MCF_INTC_IPRH_INT62 (0x40000000)
|
||||
#define MCF_INTC_IPRH_INT63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IPRL */
|
||||
#define MCF_INTC_IPRL_INT1 (0x2)
|
||||
#define MCF_INTC_IPRL_INT2 (0x4)
|
||||
#define MCF_INTC_IPRL_INT3 (0x8)
|
||||
#define MCF_INTC_IPRL_INT4 (0x10)
|
||||
#define MCF_INTC_IPRL_INT5 (0x20)
|
||||
#define MCF_INTC_IPRL_INT6 (0x40)
|
||||
#define MCF_INTC_IPRL_INT7 (0x80)
|
||||
#define MCF_INTC_IPRL_INT8 (0x100)
|
||||
#define MCF_INTC_IPRL_INT9 (0x200)
|
||||
#define MCF_INTC_IPRL_INT10 (0x400)
|
||||
#define MCF_INTC_IPRL_INT11 (0x800)
|
||||
#define MCF_INTC_IPRL_INT12 (0x1000)
|
||||
#define MCF_INTC_IPRL_INT13 (0x2000)
|
||||
#define MCF_INTC_IPRL_INT14 (0x4000)
|
||||
#define MCF_INTC_IPRL_INT15 (0x8000)
|
||||
#define MCF_INTC_IPRL_INT16 (0x10000)
|
||||
#define MCF_INTC_IPRL_INT17 (0x20000)
|
||||
#define MCF_INTC_IPRL_INT18 (0x40000)
|
||||
#define MCF_INTC_IPRL_INT19 (0x80000)
|
||||
#define MCF_INTC_IPRL_INT20 (0x100000)
|
||||
#define MCF_INTC_IPRL_INT21 (0x200000)
|
||||
#define MCF_INTC_IPRL_INT22 (0x400000)
|
||||
#define MCF_INTC_IPRL_INT23 (0x800000)
|
||||
#define MCF_INTC_IPRL_INT24 (0x1000000)
|
||||
#define MCF_INTC_IPRL_INT25 (0x2000000)
|
||||
#define MCF_INTC_IPRL_INT26 (0x4000000)
|
||||
#define MCF_INTC_IPRL_INT27 (0x8000000)
|
||||
#define MCF_INTC_IPRL_INT28 (0x10000000)
|
||||
#define MCF_INTC_IPRL_INT29 (0x20000000)
|
||||
#define MCF_INTC_IPRL_INT30 (0x40000000)
|
||||
#define MCF_INTC_IPRL_INT31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IMRH */
|
||||
#define MCF_INTC_IMRH_INT_MASK32 (0x1)
|
||||
#define MCF_INTC_IMRH_INT_MASK33 (0x2)
|
||||
#define MCF_INTC_IMRH_INT_MASK34 (0x4)
|
||||
#define MCF_INTC_IMRH_INT_MASK35 (0x8)
|
||||
#define MCF_INTC_IMRH_INT_MASK36 (0x10)
|
||||
#define MCF_INTC_IMRH_INT_MASK37 (0x20)
|
||||
#define MCF_INTC_IMRH_INT_MASK38 (0x40)
|
||||
#define MCF_INTC_IMRH_INT_MASK39 (0x80)
|
||||
#define MCF_INTC_IMRH_INT_MASK40 (0x100)
|
||||
#define MCF_INTC_IMRH_INT_MASK41 (0x200)
|
||||
#define MCF_INTC_IMRH_INT_MASK42 (0x400)
|
||||
#define MCF_INTC_IMRH_INT_MASK43 (0x800)
|
||||
#define MCF_INTC_IMRH_INT_MASK44 (0x1000)
|
||||
#define MCF_INTC_IMRH_INT_MASK45 (0x2000)
|
||||
#define MCF_INTC_IMRH_INT_MASK46 (0x4000)
|
||||
#define MCF_INTC_IMRH_INT_MASK47 (0x8000)
|
||||
#define MCF_INTC_IMRH_INT_MASK48 (0x10000)
|
||||
#define MCF_INTC_IMRH_INT_MASK49 (0x20000)
|
||||
#define MCF_INTC_IMRH_INT_MASK50 (0x40000)
|
||||
#define MCF_INTC_IMRH_INT_MASK51 (0x80000)
|
||||
#define MCF_INTC_IMRH_INT_MASK52 (0x100000)
|
||||
#define MCF_INTC_IMRH_INT_MASK53 (0x200000)
|
||||
#define MCF_INTC_IMRH_INT_MASK54 (0x400000)
|
||||
#define MCF_INTC_IMRH_INT_MASK55 (0x800000)
|
||||
#define MCF_INTC_IMRH_INT_MASK56 (0x1000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK57 (0x2000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK58 (0x4000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK59 (0x8000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IMRL */
|
||||
#define MCF_INTC_IMRL_MASKALL (0x1)
|
||||
#define MCF_INTC_IMRL_INT_MASK1 (0x2)
|
||||
#define MCF_INTC_IMRL_INT_MASK2 (0x4)
|
||||
#define MCF_INTC_IMRL_INT_MASK3 (0x8)
|
||||
#define MCF_INTC_IMRL_INT_MASK4 (0x10)
|
||||
#define MCF_INTC_IMRL_INT_MASK5 (0x20)
|
||||
#define MCF_INTC_IMRL_INT_MASK6 (0x40)
|
||||
#define MCF_INTC_IMRL_INT_MASK7 (0x80)
|
||||
#define MCF_INTC_IMRL_INT_MASK8 (0x100)
|
||||
#define MCF_INTC_IMRL_INT_MASK9 (0x200)
|
||||
#define MCF_INTC_IMRL_INT_MASK10 (0x400)
|
||||
#define MCF_INTC_IMRL_INT_MASK11 (0x800)
|
||||
#define MCF_INTC_IMRL_INT_MASK12 (0x1000)
|
||||
#define MCF_INTC_IMRL_INT_MASK13 (0x2000)
|
||||
#define MCF_INTC_IMRL_INT_MASK14 (0x4000)
|
||||
#define MCF_INTC_IMRL_INT_MASK15 (0x8000)
|
||||
#define MCF_INTC_IMRL_INT_MASK16 (0x10000)
|
||||
#define MCF_INTC_IMRL_INT_MASK17 (0x20000)
|
||||
#define MCF_INTC_IMRL_INT_MASK18 (0x40000)
|
||||
#define MCF_INTC_IMRL_INT_MASK19 (0x80000)
|
||||
#define MCF_INTC_IMRL_INT_MASK20 (0x100000)
|
||||
#define MCF_INTC_IMRL_INT_MASK21 (0x200000)
|
||||
#define MCF_INTC_IMRL_INT_MASK22 (0x400000)
|
||||
#define MCF_INTC_IMRL_INT_MASK23 (0x800000)
|
||||
#define MCF_INTC_IMRL_INT_MASK24 (0x1000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK25 (0x2000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK26 (0x4000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK27 (0x8000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_INTFRCH */
|
||||
#define MCF_INTC_INTFRCH_INTFRC32 (0x1)
|
||||
#define MCF_INTC_INTFRCH_INTFRC33 (0x2)
|
||||
#define MCF_INTC_INTFRCH_INTFRC34 (0x4)
|
||||
#define MCF_INTC_INTFRCH_INTFRC35 (0x8)
|
||||
#define MCF_INTC_INTFRCH_INTFRC36 (0x10)
|
||||
#define MCF_INTC_INTFRCH_INTFRC37 (0x20)
|
||||
#define MCF_INTC_INTFRCH_INTFRC38 (0x40)
|
||||
#define MCF_INTC_INTFRCH_INTFRC39 (0x80)
|
||||
#define MCF_INTC_INTFRCH_INTFRC40 (0x100)
|
||||
#define MCF_INTC_INTFRCH_INTFRC41 (0x200)
|
||||
#define MCF_INTC_INTFRCH_INTFRC42 (0x400)
|
||||
#define MCF_INTC_INTFRCH_INTFRC43 (0x800)
|
||||
#define MCF_INTC_INTFRCH_INTFRC44 (0x1000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC45 (0x2000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC46 (0x4000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC47 (0x8000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC48 (0x10000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC49 (0x20000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC50 (0x40000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC51 (0x80000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC52 (0x100000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC53 (0x200000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC54 (0x400000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC55 (0x800000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_INTFRCL */
|
||||
#define MCF_INTC_INTFRCL_INTFRC1 (0x2)
|
||||
#define MCF_INTC_INTFRCL_INTFRC2 (0x4)
|
||||
#define MCF_INTC_INTFRCL_INTFRC3 (0x8)
|
||||
#define MCF_INTC_INTFRCL_INTFRC4 (0x10)
|
||||
#define MCF_INTC_INTFRCL_INTFRC5 (0x20)
|
||||
#define MCF_INTC_INTFRCL_INTFRC6 (0x40)
|
||||
#define MCF_INTC_INTFRCL_INTFRC7 (0x80)
|
||||
#define MCF_INTC_INTFRCL_INTFRC8 (0x100)
|
||||
#define MCF_INTC_INTFRCL_INTFRC9 (0x200)
|
||||
#define MCF_INTC_INTFRCL_INTFRC10 (0x400)
|
||||
#define MCF_INTC_INTFRCL_INTFRC11 (0x800)
|
||||
#define MCF_INTC_INTFRCL_INTFRC12 (0x1000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC13 (0x2000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC14 (0x4000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC15 (0x8000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC16 (0x10000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC17 (0x20000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC18 (0x40000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC19 (0x80000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC20 (0x100000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC21 (0x200000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC22 (0x400000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC23 (0x800000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IRLR */
|
||||
#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IACKLPR */
|
||||
#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0)
|
||||
#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_ICR */
|
||||
#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0)
|
||||
#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_SWIACK */
|
||||
#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_LIACK */
|
||||
#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF5475_INTC_H__ */
|
||||
376
include/MCF5475_PCI.h
Normal file
376
include/MCF5475_PCI.h
Normal file
@@ -0,0 +1,376 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_PCI_H__
|
||||
#define __MCF5475_PCI_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* PCI Bus Controller (PCI)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PCI_PCIIDR (*(volatile uint32_t*)(&_MBAR[0xB00]))
|
||||
#define MCF_PCI_PCISCR (*(volatile uint32_t*)(&_MBAR[0xB04]))
|
||||
#define MCF_PCI_PCICCRIR (*(volatile uint32_t*)(&_MBAR[0xB08]))
|
||||
#define MCF_PCI_PCICR1 (*(volatile uint32_t*)(&_MBAR[0xB0C]))
|
||||
#define MCF_PCI_PCIBAR0 (*(volatile uint32_t*)(&_MBAR[0xB10]))
|
||||
#define MCF_PCI_PCIBAR1 (*(volatile uint32_t*)(&_MBAR[0xB14]))
|
||||
#define MCF_PCI_PCICCPR (*(volatile uint32_t*)(&_MBAR[0xB28]))
|
||||
#define MCF_PCI_PCISID (*(volatile uint32_t*)(&_MBAR[0xB2C]))
|
||||
#define MCF_PCI_PCICR2 (*(volatile uint32_t*)(&_MBAR[0xB3C]))
|
||||
#define MCF_PCI_PCIGSCR (*(volatile uint32_t*)(&_MBAR[0xB60]))
|
||||
#define MCF_PCI_PCITBATR0 (*(volatile uint32_t*)(&_MBAR[0xB64]))
|
||||
#define MCF_PCI_PCITBATR1 (*(volatile uint32_t*)(&_MBAR[0xB68]))
|
||||
#define MCF_PCI_PCITCR (*(volatile uint32_t*)(&_MBAR[0xB6C]))
|
||||
#define MCF_PCI_PCIIW0BTAR (*(volatile uint32_t*)(&_MBAR[0xB70]))
|
||||
#define MCF_PCI_PCIIW1BTAR (*(volatile uint32_t*)(&_MBAR[0xB74]))
|
||||
#define MCF_PCI_PCIIW2BTAR (*(volatile uint32_t*)(&_MBAR[0xB78]))
|
||||
#define MCF_PCI_PCIIWCR (*(volatile uint32_t*)(&_MBAR[0xB80]))
|
||||
#define MCF_PCI_PCIICR (*(volatile uint32_t*)(&_MBAR[0xB84]))
|
||||
#define MCF_PCI_PCIISR (*(volatile uint32_t*)(&_MBAR[0xB88]))
|
||||
#define MCF_PCI_PCICAR (*(volatile uint32_t*)(&_MBAR[0xBF8]))
|
||||
#define MCF_PCI_PCITPSR (*(volatile uint32_t*)(&_MBAR[0x8400]))
|
||||
#define MCF_PCI_PCITSAR (*(volatile uint32_t*)(&_MBAR[0x8404]))
|
||||
#define MCF_PCI_PCITTCR (*(volatile uint32_t*)(&_MBAR[0x8408]))
|
||||
#define MCF_PCI_PCITER (*(volatile uint32_t*)(&_MBAR[0x840C]))
|
||||
#define MCF_PCI_PCITNAR (*(volatile uint32_t*)(&_MBAR[0x8410]))
|
||||
#define MCF_PCI_PCITLWR (*(volatile uint32_t*)(&_MBAR[0x8414]))
|
||||
#define MCF_PCI_PCITDCR (*(volatile uint32_t*)(&_MBAR[0x8418]))
|
||||
#define MCF_PCI_PCITSR (*(volatile uint32_t*)(&_MBAR[0x841C]))
|
||||
#define MCF_PCI_PCITFDR (*(volatile uint32_t*)(&_MBAR[0x8440]))
|
||||
#define MCF_PCI_PCITFSR (*(volatile uint32_t*)(&_MBAR[0x8444]))
|
||||
#define MCF_PCI_PCITFCR (*(volatile uint32_t*)(&_MBAR[0x8448]))
|
||||
#define MCF_PCI_PCITFAR (*(volatile uint32_t*)(&_MBAR[0x844C]))
|
||||
#define MCF_PCI_PCITFRPR (*(volatile uint32_t*)(&_MBAR[0x8450]))
|
||||
#define MCF_PCI_PCITFWPR (*(volatile uint32_t*)(&_MBAR[0x8454]))
|
||||
#define MCF_PCI_PCIRPSR (*(volatile uint32_t*)(&_MBAR[0x8480]))
|
||||
#define MCF_PCI_PCIRSAR (*(volatile uint32_t*)(&_MBAR[0x8484]))
|
||||
#define MCF_PCI_PCIRTCR (*(volatile uint32_t*)(&_MBAR[0x8488]))
|
||||
#define MCF_PCI_PCIRER (*(volatile uint32_t*)(&_MBAR[0x848C]))
|
||||
#define MCF_PCI_PCIRNAR (*(volatile uint32_t*)(&_MBAR[0x8490]))
|
||||
#define MCF_PCI_PCIRDCR (*(volatile uint32_t*)(&_MBAR[0x8498]))
|
||||
#define MCF_PCI_PCIRSR (*(volatile uint32_t*)(&_MBAR[0x849C]))
|
||||
#define MCF_PCI_PCIRFDR (*(volatile uint32_t*)(&_MBAR[0x84C0]))
|
||||
#define MCF_PCI_PCIRFSR (*(volatile uint32_t*)(&_MBAR[0x84C4]))
|
||||
#define MCF_PCI_PCIRFCR (*(volatile uint32_t*)(&_MBAR[0x84C8]))
|
||||
#define MCF_PCI_PCIRFAR (*(volatile uint32_t*)(&_MBAR[0x84CC]))
|
||||
#define MCF_PCI_PCIRFRPR (*(volatile uint32_t*)(&_MBAR[0x84D0]))
|
||||
#define MCF_PCI_PCIRFWPR (*(volatile uint32_t*)(&_MBAR[0x84D4]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIIDR */
|
||||
#define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCISCR */
|
||||
#define MCF_PCI_PCISCR_IO (0x1)
|
||||
#define MCF_PCI_PCISCR_M (0x2)
|
||||
#define MCF_PCI_PCISCR_B (0x4)
|
||||
#define MCF_PCI_PCISCR_SP (0x8)
|
||||
#define MCF_PCI_PCISCR_MW (0x10)
|
||||
#define MCF_PCI_PCISCR_V (0x20)
|
||||
#define MCF_PCI_PCISCR_PER (0x40)
|
||||
#define MCF_PCI_PCISCR_ST (0x80)
|
||||
#define MCF_PCI_PCISCR_S (0x100)
|
||||
#define MCF_PCI_PCISCR_F (0x200)
|
||||
#define MCF_PCI_PCISCR_C (0x100000)
|
||||
#define MCF_PCI_PCISCR_66M (0x200000)
|
||||
#define MCF_PCI_PCISCR_R (0x400000)
|
||||
#define MCF_PCI_PCISCR_FC (0x800000)
|
||||
#define MCF_PCI_PCISCR_DP (0x1000000)
|
||||
#define MCF_PCI_PCISCR_DT(x) (((x)&0x3)<<0x19)
|
||||
#define MCF_PCI_PCISCR_TS (0x8000000)
|
||||
#define MCF_PCI_PCISCR_TR (0x10000000)
|
||||
#define MCF_PCI_PCISCR_MA (0x20000000)
|
||||
#define MCF_PCI_PCISCR_SE (0x40000000)
|
||||
#define MCF_PCI_PCISCR_PE (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCICCRIR */
|
||||
#define MCF_PCI_PCICCRIR_REVISIONID(x) (((x)&0xFF)<<0)
|
||||
#define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0xFFFFFF)<<0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCICR1 */
|
||||
#define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0xFF)<<0)
|
||||
#define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0xFF)<<0x8)
|
||||
#define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0xFF)<<0x10)
|
||||
#define MCF_PCI_PCICR1_BIST(x) (((x)&0xFF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIBAR0 */
|
||||
#define MCF_PCI_PCIBAR0_IOM (0x1)
|
||||
#define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x3)<<0x1)
|
||||
#define MCF_PCI_PCIBAR0_PREF (0x8)
|
||||
#define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x3FFF)<<0x12)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIBAR1 */
|
||||
#define MCF_PCI_PCIBAR1_IOM (0x1)
|
||||
#define MCF_PCI_PCIBAR1_RANGE(x) (((x)&0x3)<<0x1)
|
||||
#define MCF_PCI_PCIBAR1_PREF (0x8)
|
||||
#define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x3)<<0x1E)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCICCPR */
|
||||
#define MCF_PCI_PCICCPR_PCICCP(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCISID */
|
||||
#define MCF_PCI_PCISID_VENDORID(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCICR2 */
|
||||
#define MCF_PCI_PCICR2_INTLINE(x) (((x)&0xFF)<<0)
|
||||
#define MCF_PCI_PCICR2_INTPIN(x) (((x)&0xFF)<<0x8)
|
||||
#define MCF_PCI_PCICR2_MINGNT(x) (((x)&0xFF)<<0x10)
|
||||
#define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0xFF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIGSCR */
|
||||
#define MCF_PCI_PCIGSCR_PR (0x1)
|
||||
#define MCF_PCI_PCIGSCR_SEE (0x1000)
|
||||
#define MCF_PCI_PCIGSCR_PEE (0x2000)
|
||||
#define MCF_PCI_PCIGSCR_CLKINRESERVED(x) (((x)&0x7)<<0x10)
|
||||
#define MCF_PCI_PCIGSCR_XLB2CLKIN(x) (((x)&0x7)<<0x18)
|
||||
#define MCF_PCI_PCIGSCR_SE (0x10000000)
|
||||
#define MCF_PCI_PCIGSCR_PE (0x20000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITBATR0 */
|
||||
#define MCF_PCI_PCITBATR0_EN (0x1)
|
||||
#define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x3FFF)<<0x12)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITBATR1 */
|
||||
#define MCF_PCI_PCITBATR1_EN (0x1)
|
||||
#define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x3)<<0x1E)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITCR */
|
||||
#define MCF_PCI_PCITCR_P (0x10000)
|
||||
#define MCF_PCI_PCITCR_LD (0x1000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */
|
||||
#define MCF_PCI_PCIIW0BTAR_WTA0(x) (((x)&0xFF)<<0x8)
|
||||
#define MCF_PCI_PCIIW0BTAR_WAM0(x) (((x)&0xFF)<<0x10)
|
||||
#define MCF_PCI_PCIIW0BTAR_WBA0(x) (((x)&0xFF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */
|
||||
#define MCF_PCI_PCIIW1BTAR_WTA1(x) (((x)&0xFF)<<0x8)
|
||||
#define MCF_PCI_PCIIW1BTAR_WAM1(x) (((x)&0xFF)<<0x10)
|
||||
#define MCF_PCI_PCIIW1BTAR_WBA1(x) (((x)&0xFF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */
|
||||
#define MCF_PCI_PCIIW2BTAR_WTA2(x) (((x)&0xFF)<<0x8)
|
||||
#define MCF_PCI_PCIIW2BTAR_WAM2(x) (((x)&0xFF)<<0x10)
|
||||
#define MCF_PCI_PCIIW2BTAR_WBA2(x) (((x)&0xFF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIIWCR */
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL2_E (0x100)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL2_PRC(x) (((x)&0x3)<<0x9)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL2_IOM (0x800)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL1_E (0x10000)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL1_PRC(x) (((x)&0x3)<<0x11)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL1_IOM (0x80000)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL0_E (0x1000000)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL0_PRC(x) (((x)&0x3)<<0x19)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL0_IOM (0x8000000)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x100)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x300)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x500)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x900)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x10000)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x30000)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x50000)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x90000)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x1000000)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x3000000)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x5000000)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x9000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIICR */
|
||||
#define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0xFF)<<0)
|
||||
#define MCF_PCI_PCIICR_TAE (0x1000000)
|
||||
#define MCF_PCI_PCIICR_IAE (0x2000000)
|
||||
#define MCF_PCI_PCIICR_REE (0x4000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIISR */
|
||||
#define MCF_PCI_PCIISR_TA (0x1000000)
|
||||
#define MCF_PCI_PCIISR_IA (0x2000000)
|
||||
#define MCF_PCI_PCIISR_RE (0x4000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCICAR */
|
||||
#define MCF_PCI_PCICAR_DWORD(x) (((x)&0x3F)<<0x2)
|
||||
#define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x7)<<0x8)
|
||||
#define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x1F)<<0xB)
|
||||
#define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0xFF)<<0x10)
|
||||
#define MCF_PCI_PCICAR_E (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITPSR */
|
||||
#define MCF_PCI_PCITPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITSAR */
|
||||
#define MCF_PCI_PCITSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITTCR */
|
||||
#define MCF_PCI_PCITTCR_DI (0x1)
|
||||
#define MCF_PCI_PCITTCR_W (0x10)
|
||||
#define MCF_PCI_PCITTCR_MAXBEATS(x) (((x)&0x7)<<0x8)
|
||||
#define MCF_PCI_PCITTCR_MAXRETRY(x) (((x)&0xFF)<<0x10)
|
||||
#define MCF_PCI_PCITTCR_PCICMD(x) (((x)&0xF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITER */
|
||||
#define MCF_PCI_PCITER_NE (0x10000)
|
||||
#define MCF_PCI_PCITER_IAE (0x20000)
|
||||
#define MCF_PCI_PCITER_TAE (0x40000)
|
||||
#define MCF_PCI_PCITER_RE (0x80000)
|
||||
#define MCF_PCI_PCITER_SE (0x100000)
|
||||
#define MCF_PCI_PCITER_FEE (0x200000)
|
||||
#define MCF_PCI_PCITER_ME (0x1000000)
|
||||
#define MCF_PCI_PCITER_BE (0x8000000)
|
||||
#define MCF_PCI_PCITER_CM (0x10000000)
|
||||
#define MCF_PCI_PCITER_RF (0x40000000)
|
||||
#define MCF_PCI_PCITER_RC (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITNAR */
|
||||
#define MCF_PCI_PCITNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITLWR */
|
||||
#define MCF_PCI_PCITLWR_LASTWORD(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITDCR */
|
||||
#define MCF_PCI_PCITDCR_PKTSDONE(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_PCI_PCITDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITSR */
|
||||
#define MCF_PCI_PCITSR_IA (0x10000)
|
||||
#define MCF_PCI_PCITSR_TA (0x20000)
|
||||
#define MCF_PCI_PCITSR_RE (0x40000)
|
||||
#define MCF_PCI_PCITSR_SE (0x80000)
|
||||
#define MCF_PCI_PCITSR_FE (0x100000)
|
||||
#define MCF_PCI_PCITSR_BE1 (0x200000)
|
||||
#define MCF_PCI_PCITSR_BE2 (0x400000)
|
||||
#define MCF_PCI_PCITSR_BE3 (0x800000)
|
||||
#define MCF_PCI_PCITSR_NT (0x1000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITFDR */
|
||||
#define MCF_PCI_PCITFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITFSR */
|
||||
#define MCF_PCI_PCITFSR_EMPTY (0x10000)
|
||||
#define MCF_PCI_PCITFSR_ALARM (0x20000)
|
||||
#define MCF_PCI_PCITFSR_FULL (0x40000)
|
||||
#define MCF_PCI_PCITFSR_FR (0x80000)
|
||||
#define MCF_PCI_PCITFSR_OF (0x100000)
|
||||
#define MCF_PCI_PCITFSR_UF (0x200000)
|
||||
#define MCF_PCI_PCITFSR_RXW (0x400000)
|
||||
#define MCF_PCI_PCITFSR_FAE (0x800000)
|
||||
#define MCF_PCI_PCITFSR_TXW (0x40000000)
|
||||
#define MCF_PCI_PCITFSR_IP (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITFCR */
|
||||
#define MCF_PCI_PCITFCR_TXW_MASK (0x40000)
|
||||
#define MCF_PCI_PCITFCR_OF_MASK (0x80000)
|
||||
#define MCF_PCI_PCITFCR_UF_MASK (0x100000)
|
||||
#define MCF_PCI_PCITFCR_RXW_MASK (0x200000)
|
||||
#define MCF_PCI_PCITFCR_FAE_MASK (0x400000)
|
||||
#define MCF_PCI_PCITFCR_IP_MASK (0x800000)
|
||||
#define MCF_PCI_PCITFCR_GR(x) (((x)&0x7)<<0x18)
|
||||
#define MCF_PCI_PCITFCR_WFR (0x20000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITFAR */
|
||||
#define MCF_PCI_PCITFAR_ALARM(x) (((x)&0xFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITFRPR */
|
||||
#define MCF_PCI_PCITFRPR_READPTR(x) (((x)&0x7F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITFWPR */
|
||||
#define MCF_PCI_PCITFWPR_WRITEPTR(x) (((x)&0x7F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRPSR */
|
||||
#define MCF_PCI_PCIRPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRSAR */
|
||||
#define MCF_PCI_PCIRSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRTCR */
|
||||
#define MCF_PCI_PCIRTCR_DI (0x1)
|
||||
#define MCF_PCI_PCIRTCR_W (0x10)
|
||||
#define MCF_PCI_PCIRTCR_MAXBEATS(x) (((x)&0x7)<<0x8)
|
||||
#define MCF_PCI_PCIRTCR_FB (0x1000)
|
||||
#define MCF_PCI_PCIRTCR_MAXRETRY(x) (((x)&0xFF)<<0x10)
|
||||
#define MCF_PCI_PCIRTCR_PCICMD(x) (((x)&0xF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRER */
|
||||
#define MCF_PCI_PCIRER_NE (0x10000)
|
||||
#define MCF_PCI_PCIRER_IAE (0x20000)
|
||||
#define MCF_PCI_PCIRER_TAE (0x40000)
|
||||
#define MCF_PCI_PCIRER_RE (0x80000)
|
||||
#define MCF_PCI_PCIRER_SE (0x100000)
|
||||
#define MCF_PCI_PCIRER_FEE (0x200000)
|
||||
#define MCF_PCI_PCIRER_ME (0x1000000)
|
||||
#define MCF_PCI_PCIRER_BE (0x8000000)
|
||||
#define MCF_PCI_PCIRER_CM (0x10000000)
|
||||
#define MCF_PCI_PCIRER_FE (0x20000000)
|
||||
#define MCF_PCI_PCIRER_RF (0x40000000)
|
||||
#define MCF_PCI_PCIRER_RC (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRNAR */
|
||||
#define MCF_PCI_PCIRNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRDCR */
|
||||
#define MCF_PCI_PCIRDCR_PKTSDONE(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_PCI_PCIRDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRSR */
|
||||
#define MCF_PCI_PCIRSR_IA (0x10000)
|
||||
#define MCF_PCI_PCIRSR_TA (0x20000)
|
||||
#define MCF_PCI_PCIRSR_RE (0x40000)
|
||||
#define MCF_PCI_PCIRSR_SE (0x80000)
|
||||
#define MCF_PCI_PCIRSR_FE (0x100000)
|
||||
#define MCF_PCI_PCIRSR_BE1 (0x200000)
|
||||
#define MCF_PCI_PCIRSR_BE2 (0x400000)
|
||||
#define MCF_PCI_PCIRSR_BE3 (0x800000)
|
||||
#define MCF_PCI_PCIRSR_NT (0x1000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRFDR */
|
||||
#define MCF_PCI_PCIRFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRFSR */
|
||||
#define MCF_PCI_PCIRFSR_EMPTY (0x10000)
|
||||
#define MCF_PCI_PCIRFSR_ALARM (0x20000)
|
||||
#define MCF_PCI_PCIRFSR_FULL (0x40000)
|
||||
#define MCF_PCI_PCIRFSR_FR (0x80000)
|
||||
#define MCF_PCI_PCIRFSR_OF (0x100000)
|
||||
#define MCF_PCI_PCIRFSR_UF (0x200000)
|
||||
#define MCF_PCI_PCIRFSR_RXW (0x400000)
|
||||
#define MCF_PCI_PCIRFSR_FAE (0x800000)
|
||||
#define MCF_PCI_PCIRFSR_TXW (0x40000000)
|
||||
#define MCF_PCI_PCIRFSR_IP (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRFCR */
|
||||
#define MCF_PCI_PCIRFCR_TXW_MASK (0x40000)
|
||||
#define MCF_PCI_PCIRFCR_OF_MASK (0x80000)
|
||||
#define MCF_PCI_PCIRFCR_UF_MASK (0x100000)
|
||||
#define MCF_PCI_PCIRFCR_RXW_MASK (0x200000)
|
||||
#define MCF_PCI_PCIRFCR_FAE_MASK (0x400000)
|
||||
#define MCF_PCI_PCIRFCR_IP_MASK (0x800000)
|
||||
#define MCF_PCI_PCIRFCR_GR(x) (((x)&0x7)<<0x18)
|
||||
#define MCF_PCI_PCIRFCR_WFR (0x20000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRFAR */
|
||||
#define MCF_PCI_PCIRFAR_ALARM(x) (((x)&0x7F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRFRPR */
|
||||
#define MCF_PCI_PCIRFRPR_READPTR(x) (((x)&0x7F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRFWPR */
|
||||
#define MCF_PCI_PCIRFWPR_WRITEPTR(x) (((x)&0x7F)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF5475_PCI_H__ */
|
||||
99
include/arp.h
Normal file
99
include/arp.h
Normal file
@@ -0,0 +1,99 @@
|
||||
/*
|
||||
* File: arp.h
|
||||
* Purpose: ARP definitions.
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#ifndef _ARP_H
|
||||
#define _ARP_H
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
/*
|
||||
* This data definition is defined for Ethernet only!
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t ar_hrd;
|
||||
uint16_t ar_pro;
|
||||
uint8_t ar_hln;
|
||||
uint8_t ar_pln;
|
||||
uint16_t opcode;
|
||||
uint8_t ar_sha[6]; /* ethernet hw address */
|
||||
uint8_t ar_spa[4]; /* ip address */
|
||||
uint8_t ar_tha[6]; /* ethernet hw address */
|
||||
uint8_t ar_tpa[4]; /* ip address */
|
||||
} arp_frame_hdr;
|
||||
|
||||
#define ARP_HDR_LEN sizeof(arp_frame_hdr)
|
||||
|
||||
/*
|
||||
* ARP table entry definition. Note that this table only designed
|
||||
* with Ethernet and IP in mind.
|
||||
*/
|
||||
#define MAX_HWA_SIZE (6) /* 6 is enough for Ethernet address */
|
||||
#define MAX_PA_SIZE (4) /* 4 is enough for Protocol address */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t protocol;
|
||||
uint8_t hwa_size;
|
||||
uint8_t hwa[MAX_HWA_SIZE];
|
||||
uint8_t pa_size;
|
||||
uint8_t pa[MAX_PA_SIZE];
|
||||
int longevity;
|
||||
} ARPENTRY;
|
||||
#define MAX_ARP_ENTRY (10)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int tab_size;
|
||||
ARPENTRY table[MAX_ARP_ENTRY];
|
||||
} ARP_INFO;
|
||||
|
||||
#define ARP_ENTRY_EMPTY (0)
|
||||
#define ARP_ENTRY_PERM (1)
|
||||
#define ARP_ENTRY_TEMP (2)
|
||||
|
||||
|
||||
#define ETHERNET (1)
|
||||
#define ARP_REQUEST (1)
|
||||
#define ARP_REPLY (2)
|
||||
|
||||
#define ARP_TIMEOUT (1) /* Timeout in seconds */
|
||||
|
||||
/* Protocol Header information */
|
||||
#define ARP_HDR_OFFSET ETH_HDR_LEN
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
uint8_t *
|
||||
arp_get_mypa (void);
|
||||
|
||||
uint8_t *
|
||||
arp_get_myha (void);
|
||||
|
||||
uint8_t *
|
||||
arp_get_broadcast (void);
|
||||
|
||||
void
|
||||
arp_merge (ARP_INFO *, uint16_t, int, uint8_t *, int, uint8_t *, int);
|
||||
|
||||
void
|
||||
arp_remove (ARP_INFO *, uint16_t, uint8_t *, uint8_t *);
|
||||
|
||||
void
|
||||
arp_request (NIF *, uint8_t *);
|
||||
|
||||
void
|
||||
arp_handler (NIF *, NBUF *);
|
||||
|
||||
uint8_t *
|
||||
arp_resolve (NIF *, uint16_t, uint8_t *);
|
||||
|
||||
void
|
||||
arp_init (ARP_INFO *);
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* _ARP_H */
|
||||
42
include/bas_printf.h
Normal file
42
include/bas_printf.h
Normal file
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _BAS_PRINTF_H_
|
||||
#define _BAS_PRINTF_H_
|
||||
#include <stdarg.h>
|
||||
#include <stddef.h>
|
||||
#include "MCF5475.h"
|
||||
|
||||
extern void xvsnprintf(char *str, size_t size, const char *fmt, va_list va);
|
||||
extern void xvprintf(const char *fmt, va_list va);
|
||||
extern void xprintf(const char *fmt, ...);
|
||||
extern void xsnprintf(char *str, size_t size, const char *fmt, ...);
|
||||
extern int sprintf(char *str, const char *format, ...);
|
||||
|
||||
extern bool conoutstat(void);
|
||||
extern bool coninstat(void);
|
||||
extern void xputchar(int c);
|
||||
extern char xgetchar(void);
|
||||
|
||||
|
||||
extern void display_progress(void);
|
||||
extern void hexdump(uint8_t buffer[], int size);
|
||||
|
||||
|
||||
#endif /* _BAS_PRINTF_H_ */
|
||||
63
include/conout.h
Executable file
63
include/conout.h
Executable file
@@ -0,0 +1,63 @@
|
||||
#ifndef __CONOUT_H__
|
||||
#define __CONOUT_H__
|
||||
|
||||
#include "bas_types.h"
|
||||
|
||||
/*
|
||||
* conout.h - lowlevel color model dependent screen handling routines
|
||||
*
|
||||
*
|
||||
* Copyright (C) 2004-2016 by Authors:
|
||||
*
|
||||
* Authors:
|
||||
* MAD Martin Doering
|
||||
*
|
||||
* This file is distributed under the GPL, version 2 or at your
|
||||
* option any later version. See doc/license.txt for details.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* Defines for cursor */
|
||||
#define M_CFLASH 0x0001 /* cursor flash 0:disabled 1:enabled */
|
||||
#define M_CSTATE 0x0002 /* cursor flash state 0:off 1:on */
|
||||
#define M_CVIS 0x0004 /* cursor visibility 0:invisible 1:visible */
|
||||
|
||||
/*
|
||||
* The visibility flag is also used as a semaphore to prevent
|
||||
* the interrupt-driven cursor blink logic from colliding with
|
||||
* escape function/sequence cursor drawing activity.
|
||||
*/
|
||||
|
||||
#define M_CEOL 0x0008 /* end of line handling 0:overwrite 1:wrap */
|
||||
#define M_REVID 0x0010 /* reverse video 0:on 1:off */
|
||||
#define M_SVPOS 0x0020 /* position saved flag. 0:false, 1:true */
|
||||
#define M_CRIT 0x0040 /* reverse video 0:on 1:off */
|
||||
|
||||
/* Color related linea variables */
|
||||
|
||||
extern int16_t v_col_bg; /* current background color */
|
||||
extern int16_t v_col_fg; /* current foreground color */
|
||||
|
||||
/* Cursor related linea variables */
|
||||
|
||||
extern uint8_t *v_cur_ad; /* current cursor address */
|
||||
extern int16_t v_cur_of; /* cursor offset */
|
||||
extern int8_t v_cur_tim; /* cursor blink timer */
|
||||
|
||||
extern int8_t v_period;
|
||||
extern int16_t disab_cnt; /* disable depth count. (>0 means disabled) */
|
||||
extern int8_t v_stat_0; /* video cell system status */
|
||||
extern int16_t sav_cur_x; /* saved cursor cell x */
|
||||
extern int16_t sav_cur_y; /* saved cursor cell y */
|
||||
|
||||
/* Prototypes */
|
||||
|
||||
extern void ascii_out(int);
|
||||
extern void move_cursor(int, int);
|
||||
extern void blank_out (int, int, int, int);
|
||||
extern void invert_cell(int, int);
|
||||
extern void scroll_up(int);
|
||||
extern void scroll_down(int);
|
||||
|
||||
#endif /* __CONOUT_H__ */
|
||||
91
include/diskio.h
Normal file
91
include/diskio.h
Normal file
@@ -0,0 +1,91 @@
|
||||
/*-----------------------------------------------------------------------
|
||||
/ Low level disk interface modlue include file (C)ChaN, 2012
|
||||
/-----------------------------------------------------------------------*/
|
||||
|
||||
#ifndef _DISKIO_DEFINED
|
||||
#define _DISKIO_DEFINED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define _USE_WRITE 1 /* 1: Enable disk_write function */
|
||||
#define _USE_IOCTL 1 /* 1: Enable disk_ioctl fucntion */
|
||||
|
||||
#include <bas_types.h>
|
||||
|
||||
|
||||
/* Status of Disk Functions */
|
||||
typedef uint8_t DSTATUS;
|
||||
|
||||
/* Results of Disk Functions */
|
||||
typedef enum {
|
||||
RES_OK = 0, /* 0: Successful */
|
||||
RES_ERROR, /* 1: R/W Error */
|
||||
RES_WRPRT, /* 2: Write Protected */
|
||||
RES_NOTRDY, /* 3: Not Ready */
|
||||
RES_PARERR /* 4: Invalid Parameter */
|
||||
} DRESULT;
|
||||
|
||||
|
||||
/*---------------------------------------*/
|
||||
/* Prototypes for disk control functions */
|
||||
|
||||
|
||||
DSTATUS disk_initialize (uint8_t);
|
||||
DSTATUS disk_reset(uint8_t);
|
||||
DSTATUS disk_status (uint8_t);
|
||||
DRESULT disk_read (uint8_t, uint8_t*, uint32_t, uint8_t);
|
||||
#if _READONLY == 0
|
||||
DRESULT disk_write (uint8_t, const uint8_t*, uint32_t, uint8_t);
|
||||
#endif
|
||||
DRESULT disk_ioctl (uint8_t, uint8_t, void*);
|
||||
|
||||
|
||||
/* Disk Status Bits (DSTATUS) */
|
||||
#define STA_NOINIT 0x01 /* Drive not initialized */
|
||||
#define STA_NODISK 0x02 /* No medium in the drive */
|
||||
#define STA_PROTECT 0x04 /* Write protected */
|
||||
|
||||
|
||||
/* Command code for disk_ioctrl fucntion */
|
||||
|
||||
/* Generic command (used by FatFs) */
|
||||
#define CTRL_SYNC 0 /* Flush disk cache (for write functions) */
|
||||
#define GET_SECTOR_COUNT 1 /* Get media size (for only f_mkfs()) */
|
||||
#define GET_SECTOR_SIZE 2 /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */
|
||||
#define GET_BLOCK_SIZE 3 /* Get erase block size (for only f_mkfs()) */
|
||||
#define CTRL_ERASE_SECTOR 4 /* Force erased a block of sectors (for only _USE_ERASE) */
|
||||
|
||||
/* Generic command (not used by FatFs) */
|
||||
#define CTRL_POWER 5 /* Get/Set power status */
|
||||
#define CTRL_LOCK 6 /* Lock/Unlock media removal */
|
||||
#define CTRL_EJECT 7 /* Eject media */
|
||||
#define CTRL_FORMAT 8 /* Create physical format on the media */
|
||||
|
||||
/* MMC/SDC specific ioctl command */
|
||||
#define MMC_GET_TYPE 10 /* Get card type */
|
||||
#define MMC_GET_CSD 11 /* Get CSD */
|
||||
#define MMC_GET_CID 12 /* Get CID */
|
||||
#define MMC_GET_OCR 13 /* Get OCR */
|
||||
#define MMC_GET_SDSTAT 14 /* Get SD status */
|
||||
|
||||
/* ATA/CF specific ioctl command */
|
||||
#define ATA_GET_REV 20 /* Get F/W revision */
|
||||
#define ATA_GET_MODEL 21 /* Get model name */
|
||||
#define ATA_GET_SN 22 /* Get serial number */
|
||||
|
||||
|
||||
/* MMC card type flags (MMC_GET_TYPE) */
|
||||
#define CT_MMC 0x01 /* MMC ver 3 */
|
||||
#define CT_SD1 0x02 /* SD ver 1 */
|
||||
#define CT_SD2 0x04 /* SD ver 2 */
|
||||
#define CT_SDC (CT_SD1 | CT_SD2) /* SD */
|
||||
#define CT_BLOCK 0x08 /* Block addressing */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
43
include/dma.h
Normal file
43
include/dma.h
Normal file
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
* spidma.h *
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 26.02.2013
|
||||
* Author: Markus Fröschle
|
||||
*/
|
||||
|
||||
#ifndef _DMA_H_
|
||||
#define _DMA_H_
|
||||
|
||||
#include "MCF5475.h"
|
||||
#include "MCD_dma.h"
|
||||
#include "bas_string.h"
|
||||
|
||||
void *dma_memcpy(void *dst, void *src, size_t n);
|
||||
extern int dma_init(void);
|
||||
extern int dma_get_channel(int requestor);
|
||||
extern int dma_set_channel(int, void (*)(void));
|
||||
extern void dma_free_channel(int requestor);
|
||||
extern void dma_clear_channel(int channel);
|
||||
extern uint32_t dma_get_initiator(int requestor);
|
||||
extern int dma_set_initiator(int initiator);
|
||||
extern void dma_free_initiator(int initiator);
|
||||
extern void dma_irq_enable(void);
|
||||
extern void dma_irq_disable(void);
|
||||
extern bool dma_interrupt_handler(void *arg1, void *arg2);
|
||||
|
||||
|
||||
#endif /* _DMA_H_ */
|
||||
96
include/fec.h
Normal file
96
include/fec.h
Normal file
@@ -0,0 +1,96 @@
|
||||
/*
|
||||
* File: fec.h
|
||||
* Purpose: Driver for the Fast Ethernet Controller (FEC)
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#ifndef _FEC_H_
|
||||
#define _FEC_H_
|
||||
|
||||
/********************************************************************/
|
||||
/* MII Speed Settings */
|
||||
#define FEC_MII_10BASE_T 0
|
||||
#define FEC_MII_100BASE_TX 1
|
||||
|
||||
/* MII Duplex Settings */
|
||||
#define FEC_MII_HALF_DUPLEX 0
|
||||
#define FEC_MII_FULL_DUPLEX 1
|
||||
|
||||
/* Timeout for MII communications */
|
||||
#define FEC_MII_TIMEOUT 0x10000
|
||||
|
||||
/* External Interface Modes */
|
||||
#define FEC_MODE_7WIRE 0
|
||||
#define FEC_MODE_MII 1
|
||||
#define FEC_MODE_LOOPBACK 2 /* Internal Loopback */
|
||||
|
||||
/*
|
||||
* FEC Event Log
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
int total; /* total count of errors */
|
||||
int hberr; /* heartbeat error */
|
||||
int babr; /* babbling receiver */
|
||||
int babt; /* babbling transmitter */
|
||||
int gra; /* graceful stop complete */
|
||||
int txf; /* transmit frame */
|
||||
int mii; /* MII */
|
||||
int lc; /* late collision */
|
||||
int rl; /* collision retry limit */
|
||||
int xfun; /* transmit FIFO underrrun */
|
||||
int xferr; /* transmit FIFO error */
|
||||
int rferr; /* receive FIFO error */
|
||||
int dtxf; /* DMA transmit frame */
|
||||
int drxf; /* DMA receive frame */
|
||||
int rfsw_inv; /* Invalid bit in RFSW */
|
||||
int rfsw_l; /* RFSW Last in Frame */
|
||||
int rfsw_m; /* RFSW Miss */
|
||||
int rfsw_bc; /* RFSW Broadcast */
|
||||
int rfsw_mc; /* RFSW Multicast */
|
||||
int rfsw_lg; /* RFSW Length Violation */
|
||||
int rfsw_no; /* RFSW Non-octet */
|
||||
int rfsw_cr; /* RFSW Bad CRC */
|
||||
int rfsw_ov; /* RFSW Overflow */
|
||||
int rfsw_tr; /* RFSW Truncated */
|
||||
} FEC_EVENT_LOG;
|
||||
|
||||
|
||||
extern int fec_mii_write(uint8_t , uint8_t , uint8_t , uint16_t );
|
||||
extern int fec_mii_read(uint8_t , uint8_t , uint8_t , uint16_t *);
|
||||
extern void fec_mii_init(uint8_t, uint32_t);
|
||||
extern void fec_mib_init(uint8_t);
|
||||
extern void fec_mib_dump(uint8_t);
|
||||
extern void fec_log_init(uint8_t);
|
||||
extern void fec_log_dump(uint8_t);
|
||||
extern void fec_debug_dump(uint8_t);
|
||||
extern void fec_duplex (uint8_t, uint8_t);
|
||||
extern uint8_t fec_hash_address(const uint8_t *);
|
||||
extern void fec_set_address (uint8_t ch, const uint8_t *);
|
||||
extern void fec_reset (uint8_t);
|
||||
extern void fec_init(uint8_t ch, uint8_t mode, const uint8_t *pa);
|
||||
extern void fec_rx_start(uint8_t, int8_t *);
|
||||
extern void fec_rx_restart(uint8_t);
|
||||
extern void fec_rx_stop (uint8_t);
|
||||
extern void fec_rx_frame(uint8_t, NIF *);
|
||||
extern void fec0_rx_frame(void);
|
||||
extern void fec1_rx_frame(void);
|
||||
extern void fec_tx_start(uint8_t, int8_t *);
|
||||
extern void fec_tx_restart(uint8_t);
|
||||
extern void fec_tx_stop (uint8_t);
|
||||
extern void fec0_tx_frame(void);
|
||||
extern void fec1_tx_frame(void);
|
||||
extern int fec_send(uint8_t, NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *);
|
||||
extern int fec0_send(NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *);
|
||||
extern int fec1_send(NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *);
|
||||
extern void fec_irq_enable(uint8_t, uint8_t, uint8_t);
|
||||
extern void fec_irq_disable(uint8_t);
|
||||
extern void fec_interrupt_handler(uint8_t);
|
||||
extern bool fec0_interrupt_handler(void *, void *);
|
||||
extern bool fec1_interrupt_handler(void *, void *);
|
||||
extern void fec_eth_setup(uint8_t, uint8_t, uint8_t, uint8_t, const uint8_t *);
|
||||
extern void fec_eth_reset(uint8_t);
|
||||
extern void fec_eth_stop(uint8_t);
|
||||
|
||||
#endif /* _FEC_H_ */
|
||||
100
include/font.h
Normal file
100
include/font.h
Normal file
@@ -0,0 +1,100 @@
|
||||
/*
|
||||
* font.h - font specific definitions
|
||||
*
|
||||
* Copyright (c) 2001 Lineo, Inc.
|
||||
* Copyright (c) 2004 by Authors:
|
||||
*
|
||||
* Authors:
|
||||
* MAD Martin Doering
|
||||
*
|
||||
* This file is distributed under the GPL, version 2 or at your
|
||||
* option any later version. See doc/license.txt for details.
|
||||
*/
|
||||
|
||||
#ifndef FONT_H
|
||||
#define FONT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* font header flags */
|
||||
|
||||
#define F_DEFAULT 1 /* this is the default font (face and size) */
|
||||
#define F_HORZ_OFF 2 /* there are left and right offset tables */
|
||||
#define F_STDFORM 4 /* is the font in standard format */
|
||||
#define F_MONOSPACE 8 /* is the font monospaced */
|
||||
|
||||
/* font style bits */
|
||||
|
||||
#define F_THICKEN 1
|
||||
#define F_LIGHT 2
|
||||
#define F_SKEW 4
|
||||
#define F_UNDER 8
|
||||
#define F_OUTLINE 16
|
||||
#define F_SHADOW 32
|
||||
|
||||
/* font specific linea variables */
|
||||
|
||||
extern const uint16_t *v_fnt_ad; /* address of current monospace font */
|
||||
extern const uint16_t *v_off_ad; /* address of font offset table */
|
||||
extern uint16_t v_fnt_nd; /* ascii code of last cell in font */
|
||||
extern uint16_t v_fnt_st; /* ascii code of first cell in font */
|
||||
extern uint16_t v_fnt_wr; /* font cell wrap */
|
||||
|
||||
/* character cell specific linea variables */
|
||||
|
||||
extern uint16_t v_cel_ht; /* cell height (width is 8) */
|
||||
extern uint16_t v_cel_mx; /* needed by MiNT: columns on the screen minus 1 */
|
||||
extern uint16_t v_cel_my; /* needed by MiNT: rows on the screen minus 1 */
|
||||
extern uint16_t v_cel_wr; /* needed by MiNT: length (in int8_ts) of a line of characters */
|
||||
|
||||
/*
|
||||
* font_ring is a struct of four pointers, each of which points to
|
||||
* a list of font headers linked together to form a string.
|
||||
*/
|
||||
|
||||
extern struct font_head *font_ring[4]; /* Ring of available fonts */
|
||||
extern int16_t font_count; /* all three fonts and NULL */
|
||||
|
||||
/* the font header descibes a font */
|
||||
|
||||
struct font_head {
|
||||
int16_t font_id;
|
||||
int16_t point;
|
||||
int8_t name[32];
|
||||
uint16_t first_ade;
|
||||
uint16_t last_ade;
|
||||
uint16_t top;
|
||||
uint16_t ascent;
|
||||
uint16_t half;
|
||||
uint16_t descent;
|
||||
uint16_t bottom;
|
||||
uint16_t max_char_width;
|
||||
uint16_t max_cell_width;
|
||||
uint16_t left_offset; /* amount character slants left when skewed */
|
||||
uint16_t right_offset; /* amount character slants right */
|
||||
uint16_t thicken; /* number of pixels to smear */
|
||||
uint16_t ul_size; /* size of the underline */
|
||||
uint16_t lighten; /* mask to and with to lighten */
|
||||
uint16_t skew; /* mask for skewing */
|
||||
uint16_t flags;
|
||||
|
||||
const uint8_t *hor_table; /* horizontal offsets */
|
||||
const uint16_t *off_table; /* character offsets */
|
||||
const uint16_t *dat_table; /* character definitions */
|
||||
uint16_t form_width;
|
||||
uint16_t form_height;
|
||||
|
||||
struct font_head *next_font;/* pointer to next font */
|
||||
uint16_t font_seg;
|
||||
};
|
||||
|
||||
|
||||
|
||||
/* prototypes */
|
||||
|
||||
void font_init(void); /* initialize BIOS font ring */
|
||||
void font_set_default(void); /* choose the default font */
|
||||
|
||||
extern struct font_head *fnt;
|
||||
|
||||
#endif /* FONT_H */
|
||||
55
include/i2c-algo-bit.h
Normal file
55
include/i2c-algo-bit.h
Normal file
@@ -0,0 +1,55 @@
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* i2c-algo-bit.h i2c driver algorithms for bit-shift adapters */
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* Copyright (C) 1995-99 Simon G. Vogl
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/* With some changes from Ky<4B>sti M<>lkki <kmalkki@cc.hut.fi> and even
|
||||
Frodo Looijaard <frodol@dds.nl> */
|
||||
|
||||
/* $Id: i2c-algo-bit.h,v 1.1.1.1 2012/08/16 18:43:05 mfro Exp $ */
|
||||
|
||||
#ifndef I2C_ALGO_BIT_H
|
||||
#define I2C_ALGO_BIT_H
|
||||
|
||||
/* --- Defines for bit-adapters --------------------------------------- */
|
||||
/*
|
||||
* This struct contains the hw-dependent functions of bit-style adapters to
|
||||
* manipulate the line states, and to init any hw-specific features. This is
|
||||
* only used if you have more than one hw-type of adapter running.
|
||||
*/
|
||||
struct i2c_algo_bit_data
|
||||
{
|
||||
void *data; /* private data for lowlevel routines */
|
||||
void (*setsda) (void *data, int state);
|
||||
void (*setscl) (void *data, int state);
|
||||
int (*getsda) (void *data);
|
||||
int (*getscl) (void *data);
|
||||
|
||||
/* local settings */
|
||||
int udelay; /* half-clock-cycle time in microsecs */
|
||||
/* i.e. clock is (500 / udelay) KHz */
|
||||
int mdelay; /* in millisecs, unused */
|
||||
int timeout; /* in jiffies */
|
||||
};
|
||||
|
||||
#define I2C_BIT_ADAP_MAX 16
|
||||
|
||||
int i2c_bit_add_bus(struct i2c_adapter *);
|
||||
int i2c_bit_del_bus(struct i2c_adapter *);
|
||||
|
||||
#endif /* I2C_ALGO_BIT_H */
|
||||
97
include/i2c.h
Normal file
97
include/i2c.h
Normal file
@@ -0,0 +1,97 @@
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* */
|
||||
/* i2c.h - definitions for the i2c-bus interface */
|
||||
/* */
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* Copyright (C) 1995-2000 Simon G. Vogl
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/* With some changes from Ky<4B>sti M<>lkki <kmalkki@cc.hut.fi> and
|
||||
Frodo Looijaard <frodol@dds.nl> */
|
||||
|
||||
/* $Id: i2c.h,v 1.1.1.1 2012/08/16 18:43:05 mfro Exp $ */
|
||||
|
||||
#ifndef _I2C_H
|
||||
#define _I2C_H
|
||||
|
||||
#include "bas_types.h"
|
||||
|
||||
/* --- General options ------------------------------------------------ */
|
||||
|
||||
struct i2c_msg;
|
||||
struct i2c_algorithm;
|
||||
struct i2c_adapter;
|
||||
|
||||
/* Transfer num messages.
|
||||
*/
|
||||
extern int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num);
|
||||
|
||||
/*
|
||||
* The following structs are for those who like to implement new bus drivers:
|
||||
* i2c_algorithm is the interface to a class of hardware solutions which can
|
||||
* be addressed using the same bus algorithms - i.e. bit-banging or the PCF8584
|
||||
* to name two of the most common.
|
||||
*/
|
||||
struct i2c_algorithm
|
||||
{
|
||||
unsigned int id;
|
||||
int (*master_xfer)(struct i2c_adapter *adap,struct i2c_msg *msgs, int num);
|
||||
/* --- ioctl like call to set div. parameters. */
|
||||
int (*algo_control)(struct i2c_adapter *, unsigned int, unsigned long);
|
||||
};
|
||||
|
||||
/*
|
||||
* i2c_adapter is the structure used to identify a physical i2c bus along
|
||||
* with the access algorithms necessary to access it.
|
||||
*/
|
||||
struct i2c_adapter
|
||||
{
|
||||
struct i2c_algorithm *algo; /* the algorithm to access the bus */
|
||||
void *algo_data;
|
||||
int timeout;
|
||||
int retries;
|
||||
int nr;
|
||||
};
|
||||
|
||||
/*
|
||||
* I2C Message - used for pure i2c transaction, also from /dev interface
|
||||
*/
|
||||
struct i2c_msg
|
||||
{
|
||||
unsigned short addr; /* slave address */
|
||||
unsigned short flags;
|
||||
#define I2C_M_TEN 0x10 /* we have a ten bit chip address */
|
||||
#define I2C_M_RD 0x01
|
||||
#define I2C_M_NOSTART 0x4000
|
||||
#define I2C_M_REV_DIR_ADDR 0x2000
|
||||
#define I2C_M_IGNORE_NAK 0x1000
|
||||
#define I2C_M_NO_RD_ACK 0x0800
|
||||
unsigned short len; /* msg length */
|
||||
unsigned char *buf; /* pointer to msg data */
|
||||
};
|
||||
|
||||
/*
|
||||
extern void i2c_init(void);
|
||||
extern void i2c_set_frequency(int hz);
|
||||
extern int i2c_read(int address, char *data, int lengt, bool repeated);
|
||||
extern int i2c_read_byte(int ack);
|
||||
extern int i2c_write(int address, const char *data, int length, bool repeated);
|
||||
extern int i2c_write_byte(int data);
|
||||
extern void i2c_start(void);
|
||||
extern void i2c_stop(void);
|
||||
*/
|
||||
#endif /* _I2C_H */
|
||||
121
include/icmp.h
Normal file
121
include/icmp.h
Normal file
@@ -0,0 +1,121 @@
|
||||
/*
|
||||
* File: icmp.h
|
||||
* Purpose: Handle Internet Control Message Protocol packets.
|
||||
*
|
||||
* Notes: See RFC 792 "Internet Control Message Protocol"
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#ifndef _ICMP_H
|
||||
#define _ICMP_H
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t unused;
|
||||
uint8_t ih_dg;
|
||||
} icmp_dest_unreachable;
|
||||
#define ICMP_DEST_UNREACHABLE (3) /* type */
|
||||
#define ICMP_NET_UNREACHABLE (0) /* code */
|
||||
#define ICMP_HOST_UNREACHABLE (1)
|
||||
#define ICMP_PROTOCOL_UNREACHABLE (2)
|
||||
#define ICMP_PORT_UNREACHABLE (3)
|
||||
#define ICMP_FRAG_NEEDED (4)
|
||||
#define ICMP_ROUTE_FAILED (5)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t unused;
|
||||
uint8_t ih_dg;
|
||||
} icmp_time_exceeded;
|
||||
#define ICMP_TIME_EXCEEDED (11) /* type */
|
||||
#define ICMP_TTL_EXCEEDED (0) /* code */
|
||||
#define ICMP_FRAG_TIME_EXCEEDED (1)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t pointer;
|
||||
uint8_t unused1;
|
||||
uint16_t unused2;
|
||||
uint8_t ih_dg;
|
||||
} icmp_parameter_problem;
|
||||
#define ICMP_PARAMETER_PROBLEM (12) /* type */
|
||||
#define ICMP_POINTER (0) /* code -- not */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t unused;
|
||||
uint8_t ih_dg;
|
||||
} icmp_source_quench;
|
||||
#define ICMP_SOURCE_QUENCH (4) /* type */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t gateway_addr;
|
||||
uint8_t ih_dg;
|
||||
} icmp_redirect;
|
||||
#define ICMP_REDIRECT (5) /* type */
|
||||
#define ICMP_REDIRECT_NET (0) /* code */
|
||||
#define ICMP_REDIRECT_HOST (1)
|
||||
#define ICMP_REDIRECT_TOS_NET (2)
|
||||
#define ICMP_REDIRECT_TOS_HOST (3)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t identifier;
|
||||
uint16_t sequence;
|
||||
uint8_t data;
|
||||
} icmp_echo;
|
||||
#define ICMP_ECHO (8) /* type */
|
||||
#define ICMP_ECHO_REPLY (0) /* type */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t identifier;
|
||||
uint16_t sequence;
|
||||
} icmp_information;
|
||||
#define ICMP_INFORMATION_REQUEST (15) /* type */
|
||||
#define ICMP_INFORMATION_REPLY (16) /* type */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t identifier;
|
||||
uint16_t sequence;
|
||||
uint32_t originate_ts;
|
||||
uint32_t receive_ts;
|
||||
uint32_t transmit_ts;
|
||||
} icmp_timestamp;
|
||||
#define ICMP_TIMESTAMP (13) /* type */
|
||||
#define ICMP_TIMESTAMP_REPLY (14) /* type */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t type;
|
||||
uint8_t code;
|
||||
uint16_t chksum;
|
||||
union
|
||||
{
|
||||
icmp_dest_unreachable dest_unreachable;
|
||||
icmp_source_quench source_quench;
|
||||
icmp_redirect redirect;
|
||||
icmp_time_exceeded time_exceeded;
|
||||
icmp_parameter_problem parameter_problem;
|
||||
icmp_timestamp timestamp;
|
||||
icmp_information information;
|
||||
icmp_echo echo;
|
||||
} msg;
|
||||
} icmp_message;
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
/* Protocol Header information */
|
||||
#define ICMP_HDR_OFFSET (ETH_HDR_LEN + IP_HDR_SIZE)
|
||||
#define ICMP_HDR_SIZE 8
|
||||
|
||||
void
|
||||
icmp_handler(NIF *, NBUF *);
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* _ICMP_H */
|
||||
50
include/m54455.h
Normal file
50
include/m54455.h
Normal file
@@ -0,0 +1,50 @@
|
||||
#ifndef _M54455_H_
|
||||
#define _M54455_H_
|
||||
|
||||
/*
|
||||
* m54455.h
|
||||
*
|
||||
* preprocessor definitions for the M54455 Freescale machine. This file should contain nothing but preprocessor
|
||||
* definition that evaluate to numbers. It is intended for use in C sources as well as in linker control
|
||||
* files, so care must be taken to not break the syntax of either one.
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 26.02.2013
|
||||
* Author: Markus Fröschle
|
||||
*/
|
||||
|
||||
#define SYSCLK 133000
|
||||
|
||||
#define BOOTFLASH_BASE_ADDRESS 0xe0000000
|
||||
#define BOOTFLASH_SIZE 0x800000
|
||||
#define BOOTFLASH_BAM (BOOTFLASH_SIZE - 1)
|
||||
|
||||
#define SDRAM_START 0x40000000 /* start at address 40000000 */
|
||||
#define SDRAM_SIZE 0x10000000 /* 256 MB */
|
||||
|
||||
#ifdef COMPILE_RAM
|
||||
#define TARGET_ADDRESS (SDRAM_START + SDRAM_SIZE - 0x200000)
|
||||
#else
|
||||
#define TARGET_ADDRESS BOOTFLASH_BASE_ADDRESS
|
||||
#endif /* COMPILE_RAM */
|
||||
#define BFL_TARGET_ADDRESS 0x0100000 /* load address for basflash */
|
||||
|
||||
#define DRIVER_MEM_BUFFER_SIZE 0x100000
|
||||
|
||||
#define EMUTOS_BASE_ADDRESS 0xe0100000
|
||||
|
||||
#endif /* _M54455_H_ */
|
||||
49
include/nif.h
Normal file
49
include/nif.h
Normal file
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* File: nif.h
|
||||
* Purpose: Definition of a Network InterFace.
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#ifndef _NIF_H
|
||||
#define _NIF_H
|
||||
|
||||
/*
|
||||
* Maximum number of supported protoocls: IP, ARP, RARP
|
||||
*/
|
||||
#define MAX_SUP_PROTO (3)
|
||||
|
||||
typedef struct NIF_t
|
||||
{
|
||||
ETH_ADDR hwa; /* ethernet card hardware address */
|
||||
ETH_ADDR broadcast; /* broadcast address */
|
||||
int mtu; /* hardware maximum transmission unit */
|
||||
int ch; /* ethernet channel associated with this NIF */
|
||||
|
||||
struct SUP_PROTO_t
|
||||
{
|
||||
uint16_t protocol;
|
||||
void (*handler)(struct NIF_t *, NBUF *);
|
||||
void *info;
|
||||
} protocol[MAX_SUP_PROTO];
|
||||
|
||||
unsigned short num_protocol;
|
||||
|
||||
int (*send)(struct NIF_t *, uint8_t *, uint8_t *, uint16_t, NBUF *);
|
||||
|
||||
unsigned int f_rx;
|
||||
unsigned int f_tx;
|
||||
unsigned int f_rx_err;
|
||||
unsigned int f_tx_err;
|
||||
unsigned int f_err;
|
||||
} NIF;
|
||||
|
||||
|
||||
extern NIF *nif_init (NIF *);
|
||||
extern int nif_protocol_exist (NIF *, uint16_t);
|
||||
extern void nif_protocol_handler (NIF *, uint16_t, NBUF *);
|
||||
extern void *nif_get_protocol_info (NIF *, uint16_t);
|
||||
extern int nif_bind_protocol (NIF *, uint16_t, void (*)(NIF *, NBUF *), void *);
|
||||
|
||||
|
||||
#endif /* _NIF_H */
|
||||
464
include/ohci.h
Normal file
464
include/ohci.h
Normal file
@@ -0,0 +1,464 @@
|
||||
/*
|
||||
* URB OHCI HCD (Host Controller Driver) for USB.
|
||||
*
|
||||
* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
|
||||
* (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
|
||||
*
|
||||
* usb-ohci.h
|
||||
*/
|
||||
|
||||
#define USB_OHCI_MAX_ROOT_PORTS 4
|
||||
|
||||
static int cc_to_error[16] =
|
||||
{
|
||||
|
||||
/* mapping of the OHCI CC status to error codes */
|
||||
/* No Error */ 0,
|
||||
/* CRC Error */ USB_ST_CRC_ERR,
|
||||
/* Bit Stuff */ USB_ST_BIT_ERR,
|
||||
/* Data Togg */ USB_ST_CRC_ERR,
|
||||
/* Stall */ USB_ST_STALLED,
|
||||
/* DevNotResp */ -1,
|
||||
/* PIDCheck */ USB_ST_BIT_ERR,
|
||||
/* UnExpPID */ USB_ST_BIT_ERR,
|
||||
/* DataOver */ USB_ST_BUF_ERR,
|
||||
/* DataUnder */ USB_ST_BUF_ERR,
|
||||
/* reservd */ -1,
|
||||
/* reservd */ -1,
|
||||
/* BufferOver */ USB_ST_BUF_ERR,
|
||||
/* BuffUnder */ USB_ST_BUF_ERR,
|
||||
/* Not Access */ -1,
|
||||
/* Not Access */ -1
|
||||
};
|
||||
|
||||
static const char *cc_to_string[16] =
|
||||
{
|
||||
"No Error",
|
||||
"CRC: Last data packet from endpoint contained a CRC error.",
|
||||
"BITSTUFFING:\r\nLast data packet from endpoint contained a bit stuffing violation",
|
||||
"DATATOGGLEMISMATCH:\r\n Last packet from endpoint had data toggle PID\r\n" \
|
||||
"that did not match the expected value.",
|
||||
"STALL: TD was moved to the Done Queue because the endpoint returned a STALL PID",
|
||||
"DEVICENOTRESPONDING:\r\nDevice did not respond to token (IN) or did\r\n" \
|
||||
"not provide a handshake (OUT)",
|
||||
"PIDCHECKFAILURE:\r\nCheck bits on PID from endpoint failed on data PID\r\n"\
|
||||
"(IN) or handshake (OUT)",
|
||||
"UNEXPECTEDPID:\r\nReceive PID was not valid when encountered or PID\r\n" \
|
||||
"value is not defined.",
|
||||
"DATAOVERRUN:\r\nThe amount of data returned by the endpoint exceeded\r\n" \
|
||||
"either the size of the maximum data packet allowed\r\n" \
|
||||
"from the endpoint (found in MaximumPacketSize field\r\n" \
|
||||
"of ED) or the remaining buffer size.",
|
||||
"DATAUNDERRUN:\r\nThe endpoint returned less than MaximumPacketSize\r\n" \
|
||||
"and that amount was not sufficient to fill the\r\n" \
|
||||
"specified buffer",
|
||||
"reserved1",
|
||||
"reserved2",
|
||||
"BUFFEROVERRUN:\r\nDuring an IN, HC received data from endpoint faster\r\n" \
|
||||
"than it could be written to system memory",
|
||||
"BUFFERUNDERRUN:\r\nDuring an OUT, HC could not retrieve data from\r\n" \
|
||||
"system memory fast enough to keep up with data USB data rate.",
|
||||
"NOT ACCESSED:\r\nThis code is set by software before the TD is placed\r\n" \
|
||||
"on a list to be processed by the HC.(1)",
|
||||
"NOT ACCESSED:\r\nThis code is set by software before the TD is placed\r\n" \
|
||||
"on a list to be processed by the HC.(2)",
|
||||
};
|
||||
|
||||
/* ED States */
|
||||
|
||||
#define ED_NEW 0x00
|
||||
#define ED_UNLINK 0x01
|
||||
#define ED_OPER 0x02
|
||||
#define ED_DEL 0x04
|
||||
#define ED_URB_DEL 0x08
|
||||
|
||||
/* usb_ohci_ed */
|
||||
struct ed
|
||||
{
|
||||
uint32_t hwINFO;
|
||||
uint32_t hwTailP;
|
||||
uint32_t hwHeadP;
|
||||
uint32_t hwNextED;
|
||||
|
||||
volatile struct ed *ed_prev;
|
||||
uint8_t int_period;
|
||||
uint8_t int_branch;
|
||||
uint8_t int_load;
|
||||
uint8_t int_interval;
|
||||
uint8_t state;
|
||||
uint8_t type;
|
||||
uint16_t last_iso;
|
||||
struct ed *ed_rm_list;
|
||||
|
||||
struct usb_device *usb_dev;
|
||||
volatile void *purb;
|
||||
uint32_t unused[2];
|
||||
} __attribute__((aligned(16)));
|
||||
typedef struct ed ed_t;
|
||||
|
||||
|
||||
/* TD info field */
|
||||
#define TD_CC 0xf0000000
|
||||
#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
|
||||
#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
|
||||
#define TD_EC 0x0C000000
|
||||
#define TD_T 0x03000000
|
||||
#define TD_T_DATA0 0x02000000
|
||||
#define TD_T_DATA1 0x03000000
|
||||
#define TD_T_TOGGLE 0x00000000
|
||||
#define TD_R 0x00040000
|
||||
#define TD_DI 0x00E00000
|
||||
#define TD_DI_SET(X) (((X) & 0x07)<< 21)
|
||||
#define TD_DP 0x00180000
|
||||
#define TD_DP_SETUP 0x00000000
|
||||
#define TD_DP_IN 0x00100000
|
||||
#define TD_DP_OUT 0x00080000
|
||||
|
||||
#define TD_ISO 0x00010000
|
||||
#define TD_DEL 0x00020000
|
||||
|
||||
/* CC Codes */
|
||||
#define TD_CC_NOERROR 0x00
|
||||
#define TD_CC_CRC 0x01
|
||||
#define TD_CC_BITSTUFFING 0x02
|
||||
#define TD_CC_DATATOGGLEM 0x03
|
||||
#define TD_CC_STALL 0x04
|
||||
#define TD_DEVNOTRESP 0x05
|
||||
#define TD_PIDCHECKFAIL 0x06
|
||||
#define TD_UNEXPECTEDPID 0x07
|
||||
#define TD_DATAOVERRUN 0x08
|
||||
#define TD_DATAUNDERRUN 0x09
|
||||
#define TD_BUFFEROVERRUN 0x0C
|
||||
#define TD_BUFFERUNDERRUN 0x0D
|
||||
#define TD_NOTACCESSED 0x0F
|
||||
|
||||
|
||||
#define MAXPSW 1
|
||||
|
||||
struct td
|
||||
{
|
||||
uint32_t hwINFO;
|
||||
uint32_t hwCBP; /* Current Buffer Pointer */
|
||||
uint32_t hwNextTD; /* Next TD Pointer */
|
||||
uint32_t hwBE; /* Memory Buffer End Pointer */
|
||||
|
||||
uint16_t hwPSW[MAXPSW];
|
||||
uint8_t unused;
|
||||
uint8_t index;
|
||||
volatile struct ed *ed;
|
||||
volatile struct td *next_dl_td;
|
||||
struct usb_device *usb_dev;
|
||||
int transfer_len;
|
||||
uint32_t data;
|
||||
|
||||
uint32_t unused2[2];
|
||||
} __attribute__((aligned(32)));
|
||||
typedef struct td td_t;
|
||||
|
||||
#define OHCI_ED_SKIP (1 << 14)
|
||||
|
||||
/*
|
||||
* The HCCA (Host Controller Communications Area) is a 256 byte
|
||||
* structure defined in the OHCI spec. that the host controller is
|
||||
* told the base address of. It must be 256-byte aligned.
|
||||
*/
|
||||
|
||||
#define NUM_INTS 32 /* part of the OHCI standard */
|
||||
struct ohci_hcca
|
||||
{
|
||||
volatile uint32_t int_table[NUM_INTS]; /* Interrupt ED table */
|
||||
#if defined(CONFIG_MPC5200)
|
||||
uint16_t pad1; /* set to 0 on each frame_no change */
|
||||
uint16_t frame_no; /* current frame number */
|
||||
#else
|
||||
uint16_t frame_no; /* current frame number */
|
||||
uint16_t pad1; /* set to 0 on each frame_no change */
|
||||
#endif
|
||||
uint32_t done_head; /* info returned for an interrupt */
|
||||
uint8_t reserved_for_hc[116];
|
||||
} __attribute__((aligned(256)));
|
||||
|
||||
/*
|
||||
* This is the structure of the OHCI controller's memory mapped I/O
|
||||
* region. This is Memory Mapped I/O. You must use the readl() and
|
||||
* writel() macros defined in asm/io.h to access these!!
|
||||
*/
|
||||
struct ohci_regs
|
||||
{
|
||||
/* control and status registers */
|
||||
uint32_t revision;
|
||||
uint32_t control;
|
||||
uint32_t cmdstatus;
|
||||
uint32_t intrstatus;
|
||||
uint32_t intrenable;
|
||||
uint32_t intrdisable;
|
||||
/* memory pointers */
|
||||
uint32_t hcca;
|
||||
uint32_t ed_periodcurrent;
|
||||
uint32_t ed_controlhead;
|
||||
uint32_t ed_controlcurrent;
|
||||
uint32_t ed_bulkhead;
|
||||
uint32_t ed_bulkcurrent;
|
||||
uint32_t donehead;
|
||||
/* frame counters */
|
||||
uint32_t fminterval;
|
||||
uint32_t fmremaining;
|
||||
uint32_t fmnumber;
|
||||
uint32_t periodicstart;
|
||||
uint32_t lsthresh;
|
||||
/* Root hub ports */
|
||||
struct ohci_roothub_regs
|
||||
{
|
||||
uint32_t a;
|
||||
uint32_t b;
|
||||
uint32_t status;
|
||||
uint32_t portstatus[USB_OHCI_MAX_ROOT_PORTS];
|
||||
} roothub;
|
||||
} __attribute__((aligned(32)));
|
||||
|
||||
/* Some EHCI controls */
|
||||
#define EHCI_USBCMD_OFF 0x20
|
||||
#define EHCI_USBCMD_HCRESET (1 << 1)
|
||||
|
||||
/* OHCI CONTROL AND STATUS REGISTER MASKS */
|
||||
|
||||
/*
|
||||
* HcControl (control) register masks
|
||||
*/
|
||||
#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
|
||||
#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
|
||||
#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
|
||||
#define OHCI_CTRL_CLE (1 << 4) /* control list enable */
|
||||
#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
|
||||
#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
|
||||
#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
|
||||
#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
|
||||
#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
|
||||
|
||||
/* pre-shifted values for HCFS */
|
||||
# define OHCI_USB_RESET (0 << 6)
|
||||
# define OHCI_USB_RESUME (1 << 6)
|
||||
# define OHCI_USB_OPER (2 << 6)
|
||||
# define OHCI_USB_SUSPEND (3 << 6)
|
||||
|
||||
/*
|
||||
* HcCommandStatus (cmdstatus) register masks
|
||||
*/
|
||||
#define OHCI_HCR (1 << 0) /* host controller reset */
|
||||
#define OHCI_CLF (1 << 1) /* control list filled */
|
||||
#define OHCI_BLF (1 << 2) /* bulk list filled */
|
||||
#define OHCI_OCR (1 << 3) /* ownership change request */
|
||||
#define OHCI_SOC (3 << 16) /* scheduling overrun count */
|
||||
|
||||
/*
|
||||
* masks used with interrupt registers:
|
||||
* HcInterruptStatus (intrstatus)
|
||||
* HcInterruptEnable (intrenable)
|
||||
* HcInterruptDisable (intrdisable)
|
||||
*/
|
||||
#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
|
||||
#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
|
||||
#define OHCI_INTR_SF (1 << 2) /* start frame */
|
||||
#define OHCI_INTR_RD (1 << 3) /* resume detect */
|
||||
#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
|
||||
#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
|
||||
#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
|
||||
#define OHCI_INTR_OC (1 << 30) /* ownership change */
|
||||
#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
|
||||
|
||||
|
||||
/* Virtual Root HUB */
|
||||
struct virt_root_hub
|
||||
{
|
||||
int devnum; /* Address of Root Hub endpoint */
|
||||
void *dev; /* was urb */
|
||||
void *int_addr;
|
||||
int send;
|
||||
int interval;
|
||||
};
|
||||
|
||||
/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
|
||||
|
||||
/* destination of request */
|
||||
#define RH_INTERFACE 0x01
|
||||
#define RH_ENDPOINT 0x02
|
||||
#define RH_OTHER 0x03
|
||||
|
||||
#define RH_CLASS 0x20
|
||||
#define RH_VENDOR 0x40
|
||||
|
||||
/* Requests: bRequest << 8 | bmRequestType */
|
||||
#define RH_GET_STATUS 0x0080
|
||||
#define RH_CLEAR_FEATURE 0x0100
|
||||
#define RH_SET_FEATURE 0x0300
|
||||
#define RH_SET_ADDRESS 0x0500
|
||||
#define RH_GET_DESCRIPTOR 0x0680
|
||||
#define RH_SET_DESCRIPTOR 0x0700
|
||||
#define RH_GET_CONFIGURATION 0x0880
|
||||
#define RH_SET_CONFIGURATION 0x0900
|
||||
#define RH_GET_STATE 0x0280
|
||||
#define RH_GET_INTERFACE 0x0A80
|
||||
#define RH_SET_INTERFACE 0x0B00
|
||||
#define RH_SYNC_FRAME 0x0C80
|
||||
/* Our Vendor Specific Request */
|
||||
#define RH_SET_EP 0x2000
|
||||
|
||||
|
||||
/* Hub port features */
|
||||
#define RH_PORT_CONNECTION 0x00
|
||||
#define RH_PORT_ENABLE 0x01
|
||||
#define RH_PORT_SUSPEND 0x02
|
||||
#define RH_PORT_OVER_CURRENT 0x03
|
||||
#define RH_PORT_RESET 0x04
|
||||
#define RH_PORT_POWER 0x08
|
||||
#define RH_PORT_LOW_SPEED 0x09
|
||||
|
||||
#define RH_C_PORT_CONNECTION 0x10
|
||||
#define RH_C_PORT_ENABLE 0x11
|
||||
#define RH_C_PORT_SUSPEND 0x12
|
||||
#define RH_C_PORT_OVER_CURRENT 0x13
|
||||
#define RH_C_PORT_RESET 0x14
|
||||
|
||||
/* Hub features */
|
||||
#define RH_C_HUB_LOCAL_POWER 0x00
|
||||
#define RH_C_HUB_OVER_CURRENT 0x01
|
||||
|
||||
#define RH_DEVICE_REMOTE_WAKEUP 0x00
|
||||
#define RH_ENDPOINT_STALL 0x01
|
||||
|
||||
#define RH_ACK 0x01
|
||||
#define RH_REQ_ERR -1
|
||||
#define RH_NACK 0x00
|
||||
|
||||
|
||||
/* OHCI ROOT HUB REGISTER MASKS */
|
||||
|
||||
/* roothub.portstatus [i] bits */
|
||||
#define RH_PS_CCS 0x00000001 /* current connect status */
|
||||
#define RH_PS_PES 0x00000002 /* port enable status*/
|
||||
#define RH_PS_PSS 0x00000004 /* port suspend status */
|
||||
#define RH_PS_POCI 0x00000008 /* port over current indicator */
|
||||
#define RH_PS_PRS 0x00000010 /* port reset status */
|
||||
#define RH_PS_PPS 0x00000100 /* port power status */
|
||||
#define RH_PS_LSDA 0x00000200 /* low speed device attached */
|
||||
#define RH_PS_CSC 0x00010000 /* connect status change */
|
||||
#define RH_PS_PESC 0x00020000 /* port enable status change */
|
||||
#define RH_PS_PSSC 0x00040000 /* port suspend status change */
|
||||
#define RH_PS_OCIC 0x00080000 /* over current indicator change */
|
||||
#define RH_PS_PRSC 0x00100000 /* port reset status change */
|
||||
|
||||
/* roothub.status bits */
|
||||
#define RH_HS_LPS 0x00000001 /* local power status */
|
||||
#define RH_HS_OCI 0x00000002 /* over current indicator */
|
||||
#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
|
||||
#define RH_HS_LPSC 0x00010000 /* local power status change */
|
||||
#define RH_HS_OCIC 0x00020000 /* over current indicator change */
|
||||
#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
|
||||
|
||||
/* roothub.b masks */
|
||||
#define RH_B_DR 0x0000ffff /* device removable flags */
|
||||
#define RH_B_PPCM 0xffff0000 /* port power control mask */
|
||||
|
||||
/* roothub.a masks */
|
||||
#define RH_A_NDP (0xff << 0) /* number of downstream ports */
|
||||
#define RH_A_PSM (1 << 8) /* power switching mode */
|
||||
#define RH_A_NPS (1 << 9) /* no power switching */
|
||||
#define RH_A_DT (1 << 10) /* device type (mbz) */
|
||||
#define RH_A_OCPM (1 << 11) /* over current protection mode */
|
||||
#define RH_A_NOCP (1 << 12) /* no over current protection */
|
||||
#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
|
||||
|
||||
/* urb */
|
||||
#define N_URB_TD 48
|
||||
typedef struct
|
||||
{
|
||||
volatile ed_t *ed;
|
||||
uint16_t length; /* number of tds associated with this request */
|
||||
uint16_t td_cnt; /* number of tds already serviced */
|
||||
struct usb_device *dev;
|
||||
int state;
|
||||
uint32_t pipe;
|
||||
void *transfer_buffer;
|
||||
int transfer_buffer_length;
|
||||
int interval;
|
||||
int actual_length;
|
||||
int finished;
|
||||
td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
|
||||
} urb_priv_t;
|
||||
#define URB_DEL 1
|
||||
|
||||
#define NUM_EDS 8 /* num of preallocated endpoint descriptors */
|
||||
|
||||
struct ohci_device
|
||||
{
|
||||
ed_t ed[NUM_EDS];
|
||||
int ed_cnt;
|
||||
};
|
||||
|
||||
/*
|
||||
* This is the full ohci controller description
|
||||
*
|
||||
* Note how the "proper" USB information is just
|
||||
* a subset of what the full implementation needs. (Linus)
|
||||
*/
|
||||
|
||||
typedef struct ohci
|
||||
{
|
||||
/* ------- common part -------- */
|
||||
long handle; /* PCI BIOS */
|
||||
const struct pci_device_id *ent;
|
||||
int usbnum;
|
||||
/* ---- end of common part ---- */
|
||||
int big_endian; /* PCI BIOS */
|
||||
int controller;
|
||||
volatile struct ohci_hcca *hcca_unaligned;
|
||||
volatile struct ohci_hcca *hcca; /* hcca */
|
||||
td_t *td_unaligned;
|
||||
struct ohci_device *ohci_dev_unaligned;
|
||||
/* this allocates EDs for all possible endpoints */
|
||||
struct ohci_device *ohci_dev;
|
||||
|
||||
int irq_enabled;
|
||||
int stat_irq;
|
||||
volatile int irq;
|
||||
int disabled; /* e.g. got a UE, we're hung */
|
||||
int sleeping;
|
||||
#define OHCI_FLAGS_NEC 0x80000000
|
||||
uint32_t flags; /* for HC bugs */
|
||||
|
||||
uint32_t offset;
|
||||
uint32_t dma_offset;
|
||||
volatile struct ohci_regs *regs; /* OHCI controller's memory */
|
||||
|
||||
int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/
|
||||
volatile ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
|
||||
volatile ed_t *ed_bulktail; /* last endpoint of bulk list */
|
||||
volatile ed_t *ed_controltail; /* last endpoint of control list */
|
||||
int intrstatus;
|
||||
uint32_t hc_control; /* copy of the hc control reg */
|
||||
uint32_t ndp; /* copy NDP from roothub_a */
|
||||
struct virt_root_hub rh;
|
||||
|
||||
const char *slot_name;
|
||||
|
||||
/* device which was disconnected */
|
||||
struct usb_device *devgone;
|
||||
} ohci_t;
|
||||
|
||||
/* hcd */
|
||||
/* endpoint */
|
||||
static int ep_link(volatile ohci_t * ohci, volatile ed_t *ed);
|
||||
static int ep_unlink(volatile ohci_t * ohci, volatile ed_t *ed);
|
||||
static ed_t * ep_add_ed(volatile ohci_t * ohci, struct usb_device * usb_dev, uint32_t pipe, int interval, int load);
|
||||
|
||||
|
||||
/* we need more TDs than EDs */
|
||||
#define NUM_TD 64
|
||||
|
||||
|
||||
static inline void ed_free(struct ed *ed)
|
||||
{
|
||||
ed->usb_dev = NULL;
|
||||
}
|
||||
|
||||
|
||||
11
include/pci_errata.h
Executable file
11
include/pci_errata.h
Executable file
@@ -0,0 +1,11 @@
|
||||
#ifndef PCI_ERRATA_H
|
||||
#define PCI_ERRATA_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
extern void chip_errata_135(void);
|
||||
extern void chip_errata_055(int32_t handle);
|
||||
|
||||
#endif // PCI_ERRATA_H
|
||||
|
||||
51
include/queue.h
Normal file
51
include/queue.h
Normal file
@@ -0,0 +1,51 @@
|
||||
/*
|
||||
* File: queue.h
|
||||
* Purpose: Implement a first in, first out linked list
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#ifndef _QUEUE_H_
|
||||
#define _QUEUE_H_
|
||||
|
||||
/*
|
||||
* Individual queue node
|
||||
*/
|
||||
typedef struct NODE
|
||||
{
|
||||
struct NODE *next;
|
||||
} QNODE;
|
||||
|
||||
/*
|
||||
* Queue Struture - linked list of qentry items
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
QNODE *head;
|
||||
QNODE *tail;
|
||||
} QUEUE;
|
||||
|
||||
/*
|
||||
* Functions provided by queue.c
|
||||
*/
|
||||
void
|
||||
queue_init(QUEUE *);
|
||||
|
||||
int
|
||||
queue_isempty(QUEUE *);
|
||||
|
||||
void
|
||||
queue_add(QUEUE *, QNODE *);
|
||||
|
||||
QNODE*
|
||||
queue_remove(QUEUE *);
|
||||
|
||||
QNODE*
|
||||
queue_peek(QUEUE *);
|
||||
|
||||
void
|
||||
queue_move(QUEUE *, QUEUE *);
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* _QUEUE_H_ */
|
||||
45
include/sd_card.h
Normal file
45
include/sd_card.h
Normal file
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
* sd_card.h
|
||||
*
|
||||
* Exported sd-card access routines for the FireBee BaS
|
||||
*
|
||||
* Created on: 19.11.2012
|
||||
* Author: mfro
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Copyright 2010 - 2012 F. Aschwanden
|
||||
* Copyright 2011 - 2012 V. Riviere
|
||||
* Copyright 2012 M. Froeschle
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SD_CARD_H_
|
||||
#define _SD_CARD_H_
|
||||
|
||||
#include <MCF5475.h>
|
||||
#include <bas_types.h>
|
||||
|
||||
extern void sd_card_init(void);
|
||||
|
||||
/* MMC card type flags (MMC_GET_TYPE) */
|
||||
#define CT_MMC 0x01 /* MMC ver 3 */
|
||||
#define CT_SD1 0x02 /* SD ver 1 */
|
||||
#define CT_SD2 0x04 /* SD ver 2 */
|
||||
//#define CT_SDC (CT_SD1|CT_SD2) /* SD */
|
||||
#define CT_BLOCK 0x08 /* Block addressing */
|
||||
|
||||
#endif /* _SD_CARD_H_ */
|
||||
152
include/tftp.h
Normal file
152
include/tftp.h
Normal file
@@ -0,0 +1,152 @@
|
||||
/*
|
||||
* File: tftp.h
|
||||
* Purpose: Data definitions for TFTP
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#ifndef _TFTP_H_
|
||||
#define _TFTP_H_
|
||||
|
||||
#define TFTP_RRQ (1)
|
||||
#define TFTP_WRQ (2)
|
||||
#define TFTP_DATA (3)
|
||||
#define TFTP_ACK (4)
|
||||
#define TFTP_ERROR (5)
|
||||
|
||||
#define TFTP_ERR_FNF 1
|
||||
#define TFTP_ERR_AV 2
|
||||
#define TFTP_ERR_DF 3
|
||||
#define TFTP_ERR_ILL 4
|
||||
#define TFTP_ERR_TID 5
|
||||
#define TFTP_FE 6
|
||||
#define TFTP_NSU 7
|
||||
#define TFTP_ERR_UD 0
|
||||
|
||||
#define OCTET "octet"
|
||||
#define NETASCII "netascii"
|
||||
|
||||
/* Protocol Header information */
|
||||
#define TFTP_HDR_OFFSET (ETH_HDR_LEN + IP_HDR_SIZE + UDP_HDR_SIZE)
|
||||
|
||||
/* Timeout in seconds */
|
||||
#define TFTP_TIMEOUT 2
|
||||
|
||||
/* Maximum TFTP Packet Size (payload only - no header) */
|
||||
#define TFTP_PKTSIZE 512
|
||||
|
||||
/* Number of TFTP Data Buffers */
|
||||
#define NUM_TFTPBD 6
|
||||
|
||||
|
||||
/* Data Buffer Pointer Structure */
|
||||
typedef struct
|
||||
{
|
||||
uint8_t data[TFTP_PKTSIZE];
|
||||
uint16_t bytes;
|
||||
} DATA_BUF;
|
||||
|
||||
/* TFTP RRQ/WRQ Packet */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t opcode;
|
||||
char filename_mode[TFTP_PKTSIZE - 2];
|
||||
} RWRQ;
|
||||
|
||||
/* TFTP DATA Packet */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t opcode;
|
||||
uint16_t blocknum;
|
||||
uint8_t data[TFTP_PKTSIZE - 4];
|
||||
} DATA;
|
||||
|
||||
/* TFTP Acknowledge Packet */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t opcode;
|
||||
uint16_t blocknum;
|
||||
} ACK;
|
||||
|
||||
/* TFTP Error Packet */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t opcode;
|
||||
uint16_t code;
|
||||
char msg[TFTP_PKTSIZE - 4];
|
||||
} ERROR;
|
||||
|
||||
/* TFTP Generic Packet */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t opcode;
|
||||
} GEN;
|
||||
|
||||
union TFTPpacket
|
||||
{
|
||||
RWRQ rwrq;
|
||||
DATA data;
|
||||
ACK ack;
|
||||
ERROR error;
|
||||
GEN generic;
|
||||
};
|
||||
|
||||
/* TFTP Connection Status */
|
||||
typedef struct
|
||||
{
|
||||
/* Pointer to next character in buffer ring */
|
||||
uint8_t *next_char;
|
||||
|
||||
/* Direction of current connection, read or write */
|
||||
uint8_t dir;
|
||||
|
||||
/* Connection established flag */
|
||||
uint8_t open;
|
||||
|
||||
/* Pointer to our Network InterFace */
|
||||
NIF *nif;
|
||||
|
||||
/* File being transferred */
|
||||
char *file;
|
||||
|
||||
/* Server IP address */
|
||||
IP_ADDR server_ip;
|
||||
|
||||
/* Queue to hold the TFTP packets */
|
||||
QUEUE queue;
|
||||
|
||||
/* Bytes received counter */
|
||||
uint32_t bytes_recv;
|
||||
|
||||
/* Bytes sent counter */
|
||||
uint32_t bytes_sent;
|
||||
|
||||
/* Bytes remaining in current Rx buffer */
|
||||
uint32_t rem_bytes;
|
||||
|
||||
/* Server UDP port */
|
||||
uint16_t server_port;
|
||||
|
||||
/* My UDP port */
|
||||
uint16_t my_port;
|
||||
|
||||
/* Expected TFTP block number */
|
||||
uint16_t exp_blocknum;
|
||||
|
||||
/* Keep track of the last packet acknowledged */
|
||||
uint16_t last_ack;
|
||||
|
||||
/* Error Flag */
|
||||
uint8_t error;
|
||||
|
||||
} TFTP_Connection;
|
||||
|
||||
|
||||
extern void tftp_handler(NIF *, NBUF *) ;
|
||||
extern int tftp_write (NIF *, char *, IP_ADDR_P, uint32_t, uint32_t);
|
||||
extern int tftp_read(NIF *, char *, IP_ADDR_P);
|
||||
extern void tftp_end(int);
|
||||
extern int tftp_in_char(void);
|
||||
|
||||
|
||||
#endif /* _TFTP_H_ */
|
||||
57
include/user_io.h
Normal file
57
include/user_io.h
Normal file
@@ -0,0 +1,57 @@
|
||||
/*
|
||||
* user_io.h
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _USER_IO_H_
|
||||
#define _USER_IO_H_
|
||||
|
||||
#define UIO_STATUS 0x00
|
||||
#define UIO_BUT_SW 0x01
|
||||
|
||||
// codes as used by minimig (amiga)
|
||||
#define UIO_JOYSTICK0 0x02
|
||||
#define UIO_JOYSTICK1 0x03
|
||||
#define UIO_MOUSE 0x04
|
||||
#define UIO_KEYBOARD 0x05
|
||||
#define UIO_KBD_OSD 0x06 // keycodes used by OSD only
|
||||
|
||||
// codes as used by MiST (atari)
|
||||
#define UIO_IKBD_OUT 0x02
|
||||
#define UIO_IKBD_IN 0x03
|
||||
#define UIO_SERIAL_OUT 0x04
|
||||
#define UIO_SERIAL_IN 0x05
|
||||
|
||||
#define JOY_RIGHT 0x01
|
||||
#define JOY_LEFT 0x02
|
||||
#define JOY_DOWN 0x04
|
||||
#define JOY_UP 0x08
|
||||
#define JOY_BTN1 0x10
|
||||
#define JOY_BTN2 0x20
|
||||
#define JOY_MOVE (JOY_RIGHT|JOY_LEFT|JOY_UP|JOY_DOWN)
|
||||
|
||||
#define BUTTON1 0x01
|
||||
#define BUTTON2 0x02
|
||||
#define SWITCH1 0x04
|
||||
#define SWITCH2 0x08
|
||||
|
||||
// core type value should be unlikely to be returned by broken cores
|
||||
#define CORE_TYPE_UNKNOWN 0x55
|
||||
#define CORE_TYPE_DUMB 0xa0
|
||||
#define CORE_TYPE_MINIMIG 0xa1
|
||||
#define CORE_TYPE_PACE 0xa2
|
||||
#define CORE_TYPE_MIST 0xa3
|
||||
|
||||
void user_io_init();
|
||||
void user_io_detect_core_type();
|
||||
unsigned char user_io_core_type();
|
||||
void user_io_poll();
|
||||
int user_io_button_pressed();
|
||||
void user_io_osd_key_enable(char);
|
||||
|
||||
// hooks from the usb layer
|
||||
void user_io_mouse(unsigned char b, char x, char y);
|
||||
void user_io_kbd(unsigned char m, unsigned char *k);
|
||||
|
||||
#endif /* _USER_IO_H_ */
|
||||
|
||||
10
include/video.h
Normal file
10
include/video.h
Normal file
@@ -0,0 +1,10 @@
|
||||
#ifndef _VIDEO_H_
|
||||
#define _VIDEO_H_
|
||||
|
||||
#include <bas_types.h>
|
||||
#include "bas_printf.h"
|
||||
#define CONFIG_FB_RADEON_I2C
|
||||
|
||||
extern void video_init(void);
|
||||
|
||||
#endif /* _VIDEO_H_ */
|
||||
61
include/wait.h
Normal file
61
include/wait.h
Normal file
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* wait.h
|
||||
*
|
||||
* Author: mfro
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Copyright 2010 - 2012 F. Aschwanden
|
||||
* Copyright 2011 - 2012 V. Riviere
|
||||
* Copyright 2012 M. Froeschle
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _WAIT_H_
|
||||
#define _WAIT_H_
|
||||
|
||||
#include <bas_types.h>
|
||||
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
#include "firebee.h"
|
||||
#elif defined(MACHINE_M5484LITE)
|
||||
#include "m5484l.h"
|
||||
#elif defined(MACHINE_M54455)
|
||||
#include "m54455.h"
|
||||
#else
|
||||
#error "unknown machine"
|
||||
#endif /* MACHINE_FIREBEE */
|
||||
|
||||
#include "MCF5475.h"
|
||||
|
||||
typedef bool (*checker_func)(void);
|
||||
|
||||
extern void wait(uint32_t);
|
||||
extern void wait_us(uint32_t); /* this is just an alias to the above */
|
||||
|
||||
inline static void udelay(long us)
|
||||
{
|
||||
wait((uint32_t) us);
|
||||
}
|
||||
|
||||
extern bool waitfor(uint32_t us, checker_func condition);
|
||||
extern uint32_t get_timer(void);
|
||||
extern void wait_ms(uint32_t ms);
|
||||
|
||||
#define US_TO_TIMER(a) ((a) * SYSCLK) / 1000000UL
|
||||
#define TIMER_TO_US(a) ((a) * 1000000UL) / SYSCLK)
|
||||
|
||||
#endif /* _WAIT_H_ */
|
||||
169
include/x86emu_regs.h
Normal file
169
include/x86emu_regs.h
Normal file
@@ -0,0 +1,169 @@
|
||||
/* $NetBSD: x86emu_regs.h,v 1.1 2007/12/01 20:14:10 joerg Exp $ */
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* Realmode X86 Emulator Library
|
||||
*
|
||||
* Copyright (C) 1996-1999 SciTech Software, Inc.
|
||||
* Copyright (C) David Mosberger-Tang
|
||||
* Copyright (C) 1999 Egbert Eich
|
||||
* Copyright (C) 2007 Joerg Sonnenberger
|
||||
*
|
||||
* ========================================================================
|
||||
*
|
||||
* Permission to use, copy, modify, distribute, and sell this software and
|
||||
* its documentation for any purpose is hereby granted without fee,
|
||||
* provided that the above copyright notice appear in all copies and that
|
||||
* both that copyright notice and this permission notice appear in
|
||||
* supporting documentation, and that the name of the authors not be used
|
||||
* in advertising or publicity pertaining to distribution of the software
|
||||
* without specific, written prior permission. The authors makes no
|
||||
* representations about the suitability of this software for any purpose.
|
||||
* It is provided "as is" without express or implied warranty.
|
||||
*
|
||||
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
|
||||
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
|
||||
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
|
||||
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
|
||||
* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
|
||||
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __X86EMU_REGS_H
|
||||
#define __X86EMU_REGS_H
|
||||
|
||||
/*---------------------- Macros and type definitions ----------------------*/
|
||||
|
||||
/* 8 bit registers */
|
||||
#define R_AH register_a.I8_reg.h_reg
|
||||
#define R_AL register_a.I8_reg.l_reg
|
||||
#define R_BH register_b.I8_reg.h_reg
|
||||
#define R_BL register_b.I8_reg.l_reg
|
||||
#define R_CH register_c.I8_reg.h_reg
|
||||
#define R_CL register_c.I8_reg.l_reg
|
||||
#define R_DH register_d.I8_reg.h_reg
|
||||
#define R_DL register_d.I8_reg.l_reg
|
||||
|
||||
/* 16 bit registers */
|
||||
#define R_AX register_a.I16_reg.x_reg
|
||||
#define R_BX register_b.I16_reg.x_reg
|
||||
#define R_CX register_c.I16_reg.x_reg
|
||||
#define R_DX register_d.I16_reg.x_reg
|
||||
|
||||
/* 32 bit extended registers */
|
||||
#define R_EAX register_a.I32_reg.e_reg
|
||||
#define R_EBX register_b.I32_reg.e_reg
|
||||
#define R_ECX register_c.I32_reg.e_reg
|
||||
#define R_EDX register_d.I32_reg.e_reg
|
||||
|
||||
/* special registers */
|
||||
#define R_SP register_sp.I16_reg.x_reg
|
||||
#define R_BP register_bp.I16_reg.x_reg
|
||||
#define R_SI register_si.I16_reg.x_reg
|
||||
#define R_DI register_di.I16_reg.x_reg
|
||||
#define R_IP register_ip.I16_reg.x_reg
|
||||
#define R_FLG register_flags
|
||||
|
||||
/* special registers */
|
||||
#define R_ESP register_sp.I32_reg.e_reg
|
||||
#define R_EBP register_bp.I32_reg.e_reg
|
||||
#define R_ESI register_si.I32_reg.e_reg
|
||||
#define R_EDI register_di.I32_reg.e_reg
|
||||
#define R_EIP register_ip.I32_reg.e_reg
|
||||
#define R_EFLG register_flags
|
||||
|
||||
/* segment registers */
|
||||
#define R_CS register_cs
|
||||
#define R_DS register_ds
|
||||
#define R_SS register_ss
|
||||
#define R_ES register_es
|
||||
#define R_FS register_fs
|
||||
#define R_GS register_gs
|
||||
|
||||
/* flag conditions */
|
||||
#define FB_CF 0x0001 /* CARRY flag */
|
||||
#define FB_PF 0x0004 /* PARITY flag */
|
||||
#define FB_AF 0x0010 /* AUX flag */
|
||||
#define FB_ZF 0x0040 /* ZERO flag */
|
||||
#define FB_SF 0x0080 /* SIGN flag */
|
||||
#define FB_TF 0x0100 /* TRAP flag */
|
||||
#define FB_IF 0x0200 /* INTERRUPT ENABLE flag */
|
||||
#define FB_DF 0x0400 /* DIR flag */
|
||||
#define FB_OF 0x0800 /* OVERFLOW flag */
|
||||
|
||||
/* 80286 and above always have bit#1 set */
|
||||
#define F_ALWAYS_ON (0x0002) /* flag bits always on */
|
||||
|
||||
/*
|
||||
* Define a mask for only those flag bits we will ever pass back
|
||||
* (via PUSHF)
|
||||
*/
|
||||
#define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF)
|
||||
|
||||
/* following bits masked in to a 16bit quantity */
|
||||
|
||||
#define F_CF 0x0001 /* CARRY flag */
|
||||
#define F_PF 0x0004 /* PARITY flag */
|
||||
#define F_AF 0x0010 /* AUX flag */
|
||||
#define F_ZF 0x0040 /* ZERO flag */
|
||||
#define F_SF 0x0080 /* SIGN flag */
|
||||
#define F_TF 0x0100 /* TRAP flag */
|
||||
#define F_IF 0x0200 /* INTERRUPT ENABLE flag */
|
||||
#define F_DF 0x0400 /* DIR flag */
|
||||
#define F_OF 0x0800 /* OVERFLOW flag */
|
||||
|
||||
#define SET_FLAG(flag) (emu->x86.R_FLG |= (flag))
|
||||
#define CLEAR_FLAG(flag) (emu->x86.R_FLG &= ~(flag))
|
||||
#define ACCESS_FLAG(flag) (emu->x86.R_FLG & (flag))
|
||||
#define CLEARALL_FLAG(m) (emu->x86.R_FLG = 0)
|
||||
|
||||
#define CONDITIONAL_SET_FLAG(COND,FLAG) \
|
||||
if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG)
|
||||
|
||||
#define F_PF_CALC 0x010000 /* PARITY flag has been calced */
|
||||
#define F_ZF_CALC 0x020000 /* ZERO flag has been calced */
|
||||
#define F_SF_CALC 0x040000 /* SIGN flag has been calced */
|
||||
|
||||
#define F_ALL_CALC 0xff0000 /* All have been calced */
|
||||
|
||||
/*
|
||||
* Emulator machine state.
|
||||
* Segment usage control.
|
||||
*/
|
||||
#define SYSMODE_SEG_DS_SS 0x00000001
|
||||
#define SYSMODE_SEGOVR_CS 0x00000002
|
||||
#define SYSMODE_SEGOVR_DS 0x00000004
|
||||
#define SYSMODE_SEGOVR_ES 0x00000008
|
||||
#define SYSMODE_SEGOVR_FS 0x00000010
|
||||
#define SYSMODE_SEGOVR_GS 0x00000020
|
||||
#define SYSMODE_SEGOVR_SS 0x00000040
|
||||
#define SYSMODE_PREFIX_REPE 0x00000080
|
||||
#define SYSMODE_PREFIX_REPNE 0x00000100
|
||||
#define SYSMODE_PREFIX_DATA 0x00000200
|
||||
#define SYSMODE_PREFIX_ADDR 0x00000400
|
||||
#define SYSMODE_INTR_PENDING 0x10000000
|
||||
#define SYSMODE_EXTRN_INTR 0x20000000
|
||||
#define SYSMODE_HALTED 0x40000000
|
||||
|
||||
#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \
|
||||
SYSMODE_SEGOVR_CS | \
|
||||
SYSMODE_SEGOVR_DS | \
|
||||
SYSMODE_SEGOVR_ES | \
|
||||
SYSMODE_SEGOVR_FS | \
|
||||
SYSMODE_SEGOVR_GS | \
|
||||
SYSMODE_SEGOVR_SS)
|
||||
#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \
|
||||
SYSMODE_SEGOVR_CS | \
|
||||
SYSMODE_SEGOVR_DS | \
|
||||
SYSMODE_SEGOVR_ES | \
|
||||
SYSMODE_SEGOVR_FS | \
|
||||
SYSMODE_SEGOVR_GS | \
|
||||
SYSMODE_SEGOVR_SS | \
|
||||
SYSMODE_PREFIX_DATA | \
|
||||
SYSMODE_PREFIX_ADDR)
|
||||
|
||||
#define INTR_SYNCH 0x1
|
||||
|
||||
#endif /* __X86EMU_REGS_H */
|
||||
138
include/xhdi_sd.h
Normal file
138
include/xhdi_sd.h
Normal file
@@ -0,0 +1,138 @@
|
||||
/*
|
||||
* xhdi_sd.h
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 01.05.2013
|
||||
* Copyright 2012 M. Fröschle
|
||||
*/
|
||||
|
||||
#ifndef _XHDI_SD_H_
|
||||
#define _XHDI_SD_H_
|
||||
|
||||
/* XHDI function numbers */
|
||||
|
||||
#define XHDI_VERSION 0
|
||||
#define XHDI_INQUIRE_TARGET 1
|
||||
#define XHDI_RESERVE 2
|
||||
#define XHDI_LOCK 3
|
||||
#define XHDI_STOP 4
|
||||
#define XHDI_EJECT 5
|
||||
#define XHDI_DRIVEMAP 6
|
||||
#define XHDI_INQUIRE_DEVICE 7
|
||||
#define XHDI_INQUIRE_DRIVER 8
|
||||
#define XHDI_NEW_COOKIE 9
|
||||
#define XHDI_READ_WRITE 10
|
||||
#define XHDI_INQUIRE_TARGET2 11
|
||||
#define XHDI_INQUIRE_DEVICE2 12
|
||||
#define XHDI_DRIVER_SPECIAL 13
|
||||
#define XHDI_GET_CAPACITY 14
|
||||
#define XHDI_MEDIUM_CHANGED 15
|
||||
#define XHDI_MINT_INFO 16
|
||||
#define XHDI_DOS_LIMITS 17
|
||||
#define XHDI_LAST_ACCESS 18
|
||||
#define XHDI_REACCESS 19
|
||||
|
||||
/* XHDI error codes */
|
||||
|
||||
#define E_OK 0 /* OK */
|
||||
#define ERROR -1 /* unspecified error */
|
||||
#define EDRVNR -2 /* drive not ready */
|
||||
#define EUNDEV -15 /* invalid device/target number */
|
||||
#define EINVFN -32 /* invalid function number */
|
||||
#define EACCDN -36 /* access denied (device currently reserved) */
|
||||
#define EDRIVE -46 /* BIOS device not served by driver */
|
||||
|
||||
/* XHDI device capabilities */
|
||||
|
||||
#define XH_TARGET_STOPPABLE (1 << 0)
|
||||
#define XH_TARGET_REMOVABLE (1 << 1)
|
||||
#define XH_TARGET_LOCKABLE (1 << 2)
|
||||
#define XH_TARGET_EJECTABLE (1 << 3)
|
||||
#define XH_TARGET_LOCKED (1 << 29)
|
||||
#define XH_TARGET_STOPPED (1 << 30)
|
||||
#define XH_TARGET_RESERVED (1 << 31)
|
||||
|
||||
typedef struct _BPB
|
||||
{
|
||||
uint16_t recsiz; /* Bytes per sector */
|
||||
uint16_t clsiz; /* Sectors per cluster */
|
||||
uint16_t clsizb; /* Bytes per cluster */
|
||||
uint16_t rdlen; /* Directory length */
|
||||
uint16_t fsiz; /* Length of the FAT */
|
||||
uint16_t fatrec; /* Start of the 2nd FAT */
|
||||
uint16_t datrec; /* 1st free sector */
|
||||
uint16_t numcl; /* Total numbr of clusters */
|
||||
uint16_t bflags; /* Flags as bit-vector */
|
||||
/* Bit 0: 0 (12-Bit-FAT), 1 16-Bit-FAT */
|
||||
/* Bit 1: 0 (two FATs), 1 (one FAT) */
|
||||
/* only available since TOS 2.06 */
|
||||
} BPB;
|
||||
|
||||
/* a riddle: how do you typedef a function pointer to a function that returns its own type? ;) */
|
||||
typedef void* (*xhdi_call_fun)(int xhdi_fun, ...);
|
||||
|
||||
extern uint32_t xhdi_call(uint16_t *stack);
|
||||
|
||||
extern xhdi_call_fun xhdi_sd_install(xhdi_call_fun old_vector) __attribute__((__interrupt__));
|
||||
|
||||
extern uint16_t xhdi_version(void); /* XHDI 0 */
|
||||
|
||||
extern uint32_t xhdi_inquire_target(uint16_t major, uint16_t minor, uint32_t *block_size, uint32_t *flags,
|
||||
char *product_name); /* XHDI 1 */
|
||||
|
||||
extern uint32_t xhdi_reserve(uint16_t major, uint16_t minor, uint16_t do_reserve, uint16_t key); /* XHDI 2 */
|
||||
|
||||
extern uint32_t xhdi_lock(uint16_t major, uint16_t minor, uint16_t do_lock, uint16_t key); /* XHDI 3 */
|
||||
|
||||
extern uint32_t xhdi_stop(uint16_t major, uint16_t minor, uint16_t do_stop, uint16_t key); /* XHDI 4 */
|
||||
|
||||
extern uint32_t xhdi_eject(uint16_t major, uint16_t minor, uint16_t do_eject, uint16_t key); /* XHDI 5 */
|
||||
|
||||
extern uint32_t xhdi_drivemap(void); /* XHDI 6 */
|
||||
|
||||
extern uint32_t xhdi_inquire_device(uint16_t bios_device, uint16_t *major, uint16_t *minor,
|
||||
uint32_t *start_sector, /* BPB */ void *bpb); /* XHDI 7 */
|
||||
|
||||
extern uint32_t xhdi_inquire_driver(uint16_t bios_device, char *name, char *version,
|
||||
char *company, uint16_t *ahdi_version, uint16_t *maxIPL); /* XHDI 8 */
|
||||
|
||||
extern uint32_t xhdi_new_cookie(uint32_t newcookie); /* XHDI 9 */
|
||||
|
||||
extern uint32_t xhdi_read_write(uint16_t major, uint16_t minor, uint16_t rwflag,
|
||||
uint32_t recno, uint16_t count, void *buf); /* XHDI 10 */
|
||||
|
||||
extern uint32_t xhdi_inquire_target2(uint16_t major, uint16_t minor, uint32_t *block_size,
|
||||
uint32_t *device_flags, char *product_name, uint16_t stringlen); /* XHDI 11 */
|
||||
|
||||
extern uint32_t xhdi_inquire_device2(uint16_t bios_device, uint16_t *major, uint16_t *minor,
|
||||
uint32_t *start_sector, BPB *bpb, uint32_t *blocks, char *partid); /* XHDI 12 */
|
||||
|
||||
extern uint32_t xhdi_driver_special(uint32_t key1, uint32_t key2, uint16_t subopcode, void *data); /* XHDI 13 */
|
||||
|
||||
extern uint32_t xhdi_get_capacity(uint16_t major, uint16_t minor, uint32_t *blocks, uint32_t *bs); /* XHDI 14 */
|
||||
|
||||
extern uint32_t xhdi_medium_changed(uint16_t major, uint16_t minor); /* XHDI 15 */
|
||||
|
||||
extern uint32_t xhdi_mint_info(uint16_t opcode, void *data); /* XHDI 16 */
|
||||
|
||||
extern uint32_t xhdi_dos_limits(uint16_t which, uint32_t limit); /* XHDI 17 */
|
||||
|
||||
extern uint32_t xhdi_last_access(uint16_t major, uint16_t minor, uint32_t *ms); /* XHDI 18 */
|
||||
|
||||
extern uint32_t xhdi_reaccess(uint16_t major, uint16_t minor); /* XHDI 19 */
|
||||
|
||||
#endif /* _XHDI_SD_H_ */
|
||||
352
kbd/ikbd.c
Normal file
352
kbd/ikbd.c
Normal file
@@ -0,0 +1,352 @@
|
||||
/*
|
||||
|
||||
https://www.kernel.org/doc/Documentation/input/atarikbd.txt
|
||||
|
||||
ikbd ToDo:
|
||||
|
||||
Feature Example using/needing it impl. tested
|
||||
---------------------------------------------------------------------
|
||||
mouse y at bottom Bolo X X
|
||||
mouse button key events Goldrunner/A_008 X X
|
||||
joystick interrogation mode Xevious/A_004 X X
|
||||
Absolute mouse mode Backlash/A_008, A-Ball/A50
|
||||
disable mouse ? X
|
||||
disable joystick ? X
|
||||
Joysticks also generate Goldrunner X X
|
||||
mouse button events!
|
||||
Pause (cmd 0x13) Wings of Death/A_427
|
||||
|
||||
*/
|
||||
|
||||
#include <bas_types.h>
|
||||
#include "bas_printf.h"
|
||||
#include "bas_string.h"
|
||||
|
||||
#include "user_io.h"
|
||||
//#include "hardware.h"
|
||||
#include "ikbd.h"
|
||||
|
||||
#include "debug.h"
|
||||
|
||||
// atari ikbd stuff
|
||||
#define IKBD_STATE_JOYSTICK_EVENT_REPORTING 0x01
|
||||
#define IKBD_STATE_MOUSE_Y_BOTTOM 0x02
|
||||
#define IKBD_STATE_MOUSE_BUTTON_AS_KEY 0x04 // mouse buttons act like keys
|
||||
#define IKBD_STATE_MOUSE_DISABLED 0x08
|
||||
#define IKBD_STATE_MOUSE_ABSOLUTE 0x10
|
||||
|
||||
#define IKBD_DEFAULT IKBD_STATE_JOYSTICK_EVENT_REPORTING
|
||||
|
||||
#define QUEUE_LEN 16 // power of 2!
|
||||
static unsigned char tx_queue[QUEUE_LEN];
|
||||
static unsigned char wptr = 0, rptr = 0;
|
||||
|
||||
// structure to keep track of ikbd state
|
||||
static struct
|
||||
{
|
||||
unsigned char cmd;
|
||||
unsigned char state;
|
||||
unsigned char expect;
|
||||
|
||||
// joystick state
|
||||
unsigned char joystick[2];
|
||||
|
||||
// mouse state
|
||||
unsigned short mouse_pos_x, mouse_pos_y;
|
||||
unsigned char mouse_buttons;
|
||||
} ikbd;
|
||||
|
||||
// #define IKBD_DEBUG
|
||||
|
||||
void ikbd_init()
|
||||
{
|
||||
// reset ikbd state
|
||||
memset(&ikbd, 0, sizeof(ikbd));
|
||||
ikbd.state = IKBD_DEFAULT;
|
||||
}
|
||||
|
||||
static void enqueue(unsigned char b)
|
||||
{
|
||||
if (((wptr + 1)&(QUEUE_LEN-1)) == rptr)
|
||||
{
|
||||
xprintf("IKBD: !!!!!!! tx queue overflow !!!!!!!!!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
tx_queue[wptr] = b;
|
||||
wptr = (wptr + 1) & (QUEUE_LEN - 1);
|
||||
}
|
||||
|
||||
// convert internal joystick format into atari ikbd format
|
||||
static unsigned char joystick_map2ikbd(unsigned in)
|
||||
{
|
||||
unsigned char out = 0;
|
||||
|
||||
if (in & JOY_UP) out |= 0x01;
|
||||
if (in & JOY_DOWN) out |= 0x02;
|
||||
if (in & JOY_LEFT) out |= 0x04;
|
||||
if (in & JOY_RIGHT) out |= 0x08;
|
||||
if (in & JOY_BTN1) out |= 0x80;
|
||||
|
||||
return out;
|
||||
}
|
||||
|
||||
// process inout from atari core into ikbd
|
||||
void ikbd_handle_input(unsigned char cmd)
|
||||
{
|
||||
// expecting a second byte for command
|
||||
if (ikbd.expect)
|
||||
{
|
||||
ikbd.expect--;
|
||||
|
||||
// last byte of command received
|
||||
if (!ikbd.expect)
|
||||
{
|
||||
switch(ikbd.cmd)
|
||||
{
|
||||
case 0x07: // set mouse button action
|
||||
xprintf("IKBD: mouse button action = %x\n", cmd);
|
||||
|
||||
// bit 2: Mouse buttons act like keys (LEFT=0x74 & RIGHT=0x75)
|
||||
if(cmd & 0x04) ikbd.state |= IKBD_STATE_MOUSE_BUTTON_AS_KEY;
|
||||
else ikbd.state &= ~IKBD_STATE_MOUSE_BUTTON_AS_KEY;
|
||||
|
||||
break;
|
||||
|
||||
case 0x80: // ibkd reset
|
||||
// reply "everything is ok"
|
||||
enqueue(0xf0);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
ikbd.cmd = cmd;
|
||||
|
||||
switch(cmd)
|
||||
{
|
||||
case 0x07:
|
||||
xprintf("IKBD: Set mouse button action");
|
||||
ikbd.expect = 1;
|
||||
break;
|
||||
|
||||
case 0x08:
|
||||
xprintf("IKBD: Set relative mouse positioning");
|
||||
ikbd.state &= ~IKBD_STATE_MOUSE_DISABLED;
|
||||
ikbd.state &= ~IKBD_STATE_MOUSE_ABSOLUTE;
|
||||
break;
|
||||
|
||||
case 0x09:
|
||||
xprintf("IKBD: Set absolute mouse positioning");
|
||||
ikbd.state &= ~IKBD_STATE_MOUSE_DISABLED;
|
||||
ikbd.state |= IKBD_STATE_MOUSE_ABSOLUTE;
|
||||
ikbd.expect = 4;
|
||||
break;
|
||||
|
||||
case 0x0b:
|
||||
xprintf("IKBD: Set Mouse threshold");
|
||||
ikbd.expect = 2;
|
||||
break;
|
||||
|
||||
case 0x0f:
|
||||
xprintf("IKBD: Set Y at bottom");
|
||||
ikbd.state |= IKBD_STATE_MOUSE_Y_BOTTOM;
|
||||
break;
|
||||
|
||||
case 0x10:
|
||||
xprintf("IKBD: Set Y at top");
|
||||
ikbd.state &= ~IKBD_STATE_MOUSE_Y_BOTTOM;
|
||||
break;
|
||||
|
||||
case 0x12:
|
||||
xprintf("IKBD: Disable mouse");
|
||||
ikbd.state |= IKBD_STATE_MOUSE_DISABLED;
|
||||
break;
|
||||
|
||||
case 0x14:
|
||||
xprintf("IKBD: Set Joystick event reporting");
|
||||
ikbd.state |= IKBD_STATE_JOYSTICK_EVENT_REPORTING;
|
||||
break;
|
||||
|
||||
case 0x15:
|
||||
xprintf("IKBD: Set Joystick interrogation mode");
|
||||
ikbd.state &= ~IKBD_STATE_JOYSTICK_EVENT_REPORTING;
|
||||
break;
|
||||
|
||||
case 0x16: // interrogate joystick
|
||||
// send reply
|
||||
enqueue(0xfd);
|
||||
enqueue(joystick_map2ikbd(ikbd.joystick[0]));
|
||||
enqueue(joystick_map2ikbd(ikbd.joystick[1]));
|
||||
break;
|
||||
|
||||
case 0x1a:
|
||||
xprintf("IKBD: Disable joysticks");
|
||||
ikbd.state &= ~IKBD_STATE_JOYSTICK_EVENT_REPORTING;
|
||||
break;
|
||||
|
||||
case 0x1c:
|
||||
xprintf("IKBD: Interrogate time of day");
|
||||
|
||||
enqueue(0xfc);
|
||||
enqueue(0x13); // year bcd
|
||||
enqueue(0x03); // month bcd
|
||||
enqueue(0x07); // day bcd
|
||||
enqueue(0x20); // hour bcd
|
||||
enqueue(0x58); // minute bcd
|
||||
enqueue(0x00); // second bcd
|
||||
break;
|
||||
|
||||
|
||||
case 0x80:
|
||||
xprintf("IKBD: Reset");
|
||||
ikbd.expect = 1;
|
||||
ikbd.state = IKBD_DEFAULT;
|
||||
break;
|
||||
|
||||
default:
|
||||
xprintf("IKBD: unknown command: %x\n", cmd);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* FIXME: temporarily provide function prototypes for unimplemented functions here to make compiler happy
|
||||
*/
|
||||
|
||||
extern int GetTimer(int);
|
||||
extern int CheckTimer(int);
|
||||
extern void EnableIO(void);
|
||||
extern void DisableIO(void);
|
||||
extern int SPI(int);
|
||||
|
||||
void ikbd_poll(void)
|
||||
{
|
||||
static int mtimer = 0;
|
||||
if (CheckTimer(mtimer))
|
||||
{
|
||||
mtimer = GetTimer(10);
|
||||
|
||||
// check for incoming ikbd data
|
||||
EnableIO();
|
||||
SPI(UIO_IKBD_IN);
|
||||
|
||||
while(SPI(0))
|
||||
ikbd_handle_input(SPI(0));
|
||||
|
||||
DisableIO();
|
||||
}
|
||||
|
||||
// send data from queue if present
|
||||
if(rptr == wptr) return;
|
||||
|
||||
// transmit data from queue
|
||||
EnableIO();
|
||||
SPI(UIO_IKBD_OUT);
|
||||
SPI(tx_queue[rptr]);
|
||||
DisableIO();
|
||||
|
||||
rptr = (rptr + 1) & (QUEUE_LEN - 1);
|
||||
}
|
||||
|
||||
void ikbd_joystick(unsigned char joystick, unsigned char map)
|
||||
{
|
||||
// todo: suppress events for joystick 0 as long as mouse
|
||||
// is enabled?
|
||||
|
||||
if (ikbd.state & IKBD_STATE_JOYSTICK_EVENT_REPORTING)
|
||||
{
|
||||
#ifdef IKBD_DEBUG
|
||||
xprintf("IKBD: joy %d %x\n", joystick, map);
|
||||
#endif
|
||||
|
||||
// only report joystick data for joystick 0 if the mouse is disabled
|
||||
if ((ikbd.state & IKBD_STATE_MOUSE_DISABLED) || (joystick == 1))
|
||||
{
|
||||
enqueue(0xfe + joystick);
|
||||
enqueue(joystick_map2ikbd(map));
|
||||
}
|
||||
|
||||
if (!(ikbd.state & IKBD_STATE_MOUSE_DISABLED))
|
||||
{
|
||||
// the fire button also generates a mouse event if
|
||||
// mouse reporting is enabled
|
||||
if ((map & JOY_BTN1) != (ikbd.joystick[joystick] & JOY_BTN1))
|
||||
{
|
||||
// generate mouse event (ikbd_joystick_buttons is evaluated inside
|
||||
// user_io_mouse)
|
||||
ikbd.joystick[joystick] = map;
|
||||
ikbd_mouse(0, 0, 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
#ifdef IKBD_DEBUG
|
||||
else
|
||||
xprintf("IKBD: no monitor, drop joy %d %x\n", joystick, map);
|
||||
#endif
|
||||
|
||||
// save state of joystick for interrogation mode
|
||||
ikbd.joystick[joystick] = map;
|
||||
}
|
||||
|
||||
void ikbd_keyboard(unsigned char code)
|
||||
{
|
||||
#ifdef IKBD_DEBUG
|
||||
xprintf("IKBD: send keycode %x%s\n", code&0x7f, (code&0x80)?" BREAK":"");
|
||||
#endif
|
||||
enqueue(code);
|
||||
}
|
||||
|
||||
void ikbd_mouse(uint8_t b, int8_t x, int8_t y)
|
||||
{
|
||||
if (ikbd.state & IKBD_STATE_MOUSE_DISABLED)
|
||||
return;
|
||||
|
||||
// joystick and mouse buttons are wired together in
|
||||
// atari st
|
||||
b |= (ikbd.joystick[0] & JOY_BTN1)?1:0;
|
||||
b |= (ikbd.joystick[1] & JOY_BTN1)?2:0;
|
||||
|
||||
static unsigned char b_old = 0;
|
||||
// monitor state of two mouse buttons
|
||||
if (b != b_old)
|
||||
{
|
||||
// check if mouse buttons are supposed to be treated like keys
|
||||
if (ikbd.state & IKBD_STATE_MOUSE_BUTTON_AS_KEY)
|
||||
{
|
||||
// Mouse buttons act like keys (LEFT=0x74 & RIGHT=0x75)
|
||||
|
||||
// handle left mouse button
|
||||
if((b ^ b_old) & 1) ikbd_keyboard(0x74 | ((b&1)?0x00:0x80));
|
||||
// handle right mouse button
|
||||
if((b ^ b_old) & 2) ikbd_keyboard(0x75 | ((b&2)?0x00:0x80));
|
||||
}
|
||||
b_old = b;
|
||||
}
|
||||
|
||||
#if 0
|
||||
if(ikbd.state & IKBD_STATE_MOUSE_BUTTON_AS_KEY)
|
||||
{
|
||||
b = 0;
|
||||
// if mouse position is 0/0 quit here
|
||||
if(!x && !y) return;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (ikbd.state & IKBD_STATE_MOUSE_ABSOLUTE)
|
||||
{
|
||||
}
|
||||
else
|
||||
{
|
||||
// atari has mouse button bits swapped
|
||||
enqueue(0xf8|((b&1)?2:0)|((b&2)?1:0));
|
||||
enqueue(x);
|
||||
enqueue((ikbd.state & IKBD_STATE_MOUSE_Y_BOTTOM)?-y:y);
|
||||
}
|
||||
}
|
||||
|
||||
71
mcf5474.gdb
Normal file
71
mcf5474.gdb
Normal file
@@ -0,0 +1,71 @@
|
||||
#
|
||||
# GDB Init script for the Coldfire 5474 processor (firebee).
|
||||
#
|
||||
|
||||
define addresses
|
||||
set $vbr = 0x00000000
|
||||
#monitor bdm-ctl-set 0x0801 0x00000000
|
||||
|
||||
set $mbar = 0xFF000000
|
||||
#monitor bdm-ctl-set 0x0C0F 0xFF000000
|
||||
|
||||
set $rambar0 = 0xFF100000
|
||||
#monitor bdm-ctl-set 0x0C04 0xFF100007
|
||||
|
||||
set $rambar1 = 0xFF101000
|
||||
#monitor bdm-ctl-set 0x0C05 0xFF101001
|
||||
end
|
||||
|
||||
#
|
||||
# Setup the DRAM controller.
|
||||
#
|
||||
|
||||
define setup-dram
|
||||
# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
|
||||
set *((long *) 0xFF000500) = 0xE0000000
|
||||
set *((long *) 0xFF000508) = 0x00041180
|
||||
set *((long *) 0xFF000504) = 0x007F0001
|
||||
|
||||
# set *((long *) 0xFF00050C) = 0xFFF00000 # ATARI I/O address
|
||||
|
||||
# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
|
||||
set *((long *) 0xFF000004) = 0x000002AA
|
||||
set *((long *) 0xFF000020) = 0x0000001A
|
||||
set *((long *) 0xFF000024) = 0x0800001A
|
||||
set *((long *) 0xFF000028) = 0x1000001A
|
||||
set *((long *) 0xFF00002C) = 0x1800001A
|
||||
set *((long *) 0xFF000108) = 0x73622830
|
||||
set *((long *) 0xFF00010C) = 0x46770000
|
||||
|
||||
|
||||
set *((long *) 0xFF000104) = 0xE10D0002
|
||||
set *((long *) 0xFF000100) = 0x40010000
|
||||
set *((long *) 0xFF000100) = 0x048D0000
|
||||
set *((long *) 0xFF000104) = 0xE10D0002
|
||||
set *((long *) 0xFF000104) = 0xE10D0004
|
||||
set *((long *) 0xFF000104) = 0xE10D0004
|
||||
set *((long *) 0xFF000100) = 0x008D0000
|
||||
set *((long *) 0xFF000104) = 0x710D0F00
|
||||
end
|
||||
|
||||
define cu
|
||||
!killall m68k-bdm-gdbserver
|
||||
end
|
||||
|
||||
#
|
||||
# Wake up the board
|
||||
#
|
||||
|
||||
define ib
|
||||
addresses
|
||||
setup-dram
|
||||
end
|
||||
|
||||
define run
|
||||
continue
|
||||
end
|
||||
|
||||
tr
|
||||
ib
|
||||
#add-symbol-file ../emutos/emutos2.img 0xe00000
|
||||
#load firebee/ram.elf
|
||||
8
memory_map.txt
Normal file
8
memory_map.txt
Normal file
@@ -0,0 +1,8 @@
|
||||
Firebee memory map
|
||||
==================
|
||||
|
||||
Virt. Start Virt. End Phys. Start Phys. End
|
||||
ST-RAM 0x00000000 0x00dfffff 0x60000000 0x60dfffff
|
||||
TOS 0x00e00000 0x00efffff 0x00e00000 0x00efffff
|
||||
ST I/O area 0x00f00000 0x01000000 0xfff00000 0xffffffff
|
||||
TT-RAM 0x01000000 0x20ffffff 0x00000000 0x1fffffff
|
||||
119
net/am79c874.c
Normal file
119
net/am79c874.c
Normal file
@@ -0,0 +1,119 @@
|
||||
/*
|
||||
* File: am79c874.c
|
||||
* Purpose: Driver for the AMD AM79C874 10/100 Ethernet PHY
|
||||
*/
|
||||
|
||||
#include "net.h"
|
||||
#include "fec.h"
|
||||
#include "am79c874.h"
|
||||
|
||||
#include "bas_printf.h"
|
||||
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
#include "firebee.h"
|
||||
#elif defined(MACHINE_M5484LITE)
|
||||
#include "m5484l.h"
|
||||
#elif defined(MACHINE_M54455)
|
||||
#include "m54455.h"
|
||||
#else
|
||||
#error "unknown machine!"
|
||||
#endif
|
||||
|
||||
#include <debug.h>
|
||||
// #define DEBUG
|
||||
|
||||
/* Initialize the AM79C874 PHY
|
||||
*
|
||||
* This function sets up the Auto-Negotiate Advertisement register
|
||||
* within the PHY and then forces the PHY to auto-negotiate for
|
||||
* it's settings.
|
||||
*
|
||||
* Params:
|
||||
* fec_ch FEC channel
|
||||
* phy_addr Address of the PHY.
|
||||
* speed Desired speed (10BaseT or 100BaseTX)
|
||||
* duplex Desired duplex (Full or Half)
|
||||
*
|
||||
* Return Value:
|
||||
* 0 if MII commands fail
|
||||
* 1 otherwise
|
||||
*/
|
||||
int am79c874_init(uint8_t fec_ch, uint8_t phy_addr, uint8_t speed, uint8_t duplex)
|
||||
{
|
||||
int timeout;
|
||||
uint16_t settings;
|
||||
if (speed); /* to do */
|
||||
if (duplex); /* to do */
|
||||
|
||||
/* Initialize the MII interface */
|
||||
fec_mii_init(fec_ch, SYSCLK / 1000);
|
||||
dbg("%s: PHY reset\r\n", __FUNCTION__);
|
||||
|
||||
/* Reset the PHY */
|
||||
if (!fec_mii_write(fec_ch, phy_addr, MII_AM79C874_CR, MII_AM79C874_CR_RESET))
|
||||
return 0;
|
||||
|
||||
/* Wait for the PHY to reset */
|
||||
for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
|
||||
{
|
||||
fec_mii_read(fec_ch, phy_addr, MII_AM79C874_CR, &settings);
|
||||
if (!(settings & MII_AM79C874_CR_RESET))
|
||||
break;
|
||||
}
|
||||
|
||||
if (timeout >= FEC_MII_TIMEOUT)
|
||||
{
|
||||
dbg("%s: PHY reset failed\r\n", __FUNCTION__);
|
||||
return 0;
|
||||
};
|
||||
dbg("%s: PHY reset OK\r\n", __FUNCTION__);
|
||||
dbg("%s: PHY Enable Auto-Negotiation\r\n", __FUNCTION__);
|
||||
|
||||
/* Enable Auto-Negotiation */
|
||||
if (!fec_mii_write(fec_ch, phy_addr, MII_AM79C874_CR, MII_AM79C874_CR_AUTON | MII_AM79C874_CR_RST_NEG))
|
||||
return 0;
|
||||
|
||||
dbg("%s:PHY Wait for auto-negotiation to complete\r\n", __FUNCTION__);
|
||||
|
||||
/* Wait for auto-negotiation to complete */
|
||||
for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
|
||||
{
|
||||
settings = 0;
|
||||
fec_mii_read(fec_ch, phy_addr, MII_AM79C874_SR, &settings);
|
||||
if ((settings & AUTONEGLINK) == AUTONEGLINK)
|
||||
break;
|
||||
}
|
||||
|
||||
if (timeout >= FEC_MII_TIMEOUT)
|
||||
{
|
||||
dbg("%s: Auto-negotiation failed (timeout). Set default mode (100Mbps, full duplex)\r\n", __FUNCTION__);
|
||||
|
||||
/* Set the default mode (Full duplex, 100 Mbps) */
|
||||
if (!fec_mii_write(fec_ch, phy_addr, MII_AM79C874_CR, MII_AM79C874_CR_100MB | MII_AM79C874_CR_DPLX))
|
||||
{
|
||||
dbg("%s: forced setting 100Mbps/full failed.\r\n", __FUNCTION__);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef DBG_AM79
|
||||
settings = 0;
|
||||
|
||||
fec_mii_read(fec_ch, phy_addr, MII_AM79C874_DR, &settings);
|
||||
|
||||
dbg("%s: PHY Mode:\r\n", __FUNCTION__);
|
||||
if (settings & MII_AM79C874_DR_DATA_RATE)
|
||||
dbg("%s: 100Mbps", __FUNCTION__);
|
||||
else
|
||||
dbg("%s: 10Mbps ", __FUNCTION__);
|
||||
|
||||
if (settings & MII_AM79C874_DR_DPLX)
|
||||
dbg("%s: Full-duplex\r\n", __FUNCTION__);
|
||||
else
|
||||
dbg("%s: Half-duplex\r\n", __FUNCTION__);
|
||||
|
||||
dbg("%s:PHY auto-negotiation complete\r\n", __FUNCTION__);
|
||||
#endif /* DBG_AM79 */
|
||||
|
||||
return 1;
|
||||
}
|
||||
486
net/arp.c
Normal file
486
net/arp.c
Normal file
@@ -0,0 +1,486 @@
|
||||
/*
|
||||
* File: arp.c
|
||||
* Purpose: Address Resolution Protocol routines.
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#include "net.h"
|
||||
#include "net_timer.h"
|
||||
#include "bas_printf.h"
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
|
||||
//#define DEBUG
|
||||
#include "debug.h"
|
||||
|
||||
#define TIMER_NETWORK 3
|
||||
|
||||
static uint8_t *arp_find_pair(ARP_INFO *arptab, uint16_t protocol, uint8_t *hwa, uint8_t *pa)
|
||||
{
|
||||
/*
|
||||
* This function searches through the ARP table for the
|
||||
* specified <protocol,hwa> or <protocol,pa> address pair.
|
||||
* If it is found, then a a pointer to the non-specified
|
||||
* address is returned. Otherwise NULL is returned.
|
||||
* If you pass in <protocol,pa> then you get <hwa> out.
|
||||
* If you pass in <protocol,hwa> then you get <pa> out.
|
||||
*/
|
||||
int slot, i, match = false;
|
||||
uint8_t *rvalue;
|
||||
|
||||
if (((hwa == 0) && (pa == 0)) || (arptab == 0))
|
||||
return NULL;
|
||||
|
||||
rvalue = NULL;
|
||||
|
||||
/*
|
||||
* Check each protocol address for a match
|
||||
*/
|
||||
for (slot = 0; slot < arptab->tab_size; slot++)
|
||||
{
|
||||
if ((arptab->table[slot].longevity != ARP_ENTRY_EMPTY) &&
|
||||
(arptab->table[slot].protocol == protocol))
|
||||
{
|
||||
match = true;
|
||||
if (hwa != 0)
|
||||
{
|
||||
/*
|
||||
* Check the Hardware Address field
|
||||
*/
|
||||
rvalue = &arptab->table[slot].pa[0];
|
||||
for (i = 0; i < arptab->table[slot].hwa_size; i++)
|
||||
{
|
||||
if (arptab->table[slot].hwa[i] != hwa[i])
|
||||
{
|
||||
match = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* Check the Protocol Address field
|
||||
*/
|
||||
rvalue = &arptab->table[slot].hwa[0];
|
||||
for (i = 0; i < arptab->table[slot].pa_size; i++)
|
||||
{
|
||||
if (arptab->table[slot].pa[i] != pa[i])
|
||||
{
|
||||
match = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (match)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (match)
|
||||
return rvalue;
|
||||
else
|
||||
return NULL;
|
||||
}
|
||||
|
||||
void arp_merge(ARP_INFO *arptab, uint16_t protocol, int hwa_size, uint8_t *hwa,
|
||||
int pa_size, uint8_t *pa, int longevity)
|
||||
{
|
||||
/*
|
||||
* This function merges an entry into the ARP table. If
|
||||
* either piece is NULL, the function exits, otherwise
|
||||
* the entry is merged or added, provided there is space.
|
||||
*/
|
||||
int i, slot;
|
||||
uint8_t *ta;
|
||||
|
||||
if ((hwa == NULL) || (pa == NULL) || (arptab == NULL) ||
|
||||
((longevity != ARP_ENTRY_TEMP) &&
|
||||
(longevity != ARP_ENTRY_PERM)))
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* First search ARP table for existing entry */
|
||||
if ((ta = arp_find_pair(arptab,protocol,NULL,pa)) != 0)
|
||||
{
|
||||
/* Update hardware address */
|
||||
for (i = 0; i < hwa_size; i++)
|
||||
ta[i] = hwa[i];
|
||||
return;
|
||||
}
|
||||
|
||||
/* Next try to find an empty slot */
|
||||
slot = -1;
|
||||
for (i = 0; i < MAX_ARP_ENTRY; i++)
|
||||
{
|
||||
if (arptab->table[i].longevity == ARP_ENTRY_EMPTY)
|
||||
{
|
||||
slot = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* if no empty slot was found, pick a temp slot */
|
||||
if (slot == -1)
|
||||
{
|
||||
for (i = 0; i < MAX_ARP_ENTRY; i++)
|
||||
{
|
||||
if (arptab->table[i].longevity == ARP_ENTRY_TEMP)
|
||||
{
|
||||
slot = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* if after all this, still no slot found, add in last slot */
|
||||
if (slot == -1)
|
||||
slot = (MAX_ARP_ENTRY - 1);
|
||||
|
||||
/* add the entry into the slot */
|
||||
arptab->table[slot].protocol = protocol;
|
||||
|
||||
arptab->table[slot].hwa_size = (uint8_t) hwa_size;
|
||||
for (i = 0; i < hwa_size; i++)
|
||||
arptab->table[slot].hwa[i] = hwa[i];
|
||||
|
||||
arptab->table[slot].pa_size = (uint8_t) pa_size;
|
||||
for (i = 0; i < pa_size; i++)
|
||||
arptab->table[slot].pa[i] = pa[i];
|
||||
|
||||
arptab->table[slot].longevity = longevity;
|
||||
}
|
||||
|
||||
|
||||
void arp_remove(ARP_INFO *arptab, uint16_t protocol, uint8_t *hwa, uint8_t *pa)
|
||||
{
|
||||
/*
|
||||
* This function removes an entry from the ARP table. The
|
||||
* ARP table is searched according to the non-NULL address
|
||||
* that is provided.
|
||||
*/
|
||||
int slot, i, match;
|
||||
|
||||
if (((hwa == 0) && (pa == 0)) || (arptab == 0))
|
||||
return;
|
||||
|
||||
/* check each hardware adress for a match */
|
||||
for (slot = 0; slot < arptab->tab_size; slot++)
|
||||
{
|
||||
if ((arptab->table[slot].longevity != ARP_ENTRY_EMPTY) &&
|
||||
(arptab->table[slot].protocol == protocol))
|
||||
{
|
||||
match = true;
|
||||
if (hwa != 0)
|
||||
{
|
||||
/* Check Hardware Address field */
|
||||
for (i = 0; i < arptab->table[slot].hwa_size; i++)
|
||||
{
|
||||
if (arptab->table[slot].hwa[i] != hwa[i])
|
||||
{
|
||||
match = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check Protocol Address field */
|
||||
for (i = 0; i < arptab->table[slot].pa_size; i++)
|
||||
{
|
||||
if (arptab->table[slot].pa[i] != pa[i])
|
||||
{
|
||||
match = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (match)
|
||||
{
|
||||
for (i = 0; i < arptab->table[slot].hwa_size; i++)
|
||||
arptab->table[slot].hwa[i] = 0;
|
||||
for (i = 0; i < arptab->table[slot].pa_size; i++)
|
||||
arptab->table[slot].pa[i] = 0;
|
||||
arptab->table[slot].longevity = ARP_ENTRY_EMPTY;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void arp_request(NIF *nif, uint8_t *pa)
|
||||
{
|
||||
/*
|
||||
* This function broadcasts an ARP request for the protocol
|
||||
* address "pa"
|
||||
*/
|
||||
uint8_t *addr;
|
||||
NBUF *pNbuf;
|
||||
arp_frame_hdr *arpframe;
|
||||
int i, result;
|
||||
|
||||
pNbuf = nbuf_alloc();
|
||||
if (pNbuf == NULL)
|
||||
{
|
||||
dbg("could not allocate Tx buffer\n");
|
||||
return;
|
||||
}
|
||||
|
||||
arpframe = (arp_frame_hdr *)&pNbuf->data[ARP_HDR_OFFSET];
|
||||
|
||||
/* Build the ARP request packet */
|
||||
arpframe->ar_hrd = ETHERNET;
|
||||
arpframe->ar_pro = ETH_FRM_IP;
|
||||
arpframe->ar_hln = 6;
|
||||
arpframe->ar_pln = 4;
|
||||
arpframe->opcode = ARP_REQUEST;
|
||||
|
||||
addr = &nif->hwa[0];
|
||||
for (i = 0; i < 6; i++)
|
||||
arpframe->ar_sha[i] = addr[i];
|
||||
|
||||
addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP));
|
||||
for (i = 0; i < 4; i++)
|
||||
arpframe->ar_spa[i] = addr[i];
|
||||
|
||||
for (i = 0; i < 6; i++)
|
||||
arpframe->ar_tha[i] = 0x00;
|
||||
|
||||
for (i = 0; i < 4; i++)
|
||||
arpframe->ar_tpa[i] = pa[i];
|
||||
|
||||
pNbuf->length = ARP_HDR_LEN;
|
||||
|
||||
/* Send the ARP request */
|
||||
dbg("sending ARP request\r\n");
|
||||
result = nif->send(nif, nif->broadcast, nif->hwa, ETH_FRM_ARP, pNbuf);
|
||||
|
||||
if (result == 0)
|
||||
nbuf_free(pNbuf);
|
||||
}
|
||||
|
||||
static int arp_resolve_pa(NIF *nif, uint16_t protocol, uint8_t *pa, uint8_t **ha)
|
||||
{
|
||||
/*
|
||||
* This function accepts a pointer to a protocol address and
|
||||
* searches the ARP table for a hardware address match. If no
|
||||
* no match found, false is returned.
|
||||
*/
|
||||
ARP_INFO *arptab;
|
||||
|
||||
if ((pa == NULL) || (nif == NULL) || (protocol == 0))
|
||||
return 0;
|
||||
|
||||
arptab = nif_get_protocol_info (nif,ETH_FRM_ARP);
|
||||
*ha = arp_find_pair(arptab,protocol,0,pa);
|
||||
|
||||
if (*ha == NULL)
|
||||
return 0;
|
||||
else
|
||||
return 1;
|
||||
}
|
||||
|
||||
uint8_t *arp_resolve(NIF *nif, uint16_t protocol, uint8_t *pa)
|
||||
{
|
||||
int i;
|
||||
uint8_t *hwa;
|
||||
|
||||
/*
|
||||
* Check to see if the necessary MAC-to-IP translation information
|
||||
* is in table already
|
||||
*/
|
||||
if (arp_resolve_pa(nif, protocol, pa, &hwa))
|
||||
return hwa;
|
||||
|
||||
/*
|
||||
* Ok, it's not, so we need to try to obtain it by broadcasting
|
||||
* an ARP request. Hopefully the desired host is listening and
|
||||
* will respond with it's MAC address
|
||||
*/
|
||||
for (i = 0; i < 3; i++)
|
||||
{
|
||||
arp_request(nif, pa);
|
||||
|
||||
timer_set_secs(TIMER_NETWORK, ARP_TIMEOUT);
|
||||
while (timer_get_reference(TIMER_NETWORK))
|
||||
{
|
||||
dbg("try to resolve %d.%d.%d.%d\r\n",
|
||||
pa[0], pa[1], pa[2], pa[3], pa[4]);
|
||||
if (arp_resolve_pa(nif, protocol, pa, &hwa))
|
||||
{
|
||||
dbg("resolved to %02x:%02x:%02x:%02x:%02x:%02x.\r\n",
|
||||
hwa[0], hwa[1], hwa[2], hwa[3], hwa[4], hwa[5], hwa[6]);
|
||||
|
||||
return hwa;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
void arp_init(ARP_INFO *arptab)
|
||||
{
|
||||
int slot, i;
|
||||
|
||||
arptab->tab_size = MAX_ARP_ENTRY;
|
||||
for (slot = 0; slot < arptab->tab_size; slot++)
|
||||
{
|
||||
for (i = 0; i < MAX_HWA_SIZE; i++)
|
||||
arptab->table[slot].hwa[i] = 0;
|
||||
for (i = 0; i < MAX_PA_SIZE; i++)
|
||||
arptab->table[slot].pa[i] = 0;
|
||||
arptab->table[slot].longevity = ARP_ENTRY_EMPTY;
|
||||
arptab->table[slot].hwa_size = 0;
|
||||
arptab->table[slot].pa_size = 0;
|
||||
}
|
||||
}
|
||||
|
||||
void arp_handler(NIF *nif, NBUF *pNbuf)
|
||||
{
|
||||
/*
|
||||
* ARP protocol handler
|
||||
*/
|
||||
uint8_t *addr;
|
||||
ARP_INFO *arptab;
|
||||
int longevity;
|
||||
arp_frame_hdr *rx_arpframe, *tx_arpframe;
|
||||
|
||||
arptab = nif_get_protocol_info(nif, ETH_FRM_ARP);
|
||||
rx_arpframe = (arp_frame_hdr *) &pNbuf->data[pNbuf->offset];
|
||||
|
||||
/*
|
||||
* Check for an appropriate ARP packet
|
||||
*/
|
||||
if ((pNbuf->length < ARP_HDR_LEN) ||
|
||||
(rx_arpframe->ar_hrd != ETHERNET) ||
|
||||
(rx_arpframe->ar_hln != 6) ||
|
||||
(rx_arpframe->ar_pro != ETH_FRM_IP) ||
|
||||
(rx_arpframe->ar_pln != 4))
|
||||
{
|
||||
dbg("received packet is not an ARP packet, discard it\r\n");
|
||||
nbuf_free(pNbuf);
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check to see if it was addressed to me - if it was, keep this
|
||||
* ARP entry in the table permanently; if not, mark it so that it
|
||||
* can be displaced later if necessary
|
||||
*/
|
||||
addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP));
|
||||
if ((rx_arpframe->ar_tpa[0] == addr[0]) &&
|
||||
(rx_arpframe->ar_tpa[1] == addr[1]) &&
|
||||
(rx_arpframe->ar_tpa[2] == addr[2]) &&
|
||||
(rx_arpframe->ar_tpa[3] == addr[3]) )
|
||||
{
|
||||
dbg("received ARP packet is a permanent one, store it\r\n");
|
||||
longevity = ARP_ENTRY_PERM;
|
||||
}
|
||||
else
|
||||
{
|
||||
dbg("received ARP packet was not addressed to us, keep only temporarily\r\n");
|
||||
longevity = ARP_ENTRY_TEMP;
|
||||
}
|
||||
|
||||
/*
|
||||
* Add ARP info into the table
|
||||
*/
|
||||
arp_merge(arptab,
|
||||
rx_arpframe->ar_pro,
|
||||
rx_arpframe->ar_hln,
|
||||
&rx_arpframe->ar_sha[0],
|
||||
rx_arpframe->ar_pln,
|
||||
&rx_arpframe->ar_spa[0],
|
||||
longevity
|
||||
);
|
||||
|
||||
switch (rx_arpframe->opcode)
|
||||
{
|
||||
case ARP_REQUEST:
|
||||
/*
|
||||
* Check to see if request is directed to me
|
||||
*/
|
||||
if ((rx_arpframe->ar_tpa[0] == addr[0]) &&
|
||||
(rx_arpframe->ar_tpa[1] == addr[1]) &&
|
||||
(rx_arpframe->ar_tpa[2] == addr[2]) &&
|
||||
(rx_arpframe->ar_tpa[3] == addr[3]) )
|
||||
{
|
||||
dbg("received arp request directed to us, replying\r\n");
|
||||
/*
|
||||
* Reuse the current network buffer to assemble an ARP reply
|
||||
*/
|
||||
tx_arpframe = (arp_frame_hdr *)&pNbuf->data[ARP_HDR_OFFSET];
|
||||
|
||||
/*
|
||||
* Build new ARP frame from the received data
|
||||
*/
|
||||
tx_arpframe->ar_hrd = ETHERNET;
|
||||
tx_arpframe->ar_pro = ETH_FRM_IP;
|
||||
tx_arpframe->ar_hln = 6;
|
||||
tx_arpframe->ar_pln = 4;
|
||||
tx_arpframe->opcode = ARP_REPLY;
|
||||
tx_arpframe->ar_tha[0] = rx_arpframe->ar_sha[0];
|
||||
tx_arpframe->ar_tha[1] = rx_arpframe->ar_sha[1];
|
||||
tx_arpframe->ar_tha[2] = rx_arpframe->ar_sha[2];
|
||||
tx_arpframe->ar_tha[3] = rx_arpframe->ar_sha[3];
|
||||
tx_arpframe->ar_tha[4] = rx_arpframe->ar_sha[4];
|
||||
tx_arpframe->ar_tha[5] = rx_arpframe->ar_sha[5];
|
||||
tx_arpframe->ar_tpa[0] = rx_arpframe->ar_spa[0];
|
||||
tx_arpframe->ar_tpa[1] = rx_arpframe->ar_spa[1];
|
||||
tx_arpframe->ar_tpa[2] = rx_arpframe->ar_spa[2];
|
||||
tx_arpframe->ar_tpa[3] = rx_arpframe->ar_spa[3];
|
||||
|
||||
/*
|
||||
* Now copy in the new information
|
||||
*/
|
||||
addr = &nif->hwa[0];
|
||||
tx_arpframe->ar_sha[0] = addr[0];
|
||||
tx_arpframe->ar_sha[1] = addr[1];
|
||||
tx_arpframe->ar_sha[2] = addr[2];
|
||||
tx_arpframe->ar_sha[3] = addr[3];
|
||||
tx_arpframe->ar_sha[4] = addr[4];
|
||||
tx_arpframe->ar_sha[5] = addr[5];
|
||||
|
||||
addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP));
|
||||
tx_arpframe->ar_spa[0] = addr[0];
|
||||
tx_arpframe->ar_spa[1] = addr[1];
|
||||
tx_arpframe->ar_spa[2] = addr[2];
|
||||
tx_arpframe->ar_spa[3] = addr[3];
|
||||
|
||||
/*
|
||||
* Save the length of my packet in the buffer structure
|
||||
*/
|
||||
pNbuf->length = ARP_HDR_LEN;
|
||||
|
||||
nif->send(nif,
|
||||
&tx_arpframe->ar_tha[0],
|
||||
&tx_arpframe->ar_sha[0],
|
||||
ETH_FRM_ARP,
|
||||
pNbuf);
|
||||
}
|
||||
else
|
||||
{
|
||||
dbg("ARP request not addressed to us, discarding\r\n");
|
||||
nbuf_free(pNbuf);
|
||||
}
|
||||
break;
|
||||
|
||||
case ARP_REPLY:
|
||||
/*
|
||||
* The ARP Reply case is already taken care of
|
||||
*/
|
||||
|
||||
/* missing break is intentional */
|
||||
|
||||
default:
|
||||
nbuf_free(pNbuf);
|
||||
break;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
178
net/bcm5222.c
Normal file
178
net/bcm5222.c
Normal file
@@ -0,0 +1,178 @@
|
||||
/*
|
||||
* File: bcm5222.c
|
||||
* Purpose: Driver for the Micrel BCM5222 10/100 Ethernet PHY
|
||||
*
|
||||
* Notes: This driver was written specifically for the M5475EVB
|
||||
* and M5485EVB. These boards use the MII signals from
|
||||
* FEC0 to control the PHY. Therefore the fec_ch parameter
|
||||
* is ignored when doing MII reads and writes.
|
||||
*/
|
||||
|
||||
#include "net.h"
|
||||
#include "fec.h"
|
||||
#include "bcm5222.h"
|
||||
|
||||
#include "bas_printf.h"
|
||||
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
#include "firebee.h"
|
||||
#elif defined(MACHINE_M5484LITE)
|
||||
#include "m5484l.h"
|
||||
#elif defined(MACHINE_M54455)
|
||||
#include "m54455.h"
|
||||
#else
|
||||
#error "Unknown machine!"
|
||||
#endif
|
||||
|
||||
// #define DEBUG
|
||||
#include "debug.h"
|
||||
|
||||
/*
|
||||
* Initialize the BCM5222 PHY
|
||||
*
|
||||
* This function sets up the Auto-Negotiate Advertisement register
|
||||
* within the PHY and then forces the PHY to auto-negotiate for
|
||||
* it's settings.
|
||||
*
|
||||
* Params:
|
||||
* fec_ch FEC channel
|
||||
* phy_addr Address of the PHY.
|
||||
* speed Desired speed (10BaseT or 100BaseTX)
|
||||
* duplex Desired duplex (Full or Half)
|
||||
*
|
||||
* Return Value:
|
||||
* 0 if MII commands fail
|
||||
* 1 otherwise
|
||||
*/
|
||||
int bcm5222_init(uint8_t fec_ch, uint8_t phy_addr, uint8_t speed, uint8_t duplex)
|
||||
{
|
||||
int timeout;
|
||||
uint16_t settings;
|
||||
|
||||
/* Initialize the MII interface */
|
||||
fec_mii_init(fec_ch, SYSCLK / 1000);
|
||||
dbg("PHY reset\r\n");
|
||||
|
||||
/* Reset the PHY */
|
||||
if (!fec_mii_write(fec_ch, phy_addr, BCM5222_CTRL, BCM5222_CTRL_RESET | BCM5222_CTRL_ANE))
|
||||
return 0;
|
||||
|
||||
/* Wait for the PHY to reset */
|
||||
for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
|
||||
{
|
||||
fec_mii_read(fec_ch, phy_addr, BCM5222_CTRL, &settings);
|
||||
if (!(settings & BCM5222_CTRL_RESET))
|
||||
break;
|
||||
}
|
||||
if(timeout >= FEC_MII_TIMEOUT)
|
||||
return 0;
|
||||
|
||||
dbg("PHY reset OK\r\n");
|
||||
|
||||
settings = (BCM5222_AN_ADV_NEXT_PAGE | BCM5222_AN_ADV_PAUSE);
|
||||
|
||||
if (speed == FEC_MII_10BASE_T)
|
||||
settings |= (uint16_t)((duplex == FEC_MII_FULL_DUPLEX)
|
||||
? (BCM5222_AN_ADV_10BT_FDX | BCM5222_AN_ADV_10BT)
|
||||
: BCM5222_AN_ADV_10BT);
|
||||
else /* (speed == FEC_MII_100BASE_TX) */
|
||||
settings = (uint16_t)((duplex == FEC_MII_FULL_DUPLEX)
|
||||
? (BCM5222_AN_ADV_100BTX_FDX | BCM5222_AN_ADV_100BTX
|
||||
| BCM5222_AN_ADV_10BT_FDX | BCM5222_AN_ADV_10BT)
|
||||
: (BCM5222_AN_ADV_100BTX | BCM5222_AN_ADV_10BT));
|
||||
|
||||
/* Set the Auto-Negotiation Advertisement Register */
|
||||
if (!fec_mii_write(fec_ch, phy_addr, BCM5222_AN_ADV, settings))
|
||||
return 0;
|
||||
|
||||
dbg("PHY Enable Auto-Negotiation\r\n");
|
||||
|
||||
/* Enable Auto-Negotiation */
|
||||
if (!fec_mii_write(fec_ch, phy_addr, BCM5222_CTRL, (BCM5222_CTRL_ANE | BCM5222_CTRL_RESTART_AN)))
|
||||
return 0;
|
||||
|
||||
dbg("PHY Wait for auto-negotiation to complete\r\n");
|
||||
|
||||
/* Wait for auto-negotiation to complete */
|
||||
for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
|
||||
{
|
||||
if (!fec_mii_read(fec_ch, phy_addr, BCM5222_STAT, &settings))
|
||||
return 0;
|
||||
if (settings & BCM5222_STAT_AN_COMPLETE)
|
||||
break;
|
||||
}
|
||||
|
||||
if (timeout < FEC_MII_TIMEOUT)
|
||||
{
|
||||
dbg("PHY auto-negociation complete\r\n");
|
||||
|
||||
/* Read Auxiliary Control/Status Register */
|
||||
if (!fec_mii_read(fec_ch, phy_addr, BCM5222_ACSR, &settings))
|
||||
return 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
dbg("auto negotiation failed, PHY Set the default mode\r\n");
|
||||
|
||||
/* Set the default mode (Full duplex, 100 Mbps) */
|
||||
if (!fec_mii_write(fec_ch, phy_addr, BCM5222_ACSR, settings = (BCM5222_ACSR_100BTX | BCM5222_ACSR_FDX)))
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Set the proper duplex in the FEC now that we have auto-negotiated */
|
||||
if (settings & BCM5222_ACSR_FDX)
|
||||
fec_duplex(fec_ch, FEC_MII_FULL_DUPLEX);
|
||||
else
|
||||
fec_duplex(fec_ch, FEC_MII_HALF_DUPLEX);
|
||||
|
||||
dbg("PHY Mode: ");
|
||||
|
||||
if (settings & BCM5222_ACSR_100BTX)
|
||||
dbg("100Mbps\r\n");
|
||||
else
|
||||
dbg("10Mbps\r\n");
|
||||
|
||||
if (settings & BCM5222_ACSR_FDX)
|
||||
dbg("Full-duplex\r\n");
|
||||
else
|
||||
dbg("Half-duplex\r\n");
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
void bcm5222_get_reg(uint16_t* status0, uint16_t* status1)
|
||||
{
|
||||
fec_mii_read(0, 0x00, 0x00000000, &status0[0]);
|
||||
fec_mii_read(0, 0x00, 0x00000001, &status0[1]);
|
||||
fec_mii_read(0, 0x00, 0x00000004, &status0[4]);
|
||||
fec_mii_read(0, 0x00, 0x00000005, &status0[5]);
|
||||
fec_mii_read(0, 0x00, 0x00000006, &status0[6]);
|
||||
fec_mii_read(0, 0x00, 0x00000007, &status0[7]);
|
||||
fec_mii_read(0, 0x00, 0x00000008, &status0[8]);
|
||||
fec_mii_read(0, 0x00, 0x00000010, &status0[16]);
|
||||
fec_mii_read(0, 0x00, 0x00000011, &status0[17]);
|
||||
fec_mii_read(0, 0x00, 0x00000012, &status0[18]);
|
||||
fec_mii_read(0, 0x00, 0x00000013, &status0[19]);
|
||||
fec_mii_read(0, 0x00, 0x00000018, &status0[24]);
|
||||
fec_mii_read(0, 0x00, 0x00000019, &status0[25]);
|
||||
fec_mii_read(0, 0x00, 0x0000001B, &status0[27]);
|
||||
fec_mii_read(0, 0x00, 0x0000001C, &status0[28]);
|
||||
fec_mii_read(0, 0x00, 0x0000001E, &status0[30]);
|
||||
fec_mii_read(0, 0x01, 0x00000000, &status1[0]);
|
||||
fec_mii_read(0, 0x01, 0x00000001, &status1[1]);
|
||||
fec_mii_read(0, 0x01, 0x00000004, &status1[4]);
|
||||
fec_mii_read(0, 0x01, 0x00000005, &status1[5]);
|
||||
fec_mii_read(0, 0x01, 0x00000006, &status1[6]);
|
||||
fec_mii_read(0, 0x01, 0x00000007, &status1[7]);
|
||||
fec_mii_read(0, 0x01, 0x00000008, &status1[8]);
|
||||
fec_mii_read(0, 0x01, 0x00000010, &status1[16]);
|
||||
fec_mii_read(0, 0x01, 0x00000011, &status1[17]);
|
||||
fec_mii_read(0, 0x01, 0x00000012, &status1[18]);
|
||||
fec_mii_read(0, 0x01, 0x00000013, &status1[19]);
|
||||
fec_mii_read(0, 0x01, 0x00000018, &status1[24]);
|
||||
fec_mii_read(0, 0x01, 0x00000019, &status1[25]);
|
||||
fec_mii_read(0, 0x01, 0x0000001B, &status1[27]);
|
||||
fec_mii_read(0, 0x01, 0x0000001C, &status1[28]);
|
||||
fec_mii_read(0, 0x01, 0x0000001E, &status1[30]);
|
||||
}
|
||||
|
||||
114
net/bootp.c
Normal file
114
net/bootp.c
Normal file
@@ -0,0 +1,114 @@
|
||||
/*
|
||||
* File: bootp.c
|
||||
* Purpose: Address Resolution Protocol routines.
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#include "net.h"
|
||||
#include "bootp.h"
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#include "bas_printf.h"
|
||||
|
||||
// #define DEBUG
|
||||
#include "debug.h"
|
||||
|
||||
#define TIMER_NETWORK 3 /* defines GPT3 as timer for this function */
|
||||
|
||||
static struct bootp_connection connection;
|
||||
#define XID 0x1234 /* this is arbitrary */
|
||||
#define MAX_TRIES 5 /* since UDP can fail */
|
||||
|
||||
void bootp_request(NIF *nif, uint8_t *pa)
|
||||
{
|
||||
/*
|
||||
* This function broadcasts a BOOTP request for the protocol
|
||||
* address "pa"
|
||||
*/
|
||||
uint8_t *addr;
|
||||
IP_ADDR broadcast = {255, 255, 255, 255};
|
||||
NBUF *nbuf;
|
||||
struct bootp_packet *p;
|
||||
int i, result;
|
||||
|
||||
nbuf = nbuf_alloc();
|
||||
if (nbuf == NULL)
|
||||
{
|
||||
xprintf("%s: couldn't allocate Tx buffer\r\n", __FUNCTION__);
|
||||
return;
|
||||
}
|
||||
|
||||
p = (struct bootp_packet *) &nbuf->data[BOOTP_HDR_OFFSET];
|
||||
|
||||
/* Build the BOOTP request packet */
|
||||
p->type = BOOTP_TYPE_BOOTREQUEST;
|
||||
p->htype = BOOTP_HTYPE_ETHERNET;
|
||||
p->hlen = BOOTP_HLEN_ETHERNET;
|
||||
p->hops = 0;
|
||||
p->xid = XID;
|
||||
p->secs = 1;
|
||||
p->flags = BOOTP_FLAGS_BROADCAST;
|
||||
p->cl_addr = 0x0;
|
||||
p->yi_addr = 0x0;
|
||||
p->gi_addr = 0x0;
|
||||
|
||||
connection.nif = nif;
|
||||
addr = &nif->hwa[0];
|
||||
|
||||
for (i = 0; i < 6; i++)
|
||||
p->ch_addr[i] = addr[i];
|
||||
|
||||
nbuf->length = BOOTP_PACKET_LEN;
|
||||
|
||||
/* setup reply handler */
|
||||
udp_bind_port(BOOTP_CLIENT_PORT, bootp_handler);
|
||||
|
||||
for (i = 0; i < MAX_TRIES; i++)
|
||||
{
|
||||
/* Send the BOOTP request */
|
||||
result = udp_send(connection.nif, broadcast, BOOTP_CLIENT_PORT,
|
||||
BOOTP_SERVER_PORT, nbuf);
|
||||
dbg("sent bootp request\r\n");
|
||||
if (result == true)
|
||||
break;
|
||||
}
|
||||
|
||||
/* release handler */
|
||||
udp_free_port(BOOTP_CLIENT_PORT);
|
||||
|
||||
if (result == 0)
|
||||
nbuf_free(nbuf);
|
||||
}
|
||||
|
||||
void bootp_handler(NIF *nif, NBUF *nbuf)
|
||||
{
|
||||
/*
|
||||
* BOOTP protocol handler
|
||||
*/
|
||||
struct bootp_packet *rx_p;
|
||||
udp_frame_hdr *udpframe;
|
||||
|
||||
(void) udpframe; /* FIXME: just to avoid compiler warning */
|
||||
dbg("\r\n");
|
||||
|
||||
rx_p = (struct bootp_packet *) &nbuf->data[nbuf->offset];
|
||||
udpframe = (udp_frame_hdr *) &nbuf->data[nbuf->offset - UDP_HDR_SIZE];
|
||||
|
||||
/*
|
||||
* check packet if it is valid and if it is really intended for us
|
||||
*/
|
||||
|
||||
if (rx_p->type == BOOTP_TYPE_BOOTREPLY && rx_p->xid == XID)
|
||||
{
|
||||
dbg("received bootp reply\r\n");
|
||||
/* seems to be valid */
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
dbg("received invalid bootp reply\r\n");
|
||||
/* not valid */
|
||||
return;
|
||||
}
|
||||
}
|
||||
239
net/fecbd.c
Normal file
239
net/fecbd.c
Normal file
@@ -0,0 +1,239 @@
|
||||
/*
|
||||
* File: fecbd.c
|
||||
* Purpose: Provide a simple buffer management driver
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
#include "MCD_dma.h"
|
||||
#include "fecbd.h"
|
||||
#include "nbuf.h"
|
||||
#include "eth.h"
|
||||
#include "bas_printf.h"
|
||||
#include <stddef.h>
|
||||
|
||||
//#define DBG_FECBD
|
||||
#ifdef DBG_FECBD
|
||||
#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
|
||||
#else
|
||||
#define dbg(format, arg...) do { ; } while (0)
|
||||
#endif /* DBG_FECBD */
|
||||
|
||||
/*
|
||||
* This implements a simple static buffer descriptor
|
||||
* ring for each channel and each direction
|
||||
*
|
||||
* FEC Buffer Descriptors need to be aligned to a 4-byte boundary.
|
||||
* In order to accomplish this, data is over-allocated and manually
|
||||
* aligned at runtime
|
||||
*
|
||||
* Enough space is allocated for each of the two FEC channels to have
|
||||
* NRXBD Rx BDs and NTXBD Tx BDs
|
||||
*
|
||||
*/
|
||||
|
||||
static FECBD unaligned_bds[(2 * NRXBD) + (2 * NTXBD) + 1];
|
||||
|
||||
/*
|
||||
* These pointers are used to reference into the chunck of data set
|
||||
* aside for buffer descriptors
|
||||
*/
|
||||
static FECBD *RxBD;
|
||||
static FECBD *TxBD;
|
||||
|
||||
/*
|
||||
* Macros to easier access to the BD ring
|
||||
*/
|
||||
#define RxBD(ch,i) RxBD[(ch * NRXBD) + i]
|
||||
#define TxBD(ch,i) TxBD[(ch * NTXBD) + i]
|
||||
|
||||
/*
|
||||
* Buffer descriptor indexes
|
||||
*/
|
||||
static int iTxbd_new;
|
||||
static int iTxbd_old;
|
||||
static int iRxbd;
|
||||
|
||||
/*
|
||||
* Initialize the FEC Buffer Descriptor ring
|
||||
* Buffer Descriptor format is defined by the MCDAPI
|
||||
*
|
||||
* Parameters:
|
||||
* ch FEC channel
|
||||
*/
|
||||
void fecbd_init(uint8_t ch)
|
||||
{
|
||||
NBUF *nbuf;
|
||||
int i;
|
||||
|
||||
dbg("\r\n");
|
||||
|
||||
/*
|
||||
* Align Buffer Descriptors to 4-byte boundary
|
||||
*/
|
||||
RxBD = (FECBD *)(((int) unaligned_bds + 3) & 0xFFFFFFFC);
|
||||
TxBD = (FECBD *)((int) RxBD + (sizeof(FECBD) * 2 * NRXBD));
|
||||
|
||||
dbg("initialise RX buffer descriptor ring\r\n");
|
||||
|
||||
/*
|
||||
* Initialize the Rx Buffer Descriptor ring
|
||||
*/
|
||||
for (i = 0; i < NRXBD; ++i)
|
||||
{
|
||||
/* Grab a network buffer from the free list */
|
||||
nbuf = nbuf_alloc();
|
||||
if (nbuf == NULL)
|
||||
{
|
||||
dbg("could not allocate network buffer\r\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Initialize the BD */
|
||||
RxBD(ch,i).status = RX_BD_E | RX_BD_INTERRUPT;
|
||||
RxBD(ch,i).length = RX_BUF_SZ;
|
||||
RxBD(ch,i).data = nbuf->data;
|
||||
|
||||
/* Add the network buffer to the Rx queue */
|
||||
nbuf_add(NBUF_RX_RING, nbuf);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set the WRAP bit on the last one
|
||||
*/
|
||||
RxBD(ch, i - 1).status |= RX_BD_W;
|
||||
|
||||
dbg("initialise TX buffer descriptor ring\r\n");
|
||||
|
||||
/*
|
||||
* Initialize the Tx Buffer Descriptor ring
|
||||
*/
|
||||
for (i = 0; i < NTXBD; ++i)
|
||||
{
|
||||
TxBD(ch, i).status = TX_BD_INTERRUPT;
|
||||
TxBD(ch, i).length = 0;
|
||||
TxBD(ch, i).data = NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set the WRAP bit on the last one
|
||||
*/
|
||||
TxBD(ch, i - 1).status |= TX_BD_W;
|
||||
|
||||
/*
|
||||
* Initialize the buffer descriptor indexes
|
||||
*/
|
||||
iTxbd_new = iTxbd_old = iRxbd = 0;
|
||||
}
|
||||
|
||||
void fecbd_dump(uint8_t ch)
|
||||
{
|
||||
#ifdef DBG_FECBD
|
||||
int i;
|
||||
|
||||
xprintf("\n------------ FEC%d BDs -----------\n",ch);
|
||||
xprintf("RxBD Ring\n");
|
||||
for (i = 0; i < NRXBD; i++)
|
||||
{
|
||||
xprintf("%02d: BD Addr=0x%08x, Ctrl=0x%04x, Lgth=%04d, DataPtr=0x%08x\n",
|
||||
i, &RxBD(ch, i),
|
||||
RxBD(ch, i).status,
|
||||
RxBD(ch, i).length,
|
||||
RxBD(ch, i).data);
|
||||
}
|
||||
xprintf("TxBD Ring\n");
|
||||
for (i = 0; i < NTXBD; i++)
|
||||
{
|
||||
xprintf("%02d: BD Addr=0x%08x, Ctrl=0x%04x, Lgth=%04d, DataPtr=0x%08x\n",
|
||||
i, &TxBD(ch, i),
|
||||
TxBD(ch, i).status,
|
||||
TxBD(ch, i).length,
|
||||
TxBD(ch, i).data);
|
||||
}
|
||||
xprintf("--------------------------------\n\n");
|
||||
#endif /* DBG_FECBD */
|
||||
}
|
||||
|
||||
/*
|
||||
* Return the address of the first buffer descriptor in the ring.
|
||||
*
|
||||
* Parameters:
|
||||
* ch FEC channel
|
||||
* direction Rx or Tx Macro
|
||||
*
|
||||
* Return Value:
|
||||
* The start address of the selected Buffer Descriptor ring
|
||||
*/
|
||||
uint32_t fecbd_get_start(uint8_t ch, uint8_t direction)
|
||||
{
|
||||
switch (direction)
|
||||
{
|
||||
case Rx:
|
||||
return (uint32_t)((int)RxBD + (ch * sizeof(FECBD) * NRXBD));
|
||||
case Tx:
|
||||
default:
|
||||
return (uint32_t)((int)TxBD + (ch * sizeof(FECBD) * NTXBD));
|
||||
}
|
||||
}
|
||||
|
||||
FECBD *fecbd_rx_alloc(uint8_t ch)
|
||||
{
|
||||
int i = iRxbd;
|
||||
|
||||
/* Check to see if the ring of BDs is full */
|
||||
if (RxBD(ch, i).status & RX_BD_E)
|
||||
return NULL;
|
||||
|
||||
/* Increment the circular index */
|
||||
iRxbd = (uint8_t)((iRxbd + 1) % NRXBD);
|
||||
|
||||
return &RxBD(ch, i);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function keeps track of the next available Tx BD in the ring
|
||||
*
|
||||
* Parameters:
|
||||
* ch FEC channel
|
||||
*
|
||||
* Return Value:
|
||||
* Pointer to next available buffer descriptor.
|
||||
* NULL if the BD ring is full
|
||||
*/
|
||||
FECBD *fecbd_tx_alloc(uint8_t ch)
|
||||
{
|
||||
int i = iTxbd_new;
|
||||
|
||||
/* Check to see if the ring of BDs is full */
|
||||
if (TxBD(ch, i).status & TX_BD_R)
|
||||
return NULL;
|
||||
|
||||
/* Increment the circular index */
|
||||
iTxbd_new = (uint8_t)((iTxbd_new + 1) % NTXBD);
|
||||
|
||||
return &TxBD(ch, i);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function keeps track of the Tx BDs that have already been
|
||||
* processed by the FEC
|
||||
*
|
||||
* Parameters:
|
||||
* ch FEC channel
|
||||
*
|
||||
* Return Value:
|
||||
* Pointer to the oldest buffer descriptor that has already been sent
|
||||
* by the FEC, NULL if the BD ring is empty
|
||||
*/
|
||||
FECBD *fecbd_tx_free(uint8_t ch)
|
||||
{
|
||||
int i = iTxbd_old;
|
||||
|
||||
/* Check to see if the ring of BDs is empty */
|
||||
if ((TxBD(ch, i).data == NULL) || (TxBD(ch, i).status & TX_BD_R))
|
||||
return NULL;
|
||||
|
||||
/* Increment the circular index */
|
||||
iTxbd_old = (uint8_t)((iTxbd_old + 1) % NTXBD);
|
||||
|
||||
return &TxBD(ch, i);
|
||||
}
|
||||
317
net/ip.c
Normal file
317
net/ip.c
Normal file
@@ -0,0 +1,317 @@
|
||||
/*
|
||||
* File: ip.c
|
||||
* Purpose: Internet Protcol device driver
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
* Modifications:
|
||||
*/
|
||||
#include <bas_types.h>
|
||||
#include "net.h"
|
||||
#include "bas_printf.h"
|
||||
#include "bas_string.h"
|
||||
|
||||
|
||||
//#define IP_DEBUG
|
||||
#if defined(IP_DEBUG)
|
||||
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
|
||||
#else
|
||||
#define dbg(format, arg...) do { ; } while (0)
|
||||
#endif
|
||||
|
||||
void ip_init(IP_INFO *info, IP_ADDR_P myip, IP_ADDR_P gateway, IP_ADDR_P netmask)
|
||||
{
|
||||
int index;
|
||||
|
||||
for (index = 0; index < sizeof(IP_ADDR); index++)
|
||||
{
|
||||
info->myip[index] = myip[index];
|
||||
info->gateway[index] = gateway[index];
|
||||
info->netmask[index] = netmask[index];
|
||||
info->broadcast[index] = 0xFF;
|
||||
}
|
||||
|
||||
info->rx = 0;
|
||||
info->rx_unsup = 0;
|
||||
info->tx = 0;
|
||||
info->err = 0;
|
||||
}
|
||||
|
||||
uint8_t *ip_get_myip(IP_INFO *info)
|
||||
{
|
||||
if (info != 0)
|
||||
{
|
||||
return (uint8_t *) &info->myip[0];
|
||||
}
|
||||
dbg("info is NULL!\n\t");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ip_addr_compare(IP_ADDR_P addr1, IP_ADDR_P addr2)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < sizeof(IP_ADDR); i++)
|
||||
{
|
||||
if (addr1[i] != addr2[i])
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
uint8_t *ip_resolve_route(NIF *nif, IP_ADDR_P destip)
|
||||
{
|
||||
/*
|
||||
* This function determines whether or not an outgoing IP
|
||||
* packet needs to be transmitted on the local net or sent
|
||||
* to the router for transmission.
|
||||
*/
|
||||
IP_INFO *info;
|
||||
IP_ADDR mask, result;
|
||||
IP_ADDR bc = { 255, 255, 255, 255 };
|
||||
int i;
|
||||
|
||||
info = nif_get_protocol_info(nif, ETH_FRM_IP);
|
||||
|
||||
if (memcmp(destip, bc, 4) == 0)
|
||||
{
|
||||
dbg("destip is broadcast address, no gateway needed\r\n");
|
||||
return destip;
|
||||
}
|
||||
|
||||
/* create mask for local IP */
|
||||
for (i = 0; i < sizeof(IP_ADDR); i++)
|
||||
{
|
||||
mask[i] = info->myip[i] & info->netmask[i];
|
||||
}
|
||||
|
||||
/* apply mask to the destination IP */
|
||||
for (i = 0; i < sizeof(IP_ADDR); i++)
|
||||
{
|
||||
result[i] = mask[i] & destip[i];
|
||||
}
|
||||
|
||||
/* See if destination IP is local or not */
|
||||
if (ip_addr_compare(mask, result))
|
||||
{
|
||||
/* The destination IP is on the local net */
|
||||
return arp_resolve(nif, ETH_FRM_IP, destip);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* The destination IP is not on the local net */
|
||||
return arp_resolve(nif, ETH_FRM_IP, info->gateway);
|
||||
}
|
||||
}
|
||||
|
||||
int ip_send(NIF *nif, uint8_t *dest, uint8_t *src, uint8_t protocol, NBUF *pNbuf)
|
||||
{
|
||||
/*
|
||||
* This function assembles an IP datagram and passes it
|
||||
* onto the hardware to be sent over the network.
|
||||
*/
|
||||
uint8_t *route;
|
||||
ip_frame_hdr *ipframe;
|
||||
|
||||
/*
|
||||
* Construct the IP header
|
||||
*/
|
||||
ipframe = (ip_frame_hdr*) &pNbuf->data[IP_HDR_OFFSET];
|
||||
|
||||
/* IP version 4, Internet Header Length of 5 32-bit words */
|
||||
ipframe->version_ihl = 0x45;
|
||||
|
||||
/* Type of Service == 0, normal and routine */
|
||||
ipframe->service_type = 0x00;
|
||||
|
||||
/* Total length of data */
|
||||
ipframe->total_length = (uint16_t) (pNbuf->length + IP_HDR_SIZE);
|
||||
|
||||
/* User defined identification */
|
||||
ipframe->identification = 0x0000;
|
||||
|
||||
/* Fragment Flags and Offset -- Don't fragment, last frag */
|
||||
ipframe->flags_frag_offset = 0x0000;
|
||||
|
||||
/* Time To Live */
|
||||
ipframe->ttl = 0xFF;
|
||||
|
||||
/* Protocol */
|
||||
ipframe->protocol = protocol;
|
||||
|
||||
/* Checksum, computed later, zeroed for computation */
|
||||
ipframe->checksum = 0x0000;
|
||||
|
||||
/* source IP address */
|
||||
ipframe->source_addr[0] = src[0];
|
||||
ipframe->source_addr[1] = src[1];
|
||||
ipframe->source_addr[2] = src[2];
|
||||
ipframe->source_addr[3] = src[3];
|
||||
|
||||
/* dest IP address */
|
||||
ipframe->dest_addr[0] = dest[0];
|
||||
ipframe->dest_addr[1] = dest[1];
|
||||
ipframe->dest_addr[2] = dest[2];
|
||||
ipframe->dest_addr[3] = dest[3];
|
||||
|
||||
/* Compute checksum */
|
||||
ipframe->checksum = ip_chksum((uint16_t *) ipframe, IP_HDR_SIZE);
|
||||
|
||||
/* Increment the packet length by the size of the IP header */
|
||||
pNbuf->length += IP_HDR_SIZE;
|
||||
|
||||
/*
|
||||
* Determine the hardware address of the recipient
|
||||
*/
|
||||
IP_ADDR bc = { 255, 255, 255, 255};
|
||||
if (memcmp(bc, dest, 4) != 0)
|
||||
{
|
||||
route = ip_resolve_route(nif, dest);
|
||||
if (route == NULL)
|
||||
{
|
||||
dbg("Unable to locate %d.%d.%d.%d\r\n",
|
||||
dest[0], dest[1], dest[2], dest[3]);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
route = bc;
|
||||
dbg("route = broadcast\r\n");
|
||||
dbg("nif = %p\r\n", nif);
|
||||
dbg("nif->send = %p\r\n", nif->send);
|
||||
}
|
||||
|
||||
return nif->send(nif, route, &nif->hwa[0], ETH_FRM_IP, pNbuf);
|
||||
}
|
||||
|
||||
#if defined(DEBUG_PRINT)
|
||||
void dump_ip_frame(ip_frame_hdr *ipframe)
|
||||
{
|
||||
xprintf("Version: %02X\n", ((ipframe->version_ihl & 0x00f0) >> 4));
|
||||
xprintf("IHL: %02X\n", ipframe->version_ihl & 0x000f);
|
||||
xprintf("Service: %02X\n", ipframe->service_type);
|
||||
xprintf("Length: %04X\n", ipframe->total_length);
|
||||
xprintf("Ident: %04X\n", ipframe->identification);
|
||||
xprintf("Flags: %02X\n", ((ipframe->flags_frag_offset & 0xC000) >> 14));
|
||||
xprintf("Frag: %04X\n", ipframe->flags_frag_offset & 0x3FFF);
|
||||
xprintf("TTL: %02X\n", ipframe->ttl);
|
||||
xprintf("Protocol: %02X\n", ipframe->protocol);
|
||||
xprintf("Chksum: %04X\n", ipframe->checksum);
|
||||
xprintf("Source : %d.%d.%d.%d\n",
|
||||
ipframe->source_addr[0],
|
||||
ipframe->source_addr[1],
|
||||
ipframe->source_addr[2],
|
||||
ipframe->source_addr[3]);
|
||||
xprintf("Dest : %d.%d.%d.%d\n",
|
||||
ipframe->dest_addr[0],
|
||||
ipframe->dest_addr[1],
|
||||
ipframe->dest_addr[2],
|
||||
ipframe->dest_addr[3]);
|
||||
xprintf("Options: %08X\n", ipframe->options);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
uint16_t ip_chksum(uint16_t *data, int num)
|
||||
{
|
||||
int chksum, ichksum;
|
||||
uint16_t temp;
|
||||
|
||||
chksum = 0;
|
||||
num = num >> 1; /* from bytes to words */
|
||||
for (; num; num--, data++)
|
||||
{
|
||||
temp = *data;
|
||||
ichksum = chksum + temp;
|
||||
ichksum = ichksum & 0x0000FFFF;
|
||||
if ((ichksum < temp) || (ichksum < chksum))
|
||||
{
|
||||
ichksum += 1;
|
||||
ichksum = ichksum & 0x0000FFFF;
|
||||
}
|
||||
chksum = ichksum;
|
||||
}
|
||||
return (uint16_t) ~chksum;
|
||||
}
|
||||
|
||||
static int validate_ip_hdr(NIF *nif, ip_frame_hdr *ipframe)
|
||||
{
|
||||
int index, chksum;
|
||||
IP_INFO *info;
|
||||
|
||||
/*
|
||||
* Check the IP Version
|
||||
*/
|
||||
if (IP_VERSION(ipframe) != 4)
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* Check Internet Header Length
|
||||
*/
|
||||
if (IP_IHL(ipframe) < 5)
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* Check the destination IP address
|
||||
*/
|
||||
info = nif_get_protocol_info(nif,ETH_FRM_IP);
|
||||
for (index = 0; index < sizeof(IP_ADDR); index++)
|
||||
if (info->myip[index] != ipframe->dest_addr[index])
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* Check the checksum
|
||||
*/
|
||||
chksum = (int)((uint16_t) IP_CHKSUM(ipframe));
|
||||
IP_CHKSUM(ipframe) = 0;
|
||||
|
||||
if (ip_chksum((uint16_t *) ipframe, IP_IHL(ipframe) * 4) != chksum)
|
||||
return 0;
|
||||
|
||||
IP_CHKSUM(ipframe) = (uint16_t) chksum;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
void ip_handler(NIF *nif, NBUF *pNbuf)
|
||||
{
|
||||
/*
|
||||
* IP packet handler
|
||||
*/
|
||||
ip_frame_hdr *ipframe;
|
||||
|
||||
dbg("packet received\r\n");
|
||||
|
||||
ipframe = (ip_frame_hdr *) &pNbuf->data[pNbuf->offset];
|
||||
|
||||
/*
|
||||
* Verify valid IP header and destination IP
|
||||
*/
|
||||
if (!validate_ip_hdr(nif, ipframe))
|
||||
{
|
||||
dbg("not a valid IP packet!\r\n");
|
||||
|
||||
nbuf_free(pNbuf);
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Call the appriopriate handler
|
||||
*/
|
||||
switch (IP_PROTOCOL(ipframe))
|
||||
{
|
||||
case IP_PROTO_ICMP:
|
||||
// FIXME: icmp_handler(nif, pNbuf);
|
||||
break;
|
||||
case IP_PROTO_UDP:
|
||||
udp_handler(nif,pNbuf);
|
||||
break;
|
||||
default:
|
||||
dbg("no protocol handler registered for protocol %d\r\n",
|
||||
__FUNCTION__, IP_PROTOCOL(ipframe));
|
||||
nbuf_free(pNbuf);
|
||||
break;
|
||||
}
|
||||
return;
|
||||
}
|
||||
224
net/nbuf.c
Normal file
224
net/nbuf.c
Normal file
@@ -0,0 +1,224 @@
|
||||
/*
|
||||
* File: nbuf.c
|
||||
* Purpose: Implementation of network buffer scheme.
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
#include "queue.h"
|
||||
#include "net.h"
|
||||
#include "driver_mem.h"
|
||||
#include "exceptions.h"
|
||||
#include "bas_types.h"
|
||||
#include "bas_printf.h"
|
||||
|
||||
|
||||
#define DBG_NBUF
|
||||
#if defined(DBG_NBUF)
|
||||
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
|
||||
#else
|
||||
#define dbg(format, arg...) do { ; } while (0)
|
||||
#endif /* DBG_NBUF */
|
||||
/*
|
||||
* Queues used for network buffer storage
|
||||
*/
|
||||
QUEUE nbuf_queue[NBUF_MAXQ];
|
||||
|
||||
/*
|
||||
* Some devices require line-aligned buffers. In order to accomplish
|
||||
* this, the nbuf data is over-allocated and adjusted. The following
|
||||
* array keeps track of the original data pointer returned by malloc
|
||||
*/
|
||||
uint8_t *unaligned_buffers[NBUF_MAX];
|
||||
|
||||
/*
|
||||
* Initialize all the network buffer queues
|
||||
*
|
||||
* Return Value:
|
||||
* 0 success
|
||||
* 1 failure
|
||||
*/
|
||||
int nbuf_init(void)
|
||||
{
|
||||
int i;
|
||||
NBUF *nbuf;
|
||||
|
||||
for (i = 0; i < NBUF_MAXQ; ++i)
|
||||
{
|
||||
/* Initialize all the queues */
|
||||
queue_init(&nbuf_queue[i]);
|
||||
}
|
||||
|
||||
dbg("Creating %d net buffers of %d bytes\r\n", NBUF_MAX, NBUF_SZ);
|
||||
|
||||
for (i = 0; i < NBUF_MAX; ++i)
|
||||
{
|
||||
/* Allocate memory for the network buffer structure */
|
||||
nbuf = (NBUF *) driver_mem_alloc(sizeof(NBUF));
|
||||
if (!nbuf)
|
||||
{
|
||||
xprintf("failed to allocate nbuf\r\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Allocate memory for the actual data */
|
||||
unaligned_buffers[i] = driver_mem_alloc(NBUF_SZ + 16);
|
||||
nbuf->data = (uint8_t *)((uint32_t)(unaligned_buffers[i] + 15) & 0xFFFFFFF0);
|
||||
if (!nbuf->data)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Initialize the network buffer */
|
||||
nbuf->offset = 0;
|
||||
nbuf->length = 0;
|
||||
|
||||
/* Add the network buffer to the free list */
|
||||
queue_add(&nbuf_queue[NBUF_FREE], (QNODE *)nbuf);
|
||||
}
|
||||
|
||||
dbg("NBUF allocation complete\r\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Return all the allocated memory to the heap
|
||||
*/
|
||||
void nbuf_flush(void)
|
||||
{
|
||||
NBUF *nbuf;
|
||||
int i;
|
||||
int level = set_ipl(7);
|
||||
int n = 0;
|
||||
|
||||
for (i = 0; i < NBUF_MAX; ++i)
|
||||
driver_mem_free((uint8_t *) unaligned_buffers[i]);
|
||||
|
||||
for (i = 0; i < NBUF_MAXQ; ++i)
|
||||
{
|
||||
while ((nbuf = (NBUF *) queue_remove(&nbuf_queue[i])) != NULL)
|
||||
{
|
||||
driver_mem_free(nbuf);
|
||||
++n;
|
||||
}
|
||||
}
|
||||
set_ipl(level);
|
||||
}
|
||||
|
||||
/*
|
||||
* Allocate a network buffer from the free list
|
||||
*
|
||||
* Return Value:
|
||||
* Pointer to a free network buffer
|
||||
* NULL if none are available
|
||||
*/
|
||||
NBUF *nbuf_alloc(void)
|
||||
{
|
||||
NBUF *nbuf;
|
||||
int level = set_ipl(7);
|
||||
|
||||
nbuf = (NBUF *) queue_remove(&nbuf_queue[NBUF_FREE]);
|
||||
set_ipl(level);
|
||||
|
||||
return nbuf;
|
||||
}
|
||||
|
||||
/*
|
||||
* Add the specified network buffer back to the free list
|
||||
*
|
||||
* Parameters:
|
||||
* nbuf Buffer to add back to the free list
|
||||
*/
|
||||
void nbuf_free(NBUF *nbuf)
|
||||
{
|
||||
int level = set_ipl(7);
|
||||
|
||||
nbuf->offset = 0;
|
||||
nbuf->length = NBUF_SZ;
|
||||
queue_add(&nbuf_queue[NBUF_FREE],(QNODE *) nbuf);
|
||||
|
||||
set_ipl(level);
|
||||
}
|
||||
|
||||
/*
|
||||
* Remove a network buffer from the specified queue
|
||||
*
|
||||
* Parameters:
|
||||
* q The index that identifies the queue to pull the buffer from
|
||||
*/
|
||||
NBUF *nbuf_remove(int q)
|
||||
{
|
||||
NBUF *nbuf;
|
||||
int level = set_ipl(7);
|
||||
|
||||
nbuf = (NBUF *) queue_remove(&nbuf_queue[q]);
|
||||
set_ipl(level);
|
||||
|
||||
return nbuf;
|
||||
}
|
||||
|
||||
/*
|
||||
* Add a network buffer to the specified queue
|
||||
*
|
||||
* Parameters:
|
||||
* q The index that identifies the queue to add the buffer to
|
||||
*/
|
||||
void nbuf_add(int q, NBUF *nbuf)
|
||||
{
|
||||
int level = set_ipl(7);
|
||||
|
||||
queue_add(&nbuf_queue[q], (QNODE *) nbuf);
|
||||
set_ipl(level);
|
||||
}
|
||||
|
||||
/*
|
||||
* Put all the network buffers back into the free list
|
||||
*/
|
||||
void nbuf_reset(void)
|
||||
{
|
||||
NBUF *nbuf;
|
||||
int i;
|
||||
int level = set_ipl(7);
|
||||
|
||||
for (i = 1; i < NBUF_MAXQ; ++i)
|
||||
{
|
||||
while ((nbuf = nbuf_remove(i)) != NULL)
|
||||
nbuf_free(nbuf);
|
||||
}
|
||||
set_ipl(level);
|
||||
}
|
||||
|
||||
/*
|
||||
* Display all the nbuf queues
|
||||
*/
|
||||
void nbuf_debug_dump(void)
|
||||
{
|
||||
#ifdef DBG_NBUF
|
||||
NBUF *nbuf;
|
||||
int i;
|
||||
int j;
|
||||
int level;
|
||||
|
||||
level = set_ipl(7);
|
||||
|
||||
for (i = 0; i < NBUF_MAXQ; ++i)
|
||||
{
|
||||
dbg("\r\n\r\nQueue #%d\r\n\r\n", i);
|
||||
dbg("\tBuffer Location\tOffset\tLength\r\n");
|
||||
dbg("--------------------------------------\r\n");
|
||||
j = 0;
|
||||
nbuf = (NBUF *) queue_peek(&nbuf_queue[i]);
|
||||
|
||||
while (nbuf != NULL)
|
||||
{
|
||||
dbg("%d\t0x%08x\t0x%04x\t0x%04x\r\n", j++, nbuf->data,
|
||||
nbuf->offset,
|
||||
nbuf->length);
|
||||
nbuf = (NBUF *) nbuf->node.next;
|
||||
}
|
||||
}
|
||||
dbg("\r\n");
|
||||
|
||||
set_ipl(level);
|
||||
#endif /* DBG_NBUF */
|
||||
}
|
||||
202
net/net_timer.c
Normal file
202
net/net_timer.c
Normal file
@@ -0,0 +1,202 @@
|
||||
/*
|
||||
* File: net_timer.c
|
||||
* Purpose: Provide a timer use by the BaS network as a timeout
|
||||
* indicator
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#include "net_timer.h"
|
||||
#include "bas_printf.h"
|
||||
#include "MCF5475.h"
|
||||
#include "interrupts.h"
|
||||
|
||||
//#define DBG_TMR
|
||||
#ifdef DBG_TMR
|
||||
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
|
||||
#else
|
||||
#define dbg(format, arg...) do { ; } while (0)
|
||||
#endif /* DBG_TMR */
|
||||
|
||||
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
#include "firebee.h"
|
||||
#elif defined(MACHINE_M5484LITE)
|
||||
#include "m5484l.h"
|
||||
#elif defined(MACHINE_M54455)
|
||||
#include "m54455.h"
|
||||
#else
|
||||
#error unknown machine!
|
||||
#endif
|
||||
|
||||
static NET_TIMER net_timer[4] =
|
||||
{
|
||||
{0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0}
|
||||
};
|
||||
|
||||
|
||||
bool timer_default_isr(void *not_used, NET_TIMER *t)
|
||||
{
|
||||
(void) not_used;
|
||||
|
||||
/*
|
||||
* Clear the pending event
|
||||
*/
|
||||
MCF_GPT_GMS(t->ch) = 0;
|
||||
|
||||
dbg("timer isr called for timer channel %d\r\n");
|
||||
|
||||
/*
|
||||
* Clear the reference - the desired seconds have expired
|
||||
*/
|
||||
t->reference = 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
void timer_irq_enable(uint8_t ch)
|
||||
{
|
||||
/*
|
||||
* Setup the appropriate ICR
|
||||
*/
|
||||
MCF_INTC_ICR(TIMER_VECTOR(ch) - 64) = MCF_INTC_ICR_IP(net_timer[ch].pri) |
|
||||
MCF_INTC_ICR_IL(net_timer[ch].lvl);
|
||||
|
||||
/*
|
||||
* Unmask the FEC interrupt in the interrupt controller
|
||||
*/
|
||||
if (ch == 3)
|
||||
{
|
||||
MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK59;
|
||||
}
|
||||
else if (ch == 2)
|
||||
{
|
||||
MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK60;
|
||||
}
|
||||
else if (ch == 1)
|
||||
{
|
||||
MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK61;
|
||||
}
|
||||
else
|
||||
{
|
||||
MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK62;
|
||||
}
|
||||
}
|
||||
|
||||
bool timer_set_secs(uint8_t ch, uint32_t secs)
|
||||
{
|
||||
uint16_t timeout;
|
||||
|
||||
/*
|
||||
* Reset the timer
|
||||
*/
|
||||
MCF_GPT_GMS(ch) = 0;
|
||||
|
||||
/*
|
||||
* Get the timeout in seconds
|
||||
*/
|
||||
timeout = (uint16_t)(secs * net_timer[ch].cnt);
|
||||
|
||||
/*
|
||||
* Set the reference indicating that we have not yet reached the
|
||||
* desired timeout
|
||||
*/
|
||||
net_timer[ch].reference = 1;
|
||||
|
||||
/*
|
||||
* Enable timer interrupt to the processor
|
||||
*/
|
||||
timer_irq_enable(ch);
|
||||
|
||||
/*
|
||||
* Enable the timer using the pre-calculated values
|
||||
*/
|
||||
MCF_GPT_GCIR(ch) = (0
|
||||
| MCF_GPT_GCIR_CNT(timeout)
|
||||
| MCF_GPT_GCIR_PRE(net_timer[ch].pre)
|
||||
);
|
||||
MCF_GPT_GMS(ch) = net_timer[ch].gms;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
uint32_t timer_get_reference(uint8_t ch)
|
||||
{
|
||||
return (uint32_t) net_timer[ch].reference;
|
||||
}
|
||||
|
||||
bool timer_init(uint8_t ch, uint8_t lvl, uint8_t pri)
|
||||
{
|
||||
/*
|
||||
* Initialize the timer to expire after one second
|
||||
*
|
||||
* This routine should only be called by the project (board) specific
|
||||
* initialization code.
|
||||
*/
|
||||
if (!((ch <= 3) && (lvl <= 7) && (lvl >= 1) && (pri <= 7)))
|
||||
{
|
||||
dbg("illegal parameters (ch=%d, lvl=%d, pri=%d)\r\n", ch, lvl, pri);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/*
|
||||
* Reset the timer
|
||||
*/
|
||||
MCF_GPT_GMS(ch) = 0;
|
||||
|
||||
/*
|
||||
* Save off the channel, and interrupt lvl/pri information
|
||||
*/
|
||||
net_timer[ch].ch = ch;
|
||||
net_timer[ch].lvl = lvl;
|
||||
net_timer[ch].pri = pri;
|
||||
|
||||
/*
|
||||
* Register the timer interrupt handler
|
||||
*/
|
||||
if (!isr_register_handler(TIMER_VECTOR(ch), 3, 0,
|
||||
(bool (*)(void *,void *)) timer_default_isr,
|
||||
NULL,
|
||||
(void *) &net_timer[ch])
|
||||
)
|
||||
{
|
||||
dbg("could not register timer interrupt handler\r\n");
|
||||
return false;
|
||||
}
|
||||
dbg("timer handler registered\r\n", __FUNCTION__);
|
||||
|
||||
/*
|
||||
* Calculate the require CNT value to get a 1 second timeout
|
||||
*
|
||||
* 1 sec = CNT * Clk Period * PRE
|
||||
* CNT = 1 sec / (Clk Period * PRE)
|
||||
* CNT = Clk Freq / PRE
|
||||
*
|
||||
* The system clock frequency is defined as SYSTEM_CLOCK and
|
||||
* is given in MHz. We need to multiple it by 1000000 to get the
|
||||
* true value. If we assume PRE to be the maximum of 0xFFFF,
|
||||
* then the CNT value needed to achieve a 1 second timeout is
|
||||
* given by:
|
||||
*
|
||||
* CNT = SYSTEM_CLOCK * (1000000/0xFFFF)
|
||||
*/
|
||||
net_timer[ch].pre = 0xFFFF;
|
||||
net_timer[ch].cnt = (uint16_t) ((SYSCLK / 1000) * (1000000 / 0xFFFF));
|
||||
|
||||
/*
|
||||
* Save off the appropriate mode select register value
|
||||
*/
|
||||
net_timer[ch].gms = (0
|
||||
| MCF_GPT_GMS_TMS_GPIO
|
||||
| MCF_GPT_GMS_IEN
|
||||
| MCF_GPT_GMS_SC
|
||||
| MCF_GPT_GMS_CE
|
||||
);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
130
net/nif.c
Normal file
130
net/nif.c
Normal file
@@ -0,0 +1,130 @@
|
||||
/*
|
||||
* File: nif.c
|
||||
* Purpose: Network InterFace routines
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
* Modifications:
|
||||
*
|
||||
*/
|
||||
#include "net.h"
|
||||
#include "bas_types.h"
|
||||
#include "bas_printf.h"
|
||||
|
||||
#define DBG_NIF
|
||||
#ifdef DBG_NIF
|
||||
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
|
||||
#else
|
||||
#define dbg(format, arg...) do { ; } while (0)
|
||||
#endif /* DBG_NIF */
|
||||
|
||||
int nif_protocol_exist(NIF *nif, uint16_t protocol)
|
||||
{
|
||||
/*
|
||||
* This function searches the list of supported protocols
|
||||
* on the particular NIF and if a protocol handler exists,
|
||||
* true is returned. This function is useful for network cards
|
||||
* that needn't read in the entire frame but can discard frames
|
||||
* arbitrarily.
|
||||
*/
|
||||
int index;
|
||||
|
||||
for (index = 0; index < nif->num_protocol; ++index)
|
||||
{
|
||||
if (nif->protocol[index].protocol == protocol)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
void nif_protocol_handler(NIF *nif, uint16_t protocol, NBUF *pNbuf)
|
||||
{
|
||||
/*
|
||||
* This function searches the list of supported protocols
|
||||
* on the particular NIF and if a protocol handler exists,
|
||||
* the protocol handler is invoked. This routine called by
|
||||
* network device driver after receiving a frame.
|
||||
*/
|
||||
int index;
|
||||
|
||||
for (index = 0; index < nif->num_protocol; ++index)
|
||||
{
|
||||
if (nif->protocol[index].protocol == protocol)
|
||||
{
|
||||
dbg("call protocol handler for protocol %d at %p\r\n", protocol,
|
||||
nif->protocol[index].handler);
|
||||
nif->protocol[index].handler(nif,pNbuf);
|
||||
return;
|
||||
}
|
||||
}
|
||||
dbg("no protocol handler found for protocol %d\r\n", protocol);
|
||||
}
|
||||
|
||||
void *nif_get_protocol_info(NIF *nif, uint16_t protocol)
|
||||
{
|
||||
/*
|
||||
* This function searches the list of supported protocols
|
||||
* on the particular NIF and returns a pointer to the
|
||||
* config info for 'protocol', otherwise NULL is returned.
|
||||
*/
|
||||
int index;
|
||||
|
||||
for (index = 0; index < nif->num_protocol; ++index)
|
||||
{
|
||||
if (nif->protocol[index].protocol == protocol)
|
||||
return (void *)nif->protocol[index].info;
|
||||
}
|
||||
return (void *)0;
|
||||
}
|
||||
|
||||
int nif_bind_protocol(NIF *nif, uint16_t protocol, void (*handler)(NIF *,NBUF *),
|
||||
void *info)
|
||||
{
|
||||
/*
|
||||
* This function registers 'protocol' as a supported
|
||||
* protocol in 'nif'.
|
||||
*/
|
||||
if (nif->num_protocol < (MAX_SUP_PROTO - 1))
|
||||
{
|
||||
nif->protocol[nif->num_protocol].protocol = protocol;
|
||||
nif->protocol[nif->num_protocol].handler = (void(*)(NIF *, NBUF *)) handler;
|
||||
nif->protocol[nif->num_protocol].info = info;
|
||||
++nif->num_protocol;
|
||||
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
NIF *nif_init (NIF *nif)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ETH_ADDR_LEN; ++i)
|
||||
{
|
||||
nif->hwa[i] = 0;
|
||||
nif->broadcast[i] = 0xFF;
|
||||
}
|
||||
|
||||
for (i = 0; i < MAX_SUP_PROTO; ++i)
|
||||
{
|
||||
nif->protocol[i].protocol = 0;
|
||||
nif->protocol[i].handler = 0;
|
||||
nif->protocol[i].info = 0;
|
||||
}
|
||||
nif->num_protocol = 0;
|
||||
|
||||
nif->mtu = 0;
|
||||
nif->ch = 0;
|
||||
nif->send = 0;
|
||||
|
||||
nif->f_rx = 0;
|
||||
nif->f_tx = 0;
|
||||
nif->f_rx_err = 0;
|
||||
nif->f_tx_err = 0;
|
||||
nif->f_err = 0;
|
||||
|
||||
return nif;
|
||||
}
|
||||
114
net/queue.c
Normal file
114
net/queue.c
Normal file
@@ -0,0 +1,114 @@
|
||||
/*
|
||||
* File: queue.c
|
||||
* Purpose: Implement a first in, first out linked list
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
#include "bas_string.h"
|
||||
#include "queue.h"
|
||||
|
||||
/*
|
||||
* Initialize the specified queue to an empty state
|
||||
*
|
||||
* Parameters:
|
||||
* q Pointer to queue structure
|
||||
*/
|
||||
void queue_init(QUEUE *q)
|
||||
{
|
||||
q->head = NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check for an empty queue
|
||||
*
|
||||
* Parameters:
|
||||
* q Pointer to queue structure
|
||||
*
|
||||
* Return Value:
|
||||
* 1 if Queue is empty
|
||||
* 0 otherwise
|
||||
*/
|
||||
int queue_isempty(QUEUE *q)
|
||||
{
|
||||
return (q->head == NULL);
|
||||
}
|
||||
|
||||
/*
|
||||
* Add an item to the end of the queue
|
||||
*
|
||||
* Parameters:
|
||||
* q Pointer to queue structure
|
||||
* node New node to add to the queue
|
||||
*/
|
||||
void queue_add(QUEUE *q, QNODE *node)
|
||||
{
|
||||
if (queue_isempty(q))
|
||||
{
|
||||
q->head = q->tail = node;
|
||||
}
|
||||
else
|
||||
{
|
||||
q->tail->next = node;
|
||||
q->tail = node;
|
||||
}
|
||||
|
||||
node->next = NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Remove and return first (oldest) entry from the specified queue
|
||||
*
|
||||
* Parameters:
|
||||
* q Pointer to queue structure
|
||||
*
|
||||
* Return Value:
|
||||
* Node at head of queue - NULL if queue is empty
|
||||
*/
|
||||
QNODE *queue_remove(QUEUE *q)
|
||||
{
|
||||
QNODE *oldest;
|
||||
|
||||
if (queue_isempty(q))
|
||||
return NULL;
|
||||
|
||||
oldest = q->head;
|
||||
q->head = oldest->next;
|
||||
return oldest;
|
||||
}
|
||||
|
||||
/*
|
||||
* Peek into the queue and return pointer to first (oldest) entry.
|
||||
* The queue is not modified
|
||||
*
|
||||
* Parameters:
|
||||
* q Pointer to queue structure
|
||||
*
|
||||
* Return Value:
|
||||
* Node at head of queue - NULL if queue is empty
|
||||
*/
|
||||
QNODE *queue_peek(QUEUE *q)
|
||||
{
|
||||
return q->head;
|
||||
}
|
||||
|
||||
/*
|
||||
* Move entire contents of one queue to the other
|
||||
*
|
||||
* Parameters:
|
||||
* src Pointer to source queue
|
||||
* dst Pointer to destination queue
|
||||
*/
|
||||
void queue_move(QUEUE *dst, QUEUE *src)
|
||||
{
|
||||
if (queue_isempty(src))
|
||||
return;
|
||||
|
||||
if (queue_isempty(dst))
|
||||
dst->head = src->head;
|
||||
else
|
||||
dst->tail->next = src->head;
|
||||
|
||||
dst->tail = src->tail;
|
||||
src->head = NULL;
|
||||
return;
|
||||
}
|
||||
659
net/tftp.c
Normal file
659
net/tftp.c
Normal file
@@ -0,0 +1,659 @@
|
||||
/*
|
||||
* File: tftp.c
|
||||
* Purpose: Trivial File Transfer Protocol driver for reading a file
|
||||
* from a remote host.
|
||||
*
|
||||
* Notes: See RFC 1350
|
||||
*
|
||||
* Modifications:
|
||||
*
|
||||
*/
|
||||
|
||||
#include "bas_types.h"
|
||||
#include "bas_printf.h"
|
||||
#include "bas_string.h"
|
||||
#include "net.h"
|
||||
#include "net_timer.h"
|
||||
|
||||
#define TIMER_NETWORK 3
|
||||
|
||||
/* The one and only TFTP connection */
|
||||
static TFTP_Connection tcxn;
|
||||
|
||||
/* Progress Indicators */
|
||||
static char hash[] = {'-','\\','|','/'};
|
||||
static int ihash = 0;
|
||||
|
||||
static int tftp_rwrq(void)
|
||||
{
|
||||
NBUF *pNbuf;
|
||||
RWRQ *rwrq;
|
||||
int i, j, result;
|
||||
|
||||
pNbuf = nbuf_alloc();
|
||||
if (pNbuf == NULL)
|
||||
{
|
||||
xprintf("TFTP: tftp_rwrq() couldn't allocate Tx buffer\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
rwrq = (RWRQ *)&pNbuf->data[TFTP_HDR_OFFSET];
|
||||
|
||||
/* Indicate a R/WRQ */
|
||||
rwrq->opcode = tcxn.dir;
|
||||
|
||||
/* Copy in filename */
|
||||
strcpy(&rwrq->filename_mode[0], tcxn.file);
|
||||
i = strlen(tcxn.file) + 1;
|
||||
|
||||
/* Indicate transfer type */
|
||||
strcpy (&rwrq->filename_mode[i], OCTET);
|
||||
|
||||
for (j = 0; j < 3; ++j)
|
||||
{
|
||||
pNbuf->length = (uint16_t)(i + strlen(OCTET) + 1 + 2);
|
||||
result = udp_send(tcxn.nif,
|
||||
tcxn.server_ip,
|
||||
tcxn.my_port,
|
||||
tcxn.server_port,
|
||||
pNbuf);
|
||||
if (result == 1)
|
||||
break;
|
||||
}
|
||||
|
||||
if (result == 0)
|
||||
nbuf_free(pNbuf);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static int tftp_ack(uint16_t blocknum)
|
||||
{
|
||||
ACK *ack;
|
||||
NBUF *pNbuf;
|
||||
int i, result;
|
||||
|
||||
pNbuf = nbuf_alloc();
|
||||
if (pNbuf == NULL)
|
||||
{
|
||||
xprintf("TFTP: tftp_ack() couldn't allocate Tx buffer\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
ack = (ACK *)&pNbuf->data[TFTP_HDR_OFFSET];
|
||||
ack->opcode = TFTP_ACK;
|
||||
ack->blocknum = blocknum;
|
||||
|
||||
for (i = 0; i < 3; ++i)
|
||||
{
|
||||
pNbuf->length = 4;
|
||||
result = udp_send(tcxn.nif,
|
||||
tcxn.server_ip,
|
||||
tcxn.my_port,
|
||||
tcxn.server_port,
|
||||
pNbuf);
|
||||
if (result == 1)
|
||||
break;
|
||||
}
|
||||
|
||||
if (result == 0)
|
||||
nbuf_free(pNbuf);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static int tftp_error(uint16_t error_code, uint16_t server_port)
|
||||
{
|
||||
ERROR *err;
|
||||
NBUF *pNbuf;
|
||||
int i, result;
|
||||
|
||||
pNbuf = nbuf_alloc();
|
||||
if (pNbuf == NULL)
|
||||
{
|
||||
xprintf("TFTP: tftp_error() couldn't allocate Tx buffer\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
err = (ERROR *)&pNbuf->data[TFTP_HDR_OFFSET];
|
||||
err->opcode = TFTP_ERROR;
|
||||
err->code = error_code;
|
||||
err->msg[0] = '\0';
|
||||
|
||||
for (i = 0; i < 3; ++i)
|
||||
{
|
||||
pNbuf->length = 5;
|
||||
result = udp_send(tcxn.nif,
|
||||
tcxn.server_ip,
|
||||
tcxn.my_port,
|
||||
server_port,
|
||||
pNbuf);
|
||||
if (result == 1)
|
||||
break;
|
||||
}
|
||||
|
||||
if (result == 0)
|
||||
nbuf_free(pNbuf);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
void tftp_handler(NIF *nif, NBUF *pNbuf)
|
||||
{
|
||||
union TFTPpacket *tftp_pkt;
|
||||
udp_frame_hdr *udpframe;
|
||||
static int cnt;
|
||||
(void) nif;
|
||||
|
||||
tftp_pkt = (union TFTPpacket *)&pNbuf->data[pNbuf->offset];
|
||||
udpframe = (udp_frame_hdr *)&pNbuf->data[pNbuf->offset - UDP_HDR_SIZE];
|
||||
|
||||
switch (tftp_pkt->generic.opcode)
|
||||
{
|
||||
case TFTP_DATA:
|
||||
/* Is this the expected block number? */
|
||||
if (tftp_pkt->data.blocknum == tcxn.exp_blocknum)
|
||||
{
|
||||
/* Is this is the first data block received? */
|
||||
if (tftp_pkt->data.blocknum == 1)
|
||||
{
|
||||
/* Save the server's transfer ID */
|
||||
tcxn.server_port = UDP_SOURCE(udpframe);
|
||||
|
||||
/* Mark the connection as open */
|
||||
tcxn.open = true;
|
||||
|
||||
/* Start progress indicator */
|
||||
xprintf("%c", hash[0]);
|
||||
cnt = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the server's transfer ID */
|
||||
if (tcxn.server_port != UDP_SOURCE(udpframe))
|
||||
{
|
||||
xprintf("TFTP: Invalid server port: %d\n", \
|
||||
UDP_SOURCE(udpframe));
|
||||
|
||||
/* Send ERROR packet to source */
|
||||
tftp_error(TFTP_ERR_TID, UDP_SOURCE(udpframe));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Add the buffer to the TFTP queue */
|
||||
queue_add(&tcxn.queue, (QNODE *)pNbuf);
|
||||
|
||||
/* Update number of the next block expected */
|
||||
tcxn.exp_blocknum++;
|
||||
|
||||
/* Increment number of bytes received counter */
|
||||
tcxn.bytes_recv += (pNbuf->length - 4);
|
||||
|
||||
/* Update progress indicator */
|
||||
if (++cnt == 50)
|
||||
{
|
||||
ihash = (ihash + 1) % 4;
|
||||
xprintf("\r");
|
||||
xprintf("%c", hash[ihash]);
|
||||
cnt = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (tftp_pkt->data.blocknum < tcxn.exp_blocknum)
|
||||
{
|
||||
/* Re-ACK this packet */
|
||||
tftp_ack(tftp_pkt->data.blocknum);
|
||||
}
|
||||
|
||||
/* This is NOT the block expected */
|
||||
xprintf("Exp: %d, ", tcxn.exp_blocknum);
|
||||
xprintf("Rcv: %d\n", tftp_pkt->data.blocknum);
|
||||
|
||||
/* Free the network buffer */
|
||||
nbuf_free(pNbuf);
|
||||
}
|
||||
break;
|
||||
case TFTP_ERROR:
|
||||
xprintf("\nTFTP Error #%d: ",tftp_pkt->error.code);
|
||||
xprintf("%s\n",tftp_pkt->error.msg);
|
||||
tcxn.error = true;
|
||||
/* Free the network buffer */
|
||||
nbuf_free(pNbuf);
|
||||
break;
|
||||
case TFTP_ACK:
|
||||
if (tftp_pkt->ack.blocknum == tcxn.exp_blocknum)
|
||||
{
|
||||
if (tftp_pkt->data.blocknum == 0)
|
||||
{ /* This is the first ACK received */
|
||||
|
||||
/* Save the server's transfer ID */
|
||||
tcxn.server_port = UDP_SOURCE(udpframe);
|
||||
|
||||
/* Mark the connection as open */
|
||||
tcxn.open = true;
|
||||
}
|
||||
else
|
||||
{ /* Check the server's transfer ID */
|
||||
if (tcxn.server_port != UDP_SOURCE(udpframe))
|
||||
{
|
||||
xprintf("TFTP: Invalid server port: %d\n", \
|
||||
UDP_SOURCE(udpframe));
|
||||
|
||||
/*Send ERROR packet to source */
|
||||
tftp_error(TFTP_ERR_TID, UDP_SOURCE(udpframe));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
tcxn.exp_blocknum++;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* This is NOT the block number expected */
|
||||
xprintf("ACK Exp: %d, ", tcxn.exp_blocknum);
|
||||
xprintf("ACK Rcv: %d\n", tftp_pkt->ack.blocknum);
|
||||
}
|
||||
|
||||
/* Free the network buffer */
|
||||
nbuf_free(pNbuf);
|
||||
break;
|
||||
case TFTP_RRQ:
|
||||
case TFTP_WRQ:
|
||||
default:
|
||||
/* Free the network buffer */
|
||||
nbuf_free(pNbuf);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void tftp_end(int success)
|
||||
{
|
||||
/*
|
||||
* Following a successful transfer the caller should pass in
|
||||
* true, there should have been no ERROR packets received, and
|
||||
* the connection should have been marked as closed by the
|
||||
* tftp_in_char() routine.
|
||||
*/
|
||||
if (success && !tcxn.error && (tcxn.open == false))
|
||||
{
|
||||
xprintf("\bTFTP transfer completed \n");
|
||||
xprintf("Read %d bytes (%d blocks)\n", \
|
||||
tcxn.bytes_recv, tcxn.exp_blocknum - 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Send error packet to stifle the server */
|
||||
tftp_error(TFTP_ERR_ILL, tcxn.server_port);
|
||||
|
||||
xprintf("\bErrors in TFTP transfer.\n");
|
||||
xprintf("Read %d bytes (%d blocks)\n", \
|
||||
tcxn.bytes_recv, tcxn.exp_blocknum - 1);
|
||||
}
|
||||
|
||||
/* Free up any buffers left in the queue */
|
||||
while (!queue_isempty(&tcxn.queue))
|
||||
nbuf_free((NBUF *)queue_remove(&tcxn.queue));
|
||||
|
||||
/* Free the UDP port */
|
||||
udp_free_port(tcxn.my_port);
|
||||
}
|
||||
|
||||
int tftp_write(NIF *nif, char *fn, IP_ADDR_P server, uint32_t begin, uint32_t end)
|
||||
{
|
||||
DATA *data;
|
||||
NBUF *pNbuf;
|
||||
|
||||
uint32_t i, retries, bytes_to_send;
|
||||
uint16_t blocknum, this_size;
|
||||
uint8_t success, *current;
|
||||
int result;
|
||||
|
||||
if (fn == 0 || server == 0 || end < begin)
|
||||
return 0;
|
||||
|
||||
/* Setup initial connection status */
|
||||
tcxn.nif = nif;
|
||||
tcxn.file = fn;
|
||||
tcxn.server_ip[0] = server[0];
|
||||
tcxn.server_ip[1] = server[1];
|
||||
tcxn.server_ip[2] = server[2];
|
||||
tcxn.server_ip[3] = server[3];
|
||||
tcxn.server_port = UDP_PORT_TFTP;
|
||||
tcxn.exp_blocknum = 0;
|
||||
tcxn.dir = TFTP_WRQ;
|
||||
tcxn.open = false;
|
||||
tcxn.bytes_sent = 0;
|
||||
tcxn.error = false;
|
||||
|
||||
/* Use Mac address as pseudo-random port */
|
||||
udp_prime_port((uint16_t)((nif->hwa[4] << 8) | nif->hwa[5]));
|
||||
tcxn.my_port = udp_obtain_free_port();
|
||||
udp_bind_port(tcxn.my_port,&tftp_handler);
|
||||
|
||||
retries = 4;
|
||||
success = false;
|
||||
|
||||
while (--retries)
|
||||
{
|
||||
/* Make the TFTP Read/Write Request */
|
||||
if (!tftp_rwrq())
|
||||
{
|
||||
xprintf("Error: Couldn't send TFTP Write Request\n");
|
||||
udp_free_port(tcxn.my_port);
|
||||
return false;
|
||||
}
|
||||
|
||||
timer_set_secs(TIMER_NETWORK, TFTP_TIMEOUT);
|
||||
while (timer_get_reference(TIMER_NETWORK))
|
||||
{
|
||||
/* Has the server responded */
|
||||
if (tcxn.open)
|
||||
{
|
||||
success = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* If the connection is open, we are done here */
|
||||
if (success || tcxn.error)
|
||||
break;
|
||||
}
|
||||
if (!retries)
|
||||
{
|
||||
xprintf("TFTP could not make connection to server.\n");
|
||||
udp_free_port(tcxn.my_port);
|
||||
return false;
|
||||
}
|
||||
else if (tcxn.error)
|
||||
{
|
||||
xprintf("\bErrors in TFTP upload.\n");
|
||||
udp_free_port(tcxn.my_port);
|
||||
return false;
|
||||
}
|
||||
|
||||
bytes_to_send = end - begin;
|
||||
current = (uint8_t *)begin;
|
||||
blocknum = 1;
|
||||
retries = 4;
|
||||
success = false;
|
||||
|
||||
while (--retries)
|
||||
{
|
||||
pNbuf = nbuf_alloc();
|
||||
if (pNbuf == NULL)
|
||||
{
|
||||
xprintf("TFTP: tftp_write() couldn't allocate Tx buffer\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Build the packet */
|
||||
data = (DATA *)&pNbuf->data[TFTP_HDR_OFFSET];
|
||||
data->blocknum = blocknum;
|
||||
data->opcode = TFTP_DATA;
|
||||
|
||||
this_size = (bytes_to_send > TFTP_PKTSIZE) ? \
|
||||
TFTP_PKTSIZE : (uint16_t)bytes_to_send;
|
||||
|
||||
for (i = 0; i < this_size; i++)
|
||||
{
|
||||
data->data[i] = current[i];
|
||||
}
|
||||
|
||||
/* Set the packet length */
|
||||
pNbuf->length = (uint16_t)(4 + this_size);
|
||||
|
||||
/* Attempt to send the packet */
|
||||
for (i = 0; i < 3; ++i)
|
||||
{
|
||||
result = udp_send(tcxn.nif,
|
||||
tcxn.server_ip,
|
||||
tcxn.my_port,
|
||||
tcxn.server_port,
|
||||
pNbuf);
|
||||
|
||||
if (result == 1)
|
||||
break;
|
||||
}
|
||||
|
||||
if (result == 0)
|
||||
nbuf_free(pNbuf);
|
||||
|
||||
timer_set_secs(TIMER_NETWORK, TFTP_TIMEOUT);
|
||||
while (timer_get_reference(TIMER_NETWORK))
|
||||
{
|
||||
/* Has the server responded */
|
||||
if ((tcxn.exp_blocknum - 1) == blocknum)
|
||||
{
|
||||
success = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* TFTP Write Compeleted successfully */
|
||||
if (success && (this_size < TFTP_PKTSIZE))
|
||||
{
|
||||
tcxn.bytes_sent += this_size;
|
||||
break;
|
||||
}
|
||||
|
||||
if (tcxn.error)
|
||||
break;
|
||||
|
||||
/* If an ACK was received, keep sending packets */
|
||||
if (success)
|
||||
{
|
||||
tcxn.bytes_sent += TFTP_PKTSIZE;
|
||||
bytes_to_send -= TFTP_PKTSIZE;
|
||||
current += TFTP_PKTSIZE;
|
||||
blocknum++;
|
||||
retries = 4;
|
||||
success = false;
|
||||
}
|
||||
}
|
||||
if (tcxn.error)
|
||||
{
|
||||
xprintf("TFTP lost connection to server.\n");
|
||||
xprintf("Sent %d bytes (%d blocks)\n", \
|
||||
tcxn.bytes_sent, tcxn.exp_blocknum - 1);
|
||||
udp_free_port(tcxn.my_port);
|
||||
return false;
|
||||
}
|
||||
else
|
||||
{
|
||||
xprintf("\bTFTP upload successful\n");
|
||||
xprintf("Sent %d bytes (%d blocks)\n", \
|
||||
tcxn.bytes_sent, tcxn.exp_blocknum - 1);
|
||||
udp_free_port(tcxn.my_port);
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
int tftp_read(NIF *nif, char *fn, IP_ADDR_P server)
|
||||
{
|
||||
uint32_t retries;
|
||||
|
||||
if (fn == 0 || server == 0)
|
||||
return 0;
|
||||
|
||||
/* Setup initial connection status */
|
||||
tcxn.nif = nif;
|
||||
tcxn.file = fn;
|
||||
tcxn.server_ip[0] = server[0];
|
||||
tcxn.server_ip[1] = server[1];
|
||||
tcxn.server_ip[2] = server[2];
|
||||
tcxn.server_ip[3] = server[3];
|
||||
tcxn.server_port = UDP_PORT_TFTP;
|
||||
tcxn.exp_blocknum = 1;
|
||||
tcxn.last_ack = 0;
|
||||
tcxn.dir = TFTP_RRQ;
|
||||
tcxn.open = false;
|
||||
tcxn.bytes_recv = 0;
|
||||
tcxn.rem_bytes = 0;
|
||||
tcxn.next_char = NULL;
|
||||
tcxn.error = false;
|
||||
queue_init(&tcxn.queue);
|
||||
|
||||
/* Use Mac address as pseudo-random port */
|
||||
udp_prime_port((uint16_t)((nif->hwa[4] << 8) | nif->hwa[5]));
|
||||
tcxn.my_port = udp_obtain_free_port();
|
||||
udp_bind_port(tcxn.my_port,&tftp_handler);
|
||||
|
||||
retries = 4;
|
||||
|
||||
while (--retries)
|
||||
{
|
||||
/* Make the TFTP Read/Write Request */
|
||||
if (!tftp_rwrq())
|
||||
{
|
||||
xprintf("Error: Couldn't send TFTP Read Request\n");
|
||||
udp_free_port(tcxn.my_port);
|
||||
return false;
|
||||
}
|
||||
|
||||
timer_set_secs(TIMER_NETWORK, TFTP_TIMEOUT);
|
||||
while (timer_get_reference(TIMER_NETWORK))
|
||||
{
|
||||
/* Has the server responded */
|
||||
if (tcxn.open == true)
|
||||
break;
|
||||
}
|
||||
|
||||
/* If the connection is open, we are done here */
|
||||
if ((tcxn.open == true) || tcxn.error)
|
||||
break;
|
||||
}
|
||||
if (!retries)
|
||||
{
|
||||
xprintf("TFTP could not make connection to server.\n");
|
||||
udp_free_port(tcxn.my_port);
|
||||
return false;
|
||||
}
|
||||
else if (tcxn.error)
|
||||
{
|
||||
xprintf("\bErrors in TFTP download.\n");
|
||||
udp_free_port(tcxn.my_port);
|
||||
return false;
|
||||
}
|
||||
else
|
||||
return true;
|
||||
}
|
||||
|
||||
int tftp_in_char(void)
|
||||
{
|
||||
union TFTPpacket *tftp_pkt;
|
||||
int retval;
|
||||
NBUF *pNbuf;
|
||||
|
||||
if (tcxn.next_char != NULL)
|
||||
{
|
||||
/*
|
||||
* A buffer is already being worked on - grab next
|
||||
* byte from it
|
||||
*/
|
||||
retval = *tcxn.next_char++;
|
||||
if (--tcxn.rem_bytes <= 0)
|
||||
{
|
||||
/* The buffer is depleted; add it back to the free queue */
|
||||
pNbuf = (NBUF *)queue_remove(&tcxn.queue);
|
||||
|
||||
nbuf_free(pNbuf);
|
||||
tcxn.next_char = NULL;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Is the connection still open? */
|
||||
if (tcxn.open == false)
|
||||
{
|
||||
/*
|
||||
* The last packet has been received and the last data
|
||||
* buffer has been exhausted
|
||||
*/
|
||||
retval = -1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get pointer to the next buffer */
|
||||
pNbuf = (NBUF *)queue_peek(&tcxn.queue);
|
||||
|
||||
if (pNbuf == NULL)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* There was no buffer in the queue */
|
||||
for (i = 0; i < 3; ++i)
|
||||
{
|
||||
timer_set_secs(TIMER_NETWORK, 1);
|
||||
while (timer_get_reference(TIMER_NETWORK))
|
||||
{
|
||||
/* Has the server sent another DATA packet? */
|
||||
if (!queue_isempty(&tcxn.queue))
|
||||
{
|
||||
pNbuf = (NBUF *)queue_peek(&tcxn.queue);
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (pNbuf != NULL)
|
||||
break;
|
||||
|
||||
/* Ack the last packet again */
|
||||
xprintf("Re-acking %d\n",tcxn.last_ack - 1);
|
||||
retval = tftp_ack(tcxn.last_ack - 1);
|
||||
}
|
||||
}
|
||||
if (pNbuf == NULL)
|
||||
{
|
||||
/* The server didn't respond with the expected packet */
|
||||
tcxn.open = false;
|
||||
tcxn.error = true;
|
||||
xprintf("TFTP lost connection to server.\n");
|
||||
retval = -1;
|
||||
}
|
||||
else
|
||||
{
|
||||
tftp_pkt = (union TFTPpacket *)&pNbuf->data[pNbuf->offset];
|
||||
|
||||
/* Subtract the TFTP header from the data length */
|
||||
tcxn.rem_bytes = pNbuf->length - 4;
|
||||
|
||||
/* Point to first data byte in the packet */
|
||||
tcxn.next_char = tftp_pkt->data.data;
|
||||
|
||||
/* Save off the block number */
|
||||
tcxn.last_ack = tftp_pkt->data.blocknum;
|
||||
|
||||
/* Check to see if this is the last packet of the transfer */
|
||||
if (tcxn.rem_bytes < TFTP_PKTSIZE)
|
||||
tcxn.open = false;
|
||||
|
||||
/* Check for empty termination packet */
|
||||
if (tcxn.rem_bytes == 0)
|
||||
{
|
||||
pNbuf = (NBUF *)queue_remove(&tcxn.queue);
|
||||
nbuf_free(pNbuf);
|
||||
tcxn.next_char = NULL;
|
||||
retval = tftp_ack(tcxn.last_ack++);
|
||||
retval = -1;
|
||||
}
|
||||
else
|
||||
{
|
||||
retval = tftp_ack(tcxn.last_ack++);
|
||||
retval = *tcxn.next_char++;
|
||||
|
||||
/* Check for a single byte packet */
|
||||
if (--tcxn.rem_bytes == 0)
|
||||
{
|
||||
/* The buffer is depleted; add it back to the free queue */
|
||||
pNbuf = (NBUF *)queue_remove(&tcxn.queue);
|
||||
nbuf_free(pNbuf);
|
||||
tcxn.next_char = NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
184
net/udp.c
Normal file
184
net/udp.c
Normal file
@@ -0,0 +1,184 @@
|
||||
/*
|
||||
* File: udp.c
|
||||
* Purpose: User Datagram Protocol driver
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
* Modifications:
|
||||
*
|
||||
*/
|
||||
#include "bas_types.h"
|
||||
#include "bas_printf.h"
|
||||
#include "net.h"
|
||||
#include <stddef.h>
|
||||
|
||||
//#define DBG_UDP
|
||||
#if defined(DBG_UDP)
|
||||
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
|
||||
#else
|
||||
#define dbg(format, arg...) do { ; } while (0)
|
||||
#endif /* DBG_UDP */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t port;
|
||||
void (*handler)(NIF *, NBUF *);
|
||||
} UDP_BOUND_PORT;
|
||||
|
||||
#define UDP_MAX_PORTS (5) /* plenty for this implementation */
|
||||
|
||||
|
||||
static UDP_BOUND_PORT udp_port_table[UDP_MAX_PORTS];
|
||||
|
||||
static uint16_t udp_port;
|
||||
|
||||
void udp_init(void)
|
||||
{
|
||||
int index;
|
||||
|
||||
for (index = 0; index < UDP_MAX_PORTS; ++index)
|
||||
{
|
||||
udp_port_table[index].port = 0;
|
||||
udp_port_table[index].handler = 0;
|
||||
}
|
||||
|
||||
udp_port = DEFAULT_UDP_PORT; /* next free port */
|
||||
}
|
||||
|
||||
void udp_prime_port(uint16_t init_port)
|
||||
{
|
||||
udp_port = init_port;
|
||||
}
|
||||
|
||||
void udp_bind_port(uint16_t port, void (*handler)(NIF *, NBUF *))
|
||||
{
|
||||
int index;
|
||||
|
||||
for (index = 0; index < UDP_MAX_PORTS; ++index)
|
||||
{
|
||||
if (udp_port_table[index].port == 0)
|
||||
{
|
||||
udp_port_table[index].port = port;
|
||||
udp_port_table[index].handler = handler;
|
||||
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void udp_free_port(uint16_t port)
|
||||
{
|
||||
int index;
|
||||
|
||||
for (index = 0; index < UDP_MAX_PORTS; ++index)
|
||||
{
|
||||
if (udp_port_table[index].port == port)
|
||||
{
|
||||
udp_port_table[index].port = 0;
|
||||
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void *udp_port_handler(uint16_t port)
|
||||
{
|
||||
int index;
|
||||
|
||||
for (index = 0; index < UDP_MAX_PORTS; ++index)
|
||||
{
|
||||
if (udp_port_table[index].port == port)
|
||||
{
|
||||
return (void *) udp_port_table[index].handler;
|
||||
}
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
uint16_t udp_obtain_free_port(void)
|
||||
{
|
||||
uint16_t port;
|
||||
|
||||
port = udp_port;
|
||||
if (--udp_port <= 255)
|
||||
udp_port = DEFAULT_UDP_PORT;
|
||||
|
||||
return port;
|
||||
}
|
||||
|
||||
int udp_send(NIF *nif, uint8_t *dest, int sport, int dport, NBUF *pNbuf)
|
||||
{
|
||||
uint8_t *myip;
|
||||
|
||||
if (nif == NULL)
|
||||
{
|
||||
dbg("nif is NULL\r\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function takes data, creates a UDP frame from it and
|
||||
* passes it onto the IP layer
|
||||
*/
|
||||
udp_frame_hdr *udpframe;
|
||||
|
||||
udpframe = (udp_frame_hdr *) &pNbuf->data[UDP_HDR_OFFSET];
|
||||
|
||||
/* Set UDP source port */
|
||||
udpframe->src_port = (uint16_t) sport;
|
||||
|
||||
/* Set UDP destination port */
|
||||
udpframe->dest_port = (uint16_t) dport;
|
||||
|
||||
/* Set length */
|
||||
udpframe->length = (uint16_t) (pNbuf->length + UDP_HDR_SIZE);
|
||||
|
||||
/* No checksum calcualation needed */
|
||||
udpframe->chksum = (uint16_t) 0;
|
||||
|
||||
/* Add the length of the UDP packet to the total length of the packet */
|
||||
pNbuf->length += 8;
|
||||
|
||||
myip = ip_get_myip(nif_get_protocol_info(nif, ETH_FRM_IP));
|
||||
|
||||
dbg("sent UDP request to %d.%d.%d.%d from %d.%d.%d.%d\r\n",
|
||||
dest[0], dest[1], dest[2], dest[3],
|
||||
myip[0], myip[1], myip[2], myip[3]);
|
||||
|
||||
return (ip_send(nif, dest, myip, IP_PROTO_UDP, pNbuf));
|
||||
|
||||
}
|
||||
|
||||
void udp_handler(NIF *nif, NBUF *pNbuf)
|
||||
{
|
||||
/*
|
||||
* This function handles incoming UDP packets
|
||||
*/
|
||||
udp_frame_hdr *udpframe;
|
||||
void (*handler)(NIF *, NBUF *);
|
||||
|
||||
udpframe = (udp_frame_hdr *) &pNbuf->data[pNbuf->offset];
|
||||
|
||||
dbg("packet received\r\n",);
|
||||
|
||||
/*
|
||||
* Adjust the length and valid data offset of the packet we are
|
||||
* passing on
|
||||
*/
|
||||
pNbuf->length -= UDP_HDR_SIZE;
|
||||
pNbuf->offset += UDP_HDR_SIZE;
|
||||
|
||||
/*
|
||||
* Traverse the list of bound ports to see if there is a higher
|
||||
* level protocol to pass the packet on to
|
||||
*/
|
||||
if ((handler = (void(*)(NIF*, NBUF*)) udp_port_handler(UDP_DEST(udpframe))) != NULL)
|
||||
handler(nif, pNbuf);
|
||||
else
|
||||
{
|
||||
dbg("received UDP packet for non-supported port\n");
|
||||
nbuf_free(pNbuf);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
380
nutil/s19header.c
Normal file
380
nutil/s19header.c
Normal file
@@ -0,0 +1,380 @@
|
||||
/*
|
||||
* s19header.c
|
||||
*
|
||||
* Created on: 17.12.2012
|
||||
* Author: mfro
|
||||
* The ACP Firebee project
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Copyright 2012 M. Froeschle
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "s19reader.h"
|
||||
|
||||
/*
|
||||
* Yes, I know. The following doesn't really look like code should look like...
|
||||
*
|
||||
* I did try to map structures over the S-records with (packed) which didn't work reliably due to
|
||||
* gcc _not_ packing them appropiate and finally ended up with this. Not nice, put paid (and working).
|
||||
*
|
||||
*/
|
||||
#define SREC_TYPE(a) (a)[0] /* type of record */
|
||||
#define SREC_COUNT(a) (a)[1] /* length of valid bytes to follow */
|
||||
#define SREC_ADDR16(a) (256 * (a)[2] + (a)[3]) /* 2 byte address field */
|
||||
#define SREC_ADDR24(a) (0x10000 * (a)[2] + 0x100 * \
|
||||
(a)[3] + (a)[4]) /* 3 byte address field */
|
||||
#define SREC_ADDR32(a) (0x1000000 * a[2] + 0x10000 * \
|
||||
a[3] + 0x100 * (a)[4] + (a)[5]) /* 4 byte address field */
|
||||
#define SREC_DATA16(a) ((uint8_t *)&((a)[4])) /* address of first byte of data in a record */
|
||||
#define SREC_DATA24(a) ((uint8_t *)&((a)[5])) /* address of first data byte in 24 bit record */
|
||||
#define SREC_DATA32(a) ((uint8_t *)&((a)[6])) /* adress of first byte of a record with 32 bit address field */
|
||||
#define SREC_DATA16_SIZE(a) (SREC_COUNT((a)) - 3) /* length of the data[] array without the checksum field */
|
||||
#define SREC_DATA24_SIZE(a) (SREC_COUNT((a)) - 4) /* length of the data[] array without the checksum field */
|
||||
#define SREC_DATA32_SIZE(a) (SREC_COUNT((a)) - 5) /* length of the data[] array without the checksum field */
|
||||
#define SREC_CHECKSUM(a) (a)[SREC_COUNT(a) + 2 - 1] /* record's checksum (two's complement of the sum of all bytes) */
|
||||
|
||||
#define SREC_MODULENAME(a) &((a)[4]) /* module name in an S0 record */
|
||||
#define SREC_MODULENAME_LENGTH 20
|
||||
#define SREC_VERSION(a) &((a)[24]) /* version info in an S0 record */
|
||||
#define SREC_VERSION_LENGTH 2
|
||||
#define SREC_REVISION(a) &((a)[26]) /* revision info in an S0 record */
|
||||
#define SREC_REVISIION_LENGTH 2
|
||||
#define SREC_DESCRIPTION(a) &((a)[28]) /* description field in an S0 record */
|
||||
#define SREC_DESCRIPTION_LENGTH 36
|
||||
|
||||
/*
|
||||
* convert a single hex character into byte
|
||||
*/
|
||||
static uint8_t nibble_to_byte(uint8_t nibble)
|
||||
{
|
||||
if ((nibble >= '0') && (nibble <= '9'))
|
||||
return nibble - '0';
|
||||
else if ((nibble >= 'A' && nibble <= 'F'))
|
||||
return 10 + nibble - 'A';
|
||||
else if ((nibble >= 'a' && nibble <= 'f'))
|
||||
return 10 + nibble - 'a';
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* convert two hex characters into byte
|
||||
*/
|
||||
static uint8_t hex_to_byte(uint8_t hex[2])
|
||||
{
|
||||
return 16 * (nibble_to_byte(hex[0])) + (nibble_to_byte(hex[1]));
|
||||
}
|
||||
|
||||
#ifdef _NOT_USED_
|
||||
/*
|
||||
* convert four hex characters into a 16 bit word
|
||||
*/
|
||||
static uint16_t hex_to_word(uint8_t hex[4])
|
||||
{
|
||||
return 256 * hex_to_byte(&hex[0]) + hex_to_byte(&hex[2]);
|
||||
}
|
||||
|
||||
/*
|
||||
* convert eight hex characters into a 32 bit word
|
||||
*/
|
||||
static uint32_t hex_to_long(uint8_t hex[8])
|
||||
{
|
||||
return 65536 * hex_to_word(&hex[0]) + hex_to_word(&hex[4]);
|
||||
}
|
||||
#endif /* _NOT_USED_ */
|
||||
|
||||
/*
|
||||
* compute the record checksum
|
||||
*
|
||||
* it consists of the one's complement of the byte sum of the data from the count field until the end
|
||||
*/
|
||||
static uint8_t checksum(uint8_t arr[])
|
||||
{
|
||||
int i;
|
||||
uint8_t checksum = SREC_COUNT(arr);
|
||||
|
||||
for (i = 0; i < SREC_COUNT(arr) - 1; i++)
|
||||
{
|
||||
checksum += arr[i + 2];
|
||||
}
|
||||
return ~checksum;
|
||||
}
|
||||
|
||||
void print_record(uint8_t *arr)
|
||||
{
|
||||
switch (SREC_TYPE(arr))
|
||||
{
|
||||
case 0:
|
||||
{
|
||||
printf("type 0x%x ", SREC_TYPE(arr));
|
||||
printf("count 0x%x ", SREC_COUNT(arr));
|
||||
printf("addr 0x%x ", SREC_ADDR16(arr));
|
||||
printf("module %11.11s ", SREC_DATA16(arr));
|
||||
printf("chk 0x%x 0x%x\r\n", SREC_CHECKSUM(arr), checksum(arr));
|
||||
}
|
||||
break;
|
||||
|
||||
case 3:
|
||||
case 7:
|
||||
{
|
||||
printf("type 0x%x ", SREC_TYPE(arr));
|
||||
printf("count 0x%x ", SREC_COUNT(arr));
|
||||
printf("addr 0x%x ", SREC_ADDR32(arr));
|
||||
printf("data %02x,%02x,%02x,%02x,... ",
|
||||
SREC_DATA32(arr)[0], SREC_DATA32(arr)[1], SREC_DATA32(arr)[3], SREC_DATA32(arr)[4]);
|
||||
printf("chk 0x%x 0x%x\r\n", SREC_CHECKSUM(arr), checksum(arr));
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
printf("unsupported report type %d in print_record\r\n", arr[0]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* convert an S-record line into its corresponding byte vector (ASCII->binary)
|
||||
*/
|
||||
static void line_to_vector(uint8_t *buff, uint8_t *vector)
|
||||
{
|
||||
int i;
|
||||
int length;
|
||||
uint8_t *vp = vector;
|
||||
|
||||
length = hex_to_byte(buff + 2);
|
||||
|
||||
buff++;
|
||||
*vp++ = nibble_to_byte(*buff); /* record type. Only one single nibble */
|
||||
buff++;
|
||||
|
||||
for (i = 0; i <= length; i++)
|
||||
{
|
||||
*vp++ = hex_to_byte(buff);
|
||||
buff += 2;
|
||||
}
|
||||
}
|
||||
|
||||
static void vector_to_line(uint8_t *vector, uint8_t *buff)
|
||||
{
|
||||
sprintf(buff, "S");
|
||||
}
|
||||
|
||||
/*
|
||||
* read and parse a Motorola S-record file and copy contents to dst. The theory of operation is to read and parse the S-record file
|
||||
* and to use the supplied callback routine to copy the buffer to the destination once the S-record line is converted.
|
||||
* The memcpy callback can be anything (as long as it conforms parameter-wise) - a basically empty function to just let
|
||||
* read_srecords validate the file, a standard memcpy() to copy file contents to destination RAM or a more sophisticated
|
||||
* routine that does write/erase flash
|
||||
*
|
||||
* FIXME: Currently only records that the gcc toolchain emits are supported.
|
||||
*
|
||||
* Parameters:
|
||||
* IN
|
||||
* filename - the filename that contains the S-records
|
||||
* callback - the memcpy() routine discussed above
|
||||
* OUT
|
||||
* start_address - the execution address of the code as read from the file. Can be used to jump into and execute it
|
||||
* actual_length - the overall length of the binary code read from the file
|
||||
* returns
|
||||
* OK or an err_t error code if anything failed
|
||||
*/
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
int fres;
|
||||
int set;
|
||||
char *filename = NULL;
|
||||
FILE *file;
|
||||
int ret = OK;
|
||||
int i;
|
||||
|
||||
|
||||
for (i = 1; i < argc; i++)
|
||||
{
|
||||
if (argv[i][0] == '-')
|
||||
{
|
||||
/* option */
|
||||
if (strcmp(argv[i], "-s") == 0)
|
||||
{
|
||||
set = 1;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
filename = argv[i];
|
||||
}
|
||||
}
|
||||
|
||||
if (filename == NULL)
|
||||
{
|
||||
fprintf(stderr, "no filename given\n");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
if ((file = fopen(filename, "r")) != NULL)
|
||||
{
|
||||
uint8_t line[80];
|
||||
int lineno = 0;
|
||||
int data_records = 0;
|
||||
bool found_block_header = false;
|
||||
bool found_block_end = false;
|
||||
bool found_block_data = false;
|
||||
|
||||
while (ret == OK && (uint8_t *) fgets((char *) line, sizeof(line), file) != NULL)
|
||||
{
|
||||
lineno++;
|
||||
uint8_t vector[80];
|
||||
char str[255];
|
||||
int length;
|
||||
|
||||
|
||||
|
||||
line_to_vector(line, vector); /* vector now contains the decoded contents of line, from line[1] on */
|
||||
|
||||
if (line[0] == 'S')
|
||||
{
|
||||
char header[256];
|
||||
|
||||
if (SREC_CHECKSUM(vector) != checksum(vector))
|
||||
{
|
||||
printf("invalid checksum 0x%x (should be 0x%x) in line %d\r\n",
|
||||
SREC_CHECKSUM(vector), checksum(vector), lineno);
|
||||
ret = FAIL;
|
||||
}
|
||||
|
||||
switch (vector[0])
|
||||
{
|
||||
case 0: /* block header */
|
||||
found_block_header = true;
|
||||
if (found_block_data || found_block_end)
|
||||
{
|
||||
printf("S7 or S3 record found before S0: S-records corrupt?\r\n");
|
||||
ret = FAIL;
|
||||
}
|
||||
printf("address: 0x%04x\n", SREC_ADDR16(vector));
|
||||
printf("length of record: %d\n", SREC_COUNT(vector));
|
||||
length = SREC_DATA16_SIZE(vector) - (SREC_DATA16(vector) - vector);
|
||||
printf("length: %d\n", length);
|
||||
strncpy(str, SREC_DATA16(vector), length);
|
||||
str[length] = '\0';
|
||||
printf("Name: %s\n", str);
|
||||
printf("version: %d, revision %d\n",
|
||||
* (unsigned short *)((char *) SREC_DATA16(vector) + length),
|
||||
* (unsigned short *)((char *) SREC_DATA16(vector) + length + 1));
|
||||
print_record(vector);
|
||||
|
||||
break;
|
||||
|
||||
case 2: /* three byte address field data record */
|
||||
if (!found_block_header || found_block_end)
|
||||
{
|
||||
printf("S3 record found before S0 or after S7: S-records corrupt?\r\n");
|
||||
ret = FAIL;
|
||||
}
|
||||
// ret = callback((uint8_t *) SREC_ADDR24(vector), SREC_DATA24(vector), SREC_DATA24_SIZE(vector));
|
||||
data_records++;
|
||||
break;
|
||||
|
||||
case 3: /* four byte address field data record */
|
||||
if (!found_block_header || found_block_end)
|
||||
{
|
||||
printf("S3 record found before S0 or after S7: S-records corrupt?\r\n");
|
||||
ret = FAIL;
|
||||
}
|
||||
// ret = callback((uint8_t *) SREC_ADDR32(vector), SREC_DATA32(vector), SREC_DATA32_SIZE(vector));
|
||||
data_records++;
|
||||
break;
|
||||
|
||||
case 7: /* four byte address field end record */
|
||||
if (!found_block_header || found_block_end)
|
||||
{
|
||||
printf("S7 record found before S0 or after S7: S-records corrupt?\r\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
// printf("S7 record (end) found after %d valid data blocks\r\n", data_records);
|
||||
//*start_address = (void *) SREC_ADDR32(vector);
|
||||
}
|
||||
break;
|
||||
|
||||
case 8: /* three byte address field end record */
|
||||
if (!found_block_header || found_block_end)
|
||||
{
|
||||
printf("S8 record found before S0 or after S8: S-records corrupt?\r\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
// printf("S7 record (end) found after %d valid data blocks\r\n", data_records);
|
||||
//*start_address = (void *) SREC_ADDR24(vector);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
printf("unsupported record type (%d) found in line %d\r\n", vector[0], lineno);
|
||||
printf("offending line: \r\n");
|
||||
printf("%s\r\n", line);
|
||||
ret = FAIL;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
printf("illegal character ('%c') found on line %d: S-records corrupt?\r\n", line[0], lineno);
|
||||
ret = FAIL;
|
||||
break;
|
||||
}
|
||||
}
|
||||
fclose(file);
|
||||
}
|
||||
else
|
||||
{
|
||||
printf("could not open file %s\r\n", filename);
|
||||
ret = FILE_OPEN;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* this callback just does nothing besides returning OK. Meant to do a dry run over the file to check its integrity
|
||||
*/
|
||||
static err_t simulate()
|
||||
{
|
||||
err_t ret = OK;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* this callback verifies the data against the S-record file contents after a write to destination
|
||||
*/
|
||||
static err_t verify(uint8_t *dst, uint8_t *src, uint32_t length)
|
||||
{
|
||||
uint8_t *end = src + length;
|
||||
|
||||
do
|
||||
{
|
||||
if (*src++ != *dst++)
|
||||
return FAIL;
|
||||
} while (src < end);
|
||||
|
||||
return OK;
|
||||
}
|
||||
1174
pci/ehci-hcd.c
Normal file
1174
pci/ehci-hcd.c
Normal file
File diff suppressed because it is too large
Load Diff
2380
pci/ohci-hcd.c
Normal file
2380
pci/ohci-hcd.c
Normal file
File diff suppressed because it is too large
Load Diff
66
pci/pci_errata.c
Executable file
66
pci/pci_errata.c
Executable file
@@ -0,0 +1,66 @@
|
||||
#include "pci_errata.h"
|
||||
#include "pci.h"
|
||||
#include <MCF5475.h>
|
||||
|
||||
#include "debug.h"
|
||||
|
||||
__attribute__((aligned(16))) void chip_errata_135(void)
|
||||
{
|
||||
/*
|
||||
* Errata type: Silicon
|
||||
* Affected component: PCI
|
||||
* Description: When core PCI transactions that involve writes to configuration or I/O space
|
||||
* are followed by a core line access to line addresses 0x4 and 0xC, core access
|
||||
* to the XL bus can hang.
|
||||
* Workaround: Prevent PCI configuration and I/O writes from being followed by the described
|
||||
* line access by the core by generating a known good XL bus transaction after
|
||||
* the PCI transaction.
|
||||
* Create a dummy function which is called immediately after each of the affected
|
||||
* transactions. There are three requirements for this dummy function.
|
||||
* 1. The function must be aligned to a 16-byte boundary.
|
||||
* 2. The function must contain a dummy write to a location on the XL bus,
|
||||
* preferably one with no side effects.
|
||||
* 3. The function must be longer than 32 bytes. If it is not, the function should
|
||||
* be padded with 16- or 48-bit TPF instructions placed after the end of
|
||||
* the function (after the RTS instruction) such that the length is longer
|
||||
* than 32 bytes.
|
||||
*/
|
||||
|
||||
__asm__ __volatile(
|
||||
" .extern __MBAR \n\t"
|
||||
" clr.l d0 \n\t"
|
||||
" move.l d0,__MBAR+0xF0C \n\t" /* Must use direct addressing. write to EPORT module */
|
||||
/* xlbus -> slavebus -> eport, writing '0' to register */
|
||||
/* has no effect */
|
||||
" rts \n\t"
|
||||
" tpf.l #0x0 \n\t"
|
||||
" tpf.l #0x0 \n\t"
|
||||
" tpf.l #0x0 \n\t"
|
||||
" tpf.l #0x0 \n\t"
|
||||
" tpf.l #0x0 \n\t"
|
||||
::: "d0", "memory");
|
||||
}
|
||||
|
||||
void chip_errata_055(int32_t handle)
|
||||
{
|
||||
uint32_t dummy;
|
||||
|
||||
return; /* test */
|
||||
|
||||
/* initiate PCI configuration access to device */
|
||||
MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */
|
||||
MCF_PCI_PCICAR_BUSNUM(3) | /* note: invalid bus number */
|
||||
MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | /* device number, devices 0 - 9 are reserved */
|
||||
MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | /* function number */
|
||||
MCF_PCI_PCICAR_DWORD(0);
|
||||
|
||||
/* issue a dummy read to an unsupported bus number (will fail) */
|
||||
dummy = * (volatile uint32_t *) PCI_IO_OFFSET; /* access device */
|
||||
|
||||
/* silently clear the PCI errors we produced just now */
|
||||
MCF_PCI_PCIISR = 0xffffffff; /* clear all errors */
|
||||
MCF_PCI_PCIGSCR = MCF_PCI_PCIGSCR_PE | MCF_PCI_PCIGSCR_SE;
|
||||
|
||||
(void) dummy;
|
||||
}
|
||||
|
||||
469
pci/pci_wrappers.S
Normal file
469
pci/pci_wrappers.S
Normal file
@@ -0,0 +1,469 @@
|
||||
/*
|
||||
* pci.S
|
||||
*
|
||||
* Purpose: PCI configuration for the Coldfire builtin PCI bridge.
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 08.05.2014
|
||||
* Author: David Galvez
|
||||
*/
|
||||
|
||||
.global _wrapper_find_pci_device
|
||||
.global _wrapper_find_pci_classcode
|
||||
|
||||
.global _wrapper_read_config_longword
|
||||
.global _wrapper_read_config_word
|
||||
.global _wrapper_read_config_byte
|
||||
|
||||
.global _wrapper_fast_read_config_byte
|
||||
.global _wrapper_fast_read_config_word
|
||||
.global _wrapper_fast_read_config_longword
|
||||
|
||||
.global _wrapper_write_config_longword
|
||||
.global _wrapper_write_config_word
|
||||
.global _wrapper_write_config_byte
|
||||
|
||||
.global _wrapper_get_resource
|
||||
.global _wrapper_hook_interrupt
|
||||
.global _wrapper_unhook_interrupt
|
||||
|
||||
.global _wrapper_special_cycle
|
||||
.global _wrapper_get_routing
|
||||
.global _wrapper_set_interrupt
|
||||
.global _wrapper_get_resource
|
||||
.global _wrapper_get_card_used
|
||||
.global _wrapper_set_card_used
|
||||
|
||||
.global _wrapper_read_mem_byte
|
||||
.global _wrapper_read_mem_word
|
||||
.global _wrapper_read_mem_longword
|
||||
|
||||
.global _wrapper_fast_read_mem_byte
|
||||
.global _wrapper_fast_read_mem_word
|
||||
.global _wrapper_fast_read_mem_longword
|
||||
|
||||
.global _wrapper_write_mem_byte
|
||||
.global _wrapper_write_mem_word
|
||||
.global _wrapper_write_mem_longword
|
||||
|
||||
.global _wrapper_read_io_byte
|
||||
.global _wrapper_read_io_word
|
||||
.global _wrapper_read_io_longword
|
||||
|
||||
.global _wrapper_fast_read_io_byte
|
||||
.global _wrapper_fast_read_io_word
|
||||
.global _wrapper_fast_read_io_longword
|
||||
|
||||
.global _wrapper_write_io_byte
|
||||
.global _wrapper_write_io_word
|
||||
.global _wrapper_write_io_longword
|
||||
|
||||
.global _wrapper_get_machine_id
|
||||
.global _wrapper_get_pagesize
|
||||
|
||||
.global _wrapper_virt_to_bus
|
||||
.global _wrapper_bus_to_virt
|
||||
.global _wrapper_virt_to_phys
|
||||
.global _wrapper_phys_to_virt
|
||||
|
||||
|
||||
_wrapper_find_pci_device:
|
||||
move.l D1,-(SP) // index
|
||||
move.l D0,-(SP) // Vendor ID
|
||||
move.l #16,D1
|
||||
lsr.l D1,D0
|
||||
move.l D0,-(SP) // Device ID
|
||||
jsr _pci_find_device
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
_wrapper_find_pci_classcode:
|
||||
move.l D1,-(SP) // index
|
||||
move.l D0,-(SP) // ID
|
||||
jsr _pci_find_classcode
|
||||
addq.l #8,SP
|
||||
rts
|
||||
|
||||
_wrapper_read_config_byte:
|
||||
move.l A0,-(SP) // pointer to space for read data
|
||||
move.l D1,-(SP) // PCI register
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_config_byte
|
||||
move.l 8(SP),A0 // PCI_BIOS expects value in memory
|
||||
move.l D0,(A0)
|
||||
add.l #12,SP
|
||||
move.l #0,D0
|
||||
rts
|
||||
|
||||
_wrapper_read_config_word:
|
||||
move.l A0,-(SP) // pointer to space for read data
|
||||
move.l D1,-(SP) // PCI register
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_config_word
|
||||
move.l 8(SP),A0 // little to big endian
|
||||
move.l D0,(A0)
|
||||
mvz.b 1(A0),D0
|
||||
lsl.l #8,D0
|
||||
move.b (A0),D0
|
||||
move.l D0,(A0) // PCI_BIOS expects value in memory, not in D0
|
||||
add.l #12,SP
|
||||
move.l #0,D0
|
||||
rts
|
||||
|
||||
_wrapper_read_config_longword:
|
||||
move.l A0,-(SP) // pointer to space for read data
|
||||
move.l D1,-(SP) // PCI register
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_config_longword
|
||||
move.l 8(SP),A0 // little to big endian
|
||||
move.l D0,(A0)
|
||||
mvz.b 3(A0),D0
|
||||
lsl.l #8,D0
|
||||
move.b 2(A0),D0
|
||||
lsl.l #8,D0
|
||||
move.b 1(A0),D0
|
||||
lsl.l #8,D0
|
||||
move.b (A0),D0
|
||||
move.l D0,(A0) // PCI_BIOS expects value in memory, not in D0
|
||||
add.l #12,SP
|
||||
move.l #0,D0
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_fast_read_config_byte:
|
||||
move.l D1,-(SP) // PCI register
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_fast_read_config_byte
|
||||
addq.l #8,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_fast_read_config_word:
|
||||
move.l D1,-(SP) // PCI register
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_fast_read_config_word
|
||||
addq.l #8,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_fast_read_config_longword:
|
||||
move.l D1,-(SP) // PCI register
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_fast_read_config_longword
|
||||
addq.l #8,SP
|
||||
rts
|
||||
|
||||
_wrapper_write_config_byte:
|
||||
move.l D2,-(SP) // data to write
|
||||
move.l D1,-(SP) // PCI register
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_write_config_byte
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
_wrapper_write_config_word:
|
||||
move.l D0,-(SP) // make data little endian
|
||||
moveq #0,D1
|
||||
move.w D2,D1
|
||||
lsr.l #8,D1
|
||||
asl.l #8,D2
|
||||
or.l D1,D2
|
||||
move.l (SP)+,D0
|
||||
move.l D2,-(SP) // data to write
|
||||
move.l D1,-(SP) // PCI register
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_write_config_word
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
_wrapper_write_config_longword:
|
||||
move.l D0,-(SP)
|
||||
move.l D2,D0 // make data little endian
|
||||
lsr.l #8,D0
|
||||
asl.l #8,D2
|
||||
and.l #0x00FF00FF,D0
|
||||
and.l #0xFF00FF00,D2
|
||||
or.l D0,D2
|
||||
swap D2
|
||||
move.l (SP)+,D0
|
||||
move.l D2,-(SP) // data to write
|
||||
move.l D1,-(SP) // PCI register
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_write_config_longword
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
_wrapper_hook_interrupt:
|
||||
move.l A1,-(SP) // parameter for interrupt handler
|
||||
move.l A0,-(SP) // pointer to interrupt handler
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_hook_interrupt
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
_wrapper_unhook_interrupt:
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_unhook_interrupt
|
||||
addq.l #4,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_special_cycle:
|
||||
move.l D1,-(SP) // special cycle data
|
||||
move.l D0,-(SP) // bus number
|
||||
jsr _pci_special_cycle
|
||||
addq.l #8,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_get_routing:
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_get_routing
|
||||
addq.l #4,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_set_interrupt:
|
||||
move.l D1,-(SP) // mode
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_set_interrupt
|
||||
addq.l #8,SP
|
||||
rts
|
||||
|
||||
_wrapper_get_resource:
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_get_resource
|
||||
addq.l #4,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_get_card_used:
|
||||
move.l D1,-(SP) // address
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_get_card_used
|
||||
addq.l #8,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_set_card_used:
|
||||
move.l A0,-(SP) // callback
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_set_card_used
|
||||
addq.l #8,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_read_mem_byte:
|
||||
move.l A0,-(SP) // pointer to data in memory
|
||||
move.l D1,-(SP) // address to access (in PCI memory address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_mem_byte
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_read_mem_word:
|
||||
move.l A0,-(SP) // pointer to data in memory
|
||||
move.l D1,-(SP) // address to access (in PCI memory address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_mem_word
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_read_mem_longword:
|
||||
move.l A0,-(SP) // pointer to data in memory
|
||||
move.l D1,-(SP) // address to access (in PCI memory address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_mem_longword
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_fast_read_mem_byte:
|
||||
move.l D1,-(SP) // address to access (in PCI memory address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_mem_byte
|
||||
addq.l #8,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_fast_read_mem_word:
|
||||
move.l D1,-(SP) // address to access (in PCI memory address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_mem_word
|
||||
addq.l #8,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_fast_read_mem_longword:
|
||||
move.l D1,-(SP) // address to access (in PCI memory address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_mem_longword
|
||||
addq.l #8,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_write_mem_byte:
|
||||
move.l D2,-(SP) // data to write
|
||||
move.l D1,-(SP) // address to access (in PCI memory address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_write_mem_byte
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_write_mem_word:
|
||||
move.l D2,-(SP) // data to write
|
||||
move.l D1,-(SP) // address to access (in PCI memory address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_write_mem_word
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_write_mem_longword:
|
||||
move.l D2,-(SP) // data to write
|
||||
move.l D1,-(SP) // address to access (in PCI memory address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_write_mem_longword
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_read_io_byte:
|
||||
move.l A0,-(SP) // pointer to data in memory
|
||||
move.l D1,-(SP) // address to access (in PCI I/O address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_io_byte
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_read_io_word:
|
||||
move.l A0,-(SP) // pointer to data in memory
|
||||
move.l D1,-(SP) // address to access (in PCI I/O address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_io_word
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_read_io_longword:
|
||||
move.l A0,-(SP) // pointer to data in memory
|
||||
move.l D1,-(SP) // address to access (in PCI I/O address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_io_longword
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_fast_read_io_byte:
|
||||
move.l D1,-(SP) // address to access (in PCI I/O address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_io_byte
|
||||
addq.l #8,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_fast_read_io_word:
|
||||
move.l D1,-(SP) // address to access (in PCI I/O address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_io_word
|
||||
addq.l #8,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_fast_read_io_longword:
|
||||
move.l D1,-(SP) // address to access (in PCI I/O address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_io_longword
|
||||
addq.l #8,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_write_io_byte:
|
||||
move.l D2,-(SP) // data to write
|
||||
move.l D1,-(SP) // address to access (in PCI I/O address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_write_io_byte
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_write_io_word:
|
||||
move.l D2,-(SP) // data to write
|
||||
move.l D1,-(SP) // address to access (in PCI I/O address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_write_io_word
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_write_io_longword:
|
||||
move.l D2,-(SP) // data to write
|
||||
move.l D1,-(SP) // address to access (in PCI I/O address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_write_io_longword
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_get_machine_id:
|
||||
jsr _pci_get_machine_id
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_get_pagesize:
|
||||
jsr _pci_get_pagesize
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_virt_to_bus:
|
||||
move.l A0,-(SP) // ptr
|
||||
move.l D1,-(SP) // address in virtual CPU space
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_virt_to_bus
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_bus_to_virt:
|
||||
move.l A0,-(SP) // ptr
|
||||
move.l D1,-(SP) // PCI bus address
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_bus_to_virt
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_virt_to_phys:
|
||||
move.l A0,-(SP) // ptr
|
||||
move.l D0,-(SP) // address in virtual CPU space
|
||||
jsr _pci_virt_to_phys
|
||||
addq.l #8,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_phys_to_virt:
|
||||
move.l A0,-(SP) // ptr
|
||||
move.l D0,-(SP) // physical CPU address
|
||||
jsr _pci_phys_to_virt
|
||||
addq.l #8,SP
|
||||
rts
|
||||
474
radeon/i2c-algo-bit.c
Normal file
474
radeon/i2c-algo-bit.c
Normal file
@@ -0,0 +1,474 @@
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* i2c-algo-bit.c i2c driver algorithms for bit-shift adapters */
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* Copyright (C) 1995-2000 Simon G. Vogl
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/* With some changes from Frodo Looijaard <frodol@dds.nl>, Ky<4B>sti M<>lkki
|
||||
<kmalkki@cc.hut.fi> and Jean Delvare <khali@linux-fr.org> */
|
||||
|
||||
#include "wait.h"
|
||||
#include "i2c.h"
|
||||
#include "i2c-algo-bit.h"
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL ((void *)0)
|
||||
#endif
|
||||
|
||||
// #define DEBUG
|
||||
#include "debug.h"
|
||||
|
||||
extern void start_timeout(void);
|
||||
extern int end_timeout(long msec);
|
||||
|
||||
/* --- setting states on the bus with the right timing: --------------- */
|
||||
|
||||
#define setsda(adap,val) adap->setsda(adap->data, val)
|
||||
#define setscl(adap,val) adap->setscl(adap->data, val)
|
||||
#define getsda(adap) adap->getsda(adap->data)
|
||||
#define getscl(adap) adap->getscl(adap->data)
|
||||
|
||||
static inline void sdalo(struct i2c_algo_bit_data *adap)
|
||||
{
|
||||
setsda(adap,0);
|
||||
wait_us(adap->udelay);
|
||||
}
|
||||
|
||||
static inline void sdahi(struct i2c_algo_bit_data *adap)
|
||||
{
|
||||
setsda(adap,1);
|
||||
wait_us(adap->udelay);
|
||||
}
|
||||
|
||||
static inline void scllo(struct i2c_algo_bit_data *adap)
|
||||
{
|
||||
setscl(adap,0);
|
||||
wait_us(adap->udelay);
|
||||
}
|
||||
|
||||
/*
|
||||
* Raise scl line, and do checking for delays. This is necessary for slower
|
||||
* devices.
|
||||
*/
|
||||
static inline int sclhi(struct i2c_algo_bit_data *adap)
|
||||
{
|
||||
setscl(adap, 1);
|
||||
/* Not all adapters have scl sense line... */
|
||||
if(adap->getscl == NULL )
|
||||
{
|
||||
wait_us(adap->udelay);
|
||||
return 0;
|
||||
}
|
||||
start_timeout();
|
||||
while (! getscl(adap))
|
||||
{
|
||||
/* the hw knows how to read the clock line,
|
||||
* so we wait until it actually gets high.
|
||||
* This is safer as some chips may hold it low
|
||||
* while they are processing data internally.
|
||||
*/
|
||||
if (end_timeout((long)adap->timeout))
|
||||
return -110;
|
||||
}
|
||||
wait_us(adap->udelay);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/* --- other auxiliary functions -------------------------------------- */
|
||||
void i2c_start(struct i2c_algo_bit_data *adap)
|
||||
{
|
||||
/* assert: scl, sda are high */
|
||||
sdalo(adap);
|
||||
scllo(adap);
|
||||
}
|
||||
|
||||
static void i2c_repstart(struct i2c_algo_bit_data *adap)
|
||||
{
|
||||
/* scl, sda may not be high */
|
||||
setsda(adap, 1);
|
||||
sclhi(adap);
|
||||
wait_us(adap->udelay);
|
||||
sdalo(adap);
|
||||
scllo(adap);
|
||||
}
|
||||
|
||||
static void i2c_stop(struct i2c_algo_bit_data *adap)
|
||||
{
|
||||
/* assert: scl is low */
|
||||
sdalo(adap);
|
||||
sclhi(adap);
|
||||
sdahi(adap);
|
||||
}
|
||||
|
||||
/*
|
||||
* send a byte without start cond., look for arbitration,
|
||||
* check ackn. from slave
|
||||
*
|
||||
* returns:
|
||||
* 1 if the device acknowledged
|
||||
* 0 if the device did not ack
|
||||
* -ETIMEDOUT if an error occurred (while raising the scl line)
|
||||
*/
|
||||
static int i2c_outb(struct i2c_adapter *i2c_adap, char c)
|
||||
{
|
||||
int i;
|
||||
int sb;
|
||||
int ack;
|
||||
struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
|
||||
/* assert: scl is low */
|
||||
|
||||
for (i = 7; i >= 0; i--)
|
||||
{
|
||||
sb = c & (1 << i);
|
||||
setsda(adap,sb);
|
||||
wait_us(adap->udelay);
|
||||
if (sclhi(adap) < 0)
|
||||
{
|
||||
/* timed out */
|
||||
sdahi(adap); /* we don't want to block the net */
|
||||
#ifdef DEBUG
|
||||
dbg("ETIMEDOUT\r\n");
|
||||
#endif
|
||||
return -110;
|
||||
};
|
||||
/* do arbitration here:
|
||||
* if ( sb && ! getsda(adap) ) -> ouch! Get out of here.
|
||||
*/
|
||||
setscl(adap, 0 );
|
||||
wait_us(adap->udelay);
|
||||
}
|
||||
sdahi(adap);
|
||||
if(sclhi(adap)<0)
|
||||
{
|
||||
/* timeout */
|
||||
|
||||
dbg("ETIMEDOUT\r\n");
|
||||
|
||||
return -110;
|
||||
}
|
||||
/* read ack: SDA should be pulled down by slave */
|
||||
ack = getsda(adap); /* ack: sda is pulled low ->success. */
|
||||
scllo(adap);
|
||||
|
||||
dbg("0x%02x, ack=0x%02x\r\n", (unsigned long)(c & 0xff), ack);
|
||||
|
||||
return 0 == ack; /* return 1 if device acked */
|
||||
/* assert: scl is low (sda undef) */
|
||||
}
|
||||
|
||||
static int i2c_inb(struct i2c_adapter *i2c_adap)
|
||||
{
|
||||
/* read byte via i2c port, without start/stop sequence */
|
||||
/* acknowledge is sent in i2c_read. */
|
||||
int i;
|
||||
unsigned char indata = 0;
|
||||
struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
|
||||
/* assert: scl is low */
|
||||
sdahi(adap);
|
||||
for(i = 0; i < 8; i++)
|
||||
{
|
||||
if (sclhi(adap) < 0)
|
||||
{
|
||||
/* timeout */
|
||||
dbg("i2c_inb TIMEDOUT\r\n");
|
||||
return -110;
|
||||
}
|
||||
indata *= 2;
|
||||
if (getsda(adap))
|
||||
indata |= 0x01;
|
||||
scllo(adap);
|
||||
}
|
||||
/* assert: scl is low */
|
||||
dbg("0x%02x\r\n", (unsigned long)(indata & 0xff));
|
||||
|
||||
return (int) (indata & 0xff);
|
||||
}
|
||||
|
||||
/*
|
||||
* Sanity check for the adapter hardware - check the reaction of
|
||||
* the bus lines only if it seems to be idle.
|
||||
*/
|
||||
static int test_bus(struct i2c_algo_bit_data *adap)
|
||||
{
|
||||
int scl, sda;
|
||||
sda = getsda(adap);
|
||||
scl = (adap->getscl == NULL ? 1 : getscl(adap));
|
||||
if (!scl || !sda )
|
||||
goto bailout;
|
||||
sdalo(adap);
|
||||
sda = getsda(adap);
|
||||
scl = (adap->getscl == NULL ? 1 : getscl(adap));
|
||||
if (sda !=0 || scl == 0)
|
||||
goto bailout;
|
||||
sdahi(adap);
|
||||
sda = getsda(adap);
|
||||
scl = (adap->getscl == NULL ? 1 : getscl(adap));
|
||||
if (sda == 0 || scl ==0)
|
||||
goto bailout;
|
||||
scllo(adap);
|
||||
sda = getsda(adap);
|
||||
scl = (adap->getscl == NULL ? 0 : getscl(adap));
|
||||
if (scl !=0 || sda == 0)
|
||||
goto bailout;
|
||||
sclhi(adap);
|
||||
sda = getsda(adap);
|
||||
scl = (adap->getscl == NULL ? 1 : getscl(adap));
|
||||
if (scl == 0 || sda ==0)
|
||||
goto bailout;
|
||||
return 0;
|
||||
bailout:
|
||||
sdahi(adap);
|
||||
sclhi(adap);
|
||||
return -110;
|
||||
}
|
||||
|
||||
/* ----- Utility functions
|
||||
*/
|
||||
|
||||
/* try_address tries to contact a chip for a number of
|
||||
* times before it gives up.
|
||||
* return values:
|
||||
* 1 chip answered
|
||||
* 0 chip did not answer
|
||||
* -x transmission error
|
||||
*/
|
||||
static inline int try_address(struct i2c_adapter *i2c_adap,
|
||||
unsigned char addr, int retries)
|
||||
{
|
||||
struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
|
||||
int i, ret = -1;
|
||||
for (i = 0; i <= retries; i++)
|
||||
{
|
||||
ret = i2c_outb(i2c_adap, addr);
|
||||
if (ret == 1)
|
||||
break; /* success! */
|
||||
i2c_stop(adap);
|
||||
wait_us(5);
|
||||
if (i == retries) /* no success */
|
||||
break;
|
||||
i2c_start(adap);
|
||||
wait_us(adap->udelay);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sendbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msg)
|
||||
{
|
||||
struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
|
||||
char c;
|
||||
const char *temp = (const char *)msg->buf;
|
||||
int count = msg->len;
|
||||
unsigned short nak_ok = msg->flags & I2C_M_IGNORE_NAK;
|
||||
int retval;
|
||||
int wrcount=0;
|
||||
while(count > 0)
|
||||
{
|
||||
c = *temp;
|
||||
retval = i2c_outb(i2c_adap,c);
|
||||
if ((retval > 0) || (nak_ok && (retval==0)))
|
||||
{ /* ok or ignored NAK */
|
||||
count--;
|
||||
temp++;
|
||||
wrcount++;
|
||||
}
|
||||
else
|
||||
{ /* arbitration or no acknowledge */
|
||||
i2c_stop(adap);
|
||||
return (retval < 0)? retval : -110;
|
||||
/* got a better one ?? */
|
||||
}
|
||||
}
|
||||
return wrcount;
|
||||
}
|
||||
|
||||
static inline int readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msg)
|
||||
{
|
||||
int inval;
|
||||
int rdcount=0; /* counts bytes read */
|
||||
struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
|
||||
char *temp = (char *)msg->buf;
|
||||
int count = msg->len;
|
||||
while(count > 0)
|
||||
{
|
||||
inval = i2c_inb(i2c_adap);
|
||||
if (inval >= 0)
|
||||
{
|
||||
*temp = inval;
|
||||
rdcount++;
|
||||
}
|
||||
else
|
||||
/* read timed out */
|
||||
break;
|
||||
temp++;
|
||||
count--;
|
||||
if (msg->flags & I2C_M_NO_RD_ACK)
|
||||
continue;
|
||||
if (count > 0)
|
||||
/* send ack */
|
||||
sdalo(adap);
|
||||
else
|
||||
sdahi(adap); /* neg. ack on last byte */
|
||||
if (sclhi(adap) < 0)
|
||||
{
|
||||
/* timeout */
|
||||
sdahi(adap);
|
||||
return -1;
|
||||
};
|
||||
scllo(adap);
|
||||
sdahi(adap);
|
||||
}
|
||||
return rdcount;
|
||||
}
|
||||
|
||||
/* doAddress initiates the transfer by generating the start condition (in
|
||||
* try_address) and transmits the address in the necessary format to handle
|
||||
* reads, writes as well as 10bit-addresses.
|
||||
* returns:
|
||||
* 0 everything went okay, the chip ack'ed, or IGNORE_NAK flag was set
|
||||
* -x an error occurred (like: -EREMOTEIO if the device did not answer, or
|
||||
* -ETIMEDOUT, for example if the lines are stuck...)
|
||||
*/
|
||||
static inline int bit_doAddress(struct i2c_adapter *i2c_adap, struct i2c_msg *msg)
|
||||
{
|
||||
unsigned short flags = msg->flags;
|
||||
unsigned short nak_ok = msg->flags & I2C_M_IGNORE_NAK;
|
||||
struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
|
||||
unsigned char addr;
|
||||
int ret, retries;
|
||||
retries = nak_ok ? 0 : i2c_adap->retries;
|
||||
if (flags & I2C_M_TEN)
|
||||
{
|
||||
/* a ten bit address */
|
||||
addr = 0xf0 | (( msg->addr >> 7) & 0x03);
|
||||
/* try extended address code...*/
|
||||
ret = try_address(i2c_adap, addr, retries);
|
||||
if ((ret != 1) && !nak_ok)
|
||||
return -1;
|
||||
/* the remaining 8 bit address */
|
||||
ret = i2c_outb(i2c_adap,msg->addr & 0x7f);
|
||||
if ((ret != 1) && !nak_ok)
|
||||
/* the chip did not ack / xmission error occurred */
|
||||
return -1;
|
||||
if (flags & I2C_M_RD)
|
||||
{
|
||||
i2c_repstart(adap);
|
||||
/* okay, now switch into reading mode */
|
||||
addr |= 0x01;
|
||||
ret = try_address(i2c_adap, addr, retries);
|
||||
if ((ret != 1) && !nak_ok)
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
else
|
||||
{ /* normal 7bit address */
|
||||
addr = (msg->addr << 1);
|
||||
if (flags & I2C_M_RD )
|
||||
addr |= 1;
|
||||
if (flags & I2C_M_REV_DIR_ADDR )
|
||||
addr ^= 1;
|
||||
ret = try_address(i2c_adap, addr, retries);
|
||||
if ((ret != 1) && !nak_ok)
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bit_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[], int num)
|
||||
{
|
||||
struct i2c_msg *pmsg;
|
||||
struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
|
||||
int i,ret;
|
||||
unsigned short nak_ok;
|
||||
i2c_start(adap);
|
||||
for(i=0;i<num;i++)
|
||||
{
|
||||
pmsg = &msgs[i];
|
||||
nak_ok = pmsg->flags & I2C_M_IGNORE_NAK;
|
||||
if(!(pmsg->flags & I2C_M_NOSTART))
|
||||
{
|
||||
if (i)
|
||||
i2c_repstart(adap);
|
||||
ret = bit_doAddress(i2c_adap, pmsg);
|
||||
if ((ret != 0) && !nak_ok)
|
||||
return (ret < 0) ? ret : -1;
|
||||
}
|
||||
if(pmsg->flags & I2C_M_RD )
|
||||
{
|
||||
/* read bytes into buffer*/
|
||||
ret = readbytes(i2c_adap, pmsg);
|
||||
if(ret < pmsg->len)
|
||||
return (ret < 0)? ret : -1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* write bytes from buffer */
|
||||
ret = sendbytes(i2c_adap, pmsg);
|
||||
if (ret < pmsg->len )
|
||||
return (ret < 0) ? ret : -1;
|
||||
}
|
||||
}
|
||||
i2c_stop(adap);
|
||||
return num;
|
||||
}
|
||||
|
||||
/* -----exported algorithm data: ------------------------------------- */
|
||||
|
||||
static struct i2c_algorithm i2c_bit_algo = {
|
||||
.master_xfer = bit_xfer,
|
||||
};
|
||||
|
||||
/*
|
||||
* registering functions to load algorithms at runtime
|
||||
*/
|
||||
int i2c_bit_add_bus(struct i2c_adapter *adap)
|
||||
{
|
||||
struct i2c_algo_bit_data *bit_adap = adap->algo_data;
|
||||
if (1)
|
||||
{
|
||||
int ret = test_bus(bit_adap);
|
||||
if (ret < 0)
|
||||
return -1;
|
||||
}
|
||||
/* register new adapter to i2c module... */
|
||||
adap->algo = &i2c_bit_algo;
|
||||
adap->timeout = 10; /* default values, should */
|
||||
adap->retries = 3; /* be replaced by defines */
|
||||
return 0;
|
||||
}
|
||||
|
||||
int i2c_bit_del_bus(struct i2c_adapter *adap)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------
|
||||
* the functional interface to the i2c busses.
|
||||
* ----------------------------------------------------
|
||||
*/
|
||||
|
||||
int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
|
||||
{
|
||||
int ret;
|
||||
if (adap->algo->master_xfer)
|
||||
{
|
||||
ret = adap->algo->master_xfer(adap, msgs, num);
|
||||
return ret;
|
||||
}
|
||||
else
|
||||
return -1;
|
||||
}
|
||||
1036
radeon/radeon_accel.c
Normal file
1036
radeon/radeon_accel.c
Normal file
File diff suppressed because it is too large
Load Diff
2457
radeon/radeon_base.c
Normal file
2457
radeon/radeon_base.c
Normal file
File diff suppressed because it is too large
Load Diff
335
radeon/radeon_cursor.c
Normal file
335
radeon/radeon_cursor.c
Normal file
@@ -0,0 +1,335 @@
|
||||
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_cursor.c,v 1.26 2003/11/10 18:41:22 tsi Exp $ */
|
||||
/*
|
||||
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
|
||||
* VA Linux Systems Inc., Fremont, California.
|
||||
*
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation on the rights to use, copy, modify, merge,
|
||||
* publish, distribute, sublicense, and/or sell copies of the Software,
|
||||
* and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the
|
||||
* next paragraph) shall be included in all copies or substantial
|
||||
* portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
|
||||
* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Authors:
|
||||
* Kevin E. Martin <martin@xfree86.org>
|
||||
* Rickard E. Faith <faith@valinux.com>
|
||||
*
|
||||
* References:
|
||||
*
|
||||
* !!!! FIXME !!!!
|
||||
* RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
|
||||
* Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
|
||||
* 1999.
|
||||
*
|
||||
* RAGE 128 Software Development Manual (Technical Reference Manual P/N
|
||||
* SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "bas_types.h"
|
||||
#include "bas_printf.h"
|
||||
#include "radeonfb.h"
|
||||
|
||||
#define DBG_RADEON
|
||||
#ifdef DBG_RADEON
|
||||
#define dbg(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0)
|
||||
#else
|
||||
#define dbg(format, arg...) do { ; } while (0)
|
||||
#endif /* DBG_RADEON */
|
||||
|
||||
|
||||
#define CURSOR_WIDTH 64
|
||||
#define CURSOR_HEIGHT 64
|
||||
|
||||
/*
|
||||
* The cursor bits are always 32bpp. On MSBFirst buses,
|
||||
* configure byte swapping to swap 32 bit units when writing
|
||||
* the cursor image. Byte swapping must always be returned
|
||||
* to its previous value before returning.
|
||||
*/
|
||||
#define CURSOR_SWAPPING_DECL_MMIO
|
||||
#define CURSOR_SWAPPING_DECL unsigned long __surface_cntl=0;
|
||||
#define CURSOR_SWAPPING_START() \
|
||||
if (rinfo->big_endian) \
|
||||
OUTREG(SURFACE_CNTL, \
|
||||
((__surface_cntl = INREG(SURFACE_CNTL)) | \
|
||||
NONSURF_AP0_SWP_32BPP) & \
|
||||
~NONSURF_AP0_SWP_16BPP);
|
||||
#define CURSOR_SWAPPING_END() \
|
||||
if (rinfo->big_endian) \
|
||||
(OUTREG(SURFACE_CNTL, __surface_cntl));
|
||||
|
||||
/* Set cursor foreground and background colors */
|
||||
void radeon_set_cursor_colors(struct fb_info *info, int32_t bg, int32_t fg)
|
||||
{
|
||||
struct radeonfb_info *rinfo = info->par;
|
||||
unsigned long *pixels = (unsigned long *)((unsigned long) rinfo->fb_base + rinfo->cursor_start);
|
||||
int pixel, i;
|
||||
CURSOR_SWAPPING_DECL_MMIO
|
||||
CURSOR_SWAPPING_DECL
|
||||
// DPRINTVALHEX("radeonfb: RADEONSetCursorColors: cursor_start ",rinfo->cursor_start);
|
||||
// DPRINT("\r\n");
|
||||
fg |= 0xff000000;
|
||||
bg |= 0xff000000;
|
||||
/* Don't recolour the image if we don't have to. */
|
||||
if (fg == rinfo->cursor_fg && bg == rinfo->cursor_bg)
|
||||
return;
|
||||
CURSOR_SWAPPING_START();
|
||||
|
||||
/*
|
||||
* Note: We assume that the pixels are either fully opaque or fully
|
||||
* transparent, so we won't premultiply them, and we can just
|
||||
* check for non-zero pixel values; those are either fg or bg
|
||||
*/
|
||||
for (i = 0; i < CURSOR_WIDTH * CURSOR_HEIGHT; i++, pixels++)
|
||||
if ((pixel = *pixels))
|
||||
*pixels = (pixel == rinfo->cursor_fg) ? fg : bg;
|
||||
CURSOR_SWAPPING_END();
|
||||
rinfo->cursor_fg = fg;
|
||||
rinfo->cursor_bg = bg;
|
||||
}
|
||||
|
||||
/* Set cursor position to (x,y) with offset into cursor bitmap at
|
||||
* (xorigin,yorigin)
|
||||
*/
|
||||
void radeon_set_cursor_position(struct fb_info *info, int32_t x, int32_t y)
|
||||
{
|
||||
struct radeonfb_info *rinfo = info->par;
|
||||
struct fb_var_screeninfo *mode = &info->var;
|
||||
int xorigin = 0;
|
||||
int yorigin = 0;
|
||||
if (mode->vmode & FB_VMODE_DOUBLE)
|
||||
y <<= 1;
|
||||
if (x < 0)
|
||||
xorigin = 1 - x;
|
||||
if (y < 0)
|
||||
yorigin = 1 - y;
|
||||
|
||||
// DPRINTVALHEX("radeonfb: RADEONSetCursorPosition: cursor_start ",rinfo->cursor_start);
|
||||
// DPRINTVAL(" x ",x);
|
||||
// DPRINTVAL(" y ",y);
|
||||
// DPRINT("\r\n");
|
||||
|
||||
OUTREG(CUR_HORZ_VERT_OFF, (CUR_LOCK | (xorigin << 16) | yorigin));
|
||||
OUTREG(CUR_HORZ_VERT_POSN, (CUR_LOCK | ((xorigin ? 0 : x) << 16) | (yorigin ? 0 : y)));
|
||||
OUTREG(CUR_OFFSET, rinfo->cursor_start + yorigin * 256);
|
||||
rinfo->cursor_x = (unsigned long)x;
|
||||
if (mode->vmode & FB_VMODE_DOUBLE)
|
||||
rinfo->cursor_y = (unsigned long) y >> 1;
|
||||
else
|
||||
rinfo->cursor_y = (unsigned long) y;
|
||||
}
|
||||
|
||||
/*
|
||||
* Copy cursor image from `image' to video memory. RADEONSetCursorPosition
|
||||
* will be called after this, so we can ignore xorigin and yorigin.
|
||||
*/
|
||||
void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsigned short *data, int32_t zoom)
|
||||
{
|
||||
struct radeonfb_info *rinfo = info->par;
|
||||
unsigned long *d = (unsigned long *)((unsigned long)rinfo->fb_base+rinfo->cursor_start);
|
||||
unsigned long save = 0;
|
||||
unsigned short chunk, mchunk;
|
||||
unsigned long i, j, k;
|
||||
CURSOR_SWAPPING_DECL
|
||||
|
||||
// DPRINTVALHEX("radeonfb: RADEONLoadCursorImage: cursor_start ",rinfo->cursor_start);
|
||||
// DPRINT("\r\n");
|
||||
|
||||
save = INREG(CRTC_GEN_CNTL) & ~(unsigned long) (3 << 20);
|
||||
save |= (unsigned long) (2 << 20);
|
||||
OUTREG(CRTC_GEN_CNTL, save & (unsigned long)~CRTC_CUR_EN);
|
||||
|
||||
/*
|
||||
* Convert the bitmap to ARGB32.
|
||||
*/
|
||||
CURSOR_SWAPPING_START();
|
||||
#define ARGB_PER_CHUNK (8 * sizeof (chunk))
|
||||
switch(zoom)
|
||||
{
|
||||
case 1:
|
||||
default:
|
||||
for (i = 0; i < CURSOR_HEIGHT; i++)
|
||||
{
|
||||
if (i < 16)
|
||||
{
|
||||
mchunk = *mask++;
|
||||
chunk = *data++;
|
||||
}
|
||||
else
|
||||
mchunk = chunk = 0;
|
||||
for (j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j++)
|
||||
{
|
||||
for (k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
|
||||
{
|
||||
if (mchunk & 0x8000)
|
||||
{
|
||||
if (chunk & 0x8000)
|
||||
*d++ = 0xff000000; /* Black, fully opaque. */
|
||||
else
|
||||
*d++ = 0xffffffff; /* White, fully opaque. */
|
||||
}
|
||||
else
|
||||
*d++ = 0x00000000; /* White/Black, fully transparent. */
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 2:
|
||||
for (i = 0; i < CURSOR_HEIGHT; i++)
|
||||
{
|
||||
if (i < 16*2)
|
||||
{
|
||||
mchunk = *mask;
|
||||
chunk = *data;
|
||||
if ((i & 1) == 1)
|
||||
{
|
||||
mask++;
|
||||
data++;
|
||||
}
|
||||
}
|
||||
else
|
||||
mchunk = chunk = 0;
|
||||
for (j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j+=2)
|
||||
{
|
||||
for (k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
|
||||
{
|
||||
if (mchunk & 0x8000)
|
||||
{
|
||||
if (chunk & 0x8000)
|
||||
{
|
||||
*d++ = 0xff000000; /* Black, fully opaque. */
|
||||
*d++ = 0xff000000;
|
||||
}
|
||||
else
|
||||
{
|
||||
*d++ = 0xffffffff; /* White, fully opaque. */
|
||||
*d++ = 0xffffffff;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
*d++ = 0x00000000; /* White/Black, fully transparent. */
|
||||
*d++ = 0x00000000;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 4:
|
||||
for (i = 0; i < CURSOR_HEIGHT; i++)
|
||||
{
|
||||
if (i < 16 * 4)
|
||||
{
|
||||
mchunk = *mask;
|
||||
chunk = *data;
|
||||
if ((i & 3) == 3)
|
||||
{
|
||||
mask++;
|
||||
data++;
|
||||
}
|
||||
}
|
||||
else
|
||||
mchunk = chunk = 0;
|
||||
for (j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j+=4)
|
||||
{
|
||||
for (k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
|
||||
{
|
||||
if (mchunk & 0x8000)
|
||||
{
|
||||
if (chunk & 0x8000)
|
||||
{
|
||||
*d++ = 0xff000000; /* Black, fully opaque. */
|
||||
*d++ = 0xff000000;
|
||||
*d++ = 0xff000000;
|
||||
*d++ = 0xff000000;
|
||||
}
|
||||
else
|
||||
{
|
||||
*d++ = 0xffffffff; /* White, fully opaque. */
|
||||
*d++ = 0xffffffff;
|
||||
*d++ = 0xffffffff;
|
||||
*d++ = 0xffffffff;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
*d++ = 0x00000000; /* White/Black, fully transparent. */
|
||||
*d++ = 0x00000000;
|
||||
*d++ = 0x00000000;
|
||||
*d++ = 0x00000000;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
CURSOR_SWAPPING_END();
|
||||
rinfo->cursor_bg = 0xffffffff; /* White, fully opaque. */
|
||||
rinfo->cursor_fg = 0xff000000; /* Black, fully opaque. */
|
||||
OUTREG(CRTC_GEN_CNTL, save);
|
||||
}
|
||||
|
||||
/* Hide hardware cursor. */
|
||||
void radeon_hide_cursor(struct fb_info *info)
|
||||
{
|
||||
struct radeonfb_info *rinfo = info->par;
|
||||
|
||||
// DPRINT("radeonfb: RADEONHideCursor\r\n");
|
||||
OUTREGP(CRTC_GEN_CNTL, 0, ~CRTC_CUR_EN);
|
||||
rinfo->cursor_show = 0;
|
||||
}
|
||||
|
||||
/* Show hardware cursor. */
|
||||
void radeon_show_cursor(struct fb_info *info)
|
||||
{
|
||||
struct radeonfb_info *rinfo = info->par;
|
||||
|
||||
// DPRINT("radeonfb: RADEONShowCursor\r\n");
|
||||
OUTREGP(CRTC_GEN_CNTL, CRTC_CUR_EN, ~CRTC_CUR_EN);
|
||||
rinfo->cursor_show = 1;
|
||||
}
|
||||
|
||||
/* Initialize hardware cursor support. */
|
||||
long radeon_cursor_init(struct fb_info *info)
|
||||
{
|
||||
struct radeonfb_info *rinfo = info->par;
|
||||
int size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT;
|
||||
unsigned long fbarea = offscreen_alloc(rinfo->info, size_bytes + 256);
|
||||
|
||||
dbg("radeonfb: %s: fbarea: %p\r\n", fbarea);
|
||||
|
||||
if (!fbarea)
|
||||
rinfo->cursor_start = 0;
|
||||
else
|
||||
{
|
||||
unsigned short data[16], mask[16];
|
||||
|
||||
memset(data, 0, sizeof(data));
|
||||
memset(mask, 0, sizeof(data));
|
||||
rinfo->cursor_start = RADEON_ALIGN(fbarea - (unsigned long) rinfo->fb_base, 256);
|
||||
rinfo->cursor_end = rinfo->cursor_start + size_bytes;
|
||||
radeon_load_cursor_image(info, mask, data, 1);
|
||||
}
|
||||
dbg("radeonfb: %s cursor_start: %p\r\n", rinfo->cursor_start);
|
||||
|
||||
return (rinfo->cursor_start ? fbarea : 0);
|
||||
}
|
||||
237
radeon/radeon_i2c.c
Normal file
237
radeon/radeon_i2c.c
Normal file
@@ -0,0 +1,237 @@
|
||||
#include "video.h"
|
||||
#include "radeonfb.h"
|
||||
#include "edid.h"
|
||||
#include "i2c.h"
|
||||
#include "driver_mem.h"
|
||||
|
||||
// #define DEBUG
|
||||
#include "debug.h"
|
||||
|
||||
|
||||
#define CONFIG_FB_RADEON_I2C
|
||||
#ifdef CONFIG_FB_RADEON_I2C
|
||||
|
||||
#define RADEON_DDC 0x50
|
||||
|
||||
static void radeon_gpio_setscl(void* data, int state)
|
||||
{
|
||||
struct radeon_i2c_chan *chan = data;
|
||||
struct radeonfb_info *rinfo = chan->rinfo;
|
||||
unsigned long val;
|
||||
|
||||
val = INREG(chan->ddc_reg) & ~(VGA_DDC_CLK_OUT_EN);
|
||||
|
||||
if (!state)
|
||||
val |= VGA_DDC_CLK_OUT_EN;
|
||||
OUTREG(chan->ddc_reg, val);
|
||||
(void) INREG(chan->ddc_reg);
|
||||
}
|
||||
|
||||
static void radeon_gpio_setsda(void* data, int state)
|
||||
{
|
||||
struct radeon_i2c_chan *chan = data;
|
||||
struct radeonfb_info *rinfo = chan->rinfo;
|
||||
unsigned long val;
|
||||
|
||||
val = INREG(chan->ddc_reg) & ~(VGA_DDC_DATA_OUT_EN);
|
||||
if (!state)
|
||||
val |= VGA_DDC_DATA_OUT_EN;
|
||||
OUTREG(chan->ddc_reg, val);
|
||||
(void) INREG(chan->ddc_reg);
|
||||
}
|
||||
|
||||
static int radeon_gpio_getscl(void* data)
|
||||
{
|
||||
struct radeon_i2c_chan *chan = data;
|
||||
struct radeonfb_info *rinfo = chan->rinfo;
|
||||
unsigned long val;
|
||||
|
||||
val = INREG(chan->ddc_reg);
|
||||
return (val & VGA_DDC_CLK_INPUT) ? 1 : 0;
|
||||
}
|
||||
|
||||
static int radeon_gpio_getsda(void* data)
|
||||
{
|
||||
struct radeon_i2c_chan *chan = data;
|
||||
struct radeonfb_info *rinfo = chan->rinfo;
|
||||
unsigned long val;
|
||||
val = INREG(chan->ddc_reg);
|
||||
return(val & VGA_DDC_DATA_INPUT) ? 1 : 0;
|
||||
}
|
||||
|
||||
static int radeon_setup_i2c_bus(struct radeon_i2c_chan *chan)
|
||||
{
|
||||
int rc;
|
||||
chan->adapter.algo_data = &chan->algo;
|
||||
chan->algo.setsda = radeon_gpio_setsda;
|
||||
chan->algo.setscl = radeon_gpio_setscl;
|
||||
chan->algo.getsda = radeon_gpio_getsda;
|
||||
chan->algo.getscl = radeon_gpio_getscl;
|
||||
chan->algo.udelay = 40;
|
||||
chan->algo.timeout = 20;
|
||||
chan->algo.data = chan;
|
||||
/* Raise SCL and SDA */
|
||||
radeon_gpio_setsda(chan, 1);
|
||||
radeon_gpio_setscl(chan, 1);
|
||||
udelay(20);
|
||||
rc = i2c_bit_add_bus(&chan->adapter);
|
||||
return rc;
|
||||
}
|
||||
|
||||
void radeon_create_i2c_busses(struct radeonfb_info *rinfo)
|
||||
{
|
||||
rinfo->i2c[0].rinfo = rinfo;
|
||||
rinfo->i2c[0].ddc_reg = GPIO_MONID;
|
||||
radeon_setup_i2c_bus(&rinfo->i2c[0]);
|
||||
rinfo->i2c[1].rinfo = rinfo;
|
||||
rinfo->i2c[1].ddc_reg = GPIO_DVI_DDC;
|
||||
radeon_setup_i2c_bus(&rinfo->i2c[1]);
|
||||
rinfo->i2c[2].rinfo = rinfo;
|
||||
rinfo->i2c[2].ddc_reg = GPIO_VGA_DDC;
|
||||
radeon_setup_i2c_bus(&rinfo->i2c[2]);
|
||||
rinfo->i2c[3].rinfo = rinfo;
|
||||
rinfo->i2c[3].ddc_reg = GPIO_CRT2_DDC;
|
||||
radeon_setup_i2c_bus(&rinfo->i2c[3]);
|
||||
}
|
||||
|
||||
#if 0
|
||||
void radeon_delete_i2c_busses(struct radeonfb_info *rinfo)
|
||||
{
|
||||
if(rinfo->i2c[0].rinfo)
|
||||
i2c_bit_del_bus(&rinfo->i2c[0].adapter);
|
||||
rinfo->i2c[0].rinfo = NULL;
|
||||
if(rinfo->i2c[1].rinfo)
|
||||
i2c_bit_del_bus(&rinfo->i2c[1].adapter);
|
||||
rinfo->i2c[1].rinfo = NULL;
|
||||
if(rinfo->i2c[2].rinfo)
|
||||
i2c_bit_del_bus(&rinfo->i2c[2].adapter);
|
||||
rinfo->i2c[2].rinfo = NULL;
|
||||
if(rinfo->i2c[3].rinfo)
|
||||
i2c_bit_del_bus(&rinfo->i2c[3].adapter);
|
||||
rinfo->i2c[3].rinfo = NULL;
|
||||
}
|
||||
#endif
|
||||
|
||||
static unsigned char *radeon_do_probe_i2c_edid(struct radeon_i2c_chan *chan)
|
||||
{
|
||||
unsigned char start = 0x0;
|
||||
struct i2c_msg msgs[] =
|
||||
{
|
||||
{
|
||||
.addr = RADEON_DDC,
|
||||
.len = 1,
|
||||
.buf = &start,
|
||||
},
|
||||
{
|
||||
.addr = RADEON_DDC,
|
||||
.flags = I2C_M_RD,
|
||||
.len = EDID_LENGTH,
|
||||
},
|
||||
};
|
||||
|
||||
unsigned char *buf;
|
||||
|
||||
buf = driver_mem_alloc(EDID_LENGTH * 3);
|
||||
if (!buf)
|
||||
return NULL;
|
||||
|
||||
msgs[1].buf = buf;
|
||||
if (i2c_transfer(&chan->adapter, msgs, 2) == 2)
|
||||
return buf;
|
||||
else
|
||||
dbg("i2c_transfer() failed\r\n");
|
||||
|
||||
driver_mem_free(buf);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
int32_t radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int32_t conn, uint8_t **out_edid)
|
||||
{
|
||||
unsigned long reg = rinfo->i2c[conn - 1].ddc_reg;
|
||||
unsigned char *edid = NULL;
|
||||
int i, j;
|
||||
|
||||
OUTREG(reg, INREG(reg) & ~(VGA_DDC_DATA_OUTPUT | VGA_DDC_CLK_OUTPUT));
|
||||
OUTREG(reg, INREG(reg) & ~(VGA_DDC_CLK_OUT_EN));
|
||||
(void) INREG(reg);
|
||||
|
||||
for(i = 0; i < 3; i++)
|
||||
{
|
||||
/* For some old monitors we need the
|
||||
* following process to initialize/stop DDC
|
||||
*/
|
||||
OUTREG(reg, INREG(reg) & ~(VGA_DDC_DATA_OUT_EN));
|
||||
(void)INREG(reg);
|
||||
wait_ms(13);
|
||||
|
||||
OUTREG(reg, INREG(reg) & ~(VGA_DDC_CLK_OUT_EN));
|
||||
(void)INREG(reg);
|
||||
|
||||
for(j = 0; j < 5; j++)
|
||||
{
|
||||
wait_ms(10);
|
||||
if (INREG(reg) & VGA_DDC_CLK_INPUT)
|
||||
break;
|
||||
}
|
||||
|
||||
if (j == 5)
|
||||
continue;
|
||||
|
||||
OUTREG(reg, INREG(reg) | VGA_DDC_DATA_OUT_EN);
|
||||
(void) INREG(reg);
|
||||
wait_ms(15);
|
||||
|
||||
OUTREG(reg, INREG(reg) | VGA_DDC_CLK_OUT_EN);
|
||||
(void) INREG(reg);
|
||||
wait_ms(15);
|
||||
|
||||
OUTREG(reg, INREG(reg) & ~(VGA_DDC_DATA_OUT_EN));
|
||||
(void) INREG(reg);
|
||||
wait_ms(15);
|
||||
|
||||
/* Do the real work */
|
||||
edid = radeon_do_probe_i2c_edid(&rinfo->i2c[conn - 1]);
|
||||
OUTREG(reg, INREG(reg) | (VGA_DDC_DATA_OUT_EN | VGA_DDC_CLK_OUT_EN));
|
||||
(void) INREG(reg);
|
||||
wait_ms(15);
|
||||
OUTREG(reg, INREG(reg) & ~(VGA_DDC_CLK_OUT_EN));
|
||||
(void) INREG(reg);
|
||||
for(j = 0; j < 10; j++)
|
||||
{
|
||||
wait_ms(10);
|
||||
if (INREG(reg) & VGA_DDC_CLK_INPUT)
|
||||
break;
|
||||
}
|
||||
OUTREG(reg, INREG(reg) & ~(VGA_DDC_DATA_OUT_EN));
|
||||
(void) INREG(reg);
|
||||
wait_ms(15);
|
||||
|
||||
OUTREG(reg, INREG(reg) | (VGA_DDC_DATA_OUT_EN | VGA_DDC_CLK_OUT_EN));
|
||||
(void) INREG(reg);
|
||||
|
||||
if (edid)
|
||||
break;
|
||||
}
|
||||
/* Release the DDC lines when done or the Apple Cinema HD display
|
||||
* will switch off */
|
||||
OUTREG(reg, INREG(reg) & ~(VGA_DDC_CLK_OUT_EN | VGA_DDC_DATA_OUT_EN));
|
||||
(void) INREG(reg);
|
||||
|
||||
if (out_edid)
|
||||
*out_edid = edid;
|
||||
|
||||
if (!edid)
|
||||
return MT_NONE;
|
||||
|
||||
if (edid[0x14] & 0x80)
|
||||
{
|
||||
/* Fix detection using BIOS tables */
|
||||
if(rinfo->is_mobility /*&& conn == ddc_dvi*/ && (INREG(LVDS_GEN_CNTL) & LVDS_ON))
|
||||
return MT_LCD;
|
||||
else
|
||||
return MT_DFP;
|
||||
}
|
||||
return MT_CRT;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_FB_RADEON_I2C */
|
||||
748
radeon/radeon_monitor.c
Normal file
748
radeon/radeon_monitor.c
Normal file
@@ -0,0 +1,748 @@
|
||||
#include "radeonfb.h"
|
||||
#include "wait.h"
|
||||
#include "edid.h"
|
||||
#include "driver_mem.h"
|
||||
#include "bas_printf.h"
|
||||
#include "bas_string.h"
|
||||
#include "video.h"
|
||||
|
||||
// #define DEBUG
|
||||
#include "debug.h"
|
||||
|
||||
#ifndef INT_MAX
|
||||
#define INT_MAX ((int) (~0U >> 1))
|
||||
#endif
|
||||
|
||||
static struct fb_var_screeninfo radeonfb_default_var =
|
||||
{
|
||||
.xres = 640,
|
||||
.yres = 480,
|
||||
.xres_virtual = 640,
|
||||
.yres_virtual = 480,
|
||||
.bits_per_pixel = 8,
|
||||
.red = { .length = 8 },
|
||||
.green = { .length = 8 },
|
||||
.blue = { .length = 8 },
|
||||
.activate = FB_ACTIVATE_NOW,
|
||||
.height = -1,
|
||||
.width = -1,
|
||||
.pixclock = 9295,
|
||||
.left_margin = 40,
|
||||
.right_margin = 24,
|
||||
.upper_margin = 32,
|
||||
.lower_margin = 11,
|
||||
.hsync_len = 96,
|
||||
.vsync_len = 2,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
};
|
||||
|
||||
char *radeon_get_mon_name(int type)
|
||||
{
|
||||
char *pret = NULL;
|
||||
switch(type)
|
||||
{
|
||||
case MT_NONE:
|
||||
pret = "no";
|
||||
break;
|
||||
case MT_CRT:
|
||||
pret = "CRT";
|
||||
break;
|
||||
case MT_DFP:
|
||||
pret = "DFP";
|
||||
break;
|
||||
case MT_LCD:
|
||||
pret = "LCD";
|
||||
break;
|
||||
case MT_CTV:
|
||||
pret = "CTV";
|
||||
break;
|
||||
case MT_STV:
|
||||
pret = "STV";
|
||||
break;
|
||||
}
|
||||
return pret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Probe physical connection of a CRT. This code comes from XFree
|
||||
* as well and currently is only implemented for the CRT DAC, the
|
||||
* code for the TVDAC is commented out in XFree as "non working"
|
||||
*/
|
||||
static int radeon_crt_is_connected(struct radeonfb_info *rinfo, int is_crt_dac)
|
||||
{
|
||||
int connected = 0;
|
||||
/*
|
||||
* the monitor either wasn't connected or it is a non-DDC CRT.
|
||||
* try to probe it
|
||||
*/
|
||||
if (is_crt_dac)
|
||||
{
|
||||
unsigned long ulOrigVCLK_ECP_CNTL;
|
||||
unsigned long ulOrigDAC_CNTL;
|
||||
unsigned long ulOrigDAC_EXT_CNTL;
|
||||
unsigned long ulOrigCRTC_EXT_CNTL;
|
||||
unsigned long ulData;
|
||||
unsigned long ulMask;
|
||||
|
||||
ulOrigVCLK_ECP_CNTL = INPLL(VCLK_ECP_CNTL);
|
||||
ulData = ulOrigVCLK_ECP_CNTL;
|
||||
ulData &= ~(PIXCLK_ALWAYS_ONb | PIXCLK_DAC_ALWAYS_ONb);
|
||||
ulMask = ~(PIXCLK_ALWAYS_ONb | PIXCLK_DAC_ALWAYS_ONb);
|
||||
OUTPLLP(VCLK_ECP_CNTL, ulData, ulMask);
|
||||
ulOrigCRTC_EXT_CNTL = INREG(CRTC_EXT_CNTL);
|
||||
ulData = ulOrigCRTC_EXT_CNTL;
|
||||
ulData |= CRTC_CRT_ON;
|
||||
OUTREG(CRTC_EXT_CNTL, ulData);
|
||||
ulOrigDAC_EXT_CNTL = INREG(DAC_EXT_CNTL);
|
||||
ulData = ulOrigDAC_EXT_CNTL;
|
||||
ulData &= ~DAC_FORCE_DATA_MASK;
|
||||
ulData |= (DAC_FORCE_BLANK_OFF_EN | DAC_FORCE_DATA_EN | DAC_FORCE_DATA_SEL_MASK);
|
||||
if ((rinfo->family == CHIP_FAMILY_RV250) || (rinfo->family == CHIP_FAMILY_RV280))
|
||||
ulData |= (0x01b6 << DAC_FORCE_DATA_SHIFT);
|
||||
else
|
||||
ulData |= (0x01ac << DAC_FORCE_DATA_SHIFT);
|
||||
OUTREG(DAC_EXT_CNTL, ulData);
|
||||
ulOrigDAC_CNTL = INREG(DAC_CNTL);
|
||||
ulData = ulOrigDAC_CNTL;
|
||||
ulData |= DAC_CMP_EN;
|
||||
ulData &= ~(DAC_RANGE_CNTL_MASK | DAC_PDWN);
|
||||
ulData |= 0x2;
|
||||
OUTREG(DAC_CNTL, ulData);
|
||||
wait_ms(1);
|
||||
ulData = INREG(DAC_CNTL);
|
||||
connected = (DAC_CMP_OUTPUT & ulData) ? 1 : 0;
|
||||
ulData = ulOrigVCLK_ECP_CNTL;
|
||||
ulMask = 0xFFFFFFFFL;
|
||||
OUTPLLP(VCLK_ECP_CNTL, ulData, ulMask);
|
||||
OUTREG(DAC_CNTL, ulOrigDAC_CNTL);
|
||||
OUTREG(DAC_EXT_CNTL, ulOrigDAC_EXT_CNTL );
|
||||
OUTREG(CRTC_EXT_CNTL, ulOrigCRTC_EXT_CNTL);
|
||||
}
|
||||
return connected ? MT_CRT : MT_NONE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Parse the "monitor_layout" string if any. This code is mostly
|
||||
* copied from XFree's radeon driver
|
||||
*/
|
||||
static int radeon_parse_monitor_layout(struct radeonfb_info *rinfo, const char *monitor_layout)
|
||||
{
|
||||
char s1[5], s2[5];
|
||||
int i = 0, second = 0;
|
||||
const char *s;
|
||||
|
||||
if ((monitor_layout == NULL) || (*monitor_layout == '\0'))
|
||||
{
|
||||
dbg("monitor_layout missing\r\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
s = monitor_layout;
|
||||
do
|
||||
{
|
||||
switch (*s)
|
||||
{
|
||||
case ',':
|
||||
s1[i] = '\0';
|
||||
i = 0;
|
||||
second = 1;
|
||||
break;
|
||||
|
||||
case ' ':
|
||||
case '\0':
|
||||
break;
|
||||
|
||||
default:
|
||||
if (i >= 4)
|
||||
break;
|
||||
if (second)
|
||||
s2[i] = *s;
|
||||
else
|
||||
s1[i] = *s;
|
||||
i++;
|
||||
break;
|
||||
}
|
||||
} while(*s++);
|
||||
|
||||
if (second)
|
||||
s2[i] = '\0';
|
||||
else
|
||||
{
|
||||
s1[i] = '\0';
|
||||
s2[0] = '\0';
|
||||
}
|
||||
|
||||
dbg("s1=%s, s2=%s \r\n", s1, s2);
|
||||
|
||||
if (!strcmp(s1, "CRT"))
|
||||
{
|
||||
rinfo->mon1_type = MT_CRT;
|
||||
dbg("monitor 1 set to CRT\r\n");
|
||||
}
|
||||
else if (!strcmp(s1, "TMDS"))
|
||||
{
|
||||
rinfo->mon1_type = MT_DFP;
|
||||
dbg("monitor 1 set to TMDS\r\n");
|
||||
}
|
||||
else if (!strcmp(s1, "LVDS"))
|
||||
{
|
||||
rinfo->mon1_type = MT_LCD;
|
||||
dbg("monitor 1 set to LVDS\r\n");
|
||||
}
|
||||
|
||||
if (!strcmp(s2, "CRT"))
|
||||
{
|
||||
rinfo->mon2_type = MT_CRT;
|
||||
dbg("monitor 2 set to CRT\r\n");
|
||||
}
|
||||
else if (!strcmp(s2, "TMDS"))
|
||||
{
|
||||
rinfo->mon2_type = MT_DFP;
|
||||
dbg("monitor 2 set to TMDS\r\n");
|
||||
}
|
||||
else if (!strcmp(s2, "LVDS"))
|
||||
{
|
||||
rinfo->mon2_type = MT_LCD;
|
||||
dbg("monitor 2 set to LVDS\r\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Probe display on both primary and secondary card's connector (if any)
|
||||
* by i2c and try to retreive EDID. The algorithm here comes from XFree's * radeon driver
|
||||
*/
|
||||
void radeon_probe_screens(struct radeonfb_info *rinfo, const char *monitor_layout, int32_t ignore_edid)
|
||||
{
|
||||
|
||||
#ifdef CONFIG_FB_RADEON_I2C
|
||||
int ddc_crt2_used = 0;
|
||||
#endif
|
||||
|
||||
dbg("monitor_layout=%s\r\n", monitor_layout);
|
||||
if (radeon_parse_monitor_layout(rinfo, monitor_layout))
|
||||
{
|
||||
/*
|
||||
* If user specified a monitor_layout option, use it instead
|
||||
* of auto-detecting. Maybe we should only use this argument
|
||||
* on the first radeon card probed or provide a way to specify
|
||||
* a layout for each card ?
|
||||
*/
|
||||
#ifdef CONFIG_FB_RADEON_I2C
|
||||
dbg("use monitor layout\r\n");
|
||||
if (!ignore_edid)
|
||||
{
|
||||
if (rinfo->mon1_type != MT_NONE)
|
||||
{
|
||||
dbg("probe ddc_dvi on MON1\r\n");
|
||||
if (!radeon_probe_i2c_connector(rinfo, ddc_dvi, &rinfo->mon1_EDID))
|
||||
{
|
||||
dbg("probe ddc_crt2 on MON1\r\n");
|
||||
radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon1_EDID);
|
||||
ddc_crt2_used = 1;
|
||||
}
|
||||
}
|
||||
if (rinfo->mon2_type != MT_NONE)
|
||||
{
|
||||
dbg("probe ddc_vga on MON2\r\n");
|
||||
if (!radeon_probe_i2c_connector(rinfo, ddc_vga, &rinfo->mon2_EDID) && !ddc_crt2_used)
|
||||
{
|
||||
dbg("probe ddc_crt2 on MON2\r\n");
|
||||
radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon2_EDID);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_FB_RADEON_I2C */
|
||||
if (rinfo->mon1_type == MT_NONE)
|
||||
{
|
||||
if (rinfo->mon2_type != MT_NONE)
|
||||
{
|
||||
rinfo->mon1_type = rinfo->mon2_type;
|
||||
rinfo->mon1_EDID = rinfo->mon2_EDID;
|
||||
}
|
||||
else
|
||||
{
|
||||
rinfo->mon1_type = MT_CRT;
|
||||
dbg("No valid monitor, assuming CRT on first port\r\n");
|
||||
}
|
||||
rinfo->mon2_type = MT_NONE;
|
||||
rinfo->mon2_EDID = NULL;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* Auto-detecting display type (well... trying to ...)
|
||||
*/
|
||||
#ifdef CONFIG_FB_RADEON_I2C
|
||||
dbg("Auto-detecting\r\n");
|
||||
#endif
|
||||
#if 0 //#if DEBUG && defined(CONFIG_FB_RADEON_I2C)
|
||||
{
|
||||
unsigned char *EDIDs[4] = { NULL, NULL, NULL, NULL };
|
||||
int mon_types[4] = {MT_NONE, MT_NONE, MT_NONE, MT_NONE};
|
||||
int i;
|
||||
for(i = 0; i < 4; i++)
|
||||
mon_types[i] = radeon_probe_i2c_connector(rinfo, i+1, &EDIDs[i]);
|
||||
}
|
||||
#endif /* DEBUG */
|
||||
/*
|
||||
* Old single head cards
|
||||
*/
|
||||
if (!rinfo->has_CRTC2)
|
||||
{
|
||||
#ifdef CONFIG_FB_RADEON_I2C
|
||||
if (rinfo->mon1_type == MT_NONE)
|
||||
{
|
||||
dbg("probe ddc_dvi on MON1\r\n");
|
||||
rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_dvi, &rinfo->mon1_EDID);
|
||||
}
|
||||
if (rinfo->mon1_type == MT_NONE)
|
||||
{
|
||||
dbg("probe ddc_vga on MON1\r\n");
|
||||
rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_vga, &rinfo->mon1_EDID);
|
||||
}
|
||||
if (rinfo->mon1_type == MT_NONE)
|
||||
{
|
||||
dbg("probe ddc_crt2 on MON1\r\n");
|
||||
rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon1_EDID);
|
||||
}
|
||||
#endif /* CONFIG_FB_RADEON_I2C */
|
||||
if (rinfo->mon1_type == MT_NONE)
|
||||
rinfo->mon1_type = MT_CRT;
|
||||
goto bail;
|
||||
}
|
||||
/*
|
||||
* Probe primary head (DVI or laptop internal panel)
|
||||
*/
|
||||
#ifdef CONFIG_FB_RADEON_I2C
|
||||
if (rinfo->mon1_type == MT_NONE)
|
||||
{
|
||||
dbg("probe ddc_dvi on MON1\r\n");
|
||||
rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_dvi, &rinfo->mon1_EDID);
|
||||
}
|
||||
if (rinfo->mon1_type == MT_NONE)
|
||||
{
|
||||
dbg("probe ddc_crt2 on MON1\r\n");
|
||||
rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon1_EDID);
|
||||
if (rinfo->mon1_type != MT_NONE)
|
||||
ddc_crt2_used = 1;
|
||||
}
|
||||
#endif /* CONFIG_FB_RADEON_I2C */
|
||||
if (rinfo->mon1_type == MT_NONE && rinfo->is_mobility
|
||||
&& (INREG(LVDS_GEN_CNTL) & LVDS_ON))
|
||||
{
|
||||
rinfo->mon1_type = MT_LCD;
|
||||
dbg("Non-DDC laptop panel detected\r\n");
|
||||
}
|
||||
if (rinfo->mon1_type == MT_NONE)
|
||||
rinfo->mon1_type = radeon_crt_is_connected(rinfo, rinfo->reversed_DAC);
|
||||
/*
|
||||
* Probe secondary head (mostly VGA, can be DVI)
|
||||
*/
|
||||
#ifdef CONFIG_FB_RADEON_I2C
|
||||
if (rinfo->mon2_type == MT_NONE)
|
||||
{
|
||||
dbg("probe ddc_vga on MON2\r\n");
|
||||
rinfo->mon2_type = radeon_probe_i2c_connector(rinfo, ddc_vga, &rinfo->mon2_EDID);
|
||||
}
|
||||
if (rinfo->mon2_type == MT_NONE && !ddc_crt2_used)
|
||||
{
|
||||
dbg("probe ddc_crt2 on MON2\r\n");
|
||||
rinfo->mon2_type = radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon2_EDID);
|
||||
}
|
||||
#endif /* CONFIG_FB_RADEON_I2C */
|
||||
if (rinfo->mon2_type == MT_NONE)
|
||||
rinfo->mon2_type = radeon_crt_is_connected(rinfo, !rinfo->reversed_DAC);
|
||||
/*
|
||||
* If we only detected port 2, we swap them, if none detected,
|
||||
* assume CRT (maybe fallback to old BIOS_SCRATCH stuff ? or look
|
||||
* at FP registers ?)
|
||||
*/
|
||||
if (rinfo->mon1_type == MT_NONE)
|
||||
{
|
||||
if (rinfo->mon2_type != MT_NONE)
|
||||
{
|
||||
rinfo->mon1_type = rinfo->mon2_type;
|
||||
rinfo->mon1_EDID = rinfo->mon2_EDID;
|
||||
}
|
||||
else
|
||||
rinfo->mon1_type = MT_CRT;
|
||||
|
||||
rinfo->mon2_type = MT_NONE;
|
||||
rinfo->mon2_EDID = NULL;
|
||||
}
|
||||
/*
|
||||
* Deal with reversed TMDS
|
||||
*/
|
||||
if (rinfo->reversed_TMDS)
|
||||
{
|
||||
/* Always keep internal TMDS as primary head */
|
||||
if (rinfo->mon1_type == MT_DFP || rinfo->mon2_type == MT_DFP)
|
||||
{
|
||||
int tmp_type = rinfo->mon1_type;
|
||||
unsigned char *tmp_EDID = rinfo->mon1_EDID;
|
||||
rinfo->mon1_type = rinfo->mon2_type;
|
||||
rinfo->mon1_EDID = rinfo->mon2_EDID;
|
||||
rinfo->mon2_type = tmp_type;
|
||||
rinfo->mon2_EDID = tmp_EDID;
|
||||
if (rinfo->mon1_type == MT_CRT || rinfo->mon2_type == MT_CRT)
|
||||
rinfo->reversed_DAC ^= 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (ignore_edid)
|
||||
{
|
||||
driver_mem_free(rinfo->mon1_EDID);
|
||||
rinfo->mon1_EDID = NULL;
|
||||
driver_mem_free(rinfo->mon2_EDID);
|
||||
rinfo->mon2_EDID = NULL;
|
||||
}
|
||||
|
||||
bail:
|
||||
dbg("Monitor 1 type %s found\r\n", radeon_get_mon_name(rinfo->mon1_type));
|
||||
if (rinfo->mon1_EDID)
|
||||
{
|
||||
dbg("EDID probed\r\n");
|
||||
}
|
||||
|
||||
if (!rinfo->has_CRTC2)
|
||||
return;
|
||||
dbg("Monitor 2 type %s\r\n", radeon_get_mon_name(rinfo->mon2_type));
|
||||
if (rinfo->mon2_EDID)
|
||||
{
|
||||
dbg("EDID probed\r\n");
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Fill up panel infos from a mode definition, either returned by the EDID
|
||||
* or from the default mode when we can't do any better
|
||||
*/
|
||||
static void radeon_var_to_panel_info(struct radeonfb_info *rinfo, struct fb_var_screeninfo *var)
|
||||
{
|
||||
rinfo->panel_info.xres = var->xres;
|
||||
rinfo->panel_info.yres = var->yres;
|
||||
rinfo->panel_info.clock = 100000000 / var->pixclock;
|
||||
rinfo->panel_info.hOver_plus = var->right_margin;
|
||||
rinfo->panel_info.hSync_width = var->hsync_len;
|
||||
rinfo->panel_info.hblank = var->left_margin + (var->right_margin + var->hsync_len);
|
||||
rinfo->panel_info.vOver_plus = var->lower_margin;
|
||||
rinfo->panel_info.vSync_width = var->vsync_len;
|
||||
rinfo->panel_info.vblank = var->upper_margin + (var->lower_margin + var->vsync_len);
|
||||
rinfo->panel_info.hAct_high = (var->sync & FB_SYNC_HOR_HIGH_ACT) != 0;
|
||||
rinfo->panel_info.vAct_high = (var->sync & FB_SYNC_VERT_HIGH_ACT) != 0;
|
||||
rinfo->panel_info.valid = 1;
|
||||
|
||||
/*
|
||||
* We use a default of 200ms for the panel power delay,
|
||||
* I need to have a real schedule() instead of mdelay's in the panel code.
|
||||
* we might be possible to figure out a better power delay either from
|
||||
* MacOS OF tree or from the EDID block (proprietary extensions ?)
|
||||
*/
|
||||
rinfo->panel_info.pwr_delay = 200;
|
||||
}
|
||||
|
||||
static void radeon_videomode_to_var(struct fb_var_screeninfo *var,
|
||||
const struct fb_videomode *mode)
|
||||
{
|
||||
var->xres = mode->xres;
|
||||
var->yres = mode->yres;
|
||||
var->xres_virtual = mode->xres;
|
||||
var->yres_virtual = mode->yres;
|
||||
var->xoffset = 0;
|
||||
var->yoffset = 0;
|
||||
var->pixclock = mode->pixclock;
|
||||
var->left_margin = mode->left_margin;
|
||||
var->right_margin = mode->right_margin;
|
||||
var->upper_margin = mode->upper_margin;
|
||||
var->lower_margin = mode->lower_margin;
|
||||
var->hsync_len = mode->hsync_len;
|
||||
var->vsync_len = mode->vsync_len;
|
||||
var->sync = mode->sync;
|
||||
var->vmode = mode->vmode;
|
||||
}
|
||||
|
||||
/*
|
||||
* Build the modedb for head 1 (head 2 will come later), check panel infos
|
||||
* from either BIOS or EDID, and pick up the default mode
|
||||
*/
|
||||
void radeon_check_modes(struct radeonfb_info *rinfo, struct mode_option *resolution)
|
||||
{
|
||||
struct fb_info *info = rinfo->info;
|
||||
int has_default_mode = 0;
|
||||
struct mode_option xres_yres;
|
||||
dbg("\r\n");
|
||||
|
||||
/*
|
||||
* Fill default var first
|
||||
*/
|
||||
memcpy(&info->var, &radeonfb_default_var, sizeof(struct fb_var_screeninfo));
|
||||
|
||||
/*
|
||||
* Parse EDID detailed timings and deduce panel infos if any. Right now
|
||||
* we only deal with first entry returned by parse_EDID, we may do better
|
||||
* some day...
|
||||
*/
|
||||
if (!rinfo->panel_info.use_bios_dividers
|
||||
&& rinfo->mon1_type != MT_CRT && rinfo->mon1_EDID)
|
||||
{
|
||||
struct fb_var_screeninfo var;
|
||||
|
||||
dbg("fb_parse_edid\r\n");
|
||||
if (fb_parse_edid(rinfo->mon1_EDID, &var) == 0)
|
||||
{
|
||||
if ((var.xres >= rinfo->panel_info.xres) && (var.yres >= rinfo->panel_info.yres))
|
||||
radeon_var_to_panel_info(rinfo, &var);
|
||||
}
|
||||
else
|
||||
{
|
||||
dbg("no data to parse\r\n");
|
||||
}
|
||||
}
|
||||
/*
|
||||
* If we have some valid panel infos, we setup the default mode based on
|
||||
* those
|
||||
*/
|
||||
if (rinfo->mon1_type != MT_CRT && rinfo->panel_info.valid)
|
||||
{
|
||||
struct fb_var_screeninfo *var = &info->var;
|
||||
|
||||
dbg("setup the default mode based on panel info\r\n");
|
||||
var->xres = rinfo->panel_info.xres;
|
||||
var->yres = rinfo->panel_info.yres;
|
||||
var->xres_virtual = rinfo->panel_info.xres;
|
||||
var->yres_virtual = rinfo->panel_info.yres;
|
||||
var->xoffset = var->yoffset = 0;
|
||||
var->bits_per_pixel = 8;
|
||||
var->pixclock = 100000000 / rinfo->panel_info.clock;
|
||||
var->left_margin = (rinfo->panel_info.hblank - rinfo->panel_info.hOver_plus - rinfo->panel_info.hSync_width);
|
||||
var->right_margin = rinfo->panel_info.hOver_plus;
|
||||
var->upper_margin = (rinfo->panel_info.vblank - rinfo->panel_info.vOver_plus - rinfo->panel_info.vSync_width);
|
||||
var->lower_margin = rinfo->panel_info.vOver_plus;
|
||||
var->hsync_len = rinfo->panel_info.hSync_width;
|
||||
var->vsync_len = rinfo->panel_info.vSync_width;
|
||||
var->sync = 0;
|
||||
|
||||
if (rinfo->panel_info.hAct_high)
|
||||
var->sync |= FB_SYNC_HOR_HIGH_ACT;
|
||||
|
||||
if (rinfo->panel_info.vAct_high)
|
||||
var->sync |= FB_SYNC_VERT_HIGH_ACT;
|
||||
|
||||
var->vmode = 0;
|
||||
has_default_mode = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Now build modedb from EDID
|
||||
*/
|
||||
if (rinfo->mon1_EDID)
|
||||
{
|
||||
fb_edid_to_monspecs(rinfo->mon1_EDID, &info->monspecs);
|
||||
rinfo->mon1_modedb = info->monspecs.modedb;
|
||||
rinfo->mon1_dbsize = info->monspecs.modedb_len;
|
||||
}
|
||||
/*
|
||||
* Finally, if we don't have panel infos we need to figure some (or
|
||||
* we try to read it from card), we try to pick a default mode
|
||||
* and create some panel infos. Whatever...
|
||||
*/
|
||||
if (rinfo->mon1_type != MT_CRT && !rinfo->panel_info.valid)
|
||||
{
|
||||
struct fb_videomode *modedb;
|
||||
int dbsize;
|
||||
|
||||
if (rinfo->panel_info.xres == 0 || rinfo->panel_info.yres == 0)
|
||||
{
|
||||
unsigned long tmp = INREG(FP_HORZ_STRETCH) & HORZ_PANEL_SIZE;
|
||||
|
||||
rinfo->panel_info.xres = ((tmp >> HORZ_PANEL_SHIFT) + 1) * 8;
|
||||
|
||||
tmp = INREG(FP_VERT_STRETCH) & VERT_PANEL_SIZE;
|
||||
rinfo->panel_info.yres = (tmp >> VERT_PANEL_SHIFT) + 1;
|
||||
}
|
||||
|
||||
if ((rinfo->panel_info.xres <= 8) || (rinfo->panel_info.yres <= 1))
|
||||
{
|
||||
rinfo->mon1_type = MT_CRT;
|
||||
goto pickup_default;
|
||||
}
|
||||
modedb = rinfo->mon1_modedb;
|
||||
dbsize = rinfo->mon1_dbsize;
|
||||
xres_yres.used = 1;
|
||||
xres_yres.width = rinfo->panel_info.xres;
|
||||
xres_yres.height = rinfo->panel_info.yres;
|
||||
xres_yres.bpp = xres_yres.freq = 0;
|
||||
if (fb_find_mode(&info->var, info, &xres_yres, modedb, dbsize, NULL,
|
||||
(resolution->bpp >= 8) ? (unsigned int)resolution->bpp : 8) == 0)
|
||||
{
|
||||
rinfo->mon1_type = MT_CRT;
|
||||
goto pickup_default;
|
||||
}
|
||||
has_default_mode = 1;
|
||||
radeon_var_to_panel_info(rinfo, &info->var);
|
||||
}
|
||||
|
||||
pickup_default:
|
||||
|
||||
/*
|
||||
* Apply passed-in mode option if any
|
||||
*/
|
||||
if (resolution->used)
|
||||
{
|
||||
if (fb_find_mode(&info->var, info, resolution, info->monspecs.modedb,
|
||||
info->monspecs.modedb_len, NULL, (resolution->bpp >= 8) ? (unsigned int)resolution->bpp : 8) != 0)
|
||||
has_default_mode = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Still no mode, let's pick up a default from the db
|
||||
*/
|
||||
if (!has_default_mode && info->monspecs.modedb != NULL)
|
||||
{
|
||||
struct fb_monspecs *specs = &info->monspecs;
|
||||
struct fb_videomode *modedb = NULL;
|
||||
|
||||
/* get preferred timing */
|
||||
if (specs->misc & FB_MISC_1ST_DETAIL)
|
||||
{
|
||||
int i;
|
||||
for(i = 0; i < specs->modedb_len; i++)
|
||||
{
|
||||
if (specs->modedb[i].flag & FB_MODE_IS_FIRST)
|
||||
{
|
||||
modedb = &specs->modedb[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* otherwise, get first mode in database */
|
||||
modedb = &specs->modedb[0];
|
||||
}
|
||||
|
||||
if (modedb != NULL)
|
||||
{
|
||||
info->var.bits_per_pixel = 8;
|
||||
radeon_videomode_to_var(&info->var, modedb);
|
||||
has_default_mode = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* The code below is used to pick up a mode in check_var and
|
||||
* set_var. It should be made generic
|
||||
*/
|
||||
|
||||
/*
|
||||
* This is used when looking for modes. We assign a "distance" value
|
||||
* to a mode in the modedb depending how "close" it is from what we
|
||||
* are looking for.
|
||||
* Currently, we don't compare that much, we could do better but
|
||||
* the current fbcon doesn't quite mind ;)
|
||||
*/
|
||||
static int radeon_compare_modes(const struct fb_var_screeninfo *var,
|
||||
const struct fb_videomode *mode)
|
||||
{
|
||||
int distance = 0;
|
||||
|
||||
distance = mode->yres - var->yres;
|
||||
distance += (mode->xres - var->xres)/2;
|
||||
|
||||
return distance;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is called by check_var, it gets the passed in mode parameter, and
|
||||
* outputs a valid mode matching the passed-in one as closely as possible.
|
||||
* We need something better ultimately.
|
||||
*/
|
||||
int32_t radeon_match_mode(struct radeonfb_info *rinfo,
|
||||
struct fb_var_screeninfo *dest,
|
||||
const struct fb_var_screeninfo *src)
|
||||
{
|
||||
const struct fb_videomode *db = vesa_modes;
|
||||
int i, dbsize = 34;
|
||||
int has_rmx, native_db = 0;
|
||||
int distance = INT_MAX;
|
||||
const struct fb_videomode *candidate = NULL;
|
||||
|
||||
dbg("\r\n");
|
||||
|
||||
/* Start with a copy of the requested mode */
|
||||
memcpy(dest, src, sizeof(struct fb_var_screeninfo));
|
||||
|
||||
/* Check if we have a modedb built from EDID */
|
||||
if (rinfo->mon1_modedb)
|
||||
{
|
||||
db = rinfo->mon1_modedb;
|
||||
dbsize = rinfo->mon1_dbsize;
|
||||
native_db = 1;
|
||||
}
|
||||
/* Check if we have a scaler allowing any fancy mode */
|
||||
has_rmx = (rinfo->mon1_type == MT_LCD) || (rinfo->mon1_type == MT_DFP);
|
||||
|
||||
/* If we have a scaler and are passed FB_ACTIVATE_TEST or
|
||||
* FB_ACTIVATE_NOW, just do basic checking and return if the
|
||||
* mode match
|
||||
*/
|
||||
if ((src->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_TEST
|
||||
|| (src->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
|
||||
{
|
||||
/* We don't have an RMX, validate timings. If we don't have
|
||||
* monspecs, we should be paranoid and not let use go above
|
||||
* 640x480-60, but I assume userland knows what it's doing here
|
||||
* (though I may be proven wrong...)
|
||||
*/
|
||||
if ((has_rmx == 0) && rinfo->mon1_modedb)
|
||||
{
|
||||
if (fb_validate_mode((struct fb_var_screeninfo *)src, rinfo->info))
|
||||
return -1; //-EINVAL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
dbg("look for a mode in the database\r\n");
|
||||
|
||||
/* Now look for a mode in the database */
|
||||
while(db)
|
||||
{
|
||||
for (i = 0; i < dbsize; i++)
|
||||
{
|
||||
int d;
|
||||
|
||||
if ((db[i].yres < src->yres) || (db[i].xres < src->xres))
|
||||
continue;
|
||||
d = radeon_compare_modes(src, &db[i]);
|
||||
/* If the new mode is at least as good as the previous one,
|
||||
* then it's our new candidate
|
||||
*/
|
||||
if (d < distance)
|
||||
{
|
||||
candidate = &db[i];
|
||||
distance = d;
|
||||
}
|
||||
}
|
||||
db = NULL;
|
||||
/* If we have a scaler, we allow any mode from the database */
|
||||
if (native_db && has_rmx)
|
||||
{
|
||||
db = vesa_modes;
|
||||
dbsize = 34;
|
||||
native_db = 0;
|
||||
}
|
||||
}
|
||||
/* If we have found a match, return it */
|
||||
if (candidate != NULL)
|
||||
{
|
||||
radeon_videomode_to_var(dest, candidate);
|
||||
return 0;
|
||||
}
|
||||
/* If we haven't and don't have a scaler, fail */
|
||||
if (!has_rmx)
|
||||
return -1; //-EINVAL;
|
||||
return 0;
|
||||
}
|
||||
188
spi/dspi.c
Normal file
188
spi/dspi.c
Normal file
@@ -0,0 +1,188 @@
|
||||
/*
|
||||
* dspi.c
|
||||
*
|
||||
* Coldfire DSPI (DMA Serial Peripherial Interface).
|
||||
*
|
||||
* On the Coldfire, the DSPI interface supports 4 SPI output channels and one input channel.
|
||||
* On the Firebee, DSPICS5 is connected to the SD card slot.
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 16.10.2013
|
||||
* Author: mfro
|
||||
*/
|
||||
|
||||
#include <bas_types.h>
|
||||
#include <MCF5475.h>
|
||||
|
||||
struct baudrate
|
||||
{
|
||||
int br_divisor;
|
||||
int pbr_divisor;
|
||||
int divider;
|
||||
};
|
||||
|
||||
static const int system_clock = 132000000; /* System clock in Hz */
|
||||
|
||||
static struct baudrate baudrates[] =
|
||||
{
|
||||
{ 0b0000, 0b00, 4 },
|
||||
{ 0b0000, 0b01, 6 },
|
||||
{ 0b0001, 0b00, 8 },
|
||||
{ 0b0000, 0b10, 10 },
|
||||
{ 0b0001, 0b01, 12 },
|
||||
{ 0b0010, 0b00, 12 },
|
||||
{ 0b0000, 0b11, 14 },
|
||||
{ 0b0011, 0b00, 16 },
|
||||
{ 0b0010, 0b01, 18 },
|
||||
{ 0b0001, 0b10, 20 },
|
||||
{ 0b0011, 0b01, 24 },
|
||||
{ 0b0001, 0b11, 28 },
|
||||
{ 0b0010, 0b10, 30 },
|
||||
{ 0b0100, 0b00, 32 },
|
||||
{ 0b0011, 0b10, 40 },
|
||||
{ 0b0010, 0b11, 42 },
|
||||
{ 0b0100, 0b01, 48 },
|
||||
{ 0b0011, 0b11, 56 },
|
||||
{ 0b0101, 0b00, 64 },
|
||||
{ 0b0100, 0b10, 80 },
|
||||
{ 0b0101, 0b01, 96 },
|
||||
{ 0b0100, 0b11, 112 },
|
||||
{ 0b0110, 0b00, 128 },
|
||||
{ 0b0101, 0b10, 160 },
|
||||
{ 0b0110, 0b01, 192 },
|
||||
{ 0b0101, 0b11, 224 },
|
||||
{ 0b0111, 0b00, 256 },
|
||||
{ 0b0110, 0b10, 320 },
|
||||
{ 0b0111, 0b01, 384 },
|
||||
{ 0b0110, 0b11, 448 },
|
||||
{ 0b1000, 0b00, 512 },
|
||||
{ 0b0111, 0b10, 640 },
|
||||
{ 0b1000, 0b01, 768 },
|
||||
{ 0b0111, 0b11, 896 },
|
||||
{ 0b1001, 0b00, 1024 },
|
||||
{ 0b1000, 0b10, 1280 },
|
||||
{ 0b1001, 0b01, 1536 },
|
||||
{ 0b1000, 0b11, 1792 },
|
||||
{ 0b1010, 0b00, 2048 },
|
||||
{ 0b1001, 0b10, 2560 },
|
||||
{ 0b1010, 0b01, 3072 },
|
||||
{ 0b1001, 0b11, 3584 },
|
||||
{ 0b1011, 0b00, 4096 },
|
||||
{ 0b1010, 0b10, 5120 },
|
||||
{ 0b1011, 0b01, 6144 },
|
||||
{ 0b1010, 0b11, 7168 },
|
||||
{ 0b1100, 0b00, 8192 },
|
||||
{ 0b1011, 0b10, 10240 },
|
||||
{ 0b1100, 0b01, 12288 },
|
||||
{ 0b1011, 0b11, 14336 },
|
||||
{ 0b1101, 0b00, 16384 },
|
||||
{ 0b1100, 0b10, 20480 },
|
||||
{ 0b1101, 0b01, 24576 },
|
||||
{ 0b1100, 0b11, 28672 },
|
||||
{ 0b1110, 0b00, 32768 },
|
||||
{ 0b1101, 0b10, 40960 },
|
||||
{ 0b1110, 0b01, 49152 },
|
||||
{ 0b1101, 0b11, 57344 },
|
||||
{ 0b1111, 0b00, 65536 },
|
||||
{ 0b1110, 0b10, 81920 },
|
||||
{ 0b1111, 0b01, 98304 },
|
||||
{ 0b1110, 0b11, 114688 },
|
||||
{ 0b1111, 0b10, 163840 },
|
||||
{ 0b1111, 0b11, 229376 },
|
||||
};
|
||||
|
||||
/*
|
||||
* set the dspi clock to rate or - if no exact match possible - to the next lower possible baudrate
|
||||
*/
|
||||
int dspi_set_baudrate(int rate)
|
||||
{
|
||||
int set_baudrate = 0;
|
||||
int br;
|
||||
int pbr;
|
||||
int i;
|
||||
|
||||
for (i = sizeof(baudrates) / sizeof(struct baudrate) - 1; i >= 0; i--)
|
||||
{
|
||||
set_baudrate = system_clock / baudrates[i].divider;
|
||||
|
||||
if (set_baudrate > rate)
|
||||
{
|
||||
continue;
|
||||
}
|
||||
br = baudrates[i].br_divisor;
|
||||
pbr = baudrates[i].pbr_divisor;
|
||||
|
||||
/* TODO: set br and pbr here */
|
||||
(void) pbr;
|
||||
(void) br;
|
||||
return set_baudrate;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uint32_t dspi_fifo_val = MCF_DSPI_DTFR_CTCNT;
|
||||
|
||||
/*
|
||||
* Exchange a byte. If last is false (0), there will be more bytes to follow (EOQ flag in DTFR left unset)
|
||||
*/
|
||||
uint8_t dspi_xchg_byte(int device, uint8_t byte, int last)
|
||||
{
|
||||
uint32_t fifo;
|
||||
uint8_t res;
|
||||
|
||||
fifo = dspi_fifo_val | (byte & 0xff); /* transfer bytes only */
|
||||
fifo |= (last ? MCF_DSPI_DTFR_EOQ : 0); /* mark last transfer */
|
||||
MCF_DSPI_DTFR = fifo;
|
||||
while (! (MCF_DSPI_DSR & MCF_DSPI_DSR_TCF)); /* wait until DSPI transfer complete */
|
||||
fifo = MCF_DSPI_DRFR; /* read transferred word */
|
||||
|
||||
MCF_DSPI_DSR = -1; /* clear DSPI status register */
|
||||
|
||||
res = fifo & 0xff;
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
/* Receive multiple byte with 0xff as output
|
||||
*
|
||||
* buff: pointer to data buffer
|
||||
* btr: number of bytes to receive (16, 64 or 512)
|
||||
*/
|
||||
void dspi_rcv_byte_multi(int device, uint8_t *buff, uint32_t count)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < count - 1; i++)
|
||||
*buff++ = dspi_xchg_byte(device, 0xff, 0);
|
||||
*buff++ = dspi_xchg_byte(device, 0xff, 1); /* transfer last byte and stop transmission */
|
||||
}
|
||||
|
||||
/* Send multiple byte, discard input
|
||||
*
|
||||
* buff: pointer to data
|
||||
* btx: number of bytes to send
|
||||
*/
|
||||
void dspi_xmt_byte_multi(int device, const uint8_t *buff, uint32_t btx)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < btx - 1; i++)
|
||||
dspi_xchg_byte(device, *buff++, 0);
|
||||
dspi_xchg_byte(device, *buff++, 1); /* transfer last byte and indicate end of transmission */
|
||||
}
|
||||
|
||||
814
spi/mmc.c
Normal file
814
spi/mmc.c
Normal file
@@ -0,0 +1,814 @@
|
||||
#include <bas_types.h>
|
||||
#include <sd_card.h>
|
||||
#include <bas_printf.h>
|
||||
#include <sysinit.h>
|
||||
#include <wait.h>
|
||||
#include <MCF5475.h>
|
||||
|
||||
/*
|
||||
* Firebee: MMCv3/SDv1/SDv2 (SPI mode) control module
|
||||
*
|
||||
*
|
||||
* Copyright (C) 2011, ChaN, all right reserved.
|
||||
*
|
||||
* This software is a free software and there is NO WARRANTY.
|
||||
* No restriction on use. You can use, modify and redistribute it for
|
||||
* personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY.
|
||||
* Redistributions of source code must retain the above copyright notice.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Copyright (C) 2012, mfro, all rights reserved. */
|
||||
|
||||
// // #define DEBUG_MMC
|
||||
#ifdef DEBUG_MMC
|
||||
#define debug_printf(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg); } while (0)
|
||||
#else
|
||||
#define debug_printf(format, arg...) do { ; } while (0)
|
||||
#endif /* DEBUG_MMC */
|
||||
|
||||
#define CS_LOW() { dspi_fifo_val |= MCF_DSPI_DTFR_CS5; }
|
||||
#define CS_HIGH() { dspi_fifo_val &= ~MCF_DSPI_DTFR_CS5; }
|
||||
|
||||
/*
|
||||
* DCTAR_PBR (baud rate prescaler) and DCTAR_BR (baud rate scaler) together determine the SPI baud rate. The forumula is
|
||||
*
|
||||
* baud rate = system clock / DCTAR_PBR * 1 / DCTAR_BR.
|
||||
*
|
||||
* System clock for the Firebee is 133 MHZ.
|
||||
*
|
||||
* The SPICLK_FAST() example calculates as follows: baud rate = 133 MHz / 3 * 1 / 2 = 22,16 MHz
|
||||
* SPICLK_SLOW() should be between 100 and 400 kHz: 133 MHz / 1 * 1 / 1024 = 129 kHz
|
||||
*/
|
||||
#define SPICLK_FAST() { MCF_DSPI_DCTAR0 = MCF_DSPI_DCTAR_TRSZ(0b0111) | /* transfer size = 8 bit */ \
|
||||
MCF_DSPI_DCTAR_PCSSCK(0b01) | /* 3 clock DSPICS to DSPISCK delay prescaler */ \
|
||||
MCF_DSPI_DCTAR_PASC_3CLK | /* 3 clock DSPISCK to DSPICS negation prescaler */ \
|
||||
MCF_DSPI_DCTAR_PDT_3CLK | /* 3 clock delay between DSPICS assertions prescaler */ \
|
||||
MCF_DSPI_DCTAR_PBR_1CLK | /* 3 clock baudrate prescaler */ \
|
||||
MCF_DSPI_DCTAR_CSSCK(1) | /* delay scaler * 4 */\
|
||||
MCF_DSPI_DCTAR_ASC(0b0001) | /* 2 */ \
|
||||
MCF_DSPI_DCTAR_DT(0b0010) | /* 2 */ \
|
||||
MCF_DSPI_DCTAR_BR(0b0001); } /* clock / 2 */
|
||||
|
||||
#define SPICLK_SLOW() { \
|
||||
MCF_DSPI_DCTAR0 = MCF_DSPI_DCTAR_TRSZ(0b111) | /* transfer size = 8 bit */ \
|
||||
MCF_DSPI_DCTAR_PCSSCK(0b01) | /* 3 clock DSPICS to DSPISCK delay prescaler */ \
|
||||
MCF_DSPI_DCTAR_PASC_3CLK | /* 3 clock DSPISCK to DSPICS negation prescaler */ \
|
||||
MCF_DSPI_DCTAR_PDT_3CLK | /* 3 clock delay between DSPICS assertions prescaler */ \
|
||||
MCF_DSPI_DCTAR_PBR_3CLK | /* 1 clock baudrate prescaler */ \
|
||||
MCF_DSPI_DCTAR_CSSCK(8) | /* delay scaler * 512 */\
|
||||
MCF_DSPI_DCTAR_ASC(8) | /* 2 */ \
|
||||
MCF_DSPI_DCTAR_DT(9) | /* 2 */ \
|
||||
MCF_DSPI_DCTAR_BR(7); \
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------------------
|
||||
|
||||
Module Private Functions
|
||||
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
#include "diskio.h"
|
||||
|
||||
|
||||
/* MMC/SD command */
|
||||
#define CMD0 (0) /* GO_IDLE_STATE */
|
||||
#define CMD1 (1) /* SEND_OP_COND (MMC) */
|
||||
#define ACMD41 (0x80+41) /* SEND_OP_COND (SDC) */
|
||||
#define CMD8 (8) /* SEND_IF_COND */
|
||||
#define CMD9 (9) /* SEND_CSD */
|
||||
#define CMD10 (10) /* SEND_CID */
|
||||
#define CMD12 (12) /* STOP_TRANSMISSION */
|
||||
#define ACMD13 (0x80+13) /* SD_STATUS (SDC) */
|
||||
#define CMD16 (16) /* SET_BLOCKLEN */
|
||||
#define CMD17 (17) /* READ_SINGLE_BLOCK */
|
||||
#define CMD18 (18) /* READ_MULTIPLE_BLOCK */
|
||||
#define CMD23 (23) /* SET_BLOCK_COUNT (MMC) */
|
||||
#define ACMD23 (0x80+23) /* SET_WR_BLK_ERASE_COUNT (SDC) */
|
||||
#define CMD24 (24) /* WRITE_BLOCK */
|
||||
#define CMD25 (25) /* WRITE_MULTIPLE_BLOCK */
|
||||
#define CMD32 (32) /* ERASE_ER_BLK_START */
|
||||
#define CMD33 (33) /* ERASE_ER_BLK_END */
|
||||
#define CMD38 (38) /* ERASE */
|
||||
#define CMD55 (55) /* APP_CMD */
|
||||
#define CMD58 (58) /* READ_OCR */
|
||||
|
||||
|
||||
static volatile DSTATUS Stat = 0 /* STA_NOINIT */; /* Physical drive status */
|
||||
static uint8_t CardType; /* Card type flags */
|
||||
|
||||
|
||||
static uint32_t dspi_fifo_val = MCF_DSPI_DTFR_CTCNT;
|
||||
|
||||
/*-----------------------------------------------------------------------*/
|
||||
/* Send/Receive data to the MMC (Platform dependent) */
|
||||
/*-----------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Exchange a byte. If last is false (0), there will be more bytes to follow (EOQ flag in DTFR left unset)
|
||||
*/
|
||||
static uint8_t xchg_spi(uint8_t byte, int last)
|
||||
{
|
||||
uint32_t fifo;
|
||||
uint8_t res;
|
||||
|
||||
fifo = dspi_fifo_val | (byte & 0xff); /* transfer bytes only */
|
||||
//fifo |= (last ? MCF_DSPI_DTFR_EOQ : 0); /* mark last transfer */
|
||||
MCF_DSPI_DTFR = fifo;
|
||||
while (! (MCF_DSPI_DSR & MCF_DSPI_DSR_TCF)); /* wait until DSPI transfer complete */
|
||||
fifo = MCF_DSPI_DRFR; /* read transferred word */
|
||||
|
||||
MCF_DSPI_DSR = -1; /* clear DSPI status register */
|
||||
|
||||
res = fifo & 0xff;
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
|
||||
/* Receive multiple byte
|
||||
*
|
||||
* buff: pointer to data buffer
|
||||
* btr: number of bytes to receive (16, 64 or 512)
|
||||
*/
|
||||
static void rcvr_spi_multi(uint8_t *buff, uint32_t count)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < count - 1; i++)
|
||||
*buff++ = xchg_spi(0xff, 0);
|
||||
*buff++ = xchg_spi(0xff, 1); /* transfer last byte and stop transmission */
|
||||
}
|
||||
|
||||
|
||||
#if _USE_WRITE
|
||||
/* Send multiple byte
|
||||
*
|
||||
* buff: pointer to data
|
||||
* btx: number of bytes to send
|
||||
*/
|
||||
static void xmit_spi_multi(const uint8_t *buff, uint32_t btx)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < btx - 1; i++)
|
||||
xchg_spi(*buff++, 0);
|
||||
xchg_spi(*buff++, 1); /* transfer last byte and indicate end of transmission */
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
static bool card_ready(void)
|
||||
{
|
||||
uint8_t d;
|
||||
|
||||
d = xchg_spi(0xff, 1);
|
||||
return (d == 0xff);
|
||||
}
|
||||
|
||||
/*
|
||||
* Wait for card ready
|
||||
*
|
||||
* wt: timeout in ns
|
||||
* returns 1: ready, 0: timeout
|
||||
*/
|
||||
static int wait_ready(uint32_t wt)
|
||||
{
|
||||
return waitfor(wt * 1000, card_ready);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Deselect card and release SPI
|
||||
*/
|
||||
static void deselect(void)
|
||||
{
|
||||
CS_HIGH();
|
||||
wait_ready(50); /* Dummy clock (force DO hi-z for multiple slave SPI) */
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Select card and wait for ready
|
||||
*/
|
||||
|
||||
static int select(void) /* 1:OK, 0:Timeout */
|
||||
{
|
||||
CS_LOW();
|
||||
|
||||
if (wait_ready(500))
|
||||
return 1; /* OK */
|
||||
deselect();
|
||||
return 0; /* Timeout */
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Control SPI module (Platform dependent)
|
||||
*/
|
||||
static void power_on(void) /* Enable SSP module */
|
||||
{
|
||||
MCF_PAD_PAR_DSPI = 0x1fff; /* configure all DSPI GPIO pins for DSPI usage */
|
||||
dspi_fifo_val = MCF_DSPI_DTFR_CTCNT;
|
||||
/*
|
||||
* initialize DSPI module configuration register
|
||||
*/
|
||||
MCF_DSPI_DMCR = MCF_DSPI_DMCR_MSTR | /* FireBee is DSPI master*/
|
||||
MCF_DSPI_DMCR_CSIS5 | /* CS5 inactive state high */
|
||||
MCF_DSPI_DMCR_CSIS3 | /* CS3 inactive state high */
|
||||
MCF_DSPI_DMCR_CSIS2 | /* CS2 inactive state high */
|
||||
MCF_DSPI_DMCR_CSIS0 | /* CS0 inactive state high */
|
||||
MCF_DSPI_DMCR_DTXF | /* disable transmit FIFO */
|
||||
MCF_DSPI_DMCR_DRXF | /* disable receive FIFO */
|
||||
MCF_DSPI_DMCR_CTXF | /* clear transmit FIFO */
|
||||
MCF_DSPI_DMCR_CRXF; /* clear receive FIFO */
|
||||
|
||||
/* initialize DSPI clock and transfer attributes register 0 */
|
||||
SPICLK_SLOW();
|
||||
|
||||
CS_HIGH(); /* Set CS# high */
|
||||
|
||||
/* card should now be initialized as MMC */
|
||||
|
||||
wait(10 * 1000); /* 10ms */
|
||||
}
|
||||
|
||||
|
||||
static void power_off (void) /* Disable SPI function */
|
||||
{
|
||||
select(); /* Wait for card ready */
|
||||
deselect();
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------*/
|
||||
/* Receive a data packet from the MMC */
|
||||
/*-----------------------------------------------------------------------*/
|
||||
static int rcvr_datablock(uint8_t *buff, uint32_t btr)
|
||||
{
|
||||
uint8_t token;
|
||||
int32_t target = MCF_SLT_SCNT(0) - (200L * 1000L * 132L);
|
||||
|
||||
do { /* Wait for DataStart token in timeout of 200ms */
|
||||
token = xchg_spi(0xFF, 0);
|
||||
} while ((token == 0xFF) && MCF_SLT_SCNT(0) - target > 0);
|
||||
|
||||
if (token == 0xff)
|
||||
{
|
||||
debug_printf("no data start token received after 2000ms in rcvr_datablock\r\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (token != 0xFE)
|
||||
{
|
||||
debug_printf("invalid token (%x) in rcvr_datablock()!\r\n", token);
|
||||
return 0; /* Function fails if invalid DataStart token or timeout */
|
||||
}
|
||||
|
||||
rcvr_spi_multi(buff, btr); /* Store trailing data to the buffer */
|
||||
|
||||
xchg_spi(0xFF, 1);
|
||||
xchg_spi(0xFF, 1); /* Discard CRC */
|
||||
|
||||
return 1; /* Function succeeded */
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------*/
|
||||
/* Send a data packet to the MMC */
|
||||
/*-----------------------------------------------------------------------*/
|
||||
|
||||
#if _USE_WRITE
|
||||
static int xmit_datablock(const uint8_t *buff, uint8_t token)
|
||||
{
|
||||
uint8_t resp;
|
||||
|
||||
|
||||
if (!wait_ready(500))
|
||||
{
|
||||
debug_printf("card did not respond ready after 500 ms in xmit_datablock()\r\n");
|
||||
return 0; /* Wait for card ready */
|
||||
}
|
||||
|
||||
xchg_spi(token, 1); /* Send token */
|
||||
if (token != 0xFD) { /* Send data if token is other than StopTran */
|
||||
xmit_spi_multi(buff, 512); /* Data */
|
||||
xchg_spi(0xFF, 1);
|
||||
xchg_spi(0xFF, 1); /* Dummy CRC */
|
||||
|
||||
resp = xchg_spi(0xFF, 1); /* Receive data resp */
|
||||
if ((resp & 0x1F) != 0x05) /* Function fails if the data packet was not accepted */
|
||||
{
|
||||
debug_printf("card did not accept data packet in xmit_datablock() (resp = %x)\r\n", resp & 0x1F);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
wait_ready(30);
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------*/
|
||||
/* Send a command packet to the MMC */
|
||||
/*-----------------------------------------------------------------------*/
|
||||
|
||||
static uint8_t send_cmd(uint8_t cmd, uint32_t arg)
|
||||
{
|
||||
int n;
|
||||
int res;
|
||||
|
||||
if (cmd & 0x80)
|
||||
{ /* Send a CMD55 prior to ACMD<n> */
|
||||
cmd &= 0x7F;
|
||||
res = send_cmd(CMD55, 0);
|
||||
if (res > 1)
|
||||
return res;
|
||||
}
|
||||
|
||||
/* Select card */
|
||||
deselect();
|
||||
if (!select())
|
||||
{
|
||||
debug_printf("card could not be selected in send_cmd()\r\n");
|
||||
return 0xFF;
|
||||
}
|
||||
|
||||
if (!wait_ready(500))
|
||||
{
|
||||
debug_printf("card did not respond ready after 5000 ms in send_cmd()\r\n");
|
||||
return 0xff; /* Wait for card ready */
|
||||
}
|
||||
|
||||
/* Send command packet */
|
||||
xchg_spi(0x40 | cmd, 0); /* Start + command index */
|
||||
xchg_spi((uint8_t)(arg >> 24), 0); /* Argument[31..24] */
|
||||
xchg_spi((uint8_t)(arg >> 16), 0); /* Argument[23..16] */
|
||||
xchg_spi((uint8_t)(arg >> 8), 0); /* Argument[15..8] */
|
||||
xchg_spi((uint8_t)arg, 1); /* Argument[7..0] */
|
||||
|
||||
n = 0x01; /* Dummy CRC + Stop */
|
||||
if (cmd == CMD0)
|
||||
n = 0x95; /* Valid CRC for CMD0(0) */
|
||||
if (cmd == CMD8)
|
||||
n = 0x87; /* Valid CRC for CMD8(0x1AA) */
|
||||
xchg_spi(n, 0);
|
||||
|
||||
/* Receive command resp */
|
||||
if (cmd == CMD12)
|
||||
{
|
||||
xchg_spi(0xFF, 0); /* Discard following one byte when CMD12 */
|
||||
}
|
||||
|
||||
n = 1000; /* Wait for response (1000 bytes max) */
|
||||
do
|
||||
res = xchg_spi(0xFF, 1);
|
||||
while ((res & 0x80) && --n);
|
||||
return res; /* Return received response */
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------------------
|
||||
|
||||
Public Functions
|
||||
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
/*
|
||||
* Initialize disk drive
|
||||
*
|
||||
* drv: physical drive number (0)
|
||||
*/
|
||||
DSTATUS disk_initialize(uint8_t drv)
|
||||
{
|
||||
uint8_t n, cmd, card_type, ocr[4];
|
||||
|
||||
if (drv)
|
||||
return STA_NOINIT; /* Supports only drive 0 */
|
||||
|
||||
power_on(); /* Initialize SPI */
|
||||
|
||||
if (Stat & STA_NODISK)
|
||||
return Stat; /* Is card existing in the socket? */
|
||||
|
||||
SPICLK_SLOW();
|
||||
|
||||
for (n = 10; n; n--)
|
||||
xchg_spi(0xFF, 1); /* Send 80 dummy clocks */
|
||||
|
||||
card_type = 0;
|
||||
if (send_cmd(CMD0, 0) == 1)
|
||||
{
|
||||
/* Put the card SPI/Idle state */
|
||||
int32_t target;
|
||||
|
||||
if (send_cmd(CMD8, 0x1AA) == 1) { /* SDv2? */
|
||||
for (n = 0; n < 4; n++)
|
||||
ocr[n] = xchg_spi(0xFF, 1); /* Get 32 bit return value of R7 resp */
|
||||
if (ocr[2] == 0x01 && ocr[3] == 0xAA)
|
||||
{
|
||||
int res;
|
||||
|
||||
/* Is the card supports vcc of 2.7-3.6V? */
|
||||
target = MCF_SLT_SCNT(0) - (1000L * 1000L * 132); /* 1 sec */
|
||||
while (MCF_SLT_SCNT(0) - target > 0)
|
||||
{
|
||||
res = send_cmd(ACMD41, 1UL << 30); /* Wait for end of initialization with ACMD41(HCS) */
|
||||
if (res != 0xff)
|
||||
break;
|
||||
}
|
||||
debug_printf("res = %d\r\n", res);
|
||||
|
||||
target = MCF_SLT_SCNT(0) - (1000L * 1000L * 132); /* 1 sec */
|
||||
while (MCF_SLT_SCNT(0) - target > 0)
|
||||
{
|
||||
res = send_cmd(CMD58, 0); /* Check CCS bit in the OCR */
|
||||
if (res != 0xff)
|
||||
break;
|
||||
}
|
||||
debug_printf("res = %d\r\n", res);
|
||||
for (n = 0; n < 4; n++)
|
||||
ocr[n] = xchg_spi(0xFF, 1);
|
||||
card_type = (ocr[0] & 0x40) ? CT_SD2 | CT_BLOCK : CT_SD2; /* Card id SDv2 */
|
||||
}
|
||||
}
|
||||
else
|
||||
{ /* Not SDv2 card */
|
||||
if (send_cmd(ACMD41, 0) <= 1)
|
||||
{ /* SDv1 or MMC? */
|
||||
card_type = CT_SD1;
|
||||
cmd = ACMD41; /* SDv1 (ACMD41(0)) */
|
||||
} else {
|
||||
card_type = CT_MMC;
|
||||
cmd = CMD1; /* MMCv3 (CMD1(0)) */
|
||||
}
|
||||
target = MCF_SLT_SCNT(0) - (1000L * 1000L * 132); /* 1 sec */
|
||||
while (MCF_SLT_SCNT(0) - target > 0 && send_cmd(cmd, 0)); /* Wait for end of initialization */
|
||||
|
||||
if (send_cmd(CMD16, 512) != 0) /* Set block length: 512 */
|
||||
card_type = 0;
|
||||
}
|
||||
}
|
||||
CardType = card_type; /* Card type */
|
||||
|
||||
#ifdef DEBUG
|
||||
{
|
||||
uint8_t buff[16];
|
||||
res = disk_ioctl(0, MMC_GET_CSD, buff);
|
||||
|
||||
if (res == RES_OK)
|
||||
{
|
||||
debug_printf("CSD of card:\r\n");
|
||||
hexdump(buff, 16);
|
||||
}
|
||||
}
|
||||
#endif /* DEBUG */
|
||||
|
||||
deselect();
|
||||
|
||||
if (card_type)
|
||||
{
|
||||
/* OK */
|
||||
|
||||
SPICLK_FAST(); /* Set fast clock */
|
||||
Stat &= ~STA_NOINIT; /* Clear STA_NOINIT flag */
|
||||
debug_printf("card type: %d\r\n", card_type);
|
||||
//res = disk_ioctl(0, MMC_GET_CSD, buff);
|
||||
/*
|
||||
if (res == RES_OK)
|
||||
{
|
||||
debug_printf("CSD of card now:\r\n");
|
||||
hexdump(buff, 16);
|
||||
}
|
||||
*/
|
||||
deselect();
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Failed */
|
||||
xprintf("no card type detected in disk_initialize()\r\n");
|
||||
power_off();
|
||||
Stat = STA_NOINIT;
|
||||
}
|
||||
|
||||
return Stat;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------*/
|
||||
/* Get disk status */
|
||||
/*-----------------------------------------------------------------------*/
|
||||
|
||||
DSTATUS disk_status(uint8_t drv)
|
||||
{
|
||||
if (drv) return STA_NOINIT; /* Supports only drive 0 */
|
||||
|
||||
return Stat; /* Return disk status */
|
||||
}
|
||||
|
||||
DSTATUS disk_reset(uint8_t drv)
|
||||
{
|
||||
if (drv) return STA_NOINIT;
|
||||
|
||||
deselect();
|
||||
disk_initialize(0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------*/
|
||||
/* Read sector(s) */
|
||||
/*-----------------------------------------------------------------------*/
|
||||
|
||||
DRESULT disk_read(uint8_t drv, uint8_t *buff, uint32_t sector, uint8_t count)
|
||||
{
|
||||
if (drv)
|
||||
{
|
||||
debug_printf("wrong drive in disk_read()\r\n");
|
||||
return RES_PARERR; /* Check parameter */
|
||||
}
|
||||
|
||||
if (! count)
|
||||
{
|
||||
debug_printf("wrong count in disk_read()\r\n");
|
||||
return RES_PARERR;
|
||||
}
|
||||
|
||||
if (Stat & STA_NOINIT)
|
||||
{
|
||||
debug_printf("drive not ready in disk_read()\r\n");
|
||||
return RES_NOTRDY; /* Check if drive is ready */
|
||||
}
|
||||
|
||||
if (!(CardType & CT_BLOCK)) sector *= 512; /* LBA or BA conversion (byte addressing cards) */
|
||||
|
||||
if (count == 1) { /* Single sector read */
|
||||
if ((send_cmd(CMD17, sector) == 0)) /* READ_SINGLE_BLOCK */
|
||||
if (rcvr_datablock(buff, 512))
|
||||
count = 0;
|
||||
}
|
||||
else { /* Multiple sector read */
|
||||
if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */
|
||||
do {
|
||||
if (!rcvr_datablock(buff, 512))
|
||||
break;
|
||||
buff += 512;
|
||||
} while (--count);
|
||||
send_cmd(CMD12, 0); /* STOP_TRANSMISSION */
|
||||
}
|
||||
}
|
||||
deselect();
|
||||
|
||||
return count ? RES_ERROR : RES_OK; /* Return result */
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------*/
|
||||
/* Write sector(s) */
|
||||
/*-----------------------------------------------------------------------*/
|
||||
|
||||
#if _USE_WRITE
|
||||
DRESULT disk_write(uint8_t drv, const uint8_t *buff, uint32_t sector, uint8_t count)
|
||||
{
|
||||
int res;
|
||||
|
||||
if (drv || !count) return RES_PARERR; /* Check parameter */
|
||||
if (Stat & STA_NOINIT) return RES_NOTRDY; /* Check drive status */
|
||||
if (Stat & STA_PROTECT) return RES_WRPRT; /* Check write protect */
|
||||
|
||||
if (!(CardType & CT_BLOCK))
|
||||
{
|
||||
sector *= 512; /* LBA ==> BA conversion (byte addressing cards) */
|
||||
}
|
||||
|
||||
if (count == 1)
|
||||
{ /* Single sector write */
|
||||
res = send_cmd(CMD24, sector);
|
||||
if (res == 0)
|
||||
{
|
||||
count = 0;
|
||||
}
|
||||
else
|
||||
debug_printf("send_cmd(CMD24, ...) failed in disk_write()\r\n");
|
||||
|
||||
if (xmit_datablock(buff, 0xFE))
|
||||
{
|
||||
count = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
debug_printf("xmit_datablock(buff, ...) failed in disk_write()\r\n");
|
||||
}
|
||||
}
|
||||
else { /* Multiple sector write */
|
||||
if (CardType & CT_SDC) send_cmd(ACMD23, count); /* Predefine number of sectors */
|
||||
if (send_cmd(CMD25, sector) == 0)
|
||||
{ /* WRITE_MULTIPLE_BLOCK */
|
||||
do
|
||||
{
|
||||
if (!xmit_datablock(buff, 0xFC)) break;
|
||||
buff += 512;
|
||||
} while (--count);
|
||||
|
||||
if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */
|
||||
{
|
||||
count = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
deselect();
|
||||
|
||||
if (count) /* we had an error, try a reinit */
|
||||
{
|
||||
debug_printf("disk_write() failed (count=%d)\r\n", count);
|
||||
}
|
||||
|
||||
return count ? RES_ERROR : RES_OK; /* Return result */
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------*/
|
||||
/* Miscellaneous drive controls other than data read/write */
|
||||
/*-----------------------------------------------------------------------*/
|
||||
|
||||
#if _USE_IOCTL
|
||||
DRESULT disk_ioctl(uint8_t drv, uint8_t ctrl, void *buff)
|
||||
{
|
||||
DRESULT res;
|
||||
uint8_t n, csd[16], *ptr = buff;
|
||||
uint32_t *dp, st, ed, csize;
|
||||
|
||||
|
||||
if (drv) return RES_PARERR; /* Check parameter */
|
||||
if (Stat & STA_NOINIT) return RES_NOTRDY; /* Check if drive is ready */
|
||||
|
||||
res = RES_ERROR;
|
||||
|
||||
switch (ctrl) {
|
||||
case CTRL_SYNC : /* Wait for end of internal write process of the drive */
|
||||
if (select()) {
|
||||
deselect();
|
||||
res = RES_OK;
|
||||
}
|
||||
break;
|
||||
|
||||
case GET_SECTOR_COUNT : /* Get drive capacity in unit of sector (DWORD) */
|
||||
if ((send_cmd(CMD9, 0) == 0))
|
||||
{
|
||||
if (rcvr_datablock(csd, 16))
|
||||
{
|
||||
if ((csd[0] >> 6) == 1)
|
||||
{ /* SDC ver 2.00 */
|
||||
csize = csd[9] + ((uint16_t)csd[8] << 8) + ((uint32_t)(csd[7] & 63) << 16) + 1;
|
||||
* (uint32_t*) buff = csize << 10;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* SDC ver 1.XX or MMC ver 3 */
|
||||
n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2;
|
||||
csize = (csd[8] >> 6) + ((uint16_t)csd[7] << 2) + ((uint16_t)(csd[6] & 3) << 10) + 1;
|
||||
* (uint32_t*) buff = csize << (n - 9);
|
||||
}
|
||||
}
|
||||
res = RES_OK;
|
||||
}
|
||||
break;
|
||||
|
||||
case GET_SECTOR_SIZE : /* Get sector size in unit of byte (WORD) */
|
||||
* (uint32_t*) buff = 512;
|
||||
res = RES_OK;
|
||||
break;
|
||||
|
||||
case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */
|
||||
if (CardType & CT_SD2) { /* SDC ver 2.00 */
|
||||
if (send_cmd(ACMD13, 0) == 0) { /* Read SD status */
|
||||
xchg_spi(0xFF, 1);
|
||||
if (rcvr_datablock(csd, 16)) { /* Read partial block */
|
||||
for (n = 64 - 16; n; n--) xchg_spi(0xFF, 1); /* Purge trailing data */
|
||||
*(uint32_t*)buff = 16UL << (csd[10] >> 4);
|
||||
res = RES_OK;
|
||||
}
|
||||
}
|
||||
} else { /* SDC ver 1.XX or MMC */
|
||||
if ((send_cmd(CMD9, 0) == 0))
|
||||
{
|
||||
if (rcvr_datablock(csd, 16))
|
||||
{
|
||||
/* Read CSD */
|
||||
if (CardType & CT_SD1)
|
||||
{ /* SDC ver 1.XX */
|
||||
* (uint32_t*) buff = (((csd[10] & 63) << 1) + ((uint16_t)(csd[11] & 128) >> 7) + 1) << ((csd[13] >> 6) - 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* MMC */
|
||||
*(uint32_t*)buff = ((uint16_t)((csd[10] & 124) >> 2) + 1) * (((csd[11] & 3) << 3) + ((csd[11] & 224) >> 5) + 1);
|
||||
}
|
||||
}
|
||||
res = RES_OK;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case CTRL_ERASE_SECTOR : /* Erase a block of sectors (used when _USE_ERASE == 1) */
|
||||
if (!(CardType & CT_SDC)) break; /* Check if the card is SDC */
|
||||
if (disk_ioctl(drv, MMC_GET_CSD, csd)) break; /* Get CSD */
|
||||
if (!(csd[0] >> 6) && !(csd[10] & 0x40)) break; /* Check if sector erase can be applied to the card */
|
||||
dp = buff; st = dp[0]; ed = dp[1]; /* Load sector block */
|
||||
if (!(CardType & CT_BLOCK)) {
|
||||
st *= 512; ed *= 512;
|
||||
}
|
||||
if (send_cmd(CMD32, st) == 0)
|
||||
{
|
||||
if (send_cmd(CMD33, ed) == 0)
|
||||
if (send_cmd(CMD38, 0) == 0)
|
||||
if (wait_ready(30))
|
||||
; /* Erase sector block */
|
||||
}
|
||||
res = RES_OK; /* FatFs does not check result of this command */
|
||||
break;
|
||||
|
||||
/* Following command are not used by FatFs module */
|
||||
|
||||
case MMC_GET_TYPE : /* Get MMC/SDC type (BYTE) */
|
||||
*ptr = CardType;
|
||||
res = RES_OK;
|
||||
break;
|
||||
|
||||
case MMC_GET_CSD : /* Read CSD (16 bytes) */
|
||||
if (send_cmd(CMD9, 0) == 0 /* READ_CSD */
|
||||
&& rcvr_datablock(ptr, 16))
|
||||
res = RES_OK;
|
||||
break;
|
||||
|
||||
case MMC_GET_CID : /* Read CID (16 bytes) */
|
||||
if (send_cmd(CMD10, 0) == 0 /* READ_CID */
|
||||
&& rcvr_datablock(ptr, 16))
|
||||
res = RES_OK;
|
||||
break;
|
||||
|
||||
case MMC_GET_OCR : /* Read OCR (4 bytes) */
|
||||
if (send_cmd(CMD58, 0) == 0) { /* READ_OCR */
|
||||
for (n = 4; n; n--) *ptr++ = xchg_spi(0xFF, 1);
|
||||
res = RES_OK;
|
||||
}
|
||||
break;
|
||||
|
||||
case MMC_GET_SDSTAT : /* Read SD status (64 bytes) */
|
||||
if (send_cmd(ACMD13, 0) == 0) { /* SD_STATUS */
|
||||
xchg_spi(0xFF, 1);
|
||||
if (rcvr_datablock(ptr, 64))
|
||||
res = RES_OK;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
res = RES_PARERR;
|
||||
break;
|
||||
}
|
||||
|
||||
deselect();
|
||||
|
||||
return res;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------*/
|
||||
/* Device timer function */
|
||||
/*-----------------------------------------------------------------------*/
|
||||
/* This function must be called from timer interrupt routine in period
|
||||
/ of 1 ms to generate card control timing.
|
||||
*/
|
||||
|
||||
#ifdef _NOT_USED_
|
||||
void disk_timerproc (void)
|
||||
{
|
||||
uint8_t s;
|
||||
|
||||
s = Stat;
|
||||
if (WP) /* Write protected */
|
||||
s |= STA_PROTECT;
|
||||
else /* Write enabled */
|
||||
s &= ~STA_PROTECT;
|
||||
//if (INS) /* Card is in socket */
|
||||
s &= ~STA_NODISK;
|
||||
//else /* Socket empty */
|
||||
// s |= (STA_NODISK | STA_NOINIT);
|
||||
Stat = s;
|
||||
}
|
||||
#endif /* _NOT_USED_ */
|
||||
121
spi/sd_card.c
Normal file
121
spi/sd_card.c
Normal file
@@ -0,0 +1,121 @@
|
||||
/*
|
||||
* sd_card.c
|
||||
*
|
||||
* Created on: 16.12.2012
|
||||
* Author: mfro
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Copyright 2012 M. Froeschle
|
||||
*/
|
||||
|
||||
#include <sd_card.h>
|
||||
#include <diskio.h>
|
||||
#include <ff.h>
|
||||
#include <bas_printf.h>
|
||||
|
||||
#define WELCOME_NAME "WELCOME.MSG"
|
||||
#define FLASHCODE_NAME "BENCH.BIN"
|
||||
|
||||
#define FLASHCODE_ADDRESS 0x03000000L
|
||||
|
||||
/*
|
||||
* initialize SD-card and FF FAT filesystem routines. Harness to load a file during boot.
|
||||
*
|
||||
* This is currently more like a proof of concept,
|
||||
* but will be extended to load and execute a bootstrap flasher to be able to flash the Bee directly
|
||||
* from card.
|
||||
*/
|
||||
void sd_card_init(void)
|
||||
{
|
||||
DRESULT res;
|
||||
FATFS fs;
|
||||
FRESULT fres;
|
||||
|
||||
disk_initialize(0);
|
||||
res = disk_status(0);
|
||||
xprintf("disk status of SD card is %d\r\n", res);
|
||||
if (res == RES_OK)
|
||||
{
|
||||
fres = f_mount(0, &fs);
|
||||
xprintf("mount status of SD card fs is %d\r\n", fres);
|
||||
if (fres == FR_OK)
|
||||
{
|
||||
DIR directory;
|
||||
FIL file;
|
||||
|
||||
fres = f_opendir(&directory, "\\");
|
||||
if (fres == FR_OK)
|
||||
{
|
||||
FILINFO fi;
|
||||
|
||||
while (((fres = f_readdir(&directory, &fi)) == FR_OK) && fi.fname[0])
|
||||
{
|
||||
xprintf("%13.13s %d\r\n", fi.fname, fi.fsize);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
xprintf("could not open directory \"\\\" on SD-card! Error code: %d\r\n", fres);
|
||||
}
|
||||
|
||||
/*
|
||||
* let's see if we find our boot flashing executable on disk
|
||||
*/
|
||||
fres = f_open(&file, FLASHCODE_NAME, FA_READ);
|
||||
if (fres == FR_OK)
|
||||
{
|
||||
/*
|
||||
* yes, load and execute it
|
||||
*
|
||||
* FIXME: we will need some kind of user confirmation here
|
||||
* to avoid unwanted flashing or "bootsector viruses" before going productive
|
||||
*/
|
||||
uint32_t size; /* length of code piece read */
|
||||
uint32_t total_size = 0L;
|
||||
int32_t start_time = MCF_SLT_SCNT(0);
|
||||
int32_t end_time;
|
||||
int32_t time = 0;
|
||||
|
||||
while ((fres = f_read(&file, (void *) FLASHCODE_ADDRESS, 1024 * 1000, &size)) == FR_OK && size > 0)
|
||||
{
|
||||
total_size += size / 1024;
|
||||
xprintf("read hunk of %d bytes, total_size = %d kBytes\r\n", size, total_size);
|
||||
}
|
||||
end_time = MCF_SLT_SCNT(0);
|
||||
time = (end_time - start_time) / 132L;
|
||||
xprintf("result of f_read: %ld, %ld kbytes read\r\n", fres, total_size);
|
||||
xprintf("time to load %s: %ld s\r\n", FLASHCODE_NAME, time / 1000 / 100);
|
||||
xprintf("equals to about %ld kBytes/second\r\n", total_size / (time / 1000 / 100));
|
||||
|
||||
}
|
||||
f_close(&file);
|
||||
|
||||
fres = f_open(&file, WELCOME_NAME, FA_READ);
|
||||
if (fres == FR_OK)
|
||||
{
|
||||
char line[128];
|
||||
|
||||
while (f_gets(line, sizeof(line), &file))
|
||||
{
|
||||
xprintf("%s", line);
|
||||
}
|
||||
}
|
||||
f_close(&file);
|
||||
}
|
||||
f_mount(0, 0L); /* release work area */
|
||||
}
|
||||
}
|
||||
609
sys/BaS.c
Normal file
609
sys/BaS.c
Normal file
@@ -0,0 +1,609 @@
|
||||
/*
|
||||
* BaS
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Copyright 2010 - 2012 F. Aschwanden
|
||||
* Copyright 2011 - 2012 V. Riviere
|
||||
* Copyright 2012 M. Froeschle
|
||||
*/
|
||||
|
||||
#include <bas_types.h>
|
||||
|
||||
#include "MCF5475.h"
|
||||
#include "startcf.h"
|
||||
#include "sysinit.h"
|
||||
#include "util.h"
|
||||
#include "cache.h"
|
||||
#include "bas_printf.h"
|
||||
#include "bas_string.h"
|
||||
#include "bas_types.h"
|
||||
#include "bas_utils.h"
|
||||
#include "sd_card.h"
|
||||
#include "wait.h"
|
||||
|
||||
#include "ff.h"
|
||||
#include "s19reader.h"
|
||||
#include "mmu.h"
|
||||
#include "dma.h"
|
||||
#include "net.h"
|
||||
#include "eth.h"
|
||||
#include "nbuf.h"
|
||||
#include "nif.h"
|
||||
#include "fec.h"
|
||||
#include "bootp.h"
|
||||
#include "interrupts.h"
|
||||
#include "exceptions.h"
|
||||
#include "net_timer.h"
|
||||
#include "pci.h"
|
||||
#include "video.h"
|
||||
|
||||
// #define DEBUG
|
||||
#include "debug.h"
|
||||
|
||||
/* imported routines */
|
||||
extern int vec_init();
|
||||
|
||||
/* Symbols from the linker script */
|
||||
extern uint8_t _STRAM_END[];
|
||||
#define STRAM_END ((uint32_t)_STRAM_END)
|
||||
extern uint8_t _TOS[];
|
||||
#define TOS ((uint32_t)_TOS) /* final TOS location */
|
||||
extern uint8_t _FASTRAM_END[];
|
||||
#define FASTRAM_END ((uint32_t)_FASTRAM_END)
|
||||
extern uint8_t _EMUTOS[];
|
||||
#define EMUTOS ((uint32_t)_EMUTOS) /* where EmuTOS is stored in flash */
|
||||
extern uint8_t _EMUTOS_SIZE[];
|
||||
#define EMUTOS_SIZE ((uint32_t)_EMUTOS_SIZE) /* size of EmuTOS, in bytes */
|
||||
|
||||
/*
|
||||
* check if it is possible to transfer data to PIC
|
||||
*/
|
||||
static inline bool pic_txready(void)
|
||||
{
|
||||
if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_TXRDY)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/*
|
||||
* check if it is possible to receive data from PIC
|
||||
*/
|
||||
static inline bool pic_rxready(void)
|
||||
{
|
||||
if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_RXRDY)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
void write_pic_byte(uint8_t value)
|
||||
{
|
||||
/*
|
||||
* Wait until the transmitter is ready or 1000us are passed
|
||||
*/
|
||||
waitfor(1000, pic_txready);
|
||||
|
||||
/*
|
||||
* Transmit the byte
|
||||
*/
|
||||
*(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT) = value; // Really 8-bit
|
||||
}
|
||||
|
||||
uint8_t read_pic_byte(void)
|
||||
{
|
||||
/*
|
||||
* Wait until a byte has been received or 1000us are passed
|
||||
*/
|
||||
waitfor(1000, pic_rxready);
|
||||
|
||||
/*
|
||||
* Return the received byte
|
||||
*/
|
||||
return * (volatile uint8_t *) (&MCF_PSC3_PSCTB_8BIT); // Really 8-bit
|
||||
}
|
||||
|
||||
void pic_init(void)
|
||||
{
|
||||
char answer[4] = "OLD";
|
||||
|
||||
xprintf("initialize the PIC: ");
|
||||
|
||||
/*
|
||||
* Send the PIC initialization string
|
||||
*/
|
||||
write_pic_byte('A');
|
||||
write_pic_byte('C');
|
||||
write_pic_byte('P');
|
||||
write_pic_byte('F');
|
||||
|
||||
/*
|
||||
* Read the 3-char answer string. Should be "OK!".
|
||||
*/
|
||||
answer[0] = read_pic_byte();
|
||||
answer[1] = read_pic_byte();
|
||||
answer[2] = read_pic_byte();
|
||||
answer[3] = '\0';
|
||||
|
||||
if (answer[0] != 'O' || answer[1] != 'K' || answer[2] != '!')
|
||||
{
|
||||
dbg("PIC initialization failed. Already initialized?\r\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
xprintf("%s\r\n", answer);
|
||||
}
|
||||
}
|
||||
|
||||
void nvram_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
xprintf("Restore the NVRAM data: ");
|
||||
|
||||
/* Request for NVRAM backup data */
|
||||
write_pic_byte(0x01);
|
||||
|
||||
/* Check answer type */
|
||||
if (read_pic_byte() != 0x81)
|
||||
{
|
||||
// FIXME: PIC protocol error
|
||||
xprintf("FAILED\r\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Restore the NVRAM backup to the FPGA */
|
||||
for (i = 0; i < 64; i++)
|
||||
{
|
||||
uint8_t data = read_pic_byte();
|
||||
* (volatile uint8_t*) 0xffff8961 = i;
|
||||
* (volatile uint8_t*) 0xffff8963 = data;
|
||||
}
|
||||
|
||||
xprintf("finished\r\n");
|
||||
}
|
||||
|
||||
#define KBD_ACIA_CONTROL * ((uint8_t *) 0xfffffc00)
|
||||
#define MIDI_ACIA_CONTROL * ((uint8_t *) 0xfffffc04)
|
||||
#define MFP_INTR_IN_SERVICE_A * ((uint8_t *) 0xfffffa0f)
|
||||
#define MFP_INTR_IN_SERVICE_B * ((uint8_t *) 0xfffffa11)
|
||||
|
||||
void acia_init()
|
||||
{
|
||||
xprintf("init ACIA: ");
|
||||
/* init ACIA */
|
||||
KBD_ACIA_CONTROL = 3; /* master reset */
|
||||
NOP();
|
||||
|
||||
MIDI_ACIA_CONTROL = 3; /* master reset */
|
||||
NOP();
|
||||
|
||||
KBD_ACIA_CONTROL = 0x96; /* clock div = 64, 8N1, RTS low, TX int disable, RX int enable */
|
||||
NOP();
|
||||
|
||||
MFP_INTR_IN_SERVICE_A = 0xff;
|
||||
NOP();
|
||||
|
||||
MFP_INTR_IN_SERVICE_B = 0xff;
|
||||
NOP();
|
||||
|
||||
xprintf("finished\r\n");
|
||||
}
|
||||
|
||||
void enable_coldfire_interrupts()
|
||||
{
|
||||
xprintf("enable interrupts: ");
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
FBEE_INTR_CONTROL = 0L; /* disable all interrupts */
|
||||
#endif /* MACHINE_FIREBEE */
|
||||
|
||||
MCF_EPORT_EPPAR = 0xaaa8; /* all interrupts on falling edge */
|
||||
|
||||
#ifdef _NOT_USED_
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
/*
|
||||
* TIN0 on the Coldfire is connected to the FPGA. TIN0 triggers every write
|
||||
* access to 0xff8201 (vbasehi), i.e. everytime the video base address is written
|
||||
*/
|
||||
MCF_GPT0_GMS = MCF_GPT_GMS_ICT(1) | /* timer 0 on, video change capture on rising edge */
|
||||
MCF_GPT_GMS_IEN |
|
||||
MCF_GPT_GMS_TMS(1); /* route GPT0 interrupt on interrupt controller */
|
||||
MCF_INTC_ICR62 = MCF_INTC_ICR_IL(7) |
|
||||
MCF_INTC_ICR_IP(6); /* interrupt level 7, interrupt priority 6 */
|
||||
MCF_INTC_IMRH = 0xbffffffe; /* psc3 and timer 0 int on */
|
||||
#endif
|
||||
#endif
|
||||
xprintf("finished\r\n");
|
||||
}
|
||||
|
||||
void enable_pci_interrupts()
|
||||
{
|
||||
dbg("enable PCI interrupts\r\n");
|
||||
MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */
|
||||
MCF_EPORT_EPFR = 0xff; /* clear all pending interrupts */
|
||||
MCF_INTC_IMRL = 0xffffff00; /* int 1-7 on */
|
||||
MCF_INTC_IMRH = 0;
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
FBEE_INTR_ENABLE = FBEE_INTR_INT_IRQ7 | /* enable pseudo bus error */
|
||||
FBEE_INTR_INT_MFP_IRQ6 | /* enable MFP interrupts */
|
||||
FBEE_INTR_INT_FPGA_IRQ5 | /* enable Firebee (PIC, PCI, ETH PHY, DVI, DSP) interrupts */
|
||||
FBEE_INTR_INT_VSYNC_IRQ4 | /* enable vsync interrupts */
|
||||
FBEE_INTR_PCI_INTA | /* enable PCI interrupts */
|
||||
FBEE_INTR_PCI_INTB |
|
||||
FBEE_INTR_PCI_INTC |
|
||||
FBEE_INTR_PCI_INTD;
|
||||
;
|
||||
#elif defined(MACHINE_M5484LITE)
|
||||
/*
|
||||
* MCF 5484 interrupts are configured at the CPLD for the FireEngine
|
||||
*/
|
||||
|
||||
/* TODO: enable PCI interrupts on the LITEKIT */
|
||||
#elif defined(MACHINE_M54455)
|
||||
/* MCF 54455 interrupts are configured at the FPGA */
|
||||
|
||||
/* TODO: enable PCI interrupts on the MCF54455 */
|
||||
#else
|
||||
#error unknown machine!
|
||||
#endif
|
||||
}
|
||||
|
||||
void disable_coldfire_interrupts()
|
||||
{
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
FBEE_INTR_ENABLE = 0; /* disable all interrupts */
|
||||
#endif /* MACHINE_FIREBEE */
|
||||
|
||||
MCF_EPORT_EPIER = 0x0;
|
||||
MCF_INTC_IMRL = 0xfffffffe;
|
||||
MCF_INTC_IMRH = 0xffffffff;
|
||||
}
|
||||
|
||||
|
||||
|
||||
NIF nif1;
|
||||
#if defined(MACHINE_M5484LITE)
|
||||
/*
|
||||
* on the MCF 5484 LITEKIT, the second FEC interface is usable
|
||||
*/
|
||||
NIF nif2;
|
||||
#endif
|
||||
|
||||
bool spurious_interrupt_handler(void *arg1, void *arg2)
|
||||
{
|
||||
err("spurious interrupt\r\n");
|
||||
err("IMRH=%lx, IMRL=%lx\r\n", MCF_INTC_IMRH, MCF_INTC_IMRL);
|
||||
err("IPRH=%lx, IPRL=%lx\r\n", MCF_INTC_IPRH, MCF_INTC_IPRL);
|
||||
err("IRLR=%x\r\n", MCF_INTC_IRLR);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* initialize the interrupt handler tables to dispatch interrupt requests from Coldfire devices
|
||||
*/
|
||||
void init_isr(void)
|
||||
{
|
||||
isr_init(); /* need to call that explicitely, otherwise isr table might be full */
|
||||
|
||||
/*
|
||||
* register spurious interrupt handler
|
||||
*/
|
||||
if (!isr_register_handler(24, 6, 6, spurious_interrupt_handler, NULL, NULL))
|
||||
{
|
||||
dbg("unable to register spurious interrupt handler\r\n");
|
||||
}
|
||||
|
||||
/*
|
||||
* register the FEC interrupt handler
|
||||
*/
|
||||
if (!isr_register_handler(64 + INT_SOURCE_FEC0, 5, 1, fec0_interrupt_handler, NULL, (void *) &nif1))
|
||||
{
|
||||
dbg("unable to register isr for FEC0\r\n");
|
||||
}
|
||||
|
||||
/*
|
||||
* Register the DMA interrupt handler
|
||||
*/
|
||||
|
||||
if (!isr_register_handler(64 + INT_SOURCE_DMA, 5, 3, dma_interrupt_handler, NULL, NULL))
|
||||
{
|
||||
dbg("unable to register isr for DMA\r\n");
|
||||
}
|
||||
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
/*
|
||||
* register GPT0 timer interrupt vector
|
||||
*/
|
||||
if (!isr_register_handler(64 + INT_SOURCE_GPT0, 5, 2, gpt0_interrupt_handler, NULL, NULL))
|
||||
{
|
||||
dbg("unable to register isr for GPT0 timer\r\n");
|
||||
}
|
||||
|
||||
/*
|
||||
* register the PIC interrupt handler
|
||||
*/
|
||||
if (!isr_register_handler(64 + INT_SOURCE_PSC3, 5, 5, pic_interrupt_handler, NULL, NULL))
|
||||
{
|
||||
dbg("Error: unable to register ISR for PSC3\r\n");
|
||||
}
|
||||
#endif /* MACHINE_FIREBEE */
|
||||
|
||||
/*
|
||||
* register the XLB PCI interrupt handler
|
||||
*/
|
||||
if (!isr_register_handler(64 + INT_SOURCE_XLBPCI, 3, 0, xlbpci_interrupt_handler, NULL, NULL))
|
||||
{
|
||||
dbg("Error: unable to register isr for XLB PCI interrupts\r\n");
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* initialize arbiter timeout registers
|
||||
*/
|
||||
MCF_XLB_XARB_ADRTO = 0x1fffff;
|
||||
MCF_XLB_XARB_DATTO = 0x1fffff;
|
||||
MCF_XLB_XARB_BUSTO = 0xffffff;
|
||||
|
||||
|
||||
MCF_XLB_XARB_IMR = MCF_XLB_XARB_IMR_SEAE | /* slave error acknowledge interrupt */
|
||||
MCF_XLB_XARB_IMR_MME | /* multiple master at prio 0 interrupt */
|
||||
MCF_XLB_XARB_IMR_TTAE | /* TT address only interrupt */
|
||||
MCF_XLB_XARB_IMR_TTRE | /* TT reserved interrupt enable */
|
||||
MCF_XLB_XARB_IMR_ECWE | /* external control word interrupt */
|
||||
MCF_XLB_XARB_IMR_TTME | /* TBST/TSIZ mismatch interrupt */
|
||||
MCF_XLB_XARB_IMR_BAE; /* bus activity tenure timeout interrupt */
|
||||
|
||||
if (!isr_register_handler(64 + INT_SOURCE_PCIARB, 5, 0, pciarb_interrupt_handler, NULL, NULL))
|
||||
{
|
||||
dbg("Error: unable to register isr for PCIARB interrupts\r\n");
|
||||
|
||||
return;
|
||||
}
|
||||
MCF_PCIARB_PACR = MCF_PCIARB_PACR_EXTMINTEN(0x1f) | /* external master broken interrupt */
|
||||
MCF_PCIARB_PACR_INTMINTEN; /* internal master broken interrupt */
|
||||
|
||||
if (!isr_register_handler(64 + INT_SOURCE_XLBARB, 7, 1, xlbarb_interrupt_handler, NULL, NULL))
|
||||
{
|
||||
dbg("Error: unable to register isr for XLB ARB interrupts\r\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* Jump into the OS */
|
||||
typedef void void_func(void);
|
||||
struct rom_header
|
||||
{
|
||||
void *initial_sp;
|
||||
void_func *initial_pc;
|
||||
};
|
||||
|
||||
/*
|
||||
* fix ST RAM header (address 0x0 and 0x4). FreeMiNT uses these vectors on CTRL-ALT-DEL.
|
||||
*
|
||||
* Beware: Newer compilers refuse to dereference pointers to NULL and abort (trap #7) if the following
|
||||
* attribute isn't set.
|
||||
*/
|
||||
static void fix_stram_header() __attribute__((optimize("no-delete-null-pointer-checks")));
|
||||
static void fix_stram_header()
|
||||
{
|
||||
struct rom_header *bas_header = (struct rom_header *) TARGET_ADDRESS;
|
||||
struct rom_header *stram_header = (struct rom_header *) 0x0;
|
||||
|
||||
*stram_header = *bas_header;
|
||||
}
|
||||
|
||||
void BaS(void)
|
||||
{
|
||||
uint8_t *src;
|
||||
uint8_t *dst = (uint8_t *) TOS;
|
||||
|
||||
#if defined(MACHINE_FIREBEE) /* LITE board has no pic and (currently) no nvram */
|
||||
pic_init();
|
||||
nvram_init();
|
||||
#endif /* MACHINE_FIREBEE */
|
||||
|
||||
xprintf("initialize MMU: ");
|
||||
mmu_init();
|
||||
xprintf("finished\r\n");
|
||||
|
||||
xprintf("initialize Coldfire DMA: ");
|
||||
dma_init();
|
||||
xprintf("finished\r\n");
|
||||
|
||||
xprintf("copy EmuTOS: ");
|
||||
/* copy EMUTOS */
|
||||
src = (uint8_t *) EMUTOS;
|
||||
memcpy(dst, src, EMUTOS_SIZE);
|
||||
xprintf("finished\r\n");
|
||||
|
||||
xprintf("flush caches: ");
|
||||
flush_and_invalidate_caches();
|
||||
xprintf("finished\r\n");
|
||||
xprintf("enable MMU: ");
|
||||
MCF_MMU_MMUCR = MCF_MMU_MMUCR_EN; /* MMU on */
|
||||
NOP(); /* force pipeline sync */
|
||||
xprintf("finished\r\n");
|
||||
|
||||
xprintf("initialize exception vector table: ");
|
||||
vec_init();
|
||||
xprintf("finished\r\n");
|
||||
|
||||
|
||||
memset((void *) 0x0200, 0x0, 0x0400);
|
||||
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
xprintf("IDE reset: ");
|
||||
/* IDE reset */
|
||||
* (volatile uint8_t *) (0xffff8802 - 2) = 14;
|
||||
* (volatile uint8_t *) (0xffff8802 - 0) = 0x80;
|
||||
wait(1);
|
||||
|
||||
* (volatile uint8_t *) (0xffff8802 - 0) = 0;
|
||||
|
||||
xprintf("finished\r\n");
|
||||
xprintf("enable video: ");
|
||||
|
||||
/*
|
||||
* ATARI video modes "modeline"
|
||||
*
|
||||
* horizontal:
|
||||
* high word: h_total
|
||||
* low word: hsync_start
|
||||
*
|
||||
* vertical:
|
||||
* high word v_total
|
||||
* low word vsync_start
|
||||
*
|
||||
* can be calculated with umc ("universal modeline generator")
|
||||
*
|
||||
*/
|
||||
struct atari_video_timing
|
||||
{
|
||||
uint16_t total;
|
||||
uint16_t sync_start;
|
||||
};
|
||||
|
||||
static volatile struct atari_video_timing *hor_640x480 = (volatile struct atari_video_timing *) 0xf0000410;
|
||||
static volatile struct atari_video_timing *ver_640x480 = (volatile struct atari_video_timing *) 0xf0000414;
|
||||
static volatile struct atari_video_timing *hor_320x240 = (volatile struct atari_video_timing *) 0xf0000418;
|
||||
static volatile struct atari_video_timing *ver_320x240 = (volatile struct atari_video_timing *) 0xf000041c;
|
||||
|
||||
#undef VIDEO_25MHZ
|
||||
|
||||
#ifdef VIDEO_25MHZ
|
||||
hor_640x480->total = 0x320; /* 800 */
|
||||
hor_640x480->sync_start = 0x2ba; /* 698 */
|
||||
ver_640x480->total = 0x20c; /* 524 */
|
||||
ver_640x480->sync_start = 0x20a; /* 522 */
|
||||
|
||||
hor_320x240->total = 0x190; /* 400 */
|
||||
hor_320x240->sync_start = 0x15d; /* 349 */
|
||||
ver_320x240->total = 0x20c; /* 524 */
|
||||
ver_320x240->sync_start = 0x20a; /* 522 */
|
||||
#else /* 32 MHz */
|
||||
hor_640x480->total = 0x370; /* 880 */
|
||||
hor_640x480->sync_start = 0x2ba; /* 698 */
|
||||
ver_640x480->total = 0x20d; /* 525 */
|
||||
ver_640x480->sync_start = 0x20a; /* 522 */
|
||||
|
||||
hor_320x240->total = 0x2a0; /* 672 */
|
||||
hor_320x240->sync_start = 0x1e0; /* 480 */
|
||||
ver_320x240->total = 0x5a0; /* 480 */
|
||||
ver_320x240->sync_start = 0x160; /* 352 */
|
||||
#endif
|
||||
|
||||
/* fifo on, refresh on, ddrcs and cke on, video dac on */
|
||||
* (volatile uint32_t *) 0xf0000400 = 0x01070082;
|
||||
|
||||
xprintf("finished\r\n");
|
||||
#endif /* MACHINE_FIREBEE */
|
||||
|
||||
sd_card_init();
|
||||
|
||||
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
/* set Falcon bus control register */
|
||||
/* sets bit 3 and 6. Both are undefined on an original Falcon? */
|
||||
|
||||
* (volatile uint8_t *) 0xffff8007 = 0x48;
|
||||
#endif /* MACHINE_FIREBEE */
|
||||
|
||||
/* ST RAM */
|
||||
|
||||
* (uint32_t *) 0x42e = STRAM_END; /* phystop TOS system variable */
|
||||
* (uint32_t *) 0x420 = 0x752019f3; /* memvalid TOS system variable */
|
||||
* (uint32_t *) 0x43a = 0x237698aa; /* memval2 TOS system variable */
|
||||
* (uint32_t *) 0x51a = 0x5555aaaa; /* memval3 TOS system variable */
|
||||
|
||||
/* TT-RAM */
|
||||
|
||||
* (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */
|
||||
* (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */
|
||||
|
||||
#if defined(MACHINE_FIREBEE) /* m5484lite has no ACIA and no dip switch... */
|
||||
acia_init();
|
||||
#endif /* MACHINE_FIREBEE */
|
||||
|
||||
srec_execute("BASFLASH.S19");
|
||||
|
||||
xprintf("BaS initialization finished, enable interrupts\r\n");
|
||||
init_isr();
|
||||
|
||||
enable_coldfire_interrupts();
|
||||
MCF_INTC_IMRH = 0;
|
||||
MCF_INTC_IMRL = 0;
|
||||
|
||||
dma_irq_enable();
|
||||
fec_irq_enable(0, 5, 1);
|
||||
|
||||
enable_pci_interrupts();
|
||||
init_pci();
|
||||
|
||||
video_init();
|
||||
|
||||
/* initialize USB devices */
|
||||
// init_usb();
|
||||
|
||||
set_ipl(7); /* disable interrupts */
|
||||
|
||||
/*
|
||||
* start FireTOS if DIP switch is set accordingly
|
||||
*/
|
||||
if (!(DIP_SWITCH & (1 << 6)))
|
||||
{
|
||||
extern uint8_t _FIRETOS[];
|
||||
#define FIRETOS ((uint32_t)_FIRETOS) /* where FireTOS is stored in flash */
|
||||
|
||||
/* make sure MMU is disabled */
|
||||
MCF_MMU_MMUCR = 0; /* MMU off */
|
||||
NOP(); /* force pipeline sync */
|
||||
|
||||
|
||||
/* ST RAM */
|
||||
|
||||
* (uint32_t *) 0x42e = STRAM_END; /* phystop TOS system variable */
|
||||
* (uint32_t *) 0x420 = 0x752019f3; /* memvalid TOS system variable */
|
||||
* (uint32_t *) 0x43a = 0x237698aa; /* memval2 TOS system variable */
|
||||
* (uint32_t *) 0x51a = 0x5555aaaa; /* memval3 TOS system variable */
|
||||
|
||||
/* TT-RAM */
|
||||
|
||||
* (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */
|
||||
* (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */
|
||||
|
||||
xprintf("call FireTOS\r\n");
|
||||
/* Jump into FireTOS */
|
||||
|
||||
void_func* FireTOS = (void_func*) FIRETOS;
|
||||
FireTOS(); // Should never return
|
||||
}
|
||||
|
||||
/*
|
||||
* fix initial pc/sp in ST RAM for FreeMiNT. It expects valid values there
|
||||
* like on original STs (where these values reside in ROM) and uses them on
|
||||
* CTRL-ALT-DELETE reboots.
|
||||
*/
|
||||
fix_stram_header();
|
||||
|
||||
xprintf("call EmuTOS\r\n");
|
||||
struct rom_header *os_header = (struct rom_header *) TOS;
|
||||
os_header->initial_pc();
|
||||
}
|
||||
241
sys/cache.c
Normal file
241
sys/cache.c
Normal file
@@ -0,0 +1,241 @@
|
||||
/*
|
||||
* cache handling
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Copyright 2010 - 2012 F. Aschwanden
|
||||
* Copyright 2011 - 2012 V. Riviere
|
||||
* Copyright 2012 M. Froeschle
|
||||
*
|
||||
*/
|
||||
|
||||
#include "cache.h"
|
||||
|
||||
void cacr_set(uint32_t value)
|
||||
{
|
||||
extern uint32_t rt_cacr;
|
||||
|
||||
rt_cacr = value;
|
||||
__asm__ __volatile__(
|
||||
" movec %0, cacr\n\t"
|
||||
: /* output */
|
||||
: "r" (rt_cacr)
|
||||
: "memory" /* clobbers */);
|
||||
}
|
||||
|
||||
uint32_t cacr_get(void)
|
||||
{
|
||||
extern uint32_t rt_cacr;
|
||||
|
||||
return rt_cacr;
|
||||
}
|
||||
|
||||
void disable_data_cache(void)
|
||||
{
|
||||
flush_and_invalidate_caches();
|
||||
cacr_set((cacr_get() | CF_CACR_DCINVA) & ~CF_CACR_DEC);
|
||||
}
|
||||
|
||||
void disable_instruction_cache(void)
|
||||
{
|
||||
flush_and_invalidate_caches();
|
||||
cacr_set((cacr_get() | CF_CACR_ICINVA) & ~CF_CACR_IEC);
|
||||
}
|
||||
|
||||
void enable_data_cache(void)
|
||||
{
|
||||
cacr_set(cacr_get() & ~CF_CACR_DCINVA);
|
||||
}
|
||||
|
||||
void flush_and_invalidate_caches(void)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
" clr.l d0 \n\t"
|
||||
" clr.l d1 \n\t"
|
||||
" move.l d0,a0 \n\t"
|
||||
"cfa_setloop%=: \n\t"
|
||||
" cpushl bc,(a0) | flush\n\t"
|
||||
" lea 0x10(a0),a0 | index+1\n\t"
|
||||
" addq.l #1,d1 | index+1\n\t"
|
||||
" cmpi.w #512,d1 | all sets?\n\t"
|
||||
" bne.s cfa_setloop%= | no->\n\t"
|
||||
" clr.l d1 \n\t"
|
||||
" addq.l #1,d0 \n\t"
|
||||
" move.l d0,a0 \n\t"
|
||||
" cmpi.w #4,d0 | all ways?\n\t"
|
||||
" bne.s cfa_setloop%= | no->\n\t"
|
||||
/* input */ :
|
||||
/* output */ :
|
||||
/* clobber */ : "cc", "d0", "d1", "a0"
|
||||
);
|
||||
}
|
||||
|
||||
/*
|
||||
* flush and invalidate a specific memory region from the instruction cache
|
||||
*/
|
||||
void flush_icache_range(void *address, size_t size)
|
||||
{
|
||||
uint32_t set;
|
||||
uint32_t start_set;
|
||||
uint32_t end_set;
|
||||
void *endaddr = address + size;
|
||||
|
||||
start_set = (uint32_t) address & _ICACHE_SET_MASK;
|
||||
end_set = (uint32_t) endaddr & _ICACHE_SET_MASK;
|
||||
|
||||
if (start_set > end_set) {
|
||||
/* from the begining to the lowest address */
|
||||
for (set = 0; set <= end_set; set += (0x10 - 3))
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
" cpushl ic,(%[set]) \n\t"
|
||||
" addq.l #1,%[set] \n\t"
|
||||
" cpushl ic,(%[set]) \n\t"
|
||||
" addq.l #1,%[set] \n\t"
|
||||
" cpushl ic,(%[set]) \n\t"
|
||||
" addq.l #1,%[set] \n\t"
|
||||
" cpushl ic,(%[set]) \n\t"
|
||||
: /* output parameters */
|
||||
: [set] "a" (set) /* input parameters */
|
||||
: "cc" /* clobbered registers */
|
||||
);
|
||||
}
|
||||
/* next loop will finish the cache ie pass the hole */
|
||||
end_set = LAST_ICACHE_ADDR;
|
||||
}
|
||||
for (set = start_set; set <= end_set; set += (0x10 - 3)) {
|
||||
__asm__ __volatile__(
|
||||
" cpushl ic,(%[set]) \n\t"
|
||||
" addq.l #1,%[set] \n\t"
|
||||
" cpushl ic,(%[set]) \n\t"
|
||||
" addq.l #1,%[set] \n\t"
|
||||
" cpushl ic,(%[set]) \n\t"
|
||||
" addq.l #1,%[set] \n\t"
|
||||
" cpushl ic,(%[set])"
|
||||
: /* output parameters */
|
||||
: [set] "a" (set)
|
||||
: "cc"
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* flush and invalidate a specific region from the data cache
|
||||
*/
|
||||
void flush_dcache_range(void *address, size_t size)
|
||||
{
|
||||
unsigned long set;
|
||||
unsigned long start_set;
|
||||
unsigned long end_set;
|
||||
void *endaddr;
|
||||
|
||||
endaddr = address + size;
|
||||
start_set = (uint32_t) address & _DCACHE_SET_MASK;
|
||||
end_set = (uint32_t) endaddr & _DCACHE_SET_MASK;
|
||||
|
||||
if (start_set > end_set) {
|
||||
/* from the begining to the lowest address */
|
||||
for (set = 0; set <= end_set; set += (0x10 - 3))
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
" cpushl dc,(%[set]) \n\t"
|
||||
" addq.l #1,%[set] \n\t"
|
||||
" cpushl dc,(%[set]) \n\t"
|
||||
" addq.l #1,%[set] \n\t"
|
||||
" cpushl dc,(%[set]) \n\t"
|
||||
" addq.l #1,%[set] \n\t"
|
||||
" cpushl dc,(%[set]) \n\t"
|
||||
: /* output parameters */
|
||||
: [set] "a" (set)
|
||||
: "cc" /* clobbered registers */
|
||||
);
|
||||
}
|
||||
/* next loop will finish the cache ie pass the hole */
|
||||
end_set = LAST_DCACHE_ADDR;
|
||||
}
|
||||
for (set = start_set; set <= end_set; set += (0x10 - 3))
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
" cpushl dc,(%[set]) \n\t"
|
||||
" addq.l #1,%[set] \n\t"
|
||||
" cpushl dc,(%[set]) \n\t"
|
||||
" addq%.l #1,%[set] \n\t"
|
||||
" cpushl dc,(%[set]) \n\t"
|
||||
" addq.l #1,%[set] \n\t"
|
||||
" cpushl dc,(%[set]) \n\t"
|
||||
: /* output parameters */
|
||||
: [set] "a" (set)
|
||||
: "cc" /* clobbered registers */
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* flush and invalidate a specific region from the both caches. We do not know if the area is cached
|
||||
* at all, we do not know in which of the four ways it is cached, but we know the index where they
|
||||
* would be cached if they are, so we only need to flush and invalidate only a subset of the 512 index
|
||||
* entries, but all four ways.
|
||||
*/
|
||||
void flush_cache_range(void *address, size_t size)
|
||||
{
|
||||
unsigned long set;
|
||||
unsigned long start_set;
|
||||
unsigned long end_set;
|
||||
void *endaddr;
|
||||
|
||||
endaddr = address + size;
|
||||
start_set = (uint32_t) address & _DCACHE_SET_MASK;
|
||||
end_set = (uint32_t) endaddr & _DCACHE_SET_MASK;
|
||||
|
||||
if (start_set > end_set) {
|
||||
/* from the begining to the lowest address */
|
||||
for (set = 0; set <= end_set; set += (0x10 - 3))
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
" cpushl bc,(%[set]) \n\t"
|
||||
" addq.l #1,%[set] \n\t"
|
||||
" cpushl bc,(%[set]) \n\t"
|
||||
" addq.l #1,%[set] \n\t"
|
||||
" cpushl bc,(%[set]) \n\t"
|
||||
" addq.l #1,%[set] \n\t"
|
||||
" cpushl bc,(%[set]) \n\t"
|
||||
: /* output parameters */
|
||||
: [set] "a" (set)
|
||||
: "cc" /* clobbered registers */
|
||||
);
|
||||
}
|
||||
/* next loop will finish the cache ie pass the hole */
|
||||
end_set = LAST_DCACHE_ADDR;
|
||||
}
|
||||
for (set = start_set; set <= end_set; set += (0x10 - 3))
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
" cpushl bc,(%[set]) \n\t"
|
||||
" addq.l #1,%[set] \n\t"
|
||||
" cpushl bc,(%[set]) \n\t"
|
||||
" addq%.l #1,%[set] \n\t"
|
||||
" cpushl bc,(%[set]) \n\t"
|
||||
" addq.l #1,%[set] \n\t"
|
||||
" cpushl bc,(%[set]) \n\t"
|
||||
: /* output parameters */
|
||||
: [set] "a" (set)
|
||||
: "cc" /* clobbered registers */
|
||||
);
|
||||
}
|
||||
}
|
||||
338
sys/driver_mem.c
Normal file
338
sys/driver_mem.c
Normal file
@@ -0,0 +1,338 @@
|
||||
/*
|
||||
* driver_mem.c
|
||||
*
|
||||
* based from Emutos / BDOS
|
||||
*
|
||||
* Copyright (c) 2001 Lineo, Inc.
|
||||
*
|
||||
* Authors: Karl T. Braun, Martin Doering, Laurent Vogel
|
||||
*
|
||||
* This file is distributed under the GPL, version 2 or at your
|
||||
* option any later version.
|
||||
*/
|
||||
|
||||
|
||||
#include <bas_types.h>
|
||||
#include "bas_string.h"
|
||||
#include "bas_printf.h"
|
||||
#include "usb.h"
|
||||
#include "exceptions.h" /* set_ipl() */
|
||||
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
#include "firebee.h"
|
||||
#elif defined(MACHINE_M5484LITE)
|
||||
#include "m5484l.h"
|
||||
#elif defined(MACHINE_M54455)
|
||||
#include "m54455.h"
|
||||
#else
|
||||
#error "unknown machine!"
|
||||
#endif
|
||||
|
||||
// #define DEBUG
|
||||
#include "debug.h"
|
||||
|
||||
extern long offscren_reserved(void);
|
||||
|
||||
extern uint8_t driver_mem_buffer[DRIVER_MEM_BUFFER_SIZE]; /* defined in linker control file */
|
||||
|
||||
/* MD - Memory Descriptor */
|
||||
|
||||
#define MD struct _md_
|
||||
|
||||
MD
|
||||
{
|
||||
MD *m_link;
|
||||
long m_start;
|
||||
long m_length;
|
||||
void *m_own;
|
||||
};
|
||||
|
||||
/* MPB - Memory Partition Block */
|
||||
|
||||
#define MPB struct _mpb
|
||||
|
||||
MPB
|
||||
{
|
||||
MD *mp_mfl;
|
||||
MD *mp_mal;
|
||||
MD *mp_rover;
|
||||
};
|
||||
|
||||
#define MAXMD 256
|
||||
|
||||
static MD tab_md[MAXMD];
|
||||
static MPB pmd;
|
||||
|
||||
static void *xmgetblk(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < MAXMD; i++)
|
||||
{
|
||||
if (tab_md[i].m_own == NULL)
|
||||
{
|
||||
tab_md[i].m_own = (void*)1L;
|
||||
return(&tab_md[i]);
|
||||
}
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void xmfreblk(void *m)
|
||||
{
|
||||
int i = (int)(((long) m - (long) tab_md) / sizeof(MD));
|
||||
if ((i > 0) && (i < MAXMD))
|
||||
{
|
||||
tab_md[i].m_own = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
static MD *ffit(long amount, MPB *mp)
|
||||
{
|
||||
MD *p, *q, *p1; /* free list is composed of MD's */
|
||||
int maxflg;
|
||||
long maxval;
|
||||
|
||||
if (amount != -1)
|
||||
{
|
||||
amount += 15; /* 16 bytes alignment */
|
||||
amount &= 0xFFFFFFF0;
|
||||
}
|
||||
|
||||
if ((q = mp->mp_rover) == 0) /* get rotating pointer */
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
maxval = 0;
|
||||
maxflg = ((amount == -1) ? true : false) ;
|
||||
p = q->m_link; /* start with next MD */
|
||||
do /* search the list for an MD with enough space */
|
||||
{
|
||||
if (p == 0)
|
||||
{
|
||||
/* at end of list, wrap back to start */
|
||||
q = (MD *) &mp->mp_mfl; /* q => mfl field */
|
||||
p = q->m_link; /* p => 1st MD */
|
||||
}
|
||||
if ((!maxflg) && (p->m_length >= amount))
|
||||
{
|
||||
/* big enough */
|
||||
if (p->m_length == amount)
|
||||
{
|
||||
q->m_link = p->m_link; /* take the whole thing */
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* break it up - 1st allocate a new
|
||||
* MD to describe the remainder
|
||||
*/
|
||||
p1 = xmgetblk();
|
||||
if (p1 == NULL)
|
||||
{
|
||||
return(NULL);
|
||||
}
|
||||
|
||||
/* init new MD */
|
||||
p1->m_length = p->m_length - amount;
|
||||
p1->m_start = p->m_start + amount;
|
||||
p1->m_link = p->m_link;
|
||||
p->m_length = amount; /* adjust allocated block */
|
||||
q->m_link = p1;
|
||||
}
|
||||
/* link allocate block into allocated list,
|
||||
mark owner of block, & adjust rover */
|
||||
p->m_link = mp->mp_mal;
|
||||
mp->mp_mal = p;
|
||||
mp->mp_rover = (q == (MD *) &mp->mp_mfl ? q->m_link : q);
|
||||
return(p); /* got some */
|
||||
}
|
||||
else if (p->m_length > maxval)
|
||||
maxval = p->m_length;
|
||||
p = ( q=p )->m_link;
|
||||
} while(q != mp->mp_rover);
|
||||
|
||||
/*
|
||||
* return either the max, or 0 (error)
|
||||
*/
|
||||
if (maxflg)
|
||||
{
|
||||
maxval -= 15; /* 16 bytes alignment */
|
||||
if (maxval < 0)
|
||||
{
|
||||
maxval = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
maxval &= 0xFFFFFFF0;
|
||||
}
|
||||
}
|
||||
return(maxflg ? (MD *) maxval : 0);
|
||||
}
|
||||
|
||||
static void freeit(MD *m, MPB *mp)
|
||||
{
|
||||
MD *p, *q;
|
||||
|
||||
q = 0;
|
||||
for (p = mp->mp_mfl; p ; p = (q = p) -> m_link)
|
||||
{
|
||||
if (m->m_start <= p->m_start)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
m->m_link = p;
|
||||
|
||||
if (q)
|
||||
{
|
||||
q->m_link = m;
|
||||
}
|
||||
else
|
||||
{
|
||||
mp->mp_mfl = m;
|
||||
}
|
||||
|
||||
if (!mp->mp_rover)
|
||||
{
|
||||
mp->mp_rover = m;
|
||||
}
|
||||
|
||||
if (p)
|
||||
{
|
||||
if (m->m_start + m->m_length == p->m_start)
|
||||
{
|
||||
/* join to higher neighbor */
|
||||
m->m_length += p->m_length;
|
||||
m->m_link = p->m_link;
|
||||
if (p == mp->mp_rover)
|
||||
{
|
||||
mp->mp_rover = m;
|
||||
}
|
||||
xmfreblk(p);
|
||||
}
|
||||
}
|
||||
if (q)
|
||||
{
|
||||
if (q->m_start + q->m_length == m->m_start)
|
||||
{
|
||||
/* join to lower neighbor */
|
||||
q->m_length += m->m_length;
|
||||
q->m_link = m->m_link;
|
||||
if (m == mp->mp_rover)
|
||||
{
|
||||
mp->mp_rover = q;
|
||||
}
|
||||
xmfreblk(m);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int32_t driver_mem_free(void *addr)
|
||||
{
|
||||
int level;
|
||||
MD *p, **q;
|
||||
MPB *mpb;
|
||||
mpb = &pmd;
|
||||
level = set_ipl(7);
|
||||
|
||||
for(p = *(q = &mpb->mp_mal); p; p = *(q = &p->m_link))
|
||||
{
|
||||
if ((long) addr == p->m_start)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!p)
|
||||
{
|
||||
set_ipl(level);
|
||||
return(-1);
|
||||
}
|
||||
|
||||
*q = p->m_link;
|
||||
freeit(p, mpb);
|
||||
set_ipl(level);
|
||||
|
||||
dbg("addr=0x%08X)\r\n", addr);
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
void *driver_mem_alloc(uint32_t amount)
|
||||
{
|
||||
void *ret = NULL;
|
||||
int level;
|
||||
MD *m;
|
||||
|
||||
if (amount == -1L)
|
||||
{
|
||||
return (void *) ffit(-1L, &pmd);
|
||||
}
|
||||
|
||||
if (amount <= 0 )
|
||||
{
|
||||
return(0);
|
||||
}
|
||||
|
||||
if ((amount & 1))
|
||||
{
|
||||
amount++;
|
||||
}
|
||||
|
||||
level = set_ipl(7);
|
||||
m = ffit(amount, &pmd);
|
||||
|
||||
if (m != NULL)
|
||||
{
|
||||
ret = (void *) m->m_start;
|
||||
}
|
||||
set_ipl(level);
|
||||
dbg("alloc(%d) = 0x%08X\r\n", amount, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int use_count = 0;
|
||||
|
||||
int driver_mem_init(void)
|
||||
{
|
||||
if (use_count == 0)
|
||||
{
|
||||
dbg("initialise driver_mem_buffer[] at %p, size 0x%x\r\n", driver_mem_buffer, DRIVER_MEM_BUFFER_SIZE);
|
||||
memset(driver_mem_buffer, 0, DRIVER_MEM_BUFFER_SIZE);
|
||||
|
||||
pmd.mp_mfl = pmd.mp_rover = &tab_md[0];
|
||||
tab_md[0].m_link = (MD *) NULL;
|
||||
tab_md[0].m_start = ((long) driver_mem_buffer + 15) & ~15;
|
||||
tab_md[0].m_length = DRIVER_MEM_BUFFER_SIZE;
|
||||
tab_md[0].m_own = (void *) 1L;
|
||||
pmd.mp_mal = (MD *) NULL;
|
||||
memset(driver_mem_buffer, 0, tab_md[0].m_length);
|
||||
|
||||
dbg("uncached driver memory buffer at 0x%08X size %d\r\n", tab_md[0].m_start, tab_md[0].m_length);
|
||||
}
|
||||
use_count++;
|
||||
dbg("driver_mem now has a use count of %d\r\n", use_count);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void driver_mem_release(void)
|
||||
{
|
||||
if (use_count-- == 0)
|
||||
{
|
||||
#ifndef CONFIG_USB_MEM_NO_CACHE
|
||||
#ifdef USE_RADEON_MEMORY
|
||||
if (driver_mem_buffer == (void *) offscren_reserved())
|
||||
return;
|
||||
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
dbg("driver_mem use count now %d\r\n", use_count);
|
||||
}
|
||||
|
||||
|
||||
|
||||
608
sys/exceptions.S
Normal file
608
sys/exceptions.S
Normal file
@@ -0,0 +1,608 @@
|
||||
/*
|
||||
* initialize exception vectors
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 26.02.2013
|
||||
* Author: Markus Fröschle
|
||||
*/
|
||||
|
||||
#include "startcf.h"
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
#include "firebee.h"
|
||||
#elif defined(MACHINE_M5484LITE)
|
||||
#include "m5484l.h"
|
||||
#endif /* MACHINE_FIREBEE */
|
||||
|
||||
.extern __SUP_SP
|
||||
.extern _rom_entry
|
||||
.extern __RAMBAR0
|
||||
.extern _rt_mod
|
||||
.extern _rt_ssp
|
||||
.extern _rt_usp
|
||||
.extern _rt_vbr
|
||||
.extern _mmutr_miss
|
||||
.extern __MBAR
|
||||
.extern __MMUBAR
|
||||
.extern _video_tlb
|
||||
.extern _video_sbt
|
||||
.extern _flush_and_invalidate_caches
|
||||
.extern _get_bas_drivers
|
||||
|
||||
/* PCI interrupt handlers */
|
||||
.extern _irq5_handler
|
||||
.extern _irq6_handler
|
||||
.extern _irq7_handler
|
||||
|
||||
.global _vec_init
|
||||
.global _std_exc_vec /* needed by driver_vec.c */
|
||||
|
||||
/* Register read/write equates */
|
||||
|
||||
/* MMU */
|
||||
.equ MCF_MMU_MMUCR, __MMUBAR
|
||||
.equ MCF_MMU_MMUOR, __MMUBAR+0x04
|
||||
.equ MCF_MMU_MMUSR, __MMUBAR+0x08
|
||||
.equ MCF_MMU_MMUAR, __MMUBAR+0x10
|
||||
.equ MCF_MMU_MMUTR, __MMUBAR+0x14
|
||||
.equ MCF_MMU_MMUDR, __MMUBAR+0x18
|
||||
|
||||
/* EPORT flag register */
|
||||
.equ MCF_EPORT_EPFR, __MBAR+0xf0c
|
||||
|
||||
/* FEC1 port output data direction register */
|
||||
.equ MCF_GPIO_PODR_FEC1L, __MBAR+0xa07
|
||||
|
||||
/* PSC0 transmit buffer register */
|
||||
.equ MCF_PSC0_PSCTB_8BIT, __MBAR+0x860c
|
||||
|
||||
/* GPT mode select register */
|
||||
.equ MCF_GPT0_GMS, __MBAR+0x800
|
||||
|
||||
/* Slice timer 0 count register */
|
||||
.equ MCF_SLT0_SCNT, __MBAR+0x908
|
||||
|
||||
// interrupt sources
|
||||
.equ INT_SOURCE_EPORT_EPF1,1 // edge port flag 1
|
||||
.equ INT_SOURCE_EPORT_EPF2,2 // edge port flag 2
|
||||
.equ INT_SOURCE_EPORT_EPF3,3 // edge port flag 3
|
||||
.equ INT_SOURCE_EPORT_EPF4,4 // edge port flag 4
|
||||
.equ INT_SOURCE_EPORT_EPF5,5 // edge port flag 5
|
||||
.equ INT_SOURCE_EPORT_EPF6,6 // edge port flag 6
|
||||
.equ INT_SOURCE_EPORT_EPF7,7 // edge port flag 7
|
||||
.equ INT_SOURCE_USB_EP0ISR,15 // USB endpoint 0 interrupt
|
||||
.equ INT_SOURCE_USB_EP1ISR,16 // USB endpoint 1 interrupt
|
||||
.equ INT_SOURCE_USB_EP2ISR,17 // USB endpoint 2 interrupt
|
||||
.equ INT_SOURCE_USB_EP3ISR,18 // USB endpoint 3 interrupt
|
||||
.equ INT_SOURCE_USB_EP4ISR,19 // USB endpoint 4 interrupt
|
||||
.equ INT_SOURCE_USB_EP5ISR,20 // USB endpoint 5 interrupt
|
||||
.equ INT_SOURCE_USB_EP6ISR,21 // USB endpoint 6 interrupt
|
||||
.equ INT_SOURCE_USB_USBISR,22 // USB general interrupt
|
||||
.equ INT_SOURCE_USB_USBAISR,23 // USB core interrupt
|
||||
.equ INT_SOURCE_USB_ANY,24 // OR of all USB interrupts
|
||||
.equ INT_SOURCE_USB_DSPI_OVF,25 // DSPI overflow or underflow
|
||||
.equ INT_SOURCE_USB_DSPI_RFOF,26 // receive FIFO overflow interrupt
|
||||
.equ INT_SOURCE_USB_DSPI_RFDF,27 // receive FIFO drain interrupt
|
||||
.equ INT_SOURCE_USB_DSPI_TFUF,28 // transmit FIFO underflow interrupt
|
||||
.equ INT_SOURCE_USB_DSPI_TCF,29 // transfer complete interrupt
|
||||
.equ INT_SOURCE_USB_DSPI_TFFF,30 // transfer FIFO fill interrupt
|
||||
.equ INT_SOURCE_USB_DSPI_EOQF,31 // end of queue interrupt
|
||||
.equ INT_SOURCE_PSC3,32 // PSC3 interrupt
|
||||
.equ INT_SOURCE_PSC2,33 // PSC2 interrupt
|
||||
.equ INT_SOURCE_PSC1,34 // PSC1 interrupt
|
||||
.equ INT_SOURCE_PSC0,35 // PSC0 interrupt
|
||||
.equ INT_SOURCE_CTIMERS,36 // combined source for comm timers
|
||||
.equ INT_SOURCE_SEC,37 // SEC interrupt
|
||||
.equ INT_SOURCE_FEC1,38 // FEC1 interrupt
|
||||
.equ INT_SOURCE_FEC0,39 // FEC0 interrupt
|
||||
.equ INT_SOURCE_I2C,40 // I2C interrupt
|
||||
.equ INT_SOURCE_PCIARB,41 // PCI arbiter interrupt
|
||||
.equ INT_SOURCE_CBPCI,42 // COMM bus PCI interrupt
|
||||
.equ INT_SOURCE_XLBPCI,43 // XLB PCI interrupt
|
||||
.equ INT_SOURCE_XLBARB,47 // XLBARB interrupt
|
||||
.equ INT_SOURCE_DMA,48 // multichannel DMA interrupt
|
||||
.equ INT_SOURCE_CAN0_ERROR,49 // FlexCAN error interrupt
|
||||
.equ INT_SOURCE_CAN0_BUSOFF,50 // FlexCAN bus off interrupt
|
||||
.equ INT_SOURCE_CAN0_MBOR,51 // message buffer ORed interrupt
|
||||
.equ INT_SOURCE_SLT1,53 // slice timer 1 interrupt
|
||||
.equ INT_SOURCE_SLT0,54 // slice timer 0 interrupt
|
||||
.equ INT_SOURCE_CAN1_ERROR,55 // FlexCAN error interrupt
|
||||
.equ INT_SOURCE_CAN1_BUSOFF,56 // FlexCAN bus off interrupt
|
||||
.equ INT_SOURCE_CAN1_MBOR,57 // message buffer ORed interrupt
|
||||
.equ INT_SOURCE_GPT3,59 // GPT3 timer interrupt
|
||||
.equ INT_SOURCE_GPT2,60 // GPT2 timer interrupt
|
||||
.equ INT_SOURCE_GPT1,61 // GPT1 timer interrupt
|
||||
.equ INT_SOURCE_GPT0,62 // GPT0 timer interrupt
|
||||
|
||||
// Atari register equates (provided by FPGA)
|
||||
.equ vbasehi, 0xffff8201
|
||||
|
||||
/*
|
||||
* macros
|
||||
*/
|
||||
|
||||
/*
|
||||
* used for "forwarding" interrupt handlers. This just clears the "pending interrupt"
|
||||
* flag from the EDGE PORT flag register, set the status register to the appropriate interrupt
|
||||
* mask an jump through the corresponging vector
|
||||
*/
|
||||
.macro irq vector,int_mask,clr_int
|
||||
move.w #0x2700,sr // disable interrupts
|
||||
subq.l #8,sp
|
||||
movem.l d0/a5,(sp) // save registers
|
||||
|
||||
lea MCF_EPORT_EPFR,a5
|
||||
move.b #\clr_int,(a5) // clear int pending
|
||||
|
||||
movem.l (sp),d0/a5 // restore registers
|
||||
addq.l #8,sp
|
||||
move.l \vector,-(sp)
|
||||
move #0x2\int_mask\()00,sr
|
||||
rts
|
||||
.endm
|
||||
|
||||
.text
|
||||
_vec_init:
|
||||
move.l a2,-(sp) // Backup registers
|
||||
|
||||
mov3q.l #-1,_rt_mod // rt_mod auf super
|
||||
clr.l _rt_ssp
|
||||
clr.l _rt_usp
|
||||
clr.l _rt_vbr
|
||||
move.l #__RAMBAR0,d0 // exception vectors reside in rambar0
|
||||
movec d0,VBR
|
||||
move.l d0,a0
|
||||
move.l a0,a2
|
||||
|
||||
/*
|
||||
* first, set standard vector for all exceptions
|
||||
*/
|
||||
init_vec:
|
||||
move.l #256,d0
|
||||
lea std_exc_vec(pc),a1 // standard vector
|
||||
init_vec_loop:
|
||||
move.l a1,(a2)+ // set standard vector for all exceptions
|
||||
subq.l #1,d0
|
||||
bne init_vec_loop
|
||||
|
||||
// set individual interrupt handler assignments
|
||||
|
||||
move.l #__SUP_SP,(a0) // set initial stack pointer at start of exception vector table
|
||||
|
||||
lea reset_vector(pc),a1 // set reset vector
|
||||
move.l a1,0x04(a0)
|
||||
|
||||
lea access(pc),a1 // set illegal access exception handler
|
||||
move.l a1,0x08(a0)
|
||||
|
||||
// install spurious interrupt handler
|
||||
lea _lowlevel_isr_handler,a1
|
||||
move.l a1,0x60(a0)
|
||||
|
||||
// trap #0 (without any parameters for now) is used to provide BaS' driver addresses to the OS
|
||||
lea _get_bas_drivers(pc),a1
|
||||
move.l a1,0x80(a0) // trap #0 exception vector
|
||||
|
||||
// MFP non-autovector interrupt handlers. Those are just rerouted to their autovector counterparts
|
||||
|
||||
lea irq1(pc),a1
|
||||
move.l a1,0x104(a0)
|
||||
|
||||
lea irq2(pc),a1
|
||||
move.l a1,0x108(a0)
|
||||
|
||||
lea irq3(pc),a1
|
||||
move.l a1,0x10c(a0)
|
||||
|
||||
lea irq4(pc),a1
|
||||
move.l a1,0x110(a0)
|
||||
|
||||
lea irq5(pc),a1
|
||||
move.l a1,0x114(a0)
|
||||
|
||||
lea irq6(pc),a1
|
||||
move.l a1,0x118(a0)
|
||||
|
||||
lea irq7(pc),a1
|
||||
move.l a1,0x11c(a0)
|
||||
|
||||
|
||||
|
||||
// install lowlevel_isr_handler for the three GPT timers
|
||||
lea _lowlevel_isr_handler(pc),a1
|
||||
move.l a1,(INT_SOURCE_GPT1 + 64) * 4(a0)
|
||||
move.l a1,(INT_SOURCE_GPT2 + 64) * 4(a0)
|
||||
move.l a1,(INT_SOURCE_GPT3 + 64) * 4(a0)
|
||||
|
||||
// install lowlevel_isr_handler for the PSC3 interrupt
|
||||
move.l a1,(INT_SOURCE_PSC3 + 64) * 4(a0)
|
||||
|
||||
// install lowlevel_isr_handler for Coldfire DMA interrupts
|
||||
move.l a1,(INT_SOURCE_DMA + 64) * 4(a0)
|
||||
|
||||
// install lowlevel_isr_handler for the XLBPCI interrupt
|
||||
move.l a1,(INT_SOURCE_XLBPCI + 64) * 4(a0)
|
||||
|
||||
// install lowlevel_isr_handler for the XLBARB interrupt
|
||||
// move.l a1,(INT_SOURCE_XLBARB + 64) * 4(a0) // FIXME: commented out for testing
|
||||
|
||||
// install lowlevel_isr_handler for the FEC0 interrupt
|
||||
move.l a1,(INT_SOURCE_FEC0 + 64) * 4(a0)
|
||||
|
||||
#ifndef MACHINE_FIREBEE
|
||||
// FEC1 not wired on the FireBee (used for FPGA as GPIO), but available on other machines
|
||||
move.l a1,(INT_SOURCE_FEC1 + 64) * 4(a0)
|
||||
#endif
|
||||
|
||||
#ifdef MACHINE_FIREBEE
|
||||
|
||||
// timer vectors (triggers when vbashi gets changed, used for video page copy)
|
||||
// move.l a1,(INT_SOURCE_GPT0 + 64) * 4(a0)
|
||||
#endif /* MACHINE_FIREBEE */
|
||||
|
||||
move.l (sp)+,a2 // Restore registers
|
||||
rts
|
||||
|
||||
|
||||
/*
|
||||
* exception vector routines
|
||||
*/
|
||||
vector_table_start:
|
||||
std_exc_vec:
|
||||
_std_exc_vec:
|
||||
move.w #0x2700,sr // disable interrupt
|
||||
subq.l #8,sp
|
||||
movem.l d0/a5,(sp) // save registers
|
||||
move.w 8(sp),d0 // fetch vector
|
||||
and.l #0x3fc,d0 // mask out vector number
|
||||
// #define DBG_EXC
|
||||
#ifdef DBG_EXC
|
||||
// printout vector number of exception
|
||||
|
||||
lea -4 * 4(sp),sp // reserve stack space
|
||||
movem.l d0-d1/a0-a1,(sp) // save gcc scratch registers
|
||||
|
||||
lsr.l #2,d0 // shift vector number in place
|
||||
cmp.l #33,d0
|
||||
beq noprint
|
||||
cmp.l #34,d0
|
||||
beq noprint
|
||||
cmp.l #45,d0
|
||||
beq noprint
|
||||
cmp.l #46,d0
|
||||
beq noprint
|
||||
move.l 4 * 4 + 8 + 4(sp),-(sp) // pc at exception
|
||||
move.l d0,-(sp) // provide it to xprintf()
|
||||
pea exception_text
|
||||
jsr _xprintf // call xprintf()
|
||||
add.l #3*4,sp // adjust stack
|
||||
noprint:
|
||||
|
||||
movem.l (sp),d0-d1/a0-a1 // restore registers
|
||||
lea 4 * 4(sp),sp
|
||||
#endif /* DBG_EXC */
|
||||
|
||||
add.l _rt_vbr,d0 // + VBR
|
||||
move.l d0,a5
|
||||
move.l (a5),d0 // fetch exception routine address
|
||||
|
||||
move.l 4(sp),a5 // restore a5
|
||||
move.l d0,4(sp) // store exception routine address
|
||||
|
||||
move.w 10(sp),d0 // restore original SR (irq mask)
|
||||
bset #13,d0 // set supervisor bit
|
||||
move.w d0,sr //
|
||||
move.l (sp)+,d0 // restore d0
|
||||
rts // jump to exception handler
|
||||
|
||||
exception_text:
|
||||
.ascii "DEBUG: EXCEPTION %d caught at %p"
|
||||
.byte 13, 10, 0
|
||||
.align 4
|
||||
|
||||
reset_vector:
|
||||
move.w #0x2700,sr // disable interrupts
|
||||
move.l #0x31415926,d0
|
||||
cmp.l 0x426,d0 // _resvalid: reset vector valid?
|
||||
beq std_exc_vec // yes->
|
||||
jmp _rom_entry // no, cold start machine
|
||||
|
||||
access:
|
||||
move.w #0x2700,sr // disable interrupts
|
||||
|
||||
link a6,#-4 * 4 // make room for gcc scratch registers
|
||||
movem.l d0-d1/a0-a1,(sp) // save them
|
||||
|
||||
move.l 4(a6),-(sp) // push format_status
|
||||
move.l 8(a6),-(sp) // pc at exception
|
||||
move.l MCF_MMU_MMUAR,-(sp) // MMU fault address
|
||||
move.l MCF_MMU_MMUSR,-(sp) // MMU status register
|
||||
// probably doesn't make sense since we still have a potential unmapped MMU page
|
||||
// move.w #0x2300,sr // can lower interrupt mask now that MMU status is safe
|
||||
jsr _mmutr_miss // call C routine
|
||||
lea 4 * 4(sp),sp // adjust stack
|
||||
|
||||
tst.l d0 // exception handler signals bus error
|
||||
bne bus_error
|
||||
|
||||
movem.l (sp),d0-d1/a0-a1 // restore registers
|
||||
unlk a6
|
||||
rte
|
||||
|
||||
bus_error:
|
||||
movem.l (sp),d0-d1/a0-a1 // restore registers
|
||||
unlk a6
|
||||
move.l 0x08,-(sp)
|
||||
rts
|
||||
// bra std_exc_vec // FIXME: this seems to be bogous...
|
||||
|
||||
zero_divide:
|
||||
move.w #0x2700,sr // disable interrupt
|
||||
move.l a0,-(sp)
|
||||
move.l d0,-(sp)
|
||||
move.l 12(sp),a0 // pc
|
||||
move.w (a0)+,d0 // command word
|
||||
btst #7,d0 // long?
|
||||
beq zd_word // no->
|
||||
addq.l #2,a0
|
||||
|
||||
zd_word:
|
||||
and.l 0x3f,d0 // mask out ea field
|
||||
cmp.w #0x08,d0 // -(ax) or less?
|
||||
ble zd_end
|
||||
addq.l #2,a0
|
||||
cmp.w #0x39,d0 // xxx.L
|
||||
bne zd_nal
|
||||
addq.l #2,a0
|
||||
bra zd_end
|
||||
|
||||
zd_nal: cmp.w #0x3c,d0 // immediate?
|
||||
bne zd_end // no->
|
||||
btst #7,d0 // long?
|
||||
beq zd_end // no
|
||||
addq.l #2,a0
|
||||
zd_end:
|
||||
move.l a0,12(sp)
|
||||
move.l (sp)+,d0
|
||||
move.l (sp)+,a0
|
||||
rte
|
||||
|
||||
#ifdef _NOT_USED_
|
||||
linea:
|
||||
move.w #0x2700,sr // disable interrupt
|
||||
halt
|
||||
nop
|
||||
nop
|
||||
linef:
|
||||
move.w #0x2700,sr // disable interrupt
|
||||
halt
|
||||
nop
|
||||
nop
|
||||
format:
|
||||
move.w #0x2700,sr // disable interrupt
|
||||
halt
|
||||
nop
|
||||
nop
|
||||
|
||||
//floating point
|
||||
flpoow:
|
||||
move.w #0x2700,sr // disable interrupt
|
||||
halt
|
||||
nop
|
||||
nop
|
||||
#endif /* _NOT_USED */
|
||||
|
||||
|
||||
irq1: irq 0x64, 1, 0x02 // Level 1 autovector interrupt (unused)
|
||||
irq2: irq 0x68, 2, 0x04 // Level 2 autovector interrupt (horizontal blank)
|
||||
irq3: irq 0x6c, 3, 0x08 // Level 3 autovector interrupt (unused)
|
||||
irq4: irq 0x70, 4, 0x10 // Level 4 autovector interrupt (vertical blank)
|
||||
|
||||
|
||||
|
||||
#if defined(MACHINE_FIREBEE) // these handlers are only meaningful for the Firebee
|
||||
irq5: //move.w #0x2700,sr // disable interrupts
|
||||
subq.l #4,sp // extra space
|
||||
|
||||
link a6,#-4 * 4 // save gcc scratch registers
|
||||
movem.l d0-d1/a0-a1,(sp)
|
||||
|
||||
jsr _irq5_handler // call C handler routine
|
||||
|
||||
tst.b d0 // handled?
|
||||
beq irq5_forward
|
||||
|
||||
movem.l (sp),d0-d1/a0-a1 // restore registers
|
||||
unlk a6
|
||||
addq.l #4,sp
|
||||
|
||||
rte // return from exception
|
||||
|
||||
irq5_forward: move.l 0x74,a0 // fetch OS irq5 vector
|
||||
add.l _rt_vbr,a0 // add runtime vbr
|
||||
move.l a0,4(a6) // put on stack
|
||||
|
||||
movem.l (sp),d0-d1/a0-a1 // restore registers
|
||||
unlk a6 //
|
||||
move.w #0x2500,sr // set interrupt level
|
||||
rts // jump through vector
|
||||
|
||||
/*
|
||||
* irq6 needs special treatment since - because the Coldfire only supports autovector interrupts
|
||||
* - the exception vector is provided by the simulated MFP from the FPGA
|
||||
*/
|
||||
irq6: move.w #0x2700,sr // disable interrupt
|
||||
subq.l #4,sp // extra space
|
||||
|
||||
link a6,#-4 * 4 // save gcc scratch registers
|
||||
movem.l d0-d1/a0-a1,(sp)
|
||||
|
||||
move.l 8(a6),-(sp) // format status word
|
||||
move.l 12(a6),-(sp) // pc at exception
|
||||
jsr _irq6_handler // call C handler
|
||||
lea 8(sp),sp // fix stack
|
||||
|
||||
tst.b d0 // interrupt handled?
|
||||
beq irq6_forward // no, forward to TOS
|
||||
|
||||
movem.l (sp),d0-d1/a0-a1 // restore registers
|
||||
unlk a6
|
||||
addq.l #4,sp // "extra space" not needed in this case
|
||||
rte
|
||||
|
||||
irq6_forward:
|
||||
move.l 0xf0020000,a0 // fetch "MFP interrupt vector" from FPGA
|
||||
add.l _rt_vbr,a0 // add runtime VBR
|
||||
move.l (a0),4(a6) // fetch handler address and put it on "extra space"
|
||||
|
||||
movem.l (sp),d0-d1/a0-a1
|
||||
unlk a6
|
||||
move.w #0x2600,sr // set interrupt mask to MFP level
|
||||
|
||||
rts // jump through vector
|
||||
|
||||
/*
|
||||
* irq 7 = pseudo bus error
|
||||
*/
|
||||
irq7:
|
||||
lea -12(sp),sp
|
||||
movem.l d0/a0,(sp)
|
||||
|
||||
move.l __RAMBAR0+0x008,a0 // real access error handler
|
||||
move.l a0,8(sp) // this will be the return address for rts
|
||||
|
||||
move.w 12(sp),d0 // format/vector word
|
||||
andi.l #0xf000,d0 // keep only the format
|
||||
ori.l #2*4,d0 // simulate vector #2, no fault
|
||||
move.w d0,12(sp)
|
||||
|
||||
// TODO: Inside an interrupt handler, 16(sp) is the return address.
|
||||
// For an Access Error, it should be the address of the fault instruction instead
|
||||
|
||||
lea MCF_EPORT_EPFR,a0
|
||||
bset #7,(a0) // clear int 7
|
||||
|
||||
move.l (sp)+,d0 // restore registers
|
||||
move.l (sp)+,a0
|
||||
rts // Forward to the Access Error handler
|
||||
|
||||
#else // handlers for M5484LITE
|
||||
|
||||
irq5:
|
||||
move.w #0x2700,sr // disable interrupts
|
||||
subq.l #4,sp // extra space
|
||||
|
||||
link a6,#-4 * 4 // save gcc scratch registers
|
||||
movem.l d0-d1/a0-a1,(sp)
|
||||
|
||||
jsr _irq5_handler // call C handler routine
|
||||
|
||||
tst.b d0 // handled?
|
||||
beq irq5_forward
|
||||
|
||||
movem.l (sp),d0-d1/a0-a1 // restore registers
|
||||
unlk a6
|
||||
addq.l #4,sp
|
||||
|
||||
rte // return from exception
|
||||
|
||||
irq5_forward:
|
||||
move.l 0x74,a0 // fetch OS irq5 vector
|
||||
add.l _rt_vbr,a0 // add runtime vbr
|
||||
move.l a0,4(a6) // put on stack
|
||||
|
||||
movem.l (sp),d0-d1/a0-a1 // restore registers
|
||||
unlk a6 //
|
||||
move.w #0x2500,sr // set interrupt level
|
||||
rts // jump through vector
|
||||
|
||||
irq6:
|
||||
irq 0x74,5,0x20
|
||||
|
||||
irq7: // irq7 is tied to PCI INTA# and PCI INTB# on the M5484LITE
|
||||
|
||||
move.w #0x2700,sr // disable interrupts
|
||||
|
||||
lea -4*4(sp),sp // save gcc scratch registers
|
||||
movem.l d0-d1/a0-a1,(sp)
|
||||
|
||||
jsr _irq7_handler // call C handler routine
|
||||
|
||||
movem.l (sp),d0-d1/a0-a1 // restore registers
|
||||
lea 4 * 4(sp),sp
|
||||
|
||||
rte // return from exception
|
||||
|
||||
irq7text:
|
||||
.data
|
||||
.ascii "IRQ7!"
|
||||
.byte 13,10,0
|
||||
.align 4
|
||||
.text
|
||||
#endif /* MACHINE_FIREBEE */
|
||||
|
||||
/*
|
||||
* low-level interrupt service routine for routines registered with
|
||||
* isr_register_handler(int vector). If the higlevel routine (isr_execute_handler())
|
||||
* returns != true, the call is forwarded to the OS (through its own vector base).
|
||||
*/
|
||||
.global _lowlevel_isr_handler
|
||||
.extern _isr_execute_handler
|
||||
|
||||
|
||||
/*
|
||||
* stack format (after link instruction) is like this:
|
||||
*
|
||||
* +12 program counter (return address)
|
||||
* +8 format_status
|
||||
* +4 save area for rts (if we need to jump through the OS vector)
|
||||
* (a6) -> saved a6 (from link)
|
||||
* -4
|
||||
* -8
|
||||
* -12
|
||||
* (sp) -> gcc scratch registers save area
|
||||
*/
|
||||
_lowlevel_isr_handler:
|
||||
subq.l #4,sp // extra space
|
||||
link a6,#-4 * 4 // make room for
|
||||
movem.l d0-d1/a0-a1,(sp) // gcc scratch registers and save them,
|
||||
// other registers will be taken care of by gcc itself
|
||||
|
||||
move.w 8(a6),d0 // fetch vector number from stack
|
||||
lsr.l #2,d0 // move it in place
|
||||
andi.l #0xff,d0 // mask it out
|
||||
move.l d0,-(sp) // push it
|
||||
jsr _isr_execute_handler // call the C handler
|
||||
addq.l #4,sp // adjust stack
|
||||
tst.l d0 // handled?
|
||||
beq lowlevel_forward // no, forward it to TOS
|
||||
|
||||
movem.l (sp),d0-d1/a0-a1 // restore registers
|
||||
unlk a6
|
||||
addq.l #4,sp // eliminate extra space
|
||||
|
||||
rte
|
||||
|
||||
lowlevel_forward:
|
||||
move.l 8(a6),d0 // fetch OS irq vector
|
||||
lsr.l #2,d0 // move it in place
|
||||
andi.l #0xff,d0 // mask out vector number
|
||||
add.l _rt_vbr,d0 // add runtime vbr
|
||||
move.l d0,4(a6) // put on stack as return address
|
||||
|
||||
movem.l (sp),d0-d1/a0-a1 // restore registers
|
||||
unlk a6 //
|
||||
rts // jump through vector
|
||||
235
sys/fault_vectors.c
Normal file
235
sys/fault_vectors.c
Normal file
@@ -0,0 +1,235 @@
|
||||
/*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* provide an early exception vector branch table to catch exceptions _before_ VBR has been setup eventually
|
||||
* (to RAMBAR0, in exceptions.S)
|
||||
*/
|
||||
|
||||
#include "MCF5475.h"
|
||||
#include "bas_types.h"
|
||||
#include "bas_printf.h"
|
||||
|
||||
typedef void (*exception_handler)(void);
|
||||
extern exception_handler SDRAM_VECTOR_TABLE[];
|
||||
|
||||
/*
|
||||
* decipher Coldfire exception stack frame and print it out in cleartext
|
||||
*/
|
||||
void fault_handler(uint32_t pc, uint32_t format_status)
|
||||
{
|
||||
int format;
|
||||
int fault_status;
|
||||
int vector;
|
||||
int sr;
|
||||
|
||||
xprintf("\007\007exception! Processor halted.\r\n");
|
||||
xprintf("format_status: %lx\r\n", format_status);
|
||||
xprintf("pc: %lx\r\n", pc);
|
||||
|
||||
/*
|
||||
* extract info from format-/status word
|
||||
*/
|
||||
format = (format_status & 0b11110000000000000000000000000000) >> 28;
|
||||
fault_status = ((format_status & 0b00001100000000000000000000000000) >> 26) |
|
||||
((format_status & 0b00000000000000110000000000000000) >> 16);
|
||||
vector = (format_status & 0b00000011111111000000000000000000) >> 18;
|
||||
sr = (format_status & 0b00000000000000001111111111111111);
|
||||
|
||||
xprintf("format: %x\r\n", format);
|
||||
xprintf("fault_status: %x (", fault_status);
|
||||
switch (fault_status)
|
||||
{
|
||||
case 0:
|
||||
xprintf("not an access or address error nor an interrupted debug service routine");
|
||||
break;
|
||||
|
||||
case 1:
|
||||
case 3:
|
||||
case 11:
|
||||
xprintf("reserved");
|
||||
break;
|
||||
|
||||
case 2:
|
||||
xprintf("interrupt during a debug service routine for faults other than access errors");
|
||||
break;
|
||||
|
||||
case 4:
|
||||
xprintf("error (for example, protection fault) on instruction fetch");
|
||||
break;
|
||||
|
||||
case 5:
|
||||
xprintf("TLB miss on opword or instruction fetch");
|
||||
break;
|
||||
|
||||
case 6:
|
||||
xprintf("TLB miss on extension word of instruction fetch");
|
||||
break;
|
||||
|
||||
case 7:
|
||||
xprintf("IFP access error while executing in emulator mode");
|
||||
break;
|
||||
|
||||
case 8:
|
||||
xprintf("error on data write");
|
||||
break;
|
||||
|
||||
case 9:
|
||||
xprintf("error on attempted write to write-protected space");
|
||||
break;
|
||||
|
||||
case 10:
|
||||
xprintf("TLB miss on data write");
|
||||
break;
|
||||
|
||||
case 12:
|
||||
xprintf("error on data read");
|
||||
break;
|
||||
|
||||
case 13:
|
||||
xprintf("attempted read, read-modify-write of protected space");
|
||||
break;
|
||||
|
||||
case 14:
|
||||
xprintf("TLB miss on data read or read-modify-write");
|
||||
break;
|
||||
|
||||
case 15:
|
||||
xprintf("OEP access error while executing in emulator mode");
|
||||
}
|
||||
xprintf(")\r\n");
|
||||
|
||||
xprintf("vector = %d (", vector);
|
||||
switch (vector)
|
||||
{
|
||||
case 2:
|
||||
xprintf("access error");
|
||||
break;
|
||||
|
||||
case 3:
|
||||
xprintf("address error");
|
||||
break;
|
||||
|
||||
case 4:
|
||||
xprintf("illegal instruction");
|
||||
break;
|
||||
|
||||
case 5:
|
||||
xprintf("divide by zero");
|
||||
break;
|
||||
|
||||
case 8:
|
||||
xprintf("privilege violation");
|
||||
break;
|
||||
|
||||
case 9:
|
||||
xprintf("trace");
|
||||
break;
|
||||
|
||||
case 10:
|
||||
xprintf("unimplemented line-a opcode");
|
||||
break;
|
||||
|
||||
case 11:
|
||||
xprintf("unimplemented line-f opcode");
|
||||
break;
|
||||
|
||||
case 12:
|
||||
xprintf("non-PC breakpoint debug interrupt");
|
||||
break;
|
||||
|
||||
case 13:
|
||||
xprintf("PC breakpoint debug interrupt");
|
||||
break;
|
||||
|
||||
case 14:
|
||||
xprintf("format error");
|
||||
break;
|
||||
|
||||
case 24:
|
||||
xprintf("spurious interrupt");
|
||||
break;
|
||||
|
||||
default:
|
||||
if ( ((vector >= 6) && (vector <= 7)) ||
|
||||
((vector >= 16) && (vector <= 23)))
|
||||
{
|
||||
xprintf("reserved");
|
||||
}
|
||||
else if ((vector >= 25) && (vector <= 31))
|
||||
{
|
||||
xprintf("level %d autovectored interrupt", fault_status - 24);
|
||||
}
|
||||
else if ((vector >= 32) && (vector <= 47))
|
||||
{
|
||||
xprintf("trap #%d", vector - 32);
|
||||
}
|
||||
else
|
||||
{
|
||||
xprintf("unknown vector\r\n");
|
||||
}
|
||||
}
|
||||
xprintf(")\r\n");
|
||||
xprintf("sr=%4x\r\n", sr);
|
||||
|
||||
__asm__ __volatile__(
|
||||
" move.w 0x2700,d0 \r\n" // disable interrupts
|
||||
" move.w d0,sr \r\n"
|
||||
" halt \r\n" // stop processor
|
||||
: /* no output */
|
||||
: /* no input */
|
||||
: "memory");
|
||||
}
|
||||
|
||||
void __attribute__((interrupt)) handler(void)
|
||||
{
|
||||
/*
|
||||
* Prepare exception stack contents so it can be handled by a C routine.
|
||||
*
|
||||
* For standard routines, we'd have to save registers here.
|
||||
* Since we do not intend to return anyway, we just ignore that requirement.
|
||||
*/
|
||||
__asm__ __volatile__("move.l (sp),-(sp)\n\t"\
|
||||
"move.l 8(sp),-(sp)\n\t"\
|
||||
"bsr _fault_handler\n\t"\
|
||||
"halt\n\t"\
|
||||
: : : "memory");
|
||||
}
|
||||
|
||||
void setup_vectors(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
xprintf("\r\ninstall early exception vector table:");
|
||||
|
||||
for (i = 8; i < 256; i++)
|
||||
{
|
||||
SDRAM_VECTOR_TABLE[i] = &handler;
|
||||
}
|
||||
|
||||
/*
|
||||
* make sure VBR points to our table
|
||||
*/
|
||||
__asm__ __volatile__("clr.l d0\n\t"\
|
||||
"movec.l d0,VBR\n\t"\
|
||||
"nop\n\t"\
|
||||
"move.l d0,_rt_vbr"
|
||||
: /* outputs */
|
||||
: /* inputs */
|
||||
: "d0", "memory", "cc" /* clobbered registers */
|
||||
);
|
||||
|
||||
xprintf("finished.\r\n");
|
||||
}
|
||||
201
sys/init_fpga.c
Normal file
201
sys/init_fpga.c
Normal file
@@ -0,0 +1,201 @@
|
||||
/*
|
||||
* init_fpga.c
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Copyright 2010 - 2012 F. Aschwanden
|
||||
* Copyright 2011 - 2012 V. Riviere
|
||||
* Copyright 2012 M. Froeschle
|
||||
*
|
||||
*/
|
||||
|
||||
#include "MCF5475.h"
|
||||
#include "sysinit.h"
|
||||
#include "bas_printf.h"
|
||||
#include "wait.h"
|
||||
|
||||
// #define FPGA_DEBUG
|
||||
#if defined(FPGA_DEBUG)
|
||||
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
|
||||
#else
|
||||
#define dbg(format, arg...) do { ; } while (0)
|
||||
#endif
|
||||
|
||||
#define FPGA_STATUS (1 << 0)
|
||||
#define FPGA_CLOCK (1 << 1)
|
||||
#define FPGA_CONFIG (1 << 2)
|
||||
#define FPGA_DATA0 (1 << 3)
|
||||
#define FPGA_CONF_DONE (1 << 5)
|
||||
|
||||
extern uint8_t _FPGA_CONFIG[];
|
||||
#define FPGA_FLASH_DATA &_FPGA_CONFIG[0]
|
||||
extern uint8_t _FPGA_CONFIG_SIZE[];
|
||||
#define FPGA_FLASH_DATA_SIZE ((uint32_t) &_FPGA_CONFIG_SIZE[0])
|
||||
|
||||
/*
|
||||
* flag located in processor SRAM1 that indicates that the FPGA configuration has
|
||||
* been loaded through the onboard JTAG interface.
|
||||
* init_fpga() will honour this and not overwrite config.
|
||||
*/
|
||||
extern uint32_t _FPGA_JTAG_LOADED;
|
||||
extern uint32_t _FPGA_JTAG_VALID;
|
||||
#define VALID_JTAG 0xaffeaffe
|
||||
|
||||
void config_gpio_for_fpga_config(void)
|
||||
{
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
/*
|
||||
* Configure GPIO FEC1L port directions (needed to load FPGA configuration)
|
||||
*/
|
||||
MCF_GPIO_PDDR_FEC1L = 0 | /* bit 7 = input */
|
||||
0 | /* bit 6 = input */
|
||||
0 | /* bit 5 = input */
|
||||
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 | /* bit 4 = LED => output */
|
||||
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 | /* bit 3 = PRG_DQ0 => output */
|
||||
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 | /* bit 2 = FPGA_CONFIG => output */
|
||||
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 | /* bit 1 = PRG_CLK (FPGA) => output */
|
||||
0; /* bit 0 => input */
|
||||
#endif /* MACHINE_FIREBEE */
|
||||
}
|
||||
|
||||
void config_gpio_for_jtag_config(void)
|
||||
{
|
||||
/*
|
||||
* configure FEC1L port directions to enable external JTAG configuration download to FPGA
|
||||
*/
|
||||
MCF_GPIO_PDDR_FEC1L = 0 |
|
||||
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4; /* bit 4 = LED => output */
|
||||
/* all other bits = input */
|
||||
/*
|
||||
* unfortunately, the GPIO module cannot trigger interrupts. That means CONF_DONE needs to be polled to detect
|
||||
* external FPGA (re)configuration and reset the system in that case. Could be done from the OS as well...
|
||||
*/
|
||||
}
|
||||
|
||||
/*
|
||||
* load FPGA
|
||||
*/
|
||||
bool init_fpga(void)
|
||||
{
|
||||
uint8_t *fpga_data;
|
||||
volatile int32_t time, start, end;
|
||||
int i;
|
||||
|
||||
xprintf("FPGA load config...\r\n");
|
||||
xprintf("_FPGA_JTAG_LOADED = 0x%x\r\n", _FPGA_JTAG_LOADED);
|
||||
xprintf("_FPGA_JTAG_VALID = 0x%x\r\n", _FPGA_JTAG_VALID);
|
||||
if (_FPGA_JTAG_LOADED == 1 && _FPGA_JTAG_VALID == VALID_JTAG)
|
||||
{
|
||||
xprintf("detected _FPGA_JTAG_LOADED flag. FPGA config skipped.\r\n");
|
||||
|
||||
/* reset the flag so that next boot will load config again from flash */
|
||||
// _FPGA_JTAG_LOADED = 0;
|
||||
// _FPGA_JTAG_VALID = 0;
|
||||
|
||||
return true;
|
||||
}
|
||||
start = MCF_SLT0_SCNT;
|
||||
|
||||
config_gpio_for_fpga_config();
|
||||
MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK; /* FPGA clock => low */
|
||||
|
||||
/* pulling FPGA_CONFIG to low resets the FPGA */
|
||||
MCF_GPIO_PODR_FEC1L &= ~FPGA_CONFIG; /* FPGA config => low */
|
||||
wait(10); /* give it some time to do its reset stuff */
|
||||
|
||||
while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS) && (MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));
|
||||
|
||||
MCF_GPIO_PODR_FEC1L |= FPGA_CONFIG; /* pull FPGA_CONFIG high to start config cycle */
|
||||
while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS))
|
||||
; /* wait until status becomes high */
|
||||
|
||||
/*
|
||||
* excerpt from an Altera configuration manual:
|
||||
*
|
||||
* The low-to-high transition of nCONFIG on the FPGA begins the configuration cycle. The
|
||||
* configuration cycle consists of 3 stages: reset, configuration, and initialization.
|
||||
* While nCONFIG is low, the device is in reset. When the device comes out of reset,
|
||||
* nCONFIG must be at a logic high level in order for the device to release the open-drain
|
||||
* nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the FPGA
|
||||
* is ready to receive configuration data. Before and during configuration, all user I/O pins
|
||||
* are tri-stated. Stratix series, Arria series, and Cyclone series have weak pull-up resistors
|
||||
* on the I/O pins which are on, before and during configuration.
|
||||
*
|
||||
* To begin configuration, nCONFIG and nSTATUS must be at a logic high level. You can delay
|
||||
* configuration by holding the nCONFIG low. The device receives configuration data on its
|
||||
* DATA0 pins. Configuration data is latched into the FPGA on the rising edge of DCLK. After
|
||||
* the FPGA has received all configuration data successfully, it releases the CONF_DONE pin,
|
||||
* which is pulled high by a pull-up resistor. A low to high transition on CONF_DONE indicates
|
||||
* configuration is complete and initialization of the device can begin.
|
||||
*/
|
||||
|
||||
const uint8_t *fpga_flash_data_end = FPGA_FLASH_DATA + FPGA_FLASH_DATA_SIZE;
|
||||
|
||||
fpga_data = (uint8_t *) FPGA_FLASH_DATA;
|
||||
do
|
||||
{
|
||||
uint8_t value = *fpga_data++;
|
||||
for (i = 0; i < 8; i++, value >>= 1)
|
||||
{
|
||||
|
||||
if (value & 1)
|
||||
{
|
||||
/* bit set -> toggle DATA0 to high */
|
||||
MCF_GPIO_PODR_FEC1L |= FPGA_DATA0;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* bit is cleared -> toggle DATA0 to low */
|
||||
MCF_GPIO_PODR_FEC1L &= ~FPGA_DATA0;
|
||||
}
|
||||
/* toggle DCLK -> FPGA reads the bit */
|
||||
MCF_GPIO_PODR_FEC1L |= FPGA_CLOCK;
|
||||
MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK;
|
||||
}
|
||||
} while ((!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)) && (fpga_data < fpga_flash_data_end));
|
||||
|
||||
if (fpga_data < fpga_flash_data_end)
|
||||
{
|
||||
#ifdef _NOT_USED_
|
||||
while (fpga_data++ < fpga_flash_data_end)
|
||||
{
|
||||
/* toggle a little more since it's fun ;) */
|
||||
MCF_GPIO_PODR_FEC1L |= FPGA_CLOCK;
|
||||
MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK;
|
||||
}
|
||||
#endif /* _NOT_USED_ */
|
||||
end = MCF_SLT0_SCNT;
|
||||
time = (start - end) / (SYSCLK / 1000) / 1000;
|
||||
|
||||
xprintf("finished (took %f seconds).\r\n", time / 1000.0);
|
||||
config_gpio_for_jtag_config();
|
||||
|
||||
/*
|
||||
* assure skipping fpga load on warm boot
|
||||
*/
|
||||
|
||||
_FPGA_JTAG_LOADED = 1;
|
||||
_FPGA_JTAG_VALID = VALID_JTAG;
|
||||
|
||||
xprintf("SRAM now set to FPGA load skip\r\n");
|
||||
|
||||
return true;
|
||||
}
|
||||
xprintf("FAILED!\r\n");
|
||||
config_gpio_for_jtag_config();
|
||||
|
||||
return false;
|
||||
}
|
||||
685
sys/interrupts.c
Normal file
685
sys/interrupts.c
Normal file
@@ -0,0 +1,685 @@
|
||||
/*
|
||||
* Interrupts
|
||||
*
|
||||
* Handle interrupts, the levels.
|
||||
*
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 26.02.2013
|
||||
* Author: Markus Fröschle
|
||||
*/
|
||||
|
||||
#include <bas_types.h>
|
||||
#include "MCF5475.h"
|
||||
#include "bas_utils.h"
|
||||
#include "bas_printf.h"
|
||||
#include "bas_string.h"
|
||||
#include "exceptions.h"
|
||||
#include "interrupts.h"
|
||||
#include "bas_printf.h"
|
||||
#include "startcf.h"
|
||||
#include "cache.h"
|
||||
#include "util.h"
|
||||
#include "dma.h"
|
||||
#include "pci.h"
|
||||
#include <stdarg.h>
|
||||
|
||||
// #define DEBUG
|
||||
#include "debug.h"
|
||||
|
||||
#ifndef MAX_ISR_ENTRY
|
||||
#define MAX_ISR_ENTRY (20)
|
||||
#endif
|
||||
|
||||
|
||||
struct isrentry
|
||||
{
|
||||
int vector;
|
||||
bool (*handler)(void *, void *);
|
||||
void *hdev;
|
||||
void *harg;
|
||||
};
|
||||
|
||||
static struct isrentry isrtab[MAX_ISR_ENTRY]; /* list of interrupt service routines */
|
||||
|
||||
|
||||
/*
|
||||
* clear the table of interrupt service handlers
|
||||
*/
|
||||
void isr_init(void)
|
||||
{
|
||||
memset(isrtab, 0, sizeof(isrtab));
|
||||
}
|
||||
|
||||
bool isr_set_prio_and_level(int int_source, int priority, int level)
|
||||
{
|
||||
if (int_source > 8 && int_source <= 62)
|
||||
{
|
||||
/*
|
||||
* preset interrupt control registers with level and priority
|
||||
*/
|
||||
dbg("set MCF_INTC_ICR(%d) to priority %d, level %d\r\n",
|
||||
int_source, priority, level);
|
||||
MCF_INTC_ICR(int_source) = MCF_INTC_ICR_IP(priority) |
|
||||
MCF_INTC_ICR_IL(level);
|
||||
}
|
||||
else if (int_source >= 1 && int_source <= 8)
|
||||
{
|
||||
dbg("interrrupt control register for vector %d is read only!\r\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
err("invalid vector - interrupt control register not set.\r\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* enable internal int source in interrupt controller
|
||||
*/
|
||||
bool isr_enable_int_source(int int_source)
|
||||
{
|
||||
dbg("anding int_source %d, MCF_INTC_IMR%c = 0x%08x, now 0x%08x\r\n",
|
||||
int_source,
|
||||
int_source < 32 && int_source > 0 ? 'L' :
|
||||
int_source >= 32 && int_source <= 62 ? 'H' : 'U',
|
||||
int_source < 32 && int_source > 0 ? ~(1 << int_source) :
|
||||
int_source >= 32 && int_source <= 62 ? ~(1 << (int_source - 32)) : 0,
|
||||
MCF_INTC_IMRH);
|
||||
|
||||
if (int_source < 32 && int_source > 0)
|
||||
{
|
||||
MCF_INTC_IMRL &= ~(1 << int_source);
|
||||
}
|
||||
else if (int_source >= 32 && int_source <= 62)
|
||||
{
|
||||
MCF_INTC_IMRH &= ~(1 << (int_source - 32));
|
||||
}
|
||||
else
|
||||
{
|
||||
dbg("vector %d does not correspond to an internal interrupt source\r\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function places an interrupt handler in the ISR table,
|
||||
* thereby registering it so that the low-level handler may call it.
|
||||
*
|
||||
* The two parameters are intended for the first arg to be a
|
||||
* pointer to the device itself, and the second a pointer to a data
|
||||
* structure used by the device driver for that particular device.
|
||||
*/
|
||||
bool isr_register_handler(int vector, int level, int priority, bool (*handler)(void *, void *), void *hdev, void *harg)
|
||||
{
|
||||
int index;
|
||||
int int_source;
|
||||
|
||||
if ((vector <= 0) || (handler == NULL))
|
||||
{
|
||||
dbg("illegal vector or handler (vector=%x, handler=%p)!\r\n", vector, handler);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
for (index = 0; index < MAX_ISR_ENTRY; index++)
|
||||
{
|
||||
if (isrtab[index].vector == vector)
|
||||
{
|
||||
/* one cross each, only! */
|
||||
dbg("already set handler with this vector (%d, %d)\r\n", vector);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
if (isrtab[index].vector == 0)
|
||||
{
|
||||
isrtab[index].vector = vector;
|
||||
isrtab[index].handler = handler;
|
||||
isrtab[index].hdev = hdev;
|
||||
isrtab[index].harg = harg;
|
||||
|
||||
int_source = vector - 64;
|
||||
|
||||
if (int_source >= 0)
|
||||
{
|
||||
if (!isr_enable_int_source(int_source))
|
||||
{
|
||||
dbg("failed to enable internal interrupt souce %d in IMRL/IMRH\r\n", int_source);
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!isr_set_prio_and_level(int_source, priority, level))
|
||||
{
|
||||
dbg("failed to set priority and level for interrupt source %d\r\n", int_source);
|
||||
return false;
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
}
|
||||
dbg("no available slots to register handler for vector %d\n\r", vector);
|
||||
|
||||
return false; /* no available slots */
|
||||
}
|
||||
|
||||
void isr_remove_handler(bool (*handler)(void *, void *))
|
||||
{
|
||||
/*
|
||||
* This routine removes from the ISR table all
|
||||
* entries that matches 'handler'.
|
||||
*/
|
||||
int index;
|
||||
|
||||
for (index = 0; index < MAX_ISR_ENTRY; index++)
|
||||
{
|
||||
if (isrtab[index].handler == handler)
|
||||
{
|
||||
memset(&isrtab[index], 0, sizeof(struct isrentry));
|
||||
|
||||
return;
|
||||
}
|
||||
}
|
||||
dbg("no such handler registered (handler=%p\r\n", handler);
|
||||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
static char *vector_to_str[] =
|
||||
{
|
||||
"initial stack pointer", /* 0 */
|
||||
"initial program counter", /* 1 */
|
||||
"access error", /* 2 */
|
||||
"address error", /* 3 */
|
||||
"illegal instruction", /* 4 */
|
||||
"divide by zero", /* 5 */
|
||||
"reserved6", /* 6 */
|
||||
"reserved7", /* 7 */
|
||||
"privilege violation", /* 8 */
|
||||
"trace", /* 9 */
|
||||
"unimplemented line-a opcode", /* 10 */
|
||||
"unimplemented line-f opcode", /* 11 */
|
||||
"non-PC breakpoint debug interrupt", /* 12 */
|
||||
"PC breakpoint debug interrupt", /* 13 */
|
||||
"format error", /* 14 */
|
||||
"uninitialized interrupt", /* 15 */
|
||||
"reserved16",
|
||||
"reserved17",
|
||||
"reserved18",
|
||||
"reserved19",
|
||||
"reserved20",
|
||||
"reserved21",
|
||||
"reserved22",
|
||||
"reserved23",
|
||||
"spurious interrupt", /* 24 */
|
||||
"level 1 autovector", /* 25 */
|
||||
"level 2 autovector", /* 26 */
|
||||
"level 3 autovector", /* 27 */
|
||||
"level 4 autovector", /* 28 */
|
||||
"level 5 autovector", /* 29 */
|
||||
"level 6 autovector", /* 30 */
|
||||
"level 7 autovector", /* 31 */
|
||||
"trap #0", /* 32 */
|
||||
"trap #1", /* 33 */
|
||||
"trap #2", /* 34 */
|
||||
"trap #3", /* 35 */
|
||||
"trap #4", /* 36 */
|
||||
"trap #5", /* 37 */
|
||||
"trap #6", /* 38 */
|
||||
"trap #7", /* 39 */
|
||||
"trap #8", /* 40 */
|
||||
"trap #9", /* 41 */
|
||||
"trap #10" /* 42 */
|
||||
"trap #11", /* 43 */
|
||||
"trap #12", /* 44 */
|
||||
"trap #13", /* 45 */
|
||||
"trap #14", /* 46 */
|
||||
"trap #15", /* 47 */
|
||||
"floating point branch on unordered condition", /* 48 */
|
||||
"floting point inexact result", /* 49 */
|
||||
"floating point divide by zero", /* 50 */
|
||||
"floating point underflow", /* 51 */
|
||||
"floating point operand error", /* 52 */
|
||||
"floating point overflow", /* 53 */
|
||||
"floating point NaN", /* 54 */
|
||||
"floating point denormalized number", /* 55 */
|
||||
"reserved56", /* 56 */
|
||||
"reserved57",
|
||||
"reserved58",
|
||||
"reserved59",
|
||||
"reserved60",
|
||||
"unsupported instruction", /* 61 */
|
||||
"reserved62", /* 62 */
|
||||
"reserved63", /* 63 */
|
||||
"", "",
|
||||
"edge port 1", /* 1 */
|
||||
"edge port 2", /* 2 */
|
||||
"edge port 3", /* 3 */
|
||||
"edge port 4", /* 4 */
|
||||
"edge port 5", /* 5 */
|
||||
"edge port 6", /* 6 */
|
||||
"edge port 7", /* 7 */
|
||||
"unused8",
|
||||
"unused9",
|
||||
"unused10",
|
||||
"unused11",
|
||||
"unused12",
|
||||
"unused13",
|
||||
"unused14",
|
||||
"USB endpoint 0", /* 15 */
|
||||
"USB endpoint 1", /* 16 */
|
||||
"USB endpoint 2", /* 17 */
|
||||
"USB endpoint 3", /* 18 */
|
||||
"USB endpoint 4", /* 19 */
|
||||
"USB endpoint 5", /* 20 */
|
||||
"USB endpoint 6", /* 21 */
|
||||
"USB general interrupt", /* 22 */
|
||||
"USB core interrupt", /* 23 */
|
||||
"USB OR interrupt", /* 24 */
|
||||
"DSPI over/underflow", /* 25 */
|
||||
"DSPI receive FIFO overflow", /* 26 */
|
||||
"DSPI receive FIFO drain", /* 27 */
|
||||
"DSPI transmit FIFO underflow", /* 28 */
|
||||
"DSPI transfer complete", /* 29 */
|
||||
"DSPI trasmit FIFO full", /* 30 */
|
||||
"DSPI end of queue", /* 31 */
|
||||
"PSC3", /* 32 */
|
||||
"PSC2", /* 33 */
|
||||
"PSC1", /* 34 */
|
||||
"PSC0", /* 35 */
|
||||
"Comm timer", /* 36 */
|
||||
"SEC", /* 37 */
|
||||
"FEC1", /* 38 */
|
||||
"FEC0", /* 39 */
|
||||
"I2C", /* 40 */
|
||||
"PCI arbiter", /* 41 */
|
||||
"comm bus PCI", /* 42 */
|
||||
"XLB PCI", /* 43 */
|
||||
"not used44",
|
||||
"not used45",
|
||||
"not used46",
|
||||
"XLB arbiter to CPU", /* 47 */
|
||||
"multichannel DMA", /* 48 */
|
||||
"FlexCAN 0 error", /* 49 */
|
||||
"FlexCAN 0 bus off", /* 50 */
|
||||
"FlexCAN 0 message buffer", /* 51 */
|
||||
"not used52"
|
||||
"slice timer 1", /* 53 */
|
||||
"slice timer 0", /* 54 */
|
||||
"FlexCAN 1 error", /* 55 */
|
||||
"FlexCAN 1 bus off", /* 56 */
|
||||
"FlexCAN 1 message buffer", /* 57 */
|
||||
"not used58",
|
||||
"GPT3", /* 59 */
|
||||
"GPT2", /* 60 */
|
||||
"GPT1", /* 61 */
|
||||
"GPT0", /* 62 */
|
||||
"not used63"
|
||||
};
|
||||
#endif /* DEBUG */
|
||||
|
||||
/*
|
||||
* This routine searches the ISR table for an entry that matches
|
||||
* 'vector'. If one is found, then 'handler' is executed.
|
||||
*
|
||||
* This routine returns either true or false where
|
||||
* true = interrupt has been handled, return to caller
|
||||
* false= interrupt has been handled or hasn't, but needs to be forwarded to TOS
|
||||
*/
|
||||
bool isr_execute_handler(int vector)
|
||||
{
|
||||
int index;
|
||||
|
||||
dbg("vector = %d (%s)\r\n", vector, vector_to_str[vector]);
|
||||
|
||||
/*
|
||||
* locate an interrupt service routine handler.
|
||||
*/
|
||||
for (index = 0; index < MAX_ISR_ENTRY; index++)
|
||||
{
|
||||
if (isrtab[index].vector == vector)
|
||||
{
|
||||
isrtab[index].handler(isrtab[index].hdev, isrtab[index].harg);
|
||||
return true;
|
||||
}
|
||||
}
|
||||
err("no isr handler for vector %d found. Spurious?\r\n", vector);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
/*
|
||||
* PIC interrupt handler for Firebee
|
||||
*
|
||||
* Handles PIC requests that come in from PSC3 serial interface. Currently, that
|
||||
* is RTC/NVRAM requests only
|
||||
*/
|
||||
bool pic_interrupt_handler(void *arg1, void *arg2)
|
||||
{
|
||||
uint8_t rcv_byte;
|
||||
|
||||
dbg("PIC interrupt\r\n");
|
||||
|
||||
rcv_byte = read_pic_byte();
|
||||
if (rcv_byte == 2) /* PIC requests RTC data */
|
||||
{
|
||||
volatile uint8_t *rtc_reg = (uint8_t *) 0xffff8961;
|
||||
volatile uint8_t *rtc_data = (uint8_t *) 0xffff8963;
|
||||
int index = 0;
|
||||
|
||||
err("PIC interrupt: requesting RTC data\r\n");
|
||||
|
||||
write_pic_byte(0x82); // header byte to PIC
|
||||
do
|
||||
{
|
||||
*rtc_reg = index;
|
||||
write_pic_byte(*rtc_data);
|
||||
} while (++index < 64);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
#endif /* MACHINE_FIREBEE */
|
||||
|
||||
bool xlbpci_interrupt_handler(void *arg1, void *arg2)
|
||||
{
|
||||
uint32_t reason;
|
||||
|
||||
dbg("XLB PCI interrupt\r\n");
|
||||
|
||||
reason = MCF_PCI_PCIISR;
|
||||
|
||||
if (reason & MCF_PCI_PCIISR_RE)
|
||||
{
|
||||
dbg("Retry error. Retry terminated or max retries reached. Cleared\r\n");
|
||||
MCF_PCI_PCIISR |= MCF_PCI_PCIISR_RE;
|
||||
}
|
||||
|
||||
if (reason & MCF_PCI_PCIISR_IA)
|
||||
{
|
||||
dbg("Initiator abort. No target answered in time. Cleared.\r\n");
|
||||
MCF_PCI_PCIISR |= MCF_PCI_PCIISR_IA;
|
||||
}
|
||||
|
||||
if (reason & MCF_PCI_PCIISR_TA)
|
||||
{
|
||||
dbg("Target abort. Cleared.\r\n");
|
||||
MCF_PCI_PCIISR |= MCF_PCI_PCIISR_TA;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool pciarb_interrupt_handler(void *arg1, void *arg2)
|
||||
{
|
||||
dbg("PCI ARB interrupt\r\n");
|
||||
|
||||
MCF_PCIARB_PASR |= MCF_PCIARB_PASR_EXTMBK(0x1f) | MCF_PCIARB_PASR_ITLMBK;
|
||||
return true;
|
||||
}
|
||||
|
||||
bool xlbarb_interrupt_handler(void *arg1, void *arg2)
|
||||
{
|
||||
uint32_t status = MCF_XLB_XARB_SR;
|
||||
|
||||
dbg("arg1=0x%08x arg2=0x%08x\r\n", arg1, arg2);
|
||||
|
||||
/*
|
||||
* TODO: we should probably issue a bus error when this occors
|
||||
*/
|
||||
err("XLB arbiter interrupt\r\n");
|
||||
err("captured address: 0x%08lx\r\n", MCF_XLB_XARB_ADRCAP);
|
||||
|
||||
MCF_XLB_XARB_ADRCAP = 0x0L;
|
||||
MCF_XLB_XARB_SIGCAP = 0x0L;
|
||||
|
||||
if (status & MCF_XLB_XARB_SR_AT)
|
||||
err("address tenure timeout\r\n");
|
||||
if (status & MCF_XLB_XARB_SR_DT)
|
||||
err("data tenure timeout\r\n");
|
||||
if (status & MCF_XLB_XARB_SR_BA)
|
||||
err("bus activity tenure timeout\r\n");
|
||||
if (status & MCF_XLB_XARB_SR_TTM)
|
||||
err("TBST/TSIZ mismatch\r\n");
|
||||
if (status & MCF_XLB_XARB_SR_ECW)
|
||||
err("external control word read/write\r\n");
|
||||
if (status & MCF_XLB_XARB_SR_TTR)
|
||||
err("TT reserved\r\n");
|
||||
if (status & MCF_XLB_XARB_SR_TTA)
|
||||
err("TT address only\r\n");
|
||||
if (status & MCF_XLB_XARB_SR_MM)
|
||||
err("multiple masters at priority 0\r\n");
|
||||
if (status & MCF_XLB_XARB_SR_SEA)
|
||||
err("slave error acknowledge\r\n");
|
||||
|
||||
/*
|
||||
* acknowledge interrupt
|
||||
*/
|
||||
MCF_XLB_XARB_SR = status; /* rwc bits */
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
/*
|
||||
* This gets called from irq5 in exceptions.S
|
||||
*
|
||||
* IRQ5 are the "FBEE" (PIC, ETH PHY, PCI, DVI monitor sense and DSP) interrupts multiplexed by the FPGA interrupt handler
|
||||
*/
|
||||
bool irq5_handler(void *arg1, void *arg2)
|
||||
{
|
||||
uint32_t pending_interrupts = FBEE_INTR_PENDING;
|
||||
|
||||
dbg("IRQ5!\r\n");
|
||||
if (pending_interrupts & FBEE_INTR_PIC)
|
||||
{
|
||||
dbg("PIC interrupt\r\n");
|
||||
FBEE_INTR_CLEAR = FBEE_INTR_PIC;
|
||||
}
|
||||
|
||||
if (pending_interrupts & FBEE_INTR_ETHERNET)
|
||||
{
|
||||
dbg("ethernet 0 PHY interrupt\r\n");
|
||||
FBEE_INTR_CLEAR = FBEE_INTR_ETHERNET;
|
||||
}
|
||||
|
||||
if (pending_interrupts & FBEE_INTR_DVI)
|
||||
{
|
||||
dbg("DVI monitor sense interrupt\r\n");
|
||||
FBEE_INTR_CLEAR = FBEE_INTR_DVI;
|
||||
}
|
||||
|
||||
if (pending_interrupts & FBEE_INTR_PCI_INTA ||
|
||||
pending_interrupts & FBEE_INTR_PCI_INTB ||
|
||||
pending_interrupts & FBEE_INTR_PCI_INTC ||
|
||||
pending_interrupts & FBEE_INTR_PCI_INTD)
|
||||
{
|
||||
int handle;
|
||||
|
||||
if ((handle = pci_get_interrupt_cause() != -1))
|
||||
{
|
||||
pci_call_interrupt_chain(handle, 0L);
|
||||
}
|
||||
dbg("PCI interrupt IRQ5\r\n");
|
||||
FBEE_INTR_CLEAR = FBEE_INTR_PCI_INTA |
|
||||
FBEE_INTR_PCI_INTB |
|
||||
FBEE_INTR_PCI_INTC |
|
||||
FBEE_INTR_PCI_INTD;
|
||||
}
|
||||
|
||||
if (pending_interrupts & FBEE_INTR_DSP)
|
||||
{
|
||||
dbg("DSP interrupt\r\n");
|
||||
FBEE_INTR_CLEAR = FBEE_INTR_DSP;
|
||||
}
|
||||
|
||||
MCF_EPORT_EPFR |= (1 << 5); /* clear interrupt from edge port */
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* blink the Firebee's LED to show we are still alive
|
||||
*/
|
||||
void blink_led(void)
|
||||
{
|
||||
static uint16_t blinker = 0;
|
||||
|
||||
if ((blinker++ & 0x80) > 0)
|
||||
{
|
||||
MCF_GPIO_PODR_FEC1L |= (1 << 4); /* LED off */
|
||||
}
|
||||
else
|
||||
{
|
||||
MCF_GPIO_PODR_FEC1L &= ~(1 << 4); /* LED on */
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Atari MFP interrupt registers.
|
||||
*
|
||||
* TODO: should go into a header file
|
||||
*/
|
||||
|
||||
#define FALCON_MFP_IERA *((volatile uint8_t *) 0xfffffa07)
|
||||
#define FALCON_MFP_IERB *((volatile uint8_t *) 0xfffffa09)
|
||||
#define FALCON_MFP_IPRA *((volatile uint8_t *) 0xfffffa0b)
|
||||
#define FALCON_MFP_IPRB *((volatile uint8_t *) 0xfffffa0d)
|
||||
#define FALCON_MFP_IMRA *((volatile uint8_t *) 0xfffffa13)
|
||||
#define FALCON_MFP_IMRB *((volatile uint8_t *) 0xfffffa15)
|
||||
|
||||
bool irq6_acsi_dma_interrupt(void)
|
||||
{
|
||||
dbg("ACSI DMA interrupt\r\n");
|
||||
|
||||
/*
|
||||
* TODO: implement handler
|
||||
*/
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
bool irq6_handler(uint32_t sf1, uint32_t sf2)
|
||||
{
|
||||
//err("IRQ6!\r\n");
|
||||
|
||||
if (FALCON_MFP_IPRA || FALCON_MFP_IPRB)
|
||||
{
|
||||
blink_led();
|
||||
}
|
||||
|
||||
MCF_EPORT_EPFR |= (1 << 6); /* clear int6 from edge port */
|
||||
|
||||
return false; /* always forward IRQ6 to TOS */
|
||||
}
|
||||
|
||||
#else /* MACHINE_FIREBEE */
|
||||
|
||||
bool irq5_handler(void *arg1, void *arg2)
|
||||
{
|
||||
MCF_EPORT_EPFR |= (1 << 5); /* clear int5 from edge port */
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool irq6_handler(void *arg1, void *arg2)
|
||||
{
|
||||
err("IRQ6!\r\n");
|
||||
|
||||
MCF_EPORT_EPFR |= (1 << 6); /* clear int6 from edge port */
|
||||
|
||||
return false; /* always forward IRQ6 to TOS */
|
||||
}
|
||||
|
||||
/*
|
||||
* This gets called from irq7 in exceptions.S
|
||||
* Once we arrive here, the SR has been set to disable interrupts and the gcc scratch registers have been saved
|
||||
*/
|
||||
bool irq7_handler(void)
|
||||
{
|
||||
int32_t handle;
|
||||
int32_t value = 0;
|
||||
int32_t newvalue;
|
||||
|
||||
MCF_EPORT_EPFR |= (1 << 7);
|
||||
dbg("IRQ7!\r\n");
|
||||
if ((handle = pci_get_interrupt_cause()) > 0)
|
||||
{
|
||||
newvalue = pci_call_interrupt_chain(handle, value);
|
||||
if (newvalue == value)
|
||||
{
|
||||
dbg("interrupt not handled!\r\n");
|
||||
}
|
||||
}
|
||||
MCF_EPORT_EPFR |= (1 << 7); /* clear int7 from edge port */
|
||||
|
||||
return true;
|
||||
}
|
||||
#endif /* MACHINE_M548X */
|
||||
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
/*
|
||||
* this is the higlevel interrupt service routine for gpt0 timer interrupts.
|
||||
*
|
||||
* It is called from handler_gpt0 in exceptions.S
|
||||
*
|
||||
* The gpt0 timer is not used as a timer, but as interrupt trigger by the FPGA which fires
|
||||
* everytime the video base address high byte (0xffff8201) gets written by user code (i.e.
|
||||
* everytime the video base address is set).
|
||||
* The interrupt service routine checks if that page was already set as a video page (in that
|
||||
* case it does nothing), if not (if we have a newly set page), it sets up an MMU mapping for
|
||||
* that page (effectively rerouting any further access to Falcon video RAM to Firebee FPGA
|
||||
* video RAM starting at 0x60000000) and copies SDRAM contents of that page to the video
|
||||
* RAM page.
|
||||
*/
|
||||
bool gpt0_interrupt_handler(void *arg0, void *arg1)
|
||||
{
|
||||
dbg("gpt0 handler called\n\r");
|
||||
|
||||
MCF_GPT0_GMS &= ~1; /* rearm trigger */
|
||||
NOP();
|
||||
MCF_GPT0_GMS |= 1;
|
||||
|
||||
return true;
|
||||
}
|
||||
#endif /* MACHINE_FIREBEE */
|
||||
|
||||
|
||||
uint32_t set_ipl(uint32_t ipl)
|
||||
{
|
||||
uint32_t ret;
|
||||
|
||||
__asm__ __volatile__(
|
||||
" move.w sr,%[ret]\r\n" /* retrieve status register */
|
||||
" andi.l #0x07,%[ipl]\n\t" /* mask out ipl bits on new value */
|
||||
" lsl.l #8,%[ipl]\n\t" /* shift them to position */
|
||||
" move.l %[ret],d0\n\t" /* retrieve original value */
|
||||
" andi.l #0x0000f8ff,d0\n\t" /* clear ipl part */
|
||||
" or.l %[ipl],d0\n\t" /* or in new value */
|
||||
" move.w d0,sr\n\t" /* put it in place */
|
||||
" andi.l #0x0700,%[ret]\r\n" /* mask out ipl bits */
|
||||
" lsr.l #8,%[ret]\r\n" /* shift them to position */
|
||||
: [ret] "=&d" (ret) /* output */
|
||||
: [ipl] "d" (ipl) /* input */
|
||||
: "d0", "cc" /* clobber */
|
||||
);
|
||||
|
||||
return ret;
|
||||
}
|
||||
76
sys/startcf.S
Normal file
76
sys/startcf.S
Normal file
@@ -0,0 +1,76 @@
|
||||
|
||||
//
|
||||
// This object file must be the first to be linked,
|
||||
// so it will be placed at the very beginning of the ROM.
|
||||
//
|
||||
|
||||
.equ MCF_MMU_MMUCR, __MMUBAR + 0
|
||||
|
||||
.globl _rom_header
|
||||
.globl _rom_entry
|
||||
|
||||
.extern _initialize_hardware
|
||||
.extern _rt_mbar
|
||||
|
||||
/* ROM header */
|
||||
_rom_header:
|
||||
//
|
||||
// The first long is supposed to be the initial SP.
|
||||
// We replace it by bra.s to allow running the ROM from the first byte.
|
||||
// Then we add a fake jmp instruction for pretty disassembly.
|
||||
//
|
||||
bra.s _rom_entry // Short jump to the real entry point
|
||||
.short 0x4ef9 // Fake jmp instruction
|
||||
// The second long is the initial PC
|
||||
.long _rom_entry // Real entry point
|
||||
|
||||
/* ROM entry point */
|
||||
_rom_entry:
|
||||
// disable interrupts
|
||||
move.w #0x2700,sr
|
||||
|
||||
#if !defined(MACHINE_M54455) // MCF54455 does not have the MBAR register
|
||||
/* Initialize MBAR */
|
||||
move.l #__MBAR,d0
|
||||
movec d0,MBAR
|
||||
move.l d0,_rt_mbar
|
||||
#endif
|
||||
|
||||
/* mmu off */
|
||||
move.l #__MMUBAR+1,d0
|
||||
movec d0,MMUBAR
|
||||
|
||||
clr.l d0
|
||||
move.l d0,MCF_MMU_MMUCR
|
||||
nop
|
||||
|
||||
#if !defined(MACHINE_M54455) // MCF54455 does not have RAMBAR0 and RAMBAR1 registers */
|
||||
|
||||
// Initialize RAMBARs: locate SRAM and validate it
|
||||
move.l #__RAMBAR0 + 0x7,d0 // supervisor only
|
||||
movec d0,RAMBAR0
|
||||
move.l #__RAMBAR1 + 0x1,d0
|
||||
movec d0,RAMBAR1
|
||||
#else
|
||||
move.l #__RAMBAR0 + 0x7,d0
|
||||
movec d0,RAMBAR
|
||||
#endif
|
||||
|
||||
// set stack pointer to end of SRAM
|
||||
lea __SUP_SP,a7
|
||||
move.l #0,(sp)
|
||||
|
||||
// Initialize the processor caches.
|
||||
// The instruction cache is fully enabled.
|
||||
// The data cache is enabled, but cache-inhibited by default.
|
||||
// Later, the MMU will fully activate the data cache for specific areas.
|
||||
// It is important to enable both caches now, otherwise cpushl would hang.
|
||||
|
||||
move.l #0xa50c8120,d0
|
||||
movec d0,cacr
|
||||
andi.l #0xfefbfeff,d0 // Clear invalidate bits
|
||||
move.l d0,_rt_cacr
|
||||
|
||||
// initialize any hardware specific issues
|
||||
bra _initialize_hardware
|
||||
|
||||
1147
sys/sysinit.c
Normal file
1147
sys/sysinit.c
Normal file
File diff suppressed because it is too large
Load Diff
37
tos/Makefile
Normal file
37
tos/Makefile
Normal file
@@ -0,0 +1,37 @@
|
||||
.PHONY: tos
|
||||
.PHONY: jtagwait
|
||||
.PHONY: bascook
|
||||
.PHONY: vmem_test
|
||||
.PHONY: pci_test
|
||||
.PHONY: pci_mem
|
||||
.PHONY: fpga_test
|
||||
tos: jtagwait bascook vmem_test pci_test pci_mem fpga_test
|
||||
|
||||
jtagwait:
|
||||
@$(MAKE) -s -C $@
|
||||
|
||||
bascook:
|
||||
@$(MAKE) -s -C $@
|
||||
|
||||
vmem_test:
|
||||
@$(MAKE) -s -C $@
|
||||
|
||||
pci_test:
|
||||
@$(MAKE) -s -C $@
|
||||
|
||||
pci_mem:
|
||||
@$(MAKE) -s -C $@
|
||||
|
||||
fpga_test:
|
||||
@$(MAKE) -s -C $@
|
||||
|
||||
.PHONY: clean
|
||||
clean:
|
||||
@(cd jtagwait; $(MAKE) -s clean)
|
||||
@(cd bascook; $(MAKE) -s clean)
|
||||
@(cd vmem_test; $(MAKE) -s clean)
|
||||
@(cd pci_test; $(MAKE) -s clean)
|
||||
@(cd pci_mem; $(MAKE) -s clean)
|
||||
@(cd fpga_test; $(MAKE) -s clean)
|
||||
|
||||
|
||||
101
tos/bascook/Makefile
Executable file
101
tos/bascook/Makefile
Executable file
@@ -0,0 +1,101 @@
|
||||
CROSS=Y
|
||||
|
||||
CROSSBINDIR_IS_Y=m68k-atari-mint-
|
||||
CROSSBINDIR_IS_N=
|
||||
|
||||
CROSSBINDIR=$(CROSSBINDIR_IS_$(CROSS))
|
||||
|
||||
UNAME := $(shell uname)
|
||||
ifeq ($(CROSS), Y)
|
||||
ifeq ($(UNAME),Linux)
|
||||
PREFIX=m68k-atari-mint
|
||||
HATARI=hatari
|
||||
else
|
||||
PREFIX=m68k-atari-mint
|
||||
HATARI=/usr/local/bin/hatari
|
||||
endif
|
||||
else
|
||||
PREFIX=/usr
|
||||
endif
|
||||
|
||||
DEPEND=depend
|
||||
TOPDIR= ../..
|
||||
|
||||
BAS_INCLUDE=-I$(TOPDIR)/../BaS_gcc/include
|
||||
|
||||
LIBCMINI=$(TOPDIR)/../libcmini/libcmini
|
||||
|
||||
INCLUDE=-I$(LIBCMINI)/include $(BAS_INCLUDE) -nostdlib
|
||||
LIBS=-lcmini -nostdlib -lgcc
|
||||
CC=$(PREFIX)/bin/gcc
|
||||
|
||||
CC=$(CROSSBINDIR)gcc
|
||||
STRIP=$(CROSSBINDIR)strip
|
||||
STACK=$(CROSSBINDIR)stack
|
||||
|
||||
APP=bascook.prg
|
||||
TEST_APP=$(APP)
|
||||
|
||||
CFLAGS=\
|
||||
-Os\
|
||||
-g\
|
||||
-Wl,-Map,mapfile\
|
||||
-Wall
|
||||
|
||||
SRCDIR=sources
|
||||
|
||||
CSRCS=\
|
||||
$(SRCDIR)/bascook.c
|
||||
ASRCS=
|
||||
|
||||
COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS)))
|
||||
AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS)))
|
||||
OBJS=$(COBJS) $(AOBJS)
|
||||
|
||||
TRGTDIRS=.
|
||||
OBJDIRS=$(patsubst %,%/objs,$(TRGTDIRS))
|
||||
|
||||
#
|
||||
# multilib flags. These must match m68k-atari-mint-gcc -print-multi-lib output
|
||||
#
|
||||
$(APP):CFLAGS += -mcpu=5475
|
||||
|
||||
all: $(TEST_APP)
|
||||
|
||||
#
|
||||
# generate pattern rules for multilib object files.
|
||||
#
|
||||
define CC_TEMPLATE
|
||||
$(1)/objs/%.o:$(SRCDIR)/%.c
|
||||
@echo CC $$<
|
||||
@$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
|
||||
|
||||
$(1)/objs/%.o:$(SRCDIR)/%.S
|
||||
@echo CC $$<
|
||||
@$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
|
||||
|
||||
$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
|
||||
$(1)/$(APP): $$($(1)_OBJS)
|
||||
@echo CC $$<
|
||||
@$(CC) $$(CFLAGS) -o $$@ $(LIBCMINI)/m5475/startup.o $$($(1)_OBJS) -L$(LIBCMINI)/m5475 $(LIBS)
|
||||
@$(STRIP) $$@
|
||||
endef
|
||||
$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
|
||||
|
||||
$(DEPEND): $(ASRCS) $(CSRCS)
|
||||
@-rm -f $(DEPEND)
|
||||
@for d in $(TRGTDIRS);\
|
||||
do $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e "s#^\(.*\).o:#$$d/objs/\1.o:#" >> $(DEPEND); \
|
||||
done
|
||||
|
||||
|
||||
clean:
|
||||
@rm -f $(patsubst %,%/objs/*.o,$(TRGTDIRS)) $(patsubst %,%/$(APP),$(TRGTDIRS))
|
||||
@rm -f $(DEPEND) mapfile
|
||||
|
||||
.PHONY: printvars
|
||||
printvars:
|
||||
@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
|
||||
ifneq (clean,$(MAKECMDGOALS))
|
||||
-include $(DEPEND)
|
||||
endif
|
||||
175
tos/bascook/sources/bascook.c
Normal file
175
tos/bascook/sources/bascook.c
Normal file
@@ -0,0 +1,175 @@
|
||||
#include <stdio.h>
|
||||
#include <mint/osbind.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "driver_vec.h"
|
||||
|
||||
struct driver_table *get_bas_drivers(void)
|
||||
{
|
||||
struct driver_table *ret = NULL;
|
||||
|
||||
__asm__ __volatile__(
|
||||
" bra.s do_trap \n\t"
|
||||
" .dc.l 0x5f424153 \n\t" // '_BAS'
|
||||
"do_trap: trap #0 \n\t"
|
||||
" move.l d0,%[ret] \n\t"
|
||||
: [ret] "=m" (ret) /* output */
|
||||
: /* no inputs */
|
||||
: /* clobbered */
|
||||
);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* temporarily replace the trap 0 handler with this so we can avoid
|
||||
* getting caught by BaS versions that don't understand the driver interface
|
||||
* exposure call.
|
||||
* If we get here, we have a BaS version that doesn't support the trap 0 interface
|
||||
*/
|
||||
static void __attribute__((interrupt)) trap0_catcher(void)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
" clr.l d0 \n\t" // return 0 to indicate not supported
|
||||
:
|
||||
:
|
||||
:
|
||||
);
|
||||
}
|
||||
|
||||
static uint32_t cookieptr(void)
|
||||
{
|
||||
return * (uint32_t *) 0x5a0L;
|
||||
}
|
||||
|
||||
void setcookie(uint32_t cookie, uint32_t value)
|
||||
{
|
||||
uint32_t *cookiejar = (uint32_t *) Supexec(cookieptr);
|
||||
int num_slots;
|
||||
int max_slots;
|
||||
|
||||
num_slots = max_slots = 0;
|
||||
do
|
||||
{
|
||||
if (cookiejar[0] == cookie)
|
||||
{
|
||||
cookiejar[1] = value;
|
||||
return;
|
||||
}
|
||||
cookiejar = &(cookiejar[2]);
|
||||
num_slots++;
|
||||
} while (cookiejar[-2]);
|
||||
|
||||
/*
|
||||
* Here we are at the end of the list and did not find our cookie.
|
||||
* Let's check if there is any space left and append our value to the
|
||||
* list if so. If not, we are lost (extending the cookie jar does only
|
||||
* work from TSRs)
|
||||
*/
|
||||
if (cookiejar[-1])
|
||||
{
|
||||
max_slots = cookiejar[-1];
|
||||
}
|
||||
|
||||
if (max_slots > num_slots)
|
||||
{
|
||||
/* relief, there is space left, extend the list */
|
||||
cookiejar[0] = cookiejar[-2];
|
||||
cookiejar[1] = cookiejar[-1];
|
||||
/* add the new element */
|
||||
cookiejar[-2] = cookie;
|
||||
cookiejar[-1] = value;
|
||||
}
|
||||
else
|
||||
printf("cannot set cookie, cookie jar is full!\r\n");
|
||||
}
|
||||
|
||||
#define COOKIE_DMAC 0x444d4143L /* FireTOS DMA API cookie ("DMAC") */
|
||||
#define COOKIE_BAS_ 0x4241535fL /* BAS_ cookie (points to driver table struct */
|
||||
|
||||
static char *dt_to_str(enum driver_type dt)
|
||||
{
|
||||
switch (dt)
|
||||
{
|
||||
case BLOCKDEV_DRIVER: return "generic block device driver";
|
||||
case CHARDEV_DRIVER: return "generic character device driver";
|
||||
case VIDEO_DRIVER: return "video/framebuffer driver";
|
||||
case XHDI_DRIVER: return "XHDI compatible hard disk driver";
|
||||
case MCD_DRIVER: return "multichannel DMA driver";
|
||||
case PCI_DRIVER: return "PCI interface driver";
|
||||
case MMU_DRIVER: return "MMU lock/unlock pages driver";
|
||||
case PCI_NATIVE_DRIVER: return "PCI interface native driver";
|
||||
default: return "unknown driver type";
|
||||
}
|
||||
}
|
||||
|
||||
static void set_driver_cookies(void)
|
||||
{
|
||||
struct driver_table *dt;
|
||||
void *old_vector;
|
||||
char **sysbase = (char **) 0x4f2;
|
||||
uint32_t sig;
|
||||
|
||||
sig = * (long *)((*sysbase) + 0x2c);
|
||||
|
||||
/*
|
||||
* first check if we are on EmuTOS, FireTOS want's to do everything itself
|
||||
*/
|
||||
if (sig == 0x45544f53)
|
||||
{
|
||||
old_vector = Setexc(0x20, trap0_catcher); /* set our own temporarily */
|
||||
dt = get_bas_drivers(); /* trap #0 */
|
||||
(void) Setexc(0x20, old_vector); /* restore original vector */
|
||||
|
||||
if (dt)
|
||||
{
|
||||
struct generic_interface *ifc = &dt->interfaces[0];
|
||||
|
||||
printf("BaS driver table found at %p, BaS version is %d.%d\r\n", dt,
|
||||
dt->bas_version, dt->bas_revision);
|
||||
|
||||
while (ifc->type != END_OF_DRIVERS)
|
||||
{
|
||||
printf("driver \"%s (%s)\" found,\r\n"
|
||||
"interface type is %d (%s),\r\n"
|
||||
"version %d.%d\r\n\r\n",
|
||||
ifc->name, ifc->description, ifc->type, dt_to_str(ifc->type),
|
||||
ifc->version, ifc->revision);
|
||||
if (ifc->type == MCD_DRIVER)
|
||||
{
|
||||
setcookie(COOKIE_DMAC, (uint32_t) ifc->interface.dma);
|
||||
printf("\r\nDMAC cookie set to %p\r\n", ifc->interface.dma);
|
||||
}
|
||||
ifc++;
|
||||
}
|
||||
|
||||
/*
|
||||
* set cookie to be able to find the driver table later on
|
||||
*/
|
||||
setcookie(COOKIE_BAS_, (uint32_t) dt);
|
||||
printf("BAS_ cookie set to %p\r\n", dt);
|
||||
}
|
||||
else
|
||||
{
|
||||
printf("driver table not found.\r\n");
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
printf("not running on EmuTOS,\r\n(signature 0x%04x instead of 0x%04x\r\n",
|
||||
(uint32_t) sig, 0x45544f53);
|
||||
}
|
||||
}
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
(void) Cconws("retrieve BaS driver interface\r\n");
|
||||
|
||||
Supexec(set_driver_cookies);
|
||||
|
||||
while (Cconis()) Cconin(); /* eat keys */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
109
tos/fpga_test/Makefile
Executable file
109
tos/fpga_test/Makefile
Executable file
@@ -0,0 +1,109 @@
|
||||
CROSS=Y
|
||||
|
||||
CROSSBINDIR_IS_Y=m68k-atari-mint-
|
||||
CROSSBINDIR_IS_N=
|
||||
|
||||
CROSSBINDIR=$(CROSSBINDIR_IS_$(CROSS))
|
||||
|
||||
UNAME := $(shell uname)
|
||||
ifeq ($(CROSS), Y)
|
||||
ifeq ($(UNAME),Linux)
|
||||
PREFIX=m68k-atari-mint
|
||||
HATARI=hatari
|
||||
else
|
||||
PREFIX=m68k-atari-mint
|
||||
HATARI=/usr/local/bin/hatari
|
||||
endif
|
||||
else
|
||||
PREFIX=/usr
|
||||
endif
|
||||
|
||||
DEPEND=depend
|
||||
TOPDIR = ../..
|
||||
|
||||
LIBCMINI=$(TOPDIR)/../libcmini/libcmini
|
||||
|
||||
INCLUDE=-I$(LIBCMINI)/include -nostdlib -I$(TOPDIR)/include
|
||||
LIBS=-lcmini -nostdlib -lgcc -L$(TOPDIR)/firebee -lbas
|
||||
CC=$(PREFIX)/bin/gcc
|
||||
|
||||
CC=$(CROSSBINDIR)gcc
|
||||
STRIP=$(CROSSBINDIR)strip
|
||||
STACK=$(CROSSBINDIR)stack
|
||||
|
||||
APP=fpga_test.prg
|
||||
TEST_APP=$(APP)
|
||||
|
||||
CFLAGS=\
|
||||
-O0\
|
||||
-g\
|
||||
-Wl,-Map,mapfile\
|
||||
-Wl,--defsym -Wl,__MBAR=0xff000000\
|
||||
-Wl,--defsym -Wl,__MMUBAR=0xff040000\
|
||||
-Wl,--defsym -Wl,__FPGA_JTAG_LOADED=0xff101000\
|
||||
-Wl,--defsym -Wl,__FPGA_JTAG_VALID=0xff101004\
|
||||
-Wl,--defsym -Wl,__VRAM=0x60000000\
|
||||
-Wall
|
||||
|
||||
SRCDIR=sources
|
||||
INCDIR=include
|
||||
INCLUDE+=-I$(INCDIR)
|
||||
|
||||
CSRCS=\
|
||||
$(SRCDIR)/fpga_test.c \
|
||||
$(SRCDIR)/ser_printf.c
|
||||
|
||||
ASRCS=
|
||||
|
||||
COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS)))
|
||||
AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS)))
|
||||
OBJS=$(COBJS) $(AOBJS)
|
||||
|
||||
TRGTDIRS=./m5475 ./m5475/mshort
|
||||
OBJDIRS=$(patsubst %,%/objs,$(TRGTDIRS))
|
||||
|
||||
#
|
||||
# multilib flags. These must match m68k-atari-mint-gcc -print-multi-lib output
|
||||
#
|
||||
m5475/$(APP):CFLAGS += -mcpu=5475
|
||||
m5475/mshort/$(APP): CFLAGS += -mcpu=5475 -mshort
|
||||
|
||||
all:$(patsubst %,%/$(APP),$(TRGTDIRS))
|
||||
#
|
||||
# generate pattern rules for multilib object files.
|
||||
#
|
||||
define CC_TEMPLATE
|
||||
$(1)/objs/%.o:$(SRCDIR)/%.c
|
||||
@echo CC $$<
|
||||
@$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
|
||||
|
||||
$(1)/objs/%.o:$(SRCDIR)/%.S
|
||||
@echo CC $$<
|
||||
@$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
|
||||
|
||||
$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
|
||||
$(1)/$(APP): $$($(1)_OBJS)
|
||||
@echo CC $$@
|
||||
@$(CC) $$(CFLAGS) -o $$@ $(LIBCMINI)/$(1)/startup.o $$($(1)_OBJS) -L$(LIBCMINI)/$(1) $(LIBS)
|
||||
#$(STRIP) $$@
|
||||
endef
|
||||
$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
|
||||
|
||||
$(DEPEND): $(ASRCS) $(CSRCS)
|
||||
@-rm -f $(DEPEND)
|
||||
@for d in $(TRGTDIRS);\
|
||||
do $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e "s#^\(.*\).o:#$$d/objs/\1.o:#" >> $(DEPEND); \
|
||||
done
|
||||
|
||||
|
||||
clean:
|
||||
@rm -f $(patsubst %,%/objs/*.o,$(TRGTDIRS)) $(patsubst %,%/$(APP),$(TRGTDIRS))
|
||||
@rm -f $(DEPEND) mapfile
|
||||
|
||||
.PHONY: printvars
|
||||
printvars:
|
||||
@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
|
||||
|
||||
ifneq (clean,$(MAKECMDGOALS))
|
||||
-include $(DEPEND)
|
||||
endif
|
||||
491
tos/fpga_test/sources/fpga_test.c
Normal file
491
tos/fpga_test/sources/fpga_test.c
Normal file
@@ -0,0 +1,491 @@
|
||||
#include <stdio.h>
|
||||
#include <mint/osbind.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "bas_printf.h"
|
||||
#include "MCF5475.h"
|
||||
#include "driver_vec.h"
|
||||
|
||||
#define FPGA_CONFIG (1 << 2)
|
||||
#define FPGA_CONF_DONE (1 << 5)
|
||||
|
||||
#define SRAM1_START 0xff101000
|
||||
#define SRAM1_END SRAM1_START + 0x1000
|
||||
#define SAFE_STACK SRAM1_END - 4
|
||||
|
||||
#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory")
|
||||
|
||||
#define SYSCLK 132000
|
||||
|
||||
long bas_start = 0xe0000000;
|
||||
|
||||
volatile uint16_t *FB_CS1 = (volatile uint16_t *) 0xfff00000; /* "classic" ATARI I/O registers */
|
||||
volatile uint32_t *FB_CS2 = (volatile uint32_t *) 0xf0000000; /* FireBee 32 bit I/O registers */
|
||||
volatile uint16_t *FB_CS3 = (volatile uint16_t *) 0xf8000000; /* FireBee SRAM */
|
||||
volatile uint32_t *FB_CS4 = (uint32_t *) 0x40000000; /* FireBee SD RAM */
|
||||
|
||||
const long sdram_size = 128 * 1024L * 1024L;
|
||||
|
||||
static void init_ddr_ram(void)
|
||||
{
|
||||
xprintf("init video RAM: ");
|
||||
|
||||
FB_CS2[0x100] = 0xb; /* set cke = 1, cs=1, config = 1 */
|
||||
NOP();
|
||||
|
||||
FB_CS4[0] = 0x00050400; /* IPALL */
|
||||
NOP();
|
||||
|
||||
FB_CS4[0] = 0x00072000; /* load EMR pll on */
|
||||
NOP();
|
||||
|
||||
FB_CS4[0] = 0x00070122; /* load MR: reset pll, cl=2, burst=4lw */
|
||||
NOP();
|
||||
|
||||
FB_CS4[0] = 0x00050400; /* IPALL */
|
||||
NOP();
|
||||
|
||||
FB_CS4[0] = 0x00060000; /* auto refresh */
|
||||
NOP();
|
||||
|
||||
FB_CS4[0] = 0x00060000; /* auto refresh */
|
||||
NOP();
|
||||
|
||||
/* FIXME: what's this? */
|
||||
FB_CS4[0] = 0000070022; /* load MR dll on */
|
||||
NOP();
|
||||
|
||||
FB_CS2[0x100] = 0x01070082; /* fifo on, refresh on, ddrcs und cke on, video dac on, Falcon shift mode on */
|
||||
|
||||
xprintf("finished\r\n");
|
||||
}
|
||||
|
||||
|
||||
bool verify_ddr_ram(uint32_t value)
|
||||
{
|
||||
volatile uint32_t *lp;
|
||||
volatile uint16_t *wp;
|
||||
uint32_t rl;
|
||||
uint16_t rw;
|
||||
|
||||
lp = FB_CS4;
|
||||
|
||||
/*
|
||||
* write/read longs
|
||||
*/
|
||||
lp = FB_CS4;
|
||||
do
|
||||
{
|
||||
*lp = value;
|
||||
xprintf("W: 0x%08x R: 0x%08x\r", value, rl = *lp);
|
||||
|
||||
if (rl != value)
|
||||
{
|
||||
xprintf("\nvalidation error at %p: written = 0x%08x, read = 0x%08x\r\n", lp, value, rl);
|
||||
|
||||
return false;
|
||||
}
|
||||
} while (lp++ <= FB_CS4 + sdram_size - 1);
|
||||
|
||||
wp = (uint16_t *) FB_CS4;
|
||||
|
||||
/*
|
||||
* write/read words
|
||||
*/
|
||||
wp = (uint16_t *) FB_CS4;
|
||||
do
|
||||
{
|
||||
*wp = (uint16_t) value;
|
||||
|
||||
xprintf("W: 0x%04x R: 0x%04x\r", value, rw = *wp);
|
||||
|
||||
if (rw != value)
|
||||
{
|
||||
xprintf("\nvalidation error at %p: written = 0x%04x, read = 0x%04x\r\n", wp, value, rw);
|
||||
|
||||
return false;
|
||||
}
|
||||
} while (wp++ <= (uint16_t *) FB_CS4 + sdram_size - 1);
|
||||
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool verify_longaddr(volatile uint32_t * const addr, uint32_t value)
|
||||
{
|
||||
*addr = value;
|
||||
|
||||
xprintf("W: 0x%08x R: 0x%08x\r", value, *addr);
|
||||
|
||||
if (value != *addr)
|
||||
{
|
||||
xprintf("validation error at %p: written = 0x%08x, read = 0x%08x\r\n", addr, value, *addr);
|
||||
|
||||
xprintf("\r\n");
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool verify_long(volatile uint32_t * const addr, uint32_t low_value, uint32_t high_value)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = low_value; i <= high_value; i++)
|
||||
if (verify_longaddr(addr, i) == false)
|
||||
{
|
||||
xprintf("verify of %p failed: 0x%08x written, 0x%08x read\r\n",
|
||||
addr, i, *addr);
|
||||
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
void firebee_io_test(void)
|
||||
{
|
||||
volatile uint32_t *ACP_VCTR = &FB_CS2[0x100]; /* 0xf000400 */
|
||||
volatile uint32_t *CCR = &FB_CS2[0x101]; /* 0xf000401 - FireBee mode border color */
|
||||
volatile uint32_t *ATARI_HH = &FB_CS2[0x104]; /* 0xf000410 */
|
||||
volatile uint32_t *ATARI_VH = &FB_CS2[0x105]; /* 0xf000414 */
|
||||
volatile uint32_t *ATARI_HL = &FB_CS2[0x106]; /* 0xf000418 */
|
||||
volatile uint32_t *ATARI_VL = &FB_CS2[0x107]; /* 0xf00041c */
|
||||
|
||||
volatile uint32_t *VIDEO_PLL_CONFIG = &FB_CS2[0x180]; /* 0xf000600 */
|
||||
volatile uint32_t *VIDEO_PLL_RECONFIG = &FB_CS2[0x200]; /* 0xf000800 */
|
||||
|
||||
xprintf("verify ACP_VCTR register\r\n");
|
||||
verify_long(ACP_VCTR, 0, 0x1ff);
|
||||
|
||||
xprintf("verify CCR register\r\n");
|
||||
verify_long(CCR, 0, 0x1ff);
|
||||
|
||||
xprintf("verify ATARI_HH register\r\n");
|
||||
verify_long(ATARI_HH, 0, 0x1ff);
|
||||
|
||||
xprintf("verify ATARI_VH register\r\n");
|
||||
verify_long(ATARI_VH, 0, 0x1ff);
|
||||
|
||||
xprintf("verify ATARI_HL register\r\n");
|
||||
verify_long(ATARI_HL, 0, 0x1ff);
|
||||
|
||||
xprintf("verify ATARI_VL register\r\n");
|
||||
verify_long(ATARI_VL, 0, 0x1ff);
|
||||
|
||||
xprintf("verify VIDEO_PLL_CONFIG register\r\n");
|
||||
verify_long(VIDEO_PLL_CONFIG, 0, 0x1ff);
|
||||
|
||||
xprintf("verify VIDEO_PLL_RECONFIG register\r\n");
|
||||
verify_long(VIDEO_PLL_RECONFIG, 0, 0x1ff);
|
||||
}
|
||||
|
||||
bool verify_wordaddr(volatile uint16_t * const addr, uint16_t value)
|
||||
{
|
||||
long rvalue;
|
||||
*addr = value;
|
||||
|
||||
if (value != (rvalue = *addr))
|
||||
{
|
||||
xprintf("validation error at %p, wrote 0x%04x, read 0x%04x\r\n", addr, value, rvalue);
|
||||
|
||||
xprintf("\r\n");
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool verify_word(volatile uint16_t * const addr, uint16_t low_value, uint16_t high_value)
|
||||
{
|
||||
uint16_t i;
|
||||
|
||||
for (i = low_value; i <= high_value; i++)
|
||||
if (verify_wordaddr(addr, i) == false)
|
||||
{
|
||||
xprintf("verify of %p failed: 0x%04x written, 0x%04x read\r\n",
|
||||
addr, i, *addr);
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool verify_byteaddr(volatile uint8_t * const addr, uint8_t value)
|
||||
{
|
||||
uint8_t rvalue;
|
||||
*addr = value;
|
||||
|
||||
if (value != (rvalue = *addr))
|
||||
{
|
||||
xprintf("validation error at %p, wrote 0x%02x, read 0x%02x\r\n", addr, value, rvalue);
|
||||
|
||||
xprintf("\r\n");
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool verify_byte(volatile uint8_t * const addr, uint8_t low_value, uint8_t high_value)
|
||||
{
|
||||
int8_t i;
|
||||
|
||||
for (i = low_value; i <= high_value; i++)
|
||||
if (verify_byteaddr(addr, i) == false)
|
||||
{
|
||||
xprintf("verify of %p failed: 0x%02x written, 0x%02x read\r\n",
|
||||
addr, i, *addr);
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void falcon_io_test(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
volatile uint16_t *SYS_CTR = &FB_CS1[0x7c003]; /* 0xffff8006 */
|
||||
|
||||
volatile uint8_t *VIDEO_ADR_HI = ((volatile uint8_t *) &FB_CS1[0x7c100]) + 1; /* 0xffff8201 */
|
||||
volatile uint8_t *VIDEO_ADR_MI = ((volatile uint8_t *) &FB_CS1[0x7c101]) + 1; /* 0xffff8203 */
|
||||
volatile uint8_t *VIDEO_ADR_LO = ((volatile uint8_t *) &FB_CS1[0x7c106]) + 1; /* 0xffff820d */
|
||||
|
||||
volatile uint8_t *VIDEO_CNT_HI = ((volatile uint8_t *) &FB_CS1[0x7c102]) + 1; /* 0xffff8205 */
|
||||
volatile uint8_t *VIDEO_CNT_MI = ((volatile uint8_t *) &FB_CS1[0x7c103]) + 1; /* 0xffff8207 */
|
||||
volatile uint8_t *VIDEO_CNT_LO = ((volatile uint8_t *) &FB_CS1[0x7c104]) + 1; /* 0xffff8209 */
|
||||
|
||||
volatile uint8_t *SYNC_MODE = ((volatile uint8_t *) &FB_CS1[0x7c105]) + 1; /* 0xffff8006 */
|
||||
|
||||
volatile uint16_t *VDL_LOF = &FB_CS1[0x7c107]; /* 0xffff820e */
|
||||
volatile uint16_t *VDL_LWD = &FB_CS1[0x7c108]; /* 0xffff8210 */
|
||||
volatile uint16_t *VDL_HHT = &FB_CS1[0x7c141]; /* 0xffff8282 */
|
||||
volatile uint16_t *VDL_HBB = &FB_CS1[0x7c142]; /* 0xffff8284 */
|
||||
volatile uint16_t *VDL_HBE = &FB_CS1[0x7c143]; /* 0xffff8286 */
|
||||
volatile uint16_t *VDL_HDB = &FB_CS1[0x7c144]; /* 0xffff8288 */
|
||||
volatile uint16_t *VDL_HDE = &FB_CS1[0x7c145]; /* 0xffff828a */
|
||||
volatile uint16_t *VDL_HSS = &FB_CS1[0x7c146]; /* 0xffff828c */
|
||||
|
||||
volatile uint16_t *VDL_VFT = &FB_CS1[0x7c151]; /* 0xffff82a2 */
|
||||
volatile uint16_t *VDL_VBB = &FB_CS1[0x7c152]; /* 0xffff82a4 */
|
||||
volatile uint16_t *VDL_VBE = &FB_CS1[0x7c153]; /* 0xffff82a6 */
|
||||
volatile uint16_t *VDL_VDB = &FB_CS1[0x7c154]; /* 0xffff82a8 */
|
||||
volatile uint16_t *VDL_VDE = &FB_CS1[0x7c155]; /* 0xffff82aa */
|
||||
volatile uint16_t *VDL_VSS = &FB_CS1[0x7c156]; /* 0xffff82ac */
|
||||
volatile uint16_t *VDL_VCT = &FB_CS1[0x7c160]; /* 0xffff82c0 */
|
||||
volatile uint16_t *VDL_VMD = &FB_CS1[0x7c161]; /* 0xffff82c2 */
|
||||
|
||||
/* ST palette registers */
|
||||
volatile uint8_t *st_palette = (volatile uint8_t *) &FB_CS1[0x7c120]; /* 0xffff8240 */
|
||||
|
||||
/* Falcon palette registers */
|
||||
volatile uint8_t *falcon_palette = (volatile uint8_t *) &FB_CS1[0x7cc00]; /* 0xffff9800 */
|
||||
|
||||
xprintf("verify VIDEO_ADR_XX registers\r\n");
|
||||
verify_byte(VIDEO_ADR_HI, 0x00, 0xff);
|
||||
verify_byte(VIDEO_ADR_MI, 0x00, 0xff);
|
||||
verify_byte(VIDEO_ADR_LO, 0x00, 0xff);
|
||||
|
||||
xprintf("verify VIDEO_CNT_XX registers\r\n");
|
||||
verify_byte(VIDEO_CNT_HI, 0x00, 0xff);
|
||||
verify_byte(VIDEO_CNT_MI, 0x00, 0xff);
|
||||
verify_byte(VIDEO_CNT_LO, 0x00, 0xff);
|
||||
|
||||
xprintf("verify SYNC_MODE register\r\n");
|
||||
verify_byte(SYNC_MODE, 0x00, 0xff);
|
||||
|
||||
xprintf("verify SYS_CTR register\r\n");
|
||||
verify_word(SYS_CTR, 0, 0x1ff);
|
||||
|
||||
for (i = 0; i < 16 * 2; i += 2)
|
||||
{
|
||||
xprintf("verify ST palette register %d\r\n", i / 2);
|
||||
verify_byte(&st_palette[i], i / 2, i / 2);
|
||||
verify_byte(&st_palette[i], i / 2, i / 2); /* do two consecutive tests here because of RAM latency */
|
||||
}
|
||||
|
||||
for (i = 0; i < 255 * 2; i += 2)
|
||||
{
|
||||
xprintf("verify Falcon palette register %d\r\n", i / 2);
|
||||
verify_byte(&falcon_palette[i], i / 2, i / 2);
|
||||
verify_byte(&falcon_palette[i], i / 2, i / 2); /* do two consecutive tests here because of FPGA RAM latency */
|
||||
}
|
||||
|
||||
xprintf("verify LOF register\r\n");
|
||||
verify_word(VDL_LOF, 0, 0x1ff);
|
||||
|
||||
xprintf("verify LWD register \r\n");
|
||||
verify_word(VDL_LWD, 0, 0x1ff);
|
||||
|
||||
xprintf("verify HHT register\r\n");
|
||||
verify_word(VDL_HHT, 0, 0x1ff);
|
||||
|
||||
xprintf("verify HBB register\r\n");
|
||||
verify_word(VDL_HBB, 0, 0x1ff);
|
||||
|
||||
xprintf("verify HBE register\r\n");
|
||||
verify_word(VDL_HBE, 0, 0x1ff);
|
||||
|
||||
xprintf("verify HDB register\r\n");
|
||||
verify_word(VDL_HDB, 0, 0x1ff);
|
||||
|
||||
xprintf("verify HDE register\r\n");
|
||||
verify_word(VDL_HDE, 0, 0x1ff);
|
||||
|
||||
xprintf("verify HSS register\r\n");
|
||||
verify_word(VDL_HSS, 0, 0x1ff);
|
||||
|
||||
|
||||
xprintf("verify VFT register\r\n");
|
||||
verify_word(VDL_VFT, 0, 0x1ff);
|
||||
|
||||
xprintf("verify VBB register\r\n");
|
||||
verify_word(VDL_VBB, 0, 0x1ff);
|
||||
|
||||
xprintf("verify VBE register\r\n");
|
||||
verify_word(VDL_VBE, 0, 0x1ff);
|
||||
|
||||
xprintf("verify VDB register\r\n");
|
||||
verify_word(VDL_VDB, 0, 0x1ff);
|
||||
|
||||
xprintf("verify VDE register\r\n");
|
||||
verify_word(VDL_VDE, 0, 0x1ff);
|
||||
|
||||
xprintf("verify VSS register\r\n");
|
||||
verify_word(VDL_VSS, 0, 0x1ff);
|
||||
|
||||
xprintf("verify VCT register\r\n");
|
||||
verify_word(VDL_VCT, 0, 0x1ff);
|
||||
|
||||
xprintf("verify VMD register\r\n");
|
||||
verify_word(VDL_VMD, 0, 0x1ff);
|
||||
}
|
||||
|
||||
void do_tests(void)
|
||||
{
|
||||
xprintf("start tests:\r\n");
|
||||
|
||||
xprintf("Falcon I/O test\r\n");
|
||||
falcon_io_test();
|
||||
|
||||
xprintf("FireBee I/O test\r\n");
|
||||
firebee_io_test();
|
||||
|
||||
init_ddr_ram();
|
||||
verify_ddr_ram(0xaaaaaaaa);
|
||||
verify_ddr_ram(0x55555555);
|
||||
}
|
||||
|
||||
|
||||
void wait_for_jtag(void)
|
||||
{
|
||||
long i;
|
||||
|
||||
/* set supervisor stack to end of SRAM1 */
|
||||
__asm__ __volatile__ (
|
||||
" move #0x2700,sr\n\t" /* disable interrupts */
|
||||
" move.l %[stack],d0\n\t" /* 4KB on-chip core SRAM1 */
|
||||
" move.l d0,sp\n\t" /* set stack pointer */
|
||||
:
|
||||
: [stack] "i" (SAFE_STACK)
|
||||
: "d0", "cc" /* clobber */
|
||||
);
|
||||
|
||||
MCF_EPORT_EPIER = 0x0; /* disable EPORT interrupts */
|
||||
MCF_INTC_IMRL = 0xffffffff;
|
||||
MCF_INTC_IMRH = 0xffffffff; /* disable interrupt controller */
|
||||
|
||||
MCF_MMU_MMUCR &= ~MCF_MMU_MMUCR_EN; /* disable MMU */
|
||||
|
||||
xprintf("relocated supervisor stack, disabled interrupts and disabled MMU\r\n");
|
||||
|
||||
/*
|
||||
* configure FEC1L port directions to enable external JTAG configuration download to FPGA
|
||||
*/
|
||||
MCF_GPIO_PDDR_FEC1L = 0 |
|
||||
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4; /* bit 4 = LED => output */
|
||||
/* all other bits = input */
|
||||
|
||||
/*
|
||||
* configure DSPI_CS3 as GPIO input to avoid the MCU driving against the FPGA blink
|
||||
*/
|
||||
MCF_PAD_PAR_DSPI &= ~MCF_PAD_PAR_DSPI_PAR_CS3(MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3);
|
||||
/*
|
||||
* now that GPIO ports have been switched to input, we can poll for FPGA config
|
||||
* started from the JTAG interface (CONF_DONE goes low) and finish (CONF_DONE goes high)
|
||||
*/
|
||||
xprintf("waiting for JTAG configuration start\r\n");
|
||||
while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load started */
|
||||
|
||||
xprintf("waiting for JTAG configuration to finish\r\n");
|
||||
while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load finished */
|
||||
|
||||
xprintf("JTAG configuration finished.\r\n");
|
||||
|
||||
/* wait */
|
||||
xprintf("wait a little to let things settle...\r\n");
|
||||
for (i = 0; i < 100000L; i++);
|
||||
|
||||
xprintf("disable caches\r\n");
|
||||
__asm__ __volatile(
|
||||
"move.l #0x01000000,d0 \r\n"
|
||||
"movec d0,CACR \r\n"
|
||||
: /* no output */
|
||||
: /* no input */
|
||||
: "d0", "memory");
|
||||
|
||||
/* begin of tests */
|
||||
|
||||
do_tests();
|
||||
|
||||
xprintf("wait a little to let things settle...\r\n");
|
||||
for (i = 0; i < 100000L; i++);
|
||||
|
||||
xprintf("INFO: endless loop now. Press reset to reboot\r\n");
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
printf("FPGA JTAG configuration support\r\n");
|
||||
printf("test FPGA DDR RAM controller\r\n");
|
||||
printf("\xbd 2014 M. Fr\x94schle\r\n");
|
||||
|
||||
printf("You may now savely load a new FPGA configuration through the JTAG interface\r\n"
|
||||
"and your FireBee will reboot once finished using that new configuration.\r\n");
|
||||
if (argc == 2)
|
||||
{
|
||||
/*
|
||||
* we got an argument. This is supposed to be the address that we need to jump to after JTAG
|
||||
* configuration has been finished. Meant to support BaS in RAM testing
|
||||
*/
|
||||
char *addr_str = argv[1];
|
||||
char *addr = NULL;
|
||||
char *end = NULL;
|
||||
|
||||
addr = (char *) strtol(addr_str, &end, 16);
|
||||
if (addr != NULL && addr <= (char *) 0xe0000000 && addr >= (char *) 0x10000000)
|
||||
{
|
||||
/*
|
||||
* seems to be a valid address
|
||||
*/
|
||||
bas_start = (long) addr;
|
||||
|
||||
printf("BaS start address set to %p\r\n", (void *) bas_start);
|
||||
}
|
||||
else
|
||||
{
|
||||
printf("\r\nNote: BaS start address %p not valid. Stick to %p.\r\n", addr, (void *) bas_start);
|
||||
}
|
||||
}
|
||||
Supexec(wait_for_jtag);
|
||||
|
||||
return 0; /* just to make the compiler happy, we will never return */
|
||||
}
|
||||
|
||||
480
tos/fpga_test/sources/ser_printf.c
Executable file
480
tos/fpga_test/sources/ser_printf.c
Executable file
@@ -0,0 +1,480 @@
|
||||
|
||||
/*
|
||||
* tc.printf.c: A public-domain, minimal printf/sprintf routine that prints
|
||||
* through the putchar() routine. Feel free to use for
|
||||
* anything... -- 7/17/87 Paul Placeway
|
||||
*/
|
||||
/*-
|
||||
* Copyright (c) 1980, 1991 The Regents of the University of California.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the University nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdarg.h>
|
||||
#include <stdbool.h>
|
||||
#include "MCF5475.h"
|
||||
#include "bas_printf.h"
|
||||
#include "bas_string.h"
|
||||
|
||||
/*
|
||||
* Lexical definitions.
|
||||
*
|
||||
* All lexical space is allocated dynamically.
|
||||
* The eighth/sixteenth bit of characters is used to prevent recognition,
|
||||
* and eventually stripped.
|
||||
*/
|
||||
#define META 0200
|
||||
#define ASCII 0177
|
||||
#define QUOTE ((char) 0200) /* Eighth char bit used for 'ing */
|
||||
#define TRIM 0177 /* Mask to strip quote bit */
|
||||
#define UNDER 0000000 /* No extra bits to do both */
|
||||
#define BOLD 0000000 /* Bold flag */
|
||||
#define STANDOUT META /* Standout flag */
|
||||
#define LITERAL 0000000 /* Literal character flag */
|
||||
#define ATTRIBUTES 0200 /* The bits used for attributes */
|
||||
#define CHAR 0000177 /* Mask to mask out the character */
|
||||
|
||||
#define INF 32766 /* should be bigger than any field to print */
|
||||
|
||||
static char snil[] = "(nil)";
|
||||
|
||||
bool conoutstat(void)
|
||||
{
|
||||
bool stat;
|
||||
|
||||
stat = MCF_PSC0_PSCSR & MCF_PSC_PSCSR_TXRDY; /* TX FIFO can take data */
|
||||
|
||||
return stat;
|
||||
}
|
||||
|
||||
bool coninstat(void)
|
||||
{
|
||||
bool stat;
|
||||
|
||||
stat = MCF_PSC0_PSCSR & MCF_PSC_PSCSR_RXRDY; /* RX FIFO has data available */
|
||||
|
||||
return stat;
|
||||
}
|
||||
|
||||
void xputchar(int c)
|
||||
{
|
||||
do { ; } while (!conoutstat());
|
||||
MCF_PSC_PSCRB_8BIT(0) = (char) c;
|
||||
}
|
||||
|
||||
char xgetchar(void)
|
||||
{
|
||||
char c;
|
||||
|
||||
do { ; } while (!coninstat());
|
||||
c = MCF_PSC_PSCTB_8BIT(0);
|
||||
|
||||
return c;
|
||||
}
|
||||
|
||||
static void doprnt(void (*addchar)(int), const char *sfmt, va_list ap)
|
||||
{
|
||||
char buf[128];
|
||||
char *bp;
|
||||
const char *f;
|
||||
float flt;
|
||||
long l;
|
||||
unsigned long u;
|
||||
int i;
|
||||
int fmt;
|
||||
unsigned char pad = ' ';
|
||||
int flush_left = 0;
|
||||
int f_width = 0;
|
||||
int prec = INF;
|
||||
int hash = 0;
|
||||
int do_long = 0;
|
||||
int sign = 0;
|
||||
int attributes = 0;
|
||||
|
||||
f = sfmt;
|
||||
for (; *f; f++)
|
||||
{
|
||||
if (*f != '%')
|
||||
{
|
||||
/* then just out the char */
|
||||
(*addchar)((int) (((unsigned char) *f) | attributes));
|
||||
}
|
||||
else
|
||||
{
|
||||
f++; /* skip the % */
|
||||
|
||||
if (*f == '-')
|
||||
{ /* minus: flush left */
|
||||
flush_left = 1;
|
||||
f++;
|
||||
}
|
||||
|
||||
if (*f == '0' || *f == '.')
|
||||
{
|
||||
/* padding with 0 rather than blank */
|
||||
pad = '0';
|
||||
f++;
|
||||
}
|
||||
if (*f == '*')
|
||||
{
|
||||
/* field width */
|
||||
f_width = va_arg(ap, int);
|
||||
f++;
|
||||
}
|
||||
else if (isdigit((unsigned char)*f))
|
||||
{
|
||||
f_width = atoi(f);
|
||||
while (isdigit((unsigned char)*f))
|
||||
f++; /* skip the digits */
|
||||
}
|
||||
|
||||
if (*f == '.')
|
||||
{ /* precision */
|
||||
f++;
|
||||
if (*f == '*')
|
||||
{
|
||||
prec = va_arg(ap, int);
|
||||
f++;
|
||||
}
|
||||
else if (isdigit((unsigned char)*f))
|
||||
{
|
||||
prec = atoi(f);
|
||||
while (isdigit((unsigned char)*f))
|
||||
f++; /* skip the digits */
|
||||
}
|
||||
}
|
||||
|
||||
if (*f == '#')
|
||||
{ /* alternate form */
|
||||
hash = 1;
|
||||
f++;
|
||||
}
|
||||
|
||||
if (*f == 'l')
|
||||
{ /* long format */
|
||||
do_long++;
|
||||
f++;
|
||||
if (*f == 'l')
|
||||
{
|
||||
do_long++;
|
||||
f++;
|
||||
}
|
||||
}
|
||||
|
||||
fmt = (unsigned char) *f;
|
||||
if (fmt != 'S' && fmt != 'Q' && isupper(fmt))
|
||||
{
|
||||
do_long = 1;
|
||||
fmt = tolower(fmt);
|
||||
}
|
||||
bp = buf;
|
||||
switch (fmt)
|
||||
{ /* do the format */
|
||||
case 'd':
|
||||
switch (do_long)
|
||||
{
|
||||
case 0:
|
||||
l = (long) (va_arg(ap, int));
|
||||
break;
|
||||
case 1:
|
||||
default:
|
||||
l = va_arg(ap, long);
|
||||
break;
|
||||
}
|
||||
|
||||
if (l < 0)
|
||||
{
|
||||
sign = 1;
|
||||
l = -l;
|
||||
}
|
||||
do
|
||||
{
|
||||
*bp++ = (char) (l % 10) + '0';
|
||||
} while ((l /= 10) > 0);
|
||||
if (sign)
|
||||
*bp++ = '-';
|
||||
f_width = f_width - (int) (bp - buf);
|
||||
if (!flush_left)
|
||||
while (f_width-- > 0)
|
||||
(*addchar)((int) (pad | attributes));
|
||||
for (bp--; bp >= buf; bp--)
|
||||
(*addchar)((int) (((unsigned char) *bp) | attributes));
|
||||
if (flush_left)
|
||||
while (f_width-- > 0)
|
||||
(*addchar)((int) (' ' | attributes));
|
||||
break;
|
||||
|
||||
case 'f':
|
||||
/* this is actually more than stupid, but does work for now */
|
||||
flt = (float) (va_arg(ap, double)); /* beware: va_arg() extends float to double! */
|
||||
if (flt < 0)
|
||||
{
|
||||
sign = 1;
|
||||
flt = -flt;
|
||||
}
|
||||
{
|
||||
int quotient, remainder;
|
||||
|
||||
quotient = (int) flt;
|
||||
remainder = (flt - quotient) * 10E5;
|
||||
|
||||
for (i = 0; i < 6; i++)
|
||||
{
|
||||
*bp++ = (char) (remainder % 10) + '0';
|
||||
remainder /= 10;
|
||||
}
|
||||
*bp++ = '.';
|
||||
do
|
||||
{
|
||||
*bp++ = (char) (quotient % 10) + '0';
|
||||
} while ((quotient /= 10) > 0);
|
||||
if (sign)
|
||||
*bp++ = '-';
|
||||
f_width = f_width - (int) (bp - buf);
|
||||
if (!flush_left)
|
||||
while (f_width-- > 0)
|
||||
(*addchar)((int) (pad | attributes));
|
||||
for (bp--; bp >= buf; bp--)
|
||||
(*addchar)((int) (((unsigned char) *bp) | attributes));
|
||||
if (flush_left)
|
||||
while (f_width-- > 0)
|
||||
(*addchar)((int) (' ' | attributes));
|
||||
}
|
||||
break;
|
||||
|
||||
case 'p':
|
||||
do_long = 1;
|
||||
hash = 1;
|
||||
fmt = 'x';
|
||||
/* no break */
|
||||
case 'o':
|
||||
case 'x':
|
||||
case 'u':
|
||||
switch (do_long)
|
||||
{
|
||||
case 0:
|
||||
u = (unsigned long) (va_arg(ap, unsigned int));
|
||||
break;
|
||||
case 1:
|
||||
default:
|
||||
u = va_arg(ap, unsigned long);
|
||||
break;
|
||||
}
|
||||
if (fmt == 'u')
|
||||
{ /* unsigned decimal */
|
||||
do
|
||||
{
|
||||
*bp++ = (char) (u % 10) + '0';
|
||||
} while ((u /= 10) > 0);
|
||||
}
|
||||
else if (fmt == 'o')
|
||||
{ /* octal */
|
||||
do
|
||||
{
|
||||
*bp++ = (char) (u % 8) + '0';
|
||||
} while ((u /= 8) > 0);
|
||||
if (hash)
|
||||
*bp++ = '0';
|
||||
}
|
||||
else if (fmt == 'x')
|
||||
{ /* hex */
|
||||
do
|
||||
{
|
||||
i = (int) (u % 16);
|
||||
if (i < 10)
|
||||
*bp++ = i + '0';
|
||||
else
|
||||
*bp++ = i - 10 + 'a';
|
||||
} while ((u /= 16) > 0);
|
||||
if (hash)
|
||||
{
|
||||
*bp++ = 'x';
|
||||
*bp++ = '0';
|
||||
}
|
||||
}
|
||||
i = f_width - (int) (bp - buf);
|
||||
if (!flush_left)
|
||||
while (i-- > 0)
|
||||
(*addchar)((int) (pad | attributes));
|
||||
for (bp--; bp >= buf; bp--)
|
||||
(*addchar)((int) (((unsigned char) *bp) | attributes));
|
||||
if (flush_left)
|
||||
while (i-- > 0)
|
||||
(*addchar)((int) (' ' | attributes));
|
||||
break;
|
||||
|
||||
case 'c':
|
||||
i = va_arg(ap, int);
|
||||
(*addchar)((int) (i | attributes));
|
||||
break;
|
||||
|
||||
case 'S':
|
||||
case 'Q':
|
||||
case 's':
|
||||
case 'q':
|
||||
bp = va_arg(ap, char *);
|
||||
if (!bp)
|
||||
bp = snil;
|
||||
f_width = f_width - strlen((char *) bp);
|
||||
if (!flush_left)
|
||||
while (f_width-- > 0)
|
||||
(*addchar)((int) (pad | attributes));
|
||||
for (i = 0; *bp && i < prec; i++)
|
||||
{
|
||||
if (fmt == 'q' && (*bp & QUOTE))
|
||||
(*addchar)((int) ('\\' | attributes));
|
||||
(*addchar)(
|
||||
(int) (((unsigned char) *bp & TRIM) | attributes));
|
||||
bp++;
|
||||
}
|
||||
if (flush_left)
|
||||
while (f_width-- > 0)
|
||||
(*addchar)((int) (' ' | attributes));
|
||||
break;
|
||||
|
||||
case 'a':
|
||||
attributes = va_arg(ap, int);
|
||||
break;
|
||||
|
||||
case '%':
|
||||
(*addchar)((int) ('%' | attributes));
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
flush_left = 0, f_width = 0, prec = INF, hash = 0, do_long = 0;
|
||||
sign = 0;
|
||||
pad = ' ';
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static char *xstring, *xestring;
|
||||
|
||||
void xaddchar(int c)
|
||||
{
|
||||
if (xestring == xstring)
|
||||
*xstring = '\0';
|
||||
else
|
||||
*xstring++ = (char) c;
|
||||
}
|
||||
|
||||
int sprintf(char *str, const char *format, ...)
|
||||
{
|
||||
va_list va;
|
||||
va_start(va, format);
|
||||
|
||||
xstring = str;
|
||||
|
||||
doprnt(xaddchar, format, va);
|
||||
va_end(va);
|
||||
*xstring++ = '\0';
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void xsnprintf(char *str, size_t size, const char *fmt, ...)
|
||||
{
|
||||
va_list va;
|
||||
va_start(va, fmt);
|
||||
|
||||
xstring = str;
|
||||
xestring = str + size - 1;
|
||||
doprnt(xaddchar, fmt, va);
|
||||
va_end(va);
|
||||
*xstring++ = '\0';
|
||||
}
|
||||
|
||||
void xprintf(const char *fmt, ...)
|
||||
{
|
||||
va_list va;
|
||||
va_start(va, fmt);
|
||||
doprnt(xputchar, fmt, va);
|
||||
va_end(va);
|
||||
}
|
||||
|
||||
void xvprintf(const char *fmt, va_list va)
|
||||
{
|
||||
doprnt(xputchar, fmt, va);
|
||||
}
|
||||
|
||||
void xvsnprintf(char *str, size_t size, const char *fmt, va_list va)
|
||||
{
|
||||
xstring = str;
|
||||
xestring = str + size - 1;
|
||||
doprnt(xaddchar, fmt, va);
|
||||
*xstring++ = '\0';
|
||||
}
|
||||
|
||||
|
||||
void display_progress()
|
||||
{
|
||||
static int _progress_index;
|
||||
char progress_char[] = "|/-\\";
|
||||
|
||||
xputchar(progress_char[_progress_index++ % strlen(progress_char)]);
|
||||
xputchar('\r');
|
||||
}
|
||||
|
||||
void hexdump(uint8_t buffer[], int size)
|
||||
{
|
||||
int i;
|
||||
int line = 0;
|
||||
volatile uint8_t *bp = buffer;
|
||||
|
||||
while (bp < buffer + size) {
|
||||
volatile uint8_t *lbp = bp;
|
||||
|
||||
xprintf("%08x ", line);
|
||||
|
||||
for (i = 0; i < 16; i++) {
|
||||
uint8_t c = *lbp++;
|
||||
if (bp + i > buffer + size) {
|
||||
break;
|
||||
}
|
||||
xprintf("%02x ", c);
|
||||
}
|
||||
|
||||
lbp = bp;
|
||||
for (i = 0; i < 16; i++) {
|
||||
volatile int8_t c = *lbp++;
|
||||
|
||||
if (bp + i > buffer + size) {
|
||||
break;
|
||||
}
|
||||
if (c > ' ' && c < '~') {
|
||||
xprintf("%c", c);
|
||||
} else {
|
||||
xprintf(".");
|
||||
}
|
||||
}
|
||||
xprintf("\r\n");
|
||||
|
||||
bp += 16;
|
||||
line += 16;
|
||||
}
|
||||
}
|
||||
1
tos/fpga_test/vmem_test.config
Normal file
1
tos/fpga_test/vmem_test.config
Normal file
@@ -0,0 +1 @@
|
||||
// ADD PREDEFINED MACROS HERE!
|
||||
1
tos/fpga_test/vmem_test.creator
Normal file
1
tos/fpga_test/vmem_test.creator
Normal file
@@ -0,0 +1 @@
|
||||
[General]
|
||||
7
tos/fpga_test/vmem_test.files
Normal file
7
tos/fpga_test/vmem_test.files
Normal file
@@ -0,0 +1,7 @@
|
||||
include/driver_vec.h
|
||||
sources/jtagwait.c
|
||||
Makefile
|
||||
sources/bas_printf.c
|
||||
sources/bas_string.c
|
||||
sources/printf_helper.S
|
||||
sources/vmem_test.c
|
||||
2
tos/fpga_test/vmem_test.includes
Normal file
2
tos/fpga_test/vmem_test.includes
Normal file
@@ -0,0 +1,2 @@
|
||||
include
|
||||
/usr/m68k-atari-mint/include
|
||||
108
tos/jtagwait/Makefile
Executable file
108
tos/jtagwait/Makefile
Executable file
@@ -0,0 +1,108 @@
|
||||
CROSS=Y
|
||||
|
||||
CROSSBINDIR_IS_Y=m68k-atari-mint-
|
||||
CROSSBINDIR_IS_N=
|
||||
|
||||
CROSSBINDIR=$(CROSSBINDIR_IS_$(CROSS))
|
||||
|
||||
UNAME := $(shell uname)
|
||||
ifeq ($(CROSS), Y)
|
||||
ifeq ($(UNAME),Linux)
|
||||
PREFIX=m68k-atari-mint
|
||||
HATARI=hatari
|
||||
else
|
||||
PREFIX=m68k-atari-mint
|
||||
HATARI=/usr/local/bin/hatari
|
||||
endif
|
||||
else
|
||||
PREFIX=/usr
|
||||
endif
|
||||
|
||||
DEPEND=depend
|
||||
TOPDIR = ../..
|
||||
|
||||
LIBCMINI=$(TOPDIR)/../libcmini/libcmini
|
||||
|
||||
INCLUDE=-I$(LIBCMINI)/include -nostdlib
|
||||
LIBS=-lcmini -nostdlib -lgcc
|
||||
CC=$(PREFIX)/bin/gcc
|
||||
|
||||
CC=$(CROSSBINDIR)gcc
|
||||
STRIP=$(CROSSBINDIR)strip
|
||||
STACK=$(CROSSBINDIR)stack
|
||||
|
||||
APP=jtagwait.prg
|
||||
TEST_APP=$(APP)
|
||||
|
||||
CFLAGS=\
|
||||
-O0\
|
||||
-g\
|
||||
-Wl,-Map,mapfile\
|
||||
-Wl,--defsym -Wl,__MBAR=0xff000000\
|
||||
-Wl,--defsym -Wl,__MMUBAR=0xff040000\
|
||||
-Wl,--defsym -Wl,__FPGA_JTAG_LOADED=0xff101000\
|
||||
-Wl,--defsym -Wl,__FPGA_JTAG_VALID=0xff101004\
|
||||
-Wall
|
||||
|
||||
SRCDIR=sources
|
||||
INCDIR=include
|
||||
INCLUDE+=-I$(INCDIR)
|
||||
|
||||
CSRCS=\
|
||||
$(SRCDIR)/jtagwait.c \
|
||||
$(SRCDIR)/bas_printf.c
|
||||
|
||||
ASRCS=$(SRCDIR)/printf_helper.S
|
||||
|
||||
COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS)))
|
||||
AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS)))
|
||||
OBJS=$(COBJS) $(AOBJS)
|
||||
|
||||
TRGTDIRS=./m5475 ./m5475/mshort
|
||||
OBJDIRS=$(patsubst %,%/objs,$(TRGTDIRS))
|
||||
|
||||
#
|
||||
# multilib flags. These must match m68k-atari-mint-gcc -print-multi-lib output
|
||||
#
|
||||
m5475/$(APP):CFLAGS += -mcpu=5475
|
||||
m5475/mshort/$(APP): CFLAGS += -mcpu=5475 -mshort
|
||||
|
||||
all:$(patsubst %,%/$(APP),$(TRGTDIRS))
|
||||
#
|
||||
# generate pattern rules for multilib object files.
|
||||
#
|
||||
define CC_TEMPLATE
|
||||
$(1)/objs/%.o:$(SRCDIR)/%.c
|
||||
@echo CC $$<
|
||||
@$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
|
||||
|
||||
$(1)/objs/%.o:$(SRCDIR)/%.S
|
||||
@echo CC $$<
|
||||
@$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
|
||||
|
||||
$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
|
||||
$(1)/$(APP): $$($(1)_OBJS)
|
||||
@echo CC $$@
|
||||
@$(CC) $$(CFLAGS) -o $$@ $(LIBCMINI)/$(1)/startup.o $$($(1)_OBJS) -L$(LIBCMINI)/$(1) $(LIBS)
|
||||
@$(STRIP) $$@
|
||||
endef
|
||||
$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
|
||||
|
||||
$(DEPEND): $(ASRCS) $(CSRCS)
|
||||
@-rm -f $(DEPEND)
|
||||
@for d in $(TRGTDIRS);\
|
||||
do $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e "s#^\(.*\).o:#$$d/objs/\1.o:#" >> $(DEPEND); \
|
||||
done
|
||||
|
||||
|
||||
clean:
|
||||
@rm -f $(patsubst %,%/objs/*.o,$(TRGTDIRS)) $(patsubst %,%/$(APP),$(TRGTDIRS))
|
||||
@rm -f $(DEPEND) mapfile
|
||||
|
||||
.PHONY: printvars
|
||||
printvars:
|
||||
@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
|
||||
|
||||
ifneq (clean,$(MAKECMDGOALS))
|
||||
-include $(DEPEND)
|
||||
endif
|
||||
67
tos/jtagwait/include/MCF5475.h
Normal file
67
tos/jtagwait/include/MCF5475.h
Normal file
@@ -0,0 +1,67 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_H__
|
||||
#define __MCF5475_H__
|
||||
|
||||
#include <stdint.h>
|
||||
/***
|
||||
* MCF5475 Derivative Memory map definitions from linker command files:
|
||||
* __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
|
||||
* linker symbols must be defined in the linker command file.
|
||||
*/
|
||||
|
||||
typedef uint32_t __attribute__((__may_alias__)) uint32_t_a; /* a type to avoid gcc's complaints about pointer aliasing */
|
||||
|
||||
extern uint8_t _MBAR[];
|
||||
extern uint8_t _MMUBAR[];
|
||||
extern uint8_t _RAMBAR0[];
|
||||
extern uint8_t _RAMBAR0_SIZE[];
|
||||
extern uint8_t _RAMBAR1[];
|
||||
extern uint8_t _RAMBAR1_SIZE[];
|
||||
|
||||
#define MBAR_ADDRESS (uint32_t)_MBAR
|
||||
#define MMUBAR_ADDRESS (uint32_t)_MMUBAR
|
||||
#define RAMBAR0_ADDRESS (uint32_t)_RAMBAR0
|
||||
#define RAMBAR0_SIZE (uint32_t)_RAMBAR0_SIZE
|
||||
#define RAMBAR1_ADDRESS (uint32_t)_RAMBAR1
|
||||
#define RAMBAR1_SIZE (uint32_t)_RAMBAR1_SIZE
|
||||
|
||||
|
||||
#include "MCF5475_SIU.h"
|
||||
#include "MCF5475_MMU.h"
|
||||
#include "MCF5475_SDRAMC.h"
|
||||
#include "MCF5475_XLB.h"
|
||||
#include "MCF5475_CLOCK.h"
|
||||
#include "MCF5475_FBCS.h"
|
||||
#include "MCF5475_INTC.h"
|
||||
#include "MCF5475_GPT.h"
|
||||
#include "MCF5475_SLT.h"
|
||||
#include "MCF5475_GPIO.h"
|
||||
#include "MCF5475_PAD.h"
|
||||
#include "MCF5475_PCI.h"
|
||||
#include "MCF5475_PCIARB.h"
|
||||
#include "MCF5475_EPORT.h"
|
||||
#include "MCF5475_CTM.h"
|
||||
#include "MCF5475_DMA.h"
|
||||
#include "MCF5475_PSC.h"
|
||||
#include "MCF5475_DSPI.h"
|
||||
#include "MCF5475_I2C.h"
|
||||
#include "MCF5475_FEC.h"
|
||||
#include "MCF5475_USB.h"
|
||||
#include "MCF5475_SRAM.h"
|
||||
#include "MCF5475_SEC.h"
|
||||
|
||||
#endif /* __MCF5475_H__ */
|
||||
47
tos/jtagwait/include/MCF5475_CLOCK.h
Normal file
47
tos/jtagwait/include/MCF5475_CLOCK.h
Normal file
@@ -0,0 +1,47 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_CLOCK_H__
|
||||
#define __MCF5475_CLOCK_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Clock Module (CLOCK)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CLOCK_SPCR (*(volatile uint32_t*)(&_MBAR[0x300]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_CLOCK_SPCR */
|
||||
#define MCF_CLOCK_SPCR_MEMEN (0x1)
|
||||
#define MCF_CLOCK_SPCR_PCIEN (0x2)
|
||||
#define MCF_CLOCK_SPCR_FBEN (0x4)
|
||||
#define MCF_CLOCK_SPCR_CAN0EN (0x8)
|
||||
#define MCF_CLOCK_SPCR_DMAEN (0x10)
|
||||
#define MCF_CLOCK_SPCR_FEC0EN (0x20)
|
||||
#define MCF_CLOCK_SPCR_FEC1EN (0x40)
|
||||
#define MCF_CLOCK_SPCR_USBEN (0x80)
|
||||
#define MCF_CLOCK_SPCR_PSCEN (0x200)
|
||||
#define MCF_CLOCK_SPCR_CAN1EN (0x800)
|
||||
#define MCF_CLOCK_SPCR_CRYENA (0x1000)
|
||||
#define MCF_CLOCK_SPCR_CRYENB (0x2000)
|
||||
#define MCF_CLOCK_SPCR_COREN (0x4000)
|
||||
#define MCF_CLOCK_SPCR_PLLK (0x80000000)
|
||||
|
||||
|
||||
#endif /* __MCF5475_CLOCK_H__ */
|
||||
76
tos/jtagwait/include/MCF5475_CTM.h
Normal file
76
tos/jtagwait/include/MCF5475_CTM.h
Normal file
@@ -0,0 +1,76 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_CTM_H__
|
||||
#define __MCF5475_CTM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Comm Timer Module (CTM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CTM_CTCR0 (*(volatile uint32_t*)(&_MBAR[0x7F00]))
|
||||
#define MCF_CTM_CTCR1 (*(volatile uint32_t*)(&_MBAR[0x7F04]))
|
||||
#define MCF_CTM_CTCR2 (*(volatile uint32_t*)(&_MBAR[0x7F08]))
|
||||
#define MCF_CTM_CTCR3 (*(volatile uint32_t*)(&_MBAR[0x7F0C]))
|
||||
#define MCF_CTM_CTCR4 (*(volatile uint32_t*)(&_MBAR[0x7F10]))
|
||||
#define MCF_CTM_CTCR5 (*(volatile uint32_t*)(&_MBAR[0x7F14]))
|
||||
#define MCF_CTM_CTCR6 (*(volatile uint32_t*)(&_MBAR[0x7F18]))
|
||||
#define MCF_CTM_CTCR7 (*(volatile uint32_t*)(&_MBAR[0x7F1C]))
|
||||
#define MCF_CTM_CTCRF(x) (*(volatile uint32_t*)(&_MBAR[0x7F00 + ((x)*0x4)]))
|
||||
#define MCF_CTM_CTCRV(x) (*(volatile uint32_t*)(&_MBAR[0x7F10 + ((x-4)*0x4)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_CTM_CTCRF */
|
||||
#define MCF_CTM_CTCRF_CRV(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_CTM_CTCRF_S(x) (((x)&0xF)<<0x10)
|
||||
#define MCF_CTM_CTCRF_S_CLK_1 (0)
|
||||
#define MCF_CTM_CTCRF_S_CLK_2 (0x10000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_4 (0x20000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_8 (0x30000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_16 (0x40000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_32 (0x50000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_64 (0x60000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_128 (0x70000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_256 (0x80000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_EXT (0x90000)
|
||||
#define MCF_CTM_CTCRF_PCT(x) (((x)&0x7)<<0x14)
|
||||
#define MCF_CTM_CTCRF_PCT_100 (0)
|
||||
#define MCF_CTM_CTCRF_PCT_50 (0x100000)
|
||||
#define MCF_CTM_CTCRF_PCT_25 (0x200000)
|
||||
#define MCF_CTM_CTCRF_PCT_12p5 (0x300000)
|
||||
#define MCF_CTM_CTCRF_PCT_6p25 (0x400000)
|
||||
#define MCF_CTM_CTCRF_PCT_OFF (0x500000)
|
||||
#define MCF_CTM_CTCRF_M (0x800000)
|
||||
#define MCF_CTM_CTCRF_IM (0x1000000)
|
||||
#define MCF_CTM_CTCRF_I (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_CTM_CTCRV */
|
||||
#define MCF_CTM_CTCRV_CRV(x) (((x)&0xFFFFFF)<<0)
|
||||
#define MCF_CTM_CTCRV_PCT(x) (((x)&0x7)<<0x18)
|
||||
#define MCF_CTM_CTCRV_PCT_100 (0)
|
||||
#define MCF_CTM_CTCRV_PCT_50 (0x1000000)
|
||||
#define MCF_CTM_CTCRV_PCT_25 (0x2000000)
|
||||
#define MCF_CTM_CTCRV_PCT_12p5 (0x3000000)
|
||||
#define MCF_CTM_CTCRV_PCT_6p25 (0x4000000)
|
||||
#define MCF_CTM_CTCRV_PCT_OFF (0x5000000)
|
||||
#define MCF_CTM_CTCRV_M (0x8000000)
|
||||
#define MCF_CTM_CTCRV_S (0x10000000)
|
||||
|
||||
|
||||
#endif /* __MCF5475_CTM_H__ */
|
||||
234
tos/jtagwait/include/MCF5475_DMA.h
Normal file
234
tos/jtagwait/include/MCF5475_DMA.h
Normal file
@@ -0,0 +1,234 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_DMA_H__
|
||||
#define __MCF5475_DMA_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Multichannel DMA (DMA)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_DMA_TASKBAR (*(volatile uint32_t*)(&_MBAR[0x8000]))
|
||||
#define MCF_DMA_CP (*(volatile uint32_t*)(&_MBAR[0x8004]))
|
||||
#define MCF_DMA_EP (*(volatile uint32_t*)(&_MBAR[0x8008]))
|
||||
#define MCF_DMA_VP (*(volatile uint32_t*)(&_MBAR[0x800C]))
|
||||
#define MCF_DMA_PTD (*(volatile uint32_t*)(&_MBAR[0x8010]))
|
||||
#define MCF_DMA_DIPR (*(volatile uint32_t*)(&_MBAR[0x8014]))
|
||||
#define MCF_DMA_DIMR (*(volatile uint32_t*)(&_MBAR[0x8018]))
|
||||
#define MCF_DMA_TCR0 (*(volatile uint16_t*)(&_MBAR[0x801C]))
|
||||
#define MCF_DMA_TCR1 (*(volatile uint16_t*)(&_MBAR[0x801E]))
|
||||
#define MCF_DMA_TCR2 (*(volatile uint16_t*)(&_MBAR[0x8020]))
|
||||
#define MCF_DMA_TCR3 (*(volatile uint16_t*)(&_MBAR[0x8022]))
|
||||
#define MCF_DMA_TCR4 (*(volatile uint16_t*)(&_MBAR[0x8024]))
|
||||
#define MCF_DMA_TCR5 (*(volatile uint16_t*)(&_MBAR[0x8026]))
|
||||
#define MCF_DMA_TCR6 (*(volatile uint16_t*)(&_MBAR[0x8028]))
|
||||
#define MCF_DMA_TCR7 (*(volatile uint16_t*)(&_MBAR[0x802A]))
|
||||
#define MCF_DMA_TCR8 (*(volatile uint16_t*)(&_MBAR[0x802C]))
|
||||
#define MCF_DMA_TCR9 (*(volatile uint16_t*)(&_MBAR[0x802E]))
|
||||
#define MCF_DMA_TCR10 (*(volatile uint16_t*)(&_MBAR[0x8030]))
|
||||
#define MCF_DMA_TCR11 (*(volatile uint16_t*)(&_MBAR[0x8032]))
|
||||
#define MCF_DMA_TCR12 (*(volatile uint16_t*)(&_MBAR[0x8034]))
|
||||
#define MCF_DMA_TCR13 (*(volatile uint16_t*)(&_MBAR[0x8036]))
|
||||
#define MCF_DMA_TCR14 (*(volatile uint16_t*)(&_MBAR[0x8038]))
|
||||
#define MCF_DMA_TCR15 (*(volatile uint16_t*)(&_MBAR[0x803A]))
|
||||
#define MCF_DMA_PRIOR0 (*(volatile uint8_t *)(&_MBAR[0x803C]))
|
||||
#define MCF_DMA_PRIOR1 (*(volatile uint8_t *)(&_MBAR[0x803D]))
|
||||
#define MCF_DMA_PRIOR2 (*(volatile uint8_t *)(&_MBAR[0x803E]))
|
||||
#define MCF_DMA_PRIOR3 (*(volatile uint8_t *)(&_MBAR[0x803F]))
|
||||
#define MCF_DMA_PRIOR4 (*(volatile uint8_t *)(&_MBAR[0x8040]))
|
||||
#define MCF_DMA_PRIOR5 (*(volatile uint8_t *)(&_MBAR[0x8041]))
|
||||
#define MCF_DMA_PRIOR6 (*(volatile uint8_t *)(&_MBAR[0x8042]))
|
||||
#define MCF_DMA_PRIOR7 (*(volatile uint8_t *)(&_MBAR[0x8043]))
|
||||
#define MCF_DMA_PRIOR8 (*(volatile uint8_t *)(&_MBAR[0x8044]))
|
||||
#define MCF_DMA_PRIOR9 (*(volatile uint8_t *)(&_MBAR[0x8045]))
|
||||
#define MCF_DMA_PRIOR10 (*(volatile uint8_t *)(&_MBAR[0x8046]))
|
||||
#define MCF_DMA_PRIOR11 (*(volatile uint8_t *)(&_MBAR[0x8047]))
|
||||
#define MCF_DMA_PRIOR12 (*(volatile uint8_t *)(&_MBAR[0x8048]))
|
||||
#define MCF_DMA_PRIOR13 (*(volatile uint8_t *)(&_MBAR[0x8049]))
|
||||
#define MCF_DMA_PRIOR14 (*(volatile uint8_t *)(&_MBAR[0x804A]))
|
||||
#define MCF_DMA_PRIOR15 (*(volatile uint8_t *)(&_MBAR[0x804B]))
|
||||
#define MCF_DMA_PRIOR16 (*(volatile uint8_t *)(&_MBAR[0x804C]))
|
||||
#define MCF_DMA_PRIOR17 (*(volatile uint8_t *)(&_MBAR[0x804D]))
|
||||
#define MCF_DMA_PRIOR18 (*(volatile uint8_t *)(&_MBAR[0x804E]))
|
||||
#define MCF_DMA_PRIOR19 (*(volatile uint8_t *)(&_MBAR[0x804F]))
|
||||
#define MCF_DMA_PRIOR20 (*(volatile uint8_t *)(&_MBAR[0x8050]))
|
||||
#define MCF_DMA_PRIOR21 (*(volatile uint8_t *)(&_MBAR[0x8051]))
|
||||
#define MCF_DMA_PRIOR22 (*(volatile uint8_t *)(&_MBAR[0x8052]))
|
||||
#define MCF_DMA_PRIOR23 (*(volatile uint8_t *)(&_MBAR[0x8053]))
|
||||
#define MCF_DMA_PRIOR24 (*(volatile uint8_t *)(&_MBAR[0x8054]))
|
||||
#define MCF_DMA_PRIOR25 (*(volatile uint8_t *)(&_MBAR[0x8055]))
|
||||
#define MCF_DMA_PRIOR26 (*(volatile uint8_t *)(&_MBAR[0x8056]))
|
||||
#define MCF_DMA_PRIOR27 (*(volatile uint8_t *)(&_MBAR[0x8057]))
|
||||
#define MCF_DMA_PRIOR28 (*(volatile uint8_t *)(&_MBAR[0x8058]))
|
||||
#define MCF_DMA_PRIOR29 (*(volatile uint8_t *)(&_MBAR[0x8059]))
|
||||
#define MCF_DMA_PRIOR30 (*(volatile uint8_t *)(&_MBAR[0x805A]))
|
||||
#define MCF_DMA_PRIOR31 (*(volatile uint8_t *)(&_MBAR[0x805B]))
|
||||
#define MCF_DMA_IMCR (*(volatile uint32_t*)(&_MBAR[0x805C]))
|
||||
#define MCF_DMA_TSKSZ0 (*(volatile uint32_t*)(&_MBAR[0x8060]))
|
||||
#define MCF_DMA_TSKSZ1 (*(volatile uint32_t*)(&_MBAR[0x8064]))
|
||||
#define MCF_DMA_DBGCOMP0 (*(volatile uint32_t*)(&_MBAR[0x8070]))
|
||||
#define MCF_DMA_DBGCOMP2 (*(volatile uint32_t*)(&_MBAR[0x8074]))
|
||||
#define MCF_DMA_DBGCTL (*(volatile uint32_t*)(&_MBAR[0x8078]))
|
||||
#define MCF_DMA_TCR(x) (*(volatile uint16_t*)(&_MBAR[0x801C + ((x)*0x2)]))
|
||||
#define MCF_DMA_PRIOR(x) (*(volatile uint8_t *)(&_MBAR[0x803C + ((x)*0x1)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_TASKBAR */
|
||||
#define MCF_DMA_TASKBAR_TASK_BASE_ADDRESS(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_CP */
|
||||
#define MCF_DMA_CP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_EP */
|
||||
#define MCF_DMA_EP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_VP */
|
||||
#define MCF_DMA_VP_VARIABLE_POINTER(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_PTD */
|
||||
#define MCF_DMA_PTD_PCTL0 (0x1)
|
||||
#define MCF_DMA_PTD_PCTL1 (0x2)
|
||||
#define MCF_DMA_PTD_PCTL13 (0x2000)
|
||||
#define MCF_DMA_PTD_PCTL14 (0x4000)
|
||||
#define MCF_DMA_PTD_PCTL15 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DIPR */
|
||||
#define MCF_DMA_DIPR_TASK(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DIMR */
|
||||
#define MCF_DMA_DIMR_TASK(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_TCR */
|
||||
#define MCF_DMA_TCR_ASTSKNUM(x) (((x)&0xF)<<0)
|
||||
#define MCF_DMA_TCR_HLDINITNUM (0x20)
|
||||
#define MCF_DMA_TCR_HIPRITSKEN (0x40)
|
||||
#define MCF_DMA_TCR_ASTRT (0x80)
|
||||
#define MCF_DMA_TCR_INITNUM(x) (((x)&0x1F)<<0x8)
|
||||
#define MCF_DMA_TCR_ALWINIT (0x2000)
|
||||
#define MCF_DMA_TCR_V (0x4000)
|
||||
#define MCF_DMA_TCR_EN (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_PRIOR */
|
||||
#define MCF_DMA_PRIOR_PRI(x) (((x)&0x7)<<0)
|
||||
#define MCF_DMA_PRIOR_HLD (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_IMCR */
|
||||
#define MCF_DMA_IMCR_IMC16(x) (((x)&0x3)<<0)
|
||||
#define MCF_DMA_IMCR_IMC17(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_DMA_IMCR_IMC18(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_DMA_IMCR_IMC19(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_DMA_IMCR_IMC20(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_DMA_IMCR_IMC21(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_DMA_IMCR_IMC22(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_DMA_IMCR_IMC23(x) (((x)&0x3)<<0xE)
|
||||
#define MCF_DMA_IMCR_IMC24(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_DMA_IMCR_IMC25(x) (((x)&0x3)<<0x12)
|
||||
#define MCF_DMA_IMCR_IMC26(x) (((x)&0x3)<<0x14)
|
||||
#define MCF_DMA_IMCR_IMC27(x) (((x)&0x3)<<0x16)
|
||||
#define MCF_DMA_IMCR_IMC28(x) (((x)&0x3)<<0x18)
|
||||
#define MCF_DMA_IMCR_IMC29(x) (((x)&0x3)<<0x1A)
|
||||
#define MCF_DMA_IMCR_IMC30(x) (((x)&0x3)<<0x1C)
|
||||
#define MCF_DMA_IMCR_IMC31(x) (((x)&0x3)<<0x1E)
|
||||
|
||||
|
||||
#define MCF_DMA_IMCR_IMC16_FEC0RX (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC17_FEC0TX (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC18_FEC0RX (0x00000020)
|
||||
#define MCF_DMA_IMCR_IMC19_FEC0TX (0x00000080)
|
||||
#define MCF_DMA_IMCR_IMC20_FEC1RX (0x00000100)
|
||||
#define MCF_DMA_IMCR_IMC21_DREQ1 (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC21_FEC1TX (0x00000400)
|
||||
#define MCF_DMA_IMCR_IMC22_FEC0RX (0x00001000)
|
||||
#define MCF_DMA_IMCR_IMC23_FEC0TX (0x00004000)
|
||||
#define MCF_DMA_IMCR_IMC24_CTM0 (0x00010000)
|
||||
#define MCF_DMA_IMCR_IMC24_FEC1RX (0x00020000)
|
||||
#define MCF_DMA_IMCR_IMC25_CTM1 (0x00040000)
|
||||
#define MCF_DMA_IMCR_IMC25_FEC1TX (0x00080000)
|
||||
#define MCF_DMA_IMCR_IMC26_USBEP4 (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC26_CTM2 (0x00200000)
|
||||
#define MCF_DMA_IMCR_IMC27_USBEP5 (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC27_CTM3 (0x00800000)
|
||||
#define MCF_DMA_IMCR_IMC28_USBEP6 (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC28_CTM4 (0x01000000)
|
||||
#define MCF_DMA_IMCR_IMC28_DREQ1 (0x02000000)
|
||||
#define MCF_DMA_IMCR_IMC28_PSC2RX (0x03000000)
|
||||
#define MCF_DMA_IMCR_IMC29_DREQ1 (0x04000000)
|
||||
#define MCF_DMA_IMCR_IMC29_CTM5 (0x08000000)
|
||||
#define MCF_DMA_IMCR_IMC29_PSC2TX (0x0C000000)
|
||||
#define MCF_DMA_IMCR_IMC30_FEC1RX (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC30_CTM6 (0x10000000)
|
||||
#define MCF_DMA_IMCR_IMC30_PSC3RX (0x30000000)
|
||||
#define MCF_DMA_IMCR_IMC31_FEC1TX (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC31_CTM7 (0x80000000)
|
||||
#define MCF_DMA_IMCR_IMC31_PSC3TX (0xC0000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_TSKSZ0 */
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ7(x) (((x)&0x3)<<0)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ7(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ6(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ6(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ5(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ5(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ4(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ4(x) (((x)&0x3)<<0xE)
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ3(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ3(x) (((x)&0x3)<<0x12)
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ2(x) (((x)&0x3)<<0x14)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ2(x) (((x)&0x3)<<0x16)
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ1(x) (((x)&0x3)<<0x18)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ1(x) (((x)&0x3)<<0x1A)
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ0(x) (((x)&0x3)<<0x1C)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ0(x) (((x)&0x3)<<0x1E)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_TSKSZ1 */
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ15(x) (((x)&0x3)<<0)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ15(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ14(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ14(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ13(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ13(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ12(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ12(x) (((x)&0x3)<<0xE)
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ11(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ11(x) (((x)&0x3)<<0x12)
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ10(x) (((x)&0x3)<<0x14)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ10(x) (((x)&0x3)<<0x16)
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ9(x) (((x)&0x3)<<0x18)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ9(x) (((x)&0x3)<<0x1A)
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ8(x) (((x)&0x3)<<0x1C)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ8(x) (((x)&0x3)<<0x1E)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DBGCOMP0 */
|
||||
#define MCF_DMA_DBGCOMP0_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DBGCOMP2 */
|
||||
#define MCF_DMA_DBGCOMP2_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DBGCTL */
|
||||
#define MCF_DMA_DBGCTL_I (0x2)
|
||||
#define MCF_DMA_DBGCTL_E (0x4)
|
||||
#define MCF_DMA_DBGCTL_AND_OR (0x80)
|
||||
#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_2(x) (((x)&0x7)<<0x8)
|
||||
#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_1(x) (((x)&0x7)<<0xB)
|
||||
#define MCF_DMA_DBGCTL_B (0x4000)
|
||||
#define MCF_DMA_DBGCTL_AA (0x8000)
|
||||
#define MCF_DMA_DBGCTL_BLOCK_TASKS(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
|
||||
#endif /* __MCF5475_DMA_H__ */
|
||||
150
tos/jtagwait/include/MCF5475_DSPI.h
Normal file
150
tos/jtagwait/include/MCF5475_DSPI.h
Normal file
@@ -0,0 +1,150 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_DSPI_H__
|
||||
#define __MCF5475_DSPI_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* DMA Serial Peripheral Interface (DSPI)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_DSPI_DMCR (*(volatile uint32_t*)(&_MBAR[0x8A00]))
|
||||
#define MCF_DSPI_DTCR (*(volatile uint32_t*)(&_MBAR[0x8A08]))
|
||||
#define MCF_DSPI_DCTAR0 (*(volatile uint32_t*)(&_MBAR[0x8A0C]))
|
||||
#define MCF_DSPI_DCTAR1 (*(volatile uint32_t*)(&_MBAR[0x8A10]))
|
||||
#define MCF_DSPI_DCTAR2 (*(volatile uint32_t*)(&_MBAR[0x8A14]))
|
||||
#define MCF_DSPI_DCTAR3 (*(volatile uint32_t*)(&_MBAR[0x8A18]))
|
||||
#define MCF_DSPI_DCTAR4 (*(volatile uint32_t*)(&_MBAR[0x8A1C]))
|
||||
#define MCF_DSPI_DCTAR5 (*(volatile uint32_t*)(&_MBAR[0x8A20]))
|
||||
#define MCF_DSPI_DCTAR6 (*(volatile uint32_t*)(&_MBAR[0x8A24]))
|
||||
#define MCF_DSPI_DCTAR7 (*(volatile uint32_t*)(&_MBAR[0x8A28]))
|
||||
#define MCF_DSPI_DSR (*(volatile uint32_t*)(&_MBAR[0x8A2C]))
|
||||
#define MCF_DSPI_DIRSR (*(volatile uint32_t*)(&_MBAR[0x8A30]))
|
||||
#define MCF_DSPI_DTFR (*(volatile uint32_t*)(&_MBAR[0x8A34]))
|
||||
#define MCF_DSPI_DRFR (*(volatile uint32_t*)(&_MBAR[0x8A38]))
|
||||
#define MCF_DSPI_DTFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A3C]))
|
||||
#define MCF_DSPI_DTFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A40]))
|
||||
#define MCF_DSPI_DTFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A44]))
|
||||
#define MCF_DSPI_DTFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A48]))
|
||||
#define MCF_DSPI_DRFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A7C]))
|
||||
#define MCF_DSPI_DRFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A80]))
|
||||
#define MCF_DSPI_DRFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A84]))
|
||||
#define MCF_DSPI_DRFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A88]))
|
||||
#define MCF_DSPI_DCTAR(x) (*(volatile uint32_t*)(&_MBAR[0x8A0C + ((x)*0x4)]))
|
||||
#define MCF_DSPI_DTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A3C + ((x)*0x4)]))
|
||||
#define MCF_DSPI_DRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A7C + ((x)*0x4)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DMCR */
|
||||
#define MCF_DSPI_DMCR_HALT (0x1)
|
||||
#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_DSPI_DMCR_SMPL_PT_0CLK (0)
|
||||
#define MCF_DSPI_DMCR_SMPL_PT_1CLK (0x100)
|
||||
#define MCF_DSPI_DMCR_SMPL_PT_2CLK (0x200)
|
||||
#define MCF_DSPI_DMCR_CRXF (0x400)
|
||||
#define MCF_DSPI_DMCR_CTXF (0x800)
|
||||
#define MCF_DSPI_DMCR_DRXF (0x1000)
|
||||
#define MCF_DSPI_DMCR_DTXF (0x2000)
|
||||
#define MCF_DSPI_DMCR_CSIS0 (0x10000)
|
||||
#define MCF_DSPI_DMCR_CSIS2 (0x40000)
|
||||
#define MCF_DSPI_DMCR_CSIS3 (0x80000)
|
||||
#define MCF_DSPI_DMCR_CSIS5 (0x200000)
|
||||
#define MCF_DSPI_DMCR_ROOE (0x1000000)
|
||||
#define MCF_DSPI_DMCR_PCSSE (0x2000000)
|
||||
#define MCF_DSPI_DMCR_MTFE (0x4000000)
|
||||
#define MCF_DSPI_DMCR_FRZ (0x8000000)
|
||||
#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x3)<<0x1C)
|
||||
#define MCF_DSPI_DMCR_CSCK (0x40000000)
|
||||
#define MCF_DSPI_DMCR_MSTR (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DTCR */
|
||||
#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DCTAR */
|
||||
#define MCF_DSPI_DCTAR_BR(x) (((x)&0xF)<<0)
|
||||
#define MCF_DSPI_DCTAR_DT(x) (((x)&0xF)<<0x4)
|
||||
#define MCF_DSPI_DCTAR_ASC(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0xF)<<0xC)
|
||||
#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_DSPI_DCTAR_PBR_1CLK (0)
|
||||
#define MCF_DSPI_DCTAR_PBR_3CLK (0x10000)
|
||||
#define MCF_DSPI_DCTAR_PBR_5CLK (0x20000)
|
||||
#define MCF_DSPI_DCTAR_PBR_7CLK (0x30000)
|
||||
#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x3)<<0x12)
|
||||
#define MCF_DSPI_DCTAR_PDT_1CLK (0)
|
||||
#define MCF_DSPI_DCTAR_PDT_3CLK (0x40000)
|
||||
#define MCF_DSPI_DCTAR_PDT_5CLK (0x80000)
|
||||
#define MCF_DSPI_DCTAR_PDT_7CLK (0xC0000)
|
||||
#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x3)<<0x14)
|
||||
#define MCF_DSPI_DCTAR_PASC_1CLK (0)
|
||||
#define MCF_DSPI_DCTAR_PASC_3CLK (0x100000)
|
||||
#define MCF_DSPI_DCTAR_PASC_5CLK (0x200000)
|
||||
#define MCF_DSPI_DCTAR_PASC_7CLK (0x300000)
|
||||
#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x3)<<0x16)
|
||||
#define MCF_DSPI_DCTAR_LSBFE (0x1000000)
|
||||
#define MCF_DSPI_DCTAR_CPHA (0x2000000)
|
||||
#define MCF_DSPI_DCTAR_CPOL (0x4000000)
|
||||
#define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0xF)<<0x1B)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DSR */
|
||||
#define MCF_DSPI_DSR_RXPTR(x) (((x)&0xF)<<0)
|
||||
#define MCF_DSPI_DSR_RXCTR(x) (((x)&0xF)<<0x4)
|
||||
#define MCF_DSPI_DSR_TXPTR(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_DSPI_DSR_TXCTR(x) (((x)&0xF)<<0xC)
|
||||
#define MCF_DSPI_DSR_RFDF (0x20000)
|
||||
#define MCF_DSPI_DSR_RFOF (0x80000)
|
||||
#define MCF_DSPI_DSR_TFFF (0x2000000)
|
||||
#define MCF_DSPI_DSR_TFUF (0x8000000)
|
||||
#define MCF_DSPI_DSR_EOQF (0x10000000)
|
||||
#define MCF_DSPI_DSR_TXRXS (0x40000000)
|
||||
#define MCF_DSPI_DSR_TCF (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DIRSR */
|
||||
#define MCF_DSPI_DIRSR_RFDFS (0x10000)
|
||||
#define MCF_DSPI_DIRSR_RFDFE (0x20000)
|
||||
#define MCF_DSPI_DIRSR_RFOFE (0x80000)
|
||||
#define MCF_DSPI_DIRSR_TFFFS (0x1000000)
|
||||
#define MCF_DSPI_DIRSR_TFFFE (0x2000000)
|
||||
#define MCF_DSPI_DIRSR_TFUFE (0x8000000)
|
||||
#define MCF_DSPI_DIRSR_EOQFE (0x10000000)
|
||||
#define MCF_DSPI_DIRSR_TCFE (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DTFR */
|
||||
#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_DSPI_DTFR_CS0 (0x10000)
|
||||
#define MCF_DSPI_DTFR_CS2 (0x40000)
|
||||
#define MCF_DSPI_DTFR_CS3 (0x80000)
|
||||
#define MCF_DSPI_DTFR_CS5 (0x200000)
|
||||
#define MCF_DSPI_DTFR_CTCNT (0x4000000)
|
||||
#define MCF_DSPI_DTFR_EOQ (0x8000000)
|
||||
#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x7)<<0x1C)
|
||||
#define MCF_DSPI_DTFR_CONT (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DRFR */
|
||||
#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DTFDR */
|
||||
#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_DSPI_DTFDR_TXCMD(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DRFDR */
|
||||
#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF5475_DSPI_H__ */
|
||||
123
tos/jtagwait/include/MCF5475_EPORT.h
Normal file
123
tos/jtagwait/include/MCF5475_EPORT.h
Normal file
@@ -0,0 +1,123 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_EPORT_H__
|
||||
#define __MCF5475_EPORT_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Edge Port Module (EPORT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_EPORT_EPPAR (*(volatile uint16_t*)(&_MBAR[0xF00]))
|
||||
#define MCF_EPORT_EPDDR (*(volatile uint8_t *)(&_MBAR[0xF04]))
|
||||
#define MCF_EPORT_EPIER (*(volatile uint8_t *)(&_MBAR[0xF05]))
|
||||
#define MCF_EPORT_EPDR (*(volatile uint8_t *)(&_MBAR[0xF08]))
|
||||
#define MCF_EPORT_EPPDR (*(volatile uint8_t *)(&_MBAR[0xF09]))
|
||||
#define MCF_EPORT_EPFR (*(volatile uint8_t *)(&_MBAR[0xF0C]))
|
||||
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPPAR */
|
||||
#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC)
|
||||
#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30)
|
||||
#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0)
|
||||
#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300)
|
||||
#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00)
|
||||
#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
|
||||
#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
|
||||
#define MCF_EPORT_EPPAR_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_RISING (0x1)
|
||||
#define MCF_EPORT_EPPAR_FALLING (0x2)
|
||||
#define MCF_EPORT_EPPAR_BOTH (0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPDDR */
|
||||
#define MCF_EPORT_EPDDR_EPDD1 (0x2)
|
||||
#define MCF_EPORT_EPDDR_EPDD2 (0x4)
|
||||
#define MCF_EPORT_EPDDR_EPDD3 (0x8)
|
||||
#define MCF_EPORT_EPDDR_EPDD4 (0x10)
|
||||
#define MCF_EPORT_EPDDR_EPDD5 (0x20)
|
||||
#define MCF_EPORT_EPDDR_EPDD6 (0x40)
|
||||
#define MCF_EPORT_EPDDR_EPDD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPIER */
|
||||
#define MCF_EPORT_EPIER_EPIE1 (0x2)
|
||||
#define MCF_EPORT_EPIER_EPIE2 (0x4)
|
||||
#define MCF_EPORT_EPIER_EPIE3 (0x8)
|
||||
#define MCF_EPORT_EPIER_EPIE4 (0x10)
|
||||
#define MCF_EPORT_EPIER_EPIE5 (0x20)
|
||||
#define MCF_EPORT_EPIER_EPIE6 (0x40)
|
||||
#define MCF_EPORT_EPIER_EPIE7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPDR */
|
||||
#define MCF_EPORT_EPDR_EPD1 (0x2)
|
||||
#define MCF_EPORT_EPDR_EPD2 (0x4)
|
||||
#define MCF_EPORT_EPDR_EPD3 (0x8)
|
||||
#define MCF_EPORT_EPDR_EPD4 (0x10)
|
||||
#define MCF_EPORT_EPDR_EPD5 (0x20)
|
||||
#define MCF_EPORT_EPDR_EPD6 (0x40)
|
||||
#define MCF_EPORT_EPDR_EPD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPPDR */
|
||||
#define MCF_EPORT_EPPDR_EPPD1 (0x2)
|
||||
#define MCF_EPORT_EPPDR_EPPD2 (0x4)
|
||||
#define MCF_EPORT_EPPDR_EPPD3 (0x8)
|
||||
#define MCF_EPORT_EPPDR_EPPD4 (0x10)
|
||||
#define MCF_EPORT_EPPDR_EPPD5 (0x20)
|
||||
#define MCF_EPORT_EPPDR_EPPD6 (0x40)
|
||||
#define MCF_EPORT_EPPDR_EPPD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPFR */
|
||||
#define MCF_EPORT_EPFR_EPF1 (0x2)
|
||||
#define MCF_EPORT_EPFR_EPF2 (0x4)
|
||||
#define MCF_EPORT_EPFR_EPF3 (0x8)
|
||||
#define MCF_EPORT_EPFR_EPF4 (0x10)
|
||||
#define MCF_EPORT_EPFR_EPF5 (0x20)
|
||||
#define MCF_EPORT_EPFR_EPF6 (0x40)
|
||||
#define MCF_EPORT_EPFR_EPF7 (0x80)
|
||||
|
||||
|
||||
#endif /* __MCF5475_EPORT_H__ */
|
||||
100
tos/jtagwait/include/MCF5475_FBCS.h
Normal file
100
tos/jtagwait/include/MCF5475_FBCS.h
Normal file
@@ -0,0 +1,100 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_FBCS_H__
|
||||
#define __MCF5475_FBCS_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* FlexBus Chip Select Module (FBCS)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_FBCS0_CSAR (*(volatile uint32_t*)(&_MBAR[0x500]))
|
||||
#define MCF_FBCS0_CSMR (*(volatile uint32_t*)(&_MBAR[0x504]))
|
||||
#define MCF_FBCS0_CSCR (*(volatile uint32_t*)(&_MBAR[0x508]))
|
||||
|
||||
#define MCF_FBCS1_CSAR (*(volatile uint32_t*)(&_MBAR[0x50C]))
|
||||
#define MCF_FBCS1_CSMR (*(volatile uint32_t*)(&_MBAR[0x510]))
|
||||
#define MCF_FBCS1_CSCR (*(volatile uint32_t*)(&_MBAR[0x514]))
|
||||
|
||||
#define MCF_FBCS2_CSAR (*(volatile uint32_t*)(&_MBAR[0x518]))
|
||||
#define MCF_FBCS2_CSMR (*(volatile uint32_t*)(&_MBAR[0x51C]))
|
||||
#define MCF_FBCS2_CSCR (*(volatile uint32_t*)(&_MBAR[0x520]))
|
||||
|
||||
#define MCF_FBCS3_CSAR (*(volatile uint32_t*)(&_MBAR[0x524]))
|
||||
#define MCF_FBCS3_CSMR (*(volatile uint32_t*)(&_MBAR[0x528]))
|
||||
#define MCF_FBCS3_CSCR (*(volatile uint32_t*)(&_MBAR[0x52C]))
|
||||
|
||||
#define MCF_FBCS4_CSAR (*(volatile uint32_t*)(&_MBAR[0x530]))
|
||||
#define MCF_FBCS4_CSMR (*(volatile uint32_t*)(&_MBAR[0x534]))
|
||||
#define MCF_FBCS4_CSCR (*(volatile uint32_t*)(&_MBAR[0x538]))
|
||||
|
||||
#define MCF_FBCS5_CSAR (*(volatile uint32_t*)(&_MBAR[0x53C]))
|
||||
#define MCF_FBCS5_CSMR (*(volatile uint32_t*)(&_MBAR[0x540]))
|
||||
#define MCF_FBCS5_CSCR (*(volatile uint32_t*)(&_MBAR[0x544]))
|
||||
|
||||
#define MCF_FBCS_CSAR(x) (*(volatile uint32_t*)(&_MBAR[0x500 + ((x)*0xC)]))
|
||||
#define MCF_FBCS_CSMR(x) (*(volatile uint32_t*)(&_MBAR[0x504 + ((x)*0xC)]))
|
||||
#define MCF_FBCS_CSCR(x) (*(volatile uint32_t*)(&_MBAR[0x508 + ((x)*0xC)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_FBCS_CSAR */
|
||||
#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FBCS_CSMR */
|
||||
#define MCF_FBCS_CSMR_V (0x1)
|
||||
#define MCF_FBCS_CSMR_WP (0x100)
|
||||
#define MCF_FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<0x10)
|
||||
#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_256M (0xFFF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_128M (0x7FF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_64M (0x3FF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_32M (0x1FF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_16M (0xFF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_8M (0x7F0000)
|
||||
#define MCF_FBCS_CSMR_BAM_4M (0x3F0000)
|
||||
#define MCF_FBCS_CSMR_BAM_2M (0x1F0000)
|
||||
#define MCF_FBCS_CSMR_BAM_1M (0xF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_1024K (0xF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_512K (0x70000)
|
||||
#define MCF_FBCS_CSMR_BAM_256K (0x30000)
|
||||
#define MCF_FBCS_CSMR_BAM_128K (0x10000)
|
||||
#define MCF_FBCS_CSMR_BAM_64K (0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FBCS_CSCR */
|
||||
#define MCF_FBCS_CSCR_BSTW (0x8)
|
||||
#define MCF_FBCS_CSCR_BSTR (0x10)
|
||||
#define MCF_FBCS_CSCR_BEM (0x20)
|
||||
#define MCF_FBCS_CSCR_PS(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_FBCS_CSCR_PS_32 (0)
|
||||
#define MCF_FBCS_CSCR_PS_8 (0x40)
|
||||
#define MCF_FBCS_CSCR_PS_16 (0x80)
|
||||
#define MCF_FBCS_CSCR_AA (0x100)
|
||||
#define MCF_FBCS_CSCR_WS(x) (((x)&0x3F)<<0xA)
|
||||
#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x3)<<0x12)
|
||||
#define MCF_FBCS_CSCR_ASET(x) (((x)&0x3)<<0x14)
|
||||
#define MCF_FBCS_CSCR_SWSEN (0x800000)
|
||||
#define MCF_FBCS_CSCR_SWS(x) (((x)&0x3F)<<0x1A)
|
||||
|
||||
|
||||
#endif /* __MCF5475_FBCS_H__ */
|
||||
680
tos/jtagwait/include/MCF5475_FEC.h
Normal file
680
tos/jtagwait/include/MCF5475_FEC.h
Normal file
@@ -0,0 +1,680 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_FEC_H__
|
||||
#define __MCF5475_FEC_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Fast Ethernet Controller(FEC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_FEC0_EIR (*(volatile uint32_t*)(&_MBAR[0x9004]))
|
||||
#define MCF_FEC0_EIMR (*(volatile uint32_t*)(&_MBAR[0x9008]))
|
||||
#define MCF_FEC0_ECR (*(volatile uint32_t*)(&_MBAR[0x9024]))
|
||||
#define MCF_FEC0_MMFR (*(volatile uint32_t*)(&_MBAR[0x9040]))
|
||||
#define MCF_FEC0_MSCR (*(volatile uint32_t*)(&_MBAR[0x9044]))
|
||||
#define MCF_FEC0_MIBC (*(volatile uint32_t*)(&_MBAR[0x9064]))
|
||||
#define MCF_FEC0_RCR (*(volatile uint32_t*)(&_MBAR[0x9084]))
|
||||
#define MCF_FEC0_RHR (*(volatile uint32_t*)(&_MBAR[0x9088]))
|
||||
#define MCF_FEC0_TCR (*(volatile uint32_t*)(&_MBAR[0x90C4]))
|
||||
#define MCF_FEC0_PALR (*(volatile uint32_t*)(&_MBAR[0x90E4]))
|
||||
#define MCF_FEC0_PAHR (*(volatile uint32_t*)(&_MBAR[0x90E8]))
|
||||
#define MCF_FEC0_OPD (*(volatile uint32_t*)(&_MBAR[0x90EC]))
|
||||
#define MCF_FEC0_IAUR (*(volatile uint32_t*)(&_MBAR[0x9118]))
|
||||
#define MCF_FEC0_IALR (*(volatile uint32_t*)(&_MBAR[0x911C]))
|
||||
#define MCF_FEC0_GAUR (*(volatile uint32_t*)(&_MBAR[0x9120]))
|
||||
#define MCF_FEC0_GALR (*(volatile uint32_t*)(&_MBAR[0x9124]))
|
||||
#define MCF_FEC0_FECTFWR (*(volatile uint32_t*)(&_MBAR[0x9144]))
|
||||
#define MCF_FEC0_FECRFDR (*(volatile uint32_t*)(&_MBAR[0x9184]))
|
||||
#define MCF_FEC0_FECRFSR (*(volatile uint32_t*)(&_MBAR[0x9188]))
|
||||
#define MCF_FEC0_FECRFCR (*(volatile uint32_t*)(&_MBAR[0x918C]))
|
||||
#define MCF_FEC0_FECRLRFP (*(volatile uint32_t*)(&_MBAR[0x9190]))
|
||||
#define MCF_FEC0_FECRLWFP (*(volatile uint32_t*)(&_MBAR[0x9194]))
|
||||
#define MCF_FEC0_FECRFAR (*(volatile uint32_t*)(&_MBAR[0x9198]))
|
||||
#define MCF_FEC0_FECRFRP (*(volatile uint32_t*)(&_MBAR[0x919C]))
|
||||
#define MCF_FEC0_FECRFWP (*(volatile uint32_t*)(&_MBAR[0x91A0]))
|
||||
#define MCF_FEC0_FECTFDR (*(volatile uint32_t*)(&_MBAR[0x91A4]))
|
||||
#define MCF_FEC0_FECTFSR (*(volatile uint32_t*)(&_MBAR[0x91A8]))
|
||||
#define MCF_FEC0_FECTFCR (*(volatile uint32_t*)(&_MBAR[0x91AC]))
|
||||
#define MCF_FEC0_FECTLRFP (*(volatile uint32_t*)(&_MBAR[0x91B0]))
|
||||
#define MCF_FEC0_FECTLWFP (*(volatile uint32_t*)(&_MBAR[0x91B4]))
|
||||
#define MCF_FEC0_FECTFAR (*(volatile uint32_t*)(&_MBAR[0x91B8]))
|
||||
#define MCF_FEC0_FECTFRP (*(volatile uint32_t*)(&_MBAR[0x91BC]))
|
||||
#define MCF_FEC0_FECTFWP (*(volatile uint32_t*)(&_MBAR[0x91C0]))
|
||||
#define MCF_FEC0_FECFRST (*(volatile uint32_t*)(&_MBAR[0x91C4]))
|
||||
#define MCF_FEC0_FECCTCWR (*(volatile uint32_t*)(&_MBAR[0x91C8]))
|
||||
#define MCF_FEC0_RMON_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9200]))
|
||||
#define MCF_FEC0_RMON_T_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9204]))
|
||||
#define MCF_FEC0_RMON_T_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9208]))
|
||||
#define MCF_FEC0_RMON_T_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x920C]))
|
||||
#define MCF_FEC0_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9210]))
|
||||
#define MCF_FEC0_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9214]))
|
||||
#define MCF_FEC0_RMON_T_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9218]))
|
||||
#define MCF_FEC0_RMON_T_FRAG (*(volatile uint32_t*)(&_MBAR[0x921C]))
|
||||
#define MCF_FEC0_RMON_T_JAB (*(volatile uint32_t*)(&_MBAR[0x9220]))
|
||||
#define MCF_FEC0_RMON_T_COL (*(volatile uint32_t*)(&_MBAR[0x9224]))
|
||||
#define MCF_FEC0_RMON_T_P64 (*(volatile uint32_t*)(&_MBAR[0x9228]))
|
||||
#define MCF_FEC0_RMON_T_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x922C]))
|
||||
#define MCF_FEC0_RMON_T_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9230]))
|
||||
#define MCF_FEC0_RMON_T_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9234]))
|
||||
#define MCF_FEC0_RMON_T_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9238]))
|
||||
#define MCF_FEC0_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x923C]))
|
||||
#define MCF_FEC0_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9240]))
|
||||
#define MCF_FEC0_RMON_T_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9244]))
|
||||
#define MCF_FEC0_IEEE_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9248]))
|
||||
#define MCF_FEC0_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x924C]))
|
||||
#define MCF_FEC0_IEEE_T_1COL (*(volatile uint32_t*)(&_MBAR[0x9250]))
|
||||
#define MCF_FEC0_IEEE_T_MCOL (*(volatile uint32_t*)(&_MBAR[0x9254]))
|
||||
#define MCF_FEC0_IEEE_T_DEF (*(volatile uint32_t*)(&_MBAR[0x9258]))
|
||||
#define MCF_FEC0_IEEE_T_LCOL (*(volatile uint32_t*)(&_MBAR[0x925C]))
|
||||
#define MCF_FEC0_IEEE_T_EXCOL (*(volatile uint32_t*)(&_MBAR[0x9260]))
|
||||
#define MCF_FEC0_IEEE_T_MACERR (*(volatile uint32_t*)(&_MBAR[0x9264]))
|
||||
#define MCF_FEC0_IEEE_T_CSERR (*(volatile uint32_t*)(&_MBAR[0x9268]))
|
||||
#define MCF_FEC0_IEEE_T_SQE (*(volatile uint32_t*)(&_MBAR[0x926C]))
|
||||
#define MCF_FEC0_IEEE_T_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9270]))
|
||||
#define MCF_FEC0_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9274]))
|
||||
#define MCF_FEC0_RMON_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9280]))
|
||||
#define MCF_FEC0_RMON_R_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9284]))
|
||||
#define MCF_FEC0_RMON_R_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9288]))
|
||||
#define MCF_FEC0_RMON_R_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x928C]))
|
||||
#define MCF_FEC0_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9290]))
|
||||
#define MCF_FEC0_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9294]))
|
||||
#define MCF_FEC0_RMON_R_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9298]))
|
||||
#define MCF_FEC0_RMON_R_FRAG (*(volatile uint32_t*)(&_MBAR[0x929C]))
|
||||
#define MCF_FEC0_RMON_R_JAB (*(volatile uint32_t*)(&_MBAR[0x92A0]))
|
||||
#define MCF_FEC0_RMON_R_RESVD_0 (*(volatile uint32_t*)(&_MBAR[0x92A4]))
|
||||
#define MCF_FEC0_RMON_R_P64 (*(volatile uint32_t*)(&_MBAR[0x92A8]))
|
||||
#define MCF_FEC0_RMON_R_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x92AC]))
|
||||
#define MCF_FEC0_RMON_R_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x92B0]))
|
||||
#define MCF_FEC0_RMON_R_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x92B4]))
|
||||
#define MCF_FEC0_RMON_R_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x92B8]))
|
||||
#define MCF_FEC0_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x92BC]))
|
||||
#define MCF_FEC0_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x92C0]))
|
||||
#define MCF_FEC0_RMON_R_OCTETS (*(volatile uint32_t*)(&_MBAR[0x92C4]))
|
||||
#define MCF_FEC0_IEEE_R_DROP (*(volatile uint32_t*)(&_MBAR[0x92C8]))
|
||||
#define MCF_FEC0_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x92CC]))
|
||||
#define MCF_FEC0_IEEE_R_CRC (*(volatile uint32_t*)(&_MBAR[0x92D0]))
|
||||
#define MCF_FEC0_IEEE_R_ALIGN (*(volatile uint32_t*)(&_MBAR[0x92D4]))
|
||||
#define MCF_FEC0_IEEE_R_MACERR (*(volatile uint32_t*)(&_MBAR[0x92D8]))
|
||||
#define MCF_FEC0_IEEE_R_FDXFC (*(volatile uint32_t*)(&_MBAR[0x92DC]))
|
||||
#define MCF_FEC0_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x92E0]))
|
||||
|
||||
#define MCF_FEC1_EIR (*(volatile uint32_t*)(&_MBAR[0x9804]))
|
||||
#define MCF_FEC1_EIMR (*(volatile uint32_t*)(&_MBAR[0x9808]))
|
||||
#define MCF_FEC1_ECR (*(volatile uint32_t*)(&_MBAR[0x9824]))
|
||||
#define MCF_FEC1_MMFR (*(volatile uint32_t*)(&_MBAR[0x9840]))
|
||||
#define MCF_FEC1_MSCR (*(volatile uint32_t*)(&_MBAR[0x9844]))
|
||||
#define MCF_FEC1_MIBC (*(volatile uint32_t*)(&_MBAR[0x9864]))
|
||||
#define MCF_FEC1_RCR (*(volatile uint32_t*)(&_MBAR[0x9884]))
|
||||
#define MCF_FEC1_RHR (*(volatile uint32_t*)(&_MBAR[0x9888]))
|
||||
#define MCF_FEC1_TCR (*(volatile uint32_t*)(&_MBAR[0x98C4]))
|
||||
#define MCF_FEC1_PALR (*(volatile uint32_t*)(&_MBAR[0x98E4]))
|
||||
#define MCF_FEC1_PAHR (*(volatile uint32_t*)(&_MBAR[0x98E8]))
|
||||
#define MCF_FEC1_OPD (*(volatile uint32_t*)(&_MBAR[0x98EC]))
|
||||
#define MCF_FEC1_IAUR (*(volatile uint32_t*)(&_MBAR[0x9918]))
|
||||
#define MCF_FEC1_IALR (*(volatile uint32_t*)(&_MBAR[0x991C]))
|
||||
#define MCF_FEC1_GAUR (*(volatile uint32_t*)(&_MBAR[0x9920]))
|
||||
#define MCF_FEC1_GALR (*(volatile uint32_t*)(&_MBAR[0x9924]))
|
||||
#define MCF_FEC1_FECTFWR (*(volatile uint32_t*)(&_MBAR[0x9944]))
|
||||
#define MCF_FEC1_FECRFDR (*(volatile uint32_t*)(&_MBAR[0x9984]))
|
||||
#define MCF_FEC1_FECRFSR (*(volatile uint32_t*)(&_MBAR[0x9988]))
|
||||
#define MCF_FEC1_FECRFCR (*(volatile uint32_t*)(&_MBAR[0x998C]))
|
||||
#define MCF_FEC1_FECRLRFP (*(volatile uint32_t*)(&_MBAR[0x9990]))
|
||||
#define MCF_FEC1_FECRLWFP (*(volatile uint32_t*)(&_MBAR[0x9994]))
|
||||
#define MCF_FEC1_FECRFAR (*(volatile uint32_t*)(&_MBAR[0x9998]))
|
||||
#define MCF_FEC1_FECRFRP (*(volatile uint32_t*)(&_MBAR[0x999C]))
|
||||
#define MCF_FEC1_FECRFWP (*(volatile uint32_t*)(&_MBAR[0x99A0]))
|
||||
#define MCF_FEC1_FECTFDR (*(volatile uint32_t*)(&_MBAR[0x99A4]))
|
||||
#define MCF_FEC1_FECTFSR (*(volatile uint32_t*)(&_MBAR[0x99A8]))
|
||||
#define MCF_FEC1_FECTFCR (*(volatile uint32_t*)(&_MBAR[0x99AC]))
|
||||
#define MCF_FEC1_FECTLRFP (*(volatile uint32_t*)(&_MBAR[0x99B0]))
|
||||
#define MCF_FEC1_FECTLWFP (*(volatile uint32_t*)(&_MBAR[0x99B4]))
|
||||
#define MCF_FEC1_FECTFAR (*(volatile uint32_t*)(&_MBAR[0x99B8]))
|
||||
#define MCF_FEC1_FECTFRP (*(volatile uint32_t*)(&_MBAR[0x99BC]))
|
||||
#define MCF_FEC1_FECTFWP (*(volatile uint32_t*)(&_MBAR[0x99C0]))
|
||||
#define MCF_FEC1_FECFRST (*(volatile uint32_t*)(&_MBAR[0x99C4]))
|
||||
#define MCF_FEC1_FECCTCWR (*(volatile uint32_t*)(&_MBAR[0x99C8]))
|
||||
#define MCF_FEC1_RMON_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9A00]))
|
||||
#define MCF_FEC1_RMON_T_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9A04]))
|
||||
#define MCF_FEC1_RMON_T_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A08]))
|
||||
#define MCF_FEC1_RMON_T_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A0C]))
|
||||
#define MCF_FEC1_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9A10]))
|
||||
#define MCF_FEC1_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A14]))
|
||||
#define MCF_FEC1_RMON_T_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A18]))
|
||||
#define MCF_FEC1_RMON_T_FRAG (*(volatile uint32_t*)(&_MBAR[0x9A1C]))
|
||||
#define MCF_FEC1_RMON_T_JAB (*(volatile uint32_t*)(&_MBAR[0x9A20]))
|
||||
#define MCF_FEC1_RMON_T_COL (*(volatile uint32_t*)(&_MBAR[0x9A24]))
|
||||
#define MCF_FEC1_RMON_T_P64 (*(volatile uint32_t*)(&_MBAR[0x9A28]))
|
||||
#define MCF_FEC1_RMON_T_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x9A2C]))
|
||||
#define MCF_FEC1_RMON_T_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9A30]))
|
||||
#define MCF_FEC1_RMON_T_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9A34]))
|
||||
#define MCF_FEC1_RMON_T_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9A38]))
|
||||
#define MCF_FEC1_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x9A3C]))
|
||||
#define MCF_FEC1_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9A40]))
|
||||
#define MCF_FEC1_RMON_T_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9A44]))
|
||||
#define MCF_FEC1_IEEE_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9A48]))
|
||||
#define MCF_FEC1_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x9A4C]))
|
||||
#define MCF_FEC1_IEEE_T_1COL (*(volatile uint32_t*)(&_MBAR[0x9A50]))
|
||||
#define MCF_FEC1_IEEE_T_MCOL (*(volatile uint32_t*)(&_MBAR[0x9A54]))
|
||||
#define MCF_FEC1_IEEE_T_DEF (*(volatile uint32_t*)(&_MBAR[0x9A58]))
|
||||
#define MCF_FEC1_IEEE_T_LCOL (*(volatile uint32_t*)(&_MBAR[0x9A5C]))
|
||||
#define MCF_FEC1_IEEE_T_EXCOL (*(volatile uint32_t*)(&_MBAR[0x9A60]))
|
||||
#define MCF_FEC1_IEEE_T_MACERR (*(volatile uint32_t*)(&_MBAR[0x9A64]))
|
||||
#define MCF_FEC1_IEEE_T_CSERR (*(volatile uint32_t*)(&_MBAR[0x9A68]))
|
||||
#define MCF_FEC1_IEEE_T_SQE (*(volatile uint32_t*)(&_MBAR[0x9A6C]))
|
||||
#define MCF_FEC1_IEEE_T_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9A70]))
|
||||
#define MCF_FEC1_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9A74]))
|
||||
#define MCF_FEC1_RMON_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9A80]))
|
||||
#define MCF_FEC1_RMON_R_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9A84]))
|
||||
#define MCF_FEC1_RMON_R_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A88]))
|
||||
#define MCF_FEC1_RMON_R_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A8C]))
|
||||
#define MCF_FEC1_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9A90]))
|
||||
#define MCF_FEC1_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A94]))
|
||||
#define MCF_FEC1_RMON_R_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A98]))
|
||||
#define MCF_FEC1_RMON_R_FRAG (*(volatile uint32_t*)(&_MBAR[0x9A9C]))
|
||||
#define MCF_FEC1_RMON_R_JAB (*(volatile uint32_t*)(&_MBAR[0x9AA0]))
|
||||
#define MCF_FEC1_RMON_R_RESVD_0 (*(volatile uint32_t*)(&_MBAR[0x9AA4]))
|
||||
#define MCF_FEC1_RMON_R_P64 (*(volatile uint32_t*)(&_MBAR[0x9AA8]))
|
||||
#define MCF_FEC1_RMON_R_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x9AAC]))
|
||||
#define MCF_FEC1_RMON_R_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9AB0]))
|
||||
#define MCF_FEC1_RMON_R_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9AB4]))
|
||||
#define MCF_FEC1_RMON_R_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9AB8]))
|
||||
#define MCF_FEC1_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x9ABC]))
|
||||
#define MCF_FEC1_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9AC0]))
|
||||
#define MCF_FEC1_RMON_R_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9AC4]))
|
||||
#define MCF_FEC1_IEEE_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9AC8]))
|
||||
#define MCF_FEC1_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x9ACC]))
|
||||
#define MCF_FEC1_IEEE_R_CRC (*(volatile uint32_t*)(&_MBAR[0x9AD0]))
|
||||
#define MCF_FEC1_IEEE_R_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9AD4]))
|
||||
#define MCF_FEC1_IEEE_R_MACERR (*(volatile uint32_t*)(&_MBAR[0x9AD8]))
|
||||
#define MCF_FEC1_IEEE_R_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9ADC]))
|
||||
#define MCF_FEC1_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9AE0]))
|
||||
|
||||
#define MCF_FEC_EIR(x) (*(volatile uint32_t*)(&_MBAR[0x9004 + ((x)*0x800)]))
|
||||
#define MCF_FEC_EIMR(x) (*(volatile uint32_t*)(&_MBAR[0x9008 + ((x)*0x800)]))
|
||||
#define MCF_FEC_ECR(x) (*(volatile uint32_t*)(&_MBAR[0x9024 + ((x)*0x800)]))
|
||||
#define MCF_FEC_MMFR(x) (*(volatile uint32_t*)(&_MBAR[0x9040 + ((x)*0x800)]))
|
||||
#define MCF_FEC_MSCR(x) (*(volatile uint32_t*)(&_MBAR[0x9044 + ((x)*0x800)]))
|
||||
#define MCF_FEC_MIBC(x) (*(volatile uint32_t*)(&_MBAR[0x9064 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RCR(x) (*(volatile uint32_t*)(&_MBAR[0x9084 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RHR(x) (*(volatile uint32_t*)(&_MBAR[0x9088 + ((x)*0x800)]))
|
||||
#define MCF_FEC_TCR(x) (*(volatile uint32_t*)(&_MBAR[0x90C4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_PALR(x) (*(volatile uint32_t*)(&_MBAR[0x90E4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_PAHR(x) (*(volatile uint32_t*)(&_MBAR[0x90E8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_OPD(x) (*(volatile uint32_t*)(&_MBAR[0x90EC + ((x)*0x800)]))
|
||||
#define MCF_FEC_IAUR(x) (*(volatile uint32_t*)(&_MBAR[0x9118 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IALR(x) (*(volatile uint32_t*)(&_MBAR[0x911C + ((x)*0x800)]))
|
||||
#define MCF_FEC_GAUR(x) (*(volatile uint32_t*)(&_MBAR[0x9120 + ((x)*0x800)]))
|
||||
#define MCF_FEC_GALR(x) (*(volatile uint32_t*)(&_MBAR[0x9124 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTFWR(x) (*(volatile uint32_t*)(&_MBAR[0x9144 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x9184 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRFSR(x) (*(volatile uint32_t*)(&_MBAR[0x9188 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRFCR(x) (*(volatile uint32_t*)(&_MBAR[0x918C + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRLRFP(x) (*(volatile uint32_t*)(&_MBAR[0x9190 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRLWFP(x) (*(volatile uint32_t*)(&_MBAR[0x9194 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRFAR(x) (*(volatile uint32_t*)(&_MBAR[0x9198 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRFRP(x) (*(volatile uint32_t*)(&_MBAR[0x919C + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRFWP(x) (*(volatile uint32_t*)(&_MBAR[0x91A0 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x91A4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTFSR(x) (*(volatile uint32_t*)(&_MBAR[0x91A8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTFCR(x) (*(volatile uint32_t*)(&_MBAR[0x91AC + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTLRFP(x) (*(volatile uint32_t*)(&_MBAR[0x91B0 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTLWFP(x) (*(volatile uint32_t*)(&_MBAR[0x91B4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTFAR(x) (*(volatile uint32_t*)(&_MBAR[0x91B8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTFRP(x) (*(volatile uint32_t*)(&_MBAR[0x91BC + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTFWP(x) (*(volatile uint32_t*)(&_MBAR[0x91C0 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECFRST(x) (*(volatile uint32_t*)(&_MBAR[0x91C4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECCTCWR(x) (*(volatile uint32_t*)(&_MBAR[0x91C8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9200 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_PACKETS(x) (*(volatile uint32_t*)(&_MBAR[0x9204 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_BC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x9208 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_MC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x920C + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x9210 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9214 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_OVERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9218 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_FRAG(x) (*(volatile uint32_t*)(&_MBAR[0x921C + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_JAB(x) (*(volatile uint32_t*)(&_MBAR[0x9220 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_COL(x) (*(volatile uint32_t*)(&_MBAR[0x9224 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_P64(x) (*(volatile uint32_t*)(&_MBAR[0x9228 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_P65TO127(x) (*(volatile uint32_t*)(&_MBAR[0x922C + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_P128TO255(x) (*(volatile uint32_t*)(&_MBAR[0x9230 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_P256TO511(x) (*(volatile uint32_t*)(&_MBAR[0x9234 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_P512TO1023(x) (*(volatile uint32_t*)(&_MBAR[0x9238 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_P1024TO2047(x) (*(volatile uint32_t*)(&_MBAR[0x923C + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_P_GTE2048(x) (*(volatile uint32_t*)(&_MBAR[0x9240 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_OCTETS(x) (*(volatile uint32_t*)(&_MBAR[0x9244 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9248 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(volatile uint32_t*)(&_MBAR[0x924C + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_1COL(x) (*(volatile uint32_t*)(&_MBAR[0x9250 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_MCOL(x) (*(volatile uint32_t*)(&_MBAR[0x9254 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_DEF(x) (*(volatile uint32_t*)(&_MBAR[0x9258 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_LCOL(x) (*(volatile uint32_t*)(&_MBAR[0x925C + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_EXCOL(x) (*(volatile uint32_t*)(&_MBAR[0x9260 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_MACERR(x) (*(volatile uint32_t*)(&_MBAR[0x9264 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_CSERR(x) (*(volatile uint32_t*)(&_MBAR[0x9268 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_SQE(x) (*(volatile uint32_t*)(&_MBAR[0x926C + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_FDXFC(x) (*(volatile uint32_t*)(&_MBAR[0x9270 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(volatile uint32_t*)(&_MBAR[0x9274 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9280 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_PACKETS(x) (*(volatile uint32_t*)(&_MBAR[0x9284 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_BC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x9288 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_MC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x928C + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x9290 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9294 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_OVERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9298 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_FRAG(x) (*(volatile uint32_t*)(&_MBAR[0x929C + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_JAB(x) (*(volatile uint32_t*)(&_MBAR[0x92A0 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_RESVD_0(x) (*(volatile uint32_t*)(&_MBAR[0x92A4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_P64(x) (*(volatile uint32_t*)(&_MBAR[0x92A8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_P65TO127(x) (*(volatile uint32_t*)(&_MBAR[0x92AC + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_P128TO255(x) (*(volatile uint32_t*)(&_MBAR[0x92B0 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_P256TO511(x) (*(volatile uint32_t*)(&_MBAR[0x92B4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_P512TO1023(x) (*(volatile uint32_t*)(&_MBAR[0x92B8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_P1024TO2047(x) (*(volatile uint32_t*)(&_MBAR[0x92BC + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_P_GTE2048(x) (*(volatile uint32_t*)(&_MBAR[0x92C0 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_OCTETS(x) (*(volatile uint32_t*)(&_MBAR[0x92C4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_R_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x92C8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(volatile uint32_t*)(&_MBAR[0x92CC + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_R_CRC(x) (*(volatile uint32_t*)(&_MBAR[0x92D0 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_R_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x92D4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_R_MACERR(x) (*(volatile uint32_t*)(&_MBAR[0x92D8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_R_FDXFC(x) (*(volatile uint32_t*)(&_MBAR[0x92DC + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(volatile uint32_t*)(&_MBAR[0x92E0 + ((x)*0x800)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EIR */
|
||||
#define MCF_FEC_EIR_RFERR (0x20000)
|
||||
#define MCF_FEC_EIR_XFERR (0x40000)
|
||||
#define MCF_FEC_EIR_XFUN (0x80000)
|
||||
#define MCF_FEC_EIR_RL (0x100000)
|
||||
#define MCF_FEC_EIR_LC (0x200000)
|
||||
#define MCF_FEC_EIR_MII (0x800000)
|
||||
#define MCF_FEC_EIR_TXF (0x8000000)
|
||||
#define MCF_FEC_EIR_GRA (0x10000000)
|
||||
#define MCF_FEC_EIR_BABT (0x20000000)
|
||||
#define MCF_FEC_EIR_BABR (0x40000000)
|
||||
#define MCF_FEC_EIR_HBERR (0x80000000)
|
||||
#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EIMR */
|
||||
#define MCF_FEC_EIMR_RFERR (0x20000)
|
||||
#define MCF_FEC_EIMR_XFERR (0x40000)
|
||||
#define MCF_FEC_EIMR_XFUN (0x80000)
|
||||
#define MCF_FEC_EIMR_RL (0x100000)
|
||||
#define MCF_FEC_EIMR_LC (0x200000)
|
||||
#define MCF_FEC_EIMR_MII (0x800000)
|
||||
#define MCF_FEC_EIMR_TXF (0x8000000)
|
||||
#define MCF_FEC_EIMR_GRA (0x10000000)
|
||||
#define MCF_FEC_EIMR_BABT (0x20000000)
|
||||
#define MCF_FEC_EIMR_BABR (0x40000000)
|
||||
#define MCF_FEC_EIMR_HBERR (0x80000000)
|
||||
#define MCF_FEC_EIMR_MASK_ALL (0)
|
||||
#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_ECR */
|
||||
#define MCF_FEC_ECR_RESET (0x1)
|
||||
#define MCF_FEC_ECR_ETHER_EN (0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MMFR */
|
||||
#define MCF_FEC_MMFR_DATA(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_FEC_MMFR_TA(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_FEC_MMFR_TA_10 (0x20000)
|
||||
#define MCF_FEC_MMFR_RA(x) (((x)&0x1F)<<0x12)
|
||||
#define MCF_FEC_MMFR_PA(x) (((x)&0x1F)<<0x17)
|
||||
#define MCF_FEC_MMFR_OP(x) (((x)&0x3)<<0x1C)
|
||||
#define MCF_FEC_MMFR_OP_READ (0x20000000)
|
||||
#define MCF_FEC_MMFR_OP_WRITE (0x10000000)
|
||||
#define MCF_FEC_MMFR_ST(x) (((x)&0x3)<<0x1E)
|
||||
#define MCF_FEC_MMFR_ST_01 (0x40000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MSCR */
|
||||
#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1)
|
||||
#define MCF_FEC_MSCR_DIS_PREAMBLE (0x80)
|
||||
#define MCF_FEC_MSCR_MII_SPEED_133 (0x1B<<0x1)
|
||||
#define MCF_FEC_MSCR_MII_SPEED_120 (0x18<<0x1)
|
||||
#define MCF_FEC_MSCR_MII_SPEED_66 (0xE<<0x1)
|
||||
#define MCF_FEC_MSCR_MII_SPEED_60 (0xC<<0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MIBC */
|
||||
#define MCF_FEC_MIBC_MIB_IDLE (0x40000000)
|
||||
#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RCR */
|
||||
#define MCF_FEC_RCR_LOOP (0x1)
|
||||
#define MCF_FEC_RCR_DRT (0x2)
|
||||
#define MCF_FEC_RCR_MII_MODE (0x4)
|
||||
#define MCF_FEC_RCR_PROM (0x8)
|
||||
#define MCF_FEC_RCR_BC_REJ (0x10)
|
||||
#define MCF_FEC_RCR_FCE (0x20)
|
||||
#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RHR */
|
||||
#define MCF_FEC_RHR_HASH(x) (((x)&0x3F)<<0x18)
|
||||
#define MCF_FEC_RHR_MULTCAST (0x40000000)
|
||||
#define MCF_FEC_RHR_FCE (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_TCR */
|
||||
#define MCF_FEC_TCR_GTS (0x1)
|
||||
#define MCF_FEC_TCR_HBC (0x2)
|
||||
#define MCF_FEC_TCR_FDEN (0x4)
|
||||
#define MCF_FEC_TCR_TFC_PAUSE (0x8)
|
||||
#define MCF_FEC_TCR_RFC_PAUSE (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_PALR */
|
||||
#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_PAHR */
|
||||
#define MCF_FEC_PAHR_TYPE(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_FEC_PAHR_PADDR2(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_OPD */
|
||||
#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_FEC_OPD_OPCODE(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IAUR */
|
||||
#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IALR */
|
||||
#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_GAUR */
|
||||
#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_GALR */
|
||||
#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTFWR */
|
||||
#define MCF_FEC_FECTFWR_X_WMRK(x) (((x)&0xF)<<0)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_64 (0)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_128 (0x1)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_192 (0x2)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_256 (0x3)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_320 (0x4)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_384 (0x5)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_448 (0x6)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_512 (0x7)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_576 (0x8)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_640 (0x9)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_704 (0xA)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_768 (0xB)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_832 (0xC)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_896 (0xD)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_960 (0xE)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_1024 (0xF)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRFDR */
|
||||
#define MCF_FEC_FECRFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRFSR */
|
||||
#define MCF_FEC_FECRFSR_EMT (0x10000)
|
||||
#define MCF_FEC_FECRFSR_ALARM (0x20000)
|
||||
#define MCF_FEC_FECRFSR_FU (0x40000)
|
||||
#define MCF_FEC_FECRFSR_FRMRDY (0x80000)
|
||||
#define MCF_FEC_FECRFSR_OF (0x100000)
|
||||
#define MCF_FEC_FECRFSR_UF (0x200000)
|
||||
#define MCF_FEC_FECRFSR_RXW (0x400000)
|
||||
#define MCF_FEC_FECRFSR_FAE (0x800000)
|
||||
#define MCF_FEC_FECRFSR_FRM(x) (((x)&0xF)<<0x18)
|
||||
#define MCF_FEC_FECRFSR_IP (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRFCR */
|
||||
#define MCF_FEC_FECRFCR_COUNTER(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_FEC_FECRFCR_OF_MSK (0x80000)
|
||||
#define MCF_FEC_FECRFCR_UF_MSK (0x100000)
|
||||
#define MCF_FEC_FECRFCR_RXW_MSK (0x200000)
|
||||
#define MCF_FEC_FECRFCR_FAE_MSK (0x400000)
|
||||
#define MCF_FEC_FECRFCR_IP_MSK (0x800000)
|
||||
#define MCF_FEC_FECRFCR_GR(x) (((x)&0x7)<<0x18)
|
||||
#define MCF_FEC_FECRFCR_FRMEN (0x8000000)
|
||||
#define MCF_FEC_FECRFCR_TIMER (0x10000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRLRFP */
|
||||
#define MCF_FEC_FECRLRFP_LRFP(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRLWFP */
|
||||
#define MCF_FEC_FECRLWFP_LWFP(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRFAR */
|
||||
#define MCF_FEC_FECRFAR_ALARM(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRFRP */
|
||||
#define MCF_FEC_FECRFRP_READ(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRFWP */
|
||||
#define MCF_FEC_FECRFWP_WRITE(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTFDR */
|
||||
#define MCF_FEC_FECTFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTFSR */
|
||||
#define MCF_FEC_FECTFSR_EMT (0x10000)
|
||||
#define MCF_FEC_FECTFSR_ALARM (0x20000)
|
||||
#define MCF_FEC_FECTFSR_FU (0x40000)
|
||||
#define MCF_FEC_FECTFSR_FRMRDY (0x80000)
|
||||
#define MCF_FEC_FECTFSR_OF (0x100000)
|
||||
#define MCF_FEC_FECTFSR_UF (0x200000)
|
||||
#define MCF_FEC_FECTFSR_FAE (0x800000)
|
||||
#define MCF_FEC_FECTFSR_FRM(x) (((x)&0xF)<<0x18)
|
||||
#define MCF_FEC_FECTFSR_TXW (0x40000000)
|
||||
#define MCF_FEC_FECTFSR_IP (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTFCR */
|
||||
#define MCF_FEC_FECTFCR_RESERVED (0x200000)
|
||||
#define MCF_FEC_FECTFCR_COUNTER(x) (((x)&0xFFFF)<<0|0x200000)
|
||||
#define MCF_FEC_FECTFCR_TXW_MASK (0x240000)
|
||||
#define MCF_FEC_FECTFCR_OF_MSK (0x280000)
|
||||
#define MCF_FEC_FECTFCR_UF_MSK (0x300000)
|
||||
#define MCF_FEC_FECTFCR_FAE_MSK (0x600000)
|
||||
#define MCF_FEC_FECTFCR_IP_MSK (0xA00000)
|
||||
#define MCF_FEC_FECTFCR_GR(x) (((x)&0x7)<<0x18|0x200000)
|
||||
#define MCF_FEC_FECTFCR_FRMEN (0x8200000)
|
||||
#define MCF_FEC_FECTFCR_TIMER (0x10200000)
|
||||
#define MCF_FEC_FECTFCR_WFR (0x20200000)
|
||||
#define MCF_FEC_FECTFCR_WCTL (0x40200000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTLRFP */
|
||||
#define MCF_FEC_FECTLRFP_LRFP(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTLWFP */
|
||||
#define MCF_FEC_FECTLWFP_LWFP(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTFAR */
|
||||
#define MCF_FEC_FECTFAR_ALARM(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTFRP */
|
||||
#define MCF_FEC_FECTFRP_READ(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTFWP */
|
||||
#define MCF_FEC_FECTFWP_WRITE(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECFRST */
|
||||
#define MCF_FEC_FECFRST_RST_CTL (0x1000000)
|
||||
#define MCF_FEC_FECFRST_SW_RST (0x2000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECCTCWR */
|
||||
#define MCF_FEC_FECCTCWR_TFCW (0x1000000)
|
||||
#define MCF_FEC_FECCTCWR_CRC (0x2000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */
|
||||
#define MCF_FEC_RMON_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */
|
||||
#define MCF_FEC_RMON_T_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */
|
||||
#define MCF_FEC_RMON_T_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */
|
||||
#define MCF_FEC_RMON_T_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */
|
||||
#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */
|
||||
#define MCF_FEC_RMON_T_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */
|
||||
#define MCF_FEC_RMON_T_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */
|
||||
#define MCF_FEC_RMON_T_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */
|
||||
#define MCF_FEC_RMON_T_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_COL */
|
||||
#define MCF_FEC_RMON_T_COL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */
|
||||
#define MCF_FEC_RMON_T_P64_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */
|
||||
#define MCF_FEC_RMON_T_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */
|
||||
#define MCF_FEC_RMON_T_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */
|
||||
#define MCF_FEC_RMON_T_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */
|
||||
#define MCF_FEC_RMON_T_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */
|
||||
#define MCF_FEC_RMON_T_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */
|
||||
#define MCF_FEC_RMON_T_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */
|
||||
#define MCF_FEC_RMON_T_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */
|
||||
#define MCF_FEC_IEEE_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */
|
||||
#define MCF_FEC_IEEE_T_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */
|
||||
#define MCF_FEC_IEEE_T_1COL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */
|
||||
#define MCF_FEC_IEEE_T_MCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */
|
||||
#define MCF_FEC_IEEE_T_DEF_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */
|
||||
#define MCF_FEC_IEEE_T_LCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */
|
||||
#define MCF_FEC_IEEE_T_EXCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */
|
||||
#define MCF_FEC_IEEE_T_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */
|
||||
#define MCF_FEC_IEEE_T_CSERR_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */
|
||||
#define MCF_FEC_IEEE_T_SQE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */
|
||||
#define MCF_FEC_IEEE_T_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */
|
||||
#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_DROP */
|
||||
#define MCF_FEC_RMON_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */
|
||||
#define MCF_FEC_RMON_R_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */
|
||||
#define MCF_FEC_RMON_R_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */
|
||||
#define MCF_FEC_RMON_R_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */
|
||||
#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */
|
||||
#define MCF_FEC_RMON_R_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */
|
||||
#define MCF_FEC_RMON_R_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */
|
||||
#define MCF_FEC_RMON_R_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */
|
||||
#define MCF_FEC_RMON_R_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */
|
||||
#define MCF_FEC_RMON_R_RESVD_0_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */
|
||||
#define MCF_FEC_RMON_R_P64_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */
|
||||
#define MCF_FEC_RMON_R_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */
|
||||
#define MCF_FEC_RMON_R_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */
|
||||
#define MCF_FEC_RMON_R_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */
|
||||
#define MCF_FEC_RMON_R_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */
|
||||
#define MCF_FEC_RMON_R_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */
|
||||
#define MCF_FEC_RMON_R_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */
|
||||
#define MCF_FEC_RMON_R_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */
|
||||
#define MCF_FEC_IEEE_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */
|
||||
#define MCF_FEC_IEEE_R_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */
|
||||
#define MCF_FEC_IEEE_R_CRC_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */
|
||||
#define MCF_FEC_IEEE_R_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */
|
||||
#define MCF_FEC_IEEE_R_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */
|
||||
#define MCF_FEC_IEEE_R_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */
|
||||
#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF5475_FEC_H__ */
|
||||
543
tos/jtagwait/include/MCF5475_GPIO.h
Normal file
543
tos/jtagwait/include/MCF5475_GPIO.h
Normal file
@@ -0,0 +1,543 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_GPIO_H__
|
||||
#define __MCF5475_GPIO_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* General Purpose I/O (GPIO)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_GPIO_PODR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA00]))
|
||||
#define MCF_GPIO_PDDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA10]))
|
||||
#define MCF_GPIO_PPDSDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA20]))
|
||||
#define MCF_GPIO_PCLRR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA30]))
|
||||
|
||||
#define MCF_GPIO_PODR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA01]))
|
||||
#define MCF_GPIO_PDDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA11]))
|
||||
#define MCF_GPIO_PPDSDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA21]))
|
||||
#define MCF_GPIO_PCLRR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA31]))
|
||||
|
||||
#define MCF_GPIO_PODR_DMA (*(volatile uint8_t *)(&_MBAR[0xA02]))
|
||||
#define MCF_GPIO_PDDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA12]))
|
||||
#define MCF_GPIO_PPDSDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA22]))
|
||||
#define MCF_GPIO_PCLRR_DMA (*(volatile uint8_t *)(&_MBAR[0xA32]))
|
||||
|
||||
#define MCF_GPIO_PODR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA04]))
|
||||
#define MCF_GPIO_PDDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA14]))
|
||||
#define MCF_GPIO_PPDSDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA24]))
|
||||
#define MCF_GPIO_PCLRR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA34]))
|
||||
|
||||
#define MCF_GPIO_PODR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA05]))
|
||||
#define MCF_GPIO_PDDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA15]))
|
||||
#define MCF_GPIO_PPDSDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA25]))
|
||||
#define MCF_GPIO_PCLRR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA35]))
|
||||
|
||||
#define MCF_GPIO_PODR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA06]))
|
||||
#define MCF_GPIO_PDDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA16]))
|
||||
#define MCF_GPIO_PPDSDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA26]))
|
||||
#define MCF_GPIO_PCLRR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA36]))
|
||||
|
||||
#define MCF_GPIO_PODR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA07]))
|
||||
#define MCF_GPIO_PDDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA17]))
|
||||
#define MCF_GPIO_PPDSDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA27]))
|
||||
#define MCF_GPIO_PCLRR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA37]))
|
||||
|
||||
#define MCF_GPIO_PODR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA08]))
|
||||
#define MCF_GPIO_PDDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA18]))
|
||||
#define MCF_GPIO_PPDSDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA28]))
|
||||
#define MCF_GPIO_PCLRR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA38]))
|
||||
|
||||
#define MCF_GPIO_PODR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA09]))
|
||||
#define MCF_GPIO_PDDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA19]))
|
||||
#define MCF_GPIO_PPDSDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA29]))
|
||||
#define MCF_GPIO_PCLRR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA39]))
|
||||
|
||||
#define MCF_GPIO_PODR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA0A]))
|
||||
#define MCF_GPIO_PDDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA1A]))
|
||||
#define MCF_GPIO_PPDSDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA2A]))
|
||||
#define MCF_GPIO_PCLRR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA3A]))
|
||||
|
||||
#define MCF_GPIO2_PODR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA0C]))
|
||||
#define MCF_GPIO2_PDDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA1C]))
|
||||
#define MCF_GPIO2_PPDSDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA2C]))
|
||||
#define MCF_GPIO2_PCLRR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA3C]))
|
||||
|
||||
#define MCF_GPIO0_PODR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA0D]))
|
||||
#define MCF_GPIO0_PDDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA1D]))
|
||||
#define MCF_GPIO0_PPDSDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA2D]))
|
||||
#define MCF_GPIO0_PCLRR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA3D]))
|
||||
|
||||
#define MCF_GPIO_PODR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA0E]))
|
||||
#define MCF_GPIO_PDDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA1E]))
|
||||
#define MCF_GPIO_PPDSDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA2E]))
|
||||
#define MCF_GPIO_PCLRR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA3E]))
|
||||
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x1)
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x2)
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x4)
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x8)
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10)
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20)
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40)
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x1)
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x2)
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x4)
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x8)
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10)
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20)
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40)
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */
|
||||
#define MCF_GPIO_PODR_FBCS_PODR_FBCS1 (0x2)
|
||||
#define MCF_GPIO_PODR_FBCS_PODR_FBCS2 (0x4)
|
||||
#define MCF_GPIO_PODR_FBCS_PODR_FBCS3 (0x8)
|
||||
#define MCF_GPIO_PODR_FBCS_PODR_FBCS4 (0x10)
|
||||
#define MCF_GPIO_PODR_FBCS_PODR_FBCS5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */
|
||||
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x2)
|
||||
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x4)
|
||||
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x8)
|
||||
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10)
|
||||
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */
|
||||
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */
|
||||
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_DMA */
|
||||
#define MCF_GPIO_PODR_DMA_PODR_DMA0 (0x1)
|
||||
#define MCF_GPIO_PODR_DMA_PODR_DMA1 (0x2)
|
||||
#define MCF_GPIO_PODR_DMA_PODR_DMA2 (0x4)
|
||||
#define MCF_GPIO_PODR_DMA_PODR_DMA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */
|
||||
#define MCF_GPIO_PDDR_DMA_PDDR_DMA0 (0x1)
|
||||
#define MCF_GPIO_PDDR_DMA_PDDR_DMA1 (0x2)
|
||||
#define MCF_GPIO_PDDR_DMA_PDDR_DMA2 (0x4)
|
||||
#define MCF_GPIO_PDDR_DMA_PDDR_DMA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */
|
||||
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */
|
||||
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x1)
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x2)
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x4)
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x8)
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10)
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20)
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40)
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x1)
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x2)
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x4)
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x8)
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10)
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20)
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40)
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x1)
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x2)
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x4)
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x8)
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10)
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20)
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40)
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x1)
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x2)
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x4)
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x8)
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10)
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20)
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40)
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x1)
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x2)
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x4)
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x8)
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10)
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20)
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40)
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x1)
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x2)
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x4)
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x8)
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10)
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20)
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40)
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x1)
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x2)
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x4)
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x8)
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10)
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20)
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40)
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x1)
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x2)
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x4)
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x8)
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10)
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20)
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40)
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
|
||||
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x1)
|
||||
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x2)
|
||||
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x4)
|
||||
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
|
||||
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x1)
|
||||
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x2)
|
||||
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x4)
|
||||
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
|
||||
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
|
||||
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */
|
||||
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x1)
|
||||
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x2)
|
||||
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x4)
|
||||
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x8)
|
||||
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */
|
||||
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x1)
|
||||
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x2)
|
||||
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x4)
|
||||
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x8)
|
||||
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */
|
||||
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */
|
||||
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */
|
||||
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x1)
|
||||
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x2)
|
||||
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x4)
|
||||
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x8)
|
||||
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */
|
||||
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x1)
|
||||
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x2)
|
||||
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x4)
|
||||
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x8)
|
||||
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */
|
||||
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */
|
||||
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1)
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2)
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4)
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8)
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10)
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20)
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40)
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1)
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2)
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4)
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8)
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10)
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20)
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40)
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1)
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2)
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4)
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8)
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10)
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20)
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40)
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1)
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2)
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4)
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8)
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10)
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20)
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40)
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1)
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2)
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4)
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8)
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10)
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20)
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40)
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1)
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2)
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4)
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8)
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10)
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20)
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40)
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */
|
||||
#define MCF_GPIO_PODR_DSPI_PODR_DSPI0 (0x1)
|
||||
#define MCF_GPIO_PODR_DSPI_PODR_DSPI1 (0x2)
|
||||
#define MCF_GPIO_PODR_DSPI_PODR_DSPI2 (0x4)
|
||||
#define MCF_GPIO_PODR_DSPI_PODR_DSPI3 (0x8)
|
||||
#define MCF_GPIO_PODR_DSPI_PODR_DSPI4 (0x10)
|
||||
#define MCF_GPIO_PODR_DSPI_PODR_DSPI5 (0x20)
|
||||
#define MCF_GPIO_PODR_DSPI_PODR_DSPI6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */
|
||||
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x1)
|
||||
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x2)
|
||||
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x4)
|
||||
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x8)
|
||||
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10)
|
||||
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20)
|
||||
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */
|
||||
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */
|
||||
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40)
|
||||
|
||||
|
||||
#endif /* __MCF5475_GPIO_H__ */
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user