diff --git a/BaS_gcc.config b/BaS_gcc.config new file mode 100644 index 0000000..146302d --- /dev/null +++ b/BaS_gcc.config @@ -0,0 +1,3 @@ +// Add predefined macros for your project here. For example: +// #define THE_ANSWER 42 +#define MACHINE_FIREBEE diff --git a/BaS_gcc.creator b/BaS_gcc.creator new file mode 100644 index 0000000..e94cbbd --- /dev/null +++ b/BaS_gcc.creator @@ -0,0 +1 @@ +[General] diff --git a/BaS_gcc.files b/BaS_gcc.files new file mode 100644 index 0000000..08f44bd --- /dev/null +++ b/BaS_gcc.files @@ -0,0 +1,397 @@ +dma/dma.c +dma/MCD_dmaApi.c +dma/MCD_tasks.c +dma/MCD_tasksInit.c +exe/basflash.c +exe/basflash_start.c +firebee/bas.elf +firebee/bas.lk +firebee/bas.map +firebee/bas.s19 +firebee/basflash.elf +firebee/basflash.lk +firebee/basflash.map +firebee/basflash.s19 +firebee/depend +firebee/libbas.a +firebee/ram.elf +firebee/ram.lk +firebee/ram.map +firebee/ram.s19 +flash/flash.c +flash/s19reader.c +flash_scripts/flash_firebee_bas.bdm +flash_scripts/flash_firebee_etos.bdm +flash_scripts/flash_firebee_firetos.bdm +flash_scripts/flash_firebee_fpga.bdm +flash_scripts/flash_m548x_bas.bdm +flash_scripts/flash_m548x_dbug.bdm +flash_scripts/flash_m548x_etos.bdm +flash_scripts/m548xlite_dbug_ram.elf +flash_scripts/m548xlite_dbug_ram.s19 +flash_scripts/run_m548x_dbug.bdm +fs/cc932.c +fs/cc936.c +fs/cc949.c +fs/cc950.c +fs/ccsbcs.c +fs/ff.c +fs/unicode.c +i2c/i2c.c +if/driver_vec.c +include/acia.h +include/am79c874.h +include/arp.h +include/ati_ids.h +include/bas_printf.h +include/bas_string.h +include/bas_types.h +include/bas_utils.h +include/bcm5222.h +include/bootp.h +include/cache.h +include/conout.h +include/debug.h +include/diskio.h +include/dma.h +include/driver_mem.h +include/driver_vec.h +include/edid.h +include/ehci.h +include/eth.h +include/exceptions.h +include/fb.h +include/fec.h +include/fecbd.h +include/ff.h +include/ffconf.h +include/firebee.h +include/font.h +include/i2c-algo-bit.h +include/i2c.h +include/icmp.h +include/ikbd.h +include/interrupts.h +include/ip.h +include/m54455.h +include/m5484l.h +include/MCD_dma.h +include/mcd_initiators.h +include/MCD_progCheck.h +include/MCD_tasksInit.h +include/MCF5475.h +include/MCF5475_CLOCK.h +include/MCF5475_CTM.h +include/MCF5475_DMA.h +include/MCF5475_DSPI.h +include/MCF5475_EPORT.h +include/MCF5475_FBCS.h +include/MCF5475_FEC.h +include/MCF5475_GPIO.h +include/MCF5475_GPT.h +include/MCF5475_I2C.h +include/MCF5475_INTC.h +include/MCF5475_MMU.h +include/MCF5475_PAD.h +include/MCF5475_PCI.h +include/MCF5475_PCIARB.h +include/MCF5475_PSC.h +include/MCF5475_SDRAMC.h +include/MCF5475_SEC.h +include/MCF5475_SIU.h +include/MCF5475_SLT.h +include/MCF5475_SRAM.h +include/MCF5475_USB.h +include/MCF5475_XLB.h +include/mmu.h +include/mod_devicetable.h +include/nbuf.h +include/net.h +include/net_timer.h +include/nif.h +include/ohci.h +include/part.h +include/pci.h +include/pci_errata.h +include/pci_ids.h +include/queue.h +include/radeon_reg.h +include/radeonfb.h +include/s19reader.h +include/screen.h +include/sd_card.h +include/setjmp.h +include/startcf.h +include/sysinit.h +include/tftp.h +include/udp.h +include/usb.h +include/usb_defs.h +include/usb_hub.h +include/user_io.h +include/util.h +include/version.h +include/videl.h +include/video.h +include/wait.h +include/x86emu.h +include/x86emu_regs.h +include/x86pcibios.h +include/xhdi_sd.h +kbd/ikbd.c +m54455/bas.elf +m54455/bas.lk +m54455/bas.map +m54455/bas.s19 +m54455/basflash.elf +m54455/basflash.lk +m54455/basflash.map +m54455/basflash.s19 +m54455/depend +m54455/libbas.a +m54455/ram.elf +m54455/ram.lk +m54455/ram.map +m54455/ram.s19 +m5484lite/bas.elf +m5484lite/bas.lk +m5484lite/bas.map +m5484lite/bas.s19 +m5484lite/basflash.elf +m5484lite/basflash.lk +m5484lite/basflash.map +m5484lite/basflash.s19 +m5484lite/depend +m5484lite/libbas.a +m5484lite/ram.elf +m5484lite/ram.lk +m5484lite/ram.map +m5484lite/ram.s19 +net/am79c874.c +net/arp.c +net/bcm5222.c +net/bootp.c +net/fec.c +net/fecbd.c +net/ip.c +net/nbuf.c +net/net_timer.c +net/nif.c +net/queue.c +net/tftp.c +net/udp.c +nutil/s19header.c +pci/ehci-hcd.c +pci/ohci-hcd.c +pci/pci.c +pci/pci_errata.c +pci/pci_wrappers.S +radeon/i2c-algo-bit.c +radeon/radeon_accel.c +radeon/radeon_base.c +radeon/radeon_cursor.c +radeon/radeon_i2c.c +radeon/radeon_monitor.c +release/firebee/bas.s19 +release/m5484lite/bas.s19 +release/bascook.prg +release/readme.txt +spi/dspi.c +spi/mmc.c +spi/sd_card.c +sys/BaS.c +sys/cache.c +sys/driver_mem.c +sys/exceptions.S +sys/fault_vectors.c +sys/init_fpga.c +sys/interrupts.c +sys/mmu.c +sys/startcf.S +sys/sysinit.c +tos/bascook/sources/bascook.c +tos/bascook/bascook.prg +tos/bascook/depend +tos/bascook/mapfile +tos/fpga_test/m5475/mshort/fpga_test.prg +tos/fpga_test/m5475/fpga_test.prg +tos/fpga_test/sources/fpga_test.c +tos/fpga_test/sources/ser_printf.c +tos/fpga_test/sources/vmem_test.c +tos/fpga_test/depend +tos/fpga_test/mapfile +tos/jtagwait/include/bas_printf.h +tos/jtagwait/include/bas_string.h +tos/jtagwait/include/driver_vec.h +tos/jtagwait/include/MCF5475.h +tos/jtagwait/include/MCF5475_CLOCK.h +tos/jtagwait/include/MCF5475_CTM.h +tos/jtagwait/include/MCF5475_DMA.h +tos/jtagwait/include/MCF5475_DSPI.h +tos/jtagwait/include/MCF5475_EPORT.h +tos/jtagwait/include/MCF5475_FBCS.h +tos/jtagwait/include/MCF5475_FEC.h +tos/jtagwait/include/MCF5475_GPIO.h +tos/jtagwait/include/MCF5475_GPT.h +tos/jtagwait/include/MCF5475_I2C.h +tos/jtagwait/include/MCF5475_INTC.h +tos/jtagwait/include/MCF5475_MMU.h +tos/jtagwait/include/MCF5475_PAD.h +tos/jtagwait/include/MCF5475_PCI.h +tos/jtagwait/include/MCF5475_PCIARB.h +tos/jtagwait/include/MCF5475_PSC.h +tos/jtagwait/include/MCF5475_SDRAMC.h +tos/jtagwait/include/MCF5475_SEC.h +tos/jtagwait/include/MCF5475_SIU.h +tos/jtagwait/include/MCF5475_SLT.h +tos/jtagwait/include/MCF5475_SRAM.h +tos/jtagwait/include/MCF5475_USB.h +tos/jtagwait/include/MCF5475_XLB.h +tos/jtagwait/m5475/mshort/jtagwait.prg +tos/jtagwait/m5475/jtagwait.prg +tos/jtagwait/sources/bas_printf.c +tos/jtagwait/sources/bas_string.c +tos/jtagwait/sources/jtagwait.c +tos/jtagwait/sources/printf_helper.S +tos/jtagwait/depend +tos/jtagwait/mapfile +tos/pci_mem/include/bas_string.h +tos/pci_mem/include/bas_types.h +tos/pci_mem/include/driver_vec.h +tos/pci_mem/include/MCF5475.h +tos/pci_mem/include/MCF5475_CLOCK.h +tos/pci_mem/include/MCF5475_CTM.h +tos/pci_mem/include/MCF5475_DMA.h +tos/pci_mem/include/MCF5475_DSPI.h +tos/pci_mem/include/MCF5475_EPORT.h +tos/pci_mem/include/MCF5475_FBCS.h +tos/pci_mem/include/MCF5475_FEC.h +tos/pci_mem/include/MCF5475_GPIO.h +tos/pci_mem/include/MCF5475_GPT.h +tos/pci_mem/include/MCF5475_I2C.h +tos/pci_mem/include/MCF5475_INTC.h +tos/pci_mem/include/MCF5475_MMU.h +tos/pci_mem/include/MCF5475_PAD.h +tos/pci_mem/include/MCF5475_PCI.h +tos/pci_mem/include/MCF5475_PCIARB.h +tos/pci_mem/include/MCF5475_PSC.h +tos/pci_mem/include/MCF5475_SDRAMC.h +tos/pci_mem/include/MCF5475_SEC.h +tos/pci_mem/include/MCF5475_SIU.h +tos/pci_mem/include/MCF5475_SLT.h +tos/pci_mem/include/MCF5475_SRAM.h +tos/pci_mem/include/MCF5475_USB.h +tos/pci_mem/include/MCF5475_XLB.h +tos/pci_mem/include/pci.h +tos/pci_mem/include/util.h +tos/pci_mem/m5475/mshort/pci_mem.prg +tos/pci_mem/m5475/pci_mem.prg +tos/pci_mem/sources/pci_mem.c +tos/pci_mem/depend +tos/pci_mem/mapfile +tos/pci_test/include/bas_string.h +tos/pci_test/include/bas_types.h +tos/pci_test/include/driver_vec.h +tos/pci_test/include/MCF5475.h +tos/pci_test/include/MCF5475_CLOCK.h +tos/pci_test/include/MCF5475_CTM.h +tos/pci_test/include/MCF5475_DMA.h +tos/pci_test/include/MCF5475_DSPI.h +tos/pci_test/include/MCF5475_EPORT.h +tos/pci_test/include/MCF5475_FBCS.h +tos/pci_test/include/MCF5475_FEC.h +tos/pci_test/include/MCF5475_GPIO.h +tos/pci_test/include/MCF5475_GPT.h +tos/pci_test/include/MCF5475_I2C.h +tos/pci_test/include/MCF5475_INTC.h +tos/pci_test/include/MCF5475_MMU.h +tos/pci_test/include/MCF5475_PAD.h +tos/pci_test/include/MCF5475_PCI.h +tos/pci_test/include/MCF5475_PCIARB.h +tos/pci_test/include/MCF5475_PSC.h +tos/pci_test/include/MCF5475_SDRAMC.h +tos/pci_test/include/MCF5475_SEC.h +tos/pci_test/include/MCF5475_SIU.h +tos/pci_test/include/MCF5475_SLT.h +tos/pci_test/include/MCF5475_SRAM.h +tos/pci_test/include/MCF5475_USB.h +tos/pci_test/include/MCF5475_XLB.h +tos/pci_test/include/pci.h +tos/pci_test/include/util.h +tos/pci_test/m5475/mshort/pci_test.prg +tos/pci_test/m5475/pci_test.prg +tos/pci_test/sources/pci_test.c +tos/pci_test/sources/printf_helper.S +tos/pci_test/depend +tos/pci_test/mapfile +tos/vmem_test/include/bas_printf.h +tos/vmem_test/include/bas_string.h +tos/vmem_test/include/driver_vec.h +tos/vmem_test/include/MCF5475.h +tos/vmem_test/include/MCF5475_CLOCK.h +tos/vmem_test/include/MCF5475_CTM.h +tos/vmem_test/include/MCF5475_DMA.h +tos/vmem_test/include/MCF5475_DSPI.h +tos/vmem_test/include/MCF5475_EPORT.h +tos/vmem_test/include/MCF5475_FBCS.h +tos/vmem_test/include/MCF5475_FEC.h +tos/vmem_test/include/MCF5475_GPIO.h +tos/vmem_test/include/MCF5475_GPT.h +tos/vmem_test/include/MCF5475_I2C.h +tos/vmem_test/include/MCF5475_INTC.h +tos/vmem_test/include/MCF5475_MMU.h +tos/vmem_test/include/MCF5475_PAD.h +tos/vmem_test/include/MCF5475_PCI.h +tos/vmem_test/include/MCF5475_PCIARB.h +tos/vmem_test/include/MCF5475_PSC.h +tos/vmem_test/include/MCF5475_SDRAMC.h +tos/vmem_test/include/MCF5475_SEC.h +tos/vmem_test/include/MCF5475_SIU.h +tos/vmem_test/include/MCF5475_SLT.h +tos/vmem_test/include/MCF5475_SRAM.h +tos/vmem_test/include/MCF5475_USB.h +tos/vmem_test/include/MCF5475_XLB.h +tos/vmem_test/m5475/mshort/vmem_test.prg +tos/vmem_test/m5475/vmem_test.prg +tos/vmem_test/sources/bas_printf.c +tos/vmem_test/sources/bas_string.c +tos/vmem_test/sources/printf_helper.S +tos/vmem_test/sources/vmem_test.c +tos/vmem_test/depend +tos/vmem_test/mapfile +usb/usb.c +usb/usb_hub.c +usb/usb_kbd.c +usb/usb_mouse.c +util/bas_printf.c +util/bas_string.c +util/conout.c +util/libgcc_helper.S +util/setjmp.S +util/wait.c +video/fbmem.c +video/fbmodedb.c +video/fbmon.c +video/fnt_st_8x16.c +video/offscreen.c +video/vdi_fill.c +video/videl.c +video/video.c +x86emu/x86biosemu.c +x86emu/x86emu.c +x86emu/x86emu_util.c +x86emu/x86pcibios.c +xhdi/xhdi_interface.c +xhdi/xhdi_sd.c +xhdi/xhdi_vec.S +bas.lk.in +bas_firebee.bdm +bas_m5484.bdm +basflash.lk.in +check.bdm +COPYING +COPYING.LESSER +Doxyfile +dump.bdm +mcf5474.gdb +memory_map.txt diff --git a/BaS_gcc.includes b/BaS_gcc.includes new file mode 100644 index 0000000..76956f3 --- /dev/null +++ b/BaS_gcc.includes @@ -0,0 +1,5 @@ +include +tos/jtagwait/include +tos/pci_mem/include +tos/pci_test/include +tos/vmem_test/include \ No newline at end of file diff --git a/COPYING b/COPYING new file mode 100644 index 0000000..94a9ed0 --- /dev/null +++ b/COPYING @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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Combined Libraries. + + You may place library facilities that are a work based on the +Library side by side in a single library together with other library +facilities that are not Applications and are not covered by this +License, and convey such a combined library under terms of your +choice, if you do both of the following: + + a) Accompany the combined library with a copy of the same work based + on the Library, uncombined with any other library facilities, + conveyed under the terms of this License. + + b) Give prominent notice with the combined library that part of it + is a work based on the Library, and explaining where to find the + accompanying uncombined form of the same work. + + 6. Revised Versions of the GNU Lesser General Public License. + + The Free Software Foundation may publish revised and/or new versions +of the GNU Lesser General Public License from time to time. Such new +versions will be similar in spirit to the present version, but may +differ in detail to address new problems or concerns. + + Each version is given a distinguishing version number. If the +Library as you received it specifies that a certain numbered version +of the GNU Lesser General Public License "or any later version" +applies to it, you have the option of following the terms and +conditions either of that published version or of any later version +published by the Free Software Foundation. If the Library as you +received it does not specify a version number of the GNU Lesser +General Public License, you may choose any version of the GNU Lesser +General Public License ever published by the Free Software Foundation. + + If the Library as you received it specifies that a proxy can decide +whether future versions of the GNU Lesser General Public License shall +apply, that proxy's public statement of acceptance of any version is +permanent authorization for you to choose that version for the +Library. diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..0645cee --- /dev/null +++ b/Makefile @@ -0,0 +1,361 @@ +# Makefile for Firebee BaS +# +# This Makefile is meant for cross compiling the BaS with Vincent Riviere's cross compilers. +# If you want to compile native on an Atari (you will need at least GCC 4.6.3), set +# TCPREFIX to be empty. +# +# If you want to compile with the m68k-elf- toolchain, set TCPREFIX accordingly. Requires an extra +# installation, but allows source level debugging over BDM with a recent gdb (tested with 7.5), +# the m68k BDM tools from sourceforge (http://bdm.sourceforge.net) and a BDM pod (TBLCF and P&E tested). + + +ifneq (yes,$(VERBOSE)) +Q=@ +else +Q= +endif + +# can be either "Y" or "N" (without quotes). "Y" for using the m68k-elf-, "N" for using the m68k-atari-mint +# toolchain +COMPILE_ELF=Y + +ifeq (Y,$(COMPILE_ELF)) +TCPREFIX=m68k-elf- +EXE=elf +FORMAT=elf32-m68k +else +TCPREFIX=m68k-atari-mint- +EXE=s19 +FORMAT=srec +endif + +CC=$(TCPREFIX)gcc +LD=$(TCPREFIX)ld +CPP=$(TCPREFIX)cpp +OBJCOPY=$(TCPREFIX)objcopy +AR=$(TCPREFIX)ar +RANLIB=$(TCPREFIX)ranlib +NATIVECC=gcc + +ifeq (Y,$(COMPILE_ELF)) +LDLIBS=-lgcc +else +LDLIBS=-lgcc +endif + +INCLUDE=-Iinclude +CFLAGS= -Wall \ + -O2 \ + -fomit-frame-pointer \ + -ffreestanding \ + -fno-strict-aliasing \ + -fleading-underscore \ + -Winline \ + -Wa,--register-prefix-optional + +CFLAGS_OPTIMIZED = -mcpu=5474 \ + -Wall \ + -O2 \ + -fomit-frame-pointer \ + -ffreestanding \ + -fleading-underscore \ + -Wa,--register-prefix-optional +LDFLAGS= + +TRGTDIRS= ./firebee ./m54455 ./m5484lite +OBJDIRS=$(patsubst %, %/objs,$(TRGTDIRS)) +TOOLDIR=util + +VPATH=dma exe flash fs i2c if kbd pci spi sys usb net util video radeon x86emu xhdi + +# Linker control file. The final $(LDCFILE) is intermediate only (preprocessed version of $(LDCSRC) +LDCFILE=bas.lk +LDRFILE=ram.lk +LDCSRC=bas.lk.in +LDCBSRC=basflash.lk.in +LDCBFS=basflash.lk + +# this Makefile can create the BaS to flash or an arbitrary ram address (for BDM debugging). See +# below for the definition of TARGET_ADDRESS +FLASH_EXEC=bas.$(EXE) +RAM_EXEC=ram.$(EXE) +BASFLASH_EXEC=basflash.$(EXE) + +CSRCS= \ + sysinit.c \ + init_fpga.c \ + fault_vectors.c \ + interrupts.c \ + \ + bas_printf.c \ + bas_string.c \ + conout.c \ + \ + BaS.c \ + cache.c \ + mmu.c \ + mmc.c \ + unicode.c \ + ff.c \ + sd_card.c \ + wait.c \ + s19reader.c \ + flash.c \ + dma.c \ + i2c.c \ + xhdi_sd.c \ + xhdi_interface.c \ + pci.c \ + pci_errata.c \ + dspi.c \ + driver_vec.c \ + driver_mem.c \ + \ + MCD_dmaApi.c \ + MCD_tasks.c \ + MCD_tasksInit.c \ + \ + usb.c \ + ohci-hcd.c \ + ehci-hcd.c \ + usb_hub.c \ + usb_mouse.c \ + usb_kbd.c \ + ikbd.c \ + \ + nbuf.c \ + queue.c \ + net_timer.c \ + am79c874.c \ + bcm5222.c \ + nif.c \ + fecbd.c \ + fec.c \ + ip.c \ + udp.c \ + arp.c \ + bootp.c \ + tftp.c \ + \ + fbmem.c \ + fbmon.c \ + fbmodedb.c \ + offscreen.c \ + \ + videl.c \ + video.c \ + \ + i2c-algo-bit.c \ + \ + radeon_base.c \ + radeon_accel.c \ + radeon_cursor.c \ + radeon_monitor.c \ + radeon_i2c.c \ + fnt_st_8x16.c \ + \ + x86emu.c \ + x86pcibios.c \ + x86biosemu.c \ + x86emu_util.c \ + \ + basflash.c \ + basflash_start.c + + +ASRCS= \ + startcf.S \ + exceptions.S \ + setjmp.S \ + xhdi_vec.S \ + pci_wrappers.S + +ifeq (Y,$(COMPILE_ELF)) # needed for __ vs ___ kludge + ASRCS += libgcc_helper.S +endif + +SRCS=$(ASRCS) $(CSRCS) +COBJS=$(patsubst %.c,%.o,$(CSRCS)) +AOBJS=$(patsubst %.S,%.o,$(ASRCS)) + +OBJS=$(COBJS) $(AOBJS) +LIBBAS=libbas.a + +LIBS=$(patsubst %,%/$(LIBBAS),$(TRGTDIRS)) + +all: ver fls ram bfl lib tos +fls: $(patsubst %,%/$(FLASH_EXEC),$(TRGTDIRS)) +ram: $(patsubst %,%/$(RAM_EXEC),$(TRGTDIRS)) +bfl: $(patsubst %,%/$(BASFLASH_EXEC),$(TRGTDIRS)) +lib: $(LIBS) + +.PHONY: ver +ver: + touch include/version.h + +.PHONY: tos +tos: + $(Q)(cd tos; $(MAKE) -s) + +.PHONY: clean +clean: + $(Q)for d in $(TRGTDIRS);\ + do rm -f $$d/*.map $$d/*.s19 $$d/*.elf $$d/*.lk $$d/*.a $$d/objs/* $$d/depend;\ + done + $(Q)rm -f tags + $(Q)(cd tos; make -s clean) + + + +# flags for targets +m5484lite/bas.$(EXE): MACHINE=MACHINE_M5484LITE +m54455/bas.$(EXE): MACHINE=MACHINE_M54455 +firebee/bas.$(EXE): MACHINE=MACHINE_FIREBEE + +m5484lite/ram.$(EXE): MACHINE=MACHINE_M5484LITE +m54455/ram.$(EXE): MACHINE=MACHINE_M54455 +firebee/ram.$(EXE): MACHINE=MACHINE_FIREBEE + +m5484lite/basflash.$(EXE): MACHINE=MACHINE_M5484LITE +m54455/basflash.$(EXE): MACHINE=MACHINE_M54455 +firebee/basflash.$(EXE): MACHINE=MACHINE_FIREBEE + +m5484lite/bas.$(EXE): CFLAGS += -mcpu=5484 +m54455/bas.$(EXE): CFLAGS += -mcpu=54455 -msoft-float +firebee/bas.$(EXE): CFLAGS += -mcpu=5474 + +m5484lite/ram.$(EXE): CFLAGS += -mcpu=5484 +m54455/ram.$(EXE): CFLAGS += -mcpu=54455 -msoft-float +firebee/ram.$(EXE): CFLAGS += -mcpu=5474 + +m5484lite/basflash.$(EXE): CFLAGS += -mcpu=5484 +m54455/basflash.$(EXE): CFLAGS += -mcpu=54455 -msoft-float +firebee/basflash.$(EXE): CFLAGS += -mcpu=5474 + +# +# generate pattern rules for different object files +# +define CC_TEMPLATE +$(1)/objs/%.o:%.c + $(Q)echo CC $$< + $(Q)$(CC) $$(CFLAGS) -D$$(MACHINE) $(INCLUDE) -c $$< -o $$@ + +$(1)/objs/%.o:%.S + $(Q)echo CC $$< + $(Q)$(CC) $$(CFLAGS) -Wa,--bitwise-or -D$$(MACHINE) $(INCLUDE) -c $$< -o $$@ +endef +$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR)))) + +# rules for depend +define DEP_TEMPLATE +ifneq (clean,$$(MAKECMDGOALS)) +include $(1)/depend +endif + +ifeq (firebee,$(1)) + MACHINE=MACHINE_FIREBEE +else + MACHINE=MACHINE_M5484LITE +endif +$(1)/depend:$(SRCS) + $(Q)echo DEPEND + $(Q)$(CC) $$(CFLAGS) -D$$(MACHINE) $(INCLUDE) -M $$^ | sed -e "s#^\(.*\).o:#"$(1)"/objs/\1.o:#" > $$@ +endef +$(foreach DIR,$(TRGTDIRS),$(eval $(call DEP_TEMPLATE,$(DIR)))) + + +# +# generate pattern rules for libraries +# +define AR_TEMPLATE +$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS)) +$(1)/$(LIBBAS): $$($(1)_OBJS) + $(Q)echo AR $$@ + $(Q)$(AR) r $$@ $$? + $(Q)$(RANLIB) $$@ +endef +$(foreach DIR,$(TRGTDIRS),$(eval $(call AR_TEMPLATE,$(DIR)))) + +ifeq ($(COMPILE_ELF),Y) + FORMAT_ELF=1 +else + FORMAT_ELF=0 +endif + +define LK_TEMPLATE +$(1)/$$(LDCFILE): $(LDCSRC) + $(Q)echo CPP $$< + $(Q)$(CPP) $(INCLUDE) -DOBJDIR=$(1)/objs -P -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $$< -o $$@ +endef +$(foreach DIR,$(TRGTDIRS),$(eval $(call LK_TEMPLATE,$(DIR)))) + +# +# define pattern rules for binaries +# +define EX_TEMPLATE +# pattern rule for flash +$(1)_MAPFILE=$(1)/$$(basename $$(FLASH_EXEC)).map +$(1)/$$(FLASH_EXEC): $(1)/$(LIBBAS) $(1)/$$(LDCFILE) + $(Q)echo CC $$@ + $(Q)$(CC) $$(CFLAGS) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDCFILE) $(LDLIBS) -o $$@ +ifeq ($(COMPILE_ELF),Y) + $(Q)echo OBJCOPY $$@ + $(Q)$(OBJCOPY) -O srec $$@ $$(basename $$@).s19 +else + $(Q)echo OBJCOPY $$@ + $(Q)objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf +endif + +# pattern rule for RAM +$(1)_MAPFILE_RAM=$(1)/$$(basename $$(RAM_EXEC)).map +$(1)/$$(RAM_EXEC): $(1)/$(LIBBAS) $(1)/$$(LDCFILE) + $(Q)echo CPP $$@ + $(Q)$(CPP) $(INCLUDE) -DCOMPILE_RAM -DOBJDIR=$(1)/objs -P -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCSRC) -o $(1)/$$(LDRFILE) + $(Q)echo CC $$@ + $(Q)$(CC) $$(CFLAGS) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE_RAM) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDRFILE) $(LDLIBS) -o $$@ +ifeq ($(COMPILE_ELF),Y) + $(Q)echo OBJCOPY $$@ + $(Q)$(OBJCOPY) -O srec $$@ $$(basename $$@).s19 +else + $(Q)echo OBJCOPY $$< + $(Q)objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf +endif + +# pattern rule for basflash +$(1)_MAPFILE_BFL=$(1)/$$(basename $$(BASFLASH_EXEC)).map +$(1)/$$(BASFLASH_EXEC): $(1)/objs/basflash.o $(1)/objs/basflash_start.o $(1)/$(LIBBAS) $(LDCBFL) + $(Q)echo CPP $$< + $(CPP) $(INCLUDE) -P -DOBJDIR=$(1)/objs -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCBSRC) -o $(1)/$$(LDCBFS) + $(Q)echo CC $$< + $(Q)$(CC) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE_BFL) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDCBFS) -L$(1) -lbas $(LDLIBS) -o $$@ +ifeq ($(COMPILE_ELF),Y) + $(Q)echo OBJCOPY $$< + $(Q)$(OBJCOPY) -O srec $$@ $$(basename $$@).s19 +else + $(Q)echo OBJCOPY $$< + $(Q)objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf +endif +endef +$(foreach DIR,$(TRGTDIRS),$(eval $(call EX_TEMPLATE,$(DIR)))) + + +indent: $(CSRCS) + indent $< + +.PHONY: tags +tags: + ctags $(patsubst %,%/*,$(VPATH)) + +.PHONY: printvars +printvars: + $(Q)$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V)))) +ifeq (MACHINE_M5484LITE,$$(MACHINE)) + MNAME=m5484lite +else ifeq (MACHINE_FIREBEE,$(MACHINE)) + MNAME=firebee +endif + +tools: + $(NATIVECC) $(INCLUDE) -c $(TOOLDIR)/s19header.c -o $(TOOLDIR)/s19header.o + $(NATIVECC) -o $(TOOLDIR)/s19header $(TOOLDIR)/s19header.o + diff --git a/bas_firebee.bdm b/bas_firebee.bdm new file mode 100755 index 0000000..116fb57 --- /dev/null +++ b/bas_firebee.bdm @@ -0,0 +1,68 @@ +#!/usr/local/bin/bdmctrl -D2 -v9 -d9 +# +# firebee board initialization for bdmctrl +# +open $1 +reset +sleep 10 + +# Turn on MBAR at 0xFF00_0000 +write-ctrl 0x0C0F 0xFF000000 + +# set VBR +write-ctrl 0x0801 0x00000000 + +# Turn on RAMBAR0 at address FF10_0000 +write-ctrl 0x0C04 0xFF100007 + +# Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently) +write-ctrl 0x0C05 0xFF101001 + +# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) +write 0xFF000500 0xE0000000 4 +write 0xFF000508 0x00041180 4 +write 0xFF000504 0x007F0001 4 +wait + +# Init CS1 (Atari I/O address range) +write 0xFF00050C 0xFFF00000 4 +write 0xFF000514 0x00002180 4 +write 0xFF000510 0x000F0001 4 +# Init CS2 (FireBee 32 bit I/O address range) +write 0xFF000518 0xF0000000 4 +write 0xFF000520 0x00002100 4 +write 0xFF00051C 0x07FF0001 4 +# Init CS3 (FireBee 16 bit I/O address range) +write 0xFF000524 0xF8000000 4 +write 0xFF00052C 0x00000180 4 +write 0xFF000528 0x03FF0001 4 +# Init CS4 (FireBee video address range) +write 0xFF000530 0x40000000 4 +write 0xFF000538 0x00000018 4 +write 0xFF000534 0x003F0001 4 + + +# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes +write 0xFF000004 0x000002AA 4 # SDRAMDS configuration +write 0xFF000020 0x0000001A 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) +write 0xFF000024 0x0800001A 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) +write 0xFF000028 0x1000001A 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF) +write 0xFF00002C 0x1800001A 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) +write 0xFF000108 0x73622830 4 # SDCFG1 +write 0xFF00010C 0x46770000 4 # SDCFG2 + +write 0xFF000104 0xE10D0002 4 # SDCR + IPALL +write 0xFF000100 0x40010000 4 # SDMR (write to LEMR) +write 0xFF000100 0x048D0000 4 # SDMR (write to LMR) +sleep 100 +write 0xFF000104 0xE10D0002 4 # SDCR + IPALL +write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh) +write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh) +write 0xFF000100 0x008D0000 4 # SDMR (write to LMR) +write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh) +sleep 100 + +load -v firebee/ram.elf + +execute +wait diff --git a/bas_m5484.bdm b/bas_m5484.bdm new file mode 100755 index 0000000..59a40a8 --- /dev/null +++ b/bas_m5484.bdm @@ -0,0 +1,56 @@ +#!/usr/local/bin/bdmctrl -D2 -v9 -d9 +# +# firebee board initialization for bdmctrl +# +open $1 +reset +sleep 10 + +wait + +# set VBR +write-ctrl 0x0801 0x00000000 +dump-register VBR + +# Turn on MBAR at 0xFF00_0000 +write-ctrl 0x0C0F 0xFF000000 +dump-register MBAR + +# Turn on RAMBAR0 at address FF10_0000 +write-ctrl 0x0C04 0xFF100007 + +# Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently) +write-ctrl 0x0C05 0xFF101001 + +# Init CS0 (BootFLASH @ E000_0000 - E03F_FFFF 8Mbytes) +write 0xFF000500 0xE0000000 4 +write 0xFF000508 0x00041180 4 +write 0xFF000504 0x003F0001 4 +wait + +# SDRAM Initialization @ 0000_0000 - 0400_0000 64 MBytes +write 0xFF000004 0x000002AA 4 # SDRAMDS configuration +write 0xFF000020 0x00000019 4 # SDRAM CS0 configuration (64Mbytes 0000_0000 - 07FF_FFFF) +write 0xFF000024 0x00000000 4 # SDRAM CS1 configuration +write 0xFF000028 0x00000000 4 # SDRAM CS2 configuration +write 0xFF00002C 0x00000000 4 # SDRAM CS3 configuration + +write 0xFF000108 0x73711630 4 # SDCFG1 +write 0xFF00010C 0x46370000 4 # SDCFG2 + +write 0xFF000104 0xE10B0002 4 # SDCR + IPALL +write 0xFF000100 0x40010000 4 # SDMR (write to LEMR) +write 0xFF000100 0x058D0000 4 # SDMR (write to LMR) +sleep 100 +write 0xFF000104 0xE10D0002 4 # SDCR + IPALL +write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh) +write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh) +write 0xFF000100 0x018D0000 4 # SDMR (write to LMR) +write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh) +sleep 100 + +load -v m5484lite/ram.elf +execute +# wait is _needed_ here if using the P&E BDM interface. Otherwise +# the Coldfire resets after some time! +wait diff --git a/basflash.lk.in b/basflash.lk.in new file mode 100644 index 0000000..290b7e7 --- /dev/null +++ b/basflash.lk.in @@ -0,0 +1,115 @@ +#if defined(MACHINE_FIREBEE) +#include "firebee.h" +#elif defined(MACHINE_M5484LITE) +#include "m5484l.h" +#elif defined(MACHINE_M54455) +#include "m54455.h" +#else +#error unknown machine +#endif + +MEMORY +{ + flasher (WX) : ORIGIN = BFL_TARGET_ADDRESS, LENGTH = 0x00100000 /* target to load basflash */ +} + +SECTIONS +{ + .text : + { + OBJDIR/basflash_start.o(.text) + OBJDIR/basflash.o(.text) + + *(.data) + *(.bss) + *(.rodata) + *(.rodata.*) + } > flasher + + .bas : + { + } + + #define BAS_LABEL_LMA(x) ((x)) + /* _xprintf_before_copy = BAS_LABEL_LMA(_xprintf); */ + /* _display_progress_before_copy = BAS_LABEL_LMA(_display_progress); */ + /* _flush_and_invalidate_caches_before_copy = BAS_LABEL_LMA(_flush_and_invalidate_caches); */ + + /* + * Global memory map + */ + + /* SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes */ + ___SDRAM = 0x00000000; + ___SDRAM_SIZE = 0x20000000; + + /* ST-RAM */ + __STRAM = ___SDRAM; + __STRAM_END = __TOS; + + /* TOS */ + __TOS = 0x00e00000; + + /* FastRAM */ + __FASTRAM = 0x10000000; + __FASTRAM_END = 0x1FFFFFFF; + + /* Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) */ + ___BOOT_FLASH = 0xe0000000; + ___BOOT_FLASH_SIZE = 0x00800000; + + /* BaS */ + __BAS_LMA = LOADADDR(.bas); + __BAS_IN_RAM = ADDR(.bas); + __BAS_SIZE = SIZEOF(.bas); + + /* Other flash components */ + __FIRETOS = 0xe0400000; + __EMUTOS = 0xe0600000; + __EMUTOS_SIZE = 0x00100000; + + /* VIDEO RAM BASIS */ + __VRAM = 0x60000000; + + /* Memory mapped registers */ + __MBAR = 0xFF000000; + + /* 32KB on-chip System SRAM */ + __SYS_SRAM = 0xFF010000; + __SYS_SRAM_SIZE = 0x00008000; + + /* MMU memory mapped registers */ + __MMUBAR = 0xFF040000; + + /* + * 4KB on-chip Core SRAM0: -> exception table and exception stack + */ + __RAMBAR0 = 0xFF100000; + __RAMBAR0_SIZE = 0x00001000; + __SUP_SP = __RAMBAR0 + __RAMBAR0_SIZE - 4; + + /* system variables */ + + /* RAMBAR0 0 to 0x7FF -> exception vectors */ + _rt_mod = __RAMBAR0 + 0x800; + _rt_ssp = __RAMBAR0 + 0x804; + _rt_usp = __RAMBAR0 + 0x808; + _rt_vbr = __RAMBAR0 + 0x80C; /* (8)01 */ + _rt_cacr = __RAMBAR0 + 0x810; /* 002 */ + _rt_asid = __RAMBAR0 + 0x814; /* 003 */ + _rt_acr0 = __RAMBAR0 + 0x818; /* 004 */ + _rt_acr1 = __RAMBAR0 + 0x81c; /* 005 */ + _rt_acr2 = __RAMBAR0 + 0x820; /* 006 */ + _rt_acr3 = __RAMBAR0 + 0x824; /* 007 */ + _rt_mmubar = __RAMBAR0 + 0x828; /* 008 */ + _rt_sr = __RAMBAR0 + 0x82c; + _d0_save = __RAMBAR0 + 0x830; + _a7_save = __RAMBAR0 + 0x834; + _video_tlb = __RAMBAR0 + 0x838; + _video_sbt = __RAMBAR0 + 0x83C; + _rt_mbar = __RAMBAR0 + 0x844; /* (c)0f */ + + /* 4KB on-chip Core SRAM1: -> modified code */ + __RAMBAR1 = 0xFF101000; + __RAMBAR1_SIZE = 0x00001000; + } diff --git a/check.bdm b/check.bdm new file mode 100755 index 0000000..b0b3e5d --- /dev/null +++ b/check.bdm @@ -0,0 +1,76 @@ +#!/usr/local/bin/bdmctrl -D2 -v9 -d9 +# +# firebee board initialization for bdmctrl +# +open $1 +reset + +# set VBR +write-ctrl 0x0801 0x00000000 +# Turn on MBAR at 0xFF00_0000 +write-ctrl 0x0C0F 0xFF000000 + +# Turn on RAMBAR0 at address FF10_0000 +write-ctrl 0x0C04 0xFF100007 + +# Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently) +write-ctrl 0x0C05 0xFF101001 + +# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) +write 0xFF000500 0xE0000000 4 +write 0xFF000508 0x00041180 4 +write 0xFF000504 0x007F0001 4 +wait + +# Init CS1 (Atari I/O address range) +write 0xFF00050C 0xFFF00000 4 +write 0xFF000514 0x00002180 4 +write 0xFF000510 0x000F0001 4 +# Init CS2 (FireBee 32 bit I/O address range) +write 0xFF000518 0xF0000000 4 +write 0xFF000520 0x00002100 4 +write 0xFF00051C 0x07FF0001 4 +# Init CS3 (FireBee 16 bit I/O address range) +write 0xFF000524 0xF8000000 4 +write 0xFF00052C 0x00000180 4 +write 0xFF000528 0x03FF0001 4 +# Init CS4 (FireBee video address range) +write 0xFF000530 0x40000000 4 +write 0xFF000538 0x00000018 4 +write 0xFF000534 0x003F0001 4 + + +# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes +write 0xFF000004 0x000002AA 4 # SDRAMDS configuration +write 0xFF000020 0x0000001A 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) +write 0xFF000024 0x0800001A 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) +write 0xFF000028 0x1000001A 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF) +write 0xFF00002C 0x1800001A 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) +write 0xFF000108 0x73622830 4 # SDCFG1 +write 0xFF00010C 0x46770000 4 # SDCFG2 + +write 0xFF000104 0xE10D0002 4 # SDCR + IPALL +write 0xFF000100 0x40010000 4 # SDMR (write to LEMR) +write 0xFF000100 0x048D0000 4 # SDMR (write to LMR) + +write 0xFF000104 0xE10D0002 4 # SDCR + IPALL +write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh) +write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh) +write 0xFF000100 0x008D0000 4 # SDMR (write to LMR) +write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh) + +dump-register SR +write-ctrl 0x80e 0x2700 +write-ctrl 0x2 0xa50c8120 +dump-register D0 +dump-register ASID +dump-register ACR0 +dump-register ACR1 +dump-register ACR2 +dump-register ACR3 +dump-register SR +dump-register CACR +dump-register RAMBAR1 +dump-register RAMBAR2 +dump-register MBAR +dump-register 0xc05 \ No newline at end of file diff --git a/dump.bdm b/dump.bdm new file mode 100755 index 0000000..9400201 --- /dev/null +++ b/dump.bdm @@ -0,0 +1,17 @@ +#!/usr/local/bin/bdmctrl -D2 -v9 -d9 +# +# firebee board initialization for bdmctrl +# +open $1 + +dump-register D0 +#dump-register ASID +dump-register ACR0 +dump-register ACR1 +#dump-register ACR2 +#dump-register ACR3 +dump-register SR +dump-register CACR +# dump-register RAMBAR1 +# dump-register RAMBAR2 +dump-register MBAR diff --git a/include/MCF5475_DSPI.h b/include/MCF5475_DSPI.h new file mode 100644 index 0000000..76cac28 --- /dev/null +++ b/include/MCF5475_DSPI.h @@ -0,0 +1,150 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_DSPI_H__ +#define __MCF5475_DSPI_H__ + + +/********************************************************************* +* +* DMA Serial Peripheral Interface (DSPI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DSPI_DMCR (*(volatile uint32_t*)(&_MBAR[0x8A00])) +#define MCF_DSPI_DTCR (*(volatile uint32_t*)(&_MBAR[0x8A08])) +#define MCF_DSPI_DCTAR0 (*(volatile uint32_t*)(&_MBAR[0x8A0C])) +#define MCF_DSPI_DCTAR1 (*(volatile uint32_t*)(&_MBAR[0x8A10])) +#define MCF_DSPI_DCTAR2 (*(volatile uint32_t*)(&_MBAR[0x8A14])) +#define MCF_DSPI_DCTAR3 (*(volatile uint32_t*)(&_MBAR[0x8A18])) +#define MCF_DSPI_DCTAR4 (*(volatile uint32_t*)(&_MBAR[0x8A1C])) +#define MCF_DSPI_DCTAR5 (*(volatile uint32_t*)(&_MBAR[0x8A20])) +#define MCF_DSPI_DCTAR6 (*(volatile uint32_t*)(&_MBAR[0x8A24])) +#define MCF_DSPI_DCTAR7 (*(volatile uint32_t*)(&_MBAR[0x8A28])) +#define MCF_DSPI_DSR (*(volatile uint32_t*)(&_MBAR[0x8A2C])) +#define MCF_DSPI_DIRSR (*(volatile uint32_t*)(&_MBAR[0x8A30])) +#define MCF_DSPI_DTFR (*(volatile uint32_t*)(&_MBAR[0x8A34])) +#define MCF_DSPI_DRFR (*(volatile uint32_t*)(&_MBAR[0x8A38])) +#define MCF_DSPI_DTFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A3C])) +#define MCF_DSPI_DTFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A40])) +#define MCF_DSPI_DTFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A44])) +#define MCF_DSPI_DTFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A48])) +#define MCF_DSPI_DRFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A7C])) +#define MCF_DSPI_DRFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A80])) +#define MCF_DSPI_DRFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A84])) +#define MCF_DSPI_DRFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A88])) +#define MCF_DSPI_DCTAR(x) (*(volatile uint32_t*)(&_MBAR[0x8A0C + ((x)*0x4)])) +#define MCF_DSPI_DTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A3C + ((x)*0x4)])) +#define MCF_DSPI_DRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A7C + ((x)*0x4)])) + + +/* Bit definitions and macros for MCF_DSPI_DMCR */ +#define MCF_DSPI_DMCR_HALT (0x1) +#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x3)<<0x8) +#define MCF_DSPI_DMCR_SMPL_PT_0CLK (0) +#define MCF_DSPI_DMCR_SMPL_PT_1CLK (0x100) +#define MCF_DSPI_DMCR_SMPL_PT_2CLK (0x200) +#define MCF_DSPI_DMCR_CRXF (0x400) +#define MCF_DSPI_DMCR_CTXF (0x800) +#define MCF_DSPI_DMCR_DRXF (0x1000) +#define MCF_DSPI_DMCR_DTXF (0x2000) +#define MCF_DSPI_DMCR_CSIS0 (0x10000) +#define MCF_DSPI_DMCR_CSIS2 (0x40000) +#define MCF_DSPI_DMCR_CSIS3 (0x80000) +#define MCF_DSPI_DMCR_CSIS5 (0x200000) +#define MCF_DSPI_DMCR_ROOE (0x1000000) +#define MCF_DSPI_DMCR_PCSSE (0x2000000) +#define MCF_DSPI_DMCR_MTFE (0x4000000) +#define MCF_DSPI_DMCR_FRZ (0x8000000) +#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x3)<<0x1C) +#define MCF_DSPI_DMCR_CSCK (0x40000000) +#define MCF_DSPI_DMCR_MSTR (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DTCR */ +#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_DSPI_DCTAR */ +#define MCF_DSPI_DCTAR_BR(x) (((x)&0xF)<<0) +#define MCF_DSPI_DCTAR_DT(x) (((x)&0xF)<<0x4) +#define MCF_DSPI_DCTAR_ASC(x) (((x)&0xF)<<0x8) +#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0xF)<<0xC) +#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x3)<<0x10) +#define MCF_DSPI_DCTAR_PBR_1CLK (0) +#define MCF_DSPI_DCTAR_PBR_3CLK (0x10000) +#define MCF_DSPI_DCTAR_PBR_5CLK (0x20000) +#define MCF_DSPI_DCTAR_PBR_7CLK (0x30000) +#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x3)<<0x12) +#define MCF_DSPI_DCTAR_PDT_1CLK (0) +#define MCF_DSPI_DCTAR_PDT_3CLK (0x40000) +#define MCF_DSPI_DCTAR_PDT_5CLK (0x80000) +#define MCF_DSPI_DCTAR_PDT_7CLK (0xC0000) +#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x3)<<0x14) +#define MCF_DSPI_DCTAR_PASC_1CLK (0) +#define MCF_DSPI_DCTAR_PASC_3CLK (0x100000) +#define MCF_DSPI_DCTAR_PASC_5CLK (0x200000) +#define MCF_DSPI_DCTAR_PASC_7CLK (0x300000) +#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x3)<<0x16) +#define MCF_DSPI_DCTAR_LSBFE (0x1000000) +#define MCF_DSPI_DCTAR_CPHA (0x2000000) +#define MCF_DSPI_DCTAR_CPOL (0x4000000) +#define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0xF)<<0x1B) + +/* Bit definitions and macros for MCF_DSPI_DSR */ +#define MCF_DSPI_DSR_RXPTR(x) (((x)&0xF)<<0) +#define MCF_DSPI_DSR_RXCTR(x) (((x)&0xF)<<0x4) +#define MCF_DSPI_DSR_TXPTR(x) (((x)&0xF)<<0x8) +#define MCF_DSPI_DSR_TXCTR(x) (((x)&0xF)<<0xC) +#define MCF_DSPI_DSR_RFDF (0x20000) +#define MCF_DSPI_DSR_RFOF (0x80000) +#define MCF_DSPI_DSR_TFFF (0x2000000) +#define MCF_DSPI_DSR_TFUF (0x8000000) +#define MCF_DSPI_DSR_EOQF (0x10000000) +#define MCF_DSPI_DSR_TXRXS (0x40000000) +#define MCF_DSPI_DSR_TCF (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DIRSR */ +#define MCF_DSPI_DIRSR_RFDFS (0x10000) +#define MCF_DSPI_DIRSR_RFDFE (0x20000) +#define MCF_DSPI_DIRSR_RFOFE (0x80000) +#define MCF_DSPI_DIRSR_TFFFS (0x1000000) +#define MCF_DSPI_DIRSR_TFFFE (0x2000000) +#define MCF_DSPI_DIRSR_TFUFE (0x8000000) +#define MCF_DSPI_DIRSR_EOQFE (0x10000000) +#define MCF_DSPI_DIRSR_TCFE (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DTFR */ +#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0xFFFF)<<0) +#define MCF_DSPI_DTFR_CS0 (0x10000) +#define MCF_DSPI_DTFR_CS2 (0x40000) +#define MCF_DSPI_DTFR_CS3 (0x80000) +#define MCF_DSPI_DTFR_CS5 (0x200000) +#define MCF_DSPI_DTFR_CTCNT (0x4000000) +#define MCF_DSPI_DTFR_EOQ (0x8000000) +#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x7)<<0x1C) +#define MCF_DSPI_DTFR_CONT (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DRFR */ +#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_DSPI_DTFDR */ +#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0xFFFF)<<0) +#define MCF_DSPI_DTFDR_TXCMD(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_DSPI_DRFDR */ +#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0xFFFF)<<0) + + +#endif /* __MCF5475_DSPI_H__ */ diff --git a/include/MCF5475_GPIO.h b/include/MCF5475_GPIO.h new file mode 100644 index 0000000..5dd2583 --- /dev/null +++ b/include/MCF5475_GPIO.h @@ -0,0 +1,543 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_GPIO_H__ +#define __MCF5475_GPIO_H__ + + +/********************************************************************* +* +* General Purpose I/O (GPIO) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPIO_PODR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA00])) +#define MCF_GPIO_PDDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA10])) +#define MCF_GPIO_PPDSDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA20])) +#define MCF_GPIO_PCLRR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA30])) + +#define MCF_GPIO_PODR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA01])) +#define MCF_GPIO_PDDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA11])) +#define MCF_GPIO_PPDSDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA21])) +#define MCF_GPIO_PCLRR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA31])) + +#define MCF_GPIO_PODR_DMA (*(volatile uint8_t *)(&_MBAR[0xA02])) +#define MCF_GPIO_PDDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA12])) +#define MCF_GPIO_PPDSDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA22])) +#define MCF_GPIO_PCLRR_DMA (*(volatile uint8_t *)(&_MBAR[0xA32])) + +#define MCF_GPIO_PODR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA04])) +#define MCF_GPIO_PDDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA14])) +#define MCF_GPIO_PPDSDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA24])) +#define MCF_GPIO_PCLRR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA34])) + +#define MCF_GPIO_PODR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA05])) +#define MCF_GPIO_PDDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA15])) +#define MCF_GPIO_PPDSDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA25])) +#define MCF_GPIO_PCLRR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA35])) + +#define MCF_GPIO_PODR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA06])) +#define MCF_GPIO_PDDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA16])) +#define MCF_GPIO_PPDSDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA26])) +#define MCF_GPIO_PCLRR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA36])) + +#define MCF_GPIO_PODR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA07])) +#define MCF_GPIO_PDDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA17])) +#define MCF_GPIO_PPDSDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA27])) +#define MCF_GPIO_PCLRR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA37])) + +#define MCF_GPIO_PODR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA08])) +#define MCF_GPIO_PDDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA18])) +#define MCF_GPIO_PPDSDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA28])) +#define MCF_GPIO_PCLRR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA38])) + +#define MCF_GPIO_PODR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA09])) +#define MCF_GPIO_PDDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA19])) +#define MCF_GPIO_PPDSDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA29])) +#define MCF_GPIO_PCLRR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA39])) + +#define MCF_GPIO_PODR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA0A])) +#define MCF_GPIO_PDDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA1A])) +#define MCF_GPIO_PPDSDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA2A])) +#define MCF_GPIO_PCLRR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA3A])) + +#define MCF_GPIO2_PODR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA0C])) +#define MCF_GPIO2_PDDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA1C])) +#define MCF_GPIO2_PPDSDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA2C])) +#define MCF_GPIO2_PCLRR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA3C])) + +#define MCF_GPIO0_PODR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA0D])) +#define MCF_GPIO0_PDDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA1D])) +#define MCF_GPIO0_PPDSDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA2D])) +#define MCF_GPIO0_PCLRR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA3D])) + +#define MCF_GPIO_PODR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA0E])) +#define MCF_GPIO_PDDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA1E])) +#define MCF_GPIO_PPDSDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA2E])) +#define MCF_GPIO_PCLRR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA3E])) + + + +/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */ +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x1) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x2) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x4) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x8) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */ +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x1) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x2) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x4) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x8) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */ +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x1) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x2) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x4) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x8) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */ +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x1) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x2) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x4) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x8) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */ +#define MCF_GPIO_PODR_FBCS_PODR_FBCS1 (0x2) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS2 (0x4) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS3 (0x8) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS4 (0x10) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */ +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x2) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x4) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x8) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */ +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x2) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x4) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x8) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */ +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x2) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x4) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x8) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PODR_DMA */ +#define MCF_GPIO_PODR_DMA_PODR_DMA0 (0x1) +#define MCF_GPIO_PODR_DMA_PODR_DMA1 (0x2) +#define MCF_GPIO_PODR_DMA_PODR_DMA2 (0x4) +#define MCF_GPIO_PODR_DMA_PODR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */ +#define MCF_GPIO_PDDR_DMA_PDDR_DMA0 (0x1) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA1 (0x2) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA2 (0x4) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */ +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x1) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x2) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x4) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */ +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x1) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x2) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x4) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */ +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x1) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x2) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x4) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x8) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */ +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x1) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x2) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x4) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x8) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */ +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x1) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x2) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x4) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x8) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */ +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x1) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x2) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x4) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x8) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */ +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x1) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x2) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x4) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x8) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */ +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x1) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x2) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x4) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x8) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */ +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x1) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x2) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x4) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x8) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */ +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x1) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1 (0x2) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x4) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x8) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4 (0x10) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5 (0x20) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6 (0x40) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */ +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x1) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x2) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x4) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x8) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */ +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x1) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x2) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x4) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x8) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */ +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x1) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x2) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x4) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x8) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */ +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x1) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x2) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x4) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3 (0x8) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4 (0x10) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */ +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x1) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x2) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x4) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x8) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */ +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x1) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x2) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x4) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x8) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */ +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x1) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x2) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x4) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x8) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */ +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x1) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x2) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x4) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x8) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4 (0x10) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x1) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x2) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x4) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x1) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x2) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x4) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x1) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x2) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x4) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */ +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x1) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x2) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x4) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x8) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */ +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x1) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x2) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x4) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x8) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */ +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x1) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x2) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x4) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x8) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */ +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0 (0x1) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1 (0x2) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2 (0x4) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x8) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */ +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x1) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x2) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x4) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x8) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */ +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x1) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x2) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x4) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x8) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */ +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x1) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x2) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x4) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x8) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */ +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x1) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x2) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x4) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3 (0x8) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */ +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */ +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */ +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */ +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */ +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */ +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */ +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */ +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */ +#define MCF_GPIO_PODR_DSPI_PODR_DSPI0 (0x1) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI1 (0x2) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI2 (0x4) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI3 (0x8) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI4 (0x10) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI5 (0x20) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */ +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x1) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x2) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x4) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x8) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */ +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x1) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x2) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x4) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x8) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4 (0x10) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */ +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x1) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x2) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x4) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x8) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40) + + +#endif /* __MCF5475_GPIO_H__ */ diff --git a/include/MCF5475_GPT.h b/include/MCF5475_GPT.h new file mode 100644 index 0000000..f9fbc98 --- /dev/null +++ b/include/MCF5475_GPT.h @@ -0,0 +1,100 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_GPT_H__ +#define __MCF5475_GPT_H__ + + +/********************************************************************* +* +* General Purpose Timers (GPT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPT0_GMS (*(volatile uint32_t*)(&_MBAR[0x800])) +#define MCF_GPT0_GCIR (*(volatile uint32_t*)(&_MBAR[0x804])) +#define MCF_GPT0_GPWM (*(volatile uint32_t*)(&_MBAR[0x808])) +#define MCF_GPT0_GSR (*(volatile uint32_t*)(&_MBAR[0x80C])) + +#define MCF_GPT1_GMS (*(volatile uint32_t*)(&_MBAR[0x810])) +#define MCF_GPT1_GCIR (*(volatile uint32_t*)(&_MBAR[0x814])) +#define MCF_GPT1_GPWM (*(volatile uint32_t*)(&_MBAR[0x818])) +#define MCF_GPT1_GSR (*(volatile uint32_t*)(&_MBAR[0x81C])) + +#define MCF_GPT2_GMS (*(volatile uint32_t*)(&_MBAR[0x820])) +#define MCF_GPT2_GCIR (*(volatile uint32_t*)(&_MBAR[0x824])) +#define MCF_GPT2_GPWM (*(volatile uint32_t*)(&_MBAR[0x828])) +#define MCF_GPT2_GSR (*(volatile uint32_t*)(&_MBAR[0x82C])) + +#define MCF_GPT3_GMS (*(volatile uint32_t*)(&_MBAR[0x830])) +#define MCF_GPT3_GCIR (*(volatile uint32_t*)(&_MBAR[0x834])) +#define MCF_GPT3_GPWM (*(volatile uint32_t*)(&_MBAR[0x838])) +#define MCF_GPT3_GSR (*(volatile uint32_t*)(&_MBAR[0x83C])) + +#define MCF_GPT_GMS(x) (*(volatile uint32_t*)(&_MBAR[0x800 + ((x)*0x10)])) +#define MCF_GPT_GCIR(x) (*(volatile uint32_t*)(&_MBAR[0x804 + ((x)*0x10)])) +#define MCF_GPT_GPWM(x) (*(volatile uint32_t*)(&_MBAR[0x808 + ((x)*0x10)])) +#define MCF_GPT_GSR(x) (*(volatile uint32_t*)(&_MBAR[0x80C + ((x)*0x10)])) + + +/* Bit definitions and macros for MCF_GPT_GMS */ +#define MCF_GPT_GMS_TMS(x) (((x)&0x7)<<0) +#define MCF_GPT_GMS_TMS_DISABLE (0) +#define MCF_GPT_GMS_TMS_INCAPT (0x1) +#define MCF_GPT_GMS_TMS_OUTCAPT (0x2) +#define MCF_GPT_GMS_TMS_PWM (0x3) +#define MCF_GPT_GMS_TMS_GPIO (0x4) +#define MCF_GPT_GMS_GPIO(x) (((x)&0x3)<<0x4) +#define MCF_GPT_GMS_GPIO_INPUT (0) +#define MCF_GPT_GMS_GPIO_OUTLO (0x20) +#define MCF_GPT_GMS_GPIO_OUTHI (0x30) +#define MCF_GPT_GMS_IEN (0x100) +#define MCF_GPT_GMS_OD (0x200) +#define MCF_GPT_GMS_SC (0x400) +#define MCF_GPT_GMS_CE (0x1000) +#define MCF_GPT_GMS_WDEN (0x8000) +#define MCF_GPT_GMS_ICT(x) (((x)&0x3)<<0x10) +#define MCF_GPT_GMS_ICT_ANY (0) +#define MCF_GPT_GMS_ICT_RISE (0x10000) +#define MCF_GPT_GMS_ICT_FALL (0x20000) +#define MCF_GPT_GMS_ICT_PULSE (0x30000) +#define MCF_GPT_GMS_OCT(x) (((x)&0x3)<<0x14) +#define MCF_GPT_GMS_OCT_FRCLOW (0) +#define MCF_GPT_GMS_OCT_PULSEHI (0x100000) +#define MCF_GPT_GMS_OCT_PULSELO (0x200000) +#define MCF_GPT_GMS_OCT_TOGGLE (0x300000) +#define MCF_GPT_GMS_OCPW(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_GPT_GCIR */ +#define MCF_GPT_GCIR_CNT(x) (((x)&0xFFFF)<<0) +#define MCF_GPT_GCIR_PRE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_GPT_GPWM */ +#define MCF_GPT_GPWM_LOAD (0x1) +#define MCF_GPT_GPWM_PWMOP (0x100) +#define MCF_GPT_GPWM_WIDTH(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_GPT_GSR */ +#define MCF_GPT_GSR_CAPT (0x1) +#define MCF_GPT_GSR_COMP (0x2) +#define MCF_GPT_GSR_PWMP (0x4) +#define MCF_GPT_GSR_TEXP (0x8) +#define MCF_GPT_GSR_PIN (0x100) +#define MCF_GPT_GSR_OVF(x) (((x)&0x7)<<0xC) +#define MCF_GPT_GSR_CAPTURE(x) (((x)&0xFFFF)<<0x10) + + +#endif /* __MCF5475_GPT_H__ */ diff --git a/include/MCF5475_INTC.h b/include/MCF5475_INTC.h new file mode 100644 index 0000000..50e8074 --- /dev/null +++ b/include/MCF5475_INTC.h @@ -0,0 +1,330 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_INTC_H__ +#define __MCF5475_INTC_H__ + + +/********************************************************************* +* +* Interrupt Controller (INTC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_INTC_IPRH (*(volatile uint32_t*)(&_MBAR[0x700])) +#define MCF_INTC_IPRL (*(volatile uint32_t*)(&_MBAR[0x704])) +#define MCF_INTC_IMRH (*(volatile uint32_t*)(&_MBAR[0x708])) +#define MCF_INTC_IMRL (*(volatile uint32_t*)(&_MBAR[0x70C])) +#define MCF_INTC_INTFRCH (*(volatile uint32_t*)(&_MBAR[0x710])) +#define MCF_INTC_INTFRCL (*(volatile uint32_t*)(&_MBAR[0x714])) +#define MCF_INTC_IRLR (*(volatile uint8_t *)(&_MBAR[0x718])) +#define MCF_INTC_IACKLPR (*(volatile uint8_t *)(&_MBAR[0x719])) +#define MCF_INTC_ICR01 (*(volatile uint8_t *)(&_MBAR[0x741])) +#define MCF_INTC_ICR02 (*(volatile uint8_t *)(&_MBAR[0x742])) +#define MCF_INTC_ICR03 (*(volatile uint8_t *)(&_MBAR[0x743])) +#define MCF_INTC_ICR04 (*(volatile uint8_t *)(&_MBAR[0x744])) +#define MCF_INTC_ICR05 (*(volatile uint8_t *)(&_MBAR[0x745])) +#define MCF_INTC_ICR06 (*(volatile uint8_t *)(&_MBAR[0x746])) +#define MCF_INTC_ICR07 (*(volatile uint8_t *)(&_MBAR[0x747])) +#define MCF_INTC_ICR08 (*(volatile uint8_t *)(&_MBAR[0x748])) +#define MCF_INTC_ICR09 (*(volatile uint8_t *)(&_MBAR[0x749])) +#define MCF_INTC_ICR10 (*(volatile uint8_t *)(&_MBAR[0x74A])) +#define MCF_INTC_ICR11 (*(volatile uint8_t *)(&_MBAR[0x74B])) +#define MCF_INTC_ICR12 (*(volatile uint8_t *)(&_MBAR[0x74C])) +#define MCF_INTC_ICR13 (*(volatile uint8_t *)(&_MBAR[0x74D])) +#define MCF_INTC_ICR14 (*(volatile uint8_t *)(&_MBAR[0x74E])) +#define MCF_INTC_ICR15 (*(volatile uint8_t *)(&_MBAR[0x74F])) +#define MCF_INTC_ICR16 (*(volatile uint8_t *)(&_MBAR[0x750])) +#define MCF_INTC_ICR17 (*(volatile uint8_t *)(&_MBAR[0x751])) +#define MCF_INTC_ICR18 (*(volatile uint8_t *)(&_MBAR[0x752])) +#define MCF_INTC_ICR19 (*(volatile uint8_t *)(&_MBAR[0x753])) +#define MCF_INTC_ICR20 (*(volatile uint8_t *)(&_MBAR[0x754])) +#define MCF_INTC_ICR21 (*(volatile uint8_t *)(&_MBAR[0x755])) +#define MCF_INTC_ICR22 (*(volatile uint8_t *)(&_MBAR[0x756])) +#define MCF_INTC_ICR23 (*(volatile uint8_t *)(&_MBAR[0x757])) +#define MCF_INTC_ICR24 (*(volatile uint8_t *)(&_MBAR[0x758])) +#define MCF_INTC_ICR25 (*(volatile uint8_t *)(&_MBAR[0x759])) +#define MCF_INTC_ICR26 (*(volatile uint8_t *)(&_MBAR[0x75A])) +#define MCF_INTC_ICR27 (*(volatile uint8_t *)(&_MBAR[0x75B])) +#define MCF_INTC_ICR28 (*(volatile uint8_t *)(&_MBAR[0x75C])) +#define MCF_INTC_ICR29 (*(volatile uint8_t *)(&_MBAR[0x75D])) +#define MCF_INTC_ICR30 (*(volatile uint8_t *)(&_MBAR[0x75E])) +#define MCF_INTC_ICR31 (*(volatile uint8_t *)(&_MBAR[0x75F])) +#define MCF_INTC_ICR32 (*(volatile uint8_t *)(&_MBAR[0x760])) +#define MCF_INTC_ICR33 (*(volatile uint8_t *)(&_MBAR[0x761])) +#define MCF_INTC_ICR34 (*(volatile uint8_t *)(&_MBAR[0x762])) +#define MCF_INTC_ICR35 (*(volatile uint8_t *)(&_MBAR[0x763])) +#define MCF_INTC_ICR36 (*(volatile uint8_t *)(&_MBAR[0x764])) +#define MCF_INTC_ICR37 (*(volatile uint8_t *)(&_MBAR[0x765])) +#define MCF_INTC_ICR38 (*(volatile uint8_t *)(&_MBAR[0x766])) +#define MCF_INTC_ICR39 (*(volatile uint8_t *)(&_MBAR[0x767])) +#define MCF_INTC_ICR40 (*(volatile uint8_t *)(&_MBAR[0x768])) +#define MCF_INTC_ICR41 (*(volatile uint8_t *)(&_MBAR[0x769])) +#define MCF_INTC_ICR42 (*(volatile uint8_t *)(&_MBAR[0x76A])) +#define MCF_INTC_ICR43 (*(volatile uint8_t *)(&_MBAR[0x76B])) +#define MCF_INTC_ICR44 (*(volatile uint8_t *)(&_MBAR[0x76C])) +#define MCF_INTC_ICR45 (*(volatile uint8_t *)(&_MBAR[0x76D])) +#define MCF_INTC_ICR46 (*(volatile uint8_t *)(&_MBAR[0x76E])) +#define MCF_INTC_ICR47 (*(volatile uint8_t *)(&_MBAR[0x76F])) +#define MCF_INTC_ICR48 (*(volatile uint8_t *)(&_MBAR[0x770])) +#define MCF_INTC_ICR49 (*(volatile uint8_t *)(&_MBAR[0x771])) +#define MCF_INTC_ICR50 (*(volatile uint8_t *)(&_MBAR[0x772])) +#define MCF_INTC_ICR51 (*(volatile uint8_t *)(&_MBAR[0x773])) +#define MCF_INTC_ICR52 (*(volatile uint8_t *)(&_MBAR[0x774])) +#define MCF_INTC_ICR53 (*(volatile uint8_t *)(&_MBAR[0x775])) +#define MCF_INTC_ICR54 (*(volatile uint8_t *)(&_MBAR[0x776])) +#define MCF_INTC_ICR55 (*(volatile uint8_t *)(&_MBAR[0x777])) +#define MCF_INTC_ICR56 (*(volatile uint8_t *)(&_MBAR[0x778])) +#define MCF_INTC_ICR57 (*(volatile uint8_t *)(&_MBAR[0x779])) +#define MCF_INTC_ICR58 (*(volatile uint8_t *)(&_MBAR[0x77A])) +#define MCF_INTC_ICR59 (*(volatile uint8_t *)(&_MBAR[0x77B])) +#define MCF_INTC_ICR60 (*(volatile uint8_t *)(&_MBAR[0x77C])) +#define MCF_INTC_ICR61 (*(volatile uint8_t *)(&_MBAR[0x77D])) +#define MCF_INTC_ICR62 (*(volatile uint8_t *)(&_MBAR[0x77E])) +#define MCF_INTC_ICR63 (*(volatile uint8_t *)(&_MBAR[0x77F])) +#define MCF_INTC_SWIACK (*(volatile uint8_t *)(&_MBAR[0x7E0])) +#define MCF_INTC_L1IACK (*(volatile uint8_t *)(&_MBAR[0x7E4])) +#define MCF_INTC_L2IACK (*(volatile uint8_t *)(&_MBAR[0x7E8])) +#define MCF_INTC_L3IACK (*(volatile uint8_t *)(&_MBAR[0x7EC])) +#define MCF_INTC_L4IACK (*(volatile uint8_t *)(&_MBAR[0x7F0])) +#define MCF_INTC_L5IACK (*(volatile uint8_t *)(&_MBAR[0x7F4])) +#define MCF_INTC_L6IACK (*(volatile uint8_t *)(&_MBAR[0x7F8])) +#define MCF_INTC_L7IACK (*(volatile uint8_t *)(&_MBAR[0x7FC])) +#define MCF_INTC_ICR(x) (*(volatile uint8_t *)(&_MBAR[0x741 + ((x-1)*0x1)])) +#define MCF_INTC_LIACK(x) (*(volatile uint8_t *)(&_MBAR[0x7E4 + ((x-1)*0x4)])) + + +/* Bit definitions and macros for MCF_INTC_IPRH */ +#define MCF_INTC_IPRH_INT32 (0x1) +#define MCF_INTC_IPRH_INT33 (0x2) +#define MCF_INTC_IPRH_INT34 (0x4) +#define MCF_INTC_IPRH_INT35 (0x8) +#define MCF_INTC_IPRH_INT36 (0x10) +#define MCF_INTC_IPRH_INT37 (0x20) +#define MCF_INTC_IPRH_INT38 (0x40) +#define MCF_INTC_IPRH_INT39 (0x80) +#define MCF_INTC_IPRH_INT40 (0x100) +#define MCF_INTC_IPRH_INT41 (0x200) +#define MCF_INTC_IPRH_INT42 (0x400) +#define MCF_INTC_IPRH_INT43 (0x800) +#define MCF_INTC_IPRH_INT44 (0x1000) +#define MCF_INTC_IPRH_INT45 (0x2000) +#define MCF_INTC_IPRH_INT46 (0x4000) +#define MCF_INTC_IPRH_INT47 (0x8000) +#define MCF_INTC_IPRH_INT48 (0x10000) +#define MCF_INTC_IPRH_INT49 (0x20000) +#define MCF_INTC_IPRH_INT50 (0x40000) +#define MCF_INTC_IPRH_INT51 (0x80000) +#define MCF_INTC_IPRH_INT52 (0x100000) +#define MCF_INTC_IPRH_INT53 (0x200000) +#define MCF_INTC_IPRH_INT54 (0x400000) +#define MCF_INTC_IPRH_INT55 (0x800000) +#define MCF_INTC_IPRH_INT56 (0x1000000) +#define MCF_INTC_IPRH_INT57 (0x2000000) +#define MCF_INTC_IPRH_INT58 (0x4000000) +#define MCF_INTC_IPRH_INT59 (0x8000000) +#define MCF_INTC_IPRH_INT60 (0x10000000) +#define MCF_INTC_IPRH_INT61 (0x20000000) +#define MCF_INTC_IPRH_INT62 (0x40000000) +#define MCF_INTC_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IPRL */ +#define MCF_INTC_IPRL_INT1 (0x2) +#define MCF_INTC_IPRL_INT2 (0x4) +#define MCF_INTC_IPRL_INT3 (0x8) +#define MCF_INTC_IPRL_INT4 (0x10) +#define MCF_INTC_IPRL_INT5 (0x20) +#define MCF_INTC_IPRL_INT6 (0x40) +#define MCF_INTC_IPRL_INT7 (0x80) +#define MCF_INTC_IPRL_INT8 (0x100) +#define MCF_INTC_IPRL_INT9 (0x200) +#define MCF_INTC_IPRL_INT10 (0x400) +#define MCF_INTC_IPRL_INT11 (0x800) +#define MCF_INTC_IPRL_INT12 (0x1000) +#define MCF_INTC_IPRL_INT13 (0x2000) +#define MCF_INTC_IPRL_INT14 (0x4000) +#define MCF_INTC_IPRL_INT15 (0x8000) +#define MCF_INTC_IPRL_INT16 (0x10000) +#define MCF_INTC_IPRL_INT17 (0x20000) +#define MCF_INTC_IPRL_INT18 (0x40000) +#define MCF_INTC_IPRL_INT19 (0x80000) +#define MCF_INTC_IPRL_INT20 (0x100000) +#define MCF_INTC_IPRL_INT21 (0x200000) +#define MCF_INTC_IPRL_INT22 (0x400000) +#define MCF_INTC_IPRL_INT23 (0x800000) +#define MCF_INTC_IPRL_INT24 (0x1000000) +#define MCF_INTC_IPRL_INT25 (0x2000000) +#define MCF_INTC_IPRL_INT26 (0x4000000) +#define MCF_INTC_IPRL_INT27 (0x8000000) +#define MCF_INTC_IPRL_INT28 (0x10000000) +#define MCF_INTC_IPRL_INT29 (0x20000000) +#define MCF_INTC_IPRL_INT30 (0x40000000) +#define MCF_INTC_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRH */ +#define MCF_INTC_IMRH_INT_MASK32 (0x1) +#define MCF_INTC_IMRH_INT_MASK33 (0x2) +#define MCF_INTC_IMRH_INT_MASK34 (0x4) +#define MCF_INTC_IMRH_INT_MASK35 (0x8) +#define MCF_INTC_IMRH_INT_MASK36 (0x10) +#define MCF_INTC_IMRH_INT_MASK37 (0x20) +#define MCF_INTC_IMRH_INT_MASK38 (0x40) +#define MCF_INTC_IMRH_INT_MASK39 (0x80) +#define MCF_INTC_IMRH_INT_MASK40 (0x100) +#define MCF_INTC_IMRH_INT_MASK41 (0x200) +#define MCF_INTC_IMRH_INT_MASK42 (0x400) +#define MCF_INTC_IMRH_INT_MASK43 (0x800) +#define MCF_INTC_IMRH_INT_MASK44 (0x1000) +#define MCF_INTC_IMRH_INT_MASK45 (0x2000) +#define MCF_INTC_IMRH_INT_MASK46 (0x4000) +#define MCF_INTC_IMRH_INT_MASK47 (0x8000) +#define MCF_INTC_IMRH_INT_MASK48 (0x10000) +#define MCF_INTC_IMRH_INT_MASK49 (0x20000) +#define MCF_INTC_IMRH_INT_MASK50 (0x40000) +#define MCF_INTC_IMRH_INT_MASK51 (0x80000) +#define MCF_INTC_IMRH_INT_MASK52 (0x100000) +#define MCF_INTC_IMRH_INT_MASK53 (0x200000) +#define MCF_INTC_IMRH_INT_MASK54 (0x400000) +#define MCF_INTC_IMRH_INT_MASK55 (0x800000) +#define MCF_INTC_IMRH_INT_MASK56 (0x1000000) +#define MCF_INTC_IMRH_INT_MASK57 (0x2000000) +#define MCF_INTC_IMRH_INT_MASK58 (0x4000000) +#define MCF_INTC_IMRH_INT_MASK59 (0x8000000) +#define MCF_INTC_IMRH_INT_MASK60 (0x10000000) +#define MCF_INTC_IMRH_INT_MASK61 (0x20000000) +#define MCF_INTC_IMRH_INT_MASK62 (0x40000000) +#define MCF_INTC_IMRH_INT_MASK63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRL */ +#define MCF_INTC_IMRL_MASKALL (0x1) +#define MCF_INTC_IMRL_INT_MASK1 (0x2) +#define MCF_INTC_IMRL_INT_MASK2 (0x4) +#define MCF_INTC_IMRL_INT_MASK3 (0x8) +#define MCF_INTC_IMRL_INT_MASK4 (0x10) +#define MCF_INTC_IMRL_INT_MASK5 (0x20) +#define MCF_INTC_IMRL_INT_MASK6 (0x40) +#define MCF_INTC_IMRL_INT_MASK7 (0x80) +#define MCF_INTC_IMRL_INT_MASK8 (0x100) +#define MCF_INTC_IMRL_INT_MASK9 (0x200) +#define MCF_INTC_IMRL_INT_MASK10 (0x400) +#define MCF_INTC_IMRL_INT_MASK11 (0x800) +#define MCF_INTC_IMRL_INT_MASK12 (0x1000) +#define MCF_INTC_IMRL_INT_MASK13 (0x2000) +#define MCF_INTC_IMRL_INT_MASK14 (0x4000) +#define MCF_INTC_IMRL_INT_MASK15 (0x8000) +#define MCF_INTC_IMRL_INT_MASK16 (0x10000) +#define MCF_INTC_IMRL_INT_MASK17 (0x20000) +#define MCF_INTC_IMRL_INT_MASK18 (0x40000) +#define MCF_INTC_IMRL_INT_MASK19 (0x80000) +#define MCF_INTC_IMRL_INT_MASK20 (0x100000) +#define MCF_INTC_IMRL_INT_MASK21 (0x200000) +#define MCF_INTC_IMRL_INT_MASK22 (0x400000) +#define MCF_INTC_IMRL_INT_MASK23 (0x800000) +#define MCF_INTC_IMRL_INT_MASK24 (0x1000000) +#define MCF_INTC_IMRL_INT_MASK25 (0x2000000) +#define MCF_INTC_IMRL_INT_MASK26 (0x4000000) +#define MCF_INTC_IMRL_INT_MASK27 (0x8000000) +#define MCF_INTC_IMRL_INT_MASK28 (0x10000000) +#define MCF_INTC_IMRL_INT_MASK29 (0x20000000) +#define MCF_INTC_IMRL_INT_MASK30 (0x40000000) +#define MCF_INTC_IMRL_INT_MASK31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCH */ +#define MCF_INTC_INTFRCH_INTFRC32 (0x1) +#define MCF_INTC_INTFRCH_INTFRC33 (0x2) +#define MCF_INTC_INTFRCH_INTFRC34 (0x4) +#define MCF_INTC_INTFRCH_INTFRC35 (0x8) +#define MCF_INTC_INTFRCH_INTFRC36 (0x10) +#define MCF_INTC_INTFRCH_INTFRC37 (0x20) +#define MCF_INTC_INTFRCH_INTFRC38 (0x40) +#define MCF_INTC_INTFRCH_INTFRC39 (0x80) +#define MCF_INTC_INTFRCH_INTFRC40 (0x100) +#define MCF_INTC_INTFRCH_INTFRC41 (0x200) +#define MCF_INTC_INTFRCH_INTFRC42 (0x400) +#define MCF_INTC_INTFRCH_INTFRC43 (0x800) +#define MCF_INTC_INTFRCH_INTFRC44 (0x1000) +#define MCF_INTC_INTFRCH_INTFRC45 (0x2000) +#define MCF_INTC_INTFRCH_INTFRC46 (0x4000) +#define MCF_INTC_INTFRCH_INTFRC47 (0x8000) +#define MCF_INTC_INTFRCH_INTFRC48 (0x10000) +#define MCF_INTC_INTFRCH_INTFRC49 (0x20000) +#define MCF_INTC_INTFRCH_INTFRC50 (0x40000) +#define MCF_INTC_INTFRCH_INTFRC51 (0x80000) +#define MCF_INTC_INTFRCH_INTFRC52 (0x100000) +#define MCF_INTC_INTFRCH_INTFRC53 (0x200000) +#define MCF_INTC_INTFRCH_INTFRC54 (0x400000) +#define MCF_INTC_INTFRCH_INTFRC55 (0x800000) +#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000) +#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000) +#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000) +#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000) +#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) +#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) +#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) +#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCL */ +#define MCF_INTC_INTFRCL_INTFRC1 (0x2) +#define MCF_INTC_INTFRCL_INTFRC2 (0x4) +#define MCF_INTC_INTFRCL_INTFRC3 (0x8) +#define MCF_INTC_INTFRCL_INTFRC4 (0x10) +#define MCF_INTC_INTFRCL_INTFRC5 (0x20) +#define MCF_INTC_INTFRCL_INTFRC6 (0x40) +#define MCF_INTC_INTFRCL_INTFRC7 (0x80) +#define MCF_INTC_INTFRCL_INTFRC8 (0x100) +#define MCF_INTC_INTFRCL_INTFRC9 (0x200) +#define MCF_INTC_INTFRCL_INTFRC10 (0x400) +#define MCF_INTC_INTFRCL_INTFRC11 (0x800) +#define MCF_INTC_INTFRCL_INTFRC12 (0x1000) +#define MCF_INTC_INTFRCL_INTFRC13 (0x2000) +#define MCF_INTC_INTFRCL_INTFRC14 (0x4000) +#define MCF_INTC_INTFRCL_INTFRC15 (0x8000) +#define MCF_INTC_INTFRCL_INTFRC16 (0x10000) +#define MCF_INTC_INTFRCL_INTFRC17 (0x20000) +#define MCF_INTC_INTFRCL_INTFRC18 (0x40000) +#define MCF_INTC_INTFRCL_INTFRC19 (0x80000) +#define MCF_INTC_INTFRCL_INTFRC20 (0x100000) +#define MCF_INTC_INTFRCL_INTFRC21 (0x200000) +#define MCF_INTC_INTFRCL_INTFRC22 (0x400000) +#define MCF_INTC_INTFRCL_INTFRC23 (0x800000) +#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000) +#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000) +#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000) +#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000) +#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) +#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) +#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) +#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IRLR */ +#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1) + +/* Bit definitions and macros for MCF_INTC_IACKLPR */ +#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0) +#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4) + +/* Bit definitions and macros for MCF_INTC_ICR */ +#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0) +#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3) + +/* Bit definitions and macros for MCF_INTC_SWIACK */ +#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_INTC_LIACK */ +#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) + + +#endif /* __MCF5475_INTC_H__ */ diff --git a/include/MCF5475_PCI.h b/include/MCF5475_PCI.h new file mode 100644 index 0000000..3eb3341 --- /dev/null +++ b/include/MCF5475_PCI.h @@ -0,0 +1,376 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PCI_H__ +#define __MCF5475_PCI_H__ + + +/********************************************************************* +* +* PCI Bus Controller (PCI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PCI_PCIIDR (*(volatile uint32_t*)(&_MBAR[0xB00])) +#define MCF_PCI_PCISCR (*(volatile uint32_t*)(&_MBAR[0xB04])) +#define MCF_PCI_PCICCRIR (*(volatile uint32_t*)(&_MBAR[0xB08])) +#define MCF_PCI_PCICR1 (*(volatile uint32_t*)(&_MBAR[0xB0C])) +#define MCF_PCI_PCIBAR0 (*(volatile uint32_t*)(&_MBAR[0xB10])) +#define MCF_PCI_PCIBAR1 (*(volatile uint32_t*)(&_MBAR[0xB14])) +#define MCF_PCI_PCICCPR (*(volatile uint32_t*)(&_MBAR[0xB28])) +#define MCF_PCI_PCISID (*(volatile uint32_t*)(&_MBAR[0xB2C])) +#define MCF_PCI_PCICR2 (*(volatile uint32_t*)(&_MBAR[0xB3C])) +#define MCF_PCI_PCIGSCR (*(volatile uint32_t*)(&_MBAR[0xB60])) +#define MCF_PCI_PCITBATR0 (*(volatile uint32_t*)(&_MBAR[0xB64])) +#define MCF_PCI_PCITBATR1 (*(volatile uint32_t*)(&_MBAR[0xB68])) +#define MCF_PCI_PCITCR (*(volatile uint32_t*)(&_MBAR[0xB6C])) +#define MCF_PCI_PCIIW0BTAR (*(volatile uint32_t*)(&_MBAR[0xB70])) +#define MCF_PCI_PCIIW1BTAR (*(volatile uint32_t*)(&_MBAR[0xB74])) +#define MCF_PCI_PCIIW2BTAR (*(volatile uint32_t*)(&_MBAR[0xB78])) +#define MCF_PCI_PCIIWCR (*(volatile uint32_t*)(&_MBAR[0xB80])) +#define MCF_PCI_PCIICR (*(volatile uint32_t*)(&_MBAR[0xB84])) +#define MCF_PCI_PCIISR (*(volatile uint32_t*)(&_MBAR[0xB88])) +#define MCF_PCI_PCICAR (*(volatile uint32_t*)(&_MBAR[0xBF8])) +#define MCF_PCI_PCITPSR (*(volatile uint32_t*)(&_MBAR[0x8400])) +#define MCF_PCI_PCITSAR (*(volatile uint32_t*)(&_MBAR[0x8404])) +#define MCF_PCI_PCITTCR (*(volatile uint32_t*)(&_MBAR[0x8408])) +#define MCF_PCI_PCITER (*(volatile uint32_t*)(&_MBAR[0x840C])) +#define MCF_PCI_PCITNAR (*(volatile uint32_t*)(&_MBAR[0x8410])) +#define MCF_PCI_PCITLWR (*(volatile uint32_t*)(&_MBAR[0x8414])) +#define MCF_PCI_PCITDCR (*(volatile uint32_t*)(&_MBAR[0x8418])) +#define MCF_PCI_PCITSR (*(volatile uint32_t*)(&_MBAR[0x841C])) +#define MCF_PCI_PCITFDR (*(volatile uint32_t*)(&_MBAR[0x8440])) +#define MCF_PCI_PCITFSR (*(volatile uint32_t*)(&_MBAR[0x8444])) +#define MCF_PCI_PCITFCR (*(volatile uint32_t*)(&_MBAR[0x8448])) +#define MCF_PCI_PCITFAR (*(volatile uint32_t*)(&_MBAR[0x844C])) +#define MCF_PCI_PCITFRPR (*(volatile uint32_t*)(&_MBAR[0x8450])) +#define MCF_PCI_PCITFWPR (*(volatile uint32_t*)(&_MBAR[0x8454])) +#define MCF_PCI_PCIRPSR (*(volatile uint32_t*)(&_MBAR[0x8480])) +#define MCF_PCI_PCIRSAR (*(volatile uint32_t*)(&_MBAR[0x8484])) +#define MCF_PCI_PCIRTCR (*(volatile uint32_t*)(&_MBAR[0x8488])) +#define MCF_PCI_PCIRER (*(volatile uint32_t*)(&_MBAR[0x848C])) +#define MCF_PCI_PCIRNAR (*(volatile uint32_t*)(&_MBAR[0x8490])) +#define MCF_PCI_PCIRDCR (*(volatile uint32_t*)(&_MBAR[0x8498])) +#define MCF_PCI_PCIRSR (*(volatile uint32_t*)(&_MBAR[0x849C])) +#define MCF_PCI_PCIRFDR (*(volatile uint32_t*)(&_MBAR[0x84C0])) +#define MCF_PCI_PCIRFSR (*(volatile uint32_t*)(&_MBAR[0x84C4])) +#define MCF_PCI_PCIRFCR (*(volatile uint32_t*)(&_MBAR[0x84C8])) +#define MCF_PCI_PCIRFAR (*(volatile uint32_t*)(&_MBAR[0x84CC])) +#define MCF_PCI_PCIRFRPR (*(volatile uint32_t*)(&_MBAR[0x84D0])) +#define MCF_PCI_PCIRFWPR (*(volatile uint32_t*)(&_MBAR[0x84D4])) + + +/* Bit definitions and macros for MCF_PCI_PCIIDR */ +#define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCISCR */ +#define MCF_PCI_PCISCR_IO (0x1) +#define MCF_PCI_PCISCR_M (0x2) +#define MCF_PCI_PCISCR_B (0x4) +#define MCF_PCI_PCISCR_SP (0x8) +#define MCF_PCI_PCISCR_MW (0x10) +#define MCF_PCI_PCISCR_V (0x20) +#define MCF_PCI_PCISCR_PER (0x40) +#define MCF_PCI_PCISCR_ST (0x80) +#define MCF_PCI_PCISCR_S (0x100) +#define MCF_PCI_PCISCR_F (0x200) +#define MCF_PCI_PCISCR_C (0x100000) +#define MCF_PCI_PCISCR_66M (0x200000) +#define MCF_PCI_PCISCR_R (0x400000) +#define MCF_PCI_PCISCR_FC (0x800000) +#define MCF_PCI_PCISCR_DP (0x1000000) +#define MCF_PCI_PCISCR_DT(x) (((x)&0x3)<<0x19) +#define MCF_PCI_PCISCR_TS (0x8000000) +#define MCF_PCI_PCISCR_TR (0x10000000) +#define MCF_PCI_PCISCR_MA (0x20000000) +#define MCF_PCI_PCISCR_SE (0x40000000) +#define MCF_PCI_PCISCR_PE (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCICCRIR */ +#define MCF_PCI_PCICCRIR_REVISIONID(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0xFFFFFF)<<0x8) + +/* Bit definitions and macros for MCF_PCI_PCICR1 */ +#define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICR1_BIST(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIBAR0 */ +#define MCF_PCI_PCIBAR0_IOM (0x1) +#define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x3)<<0x1) +#define MCF_PCI_PCIBAR0_PREF (0x8) +#define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x3FFF)<<0x12) + +/* Bit definitions and macros for MCF_PCI_PCIBAR1 */ +#define MCF_PCI_PCIBAR1_IOM (0x1) +#define MCF_PCI_PCIBAR1_RANGE(x) (((x)&0x3)<<0x1) +#define MCF_PCI_PCIBAR1_PREF (0x8) +#define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_PCI_PCICCPR */ +#define MCF_PCI_PCICCPR_PCICCP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCISID */ +#define MCF_PCI_PCISID_VENDORID(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCICR2 */ +#define MCF_PCI_PCICR2_INTLINE(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICR2_INTPIN(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCICR2_MINGNT(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIGSCR */ +#define MCF_PCI_PCIGSCR_PR (0x1) +#define MCF_PCI_PCIGSCR_SEE (0x1000) +#define MCF_PCI_PCIGSCR_PEE (0x2000) +#define MCF_PCI_PCIGSCR_CLKINRESERVED(x) (((x)&0x7)<<0x10) +#define MCF_PCI_PCIGSCR_XLB2CLKIN(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCIGSCR_SE (0x10000000) +#define MCF_PCI_PCIGSCR_PE (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCITBATR0 */ +#define MCF_PCI_PCITBATR0_EN (0x1) +#define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x3FFF)<<0x12) + +/* Bit definitions and macros for MCF_PCI_PCITBATR1 */ +#define MCF_PCI_PCITBATR1_EN (0x1) +#define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_PCI_PCITCR */ +#define MCF_PCI_PCITCR_P (0x10000) +#define MCF_PCI_PCITCR_LD (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */ +#define MCF_PCI_PCIIW0BTAR_WTA0(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW0BTAR_WAM0(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW0BTAR_WBA0(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */ +#define MCF_PCI_PCIIW1BTAR_WTA1(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW1BTAR_WAM1(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW1BTAR_WBA1(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */ +#define MCF_PCI_PCIIW2BTAR_WTA2(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW2BTAR_WAM2(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW2BTAR_WBA2(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIWCR */ +#define MCF_PCI_PCIIWCR_WINCTRL2_E (0x100) +#define MCF_PCI_PCIIWCR_WINCTRL2_PRC(x) (((x)&0x3)<<0x9) +#define MCF_PCI_PCIIWCR_WINCTRL2_IOM (0x800) +#define MCF_PCI_PCIIWCR_WINCTRL1_E (0x10000) +#define MCF_PCI_PCIIWCR_WINCTRL1_PRC(x) (((x)&0x3)<<0x11) +#define MCF_PCI_PCIIWCR_WINCTRL1_IOM (0x80000) +#define MCF_PCI_PCIIWCR_WINCTRL0_E (0x1000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_PRC(x) (((x)&0x3)<<0x19) +#define MCF_PCI_PCIIWCR_WINCTRL0_IOM (0x8000000) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x100) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x300) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x500) +#define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x900) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x10000) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x30000) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x50000) +#define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x90000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x1000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x3000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x5000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x9000000) + +/* Bit definitions and macros for MCF_PCI_PCIICR */ +#define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCIICR_TAE (0x1000000) +#define MCF_PCI_PCIICR_IAE (0x2000000) +#define MCF_PCI_PCIICR_REE (0x4000000) + +/* Bit definitions and macros for MCF_PCI_PCIISR */ +#define MCF_PCI_PCIISR_TA (0x1000000) +#define MCF_PCI_PCIISR_IA (0x2000000) +#define MCF_PCI_PCIISR_RE (0x4000000) + +/* Bit definitions and macros for MCF_PCI_PCICAR */ +#define MCF_PCI_PCICAR_DWORD(x) (((x)&0x3F)<<0x2) +#define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x1F)<<0xB) +#define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICAR_E (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITPSR */ +#define MCF_PCI_PCITPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCITSAR */ +#define MCF_PCI_PCITSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITTCR */ +#define MCF_PCI_PCITTCR_DI (0x1) +#define MCF_PCI_PCITTCR_W (0x10) +#define MCF_PCI_PCITTCR_MAXBEATS(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCITTCR_MAXRETRY(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCITTCR_PCICMD(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCITER */ +#define MCF_PCI_PCITER_NE (0x10000) +#define MCF_PCI_PCITER_IAE (0x20000) +#define MCF_PCI_PCITER_TAE (0x40000) +#define MCF_PCI_PCITER_RE (0x80000) +#define MCF_PCI_PCITER_SE (0x100000) +#define MCF_PCI_PCITER_FEE (0x200000) +#define MCF_PCI_PCITER_ME (0x1000000) +#define MCF_PCI_PCITER_BE (0x8000000) +#define MCF_PCI_PCITER_CM (0x10000000) +#define MCF_PCI_PCITER_RF (0x40000000) +#define MCF_PCI_PCITER_RC (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITNAR */ +#define MCF_PCI_PCITNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITLWR */ +#define MCF_PCI_PCITLWR_LASTWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITDCR */ +#define MCF_PCI_PCITDCR_PKTSDONE(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCITDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCITSR */ +#define MCF_PCI_PCITSR_IA (0x10000) +#define MCF_PCI_PCITSR_TA (0x20000) +#define MCF_PCI_PCITSR_RE (0x40000) +#define MCF_PCI_PCITSR_SE (0x80000) +#define MCF_PCI_PCITSR_FE (0x100000) +#define MCF_PCI_PCITSR_BE1 (0x200000) +#define MCF_PCI_PCITSR_BE2 (0x400000) +#define MCF_PCI_PCITSR_BE3 (0x800000) +#define MCF_PCI_PCITSR_NT (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCITFDR */ +#define MCF_PCI_PCITFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFSR */ +#define MCF_PCI_PCITFSR_EMPTY (0x10000) +#define MCF_PCI_PCITFSR_ALARM (0x20000) +#define MCF_PCI_PCITFSR_FULL (0x40000) +#define MCF_PCI_PCITFSR_FR (0x80000) +#define MCF_PCI_PCITFSR_OF (0x100000) +#define MCF_PCI_PCITFSR_UF (0x200000) +#define MCF_PCI_PCITFSR_RXW (0x400000) +#define MCF_PCI_PCITFSR_FAE (0x800000) +#define MCF_PCI_PCITFSR_TXW (0x40000000) +#define MCF_PCI_PCITFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITFCR */ +#define MCF_PCI_PCITFCR_TXW_MASK (0x40000) +#define MCF_PCI_PCITFCR_OF_MASK (0x80000) +#define MCF_PCI_PCITFCR_UF_MASK (0x100000) +#define MCF_PCI_PCITFCR_RXW_MASK (0x200000) +#define MCF_PCI_PCITFCR_FAE_MASK (0x400000) +#define MCF_PCI_PCITFCR_IP_MASK (0x800000) +#define MCF_PCI_PCITFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCITFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCITFAR */ +#define MCF_PCI_PCITFAR_ALARM(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFRPR */ +#define MCF_PCI_PCITFRPR_READPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFWPR */ +#define MCF_PCI_PCITFWPR_WRITEPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRPSR */ +#define MCF_PCI_PCIRPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCIRSAR */ +#define MCF_PCI_PCIRSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRTCR */ +#define MCF_PCI_PCIRTCR_DI (0x1) +#define MCF_PCI_PCIRTCR_W (0x10) +#define MCF_PCI_PCIRTCR_MAXBEATS(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCIRTCR_FB (0x1000) +#define MCF_PCI_PCIRTCR_MAXRETRY(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIRTCR_PCICMD(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIRER */ +#define MCF_PCI_PCIRER_NE (0x10000) +#define MCF_PCI_PCIRER_IAE (0x20000) +#define MCF_PCI_PCIRER_TAE (0x40000) +#define MCF_PCI_PCIRER_RE (0x80000) +#define MCF_PCI_PCIRER_SE (0x100000) +#define MCF_PCI_PCIRER_FEE (0x200000) +#define MCF_PCI_PCIRER_ME (0x1000000) +#define MCF_PCI_PCIRER_BE (0x8000000) +#define MCF_PCI_PCIRER_CM (0x10000000) +#define MCF_PCI_PCIRER_FE (0x20000000) +#define MCF_PCI_PCIRER_RF (0x40000000) +#define MCF_PCI_PCIRER_RC (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCIRNAR */ +#define MCF_PCI_PCIRNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRDCR */ +#define MCF_PCI_PCIRDCR_PKTSDONE(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCIRDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCIRSR */ +#define MCF_PCI_PCIRSR_IA (0x10000) +#define MCF_PCI_PCIRSR_TA (0x20000) +#define MCF_PCI_PCIRSR_RE (0x40000) +#define MCF_PCI_PCIRSR_SE (0x80000) +#define MCF_PCI_PCIRSR_FE (0x100000) +#define MCF_PCI_PCIRSR_BE1 (0x200000) +#define MCF_PCI_PCIRSR_BE2 (0x400000) +#define MCF_PCI_PCIRSR_BE3 (0x800000) +#define MCF_PCI_PCIRSR_NT (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFDR */ +#define MCF_PCI_PCIRFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFSR */ +#define MCF_PCI_PCIRFSR_EMPTY (0x10000) +#define MCF_PCI_PCIRFSR_ALARM (0x20000) +#define MCF_PCI_PCIRFSR_FULL (0x40000) +#define MCF_PCI_PCIRFSR_FR (0x80000) +#define MCF_PCI_PCIRFSR_OF (0x100000) +#define MCF_PCI_PCIRFSR_UF (0x200000) +#define MCF_PCI_PCIRFSR_RXW (0x400000) +#define MCF_PCI_PCIRFSR_FAE (0x800000) +#define MCF_PCI_PCIRFSR_TXW (0x40000000) +#define MCF_PCI_PCIRFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFCR */ +#define MCF_PCI_PCIRFCR_TXW_MASK (0x40000) +#define MCF_PCI_PCIRFCR_OF_MASK (0x80000) +#define MCF_PCI_PCIRFCR_UF_MASK (0x100000) +#define MCF_PCI_PCIRFCR_RXW_MASK (0x200000) +#define MCF_PCI_PCIRFCR_FAE_MASK (0x400000) +#define MCF_PCI_PCIRFCR_IP_MASK (0x800000) +#define MCF_PCI_PCIRFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCIRFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFAR */ +#define MCF_PCI_PCIRFAR_ALARM(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFRPR */ +#define MCF_PCI_PCIRFRPR_READPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFWPR */ +#define MCF_PCI_PCIRFWPR_WRITEPTR(x) (((x)&0x7F)<<0) + + +#endif /* __MCF5475_PCI_H__ */ diff --git a/include/arp.h b/include/arp.h new file mode 100644 index 0000000..9f8a846 --- /dev/null +++ b/include/arp.h @@ -0,0 +1,99 @@ +/* + * File: arp.h + * Purpose: ARP definitions. + * + * Notes: + */ + +#ifndef _ARP_H +#define _ARP_H + +/********************************************************************/ + +/* + * This data definition is defined for Ethernet only! + */ +typedef struct +{ + uint16_t ar_hrd; + uint16_t ar_pro; + uint8_t ar_hln; + uint8_t ar_pln; + uint16_t opcode; + uint8_t ar_sha[6]; /* ethernet hw address */ + uint8_t ar_spa[4]; /* ip address */ + uint8_t ar_tha[6]; /* ethernet hw address */ + uint8_t ar_tpa[4]; /* ip address */ +} arp_frame_hdr; + +#define ARP_HDR_LEN sizeof(arp_frame_hdr) + +/* + * ARP table entry definition. Note that this table only designed + * with Ethernet and IP in mind. + */ +#define MAX_HWA_SIZE (6) /* 6 is enough for Ethernet address */ +#define MAX_PA_SIZE (4) /* 4 is enough for Protocol address */ +typedef struct +{ + uint16_t protocol; + uint8_t hwa_size; + uint8_t hwa[MAX_HWA_SIZE]; + uint8_t pa_size; + uint8_t pa[MAX_PA_SIZE]; + int longevity; +} ARPENTRY; +#define MAX_ARP_ENTRY (10) + +typedef struct +{ + unsigned int tab_size; + ARPENTRY table[MAX_ARP_ENTRY]; +} ARP_INFO; + +#define ARP_ENTRY_EMPTY (0) +#define ARP_ENTRY_PERM (1) +#define ARP_ENTRY_TEMP (2) + + +#define ETHERNET (1) +#define ARP_REQUEST (1) +#define ARP_REPLY (2) + +#define ARP_TIMEOUT (1) /* Timeout in seconds */ + +/* Protocol Header information */ +#define ARP_HDR_OFFSET ETH_HDR_LEN + +/********************************************************************/ + +uint8_t * +arp_get_mypa (void); + +uint8_t * +arp_get_myha (void); + +uint8_t * +arp_get_broadcast (void); + +void +arp_merge (ARP_INFO *, uint16_t, int, uint8_t *, int, uint8_t *, int); + +void +arp_remove (ARP_INFO *, uint16_t, uint8_t *, uint8_t *); + +void +arp_request (NIF *, uint8_t *); + +void +arp_handler (NIF *, NBUF *); + +uint8_t * +arp_resolve (NIF *, uint16_t, uint8_t *); + +void +arp_init (ARP_INFO *); + +/********************************************************************/ + +#endif /* _ARP_H */ diff --git a/include/bas_printf.h b/include/bas_printf.h new file mode 100644 index 0000000..9d6d708 --- /dev/null +++ b/include/bas_printf.h @@ -0,0 +1,42 @@ +/* + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + */ + +#ifndef _BAS_PRINTF_H_ +#define _BAS_PRINTF_H_ +#include +#include +#include "MCF5475.h" + +extern void xvsnprintf(char *str, size_t size, const char *fmt, va_list va); +extern void xvprintf(const char *fmt, va_list va); +extern void xprintf(const char *fmt, ...); +extern void xsnprintf(char *str, size_t size, const char *fmt, ...); +extern int sprintf(char *str, const char *format, ...); + +extern bool conoutstat(void); +extern bool coninstat(void); +extern void xputchar(int c); +extern char xgetchar(void); + + +extern void display_progress(void); +extern void hexdump(uint8_t buffer[], int size); + + +#endif /* _BAS_PRINTF_H_ */ diff --git a/include/conout.h b/include/conout.h new file mode 100755 index 0000000..1785948 --- /dev/null +++ b/include/conout.h @@ -0,0 +1,63 @@ +#ifndef __CONOUT_H__ +#define __CONOUT_H__ + +#include "bas_types.h" + +/* + * conout.h - lowlevel color model dependent screen handling routines + * + * + * Copyright (C) 2004-2016 by Authors: + * + * Authors: + * MAD Martin Doering + * + * This file is distributed under the GPL, version 2 or at your + * option any later version. See doc/license.txt for details. + */ + + + +/* Defines for cursor */ +#define M_CFLASH 0x0001 /* cursor flash 0:disabled 1:enabled */ +#define M_CSTATE 0x0002 /* cursor flash state 0:off 1:on */ +#define M_CVIS 0x0004 /* cursor visibility 0:invisible 1:visible */ + +/* + * The visibility flag is also used as a semaphore to prevent + * the interrupt-driven cursor blink logic from colliding with + * escape function/sequence cursor drawing activity. + */ + +#define M_CEOL 0x0008 /* end of line handling 0:overwrite 1:wrap */ +#define M_REVID 0x0010 /* reverse video 0:on 1:off */ +#define M_SVPOS 0x0020 /* position saved flag. 0:false, 1:true */ +#define M_CRIT 0x0040 /* reverse video 0:on 1:off */ + +/* Color related linea variables */ + +extern int16_t v_col_bg; /* current background color */ +extern int16_t v_col_fg; /* current foreground color */ + +/* Cursor related linea variables */ + +extern uint8_t *v_cur_ad; /* current cursor address */ +extern int16_t v_cur_of; /* cursor offset */ +extern int8_t v_cur_tim; /* cursor blink timer */ + +extern int8_t v_period; +extern int16_t disab_cnt; /* disable depth count. (>0 means disabled) */ +extern int8_t v_stat_0; /* video cell system status */ +extern int16_t sav_cur_x; /* saved cursor cell x */ +extern int16_t sav_cur_y; /* saved cursor cell y */ + +/* Prototypes */ + +extern void ascii_out(int); +extern void move_cursor(int, int); +extern void blank_out (int, int, int, int); +extern void invert_cell(int, int); +extern void scroll_up(int); +extern void scroll_down(int); + +#endif /* __CONOUT_H__ */ diff --git a/include/diskio.h b/include/diskio.h new file mode 100644 index 0000000..0fb3ac5 --- /dev/null +++ b/include/diskio.h @@ -0,0 +1,91 @@ +/*----------------------------------------------------------------------- +/ Low level disk interface modlue include file (C)ChaN, 2012 +/-----------------------------------------------------------------------*/ + +#ifndef _DISKIO_DEFINED +#define _DISKIO_DEFINED + +#ifdef __cplusplus +extern "C" { +#endif + +#define _USE_WRITE 1 /* 1: Enable disk_write function */ +#define _USE_IOCTL 1 /* 1: Enable disk_ioctl fucntion */ + +#include + + +/* Status of Disk Functions */ +typedef uint8_t DSTATUS; + +/* Results of Disk Functions */ +typedef enum { + RES_OK = 0, /* 0: Successful */ + RES_ERROR, /* 1: R/W Error */ + RES_WRPRT, /* 2: Write Protected */ + RES_NOTRDY, /* 3: Not Ready */ + RES_PARERR /* 4: Invalid Parameter */ +} DRESULT; + + +/*---------------------------------------*/ +/* Prototypes for disk control functions */ + + +DSTATUS disk_initialize (uint8_t); +DSTATUS disk_reset(uint8_t); +DSTATUS disk_status (uint8_t); +DRESULT disk_read (uint8_t, uint8_t*, uint32_t, uint8_t); +#if _READONLY == 0 +DRESULT disk_write (uint8_t, const uint8_t*, uint32_t, uint8_t); +#endif +DRESULT disk_ioctl (uint8_t, uint8_t, void*); + + +/* Disk Status Bits (DSTATUS) */ +#define STA_NOINIT 0x01 /* Drive not initialized */ +#define STA_NODISK 0x02 /* No medium in the drive */ +#define STA_PROTECT 0x04 /* Write protected */ + + +/* Command code for disk_ioctrl fucntion */ + +/* Generic command (used by FatFs) */ +#define CTRL_SYNC 0 /* Flush disk cache (for write functions) */ +#define GET_SECTOR_COUNT 1 /* Get media size (for only f_mkfs()) */ +#define GET_SECTOR_SIZE 2 /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */ +#define GET_BLOCK_SIZE 3 /* Get erase block size (for only f_mkfs()) */ +#define CTRL_ERASE_SECTOR 4 /* Force erased a block of sectors (for only _USE_ERASE) */ + +/* Generic command (not used by FatFs) */ +#define CTRL_POWER 5 /* Get/Set power status */ +#define CTRL_LOCK 6 /* Lock/Unlock media removal */ +#define CTRL_EJECT 7 /* Eject media */ +#define CTRL_FORMAT 8 /* Create physical format on the media */ + +/* MMC/SDC specific ioctl command */ +#define MMC_GET_TYPE 10 /* Get card type */ +#define MMC_GET_CSD 11 /* Get CSD */ +#define MMC_GET_CID 12 /* Get CID */ +#define MMC_GET_OCR 13 /* Get OCR */ +#define MMC_GET_SDSTAT 14 /* Get SD status */ + +/* ATA/CF specific ioctl command */ +#define ATA_GET_REV 20 /* Get F/W revision */ +#define ATA_GET_MODEL 21 /* Get model name */ +#define ATA_GET_SN 22 /* Get serial number */ + + +/* MMC card type flags (MMC_GET_TYPE) */ +#define CT_MMC 0x01 /* MMC ver 3 */ +#define CT_SD1 0x02 /* SD ver 1 */ +#define CT_SD2 0x04 /* SD ver 2 */ +#define CT_SDC (CT_SD1 | CT_SD2) /* SD */ +#define CT_BLOCK 0x08 /* Block addressing */ + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/include/dma.h b/include/dma.h new file mode 100644 index 0000000..2776b28 --- /dev/null +++ b/include/dma.h @@ -0,0 +1,43 @@ +/* + * spidma.h * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 26.02.2013 + * Author: Markus Fröschle + */ + +#ifndef _DMA_H_ +#define _DMA_H_ + +#include "MCF5475.h" +#include "MCD_dma.h" +#include "bas_string.h" + +void *dma_memcpy(void *dst, void *src, size_t n); +extern int dma_init(void); +extern int dma_get_channel(int requestor); +extern int dma_set_channel(int, void (*)(void)); +extern void dma_free_channel(int requestor); +extern void dma_clear_channel(int channel); +extern uint32_t dma_get_initiator(int requestor); +extern int dma_set_initiator(int initiator); +extern void dma_free_initiator(int initiator); +extern void dma_irq_enable(void); +extern void dma_irq_disable(void); +extern bool dma_interrupt_handler(void *arg1, void *arg2); + + +#endif /* _DMA_H_ */ diff --git a/include/fec.h b/include/fec.h new file mode 100644 index 0000000..c439618 --- /dev/null +++ b/include/fec.h @@ -0,0 +1,96 @@ +/* + * File: fec.h + * Purpose: Driver for the Fast Ethernet Controller (FEC) + * + * Notes: + */ + +#ifndef _FEC_H_ +#define _FEC_H_ + +/********************************************************************/ +/* MII Speed Settings */ +#define FEC_MII_10BASE_T 0 +#define FEC_MII_100BASE_TX 1 + +/* MII Duplex Settings */ +#define FEC_MII_HALF_DUPLEX 0 +#define FEC_MII_FULL_DUPLEX 1 + +/* Timeout for MII communications */ +#define FEC_MII_TIMEOUT 0x10000 + +/* External Interface Modes */ +#define FEC_MODE_7WIRE 0 +#define FEC_MODE_MII 1 +#define FEC_MODE_LOOPBACK 2 /* Internal Loopback */ + +/* + * FEC Event Log + */ +typedef struct +{ + int total; /* total count of errors */ + int hberr; /* heartbeat error */ + int babr; /* babbling receiver */ + int babt; /* babbling transmitter */ + int gra; /* graceful stop complete */ + int txf; /* transmit frame */ + int mii; /* MII */ + int lc; /* late collision */ + int rl; /* collision retry limit */ + int xfun; /* transmit FIFO underrrun */ + int xferr; /* transmit FIFO error */ + int rferr; /* receive FIFO error */ + int dtxf; /* DMA transmit frame */ + int drxf; /* DMA receive frame */ + int rfsw_inv; /* Invalid bit in RFSW */ + int rfsw_l; /* RFSW Last in Frame */ + int rfsw_m; /* RFSW Miss */ + int rfsw_bc; /* RFSW Broadcast */ + int rfsw_mc; /* RFSW Multicast */ + int rfsw_lg; /* RFSW Length Violation */ + int rfsw_no; /* RFSW Non-octet */ + int rfsw_cr; /* RFSW Bad CRC */ + int rfsw_ov; /* RFSW Overflow */ + int rfsw_tr; /* RFSW Truncated */ +} FEC_EVENT_LOG; + + +extern int fec_mii_write(uint8_t , uint8_t , uint8_t , uint16_t ); +extern int fec_mii_read(uint8_t , uint8_t , uint8_t , uint16_t *); +extern void fec_mii_init(uint8_t, uint32_t); +extern void fec_mib_init(uint8_t); +extern void fec_mib_dump(uint8_t); +extern void fec_log_init(uint8_t); +extern void fec_log_dump(uint8_t); +extern void fec_debug_dump(uint8_t); +extern void fec_duplex (uint8_t, uint8_t); +extern uint8_t fec_hash_address(const uint8_t *); +extern void fec_set_address (uint8_t ch, const uint8_t *); +extern void fec_reset (uint8_t); +extern void fec_init(uint8_t ch, uint8_t mode, const uint8_t *pa); +extern void fec_rx_start(uint8_t, int8_t *); +extern void fec_rx_restart(uint8_t); +extern void fec_rx_stop (uint8_t); +extern void fec_rx_frame(uint8_t, NIF *); +extern void fec0_rx_frame(void); +extern void fec1_rx_frame(void); +extern void fec_tx_start(uint8_t, int8_t *); +extern void fec_tx_restart(uint8_t); +extern void fec_tx_stop (uint8_t); +extern void fec0_tx_frame(void); +extern void fec1_tx_frame(void); +extern int fec_send(uint8_t, NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *); +extern int fec0_send(NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *); +extern int fec1_send(NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *); +extern void fec_irq_enable(uint8_t, uint8_t, uint8_t); +extern void fec_irq_disable(uint8_t); +extern void fec_interrupt_handler(uint8_t); +extern bool fec0_interrupt_handler(void *, void *); +extern bool fec1_interrupt_handler(void *, void *); +extern void fec_eth_setup(uint8_t, uint8_t, uint8_t, uint8_t, const uint8_t *); +extern void fec_eth_reset(uint8_t); +extern void fec_eth_stop(uint8_t); + +#endif /* _FEC_H_ */ diff --git a/include/font.h b/include/font.h new file mode 100644 index 0000000..92b9e32 --- /dev/null +++ b/include/font.h @@ -0,0 +1,100 @@ +/* + * font.h - font specific definitions + * + * Copyright (c) 2001 Lineo, Inc. + * Copyright (c) 2004 by Authors: + * + * Authors: + * MAD Martin Doering + * + * This file is distributed under the GPL, version 2 or at your + * option any later version. See doc/license.txt for details. + */ + +#ifndef FONT_H +#define FONT_H + +#include + +/* font header flags */ + +#define F_DEFAULT 1 /* this is the default font (face and size) */ +#define F_HORZ_OFF 2 /* there are left and right offset tables */ +#define F_STDFORM 4 /* is the font in standard format */ +#define F_MONOSPACE 8 /* is the font monospaced */ + +/* font style bits */ + +#define F_THICKEN 1 +#define F_LIGHT 2 +#define F_SKEW 4 +#define F_UNDER 8 +#define F_OUTLINE 16 +#define F_SHADOW 32 + +/* font specific linea variables */ + +extern const uint16_t *v_fnt_ad; /* address of current monospace font */ +extern const uint16_t *v_off_ad; /* address of font offset table */ +extern uint16_t v_fnt_nd; /* ascii code of last cell in font */ +extern uint16_t v_fnt_st; /* ascii code of first cell in font */ +extern uint16_t v_fnt_wr; /* font cell wrap */ + +/* character cell specific linea variables */ + +extern uint16_t v_cel_ht; /* cell height (width is 8) */ +extern uint16_t v_cel_mx; /* needed by MiNT: columns on the screen minus 1 */ +extern uint16_t v_cel_my; /* needed by MiNT: rows on the screen minus 1 */ +extern uint16_t v_cel_wr; /* needed by MiNT: length (in int8_ts) of a line of characters */ + +/* + * font_ring is a struct of four pointers, each of which points to + * a list of font headers linked together to form a string. + */ + +extern struct font_head *font_ring[4]; /* Ring of available fonts */ +extern int16_t font_count; /* all three fonts and NULL */ + +/* the font header descibes a font */ + +struct font_head { + int16_t font_id; + int16_t point; + int8_t name[32]; + uint16_t first_ade; + uint16_t last_ade; + uint16_t top; + uint16_t ascent; + uint16_t half; + uint16_t descent; + uint16_t bottom; + uint16_t max_char_width; + uint16_t max_cell_width; + uint16_t left_offset; /* amount character slants left when skewed */ + uint16_t right_offset; /* amount character slants right */ + uint16_t thicken; /* number of pixels to smear */ + uint16_t ul_size; /* size of the underline */ + uint16_t lighten; /* mask to and with to lighten */ + uint16_t skew; /* mask for skewing */ + uint16_t flags; + + const uint8_t *hor_table; /* horizontal offsets */ + const uint16_t *off_table; /* character offsets */ + const uint16_t *dat_table; /* character definitions */ + uint16_t form_width; + uint16_t form_height; + + struct font_head *next_font;/* pointer to next font */ + uint16_t font_seg; +}; + + + +/* prototypes */ + +void font_init(void); /* initialize BIOS font ring */ +void font_set_default(void); /* choose the default font */ + +extern struct font_head *fnt; + +#endif /* FONT_H */ diff --git a/include/i2c-algo-bit.h b/include/i2c-algo-bit.h new file mode 100644 index 0000000..92545ac --- /dev/null +++ b/include/i2c-algo-bit.h @@ -0,0 +1,55 @@ +/* ------------------------------------------------------------------------- */ +/* i2c-algo-bit.h i2c driver algorithms for bit-shift adapters */ +/* ------------------------------------------------------------------------- */ +/* Copyright (C) 1995-99 Simon G. Vogl + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ +/* ------------------------------------------------------------------------- */ + +/* With some changes from Kyösti Mälkki and even + Frodo Looijaard */ + +/* $Id: i2c-algo-bit.h,v 1.1.1.1 2012/08/16 18:43:05 mfro Exp $ */ + +#ifndef I2C_ALGO_BIT_H +#define I2C_ALGO_BIT_H + +/* --- Defines for bit-adapters --------------------------------------- */ +/* + * This struct contains the hw-dependent functions of bit-style adapters to + * manipulate the line states, and to init any hw-specific features. This is + * only used if you have more than one hw-type of adapter running. + */ +struct i2c_algo_bit_data +{ + void *data; /* private data for lowlevel routines */ + void (*setsda) (void *data, int state); + void (*setscl) (void *data, int state); + int (*getsda) (void *data); + int (*getscl) (void *data); + + /* local settings */ + int udelay; /* half-clock-cycle time in microsecs */ + /* i.e. clock is (500 / udelay) KHz */ + int mdelay; /* in millisecs, unused */ + int timeout; /* in jiffies */ +}; + +#define I2C_BIT_ADAP_MAX 16 + +int i2c_bit_add_bus(struct i2c_adapter *); +int i2c_bit_del_bus(struct i2c_adapter *); + +#endif /* I2C_ALGO_BIT_H */ diff --git a/include/i2c.h b/include/i2c.h new file mode 100644 index 0000000..4645f89 --- /dev/null +++ b/include/i2c.h @@ -0,0 +1,97 @@ +/* ------------------------------------------------------------------------- */ +/* */ +/* i2c.h - definitions for the i2c-bus interface */ +/* */ +/* ------------------------------------------------------------------------- */ +/* Copyright (C) 1995-2000 Simon G. Vogl + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ +/* ------------------------------------------------------------------------- */ + +/* With some changes from Kyösti Mälkki and + Frodo Looijaard */ + +/* $Id: i2c.h,v 1.1.1.1 2012/08/16 18:43:05 mfro Exp $ */ + +#ifndef _I2C_H +#define _I2C_H + +#include "bas_types.h" + +/* --- General options ------------------------------------------------ */ + +struct i2c_msg; +struct i2c_algorithm; +struct i2c_adapter; + +/* Transfer num messages. + */ +extern int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num); + +/* + * The following structs are for those who like to implement new bus drivers: + * i2c_algorithm is the interface to a class of hardware solutions which can + * be addressed using the same bus algorithms - i.e. bit-banging or the PCF8584 + * to name two of the most common. + */ +struct i2c_algorithm +{ + unsigned int id; + int (*master_xfer)(struct i2c_adapter *adap,struct i2c_msg *msgs, int num); + /* --- ioctl like call to set div. parameters. */ + int (*algo_control)(struct i2c_adapter *, unsigned int, unsigned long); +}; + +/* + * i2c_adapter is the structure used to identify a physical i2c bus along + * with the access algorithms necessary to access it. + */ +struct i2c_adapter +{ + struct i2c_algorithm *algo; /* the algorithm to access the bus */ + void *algo_data; + int timeout; + int retries; + int nr; +}; + +/* + * I2C Message - used for pure i2c transaction, also from /dev interface + */ +struct i2c_msg +{ + unsigned short addr; /* slave address */ + unsigned short flags; +#define I2C_M_TEN 0x10 /* we have a ten bit chip address */ +#define I2C_M_RD 0x01 +#define I2C_M_NOSTART 0x4000 +#define I2C_M_REV_DIR_ADDR 0x2000 +#define I2C_M_IGNORE_NAK 0x1000 +#define I2C_M_NO_RD_ACK 0x0800 + unsigned short len; /* msg length */ + unsigned char *buf; /* pointer to msg data */ +}; + +/* +extern void i2c_init(void); +extern void i2c_set_frequency(int hz); +extern int i2c_read(int address, char *data, int lengt, bool repeated); +extern int i2c_read_byte(int ack); +extern int i2c_write(int address, const char *data, int length, bool repeated); +extern int i2c_write_byte(int data); +extern void i2c_start(void); +extern void i2c_stop(void); +*/ +#endif /* _I2C_H */ diff --git a/include/icmp.h b/include/icmp.h new file mode 100644 index 0000000..2231692 --- /dev/null +++ b/include/icmp.h @@ -0,0 +1,121 @@ +/* + * File: icmp.h + * Purpose: Handle Internet Control Message Protocol packets. + * + * Notes: See RFC 792 "Internet Control Message Protocol" + * for more details. + */ + +#ifndef _ICMP_H +#define _ICMP_H + +/********************************************************************/ + +typedef struct +{ + uint32_t unused; + uint8_t ih_dg; +} icmp_dest_unreachable; +#define ICMP_DEST_UNREACHABLE (3) /* type */ +#define ICMP_NET_UNREACHABLE (0) /* code */ +#define ICMP_HOST_UNREACHABLE (1) +#define ICMP_PROTOCOL_UNREACHABLE (2) +#define ICMP_PORT_UNREACHABLE (3) +#define ICMP_FRAG_NEEDED (4) +#define ICMP_ROUTE_FAILED (5) + +typedef struct +{ + uint32_t unused; + uint8_t ih_dg; +} icmp_time_exceeded; +#define ICMP_TIME_EXCEEDED (11) /* type */ +#define ICMP_TTL_EXCEEDED (0) /* code */ +#define ICMP_FRAG_TIME_EXCEEDED (1) + +typedef struct +{ + uint8_t pointer; + uint8_t unused1; + uint16_t unused2; + uint8_t ih_dg; +} icmp_parameter_problem; +#define ICMP_PARAMETER_PROBLEM (12) /* type */ +#define ICMP_POINTER (0) /* code -- not */ + +typedef struct +{ + uint32_t unused; + uint8_t ih_dg; +} icmp_source_quench; +#define ICMP_SOURCE_QUENCH (4) /* type */ + +typedef struct +{ + uint32_t gateway_addr; + uint8_t ih_dg; +} icmp_redirect; +#define ICMP_REDIRECT (5) /* type */ +#define ICMP_REDIRECT_NET (0) /* code */ +#define ICMP_REDIRECT_HOST (1) +#define ICMP_REDIRECT_TOS_NET (2) +#define ICMP_REDIRECT_TOS_HOST (3) + +typedef struct +{ + uint16_t identifier; + uint16_t sequence; + uint8_t data; +} icmp_echo; +#define ICMP_ECHO (8) /* type */ +#define ICMP_ECHO_REPLY (0) /* type */ + +typedef struct +{ + uint16_t identifier; + uint16_t sequence; +} icmp_information; +#define ICMP_INFORMATION_REQUEST (15) /* type */ +#define ICMP_INFORMATION_REPLY (16) /* type */ + +typedef struct +{ + uint16_t identifier; + uint16_t sequence; + uint32_t originate_ts; + uint32_t receive_ts; + uint32_t transmit_ts; +} icmp_timestamp; +#define ICMP_TIMESTAMP (13) /* type */ +#define ICMP_TIMESTAMP_REPLY (14) /* type */ + +typedef struct +{ + uint8_t type; + uint8_t code; + uint16_t chksum; + union + { + icmp_dest_unreachable dest_unreachable; + icmp_source_quench source_quench; + icmp_redirect redirect; + icmp_time_exceeded time_exceeded; + icmp_parameter_problem parameter_problem; + icmp_timestamp timestamp; + icmp_information information; + icmp_echo echo; + } msg; +} icmp_message; + +/********************************************************************/ + +/* Protocol Header information */ +#define ICMP_HDR_OFFSET (ETH_HDR_LEN + IP_HDR_SIZE) +#define ICMP_HDR_SIZE 8 + +void +icmp_handler(NIF *, NBUF *); + +/********************************************************************/ + +#endif /* _ICMP_H */ diff --git a/include/m54455.h b/include/m54455.h new file mode 100644 index 0000000..3f3ae24 --- /dev/null +++ b/include/m54455.h @@ -0,0 +1,50 @@ +#ifndef _M54455_H_ +#define _M54455_H_ + +/* + * m54455.h + * + * preprocessor definitions for the M54455 Freescale machine. This file should contain nothing but preprocessor + * definition that evaluate to numbers. It is intended for use in C sources as well as in linker control + * files, so care must be taken to not break the syntax of either one. + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 26.02.2013 + * Author: Markus Fröschle + */ + +#define SYSCLK 133000 + +#define BOOTFLASH_BASE_ADDRESS 0xe0000000 +#define BOOTFLASH_SIZE 0x800000 +#define BOOTFLASH_BAM (BOOTFLASH_SIZE - 1) + +#define SDRAM_START 0x40000000 /* start at address 40000000 */ +#define SDRAM_SIZE 0x10000000 /* 256 MB */ + +#ifdef COMPILE_RAM +#define TARGET_ADDRESS (SDRAM_START + SDRAM_SIZE - 0x200000) +#else +#define TARGET_ADDRESS BOOTFLASH_BASE_ADDRESS +#endif /* COMPILE_RAM */ +#define BFL_TARGET_ADDRESS 0x0100000 /* load address for basflash */ + +#define DRIVER_MEM_BUFFER_SIZE 0x100000 + +#define EMUTOS_BASE_ADDRESS 0xe0100000 + +#endif /* _M54455_H_ */ diff --git a/include/nif.h b/include/nif.h new file mode 100644 index 0000000..639d341 --- /dev/null +++ b/include/nif.h @@ -0,0 +1,49 @@ +/* + * File: nif.h + * Purpose: Definition of a Network InterFace. + * + * Notes: + */ + +#ifndef _NIF_H +#define _NIF_H + +/* + * Maximum number of supported protoocls: IP, ARP, RARP + */ +#define MAX_SUP_PROTO (3) + +typedef struct NIF_t +{ + ETH_ADDR hwa; /* ethernet card hardware address */ + ETH_ADDR broadcast; /* broadcast address */ + int mtu; /* hardware maximum transmission unit */ + int ch; /* ethernet channel associated with this NIF */ + + struct SUP_PROTO_t + { + uint16_t protocol; + void (*handler)(struct NIF_t *, NBUF *); + void *info; + } protocol[MAX_SUP_PROTO]; + + unsigned short num_protocol; + + int (*send)(struct NIF_t *, uint8_t *, uint8_t *, uint16_t, NBUF *); + + unsigned int f_rx; + unsigned int f_tx; + unsigned int f_rx_err; + unsigned int f_tx_err; + unsigned int f_err; +} NIF; + + +extern NIF *nif_init (NIF *); +extern int nif_protocol_exist (NIF *, uint16_t); +extern void nif_protocol_handler (NIF *, uint16_t, NBUF *); +extern void *nif_get_protocol_info (NIF *, uint16_t); +extern int nif_bind_protocol (NIF *, uint16_t, void (*)(NIF *, NBUF *), void *); + + +#endif /* _NIF_H */ diff --git a/include/ohci.h b/include/ohci.h new file mode 100644 index 0000000..b0141c8 --- /dev/null +++ b/include/ohci.h @@ -0,0 +1,464 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB. + * + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2001 David Brownell + * + * usb-ohci.h + */ + +#define USB_OHCI_MAX_ROOT_PORTS 4 + +static int cc_to_error[16] = +{ + +/* mapping of the OHCI CC status to error codes */ + /* No Error */ 0, + /* CRC Error */ USB_ST_CRC_ERR, + /* Bit Stuff */ USB_ST_BIT_ERR, + /* Data Togg */ USB_ST_CRC_ERR, + /* Stall */ USB_ST_STALLED, + /* DevNotResp */ -1, + /* PIDCheck */ USB_ST_BIT_ERR, + /* UnExpPID */ USB_ST_BIT_ERR, + /* DataOver */ USB_ST_BUF_ERR, + /* DataUnder */ USB_ST_BUF_ERR, + /* reservd */ -1, + /* reservd */ -1, + /* BufferOver */ USB_ST_BUF_ERR, + /* BuffUnder */ USB_ST_BUF_ERR, + /* Not Access */ -1, + /* Not Access */ -1 +}; + +static const char *cc_to_string[16] = +{ + "No Error", + "CRC: Last data packet from endpoint contained a CRC error.", + "BITSTUFFING:\r\nLast data packet from endpoint contained a bit stuffing violation", + "DATATOGGLEMISMATCH:\r\n Last packet from endpoint had data toggle PID\r\n" \ + "that did not match the expected value.", + "STALL: TD was moved to the Done Queue because the endpoint returned a STALL PID", + "DEVICENOTRESPONDING:\r\nDevice did not respond to token (IN) or did\r\n" \ + "not provide a handshake (OUT)", + "PIDCHECKFAILURE:\r\nCheck bits on PID from endpoint failed on data PID\r\n"\ + "(IN) or handshake (OUT)", + "UNEXPECTEDPID:\r\nReceive PID was not valid when encountered or PID\r\n" \ + "value is not defined.", + "DATAOVERRUN:\r\nThe amount of data returned by the endpoint exceeded\r\n" \ + "either the size of the maximum data packet allowed\r\n" \ + "from the endpoint (found in MaximumPacketSize field\r\n" \ + "of ED) or the remaining buffer size.", + "DATAUNDERRUN:\r\nThe endpoint returned less than MaximumPacketSize\r\n" \ + "and that amount was not sufficient to fill the\r\n" \ + "specified buffer", + "reserved1", + "reserved2", + "BUFFEROVERRUN:\r\nDuring an IN, HC received data from endpoint faster\r\n" \ + "than it could be written to system memory", + "BUFFERUNDERRUN:\r\nDuring an OUT, HC could not retrieve data from\r\n" \ + "system memory fast enough to keep up with data USB data rate.", + "NOT ACCESSED:\r\nThis code is set by software before the TD is placed\r\n" \ + "on a list to be processed by the HC.(1)", + "NOT ACCESSED:\r\nThis code is set by software before the TD is placed\r\n" \ + "on a list to be processed by the HC.(2)", +}; + +/* ED States */ + +#define ED_NEW 0x00 +#define ED_UNLINK 0x01 +#define ED_OPER 0x02 +#define ED_DEL 0x04 +#define ED_URB_DEL 0x08 + +/* usb_ohci_ed */ +struct ed +{ + uint32_t hwINFO; + uint32_t hwTailP; + uint32_t hwHeadP; + uint32_t hwNextED; + + volatile struct ed *ed_prev; + uint8_t int_period; + uint8_t int_branch; + uint8_t int_load; + uint8_t int_interval; + uint8_t state; + uint8_t type; + uint16_t last_iso; + struct ed *ed_rm_list; + + struct usb_device *usb_dev; + volatile void *purb; + uint32_t unused[2]; +} __attribute__((aligned(16))); +typedef struct ed ed_t; + + +/* TD info field */ +#define TD_CC 0xf0000000 +#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) +#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) +#define TD_EC 0x0C000000 +#define TD_T 0x03000000 +#define TD_T_DATA0 0x02000000 +#define TD_T_DATA1 0x03000000 +#define TD_T_TOGGLE 0x00000000 +#define TD_R 0x00040000 +#define TD_DI 0x00E00000 +#define TD_DI_SET(X) (((X) & 0x07)<< 21) +#define TD_DP 0x00180000 +#define TD_DP_SETUP 0x00000000 +#define TD_DP_IN 0x00100000 +#define TD_DP_OUT 0x00080000 + +#define TD_ISO 0x00010000 +#define TD_DEL 0x00020000 + +/* CC Codes */ +#define TD_CC_NOERROR 0x00 +#define TD_CC_CRC 0x01 +#define TD_CC_BITSTUFFING 0x02 +#define TD_CC_DATATOGGLEM 0x03 +#define TD_CC_STALL 0x04 +#define TD_DEVNOTRESP 0x05 +#define TD_PIDCHECKFAIL 0x06 +#define TD_UNEXPECTEDPID 0x07 +#define TD_DATAOVERRUN 0x08 +#define TD_DATAUNDERRUN 0x09 +#define TD_BUFFEROVERRUN 0x0C +#define TD_BUFFERUNDERRUN 0x0D +#define TD_NOTACCESSED 0x0F + + +#define MAXPSW 1 + +struct td +{ + uint32_t hwINFO; + uint32_t hwCBP; /* Current Buffer Pointer */ + uint32_t hwNextTD; /* Next TD Pointer */ + uint32_t hwBE; /* Memory Buffer End Pointer */ + + uint16_t hwPSW[MAXPSW]; + uint8_t unused; + uint8_t index; + volatile struct ed *ed; + volatile struct td *next_dl_td; + struct usb_device *usb_dev; + int transfer_len; + uint32_t data; + + uint32_t unused2[2]; +} __attribute__((aligned(32))); +typedef struct td td_t; + +#define OHCI_ED_SKIP (1 << 14) + +/* + * The HCCA (Host Controller Communications Area) is a 256 byte + * structure defined in the OHCI spec. that the host controller is + * told the base address of. It must be 256-byte aligned. + */ + +#define NUM_INTS 32 /* part of the OHCI standard */ +struct ohci_hcca +{ + volatile uint32_t int_table[NUM_INTS]; /* Interrupt ED table */ +#if defined(CONFIG_MPC5200) + uint16_t pad1; /* set to 0 on each frame_no change */ + uint16_t frame_no; /* current frame number */ +#else + uint16_t frame_no; /* current frame number */ + uint16_t pad1; /* set to 0 on each frame_no change */ +#endif + uint32_t done_head; /* info returned for an interrupt */ + uint8_t reserved_for_hc[116]; +} __attribute__((aligned(256))); + +/* + * This is the structure of the OHCI controller's memory mapped I/O + * region. This is Memory Mapped I/O. You must use the readl() and + * writel() macros defined in asm/io.h to access these!! + */ +struct ohci_regs +{ + /* control and status registers */ + uint32_t revision; + uint32_t control; + uint32_t cmdstatus; + uint32_t intrstatus; + uint32_t intrenable; + uint32_t intrdisable; + /* memory pointers */ + uint32_t hcca; + uint32_t ed_periodcurrent; + uint32_t ed_controlhead; + uint32_t ed_controlcurrent; + uint32_t ed_bulkhead; + uint32_t ed_bulkcurrent; + uint32_t donehead; + /* frame counters */ + uint32_t fminterval; + uint32_t fmremaining; + uint32_t fmnumber; + uint32_t periodicstart; + uint32_t lsthresh; + /* Root hub ports */ + struct ohci_roothub_regs + { + uint32_t a; + uint32_t b; + uint32_t status; + uint32_t portstatus[USB_OHCI_MAX_ROOT_PORTS]; + } roothub; +} __attribute__((aligned(32))); + +/* Some EHCI controls */ +#define EHCI_USBCMD_OFF 0x20 +#define EHCI_USBCMD_HCRESET (1 << 1) + +/* OHCI CONTROL AND STATUS REGISTER MASKS */ + +/* + * HcControl (control) register masks + */ +#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ +#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ +#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ +#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ +#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ +#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ +#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ +#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ +#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ + +/* pre-shifted values for HCFS */ +# define OHCI_USB_RESET (0 << 6) +# define OHCI_USB_RESUME (1 << 6) +# define OHCI_USB_OPER (2 << 6) +# define OHCI_USB_SUSPEND (3 << 6) + +/* + * HcCommandStatus (cmdstatus) register masks + */ +#define OHCI_HCR (1 << 0) /* host controller reset */ +#define OHCI_CLF (1 << 1) /* control list filled */ +#define OHCI_BLF (1 << 2) /* bulk list filled */ +#define OHCI_OCR (1 << 3) /* ownership change request */ +#define OHCI_SOC (3 << 16) /* scheduling overrun count */ + +/* + * masks used with interrupt registers: + * HcInterruptStatus (intrstatus) + * HcInterruptEnable (intrenable) + * HcInterruptDisable (intrdisable) + */ +#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ +#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ +#define OHCI_INTR_SF (1 << 2) /* start frame */ +#define OHCI_INTR_RD (1 << 3) /* resume detect */ +#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ +#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ +#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ +#define OHCI_INTR_OC (1 << 30) /* ownership change */ +#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ + + +/* Virtual Root HUB */ +struct virt_root_hub +{ + int devnum; /* Address of Root Hub endpoint */ + void *dev; /* was urb */ + void *int_addr; + int send; + int interval; +}; + +/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ + +/* destination of request */ +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 + +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 + +/* Requests: bRequest << 8 | bmRequestType */ +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 +#define RH_SET_ADDRESS 0x0500 +#define RH_GET_DESCRIPTOR 0x0680 +#define RH_SET_DESCRIPTOR 0x0700 +#define RH_GET_CONFIGURATION 0x0880 +#define RH_SET_CONFIGURATION 0x0900 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 +/* Our Vendor Specific Request */ +#define RH_SET_EP 0x2000 + + +/* Hub port features */ +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 + +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 + +/* Hub features */ +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 + +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 + +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 + + +/* OHCI ROOT HUB REGISTER MASKS */ + +/* roothub.portstatus [i] bits */ +#define RH_PS_CCS 0x00000001 /* current connect status */ +#define RH_PS_PES 0x00000002 /* port enable status*/ +#define RH_PS_PSS 0x00000004 /* port suspend status */ +#define RH_PS_POCI 0x00000008 /* port over current indicator */ +#define RH_PS_PRS 0x00000010 /* port reset status */ +#define RH_PS_PPS 0x00000100 /* port power status */ +#define RH_PS_LSDA 0x00000200 /* low speed device attached */ +#define RH_PS_CSC 0x00010000 /* connect status change */ +#define RH_PS_PESC 0x00020000 /* port enable status change */ +#define RH_PS_PSSC 0x00040000 /* port suspend status change */ +#define RH_PS_OCIC 0x00080000 /* over current indicator change */ +#define RH_PS_PRSC 0x00100000 /* port reset status change */ + +/* roothub.status bits */ +#define RH_HS_LPS 0x00000001 /* local power status */ +#define RH_HS_OCI 0x00000002 /* over current indicator */ +#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ +#define RH_HS_LPSC 0x00010000 /* local power status change */ +#define RH_HS_OCIC 0x00020000 /* over current indicator change */ +#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ + +/* roothub.b masks */ +#define RH_B_DR 0x0000ffff /* device removable flags */ +#define RH_B_PPCM 0xffff0000 /* port power control mask */ + +/* roothub.a masks */ +#define RH_A_NDP (0xff << 0) /* number of downstream ports */ +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_DT (1 << 10) /* device type (mbz) */ +#define RH_A_OCPM (1 << 11) /* over current protection mode */ +#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ + +/* urb */ +#define N_URB_TD 48 +typedef struct +{ + volatile ed_t *ed; + uint16_t length; /* number of tds associated with this request */ + uint16_t td_cnt; /* number of tds already serviced */ + struct usb_device *dev; + int state; + uint32_t pipe; + void *transfer_buffer; + int transfer_buffer_length; + int interval; + int actual_length; + int finished; + td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ +} urb_priv_t; +#define URB_DEL 1 + +#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ + +struct ohci_device +{ + ed_t ed[NUM_EDS]; + int ed_cnt; +}; + +/* + * This is the full ohci controller description + * + * Note how the "proper" USB information is just + * a subset of what the full implementation needs. (Linus) + */ + +typedef struct ohci +{ + /* ------- common part -------- */ + long handle; /* PCI BIOS */ + const struct pci_device_id *ent; + int usbnum; + /* ---- end of common part ---- */ + int big_endian; /* PCI BIOS */ + int controller; + volatile struct ohci_hcca *hcca_unaligned; + volatile struct ohci_hcca *hcca; /* hcca */ + td_t *td_unaligned; + struct ohci_device *ohci_dev_unaligned; + /* this allocates EDs for all possible endpoints */ + struct ohci_device *ohci_dev; + + int irq_enabled; + int stat_irq; + volatile int irq; + int disabled; /* e.g. got a UE, we're hung */ + int sleeping; +#define OHCI_FLAGS_NEC 0x80000000 + uint32_t flags; /* for HC bugs */ + + uint32_t offset; + uint32_t dma_offset; + volatile struct ohci_regs *regs; /* OHCI controller's memory */ + + int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/ + volatile ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ + volatile ed_t *ed_bulktail; /* last endpoint of bulk list */ + volatile ed_t *ed_controltail; /* last endpoint of control list */ + int intrstatus; + uint32_t hc_control; /* copy of the hc control reg */ + uint32_t ndp; /* copy NDP from roothub_a */ + struct virt_root_hub rh; + + const char *slot_name; + + /* device which was disconnected */ + struct usb_device *devgone; +} ohci_t; + +/* hcd */ +/* endpoint */ +static int ep_link(volatile ohci_t * ohci, volatile ed_t *ed); +static int ep_unlink(volatile ohci_t * ohci, volatile ed_t *ed); +static ed_t * ep_add_ed(volatile ohci_t * ohci, struct usb_device * usb_dev, uint32_t pipe, int interval, int load); + + +/* we need more TDs than EDs */ +#define NUM_TD 64 + + +static inline void ed_free(struct ed *ed) +{ + ed->usb_dev = NULL; +} + + diff --git a/include/pci_errata.h b/include/pci_errata.h new file mode 100755 index 0000000..b8ac603 --- /dev/null +++ b/include/pci_errata.h @@ -0,0 +1,11 @@ +#ifndef PCI_ERRATA_H +#define PCI_ERRATA_H + +#include + + +extern void chip_errata_135(void); +extern void chip_errata_055(int32_t handle); + +#endif // PCI_ERRATA_H + diff --git a/include/queue.h b/include/queue.h new file mode 100644 index 0000000..f8fc229 --- /dev/null +++ b/include/queue.h @@ -0,0 +1,51 @@ +/* + * File: queue.h + * Purpose: Implement a first in, first out linked list + * + * Notes: + */ + +#ifndef _QUEUE_H_ +#define _QUEUE_H_ + +/* + * Individual queue node + */ +typedef struct NODE +{ + struct NODE *next; +} QNODE; + +/* + * Queue Struture - linked list of qentry items + */ +typedef struct +{ + QNODE *head; + QNODE *tail; +} QUEUE; + +/* + * Functions provided by queue.c + */ +void +queue_init(QUEUE *); + +int +queue_isempty(QUEUE *); + +void +queue_add(QUEUE *, QNODE *); + +QNODE* +queue_remove(QUEUE *); + +QNODE* +queue_peek(QUEUE *); + +void +queue_move(QUEUE *, QUEUE *); + +/********************************************************************/ + +#endif /* _QUEUE_H_ */ diff --git a/include/sd_card.h b/include/sd_card.h new file mode 100644 index 0000000..ec6d582 --- /dev/null +++ b/include/sd_card.h @@ -0,0 +1,45 @@ +/* + * sd_card.h + * + * Exported sd-card access routines for the FireBee BaS + * + * Created on: 19.11.2012 + * Author: mfro + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Copyright 2010 - 2012 F. Aschwanden + * Copyright 2011 - 2012 V. Riviere + * Copyright 2012 M. Froeschle + * + */ + +#ifndef _SD_CARD_H_ +#define _SD_CARD_H_ + +#include +#include + +extern void sd_card_init(void); + +/* MMC card type flags (MMC_GET_TYPE) */ +#define CT_MMC 0x01 /* MMC ver 3 */ +#define CT_SD1 0x02 /* SD ver 1 */ +#define CT_SD2 0x04 /* SD ver 2 */ +//#define CT_SDC (CT_SD1|CT_SD2) /* SD */ +#define CT_BLOCK 0x08 /* Block addressing */ + +#endif /* _SD_CARD_H_ */ diff --git a/include/tftp.h b/include/tftp.h new file mode 100644 index 0000000..a3f72d1 --- /dev/null +++ b/include/tftp.h @@ -0,0 +1,152 @@ +/* + * File: tftp.h + * Purpose: Data definitions for TFTP + * + * Notes: + */ + +#ifndef _TFTP_H_ +#define _TFTP_H_ + +#define TFTP_RRQ (1) +#define TFTP_WRQ (2) +#define TFTP_DATA (3) +#define TFTP_ACK (4) +#define TFTP_ERROR (5) + +#define TFTP_ERR_FNF 1 +#define TFTP_ERR_AV 2 +#define TFTP_ERR_DF 3 +#define TFTP_ERR_ILL 4 +#define TFTP_ERR_TID 5 +#define TFTP_FE 6 +#define TFTP_NSU 7 +#define TFTP_ERR_UD 0 + +#define OCTET "octet" +#define NETASCII "netascii" + +/* Protocol Header information */ +#define TFTP_HDR_OFFSET (ETH_HDR_LEN + IP_HDR_SIZE + UDP_HDR_SIZE) + +/* Timeout in seconds */ +#define TFTP_TIMEOUT 2 + +/* Maximum TFTP Packet Size (payload only - no header) */ +#define TFTP_PKTSIZE 512 + +/* Number of TFTP Data Buffers */ +#define NUM_TFTPBD 6 + + +/* Data Buffer Pointer Structure */ +typedef struct +{ + uint8_t data[TFTP_PKTSIZE]; + uint16_t bytes; +} DATA_BUF; + +/* TFTP RRQ/WRQ Packet */ +typedef struct +{ + uint16_t opcode; + char filename_mode[TFTP_PKTSIZE - 2]; +} RWRQ; + +/* TFTP DATA Packet */ +typedef struct +{ + uint16_t opcode; + uint16_t blocknum; + uint8_t data[TFTP_PKTSIZE - 4]; +} DATA; + +/* TFTP Acknowledge Packet */ +typedef struct +{ + uint16_t opcode; + uint16_t blocknum; +} ACK; + +/* TFTP Error Packet */ +typedef struct +{ + uint16_t opcode; + uint16_t code; + char msg[TFTP_PKTSIZE - 4]; +} ERROR; + +/* TFTP Generic Packet */ +typedef struct +{ + uint16_t opcode; +} GEN; + +union TFTPpacket +{ + RWRQ rwrq; + DATA data; + ACK ack; + ERROR error; + GEN generic; +}; + +/* TFTP Connection Status */ +typedef struct +{ + /* Pointer to next character in buffer ring */ + uint8_t *next_char; + + /* Direction of current connection, read or write */ + uint8_t dir; + + /* Connection established flag */ + uint8_t open; + + /* Pointer to our Network InterFace */ + NIF *nif; + + /* File being transferred */ + char *file; + + /* Server IP address */ + IP_ADDR server_ip; + + /* Queue to hold the TFTP packets */ + QUEUE queue; + + /* Bytes received counter */ + uint32_t bytes_recv; + + /* Bytes sent counter */ + uint32_t bytes_sent; + + /* Bytes remaining in current Rx buffer */ + uint32_t rem_bytes; + + /* Server UDP port */ + uint16_t server_port; + + /* My UDP port */ + uint16_t my_port; + + /* Expected TFTP block number */ + uint16_t exp_blocknum; + + /* Keep track of the last packet acknowledged */ + uint16_t last_ack; + + /* Error Flag */ + uint8_t error; + +} TFTP_Connection; + + +extern void tftp_handler(NIF *, NBUF *) ; +extern int tftp_write (NIF *, char *, IP_ADDR_P, uint32_t, uint32_t); +extern int tftp_read(NIF *, char *, IP_ADDR_P); +extern void tftp_end(int); +extern int tftp_in_char(void); + + +#endif /* _TFTP_H_ */ diff --git a/include/user_io.h b/include/user_io.h new file mode 100644 index 0000000..cc3ba04 --- /dev/null +++ b/include/user_io.h @@ -0,0 +1,57 @@ +/* +* user_io.h +* +*/ + +#ifndef _USER_IO_H_ +#define _USER_IO_H_ + +#define UIO_STATUS 0x00 +#define UIO_BUT_SW 0x01 + +// codes as used by minimig (amiga) +#define UIO_JOYSTICK0 0x02 +#define UIO_JOYSTICK1 0x03 +#define UIO_MOUSE 0x04 +#define UIO_KEYBOARD 0x05 +#define UIO_KBD_OSD 0x06 // keycodes used by OSD only + +// codes as used by MiST (atari) +#define UIO_IKBD_OUT 0x02 +#define UIO_IKBD_IN 0x03 +#define UIO_SERIAL_OUT 0x04 +#define UIO_SERIAL_IN 0x05 + +#define JOY_RIGHT 0x01 +#define JOY_LEFT 0x02 +#define JOY_DOWN 0x04 +#define JOY_UP 0x08 +#define JOY_BTN1 0x10 +#define JOY_BTN2 0x20 +#define JOY_MOVE (JOY_RIGHT|JOY_LEFT|JOY_UP|JOY_DOWN) + +#define BUTTON1 0x01 +#define BUTTON2 0x02 +#define SWITCH1 0x04 +#define SWITCH2 0x08 + +// core type value should be unlikely to be returned by broken cores +#define CORE_TYPE_UNKNOWN 0x55 +#define CORE_TYPE_DUMB 0xa0 +#define CORE_TYPE_MINIMIG 0xa1 +#define CORE_TYPE_PACE 0xa2 +#define CORE_TYPE_MIST 0xa3 + +void user_io_init(); +void user_io_detect_core_type(); +unsigned char user_io_core_type(); +void user_io_poll(); +int user_io_button_pressed(); +void user_io_osd_key_enable(char); + +// hooks from the usb layer +void user_io_mouse(unsigned char b, char x, char y); +void user_io_kbd(unsigned char m, unsigned char *k); + +#endif /* _USER_IO_H_ */ + diff --git a/include/video.h b/include/video.h new file mode 100644 index 0000000..e02f25a --- /dev/null +++ b/include/video.h @@ -0,0 +1,10 @@ +#ifndef _VIDEO_H_ +#define _VIDEO_H_ + +#include +#include "bas_printf.h" +#define CONFIG_FB_RADEON_I2C + +extern void video_init(void); + +#endif /* _VIDEO_H_ */ diff --git a/include/wait.h b/include/wait.h new file mode 100644 index 0000000..20e9eea --- /dev/null +++ b/include/wait.h @@ -0,0 +1,61 @@ +/* + * wait.h + * + * Author: mfro + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Copyright 2010 - 2012 F. Aschwanden + * Copyright 2011 - 2012 V. Riviere + * Copyright 2012 M. Froeschle + * + */ + +#ifndef _WAIT_H_ +#define _WAIT_H_ + +#include + +#if defined(MACHINE_FIREBEE) +#include "firebee.h" +#elif defined(MACHINE_M5484LITE) +#include "m5484l.h" +#elif defined(MACHINE_M54455) +#include "m54455.h" +#else +#error "unknown machine" +#endif /* MACHINE_FIREBEE */ + +#include "MCF5475.h" + +typedef bool (*checker_func)(void); + +extern void wait(uint32_t); +extern void wait_us(uint32_t); /* this is just an alias to the above */ + +inline static void udelay(long us) +{ + wait((uint32_t) us); +} + +extern bool waitfor(uint32_t us, checker_func condition); +extern uint32_t get_timer(void); +extern void wait_ms(uint32_t ms); + +#define US_TO_TIMER(a) ((a) * SYSCLK) / 1000000UL +#define TIMER_TO_US(a) ((a) * 1000000UL) / SYSCLK) + +#endif /* _WAIT_H_ */ diff --git a/include/x86emu_regs.h b/include/x86emu_regs.h new file mode 100644 index 0000000..6d6b871 --- /dev/null +++ b/include/x86emu_regs.h @@ -0,0 +1,169 @@ +/* $NetBSD: x86emu_regs.h,v 1.1 2007/12/01 20:14:10 joerg Exp $ */ + +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* Copyright (C) 2007 Joerg Sonnenberger +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +****************************************************************************/ + +#ifndef __X86EMU_REGS_H +#define __X86EMU_REGS_H + +/*---------------------- Macros and type definitions ----------------------*/ + +/* 8 bit registers */ +#define R_AH register_a.I8_reg.h_reg +#define R_AL register_a.I8_reg.l_reg +#define R_BH register_b.I8_reg.h_reg +#define R_BL register_b.I8_reg.l_reg +#define R_CH register_c.I8_reg.h_reg +#define R_CL register_c.I8_reg.l_reg +#define R_DH register_d.I8_reg.h_reg +#define R_DL register_d.I8_reg.l_reg + +/* 16 bit registers */ +#define R_AX register_a.I16_reg.x_reg +#define R_BX register_b.I16_reg.x_reg +#define R_CX register_c.I16_reg.x_reg +#define R_DX register_d.I16_reg.x_reg + +/* 32 bit extended registers */ +#define R_EAX register_a.I32_reg.e_reg +#define R_EBX register_b.I32_reg.e_reg +#define R_ECX register_c.I32_reg.e_reg +#define R_EDX register_d.I32_reg.e_reg + +/* special registers */ +#define R_SP register_sp.I16_reg.x_reg +#define R_BP register_bp.I16_reg.x_reg +#define R_SI register_si.I16_reg.x_reg +#define R_DI register_di.I16_reg.x_reg +#define R_IP register_ip.I16_reg.x_reg +#define R_FLG register_flags + +/* special registers */ +#define R_ESP register_sp.I32_reg.e_reg +#define R_EBP register_bp.I32_reg.e_reg +#define R_ESI register_si.I32_reg.e_reg +#define R_EDI register_di.I32_reg.e_reg +#define R_EIP register_ip.I32_reg.e_reg +#define R_EFLG register_flags + +/* segment registers */ +#define R_CS register_cs +#define R_DS register_ds +#define R_SS register_ss +#define R_ES register_es +#define R_FS register_fs +#define R_GS register_gs + +/* flag conditions */ +#define FB_CF 0x0001 /* CARRY flag */ +#define FB_PF 0x0004 /* PARITY flag */ +#define FB_AF 0x0010 /* AUX flag */ +#define FB_ZF 0x0040 /* ZERO flag */ +#define FB_SF 0x0080 /* SIGN flag */ +#define FB_TF 0x0100 /* TRAP flag */ +#define FB_IF 0x0200 /* INTERRUPT ENABLE flag */ +#define FB_DF 0x0400 /* DIR flag */ +#define FB_OF 0x0800 /* OVERFLOW flag */ + +/* 80286 and above always have bit#1 set */ +#define F_ALWAYS_ON (0x0002) /* flag bits always on */ + +/* + * Define a mask for only those flag bits we will ever pass back + * (via PUSHF) + */ +#define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF) + +/* following bits masked in to a 16bit quantity */ + +#define F_CF 0x0001 /* CARRY flag */ +#define F_PF 0x0004 /* PARITY flag */ +#define F_AF 0x0010 /* AUX flag */ +#define F_ZF 0x0040 /* ZERO flag */ +#define F_SF 0x0080 /* SIGN flag */ +#define F_TF 0x0100 /* TRAP flag */ +#define F_IF 0x0200 /* INTERRUPT ENABLE flag */ +#define F_DF 0x0400 /* DIR flag */ +#define F_OF 0x0800 /* OVERFLOW flag */ + +#define SET_FLAG(flag) (emu->x86.R_FLG |= (flag)) +#define CLEAR_FLAG(flag) (emu->x86.R_FLG &= ~(flag)) +#define ACCESS_FLAG(flag) (emu->x86.R_FLG & (flag)) +#define CLEARALL_FLAG(m) (emu->x86.R_FLG = 0) + +#define CONDITIONAL_SET_FLAG(COND,FLAG) \ + if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG) + +#define F_PF_CALC 0x010000 /* PARITY flag has been calced */ +#define F_ZF_CALC 0x020000 /* ZERO flag has been calced */ +#define F_SF_CALC 0x040000 /* SIGN flag has been calced */ + +#define F_ALL_CALC 0xff0000 /* All have been calced */ + +/* + * Emulator machine state. + * Segment usage control. + */ +#define SYSMODE_SEG_DS_SS 0x00000001 +#define SYSMODE_SEGOVR_CS 0x00000002 +#define SYSMODE_SEGOVR_DS 0x00000004 +#define SYSMODE_SEGOVR_ES 0x00000008 +#define SYSMODE_SEGOVR_FS 0x00000010 +#define SYSMODE_SEGOVR_GS 0x00000020 +#define SYSMODE_SEGOVR_SS 0x00000040 +#define SYSMODE_PREFIX_REPE 0x00000080 +#define SYSMODE_PREFIX_REPNE 0x00000100 +#define SYSMODE_PREFIX_DATA 0x00000200 +#define SYSMODE_PREFIX_ADDR 0x00000400 +#define SYSMODE_INTR_PENDING 0x10000000 +#define SYSMODE_EXTRN_INTR 0x20000000 +#define SYSMODE_HALTED 0x40000000 + +#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \ + SYSMODE_SEGOVR_CS | \ + SYSMODE_SEGOVR_DS | \ + SYSMODE_SEGOVR_ES | \ + SYSMODE_SEGOVR_FS | \ + SYSMODE_SEGOVR_GS | \ + SYSMODE_SEGOVR_SS) +#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \ + SYSMODE_SEGOVR_CS | \ + SYSMODE_SEGOVR_DS | \ + SYSMODE_SEGOVR_ES | \ + SYSMODE_SEGOVR_FS | \ + SYSMODE_SEGOVR_GS | \ + SYSMODE_SEGOVR_SS | \ + SYSMODE_PREFIX_DATA | \ + SYSMODE_PREFIX_ADDR) + +#define INTR_SYNCH 0x1 + +#endif /* __X86EMU_REGS_H */ diff --git a/include/xhdi_sd.h b/include/xhdi_sd.h new file mode 100644 index 0000000..e855ea6 --- /dev/null +++ b/include/xhdi_sd.h @@ -0,0 +1,138 @@ +/* + * xhdi_sd.h + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 01.05.2013 + * Copyright 2012 M. Fröschle + */ + +#ifndef _XHDI_SD_H_ +#define _XHDI_SD_H_ + +/* XHDI function numbers */ + +#define XHDI_VERSION 0 +#define XHDI_INQUIRE_TARGET 1 +#define XHDI_RESERVE 2 +#define XHDI_LOCK 3 +#define XHDI_STOP 4 +#define XHDI_EJECT 5 +#define XHDI_DRIVEMAP 6 +#define XHDI_INQUIRE_DEVICE 7 +#define XHDI_INQUIRE_DRIVER 8 +#define XHDI_NEW_COOKIE 9 +#define XHDI_READ_WRITE 10 +#define XHDI_INQUIRE_TARGET2 11 +#define XHDI_INQUIRE_DEVICE2 12 +#define XHDI_DRIVER_SPECIAL 13 +#define XHDI_GET_CAPACITY 14 +#define XHDI_MEDIUM_CHANGED 15 +#define XHDI_MINT_INFO 16 +#define XHDI_DOS_LIMITS 17 +#define XHDI_LAST_ACCESS 18 +#define XHDI_REACCESS 19 + +/* XHDI error codes */ + +#define E_OK 0 /* OK */ +#define ERROR -1 /* unspecified error */ +#define EDRVNR -2 /* drive not ready */ +#define EUNDEV -15 /* invalid device/target number */ +#define EINVFN -32 /* invalid function number */ +#define EACCDN -36 /* access denied (device currently reserved) */ +#define EDRIVE -46 /* BIOS device not served by driver */ + +/* XHDI device capabilities */ + +#define XH_TARGET_STOPPABLE (1 << 0) +#define XH_TARGET_REMOVABLE (1 << 1) +#define XH_TARGET_LOCKABLE (1 << 2) +#define XH_TARGET_EJECTABLE (1 << 3) +#define XH_TARGET_LOCKED (1 << 29) +#define XH_TARGET_STOPPED (1 << 30) +#define XH_TARGET_RESERVED (1 << 31) + +typedef struct _BPB +{ + uint16_t recsiz; /* Bytes per sector */ + uint16_t clsiz; /* Sectors per cluster */ + uint16_t clsizb; /* Bytes per cluster */ + uint16_t rdlen; /* Directory length */ + uint16_t fsiz; /* Length of the FAT */ + uint16_t fatrec; /* Start of the 2nd FAT */ + uint16_t datrec; /* 1st free sector */ + uint16_t numcl; /* Total numbr of clusters */ + uint16_t bflags; /* Flags as bit-vector */ + /* Bit 0: 0 (12-Bit-FAT), 1 16-Bit-FAT */ + /* Bit 1: 0 (two FATs), 1 (one FAT) */ + /* only available since TOS 2.06 */ +} BPB; + +/* a riddle: how do you typedef a function pointer to a function that returns its own type? ;) */ +typedef void* (*xhdi_call_fun)(int xhdi_fun, ...); + +extern uint32_t xhdi_call(uint16_t *stack); + +extern xhdi_call_fun xhdi_sd_install(xhdi_call_fun old_vector) __attribute__((__interrupt__)); + +extern uint16_t xhdi_version(void); /* XHDI 0 */ + +extern uint32_t xhdi_inquire_target(uint16_t major, uint16_t minor, uint32_t *block_size, uint32_t *flags, + char *product_name); /* XHDI 1 */ + +extern uint32_t xhdi_reserve(uint16_t major, uint16_t minor, uint16_t do_reserve, uint16_t key); /* XHDI 2 */ + +extern uint32_t xhdi_lock(uint16_t major, uint16_t minor, uint16_t do_lock, uint16_t key); /* XHDI 3 */ + +extern uint32_t xhdi_stop(uint16_t major, uint16_t minor, uint16_t do_stop, uint16_t key); /* XHDI 4 */ + +extern uint32_t xhdi_eject(uint16_t major, uint16_t minor, uint16_t do_eject, uint16_t key); /* XHDI 5 */ + +extern uint32_t xhdi_drivemap(void); /* XHDI 6 */ + +extern uint32_t xhdi_inquire_device(uint16_t bios_device, uint16_t *major, uint16_t *minor, + uint32_t *start_sector, /* BPB */ void *bpb); /* XHDI 7 */ + +extern uint32_t xhdi_inquire_driver(uint16_t bios_device, char *name, char *version, + char *company, uint16_t *ahdi_version, uint16_t *maxIPL); /* XHDI 8 */ + +extern uint32_t xhdi_new_cookie(uint32_t newcookie); /* XHDI 9 */ + +extern uint32_t xhdi_read_write(uint16_t major, uint16_t minor, uint16_t rwflag, + uint32_t recno, uint16_t count, void *buf); /* XHDI 10 */ + +extern uint32_t xhdi_inquire_target2(uint16_t major, uint16_t minor, uint32_t *block_size, + uint32_t *device_flags, char *product_name, uint16_t stringlen); /* XHDI 11 */ + +extern uint32_t xhdi_inquire_device2(uint16_t bios_device, uint16_t *major, uint16_t *minor, + uint32_t *start_sector, BPB *bpb, uint32_t *blocks, char *partid); /* XHDI 12 */ + +extern uint32_t xhdi_driver_special(uint32_t key1, uint32_t key2, uint16_t subopcode, void *data); /* XHDI 13 */ + +extern uint32_t xhdi_get_capacity(uint16_t major, uint16_t minor, uint32_t *blocks, uint32_t *bs); /* XHDI 14 */ + +extern uint32_t xhdi_medium_changed(uint16_t major, uint16_t minor); /* XHDI 15 */ + +extern uint32_t xhdi_mint_info(uint16_t opcode, void *data); /* XHDI 16 */ + +extern uint32_t xhdi_dos_limits(uint16_t which, uint32_t limit); /* XHDI 17 */ + +extern uint32_t xhdi_last_access(uint16_t major, uint16_t minor, uint32_t *ms); /* XHDI 18 */ + +extern uint32_t xhdi_reaccess(uint16_t major, uint16_t minor); /* XHDI 19 */ + +#endif /* _XHDI_SD_H_ */ diff --git a/kbd/ikbd.c b/kbd/ikbd.c new file mode 100644 index 0000000..66bbc31 --- /dev/null +++ b/kbd/ikbd.c @@ -0,0 +1,352 @@ +/* + + https://www.kernel.org/doc/Documentation/input/atarikbd.txt + + ikbd ToDo: + + Feature Example using/needing it impl. tested + --------------------------------------------------------------------- + mouse y at bottom Bolo X X + mouse button key events Goldrunner/A_008 X X + joystick interrogation mode Xevious/A_004 X X + Absolute mouse mode Backlash/A_008, A-Ball/A50 + disable mouse ? X + disable joystick ? X + Joysticks also generate Goldrunner X X + mouse button events! + Pause (cmd 0x13) Wings of Death/A_427 + + */ + +#include +#include "bas_printf.h" +#include "bas_string.h" + +#include "user_io.h" +//#include "hardware.h" +#include "ikbd.h" + +#include "debug.h" + +// atari ikbd stuff +#define IKBD_STATE_JOYSTICK_EVENT_REPORTING 0x01 +#define IKBD_STATE_MOUSE_Y_BOTTOM 0x02 +#define IKBD_STATE_MOUSE_BUTTON_AS_KEY 0x04 // mouse buttons act like keys +#define IKBD_STATE_MOUSE_DISABLED 0x08 +#define IKBD_STATE_MOUSE_ABSOLUTE 0x10 + +#define IKBD_DEFAULT IKBD_STATE_JOYSTICK_EVENT_REPORTING + +#define QUEUE_LEN 16 // power of 2! +static unsigned char tx_queue[QUEUE_LEN]; +static unsigned char wptr = 0, rptr = 0; + +// structure to keep track of ikbd state +static struct +{ + unsigned char cmd; + unsigned char state; + unsigned char expect; + + // joystick state + unsigned char joystick[2]; + + // mouse state + unsigned short mouse_pos_x, mouse_pos_y; + unsigned char mouse_buttons; +} ikbd; + +// #define IKBD_DEBUG + +void ikbd_init() +{ + // reset ikbd state + memset(&ikbd, 0, sizeof(ikbd)); + ikbd.state = IKBD_DEFAULT; +} + +static void enqueue(unsigned char b) +{ + if (((wptr + 1)&(QUEUE_LEN-1)) == rptr) + { + xprintf("IKBD: !!!!!!! tx queue overflow !!!!!!!!!\n"); + return; + } + + tx_queue[wptr] = b; + wptr = (wptr + 1) & (QUEUE_LEN - 1); +} + +// convert internal joystick format into atari ikbd format +static unsigned char joystick_map2ikbd(unsigned in) +{ + unsigned char out = 0; + + if (in & JOY_UP) out |= 0x01; + if (in & JOY_DOWN) out |= 0x02; + if (in & JOY_LEFT) out |= 0x04; + if (in & JOY_RIGHT) out |= 0x08; + if (in & JOY_BTN1) out |= 0x80; + + return out; +} + +// process inout from atari core into ikbd +void ikbd_handle_input(unsigned char cmd) +{ + // expecting a second byte for command + if (ikbd.expect) + { + ikbd.expect--; + + // last byte of command received + if (!ikbd.expect) + { + switch(ikbd.cmd) + { + case 0x07: // set mouse button action + xprintf("IKBD: mouse button action = %x\n", cmd); + + // bit 2: Mouse buttons act like keys (LEFT=0x74 & RIGHT=0x75) + if(cmd & 0x04) ikbd.state |= IKBD_STATE_MOUSE_BUTTON_AS_KEY; + else ikbd.state &= ~IKBD_STATE_MOUSE_BUTTON_AS_KEY; + + break; + + case 0x80: // ibkd reset + // reply "everything is ok" + enqueue(0xf0); + break; + + default: + break; + } + } + + return; + } + + ikbd.cmd = cmd; + + switch(cmd) + { + case 0x07: + xprintf("IKBD: Set mouse button action"); + ikbd.expect = 1; + break; + + case 0x08: + xprintf("IKBD: Set relative mouse positioning"); + ikbd.state &= ~IKBD_STATE_MOUSE_DISABLED; + ikbd.state &= ~IKBD_STATE_MOUSE_ABSOLUTE; + break; + + case 0x09: + xprintf("IKBD: Set absolute mouse positioning"); + ikbd.state &= ~IKBD_STATE_MOUSE_DISABLED; + ikbd.state |= IKBD_STATE_MOUSE_ABSOLUTE; + ikbd.expect = 4; + break; + + case 0x0b: + xprintf("IKBD: Set Mouse threshold"); + ikbd.expect = 2; + break; + + case 0x0f: + xprintf("IKBD: Set Y at bottom"); + ikbd.state |= IKBD_STATE_MOUSE_Y_BOTTOM; + break; + + case 0x10: + xprintf("IKBD: Set Y at top"); + ikbd.state &= ~IKBD_STATE_MOUSE_Y_BOTTOM; + break; + + case 0x12: + xprintf("IKBD: Disable mouse"); + ikbd.state |= IKBD_STATE_MOUSE_DISABLED; + break; + + case 0x14: + xprintf("IKBD: Set Joystick event reporting"); + ikbd.state |= IKBD_STATE_JOYSTICK_EVENT_REPORTING; + break; + + case 0x15: + xprintf("IKBD: Set Joystick interrogation mode"); + ikbd.state &= ~IKBD_STATE_JOYSTICK_EVENT_REPORTING; + break; + + case 0x16: // interrogate joystick + // send reply + enqueue(0xfd); + enqueue(joystick_map2ikbd(ikbd.joystick[0])); + enqueue(joystick_map2ikbd(ikbd.joystick[1])); + break; + + case 0x1a: + xprintf("IKBD: Disable joysticks"); + ikbd.state &= ~IKBD_STATE_JOYSTICK_EVENT_REPORTING; + break; + + case 0x1c: + xprintf("IKBD: Interrogate time of day"); + + enqueue(0xfc); + enqueue(0x13); // year bcd + enqueue(0x03); // month bcd + enqueue(0x07); // day bcd + enqueue(0x20); // hour bcd + enqueue(0x58); // minute bcd + enqueue(0x00); // second bcd + break; + + + case 0x80: + xprintf("IKBD: Reset"); + ikbd.expect = 1; + ikbd.state = IKBD_DEFAULT; + break; + + default: + xprintf("IKBD: unknown command: %x\n", cmd); + break; + } +} + +/* + * FIXME: temporarily provide function prototypes for unimplemented functions here to make compiler happy + */ + +extern int GetTimer(int); +extern int CheckTimer(int); +extern void EnableIO(void); +extern void DisableIO(void); +extern int SPI(int); + +void ikbd_poll(void) +{ + static int mtimer = 0; + if (CheckTimer(mtimer)) + { + mtimer = GetTimer(10); + + // check for incoming ikbd data + EnableIO(); + SPI(UIO_IKBD_IN); + + while(SPI(0)) + ikbd_handle_input(SPI(0)); + + DisableIO(); + } + + // send data from queue if present + if(rptr == wptr) return; + + // transmit data from queue + EnableIO(); + SPI(UIO_IKBD_OUT); + SPI(tx_queue[rptr]); + DisableIO(); + + rptr = (rptr + 1) & (QUEUE_LEN - 1); +} + +void ikbd_joystick(unsigned char joystick, unsigned char map) +{ + // todo: suppress events for joystick 0 as long as mouse + // is enabled? + + if (ikbd.state & IKBD_STATE_JOYSTICK_EVENT_REPORTING) + { +#ifdef IKBD_DEBUG + xprintf("IKBD: joy %d %x\n", joystick, map); +#endif + + // only report joystick data for joystick 0 if the mouse is disabled + if ((ikbd.state & IKBD_STATE_MOUSE_DISABLED) || (joystick == 1)) + { + enqueue(0xfe + joystick); + enqueue(joystick_map2ikbd(map)); + } + + if (!(ikbd.state & IKBD_STATE_MOUSE_DISABLED)) + { + // the fire button also generates a mouse event if + // mouse reporting is enabled + if ((map & JOY_BTN1) != (ikbd.joystick[joystick] & JOY_BTN1)) + { + // generate mouse event (ikbd_joystick_buttons is evaluated inside + // user_io_mouse) + ikbd.joystick[joystick] = map; + ikbd_mouse(0, 0, 0); + } + } + } +#ifdef IKBD_DEBUG + else + xprintf("IKBD: no monitor, drop joy %d %x\n", joystick, map); +#endif + + // save state of joystick for interrogation mode + ikbd.joystick[joystick] = map; +} + +void ikbd_keyboard(unsigned char code) +{ +#ifdef IKBD_DEBUG + xprintf("IKBD: send keycode %x%s\n", code&0x7f, (code&0x80)?" BREAK":""); +#endif + enqueue(code); +} + +void ikbd_mouse(uint8_t b, int8_t x, int8_t y) +{ + if (ikbd.state & IKBD_STATE_MOUSE_DISABLED) + return; + + // joystick and mouse buttons are wired together in + // atari st + b |= (ikbd.joystick[0] & JOY_BTN1)?1:0; + b |= (ikbd.joystick[1] & JOY_BTN1)?2:0; + + static unsigned char b_old = 0; + // monitor state of two mouse buttons + if (b != b_old) + { + // check if mouse buttons are supposed to be treated like keys + if (ikbd.state & IKBD_STATE_MOUSE_BUTTON_AS_KEY) + { + // Mouse buttons act like keys (LEFT=0x74 & RIGHT=0x75) + + // handle left mouse button + if((b ^ b_old) & 1) ikbd_keyboard(0x74 | ((b&1)?0x00:0x80)); + // handle right mouse button + if((b ^ b_old) & 2) ikbd_keyboard(0x75 | ((b&2)?0x00:0x80)); + } + b_old = b; + } + +#if 0 + if(ikbd.state & IKBD_STATE_MOUSE_BUTTON_AS_KEY) + { + b = 0; + // if mouse position is 0/0 quit here + if(!x && !y) return; + } +#endif + + if (ikbd.state & IKBD_STATE_MOUSE_ABSOLUTE) + { + } + else + { + // atari has mouse button bits swapped + enqueue(0xf8|((b&1)?2:0)|((b&2)?1:0)); + enqueue(x); + enqueue((ikbd.state & IKBD_STATE_MOUSE_Y_BOTTOM)?-y:y); + } +} + diff --git a/mcf5474.gdb b/mcf5474.gdb new file mode 100644 index 0000000..a7cf98b --- /dev/null +++ b/mcf5474.gdb @@ -0,0 +1,71 @@ +# +# GDB Init script for the Coldfire 5474 processor (firebee). +# + +define addresses +set $vbr = 0x00000000 +#monitor bdm-ctl-set 0x0801 0x00000000 + +set $mbar = 0xFF000000 +#monitor bdm-ctl-set 0x0C0F 0xFF000000 + +set $rambar0 = 0xFF100000 +#monitor bdm-ctl-set 0x0C04 0xFF100007 + +set $rambar1 = 0xFF101000 +#monitor bdm-ctl-set 0x0C05 0xFF101001 +end + +# +# Setup the DRAM controller. +# + +define setup-dram +# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) +set *((long *) 0xFF000500) = 0xE0000000 +set *((long *) 0xFF000508) = 0x00041180 +set *((long *) 0xFF000504) = 0x007F0001 + +# set *((long *) 0xFF00050C) = 0xFFF00000 # ATARI I/O address + +# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes +set *((long *) 0xFF000004) = 0x000002AA +set *((long *) 0xFF000020) = 0x0000001A +set *((long *) 0xFF000024) = 0x0800001A +set *((long *) 0xFF000028) = 0x1000001A +set *((long *) 0xFF00002C) = 0x1800001A +set *((long *) 0xFF000108) = 0x73622830 +set *((long *) 0xFF00010C) = 0x46770000 + + +set *((long *) 0xFF000104) = 0xE10D0002 +set *((long *) 0xFF000100) = 0x40010000 +set *((long *) 0xFF000100) = 0x048D0000 +set *((long *) 0xFF000104) = 0xE10D0002 +set *((long *) 0xFF000104) = 0xE10D0004 +set *((long *) 0xFF000104) = 0xE10D0004 +set *((long *) 0xFF000100) = 0x008D0000 +set *((long *) 0xFF000104) = 0x710D0F00 +end + +define cu +!killall m68k-bdm-gdbserver +end + +# +# Wake up the board +# + +define ib + addresses + setup-dram +end + +define run + continue +end + +tr +ib +#add-symbol-file ../emutos/emutos2.img 0xe00000 +#load firebee/ram.elf diff --git a/memory_map.txt b/memory_map.txt new file mode 100644 index 0000000..58acb8b --- /dev/null +++ b/memory_map.txt @@ -0,0 +1,8 @@ +Firebee memory map +================== + + Virt. Start Virt. End Phys. Start Phys. End +ST-RAM 0x00000000 0x00dfffff 0x60000000 0x60dfffff +TOS 0x00e00000 0x00efffff 0x00e00000 0x00efffff +ST I/O area 0x00f00000 0x01000000 0xfff00000 0xffffffff +TT-RAM 0x01000000 0x20ffffff 0x00000000 0x1fffffff diff --git a/net/am79c874.c b/net/am79c874.c new file mode 100644 index 0000000..6a6ca4f --- /dev/null +++ b/net/am79c874.c @@ -0,0 +1,119 @@ +/* + * File: am79c874.c + * Purpose: Driver for the AMD AM79C874 10/100 Ethernet PHY + */ + +#include "net.h" +#include "fec.h" +#include "am79c874.h" + +#include "bas_printf.h" + +#if defined(MACHINE_FIREBEE) +#include "firebee.h" +#elif defined(MACHINE_M5484LITE) +#include "m5484l.h" +#elif defined(MACHINE_M54455) +#include "m54455.h" +#else +#error "unknown machine!" +#endif + +#include +// #define DEBUG + +/* Initialize the AM79C874 PHY + * + * This function sets up the Auto-Negotiate Advertisement register + * within the PHY and then forces the PHY to auto-negotiate for + * it's settings. + * + * Params: + * fec_ch FEC channel + * phy_addr Address of the PHY. + * speed Desired speed (10BaseT or 100BaseTX) + * duplex Desired duplex (Full or Half) + * + * Return Value: + * 0 if MII commands fail + * 1 otherwise + */ +int am79c874_init(uint8_t fec_ch, uint8_t phy_addr, uint8_t speed, uint8_t duplex) +{ + int timeout; + uint16_t settings; + if (speed); /* to do */ + if (duplex); /* to do */ + + /* Initialize the MII interface */ + fec_mii_init(fec_ch, SYSCLK / 1000); + dbg("%s: PHY reset\r\n", __FUNCTION__); + + /* Reset the PHY */ + if (!fec_mii_write(fec_ch, phy_addr, MII_AM79C874_CR, MII_AM79C874_CR_RESET)) + return 0; + + /* Wait for the PHY to reset */ + for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++) + { + fec_mii_read(fec_ch, phy_addr, MII_AM79C874_CR, &settings); + if (!(settings & MII_AM79C874_CR_RESET)) + break; + } + + if (timeout >= FEC_MII_TIMEOUT) + { + dbg("%s: PHY reset failed\r\n", __FUNCTION__); + return 0; + }; + dbg("%s: PHY reset OK\r\n", __FUNCTION__); + dbg("%s: PHY Enable Auto-Negotiation\r\n", __FUNCTION__); + + /* Enable Auto-Negotiation */ + if (!fec_mii_write(fec_ch, phy_addr, MII_AM79C874_CR, MII_AM79C874_CR_AUTON | MII_AM79C874_CR_RST_NEG)) + return 0; + + dbg("%s:PHY Wait for auto-negotiation to complete\r\n", __FUNCTION__); + + /* Wait for auto-negotiation to complete */ + for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++) + { + settings = 0; + fec_mii_read(fec_ch, phy_addr, MII_AM79C874_SR, &settings); + if ((settings & AUTONEGLINK) == AUTONEGLINK) + break; + } + + if (timeout >= FEC_MII_TIMEOUT) + { + dbg("%s: Auto-negotiation failed (timeout). Set default mode (100Mbps, full duplex)\r\n", __FUNCTION__); + + /* Set the default mode (Full duplex, 100 Mbps) */ + if (!fec_mii_write(fec_ch, phy_addr, MII_AM79C874_CR, MII_AM79C874_CR_100MB | MII_AM79C874_CR_DPLX)) + { + dbg("%s: forced setting 100Mbps/full failed.\r\n", __FUNCTION__); + return 0; + } + } + +#ifdef DBG_AM79 + settings = 0; + + fec_mii_read(fec_ch, phy_addr, MII_AM79C874_DR, &settings); + + dbg("%s: PHY Mode:\r\n", __FUNCTION__); + if (settings & MII_AM79C874_DR_DATA_RATE) + dbg("%s: 100Mbps", __FUNCTION__); + else + dbg("%s: 10Mbps ", __FUNCTION__); + + if (settings & MII_AM79C874_DR_DPLX) + dbg("%s: Full-duplex\r\n", __FUNCTION__); + else + dbg("%s: Half-duplex\r\n", __FUNCTION__); + + dbg("%s:PHY auto-negotiation complete\r\n", __FUNCTION__); +#endif /* DBG_AM79 */ + + return 1; +} diff --git a/net/arp.c b/net/arp.c new file mode 100644 index 0000000..09faab9 --- /dev/null +++ b/net/arp.c @@ -0,0 +1,486 @@ +/* + * File: arp.c + * Purpose: Address Resolution Protocol routines. + * + * Notes: + */ + +#include "net.h" +#include "net_timer.h" +#include "bas_printf.h" +#include +#include + +//#define DEBUG +#include "debug.h" + +#define TIMER_NETWORK 3 + +static uint8_t *arp_find_pair(ARP_INFO *arptab, uint16_t protocol, uint8_t *hwa, uint8_t *pa) +{ + /* + * This function searches through the ARP table for the + * specified or address pair. + * If it is found, then a a pointer to the non-specified + * address is returned. Otherwise NULL is returned. + * If you pass in then you get out. + * If you pass in then you get out. + */ + int slot, i, match = false; + uint8_t *rvalue; + + if (((hwa == 0) && (pa == 0)) || (arptab == 0)) + return NULL; + + rvalue = NULL; + + /* + * Check each protocol address for a match + */ + for (slot = 0; slot < arptab->tab_size; slot++) + { + if ((arptab->table[slot].longevity != ARP_ENTRY_EMPTY) && + (arptab->table[slot].protocol == protocol)) + { + match = true; + if (hwa != 0) + { + /* + * Check the Hardware Address field + */ + rvalue = &arptab->table[slot].pa[0]; + for (i = 0; i < arptab->table[slot].hwa_size; i++) + { + if (arptab->table[slot].hwa[i] != hwa[i]) + { + match = false; + break; + } + } + } + else + { + /* + * Check the Protocol Address field + */ + rvalue = &arptab->table[slot].hwa[0]; + for (i = 0; i < arptab->table[slot].pa_size; i++) + { + if (arptab->table[slot].pa[i] != pa[i]) + { + match = false; + break; + } + } + } + if (match) + { + break; + } + } + } + + if (match) + return rvalue; + else + return NULL; +} + +void arp_merge(ARP_INFO *arptab, uint16_t protocol, int hwa_size, uint8_t *hwa, + int pa_size, uint8_t *pa, int longevity) +{ + /* + * This function merges an entry into the ARP table. If + * either piece is NULL, the function exits, otherwise + * the entry is merged or added, provided there is space. + */ + int i, slot; + uint8_t *ta; + + if ((hwa == NULL) || (pa == NULL) || (arptab == NULL) || + ((longevity != ARP_ENTRY_TEMP) && + (longevity != ARP_ENTRY_PERM))) + { + return; + } + + /* First search ARP table for existing entry */ + if ((ta = arp_find_pair(arptab,protocol,NULL,pa)) != 0) + { + /* Update hardware address */ + for (i = 0; i < hwa_size; i++) + ta[i] = hwa[i]; + return; + } + + /* Next try to find an empty slot */ + slot = -1; + for (i = 0; i < MAX_ARP_ENTRY; i++) + { + if (arptab->table[i].longevity == ARP_ENTRY_EMPTY) + { + slot = i; + break; + } + } + + /* if no empty slot was found, pick a temp slot */ + if (slot == -1) + { + for (i = 0; i < MAX_ARP_ENTRY; i++) + { + if (arptab->table[i].longevity == ARP_ENTRY_TEMP) + { + slot = i; + break; + } + } + } + + /* if after all this, still no slot found, add in last slot */ + if (slot == -1) + slot = (MAX_ARP_ENTRY - 1); + + /* add the entry into the slot */ + arptab->table[slot].protocol = protocol; + + arptab->table[slot].hwa_size = (uint8_t) hwa_size; + for (i = 0; i < hwa_size; i++) + arptab->table[slot].hwa[i] = hwa[i]; + + arptab->table[slot].pa_size = (uint8_t) pa_size; + for (i = 0; i < pa_size; i++) + arptab->table[slot].pa[i] = pa[i]; + + arptab->table[slot].longevity = longevity; +} + + +void arp_remove(ARP_INFO *arptab, uint16_t protocol, uint8_t *hwa, uint8_t *pa) +{ + /* + * This function removes an entry from the ARP table. The + * ARP table is searched according to the non-NULL address + * that is provided. + */ + int slot, i, match; + + if (((hwa == 0) && (pa == 0)) || (arptab == 0)) + return; + + /* check each hardware adress for a match */ + for (slot = 0; slot < arptab->tab_size; slot++) + { + if ((arptab->table[slot].longevity != ARP_ENTRY_EMPTY) && + (arptab->table[slot].protocol == protocol)) + { + match = true; + if (hwa != 0) + { + /* Check Hardware Address field */ + for (i = 0; i < arptab->table[slot].hwa_size; i++) + { + if (arptab->table[slot].hwa[i] != hwa[i]) + { + match = false; + break; + } + } + } + else + { + /* Check Protocol Address field */ + for (i = 0; i < arptab->table[slot].pa_size; i++) + { + if (arptab->table[slot].pa[i] != pa[i]) + { + match = false; + break; + } + } + } + if (match) + { + for (i = 0; i < arptab->table[slot].hwa_size; i++) + arptab->table[slot].hwa[i] = 0; + for (i = 0; i < arptab->table[slot].pa_size; i++) + arptab->table[slot].pa[i] = 0; + arptab->table[slot].longevity = ARP_ENTRY_EMPTY; + break; + } + } + } +} + +void arp_request(NIF *nif, uint8_t *pa) +{ + /* + * This function broadcasts an ARP request for the protocol + * address "pa" + */ + uint8_t *addr; + NBUF *pNbuf; + arp_frame_hdr *arpframe; + int i, result; + + pNbuf = nbuf_alloc(); + if (pNbuf == NULL) + { + dbg("could not allocate Tx buffer\n"); + return; + } + + arpframe = (arp_frame_hdr *)&pNbuf->data[ARP_HDR_OFFSET]; + + /* Build the ARP request packet */ + arpframe->ar_hrd = ETHERNET; + arpframe->ar_pro = ETH_FRM_IP; + arpframe->ar_hln = 6; + arpframe->ar_pln = 4; + arpframe->opcode = ARP_REQUEST; + + addr = &nif->hwa[0]; + for (i = 0; i < 6; i++) + arpframe->ar_sha[i] = addr[i]; + + addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP)); + for (i = 0; i < 4; i++) + arpframe->ar_spa[i] = addr[i]; + + for (i = 0; i < 6; i++) + arpframe->ar_tha[i] = 0x00; + + for (i = 0; i < 4; i++) + arpframe->ar_tpa[i] = pa[i]; + + pNbuf->length = ARP_HDR_LEN; + + /* Send the ARP request */ + dbg("sending ARP request\r\n"); + result = nif->send(nif, nif->broadcast, nif->hwa, ETH_FRM_ARP, pNbuf); + + if (result == 0) + nbuf_free(pNbuf); +} + +static int arp_resolve_pa(NIF *nif, uint16_t protocol, uint8_t *pa, uint8_t **ha) +{ + /* + * This function accepts a pointer to a protocol address and + * searches the ARP table for a hardware address match. If no + * no match found, false is returned. + */ + ARP_INFO *arptab; + + if ((pa == NULL) || (nif == NULL) || (protocol == 0)) + return 0; + + arptab = nif_get_protocol_info (nif,ETH_FRM_ARP); + *ha = arp_find_pair(arptab,protocol,0,pa); + + if (*ha == NULL) + return 0; + else + return 1; +} + +uint8_t *arp_resolve(NIF *nif, uint16_t protocol, uint8_t *pa) +{ + int i; + uint8_t *hwa; + + /* + * Check to see if the necessary MAC-to-IP translation information + * is in table already + */ + if (arp_resolve_pa(nif, protocol, pa, &hwa)) + return hwa; + + /* + * Ok, it's not, so we need to try to obtain it by broadcasting + * an ARP request. Hopefully the desired host is listening and + * will respond with it's MAC address + */ + for (i = 0; i < 3; i++) + { + arp_request(nif, pa); + + timer_set_secs(TIMER_NETWORK, ARP_TIMEOUT); + while (timer_get_reference(TIMER_NETWORK)) + { + dbg("try to resolve %d.%d.%d.%d\r\n", + pa[0], pa[1], pa[2], pa[3], pa[4]); + if (arp_resolve_pa(nif, protocol, pa, &hwa)) + { + dbg("resolved to %02x:%02x:%02x:%02x:%02x:%02x.\r\n", + hwa[0], hwa[1], hwa[2], hwa[3], hwa[4], hwa[5], hwa[6]); + + return hwa; + } + } + } + + return NULL; +} + +void arp_init(ARP_INFO *arptab) +{ + int slot, i; + + arptab->tab_size = MAX_ARP_ENTRY; + for (slot = 0; slot < arptab->tab_size; slot++) + { + for (i = 0; i < MAX_HWA_SIZE; i++) + arptab->table[slot].hwa[i] = 0; + for (i = 0; i < MAX_PA_SIZE; i++) + arptab->table[slot].pa[i] = 0; + arptab->table[slot].longevity = ARP_ENTRY_EMPTY; + arptab->table[slot].hwa_size = 0; + arptab->table[slot].pa_size = 0; + } +} + +void arp_handler(NIF *nif, NBUF *pNbuf) +{ + /* + * ARP protocol handler + */ + uint8_t *addr; + ARP_INFO *arptab; + int longevity; + arp_frame_hdr *rx_arpframe, *tx_arpframe; + + arptab = nif_get_protocol_info(nif, ETH_FRM_ARP); + rx_arpframe = (arp_frame_hdr *) &pNbuf->data[pNbuf->offset]; + + /* + * Check for an appropriate ARP packet + */ + if ((pNbuf->length < ARP_HDR_LEN) || + (rx_arpframe->ar_hrd != ETHERNET) || + (rx_arpframe->ar_hln != 6) || + (rx_arpframe->ar_pro != ETH_FRM_IP) || + (rx_arpframe->ar_pln != 4)) + { + dbg("received packet is not an ARP packet, discard it\r\n"); + nbuf_free(pNbuf); + return; + } + + /* + * Check to see if it was addressed to me - if it was, keep this + * ARP entry in the table permanently; if not, mark it so that it + * can be displaced later if necessary + */ + addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP)); + if ((rx_arpframe->ar_tpa[0] == addr[0]) && + (rx_arpframe->ar_tpa[1] == addr[1]) && + (rx_arpframe->ar_tpa[2] == addr[2]) && + (rx_arpframe->ar_tpa[3] == addr[3]) ) + { + dbg("received ARP packet is a permanent one, store it\r\n"); + longevity = ARP_ENTRY_PERM; + } + else + { + dbg("received ARP packet was not addressed to us, keep only temporarily\r\n"); + longevity = ARP_ENTRY_TEMP; + } + + /* + * Add ARP info into the table + */ + arp_merge(arptab, + rx_arpframe->ar_pro, + rx_arpframe->ar_hln, + &rx_arpframe->ar_sha[0], + rx_arpframe->ar_pln, + &rx_arpframe->ar_spa[0], + longevity + ); + + switch (rx_arpframe->opcode) + { + case ARP_REQUEST: + /* + * Check to see if request is directed to me + */ + if ((rx_arpframe->ar_tpa[0] == addr[0]) && + (rx_arpframe->ar_tpa[1] == addr[1]) && + (rx_arpframe->ar_tpa[2] == addr[2]) && + (rx_arpframe->ar_tpa[3] == addr[3]) ) + { + dbg("received arp request directed to us, replying\r\n"); + /* + * Reuse the current network buffer to assemble an ARP reply + */ + tx_arpframe = (arp_frame_hdr *)&pNbuf->data[ARP_HDR_OFFSET]; + + /* + * Build new ARP frame from the received data + */ + tx_arpframe->ar_hrd = ETHERNET; + tx_arpframe->ar_pro = ETH_FRM_IP; + tx_arpframe->ar_hln = 6; + tx_arpframe->ar_pln = 4; + tx_arpframe->opcode = ARP_REPLY; + tx_arpframe->ar_tha[0] = rx_arpframe->ar_sha[0]; + tx_arpframe->ar_tha[1] = rx_arpframe->ar_sha[1]; + tx_arpframe->ar_tha[2] = rx_arpframe->ar_sha[2]; + tx_arpframe->ar_tha[3] = rx_arpframe->ar_sha[3]; + tx_arpframe->ar_tha[4] = rx_arpframe->ar_sha[4]; + tx_arpframe->ar_tha[5] = rx_arpframe->ar_sha[5]; + tx_arpframe->ar_tpa[0] = rx_arpframe->ar_spa[0]; + tx_arpframe->ar_tpa[1] = rx_arpframe->ar_spa[1]; + tx_arpframe->ar_tpa[2] = rx_arpframe->ar_spa[2]; + tx_arpframe->ar_tpa[3] = rx_arpframe->ar_spa[3]; + + /* + * Now copy in the new information + */ + addr = &nif->hwa[0]; + tx_arpframe->ar_sha[0] = addr[0]; + tx_arpframe->ar_sha[1] = addr[1]; + tx_arpframe->ar_sha[2] = addr[2]; + tx_arpframe->ar_sha[3] = addr[3]; + tx_arpframe->ar_sha[4] = addr[4]; + tx_arpframe->ar_sha[5] = addr[5]; + + addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP)); + tx_arpframe->ar_spa[0] = addr[0]; + tx_arpframe->ar_spa[1] = addr[1]; + tx_arpframe->ar_spa[2] = addr[2]; + tx_arpframe->ar_spa[3] = addr[3]; + + /* + * Save the length of my packet in the buffer structure + */ + pNbuf->length = ARP_HDR_LEN; + + nif->send(nif, + &tx_arpframe->ar_tha[0], + &tx_arpframe->ar_sha[0], + ETH_FRM_ARP, + pNbuf); + } + else + { + dbg("ARP request not addressed to us, discarding\r\n"); + nbuf_free(pNbuf); + } + break; + + case ARP_REPLY: + /* + * The ARP Reply case is already taken care of + */ + + /* missing break is intentional */ + + default: + nbuf_free(pNbuf); + break; + } + + return; +} diff --git a/net/bcm5222.c b/net/bcm5222.c new file mode 100644 index 0000000..b56b3dd --- /dev/null +++ b/net/bcm5222.c @@ -0,0 +1,178 @@ +/* + * File: bcm5222.c + * Purpose: Driver for the Micrel BCM5222 10/100 Ethernet PHY + * + * Notes: This driver was written specifically for the M5475EVB + * and M5485EVB. These boards use the MII signals from + * FEC0 to control the PHY. Therefore the fec_ch parameter + * is ignored when doing MII reads and writes. + */ + +#include "net.h" +#include "fec.h" +#include "bcm5222.h" + +#include "bas_printf.h" + +#if defined(MACHINE_FIREBEE) +#include "firebee.h" +#elif defined(MACHINE_M5484LITE) +#include "m5484l.h" +#elif defined(MACHINE_M54455) +#include "m54455.h" +#else +#error "Unknown machine!" +#endif + +// #define DEBUG +#include "debug.h" + +/* + * Initialize the BCM5222 PHY + * + * This function sets up the Auto-Negotiate Advertisement register + * within the PHY and then forces the PHY to auto-negotiate for + * it's settings. + * + * Params: + * fec_ch FEC channel + * phy_addr Address of the PHY. + * speed Desired speed (10BaseT or 100BaseTX) + * duplex Desired duplex (Full or Half) + * + * Return Value: + * 0 if MII commands fail + * 1 otherwise + */ +int bcm5222_init(uint8_t fec_ch, uint8_t phy_addr, uint8_t speed, uint8_t duplex) +{ + int timeout; + uint16_t settings; + + /* Initialize the MII interface */ + fec_mii_init(fec_ch, SYSCLK / 1000); + dbg("PHY reset\r\n"); + + /* Reset the PHY */ + if (!fec_mii_write(fec_ch, phy_addr, BCM5222_CTRL, BCM5222_CTRL_RESET | BCM5222_CTRL_ANE)) + return 0; + + /* Wait for the PHY to reset */ + for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++) + { + fec_mii_read(fec_ch, phy_addr, BCM5222_CTRL, &settings); + if (!(settings & BCM5222_CTRL_RESET)) + break; + } + if(timeout >= FEC_MII_TIMEOUT) + return 0; + + dbg("PHY reset OK\r\n"); + + settings = (BCM5222_AN_ADV_NEXT_PAGE | BCM5222_AN_ADV_PAUSE); + + if (speed == FEC_MII_10BASE_T) + settings |= (uint16_t)((duplex == FEC_MII_FULL_DUPLEX) + ? (BCM5222_AN_ADV_10BT_FDX | BCM5222_AN_ADV_10BT) + : BCM5222_AN_ADV_10BT); + else /* (speed == FEC_MII_100BASE_TX) */ + settings = (uint16_t)((duplex == FEC_MII_FULL_DUPLEX) + ? (BCM5222_AN_ADV_100BTX_FDX | BCM5222_AN_ADV_100BTX + | BCM5222_AN_ADV_10BT_FDX | BCM5222_AN_ADV_10BT) + : (BCM5222_AN_ADV_100BTX | BCM5222_AN_ADV_10BT)); + + /* Set the Auto-Negotiation Advertisement Register */ + if (!fec_mii_write(fec_ch, phy_addr, BCM5222_AN_ADV, settings)) + return 0; + + dbg("PHY Enable Auto-Negotiation\r\n"); + + /* Enable Auto-Negotiation */ + if (!fec_mii_write(fec_ch, phy_addr, BCM5222_CTRL, (BCM5222_CTRL_ANE | BCM5222_CTRL_RESTART_AN))) + return 0; + + dbg("PHY Wait for auto-negotiation to complete\r\n"); + + /* Wait for auto-negotiation to complete */ + for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++) + { + if (!fec_mii_read(fec_ch, phy_addr, BCM5222_STAT, &settings)) + return 0; + if (settings & BCM5222_STAT_AN_COMPLETE) + break; + } + + if (timeout < FEC_MII_TIMEOUT) + { + dbg("PHY auto-negociation complete\r\n"); + + /* Read Auxiliary Control/Status Register */ + if (!fec_mii_read(fec_ch, phy_addr, BCM5222_ACSR, &settings)) + return 0; + } + else + { + dbg("auto negotiation failed, PHY Set the default mode\r\n"); + + /* Set the default mode (Full duplex, 100 Mbps) */ + if (!fec_mii_write(fec_ch, phy_addr, BCM5222_ACSR, settings = (BCM5222_ACSR_100BTX | BCM5222_ACSR_FDX))) + return 0; + } + + /* Set the proper duplex in the FEC now that we have auto-negotiated */ + if (settings & BCM5222_ACSR_FDX) + fec_duplex(fec_ch, FEC_MII_FULL_DUPLEX); + else + fec_duplex(fec_ch, FEC_MII_HALF_DUPLEX); + + dbg("PHY Mode: "); + + if (settings & BCM5222_ACSR_100BTX) + dbg("100Mbps\r\n"); + else + dbg("10Mbps\r\n"); + + if (settings & BCM5222_ACSR_FDX) + dbg("Full-duplex\r\n"); + else + dbg("Half-duplex\r\n"); + + return 1; +} + +void bcm5222_get_reg(uint16_t* status0, uint16_t* status1) +{ + fec_mii_read(0, 0x00, 0x00000000, &status0[0]); + fec_mii_read(0, 0x00, 0x00000001, &status0[1]); + fec_mii_read(0, 0x00, 0x00000004, &status0[4]); + fec_mii_read(0, 0x00, 0x00000005, &status0[5]); + fec_mii_read(0, 0x00, 0x00000006, &status0[6]); + fec_mii_read(0, 0x00, 0x00000007, &status0[7]); + fec_mii_read(0, 0x00, 0x00000008, &status0[8]); + fec_mii_read(0, 0x00, 0x00000010, &status0[16]); + fec_mii_read(0, 0x00, 0x00000011, &status0[17]); + fec_mii_read(0, 0x00, 0x00000012, &status0[18]); + fec_mii_read(0, 0x00, 0x00000013, &status0[19]); + fec_mii_read(0, 0x00, 0x00000018, &status0[24]); + fec_mii_read(0, 0x00, 0x00000019, &status0[25]); + fec_mii_read(0, 0x00, 0x0000001B, &status0[27]); + fec_mii_read(0, 0x00, 0x0000001C, &status0[28]); + fec_mii_read(0, 0x00, 0x0000001E, &status0[30]); + fec_mii_read(0, 0x01, 0x00000000, &status1[0]); + fec_mii_read(0, 0x01, 0x00000001, &status1[1]); + fec_mii_read(0, 0x01, 0x00000004, &status1[4]); + fec_mii_read(0, 0x01, 0x00000005, &status1[5]); + fec_mii_read(0, 0x01, 0x00000006, &status1[6]); + fec_mii_read(0, 0x01, 0x00000007, &status1[7]); + fec_mii_read(0, 0x01, 0x00000008, &status1[8]); + fec_mii_read(0, 0x01, 0x00000010, &status1[16]); + fec_mii_read(0, 0x01, 0x00000011, &status1[17]); + fec_mii_read(0, 0x01, 0x00000012, &status1[18]); + fec_mii_read(0, 0x01, 0x00000013, &status1[19]); + fec_mii_read(0, 0x01, 0x00000018, &status1[24]); + fec_mii_read(0, 0x01, 0x00000019, &status1[25]); + fec_mii_read(0, 0x01, 0x0000001B, &status1[27]); + fec_mii_read(0, 0x01, 0x0000001C, &status1[28]); + fec_mii_read(0, 0x01, 0x0000001E, &status1[30]); +} + diff --git a/net/bootp.c b/net/bootp.c new file mode 100644 index 0000000..426e732 --- /dev/null +++ b/net/bootp.c @@ -0,0 +1,114 @@ +/* + * File: bootp.c + * Purpose: Address Resolution Protocol routines. + * + * Notes: + */ + +#include "net.h" +#include "bootp.h" +#include +#include +#include "bas_printf.h" + +// #define DEBUG +#include "debug.h" + +#define TIMER_NETWORK 3 /* defines GPT3 as timer for this function */ + +static struct bootp_connection connection; +#define XID 0x1234 /* this is arbitrary */ +#define MAX_TRIES 5 /* since UDP can fail */ + +void bootp_request(NIF *nif, uint8_t *pa) +{ + /* + * This function broadcasts a BOOTP request for the protocol + * address "pa" + */ + uint8_t *addr; + IP_ADDR broadcast = {255, 255, 255, 255}; + NBUF *nbuf; + struct bootp_packet *p; + int i, result; + + nbuf = nbuf_alloc(); + if (nbuf == NULL) + { + xprintf("%s: couldn't allocate Tx buffer\r\n", __FUNCTION__); + return; + } + + p = (struct bootp_packet *) &nbuf->data[BOOTP_HDR_OFFSET]; + + /* Build the BOOTP request packet */ + p->type = BOOTP_TYPE_BOOTREQUEST; + p->htype = BOOTP_HTYPE_ETHERNET; + p->hlen = BOOTP_HLEN_ETHERNET; + p->hops = 0; + p->xid = XID; + p->secs = 1; + p->flags = BOOTP_FLAGS_BROADCAST; + p->cl_addr = 0x0; + p->yi_addr = 0x0; + p->gi_addr = 0x0; + + connection.nif = nif; + addr = &nif->hwa[0]; + + for (i = 0; i < 6; i++) + p->ch_addr[i] = addr[i]; + + nbuf->length = BOOTP_PACKET_LEN; + + /* setup reply handler */ + udp_bind_port(BOOTP_CLIENT_PORT, bootp_handler); + + for (i = 0; i < MAX_TRIES; i++) + { + /* Send the BOOTP request */ + result = udp_send(connection.nif, broadcast, BOOTP_CLIENT_PORT, + BOOTP_SERVER_PORT, nbuf); + dbg("sent bootp request\r\n"); + if (result == true) + break; + } + + /* release handler */ + udp_free_port(BOOTP_CLIENT_PORT); + + if (result == 0) + nbuf_free(nbuf); +} + +void bootp_handler(NIF *nif, NBUF *nbuf) +{ + /* + * BOOTP protocol handler + */ + struct bootp_packet *rx_p; + udp_frame_hdr *udpframe; + + (void) udpframe; /* FIXME: just to avoid compiler warning */ + dbg("\r\n"); + + rx_p = (struct bootp_packet *) &nbuf->data[nbuf->offset]; + udpframe = (udp_frame_hdr *) &nbuf->data[nbuf->offset - UDP_HDR_SIZE]; + + /* + * check packet if it is valid and if it is really intended for us + */ + + if (rx_p->type == BOOTP_TYPE_BOOTREPLY && rx_p->xid == XID) + { + dbg("received bootp reply\r\n"); + /* seems to be valid */ + + } + else + { + dbg("received invalid bootp reply\r\n"); + /* not valid */ + return; + } +} diff --git a/net/fec.c b/net/fec.c new file mode 100644 index 0000000..ce8c2d9 --- /dev/null +++ b/net/fec.c @@ -0,0 +1,1442 @@ +/* + * File: fec.c + * Purpose: Driver for the Fast Ethernet Controller (FEC) + * + * Notes: + */ + +#include "net.h" +#include "fec.h" +#include "fecbd.h" +#include "exceptions.h" +#include "interrupts.h" +#include "MCF5475.h" +#include "MCD_dma.h" +#include "mcd_initiators.h" +#include "dma.h" +#include "bas_string.h" +#include "bas_printf.h" +#include "util.h" +#include "wait.h" +#include "am79c874.h" +//#include "bcm5222.h" +#include + +#if defined(MACHINE_FIREBEE) +#include "firebee.h" +#elif defined(MACHINE_M5484LITE) +#include "m5484l.h" +#elif defined(MACHINE_M54455) +#include "m54455.h" +#else +#error Unknown machine! +#endif + +// #define DEBUG +#include "debug.h" + + +FEC_EVENT_LOG fec_log[2]; + +/* + * Write a value to a PHY's MII register. + * + * Parameters: + * ch FEC channel + * phy_addr Address of the PHY. + * reg_addr Address of the register in the PHY. + * data Data to be written to the PHY register. + * + * Return Values: + * 1 on failure + * 0 on success. + * + * Please refer to your PHY manual for registers and their meanings. + * mii_write() polls for the FEC's MII interrupt event (which should + * be masked from the interrupt handler) and clears it. If after a + * suitable amount of time the event isn't triggered, a value of 0 + * is returned. + */ +int fec_mii_write(uint8_t ch, uint8_t phy_addr, uint8_t reg_addr, uint16_t data) +{ + int timeout; + uint32_t eimr; + + /* + * Clear the MII interrupt bit + */ + MCF_FEC_EIR(ch) = MCF_FEC_EIR_MII; + + /* + * Write to the MII Management Frame Register to kick-off + * the MII write + */ + MCF_FEC_MMFR(ch) = 0 + | MCF_FEC_MMFR_ST_01 + | MCF_FEC_MMFR_OP_WRITE + | MCF_FEC_MMFR_PA(phy_addr) + | MCF_FEC_MMFR_RA(reg_addr) + | MCF_FEC_MMFR_TA_10 + | MCF_FEC_MMFR_DATA(data); + + /* + * Mask the MII interrupt + */ + eimr = MCF_FEC_EIMR(ch); + MCF_FEC_EIMR(ch) &= ~MCF_FEC_EIMR_MII; + + /* + * Poll for the MII interrupt (interrupt should be masked) + */ + for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++) + { + wait(1); + if (MCF_FEC_EIR(ch) & MCF_FEC_EIR_MII) + break; + } + + if (timeout == FEC_MII_TIMEOUT) + return 0; + + /* + * Clear the MII interrupt bit + */ + MCF_FEC_EIR(ch) = MCF_FEC_EIR_MII; + + /* + * Restore the EIMR + */ + MCF_FEC_EIMR(ch) = eimr; + + return 1; +} + +/* + * Read a value from a PHY's MII register. + * + * Parameters: + * ch FEC channel + * phy_addr Address of the PHY. + * reg_addr Address of the register in the PHY. + * data Pointer to storage for the Data to be read + * from the PHY register (passed by reference) + * + * Return Values: + * 1 on failure + * 0 on success. + * + * Please refer to your PHY manual for registers and their meanings. + * mii_read() polls for the FEC's MII interrupt event (which should + * be masked from the interrupt handler) and clears it. If after a + * suitable amount of time the event isn't triggered, a value of 0 + * is returned. + */ +int fec_mii_read(uint8_t ch, uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) +{ + int timeout; + + /* + * Clear the MII interrupt bit + */ + MCF_FEC_EIR(ch) = MCF_FEC_EIR_MII; + + /* + * Write to the MII Management Frame Register to kick-off + * the MII read + */ + MCF_FEC_MMFR(ch) = 0 + | MCF_FEC_MMFR_ST_01 + | MCF_FEC_MMFR_OP_READ + | MCF_FEC_MMFR_PA(phy_addr) + | MCF_FEC_MMFR_RA(reg_addr) + | MCF_FEC_MMFR_TA_10; + + /* + * Poll for the MII interrupt (interrupt should be masked) + */ + for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++) + { + wait(1); + if (MCF_FEC_EIR(ch) & MCF_FEC_EIR_MII) + break; + } + + if (timeout == FEC_MII_TIMEOUT) + return 0; + + /* + * Clear the MII interrupt bit + */ + MCF_FEC_EIR(ch) = MCF_FEC_EIR_MII; + + *data = (uint16_t)(MCF_FEC_MMFR(ch) & 0x0000FFFF); + + return 1; +} + +/* + * Initialize the MII interface controller + * + * Parameters: + * ch FEC channel + * sys_clk System Clock Frequency (in MHz) + */ +void fec_mii_init(uint8_t ch, uint32_t sys_clk) +{ + /* + * Initialize the MII clock (EMDC) frequency + * + * Desired MII clock is 2.5MHz + * MII Speed Setting = System_Clock / (2.5MHz * 2) + * (plus 1 to make sure we round up) + */ + MCF_FEC_MSCR(ch) = MCF_FEC_MSCR_MII_SPEED((sys_clk / 5) + 1); +} + +/* Initialize the MIB counters + * + * Parameters: + * ch FEC channel + */ +void fec_mib_init(uint8_t ch) +{ + //To do +} + +/* + * Display the MIB counters + * + * Parameters: + * ch FEC channel + */ +void fec_mib_dump(uint8_t ch) +{ + //To do +} + +/* + * Initialize the FEC log + * + * Parameters: + * ch FEC channel + */ +void fec_log_init(uint8_t ch) +{ + memset(&fec_log[ch], 0, sizeof(FEC_EVENT_LOG)); +} + +/* + * Display the FEC log + * + * Parameters: + * ch FEC channel + */ +void fec_log_dump(uint8_t ch) +{ + dbg("\r\n FEC%d Log\r\n", __FUNCTION__, ch); + dbg(" ---------------\r\n", __FUNCTION__); + dbg(" Total: %4d\r\n", fec_log[ch].total); + dbg(" hberr: %4d\r\n", fec_log[ch].hberr); + dbg(" babr: %4d\r\n", fec_log[ch].babr); + dbg(" babt: %4d\r\n", fec_log[ch].babt); + dbg(" gra: %4d\r\n", fec_log[ch].gra); + dbg(" txf: %4d\r\n", fec_log[ch].txf); + dbg(" mii: %4d\r\n", fec_log[ch].mii); + dbg(" lc: %4d\r\n", fec_log[ch].lc); + dbg(" rl: %4d\r\n", fec_log[ch].rl); + dbg(" xfun: %4d\r\n", fec_log[ch].xfun); + dbg(" xferr: %4d\r\n", fec_log[ch].xferr); + dbg(" rferr: %4d\r\n", fec_log[ch].rferr); + dbg(" dtxf: %4d\r\n", fec_log[ch].dtxf); + dbg(" drxf: %4d\r\n", fec_log[ch].drxf); + dbg(" \r\nRFSW:\r\n"); + dbg(" inv: %4d\r\n", fec_log[ch].rfsw_inv); + dbg(" m: %4d\r\n", fec_log[ch].rfsw_m); + dbg(" bc: %4d\r\n", fec_log[ch].rfsw_bc); + dbg(" mc: %4d\r\n", fec_log[ch].rfsw_mc); + dbg(" lg: %4d\r\n", fec_log[ch].rfsw_lg); + dbg(" no: %4d\r\n", fec_log[ch].rfsw_no); + dbg(" cr: %4d\r\n", fec_log[ch].rfsw_cr); + dbg(" ov: %4d\r\n", fec_log[ch].rfsw_ov); + dbg(" tr: %4d\r\n", fec_log[ch].rfsw_tr); + dbg(" ---------------\r\n\r\n"); +} + +/* + * Display some of the registers for debugging + * + * Parameters: + * ch FEC channel + */ +void fec_debug_dump(uint8_t ch) +{ + dbg("\r\n------------- FEC%d -------------\r\n",ch); + dbg("EIR %08x \r\n", MCF_FEC_EIR(ch)); + dbg("EIMR %08x \r\n", MCF_FEC_EIMR(ch)); + dbg("ECR %08x \r\n", MCF_FEC_ECR(ch)); + dbg("RCR %08x \r\n", MCF_FEC_RCR(ch)); + dbg("R_HASH %08x \r\n", MCF_FEC_RHR_HASH(ch)); + dbg("TCR %08x \r\n", MCF_FEC_TCR(ch)); + dbg("FECTFWR %08x \r\n", MCF_FEC_FECTFWR(ch)); + dbg("FECRFSR %08x \r\n", MCF_FEC_FECRFSR(ch)); + dbg("FECRFCR %08x \r\n", MCF_FEC_FECRFCR(ch)); + dbg("FECRLRFP %08x \r\n", MCF_FEC_FECRLRFP(ch)); + dbg("FECRLWFP %08x \r\n", MCF_FEC_FECRLWFP(ch)); + dbg("FECRFAR %08x \r\n", MCF_FEC_FECRFAR(ch)); + dbg("FECRFRP %08x \r\n", MCF_FEC_FECRFRP(ch)); + dbg("FECRFWP %08x \r\n", MCF_FEC_FECRFWP(ch)); + dbg("FECTFSR %08x \r\n", MCF_FEC_FECTFSR(ch)); + dbg("FECTFCR %08x \r\n", MCF_FEC_FECTFCR(ch)); + dbg("FECTLRFP %08x \r\n", MCF_FEC_FECTLRFP(ch)); + dbg("FECTLWFP %08x \r\n", MCF_FEC_FECTLWFP(ch)); + dbg("FECTFAR %08x \r\n", MCF_FEC_FECTFAR(ch)); + dbg("FECTFRP %08x \r\n", MCF_FEC_FECTFRP(ch)); + dbg("FECTFWP %08x \r\n", MCF_FEC_FECTFWP(ch)); + dbg("FRST %08x \r\n", MCF_FEC_FECFRST(ch)); + dbg("--------------------------------\r\n\r\n"); +} + +/* + * Set the duplex on the selected FEC controller + * + * Parameters: + * ch FEC channel + * duplex FEC_MII_FULL_DUPLEX or FEC_MII_HALF_DUPLEX + */ +void fec_duplex(uint8_t ch, uint8_t duplex) +{ + switch (duplex) + { + case FEC_MII_HALF_DUPLEX: + MCF_FEC_RCR(ch) |= MCF_FEC_RCR_DRT; + MCF_FEC_TCR(ch) &= (uint32_t) ~MCF_FEC_TCR_FDEN; + break; + case FEC_MII_FULL_DUPLEX: + default: + MCF_FEC_RCR(ch) &= (uint32_t) ~MCF_FEC_RCR_DRT; + MCF_FEC_TCR(ch) |= MCF_FEC_TCR_FDEN; + break; + } +} + +/* + * Generate the hash table settings for the given address + * + * Parameters: + * addr 48-bit (6 byte) Address to generate the hash for + * + * Return Value: + * The 6 most significant bits of the 32-bit CRC result + */ +uint8_t fec_hash_address(const uint8_t *addr) +{ + uint32_t crc; + uint8_t byte; + int i, j; + + crc = 0xFFFFFFFF; + for (i = 0; i < 6; ++i) + { + byte = addr[i]; + for (j = 0; j < 8; ++j) + { + if ((byte & 0x01) ^ (crc & 0x01)) + { + crc >>= 1; + crc = crc ^ 0xEDB88320; + } + else + crc >>= 1; + byte >>= 1; + } + } + return (uint8_t)(crc >> 26); +} + +/* + * Set the Physical (Hardware) Address and the Individual Address + * Hash in the selected FEC + * + * Parameters: + * ch FEC channel + * pa Physical (Hardware) Address for the selected FEC + */ +void fec_set_address(uint8_t ch, const uint8_t *pa) +{ + uint8_t crc; + + /* + * Set the Physical Address + */ + MCF_FEC_PALR(ch) = (uint32_t) ((pa[0] << 24) | (pa[1] << 16) | (pa[2] << 8) | pa[3]); + MCF_FEC_PAHR(ch) = (uint32_t) ((pa[4] << 24) | (pa[5] << 16)); + + /* + * Calculate and set the hash for given Physical Address + * in the Individual Address Hash registers + */ + crc = fec_hash_address(pa); + if(crc >= 32) + MCF_FEC_IAUR(ch) |= (uint32_t) (1 << (crc - 32)); + else + MCF_FEC_IALR(ch) |= (uint32_t) (1 << crc); +} + +/* + * Reset the selected FEC controller + * + * Parameters: + * ch FEC channel + */ +void fec_reset(uint8_t ch) +{ + int i; + + /* Clear any events in the FIFO status registers */ + MCF_FEC_FECRFSR(ch) = (0 + | MCF_FEC_FECRFSR_OF + | MCF_FEC_FECRFSR_UF + | MCF_FEC_FECRFSR_RXW + | MCF_FEC_FECRFSR_FAE + | MCF_FEC_FECRFSR_IP); + MCF_FEC_FECTFSR(ch) = (0 + | MCF_FEC_FECTFSR_OF + | MCF_FEC_FECTFSR_UF + | MCF_FEC_FECTFSR_TXW + | MCF_FEC_FECTFSR_FAE + | MCF_FEC_FECTFSR_IP); + + /* Reset the FIFOs */ + MCF_FEC_FECFRST(ch) |= MCF_FEC_FECFRST_SW_RST; + MCF_FEC_FECFRST(ch) &= ~MCF_FEC_FECFRST_SW_RST; + + /* Set the Reset bit and clear the Enable bit */ + MCF_FEC_ECR(ch) = MCF_FEC_ECR_RESET; + + /* Wait at least 8 clock cycles */ + for (i = 0; i < 10; ++i) + NOP(); +} + +/* + * Initialize the selected FEC + * + * Parameters: + * ch FEC channel + * mode External interface mode (MII, 7-wire, or internal loopback) + * pa Physical (Hardware) Address for the selected FEC + */ +void fec_init(uint8_t ch, uint8_t mode, const uint8_t *pa) +{ + /* + * Enable all the external interface signals + */ + if (mode == FEC_MODE_7WIRE) + { + if (ch == 1) + MCF_PAD_PAR_FECI2CIRQ |= MCF_PAD_PAR_FECI2CIRQ_PAR_E17; + else + MCF_PAD_PAR_FECI2CIRQ |= MCF_PAD_PAR_FECI2CIRQ_PAR_E07; + } + else if (mode == FEC_MODE_MII) + { + if (ch == 1) + MCF_PAD_PAR_FECI2CIRQ |= 0 + | MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC + | MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO + | MCF_PAD_PAR_FECI2CIRQ_PAR_E1MII + | MCF_PAD_PAR_FECI2CIRQ_PAR_E17; + else + MCF_PAD_PAR_FECI2CIRQ |= 0 + | MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC + | MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO + | MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII + | MCF_PAD_PAR_FECI2CIRQ_PAR_E07; + } + + /* + * Clear the Individual and Group Address Hash registers + */ + MCF_FEC_IALR(ch) = 0; + MCF_FEC_IAUR(ch) = 0; + MCF_FEC_GALR(ch) = 0; + MCF_FEC_GAUR(ch) = 0; + + /* + * Set the Physical Address for the selected FEC + */ + fec_set_address(ch, pa); + + /* + * Mask all FEC interrupts + */ + MCF_FEC_EIMR(ch) = MCF_FEC_EIMR_MASK_ALL; + + /* + * Clear all FEC interrupt events + */ + MCF_FEC_EIR(ch) = MCF_FEC_EIR_CLEAR_ALL; + + /* + * Initialize the Receive Control Register + */ + MCF_FEC_RCR(ch) = 0 + | MCF_FEC_RCR_MAX_FL(ETH_MAX_FRM) + | MCF_FEC_RCR_PROM + | MCF_FEC_RCR_FCE; + + if (mode == FEC_MODE_MII) + MCF_FEC_RCR(ch) |= MCF_FEC_RCR_MII_MODE; + + else if (mode == FEC_MODE_LOOPBACK) + MCF_FEC_RCR(ch) |= MCF_FEC_RCR_LOOP; + + /* + * Initialize the Transmit Control Register + */ + MCF_FEC_TCR(ch) = MCF_FEC_TCR_FDEN; + + /* + * Set Rx FIFO alarm and granularity + */ + MCF_FEC_FECRFCR(ch) = 0 + | MCF_FEC_FECRFCR_FRMEN + | MCF_FEC_FECRFCR_RXW_MSK + | MCF_FEC_FECRFCR_GR(7); + MCF_FEC_FECRFAR(ch) = MCF_FEC_FECRFAR_ALARM(768); + + /* + * Set Tx FIFO watermark, alarm and granularity + */ + MCF_FEC_FECTFCR(ch) = 0 + | MCF_FEC_FECTFCR_FRMEN + | MCF_FEC_FECTFCR_TXW_MASK + | MCF_FEC_FECTFCR_GR(7); + MCF_FEC_FECTFAR(ch) = MCF_FEC_FECTFAR_ALARM(256); + MCF_FEC_FECTFWR(ch) = MCF_FEC_FECTFWR_X_WMRK_256; + + /* + * Enable the transmitter to append the CRC + */ + MCF_FEC_FECCTCWR(ch) = 0 + | MCF_FEC_FECCTCWR_TFCW + | MCF_FEC_FECCTCWR_CRC; +} + +/* + * Start the FEC Rx DMA task + * + * Parameters: + * ch FEC channel + * rxbd First Rx buffer descriptor in the chain + */ +void fec_rx_start(uint8_t ch, int8_t *rxbd) +{ + uint32_t initiator; + int channel; +#ifdef DBG_FEC + int res; +#endif + + /* + * Make the initiator assignment + */ +#if defined(DBG_FEC) + res = +#else + (void) +#endif + dma_set_initiator(DMA_FEC_RX(ch)); + dbg("dma_set_initiator(DMA_FEC_RX(%d)): %d\r\n", ch, res); + + /* + * Grab the initiator number + */ + initiator = dma_get_initiator(DMA_FEC_RX(ch)); + dbg("dma_get_initiator(DMA_FEC_RX(%d)) = %d\r\n", ch, initiator); + + /* + * Determine the DMA channel running the task for the + * selected FEC + */ + channel = dma_set_channel(DMA_FEC_RX(ch), + (ch == 0) ? fec0_rx_frame : fec1_rx_frame); + dbg("DMA channel for FEC%1d: %d\r\n", ch, channel); + + /* + * Start the Rx DMA task + */ + MCD_startDma(channel, + (s8 *) rxbd, + 0, + (s8 *) MCF_FEC_FECRFDR(ch), + 0, + RX_BUF_SZ, + 0, + initiator, + FECRX_DMA_PRI(ch), + 0 + | MCD_FECRX_DMA + | MCD_INTERRUPT + | MCD_TT_FLAGS_CW + | MCD_TT_FLAGS_RL + | MCD_TT_FLAGS_SP + , + 0 + | MCD_NO_CSUM + | MCD_NO_BYTE_SWAP + ); + dbg("Rx DMA task for FEC%1d started\r\n", ch); +} + +/* + * Continue the Rx DMA task + * + * This routine is called after the DMA task has halted after + * encountering an Rx buffer descriptor that wasn't marked as + * ready. There is no harm in calling the DMA continue routine + * if the DMA is not halted. + * + * Parameters: + * ch FEC channel + */ +void fec_rx_continue(uint8_t ch) +{ + int channel; + + /* + * Determine the DMA channel running the task for the + * selected FEC + */ + channel = dma_get_channel(DMA_FEC_RX(ch)); + + dbg("RX DMA channel for FEC%1d is %d\r\n", ch, channel); + + /* + * Continue/restart the DMA task + */ + MCD_continDma(channel); + dbg("RX dma on channel %d continued\r\n", channel); +} + +/* + * Stop all frame receptions on the selected FEC + * + * Parameters: + * ch FEC channel + */ +void fec_rx_stop (uint8_t ch) +{ + uint32_t mask; + int channel; + + /* Save off the EIMR value */ + mask = MCF_FEC_EIMR(ch); + + /* Mask all interrupts */ + MCF_FEC_EIMR(ch) = 0; + + /* + * Determine the DMA channel running the task for the + * selected FEC + */ + channel = dma_get_channel(DMA_FEC_RX(ch)); + + /* Kill the FEC Rx DMA task */ + MCD_killDma(channel); + + /* + * Free up the FEC requestor from the software maintained + * initiator list + */ + dma_free_initiator(DMA_FEC_RX(ch)); + + /* Free up the DMA channel */ + dma_free_channel(DMA_FEC_RX(ch)); + + /* Restore the interrupt mask register value */ + MCF_FEC_EIMR(ch) = mask; +} + +/* + * Receive Frame interrupt handler - this handler is called by the + * DMA interrupt handler indicating that a packet was successfully + * transferred out of the Rx FIFO. + * + * Parameters: + * nif Pointer to Network Interface structure + * ch FEC channel + */ +void fec_rx_frame(uint8_t ch, NIF *nif) +{ + ETH_HDR *eth_hdr; + FECBD *pRxBD; + NBUF *cur_nbuf, *new_nbuf; + int keep; + + dbg("started\r\n"); + + while ((pRxBD = fecbd_rx_alloc(ch)) != NULL) + { + fec_log[ch].drxf++; + keep = true; + + /* + * Check the Receive Frame Status Word for errors + * - The L bit should always be set + * - No undefined bits should be set + * - The upper 5 bits of the length should be cleared + */ + if (!(pRxBD->status & RX_BD_L) || (pRxBD->status & 0x0608) + || (pRxBD->length & 0xF800)) + { + keep = false; + fec_log[ch].rfsw_inv++; + } + else if (pRxBD->status & RX_BD_ERROR) + { + keep = false; + if (pRxBD->status & RX_BD_NO) + fec_log[ch].rfsw_no++; + if (pRxBD->status & RX_BD_CR) + fec_log[ch].rfsw_cr++; + if (pRxBD->status & RX_BD_OV) + fec_log[ch].rfsw_ov++; + if (pRxBD->status & RX_BD_TR) + fec_log[ch].rfsw_tr++; + } + else + { + if (pRxBD->status & RX_BD_LG) + fec_log[ch].rfsw_lg++; + if (pRxBD->status & RX_BD_M) + fec_log[ch].rfsw_m++; + if (pRxBD->status & RX_BD_BC) + fec_log[ch].rfsw_bc++; + if (pRxBD->status & RX_BD_MC) + fec_log[ch].rfsw_mc++; + } + + if (keep) + { + /* + * Pull the network buffer off the Rx ring queue + */ + cur_nbuf = nbuf_remove(NBUF_RX_RING); + + /* + * Copy the buffer descriptor information to the network buffer + */ + cur_nbuf->length = (pRxBD->length - (ETH_HDR_LEN + ETH_CRC_LEN)); + cur_nbuf->offset = ETH_HDR_LEN; + + /* + * Get a new buffer pointer for this buffer descriptor + */ + new_nbuf = nbuf_alloc(); + if (new_nbuf == NULL) + { + dbg("nbuf_alloc() failed\n"); + + /* + * Can't allocate a new network buffer, so we + * have to trash the received data and reuse the buffer + * hoping that some buffers will free up in the system + * and this frame will be re-transmitted by the host + */ + pRxBD->length = RX_BUF_SZ; + pRxBD->status &= (RX_BD_W | RX_BD_INTERRUPT); + pRxBD->status |= RX_BD_E; + nbuf_add(NBUF_RX_RING, cur_nbuf); + fec_rx_continue(ch); + + continue; + } + + /* + * Add the new network buffer to the Rx ring queue + */ + nbuf_add(NBUF_RX_RING, new_nbuf); + + /* + * Re-initialize the buffer descriptor - pointing it + * to the new data buffer. The previous data buffer + * will be passed up the stack + */ + pRxBD->data = new_nbuf->data; + pRxBD->length = RX_BUF_SZ; + pRxBD->status &= (RX_BD_W | RX_BD_INTERRUPT); + pRxBD->status |= RX_BD_E; + + + /* + * Let the DMA know that there is a new Rx BD (in case the + * ring was full and the DMA was waiting for an empty one) + */ + fec_rx_continue(ch); + + /* + * Get pointer to the frame data inside the network buffer + */ + eth_hdr = (ETH_HDR *) cur_nbuf->data; + + /* + * Pass the received packet up the network stack if the + * protocol is supported in our network interface (NIF) + */ + if (nif_protocol_exist(nif, eth_hdr->type)) + { + hexdump((uint8_t *) eth_hdr, ETH_MAX_FRM); + nif_protocol_handler(nif, eth_hdr->type, cur_nbuf); + } + else + { + nbuf_free(cur_nbuf); + dbg("got unsupported packet %d, trashed it\r\n", eth_hdr->type); + } + } + else + { + /* + * This frame isn't a keeper + * Reset the status and length, but don't need to get another + * buffer since we are trashing the data in the current one + */ + pRxBD->length = RX_BUF_SZ; + pRxBD->status &= (RX_BD_W | RX_BD_INTERRUPT); + pRxBD->status |= RX_BD_E; + + /* + * Move the current buffer from the beginning to the end of the + * Rx ring queue + */ + cur_nbuf = nbuf_remove(NBUF_RX_RING); + nbuf_add(NBUF_RX_RING, cur_nbuf); + + /* + * Let the DMA know that there are new Rx BDs (in case + * it is waiting for an empty one) + */ + fec_rx_continue(ch); + } + } +} + +void fec0_rx_frame(void) +{ + extern NIF nif1; + + fec_rx_frame(0, &nif1); +} + +void fec1_rx_frame(void) +{ + extern NIF nif1; + + fec_rx_frame(1, &nif1); +} + +/* + * Start the FEC Tx DMA task + * + * Parameters: + * ch FEC channel + * txbd First Tx buffer descriptor in the chain + */ +void fec_tx_start(uint8_t ch, int8_t *txbd) +{ + uint32_t initiator; + int channel; + void fec0_tx_frame(void); + void fec1_tx_frame(void); +#ifdef DBG_FEC + int res; +#endif + + /* + * Make the initiator assignment + */ +#ifdef DBG_FEC + res = +#else + (void) +#endif + dma_set_initiator(DMA_FEC_TX(ch)); + dbg("dma_set_initiator(%d) = %d\r\n", ch, res); + + /* + * Grab the initiator number + */ + initiator = dma_get_initiator(DMA_FEC_TX(ch)); + dbg("dma_get_initiator(%d) = %d\r\n", ch, initiator); + + + /* + * Determine the DMA channel running the task for the + * selected FEC + */ + channel = dma_set_channel(DMA_FEC_TX(ch), + (ch == 0) ? fec0_tx_frame : fec1_tx_frame); + dbg("dma_set_channel(%d, ...) = %d\r\n", ch, channel); + + /* + * Start the Tx DMA task + */ + MCD_startDma(channel, + (s8 *) txbd, + 0, + (s8 *) MCF_FEC_FECTFDR(ch), + 0, + ETH_MTU, + 0, + initiator, + FECTX_DMA_PRI(ch), + 0 + | MCD_FECTX_DMA + | MCD_INTERRUPT + | MCD_TT_FLAGS_CW + | MCD_TT_FLAGS_RL + | MCD_TT_FLAGS_SP + , + 0 + | MCD_NO_CSUM + | MCD_NO_BYTE_SWAP + ); + dbg("DMA tx task started\r\n"); +} + +/* + * Continue the Tx DMA task + * + * This routine is called after the DMA task has halted after + * encountering an Tx buffer descriptor that wasn't marked as + * ready. There is no harm in calling the continue DMA routine + * if the DMA was not paused. + * + * Parameters: + * ch FEC channel + */ +void fec_tx_continue(uint8_t ch) +{ + int channel; + + /* + * Determine the DMA channel running the task for the + * selected FEC + */ + channel = dma_get_channel(DMA_FEC_TX(ch)); + dbg("dma_get_channel(DMA_FEC_TX(%d)) = %d\r\n", ch, channel); + + /* + * Continue/restart the DMA task + */ + MCD_continDma(channel); + dbg("DMA TX task continue\r\n"); +} + +/* + * Stop all transmissions on the selected FEC and kill the DMA task + * + * Parameters: + * ch FEC channel + */ +void fec_tx_stop(uint8_t ch) +{ + uint32_t mask; + int channel; + + + /* Save off the EIMR value */ + mask = MCF_FEC_EIMR(ch); + + /* Mask all interrupts */ + MCF_FEC_EIMR(ch) = 0; + + /* If the Ethernet is still enabled... */ + if (MCF_FEC_ECR(ch) & MCF_FEC_ECR_ETHER_EN) + { + /* Issue the Graceful Transmit Stop */ + MCF_FEC_TCR(ch) |= MCF_FEC_TCR_GTS; + + /* Wait for the Graceful Stop Complete interrupt */ + while (!(MCF_FEC_EIR(ch) & MCF_FEC_EIR_GRA)) + { + if (!(MCF_FEC_ECR(ch) & MCF_FEC_ECR_ETHER_EN)) + break; + } + + /* Clear the Graceful Stop Complete interrupt */ + MCF_FEC_EIR(ch) = MCF_FEC_EIR_GRA; + } + + /* + * Determine the DMA channel running the task for the + * selected FEC + */ + channel = dma_get_channel(DMA_FEC_TX(ch)); + + /* Kill the FEC Tx DMA task */ + MCD_killDma(channel); + + /* + * Free up the FEC requestor from the software maintained + * initiator list + */ + dma_free_initiator(DMA_FEC_TX(ch)); + + /* Free up the DMA channel */ + dma_free_channel(DMA_FEC_TX(ch)); + + /* Restore the interrupt mask register value */ + MCF_FEC_EIMR(ch) = mask; +} + +/* + * Trasmit Frame interrupt handler - this handler is called by the + * DMA interrupt handler indicating that a packet was successfully + * transferred to the Tx FIFO. + * + * Parameters: + * ch FEC channel + */ +void fec_tx_frame(uint8_t ch) +{ + FECBD *pTxBD; + NBUF *pNbuf; + bool is_empty = true; + + dbg("\r\n"); + while ((pTxBD = fecbd_tx_free(ch)) != NULL) + { + fec_log[ch].dtxf++; + + /* + * Grab the network buffer associated with this buffer descriptor + */ + pNbuf = nbuf_remove(NBUF_TX_RING); + + /* + * Free up the network buffer that was just transmitted + */ + nbuf_free(pNbuf); + dbg("free buffer %p from TX ring\r\n", pNbuf); + + /* + * Re-initialize the Tx BD + */ + pTxBD->data = NULL; + pTxBD->length = 0; + is_empty = false; + + } + if (is_empty) + dbg("transmit queue was empty!\r\n"); +} + +void fec0_tx_frame(void) +{ + fec_tx_frame(0); +} + +void fec1_tx_frame(void) +{ + fec_tx_frame(1); +} + +/* + * Send a packet out the selected FEC + * + * Parameters: + * ch FEC channel + * nif Pointer to Network Interface (NIF) structure + * dst Destination MAC Address + * src Source MAC Address + * type Ethernet Frame Type + * length Number of bytes to be transmitted (doesn't include type, + * src, or dest byte count) + * pkt Pointer packet network buffer + * + * Return Value: + * 1 success + * 0 otherwise + */ +int fec_send(uint8_t ch, NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NBUF *nbuf) +{ + FECBD *pTxBD; + + /* Check the length */ + if ((nbuf->length + ETH_HDR_LEN) > ETH_MTU) + { + dbg("nbuf->length (%d) + ETH_HDR_LEN (%d) exceeds ETH_MTU (%d)\r\n", + nbuf->length, ETH_HDR_LEN, ETH_MTU); + return 0; + } + + /* + * Copy the destination address, source address, and Ethernet + * type into the packet + */ + memcpy(&nbuf->data[0], dst, 6); + memcpy(&nbuf->data[6], src, 6); + memcpy(&nbuf->data[12], &type, 2); + + /* + * Grab the next available Tx Buffer Descriptor + */ + while ((pTxBD = fecbd_tx_alloc(ch)) == NULL) {}; + + /* + * Put the network buffer into the Tx waiting queue + */ + nbuf_add(NBUF_TX_RING, nbuf); + + /* + * Setup the buffer descriptor for transmission + */ + pTxBD->data = nbuf->data; + pTxBD->length = nbuf->length + ETH_HDR_LEN; + pTxBD->status |= (TX_BD_R | TX_BD_L); + + /* + * Continue the Tx DMA task (in case it was waiting for a new + * TxBD to be ready + */ + fec_tx_continue(ch); + + return 1; +} + +int fec0_send(NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NBUF *nbuf) +{ + return fec_send(0, nif, dst, src, type, nbuf); +} + +int fec1_send(NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NBUF *nbuf) +{ + return fec_send(1, nif, dst, src, type, nbuf); +} + +/* + * Enable interrupts on the selected FEC + * + * Parameters: + * ch FEC channel + * pri Interrupt Priority + * lvl Interrupt Level + */ +void fec_irq_enable(uint8_t ch, uint8_t lvl, uint8_t pri) +{ + /* + * Setup the appropriate ICR + */ + MCF_INTC_ICR((ch == 0) ? 39 : 38) = MCF_INTC_ICR_IP(pri) | + MCF_INTC_ICR_IL(lvl); + + /* + * Clear any pending FEC interrupt events + */ + MCF_FEC_EIR(ch) = MCF_FEC_EIR_CLEAR_ALL; + + /* + * Unmask all FEC interrupts + */ + MCF_FEC_EIMR(ch) = MCF_FEC_EIMR_UNMASK_ALL; + + /* + * Unmask the FEC interrupt in the interrupt controller + */ + if (ch == 0) + MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK39; + else + MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK38; +} + + +/* + * Disable interrupts on the selected FEC + * + * Parameters: + * ch FEC channel + */ +void fec_irq_disable(uint8_t ch) +{ + + /* + * Mask all FEC interrupts + */ + MCF_FEC_EIMR(ch) = MCF_FEC_EIMR_MASK_ALL; + + /* + * Mask the FEC interrupt in the interrupt controller + */ + if (ch == 0) + MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK39; + else + MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK38; +} + +/* + * FEC interrupt handler + * All interrupts are multiplexed into a single vector for each + * FEC module. The lower level interrupt handler passes in the + * channel to this handler. Note that the receive interrupt is + * generated by the Multi-channel DMA FEC Rx task. + * + * Parameters: + * ch FEC channel + */ +static bool fec_irq_handler(uint8_t ch) +{ + uint32_t event, eir; + + /* + * Determine which interrupt(s) asserted by AND'ing the + * pending interrupts with those that aren't masked. + */ + eir = MCF_FEC_EIR(ch); + event = eir & MCF_FEC_EIMR(ch); + + if (event != eir) + dbg("pending but not enabled: 0x%08x\r\n", (event ^ eir)); + + /* + * Clear the event(s) in the EIR immediately + */ + MCF_FEC_EIR(ch) = event; + + if (event & MCF_FEC_EIR_RFERR) + { + fec_log[ch].total++; + fec_log[ch].rferr++; + dbg("RFERR\r\n"); + dbg("FECRFSR%d = 0x%08x\r\n", ch, MCF_FEC_FECRFSR(ch)); + //fec_eth_stop(ch); + } + + if (event & MCF_FEC_EIR_XFERR) + { + fec_log[ch].total++; + fec_log[ch].xferr++; + dbg("XFERR\r\n"); + } + + if (event & MCF_FEC_EIR_XFUN) + { + fec_log[ch].total++; + fec_log[ch].xfun++; + dbg("XFUN\r\n"); + //fec_eth_stop(ch); + } + + if (event & MCF_FEC_EIR_RL) + { + fec_log[ch].total++; + fec_log[ch].rl++; + dbg("RL\r\n"); + } + + if (event & MCF_FEC_EIR_LC) + { + fec_log[ch].total++; + fec_log[ch].lc++; + dbg("LC\r\n"); + } + + if (event & MCF_FEC_EIR_MII) + { + fec_log[ch].mii++; + dbg("MII\r\n"); + } + + if (event & MCF_FEC_EIR_TXF) + { + fec_log[ch].txf++; + dbg("TXF\r\n"); + } + + if (event & MCF_FEC_EIR_GRA) + { + fec_log[ch].gra++; + dbg("GRA\r\n"); + } + + if (event & MCF_FEC_EIR_BABT) + { + fec_log[ch].total++; + fec_log[ch].babt++; + dbg("BABT\r\n"); + } + + if (event & MCF_FEC_EIR_BABR) + { + fec_log[ch].total++; + fec_log[ch].babr++; + dbg("BABR\r\n"); + } + + if (event & MCF_FEC_EIR_HBERR) + { + fec_log[ch].total++; + fec_log[ch].hberr++; + dbg("HBERR\r\n"); + } + + return true; +} + +/* + * handler for FEC interrupts + * arg2 is a pointer to the nif in this case + */ +bool fec0_interrupt_handler(void* arg1, void* arg2) +{ + bool res; + + (void) arg1; /* not used */ + (void) arg2; + + res = fec_irq_handler(0); + + return res; +} + +bool fec1_interrupt_handler(void* arg1, void* arg2) +{ + bool res; + + (void) arg1; /* not used */ + (void) arg2; + + res = fec_irq_handler(1); + + return res; +} + +/* + * Configure the selected Ethernet port and enable all operations + * + * Parameters: + * ch FEC channel + * trcvr Transceiver mode (MII, 7-Wire or internal loopback) + * speed Maximum operating speed (MII only) + * duplex Full or Half-duplex (MII only) + * mac Physical (MAC) Address + */ +void fec_eth_setup(uint8_t ch, uint8_t trcvr, uint8_t speed, uint8_t duplex, const uint8_t *mac) +{ + /* + * Disable FEC interrupts + */ + fec_irq_disable(ch); + + /* + * Initialize the event log + */ + fec_log_init(ch); + + /* + * Initialize the network buffers and fec buffer descriptors + */ + nbuf_init(); + fecbd_init(ch); + + /* + * Initialize the FEC + */ + fec_reset(ch); + fec_init(ch, trcvr, mac); + + if (trcvr == FEC_MODE_MII) + { + /* + * Initialize the MII interface + */ +#if defined(MACHINE_FIREBEE) + if (am79c874_init(0, 0, speed, duplex)) + dbg("PHY init completed\r\n"); + else + dbg("PHY init failed\r\n"); +#elif defined(MACHINE_M548X) + bcm_5222_init(0, 0, speed, duplex); +#else + fec_mii_init(ch, SYSCLK / 1000); +#endif /* MACHINE_FIREBEE */ + } + + /* + * Initialize and enable FEC interrupts + */ + fec_irq_enable(ch, FEC_INTC_LVL(ch), FEC_INTC_PRI(ch)); + + /* + * Enable the multi-channel DMA tasks + */ + fec_rx_start(ch, (int8_t*) fecbd_get_start(ch, Rx)); + fec_tx_start(ch, (int8_t*) fecbd_get_start(ch, Tx)); + + /* + * Enable the FEC channel + */ + MCF_FEC_ECR(ch) |= MCF_FEC_ECR_ETHER_EN; +} + +/* + * Reset the selected Ethernet port + * + * Parameters: + * ch FEC channel + */ +void fec_eth_reset(uint8_t ch) +{ + // To do +} + + +/* + * Stop the selected Ethernet port + * + * Parameters: + * ch FEC channel + */ +void fec_eth_stop(uint8_t ch) +{ + int level; + + /* + * Disable interrupts + */ + level = set_ipl(7); + + dbg("fec %d stopped\r\n", ch); + /* + * Gracefully disable the receiver and transmitter + */ + fec_tx_stop(ch); + fec_rx_stop(ch); + + /* + * Disable FEC interrupts + */ + fec_irq_disable(ch); + + /* + * Disable the FEC channel + */ + MCF_FEC_ECR(ch) &= ~MCF_FEC_ECR_ETHER_EN; + +#ifdef DBG_FEC + nbuf_debug_dump(); + fec_log_dump(ch); +#endif + + /* + * Flush the network buffers + */ + nbuf_flush(); + + /* + * Restore interrupt level + */ + set_ipl(level); +} + diff --git a/net/fecbd.c b/net/fecbd.c new file mode 100644 index 0000000..c309c5b --- /dev/null +++ b/net/fecbd.c @@ -0,0 +1,239 @@ +/* + * File: fecbd.c + * Purpose: Provide a simple buffer management driver + * + * Notes: + */ +#include "MCD_dma.h" +#include "fecbd.h" +#include "nbuf.h" +#include "eth.h" +#include "bas_printf.h" +#include + +//#define DBG_FECBD +#ifdef DBG_FECBD +#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0) +#else +#define dbg(format, arg...) do { ; } while (0) +#endif /* DBG_FECBD */ + +/* + * This implements a simple static buffer descriptor + * ring for each channel and each direction + * + * FEC Buffer Descriptors need to be aligned to a 4-byte boundary. + * In order to accomplish this, data is over-allocated and manually + * aligned at runtime + * + * Enough space is allocated for each of the two FEC channels to have + * NRXBD Rx BDs and NTXBD Tx BDs + * + */ + +static FECBD unaligned_bds[(2 * NRXBD) + (2 * NTXBD) + 1]; + +/* + * These pointers are used to reference into the chunck of data set + * aside for buffer descriptors + */ +static FECBD *RxBD; +static FECBD *TxBD; + +/* + * Macros to easier access to the BD ring + */ +#define RxBD(ch,i) RxBD[(ch * NRXBD) + i] +#define TxBD(ch,i) TxBD[(ch * NTXBD) + i] + +/* + * Buffer descriptor indexes + */ +static int iTxbd_new; +static int iTxbd_old; +static int iRxbd; + +/* + * Initialize the FEC Buffer Descriptor ring + * Buffer Descriptor format is defined by the MCDAPI + * + * Parameters: + * ch FEC channel + */ +void fecbd_init(uint8_t ch) +{ + NBUF *nbuf; + int i; + + dbg("\r\n"); + + /* + * Align Buffer Descriptors to 4-byte boundary + */ + RxBD = (FECBD *)(((int) unaligned_bds + 3) & 0xFFFFFFFC); + TxBD = (FECBD *)((int) RxBD + (sizeof(FECBD) * 2 * NRXBD)); + + dbg("initialise RX buffer descriptor ring\r\n"); + + /* + * Initialize the Rx Buffer Descriptor ring + */ + for (i = 0; i < NRXBD; ++i) + { + /* Grab a network buffer from the free list */ + nbuf = nbuf_alloc(); + if (nbuf == NULL) + { + dbg("could not allocate network buffer\r\n"); + return; + } + + /* Initialize the BD */ + RxBD(ch,i).status = RX_BD_E | RX_BD_INTERRUPT; + RxBD(ch,i).length = RX_BUF_SZ; + RxBD(ch,i).data = nbuf->data; + + /* Add the network buffer to the Rx queue */ + nbuf_add(NBUF_RX_RING, nbuf); + } + + /* + * Set the WRAP bit on the last one + */ + RxBD(ch, i - 1).status |= RX_BD_W; + + dbg("initialise TX buffer descriptor ring\r\n"); + + /* + * Initialize the Tx Buffer Descriptor ring + */ + for (i = 0; i < NTXBD; ++i) + { + TxBD(ch, i).status = TX_BD_INTERRUPT; + TxBD(ch, i).length = 0; + TxBD(ch, i).data = NULL; + } + + /* + * Set the WRAP bit on the last one + */ + TxBD(ch, i - 1).status |= TX_BD_W; + + /* + * Initialize the buffer descriptor indexes + */ + iTxbd_new = iTxbd_old = iRxbd = 0; +} + +void fecbd_dump(uint8_t ch) +{ +#ifdef DBG_FECBD + int i; + + xprintf("\n------------ FEC%d BDs -----------\n",ch); + xprintf("RxBD Ring\n"); + for (i = 0; i < NRXBD; i++) + { + xprintf("%02d: BD Addr=0x%08x, Ctrl=0x%04x, Lgth=%04d, DataPtr=0x%08x\n", + i, &RxBD(ch, i), + RxBD(ch, i).status, + RxBD(ch, i).length, + RxBD(ch, i).data); + } + xprintf("TxBD Ring\n"); + for (i = 0; i < NTXBD; i++) + { + xprintf("%02d: BD Addr=0x%08x, Ctrl=0x%04x, Lgth=%04d, DataPtr=0x%08x\n", + i, &TxBD(ch, i), + TxBD(ch, i).status, + TxBD(ch, i).length, + TxBD(ch, i).data); + } + xprintf("--------------------------------\n\n"); +#endif /* DBG_FECBD */ +} + +/* + * Return the address of the first buffer descriptor in the ring. + * + * Parameters: + * ch FEC channel + * direction Rx or Tx Macro + * + * Return Value: + * The start address of the selected Buffer Descriptor ring + */ +uint32_t fecbd_get_start(uint8_t ch, uint8_t direction) +{ + switch (direction) + { + case Rx: + return (uint32_t)((int)RxBD + (ch * sizeof(FECBD) * NRXBD)); + case Tx: + default: + return (uint32_t)((int)TxBD + (ch * sizeof(FECBD) * NTXBD)); + } +} + +FECBD *fecbd_rx_alloc(uint8_t ch) +{ + int i = iRxbd; + + /* Check to see if the ring of BDs is full */ + if (RxBD(ch, i).status & RX_BD_E) + return NULL; + + /* Increment the circular index */ + iRxbd = (uint8_t)((iRxbd + 1) % NRXBD); + + return &RxBD(ch, i); +} + +/* + * This function keeps track of the next available Tx BD in the ring + * + * Parameters: + * ch FEC channel + * + * Return Value: + * Pointer to next available buffer descriptor. + * NULL if the BD ring is full + */ +FECBD *fecbd_tx_alloc(uint8_t ch) +{ + int i = iTxbd_new; + + /* Check to see if the ring of BDs is full */ + if (TxBD(ch, i).status & TX_BD_R) + return NULL; + + /* Increment the circular index */ + iTxbd_new = (uint8_t)((iTxbd_new + 1) % NTXBD); + + return &TxBD(ch, i); +} + +/* + * This function keeps track of the Tx BDs that have already been + * processed by the FEC + * + * Parameters: + * ch FEC channel + * + * Return Value: + * Pointer to the oldest buffer descriptor that has already been sent + * by the FEC, NULL if the BD ring is empty + */ +FECBD *fecbd_tx_free(uint8_t ch) +{ + int i = iTxbd_old; + + /* Check to see if the ring of BDs is empty */ + if ((TxBD(ch, i).data == NULL) || (TxBD(ch, i).status & TX_BD_R)) + return NULL; + + /* Increment the circular index */ + iTxbd_old = (uint8_t)((iTxbd_old + 1) % NTXBD); + + return &TxBD(ch, i); +} diff --git a/net/ip.c b/net/ip.c new file mode 100644 index 0000000..b3951ce --- /dev/null +++ b/net/ip.c @@ -0,0 +1,317 @@ +/* + * File: ip.c + * Purpose: Internet Protcol device driver + * + * Notes: + * + * Modifications: + */ +#include +#include "net.h" +#include "bas_printf.h" +#include "bas_string.h" + + +//#define IP_DEBUG +#if defined(IP_DEBUG) +#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0) +#else +#define dbg(format, arg...) do { ; } while (0) +#endif + +void ip_init(IP_INFO *info, IP_ADDR_P myip, IP_ADDR_P gateway, IP_ADDR_P netmask) +{ + int index; + + for (index = 0; index < sizeof(IP_ADDR); index++) + { + info->myip[index] = myip[index]; + info->gateway[index] = gateway[index]; + info->netmask[index] = netmask[index]; + info->broadcast[index] = 0xFF; + } + + info->rx = 0; + info->rx_unsup = 0; + info->tx = 0; + info->err = 0; +} + +uint8_t *ip_get_myip(IP_INFO *info) +{ + if (info != 0) + { + return (uint8_t *) &info->myip[0]; + } + dbg("info is NULL!\n\t"); + return 0; +} + +int ip_addr_compare(IP_ADDR_P addr1, IP_ADDR_P addr2) +{ + int i; + + for (i = 0; i < sizeof(IP_ADDR); i++) + { + if (addr1[i] != addr2[i]) + return 0; + } + return 1; +} + +uint8_t *ip_resolve_route(NIF *nif, IP_ADDR_P destip) +{ + /* + * This function determines whether or not an outgoing IP + * packet needs to be transmitted on the local net or sent + * to the router for transmission. + */ + IP_INFO *info; + IP_ADDR mask, result; + IP_ADDR bc = { 255, 255, 255, 255 }; + int i; + + info = nif_get_protocol_info(nif, ETH_FRM_IP); + + if (memcmp(destip, bc, 4) == 0) + { + dbg("destip is broadcast address, no gateway needed\r\n"); + return destip; + } + + /* create mask for local IP */ + for (i = 0; i < sizeof(IP_ADDR); i++) + { + mask[i] = info->myip[i] & info->netmask[i]; + } + + /* apply mask to the destination IP */ + for (i = 0; i < sizeof(IP_ADDR); i++) + { + result[i] = mask[i] & destip[i]; + } + + /* See if destination IP is local or not */ + if (ip_addr_compare(mask, result)) + { + /* The destination IP is on the local net */ + return arp_resolve(nif, ETH_FRM_IP, destip); + } + else + { + /* The destination IP is not on the local net */ + return arp_resolve(nif, ETH_FRM_IP, info->gateway); + } +} + +int ip_send(NIF *nif, uint8_t *dest, uint8_t *src, uint8_t protocol, NBUF *pNbuf) +{ + /* + * This function assembles an IP datagram and passes it + * onto the hardware to be sent over the network. + */ + uint8_t *route; + ip_frame_hdr *ipframe; + + /* + * Construct the IP header + */ + ipframe = (ip_frame_hdr*) &pNbuf->data[IP_HDR_OFFSET]; + + /* IP version 4, Internet Header Length of 5 32-bit words */ + ipframe->version_ihl = 0x45; + + /* Type of Service == 0, normal and routine */ + ipframe->service_type = 0x00; + + /* Total length of data */ + ipframe->total_length = (uint16_t) (pNbuf->length + IP_HDR_SIZE); + + /* User defined identification */ + ipframe->identification = 0x0000; + + /* Fragment Flags and Offset -- Don't fragment, last frag */ + ipframe->flags_frag_offset = 0x0000; + + /* Time To Live */ + ipframe->ttl = 0xFF; + + /* Protocol */ + ipframe->protocol = protocol; + + /* Checksum, computed later, zeroed for computation */ + ipframe->checksum = 0x0000; + + /* source IP address */ + ipframe->source_addr[0] = src[0]; + ipframe->source_addr[1] = src[1]; + ipframe->source_addr[2] = src[2]; + ipframe->source_addr[3] = src[3]; + + /* dest IP address */ + ipframe->dest_addr[0] = dest[0]; + ipframe->dest_addr[1] = dest[1]; + ipframe->dest_addr[2] = dest[2]; + ipframe->dest_addr[3] = dest[3]; + + /* Compute checksum */ + ipframe->checksum = ip_chksum((uint16_t *) ipframe, IP_HDR_SIZE); + + /* Increment the packet length by the size of the IP header */ + pNbuf->length += IP_HDR_SIZE; + + /* + * Determine the hardware address of the recipient + */ + IP_ADDR bc = { 255, 255, 255, 255}; + if (memcmp(bc, dest, 4) != 0) + { + route = ip_resolve_route(nif, dest); + if (route == NULL) + { + dbg("Unable to locate %d.%d.%d.%d\r\n", + dest[0], dest[1], dest[2], dest[3]); + return 0; + } + } + else + { + route = bc; + dbg("route = broadcast\r\n"); + dbg("nif = %p\r\n", nif); + dbg("nif->send = %p\r\n", nif->send); + } + + return nif->send(nif, route, &nif->hwa[0], ETH_FRM_IP, pNbuf); +} + +#if defined(DEBUG_PRINT) +void dump_ip_frame(ip_frame_hdr *ipframe) +{ + xprintf("Version: %02X\n", ((ipframe->version_ihl & 0x00f0) >> 4)); + xprintf("IHL: %02X\n", ipframe->version_ihl & 0x000f); + xprintf("Service: %02X\n", ipframe->service_type); + xprintf("Length: %04X\n", ipframe->total_length); + xprintf("Ident: %04X\n", ipframe->identification); + xprintf("Flags: %02X\n", ((ipframe->flags_frag_offset & 0xC000) >> 14)); + xprintf("Frag: %04X\n", ipframe->flags_frag_offset & 0x3FFF); + xprintf("TTL: %02X\n", ipframe->ttl); + xprintf("Protocol: %02X\n", ipframe->protocol); + xprintf("Chksum: %04X\n", ipframe->checksum); + xprintf("Source : %d.%d.%d.%d\n", + ipframe->source_addr[0], + ipframe->source_addr[1], + ipframe->source_addr[2], + ipframe->source_addr[3]); + xprintf("Dest : %d.%d.%d.%d\n", + ipframe->dest_addr[0], + ipframe->dest_addr[1], + ipframe->dest_addr[2], + ipframe->dest_addr[3]); + xprintf("Options: %08X\n", ipframe->options); +} +#endif + + +uint16_t ip_chksum(uint16_t *data, int num) +{ + int chksum, ichksum; + uint16_t temp; + + chksum = 0; + num = num >> 1; /* from bytes to words */ + for (; num; num--, data++) + { + temp = *data; + ichksum = chksum + temp; + ichksum = ichksum & 0x0000FFFF; + if ((ichksum < temp) || (ichksum < chksum)) + { + ichksum += 1; + ichksum = ichksum & 0x0000FFFF; + } + chksum = ichksum; + } + return (uint16_t) ~chksum; +} + +static int validate_ip_hdr(NIF *nif, ip_frame_hdr *ipframe) +{ + int index, chksum; + IP_INFO *info; + + /* + * Check the IP Version + */ + if (IP_VERSION(ipframe) != 4) + return 0; + + /* + * Check Internet Header Length + */ + if (IP_IHL(ipframe) < 5) + return 0; + + /* + * Check the destination IP address + */ + info = nif_get_protocol_info(nif,ETH_FRM_IP); + for (index = 0; index < sizeof(IP_ADDR); index++) + if (info->myip[index] != ipframe->dest_addr[index]) + return 0; + + /* + * Check the checksum + */ + chksum = (int)((uint16_t) IP_CHKSUM(ipframe)); + IP_CHKSUM(ipframe) = 0; + + if (ip_chksum((uint16_t *) ipframe, IP_IHL(ipframe) * 4) != chksum) + return 0; + + IP_CHKSUM(ipframe) = (uint16_t) chksum; + + return 1; +} + +void ip_handler(NIF *nif, NBUF *pNbuf) +{ + /* + * IP packet handler + */ + ip_frame_hdr *ipframe; + + dbg("packet received\r\n"); + + ipframe = (ip_frame_hdr *) &pNbuf->data[pNbuf->offset]; + + /* + * Verify valid IP header and destination IP + */ + if (!validate_ip_hdr(nif, ipframe)) + { + dbg("not a valid IP packet!\r\n"); + + nbuf_free(pNbuf); + return; + } + + /* + * Call the appriopriate handler + */ + switch (IP_PROTOCOL(ipframe)) + { + case IP_PROTO_ICMP: + // FIXME: icmp_handler(nif, pNbuf); + break; + case IP_PROTO_UDP: + udp_handler(nif,pNbuf); + break; + default: + dbg("no protocol handler registered for protocol %d\r\n", + __FUNCTION__, IP_PROTOCOL(ipframe)); + nbuf_free(pNbuf); + break; + } + return; +} diff --git a/net/nbuf.c b/net/nbuf.c new file mode 100644 index 0000000..ce8de27 --- /dev/null +++ b/net/nbuf.c @@ -0,0 +1,224 @@ +/* + * File: nbuf.c + * Purpose: Implementation of network buffer scheme. + * + * Notes: + */ +#include "queue.h" +#include "net.h" +#include "driver_mem.h" +#include "exceptions.h" +#include "bas_types.h" +#include "bas_printf.h" + + +#define DBG_NBUF +#if defined(DBG_NBUF) +#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0) +#else +#define dbg(format, arg...) do { ; } while (0) +#endif /* DBG_NBUF */ +/* + * Queues used for network buffer storage + */ +QUEUE nbuf_queue[NBUF_MAXQ]; + +/* + * Some devices require line-aligned buffers. In order to accomplish + * this, the nbuf data is over-allocated and adjusted. The following + * array keeps track of the original data pointer returned by malloc + */ +uint8_t *unaligned_buffers[NBUF_MAX]; + +/* + * Initialize all the network buffer queues + * + * Return Value: + * 0 success + * 1 failure + */ +int nbuf_init(void) +{ + int i; + NBUF *nbuf; + + for (i = 0; i < NBUF_MAXQ; ++i) + { + /* Initialize all the queues */ + queue_init(&nbuf_queue[i]); + } + + dbg("Creating %d net buffers of %d bytes\r\n", NBUF_MAX, NBUF_SZ); + + for (i = 0; i < NBUF_MAX; ++i) + { + /* Allocate memory for the network buffer structure */ + nbuf = (NBUF *) driver_mem_alloc(sizeof(NBUF)); + if (!nbuf) + { + xprintf("failed to allocate nbuf\r\n"); + return 1; + } + + /* Allocate memory for the actual data */ + unaligned_buffers[i] = driver_mem_alloc(NBUF_SZ + 16); + nbuf->data = (uint8_t *)((uint32_t)(unaligned_buffers[i] + 15) & 0xFFFFFFF0); + if (!nbuf->data) + { + return 1; + } + + /* Initialize the network buffer */ + nbuf->offset = 0; + nbuf->length = 0; + + /* Add the network buffer to the free list */ + queue_add(&nbuf_queue[NBUF_FREE], (QNODE *)nbuf); + } + + dbg("NBUF allocation complete\r\n"); + + return 0; +} + +/* + * Return all the allocated memory to the heap + */ +void nbuf_flush(void) +{ + NBUF *nbuf; + int i; + int level = set_ipl(7); + int n = 0; + + for (i = 0; i < NBUF_MAX; ++i) + driver_mem_free((uint8_t *) unaligned_buffers[i]); + + for (i = 0; i < NBUF_MAXQ; ++i) + { + while ((nbuf = (NBUF *) queue_remove(&nbuf_queue[i])) != NULL) + { + driver_mem_free(nbuf); + ++n; + } + } + set_ipl(level); +} + +/* + * Allocate a network buffer from the free list + * + * Return Value: + * Pointer to a free network buffer + * NULL if none are available + */ +NBUF *nbuf_alloc(void) +{ + NBUF *nbuf; + int level = set_ipl(7); + + nbuf = (NBUF *) queue_remove(&nbuf_queue[NBUF_FREE]); + set_ipl(level); + + return nbuf; +} + +/* + * Add the specified network buffer back to the free list + * + * Parameters: + * nbuf Buffer to add back to the free list + */ +void nbuf_free(NBUF *nbuf) +{ + int level = set_ipl(7); + + nbuf->offset = 0; + nbuf->length = NBUF_SZ; + queue_add(&nbuf_queue[NBUF_FREE],(QNODE *) nbuf); + + set_ipl(level); +} + +/* + * Remove a network buffer from the specified queue + * + * Parameters: + * q The index that identifies the queue to pull the buffer from + */ +NBUF *nbuf_remove(int q) +{ + NBUF *nbuf; + int level = set_ipl(7); + + nbuf = (NBUF *) queue_remove(&nbuf_queue[q]); + set_ipl(level); + + return nbuf; +} + +/* + * Add a network buffer to the specified queue + * + * Parameters: + * q The index that identifies the queue to add the buffer to + */ +void nbuf_add(int q, NBUF *nbuf) +{ + int level = set_ipl(7); + + queue_add(&nbuf_queue[q], (QNODE *) nbuf); + set_ipl(level); +} + +/* + * Put all the network buffers back into the free list + */ +void nbuf_reset(void) +{ + NBUF *nbuf; + int i; + int level = set_ipl(7); + + for (i = 1; i < NBUF_MAXQ; ++i) + { + while ((nbuf = nbuf_remove(i)) != NULL) + nbuf_free(nbuf); + } + set_ipl(level); +} + +/* + * Display all the nbuf queues + */ +void nbuf_debug_dump(void) +{ +#ifdef DBG_NBUF + NBUF *nbuf; + int i; + int j; + int level; + + level = set_ipl(7); + + for (i = 0; i < NBUF_MAXQ; ++i) + { + dbg("\r\n\r\nQueue #%d\r\n\r\n", i); + dbg("\tBuffer Location\tOffset\tLength\r\n"); + dbg("--------------------------------------\r\n"); + j = 0; + nbuf = (NBUF *) queue_peek(&nbuf_queue[i]); + + while (nbuf != NULL) + { + dbg("%d\t0x%08x\t0x%04x\t0x%04x\r\n", j++, nbuf->data, + nbuf->offset, + nbuf->length); + nbuf = (NBUF *) nbuf->node.next; + } + } + dbg("\r\n"); + + set_ipl(level); +#endif /* DBG_NBUF */ +} diff --git a/net/net_timer.c b/net/net_timer.c new file mode 100644 index 0000000..747b0a0 --- /dev/null +++ b/net/net_timer.c @@ -0,0 +1,202 @@ +/* + * File: net_timer.c + * Purpose: Provide a timer use by the BaS network as a timeout + * indicator + * + * Notes: + */ + +#include "net_timer.h" +#include "bas_printf.h" +#include "MCF5475.h" +#include "interrupts.h" + +//#define DBG_TMR +#ifdef DBG_TMR +#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0) +#else +#define dbg(format, arg...) do { ; } while (0) +#endif /* DBG_TMR */ + + +#if defined(MACHINE_FIREBEE) +#include "firebee.h" +#elif defined(MACHINE_M5484LITE) +#include "m5484l.h" +#elif defined(MACHINE_M54455) +#include "m54455.h" +#else +#error unknown machine! +#endif + +static NET_TIMER net_timer[4] = +{ + {0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0} +}; + + +bool timer_default_isr(void *not_used, NET_TIMER *t) +{ + (void) not_used; + + /* + * Clear the pending event + */ + MCF_GPT_GMS(t->ch) = 0; + + dbg("timer isr called for timer channel %d\r\n"); + + /* + * Clear the reference - the desired seconds have expired + */ + t->reference = 0; + + return 1; +} + +void timer_irq_enable(uint8_t ch) +{ + /* + * Setup the appropriate ICR + */ + MCF_INTC_ICR(TIMER_VECTOR(ch) - 64) = MCF_INTC_ICR_IP(net_timer[ch].pri) | + MCF_INTC_ICR_IL(net_timer[ch].lvl); + + /* + * Unmask the FEC interrupt in the interrupt controller + */ + if (ch == 3) + { + MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK59; + } + else if (ch == 2) + { + MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK60; + } + else if (ch == 1) + { + MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK61; + } + else + { + MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK62; + } +} + +bool timer_set_secs(uint8_t ch, uint32_t secs) +{ + uint16_t timeout; + + /* + * Reset the timer + */ + MCF_GPT_GMS(ch) = 0; + + /* + * Get the timeout in seconds + */ + timeout = (uint16_t)(secs * net_timer[ch].cnt); + + /* + * Set the reference indicating that we have not yet reached the + * desired timeout + */ + net_timer[ch].reference = 1; + + /* + * Enable timer interrupt to the processor + */ + timer_irq_enable(ch); + + /* + * Enable the timer using the pre-calculated values + */ + MCF_GPT_GCIR(ch) = (0 + | MCF_GPT_GCIR_CNT(timeout) + | MCF_GPT_GCIR_PRE(net_timer[ch].pre) + ); + MCF_GPT_GMS(ch) = net_timer[ch].gms; + + return true; +} + +uint32_t timer_get_reference(uint8_t ch) +{ + return (uint32_t) net_timer[ch].reference; +} + +bool timer_init(uint8_t ch, uint8_t lvl, uint8_t pri) +{ + /* + * Initialize the timer to expire after one second + * + * This routine should only be called by the project (board) specific + * initialization code. + */ + if (!((ch <= 3) && (lvl <= 7) && (lvl >= 1) && (pri <= 7))) + { + dbg("illegal parameters (ch=%d, lvl=%d, pri=%d)\r\n", ch, lvl, pri); + + return false; + } + + /* + * Reset the timer + */ + MCF_GPT_GMS(ch) = 0; + + /* + * Save off the channel, and interrupt lvl/pri information + */ + net_timer[ch].ch = ch; + net_timer[ch].lvl = lvl; + net_timer[ch].pri = pri; + + /* + * Register the timer interrupt handler + */ + if (!isr_register_handler(TIMER_VECTOR(ch), 3, 0, + (bool (*)(void *,void *)) timer_default_isr, + NULL, + (void *) &net_timer[ch]) + ) + { + dbg("could not register timer interrupt handler\r\n"); + return false; + } + dbg("timer handler registered\r\n", __FUNCTION__); + + /* + * Calculate the require CNT value to get a 1 second timeout + * + * 1 sec = CNT * Clk Period * PRE + * CNT = 1 sec / (Clk Period * PRE) + * CNT = Clk Freq / PRE + * + * The system clock frequency is defined as SYSTEM_CLOCK and + * is given in MHz. We need to multiple it by 1000000 to get the + * true value. If we assume PRE to be the maximum of 0xFFFF, + * then the CNT value needed to achieve a 1 second timeout is + * given by: + * + * CNT = SYSTEM_CLOCK * (1000000/0xFFFF) + */ + net_timer[ch].pre = 0xFFFF; + net_timer[ch].cnt = (uint16_t) ((SYSCLK / 1000) * (1000000 / 0xFFFF)); + + /* + * Save off the appropriate mode select register value + */ + net_timer[ch].gms = (0 + | MCF_GPT_GMS_TMS_GPIO + | MCF_GPT_GMS_IEN + | MCF_GPT_GMS_SC + | MCF_GPT_GMS_CE + ); + + return true; +} + diff --git a/net/nif.c b/net/nif.c new file mode 100644 index 0000000..ee7dfee --- /dev/null +++ b/net/nif.c @@ -0,0 +1,130 @@ +/* + * File: nif.c + * Purpose: Network InterFace routines + * + * Notes: + * + * Modifications: + * + */ +#include "net.h" +#include "bas_types.h" +#include "bas_printf.h" + +#define DBG_NIF +#ifdef DBG_NIF +#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0) +#else +#define dbg(format, arg...) do { ; } while (0) +#endif /* DBG_NIF */ + +int nif_protocol_exist(NIF *nif, uint16_t protocol) +{ + /* + * This function searches the list of supported protocols + * on the particular NIF and if a protocol handler exists, + * true is returned. This function is useful for network cards + * that needn't read in the entire frame but can discard frames + * arbitrarily. + */ + int index; + + for (index = 0; index < nif->num_protocol; ++index) + { + if (nif->protocol[index].protocol == protocol) + { + return true; + } + } + return false; +} + +void nif_protocol_handler(NIF *nif, uint16_t protocol, NBUF *pNbuf) +{ + /* + * This function searches the list of supported protocols + * on the particular NIF and if a protocol handler exists, + * the protocol handler is invoked. This routine called by + * network device driver after receiving a frame. + */ + int index; + + for (index = 0; index < nif->num_protocol; ++index) + { + if (nif->protocol[index].protocol == protocol) + { + dbg("call protocol handler for protocol %d at %p\r\n", protocol, + nif->protocol[index].handler); + nif->protocol[index].handler(nif,pNbuf); + return; + } + } + dbg("no protocol handler found for protocol %d\r\n", protocol); +} + +void *nif_get_protocol_info(NIF *nif, uint16_t protocol) +{ + /* + * This function searches the list of supported protocols + * on the particular NIF and returns a pointer to the + * config info for 'protocol', otherwise NULL is returned. + */ + int index; + + for (index = 0; index < nif->num_protocol; ++index) + { + if (nif->protocol[index].protocol == protocol) + return (void *)nif->protocol[index].info; + } + return (void *)0; +} + +int nif_bind_protocol(NIF *nif, uint16_t protocol, void (*handler)(NIF *,NBUF *), + void *info) +{ + /* + * This function registers 'protocol' as a supported + * protocol in 'nif'. + */ + if (nif->num_protocol < (MAX_SUP_PROTO - 1)) + { + nif->protocol[nif->num_protocol].protocol = protocol; + nif->protocol[nif->num_protocol].handler = (void(*)(NIF *, NBUF *)) handler; + nif->protocol[nif->num_protocol].info = info; + ++nif->num_protocol; + + return true; + } + return false; +} + +NIF *nif_init (NIF *nif) +{ + int i; + + for (i = 0; i < ETH_ADDR_LEN; ++i) + { + nif->hwa[i] = 0; + nif->broadcast[i] = 0xFF; + } + + for (i = 0; i < MAX_SUP_PROTO; ++i) + { + nif->protocol[i].protocol = 0; + nif->protocol[i].handler = 0; + nif->protocol[i].info = 0; + } + nif->num_protocol = 0; + + nif->mtu = 0; + nif->ch = 0; + nif->send = 0; + + nif->f_rx = 0; + nif->f_tx = 0; + nif->f_rx_err = 0; + nif->f_tx_err = 0; + nif->f_err = 0; + + return nif; +} diff --git a/net/queue.c b/net/queue.c new file mode 100644 index 0000000..756a9a7 --- /dev/null +++ b/net/queue.c @@ -0,0 +1,114 @@ +/* + * File: queue.c + * Purpose: Implement a first in, first out linked list + * + * Notes: + */ +#include "bas_string.h" +#include "queue.h" + +/* + * Initialize the specified queue to an empty state + * + * Parameters: + * q Pointer to queue structure + */ +void queue_init(QUEUE *q) +{ + q->head = NULL; +} + +/* + * Check for an empty queue + * + * Parameters: + * q Pointer to queue structure + * + * Return Value: + * 1 if Queue is empty + * 0 otherwise + */ +int queue_isempty(QUEUE *q) +{ + return (q->head == NULL); +} + +/* + * Add an item to the end of the queue + * + * Parameters: + * q Pointer to queue structure + * node New node to add to the queue + */ +void queue_add(QUEUE *q, QNODE *node) +{ + if (queue_isempty(q)) + { + q->head = q->tail = node; + } + else + { + q->tail->next = node; + q->tail = node; + } + + node->next = NULL; +} + +/* + * Remove and return first (oldest) entry from the specified queue + * + * Parameters: + * q Pointer to queue structure + * + * Return Value: + * Node at head of queue - NULL if queue is empty + */ +QNODE *queue_remove(QUEUE *q) +{ + QNODE *oldest; + + if (queue_isempty(q)) + return NULL; + + oldest = q->head; + q->head = oldest->next; + return oldest; +} + +/* + * Peek into the queue and return pointer to first (oldest) entry. + * The queue is not modified + * + * Parameters: + * q Pointer to queue structure + * + * Return Value: + * Node at head of queue - NULL if queue is empty + */ +QNODE *queue_peek(QUEUE *q) +{ + return q->head; +} + +/* + * Move entire contents of one queue to the other + * + * Parameters: + * src Pointer to source queue + * dst Pointer to destination queue + */ +void queue_move(QUEUE *dst, QUEUE *src) +{ + if (queue_isempty(src)) + return; + + if (queue_isempty(dst)) + dst->head = src->head; + else + dst->tail->next = src->head; + + dst->tail = src->tail; + src->head = NULL; + return; +} diff --git a/net/tftp.c b/net/tftp.c new file mode 100644 index 0000000..ac19e25 --- /dev/null +++ b/net/tftp.c @@ -0,0 +1,659 @@ +/* + * File: tftp.c + * Purpose: Trivial File Transfer Protocol driver for reading a file + * from a remote host. + * + * Notes: See RFC 1350 + * + * Modifications: + * + */ + +#include "bas_types.h" +#include "bas_printf.h" +#include "bas_string.h" +#include "net.h" +#include "net_timer.h" + +#define TIMER_NETWORK 3 + +/* The one and only TFTP connection */ +static TFTP_Connection tcxn; + +/* Progress Indicators */ +static char hash[] = {'-','\\','|','/'}; +static int ihash = 0; + +static int tftp_rwrq(void) +{ + NBUF *pNbuf; + RWRQ *rwrq; + int i, j, result; + + pNbuf = nbuf_alloc(); + if (pNbuf == NULL) + { + xprintf("TFTP: tftp_rwrq() couldn't allocate Tx buffer\n"); + return 0; + } + + rwrq = (RWRQ *)&pNbuf->data[TFTP_HDR_OFFSET]; + + /* Indicate a R/WRQ */ + rwrq->opcode = tcxn.dir; + + /* Copy in filename */ + strcpy(&rwrq->filename_mode[0], tcxn.file); + i = strlen(tcxn.file) + 1; + + /* Indicate transfer type */ + strcpy (&rwrq->filename_mode[i], OCTET); + + for (j = 0; j < 3; ++j) + { + pNbuf->length = (uint16_t)(i + strlen(OCTET) + 1 + 2); + result = udp_send(tcxn.nif, + tcxn.server_ip, + tcxn.my_port, + tcxn.server_port, + pNbuf); + if (result == 1) + break; + } + + if (result == 0) + nbuf_free(pNbuf); + + return result; +} + +static int tftp_ack(uint16_t blocknum) +{ + ACK *ack; + NBUF *pNbuf; + int i, result; + + pNbuf = nbuf_alloc(); + if (pNbuf == NULL) + { + xprintf("TFTP: tftp_ack() couldn't allocate Tx buffer\n"); + return 0; + } + + ack = (ACK *)&pNbuf->data[TFTP_HDR_OFFSET]; + ack->opcode = TFTP_ACK; + ack->blocknum = blocknum; + + for (i = 0; i < 3; ++i) + { + pNbuf->length = 4; + result = udp_send(tcxn.nif, + tcxn.server_ip, + tcxn.my_port, + tcxn.server_port, + pNbuf); + if (result == 1) + break; + } + + if (result == 0) + nbuf_free(pNbuf); + + return result; +} + +static int tftp_error(uint16_t error_code, uint16_t server_port) +{ + ERROR *err; + NBUF *pNbuf; + int i, result; + + pNbuf = nbuf_alloc(); + if (pNbuf == NULL) + { + xprintf("TFTP: tftp_error() couldn't allocate Tx buffer\n"); + return 0; + } + + err = (ERROR *)&pNbuf->data[TFTP_HDR_OFFSET]; + err->opcode = TFTP_ERROR; + err->code = error_code; + err->msg[0] = '\0'; + + for (i = 0; i < 3; ++i) + { + pNbuf->length = 5; + result = udp_send(tcxn.nif, + tcxn.server_ip, + tcxn.my_port, + server_port, + pNbuf); + if (result == 1) + break; + } + + if (result == 0) + nbuf_free(pNbuf); + + return result; +} + + +void tftp_handler(NIF *nif, NBUF *pNbuf) +{ + union TFTPpacket *tftp_pkt; + udp_frame_hdr *udpframe; + static int cnt; + (void) nif; + + tftp_pkt = (union TFTPpacket *)&pNbuf->data[pNbuf->offset]; + udpframe = (udp_frame_hdr *)&pNbuf->data[pNbuf->offset - UDP_HDR_SIZE]; + + switch (tftp_pkt->generic.opcode) + { + case TFTP_DATA: + /* Is this the expected block number? */ + if (tftp_pkt->data.blocknum == tcxn.exp_blocknum) + { + /* Is this is the first data block received? */ + if (tftp_pkt->data.blocknum == 1) + { + /* Save the server's transfer ID */ + tcxn.server_port = UDP_SOURCE(udpframe); + + /* Mark the connection as open */ + tcxn.open = true; + + /* Start progress indicator */ + xprintf("%c", hash[0]); + cnt = 0; + } + else + { + /* Check the server's transfer ID */ + if (tcxn.server_port != UDP_SOURCE(udpframe)) + { + xprintf("TFTP: Invalid server port: %d\n", \ + UDP_SOURCE(udpframe)); + + /* Send ERROR packet to source */ + tftp_error(TFTP_ERR_TID, UDP_SOURCE(udpframe)); + break; + } + } + + /* Add the buffer to the TFTP queue */ + queue_add(&tcxn.queue, (QNODE *)pNbuf); + + /* Update number of the next block expected */ + tcxn.exp_blocknum++; + + /* Increment number of bytes received counter */ + tcxn.bytes_recv += (pNbuf->length - 4); + + /* Update progress indicator */ + if (++cnt == 50) + { + ihash = (ihash + 1) % 4; + xprintf("\r"); + xprintf("%c", hash[ihash]); + cnt = 0; + } + } + else + { + if (tftp_pkt->data.blocknum < tcxn.exp_blocknum) + { + /* Re-ACK this packet */ + tftp_ack(tftp_pkt->data.blocknum); + } + + /* This is NOT the block expected */ + xprintf("Exp: %d, ", tcxn.exp_blocknum); + xprintf("Rcv: %d\n", tftp_pkt->data.blocknum); + + /* Free the network buffer */ + nbuf_free(pNbuf); + } + break; + case TFTP_ERROR: + xprintf("\nTFTP Error #%d: ",tftp_pkt->error.code); + xprintf("%s\n",tftp_pkt->error.msg); + tcxn.error = true; + /* Free the network buffer */ + nbuf_free(pNbuf); + break; + case TFTP_ACK: + if (tftp_pkt->ack.blocknum == tcxn.exp_blocknum) + { + if (tftp_pkt->data.blocknum == 0) + { /* This is the first ACK received */ + + /* Save the server's transfer ID */ + tcxn.server_port = UDP_SOURCE(udpframe); + + /* Mark the connection as open */ + tcxn.open = true; + } + else + { /* Check the server's transfer ID */ + if (tcxn.server_port != UDP_SOURCE(udpframe)) + { + xprintf("TFTP: Invalid server port: %d\n", \ + UDP_SOURCE(udpframe)); + + /*Send ERROR packet to source */ + tftp_error(TFTP_ERR_TID, UDP_SOURCE(udpframe)); + break; + } + } + + tcxn.exp_blocknum++; + } + else + { + /* This is NOT the block number expected */ + xprintf("ACK Exp: %d, ", tcxn.exp_blocknum); + xprintf("ACK Rcv: %d\n", tftp_pkt->ack.blocknum); + } + + /* Free the network buffer */ + nbuf_free(pNbuf); + break; + case TFTP_RRQ: + case TFTP_WRQ: + default: + /* Free the network buffer */ + nbuf_free(pNbuf); + break; + } +} + +void tftp_end(int success) +{ + /* + * Following a successful transfer the caller should pass in + * true, there should have been no ERROR packets received, and + * the connection should have been marked as closed by the + * tftp_in_char() routine. + */ + if (success && !tcxn.error && (tcxn.open == false)) + { + xprintf("\bTFTP transfer completed \n"); + xprintf("Read %d bytes (%d blocks)\n", \ + tcxn.bytes_recv, tcxn.exp_blocknum - 1); + } + else + { + /* Send error packet to stifle the server */ + tftp_error(TFTP_ERR_ILL, tcxn.server_port); + + xprintf("\bErrors in TFTP transfer.\n"); + xprintf("Read %d bytes (%d blocks)\n", \ + tcxn.bytes_recv, tcxn.exp_blocknum - 1); + } + + /* Free up any buffers left in the queue */ + while (!queue_isempty(&tcxn.queue)) + nbuf_free((NBUF *)queue_remove(&tcxn.queue)); + + /* Free the UDP port */ + udp_free_port(tcxn.my_port); +} + +int tftp_write(NIF *nif, char *fn, IP_ADDR_P server, uint32_t begin, uint32_t end) +{ + DATA *data; + NBUF *pNbuf; + + uint32_t i, retries, bytes_to_send; + uint16_t blocknum, this_size; + uint8_t success, *current; + int result; + + if (fn == 0 || server == 0 || end < begin) + return 0; + + /* Setup initial connection status */ + tcxn.nif = nif; + tcxn.file = fn; + tcxn.server_ip[0] = server[0]; + tcxn.server_ip[1] = server[1]; + tcxn.server_ip[2] = server[2]; + tcxn.server_ip[3] = server[3]; + tcxn.server_port = UDP_PORT_TFTP; + tcxn.exp_blocknum = 0; + tcxn.dir = TFTP_WRQ; + tcxn.open = false; + tcxn.bytes_sent = 0; + tcxn.error = false; + + /* Use Mac address as pseudo-random port */ + udp_prime_port((uint16_t)((nif->hwa[4] << 8) | nif->hwa[5])); + tcxn.my_port = udp_obtain_free_port(); + udp_bind_port(tcxn.my_port,&tftp_handler); + + retries = 4; + success = false; + + while (--retries) + { + /* Make the TFTP Read/Write Request */ + if (!tftp_rwrq()) + { + xprintf("Error: Couldn't send TFTP Write Request\n"); + udp_free_port(tcxn.my_port); + return false; + } + + timer_set_secs(TIMER_NETWORK, TFTP_TIMEOUT); + while (timer_get_reference(TIMER_NETWORK)) + { + /* Has the server responded */ + if (tcxn.open) + { + success = true; + break; + } + } + + /* If the connection is open, we are done here */ + if (success || tcxn.error) + break; + } + if (!retries) + { + xprintf("TFTP could not make connection to server.\n"); + udp_free_port(tcxn.my_port); + return false; + } + else if (tcxn.error) + { + xprintf("\bErrors in TFTP upload.\n"); + udp_free_port(tcxn.my_port); + return false; + } + + bytes_to_send = end - begin; + current = (uint8_t *)begin; + blocknum = 1; + retries = 4; + success = false; + + while (--retries) + { + pNbuf = nbuf_alloc(); + if (pNbuf == NULL) + { + xprintf("TFTP: tftp_write() couldn't allocate Tx buffer\n"); + return false; + } + + /* Build the packet */ + data = (DATA *)&pNbuf->data[TFTP_HDR_OFFSET]; + data->blocknum = blocknum; + data->opcode = TFTP_DATA; + + this_size = (bytes_to_send > TFTP_PKTSIZE) ? \ + TFTP_PKTSIZE : (uint16_t)bytes_to_send; + + for (i = 0; i < this_size; i++) + { + data->data[i] = current[i]; + } + + /* Set the packet length */ + pNbuf->length = (uint16_t)(4 + this_size); + + /* Attempt to send the packet */ + for (i = 0; i < 3; ++i) + { + result = udp_send(tcxn.nif, + tcxn.server_ip, + tcxn.my_port, + tcxn.server_port, + pNbuf); + + if (result == 1) + break; + } + + if (result == 0) + nbuf_free(pNbuf); + + timer_set_secs(TIMER_NETWORK, TFTP_TIMEOUT); + while (timer_get_reference(TIMER_NETWORK)) + { + /* Has the server responded */ + if ((tcxn.exp_blocknum - 1) == blocknum) + { + success = true; + break; + } + } + + /* TFTP Write Compeleted successfully */ + if (success && (this_size < TFTP_PKTSIZE)) + { + tcxn.bytes_sent += this_size; + break; + } + + if (tcxn.error) + break; + + /* If an ACK was received, keep sending packets */ + if (success) + { + tcxn.bytes_sent += TFTP_PKTSIZE; + bytes_to_send -= TFTP_PKTSIZE; + current += TFTP_PKTSIZE; + blocknum++; + retries = 4; + success = false; + } + } + if (tcxn.error) + { + xprintf("TFTP lost connection to server.\n"); + xprintf("Sent %d bytes (%d blocks)\n", \ + tcxn.bytes_sent, tcxn.exp_blocknum - 1); + udp_free_port(tcxn.my_port); + return false; + } + else + { + xprintf("\bTFTP upload successful\n"); + xprintf("Sent %d bytes (%d blocks)\n", \ + tcxn.bytes_sent, tcxn.exp_blocknum - 1); + udp_free_port(tcxn.my_port); + return true; + } +} + +int tftp_read(NIF *nif, char *fn, IP_ADDR_P server) +{ + uint32_t retries; + + if (fn == 0 || server == 0) + return 0; + + /* Setup initial connection status */ + tcxn.nif = nif; + tcxn.file = fn; + tcxn.server_ip[0] = server[0]; + tcxn.server_ip[1] = server[1]; + tcxn.server_ip[2] = server[2]; + tcxn.server_ip[3] = server[3]; + tcxn.server_port = UDP_PORT_TFTP; + tcxn.exp_blocknum = 1; + tcxn.last_ack = 0; + tcxn.dir = TFTP_RRQ; + tcxn.open = false; + tcxn.bytes_recv = 0; + tcxn.rem_bytes = 0; + tcxn.next_char = NULL; + tcxn.error = false; + queue_init(&tcxn.queue); + + /* Use Mac address as pseudo-random port */ + udp_prime_port((uint16_t)((nif->hwa[4] << 8) | nif->hwa[5])); + tcxn.my_port = udp_obtain_free_port(); + udp_bind_port(tcxn.my_port,&tftp_handler); + + retries = 4; + + while (--retries) + { + /* Make the TFTP Read/Write Request */ + if (!tftp_rwrq()) + { + xprintf("Error: Couldn't send TFTP Read Request\n"); + udp_free_port(tcxn.my_port); + return false; + } + + timer_set_secs(TIMER_NETWORK, TFTP_TIMEOUT); + while (timer_get_reference(TIMER_NETWORK)) + { + /* Has the server responded */ + if (tcxn.open == true) + break; + } + + /* If the connection is open, we are done here */ + if ((tcxn.open == true) || tcxn.error) + break; + } + if (!retries) + { + xprintf("TFTP could not make connection to server.\n"); + udp_free_port(tcxn.my_port); + return false; + } + else if (tcxn.error) + { + xprintf("\bErrors in TFTP download.\n"); + udp_free_port(tcxn.my_port); + return false; + } + else + return true; +} + +int tftp_in_char(void) +{ + union TFTPpacket *tftp_pkt; + int retval; + NBUF *pNbuf; + + if (tcxn.next_char != NULL) + { + /* + * A buffer is already being worked on - grab next + * byte from it + */ + retval = *tcxn.next_char++; + if (--tcxn.rem_bytes <= 0) + { + /* The buffer is depleted; add it back to the free queue */ + pNbuf = (NBUF *)queue_remove(&tcxn.queue); + + nbuf_free(pNbuf); + tcxn.next_char = NULL; + } + } + else + { + /* Is the connection still open? */ + if (tcxn.open == false) + { + /* + * The last packet has been received and the last data + * buffer has been exhausted + */ + retval = -1; + } + else + { + /* Get pointer to the next buffer */ + pNbuf = (NBUF *)queue_peek(&tcxn.queue); + + if (pNbuf == NULL) + { + int i; + + /* There was no buffer in the queue */ + for (i = 0; i < 3; ++i) + { + timer_set_secs(TIMER_NETWORK, 1); + while (timer_get_reference(TIMER_NETWORK)) + { + /* Has the server sent another DATA packet? */ + if (!queue_isempty(&tcxn.queue)) + { + pNbuf = (NBUF *)queue_peek(&tcxn.queue); + break; + } + } + if (pNbuf != NULL) + break; + + /* Ack the last packet again */ + xprintf("Re-acking %d\n",tcxn.last_ack - 1); + retval = tftp_ack(tcxn.last_ack - 1); + } + } + if (pNbuf == NULL) + { + /* The server didn't respond with the expected packet */ + tcxn.open = false; + tcxn.error = true; + xprintf("TFTP lost connection to server.\n"); + retval = -1; + } + else + { + tftp_pkt = (union TFTPpacket *)&pNbuf->data[pNbuf->offset]; + + /* Subtract the TFTP header from the data length */ + tcxn.rem_bytes = pNbuf->length - 4; + + /* Point to first data byte in the packet */ + tcxn.next_char = tftp_pkt->data.data; + + /* Save off the block number */ + tcxn.last_ack = tftp_pkt->data.blocknum; + + /* Check to see if this is the last packet of the transfer */ + if (tcxn.rem_bytes < TFTP_PKTSIZE) + tcxn.open = false; + + /* Check for empty termination packet */ + if (tcxn.rem_bytes == 0) + { + pNbuf = (NBUF *)queue_remove(&tcxn.queue); + nbuf_free(pNbuf); + tcxn.next_char = NULL; + retval = tftp_ack(tcxn.last_ack++); + retval = -1; + } + else + { + retval = tftp_ack(tcxn.last_ack++); + retval = *tcxn.next_char++; + + /* Check for a single byte packet */ + if (--tcxn.rem_bytes == 0) + { + /* The buffer is depleted; add it back to the free queue */ + pNbuf = (NBUF *)queue_remove(&tcxn.queue); + nbuf_free(pNbuf); + tcxn.next_char = NULL; + } + } + } + } + } + return retval; +} diff --git a/net/udp.c b/net/udp.c new file mode 100644 index 0000000..cd84c4e --- /dev/null +++ b/net/udp.c @@ -0,0 +1,184 @@ +/* + * File: udp.c + * Purpose: User Datagram Protocol driver + * + * Notes: + * + * Modifications: + * + */ +#include "bas_types.h" +#include "bas_printf.h" +#include "net.h" +#include + +//#define DBG_UDP +#if defined(DBG_UDP) +#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0) +#else +#define dbg(format, arg...) do { ; } while (0) +#endif /* DBG_UDP */ + +typedef struct +{ + uint16_t port; + void (*handler)(NIF *, NBUF *); +} UDP_BOUND_PORT; + +#define UDP_MAX_PORTS (5) /* plenty for this implementation */ + + +static UDP_BOUND_PORT udp_port_table[UDP_MAX_PORTS]; + +static uint16_t udp_port; + +void udp_init(void) +{ + int index; + + for (index = 0; index < UDP_MAX_PORTS; ++index) + { + udp_port_table[index].port = 0; + udp_port_table[index].handler = 0; + } + + udp_port = DEFAULT_UDP_PORT; /* next free port */ +} + +void udp_prime_port(uint16_t init_port) +{ + udp_port = init_port; +} + +void udp_bind_port(uint16_t port, void (*handler)(NIF *, NBUF *)) +{ + int index; + + for (index = 0; index < UDP_MAX_PORTS; ++index) + { + if (udp_port_table[index].port == 0) + { + udp_port_table[index].port = port; + udp_port_table[index].handler = handler; + + return; + } + } +} + +void udp_free_port(uint16_t port) +{ + int index; + + for (index = 0; index < UDP_MAX_PORTS; ++index) + { + if (udp_port_table[index].port == port) + { + udp_port_table[index].port = 0; + + return; + } + } +} + +static void *udp_port_handler(uint16_t port) +{ + int index; + + for (index = 0; index < UDP_MAX_PORTS; ++index) + { + if (udp_port_table[index].port == port) + { + return (void *) udp_port_table[index].handler; + } + } + return NULL; +} + +uint16_t udp_obtain_free_port(void) +{ + uint16_t port; + + port = udp_port; + if (--udp_port <= 255) + udp_port = DEFAULT_UDP_PORT; + + return port; +} + +int udp_send(NIF *nif, uint8_t *dest, int sport, int dport, NBUF *pNbuf) +{ + uint8_t *myip; + + if (nif == NULL) + { + dbg("nif is NULL\r\n"); + return 0; + } + + /* + * This function takes data, creates a UDP frame from it and + * passes it onto the IP layer + */ + udp_frame_hdr *udpframe; + + udpframe = (udp_frame_hdr *) &pNbuf->data[UDP_HDR_OFFSET]; + + /* Set UDP source port */ + udpframe->src_port = (uint16_t) sport; + + /* Set UDP destination port */ + udpframe->dest_port = (uint16_t) dport; + + /* Set length */ + udpframe->length = (uint16_t) (pNbuf->length + UDP_HDR_SIZE); + + /* No checksum calcualation needed */ + udpframe->chksum = (uint16_t) 0; + + /* Add the length of the UDP packet to the total length of the packet */ + pNbuf->length += 8; + + myip = ip_get_myip(nif_get_protocol_info(nif, ETH_FRM_IP)); + + dbg("sent UDP request to %d.%d.%d.%d from %d.%d.%d.%d\r\n", + dest[0], dest[1], dest[2], dest[3], + myip[0], myip[1], myip[2], myip[3]); + + return (ip_send(nif, dest, myip, IP_PROTO_UDP, pNbuf)); + +} + +void udp_handler(NIF *nif, NBUF *pNbuf) +{ + /* + * This function handles incoming UDP packets + */ + udp_frame_hdr *udpframe; + void (*handler)(NIF *, NBUF *); + + udpframe = (udp_frame_hdr *) &pNbuf->data[pNbuf->offset]; + + dbg("packet received\r\n",); + + /* + * Adjust the length and valid data offset of the packet we are + * passing on + */ + pNbuf->length -= UDP_HDR_SIZE; + pNbuf->offset += UDP_HDR_SIZE; + + /* + * Traverse the list of bound ports to see if there is a higher + * level protocol to pass the packet on to + */ + if ((handler = (void(*)(NIF*, NBUF*)) udp_port_handler(UDP_DEST(udpframe))) != NULL) + handler(nif, pNbuf); + else + { + dbg("received UDP packet for non-supported port\n"); + nbuf_free(pNbuf); + } + + return; +} diff --git a/nutil/s19header.c b/nutil/s19header.c new file mode 100644 index 0000000..e40fe6b --- /dev/null +++ b/nutil/s19header.c @@ -0,0 +1,380 @@ +/* + * s19header.c + * + * Created on: 17.12.2012 + * Author: mfro + * The ACP Firebee project + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Copyright 2012 M. Froeschle + */ + +#include +#include +#include +#include +#include + +#include "s19reader.h" + +/* + * Yes, I know. The following doesn't really look like code should look like... + * + * I did try to map structures over the S-records with (packed) which didn't work reliably due to + * gcc _not_ packing them appropiate and finally ended up with this. Not nice, put paid (and working). + * + */ +#define SREC_TYPE(a) (a)[0] /* type of record */ +#define SREC_COUNT(a) (a)[1] /* length of valid bytes to follow */ +#define SREC_ADDR16(a) (256 * (a)[2] + (a)[3]) /* 2 byte address field */ +#define SREC_ADDR24(a) (0x10000 * (a)[2] + 0x100 * \ + (a)[3] + (a)[4]) /* 3 byte address field */ +#define SREC_ADDR32(a) (0x1000000 * a[2] + 0x10000 * \ + a[3] + 0x100 * (a)[4] + (a)[5]) /* 4 byte address field */ +#define SREC_DATA16(a) ((uint8_t *)&((a)[4])) /* address of first byte of data in a record */ +#define SREC_DATA24(a) ((uint8_t *)&((a)[5])) /* address of first data byte in 24 bit record */ +#define SREC_DATA32(a) ((uint8_t *)&((a)[6])) /* adress of first byte of a record with 32 bit address field */ +#define SREC_DATA16_SIZE(a) (SREC_COUNT((a)) - 3) /* length of the data[] array without the checksum field */ +#define SREC_DATA24_SIZE(a) (SREC_COUNT((a)) - 4) /* length of the data[] array without the checksum field */ +#define SREC_DATA32_SIZE(a) (SREC_COUNT((a)) - 5) /* length of the data[] array without the checksum field */ +#define SREC_CHECKSUM(a) (a)[SREC_COUNT(a) + 2 - 1] /* record's checksum (two's complement of the sum of all bytes) */ + +#define SREC_MODULENAME(a) &((a)[4]) /* module name in an S0 record */ +#define SREC_MODULENAME_LENGTH 20 +#define SREC_VERSION(a) &((a)[24]) /* version info in an S0 record */ +#define SREC_VERSION_LENGTH 2 +#define SREC_REVISION(a) &((a)[26]) /* revision info in an S0 record */ +#define SREC_REVISIION_LENGTH 2 +#define SREC_DESCRIPTION(a) &((a)[28]) /* description field in an S0 record */ +#define SREC_DESCRIPTION_LENGTH 36 + +/* + * convert a single hex character into byte + */ +static uint8_t nibble_to_byte(uint8_t nibble) +{ + if ((nibble >= '0') && (nibble <= '9')) + return nibble - '0'; + else if ((nibble >= 'A' && nibble <= 'F')) + return 10 + nibble - 'A'; + else if ((nibble >= 'a' && nibble <= 'f')) + return 10 + nibble - 'a'; + return 0; +} + +/* + * convert two hex characters into byte + */ +static uint8_t hex_to_byte(uint8_t hex[2]) +{ + return 16 * (nibble_to_byte(hex[0])) + (nibble_to_byte(hex[1])); +} + +#ifdef _NOT_USED_ +/* + * convert four hex characters into a 16 bit word + */ +static uint16_t hex_to_word(uint8_t hex[4]) +{ + return 256 * hex_to_byte(&hex[0]) + hex_to_byte(&hex[2]); +} + +/* + * convert eight hex characters into a 32 bit word + */ +static uint32_t hex_to_long(uint8_t hex[8]) +{ + return 65536 * hex_to_word(&hex[0]) + hex_to_word(&hex[4]); +} +#endif /* _NOT_USED_ */ + +/* + * compute the record checksum + * + * it consists of the one's complement of the byte sum of the data from the count field until the end + */ +static uint8_t checksum(uint8_t arr[]) +{ + int i; + uint8_t checksum = SREC_COUNT(arr); + + for (i = 0; i < SREC_COUNT(arr) - 1; i++) + { + checksum += arr[i + 2]; + } + return ~checksum; +} + +void print_record(uint8_t *arr) +{ + switch (SREC_TYPE(arr)) + { + case 0: + { + printf("type 0x%x ", SREC_TYPE(arr)); + printf("count 0x%x ", SREC_COUNT(arr)); + printf("addr 0x%x ", SREC_ADDR16(arr)); + printf("module %11.11s ", SREC_DATA16(arr)); + printf("chk 0x%x 0x%x\r\n", SREC_CHECKSUM(arr), checksum(arr)); + } + break; + + case 3: + case 7: + { + printf("type 0x%x ", SREC_TYPE(arr)); + printf("count 0x%x ", SREC_COUNT(arr)); + printf("addr 0x%x ", SREC_ADDR32(arr)); + printf("data %02x,%02x,%02x,%02x,... ", + SREC_DATA32(arr)[0], SREC_DATA32(arr)[1], SREC_DATA32(arr)[3], SREC_DATA32(arr)[4]); + printf("chk 0x%x 0x%x\r\n", SREC_CHECKSUM(arr), checksum(arr)); + } + break; + + default: + printf("unsupported report type %d in print_record\r\n", arr[0]); + break; + } +} + +/* + * convert an S-record line into its corresponding byte vector (ASCII->binary) + */ +static void line_to_vector(uint8_t *buff, uint8_t *vector) +{ + int i; + int length; + uint8_t *vp = vector; + + length = hex_to_byte(buff + 2); + + buff++; + *vp++ = nibble_to_byte(*buff); /* record type. Only one single nibble */ + buff++; + + for (i = 0; i <= length; i++) + { + *vp++ = hex_to_byte(buff); + buff += 2; + } +} + +static void vector_to_line(uint8_t *vector, uint8_t *buff) +{ + sprintf(buff, "S"); +} + +/* + * read and parse a Motorola S-record file and copy contents to dst. The theory of operation is to read and parse the S-record file + * and to use the supplied callback routine to copy the buffer to the destination once the S-record line is converted. + * The memcpy callback can be anything (as long as it conforms parameter-wise) - a basically empty function to just let + * read_srecords validate the file, a standard memcpy() to copy file contents to destination RAM or a more sophisticated + * routine that does write/erase flash + * + * FIXME: Currently only records that the gcc toolchain emits are supported. + * + * Parameters: + * IN + * filename - the filename that contains the S-records + * callback - the memcpy() routine discussed above + * OUT + * start_address - the execution address of the code as read from the file. Can be used to jump into and execute it + * actual_length - the overall length of the binary code read from the file + * returns + * OK or an err_t error code if anything failed + */ +int main(int argc, char *argv[]) +{ + int fres; + int set; + char *filename = NULL; + FILE *file; + int ret = OK; + int i; + + + for (i = 1; i < argc; i++) + { + if (argv[i][0] == '-') + { + /* option */ + if (strcmp(argv[i], "-s") == 0) + { + set = 1; + } + } + else + { + filename = argv[i]; + } + } + + if (filename == NULL) + { + fprintf(stderr, "no filename given\n"); + exit(1); + } + + if ((file = fopen(filename, "r")) != NULL) + { + uint8_t line[80]; + int lineno = 0; + int data_records = 0; + bool found_block_header = false; + bool found_block_end = false; + bool found_block_data = false; + + while (ret == OK && (uint8_t *) fgets((char *) line, sizeof(line), file) != NULL) + { + lineno++; + uint8_t vector[80]; + char str[255]; + int length; + + + + line_to_vector(line, vector); /* vector now contains the decoded contents of line, from line[1] on */ + + if (line[0] == 'S') + { + char header[256]; + + if (SREC_CHECKSUM(vector) != checksum(vector)) + { + printf("invalid checksum 0x%x (should be 0x%x) in line %d\r\n", + SREC_CHECKSUM(vector), checksum(vector), lineno); + ret = FAIL; + } + + switch (vector[0]) + { + case 0: /* block header */ + found_block_header = true; + if (found_block_data || found_block_end) + { + printf("S7 or S3 record found before S0: S-records corrupt?\r\n"); + ret = FAIL; + } + printf("address: 0x%04x\n", SREC_ADDR16(vector)); + printf("length of record: %d\n", SREC_COUNT(vector)); + length = SREC_DATA16_SIZE(vector) - (SREC_DATA16(vector) - vector); + printf("length: %d\n", length); + strncpy(str, SREC_DATA16(vector), length); + str[length] = '\0'; + printf("Name: %s\n", str); + printf("version: %d, revision %d\n", + * (unsigned short *)((char *) SREC_DATA16(vector) + length), + * (unsigned short *)((char *) SREC_DATA16(vector) + length + 1)); + print_record(vector); + + break; + + case 2: /* three byte address field data record */ + if (!found_block_header || found_block_end) + { + printf("S3 record found before S0 or after S7: S-records corrupt?\r\n"); + ret = FAIL; + } + // ret = callback((uint8_t *) SREC_ADDR24(vector), SREC_DATA24(vector), SREC_DATA24_SIZE(vector)); + data_records++; + break; + + case 3: /* four byte address field data record */ + if (!found_block_header || found_block_end) + { + printf("S3 record found before S0 or after S7: S-records corrupt?\r\n"); + ret = FAIL; + } + // ret = callback((uint8_t *) SREC_ADDR32(vector), SREC_DATA32(vector), SREC_DATA32_SIZE(vector)); + data_records++; + break; + + case 7: /* four byte address field end record */ + if (!found_block_header || found_block_end) + { + printf("S7 record found before S0 or after S7: S-records corrupt?\r\n"); + } + else + { + // printf("S7 record (end) found after %d valid data blocks\r\n", data_records); + //*start_address = (void *) SREC_ADDR32(vector); + } + break; + + case 8: /* three byte address field end record */ + if (!found_block_header || found_block_end) + { + printf("S8 record found before S0 or after S8: S-records corrupt?\r\n"); + } + else + { + // printf("S7 record (end) found after %d valid data blocks\r\n", data_records); + //*start_address = (void *) SREC_ADDR24(vector); + } + break; + + default: + printf("unsupported record type (%d) found in line %d\r\n", vector[0], lineno); + printf("offending line: \r\n"); + printf("%s\r\n", line); + ret = FAIL; + break; + } + } + else + { + printf("illegal character ('%c') found on line %d: S-records corrupt?\r\n", line[0], lineno); + ret = FAIL; + break; + } + } + fclose(file); + } + else + { + printf("could not open file %s\r\n", filename); + ret = FILE_OPEN; + } + return ret; +} + +/* + * this callback just does nothing besides returning OK. Meant to do a dry run over the file to check its integrity + */ +static err_t simulate() +{ + err_t ret = OK; + + return ret; +} + + +/* + * this callback verifies the data against the S-record file contents after a write to destination + */ +static err_t verify(uint8_t *dst, uint8_t *src, uint32_t length) +{ + uint8_t *end = src + length; + + do + { + if (*src++ != *dst++) + return FAIL; + } while (src < end); + + return OK; +} diff --git a/pci/ehci-hcd.c b/pci/ehci-hcd.c new file mode 100644 index 0000000..9be487a --- /dev/null +++ b/pci/ehci-hcd.c @@ -0,0 +1,1174 @@ +/* + * Copyright (c) 2007-2008, Juniper Networks, Inc. + * Copyright (c) 2008, Excito Elektronik i SkÃ¥ne AB + * Copyright (c) 2008, Michael Trimarchi + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include "util.h" /* for endian conversions */ +#include "bas_printf.h" /* for diagnostics */ +#include "wait.h" +#include "cache.h" +#include "usb.h" +#include "ehci.h" +#include "pci.h" + +// #define DEBUG +#include "debug.h" + +static char ehci_inited; +static int rootdev; + +static uint16_t portreset; +static uint16_t companion; + +struct descriptor +{ + struct usb_hub_descriptor hub; + struct usb_device_descriptor device; + struct usb_linux_config_descriptor config; + struct usb_linux_interface_descriptor interface; + struct usb_endpoint_descriptor endpoint; +} __attribute__ ((packed)); + +static struct descriptor rom_descriptor = +{ +{ + 0x8, /* bDescLength */ + 0x29, /* bDescriptorType: hub descriptor */ + 2, /* bNrPorts -- runtime modified */ + 0, /* wHubCharacteristics */ + 0xff, /* bPwrOn2PwrGood */ + 0, /* bHubCntrCurrent */ +{}, /* Device removable */ +{} /* at most 7 ports! XXX */ +}, +{ + 0x12, /* bLength */ + 1, /* bDescriptorType: UDESC_DEVICE */ + 0x0002, /* bcdUSB: v2.0 */ + 9, /* bDeviceClass: UDCLASS_HUB */ + 0, /* bDeviceSubClass: UDSUBCLASS_HUB */ + 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */ + 64, /* bMaxPacketSize: 64 bytes */ + 0x0000, /* idVendor */ + 0x0000, /* idProduct */ + 0x0001, /* bcdDevice */ + 1, /* iManufacturer */ + 2, /* iProduct */ + 0, /* iSerialNumber */ + 1 /* bNumConfigurations: 1 */ +}, +{ + 0x9, + 2, /* bDescriptorType: UDESC_CONFIG */ + (0x19 << 8), /* cpu_to_le16(0x19), */ + 1, /* bNumInterface */ + 1, /* bConfigurationValue */ + 0, /* iConfiguration */ + 0x40, /* bmAttributes: UC_SELF_POWER */ + 0 /* bMaxPower */ +}, +{ + 0x9, /* bLength */ + 4, /* bDescriptorType: UDESC_INTERFACE */ + 0, /* bInterfaceNumber */ + 0, /* bAlternateSetting */ + 1, /* bNumEndpoints */ + 9, /* bInterfaceClass: UICLASS_HUB */ + 0, /* bInterfaceSubClass: UISUBCLASS_HUB */ + 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */ + 0 /* iInterface */ +}, +{ + 0x7, /* bLength */ + 5, /* bDescriptorType: UDESC_ENDPOINT */ + 0x81, /* bEndpointAddress: UE_DIR_IN | EHCI_INTR_ENDPT */ + 3, /* bmAttributes: UE_INTERRUPT */ + 8, 0, /* wMaxPacketSize */ + 255 /* bInterval */ +}, +}; + +struct pci_device_id ehci_usb_pci_table[] = +{ +{ + PCI_VENDOR_ID_NEC, + PCI_DEVICE_ID_NEC_USB_2, + PCI_ANY_ID, + PCI_ANY_ID, + PCI_CLASS_SERIAL_USB_EHCI, + 0, + 0 +}, /* NEC PCI OHCI module ids */ +{ + PCI_VENDOR_ID_NEC, + PCI_DEVICE_ID_NEC_USB_3, + PCI_ANY_ID, + PCI_ANY_ID, + PCI_CLASS_SERIAL_USB_EHCI, + 0, + 0 +}, +{ + PCI_VENDOR_ID_PHILIPS, + PCI_DEVICE_ID_PHILIPS_ISP1561_2, + PCI_ANY_ID, + PCI_ANY_ID, + PCI_CLASS_SERIAL_USB_EHCI, + 0, + 0 +}, /* Philips 1561 PCI OHCI module ids */ +/* Please add supported PCI OHCI controller ids here */ +{ + 0, + 0, + 0, + 0, + 0, + 0, + 0 +} +}; + +static struct ehci +{ + /* ------- common part -------- */ + long handle; /* PCI BIOS */ + const struct pci_device_id *ent; + int usbnum; + /* ---- end of common part ---- */ + int big_endian; /* PCI BIOS */ + struct ehci_hccr *hccr; /* R/O registers, not need for volatile */ + volatile struct ehci_hcor *hcor; + struct QH *qh_list_unaligned; + struct QH *qh_list; + struct QH *qh_unaligned; + struct QH *qh; + struct qTD *td_unaligned[3]; + struct qTD *td[3]; + struct descriptor *descriptor; + int irq; + uint32_t dma_offset; + const char *slot_name; +} gehci; + +static void cache_qtd(struct qTD *qtd, int flush) +{ + /* + * not needed + */ + //flush_and_invalidate_caches(); +} + +static inline struct QH *qh_addr(struct QH *qh) +{ + return (struct QH *)((uint32_t) qh & 0xffffffe0); +} + +static void cache_qh(struct QH *qh, int flush) +{ + struct qTD *qtd; + struct qTD *next; + static struct qTD *first_qtd; + + /* Walk the QH list and flush/invalidate all entries */ + while(1) + { + flush_and_invalidate_caches(); + if ((uint32_t) qh & QH_LINK_TYPE_QH) + break; + qh = qh_addr(qh); + qh = (struct QH *)(swpl(qh->qh_link) + gehci.dma_offset); + } + qh = qh_addr(qh); + + /* Save first qTD pointer, needed for invalidating pass on this QH */ + if (flush) + { + qtd = (struct qTD *)(swpl(*(uint32_t *)&qh->qh_overlay) & 0xffffffe0); + if (qtd != NULL) + qtd = (struct qTD *)(gehci.dma_offset + (uint32_t)qtd); + first_qtd = qtd; + } + else + qtd = first_qtd; + + /* Walk the qTD list and flush/invalidate all entries */ + while(1) + { + if (qtd == NULL) + break; + cache_qtd(qtd, flush); + next = (struct qTD *)((uint32_t)swpl(qtd->qt_next) & 0xffffffe0); + if (next != NULL) + next = (struct qTD *)(gehci.dma_offset + (uint32_t)next); + if (next == qtd) + break; + qtd = next; + } +} + +static inline void ehci_flush_dcache(struct QH *qh) +{ + cache_qh(qh, 1); +} + +static inline void ehci_invalidate_dcache(struct QH *qh) +{ + cache_qh(qh, 0); +} + +static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec) +{ + uint32_t result; + + do + { + result = ehci_readl(ptr); + if (result == ~ (uint32_t) 0) + { + return -1; + } + result &= mask; + if (result == done) + { + return 0; + } + wait(1); + usec--; + } while (usec > 0); + + return -1; +} + +static void ehci_free(void *p, size_t sz) +{ +} + +static int ehci_reset(void) +{ + uint32_t cmd; + int ret = 0; + + if ((gehci.ent->vendor == PCI_VENDOR_ID_NEC) && (gehci.ent->device == PCI_DEVICE_ID_NEC_USB_2)) + { + dbg("ehci_reset set 48MHz clock\r\n"); + pci_write_config_longword(gehci.handle, 0xE4, 0x20); // oscillator + wait(5); + } + + cmd = ehci_readl(&gehci.hcor->or_usbcmd); + dbg("%s cmd: 0x%08x\r\n", __FUNCTION__, cmd); + + cmd |= CMD_RESET; + ehci_writel(&gehci.hcor->or_usbcmd, cmd); + ret = handshake((uint32_t *) &gehci.hcor->or_usbcmd, CMD_RESET, 0, 250); + if (ret < 0) + { + err("*** EHCI fail to reset! ***\r\n"); + goto out; + } + +out: + return ret; +} + +static void *ehci_alloc(size_t sz, size_t align) +{ + static int ntds; + void *p; + switch(sz) + { + case sizeof(struct QH): + p = gehci.qh; + ntds = 0; + break; + + case sizeof(struct qTD): + if (ntds == 3) + { + dbg("out of TDs\r\n"); + return NULL; + } + p = gehci.td[ntds]; + ntds++; + break; + + default: + dbg("unknown allocation size\r\n"); + return NULL; + } + memset(p, sz, 0); + return p; +} + +static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz) +{ + uint32_t addr; + uint32_t delta; + uint32_t next; + int idx; + + addr = (uint32_t)buf; + idx = 0; + + while (idx < 5) + { + td->qt_buffer[idx] = swpl(addr - gehci.dma_offset); + next = (addr + 4096) & ~4095; + delta = next - addr; + if (delta >= sz) + break; + sz -= delta; + addr = next; + idx++; + } + + if (idx == 5) + { + dbg("out of buffer pointers (%u bytes left)\r\n", sz); + return -1; + } + return 0; +} + +static int ehci_submit_async(struct usb_device *dev, uint32_t pipe, void *buffer, int length, struct devrequest *req) +{ + struct QH *qh; + struct qTD *td; + volatile struct qTD *vtd; + uint32_t ts; + uint32_t *tdp; + uint32_t endpt; + uint32_t token; + uint32_t usbsts; + uint32_t c; + uint32_t toggle; + uint32_t cmd; + int ret = 0; + + dbg("%s: dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\r\n", __FUNCTION__, dev, pipe, buffer, length, req); + +#ifdef DBG_EHCI + if (req != NULL) + dbg("ehci_submit_async req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\r\n", + req->request, req->request, + req->requesttype, req->requesttype, + swpw(req->value), swpw(req->value), swpw(req->index)); +#endif /* DBG_EHCI */ + + qh = ehci_alloc(sizeof(struct QH), 32); + if (qh == NULL) + { + dbg("unable to allocate QH\r\n"); + return -1; + } + qh->qh_link = swpl(((uint32_t) gehci.qh_list - gehci.dma_offset) | QH_LINK_TYPE_QH); + + c = (usb_pipespeed(pipe) != USB_SPEED_HIGH && usb_pipeendpoint(pipe) == 0) ? 1 : 0; + endpt = (8 << 28) | + (c << 27) | + (usb_maxpacket(dev, pipe) << 16) | + (0 << 15) | + (1 << 14) | + (usb_pipespeed(pipe) << 12) | + (usb_pipeendpoint(pipe) << 8) | + (0 << 7) | + (usb_pipedevice(pipe) << 0); + qh->qh_endpt1 = swpl(endpt); + endpt = (1 << 30) | + (dev->portnr << 23) | + (dev->parent->devnum << 16) | + (0 << 8) | + (0 << 0); + qh->qh_endpt2 = swpl(endpt); + qh->qh_overlay.qt_next = swpl(QT_NEXT_TERMINATE); + qh->qh_overlay.qt_altnext = swpl(QT_NEXT_TERMINATE); + td = NULL; + tdp = &qh->qh_overlay.qt_next; + toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); + + if (req != NULL) + { + td = ehci_alloc(sizeof(struct qTD), 32); + if (td == NULL) + { + dbg("unable to allocate SETUP td\r\n"); + goto fail; + } + td->qt_next = swpl(QT_NEXT_TERMINATE); + td->qt_altnext = swpl(QT_NEXT_TERMINATE); + token = (0 << 31) | (sizeof(*req) << 16) | (0 << 15) | (0 << 12) | (3 << 10) | (2 << 8) | (0x80 << 0); + td->qt_token = swpl(token); + if (ehci_td_buffer(td, req, sizeof(*req)) != 0) + { + dbg("unable construct SETUP td\r\n"); + ehci_free(td, sizeof(*td)); + goto fail; + } + *tdp = swpl((uint32_t)td - gehci.dma_offset); + tdp = &td->qt_next; + toggle = 1; + } + + if (length > 0 || req == NULL) + { + td = ehci_alloc(sizeof(struct qTD), 32); + if (td == NULL) + { + dbg("unable to allocate DATA td\r\n"); + goto fail; + } + td->qt_next = swpl(QT_NEXT_TERMINATE); + td->qt_altnext = swpl(QT_NEXT_TERMINATE); + token = (toggle << 31) | (length << 16) | ((req == NULL ? 1 : 0) << 15) | (0 << 12) | (3 << 10) | ((usb_pipein(pipe) ? 1 : 0) << 8) | (0x80 << 0); + td->qt_token = swpl(token); + if (ehci_td_buffer(td, buffer, length) != 0) + { + dbg("unable construct DATA td\r\n"); + ehci_free(td, sizeof(*td)); + goto fail; + } + *tdp = swpl((uint32_t)td - gehci.dma_offset); + tdp = &td->qt_next; + } + + if (req != NULL) + { + td = ehci_alloc(sizeof(struct qTD), 32); + if (td == NULL) + { + dbg("unable to allocate ACK td\r\n"); + goto fail; + } + td->qt_next = swpl(QT_NEXT_TERMINATE); + td->qt_altnext = swpl(QT_NEXT_TERMINATE); + token = (toggle << 31) | (0 << 16) | (1 << 15) | (0 << 12) | (3 << 10) | ((usb_pipein(pipe) ? 0 : 1) << 8) | (0x80 << 0); + td->qt_token = swpl(token); + *tdp = swpl((uint32_t)td - gehci.dma_offset); + tdp = &td->qt_next; + } + + gehci.qh_list->qh_link = swpl(((uint32_t)qh - gehci.dma_offset) | QH_LINK_TYPE_QH); + + /* Flush dcache */ + ehci_flush_dcache(gehci.qh_list); + usbsts = ehci_readl(&gehci.hcor->or_usbsts); + ehci_writel(&gehci.hcor->or_usbsts, (usbsts & 0x3f)); + + /* Enable async. schedule. */ + cmd = ehci_readl(&gehci.hcor->or_usbcmd); + cmd |= CMD_ASE; + ehci_writel(&gehci.hcor->or_usbcmd, cmd); + + ret = handshake((uint32_t *) &gehci.hcor->or_usbsts, STD_ASS, STD_ASS, 100 * 1000); + if (ret < 0) + { + err("EHCI fail timeout STD_ASS set (usbsts=%#x)", ehci_readl(&gehci.hcor->or_usbsts)); + goto fail; + } + + /* Wait for TDs to be processed. */ + ts = 0; + vtd = td; + do + { + /* Invalidate dcache */ + ehci_invalidate_dcache(gehci.qh_list); + token = swpl(vtd->qt_token); + if (!(token & 0x80)) + { + break; + } + wait(1 * 1000); + ts++; + } while (ts < 1000); + + /* Disable async schedule. */ + cmd = ehci_readl(&gehci.hcor->or_usbcmd); + cmd &= ~CMD_ASE; + ehci_writel(&gehci.hcor->or_usbcmd, cmd); + ret = handshake((uint32_t *) &gehci.hcor->or_usbsts, STD_ASS, 0, 100 * 1000); + if (ret < 0) + { + err("EHCI fail timeout STD_ASS reset (usbsts=%#x)", ehci_readl(&gehci.hcor->or_usbsts)); + goto fail; + } + gehci.qh_list->qh_link = swpl(((uint32_t)gehci.qh_list - gehci.dma_offset) | QH_LINK_TYPE_QH); + + token = swpl(qh->qh_overlay.qt_token); + if (!(token & 0x80)) + { + dbg("TOKEN=%#x\r\n", token); + switch(token & 0xfc) + { + case 0: + toggle = token >> 31; + usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle); + dev->status = 0; + break; + + case 0x40: + dev->status = USB_ST_STALLED; + break; + + case 0xa0: + case 0x20: + dev->status = USB_ST_BUF_ERR; + break; + + case 0x50: + case 0x10: + dev->status = USB_ST_BABBLE_DET; + break; + + default: + dev->status = USB_ST_CRC_ERR; + break; + } + dev->act_len = length - ((token >> 16) & 0x7fff); + } + else + { + dev->act_len = 0; + dbg("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\r\n", + dev->devnum, ehci_readl(&gehci.hcor->or_usbsts), + ehci_readl(&gehci.hcor->or_portsc[0]), ehci_readl(&gehci.hcor->or_portsc[1])); + } + return (dev->status != USB_ST_NOT_PROC) ? 0 : -1; +fail: + td = (void *) swpl(qh->qh_overlay.qt_next); + if (td != (void *)QT_NEXT_TERMINATE) + td = (struct qTD *)(gehci.dma_offset + (uint32_t)td); + while(td != (void *)QT_NEXT_TERMINATE) + { + qh->qh_overlay.qt_next = td->qt_next; + ehci_free(td, sizeof(*td)); + td = (void *)swpl(qh->qh_overlay.qt_next); + if (td != (void *)QT_NEXT_TERMINATE) + td = (struct qTD *)(gehci.dma_offset + (uint32_t)td); + } + ehci_free(qh, sizeof(*qh)); + if (ehci_readl(&gehci.hcor->or_usbsts) & STS_HSE) /* Host System Error */ + { + unsigned short status = pci_read_config_word(gehci.handle, PCISR); + err("EHCI Host System Error, controller usb-%s disabled\r\n(SR:0x%04X%s%s%s%s%s%s)", + gehci.slot_name, status & 0xFFFF, status & 0x8000 ? ", Parity error" : "", + status & 0x4000 ? ", Signaled system error" : "", + status & 0x2000 ? ", Received master abort" : "", + status & 0x1000 ? ", Received target abort" : "", + status & 0x800 ? ", Signaled target abort" : "", + status & 0x100 ? ", Data parity error" : ""); + } + return -1; +} + +static inline int min3(int a, int b, int c) +{ + if (b < a) + a = b; + if (c < a) + a = c; + return a; +} + +static int ehci_submit_root(struct usb_device *dev, uint32_t pipe, void *buffer, int length, struct devrequest *req) +{ + uint8_t tmpbuf[4]; + u16 typeReq; + void *srcptr = NULL; + int len, srclen; + uint32_t reg; + uint32_t *status_reg; + + if (swpw(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) + { + err("the requested port(%d) is not configured\r\n", swpw(req->index) - 1); + return -1; + } + + status_reg = (uint32_t *) &gehci.hcor->or_portsc[swpw(req->index) - 1]; + srclen = 0; + dbg("ehci_submit_root req=%u (%#x), type=%u (%#x), value=%u, index=%u\r\n", + req->request, req->request, req->requesttype, req->requesttype, swpw(req->value), swpw(req->index)); + typeReq = req->request | req->requesttype << 8; + + switch(typeReq) + { + case DeviceRequest | USB_REQ_GET_DESCRIPTOR: + switch(swpw(req->value) >> 8) + { + case USB_DT_DEVICE: + dbg("USB_DT_DEVICE request\r\n"); + srcptr = &gehci.descriptor->device; + srclen = 0x12; + break; + + case USB_DT_CONFIG: + dbg("USB_DT_CONFIG config\r\n"); + srcptr = &gehci.descriptor->config; + srclen = 0x19; + break; + + case USB_DT_STRING: + dbg("USB_DT_STRING config\r\n"); + switch(swpw(req->value) & 0xff) + { + case 0: /* Language */ + srcptr = "\4\3\1\0"; + srclen = 4; + break; + + case 1: /* Vendor */ + srcptr = "\2\3"; + srclen = 2; + break; + + case 2: /* Product */ + srcptr = "\34\3E\0H\0C\0I\0 \0R\0o\0o\0t\0 \0H\0u\0b\0"; + srclen = 28; + break; + + default: + dbg("unknown value DT_STRING %x\r\n", + swpw(req->value)); + goto unknown; + } + break; + default: + dbg("unknown value %x\r\n", swpw(req->value)); + goto unknown; + } + break; + + case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8): + switch(swpw(req->value) >> 8) + { + case USB_DT_HUB: + dbg("USB_DT_HUB config\r\n"); + srcptr = &gehci.descriptor->hub; + srclen = 0x8; + break; + + default: + dbg("unknown value %x\r\n", swpw(req->value)); + goto unknown; + } + break; + + case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8): + dbg("USB_REQ_SET_ADDRESS\r\n"); + rootdev = swpw(req->value); + break; + + case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: + dbg("USB_REQ_SET_CONFIGURATION\r\n"); + /* Nothing to do */ + break; + + case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8): + tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */ + tmpbuf[1] = 0; + srcptr = tmpbuf; + srclen = 2; + break; + + case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): + memset(tmpbuf, 0, 4); + reg = ehci_readl(status_reg); + + if ((reg & EHCI_PS_PR) && (portreset & (1 << swpw(req->index)))) + { + int ret; + /* force reset to complete */ + reg = reg & ~(EHCI_PS_PR | EHCI_PS_CLEAR); + ehci_writel(status_reg, reg); + ret = handshake(status_reg, EHCI_PS_PR, 0, 2 * 1000); + if (!ret) + { + tmpbuf[0] |= USB_PORT_STAT_RESET; + reg = ehci_readl(status_reg); + } + else + err("port(%d) reset error", swpw(req->index) - 1); + } + + if (reg & EHCI_PS_CS) + tmpbuf[0] |= USB_PORT_STAT_CONNECTION; + if (reg & EHCI_PS_PE) + tmpbuf[0] |= USB_PORT_STAT_ENABLE; + if (reg & EHCI_PS_SUSP) + tmpbuf[0] |= USB_PORT_STAT_SUSPEND; + if (reg & EHCI_PS_OCA) + tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT; + if (reg & EHCI_PS_PP) + tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; + + tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; + + if (reg & EHCI_PS_CSC) + tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION; + if (reg & EHCI_PS_PEC) + tmpbuf[2] |= USB_PORT_STAT_C_ENABLE; + if (reg & EHCI_PS_OCC) + tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT; + if (portreset & (1 << swpw(req->index))) + tmpbuf[2] |= USB_PORT_STAT_C_RESET; + + srcptr = tmpbuf; + srclen = 4; + break; + + case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): + reg = ehci_readl(status_reg); + reg &= ~EHCI_PS_CLEAR; + switch(swpw(req->value)) + { + case USB_PORT_FEAT_ENABLE: + reg |= EHCI_PS_PE; + ehci_writel(status_reg, reg); + break; + + case USB_PORT_FEAT_POWER: + if (HCS_PPC(ehci_readl(&gehci.hccr->cr_hcsparams))) + { + reg |= EHCI_PS_PP; + ehci_writel(status_reg, reg); + } + break; + + case USB_PORT_FEAT_RESET: + if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS && EHCI_PS_IS_LOWSPEED(reg)) + { + /* Low speed device, give up ownership. */ + dbg("port %d low speed --> companion\r\n", swpw(req->index)); + reg |= EHCI_PS_PO; + ehci_writel(status_reg, reg); + companion |= (1 << swpw(req->index)); + break; + } + else + { + reg |= EHCI_PS_PR; + reg &= ~EHCI_PS_PE; + ehci_writel(status_reg, reg); + /* + * caller must wait, then call GetPortStatus + * usb 2.0 specification say 50 ms resets on root + */ + wait(50 * 1000); + portreset |= (1 << swpw(req->index)); + } + break; + + default: + dbg("unknown feature %x\r\n", swpw(req->value)); + goto unknown; + } + /* unblock posted writes */ + (void) ehci_readl(&gehci.hcor->or_usbcmd); + break; + + case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): + reg = ehci_readl(status_reg); + switch(swpw(req->value)) + { + case USB_PORT_FEAT_ENABLE: + reg &= ~EHCI_PS_PE; + break; + + case USB_PORT_FEAT_C_ENABLE: + reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE; + break; + + case USB_PORT_FEAT_POWER: + if (HCS_PPC(ehci_readl(&gehci.hccr->cr_hcsparams))) + reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP); + case USB_PORT_FEAT_C_CONNECTION: + reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC; + break; + + case USB_PORT_FEAT_OVER_CURRENT: + reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC; + break; + + case USB_PORT_FEAT_C_RESET: + portreset &= ~(1 << swpw(req->index)); + break; + + default: + dbg("unknown feature %x\r\n", swpw(req->value)); + goto unknown; + } + ehci_writel(status_reg, reg); + /* unblock posted write */ + (void) ehci_readl(&gehci.hcor->or_usbcmd); + break; + + default: + dbg("Unknown request\r\n"); + goto unknown; + } + wait(1 * 1000); + len = min3(srclen, swpw(req->length), length); + if (srcptr != NULL && len > 0) + memcpy(buffer, srcptr, len); + else + dbg("Len is 0\r\n"); + dev->act_len = len; + dev->status = 0; + return 0; +unknown: + dbg("Unknown: requesttype=%x, request=%x, value=%x, index=%x, length=%x\r\n", + req->requesttype, req->request, swpw(req->value), swpw(req->index), swpw(req->length)); + dev->act_len = 0; + dev->status = USB_ST_STALLED; + return -1; +} + +/* an interrupt happens */ +static int hc_interrupt(struct ehci *ehci) +{ + uint32_t status = ehci_readl(&ehci->hcor->or_usbsts); + + dbg("\r\n"); + + if (status & STS_PCD) /* port change detect */ + { + uint32_t reg = ehci_readl(&ehci->hccr->cr_hcsparams); + uint32_t i = HCS_N_PORTS(reg); + + while(i) + { + uint32_t pstatus = ehci_readl(&ehci->hcor->or_portsc[i-1]); + if (pstatus & EHCI_PS_PO) + { + i--; + continue; + } + + if (companion & (1 << i)) + { + /* Low speed device, give up ownership. */ + pstatus |= EHCI_PS_PO; + ehci_writel(&ehci->hcor->or_portsc[i - 1], pstatus); + } + i--; + } + } + ehci_writel(&ehci->hcor->or_usbsts, status); + + return 1; /* interrupt was from this card */ +} + +void ehci_usb_enable_interrupt(int enable) +{ + if (enable); +} + +static int handle_usb_interrupt(struct ehci *ehci) +{ + return hc_interrupt(ehci); +} + +static void hc_free_buffers(struct ehci *ehci) +{ + int i; + + if (ehci->descriptor != NULL) + { + driver_mem_free(ehci->descriptor); + ehci->descriptor = NULL; + } + + for (i = 0; i < 3; i++) + { + if (ehci->td_unaligned[i] != NULL) + { + driver_mem_free(ehci->td_unaligned[i]); + ehci->td_unaligned[i] = NULL; + } + } + + if (ehci->qh_unaligned != NULL) + { + driver_mem_free(ehci->qh_unaligned); + ehci->qh_unaligned = NULL; + } + + if (ehci->qh_list_unaligned != NULL) + { + driver_mem_free(ehci->qh_list_unaligned); + ehci->qh_list_unaligned = NULL; + } +} + +int ehci_usb_lowlevel_init(long handle, const struct pci_device_id *ent, void **priv) +{ + int i; + uint32_t reg; + uint32_t cmd; + uint32_t usb_base_addr = 0xFFFFFFFF; + struct pci_rd *pci_rsc_desc; + + pci_rsc_desc = pci_get_resource(handle); /* USB EHCI */ + if (handle && (ent != NULL)) + { + memset(&gehci, 0, sizeof(struct ehci)); + gehci.handle = handle; + gehci.ent = ent; + } + else if (!gehci.handle) /* for restart USB cmd */ + { + dbg("!gehci.handle\r\n"); + return -1; + } + + gehci.qh_list_unaligned = (struct QH *) driver_mem_alloc(sizeof(struct QH) + 32); + if (gehci.qh_list_unaligned == NULL) + { + dbg("QHs malloc failed\r\n"); + hc_free_buffers(&gehci); + return -1; + } + + gehci.qh_list = (struct QH *)(((uint32_t)gehci.qh_list_unaligned + 31) & ~31); + memset(gehci.qh_list, 0, sizeof(struct QH)); + gehci.qh_unaligned = (struct QH *)driver_mem_alloc(sizeof(struct QH) + 32); + + if (gehci.qh_unaligned == NULL) + { + dbg("QHs malloc failed\r\n"); + hc_free_buffers(&gehci); + + return -1; + } + gehci.qh = (struct QH *)(((uint32_t) gehci.qh_unaligned + 31) & ~31); + memset(gehci.qh, 0, sizeof(struct QH)); + + for (i = 0; i < 3; i++) + { + gehci.td_unaligned[i] = (struct qTD *) driver_mem_alloc(sizeof(struct qTD) + 32); + if (gehci.td_unaligned[i] == NULL) + { + dbg("TDs malloc failed\r\n"); + hc_free_buffers(&gehci); + + return -1; + } + gehci.td[i] = (struct qTD *)(((uint32_t) gehci.td_unaligned[i] + 31) & ~31); + memset(gehci.td[i], 0, sizeof(struct qTD)); + } + + gehci.descriptor = (struct descriptor *) driver_mem_alloc(sizeof(struct descriptor)); + if (gehci.descriptor == NULL) + { + dbg("decriptor malloc failed\r\n"); + hc_free_buffers(&gehci); + + return -1; + } + memcpy(gehci.descriptor, &rom_descriptor, sizeof(struct descriptor)); + + if ((long) pci_rsc_desc >= 0) + { + unsigned short flags; + do + { + dbg("PCI USB descriptors (at %p): flags 0x%04x start 0x%08lx \r\n offset 0x%08lx dmaoffset 0x%08lx length 0x%08lx\r\n", pci_rsc_desc, + pci_rsc_desc->flags, pci_rsc_desc->start, pci_rsc_desc->offset, pci_rsc_desc->dmaoffset, pci_rsc_desc->length); + if (!(pci_rsc_desc->flags & FLG_IO)) + { + if (usb_base_addr == 0xFFFFFFFF) + { + usb_base_addr = pci_rsc_desc->start; + gehci.hccr = (struct ehci_hccr *) (pci_rsc_desc->offset + pci_rsc_desc->start); + gehci.dma_offset = pci_rsc_desc->dmaoffset; + if ((pci_rsc_desc->flags & FLG_ENDMASK) == ORD_MOTOROLA) + gehci.big_endian = 0; /* host bridge make swapping intel -> motorola */ + else + gehci.big_endian = 1; /* driver must swapping intel -> motorola */ + } + } + flags = pci_rsc_desc->flags; + pci_rsc_desc = (struct pci_rd *)((uint32_t) pci_rsc_desc->next + (uint32_t) pci_rsc_desc); + } + while (!(flags & FLG_LAST)); + } + else + { + hc_free_buffers(&gehci); + dbg("pci_get_resource() error\r\n"); + + return -1; + } + + if (usb_base_addr == 0xFFFFFFFF) + { + hc_free_buffers(&gehci); + return(-1); + } + + if (handle && (ent != NULL)) + { + switch(ent->vendor) + { + case PCI_VENDOR_ID_NEC: gehci.slot_name = "uPD720101"; break; + case PCI_VENDOR_ID_PHILIPS: gehci.slot_name = "isp1561"; break; + default: gehci.slot_name = "generic"; break; + } + } + gehci.hcor = (struct ehci_hcor *)((uint32_t) gehci.hccr + HC_LENGTH(ehci_readl(&gehci.hccr->cr_capbase))); + xprintf("EHCI usb-%s, regs address 0x%08X, PCI handle 0x%X\r\n", gehci.slot_name, gehci.hccr, handle); + + /* EHCI spec section 4.1 */ + if (ehci_reset() != 0) + { + hc_free_buffers(&gehci); + + dbg("ehci_reset() failed\r\n"); + + return -1; + } + + /* Set head of reclaim list */ + gehci.qh_list->qh_link = swpl(((uint32_t) gehci.qh_list - gehci.dma_offset) | QH_LINK_TYPE_QH); + gehci.qh_list->qh_endpt1 = swpl((1 << 15) | (USB_SPEED_HIGH << 12)); + gehci.qh_list->qh_curtd = swpl(QT_NEXT_TERMINATE); + gehci.qh_list->qh_overlay.qt_next = swpl(QT_NEXT_TERMINATE); + gehci.qh_list->qh_overlay.qt_altnext = swpl(QT_NEXT_TERMINATE); + gehci.qh_list->qh_overlay.qt_token = swpl(0x40); + + /* Set async. queue head pointer. */ + ehci_writel(&gehci.hcor->or_asynclistaddr, (uint32_t) gehci.qh_list - gehci.dma_offset); + reg = ehci_readl(&gehci.hccr->cr_hcsparams); + gehci.descriptor->hub.bNbrPorts = HCS_N_PORTS(reg); + xprintf("Register %x NbrPorts %d\r\n", reg, gehci.descriptor->hub.bNbrPorts); + + /* Port Indicators */ + if (HCS_INDICATOR(reg)) + { + gehci.descriptor->hub.wHubCharacteristics |= 0x80; + } + + /* Port Power Control */ + if (HCS_PPC(reg)) + { + gehci.descriptor->hub.wHubCharacteristics |= 0x01; + } + + /* Start the host controller. */ + cmd = ehci_readl(&gehci.hcor->or_usbcmd); + + /* + * Philips, Intel, and maybe others need CMD_RUN before the + * root hub will detect new devices (why?); NEC doesn't + */ + cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); + cmd |= CMD_RUN; + ehci_writel(&gehci.hcor->or_usbcmd, cmd); + + /* take control over the ports */ + ehci_writel(&gehci.hcor->or_configflag, FLAG_CF); + + /* unblock posted write */ + cmd = ehci_readl(&gehci.hcor->or_usbcmd); + wait(5 * 1000); + + reg = HC_VERSION(ehci_readl(&gehci.hccr->cr_capbase)); + xprintf("USB EHCI host controller version %x.%02x\r\n", reg >> 8, reg & 0xff); + + /* turn on interrupts */ + pci_hook_interrupt(handle, handle_usb_interrupt, &gehci); + ehci_writel(&gehci.hcor->or_usbintr, INTR_PCDE); + + rootdev = 0; + if (priv != NULL) + { + *priv = (void *) &gehci; + } + ehci_inited = 1; + + return 0; +} + +int ehci_usb_lowlevel_stop(void *priv) +{ + uint32_t cmd; + + if (priv); + if (!ehci_inited) + return(0); + + /* turn off interrupts */ + ehci_writel(&gehci.hcor->or_usbintr, 0); + pci_unhook_interrupt(gehci.handle); + + /* stop the controller */ + cmd = ehci_readl(&gehci.hcor->or_usbcmd); + cmd &= ~CMD_RUN; + ehci_writel(&gehci.hcor->or_usbcmd, cmd); + + /* turn off all ports => todo */ + /* use the companions */ + ehci_writel(&gehci.hcor->or_configflag, 0); + + /* unblock posted write */ + cmd = ehci_readl(&gehci.hcor->or_usbcmd); + ehci_reset(); + hc_free_buffers(&gehci); + ehci_inited = 0; + return(0); +} + +int ehci_submit_bulk_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int length) +{ + if (usb_pipetype(pipe) != PIPE_BULK) + { + dbg("non-bulk pipe (type=%lu)", usb_pipetype(pipe)); + return -1; + } + return ehci_submit_async(dev, pipe, buffer, length, NULL); +} + +int ehci_submit_control_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int length, struct devrequest *setup) +{ + if (usb_pipetype(pipe) != PIPE_CONTROL) + { + dbg("non-control pipe (type=%lu)", usb_pipetype(pipe)); + return -1; + } + + if (usb_pipedevice(pipe) == rootdev) + { + if (rootdev == 0) + dev->speed = USB_SPEED_HIGH; + return ehci_submit_root(dev, pipe, buffer, length, setup); + } + return ehci_submit_async(dev, pipe, buffer, length, setup); +} + +int ehci_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int length, int interval) +{ + dbg("submit_int_msg dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d", dev, pipe, buffer, length, interval); + return -1; +} + diff --git a/pci/ohci-hcd.c b/pci/ohci-hcd.c new file mode 100644 index 0000000..3f635b2 --- /dev/null +++ b/pci/ohci-hcd.c @@ -0,0 +1,2380 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB and PCI bus. + * + * Interrupt support is added. Now, it has been tested + * on ULI1575.cpu and works well with USB keyboard. + * + * (C) Copyright 2007 + * Zhang Wei, Freescale Semiconductor, Inc. + * + * (C) Copyright 2003 + * Gary Jennejohn, DENX Software Engineering + * + * Note: Much of this code has been derived from Linux 2.4 + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2002 David Brownell + * + * Modified for the MP2USB by (C) Copyright 2005 Eric Benard + * ebenard@eukrea.com - based on s3c24x0's driver + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +/* + * IMPORTANT NOTE + * this driver is intended for use with USB Mass Storage Devices + * (BBB) and USB keyboard. There is NO support for Isochronous pipes! + */ + + +#include "wait.h" /* for wait_ms routines */ +#include "bas_printf.h" +#include "bas_string.h" /* for memset() */ +#include "pci.h" +#include "interrupts.h" + +// #define DEBUG +#include "debug.h" + +#undef OHCI_USE_NPS /* force NoPowerSwitching mode */ + +#undef OHCI_VERBOSE_DEBUG /* not always helpful */ +#undef OHCI_FILL_TRACE + +#include "usb.h" +#include "ohci.h" +#include "util.h" /* for endian conversions */ + +/* For initializing controller (mask in an HCFS mode too) */ +#define OHCI_CONTROL_INIT (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE + +/* + * e.g. PCI controllers need this + */ + +#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS +#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS + +/* + * do a longword read from addr and byteswap the result + */ +static inline uint32_t readl(volatile uint32_t *addr) +{ + uint32_t res; + + res = swpl(*addr); + //chip_errata_135(); + //dbg("reading from 0x%08x = 0x%08x\r\n", addr, res); + return res; +} + +/* + * byteswap value and write it to address + */ +static inline void writel(uint32_t value, volatile uint32_t *address) +{ + // dbg("writing %08x to %08x\r\n", value, address); + * (volatile uint32_t *) address = swpl(value); +} +#else +/* +#define readl(a) (*((volatile uint32_t *)(a))) +#define writel(a, b) (*((volatile uint32_t *)(b)) = ((volatile uint32_t)a)) +*/ +#error CONFIG_SYS_OHCI_SWAP_REG_ACESS must be defined +#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */ + +#define min_t(type, x, y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) + +struct pci_device_id ohci_usb_pci_table[] = +{ +{ + PCI_VENDOR_ID_AL, + PCI_DEVICE_ID_AL_M5237, + PCI_ANY_ID, + PCI_ANY_ID, + PCI_CLASS_SERIAL_USB_OHCI, + 0, + 0 +}, /* ULI1575 PCI OHCI module ids */ +{ + PCI_VENDOR_ID_NEC, + PCI_DEVICE_ID_NEC_USB, + PCI_ANY_ID, + PCI_ANY_ID, + PCI_CLASS_SERIAL_USB_OHCI, + 0, + 0 +}, /* NEC PCI OHCI module ids */ +{ + PCI_VENDOR_ID_NEC, + PCI_DEVICE_ID_NEC_USB_A, + PCI_ANY_ID, + PCI_ANY_ID, + PCI_CLASS_SERIAL_USB_OHCI, + 0, + 0 +}, /* NEC PCI OHCI module ids */ +{ + PCI_VENDOR_ID_PHILIPS, + PCI_DEVICE_ID_PHILIPS_ISP1561, + PCI_ANY_ID, + PCI_ANY_ID, + PCI_CLASS_SERIAL_USB_OHCI, + 0, + 0 +}, /* Philips 1561 PCI OHCI module ids */ +/* Please add supported PCI OHCI controller ids here */ +{ + 0, + 0, + 0, + 0, + 0, + 0, + 0 +} +}; + +/* global ohci_t */ +static ohci_t gohci[10]; +int ohci_inited; + +static inline uint32_t roothub_a(volatile ohci_t *ohci) { return readl(&ohci->regs->roothub.a); } +static inline uint32_t roothub_b(volatile ohci_t *ohci) { return readl(&ohci->regs->roothub.b); } +static inline uint32_t roothub_status(volatile ohci_t *ohci) { return readl(&ohci->regs->roothub.status); } +static inline uint32_t roothub_portstatus(volatile ohci_t *ohci, int i) { return readl(&ohci->regs->roothub.portstatus[i]); } + +/* forward declaration */ +static int hc_interrupt(volatile ohci_t *ohci); +static void td_submit_job(volatile ohci_t *ohci, struct usb_device *dev, uint32_t pipe, + void *buffer, int transfer_len, struct devrequest *setup, + volatile urb_priv_t *urb, int interval); + + +static struct td *ptd; + +/* TDs ... */ +static struct td *td_alloc(struct usb_device *usb_dev) +{ + int i; + struct td *td; + + td = NULL; + + for (i = 0; i < NUM_TD; i++) + { + if (ptd[i].usb_dev == NULL) + { + td = &ptd[i]; + td->usb_dev = usb_dev; + break; + } + } + return td; +} + +/*-------------------------------------------------------------------------* + * URB support functions + *-------------------------------------------------------------------------*/ + +/* free HCD-private data associated with this URB */ + +static void urb_free_priv(volatile urb_priv_t *urb) +{ + int i; + struct td *td; + int last = urb->length - 1; + + if (last >= 0) + { + for (i = 0; i <= last; i++) + { + td = urb->td[i]; + if (td) + { + td->usb_dev = NULL; + urb->td[i] = NULL; + } + } + } + /* FIXME: driver_mem_free(urb); */ +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG_OHCI +static int sohci_get_current_frame_number(ohci_t *ohci, struct usb_device *dev); + +/* debug| print the main components of an URB + * small: 0) header + data packets 1) just header */ + +static void pkt_print(ohci_t *ohci, urb_priv_t *purb, struct usb_device *dev, + uint32_t pipe, void *buffer, int transfer_len, + struct devrequest *setup, char *str, int small) +{ + dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx\r\n", + str, + sohci_get_current_frame_number(ohci, dev), + usb_pipedevice(pipe), + usb_pipeendpoint(pipe), + usb_pipeout(pipe)? 'O': 'I', + usb_pipetype(pipe) < 2 ? \ + (usb_pipeint(pipe)? "INTR": "ISOC"): \ + (usb_pipecontrol(pipe)? "CTRL": "BULK"), + (purb ? purb->actual_length : 0), + transfer_len, dev->status); +#ifdef OHCI_VERBOSE_DEBUG + if (!small) + { + int i; + int len; + + if (usb_pipecontrol(pipe)) + { + dbg(__FILE__ ": cmd(8):"); + for (i = 0; i < 8 ; i++) + dbg(" %02x", ((uint8_t *)setup)[i]); + dbg("\r\n"); + } + + if (transfer_len > 0 && buffer) + { + dbg(__FILE__ ": data(%d/%d):", (purb ? purb->actual_length : 0), transfer_len); + len = usb_pipeout(pipe)? transfer_len : (purb ? purb->actual_length : 0); + + for (i = 0; i < 16 && i < len; i++) + dbg(" %02x", ((uint8_t *)buffer)[i]); + dbg("%s\r\n", i < len? "...": ""); + } + } +#endif +} + +/* + * just for debugging; prints non-empty branches of the int ed tree + * inclusive iso eds + */ +static void ep_print_int_eds(ohci_t *ohci, char *str) +{ + int i, j; + uint32_t *ed_p; + + for (i = 0; i < 32; i++) + { + j = 5; + ed_p = &(ohci->hcca->int_table[i]); + if (*ed_p == 0) + continue; + + dbg("%s branch int %2d(%2x):\r\n", str, i, i); + while (*ed_p != 0 && j--) + { + ed_t *ed = (ed_t *) swpl((uint32_t) ed_p); + dbg(" ed: %4x;", ed->hwINFO); + ed_p = &ed->hwNextED; + } + dbg("\r\n"); + } +} + +static void ohci_dump_intr_mask(char *label, uint32_t mask) +{ + dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s\r\n", + label, + mask, + (mask & OHCI_INTR_MIE) ? " MIE" : "", + (mask & OHCI_INTR_OC) ? " OC" : "", + (mask & OHCI_INTR_RHSC) ? " RHSC" : "", + (mask & OHCI_INTR_FNO) ? " FNO" : "", + (mask & OHCI_INTR_UE) ? " UE" : "", + (mask & OHCI_INTR_RD) ? " RD" : "", + (mask & OHCI_INTR_SF) ? " SF" : "", + (mask & OHCI_INTR_WDH) ? " WDH" : "", + (mask & OHCI_INTR_SO) ? " SO" : "" + ); +} + +static void maybe_print_eds(ohci_t *controller, char *label, uint32_t value) +{ + ed_t *edp; + + value += controller->dma_offset; + edp = (ed_t *) value; + (void) edp; + + if (value && (value < 0xDFFFF0)) /* STRAM */ + { + dbg("%s %08x\r\n", label, value); + dbg("%08x\r\n", edp->hwINFO); + dbg("%08x\r\n", edp->hwTailP); + dbg("%08x\r\n", edp->hwHeadP); + dbg("%08x\r\n", edp->hwNextED); + } +} + +static char *hcfs2string(int state) +{ + switch (state) + { + case OHCI_USB_RESET: return "reset"; + case OHCI_USB_RESUME: return "resume"; + case OHCI_USB_OPER: return "operational"; + case OHCI_USB_SUSPEND: return "suspend"; + } + return "?"; +} + +/* dump control and status registers */ +static void ohci_dump_status(ohci_t *controller) +{ + struct ohci_regs *regs = controller->regs; + uint32_t temp = readl(®s->revision) & 0xff; + + if (temp != 0x10) + dbg("spec %d.%d\r\n", (temp >> 4), (temp & 0x0f)); + + temp = readl(®s->control); + dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d\r\n", temp, + (temp & OHCI_CTRL_RWE) ? " RWE" : "", + (temp & OHCI_CTRL_RWC) ? " RWC" : "", + (temp & OHCI_CTRL_IR) ? " IR" : "", + hcfs2string(temp & OHCI_CTRL_HCFS), + (temp & OHCI_CTRL_BLE) ? " BLE" : "", + (temp & OHCI_CTRL_CLE) ? " CLE" : "", + (temp & OHCI_CTRL_IE) ? " IE" : "", + (temp & OHCI_CTRL_PLE) ? " PLE" : "", + temp & OHCI_CTRL_CBSR + ); + + temp = readl(®s->cmdstatus); + dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s\r\n", temp, + (temp & OHCI_SOC) >> 16, + (temp & OHCI_OCR) ? " OCR" : "", + (temp & OHCI_BLF) ? " BLF" : "", + (temp & OHCI_CLF) ? " CLF" : "", + (temp & OHCI_HCR) ? " HCR" : "" + ); + ohci_dump_intr_mask("intrstatus", readl(®s->intrstatus)); + ohci_dump_intr_mask("intrenable", readl(®s->intrenable)); + maybe_print_eds(controller, "ed_periodcurrent", readl(®s->ed_periodcurrent)); + maybe_print_eds(controller, "ed_controlhead", readl(®s->ed_controlhead)); + maybe_print_eds(controller, "ed_controlcurrent", readl(®s->ed_controlcurrent)); + maybe_print_eds(controller, "ed_bulkhead", readl(®s->ed_bulkhead)); + maybe_print_eds(controller, "ed_bulkcurrent", readl(®s->ed_bulkcurrent)); + maybe_print_eds(controller, "donehead", readl(®s->donehead)); +} + +static void ohci_dump_roothub(ohci_t *controller, int verbose) +{ + uint32_t temp; + uint32_t ndp; + uint32_t i; + + temp = roothub_a(controller); + (void) temp; + + // ndp = (temp & RH_A_NDP); + ndp = controller->ndp; + if (verbose) + { + dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d\r\n", temp, + ((temp & RH_A_POTPGT) >> 24) & 0xff, + (temp & RH_A_NOCP) ? " NOCP" : "", + (temp & RH_A_OCPM) ? " OCPM" : "", + (temp & RH_A_DT) ? " DT" : "", + (temp & RH_A_NPS) ? " NPS" : "", + (temp & RH_A_PSM) ? " PSM" : "", + ndp + ); + temp = roothub_b(controller); + dbg("roothub.b: %08x PPCM=%04x DR=%04x\r\n", + temp, + (temp & RH_B_PPCM) >> 16, + (temp & RH_B_DR) + ); + temp = roothub_status(controller); + dbg("roothub.status: %08x%s%s%s%s%s%s\r\n", + temp, + (temp & RH_HS_CRWE) ? " CRWE" : "", + (temp & RH_HS_OCIC) ? " OCIC" : "", + (temp & RH_HS_LPSC) ? " LPSC" : "", + (temp & RH_HS_DRWE) ? " DRWE" : "", + (temp & RH_HS_OCI) ? " OCI" : "", + (temp & RH_HS_LPS) ? " LPS" : "" + ); + } + + for (i = 0; i < ndp; i++) + { + temp = roothub_portstatus(controller, i); + dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s\r\n", + i, + temp, + (temp & RH_PS_PRSC) ? " PRSC" : "", + (temp & RH_PS_OCIC) ? " OCIC" : "", + (temp & RH_PS_PSSC) ? " PSSC" : "", + (temp & RH_PS_PESC) ? " PESC" : "", + (temp & RH_PS_CSC) ? " CSC" : "", + + (temp & RH_PS_LSDA) ? " LSDA" : "", + (temp & RH_PS_PPS) ? " PPS" : "", + (temp & RH_PS_PRS) ? " PRS" : "", + (temp & RH_PS_POCI) ? " POCI" : "", + (temp & RH_PS_PSS) ? " PSS" : "", + + (temp & RH_PS_PES) ? " PES" : "", + (temp & RH_PS_CCS) ? " CCS" : "" + ); + } +} + +static void ohci_dump(ohci_t *ohci, int verbose) +{ + dbg("OHCI controller usb-%s-%c state\r\n", ohci->slot_name, (char)ohci->controller + '0'); + /* dumps some of the state we know about */ + ohci_dump_status(ohci); + if (verbose) + ep_print_int_eds(ohci, "hcca"); + dbg("hcca frame #%04x\r\n", ohci->hcca->frame_no); + ohci_dump_roothub(ohci, 1); +} +#endif /* DEBUG_OHCI */ + +/* + * Interface functions (URB) + */ + +/* get a transfer request */ + +static int sohci_submit_job(volatile ohci_t *ohci, volatile urb_priv_t *urb, struct devrequest *setup) +{ + volatile ed_t *ed; + volatile urb_priv_t *purb_priv = urb; + int i; + int size = 0; + struct usb_device *dev = urb->dev; + uint32_t pipe = urb->pipe; + void *buffer = urb->transfer_buffer; + int transfer_len = urb->transfer_buffer_length; + int interval = urb->interval; + + /* + * when controller's hung, permit only roothub cleanup attempts + * such as powering down ports + */ + if (ohci->disabled) + { + urb_free_priv(purb_priv); // added + err("sohci_submit_job: EPIPE\r\n"); + + return -1; + } + + /* + * we're about to begin a new transaction here so mark the + * URB unfinished + */ + urb->finished = 0; + + /* every endpoint has an ed, locate and fill it */ + ed = ep_add_ed(ohci, dev, pipe, interval, 1); + if (!ed) + { + urb_free_priv(purb_priv); // added + err("sohci_submit_job: ENOMEM"); + return -1; + } + + /* for the private part of the URB we need the number of TDs (size) */ + switch (usb_pipetype(pipe)) + { + case PIPE_BULK: /* one TD for every 4096 Byte */ + size = (transfer_len - 1) / 4096 + 1; + break; + + case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ + size = (transfer_len == 0) ? 2 : (transfer_len - 1) / 4096 + 3; + break; + + case PIPE_INTERRUPT: /* 1 TD */ + size = 1; + break; + } + ed->purb = urb; + if (size >= (N_URB_TD - 1)) + { + urb_free_priv(purb_priv); // added + err("need %d TDs, only have %d", size, N_URB_TD); + return -1; + } + purb_priv->pipe = pipe; + + /* fill the private part of the URB */ + purb_priv->length = size; + purb_priv->ed = ed; + purb_priv->actual_length = 0; + + /* allocate the TDs */ + /* note that td[0] was allocated in ep_add_ed */ + for (i = 0; i < size; i++) + { + purb_priv->td[i] = td_alloc(dev); + if (!purb_priv->td[i]) + { + purb_priv->length = i; + urb_free_priv(purb_priv); + err("sohci_submit_job: ENOMEM\r\n"); + return -1; + } + } + + if (ed->state == ED_NEW || (ed->state & ED_DEL)) + { + urb_free_priv(purb_priv); + err("sohci_submit_job: EINVAL\r\n"); + return -1; + } + + /* link the ed into a chain if is not already */ + if (ed->state != ED_OPER) + { + ep_link(ohci, ed); + } + + /* fill the TDs and link it to the ed */ + td_submit_job(ohci, dev, pipe, buffer, transfer_len, setup, purb_priv, interval); + + return 0; +} + +static inline int sohci_return_job(volatile ohci_t *ohci, volatile urb_priv_t *urb) +{ + volatile struct ohci_regs *regs = ohci->regs; + + switch (usb_pipetype(urb->pipe)) + { + case PIPE_INTERRUPT: + /* implicitly requeued */ + if ((urb->dev->irq_handle != NULL) && (urb->dev->irq_act_len = urb->actual_length)) + { + writel(OHCI_INTR_WDH, ®s->intrenable); + readl(®s->intrenable); /* PCI posting flush */ + + /* call interrupt device routine */ + dbg("irq_handle device %d", urb->dev->devnum); + urb->dev->irq_handle(urb->dev); + + writel(OHCI_INTR_WDH, ®s->intrdisable); + readl(®s->intrdisable); /* PCI posting flush */ + } + urb->actual_length = 0; + td_submit_job(ohci, urb->dev, urb->pipe, urb->transfer_buffer, urb->transfer_buffer_length, NULL, urb, urb->interval); + break; + + case PIPE_CONTROL: + case PIPE_BULK: + break; + + default: + return 0; + } + return 1; +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG_OHCI +/* tell us the current USB frame number */ + +static int sohci_get_current_frame_number(ohci_t *ohci, struct usb_device *usb_dev) +{ + return swpw(ohci->hcca->frame_no); +} +#endif + +/*-------------------------------------------------------------------------* + * ED handling functions + *-------------------------------------------------------------------------*/ + +/* + * search for the right branch to insert an interrupt ed into the int tree + * do some load balancing; + * returns the branch and + * sets the interval to interval = 2^integer (ld (interval)) + */ + +static int ep_int_balance(volatile ohci_t *ohci, int interval, int load) +{ + int i; + int branch = 0; + + /* + * search for the least loaded interrupt endpoint + * branch of all 32 branches + */ + for (i = 0; i < 32; i++) + { + if (ohci->ohci_int_load[branch] > ohci->ohci_int_load[i]) + branch = i; + } + branch = branch % interval; + for (i = branch; i < 32; i += interval) + ohci->ohci_int_load[i] += load; + return branch; +} + +/*-------------------------------------------------------------------------*/ + +/* 2^int( ld (inter)) */ + +static int ep_2_n_interval(int inter) +{ + int i; + + for (i = 0; ((inter >> i) > 1) && (i < 5); i++); + return 1 << i; +} + +/*-------------------------------------------------------------------------*/ + +/* + * the int tree is a binary tree + * in order to process it sequentially the indexes of the branches have to + * be mapped the mapping reverses the bits of a word of num_bits length + */ +static int ep_rev(int num_bits, int word) +{ + int i; + int wout = 0; + + for (i = 0; i < num_bits; i++) + wout |= (((word >> i) & 1) << (num_bits - i - 1)); + + return wout; +} + +/*-------------------------------------------------------------------------* + * ED handling functions + *-------------------------------------------------------------------------*/ + +/* link an ed into one of the HC chains */ + +static int ep_link(volatile ohci_t *ohci, volatile ed_t *edi) +{ + volatile ed_t *ed = edi; + int int_branch; + int i; + int inter; + int interval; + int load; + volatile uint32_t *ed_p; + + ed->state = ED_OPER; + ed->int_interval = 0; + switch (ed->type) + { + case PIPE_CONTROL: + ed->hwNextED = 0; + if (ohci->ed_controltail == NULL) + writel((uint32_t) ed - ohci->dma_offset, &ohci->regs->ed_controlhead); + else + ohci->ed_controltail->hwNextED = swpl((uint32_t)ed - ohci->dma_offset); + + ed->ed_prev = ohci->ed_controltail; + if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && !ohci->ed_rm_list[1] && !ohci->sleeping) + { + ohci->hc_control |= OHCI_CTRL_CLE; + writel(ohci->hc_control, &ohci->regs->control); + } + ohci->ed_controltail = edi; + break; + + case PIPE_BULK: + ed->hwNextED = 0; + if (ohci->ed_bulktail == NULL) + writel((uint32_t) ed - ohci->dma_offset, &ohci->regs->ed_bulkhead); + else + ohci->ed_bulktail->hwNextED = swpl((uint32_t)ed - ohci->dma_offset); + ed->ed_prev = ohci->ed_bulktail; + if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && !ohci->ed_rm_list[1] && !ohci->sleeping) + { + ohci->hc_control |= OHCI_CTRL_BLE; + writel(ohci->hc_control, &ohci->regs->control); + } + ohci->ed_bulktail = edi; + break; + + case PIPE_INTERRUPT: + load = ed->int_load; + interval = ep_2_n_interval(ed->int_period); + ed->int_interval = interval; + int_branch = ep_int_balance(ohci, interval, load); + ed->int_branch = int_branch; + for (i = 0; i < ep_rev(6, interval); i += inter) + { + inter = 1; + for (ed_p = &(ohci->hcca->int_table[ep_rev(5, i) + int_branch]); + (*ed_p != 0) && (((volatile ed_t *)ed_p)->int_interval >= interval); + ed_p = &(((ed_t *)ed_p)->hwNextED)) + inter = ep_rev(6, ((ed_t *)ed_p)->int_interval); + ed->hwNextED = *ed_p; + *ed_p = swpl((uint32_t)ed - ohci->dma_offset); + } + break; + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* scan the periodic table to find and unlink this ED */ +static void periodic_unlink(volatile struct ohci *ohci, volatile struct ed *ed, unsigned index, unsigned period) +{ + for ( ;index < NUM_INTS; index += period) + { + volatile uint32_t *ed_p = &ohci->hcca->int_table[index]; + + /* ED might have been unlinked through another path */ + while (*ed_p != 0) + { + if ((uint32_t)*ed_p == swpl((uint32_t)ed - ohci->dma_offset)) /* changed */ + { + *ed_p = ed->hwNextED; + break; + } + ed_p = &(((struct ed *)ed_p)->hwNextED); /* changed */ + } + } +} + +/* + * unlink an ed from one of the HC chains. + * just the link to the ed is unlinked. + * the link from the ed still points to another operational ed or 0 + * so the HC can eventually finish the processing of the unlinked ed + */ + +static int ep_unlink(volatile ohci_t *ohci, volatile ed_t *edi) +{ + volatile ed_t *ed = edi; + int i; + + ed->hwINFO |= swpl(OHCI_ED_SKIP); + switch (ed->type) + { + case PIPE_CONTROL: + if (ed->ed_prev == NULL) + { + if (!ed->hwNextED) + { + ohci->hc_control &= ~OHCI_CTRL_CLE; + writel(ohci->hc_control, &ohci->regs->control); + } + writel(swpl(*((uint32_t *)&ed->hwNextED)), &ohci->regs->ed_controlhead); + } + else + ed->ed_prev->hwNextED = ed->hwNextED; + if (ohci->ed_controltail == ed) + ohci->ed_controltail = ed->ed_prev; + else + ((ed_t *)(swpl(*((uint32_t *)&ed->hwNextED)) + ohci->dma_offset))->ed_prev = ed->ed_prev; + break; + + case PIPE_BULK: + if (ed->ed_prev == NULL) + { + if (!ed->hwNextED) + { + ohci->hc_control &= ~OHCI_CTRL_BLE; + writel(ohci->hc_control, &ohci->regs->control); + } + writel(swpl(*((uint32_t *) &ed->hwNextED)), &ohci->regs->ed_bulkhead); + } + else + ed->ed_prev->hwNextED = ed->hwNextED; + + if (ohci->ed_bulktail == ed) + ohci->ed_bulktail = ed->ed_prev; + else + ((ed_t *)(swpl(*((uint32_t *) &ed->hwNextED)) + ohci->dma_offset))->ed_prev = ed->ed_prev; + break; + + case PIPE_INTERRUPT: + periodic_unlink(ohci, ed, 0, 1); + for (i = ed->int_branch; i < 32; i += ed->int_interval) + ohci->ohci_int_load[i] -= ed->int_load; + break; + } + ed->state = ED_UNLINK; + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* + * add/reinit an endpoint; this should be done once at the + * usb_set_configuration command, but the USB stack is a little bit + * stateless so we do it at every transaction if the state of the ed + * is ED_NEW then a dummy td is added and the state is changed to + * ED_UNLINK in all other cases the state is left unchanged the ed + * info fields are setted anyway even though most of them should not + * change + */ +static ed_t *ep_add_ed(volatile ohci_t *ohci, struct usb_device *usb_dev, uint32_t pipe, int interval, int load) +{ + td_t *td; + ed_t *ed_ret; + volatile ed_t *ed; + struct ohci_device *ohci_dev = ohci->ohci_dev; + + ed = ed_ret = &ohci_dev->ed[(usb_pipeendpoint(pipe) << 1) | (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))]; + if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) + { + err("ep_add_ed: pending delete"); + /* pending delete request */ + return NULL; + } + + if (ed->state == ED_NEW) + { + /* dummy td; end of td list for ed */ + td = td_alloc(usb_dev); + ed->hwTailP = swpl((uint32_t)td - ohci->dma_offset); + ed->hwHeadP = ed->hwTailP; + ed->state = ED_UNLINK; + ed->type = usb_pipetype(pipe); + ohci_dev->ed_cnt++; + } + + ed->hwINFO = swpl(usb_pipedevice(pipe) + | usb_pipeendpoint(pipe) << 7 + | (usb_pipeisoc(pipe)? 0x8000: 0) + | (usb_pipecontrol(pipe)? 0: (usb_pipeout(pipe)? 0x800: 0x1000)) + | usb_pipeslow(pipe) << 13 + | usb_maxpacket(usb_dev, pipe) << 16); + + if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) + { + ed->int_period = interval; + ed->int_load = load; + } + return ed_ret; +} + +/*-------------------------------------------------------------------------* + * TD handling functions + *-------------------------------------------------------------------------*/ + +/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ + +static void td_fill(volatile ohci_t *ohci, unsigned int info, void *data, int len, + struct usb_device *dev, int index, volatile urb_priv_t *urb_priv) +{ + volatile td_t *td; + volatile td_t *td_pt; + +#ifdef OHCI_FILL_TRACE + int i; +#endif + if (index > urb_priv->length) + { + err("index > length"); + return; + } + /* use this td as the next dummy */ + td_pt = urb_priv->td[index]; + td_pt->hwNextTD = 0; + + /* fill the old dummy TD */ + td = urb_priv->td[index] = (td_t *)((swpl(urb_priv->ed->hwTailP) & ~0xf) + ohci->dma_offset); + td->ed = urb_priv->ed; + td->next_dl_td = NULL; + td->index = index; + td->data = (uint32_t)data; +#ifdef OHCI_FILL_TRACE + if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) + { + for (i = 0; i < len; i++) + dbg("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]); + dbg("\r\n"); + } +#endif + if (!len) + data = NULL; + td->hwINFO = swpl(info); + if (data != NULL) + { + td->hwCBP = swpl((uint32_t)data - ohci->dma_offset); + td->hwBE = swpl((uint32_t)(data + len - 1 - ohci->dma_offset)); + } + else + { + td->hwCBP = 0; + td->hwBE = 0; + } + td->hwNextTD = swpl((uint32_t)td_pt - ohci->dma_offset); + /* append to queue */ + td->ed->hwTailP = td->hwNextTD; + +#if 0 + if (data) + { + int i; + dbg("td_fill: %08x %08x %08X %08X at 0x%08X\r\n", + swpl(td->hwINFO), swpl(td->hwCBP), swpl(td->hwNextTD), swpl(td->hwBE), td); + for (i = 0; i < len; i++) + dbg("%02X ", *(unsigned char *)(data + i) & 0xff); + dbg("\r\n"); + } + else + dbg("td_fill: %08x %08x %08X %08X at 0x%08X\r\n", + swpl(td->hwINFO), swpl(td->hwCBP), swpl(td->hwNextTD), swpl(td->hwBE), td); +#endif +} + +/*-------------------------------------------------------------------------*/ + +/* prepare all TDs of a transfer */ + +static void td_submit_job(volatile ohci_t *ohci, struct usb_device *dev, uint32_t pipe, + void *buffer, int transfer_len, struct devrequest *setup, + volatile urb_priv_t *urb, int interval) +{ + int data_len = transfer_len; + void *data; + int cnt = 0; + uint32_t info = 0; + unsigned int toggle = 0; + + /* OHCI handles the DATA-toggles itself, we just use the USB-toggle + * bits for reseting */ + if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) + toggle = TD_T_TOGGLE; + else + { + toggle = TD_T_DATA0; + usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); + } + + urb->td_cnt = 0; + if (data_len) + data = buffer; + else + data = NULL; + + switch (usb_pipetype(pipe)) + { + case PIPE_BULK: + info = usb_pipeout(pipe) ? TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; + while (data_len > 4096) + { + td_fill(ohci, info | (cnt? TD_T_TOGGLE : toggle), data, 4096, dev, cnt, urb); + data += 4096; data_len -= 4096; cnt++; + } + info = usb_pipeout(pipe) ? TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; + td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); + cnt++; + if (!ohci->sleeping) /* start bulk list */ + writel(OHCI_BLF, &ohci->regs->cmdstatus); + break; + + case PIPE_CONTROL: + /* Setup phase */ + info = TD_CC | TD_DP_SETUP | TD_T_DATA0; + td_fill(ohci, info, setup, 8, dev, cnt++, urb); + /* Optional Data phase */ + if (data_len > 0) + { + info = usb_pipeout(pipe) ? TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; + /* NOTE: mishandles transfers >8K, some >4K */ + td_fill(ohci, info, data, data_len, dev, cnt++, urb); + } + /* Status phase */ + info = usb_pipeout(pipe) ? TD_CC | TD_DP_IN | TD_T_DATA1 : TD_CC | TD_DP_OUT | TD_T_DATA1; + td_fill(ohci, info, data, 0, dev, cnt++, urb); + if (!ohci->sleeping) /* start Control list */ + writel(OHCI_CLF, &ohci->regs->cmdstatus); + break; + + case PIPE_INTERRUPT: + info = usb_pipeout(urb->pipe) ? TD_CC | TD_DP_OUT | toggle : TD_CC | TD_R | TD_DP_IN | toggle; + td_fill(ohci, info, data, data_len, dev, cnt++, urb); + break; + } + if (urb->length != cnt) + dbg("TD LENGTH %d != CNT %d", urb->length, cnt); +} + +/*-------------------------------------------------------------------------* + * Done List handling functions + *-------------------------------------------------------------------------*/ + +/* calculate the transfer length and update the urb */ + +static void dl_transfer_length(volatile ohci_t *ohci, volatile td_t *td) +{ + uint32_t tdBE; + uint32_t tdCBP; + + volatile urb_priv_t *lurb_priv = td->ed->purb; + + tdBE = swpl(td->hwBE); + tdCBP = swpl(td->hwCBP); + + if (tdBE) + tdBE += ohci->dma_offset; + if (tdCBP) + tdCBP += ohci->dma_offset; + + if (!(usb_pipecontrol(lurb_priv->pipe) && ((td->index == 0) || (td->index == lurb_priv->length - 1)))) + { + if (tdBE != 0) + { + if (td->hwCBP == 0) + lurb_priv->actual_length += (tdBE - td->data + 1); + else + lurb_priv->actual_length += (tdCBP - td->data); + } + } +} + +/*-------------------------------------------------------------------------*/ +static void check_status(volatile ohci_t *ohci, td_t *td_list) +{ + volatile urb_priv_t *lurb_priv = td_list->ed->purb; + int urb_len = lurb_priv->length; + volatile uint32_t *phwHeadP = &td_list->ed->hwHeadP; + int cc = TD_CC_GET(swpl(td_list->hwINFO)); + + if (cc) + { + err("OHCI usb-%s-%c error: %s (%x)\r\n", ohci->slot_name, (char) ohci->controller + '0', cc_to_string[cc], cc); + if (*phwHeadP & swpl(0x1)) + { + if (lurb_priv && ((td_list->index + 1) < urb_len)) + { + *phwHeadP = (lurb_priv->td[urb_len - 1]->hwNextTD & swpl(0xfffffff0)) | (*phwHeadP & swpl(0x2)); + lurb_priv->td_cnt += urb_len - td_list->index - 1; + } + else + *phwHeadP &= swpl(0xfffffff2); + } +#ifdef CONFIG_MPC5200 + td_list->hwNextTD = 0; +#endif + } +} + +/* + * replies to the request have to be on a FIFO basis so + * we reverse the reversed done-list + */ +static td_t *dl_reverse_done_list(volatile ohci_t *ohci) +{ + uint32_t td_list_hc; + td_t *td_rev = NULL; + td_t *td_list = NULL; + + td_list_hc = swpl(ohci->hcca->done_head) & ~0xf; + + if (td_list_hc) + { + td_list_hc += ohci->dma_offset; + } + + ohci->hcca->done_head = 0; + while (td_list_hc) + { + td_list = (td_t *) td_list_hc; + check_status(ohci, td_list); + td_list->next_dl_td = td_rev; + td_rev = td_list; + td_list_hc = swpl(td_list->hwNextTD) & ~0xf; + if (td_list_hc) + { + td_list_hc += ohci->dma_offset; + } + } + return td_list; +} + +/*-------------------------------------------------------------------------*/ + +static void finish_urb(volatile ohci_t *ohci, volatile urb_priv_t *urb, int status) +{ + if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL)) + { + urb->finished = sohci_return_job(ohci, urb); + } + else + { + dbg("finish_urb: strange.., ED state %x, \r\n", status); + } +} + +/* + * Used to take back a TD from the host controller. This would normally be + * called from within dl_done_list, however it may be called directly if the + * HC no longer sees the TD and it has not appeared on the donelist (after + * two frames). This bug has been observed on ZF Micro systems. + */ +static int takeback_td(volatile ohci_t *ohci, volatile td_t *td_list) +{ + volatile ed_t *ed; + int cc; + int stat = 0; + volatile urb_priv_t *lurb_priv; + uint32_t tdINFO; + uint32_t edHeadP; + uint32_t edTailP; + + tdINFO = swpl(td_list->hwINFO); + + ed = td_list->ed; + if (ed == NULL) + { + err("OHCI usb-%s-%c cannot get error code ED is null\r\n", ohci->slot_name, (char) ohci->controller + '0'); + + return stat; + } + + lurb_priv = ed->purb; + dl_transfer_length(ohci, td_list); + lurb_priv->td_cnt++; + + /* error code of transfer */ + cc = TD_CC_GET(tdINFO); + if (cc) + { + err("OHCI usb-%s-%c error: %s (%x)\r\n", ohci->slot_name, (char) ohci->controller + '0', cc_to_string[cc], cc); + stat = cc_to_error[cc]; + } + + /* + * see if this done list makes for all TD's of current URB, + * and mark the URB finished if so + */ + if (lurb_priv->td_cnt == lurb_priv->length) + { + finish_urb(ohci, lurb_priv, ed->state); + } + + if (ohci->irq) + { + dbg("dl_done_list: processing TD %x, len %x\r\n", lurb_priv->td_cnt, lurb_priv->length); + } + + if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) + { + edHeadP = swpl(ed->hwHeadP) & ~0xf; + edTailP = swpl(ed->hwTailP); + + /* unlink eds if they are not busy */ + if ((edHeadP == edTailP) && (ed->state == ED_OPER)) + { + ep_unlink(ohci, ed); + } + } + + if (cc && (ed->type == PIPE_INTERRUPT)) /* added, but it's not the better method */ + { + ep_unlink(ohci, ed); + } + return stat; +} + +static int dl_done_list(volatile ohci_t *ohci) +{ + int stat = 0; + volatile td_t *td_list = dl_reverse_done_list(ohci); + + while (td_list) + { + volatile td_t *td_next = td_list->next_dl_td; + + stat = takeback_td(ohci, td_list); + td_list = td_next; + } + return stat; +} + +/*-------------------------------------------------------------------------* + * Virtual Root Hub + *-------------------------------------------------------------------------*/ + +/* Device descriptor */ +static uint8_t root_hub_dev_des[] = +{ + 0x12, /* uint8_t bLength; */ + 0x01, /* uint8_t bDescriptorType; Device */ + 0x10, /* uint16_t bcdUSB; v1.1 */ + 0x01, + 0x09, /* uint8_t bDeviceClass; HUB_CLASSCODE */ + 0x00, /* uint8_t bDeviceSubClass; */ + 0x00, /* uint8_t bDeviceProtocol; */ + 0x08, /* uint8_t bMaxPacketSize0; 8 Bytes */ + 0x00, /* uint16_t idVendor; */ + 0x00, + 0x00, /* uint16_t idProduct; */ + 0x00, + 0x00, /* uint16_t bcdDevice; */ + 0x00, + 0x00, /* uint8_t iManufacturer; */ + 0x01, /* uint8_t iProduct; */ + 0x00, /* uint8_t iSerialNumber; */ + 0x01 /* uint8_t bNumConfigurations; */ +}; + +/* Configuration descriptor */ +static uint8_t root_hub_config_des[] = +{ + 0x09, /* uint8_t bLength; */ + 0x02, /* uint8_t bDescriptorType; Configuration */ + 0x19, /* uint16_t wTotalLength; */ + 0x00, + 0x01, /* uint8_t bNumInterfaces; */ + 0x01, /* uint8_t bConfigurationValue; */ + 0x00, /* uint8_t iConfiguration; */ + 0x40, /* uint8_t bmAttributes; + Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ + 0x00, /* uint8_t MaxPower; */ + + /* interface */ + 0x09, /* uint8_t if_bLength; */ + 0x04, /* uint8_t if_bDescriptorType; Interface */ + 0x00, /* uint8_t if_bInterfaceNumber; */ + 0x00, /* uint8_t if_bAlternateSetting; */ + 0x01, /* uint8_t if_bNumEndpoints; */ + 0x09, /* uint8_t if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* uint8_t if_bInterfaceSubClass; */ + 0x00, /* uint8_t if_bInterfaceProtocol; */ + 0x00, /* uint8_t if_iInterface; */ + + /* endpoint */ + 0x07, /* uint8_t ep_bLength; */ + 0x05, /* uint8_t ep_bDescriptorType; Endpoint */ + 0x81, /* uint8_t ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* uint8_t ep_bmAttributes; Interrupt */ + 0x02, /* uint16_t ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ + 0x00, + 0xff /* uint8_t ep_bInterval; 255 ms */ +}; + +static unsigned char root_hub_str_index0[] = +{ + 0x04, /* uint8_t bLength; */ + 0x03, /* uint8_t bDescriptorType; String-descriptor */ + 0x09, /* uint8_t lang ID */ + 0x04, /* uint8_t lang ID */ +}; + +static unsigned char root_hub_str_index1[] = +{ + 28, /* uint8_t bLength; */ + 0x03, /* uint8_t bDescriptorType; String-descriptor */ + 'O', /* uint8_t Unicode */ + 0, /* uint8_t Unicode */ + 'H', /* uint8_t Unicode */ + 0, /* uint8_t Unicode */ + 'C', /* uint8_t Unicode */ + 0, /* uint8_t Unicode */ + 'I', /* uint8_t Unicode */ + 0, /* uint8_t Unicode */ + ' ', /* uint8_t Unicode */ + 0, /* uint8_t Unicode */ + 'R', /* uint8_t Unicode */ + 0, /* uint8_t Unicode */ + 'o', /* uint8_t Unicode */ + 0, /* uint8_t Unicode */ + 'o', /* uint8_t Unicode */ + 0, /* uint8_t Unicode */ + 't', /* uint8_t Unicode */ + 0, /* uint8_t Unicode */ + ' ', /* uint8_t Unicode */ + 0, /* uint8_t Unicode */ + 'H', /* uint8_t Unicode */ + 0, /* uint8_t Unicode */ + 'u', /* uint8_t Unicode */ + 0, /* uint8_t Unicode */ + 'b', /* uint8_t Unicode */ + 0, /* uint8_t Unicode */ +}; + +/* Hub class-specific descriptor is constructed dynamically */ + +/*-------------------------------------------------------------------------*/ + +#define OK(x) len = (x); break +#ifdef DEBUG_OHCI +#define WR_RH_STAT(x) { err("WR:status %#8x", (x)); writel((x), &ohci->regs->roothub.status); } +#define WR_RH_PORTSTAT(x) { err("WR:portstatus[%d] %#8x", wIndex - 1, (x)); writel((x), &ohci->regs->roothub.portstatus[wIndex - 1]); } +#else +#define WR_RH_STAT(x) { writel((x), &ohci->regs->roothub.status); } +#define WR_RH_PORTSTAT(x) { writel((x), &ohci->regs->roothub.portstatus[wIndex - 1]); } +#endif +#define RD_RH_STAT roothub_status(ohci) +#define RD_RH_PORTSTAT roothub_portstatus(ohci, wIndex-1) + +/* request to virtual root hub */ + +int rh_check_port_status(ohci_t *controller) +{ + uint32_t temp, ndp, i; + int res = -1; + temp = roothub_a(controller); + // ndp = (temp & RH_A_NDP); + ndp = controller->ndp; + for (i = 0; i < ndp; i++) + { + temp = roothub_portstatus(controller, i); + + /* check for a device disconnect */ + if (((temp & (RH_PS_PESC | RH_PS_CSC)) == (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) + { + res = i; + break; + } + + /* check for a device connect */ + if ((temp & RH_PS_CSC) && (temp & RH_PS_CCS)) + { + res = i; + break; + } + } + return res; +} + +static int ohci_submit_rh_msg(volatile ohci_t *ohci, struct usb_device *dev, uint32_t pipe, + void *buffer, int transfer_len, struct devrequest *cmd) +{ + void *data = buffer; + int leni = transfer_len; + int len = 0; + int stat = 0; + uint32_t datab[4]; + uint8_t *data_buf = (uint8_t *)datab; + uint16_t bmRType_bReq; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; + +#ifdef DEBUG_OHCI + pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); +#else + if (ohci->irq) + { + wait_ms(10); + } +#endif + + if (usb_pipeint(pipe)) + { + err("Root-Hub submit IRQ: NOT implemented\r\n"); + + return 0; + } + + bmRType_bReq = cmd->requesttype | (cmd->request << 8); + wValue = swpw(cmd->value); + wIndex = swpw(cmd->index); + wLength = swpw(cmd->length); + dbg("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x\r\n", dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); + + switch (bmRType_bReq) + { + /* + * Request Destination: + * without flags: Device, + * RH_INTERFACE: interface, + * RH_ENDPOINT: endpoint, + * RH_CLASS means HUB here, + * RH_OTHER | RH_CLASS almost ever means HUB_PORT here + */ + case RH_GET_STATUS: + *(uint16_t *) data_buf = swpw(1); + OK(2); + + case RH_GET_STATUS | RH_INTERFACE: + *(uint16_t *) data_buf = swpw(0); + OK(2); + + case RH_GET_STATUS | RH_ENDPOINT: + *(uint16_t *) data_buf = swpw(0); + OK(2); + + case RH_GET_STATUS | RH_CLASS: + *(uint32_t *) data_buf = swpl(RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); + OK(4); + + case RH_GET_STATUS | RH_OTHER | RH_CLASS: + *(uint32_t *) data_buf = swpl(RD_RH_PORTSTAT); + OK(4); + + case RH_CLEAR_FEATURE | RH_ENDPOINT: + switch (wValue) + { + case (RH_ENDPOINT_STALL): OK(0); + } + break; + + case RH_CLEAR_FEATURE | RH_CLASS: + switch (wValue) + { + case RH_C_HUB_LOCAL_POWER: OK(0); + case (RH_C_HUB_OVER_CURRENT): WR_RH_STAT(RH_HS_OCIC); OK(0); + } + break; + + case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: + switch (wValue) + { + case (RH_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_CCS); OK(0); + case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_POCI); OK(0); + case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_LSDA); OK(0); + case (RH_C_PORT_CONNECTION): WR_RH_PORTSTAT(RH_PS_CSC); OK(0); + case (RH_C_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_PESC); OK(0); + case (RH_C_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSSC); OK(0); + case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0); + case (RH_C_PORT_RESET): WR_RH_PORTSTAT(RH_PS_PRSC); OK(0); + } + break; + + case RH_SET_FEATURE | RH_OTHER | RH_CLASS: + switch (wValue) + { + case (RH_PORT_SUSPEND): + WR_RH_PORTSTAT(RH_PS_PSS); + OK(0); + case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ + if (RD_RH_PORTSTAT & RH_PS_CCS) + WR_RH_PORTSTAT(RH_PS_PRS); + OK(0); + case (RH_PORT_POWER): + WR_RH_PORTSTAT(RH_PS_PPS); + wait_ms(100); + OK(0); + case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ + if (RD_RH_PORTSTAT & RH_PS_CCS) + WR_RH_PORTSTAT(RH_PS_PES); + OK(0); + } + break; + + case RH_SET_ADDRESS: + ohci->rh.devnum = wValue; + OK(0); + + case RH_GET_DESCRIPTOR: + switch ((wValue & 0xff00) >> 8) + { + case(0x01): /* device descriptor */ + len = min_t(unsigned int, leni, min_t(unsigned int, sizeof(root_hub_dev_des), wLength)); + data_buf = root_hub_dev_des; + OK(len); + + case(0x02): /* configuration descriptor */ + len = min_t(unsigned int, leni, min_t(unsigned int, sizeof(root_hub_config_des), wLength)); + data_buf = root_hub_config_des; + OK(len); + + case(0x03): /* string descriptors */ + if (wValue == 0x0300) + { + len = min_t(unsigned int, leni, min_t(unsigned int, sizeof(root_hub_str_index0), wLength)); + data_buf = root_hub_str_index0; + OK(len); + } + if (wValue == 0x0301) + { + len = min_t(unsigned int, leni, min_t(unsigned int, sizeof(root_hub_str_index1), wLength)); + data_buf = root_hub_str_index1; + OK(len); + } + + default: + stat = USB_ST_STALLED; + } + break; + + case RH_GET_DESCRIPTOR | RH_CLASS: + { + uint32_t temp = roothub_a(ohci); + data_buf[0] = 9; /* min length; */ + data_buf[1] = 0x29; + // data_buf[2] = temp & RH_A_NDP; + data_buf[2] = (uint8_t)ohci->ndp; + data_buf[3] = 0; + + if (temp & RH_A_PSM) /* per-port power switching? */ + { + data_buf[3] |= 0x1; + } + + if (temp & RH_A_NOCP) /* no overcurrent reporting? */ + { + data_buf[3] |= 0x10; + } + else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ + { + data_buf[3] |= 0x8; + } + + /* corresponds to data_buf[4-7] */ + datab[1] = 0; + data_buf[5] = (temp & RH_A_POTPGT) >> 24; + temp = roothub_b(ohci); + data_buf[7] = temp & RH_B_DR; + if (data_buf[2] < 7) + { + data_buf[8] = 0xff; + } + else + { + data_buf[0] += 2; + data_buf[8] = (temp & RH_B_DR) >> 8; + data_buf[10] = data_buf[9] = 0xff; + } + len = min_t(unsigned int, leni, min_t(unsigned int, data_buf[0], wLength)); + OK(len); + } + + case RH_GET_CONFIGURATION: *(uint8_t *) data_buf = 0x01; OK(1); + + case RH_SET_CONFIGURATION: WR_RH_STAT(0x10000); OK(0); + + default: + dbg("unsupported root hub command"); + stat = USB_ST_STALLED; + } +#ifdef DEBUG_OHCI + ohci_dump_roothub(ohci, 1); +#else + if (ohci->irq) + { + wait_ms(10); + } +#endif + + len = min_t(int, len, leni); + + if (data != data_buf) + { + memcpy(data, data_buf, len); + } + + dev->act_len = len; + dev->status = stat; + +#ifdef DEBUG_OHCI + pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); +#else + + if (ohci->irq) + { + wait_ms(10); + } +#endif + + return stat; +} + + +/* + * common code for handling submit messages - used for all but root hub accesses. + */ + +static int submit_common_msg(volatile ohci_t *ohci, struct usb_device *dev, uint32_t pipe, void *buffer, + int transfer_len, struct devrequest *setup, int interval) +{ + int stat = 0; + int maxsize = usb_maxpacket(dev, pipe); + int timeout; + volatile urb_priv_t *urb = driver_mem_alloc(sizeof(urb_priv_t)); + + if (urb == NULL) + { + err("submit_common_msg driver_mem_alloc() failed\r\n"); + + return -1; + } + memset((void *) urb, 0, sizeof(urb_priv_t)); + + urb->dev = dev; + urb->pipe = pipe; + urb->transfer_buffer = buffer; + urb->transfer_buffer_length = transfer_len; + urb->interval = interval; + + /* device pulled? Shortcut the action. */ + if (ohci->devgone == dev) + { + dev->status = USB_ST_CRC_ERR; + err("device is gone...\r\n"); + return 0; + } +#ifdef DEBUG_OHCI + urb->actual_length = 0; + pkt_print(ohci, urb, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); +#else + if (ohci->irq) + { + wait_us(10); + } +#endif + + if (!maxsize) + { + err("submit_common_message: pipesize for pipe %lx is zero\r\n", pipe); + return -1; + } + + if (sohci_submit_job(ohci, urb, setup) < 0) + { + err("sohci_submit_job failed\r\n"); + return -1; + } + +#if 0 + wait_us(10); + /* ohci_dump_status(ohci); */ +#endif + + /* allow more time for a BULK device to react - some are slow */ + +#define BULK_TO 5000 /* timeout in milliseconds */ + + if (usb_pipebulk(pipe)) + { + timeout = BULK_TO; + } + else + { + timeout = 1000; + } + + /* wait for it to complete */ + while (ohci->irq) + { + /* check whether the controller is done */ + // flush_data_cache(ohci); no need to do that, PCI is uncached, as well as USB memory + +#ifndef CONFIG_USB_INTERRUPT_POLLING + if (ohci->irq_enabled) + { + stat = ohci->stat_irq; + } + else +#endif + stat = hc_interrupt(ohci); + + if (stat < 0) + { + err("USB CRC error\r\n"); + stat = USB_ST_CRC_ERR; + break; + } + /* + * NOTE: since we are not interrupt driven in U-Boot and always + * handle only one URB at a time, we cannot assume the + * transaction finished on the first successful return from + * hc_interrupt().. unless the flag for current URB is set, + * meaning that all TD's to/from device got actually + * transferred and processed. If the current URB is not + * finished we need to re-iterate this loop so as + * hc_interrupt() gets called again as there needs to be some + * more TD's to process still + */ + if ((stat >= 0) && (stat != 0xff) && (urb->finished)) + { + /* 0xff is returned for an SF-interrupt */ + break; + } + + if (--timeout) + { + wait_ms(10); +// if (!urb->finished) +// xprintf("*\r\n"); + } + else + { + err("OHCI usb-%s-%c CTL:TIMEOUT\r\n", ohci->slot_name, (char) ohci->controller + '0'); + dbg("submit_common_msg: TO status %x\r\n", stat); + urb->finished = 1; + stat = USB_ST_CRC_ERR; + break; + } + } + + dev->status = stat; + dev->act_len = transfer_len; +#ifdef DEBUG_OHCI + pkt_print(ohci, urb, dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); +#else + if (ohci->irq) + wait_ms(10); +#endif + /* free TDs in urb_priv */ + if (!usb_pipeint(pipe)) + urb_free_priv(urb); + return 0; +} + +/* submit routines called from usb.c */ +int ohci_submit_bulk_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len) +{ + err("submit_bulk_msg dev 0x%p ohci 0x%p buffer 0x%p len %d", dev, dev->priv_hcd, buffer, transfer_len); + return submit_common_msg((ohci_t *)dev->priv_hcd, dev, pipe, buffer, transfer_len, NULL, 0); +} + +int ohci_submit_control_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, struct devrequest *setup) +{ + volatile ohci_t *ohci = (ohci_t *) dev->priv_hcd; + int maxsize = usb_maxpacket(dev, pipe); + + dbg("submit_control_msg dev 0x%p ohci 0x%p\r\n", dev, ohci); + +#ifdef DEBUG_OHCI + pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); +#else + if (ohci->irq) + { + wait_us(10); + } +#endif + + if (!maxsize) + { + err("submit_control_message: pipesize for pipe %lx is zero", pipe); + return -1; + } + + if (((pipe >> 8) & 0x7f) == ohci->rh.devnum) + { + ohci->rh.dev = dev; + dbg("redirect\r\n"); + /* root hub - redirect */ + return ohci_submit_rh_msg(ohci, dev, pipe, buffer, transfer_len, setup); + } + return submit_common_msg(ohci, dev, pipe, buffer, transfer_len, setup, 0); +} + +int ohci_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval) +{ + err("submit_int_msg dev 0x%p ohci 0x%p buffer 0x%p len %d", dev, dev->priv_hcd, buffer, transfer_len); + return submit_common_msg((ohci_t *)dev->priv_hcd, dev, pipe, buffer, transfer_len, NULL, interval); +} + +/*-------------------------------------------------------------------------* + * HC functions + *-------------------------------------------------------------------------*/ + +/* reset the HC and BUS */ + +static int hc_reset(volatile ohci_t *ohci) +{ + int timeout = 30; + int smm_timeout = 50; /* 0,5 sec */ + + if ((ohci->ent->vendor == PCI_VENDOR_ID_PHILIPS) + && (ohci->ent->device == PCI_DEVICE_ID_PHILIPS_ISP1561)) + { +#define EHCI_USBCMD_OFF 0x20 +#define EHCI_USBCMD_HCRESET (1 << 1) + + /* + * Some multi-function controllers (e.g. ISP1562) allow root hub + * resetting via EHCI registers only. + */ + int index = 0; + long handle; + + do + { + handle = pci_find_device(0x0, 0xffff, index++); + + if (handle >= 0) + { + uint32_t id = 0; + id = pci_read_config_longword(handle, PCIIDR); + if ((PCI_VENDOR_ID_PHILIPS == (id & 0xFFFF)) && (PCI_DEVICE_ID_PHILIPS_ISP1561_2 == (id >> 16))) + { + int timeout = 1000; + uint32_t usb_base_addr = 0xFFFFFFFF; + struct pci_rd *pci_rsc_desc; + pci_rsc_desc = pci_get_resource(handle); /* USB OHCI */ + if ((long)pci_rsc_desc >= 0) + { + unsigned short flags; + do + { + if (!(pci_rsc_desc->flags & FLG_IO)) + { + if (usb_base_addr == 0xFFFFFFFF) + { + uint32_t base = pci_rsc_desc->offset + pci_rsc_desc->start; + writel((uint32_t) readl((uint32_t *) base + EHCI_USBCMD_OFF) | EHCI_USBCMD_HCRESET, (uint32_t *) base + EHCI_USBCMD_OFF); + while (readl((uint32_t *) base + EHCI_USBCMD_OFF) & EHCI_USBCMD_HCRESET) + { + if (timeout-- <= 0) + { + err("USB RootHub reset timed out!\r\n"); + break; + } + wait_us(1); + } + } + } + flags = pci_rsc_desc->flags; + pci_rsc_desc = (struct pci_rd *) ((uint32_t) pci_rsc_desc->next + (uint32_t) pci_rsc_desc); + } + while (!(flags & FLG_LAST)); + } + } + } + } + while (handle >= 0); + } + + if ((ohci->controller == 0) && (ohci->ent->vendor == PCI_VENDOR_ID_NEC) + && (ohci->ent->device == PCI_DEVICE_ID_NEC_USB)) + { + //if (ohci->handle == 1) /* NEC on motherboard has FPGA clock */ +#if defined(MACHINE_FIREBEE) + { + dbg("USB OHCI set 48MHz clock\r\n"); + pci_write_config_longword(ohci->handle, 0xE4, 0x21); // oscillator & disable ehci + wait_us(1); + } + //else +#else + { + pci_write_config_longword(ohci->handle, 0xE4, pci_read_config_longword(ohci->handle, 0xE4) | 0x01); // disable ehci + wait_us(1); + } +#endif + } + + dbg("control: %x\r\n", readl(&ohci->regs->control)); + + if (readl(&ohci->regs->control) & OHCI_CTRL_IR) + { + /* SMM owns the HC */ + writel(OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ + + err("USB HC TakeOver from SMM"); + while (readl(&ohci->regs->control) & OHCI_CTRL_IR) + { + wait_us(10); + if (--smm_timeout == 0) + { + err("USB HC TakeOver failed!"); + return -1; + } + } + } + + /* Disable HC interrupts */ + writel(OHCI_INTR_MIE, &ohci->regs->intrdisable); + + dbg("USB OHCI HC reset_hc usb-%s-%c: ctrl = 0x%X\r\n", ohci->slot_name, + (char) ohci->controller + '0', readl(&ohci->regs->control)); + + /* Reset USB (needed by some controllers) */ + ohci->hc_control = 0; + writel(ohci->hc_control, &ohci->regs->control); + + /* HC Reset requires max 10 us delay */ + writel(OHCI_HCR, &ohci->regs->cmdstatus); + while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) + { + if (--timeout == 0) + { + err("USB HC reset timed out!"); +#ifdef DEBUG_OHCI + ohci_dump_status(ohci); +#endif /* DEBUG_OHCI */ + return -1; + } + wait_us(1); + } + return 0; +} + + +/* + * Start an OHCI controller, set the BUS operational + * enable interrupts + * connect the virtual root hub + */ + +static int hc_start(volatile ohci_t *ohci) +{ + uint32_t mask; + unsigned int fminterval; + + ohci->disabled = 1; + + /* + * Tell the controller where the control and bulk lists are + * The lists are empty now. + */ + writel(0, &ohci->regs->ed_controlhead); + writel(0, &ohci->regs->ed_bulkhead); + + writel((uint32_t) ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ + + fminterval = 0x2edf; + writel((fminterval * 9) / 10, &ohci->regs->periodicstart); + + fminterval |= ((((fminterval - 210) * 6) / 7) << 16); + writel(fminterval, &ohci->regs->fminterval); + writel(0x628, &ohci->regs->lsthresh); + + /* start controller operations */ + ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; + ohci->disabled = 0; + writel(ohci->hc_control, &ohci->regs->control); + + /* disable all interrupts */ + mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | + OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | + OHCI_INTR_OC | OHCI_INTR_MIE); + writel(mask, &ohci->regs->intrdisable); + + /* clear all interrupts */ + mask &= ~OHCI_INTR_MIE; + writel(mask, &ohci->regs->intrstatus); + + /* Choose the interrupts we care about now - but w/o MIE */ + mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; + writel(mask, &ohci->regs->intrenable); + ohci->ndp = roothub_a(ohci); + +#ifdef OHCI_USE_NPS + /* required for AMD-756 and some Mac platforms */ + writel((ohci->ndp | RH_A_NPS) & ~RH_A_PSM, &ohci->regs->roothub.a); + writel(RH_HS_LPSC, &ohci->regs->roothub.status); +#endif /* OHCI_USE_NPS */ + + /* POTPGT delay is bits 24-31, in 2 ms units. */ +#define mdelay(n) ({unsigned long msec = (n); while (msec--) wait_ms(1); }) + + dbg("wait_ms(0x%x)\r\n", (ohci->ndp >> 23) & 0x1fe); + mdelay((ohci->ndp >> 23) & 0x1fe); + + // ohci->ndp &= RH_A_NDP; + + /* connect the virtual root hub */ + ohci->rh.devnum = 0; + + return 0; +} + + + + +/* + * an interrupt happens + */ +static int hc_interrupt(volatile ohci_t *ohci) +{ + volatile struct ohci_regs *regs = ohci->regs; + int ints; + int stat = -1; + + dbg("\r\n"); + if ((ohci->hcca->done_head != 0) && !(swpl(ohci->hcca->done_head) & 0x01)) + { + ints = OHCI_INTR_WDH; + } + else + { + ints = readl(®s->intrstatus); + if (ints == ~0UL) + { + ohci->disabled++; + err("OHCI usb-%s-%c device removed!\r\n", ohci->slot_name, (char) ohci->controller + '0'); + return -1; + } + else + { + ints &= readl(®s->intrenable); + if (ints == 0) + { + dbg("no interrupt...\r\n"); + + return 0xff; + } + } + } + + if (ohci->irq) + { + dbg("Interrupt: 0x%x frame: 0x%x bus: %d\r\n", ints, swpw(ohci->hcca->frame_no), ohci->controller); + } + + if (ints & OHCI_INTR_RHSC) /* root hub status change */ + { + stat = 0xff; + } + + if (ints & OHCI_INTR_UE) /* e.g. due to PCI Master/Target Abort */ + { + unsigned short status = pci_read_config_word(ohci->handle, PCISR); + + err("OHCI Unrecoverable Error, controller usb-%s-%c disabled\r\n(SR:0x%04X%s%s%s%s%s%s)", + ohci->slot_name, (char) ohci->controller + '0', status & 0xFFFF, + status & 0x8000 ? ", Parity error" : "", + status & 0x4000 ? ", Signaled system error" : "", + status & 0x2000 ? ", Received master abort" : "", + status & 0x1000 ? ", Received target abort" : "", + status & 0x800 ? ", Signaled target abort" : "", + status & 0x100 ? ", Data parity error" : ""); + ohci->disabled++; +#ifdef DEBUG_OHCI + ohci_dump(ohci, 1); +#else + if (ohci->irq) + { + wait_ms(1); + } +#endif + /* HC Reset */ + ohci->hc_control = 0; + writel(ohci->hc_control, &ohci->regs->control); + + return -1; + } + + if (ints & OHCI_INTR_WDH) + { + if (ohci->irq) + { + wait_ms(1); + } + + writel(OHCI_INTR_WDH, ®s->intrdisable); + (void) readl(®s->intrdisable); /* flush */ + stat = dl_done_list(ohci); + + writel(OHCI_INTR_WDH, ®s->intrenable); + (void) readl(®s->intrdisable); /* flush */ + } + + if (ints & OHCI_INTR_SO) + { + dbg("USB Schedule overrun\r\n"); + writel(OHCI_INTR_SO, ®s->intrenable); + stat = -1; + } + + /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ + if (ints & OHCI_INTR_SF) + { + unsigned int frame = swpw(ohci->hcca->frame_no) & 1; + + wait_ms(1); + writel(OHCI_INTR_SF, ®s->intrdisable); + if (ohci->ed_rm_list[frame] != NULL) + { + writel(OHCI_INTR_SF, ®s->intrenable); + } + stat = 0xff; + } + writel(ints, ®s->intrstatus); + + return stat; +} + +static int handle_usb_interrupt(ohci_t *ohci) +{ + if(!ohci->irq_enabled) + { + return 0; + } + + ohci->irq = 0; + ohci->stat_irq = hc_interrupt(ohci); + ohci->irq = -1; + + return 1; /* clear interrupt, 0: disable interrupt */ +} + +void ohci_usb_enable_interrupt(int enable) +{ + int i; + + dbg("usb_enable_interrupt(%d)", enable); + + for(i = 0; i < (sizeof(gohci) / sizeof(ohci_t)); i++) + { + ohci_t *ohci = &gohci[i]; + if(!ohci->handle) + { + continue; + } + ohci->irq_enabled = enable; + if (enable) + writel(OHCI_INTR_MIE, &ohci->regs->intrenable); + else + writel(OHCI_INTR_MIE, &ohci->regs->intrdisable); + } +} + +/* De-allocate all resources.. */ + +static void hc_release_ohci(volatile ohci_t *ohci) +{ + dbg("USB HC release OHCI usb-%s-%c", ohci->slot_name, (char) ohci->controller + '0'); + if (!ohci->disabled) + { + hc_reset(ohci); + } +} + +static void hc_free_buffers(volatile ohci_t *ohci) +{ + if (ohci->td_unaligned != NULL) + { + /* FIXME: driver_mem_free(ohci->td_unaligned); */ + ohci->td_unaligned = NULL; + } + if (ohci->ohci_dev_unaligned != NULL) + { + /* FIXME: driver_mem_free(ohci->ohci_dev_unaligned); */ + ohci->ohci_dev_unaligned = NULL; + } + if (ohci->hcca_unaligned != NULL) + { + /* FIXME: driver_mem_free(ohci->hcca_unaligned); */ + ohci->hcca_unaligned = NULL; + } +} + +/* + * low level initalisation routine, called from usb.c + */ +int ohci_usb_lowlevel_init(int32_t handle, const struct pci_device_id *ent, void **priv) +{ + uint32_t usb_base_addr = 0xFFFFFFFF; + volatile ohci_t *ohci = &gohci[pci_handle2index(handle)]; + struct pci_rd *pci_rsc_desc = pci_get_resource(handle); /* USB OHCI */ + + if (handle && (ent != NULL)) + { + memset((void *) ohci, 0, sizeof(ohci_t)); + ohci->handle = handle; + ohci->ent = ent; + } + else if (!ohci->handle) /* for restart USB cmd */ + { + return -1; + } + + inf("ohci %p, handle = 0x%x, fctn = 0x%x\r\n", ohci, handle, PCI_FUNCTION_FROM_HANDLE(handle)); + + ohci->controller = PCI_FUNCTION_FROM_HANDLE(ohci->handle); + + dbg("handle = 0x%x, function = 0x%x\r\n", ohci->handle, ohci->controller); + // ohci->controller = (ohci->handle >> 16) & 3; /* PCI function */ + + /* this must be aligned to a 256 byte boundary */ + ohci->hcca_unaligned = driver_mem_alloc(sizeof(struct ohci_hcca) + 256); + if (ohci->hcca_unaligned == NULL) + { + err("HCCA malloc failed\r\n"); + return -1; + } + + /* align the storage */ + ohci->hcca = (struct ohci_hcca *) (((uint32_t) ohci->hcca_unaligned + 255) & ~255); + memset((void *) ohci->hcca, 0, sizeof(struct ohci_hcca)); + inf("aligned ghcca %p\r\n", ohci->hcca); + + ohci->ohci_dev_unaligned = driver_mem_alloc(sizeof(struct ohci_device) + 8); + if (ohci->ohci_dev_unaligned == NULL) + { + err("EDs malloc failed\r\n"); + hc_free_buffers(ohci); + + return -1; + } + ohci->ohci_dev = (struct ohci_device *) (((uint32_t) ohci->ohci_dev_unaligned + 7) & ~7); + memset(ohci->ohci_dev, 0, sizeof(struct ohci_device)); + dbg("aligned EDs %p\r\n", ohci->ohci_dev); + + ohci->td_unaligned = driver_mem_alloc(sizeof(struct td) * (NUM_TD + 1)); + if (ohci->td_unaligned == NULL) + { + err("TDs malloc failed\r\n"); + hc_free_buffers(ohci); + + return -1; + } + + ptd = (struct td *) (((uint32_t) ohci->td_unaligned + 7) & ~7); + + dbg("memset from %p to %p\r\n", ptd, ptd + sizeof(td_t) * NUM_TD); + memset(ptd, 0, sizeof(td_t) * NUM_TD); + dbg("aligned TDs %p\r\n", ptd); + + ohci->disabled = 1; + ohci->sleeping = 0; + ohci->irq = -1; + + if (pci_rsc_desc != NULL) + { + unsigned short flags; + do + { + dbg("PCI USB descriptors (at %p): flags 0x%04x start 0x%08lx\r\n", + pci_rsc_desc, pci_rsc_desc->flags, pci_rsc_desc->start); + dbg("offset 0x%08lx dmaoffset 0x%08lx length 0x%08lx\r\n", + pci_rsc_desc->offset, + pci_rsc_desc->dmaoffset, + pci_rsc_desc->length); + + if (!(pci_rsc_desc->flags & FLG_IO)) + { + /* if this is a memory-mapped resource */ + + if (usb_base_addr == 0xFFFFFFFF) + { + /* and if its not initialized yet */ + + usb_base_addr = pci_rsc_desc->start; + ohci->offset = pci_rsc_desc->offset; + ohci->regs = (void *) (pci_rsc_desc->offset + pci_rsc_desc->start); + ohci->dma_offset = pci_rsc_desc->dmaoffset; + + /* big_endian unused actually */ + if ((pci_rsc_desc->flags & FLG_ENDMASK) == ORD_MOTOROLA) + ohci->big_endian = 0; /* host bridge make swapping intel -> motorola */ + else + ohci->big_endian = 1; /* driver must do swapping intel -> motorola */ + } + } + flags = pci_rsc_desc->flags; + pci_rsc_desc = (struct pci_rd *) ((uint32_t) pci_rsc_desc->next + (uint32_t) pci_rsc_desc); + } while (!(flags & FLG_LAST)); + } + else + { + hc_free_buffers(ohci); + dbg("pci_get_resource() failed\r\n"); + + return -1; /* get_resource error */ + } + + if (usb_base_addr == 0xFFFFFFFF) + { + hc_free_buffers(ohci); + return -1; + } + + if (handle && (ent != NULL)) + { + ohci->flags = 0; + switch (ent->vendor) + { + case PCI_VENDOR_ID_AL: + ohci->slot_name = "uli1575"; + break; + + case PCI_VENDOR_ID_NEC: + ohci->slot_name = "uPD720101"; + ohci->flags |= OHCI_FLAGS_NEC; + break; + + case PCI_VENDOR_ID_PHILIPS: + ohci->slot_name = "isp1561"; + break; + + default: + ohci->slot_name = "generic"; + break; + } + } + + dbg("OHCI usb-%s-%c, regs address 0x%08X, PCI handle 0x%X\r\n", + ohci->slot_name, + (char) ohci->controller + '0', + ohci->regs, handle); + + if (hc_reset(ohci) < 0) + { + err("Can't reset OHCI usb-%s-%c", ohci->slot_name, (char) ohci->controller + '0'); + hc_release_ohci(ohci); + hc_free_buffers(ohci); + return -1; + } + + if (hc_start(ohci) < 0) + { + err("Can't start OHCI usb-%s-%c", ohci->slot_name, (char) ohci->controller + '0'); + hc_release_ohci(ohci); + hc_free_buffers(ohci); + + /* Initialization failed */ + return -1; + } + +#ifdef DEBUG_OHCI + ohci_dump(ohci, 1); +#endif + pci_hook_interrupt(handle, (pci_interrupt_handler) handle_usb_interrupt, (void *) ohci); + if (priv != NULL) + { + *priv = (void *) ohci; + } + + ohci_inited = 1; + + return 0; +} + +int ohci_usb_lowlevel_stop(void *priv) +{ + /* this gets called really early - before the controller has */ + /* even been initialized! */ + + ohci_t *ohci = (ohci_t *) priv; + + if (!ohci_inited) + return 0; + + if (ohci == NULL) + ohci = &gohci[0]; + + pci_unhook_interrupt(ohci->handle); + + hc_reset(ohci); + hc_free_buffers(ohci); + + /* This driver is no longer initialised. It needs a new low-level + * init (board/cpu) before it can be used again. */ + + ohci_inited = 0; + + return 0; +} + diff --git a/pci/pci.c b/pci/pci.c new file mode 100644 index 0000000..1a13fd8 --- /dev/null +++ b/pci/pci.c @@ -0,0 +1,1281 @@ +/* + * pci.c + * + * Purpose: PCI configuration for the Coldfire builtin PCI bridge. + * + * Notes: + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 08.01.2013 + * Author: Markus Froeschle + */ + +#include +#include "pci.h" +#include "pci_errata.h" +#include "bas_types.h" +#include "bas_printf.h" +#include "bas_string.h" +#include "util.h" +#include "interrupts.h" +#include "wait.h" + +// #define DEBUG +#include "debug.h" + +#define pci_config_wait() do { __asm__ __volatile("tpf" ::: "memory"); } while (0) + +/* + * PCI device class descriptions displayed during PCI bus scan + */ +static struct pci_class +{ + int classcode; + char *description; +} pci_classes[] = +{ +{ 0x00, "device was built prior definition of the class code field" }, +{ 0x01, "Mass Storage Controller" }, +{ 0x02, "Network Controller" }, +{ 0x03, "Display Controller" }, +{ 0x04, "Multimedia Controller" }, +{ 0x05, "Memory Controller" }, +{ 0x06, "Bridge Device" }, +{ 0x07, "Simple Communication Controller" }, +{ 0x08, "Base System Peripherial" }, +{ 0x09, "Input Device" }, +{ 0x0a, "Docking Station" }, +{ 0x0b, "Processor" }, +{ 0x0c, "Serial Bus Controller" }, +{ 0x0d, "Wireless Controller" }, +{ 0x0e, "Intelligent I/O Controller" }, +{ 0x0f, "Satellite Communication Controller" }, +{ 0x10, "Encryption/Decryption Controller" }, +{ 0x11, "Data Acquisition and Signal Processing Controller" }, +{ 0xff, "Device does not fit any defined class" }, +}; +static int num_pci_classes = sizeof(pci_classes) / sizeof(struct pci_class); + +#define NUM_CARDS 10 +#define NUM_RESOURCES 7 +/* holds the handle of a card at position = array index */ +static int32_t handles[NUM_CARDS] = { -1 }; + +/* holds the card's resource descriptors; filled in pci_device_config() */ +static struct pci_rd resource_descriptors[NUM_CARDS][NUM_RESOURCES]; + +/* + * holds the interrupt handler addresses (see pci_hook_interrupt() + * and pci_unhook_interrupt()) of the PCI cards + */ +struct pci_interrupt +{ + int32_t handle; + int irq; + pci_interrupt_handler handler; + int32_t parameter; + struct pci_interrupt *next; +}; + +#define MAX_INTERRUPTS (NUM_CARDS * 3) +static struct pci_interrupt interrupts[MAX_INTERRUPTS]; + + +/* + * Although this pragma stuff should work according to the GCC docs, it doesn't seem to + * with m68k-atari-mint-gcc. At least not currently. + * I nevertheless keep it here for future reference + */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-function" + +int32_t pci_get_interrupt_cause(void) +{ + int32_t handle; + int32_t *hdl = &handles[0]; + /* + * loop through all PCI devices... + */ + dbg(""); + while ((handle = *hdl++) != -1) + { + uint16_t command_register = swpw(pci_read_config_word(handle, PCI_LANESWAP_W(PCICR))); + uint16_t status_register = swpw(pci_read_config_word(handle, PCI_LANESWAP_W(PCISR))); + + /* + * ...to see which device caused the interrupt + */ + if ((status_register & PCISR_INTERRUPT) && !(command_register & PCICR_INT_DISABLE)) + { + /* device has interrupts enabled and has an active interrupt, so its probably ours */ + + return handle; + } + } + dbg("no interrupt cause found\r\n"); + return -1; +} + +int32_t pci_call_interrupt_chain(int32_t handle, int32_t data) +{ + int i; + + dbg(""); + for (i = 0; i < MAX_INTERRUPTS; i++) + { + if (interrupts[i].handle == handle) + { + interrupts[i].handler(data); + + return 1; + } + } + return data; /* unmodified - means: not handled */ +} +#pragma GCC diagnostic pop + + + +/* + * retrieve handle for i'th device + */ +int pci_handle2index(int32_t handle) +{ + int i; + + for (i = 0; i < NUM_CARDS; i++) + { + if (handles[i] == handle) + { + return i; + } + } + return -1; +} + +/* + * retrieve device class (in cleartext) for a PCI classcode + */ +static char *device_class(int classcode) +{ + int i; + + for (i = 0; i < num_pci_classes; i++) + { + if (pci_classes[i].classcode == classcode) + { + return pci_classes[i].description; + } + } + return "unknown device class"; +} + +/* + * do error checking after a PCI transaction + */ +static int pci_check_status(void) +{ + uint32_t pcisr; + uint32_t pcigscr; + + int ret = 0; + + pcisr = MCF_PCI_PCIISR; /* retrieve initiator status register */ + + if (pcisr & MCF_PCI_PCIISR_RE) + { + dbg("PCI initiator retry error. Cleared.\r\n"); + MCF_PCI_PCIISR |= MCF_PCI_PCIISR_RE; + + ret = 1; + } + + if (pcisr & MCF_PCI_PCIISR_IA) + { + dbg("PCI initiator abort. Error cleared\r\n"); + MCF_PCI_PCIISR |= MCF_PCI_PCIISR_IA; + + ret = 1; + } + + if (pcisr & MCF_PCI_PCIISR_TA) + { + dbg("PCI initiator target abort error. Error cleared\r\n"); + MCF_PCI_PCIISR |= MCF_PCI_PCIISR_TA; + + ret = 1; + } + + pcigscr = MCF_PCI_PCIGSCR; + + if (pcigscr & MCF_PCI_PCIGSCR_PE) + { + dbg("PCI parity error. Error cleared\r\n"); + MCF_PCI_PCIGSCR |= MCF_PCI_PCIGSCR_PE; + + ret = 1; + } + + if (pcigscr & MCF_PCI_PCIGSCR_SE) + { + dbg("PCI system error. Error cleared\r\n"); + MCF_PCI_PCIGSCR |= MCF_PCI_PCIGSCR_SE; + + ret = 1; + } + return ret; +} + +/* + * read an uint32_t from configuration space of card with handle and offset + * + * The returned value is in little endian format. + */ +uint32_t pci_read_config_longword(int32_t handle, int offset) +{ + uint32_t value; + + /* initiate PCI configuration access to device */ + MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */ + MCF_PCI_PCICAR_BUSNUM(PCI_BUS_FROM_HANDLE(handle)) | + MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | /* device number, devices 0 - 9 are reserved */ + MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | /* function number */ + MCF_PCI_PCICAR_DWORD(offset / 4); + + NOP(); + + value = * (volatile uint32_t *) PCI_IO_OFFSET; /* access device */ + + NOP(); + + /* finish PCI configuration access special cycle (allow regular PCI accesses) */ + MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E; + + pci_check_status(); + + return value; +} + +uint16_t pci_read_config_word(int32_t handle, int offset) +{ + uint16_t value; + + /* + * initiate PCI configuration space access to device + */ + MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration space special cycle */ + MCF_PCI_PCICAR_BUSNUM(PCI_BUS_FROM_HANDLE(handle)) | + MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | + MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | + MCF_PCI_PCICAR_DWORD(offset / 4); + + NOP(); + + value = * (volatile uint16_t *) (PCI_IO_OFFSET + (offset & 2)); + + NOP(); + + /* finish PCI configuration access special cycle */ + MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E; + + pci_check_status(); + + return value; +} + +uint8_t pci_read_config_byte(int32_t handle, int offset) +{ + uint8_t value; + + /* initiate PCI configuration access to device */ + MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */ + MCF_PCI_PCICAR_BUSNUM(PCI_BUS_FROM_HANDLE(handle)) | + MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | /* device number, devices 0 - 9 are reserved */ + MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | /* function number */ + MCF_PCI_PCICAR_DWORD(offset / 4); + + NOP(); + + value = * (volatile uint8_t *) (PCI_IO_OFFSET + (offset & 3)); + + NOP(); + + MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E; + + pci_check_status(); + + return value; +} + +/* + * pci_write_config_longword() + * + * write an uint32_t value (must be in little endian format) to the configuration space of a PCI device + */ +int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t value) +{ + /* initiate PCI configuration access to device */ + + MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */ + MCF_PCI_PCICAR_BUSNUM(PCI_BUS_FROM_HANDLE(handle)) | + MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | /* device number, devices 0 - 9 are reserved */ + MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | /* function number */ + MCF_PCI_PCICAR_DWORD(offset / 4); + + chip_errata_135(); + NOP(); + + * (volatile uint32_t *) PCI_IO_OFFSET = value; /* access device */ + + dbg("chip errata\r\n"); + chip_errata_135(); + + NOP(); + + /* finish configuration space access cycle */ + MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E; + + pci_check_status(); + + return PCI_SUCCESSFUL; +} + +/* + * write a 16-bit value to config space. Must be in little-endian format + */ +int32_t pci_write_config_word(int32_t handle, int offset, uint16_t value) +{ + /* initiate PCI configuration access to device */ + MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */ + MCF_PCI_PCICAR_BUSNUM(PCI_BUS_FROM_HANDLE(handle)) | + MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | + MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | + MCF_PCI_PCICAR_DWORD(offset / 4); + + chip_errata_135(); + + NOP(); + + * (volatile uint16_t *) (PCI_IO_OFFSET + (offset & 2)) = value; + chip_errata_135(); + NOP(); + + /* finish configuration space access cycle */ + MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E; + + pci_check_status(); + + return PCI_SUCCESSFUL; +} + +/* + * write a single byte to config space + */ +int32_t pci_write_config_byte(int32_t handle, int offset, uint8_t value) +{ + MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | + MCF_PCI_PCICAR_BUSNUM(PCI_BUS_FROM_HANDLE(handle)) | + MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | + MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | + MCF_PCI_PCICAR_DWORD(offset / 4); + chip_errata_135(); + + NOP(); + + * (volatile uint8_t *) (PCI_IO_OFFSET + (offset & 3)) = value; + chip_errata_135(); + + NOP(); + + + /* finish configuration space access cycle */ + MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E; + + pci_check_status(); + + return PCI_SUCCESSFUL; +} + +/* + * pci_get_resource + * + * get resource descriptor chain for handle + */ +struct pci_rd *pci_get_resource(int32_t handle) +{ + int index = -1; + struct pci_rd *ret; + + index = pci_handle2index(handle); + if (index == -1) + { + ret = NULL; + } + else + { + ret = &resource_descriptors[index][0]; + } + + dbg("pci_get_resource: resource struct for handle %lx (index %d) is at %p\r\n", handle, index, ret); + + return ret; +} + +/* + * pci_find_device() + * + * find index'th device by device_id and vendor_id. Special case: vendor id -1 (0xffff) + * matches all devices. You can search the whole bus by repeatedly calling this function + */ +int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index) +{ + uint16_t bus; + uint16_t device; + uint16_t function = 0; + uint16_t n = 0; + int32_t handle; + + for (bus = 0; bus < 1; bus++) + { + for (device = 10; device < 31; device++) + { + uint32_t value; + uint8_t htr; + + handle = PCI_HANDLE(bus, device, 0); + value = swpl(pci_read_config_longword(handle, PCIIDR)); + if (value != 0xffffffff) /* we have a device at this position */ + { + if (vendor_id == 0xffff || + (PCI_VENDOR_ID(value) == vendor_id && PCI_DEVICE_ID(value) == device_id)) + { + if (n == index) + { + return handle; + } + n++; + } + + /* + * There is a device at this position, but not the one we are looking for. + * Check to see if it is a multi-function device. We need to look "behind" it + * for the other functions in that case. + */ + if ((htr = pci_read_config_byte(handle, PCI_LANESWAP_B(PCIHTR))) & 0x80) + { + /* yes, this is a multi-function device, look for more functions */ + + for (function = 1; function < 8; function++) + { + handle = PCI_HANDLE(bus, device, function); + value = swpl(pci_read_config_longword(handle, PCIIDR)); + if (value != 0xffffffff) /* device found */ + { + if (vendor_id == 0xffff || + ((PCI_VENDOR_ID(value) == vendor_id) && (PCI_DEVICE_ID(value) == device_id))) + { + if (n == index) + { + return handle; + } + n++; + } + } + } + } + } + } + } + return PCI_DEVICE_NOT_FOUND; +} + +static bool match_classcode(uint32_t handle, uint32_t classcode) +{ + uint8_t find_mask = (classcode >> 24) & 0xff; + uint32_t value = swpl(pci_read_config_longword(handle, PCICCR)); + int i; + + classcode &= 0x00ffffff; + value >>= 8; /* shift away revision id */ + + //dbg("classcode=0x%08x, value=0x%08x\r\n", classcode, value); + + for (i = 0; i < 3; i++) /* loop through mask */ + { + if ((find_mask >> i) & 1) + { + //dbg("compare 0x%02x against 0x%02x\r\n", value & 0xff, classcode & 0xff); + if ((value & 0xff) != (classcode & 0xff)) + return false; + //dbg("match\r\n"); + classcode >>= 8; + } + value >>= 8; + //dbg("value=0x%08x\r\n", value); + } + dbg("return true\r\n"); + return true; +} + +/* + * pci_find_classcode(uint32_t classcode, int index) + * + * Find the index'th pci device with a specific classcode. Bits 0-23 describe this classcode. + * + * Bits 24 - 26 describe what needs to match: 24: prog interface, 25: PCI subclass, 26: PCI base class. + * If no bits are set, there is a match for each device. + */ +int32_t pci_find_classcode(uint32_t classcode, int index) +{ + int i; + uint32_t handle; + int n = 0; + + for (i = 0; (handle = handles[i]) != -1; i++) + { + dbg("handle=0x%x, n=%d, index=%d\r\n", handle, n, index); + if (match_classcode(handle, classcode)) + { + if (n == index) + return handle; + else + n++; + } + } + + dbg("not found\r\n"); + return PCI_DEVICE_NOT_FOUND; +} + +int32_t pci_hook_interrupt(int32_t handle, void *handler, void *parameter) +{ + int i; + + // pci_interrupt_handler h = handler; + + /* + * find empty slot + */ + for (i = 0; i < MAX_INTERRUPTS; i++) + { + if (interrupts[i].handle == 0) + { + interrupts[i].handle = handle; + interrupts[i].handler = handler; + interrupts[i].parameter = (int32_t) parameter; + + return PCI_SUCCESSFUL; + } + } + return PCI_BUFFER_TOO_SMALL; +} + +int32_t pci_unhook_interrupt(int32_t handle) +{ + int i; + + for (i = 0; i < MAX_INTERRUPTS; i++) + { + if (interrupts[i].handle == handle) + { + memset(&interrupts[i], 0, sizeof(struct pci_interrupt)); + + return PCI_SUCCESSFUL; + } + } + return PCI_DEVICE_NOT_FOUND; +} + +/* + * Not implemented PCI_BIOS functions + */ + +uint8_t pci_fast_read_config_byte(int32_t handle, uint16_t reg) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +uint16_t pci_fast_read_config_word(int32_t handle, uint16_t reg) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +uint32_t pci_fast_read_config_longword(int32_t handle, uint16_t reg) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +int32_t pci_special_cycle(uint16_t bus, uint32_t data) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +int32_t pci_get_routing(int32_t handle) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +int32_t pci_set_interrupt(int32_t handle) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +int32_t pci_get_card_used(int32_t handle, uint32_t *address) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +int32_t pci_set_card_used(int32_t handle, uint32_t *callback) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +int32_t pci_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +int32_t pci_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +int32_t pci_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +uint8_t pci_fast_read_mem_byte(int32_t handle, uint32_t offset) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +uint16_t pci_fast_read_mem_word(int32_t handle, uint32_t offset) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +uint32_t pci_fast_read_mem_longword(int32_t handle, uint32_t offset) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +int32_t pci_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +int32_t pci_write_mem_word(int32_t handle, uint32_t offset, uint16_t val) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +int32_t pci_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +int32_t pci_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +int32_t pci_read_io_word(int32_t handle, uint32_t offset, uint16_t *address) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +int32_t pci_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +uint8_t pci_fast_read_io_byte(int32_t handle, uint32_t offset) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +uint16_t pci_fast_read_io_word(int32_t handle, uint32_t offset) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +uint32_t pci_fast_read_io_longword(int32_t handle, uint32_t offset) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +int32_t pci_write_io_byte(int32_t handle, uint32_t offset, uint16_t val) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +int32_t pci_write_io_word(int32_t handle, uint32_t offset, uint16_t val) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +int32_t pci_write_io_longword(int32_t handle, uint32_t offset, uint32_t val) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +int32_t pci_get_machine_id(void) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +int32_t pci_get_pagesize(void) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +int32_t pci_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer) +{ + return PCI_FUNC_NOT_SUPPORTED; +} +int32_t pci_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +int32_t pci_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +int32_t pci_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer) +{ + return PCI_FUNC_NOT_SUPPORTED; +} + +/* + * pci_device_config() + * + * Map card resources, adjust BARs and fill resource descriptors + */ +static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function) +{ + uint32_t address; + int32_t handle; + int16_t index = - 1; + uint8_t il; + struct pci_rd *descriptors; + int i; + uint32_t value; + static uint32_t mem_address = PCI_MEMORY_OFFSET; + static uint32_t io_address = PCI_IO_OFFSET; + uint16_t cr; + + /* + * should make compiler happy (these are used only in debug builds) + */ + (void) value; + (void) il; + + /* determine pci handle from bus, device + function number */ + handle = PCI_HANDLE(bus, device, function); + + /* find index into resource descriptor table for handle */ + index = pci_handle2index(handle); + + if (index == -1) + { + dbg("cannot find index for handle %d\r\n", handle); + return; + } + + /* + * disable device + */ + + cr = swpw(pci_read_config_word(handle, PCI_LANESWAP_W(PCICR))); + cr &= ~3; /* disable device response to address */ + pci_write_config_word(handle, PCI_LANESWAP_W(PCICR), swpw(cr)); + + int barnum = 0; + + descriptors = resource_descriptors[index]; + for (i = 0; i < 6 * 4; i += 4) /* for all bars */ + { + /* + * write all bits of BAR[i] + */ + pci_write_config_longword(handle, PCIBAR0 + i, 0xffffffff); + + /* + * read back value to see which bits have been set + */ + address = swpl(pci_read_config_longword(handle, PCIBAR0 + i)); + + if (address) /* is bar in use? */ + { + /* + * resource descriptor for this device + */ + struct pci_rd *rd = &descriptors[barnum]; + + dbg("address = %08x\r\n", address); + if (IS_PCI_MEM_BAR(address)) + { + /* adjust base address to card's alignment requirements */ + size_t size = ~(address & 0xfffffff0) + 1; + dbg("device 0x%02x: BAR[%d] requests %ld kBytes of memory\r\n", handle, i / 4, size / 1024); + + /* calculate a valid map adress with alignment requirements */ + address = (mem_address + size - 1) & ~(size - 1); + + /* write it to the BAR */ + pci_write_config_longword(handle, PCIBAR0 + i, swpl(address)); + + /* read it back, just to be sure */ + value = swpl(pci_read_config_longword(handle, PCIBAR0 + i)) & ~1; + + dbg("set PCIBAR%d on device 0x%02x to 0x%08x\r\n", + i / 4, handle, value); + + /* fill resource descriptor */ + rd->next = sizeof(struct pci_rd); + rd->flags = 0 | FLG_32BIT | FLG_16BIT | FLG_8BIT | ORD_INTEL_LS; /* little endian, lane swapped */ + rd->start = address; + rd->length = size; + rd->offset = 0; + rd->dmaoffset = 0; + + /* adjust memory adress for next turn */ + mem_address += size; + + cr |= 2; + + /* index to next unused resource descriptor */ + barnum++; + } + else if (IS_PCI_IO_BAR(address)) /* same as above for I/O resources */ + { + int size = ~(address & 0xfffffffc) + 1; + dbg("device 0x%x: BAR[%d] requests %d bytes of I/O space\r\n", handle, i, size); + + address = (io_address + size - 1) & ~(size - 1); + pci_write_config_longword(handle, PCIBAR0 + i, swpl(address | 1)); + value = swpl(pci_read_config_longword(handle, PCIBAR0 + i)); + + dbg("set PCIBAR%d on device 0x%02x to 0x%08x\r\n", + i / 4, handle, value); + + rd->next = sizeof(struct pci_rd); + rd->flags = FLG_IO | FLG_8BIT | FLG_16BIT | FLG_32BIT | 2; + rd->start = address; + rd->offset = 0; + rd->length = size; + rd->dmaoffset = 0; + + io_address += size; + + cr |= 1; + + barnum++; + } + } + } + + /* + * check if we have an expansion ROM + */ + + /* + * write all bits of PCIERBAR + */ + pci_write_config_longword(handle, PCIERBAR, 0xffffffff); + + /* + * read back value to see which bits have been set + */ + address = swpl(pci_read_config_longword(handle, PCIERBAR)); + if (address & 1) + { + /* + * there is a ROM + */ + + struct pci_rd *rd = &descriptors[barnum]; + int size = ~(address & ~0x7ff) + 1; + + dbg("expansion ROM requested size=0x%08x\r\n", size); + dbg("device 0x%02x: requests %ld kBytes for expansion ROM\r\n", handle, size / 1024); + + /* expansion ROM active and mapped */ + + /* calculate a valid map adress with alignment requirements */ + address = (mem_address + size - 1) & ~(size - 1); + + /* write it to PCIERBAR and enable ROM */ + pci_write_config_longword(handle, PCIERBAR, swpl(address | 1)); + dbg("set PCIERBAR on device 0x%02x to 0x%08x\r\n", handle, address | 1); + + /* read value back just to be sure */ + dbg("PCIERBAR = %p\r\n", swpl(pci_read_config_longword(handle, PCIERBAR))); + + + rd->next = sizeof(struct pci_rd); + rd->flags = FLG_ROM | FLG_8BIT | FLG_16BIT | FLG_32BIT | 2; + rd->start = address; + rd->offset = 0; + rd->length = size; + rd->dmaoffset = 0; + + cr |= 2; /* enable Memory */ + mem_address += size; + barnum++; + } + + /* mark end of resource chain */ + if (barnum > 0) + descriptors[barnum - 1].flags |= FLG_LAST; + + /* check if device requests an interrupt */ + il = pci_read_config_byte(handle, PCI_LANESWAP_B(PCIIPR)); + dbg("device requests interrupts on interrupt pin %d\r\n", il); + + /* disable interrupt on PCI device */ + + cr |= PCICR_INT_DISABLE; + + /* + * enable device memory or I/O access + */ + pci_write_config_word(handle, PCI_LANESWAP_W(PCICR), swpw(cr)); +} + +static void pci_bridge_config(uint16_t bus, uint16_t device, uint16_t function) +{ + int32_t handle; + + if (function != 0) + { + err("trying to configure a multi-function bridge. Cancelled\r\n"); + return; + } + handle = PCI_HANDLE(bus, device, function); + dbg("handle=%d\r\n", handle); + + pci_write_config_longword(handle, PCIBISTR, MCF_PCI_PCICR1_CACHELINESIZE(8) | + MCF_PCI_PCICR1_LATTIMER(0x20)); + pci_write_config_longword(handle, PCIBAR0, swpl(0x80000000)); + pci_write_config_longword(handle, PCIBAR1, 0x0); + pci_write_config_word(handle, PCI_LANESWAP_W(PCICR), swpw( + (1 << 1) /* memory space */ + | (1 << 2) /* bus master */ + | (1 << 4) /* memory write and invalidate */ + | (1 << 6) /* parity errors */ + | (1 << 8) /* SERR */ + | (1 << 9) /* fast back-to-back */ + )); +} + +/* + * scan PCI bus and display devices found. Create a handle for each device and call pci_device_config() for it + */ +void pci_scan(void) +{ + int16_t handle; + int16_t index = 0; + + xprintf("\r\nPCI bus scan...\r\n\r\n"); + xprintf(" Bus| Dev|Func|Vndr|D-ID|Hndl|\r\n"); + xprintf("----+----+----+----+----+----+\r\n"); + + handle = pci_find_device(0x0, 0xFFFF, index); + while (handle > 0) + { + uint32_t value; + + value = swpl(pci_read_config_longword(handle, PCIIDR)); + + xprintf(" %02x | %02x | %02x |%04x|%04x|%04x| %s (0x%02x, 0x%04x)\r\n", + PCI_BUS_FROM_HANDLE(handle), + PCI_DEVICE_FROM_HANDLE(handle), + PCI_FUNCTION_FROM_HANDLE(handle), + PCI_VENDOR_ID(value), PCI_DEVICE_ID(value), + handle, + device_class(pci_read_config_byte(handle, PCI_LANESWAP_B(PCICCR))), + pci_read_config_byte(handle, PCI_LANESWAP_B(PCICCR)), + pci_read_config_word(handle, PCI_LANESWAP_W(PCICCR))); + + /* save handle to index value so that we'll be able to later find our resources */ + handles[index] = handle; + handles[index + 1] = -1; + + if (PCI_VENDOR_ID(value) != 0x1057 && PCI_DEVICE_ID(value) != 0x5806) /* do not configure bridge */ + { + /* configure memory and I/O for card */ + pci_device_config(PCI_BUS_FROM_HANDLE(handle), + PCI_DEVICE_FROM_HANDLE(handle), + PCI_FUNCTION_FROM_HANDLE(handle)); + } + else + { + dbg("\r\n"); + pci_bridge_config(PCI_BUS_FROM_HANDLE(handle), + PCI_DEVICE_FROM_HANDLE(handle), + PCI_FUNCTION_FROM_HANDLE(handle)); + } + dbg("\r\n"); + handle = pci_find_device(0x0, 0xFFFF, ++index); + } + xprintf("\r\n...finished\r\n"); +} + +/* start of PCI initialization code */ +void init_eport(void) +{ + /* configure IRQ1-7 pins on EPORT falling edge triggered */ + MCF_EPORT_EPPAR = MCF_EPORT_EPPAR_EPPA7(MCF_EPORT_EPPAR_FALLING) | + MCF_EPORT_EPPAR_EPPA6(MCF_EPORT_EPPAR_FALLING) | + #if defined(MACHINE_FIREBEE) /* irq5 level triggered on FireBee */ + MCF_EPORT_EPPAR_EPPA5(MCF_EPORT_EPPAR_LEVEL) | + #elif defined(MACHINE_M5484LITE) + MCF_EPORT_EPPAR_EPPA5(MCF_EPORT_EPPAR_FALLING) | + #endif /* MACHINE_FIREBEE */ + MCF_EPORT_EPPAR_EPPA4(MCF_EPORT_EPPAR_FALLING) | + MCF_EPORT_EPPAR_EPPA3(MCF_EPORT_EPPAR_FALLING) | + MCF_EPORT_EPPAR_EPPA2(MCF_EPORT_EPPAR_FALLING) | + MCF_EPORT_EPPAR_EPPA1(MCF_EPORT_EPPAR_FALLING); + + MCF_EPORT_EPDDR = 0; /* clear data direction register. All pins as input */ + MCF_EPORT_EPFR = -1; /* clear all EPORT interrupt flags */ + MCF_EPORT_EPIER = 0xfe; /* enable all EPORT interrupts (for now) */ +} + +void init_xlbus_arbiter(void) +{ + uint8_t clock_ratio; + + /* setup XL bus arbiter */ + clock_ratio = (MCF_PCI_PCIGSCR >> 24) & 0x07; + if (clock_ratio == 4) + { + MCF_XLB_XARB_CFG = MCF_XLB_XARB_CFG_BA | + MCF_XLB_XARB_CFG_DT | + MCF_XLB_XARB_CFG_AT | + MCF_XLB_XARB_CFG_PLDIS; + } + else + { + MCF_XLB_XARB_CFG = MCF_XLB_XARB_CFG_BA | + MCF_XLB_XARB_CFG_DT | + MCF_XLB_XARB_CFG_AT; + } + + /* + * set arbitration priorities for XL bus masters + * + * M0 = ColdFire core + * M2 = Multichannel DMA + * M3 = PCI target interface + */ +#if 0 + MCF_XLB_XARB_PRIEN = MCF_XLB_XARB_PRIEN_M0 | /* activate programmed priority for Coldfire core */ + MCF_XLB_XARB_PRIEN_M2 | /* activate programmed priority for Multichannel DMA */ + MCF_XLB_XARB_PRIEN_M3; /* activate programmed priority for PCI target interface */ + MCF_XLB_XARB_PRI = MCF_XLB_XARB_PRI_M0P(7) | /* Coldfire core gets lowest */ + MCF_XLB_XARB_PRI_M2P(5) | /* Multichannel DMA mid priority */ + MCF_XLB_XARB_PRI_M3P(3); /* PCI target interface is highest priority */ +#endif +} + +void init_pci(void) +{ + int res; + + xprintf("initializing PCI bridge:\r\n"); + + (void) res; /* for now */ + + init_eport(); + init_xlbus_arbiter(); + + MCF_PCI_PCIGSCR |= MCF_PCI_PCIGSCR_PR; /* reset PCI devices */ + + + /* + * setup the PCI arbiter + */ + MCF_PCIARB_PACR = MCF_PCIARB_PACR_INTMPRI /* internal master priority: high */ + | MCF_PCIARB_PACR_EXTMPRI(0x0) /* external master priority: high */ + | MCF_PCIARB_PACR_INTMINTEN /* enable "internal master broken" interrupt */ + | MCF_PCIARB_PACR_EXTMINTEN(0x0f); /* enable "external master broken" interrupt */ + +#if defined(MACHINE_FIREBEE) + MCF_PAD_PAR_PCIBG = MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST | + MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO | + MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 | + MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 | + MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0; + MCF_PAD_PAR_PCIBR = MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4 | + MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO | + MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 | + MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 | + MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0; +#elif defined(MACHINE_M5484LITE) + MCF_PAD_PAR_PCIBG = MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0 | + MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 | + MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 | + MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3 | + MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4; /* enable all PCI bus grant and bus requests on the LITE board */ + MCF_PAD_PAR_PCIBR = MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0 | + MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 | + MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 | + MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3 | + MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4; +#endif /* MACHINE_FIREBEE */ + + MCF_PCI_PCISCR = MCF_PCI_PCISCR_M | /* memory access control enabled */ + MCF_PCI_PCISCR_B | /* bus master enabled */ + MCF_PCI_PCISCR_M | /* mem access enable */ + MCF_PCI_PCISCR_MA | /* clear master abort error */ + MCF_PCI_PCISCR_MW | /* memory write and invalidate enabled */ + MCF_PCI_PCISCR_PER; /* assert PERR on parity error */ + + + /* Setup burst parameters */ + MCF_PCI_PCICR1 = MCF_PCI_PCICR1_CACHELINESIZE(8) | + MCF_PCI_PCICR1_LATTIMER(0x20); /* TODO: test increased latency timer */ + + MCF_PCI_PCICR2 = MCF_PCI_PCICR2_MINGNT(1) | + MCF_PCI_PCICR2_MAXLAT(32); + + // MCF_PCI_PCICR2 = 0; /* this is what Linux does */ + + /* error signaling */ + + MCF_PCI_PCIICR = MCF_PCI_PCIICR_TAE | /* target abort enable */ + MCF_PCI_PCIICR_IAE; /* initiator abort enable */ + + // MCF_PCI_PCIICR = 0; /* this is what Linux does */ + + MCF_PCI_PCIGSCR |= MCF_PCI_PCIGSCR_SEE | /* system error interrupt enable */ + MCF_PCI_PCIGSCR_PEE; /* parity error interrupt enable */ + /* Configure Initiator Windows */ + + /* + * initiator window 0 base / translation adress register + * used for PCI memory access + */ + MCF_PCI_PCIIW0BTAR = ((PCI_MEMORY_OFFSET + ((PCI_MEMORY_SIZE - 1) >> 8)) & 0xffff0000) + | (PCI_MEMORY_OFFSET >> 16); + + NOP(); + dbg("PCIIW0BTAR=0x%08x\r\n", MCF_PCI_PCIIW0BTAR); + + /* + * initiator window 1 base / translation adress register + * used for PCI I/O access + */ + MCF_PCI_PCIIW1BTAR = ((PCI_IO_OFFSET + ((PCI_IO_SIZE - 1) >> 8)) & 0xffff0000) + | (PCI_IO_OFFSET >> 16); + NOP(); + /* initiator window 2 base / translation address register */ + MCF_PCI_PCIIW2BTAR = 0L; /* not used */ + NOP(); + /* initiator window configuration register */ + MCF_PCI_PCIIWCR = MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE | + MCF_PCI_PCIIWCR_WINCTRL1_IO | + MCF_PCI_PCIIWCR_WINCTRL0_E | + MCF_PCI_PCIIWCR_WINCTRL1_E; + NOP(); + + /* + * Initialize target control register. + * Used when an external bus master accesses the Coldfire PCI as target + */ + MCF_PCI_PCIBAR0 = 0x40000000; /* 256 kB window */ + MCF_PCI_PCITBATR0 = (uint32_t) &_MBAR[0] | MCF_PCI_PCITBATR0_EN; /* target base address translation register 0 */ + MCF_PCI_PCIBAR1 = 0; /* 1GB window */ + MCF_PCI_PCITBATR1 = MCF_PCI_PCITBATR1_EN; + + /* reset PCI devices */ + MCF_PCI_PCIGSCR &= ~MCF_PCI_PCIGSCR_PR; + do { NOP(); } while (MCF_PCI_PCIGSCR & MCF_PCI_PCIGSCR_PR); /* wait until reset finished */ + wait(200); + + xprintf("finished\r\n"); + + /* initialize/clear resource descriptor table */ + memset(&resource_descriptors, 0, NUM_CARDS * NUM_RESOURCES * sizeof(struct pci_rd)); + + /* initialize/clear handles array */ + memset(handles, 0, NUM_CARDS * sizeof(int32_t)); + + /* initialize/clear interrupts array */ + memset(interrupts, 0, MAX_INTERRUPTS * sizeof(struct pci_interrupt)); + + /* + * give devices a chance to come up befor attempting to configure them, + * necessary to properly detect the FireBee USB chip + */ + wait_ms(400); + + /* + * do normal initialization + */ + pci_scan(); +} + + +#ifdef DEBUG_PCI +void pci_print_device_abilities(int32_t handle) +{ + uint16_t value; + uint16_t saved_value; + + saved_value = pci_read_config_word(handle, PCICSR); + pci_write_config_word(handle, PCICSR, 0xffff); + value = swpw(pci_read_config_word(handle, PCICSR)); + dbg("IO: %1d MEM: %1d MSTR:%1d SPCC: %1d MEMW: %1d VGAS: %1d PERR: %1d STEP: %1d SERR: %1d FBTB: %1d\r\n", + value & PCICSR_IO ? 1 : 0, + value & PCICSR_MEMORY ? 1 : 0, + value & PCICSR_MASTER ? 1 : 0, + value & PCICSR_SPECIAL ? 1 : 0, + value & PCICSR_MEMWI ? 1 : 0, + value & PCICSR_VGA_SNOOP ? 1 : 0, + value & PCICSR_PERR ? 1 : 0, + value & PCICSR_STEPPING ? 1 : 0, + value & PCICSR_SERR ? 1 : 0, + value & PCICSR_FAST_BTOB_E ? 1 : 0); + pci_write_config_word(handle, PCICSR, saved_value); +} + + +void pci_print_device_config(int32_t handle) +{ + uint16_t value; + + value = swpw(pci_read_config_word(handle, PCICSR + 2)); + dbg("66M: %1d UDF: %1d FB2B:%1d PERR: %1d TABR: %1d DABR: %1d SERR: %1d PPER: %1d\r\n", + value & PCICSR_66MHZ ? 1 : 0, + value & PCICSR_UDF ? 1 : 0, + value & PCICSR_FAST_BTOB ? 1 : 0, + value & PCICSR_DPARITY_ERROR ? 1 : 0, + value & PCICSR_T_ABORT_S ? 1 : 0, + value & PCICSR_T_ABORT_R ? 1 : 0, + value & PCICSR_M_ABORT_R ? 1 : 0, + value & PCICSR_S_ERROR_S ? 1 : 0, + value & PCICSR_PARITY_ERR ? 1 : 0); +} +#endif /* DEBUG_PCI */ + + diff --git a/pci/pci_errata.c b/pci/pci_errata.c new file mode 100755 index 0000000..52ca707 --- /dev/null +++ b/pci/pci_errata.c @@ -0,0 +1,66 @@ +#include "pci_errata.h" +#include "pci.h" +#include + +#include "debug.h" + +__attribute__((aligned(16))) void chip_errata_135(void) +{ + /* + * Errata type: Silicon + * Affected component: PCI + * Description: When core PCI transactions that involve writes to configuration or I/O space + * are followed by a core line access to line addresses 0x4 and 0xC, core access + * to the XL bus can hang. + * Workaround: Prevent PCI configuration and I/O writes from being followed by the described + * line access by the core by generating a known good XL bus transaction after + * the PCI transaction. + * Create a dummy function which is called immediately after each of the affected + * transactions. There are three requirements for this dummy function. + * 1. The function must be aligned to a 16-byte boundary. + * 2. The function must contain a dummy write to a location on the XL bus, + * preferably one with no side effects. + * 3. The function must be longer than 32 bytes. If it is not, the function should + * be padded with 16- or 48-bit TPF instructions placed after the end of + * the function (after the RTS instruction) such that the length is longer + * than 32 bytes. + */ + + __asm__ __volatile( + " .extern __MBAR \n\t" + " clr.l d0 \n\t" + " move.l d0,__MBAR+0xF0C \n\t" /* Must use direct addressing. write to EPORT module */ + /* xlbus -> slavebus -> eport, writing '0' to register */ + /* has no effect */ + " rts \n\t" + " tpf.l #0x0 \n\t" + " tpf.l #0x0 \n\t" + " tpf.l #0x0 \n\t" + " tpf.l #0x0 \n\t" + " tpf.l #0x0 \n\t" + ::: "d0", "memory"); +} + +void chip_errata_055(int32_t handle) +{ + uint32_t dummy; + + return; /* test */ + + /* initiate PCI configuration access to device */ + MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */ + MCF_PCI_PCICAR_BUSNUM(3) | /* note: invalid bus number */ + MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | /* device number, devices 0 - 9 are reserved */ + MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | /* function number */ + MCF_PCI_PCICAR_DWORD(0); + + /* issue a dummy read to an unsupported bus number (will fail) */ + dummy = * (volatile uint32_t *) PCI_IO_OFFSET; /* access device */ + + /* silently clear the PCI errors we produced just now */ + MCF_PCI_PCIISR = 0xffffffff; /* clear all errors */ + MCF_PCI_PCIGSCR = MCF_PCI_PCIGSCR_PE | MCF_PCI_PCIGSCR_SE; + + (void) dummy; +} + diff --git a/pci/pci_wrappers.S b/pci/pci_wrappers.S new file mode 100644 index 0000000..faf166e --- /dev/null +++ b/pci/pci_wrappers.S @@ -0,0 +1,469 @@ +/* + * pci.S + * + * Purpose: PCI configuration for the Coldfire builtin PCI bridge. + * + * Notes: + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 08.05.2014 + * Author: David Galvez + */ + +.global _wrapper_find_pci_device +.global _wrapper_find_pci_classcode + +.global _wrapper_read_config_longword +.global _wrapper_read_config_word +.global _wrapper_read_config_byte + +.global _wrapper_fast_read_config_byte +.global _wrapper_fast_read_config_word +.global _wrapper_fast_read_config_longword + +.global _wrapper_write_config_longword +.global _wrapper_write_config_word +.global _wrapper_write_config_byte + +.global _wrapper_get_resource +.global _wrapper_hook_interrupt +.global _wrapper_unhook_interrupt + +.global _wrapper_special_cycle +.global _wrapper_get_routing +.global _wrapper_set_interrupt +.global _wrapper_get_resource +.global _wrapper_get_card_used +.global _wrapper_set_card_used + +.global _wrapper_read_mem_byte +.global _wrapper_read_mem_word +.global _wrapper_read_mem_longword + +.global _wrapper_fast_read_mem_byte +.global _wrapper_fast_read_mem_word +.global _wrapper_fast_read_mem_longword + +.global _wrapper_write_mem_byte +.global _wrapper_write_mem_word +.global _wrapper_write_mem_longword + +.global _wrapper_read_io_byte +.global _wrapper_read_io_word +.global _wrapper_read_io_longword + +.global _wrapper_fast_read_io_byte +.global _wrapper_fast_read_io_word +.global _wrapper_fast_read_io_longword + +.global _wrapper_write_io_byte +.global _wrapper_write_io_word +.global _wrapper_write_io_longword + +.global _wrapper_get_machine_id +.global _wrapper_get_pagesize + +.global _wrapper_virt_to_bus +.global _wrapper_bus_to_virt +.global _wrapper_virt_to_phys +.global _wrapper_phys_to_virt + + +_wrapper_find_pci_device: + move.l D1,-(SP) // index + move.l D0,-(SP) // Vendor ID + move.l #16,D1 + lsr.l D1,D0 + move.l D0,-(SP) // Device ID + jsr _pci_find_device + add.l #12,SP + rts + +_wrapper_find_pci_classcode: + move.l D1,-(SP) // index + move.l D0,-(SP) // ID + jsr _pci_find_classcode + addq.l #8,SP + rts + +_wrapper_read_config_byte: + move.l A0,-(SP) // pointer to space for read data + move.l D1,-(SP) // PCI register + move.l D0,-(SP) // handle + jsr _pci_read_config_byte + move.l 8(SP),A0 // PCI_BIOS expects value in memory + move.l D0,(A0) + add.l #12,SP + move.l #0,D0 + rts + +_wrapper_read_config_word: + move.l A0,-(SP) // pointer to space for read data + move.l D1,-(SP) // PCI register + move.l D0,-(SP) // handle + jsr _pci_read_config_word + move.l 8(SP),A0 // little to big endian + move.l D0,(A0) + mvz.b 1(A0),D0 + lsl.l #8,D0 + move.b (A0),D0 + move.l D0,(A0) // PCI_BIOS expects value in memory, not in D0 + add.l #12,SP + move.l #0,D0 + rts + +_wrapper_read_config_longword: + move.l A0,-(SP) // pointer to space for read data + move.l D1,-(SP) // PCI register + move.l D0,-(SP) // handle + jsr _pci_read_config_longword + move.l 8(SP),A0 // little to big endian + move.l D0,(A0) + mvz.b 3(A0),D0 + lsl.l #8,D0 + move.b 2(A0),D0 + lsl.l #8,D0 + move.b 1(A0),D0 + lsl.l #8,D0 + move.b (A0),D0 + move.l D0,(A0) // PCI_BIOS expects value in memory, not in D0 + add.l #12,SP + move.l #0,D0 + rts + +/* Not implemented */ +_wrapper_fast_read_config_byte: + move.l D1,-(SP) // PCI register + move.l D0,-(SP) // handle + jsr _pci_fast_read_config_byte + addq.l #8,SP + rts + +/* Not implemented */ +_wrapper_fast_read_config_word: + move.l D1,-(SP) // PCI register + move.l D0,-(SP) // handle + jsr _pci_fast_read_config_word + addq.l #8,SP + rts + +/* Not implemented */ +_wrapper_fast_read_config_longword: + move.l D1,-(SP) // PCI register + move.l D0,-(SP) // handle + jsr _pci_fast_read_config_longword + addq.l #8,SP + rts + +_wrapper_write_config_byte: + move.l D2,-(SP) // data to write + move.l D1,-(SP) // PCI register + move.l D0,-(SP) // handle + jsr _pci_write_config_byte + add.l #12,SP + rts + +_wrapper_write_config_word: + move.l D0,-(SP) // make data little endian + moveq #0,D1 + move.w D2,D1 + lsr.l #8,D1 + asl.l #8,D2 + or.l D1,D2 + move.l (SP)+,D0 + move.l D2,-(SP) // data to write + move.l D1,-(SP) // PCI register + move.l D0,-(SP) // handle + jsr _pci_write_config_word + add.l #12,SP + rts + +_wrapper_write_config_longword: + move.l D0,-(SP) + move.l D2,D0 // make data little endian + lsr.l #8,D0 + asl.l #8,D2 + and.l #0x00FF00FF,D0 + and.l #0xFF00FF00,D2 + or.l D0,D2 + swap D2 + move.l (SP)+,D0 + move.l D2,-(SP) // data to write + move.l D1,-(SP) // PCI register + move.l D0,-(SP) // handle + jsr _pci_write_config_longword + add.l #12,SP + rts + +_wrapper_hook_interrupt: + move.l A1,-(SP) // parameter for interrupt handler + move.l A0,-(SP) // pointer to interrupt handler + move.l D0,-(SP) // handle + jsr _pci_hook_interrupt + add.l #12,SP + rts + +_wrapper_unhook_interrupt: + move.l D0,-(SP) // handle + jsr _pci_unhook_interrupt + addq.l #4,SP + rts + +/* Not implemented */ +_wrapper_special_cycle: + move.l D1,-(SP) // special cycle data + move.l D0,-(SP) // bus number + jsr _pci_special_cycle + addq.l #8,SP + rts + +/* Not implemented */ +_wrapper_get_routing: + move.l D0,-(SP) // handle + jsr _pci_get_routing + addq.l #4,SP + rts + +/* Not implemented */ +_wrapper_set_interrupt: + move.l D1,-(SP) // mode + move.l D0,-(SP) // handle + jsr _pci_set_interrupt + addq.l #8,SP + rts + +_wrapper_get_resource: + move.l D0,-(SP) // handle + jsr _pci_get_resource + addq.l #4,SP + rts + +/* Not implemented */ +_wrapper_get_card_used: + move.l D1,-(SP) // address + move.l D0,-(SP) // handle + jsr _pci_get_card_used + addq.l #8,SP + rts + +/* Not implemented */ +_wrapper_set_card_used: + move.l A0,-(SP) // callback + move.l D0,-(SP) // handle + jsr _pci_set_card_used + addq.l #8,SP + rts + +/* Not implemented */ +_wrapper_read_mem_byte: + move.l A0,-(SP) // pointer to data in memory + move.l D1,-(SP) // address to access (in PCI memory address space) + move.l D0,-(SP) // handle + jsr _pci_read_mem_byte + add.l #12,SP + rts + +/* Not implemented */ +_wrapper_read_mem_word: + move.l A0,-(SP) // pointer to data in memory + move.l D1,-(SP) // address to access (in PCI memory address space) + move.l D0,-(SP) // handle + jsr _pci_read_mem_word + add.l #12,SP + rts + +/* Not implemented */ +_wrapper_read_mem_longword: + move.l A0,-(SP) // pointer to data in memory + move.l D1,-(SP) // address to access (in PCI memory address space) + move.l D0,-(SP) // handle + jsr _pci_read_mem_longword + add.l #12,SP + rts + +/* Not implemented */ +_wrapper_fast_read_mem_byte: + move.l D1,-(SP) // address to access (in PCI memory address space) + move.l D0,-(SP) // handle + jsr _pci_read_mem_byte + addq.l #8,SP + rts + +/* Not implemented */ +_wrapper_fast_read_mem_word: + move.l D1,-(SP) // address to access (in PCI memory address space) + move.l D0,-(SP) // handle + jsr _pci_read_mem_word + addq.l #8,SP + rts + +/* Not implemented */ +_wrapper_fast_read_mem_longword: + move.l D1,-(SP) // address to access (in PCI memory address space) + move.l D0,-(SP) // handle + jsr _pci_read_mem_longword + addq.l #8,SP + rts + +/* Not implemented */ +_wrapper_write_mem_byte: + move.l D2,-(SP) // data to write + move.l D1,-(SP) // address to access (in PCI memory address space) + move.l D0,-(SP) // handle + jsr _pci_write_mem_byte + add.l #12,SP + rts + +/* Not implemented */ +_wrapper_write_mem_word: + move.l D2,-(SP) // data to write + move.l D1,-(SP) // address to access (in PCI memory address space) + move.l D0,-(SP) // handle + jsr _pci_write_mem_word + add.l #12,SP + rts + +/* Not implemented */ +_wrapper_write_mem_longword: + move.l D2,-(SP) // data to write + move.l D1,-(SP) // address to access (in PCI memory address space) + move.l D0,-(SP) // handle + jsr _pci_write_mem_longword + add.l #12,SP + rts + +/* Not implemented */ +_wrapper_read_io_byte: + move.l A0,-(SP) // pointer to data in memory + move.l D1,-(SP) // address to access (in PCI I/O address space) + move.l D0,-(SP) // handle + jsr _pci_read_io_byte + add.l #12,SP + rts + +/* Not implemented */ +_wrapper_read_io_word: + move.l A0,-(SP) // pointer to data in memory + move.l D1,-(SP) // address to access (in PCI I/O address space) + move.l D0,-(SP) // handle + jsr _pci_read_io_word + add.l #12,SP + rts + +/* Not implemented */ +_wrapper_read_io_longword: + move.l A0,-(SP) // pointer to data in memory + move.l D1,-(SP) // address to access (in PCI I/O address space) + move.l D0,-(SP) // handle + jsr _pci_read_io_longword + add.l #12,SP + rts + +/* Not implemented */ +_wrapper_fast_read_io_byte: + move.l D1,-(SP) // address to access (in PCI I/O address space) + move.l D0,-(SP) // handle + jsr _pci_read_io_byte + addq.l #8,SP + rts + +/* Not implemented */ +_wrapper_fast_read_io_word: + move.l D1,-(SP) // address to access (in PCI I/O address space) + move.l D0,-(SP) // handle + jsr _pci_read_io_word + addq.l #8,SP + rts + +/* Not implemented */ +_wrapper_fast_read_io_longword: + move.l D1,-(SP) // address to access (in PCI I/O address space) + move.l D0,-(SP) // handle + jsr _pci_read_io_longword + addq.l #8,SP + rts + +/* Not implemented */ +_wrapper_write_io_byte: + move.l D2,-(SP) // data to write + move.l D1,-(SP) // address to access (in PCI I/O address space) + move.l D0,-(SP) // handle + jsr _pci_write_io_byte + add.l #12,SP + rts + +/* Not implemented */ +_wrapper_write_io_word: + move.l D2,-(SP) // data to write + move.l D1,-(SP) // address to access (in PCI I/O address space) + move.l D0,-(SP) // handle + jsr _pci_write_io_word + add.l #12,SP + rts + +/* Not implemented */ +_wrapper_write_io_longword: + move.l D2,-(SP) // data to write + move.l D1,-(SP) // address to access (in PCI I/O address space) + move.l D0,-(SP) // handle + jsr _pci_write_io_longword + add.l #12,SP + rts + +/* Not implemented */ +_wrapper_get_machine_id: + jsr _pci_get_machine_id + rts + +/* Not implemented */ +_wrapper_get_pagesize: + jsr _pci_get_pagesize + rts + +/* Not implemented */ +_wrapper_virt_to_bus: + move.l A0,-(SP) // ptr + move.l D1,-(SP) // address in virtual CPU space + move.l D0,-(SP) // handle + jsr _pci_virt_to_bus + add.l #12,SP + rts + +/* Not implemented */ +_wrapper_bus_to_virt: + move.l A0,-(SP) // ptr + move.l D1,-(SP) // PCI bus address + move.l D0,-(SP) // handle + jsr _pci_bus_to_virt + add.l #12,SP + rts + +/* Not implemented */ +_wrapper_virt_to_phys: + move.l A0,-(SP) // ptr + move.l D0,-(SP) // address in virtual CPU space + jsr _pci_virt_to_phys + addq.l #8,SP + rts + +/* Not implemented */ +_wrapper_phys_to_virt: + move.l A0,-(SP) // ptr + move.l D0,-(SP) // physical CPU address + jsr _pci_phys_to_virt + addq.l #8,SP + rts diff --git a/radeon/i2c-algo-bit.c b/radeon/i2c-algo-bit.c new file mode 100644 index 0000000..aa4ee13 --- /dev/null +++ b/radeon/i2c-algo-bit.c @@ -0,0 +1,474 @@ +/* ------------------------------------------------------------------------- */ +/* i2c-algo-bit.c i2c driver algorithms for bit-shift adapters */ +/* ------------------------------------------------------------------------- */ +/* Copyright (C) 1995-2000 Simon G. Vogl + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ +/* ------------------------------------------------------------------------- */ + +/* With some changes from Frodo Looijaard , Kyösti Mälkki + and Jean Delvare */ + +#include "wait.h" +#include "i2c.h" +#include "i2c-algo-bit.h" + +#ifndef NULL +#define NULL ((void *)0) +#endif + +// #define DEBUG +#include "debug.h" + +extern void start_timeout(void); +extern int end_timeout(long msec); + +/* --- setting states on the bus with the right timing: --------------- */ + +#define setsda(adap,val) adap->setsda(adap->data, val) +#define setscl(adap,val) adap->setscl(adap->data, val) +#define getsda(adap) adap->getsda(adap->data) +#define getscl(adap) adap->getscl(adap->data) + +static inline void sdalo(struct i2c_algo_bit_data *adap) +{ + setsda(adap,0); + wait_us(adap->udelay); +} + +static inline void sdahi(struct i2c_algo_bit_data *adap) +{ + setsda(adap,1); + wait_us(adap->udelay); +} + +static inline void scllo(struct i2c_algo_bit_data *adap) +{ + setscl(adap,0); + wait_us(adap->udelay); +} + +/* + * Raise scl line, and do checking for delays. This is necessary for slower + * devices. + */ +static inline int sclhi(struct i2c_algo_bit_data *adap) +{ + setscl(adap, 1); + /* Not all adapters have scl sense line... */ + if(adap->getscl == NULL ) + { + wait_us(adap->udelay); + return 0; + } + start_timeout(); + while (! getscl(adap)) + { + /* the hw knows how to read the clock line, + * so we wait until it actually gets high. + * This is safer as some chips may hold it low + * while they are processing data internally. + */ + if (end_timeout((long)adap->timeout)) + return -110; + } + wait_us(adap->udelay); + return 0; +} + + +/* --- other auxiliary functions -------------------------------------- */ +void i2c_start(struct i2c_algo_bit_data *adap) +{ + /* assert: scl, sda are high */ + sdalo(adap); + scllo(adap); +} + +static void i2c_repstart(struct i2c_algo_bit_data *adap) +{ + /* scl, sda may not be high */ + setsda(adap, 1); + sclhi(adap); + wait_us(adap->udelay); + sdalo(adap); + scllo(adap); +} + +static void i2c_stop(struct i2c_algo_bit_data *adap) +{ + /* assert: scl is low */ + sdalo(adap); + sclhi(adap); + sdahi(adap); +} + +/* + * send a byte without start cond., look for arbitration, + * check ackn. from slave + * + * returns: + * 1 if the device acknowledged + * 0 if the device did not ack + * -ETIMEDOUT if an error occurred (while raising the scl line) + */ +static int i2c_outb(struct i2c_adapter *i2c_adap, char c) +{ + int i; + int sb; + int ack; + struct i2c_algo_bit_data *adap = i2c_adap->algo_data; + /* assert: scl is low */ + + for (i = 7; i >= 0; i--) + { + sb = c & (1 << i); + setsda(adap,sb); + wait_us(adap->udelay); + if (sclhi(adap) < 0) + { + /* timed out */ + sdahi(adap); /* we don't want to block the net */ +#ifdef DEBUG + dbg("ETIMEDOUT\r\n"); +#endif + return -110; + }; + /* do arbitration here: + * if ( sb && ! getsda(adap) ) -> ouch! Get out of here. + */ + setscl(adap, 0 ); + wait_us(adap->udelay); + } + sdahi(adap); + if(sclhi(adap)<0) + { + /* timeout */ + + dbg("ETIMEDOUT\r\n"); + + return -110; + } + /* read ack: SDA should be pulled down by slave */ + ack = getsda(adap); /* ack: sda is pulled low ->success. */ + scllo(adap); + + dbg("0x%02x, ack=0x%02x\r\n", (unsigned long)(c & 0xff), ack); + + return 0 == ack; /* return 1 if device acked */ + /* assert: scl is low (sda undef) */ +} + +static int i2c_inb(struct i2c_adapter *i2c_adap) +{ + /* read byte via i2c port, without start/stop sequence */ + /* acknowledge is sent in i2c_read. */ + int i; + unsigned char indata = 0; + struct i2c_algo_bit_data *adap = i2c_adap->algo_data; + /* assert: scl is low */ + sdahi(adap); + for(i = 0; i < 8; i++) + { + if (sclhi(adap) < 0) + { + /* timeout */ + dbg("i2c_inb TIMEDOUT\r\n"); + return -110; + } + indata *= 2; + if (getsda(adap)) + indata |= 0x01; + scllo(adap); + } + /* assert: scl is low */ + dbg("0x%02x\r\n", (unsigned long)(indata & 0xff)); + + return (int) (indata & 0xff); +} + +/* + * Sanity check for the adapter hardware - check the reaction of + * the bus lines only if it seems to be idle. + */ +static int test_bus(struct i2c_algo_bit_data *adap) +{ + int scl, sda; + sda = getsda(adap); + scl = (adap->getscl == NULL ? 1 : getscl(adap)); + if (!scl || !sda ) + goto bailout; + sdalo(adap); + sda = getsda(adap); + scl = (adap->getscl == NULL ? 1 : getscl(adap)); + if (sda !=0 || scl == 0) + goto bailout; + sdahi(adap); + sda = getsda(adap); + scl = (adap->getscl == NULL ? 1 : getscl(adap)); + if (sda == 0 || scl ==0) + goto bailout; + scllo(adap); + sda = getsda(adap); + scl = (adap->getscl == NULL ? 0 : getscl(adap)); + if (scl !=0 || sda == 0) + goto bailout; + sclhi(adap); + sda = getsda(adap); + scl = (adap->getscl == NULL ? 1 : getscl(adap)); + if (scl == 0 || sda ==0) + goto bailout; + return 0; +bailout: + sdahi(adap); + sclhi(adap); + return -110; +} + +/* ----- Utility functions + */ + +/* try_address tries to contact a chip for a number of + * times before it gives up. + * return values: + * 1 chip answered + * 0 chip did not answer + * -x transmission error + */ +static inline int try_address(struct i2c_adapter *i2c_adap, + unsigned char addr, int retries) +{ + struct i2c_algo_bit_data *adap = i2c_adap->algo_data; + int i, ret = -1; + for (i = 0; i <= retries; i++) + { + ret = i2c_outb(i2c_adap, addr); + if (ret == 1) + break; /* success! */ + i2c_stop(adap); + wait_us(5); + if (i == retries) /* no success */ + break; + i2c_start(adap); + wait_us(adap->udelay); + } + return ret; +} + +static int sendbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msg) +{ + struct i2c_algo_bit_data *adap = i2c_adap->algo_data; + char c; + const char *temp = (const char *)msg->buf; + int count = msg->len; + unsigned short nak_ok = msg->flags & I2C_M_IGNORE_NAK; + int retval; + int wrcount=0; + while(count > 0) + { + c = *temp; + retval = i2c_outb(i2c_adap,c); + if ((retval > 0) || (nak_ok && (retval==0))) + { /* ok or ignored NAK */ + count--; + temp++; + wrcount++; + } + else + { /* arbitration or no acknowledge */ + i2c_stop(adap); + return (retval < 0)? retval : -110; + /* got a better one ?? */ + } + } + return wrcount; +} + +static inline int readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msg) +{ + int inval; + int rdcount=0; /* counts bytes read */ + struct i2c_algo_bit_data *adap = i2c_adap->algo_data; + char *temp = (char *)msg->buf; + int count = msg->len; + while(count > 0) + { + inval = i2c_inb(i2c_adap); + if (inval >= 0) + { + *temp = inval; + rdcount++; + } + else + /* read timed out */ + break; + temp++; + count--; + if (msg->flags & I2C_M_NO_RD_ACK) + continue; + if (count > 0) + /* send ack */ + sdalo(adap); + else + sdahi(adap); /* neg. ack on last byte */ + if (sclhi(adap) < 0) + { + /* timeout */ + sdahi(adap); + return -1; + }; + scllo(adap); + sdahi(adap); + } + return rdcount; +} + +/* doAddress initiates the transfer by generating the start condition (in + * try_address) and transmits the address in the necessary format to handle + * reads, writes as well as 10bit-addresses. + * returns: + * 0 everything went okay, the chip ack'ed, or IGNORE_NAK flag was set + * -x an error occurred (like: -EREMOTEIO if the device did not answer, or + * -ETIMEDOUT, for example if the lines are stuck...) + */ +static inline int bit_doAddress(struct i2c_adapter *i2c_adap, struct i2c_msg *msg) +{ + unsigned short flags = msg->flags; + unsigned short nak_ok = msg->flags & I2C_M_IGNORE_NAK; + struct i2c_algo_bit_data *adap = i2c_adap->algo_data; + unsigned char addr; + int ret, retries; + retries = nak_ok ? 0 : i2c_adap->retries; + if (flags & I2C_M_TEN) + { + /* a ten bit address */ + addr = 0xf0 | (( msg->addr >> 7) & 0x03); + /* try extended address code...*/ + ret = try_address(i2c_adap, addr, retries); + if ((ret != 1) && !nak_ok) + return -1; + /* the remaining 8 bit address */ + ret = i2c_outb(i2c_adap,msg->addr & 0x7f); + if ((ret != 1) && !nak_ok) + /* the chip did not ack / xmission error occurred */ + return -1; + if (flags & I2C_M_RD) + { + i2c_repstart(adap); + /* okay, now switch into reading mode */ + addr |= 0x01; + ret = try_address(i2c_adap, addr, retries); + if ((ret != 1) && !nak_ok) + return -1; + } + } + else + { /* normal 7bit address */ + addr = (msg->addr << 1); + if (flags & I2C_M_RD ) + addr |= 1; + if (flags & I2C_M_REV_DIR_ADDR ) + addr ^= 1; + ret = try_address(i2c_adap, addr, retries); + if ((ret != 1) && !nak_ok) + return -1; + } + return 0; +} + +static int bit_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[], int num) +{ + struct i2c_msg *pmsg; + struct i2c_algo_bit_data *adap = i2c_adap->algo_data; + int i,ret; + unsigned short nak_ok; + i2c_start(adap); + for(i=0;iflags & I2C_M_IGNORE_NAK; + if(!(pmsg->flags & I2C_M_NOSTART)) + { + if (i) + i2c_repstart(adap); + ret = bit_doAddress(i2c_adap, pmsg); + if ((ret != 0) && !nak_ok) + return (ret < 0) ? ret : -1; + } + if(pmsg->flags & I2C_M_RD ) + { + /* read bytes into buffer*/ + ret = readbytes(i2c_adap, pmsg); + if(ret < pmsg->len) + return (ret < 0)? ret : -1; + } + else + { + /* write bytes from buffer */ + ret = sendbytes(i2c_adap, pmsg); + if (ret < pmsg->len ) + return (ret < 0) ? ret : -1; + } + } + i2c_stop(adap); + return num; +} + +/* -----exported algorithm data: ------------------------------------- */ + +static struct i2c_algorithm i2c_bit_algo = { + .master_xfer = bit_xfer, +}; + +/* + * registering functions to load algorithms at runtime + */ +int i2c_bit_add_bus(struct i2c_adapter *adap) +{ + struct i2c_algo_bit_data *bit_adap = adap->algo_data; + if (1) + { + int ret = test_bus(bit_adap); + if (ret < 0) + return -1; + } + /* register new adapter to i2c module... */ + adap->algo = &i2c_bit_algo; + adap->timeout = 10; /* default values, should */ + adap->retries = 3; /* be replaced by defines */ + return 0; +} + +int i2c_bit_del_bus(struct i2c_adapter *adap) +{ + return 0; +} + +/* ---------------------------------------------------- + * the functional interface to the i2c busses. + * ---------------------------------------------------- + */ + +int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) +{ + int ret; + if (adap->algo->master_xfer) + { + ret = adap->algo->master_xfer(adap, msgs, num); + return ret; + } + else + return -1; +} diff --git a/radeon/radeon_accel.c b/radeon/radeon_accel.c new file mode 100644 index 0000000..3fa6d96 --- /dev/null +++ b/radeon/radeon_accel.c @@ -0,0 +1,1036 @@ +/* + * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and + * VA Linux Systems Inc., Fremont, California. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR + * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * Rickard E. Faith + * Alan Hourihane + * + * Credits: + * + * Thanks to Ani Joshi for providing source + * code to his Radeon driver. Portions of this file are based on the + * initialization code for that driver. + * + * References: + * + * !!!! FIXME !!!! + * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical + * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April + * 1999. + * + * RAGE 128 Software Development Manual (Technical Reference Manual P/N + * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. + * + * Notes on unimplemented XAA optimizations: + * + * SetClipping: This has been removed as XAA expects 16bit registers + * for full clipping. + * TwoPointLine: The Radeon supports this. Not Bresenham. + * DashedLine with non-power-of-two pattern length: Apparently, there is + * no way to set the length of the pattern -- it is always + * assumed to be 8 or 32 (or 1024?). + * ScreenToScreenColorExpandFill: See p. 4-17 of the Technical Reference + * Manual where it states that monochrome expansion of frame + * buffer data is not supported. + * Color8x8PatternFill: Apparently, an 8x8 color brush cannot take an 8x8 + * pattern from frame buffer memory. + * + */ + +// #define DEBUG +#include "debug.h" + +#include "fb.h" +#include "radeonfb.h" + +static struct { + int32_t rop; + int32_t pattern; +} RADEON_ROP[] = { + { ROP3_ZERO, ROP3_ZERO }, /* GXclear */ + { ROP3_DSa, ROP3_DPa }, /* Gxand */ + { ROP3_SDna, ROP3_PDna }, /* GXandReverse */ + { ROP3_S, ROP3_P }, /* GXcopy */ + { ROP3_DSna, ROP3_DPna }, /* GXandInverted */ + { ROP3_D, ROP3_D }, /* GXnoop */ + { ROP3_DSx, ROP3_DPx }, /* GXxor */ + { ROP3_DSo, ROP3_DPo }, /* GXor */ + { ROP3_DSon, ROP3_DPon }, /* GXnor */ + { ROP3_DSxn, ROP3_PDxn }, /* GXequiv */ + { ROP3_Dn, ROP3_Dn }, /* GXinvert */ + { ROP3_SDno, ROP3_PDno }, /* GXorReverse */ + { ROP3_Sn, ROP3_Pn }, /* GXcopyInverted */ + { ROP3_DSno, ROP3_DPno }, /* GXorInverted */ + { ROP3_DSan, ROP3_DPan }, /* GXnand */ + { ROP3_ONE, ROP3_ONE } /* GXset */ +}; + +#define ACCEL_MMIO +#define ACCEL_PREAMBLE() +#define BEGIN_ACCEL(n) radeon_wait_for_fifo(rinfo, (n)) +#define OUT_ACCEL_REG(reg, val) OUTREG(reg, val) +#define FINISH_ACCEL() + +/* MMIO: + * + * Wait for the graphics engine to be completely idle: the FIFO has + * drained, the Pixel Cache is flushed, and the engine is idle. This is + * a standard "sync" function that will make the hardware "quiescent". + */ +void radeon_wait_for_idle_mmio(struct radeonfb_info *rinfo) +{ + int32_t i = 0; + /* Wait for the engine to go idle */ + radeon_wait_for_fifo_function(rinfo, 64); + while(1) + { + for(i = 0; i < RADEON_TIMEOUT; i++) + { + if (!(INREG(RBBM_STATUS) & RBBM_ACTIVE)) + { + radeon_engine_flush(rinfo); + return; + } + } + radeon_engine_reset(rinfo); + radeon_engine_restore(rinfo); + } +} + +#if 0 + +/* This callback is required for multiheader cards using XAA */ +void RADEONRestoreAccelStateMMIO(struct fb_info *info) +{ + struct radeonfb_info *rinfo = info->par; +// unsigned long pitch64 = ((info->var.xres * (rinfo->bpp / 8) + 0x3f)) >> 6; + OUTREG(DEFAULT_OFFSET, (((INREG(DISPLAY_BASE_ADDR) + rinfo->fb_local_base) >> 10) | (rinfo->pitch << 22))); + /* FIXME: May need to restore other things, like BKGD_CLK FG_CLK... */ + RADEONWaitForIdleMMIO(rinfo); +} + +#endif + +/* Setup for XAA SolidFill */ +void radeon_setup_for_solid_fill(struct fb_info *info, int32_t color, int32_t rop, uint32_t planemask) +{ + struct radeonfb_info *rinfo = info->par; + ACCEL_PREAMBLE(); + /* Save for later clipping */ + rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl + | GMC_BRUSH_SOLID_COLOR | GMC_SRC_DATATYPE_COLOR | RADEON_ROP[rop].pattern); + BEGIN_ACCEL(4); + OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_master_cntl_clip); + OUT_ACCEL_REG(DP_BRUSH_FRGD_CLR, color); + OUT_ACCEL_REG(DP_WRITE_MSK, planemask); + OUT_ACCEL_REG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM)); + FINISH_ACCEL(); +} + +/* Subsequent XAA SolidFillRect */ +void radeon_subsequent_solid_fill_rect_mmio(struct fb_info *info, int32_t x, int32_t y, int32_t w, int32_t h) +{ + struct radeonfb_info *rinfo = info->par; + ACCEL_PREAMBLE(); +#ifdef RADEON_TILING + BEGIN_ACCEL(3); + OUT_ACCEL_REG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset + | ((rinfo->tilingEnabled && (y <= info->var.yres_virtual)) ? DST_TILE_MACRO : 0)); +#else + BEGIN_ACCEL(2); +#endif + OUT_ACCEL_REG(DST_Y_X, (y << 16) | x); + OUT_ACCEL_REG(DST_WIDTH_HEIGHT, (w << 16) | h); + FINISH_ACCEL(); +} + +/* Setup for XAA solid lines */ +void radeon_setup_for_solid_line_mmio(struct fb_info *info, int32_t color, int32_t rop, uint32_t planemask) +{ + struct radeonfb_info *rinfo = info->par; + ACCEL_PREAMBLE(); + /* Save for later clipping */ + rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl + | GMC_BRUSH_SOLID_COLOR | GMC_SRC_DATATYPE_COLOR | RADEON_ROP[rop].pattern); + if (rinfo->family >= CHIP_FAMILY_RV200) + { + BEGIN_ACCEL(1); + OUT_ACCEL_REG(DST_LINE_PATCOUNT, 0x55 << BRES_CNTL_SHIFT); + } + BEGIN_ACCEL(3); + OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_master_cntl_clip); + OUT_ACCEL_REG(DP_BRUSH_FRGD_CLR, color); + OUT_ACCEL_REG(DP_WRITE_MSK, planemask); + FINISH_ACCEL(); +} + +/* Subsequent XAA solid horizontal and vertical lines */ +void radeon_subsequent_solid_hor_vert_line_mmio(struct fb_info *info, int32_t x, int32_t y, int32_t len, int32_t dir) +{ + struct radeonfb_info *rinfo = info->par; + int32_t w = 1; + int32_t h = 1; + ACCEL_PREAMBLE(); + if (dir == DEGREES_0) + w = len; + else + h = len; +#ifdef RADEON_TILING + BEGIN_ACCEL(4); + OUT_ACCEL_REG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM)); + OUT_ACCEL_REG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset + | ((rinfo->tilingEnabled && (y <= info->var.xres_virtual)) ? DST_TILE_MACRO : 0)); +#else + BEGIN_ACCEL(3); + OUT_ACCEL_REG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM)); +#endif + OUT_ACCEL_REG(DST_Y_X, (y << 16) | x); + OUT_ACCEL_REG(DST_WIDTH_HEIGHT, (w << 16) | h); + FINISH_ACCEL(); +} + +/* Subsequent XAA solid TwoPointLine line */ +void radeon_subsequent_solid_two_point_line_mmio(struct fb_info *info, + int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t flags) +{ + struct radeonfb_info *rinfo = info->par; + + ACCEL_PREAMBLE(); + + /* TODO: Check bounds -- RADEON only has 14 bits */ + if (!(flags & OMIT_LAST)) + radeon_subsequent_solid_hor_vert_line_mmio(info, xb, yb, 1, DEGREES_0); +#ifdef RADEON_TILING + BEGIN_ACCEL(3); + OUT_ACCEL_REG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset + | ((rinfo->tilingEnabled && (ya <= info->var.yres_virtual)) ? DST_TILE_MACRO : 0)); +#else + BEGIN_ACCEL(2); +#endif + OUT_ACCEL_REG(DST_LINE_START, (ya << 16) | xa); + OUT_ACCEL_REG(DST_LINE_END, (yb << 16) | xb); + FINISH_ACCEL(); +} + +/* Setup for XAA dashed lines + * NOTE: Since we can only accelerate lines with power-of-2 patterns of * length <= 32 + */ +void radeon_setup_for_dashed_line_mmio(struct fb_info *info, int32_t fg, int32_t bg, + int32_t rop, uint32_t planemask, int32_t length, unsigned char *pattern) +{ + struct radeonfb_info *rinfo = info->par; + unsigned long pat = *(unsigned long *) pattern; + + ACCEL_PREAMBLE(); + /* Save for determining whether or not to draw last pixel */ + rinfo->dashLen = length; + rinfo->dashPattern = pat; + if (rinfo->big_endian) + { + switch (length) + { + case 2: pat |= (pat >> 2); /* fall through */ + case 4: pat |= (pat >> 4); /* fall through */ + case 8: pat |= (pat >> 8); /* fall through */ + case 16: pat |= (pat >> 16); + } + } + else + { + switch (length) + { + case 2: pat |= (pat << 2); /* fall through */ + case 4: pat |= (pat << 4); /* fall through */ + case 8: pat |= (pat << 8); /* fall through */ + case 16: pat |= (pat << 16); + } + } + /* Save for later clipping */ + rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl + | (bg == -1 ? GMC_BRUSH_32X1_MONO_FG_LA : GMC_BRUSH_32X1_MONO_FG_BG) + | RADEON_ROP[rop].pattern | GMC_BYTE_LSB_TO_MSB); + rinfo->dash_fg = fg; + rinfo->dash_bg = bg; + BEGIN_ACCEL((bg == -1) ? 4 : 5); + OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_master_cntl_clip); + OUT_ACCEL_REG(DP_WRITE_MSK, planemask); + OUT_ACCEL_REG(DP_BRUSH_FRGD_CLR, fg); + if (bg != -1) + OUT_ACCEL_REG(DP_BRUSH_BKGD_CLR, bg); + OUT_ACCEL_REG(BRUSH_DATA0, pat); + FINISH_ACCEL(); +} + +/* Helper function to draw last point for dashed lines */ +static void RADEONDashedLastPelMMIO(struct fb_info *info, + int32_t x, int32_t y, int32_t fg) +{ + struct radeonfb_info *rinfo = info->par; + unsigned long dp_gui_master_cntl = rinfo->dp_gui_master_cntl_clip; + ACCEL_PREAMBLE(); + dp_gui_master_cntl &= ~GMC_BRUSH_DATATYPE_MASK; + dp_gui_master_cntl |= GMC_BRUSH_SOLID_COLOR; + dp_gui_master_cntl &= ~GMC_SRC_DATATYPE_MASK; + dp_gui_master_cntl |= GMC_SRC_DATATYPE_COLOR; +#ifdef RADEON_TILING + BEGIN_ACCEL(8); + OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, dp_gui_master_cntl); + OUT_ACCEL_REG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM)); + OUT_ACCEL_REG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset + | ((rinfo->tilingEnabled && (y <= info->var.yres_virtual)) ? DST_TILE_MACRO : 0)); +#else + BEGIN_ACCEL(7); + OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, dp_gui_master_cntl); + OUT_ACCEL_REG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM)); +#endif + OUT_ACCEL_REG(DP_BRUSH_FRGD_CLR, fg); + OUT_ACCEL_REG(DST_Y_X, (y << 16) | x); + OUT_ACCEL_REG(DST_WIDTH_HEIGHT, (1 << 16) | 1); + /* Restore old values */ + OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_master_cntl_clip); + OUT_ACCEL_REG(DP_BRUSH_FRGD_CLR, rinfo->dash_fg); + FINISH_ACCEL(); +} + +/* Subsequent XAA dashed line */ +void radeon_subsequent_dashed_two_point_line_mmio(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t flags, int32_t phase) +{ + struct radeonfb_info *rinfo = info->par; + + ACCEL_PREAMBLE(); + + /* TODO: Check bounds -- RADEON only has 14 bits */ + if (!(flags & OMIT_LAST)) + { + int32_t deltax = xa - xb; + int32_t deltay = ya - yb; + int32_t shift; + if (deltax < 0) + deltax = -deltax; + if (deltay < 0) + deltay = -deltay; + if (deltax > deltay) + shift = deltax; + else + shift = deltay; + shift += phase; + shift %= rinfo->dashLen; + if ((rinfo->dashPattern >> shift) & 1) + RADEONDashedLastPelMMIO(info, xb, yb, rinfo->dash_fg); + else if (rinfo->dash_bg != -1) + RADEONDashedLastPelMMIO(info, xb, yb, rinfo->dash_bg); + } +#ifdef RADEON_TILING + BEGIN_ACCEL(4); + OUT_ACCEL_REG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset + | ((rinfo->tilingEnabled && (ya <= info->var.yres_virtual)) ? DST_TILE_MACRO : 0)); +#else + BEGIN_ACCEL(3); +#endif + OUT_ACCEL_REG(DST_LINE_START, (ya << 16) | xa); + OUT_ACCEL_REG(DST_LINE_PATCOUNT, phase); + OUT_ACCEL_REG(DST_LINE_END, (yb << 16) | xb); + FINISH_ACCEL(); +} + +/* Set up for transparency + * + * Mmmm, Seems as though the transparency compare is opposite to r128. + * It should only draw when source != trans_color, this is the opposite + * of that. + */ +static void radeon_set_transparency_mmio(struct radeonfb_info *rinfo, int32_t trans_color) +{ + if (trans_color != -1) + { + ACCEL_PREAMBLE(); + BEGIN_ACCEL(3); + OUT_ACCEL_REG(CLR_CMP_CLR_SRC, trans_color); + OUT_ACCEL_REG(CLR_CMP_MSK, 0xffffffff); + OUT_ACCEL_REG(CLR_CMP_CNTL, (SRC_CMP_EQ_COLOR | CLR_CMP_SRC_SOURCE)); + FINISH_ACCEL(); + } +} + +/* Setup for XAA screen-to-screen copy */ +void radeon_setup_for_screen_to_screen_copy_mmio(struct fb_info *info, + int32_t xdir, int32_t ydir, int32_t rop, uint32_t planemask, int32_t trans_color) +{ + struct radeonfb_info *rinfo = info->par; + + ACCEL_PREAMBLE(); + rinfo->xdir = xdir; + rinfo->ydir = ydir; + /* Save for later clipping */ +#ifdef RADEON_TILING + rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl + | GMC_BRUSH_NONE | GMC_SRC_DATATYPE_COLOR | RADEON_ROP[rop].rop + | DP_SRC_SOURCE_MEMORY | GMC_SRC_PITCH_OFFSET_CNTL); +#else + rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl + | GMC_BRUSH_NONE | GMC_SRC_DATATYPE_COLOR | RADEON_ROP[rop].rop | DP_SRC_SOURCE_MEMORY); +#endif + BEGIN_ACCEL(3); + OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_master_cntl_clip); + OUT_ACCEL_REG(DP_WRITE_MSK, planemask); + OUT_ACCEL_REG(DP_CNTL, ((xdir >= 0 ? DST_X_LEFT_TO_RIGHT : 0) | (ydir >= 0 ? DST_Y_TOP_TO_BOTTOM : 0))); + FINISH_ACCEL(); + rinfo->trans_color = trans_color; + if (trans_color != -1) + radeon_set_transparency_mmio(rinfo, trans_color); +} + +/* Subsequent XAA screen-to-screen copy */ +void radeon_subsequent_screen_to_screen_copy_mmio(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h) +{ + struct radeonfb_info *rinfo = info->par; + + ACCEL_PREAMBLE(); + if (rinfo->xdir < 0) + xa += w - 1, xb += w - 1; + + if (rinfo->ydir < 0) + ya += h - 1, yb += h - 1; + +#ifdef RADEON_TILING + BEGIN_ACCEL(5); + OUT_ACCEL_REG(SRC_PITCH_OFFSET, rinfo->dst_pitch_offset + | ((rinfo->tilingEnabled && (ya <= info->var.yres_virtual)) ? DST_TILE_MACRO : 0)); + OUT_ACCEL_REG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset + | ((rinfo->tilingEnabled && (yb <= info->var.yres_virtual)) ? DST_TILE_MACRO : 0)); +#else + BEGIN_ACCEL(3); +#endif + OUT_ACCEL_REG(SRC_Y_X, (ya << 16) | xa); + OUT_ACCEL_REG(DST_Y_X, (yb << 16) | xb); + OUT_ACCEL_REG(DST_HEIGHT_WIDTH, (h << 16) | w); + FINISH_ACCEL(); +} + +/* XAA screen-to-screen copy */ +void radeon_screen_to_screen_copy_mmio(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h, int32_t rop) +{ + struct radeonfb_info *rinfo = info->par; + + int32_t xdir = xa - xb; + int32_t ydir = ya - yb; + ACCEL_PREAMBLE(); + if (xdir < 0) + xa += w - 1, xb += w - 1; + if (ydir < 0) + ya += h - 1, yb += h - 1; +#ifdef RADEON_TILING + /* Save for later clipping */ + rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl + | GMC_BRUSH_NONE | GMC_SRC_DATATYPE_COLOR | RADEON_ROP[rop].rop + | DP_SRC_SOURCE_MEMORY | GMC_SRC_PITCH_OFFSET_CNTL); + BEGIN_ACCEL(8); + + OUT_ACCEL_REG(SRC_PITCH_OFFSET, rinfo->dst_pitch_offset + | ((rinfo->tilingEnabled && (ya <= info->var.yres_virtual)) ? DST_TILE_MACRO : 0)); + OUT_ACCEL_REG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset + | ((rinfo->tilingEnabled && (yb <= info->var.yres_virtual)) ? DST_TILE_MACRO : 0)); +#else + /* Save for later clipping */ + rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl + | GMC_BRUSH_NONE | GMC_SRC_DATATYPE_COLOR | RADEON_ROP[rop].rop | DP_SRC_SOURCE_MEMORY); + BEGIN_ACCEL(6); +#endif + OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_master_cntl_clip); + OUT_ACCEL_REG(DP_WRITE_MSK, -1); + OUT_ACCEL_REG(DP_CNTL, ((xdir >= 0 ? DST_X_LEFT_TO_RIGHT : 0) | (ydir >= 0 ? DST_Y_TOP_TO_BOTTOM : 0))); + OUT_ACCEL_REG(SRC_Y_X, (ya << 16) | xa); + OUT_ACCEL_REG(DST_Y_X, (yb << 16) | xb); + OUT_ACCEL_REG(DST_HEIGHT_WIDTH, (h << 16) | w); + FINISH_ACCEL(); +} + +/* Setup for XAA mono 8x8 pattern color expansion. Patterns with + * transparency use `bg == -1'. This routine is only used if the XAA + * pixmap cache is turned on. + */ +void radeon_setup_for_mono_8x8_pattern_fill_mmio(struct fb_info *info, int32_t patternx, int32_t patterny, + int32_t fg, int32_t bg, int32_t rop, uint32_t planemask) +{ + struct radeonfb_info *rinfo = info->par; + unsigned char pattern[8]; + + ACCEL_PREAMBLE(); + if (rinfo->big_endian) + { + /* Take care of endianness */ + pattern[0] = (patternx & 0x000000ff); + pattern[1] = (patternx & 0x0000ff00) >> 8; + pattern[2] = (patternx & 0x00ff0000) >> 16; + pattern[3] = (patternx & 0xff000000) >> 24; + pattern[4] = (patterny & 0x000000ff); + pattern[5] = (patterny & 0x0000ff00) >> 8; + pattern[6] = (patterny & 0x00ff0000) >> 16; + pattern[7] = (patterny & 0xff000000) >> 24; + /* Save for later clipping */ + rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl + | (bg == -1 ? GMC_BRUSH_8X8_MONO_FG_LA : GMC_BRUSH_8X8_MONO_FG_BG) + | RADEON_ROP[rop].pattern | GMC_BYTE_MSB_TO_LSB); + } + else + /* Save for later clipping */ + rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl + | (bg == -1 ? GMC_BRUSH_8X8_MONO_FG_LA : GMC_BRUSH_8X8_MONO_FG_BG) + | RADEON_ROP[rop].pattern); + BEGIN_ACCEL((bg == -1) ? 5 : 6); + OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_master_cntl_clip); + OUT_ACCEL_REG(DP_WRITE_MSK, planemask); + OUT_ACCEL_REG(DP_BRUSH_FRGD_CLR, fg); + if (bg != -1) + OUT_ACCEL_REG(DP_BRUSH_BKGD_CLR, bg); + if (rinfo->big_endian) + { + OUT_ACCEL_REG(BRUSH_DATA0, &pattern[0]); + OUT_ACCEL_REG(BRUSH_DATA1, &pattern[4]); + } + else + { + OUT_ACCEL_REG(BRUSH_DATA0, patternx); + OUT_ACCEL_REG(BRUSH_DATA1, patterny); + } + FINISH_ACCEL(); +} + +/* Subsequent XAA 8x8 pattern color expansion. Because they are used in + * the setup function, `patternx' and `patterny' are not used here. + */ +void radeon_subsequent_mono_8x8_pattern_fill_rect_mmio(struct fb_info *info, int32_t patternx, int32_t patterny, + int32_t x, int32_t y, int32_t w, int32_t h) +{ + struct radeonfb_info *rinfo = info->par; + + ACCEL_PREAMBLE(); +#ifdef RADEON_TILING + BEGIN_ACCEL(4); + OUT_ACCEL_REG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset + | ((rinfo->tilingEnabled && (y <= info->var.yres_virtual)) ? DST_TILE_MACRO : 0)); +#else + BEGIN_ACCEL(3); +#endif + OUT_ACCEL_REG(BRUSH_Y_X, (patterny << 8) | patternx); + OUT_ACCEL_REG(DST_Y_X, (y << 16) | x); + OUT_ACCEL_REG(DST_HEIGHT_WIDTH, (h << 16) | w); + FINISH_ACCEL(); +} + +/* Setup for XAA indirect CPU-to-screen color expansion (indirect). + * Because of how the scratch buffer is initialized, this is really a + * mainstore-to-screen color expansion. Transparency is supported when + * `bg == -1'. + */ +void radeon_setup_for_scanline_cpu_to_screen_color_expand_fill_mmio(struct fb_info *info, + int32_t fg, int32_t bg, int32_t rop, uint32_t planemask) +{ + struct radeonfb_info *rinfo = info->par; + + ACCEL_PREAMBLE(); + /* Save for later clipping */ + if (rinfo->big_endian) + rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl + | GMC_DST_CLIPPING | GMC_BRUSH_NONE + | (bg == -1 ? GMC_SRC_DATATYPE_MONO_FG_LA : GMC_SRC_DATATYPE_MONO_FG_BG) + | RADEON_ROP[rop].rop | GMC_BYTE_MSB_TO_LSB | DP_SRC_SOURCE_HOST_DATA); + else + rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl + | GMC_DST_CLIPPING | GMC_BRUSH_NONE + | (bg == -1 ? GMC_SRC_DATATYPE_MONO_FG_LA : GMC_SRC_DATATYPE_MONO_FG_BG) + | RADEON_ROP[rop].rop | GMC_BYTE_LSB_TO_MSB | DP_SRC_SOURCE_HOST_DATA); + if (rinfo->big_endian) + { + BEGIN_ACCEL(5); + OUT_ACCEL_REG(RBBM_GUICNTL, HOST_DATA_SWAP_NONE); + } + else + BEGIN_ACCEL(4); + OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_master_cntl_clip); + OUT_ACCEL_REG(DP_WRITE_MSK, planemask); + OUT_ACCEL_REG(DP_SRC_FRGD_CLR, fg); + OUT_ACCEL_REG(DP_SRC_BKGD_CLR, bg); + FINISH_ACCEL(); +} + +/* Subsequent XAA indirect CPU-to-screen color expansion. This is only + * called once for each rectangle. + */ +void radeon_subsequent_scanline_cpu_to_screen_color_expand_fill_mmio(struct fb_info *info, + int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft) +{ + struct radeonfb_info *rinfo = info->par; + ACCEL_PREAMBLE(); + rinfo->scanline_h = h; + rinfo->scanline_words = (w + 31) >> 5; +#ifdef RADEON_TILING + BEGIN_ACCEL(5); + OUT_ACCEL_REG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset + | ((rinfo->tilingEnabled && (y <= info->var.yres_virtual)) ? DST_TILE_MACRO : 0)); +#else + BEGIN_ACCEL(4); +#endif + OUT_ACCEL_REG(SC_TOP_LEFT, (y << 16) | ((x + skipleft) & 0xffff)); + OUT_ACCEL_REG(SC_BOTTOM_RIGHT, ((y+h) << 16) | ((x + w) & 0xffff)); + OUT_ACCEL_REG(DST_Y_X, (y << 16) | (x & 0xffff)); + /* Have to pad the width here and use clipping engine */ + OUT_ACCEL_REG(DST_HEIGHT_WIDTH, (h << 16) | ((w + 31) & ~31)); + FINISH_ACCEL(); +} + +/* Subsequent XAA indirect CPU-to-screen color expansion and indirect + * image write. This is called once for each scanline. + */ +void radeon_subsequent_scanline_mmio(struct fb_info *info, uint32_t *src) +{ + struct radeonfb_info *rinfo = info->par; + int32_t left = rinfo->scanline_words; + volatile unsigned long *d; + ACCEL_PREAMBLE(); + --rinfo->scanline_h; + while(left) + { + if (left <= 8) + { + /* Last scanline - finish write to DATA_LAST */ + if (rinfo->scanline_h == 0) + { + BEGIN_ACCEL(left); + /* Unrolling doesn't improve performance */ + for (d = (volatile unsigned long *) ADDRREG(HOST_DATA_LAST) - (left - 1); left; --left) + *d++ = *src++; + return; + } + else + { + BEGIN_ACCEL(left); + /* Unrolling doesn't improve performance */ + for (d = (volatile unsigned long *) ADDRREG(HOST_DATA7) - (left - 1); left; --left) + *d++ = *src++; + } + } + else + { + BEGIN_ACCEL(8); + /* Unrolling doesn't improve performance */ + d = (volatile unsigned long *) ADDRREG(HOST_DATA0); + *d++ = *src++; + *d++ = *src++; + *d++ = *src++; + *d++ = *src++; + *d++ = *src++; + *d++ = *src++; + *d++ = *src++; + *d++ = *src++; + left -= 8; + } + } + FINISH_ACCEL(); +} + +/* Setup for XAA indirect image write */ +void radeon_setup_for_scanline_image_write_mmio(struct fb_info *info, int32_t rop, uint32_t planemask, + int32_t trans_color, int32_t bpp) +{ + struct radeonfb_info *rinfo = info->par; + + ACCEL_PREAMBLE(); + rinfo->scanline_bpp = bpp; + /* Save for later clipping */ + rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl + | GMC_DST_CLIPPING | GMC_BRUSH_NONE | GMC_SRC_DATATYPE_COLOR | RADEON_ROP[rop].rop + | GMC_BYTE_MSB_TO_LSB | DP_SRC_SOURCE_HOST_DATA); + if (rinfo->big_endian) + { + BEGIN_ACCEL(3); + if (bpp == 16) + OUT_ACCEL_REG(RBBM_GUICNTL, HOST_DATA_SWAP_16BIT); + else if (bpp == 32) + OUT_ACCEL_REG(RBBM_GUICNTL, HOST_DATA_SWAP_32BIT); + else + OUT_ACCEL_REG(RBBM_GUICNTL, HOST_DATA_SWAP_NONE); + } + else + BEGIN_ACCEL(2); + OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_master_cntl_clip); + OUT_ACCEL_REG(DP_WRITE_MSK, planemask); + FINISH_ACCEL(); + rinfo->trans_color = trans_color; + if (trans_color != -1) + radeon_set_transparency_mmio(rinfo, trans_color); +} + +/* Subsequent XAA indirect image write. This is only called once for each rectangle. */ +void radeon_subsequent_scanline_image_write_rect_mmio(struct fb_info *info, int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft) +{ + struct radeonfb_info *rinfo = info->par; + int32_t shift = 0; /* 32bpp */ + ACCEL_PREAMBLE(); + if (rinfo->bpp == 8) + shift = 3; + else if (rinfo->bpp == 16) + shift = 1; + rinfo->scanline_h = h; + rinfo->scanline_words = (w * rinfo->scanline_bpp + 31) >> 5; +#ifdef RADEON_TILING + BEGIN_ACCEL(5); + OUT_ACCEL_REG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset + | ((rinfo->tilingEnabled && (y <= info->var.yres_virtual)) ? DST_TILE_MACRO : 0)); +#else + BEGIN_ACCEL(4); +#endif + OUT_ACCEL_REG(SC_TOP_LEFT, (y << 16) | ((x+skipleft) & 0xffff)); + OUT_ACCEL_REG(SC_BOTTOM_RIGHT, ((y+h) << 16) | ((x+w) & 0xffff)); + OUT_ACCEL_REG(DST_Y_X, (y << 16) | (x & 0xffff)); + /* Have to pad the width here and use clipping engine */ + OUT_ACCEL_REG(DST_HEIGHT_WIDTH, (h << 16) | ((w + shift) & ~shift)); + FINISH_ACCEL(); +} + +/* Set up the clipping rectangle */ +void radeon_set_clipping_rectangle_mmio(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb) +{ + struct radeonfb_info *rinfo = info->par; + + unsigned long tmp1 = 0; + unsigned long tmp2 = 0; + ACCEL_PREAMBLE(); + if (xa < 0) + { + tmp1 = (-xa) & 0x3fff; + tmp1 |= SC_SIGN_MASK_LO; + } + else + tmp1 = xa; + if (ya < 0) + { + tmp1 |= (((-ya) & 0x3fff) << 16); + tmp1 |= SC_SIGN_MASK_HI; + } + else + tmp1 |= (ya << 16); + xb++; yb++; + if (xb < 0) + { + tmp2 = (-xb) & 0x3fff; + tmp2 |= SC_SIGN_MASK_LO; + } + else + tmp2 = xb; + if (yb < 0) + { + tmp2 |= (((-yb) & 0x3fff) << 16); + tmp2 |= SC_SIGN_MASK_HI; + } + else + tmp2 |= (yb << 16); + BEGIN_ACCEL(3); + OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl_clip | GMC_DST_CLIPPING)); + OUT_ACCEL_REG(SC_TOP_LEFT, tmp1); + OUT_ACCEL_REG(SC_BOTTOM_RIGHT, tmp2); + FINISH_ACCEL(); + if (rinfo->trans_color != -1) + radeon_set_transparency_mmio(rinfo, rinfo->trans_color); +} + +/* Disable the clipping rectangle */ +void radeon_disable_clipping_mmio(struct fb_info *info) +{ + struct radeonfb_info *rinfo = info->par; + + ACCEL_PREAMBLE(); + BEGIN_ACCEL(3); + OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_master_cntl_clip); + OUT_ACCEL_REG(SC_TOP_LEFT, 0); + OUT_ACCEL_REG(SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | DEFAULT_SC_BOTTOM_MAX)); + FINISH_ACCEL(); + if (rinfo->trans_color != -1) + radeon_set_transparency_mmio(rinfo, rinfo->trans_color); +} + +#if 0 + +/* Change surfaces + The idea here is to only set up front buffer as tiled, and back/depth buffer when needed. + Everything else is left as untiled. This means we need to use eplicit src/dst pitch control + when blitting, based on the src/target address, and can no longer use a default offset. + But OTOH we don't need to dynamically change surfaces (for xv for instance), and some + ugly offset / fb reservation (cursor) is gone. And as a bonus, everything actually works... + All surface addresses are relative to MC_FB_LOCATION + */ +void RADEONChangeSurfaces(struct fb_info *info) +{ + struct radeonfb_info *rinfo = info->par; + int32_t cpp = rinfo->bpp >> 3; + /* depth/front/back pitch must be identical (and the same as displayWidth) */ + int32_t width_bytes = info->var.xres_virtual * cpp; + int32_t bufferSize = (((((info->var.yres_virtual + 15) & ~15) * width_bytes) + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN); + uint32_t depth_pattern, color_pattern, swap_pattern, surf_info; + if (rinfo->big_endian) + { + switch(rinfo->bpp) + { + case 16: + swap_pattern = SURF_AP0_SWP_16BPP | SURF_AP1_SWP_16BPP; + break; + case 32: + swap_pattern = SURF_AP0_SWP_32BPP | SURF_AP1_SWP_32BPP; + break; + default: + swap_pattern = 0; + } + } + else + swap_pattern = 0; + if (rinfo->family < CHIP_FAMILY_R200) + { + color_pattern = SURF_TILE_COLOR_MACRO; + if (cpp == 2) + depth_pattern = SURF_TILE_DEPTH_16BPP; + else + depth_pattern = SURF_TILE_DEPTH_32BPP; + } + else if (rinfo->family >= CHIP_FAMILY_R300) + { + color_pattern = R300_SURF_TILE_COLOR_MACRO; + if (cpp == 2) + depth_pattern = R300_SURF_TILE_COLOR_MACRO; + else + depth_pattern = R300_SURF_TILE_COLOR_MACRO | R300_SURF_TILE_DEPTH_32BPP; + } + else + { + color_pattern = R200_SURF_TILE_COLOR_MACRO; + if (cpp == 2) + depth_pattern = R200_SURF_TILE_DEPTH_16BPP; + else + depth_pattern = R200_SURF_TILE_DEPTH_32BPP; + } + /* we don't need anything like WaitForFifo, no? */ +#ifdef RADEON_TILING + if (rinfo->tilingEnabled) + { + if (rinfo->family >= CHIP_FAMILY_R300) + surf_info = swap_pattern | (width_bytes / 8) | color_pattern; + else + surf_info = swap_pattern | (width_bytes / 16) | color_pattern; + } + else +#endif + surf_info = 0; + OUTREG(SURFACE0_INFO, surf_info); + OUTREG(SURFACE0_LOWER_BOUND, 0); + OUTREG(SURFACE0_UPPER_BOUND, bufferSize - 1); +} + +#endif + +/* + * The FIFO has 64 slots. This routines waits until at least `entries' + * of these slots are empty. + */ +void radeon_wait_for_fifo_function(struct radeonfb_info *rinfo, int32_t entries) +{ + int32_t i; + while(1) + { + for(i = 0; i < RADEON_TIMEOUT; i++) + { + rinfo->fifo_slots = INREG(RBBM_STATUS) & RBBM_FIFOCNT_MASK; + if (rinfo->fifo_slots >= entries) + return; + } + radeon_engine_reset(rinfo); + radeon_engine_restore(rinfo); + } +} + +/* Flush all dirty data in the Pixel Cache to memory */ +void radeon_engine_flush(struct radeonfb_info *rinfo) +{ + int32_t i; + OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, ~RB2D_DC_FLUSH_ALL); + for(i = 0; i < RADEON_TIMEOUT; i++) + { + if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) + break; + } +} + +/* + * Reset graphics card to known state + */ +void radeon_engine_reset(struct radeonfb_info *rinfo) +{ + unsigned long clock_cntl_index; + unsigned long mclk_cntl; + unsigned long rbbm_soft_reset; + unsigned long host_path_cntl; + + radeon_engine_flush(rinfo); + clock_cntl_index = INREG(CLOCK_CNTL_INDEX); + + /* Some ASICs have bugs with dynamic-on feature, which are + * ASIC-version dependent, so we force all blocks on for now + */ + if (rinfo->has_CRTC2) + { + unsigned long tmp; + + tmp = INPLL(SCLK_CNTL); + OUTPLL(SCLK_CNTL, ((tmp & ~DYN_STOP_LAT_MASK) | CP_MAX_DYN_STOP_LAT | SCLK_FORCEON_MASK)); + if (rinfo->family == CHIP_FAMILY_RV200) + { + tmp = INPLL(SCLK_MORE_CNTL); + OUTPLL(SCLK_MORE_CNTL, tmp | SCLK_MORE_FORCEON); + } + } + mclk_cntl = INPLL(MCLK_CNTL); + OUTPLL(MCLK_CNTL, (mclk_cntl | FORCEON_MCLKA + | FORCEON_MCLKB + | FORCEON_YCLKA + | FORCEON_YCLKB + | FORCEON_MC + | FORCEON_AIC)); + + /* + * Soft resetting HDP thru RBBM_SOFT_RESET register can cause some + * unexpected behaviour on some machines. Here we use + * HOST_PATH_CNTL to reset it. + */ + host_path_cntl = INREG(HOST_PATH_CNTL); + + rbbm_soft_reset = INREG(RBBM_SOFT_RESET); + + if ((rinfo->family == CHIP_FAMILY_R300) || (rinfo->family == CHIP_FAMILY_R350) + || (rinfo->family == CHIP_FAMILY_RV350)) + { + unsigned long tmp; + + OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset | SOFT_RESET_CP | SOFT_RESET_HI | SOFT_RESET_E2)); + INREG(RBBM_SOFT_RESET); + OUTREG(RBBM_SOFT_RESET, 0); + tmp = INREG(RB2D_DSTCACHE_MODE); + OUTREG(RB2D_DSTCACHE_MODE, tmp | (1 << 17)); /* FIXME */ + } + else + { + OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset | SOFT_RESET_CP + | SOFT_RESET_HI | SOFT_RESET_SE | SOFT_RESET_RE + | SOFT_RESET_PP | SOFT_RESET_E2 | SOFT_RESET_RB)); + + INREG(RBBM_SOFT_RESET); + + OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset & (unsigned long) ~(SOFT_RESET_CP | SOFT_RESET_HI | SOFT_RESET_SE + | SOFT_RESET_RE | SOFT_RESET_PP | SOFT_RESET_E2 | SOFT_RESET_RB))); + INREG(RBBM_SOFT_RESET); + } + OUTREG(HOST_PATH_CNTL, host_path_cntl | HDP_SOFT_RESET); + INREG(HOST_PATH_CNTL); + OUTREG(HOST_PATH_CNTL, host_path_cntl); + + if ((rinfo->family != CHIP_FAMILY_R300) + && (rinfo->family != CHIP_FAMILY_R350) + && (rinfo->family != CHIP_FAMILY_RV350)) + OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset); + + OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); + OUTPLL(MCLK_CNTL, mclk_cntl); +} + +/* + * Restore the acceleration hardware to its previous state + */ +void radeon_engine_restore(struct radeonfb_info *rinfo) +{ + BEGIN_ACCEL(1); + /* NOTE: The following RB2D_DSTCACHE_MODE setting will cause the + * R300 to hang. ATI does not see a reason to change it from the + * default BIOS settings (even on non-R300 cards). This setting + * might be removed in future versions of the Radeon driver. + */ + /* Turn of all automatic flushing - we'll do it all */ + if ((rinfo->family != CHIP_FAMILY_R300) + && (rinfo->family != CHIP_FAMILY_R350) + && (rinfo->family != CHIP_FAMILY_RV350)) + OUTREG(RB2D_DSTCACHE_MODE, 0); + + rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; + + BEGIN_ACCEL(3); + OUTREG(DEFAULT_PITCH_OFFSET, rinfo->dst_pitch_offset); + OUTREG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset); + OUTREG(SRC_PITCH_OFFSET, rinfo->dst_pitch_offset); + + BEGIN_ACCEL(1); + if (rinfo->big_endian) + OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); + else + OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); + + /* Restore SURFACE_CNTL - only the first head contains valid data */ + OUTREG(SURFACE_CNTL, rinfo->state.surface_cntl); + + BEGIN_ACCEL(2); + OUTREG(DEFAULT_SC_TOP_LEFT, 0); + OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | DEFAULT_SC_BOTTOM_MAX)); + + BEGIN_ACCEL(1); + OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl | GMC_BRUSH_SOLID_COLOR | GMC_SRC_DATATYPE_COLOR)); + + BEGIN_ACCEL(7); + OUTREG(DST_LINE_START, 0); + OUTREG(DST_LINE_END, 0); + OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff); + OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000); + OUTREG(DP_SRC_FRGD_CLR, 0xffffffff); + OUTREG(DP_SRC_BKGD_CLR, 0x00000000); + OUTREG(DP_WRITE_MSK, 0xffffffff); + + radeon_wait_for_idle_mmio(rinfo); +} + +/* Initialize the acceleration hardware */ +void radeon_engine_init(struct radeonfb_info *rinfo) +{ + unsigned long temp; + + OUTREG(RB3D_CNTL, 0); + radeon_engine_reset(rinfo); + temp = radeon_get_dstbpp(rinfo->depth); +#ifdef RADEON_TILING + rinfo->dp_gui_master_cntl = ((temp << GMC_DST_DATATYPE_SHIFT) | GMC_CLR_CMP_CNTL_DIS | GMC_DST_PITCH_OFFSET_CNTL); +#else + rinfo->dp_gui_master_cntl = ((temp << GMC_DST_DATATYPE_SHIFT) | GMC_CLR_CMP_CNTL_DIS); +#endif + radeon_engine_restore(rinfo); +} + diff --git a/radeon/radeon_base.c b/radeon/radeon_base.c new file mode 100644 index 0000000..0a42bba --- /dev/null +++ b/radeon/radeon_base.c @@ -0,0 +1,2457 @@ +/* + * radeon_base.c + * + * framebuffer driver for ATI Radeon chipset video boards + * + * Copyright 2003 Ben. Herrenschmidt + * Copyright 2000 Ani Joshi + * + * i2c bits from Luca Tettamanti + * + * Special thanks to ATI DevRel team for their hardware donations. + * + * ...Insert GPL boilerplate here... + * + * Significant portions of this driver apdated from XFree86 Radeon + * driver which has the following copyright notice: + * + * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and + * VA Linux Systems Inc., Fremont, California. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR + * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * XFree86 driver authors: + * + * Kevin E. Martin + * Rickard E. Faith + * Alan Hourihane + * + */ + +#define RADEON_VERSION "0.2.0" + +#include "fb.h" +#include "i2c.h" +#include "pci.h" +#include "radeonfb.h" +#include "edid.h" +#include "ati_ids.h" +#include "driver_mem.h" +#include "bas_printf.h" +#include "bas_string.h" +#include "exceptions.h" /* for set_ipl() */ + +// #define DEBUG +#include "debug.h" + +extern void run_bios(struct radeonfb_info *rinfo); + +#define MAX_MAPPED_VRAM (2048 * 2048 * 4) +#define MIN_MAPPED_VRAM (1024 * 768 * 4) + +#define CHIP_DEF(id, family, flags) \ +{ \ + PCI_VENDOR_ID_ATI, \ + id, \ + PCI_ANY_ID, \ + PCI_ANY_ID, \ + 0, \ + 0, \ + (flags) | (CHIP_FAMILY_##family) \ +} + +struct pci_device_id radeonfb_pci_table[] = +{ + /* Mobility M6 */ + CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + /* Radeon VE/7000 */ + CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2), + /* Radeon IGP320M (U1) */ + CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), + /* Radeon IGP320 (A3) */ + CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP), + /* IGP330M/340M/350M (U2) */ + CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), + /* IGP330/340/350 (A4) */ + CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP), + /* Mobility 7000 IGP */ + CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), + /* 7000 IGP (A4+) */ + CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP), + /* 8500 AIW */ + CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2), + /* 8700/8800 */ + CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2), + /* 8500 */ + CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2), + /* 9100 */ + CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2), + /* Mobility M7 */ + CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + /* 7500 */ + CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2), + /* Mobility M9 */ + CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + /* 9000/Pro */ + CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2), + /* Mobility 9100 IGP (U3) */ + CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), + /* 9100 IGP (A5) */ + CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP), + CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP), + /* Mobility 9200 (M9+) */ + CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + /* 9200 */ + CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2), + /* 9500 */ + CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2), + /* 9600TX / FireGL Z1 */ + CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2), + /* 9700/9500/Pro/FireGL X1 */ + CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2), + /* Mobility M10/M11 */ + CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + /* 9600/FireGL T2 */ + CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2), + /* 9800/Pro/FileGL X2 */ + CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2), + /* Newer stuff */ + CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2), + /* Original Radeon/7200 */ + CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0), + CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0), + CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0), + CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0), + { 0, 0, 0, 0, 0, 0, 0 } +}; + + +typedef struct +{ + uint16_t reg; + uint32_t val; +} reg_val; + + +/* these common regs are cleared before mode setting so they do not + * interfere with anything + */ +static reg_val common_regs[] = +{ + { OVR_CLR, 0 }, + { OVR_WID_LEFT_RIGHT, 0 }, + { OVR_WID_TOP_BOTTOM, 0 }, + { OV0_SCALE_CNTL, 0 }, + { SUBPIC_CNTL, 0 }, + { VIPH_CONTROL, 0 }, + { I2C_CNTL_1, 0 }, + { GEN_INT_CNTL, 0 }, + { CAP0_TRIG_CNTL, 0 }, + { CAP1_TRIG_CNTL, 0 }, +}; + +extern struct fb_info *info_fb; +#define rinfo ((struct radeonfb_info *) info_fb->par) +static uint32_t inreg(uint32_t addr) +{ + return INREG(addr); +} + +static void outreg(uint32_t addr, uint32_t val) +{ + OUTREG(addr, val); +} + +#undef rinfo +#undef INREG +#define INREG inreg +#undef OUTREG +#define OUTREG outreg + +void _OUTREGP(struct radeonfb_info *rinfo, uint32_t addr, uint32_t val, uint32_t mask) +{ + uint32_t tmp; + tmp = INREG(addr); + tmp &= (mask); + tmp |= (val); + OUTREG(addr, tmp); +} + +/* + * Note about PLL register accesses: + * + * I have removed the spinlock on them on purpose. The driver now + * expects that it will only manipulate the PLL registers in normal + * task environment, where radeon_msleep() will be called, protected + * by a semaphore (currently the console semaphore) so that no conflict + * will happen on the PLL register index. + * + * With the latest changes to the VT layer, this is guaranteed for all + * calls except the actual drawing/blits which aren't supposed to use + * the PLL registers anyway + * + * This is very important for the workarounds to work properly. The only + * possible exception to this rule is the call to unblank(), which may + * be done at irq time if an oops is in progress. + */ +void radeon_pll_errata_after_index(struct radeonfb_info *rinfo) +{ + if (!(rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS)) + return; + (void) INREG(CLOCK_CNTL_DATA); + (void) INREG(CRTC_GEN_CNTL); +} + +void radeon_pll_errata_after_data(struct radeonfb_info *rinfo) +{ + if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) + { + /* we can't deal with posted writes here ... */ + radeon_msleep(5); + } + + if (rinfo->errata & CHIP_ERRATA_R300_CG) + { + uint32_t save, tmp; + save = INREG(CLOCK_CNTL_INDEX); + tmp = save & ~(0x3f | PLL_WR_EN); + OUTREG(CLOCK_CNTL_INDEX, tmp); + tmp = INREG(CLOCK_CNTL_DATA); + OUTREG(CLOCK_CNTL_INDEX, save); + } +} + +uint32_t __INPLL(struct radeonfb_info *rinfo, uint32_t addr) +{ + uint32_t data; + + OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); + radeon_pll_errata_after_index(rinfo); + data = INREG(CLOCK_CNTL_DATA); + radeon_pll_errata_after_data(rinfo); + + return data; +} + +void __OUTPLL(struct radeonfb_info *rinfo, uint32_t index, uint32_t val) +{ + OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080); + radeon_pll_errata_after_index(rinfo); + OUTREG(CLOCK_CNTL_DATA, val); + radeon_pll_errata_after_data(rinfo); +} + +void __OUTPLLP(struct radeonfb_info *rinfo, uint32_t index, uint32_t val, uint32_t mask) +{ + uint32_t tmp; + + tmp = __INPLL(rinfo, index); + tmp &= (mask); + tmp |= (val); + __OUTPLL(rinfo, index, tmp); +} + +static __inline int32_t round_div(int32_t num, int32_t den) +{ + return(num + (den / 2)) / den; +} + +static __inline uint32_t read_vline_crnt(struct radeonfb_info *rinfo) +{ + return (INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3FF; +} + +static int32_t radeon_map_ROM(struct radeonfb_info *rinfo) +{ + uint16_t dptr; + uint8_t rom_type; + + /* + * If this is a primary card, there is a shadow copy of the + * ROM somewhere in the first meg. We will just ignore the copy + * and use the ROM directly. + */ + + /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */ + + uint32_t temp; + + temp = inreg(MPP_TB_CONFIG); + + temp &= 0x00ffffffu; + temp |= 0x04 << 24; + OUTREG(MPP_TB_CONFIG, temp); + temp = INREG(MPP_TB_CONFIG); + + if (rinfo->bios_seg == NULL) + { + err("no ROM found on ATI card\r\n"); + return -1; + } + + /* Very simple test to make sure it appeared */ + if (BIOS_IN16(0) != 0xaa55) + { + err("Invalid ROM signature 0x%04x instead of 0x%04x found\r\n", BIOS_IN16(0), 0xaa55); + goto failed; + } + + /* Look for the PCI data to check the ROM type */ + dptr = BIOS_IN16(0x18); + + /* + * Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM + * for now, until I've verified this works everywhere. The goal here is more + * to phase out Open Firmware images. + * + * Currently, we only look at the first PCI data, we could iteratre and deal with + * them all, and we should use fb_bios_start relative to start of image and not + * relative start of ROM, but so far, I never found a dual-image ATI card + * + * typedef struct + * { + * u32 signature; + 0x00 + * u16 vendor; + 0x04 + * u16 device; + 0x06 + * u16 reserved_1; + 0x08 + * u16 dlen; + 0x0a + * u8 drevision; + 0x0c + * u8 class_hi; + 0x0d + * u16 class_lo; + 0x0e + * u16 ilen; + 0x10 + * u16 irevision; + 0x12 + * u8 type; + 0x14 + * u8 indicator; + 0x15 + * u16 reserved_2; + 0x16 + * } pci_data_t; + */ + + if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) + { + err("PCI DATA signature in ROM incorrect: %p\r\n", BIOS_IN32(dptr)); + goto anyway; + } + + rom_type = BIOS_IN8(dptr + 0x14); + switch(rom_type) + { + case 0: + inf("Found Intel x86 BIOS ROM Image\r\n"); + break; + case 1: + inf("Found Open Firmware ROM Image\r\n"); + goto failed; + case 2: + inf("Found HP PA-RISC ROM Image\r\n"); + goto failed; + default: + inf("Found unknown type %d ROM Image\r\n", rom_type); + goto failed; + } + +anyway: + /* Locate the flat panel infos, do some sanity checking !!! */ + rinfo->fp_bios_start = BIOS_IN16(0x48); + dbg("BIOS start offset: %p\r\n", BIOS_IN16(0x48)); + + /* Save BIOS PLL informations */ + + uint16_t pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30); + + dbg("BIOS PLL info block offset: %p\r\n", BIOS_IN16(rinfo->fp_bios_start + 0x30)); + rinfo->bios_pll.sclk = BIOS_IN16(pll_info_block + 0x08); + rinfo->bios_pll.mclk = BIOS_IN16(pll_info_block + 0x0a); + rinfo->bios_pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e); + rinfo->bios_pll.ref_div = BIOS_IN16(pll_info_block + 0x10); + rinfo->bios_pll.ppll_min = BIOS_IN32(pll_info_block + 0x12); + rinfo->bios_pll.ppll_max = BIOS_IN32(pll_info_block + 0x16); + + return 0; + +failed: + rinfo->bios_seg = NULL; + return -1; //-ENXIO; +} + +/* + * Read PLL infos from chip registers + */ +static int32_t radeon_probe_pll_params(struct radeonfb_info *rinfo) +{ + uint8_t ppll_div_sel; + uint32_t Ns; + uint32_t Nm; + uint32_t M; + uint32_t sclk; + uint32_t mclk; + uint32_t tmp; + uint32_t ref_div; + int32_t hTotal; + int32_t vTotal; + int32_t num; + int32_t denom; + int32_t m; + int32_t n; + double hz; + double vclk; + int32_t xtal; + uint32_t start_tv; + uint32_t stop_tv; + int32_t timeout = 0; + int32_t ipl; + uint32_t vline; + + /* + * Ugh, we cut interrupts, bad bad bad, but we want some precision + * here, so... --BenH + */ + ipl = set_ipl(0); + + dbg("\r\n"); + + /* Flush PCI buffers ? */ + tmp = INREG16(DEVICE_ID); + + start_tv = get_timer(); + while ((vline = read_vline_crnt(rinfo)) != 0) + { + if ((start_tv - get_timer()) > US_TO_TIMER(10000000UL)) /* 10 sec */ + { + timeout = 1; + dbg("timeout\r\n"); + break; + } + } + + if (!timeout) + { + start_tv = get_timer(); + while (read_vline_crnt(rinfo) == 0) + { + if ((start_tv - get_timer()) > US_TO_TIMER(1000000UL)) /* 1 sec */ + { + timeout = 1; + dbg("timeout2\r\n"); + break; + } + } + + if (!timeout) + { + while (read_vline_crnt(rinfo) != 0) + { + if ((start_tv - get_timer()) > US_TO_TIMER(10000000UL)) /* 10 sec */ + { + timeout = 1; + dbg("timeout3\r\n"); + break; + } + } + } + } + stop_tv = get_timer(); + + set_ipl(ipl); + + hz = US_TO_TIMER(1000000.0) / (double)(start_tv - stop_tv); + dbg("hz %d\r\n", (int32_t) hz); + + // OUTREG(CRTC_H_TOTAL_DISP, 640 / 8 - 1); + // OUTREG(CRTC_V_TOTAL_DISP, 480 - 1); + dbg("h_total=%d vtotal=%d\r\n", INREG(CRTC_H_TOTAL_DISP), INREG(CRTC_V_TOTAL_DISP)); + + hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8; + vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1); + dbg("hTotal=%d\r\n", hTotal); + dbg("vTotal=%d\r\n", vTotal); + + vclk = (double) hTotal * (double) vTotal * hz; + dbg("vclk=%d\r\n", (int32_t) vclk); + + switch ((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) + { + case 1: + n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff); + m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff); + num = 2 * n; + denom = 2 * m; + break; + + case 2: + n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff); + m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff); + num = 2 * n; + denom = 2 * m; + break; + + case 0: + default: + num = 1; + denom = 1; + break; + } + + ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3; + radeon_pll_errata_after_index(rinfo); + + n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff); + m = (INPLL(PPLL_REF_DIV) & 0x3ff); + + num *= n; + denom *= m; + + switch((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) + { + case 1: + denom *= 2; + break; + + case 2: + denom *= 4; + break; + + case 3: + denom *= 8; + break; + + case 4: + denom *= 3; + break; + + case 6: + denom *= 6; + break; + + case 7: + denom *= 12; + break; + } + vclk *= (double) denom; + vclk /= (double) (1000 * num); + xtal = (int32_t) vclk; + + if ((xtal > 26900) && (xtal < 27100)) + xtal = 2700; /* 27 MHz */ + else if ((xtal > 14200) && (xtal < 14400)) + xtal = 1432; + else if ((xtal > 29400) && (xtal < 29600)) + xtal = 2950; + else + { + err("xtal calculation failed: %d\r\n", xtal); + return -1; /* error */ + } + + tmp = INPLL(M_SPLL_REF_FB_DIV); + ref_div = INPLL(PPLL_REF_DIV) & 0x3ff; + + Ns = (tmp & 0xff0000) >> 16; + Nm = (tmp & 0xff00) >> 8; + M = (tmp & 0xff); + + sclk = round_div((2 * Ns * xtal), (2 * M)); + mclk = round_div((2 * Nm * xtal), (2 * M)); + + /* we're done, hopefully these are sane values */ + rinfo->pll.ref_clk = xtal; + rinfo->pll.ref_div = ref_div; + rinfo->pll.sclk = sclk; + rinfo->pll.mclk = mclk; + + return 0; +} + +/* + * Retreive PLL infos by register probing... + */ +static void radeon_get_pllinfo(struct radeonfb_info *rinfo) +{ + /* + * In the case nothing works, these are defaults; they are mostly + * incomplete, however. It does provide ppll_max and _min values + * even for most other methods, however. + */ + dbg("\r\n"); + + switch(rinfo->chipset) + { + case PCI_DEVICE_ID_ATI_RADEON_QW: + case PCI_DEVICE_ID_ATI_RADEON_QX: + rinfo->pll.ppll_max = 35000; + rinfo->pll.ppll_min = 12000; + rinfo->pll.mclk = 23000; + rinfo->pll.sclk = 23000; + rinfo->pll.ref_clk = 2700; + break; + + case PCI_DEVICE_ID_ATI_RADEON_QL: + case PCI_DEVICE_ID_ATI_RADEON_QN: + case PCI_DEVICE_ID_ATI_RADEON_QO: + case PCI_DEVICE_ID_ATI_RADEON_Ql: + case PCI_DEVICE_ID_ATI_RADEON_BB: + rinfo->pll.ppll_max = 35000; + rinfo->pll.ppll_min = 12000; + rinfo->pll.mclk = 27500; + rinfo->pll.sclk = 27500; + rinfo->pll.ref_clk = 2700; + break; + + case PCI_DEVICE_ID_ATI_RADEON_Id: + case PCI_DEVICE_ID_ATI_RADEON_Ie: + case PCI_DEVICE_ID_ATI_RADEON_If: + case PCI_DEVICE_ID_ATI_RADEON_Ig: + rinfo->pll.ppll_max = 35000; + rinfo->pll.ppll_min = 12000; + rinfo->pll.mclk = 25000; + rinfo->pll.sclk = 25000; + rinfo->pll.ref_clk = 2700; + break; + + case PCI_DEVICE_ID_ATI_RADEON_ND: + case PCI_DEVICE_ID_ATI_RADEON_NE: + case PCI_DEVICE_ID_ATI_RADEON_NF: + case PCI_DEVICE_ID_ATI_RADEON_NG: + rinfo->pll.ppll_max = 40000; + rinfo->pll.ppll_min = 20000; + rinfo->pll.mclk = 27000; + rinfo->pll.sclk = 27000; + rinfo->pll.ref_clk = 2700; + break; + + case PCI_DEVICE_ID_ATI_RADEON_QD: + case PCI_DEVICE_ID_ATI_RADEON_QE: + case PCI_DEVICE_ID_ATI_RADEON_QF: + case PCI_DEVICE_ID_ATI_RADEON_QG: + default: + rinfo->pll.ppll_max = 35000; + rinfo->pll.ppll_min = 12000; + rinfo->pll.mclk = 16600; + rinfo->pll.sclk = 16600; + rinfo->pll.ref_clk = 2700; + break; + } + rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; + + /* + * Check out if we have an X86 which gave us some PLL informations + * and if yes, retreive them + */ + if (!force_measure_pll && (rinfo->bios_seg != NULL)) + { + rinfo->pll.sclk = rinfo->bios_pll.sclk; + rinfo->pll.mclk = rinfo->bios_pll.mclk; + rinfo->pll.ref_clk = rinfo->bios_pll.ref_clk; + rinfo->pll.ref_div = rinfo->bios_pll.ref_div; + rinfo->pll.ppll_min = rinfo->bios_pll.ppll_min; + rinfo->pll.ppll_max = rinfo->bios_pll.ppll_max; + inf("Retreived PLL infos from BIOS\r\n"); + + goto found; + } + + /* + * We didn't get PLL parameters from either OF or BIOS, we try to + * probe them + */ + if (radeon_probe_pll_params(rinfo) == 0) + { + inf("Retreived PLL infos from registers\r\n"); + goto found; + } + + /* + * Fall back to already-set defaults... + */ + inf("Used default PLL infos\r\n"); + +found: + /* + * Some methods fail to retreive SCLK and MCLK values, we apply default + * settings in this case (200Mhz). If that really happne often, we could + * fetch from registers instead... + */ + if (rinfo->pll.mclk == 0) + rinfo->pll.mclk = 20000; + if (rinfo->pll.sclk == 0) + rinfo->pll.sclk = 20000; + + dbg("Reference=%d MHz (RefDiv=0x%x) Memory=%d MHz\r\n", + rinfo->pll.ref_clk / 100, rinfo->pll.ref_div, rinfo->pll.mclk / 100); + dbg("System=%d MHz PLL min %d, max %d\r\n", + rinfo->pll.sclk / 100, rinfo->pll.ppll_min, rinfo->pll.ppll_max); +} + +static int32_t var_to_depth(const struct fb_var_screeninfo *var) +{ + if (var->bits_per_pixel != 16) + return var->bits_per_pixel; + + return(var->green.length == 5) ? 15 : 16; +} + +int32_t radeonfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) +{ + struct radeonfb_info *rinfo = info->par; + struct fb_var_screeninfo v; + int32_t nom, den; + uint32_t pitch; + + dbg("\r\n"); + + /* clocks over 135 MHz have heat isues with DVI on RV100 */ + if ((rinfo->mon1_type == MT_DFP) && (rinfo->family == CHIP_FAMILY_RV100) && ((100000000 / var->pixclock) > 13500)) + { + err("mode %d x %d x %d", var->xres, var->yres, var->bits_per_pixel); + err("rejected, RV100 DVI clock over 135 MHz\r\n"); + + return -1; //-EINVAL; + } + + if (radeon_match_mode(rinfo, &v, var)) + { + err("invalid mode\r\n"); + return -1; //-EINVAL; + } + + switch (v.bits_per_pixel) + { + case 0 ... 8: + v.bits_per_pixel = 8; + break; + + case 9 ... 16: + v.bits_per_pixel = 16; + break; + +#if 0 /* Doesn't seem to work */ + case 17 ... 24: + v.bits_per_pixel = 24; + break; +#endif + case 25 ... 32: + v.bits_per_pixel = 32; + break; + + default: + err("invalid bits per pixel\r\n"); + return -1; //-EINVAL; + } + + switch (var_to_depth(&v)) + { + case 8: + nom = den = 1; + v.red.offset = v.green.offset = v.blue.offset = 0; + v.red.length = v.green.length = v.blue.length = 8; + v.transp.offset = v.transp.length = 0; + break; + + case 15: + nom = 2; + den = 1; + v.red.offset = 10; + v.green.offset = 5; + v.blue.offset = 0; + v.red.length = v.green.length = v.blue.length = 5; + v.transp.offset = v.transp.length = 0; + break; + + case 16: + nom = 2; + den = 1; + v.red.offset = 11; + v.green.offset = 5; + v.blue.offset = 0; + v.red.length = 5; + v.green.length = 6; + v.blue.length = 5; + v.transp.offset = v.transp.length = 0; + break; + + case 24: + nom = 4; + den = 1; + v.red.offset = 16; + v.green.offset = 8; + v.blue.offset = 0; + v.red.length = v.blue.length = v.green.length = 8; + v.transp.offset = v.transp.length = 0; + break; + + case 32: + nom = 4; + den = 1; + v.red.offset = 16; + v.green.offset = 8; + v.blue.offset = 0; + v.red.length = v.blue.length = v.green.length = 8; + v.transp.offset = 24; + v.transp.length = 8; + break; + + default: + err("radeonfb: mode %d x %d x %d rejected, color depth invalid\r\n ", + var->xres, var->yres, var->bits_per_pixel); + return -1; //-EINVAL; + } + + if (v.yres_virtual < v.yres) + v.yres_virtual = v.yres; + if (v.xres_virtual < v.xres) + v.xres_virtual = v.xres; + + /* + * XXX I'm adjusting xres_virtual to the pitch, that may help XFree + * with some panels, though I don't quite like this solution + */ + pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f) & ~(0x3f)) >> 6; + v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8); + + if (((v.xres_virtual * v.yres_virtual * nom) / den) > info->screen_size) + { + err("mode %d x %d rejected (screen size too small)\r\n", v.xres_virtual, v.yres_virtual); + return -1; //-EINVAL; + } + + if (v.xres_virtual < v.xres) + v.xres = v.xres_virtual; + + if (v.xoffset < 0) + v.xoffset = 0; + + if (v.yoffset < 0) + v.yoffset = 0; + + if (v.xoffset > v.xres_virtual - v.xres) + v.xoffset = v.xres_virtual - v.xres - 1; + + if (v.yoffset > v.yres_virtual - v.yres) + v.yoffset = v.yres_virtual - v.yres - 1; + + v.red.msb_right = v.green.msb_right = v.blue.msb_right = 0; + v.transp.offset = v.transp.length = v.transp.msb_right = 0; + + inf("using mode %d x %d \r\n", v.xres, v.yres); + + memcpy(var, &v, sizeof(v)); + + return 0; +} + +int32_t radeonfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) +{ + struct radeonfb_info *rinfo = info->par; + dbg("\r\n"); + if ((var->xoffset + var->xres) > var->xres_virtual) + { + dbg("xoffset = %d, xres = %d, xres_virtual=%d\r\n", + var->xoffset, var->xres, var->xres_virtual); + return -1; //-EINVAL; + } + + if (((var->yoffset * var->xres_virtual) + var->xoffset) >= + (rinfo->mapped_vram - (var->yres * var->xres * (var->bits_per_pixel / 8)))) + { + dbg("yoffset=%d, xres_virtual=%d, mapped_vram=%ld,\r\n", + "yres=%d, xres=%d, bpp=%d\r\n", + var->yoffset, var->xres_virtual, var->xoffset, rinfo->mapped_vram, + var->yres, var->xres, var->bits_per_pixel); + return -1; //-EINVAL; + } + + if (rinfo->asleep) + return 0; + + radeon_wait_for_fifo(rinfo, 2); + rinfo->fb_offset = ((var->yoffset * var->xres_virtual + var->xoffset) * var->bits_per_pixel / 8) & ~7; + rinfo->dst_pitch_offset = (rinfo->pitch << 22) | ((rinfo->fb_local_base + rinfo->fb_offset) >> 10); + OUTREG(CRTC_OFFSET, rinfo->fb_offset); + + return 0; +} + +short mirror; + +int32_t radeonfb_ioctl(uint32_t cmd, uint32_t arg, struct fb_info *info) +{ + struct radeonfb_info *rinfo = info->par; + uint32_t tmp; + uint32_t value = 0; + + switch(cmd) + { + /* + * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's + * and do something better using 2nd CRTC instead of just hackish + * routing to second output + */ + case FBIO_RADEON_SET_MIRROR: + if (!rinfo->is_mobility) + return -1; //-EINVAL; + radeon_wait_for_fifo(rinfo, 2); + + if (value & 0x01) + { + tmp = INREG(LVDS_GEN_CNTL); + tmp |= (LVDS_ON | LVDS_BLON); + } + else + { + tmp = INREG(LVDS_GEN_CNTL); + tmp &= ~(LVDS_ON | LVDS_BLON); + } + OUTREG(LVDS_GEN_CNTL, tmp); + + if (value & 0x02) + { + tmp = INREG(CRTC_EXT_CNTL); + tmp |= CRTC_CRT_ON; + mirror = 1; + } + else + { + tmp = INREG(CRTC_EXT_CNTL); + tmp &= ~CRTC_CRT_ON; + mirror = 0; + } + OUTREG(CRTC_EXT_CNTL, tmp); + return 0; + + case FBIO_RADEON_GET_MIRROR: + if (!rinfo->is_mobility) + return -1; //-EINVAL; + tmp = INREG(LVDS_GEN_CNTL); + if ((LVDS_ON | LVDS_BLON) & tmp) + value |= 0x01; + tmp = INREG(CRTC_EXT_CNTL); + if (CRTC_CRT_ON & tmp) + value |= 0x02; + return 0; + + default: + return -1; //-EINVAL; + } + return -1; //-EINVAL; +} + +int32_t radeon_screen_blank(struct radeonfb_info *rinfo, int32_t blank, int32_t mode_switch) +{ + uint32_t val; + uint32_t tmp_pix_clks; + int32_t unblank = 0; + + if (rinfo->lock_blank) + return 0; + + dbg("radeonfb: radeon_screen_blank\r\n"); + radeon_engine_idle(); + val = INREG(CRTC_EXT_CNTL); + val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS); + + switch(blank) + { + case FB_BLANK_VSYNC_SUSPEND: + val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS); + break; + + case FB_BLANK_HSYNC_SUSPEND: + val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS); + break; + + case FB_BLANK_POWERDOWN: + val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS | CRTC_HSYNC_DIS); + break; + + case FB_BLANK_NORMAL: + val |= CRTC_DISPLAY_DIS; + break; + + case FB_BLANK_UNBLANK: + default: + unblank = 1; + break; + } + OUTREG(CRTC_EXT_CNTL, val); + + switch(rinfo->mon1_type) + { + case MT_DFP: + if (unblank) + OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN), ~(FP_FPON | FP_TMDS_EN)); + else + { + if (mode_switch || blank == FB_BLANK_NORMAL) + break; + OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN)); + } + break; + + case MT_LCD: + rinfo->lvds_timer = 0; + val = INREG(LVDS_GEN_CNTL); + if (unblank) + { + uint32_t target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON + | LVDS_EN | (rinfo->init_state.lvds_gen_cntl & (LVDS_DIGON | LVDS_BL_MOD_EN)); + if ((val ^ target_val) == LVDS_DISPLAY_DIS) + OUTREG(LVDS_GEN_CNTL, target_val); + else if ((val ^ target_val) != 0) + { + OUTREG(LVDS_GEN_CNTL, target_val & ~(LVDS_ON | LVDS_BL_MOD_EN)); + rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; + rinfo->init_state.lvds_gen_cntl |= target_val & LVDS_STATE_MASK; + if (mode_switch) + { + radeon_msleep(rinfo->panel_info.pwr_delay); + OUTREG(LVDS_GEN_CNTL, target_val); + } + else + { + rinfo->pending_lvds_gen_cntl = target_val; + rinfo->lvds_timer = (int32_t)rinfo->panel_info.pwr_delay; + } + } + } + else + { + val |= LVDS_DISPLAY_DIS; + OUTREG(LVDS_GEN_CNTL, val); + /* We don't do a full switch-off on a simple mode switch */ + if (mode_switch || blank == FB_BLANK_NORMAL) + break; + + /* Asic bug, when turning off LVDS_ON, we have to make sure + * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off + */ + tmp_pix_clks = INPLL(PIXCLKS_CNTL); + if (rinfo->is_mobility || rinfo->is_IGP) + OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb); + + val &= ~(LVDS_BL_MOD_EN); + OUTREG(LVDS_GEN_CNTL, val); + + wait(100); + + val &= ~(LVDS_ON | LVDS_EN); + OUTREG(LVDS_GEN_CNTL, val); + val &= ~LVDS_DIGON; + rinfo->pending_lvds_gen_cntl = val; + rinfo->lvds_timer = (int32_t)rinfo->panel_info.pwr_delay; + rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; + rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK; + + if (rinfo->is_mobility || rinfo->is_IGP) + OUTPLL(PIXCLKS_CNTL, tmp_pix_clks); + } + break; + case MT_CRT: + // todo: powerdown DAC + default: + break; + } + /* let fbcon do a soft blank for us */ + return(blank == FB_BLANK_NORMAL) ? -1 /* -EINVAL */ : 0; +} + +int32_t radeonfb_blank(int32_t blank, struct fb_info *info) +{ + struct radeonfb_info *rinfo = info->par; + + if (rinfo->asleep) + return 0; + + return radeon_screen_blank(rinfo, blank, 0); +} + +static int32_t radeon_setcolreg(uint32_t regno, uint32_t red, uint32_t green, + uint32_t blue, uint32_t transp, struct fb_info *info) +{ + struct radeonfb_info *rinfo = info->par; + uint32_t pindex; + + if (regno > 255) + return 1; + + red >>= 8; + green >>= 8; + blue >>= 8; + + rinfo->palette[regno].red = red; + rinfo->palette[regno].green = green; + rinfo->palette[regno].blue = blue; + + /* default */ + pindex = regno; + if (!rinfo->asleep) + { + radeon_wait_for_fifo(rinfo, 9); + if (rinfo->bpp == 16) + { + pindex = regno * 8; + if (rinfo->depth == 16 && regno > 63) + return 1; + if (rinfo->depth == 15 && regno > 31) + return 1; + + /* + * For 565, the green component is mixed one order + * below + */ + if (rinfo->depth == 16) + { + OUTREG(PALETTE_INDEX, pindex>>1); + OUTREG(PALETTE_DATA,(rinfo->palette[regno>>1].red << 16) + | (green << 8) | (rinfo->palette[regno>>1].blue)); + green = rinfo->palette[regno<<1].green; + } + } + if (rinfo->depth != 16 || regno < 32) + { + OUTREG(PALETTE_INDEX, pindex); + OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue); + } + } + return 0; +} + +int32_t radeonfb_setcolreg(uint32_t regno, uint32_t red, uint32_t green, + uint32_t blue, uint32_t transp, struct fb_info *info) +{ + struct radeonfb_info *rinfo = info->par; + uint32_t dac_cntl2, vclk_cntl = 0; + int32_t rc; + + if (!rinfo->asleep) + { + if (rinfo->is_mobility) + { + vclk_cntl = INPLL(VCLK_ECP_CNTL); + OUTPLL(VCLK_ECP_CNTL, vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb); + } + + /* Make sure we are on first palette */ + if (rinfo->has_CRTC2) + { + dac_cntl2 = INREG(DAC_CNTL2); + dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL; + OUTREG(DAC_CNTL2, dac_cntl2); + } + } + rc = radeon_setcolreg(regno, red, green, blue, transp, info); + if (!rinfo->asleep && rinfo->is_mobility) + OUTPLL(VCLK_ECP_CNTL, vclk_cntl); + + return rc; +} + +static void radeon_save_state(struct radeonfb_info *rinfo, struct radeon_regs *save) +{ + /* CRTC regs */ + save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL); + save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL); + save->crtc_more_cntl = INREG(CRTC_MORE_CNTL); + save->dac_cntl = INREG(DAC_CNTL); + save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP); + save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID); + save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP); + save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID); + save->crtc_pitch = INREG(CRTC_PITCH); + save->surface_cntl = INREG(SURFACE_CNTL); + + /* FP regs */ + save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP); + save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP); + save->fp_gen_cntl = INREG(FP_GEN_CNTL); + save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID); + save->fp_horz_stretch = INREG(FP_HORZ_STRETCH); + save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID); + save->fp_vert_stretch = INREG(FP_VERT_STRETCH); + save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL); + save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL); + save->tmds_crc = INREG(TMDS_CRC); + save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL); + save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL); + /* PLL regs */ + + save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f; + radeon_pll_errata_after_index(rinfo); + save->ppll_div_3 = INPLL(PPLL_DIV_3); + save->ppll_ref_div = INPLL(PPLL_REF_DIV); +} + +static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode) +{ + int32_t i; + + dbg("\r\n"); + radeon_wait_for_fifo(rinfo, 20); + +#if 0 + /* Workaround from XFree */ + if (rinfo->is_mobility) + { + /* A temporal workaround for the occational blanking on certain laptop + * panels. This appears to related to the PLL divider registers + * (fail to lock?). It occurs even when all dividers are the same + * with their old settings. In this case we really don't need to + * fiddle with PLL registers. By doing this we can avoid the blanking + * problem with some panels. + */ + if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) + && (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) + { + /* We still have to force a switch to selected PPLL div thanks to + * an XFree86 driver bug which will switch it away in some cases + * even when using UseFDev */ + OUTREGP(CLOCK_CNTL_INDEX, + mode->clk_cntl_index & PPLL_DIV_SEL_MASK, + ~PPLL_DIV_SEL_MASK); + radeon_pll_errata_after_index(rinfo); + radeon_pll_errata_after_data(rinfo); + return; + } + } +#endif + + /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ + OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK); + + /* Reset PPLL & enable atomic update */ + OUTPLLP(PPLL_CNTL, PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN, + ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); + + /* Switch to selected PPLL divider */ + OUTREGP(CLOCK_CNTL_INDEX, mode->clk_cntl_index & PPLL_DIV_SEL_MASK, ~PPLL_DIV_SEL_MASK); + radeon_pll_errata_after_index(rinfo); + radeon_pll_errata_after_data(rinfo); + + /* Set PPLL ref. div */ + if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_RS300 + || rinfo->family == CHIP_FAMILY_R350 || rinfo->family == CHIP_FAMILY_RV350) + { + if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) + { + /* + * When restoring console mode, use saved PPLL_REF_DIV + * setting. + */ + OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); + } + else + { + /* R300 uses ref_div_acc field as real ref divider */ + OUTPLLP(PPLL_REF_DIV,(mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),~R300_PPLL_REF_DIV_ACC_MASK); + } + } + else + OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); + + /* Set PPLL divider 3 & post divider*/ + OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); + OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); + + /* Write update */ + while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); + OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W); + + /* Wait read update complete */ + /* FIXME: Certain revisions of R300 can't recover here. Not sure of + the cause yet, but this workaround will mask the problem for now. + Other chips usually will pass at the very first test, so the + workaround shouldn't have any effect on them. */ + + for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++); + OUTPLL(HTOTAL_CNTL, 0); + + /* Clear reset & atomic update */ + OUTPLLP(PPLL_CNTL, 0, ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); + + /* We may want some locking ... oh well */ + radeon_msleep(5); + + /* Switch back VCLK source to PPLL */ + OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK); +} + +static void radeon_wait_vbl(struct fb_info *info) +{ + uint32_t cnt = INREG(CRTC_CRNT_FRAME); + + while (cnt == INREG(CRTC_CRNT_FRAME)); +} + +static void radeon_timer_func(void) +{ + struct fb_info *info = info_fb; + struct radeonfb_info *rinfo = info->par; + struct fb_var_screeninfo var; + uint32_t x; + uint32_t y; + int32_t chg; + int32_t disp; + + static int32_t start_timer; + + /* delayed LVDS panel power up/down */ + if (rinfo->lvds_timer) + { + if (!start_timer) + start_timer = get_timer(); + + if (((start_timer - get_timer())) >= (int32_t)rinfo->lvds_timer) + { + rinfo->lvds_timer = 0; + radeon_engine_idle(); + OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl); + } + } + else + start_timer = 0; + + if (rinfo->RenderCallback != NULL) + rinfo->RenderCallback(rinfo); + + if ((info->screen_mono != NULL) && info->update_mono) + { + int32_t foreground = 255; + int32_t background = 0; + uint8_t *src_buf = (uint8_t *) info->screen_mono; + int32_t skipleft = ((int32_t) src_buf & 3) << 3; + int32_t dst_x = 0; + int32_t w = (int32_t) info->var.xres_virtual; + int32_t h = (int32_t) info->var.yres_virtual; + + // info->fbops->SetClippingRectangle(info,0,0,w-1,h-1); + + src_buf = (uint8_t*) ((int32_t) src_buf & ~3); + dst_x -= (int32_t) skipleft; + w += (int32_t) skipleft; + info->fbops->SetupForScanlineCPUToScreenColorExpandFill(info, (int32_t) foreground, (int32_t) background, 3, 0xffffffff); + info->fbops->SubsequentScanlineCPUToScreenColorExpandFill(info, (int32_t) dst_x, 0, w, h, skipleft); + + while (--h >= 0) + { + info->fbops->SubsequentScanline(info, (uint32_t *) src_buf); + src_buf += (info->var.xres_virtual >> 3); + } + + // info->fbops->DisableClipping(info); + if (info->update_mono > 0) + info->update_mono = 0; + } + + if ((info->var.xres_virtual != info->var.xres) + || (info->var.yres_virtual != info->var.yres)) + { + int32_t ipl; + ipl = set_ipl(0); + + chg = 0; + x = info->var.xoffset; + y = info->var.yoffset; + + if (((x + info->var.xres) < info->var.xres_virtual) && (rinfo->cursor_x >= (info->var.xres - 8))) + { + x += 8; + chg = 1; + } + else if ((x >= 8) && (rinfo->cursor_x <= 8)) + { + x -= 8; + chg = 1; + } + + if (((y + info->var.yres) < info->var.yres_virtual) && (rinfo->cursor_y >= (info->var.yres - 8))) + { + y += 8; + chg = 1; + } + else if ((y >=8) && (rinfo->cursor_y <= 8)) + { + y -= 8; + chg = 1; + } + + if (chg) + { + memcpy(&var, &info->var, sizeof(struct fb_var_screeninfo)); + var.xoffset = x; + var.yoffset = y; + disp = rinfo->cursor_show; + if (disp) + info->fbops->HideCursor(info); + + fb_pan_display(info,&var); + + if (disp) + info->fbops->ShowCursor(info); + } + set_ipl(ipl); + } +} + +/* + * Apply a video mode. This will apply the whole register set, including + * the PLL registers, to the card + */ +void radeon_write_mode(struct radeonfb_info *rinfo, struct radeon_regs *mode, int32_t regs_only) +{ + int32_t i; + int32_t primary_mon = PRIMARY_MONITOR(rinfo); + + dbg("radeonfb: radeon_write_mode\r\n"); + + if (!regs_only) + radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0); + + radeon_wait_for_fifo(rinfo, 31); + + for (i = 0; i < 10; i++) + OUTREG(common_regs[i].reg, common_regs[i].val); + + /* Apply surface registers */ + for (i = 0; i < 8; i++) + { + OUTREG(SURFACE0_LOWER_BOUND + 0x10 * i, mode->surf_lower_bound[i]); + OUTREG(SURFACE0_UPPER_BOUND + 0x10 * i, mode->surf_upper_bound[i]); + OUTREG(SURFACE0_INFO + 0x10 * i, mode->surf_info[i]); + } + OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); + OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); + OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl); + OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); + OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); + OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); + OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); + OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); + rinfo->fb_offset = 0; + rinfo->dst_pitch_offset = (rinfo->pitch << 22) | ((rinfo->fb_local_base + rinfo->fb_offset) >> 10); + OUTREG(CRTC_OFFSET, rinfo->fb_offset); +#ifdef RADEON_TILING + if (rinfo->tilingEnabled) + { + if (rinfo->family >= CHIP_FAMILY_R300) + OUTREG(CRTC_OFFSET_CNTL, R300_CRTC_X_Y_MODE_EN | R300_CRTC_MICRO_TILE_BUFFER_DIS | R300_CRTC_MACRO_TILE_EN); + else + OUTREG(CRTC_OFFSET_CNTL, CRTC_OFFSET_CNTL__CRTC_TILE_EN); + } + else +#endif + OUTREG(CRTC_OFFSET_CNTL, 0); + + OUTREG(CRTC_PITCH, mode->crtc_pitch); + OUTREG(SURFACE_CNTL, mode->surface_cntl); + radeon_write_pll_regs(rinfo, mode); + + if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) + { + radeon_wait_for_fifo(rinfo, 10); + OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp); + OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp); + OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid); + OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid); + OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch); + OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch); + OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl); + OUTREG(TMDS_CRC, mode->tmds_crc); + OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl); + } + + if (!regs_only) + radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0); + radeon_wait_for_fifo(rinfo, 2); + OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl); +} + +/* + * Calculate the PLL values for a given mode + */ +static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs, uint32_t freq) +{ + static const struct + { + int32_t divider; + int32_t bitvalue; + } *post_div, + post_divs[] = + { + { 1, 0 }, + { 2, 1 }, + { 4, 2 }, + { 8, 3 }, + { 3, 4 }, + { 16, 5 }, + { 6, 6 }, + { 12, 7 }, + { 0, 0 }, + }; + int32_t fb_div; + int32_t pll_output_freq = 0; + int32_t uses_dvo = 0; + + /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm + * not sure which model starts having FP2_GEN_CNTL, I assume anything more + * recent than an r(v)100... + */ +#if 1 + /* XXX I had reports of flicker happening with the cinema display + * on TMDS1 that seem to be fixed if I also forbid odd dividers in + * this case. This could just be a bandwidth calculation issue, I + * haven't implemented the bandwidth code yet, but in the meantime, + * forcing uses_dvo to 1 fixes it and shouln't have bad side effects, + * I haven't seen a case were were absolutely needed an odd PLL + * divider. I'll find a better fix once I have more infos on the + * real cause of the problem. + */ + while (rinfo->has_CRTC2) + { + uint32_t fp2_gen_cntl = INREG(FP2_GEN_CNTL); + uint32_t disp_output_cntl; + int32_t source; + + /* FP2 path not enabled */ + if ((fp2_gen_cntl & FP2_ON) == 0) + break; + + /* Not all chip revs have the same format for this register, + * extract the source selection + */ + if (rinfo->family == CHIP_FAMILY_R200 || rinfo->family == CHIP_FAMILY_R300 + || rinfo->family == CHIP_FAMILY_R350 || rinfo->family == CHIP_FAMILY_RV350) + { + source = (fp2_gen_cntl >> 10) & 0x3; + /* sourced from transform unit, check for transform unit + * own source + */ + if (source == 3) + { + disp_output_cntl = INREG(DISP_OUTPUT_CNTL); + source = (disp_output_cntl >> 12) & 0x3; + } + } + else + source = (fp2_gen_cntl >> 13) & 0x1; + + /* sourced from CRTC2 -> exit */ + if (source == 1) + break; + + /* so we end up on CRTC1, let's set uses_dvo to 1 now */ + uses_dvo = 1; + break; + } +#else + uses_dvo = 1; +#endif + if (freq > rinfo->pll.ppll_max) + freq = rinfo->pll.ppll_max; + if (freq * 12 < rinfo->pll.ppll_min) + freq = rinfo->pll.ppll_min / 12; + for (post_div = &post_divs[0]; post_div->divider; ++post_div) + { + pll_output_freq = post_div->divider * freq; + + /* + * If we output to the DVO port (external TMDS), we don't allow an + * odd PLL divider as those aren't supported on this path + */ + if (uses_dvo && (post_div->divider & 1)) + continue; + + if (pll_output_freq >= rinfo->pll.ppll_min && + pll_output_freq <= rinfo->pll.ppll_max) + break; + } + + /* If we fall through the bottom, try the "default value" + given by the terminal post_div->bitvalue */ + if (!post_div->divider) + { + post_div = &post_divs[post_div->bitvalue]; + pll_output_freq = post_div->divider * freq; + } + + /* If we fall through the bottom, try the "default value" + given by the terminal post_div->bitvalue */ + if ( !post_div->divider ) + { + post_div = &post_divs[post_div->bitvalue]; + pll_output_freq = post_div->divider * freq; + } + fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,rinfo->pll.ref_clk); + regs->ppll_ref_div = rinfo->pll.ref_div; + regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16); +} + +int32_t radeonfb_set_par(struct fb_info *info) +{ + struct radeonfb_info *rinfo = info->par; + struct fb_var_screeninfo *mode = &info->var; + struct radeon_regs *newmode; + int32_t hTotal; + int32_t vTotal; + int32_t hSyncStart; + int32_t hSyncEnd; + int32_t vSyncStart; + int32_t vSyncEnd; + + // FIXME: int32_t hSyncPol; this is not used anywhere + // FIXME: int32_t vSyncPol; this is not used anywhere + // FIXME: int32_t cSync; this is not used anywhere + + static uint8_t hsync_adj_tab[] = { 0, 0x12, 9, 9, 6, 5 }; + static uint8_t hsync_fudge_fp[] = { 2, 2, 0, 0, 5, 5 }; + uint32_t sync; + uint32_t h_sync_pol; + uint32_t v_sync_pol; + uint32_t dotClock; + uint32_t pixClock; + int32_t i; + int32_t freq; + int32_t format = 0; + int32_t nopllcalc = 0; + int32_t hsync_start; + int32_t hsync_fudge; + + // int32_t bytpp; FIXME: this doesn't seem to be used anywhere + int32_t hsync_wid; + int32_t vsync_wid; + int32_t primary_mon = PRIMARY_MONITOR(rinfo); + int32_t depth = var_to_depth(mode); + int32_t use_rmx = 0; + + dbg("depth=%d\r\n", depth); + + newmode = (struct radeon_regs *) driver_mem_alloc(sizeof(struct radeon_regs)); + if (!newmode) + { + err("driver_mem_alloc() failed (ret=%p)\r\n", newmode); + return -1; + } + + /* + * We always want engine to be idle on a mode switch, even + * if we won't actually change the mode + */ + radeon_engine_idle(); + + dbg("xres=%d yres=%d\r\n", mode->xres, mode->yres); + + hSyncStart = mode->xres + mode->right_margin; + hSyncEnd = hSyncStart + mode->hsync_len; + hTotal = hSyncEnd + mode->left_margin; + + vSyncStart = mode->yres + mode->lower_margin; + vSyncEnd = vSyncStart + mode->vsync_len; + vTotal = vSyncEnd + mode->upper_margin; + + dbg("pixel clock = %d\r\n", mode->pixclock); + + pixClock = mode->pixclock; + + dbg("sync = %d\r\n", mode->sync); + sync = mode->sync; + + h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; + v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; + + if (primary_mon == MT_DFP || primary_mon == MT_LCD) + { + if (rinfo->panel_info.xres < mode->xres) + mode->xres = rinfo->panel_info.xres; + + if (rinfo->panel_info.yres < mode->yres) + mode->yres = rinfo->panel_info.yres; + + hTotal = mode->xres + rinfo->panel_info.hblank; + hSyncStart = mode->xres + rinfo->panel_info.hOver_plus; + hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width; + + vTotal = mode->yres + rinfo->panel_info.vblank; + vSyncStart = mode->yres + rinfo->panel_info.vOver_plus; + vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width; + + h_sync_pol = !rinfo->panel_info.hAct_high; + v_sync_pol = !rinfo->panel_info.vAct_high; + + pixClock = 100000000 / rinfo->panel_info.clock; + + if (rinfo->panel_info.use_bios_dividers) + { + nopllcalc = 1; + newmode->ppll_div_3 = rinfo->panel_info.fbk_divider | (rinfo->panel_info.post_divider << 16); + newmode->ppll_ref_div = rinfo->panel_info.ref_divider; + } + } + + dotClock = 1000000000 / pixClock; + freq = dotClock / 10; /* x100 */ + + dbg("dotClock=%ld, freq = %ld\r\n", dotClock, freq); + + hsync_wid = (hSyncEnd - hSyncStart) / 8; + + if (hsync_wid == 0) + hsync_wid = 1; + else if (hsync_wid > 0x3f) /* max */ + hsync_wid = 0x3f; + + dbg("hsync_wid=%d\r\n", hsync_wid); + + if (mode->vmode & FB_VMODE_DOUBLE) + { + vSyncStart <<= 1; + vSyncEnd <<= 1; + vTotal <<= 1; + } + + vsync_wid = vSyncEnd - vSyncStart; + if (vsync_wid == 0) + vsync_wid = 1; + else if (vsync_wid > 0x1f) /* max */ + vsync_wid = 0x1f; + + dbg("vsync_wid=%d\r\n", vsync_wid); + + // FIXME: this doesn't seem to be used anywhere hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; + // FIXME: this doesn't seem to be used anywhere vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; + // FIXME: this doesn't seem to be used anywhere cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0; + + format = radeon_get_dstbpp(depth); + dbg("format=%d\r\n", format); + + // FIXME: this doesn't seem to be used anywhere bytpp = mode->bits_per_pixel >> 3; + + if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) + hsync_fudge = hsync_fudge_fp[format - 1]; + else + hsync_fudge = hsync_adj_tab[format - 1]; + + if (mode->vmode & FB_VMODE_DOUBLE) + hsync_fudge = 0; /* todo: need adjust */ + + hsync_start = hSyncStart - 8 + hsync_fudge; + newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | (format << 8); + if (mode->vmode & FB_VMODE_DOUBLE) + newmode->crtc_gen_cntl |= CRTC_DBL_SCAN_EN; + if (mode->vmode & FB_VMODE_INTERLACED) + newmode->crtc_gen_cntl |= CRTC_INTERLACE_EN; + + /* Clear auto-center etc... */ + newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl; + newmode->crtc_more_cntl &= 0xfffffff0; + + if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) + { + newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN; + if (mirror) + newmode->crtc_ext_cntl |= CRTC_CRT_ON; + newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN | CRTC_INTERLACE_EN); + } + else + newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON; + + newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN | DAC_8BIT_EN; + newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) | (((mode->xres / 8) - 1) << 16)); + newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) | (hsync_wid << 16) | (h_sync_pol << 23)); + + if (mode->vmode & FB_VMODE_DOUBLE) + newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) | (((mode->yres << 1) - 1) << 16); + else + newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) | ((mode->yres - 1) << 16); + + newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) | (vsync_wid << 16) | (v_sync_pol << 23)); + + /* We first calculate the engine pitch */ + rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f) & ~(0x3f)) >> 6; + + /* Then, re-multiply it to get the CRTC pitch */ + newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8); + newmode->crtc_pitch |= (newmode->crtc_pitch << 16); + + /* + * It looks like recent chips have a problem with SURFACE_CNTL, + * setting SURF_TRANSLATION_DIS completely disables the + * swapper as well, so we leave it unset now. + */ + newmode->surface_cntl = 0; + + if (rinfo->big_endian) + { + /* Setup swapping on both apertures, though we currently + * only use aperture 0, enabling swapper on aperture 1 + * won't harm + */ + switch(mode->bits_per_pixel) + { + case 16: + newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP; + newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP; + break; + case 24: + case 32: + newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP; + newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP; + break; + } + } + + /* Clear surface registers */ + for (i = 0; i < 8; i++) + { + newmode->surf_lower_bound[i] = 0; + newmode->surf_upper_bound[i] = 0x1f; + newmode->surf_info[i] = 0; + } + + rinfo->bpp = mode->bits_per_pixel; + rinfo->depth = depth; + + /* We use PPLL_DIV_3 */ + newmode->clk_cntl_index = 0x300; + + /* Calculate PPLL value if necessary */ + if (!nopllcalc) + radeon_calc_pll_regs(rinfo, newmode, freq); + + newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl; + if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) + { + int32_t hRatio, vRatio; + if (mode->xres > rinfo->panel_info.xres) + mode->xres = rinfo->panel_info.xres; + if (mode->yres > rinfo->panel_info.yres) + mode->yres = rinfo->panel_info.yres; + newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1) << HORZ_PANEL_SHIFT); + newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1) << VERT_PANEL_SHIFT); + + if (mode->xres != rinfo->panel_info.xres) + { + hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX, rinfo->panel_info.xres); + newmode->fp_horz_stretch = (((hRatio & HORZ_STRETCH_RATIO_MASK)) + | (newmode->fp_horz_stretch & (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH | HORZ_AUTO_RATIO_INC))); + newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND | HORZ_STRETCH_ENABLE); + use_rmx = 1; + } + + newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO; + if (mode->yres != rinfo->panel_info.yres) + { + vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX, rinfo->panel_info.yres); + newmode->fp_vert_stretch = (((((uint32_t)vRatio) & VERT_STRETCH_RATIO_MASK)) + | (newmode->fp_vert_stretch & (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED))); + newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND | VERT_STRETCH_ENABLE); + use_rmx = 1; + } + newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN; + newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl + & ~(FP_SEL_CRTC2 | FP_RMX_HVSYNC_CONTROL_EN | FP_DFP_SYNC_SEL | FP_CRT_SYNC_SEL + | FP_CRTC_LOCK_8DOT | FP_USE_SHADOW_EN | FP_CRTC_USE_SHADOW_VEND | FP_CRT_SYNC_ALT)); + newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR | FP_CRTC_DONT_SHADOW_HEND | FP_PANEL_FORMAT); + + if (IS_R300_VARIANT(rinfo) || (rinfo->family == CHIP_FAMILY_R200)) + { + newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; + if (use_rmx) + newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; + else + newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; + } + else + newmode->fp_gen_cntl |= FP_SEL_CRTC1; + + newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl; + newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl; + newmode->tmds_crc = rinfo->init_state.tmds_crc; + newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl; + + if (primary_mon == MT_LCD) + { + newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON); + newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN); + } + else + { + /* DFP */ + newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN); + newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST); + /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */ + if (IS_R300_VARIANT(rinfo) || (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2) + newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN; + else + newmode->tmds_transmitter_cntl |= TMDS_PLL_EN; + newmode->crtc_ext_cntl &= ~CRTC_CRT_ON; + } + + newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) | (((mode->xres / 8) - 1) << 16)); + newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) | ((mode->yres - 1) << 16); + newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) | (hsync_wid << 16) | (h_sync_pol << 23)); + newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) | (vsync_wid << 16) | (v_sync_pol << 23)); + } + + /* do it! */ + if (!rinfo->asleep) + { +#if 0 + if (debug) + { + dbg("Press a key for write the video mode...\r\n"); + Bconin(2); + } +#endif + memcpy(&rinfo->state, newmode, sizeof(*newmode)); +#ifdef RADEON_TILING + rinfo->tilingEnabled = (mode->vmode & (FB_VMODE_DOUBLE | FB_VMODE_INTERLACED)) ? false : true; +#endif + radeon_write_mode(rinfo, newmode, 0); + /* (re)initialize the engine */ + radeon_engine_init(rinfo); + } + + /* Update fix */ + info->fix.line_length = rinfo->pitch * 64; + info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; + driver_mem_free(newmode); + + return 0; +} + +static void radeonfb_check_modes(struct fb_info *info, struct mode_option *resolution) +{ + struct radeonfb_info *rinfo = info->par; + + radeon_check_modes(rinfo, resolution); +} + +static struct fb_ops radeonfb_ops = +{ + .fb_check_var = radeonfb_check_var, + .fb_set_par = radeonfb_set_par, + .fb_setcolreg = radeonfb_setcolreg, + .fb_pan_display = radeonfb_pan_display, + .fb_blank = radeonfb_blank, + .fb_sync = radeonfb_sync, + .fb_ioctl = radeonfb_ioctl, + .fb_check_modes = radeonfb_check_modes, + .SetupForSolidFill = radeon_setup_for_solid_fill, + .SubsequentSolidFillRect = radeon_subsequent_solid_fill_rect_mmio, + .SetupForSolidLine = radeon_setup_for_solid_line_mmio, + .SubsequentSolidHorVertLine = radeon_subsequent_solid_hor_vert_line_mmio, + .SubsequentSolidTwoPointLine = radeon_subsequent_solid_two_point_line_mmio, + .SetupForDashedLine = radeon_setup_for_dashed_line_mmio, + .SubsequentDashedTwoPointLine = radeon_subsequent_dashed_two_point_line_mmio, + .SetupForScreenToScreenCopy = radeon_setup_for_screen_to_screen_copy_mmio, + .SubsequentScreenToScreenCopy = radeon_subsequent_screen_to_screen_copy_mmio, + .ScreenToScreenCopy = radeon_screen_to_screen_copy_mmio, + .SetupForMono8x8PatternFill = radeon_setup_for_mono_8x8_pattern_fill_mmio, + .SubsequentMono8x8PatternFillRect = radeon_subsequent_mono_8x8_pattern_fill_rect_mmio, + .SetupForScanlineCPUToScreenColorExpandFill = radeon_setup_for_scanline_cpu_to_screen_color_expand_fill_mmio, + .SubsequentScanlineCPUToScreenColorExpandFill = radeon_subsequent_scanline_cpu_to_screen_color_expand_fill_mmio, + .SubsequentScanline = radeon_subsequent_scanline_mmio, + .SetupForScanlineImageWrite = radeon_setup_for_scanline_image_write_mmio, + .SubsequentScanlineImageWriteRect = radeon_subsequent_scanline_image_write_rect_mmio, + .SetClippingRectangle = radeon_set_clipping_rectangle_mmio, + .DisableClipping = radeon_disable_clipping_mmio, +#ifdef RADEON_RENDER + .SetupForCPUToScreenAlphaTexture = radeon_setup_for_cpu_to_screen_alpha_texture_mmio, + .SetupForCPUToScreenTexture = radeon_setup_for_cpu_to_screen_texture_mmio, + .SubsequentCPUToScreenTexture = radeon_subsequent_cpu_to_screen_texture_mmio, +#else + .SetupForCPUToScreenAlphaTexture = NULL, + .SetupForCPUToScreenTexture = NULL, + .SubsequentCPUToScreenTexture = NULL, +#endif /* RADEON_RENDER */ + .SetCursorColors = radeon_set_cursor_colors, + .SetCursorPosition = radeon_set_cursor_position, + .LoadCursorImage = radeon_load_cursor_image, + .HideCursor = radeon_hide_cursor, + .ShowCursor = radeon_show_cursor, + .CursorInit = radeon_cursor_init, + .WaitVbl = radeon_wait_vbl, +}; + +static int radeon_set_fbinfo(struct radeonfb_info *rinfo) +{ + struct fb_info *info = rinfo->info; + + info->par = rinfo; + info->fbops = &radeonfb_ops; + info->ram_base = info->screen_base = rinfo->fb_base; + info->screen_size = rinfo->mapped_vram; + info->ram_size = rinfo->mapped_vram; + if (info->screen_size > MAX_MAPPED_VRAM) + info->screen_size = MAX_MAPPED_VRAM; + else if (info->screen_size > MIN_MAPPED_VRAM) + info->screen_size = MIN_MAPPED_VRAM; + + dbg("ram_base %p\r\n", info->screen_base); + dbg("ram_size 0x%08lx\r\n", info->ram_size); + + /* Fill fix common fields */ + memcpy(info->fix.id, rinfo->name, sizeof(info->fix.id)); + info->fix.smem_start = rinfo->fb_base_phys; + info->fix.smem_len = rinfo->video_ram; + info->fix.type = FB_TYPE_PACKED_PIXELS; + info->fix.visual = FB_VISUAL_PSEUDOCOLOR; + info->fix.xpanstep = 8; + info->fix.ypanstep = 1; + info->fix.ywrapstep = 0; + info->fix.type_aux = 0; + info->fix.mmio_start = rinfo->mmio_base_phys; + info->fix.mmio_len = RADEON_REGSIZE; + info->fix.accel = FB_ACCEL_ATI_RADEON; + + return 0; +} + +static void radeon_identify_vram(struct radeonfb_info *rinfo) +{ + uint32_t tmp; + /* framebuffer size */ + if ((rinfo->family == CHIP_FAMILY_RS100) + || (rinfo->family == CHIP_FAMILY_RS200) + || (rinfo->family == CHIP_FAMILY_RS300)) + { + uint32_t tom = INREG(NB_TOM); + tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); + radeon_wait_for_fifo(rinfo, 6); + OUTREG(MC_FB_LOCATION, tom); + OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); + OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); + OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16); + /* This is supposed to fix the crtc2 noise problem. */ + OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000); + if ((rinfo->family == CHIP_FAMILY_RS100) || (rinfo->family == CHIP_FAMILY_RS200)) + { + /* This is to workaround the asic bug for RMX, some versions + of BIOS dosen't have this register initialized correctly. */ + OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN, ~CRTC_H_CUTOFF_ACTIVE_EN); + } + } + else + tmp = INREG(CONFIG_MEMSIZE); + /* mem size is bits [28:0], mask off the rest */ + rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK; + /* + * Hack to get around some busted production M6's + * reporting no ram + */ + if (rinfo->video_ram == 0) + { + switch(rinfo->chipset) + { + case PCI_CHIP_RADEON_LY: + case PCI_CHIP_RADEON_LZ: rinfo->video_ram = 8192 * 1024; break; + default: break; + } + } + /* + * Now try to identify VRAM type + */ + if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) + || (INREG(MEM_SDRAM_MODE_REG) & (1<<30))) + rinfo->vram_ddr = 1; + else + rinfo->vram_ddr = 0; + tmp = INREG(MEM_CNTL); + if (IS_R300_VARIANT(rinfo)) + { + tmp &= R300_MEM_NUM_CHANNELS_MASK; + switch(tmp) + { + case 0: rinfo->vram_width = 64; break; + case 1: rinfo->vram_width = 128; break; + case 2: rinfo->vram_width = 256; break; + default: rinfo->vram_width = 128; break; + } + } + else if ((rinfo->family == CHIP_FAMILY_RV100) + || (rinfo->family == CHIP_FAMILY_RS100) + || (rinfo->family == CHIP_FAMILY_RS200)) + { + if (tmp & RV100_MEM_HALF_MODE) + rinfo->vram_width = 32; + else + rinfo->vram_width = 64; + } + else + { + if (tmp & MEM_NUM_CHANNELS_MASK) + rinfo->vram_width = 128; + else + rinfo->vram_width = 64; + } + + /* + * This may not be correct, as some cards can have half of channel disabled + * ToDo: identify these cases + */ + switch(rinfo->family) + { + case CHIP_FAMILY_LEGACY: inf("chip type: %s\r\n", "LEGACY"); break; + case CHIP_FAMILY_RADEON: inf("chip type: %s\r\n", "RADEON"); break; + case CHIP_FAMILY_RV100: inf("chip type: %s\r\n", "RV100"); break; + case CHIP_FAMILY_RS100: inf("chip type: %s\r\n", "RS100"); break; + case CHIP_FAMILY_RV200: inf("chip type: %s\r\n", "RV200"); break; + case CHIP_FAMILY_RS200: inf("chip type: %s\r\n", "RS200"); break; + case CHIP_FAMILY_R200: inf("chip type: %s\r\n", "R200"); break; + case CHIP_FAMILY_RV250: inf("chip type: %s\r\n", "RV250"); break; + case CHIP_FAMILY_RS300: inf("chip type: %s\r\n", "RS300"); break; + case CHIP_FAMILY_RV280: inf("chip type: %s\r\n", "RV280"); break; + case CHIP_FAMILY_R300: inf("chip type: %s\r\n", "R300"); break; + case CHIP_FAMILY_R350: inf("chip type: %s\r\n", "R350"); break; + case CHIP_FAMILY_RV350: inf("chip type: %s\r\n", "RV350"); break; + case CHIP_FAMILY_RV380: inf("chip type: %s\r\n", "RV380"); break; + case CHIP_FAMILY_R420: inf("chip type: %s\r\n", "R420"); break; + default: inf("chip type: %s\r\n", "UNKNOWN"); break; + } + inf("found %d KB of %d bits wide %s video RAM\r\n", rinfo->video_ram / 1024, + rinfo->vram_width, rinfo->vram_ddr ? "DDR" : "SDRAM"); +} + +int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent) +{ + struct fb_info *info; + struct radeonfb_info *rinfo; + struct pci_rd *pci_rsc_desc; + + dbg("\r\n"); + info = framebuffer_alloc(sizeof(struct radeonfb_info)); + if (!info) + { + err("could not allocate frame buffer info\r\n"); + return -1; // -ENOMEM; + } + + rinfo = info->par; + + rinfo->info = info; + rinfo->handle = handle; + + strcpy((char *) rinfo->name, "ATI Radeon XX "); + rinfo->name[11] = (char) (ent->device >> 8); + rinfo->name[12] = (char) ent->device; + + rinfo->family = ent->driver_data & CHIP_FAMILY_MASK; + rinfo->chipset = ent->device; + rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0; + rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0; + rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0; + + /* Set base addrs */ + dbg("Set base addrs\r\n"); + rinfo->fb_base_phys = rinfo->mmio_base_phys = rinfo->io_base_phys = 0xFFFFFFFF; + rinfo->mapped_vram = 0; + rinfo->mmio_base = rinfo->io_base = NULL; + rinfo->bios_seg = NULL; + + pci_rsc_desc = pci_get_resource(handle); + if ((int32_t) pci_rsc_desc >= 0) + { + uint16_t flags; + do + { + dbg("flags %p\r\n", pci_rsc_desc->flags); + dbg(" start %p\r\n", pci_rsc_desc->start); + dbg(" offset 0x%x\r\n", pci_rsc_desc->offset); + dbg(" length 0x%x\r\n", pci_rsc_desc->length); + + if (!(pci_rsc_desc->flags & FLG_IO)) + { + if ((rinfo->fb_base_phys == 0xFFFFFFFF) && (pci_rsc_desc->length >= 0x100000)) + { + rinfo->fb_base = (void *)(pci_rsc_desc->offset + pci_rsc_desc->start); + rinfo->fb_base_phys = pci_rsc_desc->start; + rinfo->mapped_vram = pci_rsc_desc->length; + // rinfo->dma_offset = pci_rsc_desc->dmaoffset; + if ((pci_rsc_desc->flags & FLG_ENDMASK) == ORD_MOTOROLA) + { + rinfo->big_endian = 0; /* host bridge make swapping intel -> motorola */ + dbg("host bridge is big endian\r\n"); + } + else + { + rinfo->big_endian = 1; /* radeon make swapping intel -> motorola */ + dbg("host bridge is little endian\r\n"); + } + } + else if ((pci_rsc_desc->length >= RADEON_REGSIZE) && (pci_rsc_desc->length < 0x100000)) + { + if (pci_rsc_desc->flags & FLG_ROM) + { + dbg("FLG_ROM resource descriptor found\r\n"); + dbg(" start = %p, size = 0x%x\r\n", pci_rsc_desc->start, pci_rsc_desc->length); + dbg(" bios_seg = %p\r\n", rinfo->bios_seg); + + if (rinfo->bios_seg == NULL) + { + rinfo->bios_seg_phys = pci_rsc_desc->start; + if (BIOS_IN16(0) == 0xaa55) + { + rinfo->bios_seg = (void *) (pci_rsc_desc->offset + pci_rsc_desc->start); + } + else + { + dbg("rinfo->bios_seg[0] (%p) was %x (expected 0xaa55)\r\n", + rinfo->bios_seg_phys, * (uint16_t *) rinfo->bios_seg_phys); + rinfo->bios_seg_phys = 0; + return 0; + } + } + } + else + { + if (rinfo->mmio_base_phys == 0xFFFFFFFF) + { + rinfo->mmio_base = (void *)(pci_rsc_desc->offset + pci_rsc_desc->start); + rinfo->mmio_base_phys = pci_rsc_desc->start; + } + } + } + } + else + { + if (rinfo->io_base_phys == 0xFFFFFFFF) + { + rinfo->io_base = (void *)(pci_rsc_desc->offset + pci_rsc_desc->start); + rinfo->io_base_phys = pci_rsc_desc->start; + } + } + flags = pci_rsc_desc->flags; + pci_rsc_desc = (struct pci_rd *) ((uint32_t) pci_rsc_desc->next + (uint32_t) pci_rsc_desc); + } while (!(flags & FLG_LAST)); + } + else + err("get_resource error\r\n"); + + /* map the regions */ + dbg("map memory regions\r\n"); + if (rinfo->mmio_base == NULL) + { + err("cannot map MMIO\r\n"); + framebuffer_release(info); + return -2; //(-EIO); + } + dbg("mmio_base_phys %p, mmio_base %p\r\n", rinfo->mmio_base_phys, rinfo->mmio_base); + dbg("io_base_phys %p, io_base %p\r\n", rinfo->io_base_phys, rinfo->io_base); + dbg("fb_base_phys %p, fb_base %p\r\n", rinfo->fb_base_phys, rinfo->fb_base); + + /* + * Check for errata + */ + dbg("check for errata\r\n"); + rinfo->errata = 0; + if (rinfo->family == CHIP_FAMILY_R300 + && (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) == CFG_ATI_REV_A11) + rinfo->errata |= CHIP_ERRATA_R300_CG; + if (rinfo->family == CHIP_FAMILY_RV200 || rinfo->family == CHIP_FAMILY_RS200) + rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS; + if (rinfo->family == CHIP_FAMILY_RV100 + || rinfo->family == CHIP_FAMILY_RS100 + || rinfo->family == CHIP_FAMILY_RS200) + rinfo->errata |= CHIP_ERRATA_PLL_DELAY; + + /* + * Map the BIOS ROM if any and retreive PLL parameters from + * the BIOS. + */ + dbg("bios_seg_phys %p\r\n", rinfo->bios_seg_phys); + dbg("map the BIOS ROM\r\n"); + radeon_map_ROM(rinfo); + + /* + * Run VGA BIOS + */ + if ((rinfo->bios_seg != NULL)) + { + dbg("run VGA BIOS\r\n"); + run_bios(rinfo); + } + else + { + err("could not run VGA bios - rinfo->bios_seg is NULL\r\n"); + } + + dbg("fixup display base address \r\n"); + + OUTREG(MC_FB_LOCATION, 0x7fff0000); + rinfo->fb_local_base = 0; + + /* + * Fixup the display base addresses & engine offsets while we + * are at it as well + */ + OUTREG(DISPLAY_BASE_ADDR, 0); + if (rinfo->has_CRTC2) + OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0); + + OUTREG(OV0_BASE_ADDR, 0); + + /* Get VRAM size and type */ + dbg("get VRAM size\r\n"); + radeon_identify_vram(rinfo); + + if ((rinfo->fb_base == NULL) + || ((rinfo->video_ram > rinfo->mapped_vram) && (rinfo->mapped_vram < MIN_MAPPED_VRAM * 2))) + { + err("cannot map FB, video ram: %d KB\r\n", rinfo->mapped_vram / 1024); + framebuffer_release(info); + return -2; //(-EIO); + } + else + { + inf("%d KB of video RAM mapped to %p\r\n", rinfo->mapped_vram / 1024, rinfo->fb_base); + } + + /* Get information about the board's PLL */ + dbg("get information about the board's PLL\r\n"); + radeon_get_pllinfo(rinfo); + +#ifdef CONFIG_FB_RADEON_I2C + /* Register I2C bus */ + dbg("register I2C bus\r\n"); + radeon_create_i2c_busses(rinfo); +#endif /* CONFIG_FB_RADEON_I2C */ + + /* set all the vital stuff */ + dbg("set all the vital stuff\r\n"); + radeon_set_fbinfo(rinfo); + + /* set offscreen memory descriptor */ + dbg("set offscreen memory descriptor\r\n"); + offscreen_init(info); + + /* Probe screen types */ + dbg("probe screen types, monitor_layout: %s\r\n", monitor_layout); + radeon_probe_screens(rinfo, monitor_layout, ignore_edid); + + /* Build mode list, check out panel native model */ + dbg("build mode list\r\n"); + radeon_check_modes(rinfo, &resolution); + + /* + * save current mode regs before we switch into the new one + * so we can restore this upon exit + */ + dbg("save current mode\r\n"); + radeon_save_state(rinfo, &rinfo->init_state); + memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs)); + + dbg("install VBL timer\r\n"); + rinfo->lvds_timer = 0; + +#ifndef DRIVER_IN_ROM + install_vbl_timer(radeon_timer_func, 1); /* remove old vector */ +#else + install_vbl_timer(radeon_timer_func, 0); +#endif + radeon_timer_func(); + + return 0; +} + +#if 0 + +void radeonfb_pci_unregister(void) +{ + struct fb_info *info = info_fb; + struct radeonfb_info *rinfo = info->par; + // radeonfb_pm_exit(rinfo); + uninstall_vbl_timer(radeon_timer_func); + if (rinfo->mon1_EDID!=NULL) + driver_mem_free(rinfo->mon1_EDID); + if (rinfo->mon2_EDID!=NULL) + driver_mem_free(rinfo->mon2_EDID); + if (rinfo->mon1_modedb) + fb_destroy_modedb(rinfo->mon1_modedb); +#ifdef CONFIG_FB_RADEON_I2C + radeon_delete_i2c_busses(rinfo); +#endif + framebuffer_release(info); +} + +#endif + + diff --git a/radeon/radeon_cursor.c b/radeon/radeon_cursor.c new file mode 100644 index 0000000..32a93c8 --- /dev/null +++ b/radeon/radeon_cursor.c @@ -0,0 +1,335 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_cursor.c,v 1.26 2003/11/10 18:41:22 tsi Exp $ */ +/* + * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and + * VA Linux Systems Inc., Fremont, California. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR + * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * Rickard E. Faith + * + * References: + * + * !!!! FIXME !!!! + * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical + * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April + * 1999. + * + * RAGE 128 Software Development Manual (Technical Reference Manual P/N + * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. + * + */ + +#include "bas_types.h" +#include "bas_printf.h" +#include "radeonfb.h" + +#define DBG_RADEON +#ifdef DBG_RADEON +#define dbg(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0) +#else +#define dbg(format, arg...) do { ; } while (0) +#endif /* DBG_RADEON */ + + +#define CURSOR_WIDTH 64 +#define CURSOR_HEIGHT 64 + +/* + * The cursor bits are always 32bpp. On MSBFirst buses, + * configure byte swapping to swap 32 bit units when writing + * the cursor image. Byte swapping must always be returned + * to its previous value before returning. + */ +#define CURSOR_SWAPPING_DECL_MMIO +#define CURSOR_SWAPPING_DECL unsigned long __surface_cntl=0; +#define CURSOR_SWAPPING_START() \ + if (rinfo->big_endian) \ + OUTREG(SURFACE_CNTL, \ + ((__surface_cntl = INREG(SURFACE_CNTL)) | \ + NONSURF_AP0_SWP_32BPP) & \ + ~NONSURF_AP0_SWP_16BPP); +#define CURSOR_SWAPPING_END() \ + if (rinfo->big_endian) \ + (OUTREG(SURFACE_CNTL, __surface_cntl)); + +/* Set cursor foreground and background colors */ +void radeon_set_cursor_colors(struct fb_info *info, int32_t bg, int32_t fg) +{ + struct radeonfb_info *rinfo = info->par; + unsigned long *pixels = (unsigned long *)((unsigned long) rinfo->fb_base + rinfo->cursor_start); + int pixel, i; + CURSOR_SWAPPING_DECL_MMIO + CURSOR_SWAPPING_DECL + // DPRINTVALHEX("radeonfb: RADEONSetCursorColors: cursor_start ",rinfo->cursor_start); + // DPRINT("\r\n"); + fg |= 0xff000000; + bg |= 0xff000000; + /* Don't recolour the image if we don't have to. */ + if (fg == rinfo->cursor_fg && bg == rinfo->cursor_bg) + return; + CURSOR_SWAPPING_START(); + + /* + * Note: We assume that the pixels are either fully opaque or fully + * transparent, so we won't premultiply them, and we can just + * check for non-zero pixel values; those are either fg or bg + */ + for (i = 0; i < CURSOR_WIDTH * CURSOR_HEIGHT; i++, pixels++) + if ((pixel = *pixels)) + *pixels = (pixel == rinfo->cursor_fg) ? fg : bg; + CURSOR_SWAPPING_END(); + rinfo->cursor_fg = fg; + rinfo->cursor_bg = bg; +} + +/* Set cursor position to (x,y) with offset into cursor bitmap at + * (xorigin,yorigin) + */ +void radeon_set_cursor_position(struct fb_info *info, int32_t x, int32_t y) +{ + struct radeonfb_info *rinfo = info->par; + struct fb_var_screeninfo *mode = &info->var; + int xorigin = 0; + int yorigin = 0; + if (mode->vmode & FB_VMODE_DOUBLE) + y <<= 1; + if (x < 0) + xorigin = 1 - x; + if (y < 0) + yorigin = 1 - y; + + // DPRINTVALHEX("radeonfb: RADEONSetCursorPosition: cursor_start ",rinfo->cursor_start); + // DPRINTVAL(" x ",x); + // DPRINTVAL(" y ",y); + // DPRINT("\r\n"); + + OUTREG(CUR_HORZ_VERT_OFF, (CUR_LOCK | (xorigin << 16) | yorigin)); + OUTREG(CUR_HORZ_VERT_POSN, (CUR_LOCK | ((xorigin ? 0 : x) << 16) | (yorigin ? 0 : y))); + OUTREG(CUR_OFFSET, rinfo->cursor_start + yorigin * 256); + rinfo->cursor_x = (unsigned long)x; + if (mode->vmode & FB_VMODE_DOUBLE) + rinfo->cursor_y = (unsigned long) y >> 1; + else + rinfo->cursor_y = (unsigned long) y; +} + +/* + * Copy cursor image from `image' to video memory. RADEONSetCursorPosition + * will be called after this, so we can ignore xorigin and yorigin. + */ +void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsigned short *data, int32_t zoom) +{ + struct radeonfb_info *rinfo = info->par; + unsigned long *d = (unsigned long *)((unsigned long)rinfo->fb_base+rinfo->cursor_start); + unsigned long save = 0; + unsigned short chunk, mchunk; + unsigned long i, j, k; + CURSOR_SWAPPING_DECL + + // DPRINTVALHEX("radeonfb: RADEONLoadCursorImage: cursor_start ",rinfo->cursor_start); + // DPRINT("\r\n"); + + save = INREG(CRTC_GEN_CNTL) & ~(unsigned long) (3 << 20); + save |= (unsigned long) (2 << 20); + OUTREG(CRTC_GEN_CNTL, save & (unsigned long)~CRTC_CUR_EN); + + /* + * Convert the bitmap to ARGB32. + */ + CURSOR_SWAPPING_START(); +#define ARGB_PER_CHUNK (8 * sizeof (chunk)) + switch(zoom) + { + case 1: + default: + for (i = 0; i < CURSOR_HEIGHT; i++) + { + if (i < 16) + { + mchunk = *mask++; + chunk = *data++; + } + else + mchunk = chunk = 0; + for (j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j++) + { + for (k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1) + { + if (mchunk & 0x8000) + { + if (chunk & 0x8000) + *d++ = 0xff000000; /* Black, fully opaque. */ + else + *d++ = 0xffffffff; /* White, fully opaque. */ + } + else + *d++ = 0x00000000; /* White/Black, fully transparent. */ + } + } + } + break; + case 2: + for (i = 0; i < CURSOR_HEIGHT; i++) + { + if (i < 16*2) + { + mchunk = *mask; + chunk = *data; + if ((i & 1) == 1) + { + mask++; + data++; + } + } + else + mchunk = chunk = 0; + for (j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j+=2) + { + for (k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1) + { + if (mchunk & 0x8000) + { + if (chunk & 0x8000) + { + *d++ = 0xff000000; /* Black, fully opaque. */ + *d++ = 0xff000000; + } + else + { + *d++ = 0xffffffff; /* White, fully opaque. */ + *d++ = 0xffffffff; + } + } + else + { + *d++ = 0x00000000; /* White/Black, fully transparent. */ + *d++ = 0x00000000; + } + } + } + } + break; + case 4: + for (i = 0; i < CURSOR_HEIGHT; i++) + { + if (i < 16 * 4) + { + mchunk = *mask; + chunk = *data; + if ((i & 3) == 3) + { + mask++; + data++; + } + } + else + mchunk = chunk = 0; + for (j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j+=4) + { + for (k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1) + { + if (mchunk & 0x8000) + { + if (chunk & 0x8000) + { + *d++ = 0xff000000; /* Black, fully opaque. */ + *d++ = 0xff000000; + *d++ = 0xff000000; + *d++ = 0xff000000; + } + else + { + *d++ = 0xffffffff; /* White, fully opaque. */ + *d++ = 0xffffffff; + *d++ = 0xffffffff; + *d++ = 0xffffffff; + } + } + else + { + *d++ = 0x00000000; /* White/Black, fully transparent. */ + *d++ = 0x00000000; + *d++ = 0x00000000; + *d++ = 0x00000000; + } + } + } + } + break; + } + CURSOR_SWAPPING_END(); + rinfo->cursor_bg = 0xffffffff; /* White, fully opaque. */ + rinfo->cursor_fg = 0xff000000; /* Black, fully opaque. */ + OUTREG(CRTC_GEN_CNTL, save); +} + +/* Hide hardware cursor. */ +void radeon_hide_cursor(struct fb_info *info) +{ + struct radeonfb_info *rinfo = info->par; + + // DPRINT("radeonfb: RADEONHideCursor\r\n"); + OUTREGP(CRTC_GEN_CNTL, 0, ~CRTC_CUR_EN); + rinfo->cursor_show = 0; +} + +/* Show hardware cursor. */ +void radeon_show_cursor(struct fb_info *info) +{ + struct radeonfb_info *rinfo = info->par; + + // DPRINT("radeonfb: RADEONShowCursor\r\n"); + OUTREGP(CRTC_GEN_CNTL, CRTC_CUR_EN, ~CRTC_CUR_EN); + rinfo->cursor_show = 1; +} + +/* Initialize hardware cursor support. */ +long radeon_cursor_init(struct fb_info *info) +{ + struct radeonfb_info *rinfo = info->par; + int size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT; + unsigned long fbarea = offscreen_alloc(rinfo->info, size_bytes + 256); + + dbg("radeonfb: %s: fbarea: %p\r\n", fbarea); + + if (!fbarea) + rinfo->cursor_start = 0; + else + { + unsigned short data[16], mask[16]; + + memset(data, 0, sizeof(data)); + memset(mask, 0, sizeof(data)); + rinfo->cursor_start = RADEON_ALIGN(fbarea - (unsigned long) rinfo->fb_base, 256); + rinfo->cursor_end = rinfo->cursor_start + size_bytes; + radeon_load_cursor_image(info, mask, data, 1); + } + dbg("radeonfb: %s cursor_start: %p\r\n", rinfo->cursor_start); + + return (rinfo->cursor_start ? fbarea : 0); +} diff --git a/radeon/radeon_i2c.c b/radeon/radeon_i2c.c new file mode 100644 index 0000000..55ff7a7 --- /dev/null +++ b/radeon/radeon_i2c.c @@ -0,0 +1,237 @@ +#include "video.h" +#include "radeonfb.h" +#include "edid.h" +#include "i2c.h" +#include "driver_mem.h" + +// #define DEBUG +#include "debug.h" + + +#define CONFIG_FB_RADEON_I2C +#ifdef CONFIG_FB_RADEON_I2C + +#define RADEON_DDC 0x50 + +static void radeon_gpio_setscl(void* data, int state) +{ + struct radeon_i2c_chan *chan = data; + struct radeonfb_info *rinfo = chan->rinfo; + unsigned long val; + + val = INREG(chan->ddc_reg) & ~(VGA_DDC_CLK_OUT_EN); + + if (!state) + val |= VGA_DDC_CLK_OUT_EN; + OUTREG(chan->ddc_reg, val); + (void) INREG(chan->ddc_reg); +} + +static void radeon_gpio_setsda(void* data, int state) +{ + struct radeon_i2c_chan *chan = data; + struct radeonfb_info *rinfo = chan->rinfo; + unsigned long val; + + val = INREG(chan->ddc_reg) & ~(VGA_DDC_DATA_OUT_EN); + if (!state) + val |= VGA_DDC_DATA_OUT_EN; + OUTREG(chan->ddc_reg, val); + (void) INREG(chan->ddc_reg); +} + +static int radeon_gpio_getscl(void* data) +{ + struct radeon_i2c_chan *chan = data; + struct radeonfb_info *rinfo = chan->rinfo; + unsigned long val; + + val = INREG(chan->ddc_reg); + return (val & VGA_DDC_CLK_INPUT) ? 1 : 0; +} + +static int radeon_gpio_getsda(void* data) +{ + struct radeon_i2c_chan *chan = data; + struct radeonfb_info *rinfo = chan->rinfo; + unsigned long val; + val = INREG(chan->ddc_reg); + return(val & VGA_DDC_DATA_INPUT) ? 1 : 0; +} + +static int radeon_setup_i2c_bus(struct radeon_i2c_chan *chan) +{ + int rc; + chan->adapter.algo_data = &chan->algo; + chan->algo.setsda = radeon_gpio_setsda; + chan->algo.setscl = radeon_gpio_setscl; + chan->algo.getsda = radeon_gpio_getsda; + chan->algo.getscl = radeon_gpio_getscl; + chan->algo.udelay = 40; + chan->algo.timeout = 20; + chan->algo.data = chan; + /* Raise SCL and SDA */ + radeon_gpio_setsda(chan, 1); + radeon_gpio_setscl(chan, 1); + udelay(20); + rc = i2c_bit_add_bus(&chan->adapter); + return rc; +} + +void radeon_create_i2c_busses(struct radeonfb_info *rinfo) +{ + rinfo->i2c[0].rinfo = rinfo; + rinfo->i2c[0].ddc_reg = GPIO_MONID; + radeon_setup_i2c_bus(&rinfo->i2c[0]); + rinfo->i2c[1].rinfo = rinfo; + rinfo->i2c[1].ddc_reg = GPIO_DVI_DDC; + radeon_setup_i2c_bus(&rinfo->i2c[1]); + rinfo->i2c[2].rinfo = rinfo; + rinfo->i2c[2].ddc_reg = GPIO_VGA_DDC; + radeon_setup_i2c_bus(&rinfo->i2c[2]); + rinfo->i2c[3].rinfo = rinfo; + rinfo->i2c[3].ddc_reg = GPIO_CRT2_DDC; + radeon_setup_i2c_bus(&rinfo->i2c[3]); +} + +#if 0 +void radeon_delete_i2c_busses(struct radeonfb_info *rinfo) +{ + if(rinfo->i2c[0].rinfo) + i2c_bit_del_bus(&rinfo->i2c[0].adapter); + rinfo->i2c[0].rinfo = NULL; + if(rinfo->i2c[1].rinfo) + i2c_bit_del_bus(&rinfo->i2c[1].adapter); + rinfo->i2c[1].rinfo = NULL; + if(rinfo->i2c[2].rinfo) + i2c_bit_del_bus(&rinfo->i2c[2].adapter); + rinfo->i2c[2].rinfo = NULL; + if(rinfo->i2c[3].rinfo) + i2c_bit_del_bus(&rinfo->i2c[3].adapter); + rinfo->i2c[3].rinfo = NULL; +} +#endif + +static unsigned char *radeon_do_probe_i2c_edid(struct radeon_i2c_chan *chan) +{ + unsigned char start = 0x0; + struct i2c_msg msgs[] = + { + { + .addr = RADEON_DDC, + .len = 1, + .buf = &start, + }, + { + .addr = RADEON_DDC, + .flags = I2C_M_RD, + .len = EDID_LENGTH, + }, + }; + + unsigned char *buf; + + buf = driver_mem_alloc(EDID_LENGTH * 3); + if (!buf) + return NULL; + + msgs[1].buf = buf; + if (i2c_transfer(&chan->adapter, msgs, 2) == 2) + return buf; + else + dbg("i2c_transfer() failed\r\n"); + + driver_mem_free(buf); + return NULL; +} + +int32_t radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int32_t conn, uint8_t **out_edid) +{ + unsigned long reg = rinfo->i2c[conn - 1].ddc_reg; + unsigned char *edid = NULL; + int i, j; + + OUTREG(reg, INREG(reg) & ~(VGA_DDC_DATA_OUTPUT | VGA_DDC_CLK_OUTPUT)); + OUTREG(reg, INREG(reg) & ~(VGA_DDC_CLK_OUT_EN)); + (void) INREG(reg); + + for(i = 0; i < 3; i++) + { + /* For some old monitors we need the + * following process to initialize/stop DDC + */ + OUTREG(reg, INREG(reg) & ~(VGA_DDC_DATA_OUT_EN)); + (void)INREG(reg); + wait_ms(13); + + OUTREG(reg, INREG(reg) & ~(VGA_DDC_CLK_OUT_EN)); + (void)INREG(reg); + + for(j = 0; j < 5; j++) + { + wait_ms(10); + if (INREG(reg) & VGA_DDC_CLK_INPUT) + break; + } + + if (j == 5) + continue; + + OUTREG(reg, INREG(reg) | VGA_DDC_DATA_OUT_EN); + (void) INREG(reg); + wait_ms(15); + + OUTREG(reg, INREG(reg) | VGA_DDC_CLK_OUT_EN); + (void) INREG(reg); + wait_ms(15); + + OUTREG(reg, INREG(reg) & ~(VGA_DDC_DATA_OUT_EN)); + (void) INREG(reg); + wait_ms(15); + + /* Do the real work */ + edid = radeon_do_probe_i2c_edid(&rinfo->i2c[conn - 1]); + OUTREG(reg, INREG(reg) | (VGA_DDC_DATA_OUT_EN | VGA_DDC_CLK_OUT_EN)); + (void) INREG(reg); + wait_ms(15); + OUTREG(reg, INREG(reg) & ~(VGA_DDC_CLK_OUT_EN)); + (void) INREG(reg); + for(j = 0; j < 10; j++) + { + wait_ms(10); + if (INREG(reg) & VGA_DDC_CLK_INPUT) + break; + } + OUTREG(reg, INREG(reg) & ~(VGA_DDC_DATA_OUT_EN)); + (void) INREG(reg); + wait_ms(15); + + OUTREG(reg, INREG(reg) | (VGA_DDC_DATA_OUT_EN | VGA_DDC_CLK_OUT_EN)); + (void) INREG(reg); + + if (edid) + break; + } + /* Release the DDC lines when done or the Apple Cinema HD display + * will switch off */ + OUTREG(reg, INREG(reg) & ~(VGA_DDC_CLK_OUT_EN | VGA_DDC_DATA_OUT_EN)); + (void) INREG(reg); + + if (out_edid) + *out_edid = edid; + + if (!edid) + return MT_NONE; + + if (edid[0x14] & 0x80) + { + /* Fix detection using BIOS tables */ + if(rinfo->is_mobility /*&& conn == ddc_dvi*/ && (INREG(LVDS_GEN_CNTL) & LVDS_ON)) + return MT_LCD; + else + return MT_DFP; + } + return MT_CRT; +} + +#endif /* CONFIG_FB_RADEON_I2C */ diff --git a/radeon/radeon_monitor.c b/radeon/radeon_monitor.c new file mode 100644 index 0000000..c46b7f9 --- /dev/null +++ b/radeon/radeon_monitor.c @@ -0,0 +1,748 @@ +#include "radeonfb.h" +#include "wait.h" +#include "edid.h" +#include "driver_mem.h" +#include "bas_printf.h" +#include "bas_string.h" +#include "video.h" + +// #define DEBUG +#include "debug.h" + +#ifndef INT_MAX +#define INT_MAX ((int) (~0U >> 1)) +#endif + +static struct fb_var_screeninfo radeonfb_default_var = +{ + .xres = 640, + .yres = 480, + .xres_virtual = 640, + .yres_virtual = 480, + .bits_per_pixel = 8, + .red = { .length = 8 }, + .green = { .length = 8 }, + .blue = { .length = 8 }, + .activate = FB_ACTIVATE_NOW, + .height = -1, + .width = -1, + .pixclock = 9295, + .left_margin = 40, + .right_margin = 24, + .upper_margin = 32, + .lower_margin = 11, + .hsync_len = 96, + .vsync_len = 2, + .vmode = FB_VMODE_NONINTERLACED +}; + +char *radeon_get_mon_name(int type) +{ + char *pret = NULL; + switch(type) + { + case MT_NONE: + pret = "no"; + break; + case MT_CRT: + pret = "CRT"; + break; + case MT_DFP: + pret = "DFP"; + break; + case MT_LCD: + pret = "LCD"; + break; + case MT_CTV: + pret = "CTV"; + break; + case MT_STV: + pret = "STV"; + break; + } + return pret; +} + +/* + * Probe physical connection of a CRT. This code comes from XFree + * as well and currently is only implemented for the CRT DAC, the + * code for the TVDAC is commented out in XFree as "non working" + */ +static int radeon_crt_is_connected(struct radeonfb_info *rinfo, int is_crt_dac) +{ + int connected = 0; + /* + * the monitor either wasn't connected or it is a non-DDC CRT. + * try to probe it + */ + if (is_crt_dac) + { + unsigned long ulOrigVCLK_ECP_CNTL; + unsigned long ulOrigDAC_CNTL; + unsigned long ulOrigDAC_EXT_CNTL; + unsigned long ulOrigCRTC_EXT_CNTL; + unsigned long ulData; + unsigned long ulMask; + + ulOrigVCLK_ECP_CNTL = INPLL(VCLK_ECP_CNTL); + ulData = ulOrigVCLK_ECP_CNTL; + ulData &= ~(PIXCLK_ALWAYS_ONb | PIXCLK_DAC_ALWAYS_ONb); + ulMask = ~(PIXCLK_ALWAYS_ONb | PIXCLK_DAC_ALWAYS_ONb); + OUTPLLP(VCLK_ECP_CNTL, ulData, ulMask); + ulOrigCRTC_EXT_CNTL = INREG(CRTC_EXT_CNTL); + ulData = ulOrigCRTC_EXT_CNTL; + ulData |= CRTC_CRT_ON; + OUTREG(CRTC_EXT_CNTL, ulData); + ulOrigDAC_EXT_CNTL = INREG(DAC_EXT_CNTL); + ulData = ulOrigDAC_EXT_CNTL; + ulData &= ~DAC_FORCE_DATA_MASK; + ulData |= (DAC_FORCE_BLANK_OFF_EN | DAC_FORCE_DATA_EN | DAC_FORCE_DATA_SEL_MASK); + if ((rinfo->family == CHIP_FAMILY_RV250) || (rinfo->family == CHIP_FAMILY_RV280)) + ulData |= (0x01b6 << DAC_FORCE_DATA_SHIFT); + else + ulData |= (0x01ac << DAC_FORCE_DATA_SHIFT); + OUTREG(DAC_EXT_CNTL, ulData); + ulOrigDAC_CNTL = INREG(DAC_CNTL); + ulData = ulOrigDAC_CNTL; + ulData |= DAC_CMP_EN; + ulData &= ~(DAC_RANGE_CNTL_MASK | DAC_PDWN); + ulData |= 0x2; + OUTREG(DAC_CNTL, ulData); + wait_ms(1); + ulData = INREG(DAC_CNTL); + connected = (DAC_CMP_OUTPUT & ulData) ? 1 : 0; + ulData = ulOrigVCLK_ECP_CNTL; + ulMask = 0xFFFFFFFFL; + OUTPLLP(VCLK_ECP_CNTL, ulData, ulMask); + OUTREG(DAC_CNTL, ulOrigDAC_CNTL); + OUTREG(DAC_EXT_CNTL, ulOrigDAC_EXT_CNTL ); + OUTREG(CRTC_EXT_CNTL, ulOrigCRTC_EXT_CNTL); + } + return connected ? MT_CRT : MT_NONE; +} + +/* + * Parse the "monitor_layout" string if any. This code is mostly + * copied from XFree's radeon driver + */ +static int radeon_parse_monitor_layout(struct radeonfb_info *rinfo, const char *monitor_layout) +{ + char s1[5], s2[5]; + int i = 0, second = 0; + const char *s; + + if ((monitor_layout == NULL) || (*monitor_layout == '\0')) + { + dbg("monitor_layout missing\r\n"); + return 0; + } + + s = monitor_layout; + do + { + switch (*s) + { + case ',': + s1[i] = '\0'; + i = 0; + second = 1; + break; + + case ' ': + case '\0': + break; + + default: + if (i >= 4) + break; + if (second) + s2[i] = *s; + else + s1[i] = *s; + i++; + break; + } + } while(*s++); + + if (second) + s2[i] = '\0'; + else + { + s1[i] = '\0'; + s2[0] = '\0'; + } + + dbg("s1=%s, s2=%s \r\n", s1, s2); + + if (!strcmp(s1, "CRT")) + { + rinfo->mon1_type = MT_CRT; + dbg("monitor 1 set to CRT\r\n"); + } + else if (!strcmp(s1, "TMDS")) + { + rinfo->mon1_type = MT_DFP; + dbg("monitor 1 set to TMDS\r\n"); + } + else if (!strcmp(s1, "LVDS")) + { + rinfo->mon1_type = MT_LCD; + dbg("monitor 1 set to LVDS\r\n"); + } + + if (!strcmp(s2, "CRT")) + { + rinfo->mon2_type = MT_CRT; + dbg("monitor 2 set to CRT\r\n"); + } + else if (!strcmp(s2, "TMDS")) + { + rinfo->mon2_type = MT_DFP; + dbg("monitor 2 set to TMDS\r\n"); + } + else if (!strcmp(s2, "LVDS")) + { + rinfo->mon2_type = MT_LCD; + dbg("monitor 2 set to LVDS\r\n"); + } + return 1; +} + +/* + * Probe display on both primary and secondary card's connector (if any) + * by i2c and try to retreive EDID. The algorithm here comes from XFree's * radeon driver + */ +void radeon_probe_screens(struct radeonfb_info *rinfo, const char *monitor_layout, int32_t ignore_edid) +{ + +#ifdef CONFIG_FB_RADEON_I2C + int ddc_crt2_used = 0; +#endif + + dbg("monitor_layout=%s\r\n", monitor_layout); + if (radeon_parse_monitor_layout(rinfo, monitor_layout)) + { + /* + * If user specified a monitor_layout option, use it instead + * of auto-detecting. Maybe we should only use this argument + * on the first radeon card probed or provide a way to specify + * a layout for each card ? + */ +#ifdef CONFIG_FB_RADEON_I2C + dbg("use monitor layout\r\n"); + if (!ignore_edid) + { + if (rinfo->mon1_type != MT_NONE) + { + dbg("probe ddc_dvi on MON1\r\n"); + if (!radeon_probe_i2c_connector(rinfo, ddc_dvi, &rinfo->mon1_EDID)) + { + dbg("probe ddc_crt2 on MON1\r\n"); + radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon1_EDID); + ddc_crt2_used = 1; + } + } + if (rinfo->mon2_type != MT_NONE) + { + dbg("probe ddc_vga on MON2\r\n"); + if (!radeon_probe_i2c_connector(rinfo, ddc_vga, &rinfo->mon2_EDID) && !ddc_crt2_used) + { + dbg("probe ddc_crt2 on MON2\r\n"); + radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon2_EDID); + } + } + } +#endif /* CONFIG_FB_RADEON_I2C */ + if (rinfo->mon1_type == MT_NONE) + { + if (rinfo->mon2_type != MT_NONE) + { + rinfo->mon1_type = rinfo->mon2_type; + rinfo->mon1_EDID = rinfo->mon2_EDID; + } + else + { + rinfo->mon1_type = MT_CRT; + dbg("No valid monitor, assuming CRT on first port\r\n"); + } + rinfo->mon2_type = MT_NONE; + rinfo->mon2_EDID = NULL; + } + } + else + { + /* + * Auto-detecting display type (well... trying to ...) + */ +#ifdef CONFIG_FB_RADEON_I2C + dbg("Auto-detecting\r\n"); +#endif +#if 0 //#if DEBUG && defined(CONFIG_FB_RADEON_I2C) + { + unsigned char *EDIDs[4] = { NULL, NULL, NULL, NULL }; + int mon_types[4] = {MT_NONE, MT_NONE, MT_NONE, MT_NONE}; + int i; + for(i = 0; i < 4; i++) + mon_types[i] = radeon_probe_i2c_connector(rinfo, i+1, &EDIDs[i]); + } +#endif /* DEBUG */ + /* + * Old single head cards + */ + if (!rinfo->has_CRTC2) + { +#ifdef CONFIG_FB_RADEON_I2C + if (rinfo->mon1_type == MT_NONE) + { + dbg("probe ddc_dvi on MON1\r\n"); + rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_dvi, &rinfo->mon1_EDID); + } + if (rinfo->mon1_type == MT_NONE) + { + dbg("probe ddc_vga on MON1\r\n"); + rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_vga, &rinfo->mon1_EDID); + } + if (rinfo->mon1_type == MT_NONE) + { + dbg("probe ddc_crt2 on MON1\r\n"); + rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon1_EDID); + } +#endif /* CONFIG_FB_RADEON_I2C */ + if (rinfo->mon1_type == MT_NONE) + rinfo->mon1_type = MT_CRT; + goto bail; + } + /* + * Probe primary head (DVI or laptop internal panel) + */ +#ifdef CONFIG_FB_RADEON_I2C + if (rinfo->mon1_type == MT_NONE) + { + dbg("probe ddc_dvi on MON1\r\n"); + rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_dvi, &rinfo->mon1_EDID); + } + if (rinfo->mon1_type == MT_NONE) + { + dbg("probe ddc_crt2 on MON1\r\n"); + rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon1_EDID); + if (rinfo->mon1_type != MT_NONE) + ddc_crt2_used = 1; + } +#endif /* CONFIG_FB_RADEON_I2C */ + if (rinfo->mon1_type == MT_NONE && rinfo->is_mobility + && (INREG(LVDS_GEN_CNTL) & LVDS_ON)) + { + rinfo->mon1_type = MT_LCD; + dbg("Non-DDC laptop panel detected\r\n"); + } + if (rinfo->mon1_type == MT_NONE) + rinfo->mon1_type = radeon_crt_is_connected(rinfo, rinfo->reversed_DAC); + /* + * Probe secondary head (mostly VGA, can be DVI) + */ +#ifdef CONFIG_FB_RADEON_I2C + if (rinfo->mon2_type == MT_NONE) + { + dbg("probe ddc_vga on MON2\r\n"); + rinfo->mon2_type = radeon_probe_i2c_connector(rinfo, ddc_vga, &rinfo->mon2_EDID); + } + if (rinfo->mon2_type == MT_NONE && !ddc_crt2_used) + { + dbg("probe ddc_crt2 on MON2\r\n"); + rinfo->mon2_type = radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon2_EDID); + } +#endif /* CONFIG_FB_RADEON_I2C */ + if (rinfo->mon2_type == MT_NONE) + rinfo->mon2_type = radeon_crt_is_connected(rinfo, !rinfo->reversed_DAC); + /* + * If we only detected port 2, we swap them, if none detected, + * assume CRT (maybe fallback to old BIOS_SCRATCH stuff ? or look + * at FP registers ?) + */ + if (rinfo->mon1_type == MT_NONE) + { + if (rinfo->mon2_type != MT_NONE) + { + rinfo->mon1_type = rinfo->mon2_type; + rinfo->mon1_EDID = rinfo->mon2_EDID; + } + else + rinfo->mon1_type = MT_CRT; + + rinfo->mon2_type = MT_NONE; + rinfo->mon2_EDID = NULL; + } + /* + * Deal with reversed TMDS + */ + if (rinfo->reversed_TMDS) + { + /* Always keep internal TMDS as primary head */ + if (rinfo->mon1_type == MT_DFP || rinfo->mon2_type == MT_DFP) + { + int tmp_type = rinfo->mon1_type; + unsigned char *tmp_EDID = rinfo->mon1_EDID; + rinfo->mon1_type = rinfo->mon2_type; + rinfo->mon1_EDID = rinfo->mon2_EDID; + rinfo->mon2_type = tmp_type; + rinfo->mon2_EDID = tmp_EDID; + if (rinfo->mon1_type == MT_CRT || rinfo->mon2_type == MT_CRT) + rinfo->reversed_DAC ^= 1; + } + } + } + + if (ignore_edid) + { + driver_mem_free(rinfo->mon1_EDID); + rinfo->mon1_EDID = NULL; + driver_mem_free(rinfo->mon2_EDID); + rinfo->mon2_EDID = NULL; + } + +bail: + dbg("Monitor 1 type %s found\r\n", radeon_get_mon_name(rinfo->mon1_type)); + if (rinfo->mon1_EDID) + { + dbg("EDID probed\r\n"); + } + + if (!rinfo->has_CRTC2) + return; + dbg("Monitor 2 type %s\r\n", radeon_get_mon_name(rinfo->mon2_type)); + if (rinfo->mon2_EDID) + { + dbg("EDID probed\r\n"); + } +} + +/* + * Fill up panel infos from a mode definition, either returned by the EDID + * or from the default mode when we can't do any better + */ +static void radeon_var_to_panel_info(struct radeonfb_info *rinfo, struct fb_var_screeninfo *var) +{ + rinfo->panel_info.xres = var->xres; + rinfo->panel_info.yres = var->yres; + rinfo->panel_info.clock = 100000000 / var->pixclock; + rinfo->panel_info.hOver_plus = var->right_margin; + rinfo->panel_info.hSync_width = var->hsync_len; + rinfo->panel_info.hblank = var->left_margin + (var->right_margin + var->hsync_len); + rinfo->panel_info.vOver_plus = var->lower_margin; + rinfo->panel_info.vSync_width = var->vsync_len; + rinfo->panel_info.vblank = var->upper_margin + (var->lower_margin + var->vsync_len); + rinfo->panel_info.hAct_high = (var->sync & FB_SYNC_HOR_HIGH_ACT) != 0; + rinfo->panel_info.vAct_high = (var->sync & FB_SYNC_VERT_HIGH_ACT) != 0; + rinfo->panel_info.valid = 1; + + /* + * We use a default of 200ms for the panel power delay, + * I need to have a real schedule() instead of mdelay's in the panel code. + * we might be possible to figure out a better power delay either from + * MacOS OF tree or from the EDID block (proprietary extensions ?) + */ + rinfo->panel_info.pwr_delay = 200; +} + +static void radeon_videomode_to_var(struct fb_var_screeninfo *var, + const struct fb_videomode *mode) +{ + var->xres = mode->xres; + var->yres = mode->yres; + var->xres_virtual = mode->xres; + var->yres_virtual = mode->yres; + var->xoffset = 0; + var->yoffset = 0; + var->pixclock = mode->pixclock; + var->left_margin = mode->left_margin; + var->right_margin = mode->right_margin; + var->upper_margin = mode->upper_margin; + var->lower_margin = mode->lower_margin; + var->hsync_len = mode->hsync_len; + var->vsync_len = mode->vsync_len; + var->sync = mode->sync; + var->vmode = mode->vmode; +} + +/* + * Build the modedb for head 1 (head 2 will come later), check panel infos + * from either BIOS or EDID, and pick up the default mode + */ +void radeon_check_modes(struct radeonfb_info *rinfo, struct mode_option *resolution) +{ + struct fb_info *info = rinfo->info; + int has_default_mode = 0; + struct mode_option xres_yres; + dbg("\r\n"); + + /* + * Fill default var first + */ + memcpy(&info->var, &radeonfb_default_var, sizeof(struct fb_var_screeninfo)); + + /* + * Parse EDID detailed timings and deduce panel infos if any. Right now + * we only deal with first entry returned by parse_EDID, we may do better + * some day... + */ + if (!rinfo->panel_info.use_bios_dividers + && rinfo->mon1_type != MT_CRT && rinfo->mon1_EDID) + { + struct fb_var_screeninfo var; + + dbg("fb_parse_edid\r\n"); + if (fb_parse_edid(rinfo->mon1_EDID, &var) == 0) + { + if ((var.xres >= rinfo->panel_info.xres) && (var.yres >= rinfo->panel_info.yres)) + radeon_var_to_panel_info(rinfo, &var); + } + else + { + dbg("no data to parse\r\n"); + } + } + /* + * If we have some valid panel infos, we setup the default mode based on + * those + */ + if (rinfo->mon1_type != MT_CRT && rinfo->panel_info.valid) + { + struct fb_var_screeninfo *var = &info->var; + + dbg("setup the default mode based on panel info\r\n"); + var->xres = rinfo->panel_info.xres; + var->yres = rinfo->panel_info.yres; + var->xres_virtual = rinfo->panel_info.xres; + var->yres_virtual = rinfo->panel_info.yres; + var->xoffset = var->yoffset = 0; + var->bits_per_pixel = 8; + var->pixclock = 100000000 / rinfo->panel_info.clock; + var->left_margin = (rinfo->panel_info.hblank - rinfo->panel_info.hOver_plus - rinfo->panel_info.hSync_width); + var->right_margin = rinfo->panel_info.hOver_plus; + var->upper_margin = (rinfo->panel_info.vblank - rinfo->panel_info.vOver_plus - rinfo->panel_info.vSync_width); + var->lower_margin = rinfo->panel_info.vOver_plus; + var->hsync_len = rinfo->panel_info.hSync_width; + var->vsync_len = rinfo->panel_info.vSync_width; + var->sync = 0; + + if (rinfo->panel_info.hAct_high) + var->sync |= FB_SYNC_HOR_HIGH_ACT; + + if (rinfo->panel_info.vAct_high) + var->sync |= FB_SYNC_VERT_HIGH_ACT; + + var->vmode = 0; + has_default_mode = 1; + } + + /* + * Now build modedb from EDID + */ + if (rinfo->mon1_EDID) + { + fb_edid_to_monspecs(rinfo->mon1_EDID, &info->monspecs); + rinfo->mon1_modedb = info->monspecs.modedb; + rinfo->mon1_dbsize = info->monspecs.modedb_len; + } + /* + * Finally, if we don't have panel infos we need to figure some (or + * we try to read it from card), we try to pick a default mode + * and create some panel infos. Whatever... + */ + if (rinfo->mon1_type != MT_CRT && !rinfo->panel_info.valid) + { + struct fb_videomode *modedb; + int dbsize; + + if (rinfo->panel_info.xres == 0 || rinfo->panel_info.yres == 0) + { + unsigned long tmp = INREG(FP_HORZ_STRETCH) & HORZ_PANEL_SIZE; + + rinfo->panel_info.xres = ((tmp >> HORZ_PANEL_SHIFT) + 1) * 8; + + tmp = INREG(FP_VERT_STRETCH) & VERT_PANEL_SIZE; + rinfo->panel_info.yres = (tmp >> VERT_PANEL_SHIFT) + 1; + } + + if ((rinfo->panel_info.xres <= 8) || (rinfo->panel_info.yres <= 1)) + { + rinfo->mon1_type = MT_CRT; + goto pickup_default; + } + modedb = rinfo->mon1_modedb; + dbsize = rinfo->mon1_dbsize; + xres_yres.used = 1; + xres_yres.width = rinfo->panel_info.xres; + xres_yres.height = rinfo->panel_info.yres; + xres_yres.bpp = xres_yres.freq = 0; + if (fb_find_mode(&info->var, info, &xres_yres, modedb, dbsize, NULL, + (resolution->bpp >= 8) ? (unsigned int)resolution->bpp : 8) == 0) + { + rinfo->mon1_type = MT_CRT; + goto pickup_default; + } + has_default_mode = 1; + radeon_var_to_panel_info(rinfo, &info->var); + } + +pickup_default: + + /* + * Apply passed-in mode option if any + */ + if (resolution->used) + { + if (fb_find_mode(&info->var, info, resolution, info->monspecs.modedb, + info->monspecs.modedb_len, NULL, (resolution->bpp >= 8) ? (unsigned int)resolution->bpp : 8) != 0) + has_default_mode = 1; + } + + /* + * Still no mode, let's pick up a default from the db + */ + if (!has_default_mode && info->monspecs.modedb != NULL) + { + struct fb_monspecs *specs = &info->monspecs; + struct fb_videomode *modedb = NULL; + + /* get preferred timing */ + if (specs->misc & FB_MISC_1ST_DETAIL) + { + int i; + for(i = 0; i < specs->modedb_len; i++) + { + if (specs->modedb[i].flag & FB_MODE_IS_FIRST) + { + modedb = &specs->modedb[i]; + break; + } + } + } + else + { + /* otherwise, get first mode in database */ + modedb = &specs->modedb[0]; + } + + if (modedb != NULL) + { + info->var.bits_per_pixel = 8; + radeon_videomode_to_var(&info->var, modedb); + has_default_mode = 1; + } + } +} + +/* + * The code below is used to pick up a mode in check_var and + * set_var. It should be made generic + */ + +/* + * This is used when looking for modes. We assign a "distance" value + * to a mode in the modedb depending how "close" it is from what we + * are looking for. + * Currently, we don't compare that much, we could do better but + * the current fbcon doesn't quite mind ;) + */ +static int radeon_compare_modes(const struct fb_var_screeninfo *var, + const struct fb_videomode *mode) +{ + int distance = 0; + + distance = mode->yres - var->yres; + distance += (mode->xres - var->xres)/2; + + return distance; +} + +/* + * This function is called by check_var, it gets the passed in mode parameter, and + * outputs a valid mode matching the passed-in one as closely as possible. + * We need something better ultimately. + */ +int32_t radeon_match_mode(struct radeonfb_info *rinfo, + struct fb_var_screeninfo *dest, + const struct fb_var_screeninfo *src) +{ + const struct fb_videomode *db = vesa_modes; + int i, dbsize = 34; + int has_rmx, native_db = 0; + int distance = INT_MAX; + const struct fb_videomode *candidate = NULL; + + dbg("\r\n"); + + /* Start with a copy of the requested mode */ + memcpy(dest, src, sizeof(struct fb_var_screeninfo)); + + /* Check if we have a modedb built from EDID */ + if (rinfo->mon1_modedb) + { + db = rinfo->mon1_modedb; + dbsize = rinfo->mon1_dbsize; + native_db = 1; + } + /* Check if we have a scaler allowing any fancy mode */ + has_rmx = (rinfo->mon1_type == MT_LCD) || (rinfo->mon1_type == MT_DFP); + + /* If we have a scaler and are passed FB_ACTIVATE_TEST or + * FB_ACTIVATE_NOW, just do basic checking and return if the + * mode match + */ + if ((src->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_TEST + || (src->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) + { + /* We don't have an RMX, validate timings. If we don't have + * monspecs, we should be paranoid and not let use go above + * 640x480-60, but I assume userland knows what it's doing here + * (though I may be proven wrong...) + */ + if ((has_rmx == 0) && rinfo->mon1_modedb) + { + if (fb_validate_mode((struct fb_var_screeninfo *)src, rinfo->info)) + return -1; //-EINVAL; + } + return 0; + } + dbg("look for a mode in the database\r\n"); + + /* Now look for a mode in the database */ + while(db) + { + for (i = 0; i < dbsize; i++) + { + int d; + + if ((db[i].yres < src->yres) || (db[i].xres < src->xres)) + continue; + d = radeon_compare_modes(src, &db[i]); + /* If the new mode is at least as good as the previous one, + * then it's our new candidate + */ + if (d < distance) + { + candidate = &db[i]; + distance = d; + } + } + db = NULL; + /* If we have a scaler, we allow any mode from the database */ + if (native_db && has_rmx) + { + db = vesa_modes; + dbsize = 34; + native_db = 0; + } + } + /* If we have found a match, return it */ + if (candidate != NULL) + { + radeon_videomode_to_var(dest, candidate); + return 0; + } + /* If we haven't and don't have a scaler, fail */ + if (!has_rmx) + return -1; //-EINVAL; + return 0; +} diff --git a/spi/dspi.c b/spi/dspi.c new file mode 100644 index 0000000..6b77a99 --- /dev/null +++ b/spi/dspi.c @@ -0,0 +1,188 @@ +/* + * dspi.c + * + * Coldfire DSPI (DMA Serial Peripherial Interface). + * + * On the Coldfire, the DSPI interface supports 4 SPI output channels and one input channel. + * On the Firebee, DSPICS5 is connected to the SD card slot. + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 16.10.2013 + * Author: mfro + */ + +#include +#include + +struct baudrate +{ + int br_divisor; + int pbr_divisor; + int divider; +}; + +static const int system_clock = 132000000; /* System clock in Hz */ + +static struct baudrate baudrates[] = +{ + { 0b0000, 0b00, 4 }, + { 0b0000, 0b01, 6 }, + { 0b0001, 0b00, 8 }, + { 0b0000, 0b10, 10 }, + { 0b0001, 0b01, 12 }, + { 0b0010, 0b00, 12 }, + { 0b0000, 0b11, 14 }, + { 0b0011, 0b00, 16 }, + { 0b0010, 0b01, 18 }, + { 0b0001, 0b10, 20 }, + { 0b0011, 0b01, 24 }, + { 0b0001, 0b11, 28 }, + { 0b0010, 0b10, 30 }, + { 0b0100, 0b00, 32 }, + { 0b0011, 0b10, 40 }, + { 0b0010, 0b11, 42 }, + { 0b0100, 0b01, 48 }, + { 0b0011, 0b11, 56 }, + { 0b0101, 0b00, 64 }, + { 0b0100, 0b10, 80 }, + { 0b0101, 0b01, 96 }, + { 0b0100, 0b11, 112 }, + { 0b0110, 0b00, 128 }, + { 0b0101, 0b10, 160 }, + { 0b0110, 0b01, 192 }, + { 0b0101, 0b11, 224 }, + { 0b0111, 0b00, 256 }, + { 0b0110, 0b10, 320 }, + { 0b0111, 0b01, 384 }, + { 0b0110, 0b11, 448 }, + { 0b1000, 0b00, 512 }, + { 0b0111, 0b10, 640 }, + { 0b1000, 0b01, 768 }, + { 0b0111, 0b11, 896 }, + { 0b1001, 0b00, 1024 }, + { 0b1000, 0b10, 1280 }, + { 0b1001, 0b01, 1536 }, + { 0b1000, 0b11, 1792 }, + { 0b1010, 0b00, 2048 }, + { 0b1001, 0b10, 2560 }, + { 0b1010, 0b01, 3072 }, + { 0b1001, 0b11, 3584 }, + { 0b1011, 0b00, 4096 }, + { 0b1010, 0b10, 5120 }, + { 0b1011, 0b01, 6144 }, + { 0b1010, 0b11, 7168 }, + { 0b1100, 0b00, 8192 }, + { 0b1011, 0b10, 10240 }, + { 0b1100, 0b01, 12288 }, + { 0b1011, 0b11, 14336 }, + { 0b1101, 0b00, 16384 }, + { 0b1100, 0b10, 20480 }, + { 0b1101, 0b01, 24576 }, + { 0b1100, 0b11, 28672 }, + { 0b1110, 0b00, 32768 }, + { 0b1101, 0b10, 40960 }, + { 0b1110, 0b01, 49152 }, + { 0b1101, 0b11, 57344 }, + { 0b1111, 0b00, 65536 }, + { 0b1110, 0b10, 81920 }, + { 0b1111, 0b01, 98304 }, + { 0b1110, 0b11, 114688 }, + { 0b1111, 0b10, 163840 }, + { 0b1111, 0b11, 229376 }, +}; + +/* + * set the dspi clock to rate or - if no exact match possible - to the next lower possible baudrate + */ +int dspi_set_baudrate(int rate) +{ + int set_baudrate = 0; + int br; + int pbr; + int i; + + for (i = sizeof(baudrates) / sizeof(struct baudrate) - 1; i >= 0; i--) + { + set_baudrate = system_clock / baudrates[i].divider; + + if (set_baudrate > rate) + { + continue; + } + br = baudrates[i].br_divisor; + pbr = baudrates[i].pbr_divisor; + + /* TODO: set br and pbr here */ + (void) pbr; + (void) br; + return set_baudrate; + } + + return 0; +} + +static uint32_t dspi_fifo_val = MCF_DSPI_DTFR_CTCNT; + +/* + * Exchange a byte. If last is false (0), there will be more bytes to follow (EOQ flag in DTFR left unset) + */ +uint8_t dspi_xchg_byte(int device, uint8_t byte, int last) +{ + uint32_t fifo; + uint8_t res; + + fifo = dspi_fifo_val | (byte & 0xff); /* transfer bytes only */ + fifo |= (last ? MCF_DSPI_DTFR_EOQ : 0); /* mark last transfer */ + MCF_DSPI_DTFR = fifo; + while (! (MCF_DSPI_DSR & MCF_DSPI_DSR_TCF)); /* wait until DSPI transfer complete */ + fifo = MCF_DSPI_DRFR; /* read transferred word */ + + MCF_DSPI_DSR = -1; /* clear DSPI status register */ + + res = fifo & 0xff; + + return res; +} + +/* Receive multiple byte with 0xff as output + * + * buff: pointer to data buffer + * btr: number of bytes to receive (16, 64 or 512) + */ +void dspi_rcv_byte_multi(int device, uint8_t *buff, uint32_t count) +{ + int i; + + for (i = 0; i < count - 1; i++) + *buff++ = dspi_xchg_byte(device, 0xff, 0); + *buff++ = dspi_xchg_byte(device, 0xff, 1); /* transfer last byte and stop transmission */ +} + +/* Send multiple byte, discard input + * + * buff: pointer to data + * btx: number of bytes to send + */ +void dspi_xmt_byte_multi(int device, const uint8_t *buff, uint32_t btx) +{ + int i; + + for (i = 0; i < btx - 1; i++) + dspi_xchg_byte(device, *buff++, 0); + dspi_xchg_byte(device, *buff++, 1); /* transfer last byte and indicate end of transmission */ +} + diff --git a/spi/mmc.c b/spi/mmc.c new file mode 100644 index 0000000..8819b59 --- /dev/null +++ b/spi/mmc.c @@ -0,0 +1,814 @@ +#include +#include +#include +#include +#include +#include + +/* + * Firebee: MMCv3/SDv1/SDv2 (SPI mode) control module + * + * + * Copyright (C) 2011, ChaN, all right reserved. + * + * This software is a free software and there is NO WARRANTY. + * No restriction on use. You can use, modify and redistribute it for + * personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY. + * Redistributions of source code must retain the above copyright notice. + * + */ + +/* Copyright (C) 2012, mfro, all rights reserved. */ + +// // #define DEBUG_MMC +#ifdef DEBUG_MMC +#define debug_printf(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg); } while (0) +#else +#define debug_printf(format, arg...) do { ; } while (0) +#endif /* DEBUG_MMC */ + +#define CS_LOW() { dspi_fifo_val |= MCF_DSPI_DTFR_CS5; } +#define CS_HIGH() { dspi_fifo_val &= ~MCF_DSPI_DTFR_CS5; } + +/* + * DCTAR_PBR (baud rate prescaler) and DCTAR_BR (baud rate scaler) together determine the SPI baud rate. The forumula is + * + * baud rate = system clock / DCTAR_PBR * 1 / DCTAR_BR. + * + * System clock for the Firebee is 133 MHZ. + * + * The SPICLK_FAST() example calculates as follows: baud rate = 133 MHz / 3 * 1 / 2 = 22,16 MHz + * SPICLK_SLOW() should be between 100 and 400 kHz: 133 MHz / 1 * 1 / 1024 = 129 kHz + */ +#define SPICLK_FAST() { MCF_DSPI_DCTAR0 = MCF_DSPI_DCTAR_TRSZ(0b0111) | /* transfer size = 8 bit */ \ + MCF_DSPI_DCTAR_PCSSCK(0b01) | /* 3 clock DSPICS to DSPISCK delay prescaler */ \ + MCF_DSPI_DCTAR_PASC_3CLK | /* 3 clock DSPISCK to DSPICS negation prescaler */ \ + MCF_DSPI_DCTAR_PDT_3CLK | /* 3 clock delay between DSPICS assertions prescaler */ \ + MCF_DSPI_DCTAR_PBR_1CLK | /* 3 clock baudrate prescaler */ \ + MCF_DSPI_DCTAR_CSSCK(1) | /* delay scaler * 4 */\ + MCF_DSPI_DCTAR_ASC(0b0001) | /* 2 */ \ + MCF_DSPI_DCTAR_DT(0b0010) | /* 2 */ \ + MCF_DSPI_DCTAR_BR(0b0001); } /* clock / 2 */ + +#define SPICLK_SLOW() { \ + MCF_DSPI_DCTAR0 = MCF_DSPI_DCTAR_TRSZ(0b111) | /* transfer size = 8 bit */ \ + MCF_DSPI_DCTAR_PCSSCK(0b01) | /* 3 clock DSPICS to DSPISCK delay prescaler */ \ + MCF_DSPI_DCTAR_PASC_3CLK | /* 3 clock DSPISCK to DSPICS negation prescaler */ \ + MCF_DSPI_DCTAR_PDT_3CLK | /* 3 clock delay between DSPICS assertions prescaler */ \ + MCF_DSPI_DCTAR_PBR_3CLK | /* 1 clock baudrate prescaler */ \ + MCF_DSPI_DCTAR_CSSCK(8) | /* delay scaler * 512 */\ + MCF_DSPI_DCTAR_ASC(8) | /* 2 */ \ + MCF_DSPI_DCTAR_DT(9) | /* 2 */ \ + MCF_DSPI_DCTAR_BR(7); \ + } + + + +/*-------------------------------------------------------------------------- + + Module Private Functions + +---------------------------------------------------------------------------*/ + +#include "diskio.h" + + +/* MMC/SD command */ +#define CMD0 (0) /* GO_IDLE_STATE */ +#define CMD1 (1) /* SEND_OP_COND (MMC) */ +#define ACMD41 (0x80+41) /* SEND_OP_COND (SDC) */ +#define CMD8 (8) /* SEND_IF_COND */ +#define CMD9 (9) /* SEND_CSD */ +#define CMD10 (10) /* SEND_CID */ +#define CMD12 (12) /* STOP_TRANSMISSION */ +#define ACMD13 (0x80+13) /* SD_STATUS (SDC) */ +#define CMD16 (16) /* SET_BLOCKLEN */ +#define CMD17 (17) /* READ_SINGLE_BLOCK */ +#define CMD18 (18) /* READ_MULTIPLE_BLOCK */ +#define CMD23 (23) /* SET_BLOCK_COUNT (MMC) */ +#define ACMD23 (0x80+23) /* SET_WR_BLK_ERASE_COUNT (SDC) */ +#define CMD24 (24) /* WRITE_BLOCK */ +#define CMD25 (25) /* WRITE_MULTIPLE_BLOCK */ +#define CMD32 (32) /* ERASE_ER_BLK_START */ +#define CMD33 (33) /* ERASE_ER_BLK_END */ +#define CMD38 (38) /* ERASE */ +#define CMD55 (55) /* APP_CMD */ +#define CMD58 (58) /* READ_OCR */ + + +static volatile DSTATUS Stat = 0 /* STA_NOINIT */; /* Physical drive status */ +static uint8_t CardType; /* Card type flags */ + + +static uint32_t dspi_fifo_val = MCF_DSPI_DTFR_CTCNT; + +/*-----------------------------------------------------------------------*/ +/* Send/Receive data to the MMC (Platform dependent) */ +/*-----------------------------------------------------------------------*/ + +/* + * Exchange a byte. If last is false (0), there will be more bytes to follow (EOQ flag in DTFR left unset) + */ +static uint8_t xchg_spi(uint8_t byte, int last) +{ + uint32_t fifo; + uint8_t res; + + fifo = dspi_fifo_val | (byte & 0xff); /* transfer bytes only */ + //fifo |= (last ? MCF_DSPI_DTFR_EOQ : 0); /* mark last transfer */ + MCF_DSPI_DTFR = fifo; + while (! (MCF_DSPI_DSR & MCF_DSPI_DSR_TCF)); /* wait until DSPI transfer complete */ + fifo = MCF_DSPI_DRFR; /* read transferred word */ + + MCF_DSPI_DSR = -1; /* clear DSPI status register */ + + res = fifo & 0xff; + + return res; +} + + +/* Receive multiple byte + * + * buff: pointer to data buffer + * btr: number of bytes to receive (16, 64 or 512) + */ +static void rcvr_spi_multi(uint8_t *buff, uint32_t count) +{ + int i; + + for (i = 0; i < count - 1; i++) + *buff++ = xchg_spi(0xff, 0); + *buff++ = xchg_spi(0xff, 1); /* transfer last byte and stop transmission */ +} + + +#if _USE_WRITE +/* Send multiple byte + * + * buff: pointer to data + * btx: number of bytes to send + */ +static void xmit_spi_multi(const uint8_t *buff, uint32_t btx) +{ + int i; + + for (i = 0; i < btx - 1; i++) + xchg_spi(*buff++, 0); + xchg_spi(*buff++, 1); /* transfer last byte and indicate end of transmission */ +} +#endif + + +static bool card_ready(void) +{ + uint8_t d; + + d = xchg_spi(0xff, 1); + return (d == 0xff); +} + +/* + * Wait for card ready + * + * wt: timeout in ns + * returns 1: ready, 0: timeout + */ +static int wait_ready(uint32_t wt) +{ + return waitfor(wt * 1000, card_ready); +} + + + +/* + * Deselect card and release SPI + */ +static void deselect(void) +{ + CS_HIGH(); + wait_ready(50); /* Dummy clock (force DO hi-z for multiple slave SPI) */ +} + + + +/* + * Select card and wait for ready + */ + +static int select(void) /* 1:OK, 0:Timeout */ +{ + CS_LOW(); + + if (wait_ready(500)) + return 1; /* OK */ + deselect(); + return 0; /* Timeout */ +} + + + +/* + * Control SPI module (Platform dependent) + */ +static void power_on(void) /* Enable SSP module */ +{ + MCF_PAD_PAR_DSPI = 0x1fff; /* configure all DSPI GPIO pins for DSPI usage */ + dspi_fifo_val = MCF_DSPI_DTFR_CTCNT; + /* + * initialize DSPI module configuration register + */ + MCF_DSPI_DMCR = MCF_DSPI_DMCR_MSTR | /* FireBee is DSPI master*/ + MCF_DSPI_DMCR_CSIS5 | /* CS5 inactive state high */ + MCF_DSPI_DMCR_CSIS3 | /* CS3 inactive state high */ + MCF_DSPI_DMCR_CSIS2 | /* CS2 inactive state high */ + MCF_DSPI_DMCR_CSIS0 | /* CS0 inactive state high */ + MCF_DSPI_DMCR_DTXF | /* disable transmit FIFO */ + MCF_DSPI_DMCR_DRXF | /* disable receive FIFO */ + MCF_DSPI_DMCR_CTXF | /* clear transmit FIFO */ + MCF_DSPI_DMCR_CRXF; /* clear receive FIFO */ + + /* initialize DSPI clock and transfer attributes register 0 */ + SPICLK_SLOW(); + + CS_HIGH(); /* Set CS# high */ + + /* card should now be initialized as MMC */ + + wait(10 * 1000); /* 10ms */ +} + + +static void power_off (void) /* Disable SPI function */ +{ + select(); /* Wait for card ready */ + deselect(); +} + + +/*-----------------------------------------------------------------------*/ +/* Receive a data packet from the MMC */ +/*-----------------------------------------------------------------------*/ +static int rcvr_datablock(uint8_t *buff, uint32_t btr) +{ + uint8_t token; + int32_t target = MCF_SLT_SCNT(0) - (200L * 1000L * 132L); + + do { /* Wait for DataStart token in timeout of 200ms */ + token = xchg_spi(0xFF, 0); + } while ((token == 0xFF) && MCF_SLT_SCNT(0) - target > 0); + + if (token == 0xff) + { + debug_printf("no data start token received after 2000ms in rcvr_datablock\r\n"); + return 0; + } + + if (token != 0xFE) + { + debug_printf("invalid token (%x) in rcvr_datablock()!\r\n", token); + return 0; /* Function fails if invalid DataStart token or timeout */ + } + + rcvr_spi_multi(buff, btr); /* Store trailing data to the buffer */ + + xchg_spi(0xFF, 1); + xchg_spi(0xFF, 1); /* Discard CRC */ + + return 1; /* Function succeeded */ +} + + + +/*-----------------------------------------------------------------------*/ +/* Send a data packet to the MMC */ +/*-----------------------------------------------------------------------*/ + +#if _USE_WRITE +static int xmit_datablock(const uint8_t *buff, uint8_t token) +{ + uint8_t resp; + + + if (!wait_ready(500)) + { + debug_printf("card did not respond ready after 500 ms in xmit_datablock()\r\n"); + return 0; /* Wait for card ready */ + } + + xchg_spi(token, 1); /* Send token */ + if (token != 0xFD) { /* Send data if token is other than StopTran */ + xmit_spi_multi(buff, 512); /* Data */ + xchg_spi(0xFF, 1); + xchg_spi(0xFF, 1); /* Dummy CRC */ + + resp = xchg_spi(0xFF, 1); /* Receive data resp */ + if ((resp & 0x1F) != 0x05) /* Function fails if the data packet was not accepted */ + { + debug_printf("card did not accept data packet in xmit_datablock() (resp = %x)\r\n", resp & 0x1F); + return 0; + } + } + + wait_ready(30); + + return 1; +} +#endif + + +/*-----------------------------------------------------------------------*/ +/* Send a command packet to the MMC */ +/*-----------------------------------------------------------------------*/ + +static uint8_t send_cmd(uint8_t cmd, uint32_t arg) +{ + int n; + int res; + + if (cmd & 0x80) + { /* Send a CMD55 prior to ACMD */ + cmd &= 0x7F; + res = send_cmd(CMD55, 0); + if (res > 1) + return res; + } + + /* Select card */ + deselect(); + if (!select()) + { + debug_printf("card could not be selected in send_cmd()\r\n"); + return 0xFF; + } + + if (!wait_ready(500)) + { + debug_printf("card did not respond ready after 5000 ms in send_cmd()\r\n"); + return 0xff; /* Wait for card ready */ + } + + /* Send command packet */ + xchg_spi(0x40 | cmd, 0); /* Start + command index */ + xchg_spi((uint8_t)(arg >> 24), 0); /* Argument[31..24] */ + xchg_spi((uint8_t)(arg >> 16), 0); /* Argument[23..16] */ + xchg_spi((uint8_t)(arg >> 8), 0); /* Argument[15..8] */ + xchg_spi((uint8_t)arg, 1); /* Argument[7..0] */ + + n = 0x01; /* Dummy CRC + Stop */ + if (cmd == CMD0) + n = 0x95; /* Valid CRC for CMD0(0) */ + if (cmd == CMD8) + n = 0x87; /* Valid CRC for CMD8(0x1AA) */ + xchg_spi(n, 0); + + /* Receive command resp */ + if (cmd == CMD12) + { + xchg_spi(0xFF, 0); /* Discard following one byte when CMD12 */ + } + + n = 1000; /* Wait for response (1000 bytes max) */ + do + res = xchg_spi(0xFF, 1); + while ((res & 0x80) && --n); + return res; /* Return received response */ +} + + + +/*-------------------------------------------------------------------------- + + Public Functions + +---------------------------------------------------------------------------*/ + + +/* + * Initialize disk drive + * + * drv: physical drive number (0) + */ +DSTATUS disk_initialize(uint8_t drv) +{ + uint8_t n, cmd, card_type, ocr[4]; + + if (drv) + return STA_NOINIT; /* Supports only drive 0 */ + + power_on(); /* Initialize SPI */ + + if (Stat & STA_NODISK) + return Stat; /* Is card existing in the socket? */ + + SPICLK_SLOW(); + + for (n = 10; n; n--) + xchg_spi(0xFF, 1); /* Send 80 dummy clocks */ + + card_type = 0; + if (send_cmd(CMD0, 0) == 1) + { + /* Put the card SPI/Idle state */ + int32_t target; + + if (send_cmd(CMD8, 0x1AA) == 1) { /* SDv2? */ + for (n = 0; n < 4; n++) + ocr[n] = xchg_spi(0xFF, 1); /* Get 32 bit return value of R7 resp */ + if (ocr[2] == 0x01 && ocr[3] == 0xAA) + { + int res; + + /* Is the card supports vcc of 2.7-3.6V? */ + target = MCF_SLT_SCNT(0) - (1000L * 1000L * 132); /* 1 sec */ + while (MCF_SLT_SCNT(0) - target > 0) + { + res = send_cmd(ACMD41, 1UL << 30); /* Wait for end of initialization with ACMD41(HCS) */ + if (res != 0xff) + break; + } + debug_printf("res = %d\r\n", res); + + target = MCF_SLT_SCNT(0) - (1000L * 1000L * 132); /* 1 sec */ + while (MCF_SLT_SCNT(0) - target > 0) + { + res = send_cmd(CMD58, 0); /* Check CCS bit in the OCR */ + if (res != 0xff) + break; + } + debug_printf("res = %d\r\n", res); + for (n = 0; n < 4; n++) + ocr[n] = xchg_spi(0xFF, 1); + card_type = (ocr[0] & 0x40) ? CT_SD2 | CT_BLOCK : CT_SD2; /* Card id SDv2 */ + } + } + else + { /* Not SDv2 card */ + if (send_cmd(ACMD41, 0) <= 1) + { /* SDv1 or MMC? */ + card_type = CT_SD1; + cmd = ACMD41; /* SDv1 (ACMD41(0)) */ + } else { + card_type = CT_MMC; + cmd = CMD1; /* MMCv3 (CMD1(0)) */ + } + target = MCF_SLT_SCNT(0) - (1000L * 1000L * 132); /* 1 sec */ + while (MCF_SLT_SCNT(0) - target > 0 && send_cmd(cmd, 0)); /* Wait for end of initialization */ + + if (send_cmd(CMD16, 512) != 0) /* Set block length: 512 */ + card_type = 0; + } + } + CardType = card_type; /* Card type */ + +#ifdef DEBUG + { + uint8_t buff[16]; + res = disk_ioctl(0, MMC_GET_CSD, buff); + + if (res == RES_OK) + { + debug_printf("CSD of card:\r\n"); + hexdump(buff, 16); + } + } +#endif /* DEBUG */ + + deselect(); + + if (card_type) + { + /* OK */ + + SPICLK_FAST(); /* Set fast clock */ + Stat &= ~STA_NOINIT; /* Clear STA_NOINIT flag */ + debug_printf("card type: %d\r\n", card_type); + //res = disk_ioctl(0, MMC_GET_CSD, buff); + /* + if (res == RES_OK) + { + debug_printf("CSD of card now:\r\n"); + hexdump(buff, 16); + } + */ + deselect(); + + } + else + { + /* Failed */ + xprintf("no card type detected in disk_initialize()\r\n"); + power_off(); + Stat = STA_NOINIT; + } + + return Stat; +} + + + +/*-----------------------------------------------------------------------*/ +/* Get disk status */ +/*-----------------------------------------------------------------------*/ + +DSTATUS disk_status(uint8_t drv) +{ + if (drv) return STA_NOINIT; /* Supports only drive 0 */ + + return Stat; /* Return disk status */ +} + +DSTATUS disk_reset(uint8_t drv) +{ + if (drv) return STA_NOINIT; + + deselect(); + disk_initialize(0); + + return 0; +} + +/*-----------------------------------------------------------------------*/ +/* Read sector(s) */ +/*-----------------------------------------------------------------------*/ + +DRESULT disk_read(uint8_t drv, uint8_t *buff, uint32_t sector, uint8_t count) +{ + if (drv) + { + debug_printf("wrong drive in disk_read()\r\n"); + return RES_PARERR; /* Check parameter */ + } + + if (! count) + { + debug_printf("wrong count in disk_read()\r\n"); + return RES_PARERR; + } + + if (Stat & STA_NOINIT) + { + debug_printf("drive not ready in disk_read()\r\n"); + return RES_NOTRDY; /* Check if drive is ready */ + } + + if (!(CardType & CT_BLOCK)) sector *= 512; /* LBA or BA conversion (byte addressing cards) */ + + if (count == 1) { /* Single sector read */ + if ((send_cmd(CMD17, sector) == 0)) /* READ_SINGLE_BLOCK */ + if (rcvr_datablock(buff, 512)) + count = 0; + } + else { /* Multiple sector read */ + if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */ + do { + if (!rcvr_datablock(buff, 512)) + break; + buff += 512; + } while (--count); + send_cmd(CMD12, 0); /* STOP_TRANSMISSION */ + } + } + deselect(); + + return count ? RES_ERROR : RES_OK; /* Return result */ +} + + + +/*-----------------------------------------------------------------------*/ +/* Write sector(s) */ +/*-----------------------------------------------------------------------*/ + +#if _USE_WRITE +DRESULT disk_write(uint8_t drv, const uint8_t *buff, uint32_t sector, uint8_t count) +{ + int res; + + if (drv || !count) return RES_PARERR; /* Check parameter */ + if (Stat & STA_NOINIT) return RES_NOTRDY; /* Check drive status */ + if (Stat & STA_PROTECT) return RES_WRPRT; /* Check write protect */ + + if (!(CardType & CT_BLOCK)) + { + sector *= 512; /* LBA ==> BA conversion (byte addressing cards) */ + } + + if (count == 1) + { /* Single sector write */ + res = send_cmd(CMD24, sector); + if (res == 0) + { + count = 0; + } + else + debug_printf("send_cmd(CMD24, ...) failed in disk_write()\r\n"); + + if (xmit_datablock(buff, 0xFE)) + { + count = 0; + } + else + { + debug_printf("xmit_datablock(buff, ...) failed in disk_write()\r\n"); + } + } + else { /* Multiple sector write */ + if (CardType & CT_SDC) send_cmd(ACMD23, count); /* Predefine number of sectors */ + if (send_cmd(CMD25, sector) == 0) + { /* WRITE_MULTIPLE_BLOCK */ + do + { + if (!xmit_datablock(buff, 0xFC)) break; + buff += 512; + } while (--count); + + if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */ + { + count = 1; + } + } + } + deselect(); + + if (count) /* we had an error, try a reinit */ + { + debug_printf("disk_write() failed (count=%d)\r\n", count); + } + + return count ? RES_ERROR : RES_OK; /* Return result */ +} +#endif + + +/*-----------------------------------------------------------------------*/ +/* Miscellaneous drive controls other than data read/write */ +/*-----------------------------------------------------------------------*/ + +#if _USE_IOCTL +DRESULT disk_ioctl(uint8_t drv, uint8_t ctrl, void *buff) +{ + DRESULT res; + uint8_t n, csd[16], *ptr = buff; + uint32_t *dp, st, ed, csize; + + + if (drv) return RES_PARERR; /* Check parameter */ + if (Stat & STA_NOINIT) return RES_NOTRDY; /* Check if drive is ready */ + + res = RES_ERROR; + + switch (ctrl) { + case CTRL_SYNC : /* Wait for end of internal write process of the drive */ + if (select()) { + deselect(); + res = RES_OK; + } + break; + + case GET_SECTOR_COUNT : /* Get drive capacity in unit of sector (DWORD) */ + if ((send_cmd(CMD9, 0) == 0)) + { + if (rcvr_datablock(csd, 16)) + { + if ((csd[0] >> 6) == 1) + { /* SDC ver 2.00 */ + csize = csd[9] + ((uint16_t)csd[8] << 8) + ((uint32_t)(csd[7] & 63) << 16) + 1; + * (uint32_t*) buff = csize << 10; + } + else + { + /* SDC ver 1.XX or MMC ver 3 */ + n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2; + csize = (csd[8] >> 6) + ((uint16_t)csd[7] << 2) + ((uint16_t)(csd[6] & 3) << 10) + 1; + * (uint32_t*) buff = csize << (n - 9); + } + } + res = RES_OK; + } + break; + + case GET_SECTOR_SIZE : /* Get sector size in unit of byte (WORD) */ + * (uint32_t*) buff = 512; + res = RES_OK; + break; + + case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */ + if (CardType & CT_SD2) { /* SDC ver 2.00 */ + if (send_cmd(ACMD13, 0) == 0) { /* Read SD status */ + xchg_spi(0xFF, 1); + if (rcvr_datablock(csd, 16)) { /* Read partial block */ + for (n = 64 - 16; n; n--) xchg_spi(0xFF, 1); /* Purge trailing data */ + *(uint32_t*)buff = 16UL << (csd[10] >> 4); + res = RES_OK; + } + } + } else { /* SDC ver 1.XX or MMC */ + if ((send_cmd(CMD9, 0) == 0)) + { + if (rcvr_datablock(csd, 16)) + { + /* Read CSD */ + if (CardType & CT_SD1) + { /* SDC ver 1.XX */ + * (uint32_t*) buff = (((csd[10] & 63) << 1) + ((uint16_t)(csd[11] & 128) >> 7) + 1) << ((csd[13] >> 6) - 1); + } + else + { + /* MMC */ + *(uint32_t*)buff = ((uint16_t)((csd[10] & 124) >> 2) + 1) * (((csd[11] & 3) << 3) + ((csd[11] & 224) >> 5) + 1); + } + } + res = RES_OK; + } + } + break; + + case CTRL_ERASE_SECTOR : /* Erase a block of sectors (used when _USE_ERASE == 1) */ + if (!(CardType & CT_SDC)) break; /* Check if the card is SDC */ + if (disk_ioctl(drv, MMC_GET_CSD, csd)) break; /* Get CSD */ + if (!(csd[0] >> 6) && !(csd[10] & 0x40)) break; /* Check if sector erase can be applied to the card */ + dp = buff; st = dp[0]; ed = dp[1]; /* Load sector block */ + if (!(CardType & CT_BLOCK)) { + st *= 512; ed *= 512; + } + if (send_cmd(CMD32, st) == 0) + { + if (send_cmd(CMD33, ed) == 0) + if (send_cmd(CMD38, 0) == 0) + if (wait_ready(30)) + ; /* Erase sector block */ + } + res = RES_OK; /* FatFs does not check result of this command */ + break; + + /* Following command are not used by FatFs module */ + + case MMC_GET_TYPE : /* Get MMC/SDC type (BYTE) */ + *ptr = CardType; + res = RES_OK; + break; + + case MMC_GET_CSD : /* Read CSD (16 bytes) */ + if (send_cmd(CMD9, 0) == 0 /* READ_CSD */ + && rcvr_datablock(ptr, 16)) + res = RES_OK; + break; + + case MMC_GET_CID : /* Read CID (16 bytes) */ + if (send_cmd(CMD10, 0) == 0 /* READ_CID */ + && rcvr_datablock(ptr, 16)) + res = RES_OK; + break; + + case MMC_GET_OCR : /* Read OCR (4 bytes) */ + if (send_cmd(CMD58, 0) == 0) { /* READ_OCR */ + for (n = 4; n; n--) *ptr++ = xchg_spi(0xFF, 1); + res = RES_OK; + } + break; + + case MMC_GET_SDSTAT : /* Read SD status (64 bytes) */ + if (send_cmd(ACMD13, 0) == 0) { /* SD_STATUS */ + xchg_spi(0xFF, 1); + if (rcvr_datablock(ptr, 64)) + res = RES_OK; + } + break; + + default: + res = RES_PARERR; + break; + } + + deselect(); + + return res; +} +#endif + + +/*-----------------------------------------------------------------------*/ +/* Device timer function */ +/*-----------------------------------------------------------------------*/ +/* This function must be called from timer interrupt routine in period +/ of 1 ms to generate card control timing. +*/ + +#ifdef _NOT_USED_ +void disk_timerproc (void) +{ + uint8_t s; + + s = Stat; + if (WP) /* Write protected */ + s |= STA_PROTECT; + else /* Write enabled */ + s &= ~STA_PROTECT; + //if (INS) /* Card is in socket */ + s &= ~STA_NODISK; + //else /* Socket empty */ + // s |= (STA_NODISK | STA_NOINIT); + Stat = s; +} +#endif /* _NOT_USED_ */ diff --git a/spi/sd_card.c b/spi/sd_card.c new file mode 100644 index 0000000..b14af74 --- /dev/null +++ b/spi/sd_card.c @@ -0,0 +1,121 @@ +/* + * sd_card.c + * + * Created on: 16.12.2012 + * Author: mfro + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Copyright 2012 M. Froeschle + */ + +#include +#include +#include +#include + +#define WELCOME_NAME "WELCOME.MSG" +#define FLASHCODE_NAME "BENCH.BIN" + +#define FLASHCODE_ADDRESS 0x03000000L + +/* + * initialize SD-card and FF FAT filesystem routines. Harness to load a file during boot. + * + * This is currently more like a proof of concept, + * but will be extended to load and execute a bootstrap flasher to be able to flash the Bee directly + * from card. + */ +void sd_card_init(void) +{ + DRESULT res; + FATFS fs; + FRESULT fres; + + disk_initialize(0); + res = disk_status(0); + xprintf("disk status of SD card is %d\r\n", res); + if (res == RES_OK) + { + fres = f_mount(0, &fs); + xprintf("mount status of SD card fs is %d\r\n", fres); + if (fres == FR_OK) + { + DIR directory; + FIL file; + + fres = f_opendir(&directory, "\\"); + if (fres == FR_OK) + { + FILINFO fi; + + while (((fres = f_readdir(&directory, &fi)) == FR_OK) && fi.fname[0]) + { + xprintf("%13.13s %d\r\n", fi.fname, fi.fsize); + } + } + else + { + xprintf("could not open directory \"\\\" on SD-card! Error code: %d\r\n", fres); + } + + /* + * let's see if we find our boot flashing executable on disk + */ + fres = f_open(&file, FLASHCODE_NAME, FA_READ); + if (fres == FR_OK) + { + /* + * yes, load and execute it + * + * FIXME: we will need some kind of user confirmation here + * to avoid unwanted flashing or "bootsector viruses" before going productive + */ + uint32_t size; /* length of code piece read */ + uint32_t total_size = 0L; + int32_t start_time = MCF_SLT_SCNT(0); + int32_t end_time; + int32_t time = 0; + + while ((fres = f_read(&file, (void *) FLASHCODE_ADDRESS, 1024 * 1000, &size)) == FR_OK && size > 0) + { + total_size += size / 1024; + xprintf("read hunk of %d bytes, total_size = %d kBytes\r\n", size, total_size); + } + end_time = MCF_SLT_SCNT(0); + time = (end_time - start_time) / 132L; + xprintf("result of f_read: %ld, %ld kbytes read\r\n", fres, total_size); + xprintf("time to load %s: %ld s\r\n", FLASHCODE_NAME, time / 1000 / 100); + xprintf("equals to about %ld kBytes/second\r\n", total_size / (time / 1000 / 100)); + + } + f_close(&file); + + fres = f_open(&file, WELCOME_NAME, FA_READ); + if (fres == FR_OK) + { + char line[128]; + + while (f_gets(line, sizeof(line), &file)) + { + xprintf("%s", line); + } + } + f_close(&file); + } + f_mount(0, 0L); /* release work area */ + } +} diff --git a/sys/BaS.c b/sys/BaS.c new file mode 100644 index 0000000..22accd1 --- /dev/null +++ b/sys/BaS.c @@ -0,0 +1,609 @@ +/* + * BaS + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Copyright 2010 - 2012 F. Aschwanden + * Copyright 2011 - 2012 V. Riviere + * Copyright 2012 M. Froeschle + */ + +#include + +#include "MCF5475.h" +#include "startcf.h" +#include "sysinit.h" +#include "util.h" +#include "cache.h" +#include "bas_printf.h" +#include "bas_string.h" +#include "bas_types.h" +#include "bas_utils.h" +#include "sd_card.h" +#include "wait.h" + +#include "ff.h" +#include "s19reader.h" +#include "mmu.h" +#include "dma.h" +#include "net.h" +#include "eth.h" +#include "nbuf.h" +#include "nif.h" +#include "fec.h" +#include "bootp.h" +#include "interrupts.h" +#include "exceptions.h" +#include "net_timer.h" +#include "pci.h" +#include "video.h" + +// #define DEBUG +#include "debug.h" + +/* imported routines */ +extern int vec_init(); + +/* Symbols from the linker script */ +extern uint8_t _STRAM_END[]; +#define STRAM_END ((uint32_t)_STRAM_END) +extern uint8_t _TOS[]; +#define TOS ((uint32_t)_TOS) /* final TOS location */ +extern uint8_t _FASTRAM_END[]; +#define FASTRAM_END ((uint32_t)_FASTRAM_END) +extern uint8_t _EMUTOS[]; +#define EMUTOS ((uint32_t)_EMUTOS) /* where EmuTOS is stored in flash */ +extern uint8_t _EMUTOS_SIZE[]; +#define EMUTOS_SIZE ((uint32_t)_EMUTOS_SIZE) /* size of EmuTOS, in bytes */ + +/* + * check if it is possible to transfer data to PIC + */ +static inline bool pic_txready(void) +{ + if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_TXRDY) + { + return true; + } + + return false; +} + +/* + * check if it is possible to receive data from PIC + */ +static inline bool pic_rxready(void) +{ + if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_RXRDY) + { + return true; + } + + return false; +} + +void write_pic_byte(uint8_t value) +{ + /* + * Wait until the transmitter is ready or 1000us are passed + */ + waitfor(1000, pic_txready); + + /* + * Transmit the byte + */ + *(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT) = value; // Really 8-bit +} + +uint8_t read_pic_byte(void) +{ + /* + * Wait until a byte has been received or 1000us are passed + */ + waitfor(1000, pic_rxready); + + /* + * Return the received byte + */ + return * (volatile uint8_t *) (&MCF_PSC3_PSCTB_8BIT); // Really 8-bit +} + +void pic_init(void) +{ + char answer[4] = "OLD"; + + xprintf("initialize the PIC: "); + + /* + * Send the PIC initialization string + */ + write_pic_byte('A'); + write_pic_byte('C'); + write_pic_byte('P'); + write_pic_byte('F'); + + /* + * Read the 3-char answer string. Should be "OK!". + */ + answer[0] = read_pic_byte(); + answer[1] = read_pic_byte(); + answer[2] = read_pic_byte(); + answer[3] = '\0'; + + if (answer[0] != 'O' || answer[1] != 'K' || answer[2] != '!') + { + dbg("PIC initialization failed. Already initialized?\r\n"); + } + else + { + xprintf("%s\r\n", answer); + } +} + +void nvram_init(void) +{ + int i; + + xprintf("Restore the NVRAM data: "); + + /* Request for NVRAM backup data */ + write_pic_byte(0x01); + + /* Check answer type */ + if (read_pic_byte() != 0x81) + { + // FIXME: PIC protocol error + xprintf("FAILED\r\n"); + return; + } + + /* Restore the NVRAM backup to the FPGA */ + for (i = 0; i < 64; i++) + { + uint8_t data = read_pic_byte(); + * (volatile uint8_t*) 0xffff8961 = i; + * (volatile uint8_t*) 0xffff8963 = data; + } + + xprintf("finished\r\n"); +} + +#define KBD_ACIA_CONTROL * ((uint8_t *) 0xfffffc00) +#define MIDI_ACIA_CONTROL * ((uint8_t *) 0xfffffc04) +#define MFP_INTR_IN_SERVICE_A * ((uint8_t *) 0xfffffa0f) +#define MFP_INTR_IN_SERVICE_B * ((uint8_t *) 0xfffffa11) + +void acia_init() +{ + xprintf("init ACIA: "); + /* init ACIA */ + KBD_ACIA_CONTROL = 3; /* master reset */ + NOP(); + + MIDI_ACIA_CONTROL = 3; /* master reset */ + NOP(); + + KBD_ACIA_CONTROL = 0x96; /* clock div = 64, 8N1, RTS low, TX int disable, RX int enable */ + NOP(); + + MFP_INTR_IN_SERVICE_A = 0xff; + NOP(); + + MFP_INTR_IN_SERVICE_B = 0xff; + NOP(); + + xprintf("finished\r\n"); +} + +void enable_coldfire_interrupts() +{ + xprintf("enable interrupts: "); +#if defined(MACHINE_FIREBEE) + FBEE_INTR_CONTROL = 0L; /* disable all interrupts */ +#endif /* MACHINE_FIREBEE */ + + MCF_EPORT_EPPAR = 0xaaa8; /* all interrupts on falling edge */ + +#ifdef _NOT_USED_ +#if defined(MACHINE_FIREBEE) + /* + * TIN0 on the Coldfire is connected to the FPGA. TIN0 triggers every write + * access to 0xff8201 (vbasehi), i.e. everytime the video base address is written + */ + MCF_GPT0_GMS = MCF_GPT_GMS_ICT(1) | /* timer 0 on, video change capture on rising edge */ + MCF_GPT_GMS_IEN | + MCF_GPT_GMS_TMS(1); /* route GPT0 interrupt on interrupt controller */ + MCF_INTC_ICR62 = MCF_INTC_ICR_IL(7) | + MCF_INTC_ICR_IP(6); /* interrupt level 7, interrupt priority 6 */ + MCF_INTC_IMRH = 0xbffffffe; /* psc3 and timer 0 int on */ +#endif +#endif + xprintf("finished\r\n"); +} + +void enable_pci_interrupts() +{ + dbg("enable PCI interrupts\r\n"); + MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */ + MCF_EPORT_EPFR = 0xff; /* clear all pending interrupts */ + MCF_INTC_IMRL = 0xffffff00; /* int 1-7 on */ + MCF_INTC_IMRH = 0; +#if defined(MACHINE_FIREBEE) + FBEE_INTR_ENABLE = FBEE_INTR_INT_IRQ7 | /* enable pseudo bus error */ + FBEE_INTR_INT_MFP_IRQ6 | /* enable MFP interrupts */ + FBEE_INTR_INT_FPGA_IRQ5 | /* enable Firebee (PIC, PCI, ETH PHY, DVI, DSP) interrupts */ + FBEE_INTR_INT_VSYNC_IRQ4 | /* enable vsync interrupts */ + FBEE_INTR_PCI_INTA | /* enable PCI interrupts */ + FBEE_INTR_PCI_INTB | + FBEE_INTR_PCI_INTC | + FBEE_INTR_PCI_INTD; + ; +#elif defined(MACHINE_M5484LITE) + /* + * MCF 5484 interrupts are configured at the CPLD for the FireEngine + */ + + /* TODO: enable PCI interrupts on the LITEKIT */ +#elif defined(MACHINE_M54455) + /* MCF 54455 interrupts are configured at the FPGA */ + + /* TODO: enable PCI interrupts on the MCF54455 */ +#else +#error unknown machine! +#endif +} + +void disable_coldfire_interrupts() +{ +#if defined(MACHINE_FIREBEE) + FBEE_INTR_ENABLE = 0; /* disable all interrupts */ +#endif /* MACHINE_FIREBEE */ + + MCF_EPORT_EPIER = 0x0; + MCF_INTC_IMRL = 0xfffffffe; + MCF_INTC_IMRH = 0xffffffff; +} + + + +NIF nif1; +#if defined(MACHINE_M5484LITE) + /* + * on the MCF 5484 LITEKIT, the second FEC interface is usable + */ +NIF nif2; +#endif + +bool spurious_interrupt_handler(void *arg1, void *arg2) +{ + err("spurious interrupt\r\n"); + err("IMRH=%lx, IMRL=%lx\r\n", MCF_INTC_IMRH, MCF_INTC_IMRL); + err("IPRH=%lx, IPRL=%lx\r\n", MCF_INTC_IPRH, MCF_INTC_IPRL); + err("IRLR=%x\r\n", MCF_INTC_IRLR); + + return true; +} + +/* + * initialize the interrupt handler tables to dispatch interrupt requests from Coldfire devices + */ +void init_isr(void) +{ + isr_init(); /* need to call that explicitely, otherwise isr table might be full */ + + /* + * register spurious interrupt handler + */ + if (!isr_register_handler(24, 6, 6, spurious_interrupt_handler, NULL, NULL)) + { + dbg("unable to register spurious interrupt handler\r\n"); + } + + /* + * register the FEC interrupt handler + */ + if (!isr_register_handler(64 + INT_SOURCE_FEC0, 5, 1, fec0_interrupt_handler, NULL, (void *) &nif1)) + { + dbg("unable to register isr for FEC0\r\n"); + } + + /* + * Register the DMA interrupt handler + */ + + if (!isr_register_handler(64 + INT_SOURCE_DMA, 5, 3, dma_interrupt_handler, NULL, NULL)) + { + dbg("unable to register isr for DMA\r\n"); + } + +#if defined(MACHINE_FIREBEE) + /* + * register GPT0 timer interrupt vector + */ + if (!isr_register_handler(64 + INT_SOURCE_GPT0, 5, 2, gpt0_interrupt_handler, NULL, NULL)) + { + dbg("unable to register isr for GPT0 timer\r\n"); + } + + /* + * register the PIC interrupt handler + */ + if (!isr_register_handler(64 + INT_SOURCE_PSC3, 5, 5, pic_interrupt_handler, NULL, NULL)) + { + dbg("Error: unable to register ISR for PSC3\r\n"); + } +#endif /* MACHINE_FIREBEE */ + + /* + * register the XLB PCI interrupt handler + */ + if (!isr_register_handler(64 + INT_SOURCE_XLBPCI, 3, 0, xlbpci_interrupt_handler, NULL, NULL)) + { + dbg("Error: unable to register isr for XLB PCI interrupts\r\n"); + } + + + /* + * initialize arbiter timeout registers + */ + MCF_XLB_XARB_ADRTO = 0x1fffff; + MCF_XLB_XARB_DATTO = 0x1fffff; + MCF_XLB_XARB_BUSTO = 0xffffff; + + + MCF_XLB_XARB_IMR = MCF_XLB_XARB_IMR_SEAE | /* slave error acknowledge interrupt */ + MCF_XLB_XARB_IMR_MME | /* multiple master at prio 0 interrupt */ + MCF_XLB_XARB_IMR_TTAE | /* TT address only interrupt */ + MCF_XLB_XARB_IMR_TTRE | /* TT reserved interrupt enable */ + MCF_XLB_XARB_IMR_ECWE | /* external control word interrupt */ + MCF_XLB_XARB_IMR_TTME | /* TBST/TSIZ mismatch interrupt */ + MCF_XLB_XARB_IMR_BAE; /* bus activity tenure timeout interrupt */ + + if (!isr_register_handler(64 + INT_SOURCE_PCIARB, 5, 0, pciarb_interrupt_handler, NULL, NULL)) + { + dbg("Error: unable to register isr for PCIARB interrupts\r\n"); + + return; + } + MCF_PCIARB_PACR = MCF_PCIARB_PACR_EXTMINTEN(0x1f) | /* external master broken interrupt */ + MCF_PCIARB_PACR_INTMINTEN; /* internal master broken interrupt */ + + if (!isr_register_handler(64 + INT_SOURCE_XLBARB, 7, 1, xlbarb_interrupt_handler, NULL, NULL)) + { + dbg("Error: unable to register isr for XLB ARB interrupts\r\n"); + } +} + +/* Jump into the OS */ +typedef void void_func(void); +struct rom_header +{ + void *initial_sp; + void_func *initial_pc; +}; + +/* + * fix ST RAM header (address 0x0 and 0x4). FreeMiNT uses these vectors on CTRL-ALT-DEL. + * + * Beware: Newer compilers refuse to dereference pointers to NULL and abort (trap #7) if the following + * attribute isn't set. + */ +static void fix_stram_header() __attribute__((optimize("no-delete-null-pointer-checks"))); +static void fix_stram_header() +{ + struct rom_header *bas_header = (struct rom_header *) TARGET_ADDRESS; + struct rom_header *stram_header = (struct rom_header *) 0x0; + + *stram_header = *bas_header; +} + +void BaS(void) +{ + uint8_t *src; + uint8_t *dst = (uint8_t *) TOS; + +#if defined(MACHINE_FIREBEE) /* LITE board has no pic and (currently) no nvram */ + pic_init(); + nvram_init(); +#endif /* MACHINE_FIREBEE */ + + xprintf("initialize MMU: "); + mmu_init(); + xprintf("finished\r\n"); + + xprintf("initialize Coldfire DMA: "); + dma_init(); + xprintf("finished\r\n"); + + xprintf("copy EmuTOS: "); + /* copy EMUTOS */ + src = (uint8_t *) EMUTOS; + memcpy(dst, src, EMUTOS_SIZE); + xprintf("finished\r\n"); + + xprintf("flush caches: "); + flush_and_invalidate_caches(); + xprintf("finished\r\n"); + xprintf("enable MMU: "); + MCF_MMU_MMUCR = MCF_MMU_MMUCR_EN; /* MMU on */ + NOP(); /* force pipeline sync */ + xprintf("finished\r\n"); + + xprintf("initialize exception vector table: "); + vec_init(); + xprintf("finished\r\n"); + + + memset((void *) 0x0200, 0x0, 0x0400); + +#if defined(MACHINE_FIREBEE) + xprintf("IDE reset: "); + /* IDE reset */ + * (volatile uint8_t *) (0xffff8802 - 2) = 14; + * (volatile uint8_t *) (0xffff8802 - 0) = 0x80; + wait(1); + + * (volatile uint8_t *) (0xffff8802 - 0) = 0; + + xprintf("finished\r\n"); + xprintf("enable video: "); + + /* + * ATARI video modes "modeline" + * + * horizontal: + * high word: h_total + * low word: hsync_start + * + * vertical: + * high word v_total + * low word vsync_start + * + * can be calculated with umc ("universal modeline generator") + * + */ + struct atari_video_timing + { + uint16_t total; + uint16_t sync_start; + }; + + static volatile struct atari_video_timing *hor_640x480 = (volatile struct atari_video_timing *) 0xf0000410; + static volatile struct atari_video_timing *ver_640x480 = (volatile struct atari_video_timing *) 0xf0000414; + static volatile struct atari_video_timing *hor_320x240 = (volatile struct atari_video_timing *) 0xf0000418; + static volatile struct atari_video_timing *ver_320x240 = (volatile struct atari_video_timing *) 0xf000041c; + +#undef VIDEO_25MHZ + +#ifdef VIDEO_25MHZ + hor_640x480->total = 0x320; /* 800 */ + hor_640x480->sync_start = 0x2ba; /* 698 */ + ver_640x480->total = 0x20c; /* 524 */ + ver_640x480->sync_start = 0x20a; /* 522 */ + + hor_320x240->total = 0x190; /* 400 */ + hor_320x240->sync_start = 0x15d; /* 349 */ + ver_320x240->total = 0x20c; /* 524 */ + ver_320x240->sync_start = 0x20a; /* 522 */ +#else /* 32 MHz */ + hor_640x480->total = 0x370; /* 880 */ + hor_640x480->sync_start = 0x2ba; /* 698 */ + ver_640x480->total = 0x20d; /* 525 */ + ver_640x480->sync_start = 0x20a; /* 522 */ + + hor_320x240->total = 0x2a0; /* 672 */ + hor_320x240->sync_start = 0x1e0; /* 480 */ + ver_320x240->total = 0x5a0; /* 480 */ + ver_320x240->sync_start = 0x160; /* 352 */ +#endif + + /* fifo on, refresh on, ddrcs and cke on, video dac on */ + * (volatile uint32_t *) 0xf0000400 = 0x01070082; + + xprintf("finished\r\n"); +#endif /* MACHINE_FIREBEE */ + + sd_card_init(); + + +#if defined(MACHINE_FIREBEE) + /* set Falcon bus control register */ + /* sets bit 3 and 6. Both are undefined on an original Falcon? */ + + * (volatile uint8_t *) 0xffff8007 = 0x48; +#endif /* MACHINE_FIREBEE */ + + /* ST RAM */ + + * (uint32_t *) 0x42e = STRAM_END; /* phystop TOS system variable */ + * (uint32_t *) 0x420 = 0x752019f3; /* memvalid TOS system variable */ + * (uint32_t *) 0x43a = 0x237698aa; /* memval2 TOS system variable */ + * (uint32_t *) 0x51a = 0x5555aaaa; /* memval3 TOS system variable */ + + /* TT-RAM */ + + * (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */ + * (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */ + +#if defined(MACHINE_FIREBEE) /* m5484lite has no ACIA and no dip switch... */ + acia_init(); +#endif /* MACHINE_FIREBEE */ + + srec_execute("BASFLASH.S19"); + + xprintf("BaS initialization finished, enable interrupts\r\n"); + init_isr(); + + enable_coldfire_interrupts(); + MCF_INTC_IMRH = 0; + MCF_INTC_IMRL = 0; + + dma_irq_enable(); + fec_irq_enable(0, 5, 1); + + enable_pci_interrupts(); + init_pci(); + + video_init(); + + /* initialize USB devices */ + // init_usb(); + + set_ipl(7); /* disable interrupts */ + + /* + * start FireTOS if DIP switch is set accordingly + */ + if (!(DIP_SWITCH & (1 << 6))) + { + extern uint8_t _FIRETOS[]; +#define FIRETOS ((uint32_t)_FIRETOS) /* where FireTOS is stored in flash */ + + /* make sure MMU is disabled */ + MCF_MMU_MMUCR = 0; /* MMU off */ + NOP(); /* force pipeline sync */ + + + /* ST RAM */ + + * (uint32_t *) 0x42e = STRAM_END; /* phystop TOS system variable */ + * (uint32_t *) 0x420 = 0x752019f3; /* memvalid TOS system variable */ + * (uint32_t *) 0x43a = 0x237698aa; /* memval2 TOS system variable */ + * (uint32_t *) 0x51a = 0x5555aaaa; /* memval3 TOS system variable */ + + /* TT-RAM */ + + * (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */ + * (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */ + + xprintf("call FireTOS\r\n"); + /* Jump into FireTOS */ + + void_func* FireTOS = (void_func*) FIRETOS; + FireTOS(); // Should never return + } + + /* + * fix initial pc/sp in ST RAM for FreeMiNT. It expects valid values there + * like on original STs (where these values reside in ROM) and uses them on + * CTRL-ALT-DELETE reboots. + */ + fix_stram_header(); + + xprintf("call EmuTOS\r\n"); + struct rom_header *os_header = (struct rom_header *) TOS; + os_header->initial_pc(); +} diff --git a/sys/cache.c b/sys/cache.c new file mode 100644 index 0000000..62cd565 --- /dev/null +++ b/sys/cache.c @@ -0,0 +1,241 @@ +/* + * cache handling + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Copyright 2010 - 2012 F. Aschwanden + * Copyright 2011 - 2012 V. Riviere + * Copyright 2012 M. Froeschle + * + */ + +#include "cache.h" + +void cacr_set(uint32_t value) +{ + extern uint32_t rt_cacr; + + rt_cacr = value; + __asm__ __volatile__( + " movec %0, cacr\n\t" + : /* output */ + : "r" (rt_cacr) + : "memory" /* clobbers */); +} + +uint32_t cacr_get(void) +{ + extern uint32_t rt_cacr; + + return rt_cacr; +} + +void disable_data_cache(void) +{ + flush_and_invalidate_caches(); + cacr_set((cacr_get() | CF_CACR_DCINVA) & ~CF_CACR_DEC); +} + +void disable_instruction_cache(void) +{ + flush_and_invalidate_caches(); + cacr_set((cacr_get() | CF_CACR_ICINVA) & ~CF_CACR_IEC); +} + +void enable_data_cache(void) +{ + cacr_set(cacr_get() & ~CF_CACR_DCINVA); +} + +void flush_and_invalidate_caches(void) +{ + __asm__ __volatile__( + " clr.l d0 \n\t" + " clr.l d1 \n\t" + " move.l d0,a0 \n\t" + "cfa_setloop%=: \n\t" + " cpushl bc,(a0) | flush\n\t" + " lea 0x10(a0),a0 | index+1\n\t" + " addq.l #1,d1 | index+1\n\t" + " cmpi.w #512,d1 | all sets?\n\t" + " bne.s cfa_setloop%= | no->\n\t" + " clr.l d1 \n\t" + " addq.l #1,d0 \n\t" + " move.l d0,a0 \n\t" + " cmpi.w #4,d0 | all ways?\n\t" + " bne.s cfa_setloop%= | no->\n\t" + /* input */ : + /* output */ : + /* clobber */ : "cc", "d0", "d1", "a0" + ); +} + +/* + * flush and invalidate a specific memory region from the instruction cache + */ +void flush_icache_range(void *address, size_t size) +{ + uint32_t set; + uint32_t start_set; + uint32_t end_set; + void *endaddr = address + size; + + start_set = (uint32_t) address & _ICACHE_SET_MASK; + end_set = (uint32_t) endaddr & _ICACHE_SET_MASK; + + if (start_set > end_set) { + /* from the begining to the lowest address */ + for (set = 0; set <= end_set; set += (0x10 - 3)) + { + __asm__ __volatile__( + " cpushl ic,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl ic,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl ic,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl ic,(%[set]) \n\t" + : /* output parameters */ + : [set] "a" (set) /* input parameters */ + : "cc" /* clobbered registers */ + ); + } + /* next loop will finish the cache ie pass the hole */ + end_set = LAST_ICACHE_ADDR; + } + for (set = start_set; set <= end_set; set += (0x10 - 3)) { + __asm__ __volatile__( + " cpushl ic,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl ic,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl ic,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl ic,(%[set])" + : /* output parameters */ + : [set] "a" (set) + : "cc" + ); + } +} + + + +/* + * flush and invalidate a specific region from the data cache + */ +void flush_dcache_range(void *address, size_t size) +{ + unsigned long set; + unsigned long start_set; + unsigned long end_set; + void *endaddr; + + endaddr = address + size; + start_set = (uint32_t) address & _DCACHE_SET_MASK; + end_set = (uint32_t) endaddr & _DCACHE_SET_MASK; + + if (start_set > end_set) { + /* from the begining to the lowest address */ + for (set = 0; set <= end_set; set += (0x10 - 3)) + { + __asm__ __volatile__( + " cpushl dc,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl dc,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl dc,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl dc,(%[set]) \n\t" + : /* output parameters */ + : [set] "a" (set) + : "cc" /* clobbered registers */ + ); + } + /* next loop will finish the cache ie pass the hole */ + end_set = LAST_DCACHE_ADDR; + } + for (set = start_set; set <= end_set; set += (0x10 - 3)) + { + __asm__ __volatile__( + " cpushl dc,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl dc,(%[set]) \n\t" + " addq%.l #1,%[set] \n\t" + " cpushl dc,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl dc,(%[set]) \n\t" + : /* output parameters */ + : [set] "a" (set) + : "cc" /* clobbered registers */ + ); + } +} + + +/* + * flush and invalidate a specific region from the both caches. We do not know if the area is cached + * at all, we do not know in which of the four ways it is cached, but we know the index where they + * would be cached if they are, so we only need to flush and invalidate only a subset of the 512 index + * entries, but all four ways. + */ +void flush_cache_range(void *address, size_t size) +{ + unsigned long set; + unsigned long start_set; + unsigned long end_set; + void *endaddr; + + endaddr = address + size; + start_set = (uint32_t) address & _DCACHE_SET_MASK; + end_set = (uint32_t) endaddr & _DCACHE_SET_MASK; + + if (start_set > end_set) { + /* from the begining to the lowest address */ + for (set = 0; set <= end_set; set += (0x10 - 3)) + { + __asm__ __volatile__( + " cpushl bc,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl bc,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl bc,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl bc,(%[set]) \n\t" + : /* output parameters */ + : [set] "a" (set) + : "cc" /* clobbered registers */ + ); + } + /* next loop will finish the cache ie pass the hole */ + end_set = LAST_DCACHE_ADDR; + } + for (set = start_set; set <= end_set; set += (0x10 - 3)) + { + __asm__ __volatile__( + " cpushl bc,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl bc,(%[set]) \n\t" + " addq%.l #1,%[set] \n\t" + " cpushl bc,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl bc,(%[set]) \n\t" + : /* output parameters */ + : [set] "a" (set) + : "cc" /* clobbered registers */ + ); + } +} diff --git a/sys/driver_mem.c b/sys/driver_mem.c new file mode 100644 index 0000000..79e6d01 --- /dev/null +++ b/sys/driver_mem.c @@ -0,0 +1,338 @@ +/* + * driver_mem.c + * + * based from Emutos / BDOS + * + * Copyright (c) 2001 Lineo, Inc. + * + * Authors: Karl T. Braun, Martin Doering, Laurent Vogel + * + * This file is distributed under the GPL, version 2 or at your + * option any later version. + */ + + +#include +#include "bas_string.h" +#include "bas_printf.h" +#include "usb.h" +#include "exceptions.h" /* set_ipl() */ + +#if defined(MACHINE_FIREBEE) +#include "firebee.h" +#elif defined(MACHINE_M5484LITE) +#include "m5484l.h" +#elif defined(MACHINE_M54455) +#include "m54455.h" +#else +#error "unknown machine!" +#endif + +// #define DEBUG +#include "debug.h" + +extern long offscren_reserved(void); + +extern uint8_t driver_mem_buffer[DRIVER_MEM_BUFFER_SIZE]; /* defined in linker control file */ + +/* MD - Memory Descriptor */ + +#define MD struct _md_ + +MD +{ + MD *m_link; + long m_start; + long m_length; + void *m_own; +}; + +/* MPB - Memory Partition Block */ + +#define MPB struct _mpb + +MPB +{ + MD *mp_mfl; + MD *mp_mal; + MD *mp_rover; +}; + +#define MAXMD 256 + +static MD tab_md[MAXMD]; +static MPB pmd; + +static void *xmgetblk(void) +{ + int i; + + for (i = 0; i < MAXMD; i++) + { + if (tab_md[i].m_own == NULL) + { + tab_md[i].m_own = (void*)1L; + return(&tab_md[i]); + } + } + return NULL; +} + +static void xmfreblk(void *m) +{ + int i = (int)(((long) m - (long) tab_md) / sizeof(MD)); + if ((i > 0) && (i < MAXMD)) + { + tab_md[i].m_own = NULL; + } +} + +static MD *ffit(long amount, MPB *mp) +{ + MD *p, *q, *p1; /* free list is composed of MD's */ + int maxflg; + long maxval; + + if (amount != -1) + { + amount += 15; /* 16 bytes alignment */ + amount &= 0xFFFFFFF0; + } + + if ((q = mp->mp_rover) == 0) /* get rotating pointer */ + { + return 0; + } + + maxval = 0; + maxflg = ((amount == -1) ? true : false) ; + p = q->m_link; /* start with next MD */ + do /* search the list for an MD with enough space */ + { + if (p == 0) + { + /* at end of list, wrap back to start */ + q = (MD *) &mp->mp_mfl; /* q => mfl field */ + p = q->m_link; /* p => 1st MD */ + } + if ((!maxflg) && (p->m_length >= amount)) + { + /* big enough */ + if (p->m_length == amount) + { + q->m_link = p->m_link; /* take the whole thing */ + } + else + { + /* + * break it up - 1st allocate a new + * MD to describe the remainder + */ + p1 = xmgetblk(); + if (p1 == NULL) + { + return(NULL); + } + + /* init new MD */ + p1->m_length = p->m_length - amount; + p1->m_start = p->m_start + amount; + p1->m_link = p->m_link; + p->m_length = amount; /* adjust allocated block */ + q->m_link = p1; + } + /* link allocate block into allocated list, + mark owner of block, & adjust rover */ + p->m_link = mp->mp_mal; + mp->mp_mal = p; + mp->mp_rover = (q == (MD *) &mp->mp_mfl ? q->m_link : q); + return(p); /* got some */ + } + else if (p->m_length > maxval) + maxval = p->m_length; + p = ( q=p )->m_link; + } while(q != mp->mp_rover); + + /* + * return either the max, or 0 (error) + */ + if (maxflg) + { + maxval -= 15; /* 16 bytes alignment */ + if (maxval < 0) + { + maxval = 0; + } + else + { + maxval &= 0xFFFFFFF0; + } + } + return(maxflg ? (MD *) maxval : 0); +} + +static void freeit(MD *m, MPB *mp) +{ + MD *p, *q; + + q = 0; + for (p = mp->mp_mfl; p ; p = (q = p) -> m_link) + { + if (m->m_start <= p->m_start) + { + break; + } + } + m->m_link = p; + + if (q) + { + q->m_link = m; + } + else + { + mp->mp_mfl = m; + } + + if (!mp->mp_rover) + { + mp->mp_rover = m; + } + + if (p) + { + if (m->m_start + m->m_length == p->m_start) + { + /* join to higher neighbor */ + m->m_length += p->m_length; + m->m_link = p->m_link; + if (p == mp->mp_rover) + { + mp->mp_rover = m; + } + xmfreblk(p); + } + } + if (q) + { + if (q->m_start + q->m_length == m->m_start) + { + /* join to lower neighbor */ + q->m_length += m->m_length; + q->m_link = m->m_link; + if (m == mp->mp_rover) + { + mp->mp_rover = q; + } + xmfreblk(m); + } + } +} + +int32_t driver_mem_free(void *addr) +{ + int level; + MD *p, **q; + MPB *mpb; + mpb = &pmd; + level = set_ipl(7); + + for(p = *(q = &mpb->mp_mal); p; p = *(q = &p->m_link)) + { + if ((long) addr == p->m_start) + { + break; + } + } + + if (!p) + { + set_ipl(level); + return(-1); + } + + *q = p->m_link; + freeit(p, mpb); + set_ipl(level); + + dbg("addr=0x%08X)\r\n", addr); + + return(0); +} + +void *driver_mem_alloc(uint32_t amount) +{ + void *ret = NULL; + int level; + MD *m; + + if (amount == -1L) + { + return (void *) ffit(-1L, &pmd); + } + + if (amount <= 0 ) + { + return(0); + } + + if ((amount & 1)) + { + amount++; + } + + level = set_ipl(7); + m = ffit(amount, &pmd); + + if (m != NULL) + { + ret = (void *) m->m_start; + } + set_ipl(level); + dbg("alloc(%d) = 0x%08X\r\n", amount, ret); + + return ret; +} + +static int use_count = 0; + +int driver_mem_init(void) +{ + if (use_count == 0) + { + dbg("initialise driver_mem_buffer[] at %p, size 0x%x\r\n", driver_mem_buffer, DRIVER_MEM_BUFFER_SIZE); + memset(driver_mem_buffer, 0, DRIVER_MEM_BUFFER_SIZE); + + pmd.mp_mfl = pmd.mp_rover = &tab_md[0]; + tab_md[0].m_link = (MD *) NULL; + tab_md[0].m_start = ((long) driver_mem_buffer + 15) & ~15; + tab_md[0].m_length = DRIVER_MEM_BUFFER_SIZE; + tab_md[0].m_own = (void *) 1L; + pmd.mp_mal = (MD *) NULL; + memset(driver_mem_buffer, 0, tab_md[0].m_length); + + dbg("uncached driver memory buffer at 0x%08X size %d\r\n", tab_md[0].m_start, tab_md[0].m_length); + } + use_count++; + dbg("driver_mem now has a use count of %d\r\n", use_count); + + return 0; +} + +void driver_mem_release(void) +{ + if (use_count-- == 0) + { +#ifndef CONFIG_USB_MEM_NO_CACHE +#ifdef USE_RADEON_MEMORY + if (driver_mem_buffer == (void *) offscren_reserved()) + return; + +#endif +#endif + } + dbg("driver_mem use count now %d\r\n", use_count); +} + + + diff --git a/sys/exceptions.S b/sys/exceptions.S new file mode 100644 index 0000000..0c8aded --- /dev/null +++ b/sys/exceptions.S @@ -0,0 +1,608 @@ +/* + * initialize exception vectors + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 26.02.2013 + * Author: Markus Fröschle + */ + +#include "startcf.h" +#if defined(MACHINE_FIREBEE) +#include "firebee.h" +#elif defined(MACHINE_M5484LITE) +#include "m5484l.h" +#endif /* MACHINE_FIREBEE */ + + .extern __SUP_SP + .extern _rom_entry + .extern __RAMBAR0 + .extern _rt_mod + .extern _rt_ssp + .extern _rt_usp + .extern _rt_vbr + .extern _mmutr_miss + .extern __MBAR + .extern __MMUBAR + .extern _video_tlb + .extern _video_sbt + .extern _flush_and_invalidate_caches + .extern _get_bas_drivers + + /* PCI interrupt handlers */ + .extern _irq5_handler + .extern _irq6_handler + .extern _irq7_handler + + .global _vec_init + .global _std_exc_vec /* needed by driver_vec.c */ + +/* Register read/write equates */ + + /* MMU */ + .equ MCF_MMU_MMUCR, __MMUBAR + .equ MCF_MMU_MMUOR, __MMUBAR+0x04 + .equ MCF_MMU_MMUSR, __MMUBAR+0x08 + .equ MCF_MMU_MMUAR, __MMUBAR+0x10 + .equ MCF_MMU_MMUTR, __MMUBAR+0x14 + .equ MCF_MMU_MMUDR, __MMUBAR+0x18 + + /* EPORT flag register */ + .equ MCF_EPORT_EPFR, __MBAR+0xf0c + + /* FEC1 port output data direction register */ + .equ MCF_GPIO_PODR_FEC1L, __MBAR+0xa07 + + /* PSC0 transmit buffer register */ + .equ MCF_PSC0_PSCTB_8BIT, __MBAR+0x860c + + /* GPT mode select register */ + .equ MCF_GPT0_GMS, __MBAR+0x800 + + /* Slice timer 0 count register */ + .equ MCF_SLT0_SCNT, __MBAR+0x908 + + // interrupt sources + .equ INT_SOURCE_EPORT_EPF1,1 // edge port flag 1 + .equ INT_SOURCE_EPORT_EPF2,2 // edge port flag 2 + .equ INT_SOURCE_EPORT_EPF3,3 // edge port flag 3 + .equ INT_SOURCE_EPORT_EPF4,4 // edge port flag 4 + .equ INT_SOURCE_EPORT_EPF5,5 // edge port flag 5 + .equ INT_SOURCE_EPORT_EPF6,6 // edge port flag 6 + .equ INT_SOURCE_EPORT_EPF7,7 // edge port flag 7 + .equ INT_SOURCE_USB_EP0ISR,15 // USB endpoint 0 interrupt + .equ INT_SOURCE_USB_EP1ISR,16 // USB endpoint 1 interrupt + .equ INT_SOURCE_USB_EP2ISR,17 // USB endpoint 2 interrupt + .equ INT_SOURCE_USB_EP3ISR,18 // USB endpoint 3 interrupt + .equ INT_SOURCE_USB_EP4ISR,19 // USB endpoint 4 interrupt + .equ INT_SOURCE_USB_EP5ISR,20 // USB endpoint 5 interrupt + .equ INT_SOURCE_USB_EP6ISR,21 // USB endpoint 6 interrupt + .equ INT_SOURCE_USB_USBISR,22 // USB general interrupt + .equ INT_SOURCE_USB_USBAISR,23 // USB core interrupt + .equ INT_SOURCE_USB_ANY,24 // OR of all USB interrupts + .equ INT_SOURCE_USB_DSPI_OVF,25 // DSPI overflow or underflow + .equ INT_SOURCE_USB_DSPI_RFOF,26 // receive FIFO overflow interrupt + .equ INT_SOURCE_USB_DSPI_RFDF,27 // receive FIFO drain interrupt + .equ INT_SOURCE_USB_DSPI_TFUF,28 // transmit FIFO underflow interrupt + .equ INT_SOURCE_USB_DSPI_TCF,29 // transfer complete interrupt + .equ INT_SOURCE_USB_DSPI_TFFF,30 // transfer FIFO fill interrupt + .equ INT_SOURCE_USB_DSPI_EOQF,31 // end of queue interrupt + .equ INT_SOURCE_PSC3,32 // PSC3 interrupt + .equ INT_SOURCE_PSC2,33 // PSC2 interrupt + .equ INT_SOURCE_PSC1,34 // PSC1 interrupt + .equ INT_SOURCE_PSC0,35 // PSC0 interrupt + .equ INT_SOURCE_CTIMERS,36 // combined source for comm timers + .equ INT_SOURCE_SEC,37 // SEC interrupt + .equ INT_SOURCE_FEC1,38 // FEC1 interrupt + .equ INT_SOURCE_FEC0,39 // FEC0 interrupt + .equ INT_SOURCE_I2C,40 // I2C interrupt + .equ INT_SOURCE_PCIARB,41 // PCI arbiter interrupt + .equ INT_SOURCE_CBPCI,42 // COMM bus PCI interrupt + .equ INT_SOURCE_XLBPCI,43 // XLB PCI interrupt + .equ INT_SOURCE_XLBARB,47 // XLBARB interrupt + .equ INT_SOURCE_DMA,48 // multichannel DMA interrupt + .equ INT_SOURCE_CAN0_ERROR,49 // FlexCAN error interrupt + .equ INT_SOURCE_CAN0_BUSOFF,50 // FlexCAN bus off interrupt + .equ INT_SOURCE_CAN0_MBOR,51 // message buffer ORed interrupt + .equ INT_SOURCE_SLT1,53 // slice timer 1 interrupt + .equ INT_SOURCE_SLT0,54 // slice timer 0 interrupt + .equ INT_SOURCE_CAN1_ERROR,55 // FlexCAN error interrupt + .equ INT_SOURCE_CAN1_BUSOFF,56 // FlexCAN bus off interrupt + .equ INT_SOURCE_CAN1_MBOR,57 // message buffer ORed interrupt + .equ INT_SOURCE_GPT3,59 // GPT3 timer interrupt + .equ INT_SOURCE_GPT2,60 // GPT2 timer interrupt + .equ INT_SOURCE_GPT1,61 // GPT1 timer interrupt + .equ INT_SOURCE_GPT0,62 // GPT0 timer interrupt + +// Atari register equates (provided by FPGA) + .equ vbasehi, 0xffff8201 + +/* + * macros + */ + +/* + * used for "forwarding" interrupt handlers. This just clears the "pending interrupt" + * flag from the EDGE PORT flag register, set the status register to the appropriate interrupt + * mask an jump through the corresponging vector + */ + .macro irq vector,int_mask,clr_int + move.w #0x2700,sr // disable interrupts + subq.l #8,sp + movem.l d0/a5,(sp) // save registers + + lea MCF_EPORT_EPFR,a5 + move.b #\clr_int,(a5) // clear int pending + + movem.l (sp),d0/a5 // restore registers + addq.l #8,sp + move.l \vector,-(sp) + move #0x2\int_mask\()00,sr + rts + .endm + + .text +_vec_init: + move.l a2,-(sp) // Backup registers + + mov3q.l #-1,_rt_mod // rt_mod auf super + clr.l _rt_ssp + clr.l _rt_usp + clr.l _rt_vbr + move.l #__RAMBAR0,d0 // exception vectors reside in rambar0 + movec d0,VBR + move.l d0,a0 + move.l a0,a2 + +/* + * first, set standard vector for all exceptions + */ +init_vec: + move.l #256,d0 + lea std_exc_vec(pc),a1 // standard vector +init_vec_loop: + move.l a1,(a2)+ // set standard vector for all exceptions + subq.l #1,d0 + bne init_vec_loop + +// set individual interrupt handler assignments + + move.l #__SUP_SP,(a0) // set initial stack pointer at start of exception vector table + + lea reset_vector(pc),a1 // set reset vector + move.l a1,0x04(a0) + + lea access(pc),a1 // set illegal access exception handler + move.l a1,0x08(a0) + +// install spurious interrupt handler + lea _lowlevel_isr_handler,a1 + move.l a1,0x60(a0) + +// trap #0 (without any parameters for now) is used to provide BaS' driver addresses to the OS + lea _get_bas_drivers(pc),a1 + move.l a1,0x80(a0) // trap #0 exception vector + +// MFP non-autovector interrupt handlers. Those are just rerouted to their autovector counterparts + + lea irq1(pc),a1 + move.l a1,0x104(a0) + + lea irq2(pc),a1 + move.l a1,0x108(a0) + + lea irq3(pc),a1 + move.l a1,0x10c(a0) + + lea irq4(pc),a1 + move.l a1,0x110(a0) + + lea irq5(pc),a1 + move.l a1,0x114(a0) + + lea irq6(pc),a1 + move.l a1,0x118(a0) + + lea irq7(pc),a1 + move.l a1,0x11c(a0) + + + +// install lowlevel_isr_handler for the three GPT timers + lea _lowlevel_isr_handler(pc),a1 + move.l a1,(INT_SOURCE_GPT1 + 64) * 4(a0) + move.l a1,(INT_SOURCE_GPT2 + 64) * 4(a0) + move.l a1,(INT_SOURCE_GPT3 + 64) * 4(a0) + +// install lowlevel_isr_handler for the PSC3 interrupt + move.l a1,(INT_SOURCE_PSC3 + 64) * 4(a0) + +// install lowlevel_isr_handler for Coldfire DMA interrupts + move.l a1,(INT_SOURCE_DMA + 64) * 4(a0) + +// install lowlevel_isr_handler for the XLBPCI interrupt + move.l a1,(INT_SOURCE_XLBPCI + 64) * 4(a0) + +// install lowlevel_isr_handler for the XLBARB interrupt +// move.l a1,(INT_SOURCE_XLBARB + 64) * 4(a0) // FIXME: commented out for testing + +// install lowlevel_isr_handler for the FEC0 interrupt + move.l a1,(INT_SOURCE_FEC0 + 64) * 4(a0) + +#ifndef MACHINE_FIREBEE +// FEC1 not wired on the FireBee (used for FPGA as GPIO), but available on other machines + move.l a1,(INT_SOURCE_FEC1 + 64) * 4(a0) +#endif + +#ifdef MACHINE_FIREBEE + +// timer vectors (triggers when vbashi gets changed, used for video page copy) + // move.l a1,(INT_SOURCE_GPT0 + 64) * 4(a0) +#endif /* MACHINE_FIREBEE */ + + move.l (sp)+,a2 // Restore registers + rts + + +/* + * exception vector routines + */ +vector_table_start: +std_exc_vec: +_std_exc_vec: + move.w #0x2700,sr // disable interrupt + subq.l #8,sp + movem.l d0/a5,(sp) // save registers + move.w 8(sp),d0 // fetch vector + and.l #0x3fc,d0 // mask out vector number +// #define DBG_EXC +#ifdef DBG_EXC + // printout vector number of exception + + lea -4 * 4(sp),sp // reserve stack space + movem.l d0-d1/a0-a1,(sp) // save gcc scratch registers + + lsr.l #2,d0 // shift vector number in place + cmp.l #33,d0 + beq noprint + cmp.l #34,d0 + beq noprint + cmp.l #45,d0 + beq noprint + cmp.l #46,d0 + beq noprint + move.l 4 * 4 + 8 + 4(sp),-(sp) // pc at exception + move.l d0,-(sp) // provide it to xprintf() + pea exception_text + jsr _xprintf // call xprintf() + add.l #3*4,sp // adjust stack +noprint: + + movem.l (sp),d0-d1/a0-a1 // restore registers + lea 4 * 4(sp),sp +#endif /* DBG_EXC */ + + add.l _rt_vbr,d0 // + VBR + move.l d0,a5 + move.l (a5),d0 // fetch exception routine address + + move.l 4(sp),a5 // restore a5 + move.l d0,4(sp) // store exception routine address + + move.w 10(sp),d0 // restore original SR (irq mask) + bset #13,d0 // set supervisor bit + move.w d0,sr // + move.l (sp)+,d0 // restore d0 + rts // jump to exception handler + +exception_text: + .ascii "DEBUG: EXCEPTION %d caught at %p" + .byte 13, 10, 0 + .align 4 + +reset_vector: + move.w #0x2700,sr // disable interrupts + move.l #0x31415926,d0 + cmp.l 0x426,d0 // _resvalid: reset vector valid? + beq std_exc_vec // yes-> + jmp _rom_entry // no, cold start machine + +access: + move.w #0x2700,sr // disable interrupts + + link a6,#-4 * 4 // make room for gcc scratch registers + movem.l d0-d1/a0-a1,(sp) // save them + + move.l 4(a6),-(sp) // push format_status + move.l 8(a6),-(sp) // pc at exception + move.l MCF_MMU_MMUAR,-(sp) // MMU fault address + move.l MCF_MMU_MMUSR,-(sp) // MMU status register + // probably doesn't make sense since we still have a potential unmapped MMU page + // move.w #0x2300,sr // can lower interrupt mask now that MMU status is safe + jsr _mmutr_miss // call C routine + lea 4 * 4(sp),sp // adjust stack + + tst.l d0 // exception handler signals bus error + bne bus_error + + movem.l (sp),d0-d1/a0-a1 // restore registers + unlk a6 + rte + +bus_error: + movem.l (sp),d0-d1/a0-a1 // restore registers + unlk a6 + move.l 0x08,-(sp) + rts + // bra std_exc_vec // FIXME: this seems to be bogous... + +zero_divide: + move.w #0x2700,sr // disable interrupt + move.l a0,-(sp) + move.l d0,-(sp) + move.l 12(sp),a0 // pc + move.w (a0)+,d0 // command word + btst #7,d0 // long? + beq zd_word // no-> + addq.l #2,a0 + +zd_word: + and.l 0x3f,d0 // mask out ea field + cmp.w #0x08,d0 // -(ax) or less? + ble zd_end + addq.l #2,a0 + cmp.w #0x39,d0 // xxx.L + bne zd_nal + addq.l #2,a0 + bra zd_end + +zd_nal: cmp.w #0x3c,d0 // immediate? + bne zd_end // no-> + btst #7,d0 // long? + beq zd_end // no + addq.l #2,a0 +zd_end: + move.l a0,12(sp) + move.l (sp)+,d0 + move.l (sp)+,a0 + rte + +#ifdef _NOT_USED_ +linea: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +linef: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +format: + move.w #0x2700,sr // disable interrupt + halt + nop + nop + +//floating point +flpoow: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +#endif /* _NOT_USED */ + + +irq1: irq 0x64, 1, 0x02 // Level 1 autovector interrupt (unused) +irq2: irq 0x68, 2, 0x04 // Level 2 autovector interrupt (horizontal blank) +irq3: irq 0x6c, 3, 0x08 // Level 3 autovector interrupt (unused) +irq4: irq 0x70, 4, 0x10 // Level 4 autovector interrupt (vertical blank) + + + +#if defined(MACHINE_FIREBEE) // these handlers are only meaningful for the Firebee +irq5: //move.w #0x2700,sr // disable interrupts + subq.l #4,sp // extra space + + link a6,#-4 * 4 // save gcc scratch registers + movem.l d0-d1/a0-a1,(sp) + + jsr _irq5_handler // call C handler routine + + tst.b d0 // handled? + beq irq5_forward + + movem.l (sp),d0-d1/a0-a1 // restore registers + unlk a6 + addq.l #4,sp + + rte // return from exception + +irq5_forward: move.l 0x74,a0 // fetch OS irq5 vector + add.l _rt_vbr,a0 // add runtime vbr + move.l a0,4(a6) // put on stack + + movem.l (sp),d0-d1/a0-a1 // restore registers + unlk a6 // + move.w #0x2500,sr // set interrupt level + rts // jump through vector + +/* + * irq6 needs special treatment since - because the Coldfire only supports autovector interrupts + * - the exception vector is provided by the simulated MFP from the FPGA + */ +irq6: move.w #0x2700,sr // disable interrupt + subq.l #4,sp // extra space + + link a6,#-4 * 4 // save gcc scratch registers + movem.l d0-d1/a0-a1,(sp) + + move.l 8(a6),-(sp) // format status word + move.l 12(a6),-(sp) // pc at exception + jsr _irq6_handler // call C handler + lea 8(sp),sp // fix stack + + tst.b d0 // interrupt handled? + beq irq6_forward // no, forward to TOS + + movem.l (sp),d0-d1/a0-a1 // restore registers + unlk a6 + addq.l #4,sp // "extra space" not needed in this case + rte + +irq6_forward: + move.l 0xf0020000,a0 // fetch "MFP interrupt vector" from FPGA + add.l _rt_vbr,a0 // add runtime VBR + move.l (a0),4(a6) // fetch handler address and put it on "extra space" + + movem.l (sp),d0-d1/a0-a1 + unlk a6 + move.w #0x2600,sr // set interrupt mask to MFP level + + rts // jump through vector + +/* + * irq 7 = pseudo bus error + */ +irq7: + lea -12(sp),sp + movem.l d0/a0,(sp) + + move.l __RAMBAR0+0x008,a0 // real access error handler + move.l a0,8(sp) // this will be the return address for rts + + move.w 12(sp),d0 // format/vector word + andi.l #0xf000,d0 // keep only the format + ori.l #2*4,d0 // simulate vector #2, no fault + move.w d0,12(sp) + + // TODO: Inside an interrupt handler, 16(sp) is the return address. + // For an Access Error, it should be the address of the fault instruction instead + + lea MCF_EPORT_EPFR,a0 + bset #7,(a0) // clear int 7 + + move.l (sp)+,d0 // restore registers + move.l (sp)+,a0 + rts // Forward to the Access Error handler + +#else // handlers for M5484LITE + +irq5: + move.w #0x2700,sr // disable interrupts + subq.l #4,sp // extra space + + link a6,#-4 * 4 // save gcc scratch registers + movem.l d0-d1/a0-a1,(sp) + + jsr _irq5_handler // call C handler routine + + tst.b d0 // handled? + beq irq5_forward + + movem.l (sp),d0-d1/a0-a1 // restore registers + unlk a6 + addq.l #4,sp + + rte // return from exception + +irq5_forward: + move.l 0x74,a0 // fetch OS irq5 vector + add.l _rt_vbr,a0 // add runtime vbr + move.l a0,4(a6) // put on stack + + movem.l (sp),d0-d1/a0-a1 // restore registers + unlk a6 // + move.w #0x2500,sr // set interrupt level + rts // jump through vector + +irq6: + irq 0x74,5,0x20 + +irq7: // irq7 is tied to PCI INTA# and PCI INTB# on the M5484LITE + + move.w #0x2700,sr // disable interrupts + + lea -4*4(sp),sp // save gcc scratch registers + movem.l d0-d1/a0-a1,(sp) + + jsr _irq7_handler // call C handler routine + + movem.l (sp),d0-d1/a0-a1 // restore registers + lea 4 * 4(sp),sp + + rte // return from exception + +irq7text: + .data + .ascii "IRQ7!" + .byte 13,10,0 + .align 4 + .text +#endif /* MACHINE_FIREBEE */ + +/* + * low-level interrupt service routine for routines registered with + * isr_register_handler(int vector). If the higlevel routine (isr_execute_handler()) + * returns != true, the call is forwarded to the OS (through its own vector base). + */ + .global _lowlevel_isr_handler + .extern _isr_execute_handler + + +/* + * stack format (after link instruction) is like this: + * + * +12 program counter (return address) + * +8 format_status + * +4 save area for rts (if we need to jump through the OS vector) + * (a6) -> saved a6 (from link) + * -4 + * -8 + * -12 + * (sp) -> gcc scratch registers save area + */ +_lowlevel_isr_handler: + subq.l #4,sp // extra space + link a6,#-4 * 4 // make room for + movem.l d0-d1/a0-a1,(sp) // gcc scratch registers and save them, + // other registers will be taken care of by gcc itself + + move.w 8(a6),d0 // fetch vector number from stack + lsr.l #2,d0 // move it in place + andi.l #0xff,d0 // mask it out + move.l d0,-(sp) // push it + jsr _isr_execute_handler // call the C handler + addq.l #4,sp // adjust stack + tst.l d0 // handled? + beq lowlevel_forward // no, forward it to TOS + + movem.l (sp),d0-d1/a0-a1 // restore registers + unlk a6 + addq.l #4,sp // eliminate extra space + + rte + +lowlevel_forward: + move.l 8(a6),d0 // fetch OS irq vector + lsr.l #2,d0 // move it in place + andi.l #0xff,d0 // mask out vector number + add.l _rt_vbr,d0 // add runtime vbr + move.l d0,4(a6) // put on stack as return address + + movem.l (sp),d0-d1/a0-a1 // restore registers + unlk a6 // + rts // jump through vector diff --git a/sys/fault_vectors.c b/sys/fault_vectors.c new file mode 100644 index 0000000..c4ad5de --- /dev/null +++ b/sys/fault_vectors.c @@ -0,0 +1,235 @@ +/* + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * provide an early exception vector branch table to catch exceptions _before_ VBR has been setup eventually + * (to RAMBAR0, in exceptions.S) + */ + +#include "MCF5475.h" +#include "bas_types.h" +#include "bas_printf.h" + +typedef void (*exception_handler)(void); +extern exception_handler SDRAM_VECTOR_TABLE[]; + +/* + * decipher Coldfire exception stack frame and print it out in cleartext + */ +void fault_handler(uint32_t pc, uint32_t format_status) +{ + int format; + int fault_status; + int vector; + int sr; + + xprintf("\007\007exception! Processor halted.\r\n"); + xprintf("format_status: %lx\r\n", format_status); + xprintf("pc: %lx\r\n", pc); + + /* + * extract info from format-/status word + */ + format = (format_status & 0b11110000000000000000000000000000) >> 28; + fault_status = ((format_status & 0b00001100000000000000000000000000) >> 26) | + ((format_status & 0b00000000000000110000000000000000) >> 16); + vector = (format_status & 0b00000011111111000000000000000000) >> 18; + sr = (format_status & 0b00000000000000001111111111111111); + + xprintf("format: %x\r\n", format); + xprintf("fault_status: %x (", fault_status); + switch (fault_status) + { + case 0: + xprintf("not an access or address error nor an interrupted debug service routine"); + break; + + case 1: + case 3: + case 11: + xprintf("reserved"); + break; + + case 2: + xprintf("interrupt during a debug service routine for faults other than access errors"); + break; + + case 4: + xprintf("error (for example, protection fault) on instruction fetch"); + break; + + case 5: + xprintf("TLB miss on opword or instruction fetch"); + break; + + case 6: + xprintf("TLB miss on extension word of instruction fetch"); + break; + + case 7: + xprintf("IFP access error while executing in emulator mode"); + break; + + case 8: + xprintf("error on data write"); + break; + + case 9: + xprintf("error on attempted write to write-protected space"); + break; + + case 10: + xprintf("TLB miss on data write"); + break; + + case 12: + xprintf("error on data read"); + break; + + case 13: + xprintf("attempted read, read-modify-write of protected space"); + break; + + case 14: + xprintf("TLB miss on data read or read-modify-write"); + break; + + case 15: + xprintf("OEP access error while executing in emulator mode"); + } + xprintf(")\r\n"); + + xprintf("vector = %d (", vector); + switch (vector) + { + case 2: + xprintf("access error"); + break; + + case 3: + xprintf("address error"); + break; + + case 4: + xprintf("illegal instruction"); + break; + + case 5: + xprintf("divide by zero"); + break; + + case 8: + xprintf("privilege violation"); + break; + + case 9: + xprintf("trace"); + break; + + case 10: + xprintf("unimplemented line-a opcode"); + break; + + case 11: + xprintf("unimplemented line-f opcode"); + break; + + case 12: + xprintf("non-PC breakpoint debug interrupt"); + break; + + case 13: + xprintf("PC breakpoint debug interrupt"); + break; + + case 14: + xprintf("format error"); + break; + + case 24: + xprintf("spurious interrupt"); + break; + + default: + if ( ((vector >= 6) && (vector <= 7)) || + ((vector >= 16) && (vector <= 23))) + { + xprintf("reserved"); + } + else if ((vector >= 25) && (vector <= 31)) + { + xprintf("level %d autovectored interrupt", fault_status - 24); + } + else if ((vector >= 32) && (vector <= 47)) + { + xprintf("trap #%d", vector - 32); + } + else + { + xprintf("unknown vector\r\n"); + } + } + xprintf(")\r\n"); + xprintf("sr=%4x\r\n", sr); + + __asm__ __volatile__( + " move.w 0x2700,d0 \r\n" // disable interrupts + " move.w d0,sr \r\n" + " halt \r\n" // stop processor + : /* no output */ + : /* no input */ + : "memory"); +} + +void __attribute__((interrupt)) handler(void) +{ + /* + * Prepare exception stack contents so it can be handled by a C routine. + * + * For standard routines, we'd have to save registers here. + * Since we do not intend to return anyway, we just ignore that requirement. + */ + __asm__ __volatile__("move.l (sp),-(sp)\n\t"\ + "move.l 8(sp),-(sp)\n\t"\ + "bsr _fault_handler\n\t"\ + "halt\n\t"\ + : : : "memory"); +} + +void setup_vectors(void) +{ + int i; + + xprintf("\r\ninstall early exception vector table:"); + + for (i = 8; i < 256; i++) + { + SDRAM_VECTOR_TABLE[i] = &handler; + } + + /* + * make sure VBR points to our table + */ + __asm__ __volatile__("clr.l d0\n\t"\ + "movec.l d0,VBR\n\t"\ + "nop\n\t"\ + "move.l d0,_rt_vbr" + : /* outputs */ + : /* inputs */ + : "d0", "memory", "cc" /* clobbered registers */ + ); + + xprintf("finished.\r\n"); +} diff --git a/sys/init_fpga.c b/sys/init_fpga.c new file mode 100644 index 0000000..ec96545 --- /dev/null +++ b/sys/init_fpga.c @@ -0,0 +1,201 @@ +/* + * init_fpga.c + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Copyright 2010 - 2012 F. Aschwanden + * Copyright 2011 - 2012 V. Riviere + * Copyright 2012 M. Froeschle + * + */ + +#include "MCF5475.h" +#include "sysinit.h" +#include "bas_printf.h" +#include "wait.h" + +// #define FPGA_DEBUG +#if defined(FPGA_DEBUG) +#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0) +#else +#define dbg(format, arg...) do { ; } while (0) +#endif + +#define FPGA_STATUS (1 << 0) +#define FPGA_CLOCK (1 << 1) +#define FPGA_CONFIG (1 << 2) +#define FPGA_DATA0 (1 << 3) +#define FPGA_CONF_DONE (1 << 5) + +extern uint8_t _FPGA_CONFIG[]; +#define FPGA_FLASH_DATA &_FPGA_CONFIG[0] +extern uint8_t _FPGA_CONFIG_SIZE[]; +#define FPGA_FLASH_DATA_SIZE ((uint32_t) &_FPGA_CONFIG_SIZE[0]) + +/* + * flag located in processor SRAM1 that indicates that the FPGA configuration has + * been loaded through the onboard JTAG interface. + * init_fpga() will honour this and not overwrite config. + */ +extern uint32_t _FPGA_JTAG_LOADED; +extern uint32_t _FPGA_JTAG_VALID; +#define VALID_JTAG 0xaffeaffe + +void config_gpio_for_fpga_config(void) +{ +#if defined(MACHINE_FIREBEE) + /* + * Configure GPIO FEC1L port directions (needed to load FPGA configuration) + */ + MCF_GPIO_PDDR_FEC1L = 0 | /* bit 7 = input */ + 0 | /* bit 6 = input */ + 0 | /* bit 5 = input */ + MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 | /* bit 4 = LED => output */ + MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 | /* bit 3 = PRG_DQ0 => output */ + MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 | /* bit 2 = FPGA_CONFIG => output */ + MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 | /* bit 1 = PRG_CLK (FPGA) => output */ + 0; /* bit 0 => input */ +#endif /* MACHINE_FIREBEE */ +} + +void config_gpio_for_jtag_config(void) +{ + /* + * configure FEC1L port directions to enable external JTAG configuration download to FPGA + */ + MCF_GPIO_PDDR_FEC1L = 0 | + MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4; /* bit 4 = LED => output */ + /* all other bits = input */ + /* + * unfortunately, the GPIO module cannot trigger interrupts. That means CONF_DONE needs to be polled to detect + * external FPGA (re)configuration and reset the system in that case. Could be done from the OS as well... + */ +} + +/* + * load FPGA + */ +bool init_fpga(void) +{ + uint8_t *fpga_data; + volatile int32_t time, start, end; + int i; + + xprintf("FPGA load config...\r\n"); + xprintf("_FPGA_JTAG_LOADED = 0x%x\r\n", _FPGA_JTAG_LOADED); + xprintf("_FPGA_JTAG_VALID = 0x%x\r\n", _FPGA_JTAG_VALID); + if (_FPGA_JTAG_LOADED == 1 && _FPGA_JTAG_VALID == VALID_JTAG) + { + xprintf("detected _FPGA_JTAG_LOADED flag. FPGA config skipped.\r\n"); + + /* reset the flag so that next boot will load config again from flash */ + // _FPGA_JTAG_LOADED = 0; + // _FPGA_JTAG_VALID = 0; + + return true; + } + start = MCF_SLT0_SCNT; + + config_gpio_for_fpga_config(); + MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK; /* FPGA clock => low */ + + /* pulling FPGA_CONFIG to low resets the FPGA */ + MCF_GPIO_PODR_FEC1L &= ~FPGA_CONFIG; /* FPGA config => low */ + wait(10); /* give it some time to do its reset stuff */ + + while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS) && (MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); + + MCF_GPIO_PODR_FEC1L |= FPGA_CONFIG; /* pull FPGA_CONFIG high to start config cycle */ + while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS)) + ; /* wait until status becomes high */ + + /* + * excerpt from an Altera configuration manual: + * + * The low-to-high transition of nCONFIG on the FPGA begins the configuration cycle. The + * configuration cycle consists of 3 stages: reset, configuration, and initialization. + * While nCONFIG is low, the device is in reset. When the device comes out of reset, + * nCONFIG must be at a logic high level in order for the device to release the open-drain + * nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the FPGA + * is ready to receive configuration data. Before and during configuration, all user I/O pins + * are tri-stated. Stratix series, Arria series, and Cyclone series have weak pull-up resistors + * on the I/O pins which are on, before and during configuration. + * + * To begin configuration, nCONFIG and nSTATUS must be at a logic high level. You can delay + * configuration by holding the nCONFIG low. The device receives configuration data on its + * DATA0 pins. Configuration data is latched into the FPGA on the rising edge of DCLK. After + * the FPGA has received all configuration data successfully, it releases the CONF_DONE pin, + * which is pulled high by a pull-up resistor. A low to high transition on CONF_DONE indicates + * configuration is complete and initialization of the device can begin. + */ + + const uint8_t *fpga_flash_data_end = FPGA_FLASH_DATA + FPGA_FLASH_DATA_SIZE; + + fpga_data = (uint8_t *) FPGA_FLASH_DATA; + do + { + uint8_t value = *fpga_data++; + for (i = 0; i < 8; i++, value >>= 1) + { + + if (value & 1) + { + /* bit set -> toggle DATA0 to high */ + MCF_GPIO_PODR_FEC1L |= FPGA_DATA0; + } + else + { + /* bit is cleared -> toggle DATA0 to low */ + MCF_GPIO_PODR_FEC1L &= ~FPGA_DATA0; + } + /* toggle DCLK -> FPGA reads the bit */ + MCF_GPIO_PODR_FEC1L |= FPGA_CLOCK; + MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK; + } + } while ((!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)) && (fpga_data < fpga_flash_data_end)); + + if (fpga_data < fpga_flash_data_end) + { +#ifdef _NOT_USED_ + while (fpga_data++ < fpga_flash_data_end) + { + /* toggle a little more since it's fun ;) */ + MCF_GPIO_PODR_FEC1L |= FPGA_CLOCK; + MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK; + } +#endif /* _NOT_USED_ */ + end = MCF_SLT0_SCNT; + time = (start - end) / (SYSCLK / 1000) / 1000; + + xprintf("finished (took %f seconds).\r\n", time / 1000.0); + config_gpio_for_jtag_config(); + + /* + * assure skipping fpga load on warm boot + */ + + _FPGA_JTAG_LOADED = 1; + _FPGA_JTAG_VALID = VALID_JTAG; + + xprintf("SRAM now set to FPGA load skip\r\n"); + + return true; + } + xprintf("FAILED!\r\n"); + config_gpio_for_jtag_config(); + + return false; +} diff --git a/sys/interrupts.c b/sys/interrupts.c new file mode 100644 index 0000000..50e6680 --- /dev/null +++ b/sys/interrupts.c @@ -0,0 +1,685 @@ +/* + * Interrupts + * + * Handle interrupts, the levels. + * + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 26.02.2013 + * Author: Markus Fröschle + */ + +#include +#include "MCF5475.h" +#include "bas_utils.h" +#include "bas_printf.h" +#include "bas_string.h" +#include "exceptions.h" +#include "interrupts.h" +#include "bas_printf.h" +#include "startcf.h" +#include "cache.h" +#include "util.h" +#include "dma.h" +#include "pci.h" +#include + +// #define DEBUG +#include "debug.h" + +#ifndef MAX_ISR_ENTRY +#define MAX_ISR_ENTRY (20) +#endif + + +struct isrentry +{ + int vector; + bool (*handler)(void *, void *); + void *hdev; + void *harg; +}; + +static struct isrentry isrtab[MAX_ISR_ENTRY]; /* list of interrupt service routines */ + + +/* + * clear the table of interrupt service handlers + */ +void isr_init(void) +{ + memset(isrtab, 0, sizeof(isrtab)); +} + +bool isr_set_prio_and_level(int int_source, int priority, int level) +{ + if (int_source > 8 && int_source <= 62) + { + /* + * preset interrupt control registers with level and priority + */ + dbg("set MCF_INTC_ICR(%d) to priority %d, level %d\r\n", + int_source, priority, level); + MCF_INTC_ICR(int_source) = MCF_INTC_ICR_IP(priority) | + MCF_INTC_ICR_IL(level); + } + else if (int_source >= 1 && int_source <= 8) + { + dbg("interrrupt control register for vector %d is read only!\r\n"); + } + else + { + err("invalid vector - interrupt control register not set.\r\n"); + return false; + } + + return true; +} + +/* + * enable internal int source in interrupt controller + */ +bool isr_enable_int_source(int int_source) +{ + dbg("anding int_source %d, MCF_INTC_IMR%c = 0x%08x, now 0x%08x\r\n", + int_source, + int_source < 32 && int_source > 0 ? 'L' : + int_source >= 32 && int_source <= 62 ? 'H' : 'U', + int_source < 32 && int_source > 0 ? ~(1 << int_source) : + int_source >= 32 && int_source <= 62 ? ~(1 << (int_source - 32)) : 0, + MCF_INTC_IMRH); + + if (int_source < 32 && int_source > 0) + { + MCF_INTC_IMRL &= ~(1 << int_source); + } + else if (int_source >= 32 && int_source <= 62) + { + MCF_INTC_IMRH &= ~(1 << (int_source - 32)); + } + else + { + dbg("vector %d does not correspond to an internal interrupt source\r\n"); + return false; + } + + return true; +} + +/* + * This function places an interrupt handler in the ISR table, + * thereby registering it so that the low-level handler may call it. + * + * The two parameters are intended for the first arg to be a + * pointer to the device itself, and the second a pointer to a data + * structure used by the device driver for that particular device. + */ +bool isr_register_handler(int vector, int level, int priority, bool (*handler)(void *, void *), void *hdev, void *harg) +{ + int index; + int int_source; + + if ((vector <= 0) || (handler == NULL)) + { + dbg("illegal vector or handler (vector=%x, handler=%p)!\r\n", vector, handler); + + return false; + } + + for (index = 0; index < MAX_ISR_ENTRY; index++) + { + if (isrtab[index].vector == vector) + { + /* one cross each, only! */ + dbg("already set handler with this vector (%d, %d)\r\n", vector); + + return false; + } + + if (isrtab[index].vector == 0) + { + isrtab[index].vector = vector; + isrtab[index].handler = handler; + isrtab[index].hdev = hdev; + isrtab[index].harg = harg; + + int_source = vector - 64; + + if (int_source >= 0) + { + if (!isr_enable_int_source(int_source)) + { + dbg("failed to enable internal interrupt souce %d in IMRL/IMRH\r\n", int_source); + return false; + } + + if (!isr_set_prio_and_level(int_source, priority, level)) + { + dbg("failed to set priority and level for interrupt source %d\r\n", int_source); + return false; + } + } + return true; + } + } + dbg("no available slots to register handler for vector %d\n\r", vector); + + return false; /* no available slots */ +} + +void isr_remove_handler(bool (*handler)(void *, void *)) +{ + /* + * This routine removes from the ISR table all + * entries that matches 'handler'. + */ + int index; + + for (index = 0; index < MAX_ISR_ENTRY; index++) + { + if (isrtab[index].handler == handler) + { + memset(&isrtab[index], 0, sizeof(struct isrentry)); + + return; + } + } + dbg("no such handler registered (handler=%p\r\n", handler); +} + +#ifdef DEBUG +static char *vector_to_str[] = +{ + "initial stack pointer", /* 0 */ + "initial program counter", /* 1 */ + "access error", /* 2 */ + "address error", /* 3 */ + "illegal instruction", /* 4 */ + "divide by zero", /* 5 */ + "reserved6", /* 6 */ + "reserved7", /* 7 */ + "privilege violation", /* 8 */ + "trace", /* 9 */ + "unimplemented line-a opcode", /* 10 */ + "unimplemented line-f opcode", /* 11 */ + "non-PC breakpoint debug interrupt", /* 12 */ + "PC breakpoint debug interrupt", /* 13 */ + "format error", /* 14 */ + "uninitialized interrupt", /* 15 */ + "reserved16", + "reserved17", + "reserved18", + "reserved19", + "reserved20", + "reserved21", + "reserved22", + "reserved23", + "spurious interrupt", /* 24 */ + "level 1 autovector", /* 25 */ + "level 2 autovector", /* 26 */ + "level 3 autovector", /* 27 */ + "level 4 autovector", /* 28 */ + "level 5 autovector", /* 29 */ + "level 6 autovector", /* 30 */ + "level 7 autovector", /* 31 */ + "trap #0", /* 32 */ + "trap #1", /* 33 */ + "trap #2", /* 34 */ + "trap #3", /* 35 */ + "trap #4", /* 36 */ + "trap #5", /* 37 */ + "trap #6", /* 38 */ + "trap #7", /* 39 */ + "trap #8", /* 40 */ + "trap #9", /* 41 */ + "trap #10" /* 42 */ + "trap #11", /* 43 */ + "trap #12", /* 44 */ + "trap #13", /* 45 */ + "trap #14", /* 46 */ + "trap #15", /* 47 */ + "floating point branch on unordered condition", /* 48 */ + "floting point inexact result", /* 49 */ + "floating point divide by zero", /* 50 */ + "floating point underflow", /* 51 */ + "floating point operand error", /* 52 */ + "floating point overflow", /* 53 */ + "floating point NaN", /* 54 */ + "floating point denormalized number", /* 55 */ + "reserved56", /* 56 */ + "reserved57", + "reserved58", + "reserved59", + "reserved60", + "unsupported instruction", /* 61 */ + "reserved62", /* 62 */ + "reserved63", /* 63 */ + "", "", + "edge port 1", /* 1 */ + "edge port 2", /* 2 */ + "edge port 3", /* 3 */ + "edge port 4", /* 4 */ + "edge port 5", /* 5 */ + "edge port 6", /* 6 */ + "edge port 7", /* 7 */ + "unused8", + "unused9", + "unused10", + "unused11", + "unused12", + "unused13", + "unused14", + "USB endpoint 0", /* 15 */ + "USB endpoint 1", /* 16 */ + "USB endpoint 2", /* 17 */ + "USB endpoint 3", /* 18 */ + "USB endpoint 4", /* 19 */ + "USB endpoint 5", /* 20 */ + "USB endpoint 6", /* 21 */ + "USB general interrupt", /* 22 */ + "USB core interrupt", /* 23 */ + "USB OR interrupt", /* 24 */ + "DSPI over/underflow", /* 25 */ + "DSPI receive FIFO overflow", /* 26 */ + "DSPI receive FIFO drain", /* 27 */ + "DSPI transmit FIFO underflow", /* 28 */ + "DSPI transfer complete", /* 29 */ + "DSPI trasmit FIFO full", /* 30 */ + "DSPI end of queue", /* 31 */ + "PSC3", /* 32 */ + "PSC2", /* 33 */ + "PSC1", /* 34 */ + "PSC0", /* 35 */ + "Comm timer", /* 36 */ + "SEC", /* 37 */ + "FEC1", /* 38 */ + "FEC0", /* 39 */ + "I2C", /* 40 */ + "PCI arbiter", /* 41 */ + "comm bus PCI", /* 42 */ + "XLB PCI", /* 43 */ + "not used44", + "not used45", + "not used46", + "XLB arbiter to CPU", /* 47 */ + "multichannel DMA", /* 48 */ + "FlexCAN 0 error", /* 49 */ + "FlexCAN 0 bus off", /* 50 */ + "FlexCAN 0 message buffer", /* 51 */ + "not used52" + "slice timer 1", /* 53 */ + "slice timer 0", /* 54 */ + "FlexCAN 1 error", /* 55 */ + "FlexCAN 1 bus off", /* 56 */ + "FlexCAN 1 message buffer", /* 57 */ + "not used58", + "GPT3", /* 59 */ + "GPT2", /* 60 */ + "GPT1", /* 61 */ + "GPT0", /* 62 */ + "not used63" +}; +#endif /* DEBUG */ + +/* + * This routine searches the ISR table for an entry that matches + * 'vector'. If one is found, then 'handler' is executed. + * + * This routine returns either true or false where + * true = interrupt has been handled, return to caller + * false= interrupt has been handled or hasn't, but needs to be forwarded to TOS + */ +bool isr_execute_handler(int vector) +{ + int index; + + dbg("vector = %d (%s)\r\n", vector, vector_to_str[vector]); + + /* + * locate an interrupt service routine handler. + */ + for (index = 0; index < MAX_ISR_ENTRY; index++) + { + if (isrtab[index].vector == vector) + { + isrtab[index].handler(isrtab[index].hdev, isrtab[index].harg); + return true; + } + } + err("no isr handler for vector %d found. Spurious?\r\n", vector); + + return true; +} + +#if defined(MACHINE_FIREBEE) +/* + * PIC interrupt handler for Firebee + * + * Handles PIC requests that come in from PSC3 serial interface. Currently, that + * is RTC/NVRAM requests only + */ +bool pic_interrupt_handler(void *arg1, void *arg2) +{ + uint8_t rcv_byte; + + dbg("PIC interrupt\r\n"); + + rcv_byte = read_pic_byte(); + if (rcv_byte == 2) /* PIC requests RTC data */ + { + volatile uint8_t *rtc_reg = (uint8_t *) 0xffff8961; + volatile uint8_t *rtc_data = (uint8_t *) 0xffff8963; + int index = 0; + + err("PIC interrupt: requesting RTC data\r\n"); + + write_pic_byte(0x82); // header byte to PIC + do + { + *rtc_reg = index; + write_pic_byte(*rtc_data); + } while (++index < 64); + } + return true; +} +#endif /* MACHINE_FIREBEE */ + +bool xlbpci_interrupt_handler(void *arg1, void *arg2) +{ + uint32_t reason; + + dbg("XLB PCI interrupt\r\n"); + + reason = MCF_PCI_PCIISR; + + if (reason & MCF_PCI_PCIISR_RE) + { + dbg("Retry error. Retry terminated or max retries reached. Cleared\r\n"); + MCF_PCI_PCIISR |= MCF_PCI_PCIISR_RE; + } + + if (reason & MCF_PCI_PCIISR_IA) + { + dbg("Initiator abort. No target answered in time. Cleared.\r\n"); + MCF_PCI_PCIISR |= MCF_PCI_PCIISR_IA; + } + + if (reason & MCF_PCI_PCIISR_TA) + { + dbg("Target abort. Cleared.\r\n"); + MCF_PCI_PCIISR |= MCF_PCI_PCIISR_TA; + } + + return true; +} + +bool pciarb_interrupt_handler(void *arg1, void *arg2) +{ + dbg("PCI ARB interrupt\r\n"); + + MCF_PCIARB_PASR |= MCF_PCIARB_PASR_EXTMBK(0x1f) | MCF_PCIARB_PASR_ITLMBK; + return true; +} + +bool xlbarb_interrupt_handler(void *arg1, void *arg2) +{ + uint32_t status = MCF_XLB_XARB_SR; + + dbg("arg1=0x%08x arg2=0x%08x\r\n", arg1, arg2); + + /* + * TODO: we should probably issue a bus error when this occors + */ + err("XLB arbiter interrupt\r\n"); + err("captured address: 0x%08lx\r\n", MCF_XLB_XARB_ADRCAP); + + MCF_XLB_XARB_ADRCAP = 0x0L; + MCF_XLB_XARB_SIGCAP = 0x0L; + + if (status & MCF_XLB_XARB_SR_AT) + err("address tenure timeout\r\n"); + if (status & MCF_XLB_XARB_SR_DT) + err("data tenure timeout\r\n"); + if (status & MCF_XLB_XARB_SR_BA) + err("bus activity tenure timeout\r\n"); + if (status & MCF_XLB_XARB_SR_TTM) + err("TBST/TSIZ mismatch\r\n"); + if (status & MCF_XLB_XARB_SR_ECW) + err("external control word read/write\r\n"); + if (status & MCF_XLB_XARB_SR_TTR) + err("TT reserved\r\n"); + if (status & MCF_XLB_XARB_SR_TTA) + err("TT address only\r\n"); + if (status & MCF_XLB_XARB_SR_MM) + err("multiple masters at priority 0\r\n"); + if (status & MCF_XLB_XARB_SR_SEA) + err("slave error acknowledge\r\n"); + + /* + * acknowledge interrupt + */ + MCF_XLB_XARB_SR = status; /* rwc bits */ + + return true; +} + +#if defined(MACHINE_FIREBEE) +/* + * This gets called from irq5 in exceptions.S + * + * IRQ5 are the "FBEE" (PIC, ETH PHY, PCI, DVI monitor sense and DSP) interrupts multiplexed by the FPGA interrupt handler + */ +bool irq5_handler(void *arg1, void *arg2) +{ + uint32_t pending_interrupts = FBEE_INTR_PENDING; + + dbg("IRQ5!\r\n"); + if (pending_interrupts & FBEE_INTR_PIC) + { + dbg("PIC interrupt\r\n"); + FBEE_INTR_CLEAR = FBEE_INTR_PIC; + } + + if (pending_interrupts & FBEE_INTR_ETHERNET) + { + dbg("ethernet 0 PHY interrupt\r\n"); + FBEE_INTR_CLEAR = FBEE_INTR_ETHERNET; + } + + if (pending_interrupts & FBEE_INTR_DVI) + { + dbg("DVI monitor sense interrupt\r\n"); + FBEE_INTR_CLEAR = FBEE_INTR_DVI; + } + + if (pending_interrupts & FBEE_INTR_PCI_INTA || + pending_interrupts & FBEE_INTR_PCI_INTB || + pending_interrupts & FBEE_INTR_PCI_INTC || + pending_interrupts & FBEE_INTR_PCI_INTD) + { + int handle; + + if ((handle = pci_get_interrupt_cause() != -1)) + { + pci_call_interrupt_chain(handle, 0L); + } + dbg("PCI interrupt IRQ5\r\n"); + FBEE_INTR_CLEAR = FBEE_INTR_PCI_INTA | + FBEE_INTR_PCI_INTB | + FBEE_INTR_PCI_INTC | + FBEE_INTR_PCI_INTD; + } + + if (pending_interrupts & FBEE_INTR_DSP) + { + dbg("DSP interrupt\r\n"); + FBEE_INTR_CLEAR = FBEE_INTR_DSP; + } + + MCF_EPORT_EPFR |= (1 << 5); /* clear interrupt from edge port */ + + return true; +} + +/* + * blink the Firebee's LED to show we are still alive + */ +void blink_led(void) +{ + static uint16_t blinker = 0; + + if ((blinker++ & 0x80) > 0) + { + MCF_GPIO_PODR_FEC1L |= (1 << 4); /* LED off */ + } + else + { + MCF_GPIO_PODR_FEC1L &= ~(1 << 4); /* LED on */ + } +} + +/* + * Atari MFP interrupt registers. + * + * TODO: should go into a header file + */ + +#define FALCON_MFP_IERA *((volatile uint8_t *) 0xfffffa07) +#define FALCON_MFP_IERB *((volatile uint8_t *) 0xfffffa09) +#define FALCON_MFP_IPRA *((volatile uint8_t *) 0xfffffa0b) +#define FALCON_MFP_IPRB *((volatile uint8_t *) 0xfffffa0d) +#define FALCON_MFP_IMRA *((volatile uint8_t *) 0xfffffa13) +#define FALCON_MFP_IMRB *((volatile uint8_t *) 0xfffffa15) + +bool irq6_acsi_dma_interrupt(void) +{ + dbg("ACSI DMA interrupt\r\n"); + + /* + * TODO: implement handler + */ + + return false; +} + +bool irq6_handler(uint32_t sf1, uint32_t sf2) +{ + //err("IRQ6!\r\n"); + + if (FALCON_MFP_IPRA || FALCON_MFP_IPRB) + { + blink_led(); + } + + MCF_EPORT_EPFR |= (1 << 6); /* clear int6 from edge port */ + + return false; /* always forward IRQ6 to TOS */ +} + +#else /* MACHINE_FIREBEE */ + +bool irq5_handler(void *arg1, void *arg2) +{ + MCF_EPORT_EPFR |= (1 << 5); /* clear int5 from edge port */ + + return true; +} + +bool irq6_handler(void *arg1, void *arg2) +{ + err("IRQ6!\r\n"); + + MCF_EPORT_EPFR |= (1 << 6); /* clear int6 from edge port */ + + return false; /* always forward IRQ6 to TOS */ +} + +/* + * This gets called from irq7 in exceptions.S + * Once we arrive here, the SR has been set to disable interrupts and the gcc scratch registers have been saved + */ +bool irq7_handler(void) +{ + int32_t handle; + int32_t value = 0; + int32_t newvalue; + + MCF_EPORT_EPFR |= (1 << 7); + dbg("IRQ7!\r\n"); + if ((handle = pci_get_interrupt_cause()) > 0) + { + newvalue = pci_call_interrupt_chain(handle, value); + if (newvalue == value) + { + dbg("interrupt not handled!\r\n"); + } + } + MCF_EPORT_EPFR |= (1 << 7); /* clear int7 from edge port */ + + return true; +} +#endif /* MACHINE_M548X */ + +#if defined(MACHINE_FIREBEE) +/* + * this is the higlevel interrupt service routine for gpt0 timer interrupts. + * + * It is called from handler_gpt0 in exceptions.S + * + * The gpt0 timer is not used as a timer, but as interrupt trigger by the FPGA which fires + * everytime the video base address high byte (0xffff8201) gets written by user code (i.e. + * everytime the video base address is set). + * The interrupt service routine checks if that page was already set as a video page (in that + * case it does nothing), if not (if we have a newly set page), it sets up an MMU mapping for + * that page (effectively rerouting any further access to Falcon video RAM to Firebee FPGA + * video RAM starting at 0x60000000) and copies SDRAM contents of that page to the video + * RAM page. + */ +bool gpt0_interrupt_handler(void *arg0, void *arg1) +{ + dbg("gpt0 handler called\n\r"); + + MCF_GPT0_GMS &= ~1; /* rearm trigger */ + NOP(); + MCF_GPT0_GMS |= 1; + + return true; +} +#endif /* MACHINE_FIREBEE */ + + +uint32_t set_ipl(uint32_t ipl) +{ + uint32_t ret; + + __asm__ __volatile__( + " move.w sr,%[ret]\r\n" /* retrieve status register */ + " andi.l #0x07,%[ipl]\n\t" /* mask out ipl bits on new value */ + " lsl.l #8,%[ipl]\n\t" /* shift them to position */ + " move.l %[ret],d0\n\t" /* retrieve original value */ + " andi.l #0x0000f8ff,d0\n\t" /* clear ipl part */ + " or.l %[ipl],d0\n\t" /* or in new value */ + " move.w d0,sr\n\t" /* put it in place */ + " andi.l #0x0700,%[ret]\r\n" /* mask out ipl bits */ + " lsr.l #8,%[ret]\r\n" /* shift them to position */ + : [ret] "=&d" (ret) /* output */ + : [ipl] "d" (ipl) /* input */ + : "d0", "cc" /* clobber */ + ); + + return ret; +} diff --git a/sys/mmu.c b/sys/mmu.c new file mode 100644 index 0000000..435e6c3 --- /dev/null +++ b/sys/mmu.c @@ -0,0 +1,1017 @@ +#include "mmu.h" +#include "acia.h" +#include "exceptions.h" +#include "pci.h" + +// #define DEBUG +#include "debug.h" + +/* + * mmu.c + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * derived from original assembler sources: + * Copyright 2010 - 2012 F. Aschwanden + * Copyright 2013 M. Froeschle + */ + +#include +#include "bas_printf.h" +#include "bas_types.h" +#include "MCF5475.h" +#include "pci.h" +#include "cache.h" +#include "util.h" + +#if defined(MACHINE_FIREBEE) +#include "firebee.h" +#elif defined(MACHINE_M5484LITE) +#include "m5484l.h" +#elif defined(MACHINE_M54455) +#include "m54455.h" +#else +#error "unknown machine!"x +#endif /* MACHINE_FIREBEE */ + +/* + * set ASID register + * saves new value to rt_asid and returns former value + */ +inline uint32_t set_asid(uint32_t value) +{ + extern long rt_asid; + uint32_t ret = rt_asid; + + __asm__ __volatile__( + "movec %[value],ASID\n\t" + : /* no output */ + : [value] "r" (value) + : + ); + + rt_asid = value; + + return ret; +} + + +/* + * set ACRx register + * saves new value to rt_acrx and returns former value + */ +inline uint32_t set_acr0(uint32_t value) +{ + extern uint32_t rt_acr0; + uint32_t ret = rt_acr0; + + __asm__ __volatile__( + "movec %[value],ACR0\n\t" + : /* not output */ + : [value] "r" (value) + : + ); + rt_acr0 = value; + + return ret; +} + +/* + * set ACRx register + * saves new value to rt_acrx and returns former value + */ +inline uint32_t set_acr1(uint32_t value) +{ + extern uint32_t rt_acr1; + uint32_t ret = rt_acr1; + + __asm__ __volatile__( + "movec %[value],ACR1\n\t" + : /* not output */ + : [value] "r" (value) + : + ); + rt_acr1 = value; + + return ret; +} + + +/* + * set ACRx register + * saves new value to rt_acrx and returns former value + */ +inline uint32_t set_acr2(uint32_t value) +{ + extern uint32_t rt_acr2; + uint32_t ret = rt_acr2; + + __asm__ __volatile__( + "movec %[value],ACR2\n\t" + : /* not output */ + : [value] "r" (value) + : + ); + rt_acr2 = value; + + return ret; +} + +/* + * set ACRx register + * saves new value to rt_acrx and returns former value + */ +inline uint32_t set_acr3(uint32_t value) +{ + extern uint32_t rt_acr3; + uint32_t ret = rt_acr3; + + __asm__ __volatile__( + "movec %[value],ACR3\n\t" + : /* not output */ + : [value] "r" (value) + : + ); + rt_acr3 = value; + + return ret; +} + +inline uint32_t set_mmubar(uint32_t value) +{ + extern uint32_t rt_mmubar; + uint32_t ret = rt_mmubar; + + __asm__ __volatile__( + "movec %[value],MMUBAR\n\t" + : /* no output */ + : [value] "r" (value) + : /* no clobber */ + ); + rt_mmubar = value; + NOP(); + + return ret; +} + + +/* + * translation table for virtual address ranges. Holds the physical_offset (which must be added to a virtual + * address to get its physical counterpart) for memory ranges. + */ +struct virt_to_phys +{ + uint32_t start_address; + uint32_t length; + uint32_t physical_offset; +}; + +#if defined(MACHINE_FIREBEE) +static struct virt_to_phys translation[] = +{ + /* virtual , length , offset */ + { 0x00000000, 0x00e00000, 0x60000000 }, /* map first 14 MByte to first 14 Mb of video ram */ + { 0x00e00000, 0x00100000, 0x00000000 }, /* map TOS to SDRAM */ + { 0x00f00000, 0x00100000, 0xff000000 }, /* map Falcon I/O area to FPGA */ + { 0x01000000, 0x1f000000, 0x00000000 }, /* map rest of ram virt = phys */ +}; +#elif defined(MACHINE_M5484LITE) +static struct virt_to_phys translation[] = +{ + /* virtual , length , offset */ + { 0x00000000, 0x00e00000, 0x00000000 }, /* map first 14 MByte to first 14 Mb of SD ram */ + { 0x00e00000, 0x00100000, 0x00000000 }, /* map TOS to SDRAM */ + { 0x01000000, 0x04000000, 0x00000000 }, /* map rest of ram virt = phys */ +#if 0 + { 0x04000000, 0x08000000, 0x7C000000 }, /* experimental mapping for PCI memory */ +#endif +}; +#elif defined(MACHINE_M54455) +/* FIXME: this is not determined yet! */ +static struct virt_to_phys translation[] = +{ + /* virtual , length , offset */ + { 0x00000000, 0x00e00000, 0x60000000 }, /* map first 14 MByte to first 14 Mb of video ram */ + { 0x00e00000, 0x00100000, 0x00000000 }, /* map TOS to SDRAM */ + { 0x00f00000, 0x00100000, 0xff000000 }, /* map Falcon I/O area to FPGA */ + { 0x01000000, 0x1f000000, 0x00000000 }, /* map rest of ram virt = phys */ +}; +#else +#error unknown machine! +#endif + +static int num_translations = sizeof(translation) / sizeof(struct virt_to_phys); + +static inline uint32_t lookup_phys(int32_t virt) +{ + int i; + + for (i = 0; i < num_translations; i++) + { + if (virt >= translation[i].start_address && virt < translation[i].start_address + translation[i].length) + { + return virt + translation[i].physical_offset; + } + } + err("virtual address 0x%lx not found in translation table!\r\n", virt); + + return -1; +} + + +/* + * page descriptors. Size depending on DEFAULT_PAGE_SIZE, either 1M (resulting in 512 + * bytes size) or 8k pages (64k descriptor array size) + */ +#define NUM_PAGES (SDRAM_SIZE / SIZE_DEFAULT) +static struct mmu_page_descriptor_ram pages[NUM_PAGES]; + + +int mmu_map_instruction_page(uint32_t virt, uint8_t asid) +{ + const uint32_t size_mask = ~ (SIZE_DEFAULT - 1); /* pagesize */ + int page_index = (virt & size_mask) / SIZE_DEFAULT; /* index into page_descriptor array */ + struct mmu_page_descriptor_ram *page = &pages[page_index]; /* attributes of page to map */ + int ipl; + uint32_t phys = lookup_phys(virt); /* virtual to physical translation of page */ + + if (phys == (uint32_t) -1) + { + /* no valid mapping found, caller will issue a bus error in return */ + dbg("no mapping found\r\n"); + return 0; + } + +#ifdef DBG_MMU + register int sp asm("sp"); + dbg("page_descriptor: 0x%02x, ssp = 0x%08x\r\n", * (uint8_t *) page, sp); +#endif /* DBG_MMU */ + + /* + * add page to TLB + */ + + ipl = set_ipl(7); /* do not disturb */ + + MCF_MMU_MMUAR = (virt & size_mask); + + MCF_MMU_MMUTR = (virt & size_mask) | /* virtual address */ + MCF_MMU_MMUTR_ID(asid) | /* address space id (ASID) */ + (page->global ? MCF_MMU_MMUTR_SG : 0) | /* shared global */ + MCF_MMU_MMUTR_V; /* valid */ + + MCF_MMU_MMUDR = (phys & size_mask) | /* physical address */ + MCF_MMU_MMUDR_SZ(MMU_PAGE_SIZE_DEFAULT) | /* page size */ + MCF_MMU_MMUDR_CM(page->cache_mode) | /* cache mode */ + (page->supervisor_protect ? MCF_MMU_MMUDR_SP : 0) | /* supervisor protect */ + (page->read ? MCF_MMU_MMUDR_R : 0) | /* read access enable */ + (page->write ? MCF_MMU_MMUDR_W : 0) | /* write access enable */ + (page->execute ? MCF_MMU_MMUDR_X : 0) | /* execute access enable */ + (page->locked ? MCF_MMU_MMUDR_LK : 0); + + MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */ + MCF_MMU_MMUOR_ACC | /* access TLB */ + MCF_MMU_MMUOR_UAA; /* update allocation address field */ + + set_ipl(ipl); + + dbg("mapped virt=0x%08x to phys=0x%08x\r\n", virt & size_mask, phys & size_mask); + + dbg("ITLB: MCF_MMU_MMUOR = %08x\r\n", MCF_MMU_MMUOR); + + return 1; +} + +struct mmu_page_descriptor_ram pci_descriptor = +{ + .cache_mode = CACHE_NOCACHE_PRECISE, + .supervisor_protect = 0, + .read = 1, + .write = 1, + .execute = 1, + .global = 1, + .locked = 0 +}; + +int mmu_map_data_page(uint32_t virt, uint8_t asid) +{ + uint16_t ipl; + const uint32_t size_mask = ~ (SIZE_DEFAULT - 1); /* pagesize */ + int page_index = (virt & size_mask) / SIZE_DEFAULT; /* index into page_descriptor array */ + struct mmu_page_descriptor_ram *page; + uint32_t phys = 0L; + + if (page_index < sizeof(pages) / sizeof(struct mmu_page_descriptor_ram)) + { + page = &pages[page_index]; /* attributes of page to map */ + phys = lookup_phys(virt); /* virtual to physical translation of page */ + } + + /* + * check if we are trying to access PCI space + */ + else if (virt >= PCI_MEMORY_OFFSET && virt <= PCI_MEMORY_OFFSET + PCI_MEMORY_SIZE) + { + phys = virt; + page = &pci_descriptor; + } + else + return 0; + + + + if (phys == (uint32_t) -1) + { + /* no valid mapping found, caller will issue a bus error in return */ + dbg("no mapping found\r\n"); + return 0; + } + +#ifdef DEBUG + register int sp asm("sp"); + dbg("page_descriptor: 0x%02x, ssp = 0x%08x\r\n", * (uint8_t *) page, sp); +#endif /* DBG_MMU */ + + /* + * add page to TLB + */ + + ipl = set_ipl(7); /* do not disturb */ + + MCF_MMU_MMUTR = (virt & size_mask) | /* virtual address */ + MCF_MMU_MMUTR_ID(asid) | /* address space id (ASID) */ + (page->global ? MCF_MMU_MMUTR_SG : 0) | /* shared global */ + MCF_MMU_MMUTR_V; /* valid */ + + MCF_MMU_MMUDR = (phys & size_mask) | /* physical address */ + MCF_MMU_MMUDR_SZ(MMU_PAGE_SIZE_DEFAULT) | /* page size */ + MCF_MMU_MMUDR_CM(page->cache_mode) | /* cache mode */ + (page->supervisor_protect ? MCF_MMU_MMUDR_SP : 0) | /* supervisor protect */ + (page->read ? MCF_MMU_MMUDR_R : 0) | /* read access enable */ + (page->write ? MCF_MMU_MMUDR_W : 0) | /* write access enable */ + (page->execute ? MCF_MMU_MMUDR_X : 0) | /* execute access enable */ + (page->locked ? MCF_MMU_MMUDR_LK : 0); + + MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */ + MCF_MMU_MMUOR_UAA; /* update allocation address field */ + + set_ipl(ipl); + + dbg("mapped virt=0x%08x to phys=0x%08x\r\n", virt & size_mask, phys & size_mask); + + dbg("DTLB: MCF_MMU_MMUOR = %08x\r\n", MCF_MMU_MMUOR); + + return 1; +} + +/* + * map a page of memory using virt and phys as addresses with the Coldfire MMU. + * + * Theory of operation: the Coldfire MMU in the Firebee has 64 TLB entries, 32 for data (DTLB), 32 for + * instructions (ITLB). Mappings can either be done locked (normal MMU TLB misses will not consider them + * for replacement) or unlocked (mappings will reallocate using a LRU scheme when the MMU runs out of + * TLB entries). For proper operation, the MMU needs at least two ITLBs and/or four free/allocatable DTLBs + * per instruction as a minimum, more for performance. Thus locked pages (that can't be touched by the + * LRU algorithm) should be used sparsingly. + */ +uint32_t mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor_ram *flags) +{ + int size_mask; + int ipl; + + switch (sz) + { + case MMU_PAGE_SIZE_1M: + size_mask = ~ (SIZE_1M - 1); + break; + + case MMU_PAGE_SIZE_8K: + size_mask = ~ (SIZE_8K - 1); + break; + + case MMU_PAGE_SIZE_4K: + size_mask = ~ (SIZE_4K - 1); + break; + + case MMU_PAGE_SIZE_1K: + size_mask = ~ (SIZE_1K - 1); + break; + + default: + dbg("illegal map size %d\r\n", sz); + return 0; + } + + /* + * add page to TLB + */ + + ipl = set_ipl(7); /* do not disturb */ + + MCF_MMU_MMUTR = (virt & size_mask) | /* virtual address */ + MCF_MMU_MMUTR_ID(page_id) | /* address space id (ASID) */ + (flags->global ? MCF_MMU_MMUTR_SG : 0) | /* shared global */ + MCF_MMU_MMUTR_V; /* valid */ + + MCF_MMU_MMUDR = (phys & size_mask) | /* physical address */ + MCF_MMU_MMUDR_SZ(sz) | /* page size */ + MCF_MMU_MMUDR_CM(flags->cache_mode) | + (flags->read ? MCF_MMU_MMUDR_R : 0) | /* read access enable */ + (flags->write ? MCF_MMU_MMUDR_W : 0) | /* write access enable */ + (flags->execute ? MCF_MMU_MMUDR_X : 0) | /* execute access enable */ + (flags->supervisor_protect ? MCF_MMU_MMUDR_SP : 0) | /* supervisor protect */ + (flags->locked ? MCF_MMU_MMUDR_LK : 0); + + MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */ + MCF_MMU_MMUOR_UAA; /* update allocation address field */ + NOP(); + + MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */ + MCF_MMU_MMUOR_ACC | /* access TLB */ + MCF_MMU_MMUOR_UAA; /* update allocation address field */ + + set_ipl(ipl); + + dbg("mapped virt=0x%08x to phys=0x%08x size mask 0x%lx\r\n", virt, phys, size_mask); + + return 1; +} + +void mmu_init(void) +{ + extern uint8_t _MMUBAR[]; + uint32_t MMUBAR = (uint32_t) &_MMUBAR[0]; + struct mmu_page_descriptor_ram flags; + int i; + + /* + * clear all MMU TLB entries first + */ + MCF_MMU_MMUOR = MCF_MMU_MMUOR_CA; /* clears _all_ TLBs (including locked ones) */ + NOP(); + + /* + * prelaminary initialization of page descriptor 0 (root) table + */ + for (i = 0; i < NUM_PAGES; i++) + { + uint32_t addr = i * SIZE_DEFAULT; + +#if defined(MACHINE_FIREBEE) + if (addr >= 0x00f00000UL && addr < 0x00ffffffUL) /* Falcon I/O area on the Firebee */ + { + pages[i].cache_mode = CACHE_NOCACHE_PRECISE; + pages[i].supervisor_protect = 1; + pages[i].read = 1; + pages[i].write = 1; + pages[i].execute = 0; + pages[i].global = 1; + } + else if (addr >= 0xfff00000UL && addr <= 0xffffffffUL) /* Falcon I/O area on the Firebee */ + { + pages[i].cache_mode = CACHE_NOCACHE_PRECISE; + pages[i].supervisor_protect = 1; + pages[i].read = 1; + pages[i].write = 1; + pages[i].execute = 0; + pages[i].global = 1; + } + else if (addr >= 0x0UL && addr < 0x00e00000UL) /* ST-RAM, potential video memory */ + { + pages[i].cache_mode = CACHE_WRITETHROUGH; + pages[i].supervisor_protect = 0; // (addr == 0x0L ? 1 : 0); + pages[i].read = 1; + pages[i].write = 1; + pages[i].execute = 1; + pages[i].global = 1; + } + else if (addr >= 0x00e00000UL && addr < 0x00f00000UL) /* EmuTOS */ + { + pages[i].cache_mode = CACHE_COPYBACK; + pages[i].supervisor_protect = 0; + pages[i].read = 1; + pages[i].write = 0; + pages[i].execute = 1; + pages[i].global = 1; + } + else if (addr >= 0x00000000 && addr <= 0x00010000) /* first Megabyte of ST RAM */ + { + pages[i].cache_mode = CACHE_COPYBACK; + pages[i].supervisor_protect = 0; + pages[i].read = 1; + pages[i].write = 1; + pages[i].execute = 1; + pages[i].global = 1; + } + else + { + pages[i].cache_mode = CACHE_COPYBACK; + pages[i].supervisor_protect = 0; + pages[i].read = 1; + pages[i].write = 1; + pages[i].execute = 1; + pages[i].global = 1; + } + pages[i].locked = 0; /* not locked */ + +#elif defined(MACHINE_M5484LITE) + if (addr >= 0x60000000UL && addr < 0x70000000UL) /* Compact Flash on the m5484lite */ + { + pages[i].cache_mode = CACHE_NOCACHE_PRECISE; + pages[i].supervisor_protect = 0; + pages[i].read = 1; + pages[i].write = 1; + pages[i].execute = 1; + pages[i].global = 1; + } + else if (addr >= 0x0UL && addr < 0x00e00000UL) /* ST-RAM, potential video memory */ + { + pages[i].cache_mode = CACHE_WRITETHROUGH; + pages[i].supervisor_protect = 0; + pages[i].read = 1; + pages[i].write = 1; + pages[i].execute = 1; + pages[i].global = 1; + } + else if (addr >= 0x00e00000UL && addr < 0x00f00000UL) /* EmuTOS */ + { + pages[i].cache_mode = CACHE_COPYBACK; + pages[i].execute = 1; + pages[i].supervisor_protect = 1; + pages[i].read = 1; + pages[i].write = 0; + pages[i].execute = 1; + pages[i].global = 1; + } + else + { + pages[i].cache_mode = CACHE_COPYBACK; /* rest of RAM */ + pages[i].execute = 1; + pages[i].read = 1; + pages[i].write = 1; + pages[i].supervisor_protect = 0; + pages[i].global = 1; + } + pages[i].locked = 0; /* not locked */ + +#elif defined(MACHINE_M54455) + if (addr >= 0x60000000UL && addr < 0x70000000UL) /* Compact Flash on the m5484lite */ + { + pages[i].cache_mode = CACHE_NOCACHE_PRECISE; + pages[i].execute = 0; + pages[i].read = 1; + pages[i].write = 1; + pages[i].execute = 0; + pages[i].global = 1; + pages[i].supervisor_protect = 1; + } + else if (addr >= 0x0UL && addr < 0x00e00000UL) /* ST-RAM, potential video memory */ + { + pages[i].cache_mode = CACHE_WRITETHROUGH; + pages[i].execute = 1; + pages[i].supervisor_protect = 0; + pages[i].read = 1; + pages[i].write = 1; + pages[i].execute = 1; + pages[i].global = 1; + } + else if (addr >= 0x00e00000UL && addr < 0x00f00000UL) /* EmuTOS */ + { + pages[i].cache_mode = CACHE_COPYBACK; + pages[i].execute = 1; + pages[i].supervisor_protect = 1; + pages[i].read = 1; + pages[i].write = 0; + pages[i].execute = 1; + pages[i].global = 1; + } + else + { + pages[i].cache_mode = CACHE_COPYBACK; /* rest of RAM */ + pages[i].execute = 1; + pages[i].read = 1; + pages[i].write = 1; + pages[i].supervisor_protect = 0; + pages[i].global = 1; + } + pages[i].locked = 0; /* not locked */ +#else +#error Unknown machine! +#endif /* MACHINE_FIREBEE */ + } + + set_asid(0); /* do not use address extension (ASID provides virtual 48 bit addresses */ + + // pages[0].supervisor_protect = 1; /* protect system vectors */ + + /* set data access attributes in ACR0 and ACR1 */ + + /* map PCI address space */ + /* set SRAM and MBAR access */ + set_acr0(ACR_W(0) | /* read and write accesses permitted */ + // ACR_SP(1) | /* supervisor only access permitted */ + ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* cache inhibit, precise */ + ACR_AMM(0) | /* control region > 16 MB */ + ACR_S(ACR_S_SUPERVISOR_MODE) | /* match addresses in supervisor and user mode */ + ACR_E(1) | /* enable ACR */ +#if defined(MACHINE_FIREBEE) + ACR_ADMSK(0x7f) | /* cover 2GB area from 0x80000000 to 0xffffffff */ + // ACR_BA(PCI_MEMORY_OFFSET)); /* (equals area from 3 to 4 GB */ + ACR_BA(0xe0000000)); +#elif defined(MACHINE_M5484LITE) + ACR_ADMSK(0x7f) | /* cover 2 GB area from 0x80000000 to 0xffffffff */ + // ACR_BA(PCI_MEMORY_OFFSET)); + ACR_BA(0xe0000000)); +#elif defined(MACHINE_M54455) + ACR_ADMSK(0x7f) | + ACR_BA(0x80000000)); /* FIXME: not determined yet */ +#else +#error unknown machine! +#endif /* MACHINE_FIREBEE */ + + /* data access attributes for BaS in flash */ + + set_acr1(ACR_W(0) | + ACR_SP(0) | + ACR_CM(0) | +#if defined(MACHINE_FIREBEE) + ACR_CM(ACR_CM_CACHEABLE_WT) | +#elif defined(MACHINE_M5484LITE) + ACR_CM(ACR_CM_CACHEABLE_WT) | +#elif defined(MACHINE_M54455) + ACR_CM(ACR_CM_CACHEABLE_WT) | +#else +#error unknown machine! +#endif /* MACHINE_FIREBEE */ + ACR_AMM(0) | + ACR_S(ACR_S_ALL) | + ACR_E(1) | + ACR_ADMSK(0x1f) | + ACR_BA(0xe0000000)); + + /* set instruction access attributes in ACR2 and ACR3 */ + + //set_acr2(0xe007c400); + + /* instruction access attribute for BaS in flash */ + + set_acr2(ACR_W(0) | + ACR_SP(0) | + ACR_CM(0) | + ACR_CM(ACR_CM_CACHEABLE_WT) | + ACR_AMM(1) | + ACR_S(ACR_S_ALL) | + ACR_E(1) | + ACR_ADMSK(0x7) | + ACR_BA(0xe0000000)); + + + /* disable ACR3 */ + set_acr3(0x0); + + set_mmubar(MMUBAR + 1); /* set and enable MMUBAR */ + + /* + * Make the TOS (in SDRAM) read-only + * This maps virtual 0x00e0'0000 - 0x00ef'ffff to the same virtual address + */ + flags.cache_mode = CACHE_COPYBACK; + flags.supervisor_protect = 0; // needs to stay like this or cf_flasher will choke */ + flags.read = 1; + flags.write = 0; + flags.execute = 1; + flags.locked = 1; + mmu_map_page(0xe00000, 0xe00000, MMU_PAGE_SIZE_1M, 0, &flags); + +#if defined(MACHINE_FIREBEE) + /* + * Map FireBee I/O area (0xfff0'0000 - 0xffff'ffff physical) to the Falcon-compatible I/O + * area (0x00f0'0000 - 0x00ff'ffff virtual) for the FireBee + */ + flags.cache_mode = CACHE_NOCACHE_PRECISE; + flags.supervisor_protect = 1; + flags.read = 1; + flags.write = 1; + flags.execute = 0; + flags.locked = 1; + mmu_map_page(0x00f00000, 0xfff00000, MMU_PAGE_SIZE_1M, 0, &flags); +#elif defined(MACHINE_M5484LITE) + /* + * Map m5484LITE CPLD access + */ + flags.cache_mode = CACHE_NOCACHE_PRECISE; + flags.supervisor_protect = 1; + flags.read = 1; + flags.write = 1; + flags.execute = 0; + flags.locked = 1; + mmu_map_page(0x6a000000, 0x6a000000, MMU_PAGE_SIZE_1M, 0, &flags); +#elif defined(MACHINE_M54455) +#warning MMU specs for M54455 not yet determined +#else +#error Unknown machine +#endif /* MACHINE_FIREBEE */ + + /* + * Map (locked) the second last MB of physical SDRAM (this is where BaS .data and .bss reside) to the same + * virtual address. This is also used (completely) when BaS is in RAM + */ + flags.cache_mode = CACHE_COPYBACK; + flags.supervisor_protect = 0; + flags.read = 1; + flags.write = 1; + flags.execute = 1; + flags.locked = 1; + mmu_map_page(SDRAM_START + SDRAM_SIZE - 0x00200000, SDRAM_START + SDRAM_SIZE - 0x00200000, MMU_PAGE_SIZE_1M, 0, &flags); + + /* + * Map (locked) the very last MB of physical SDRAM (this is where the driver buffers reside) to the same + * virtual address. Used uncached for drivers. + */ + flags.cache_mode = CACHE_NOCACHE_PRECISE; + flags.supervisor_protect = 0; + flags.read = 1; + flags.write = 1; + flags.execute = 0; + flags.locked = 1; + mmu_map_page(SDRAM_START + SDRAM_SIZE - 0x00100000, SDRAM_START + SDRAM_SIZE - 0x00100000, MMU_PAGE_SIZE_1M, 0, &flags); +} + + +uint32_t mmutr_miss(uint32_t mmu_sr, uint32_t fault_address, uint32_t pc, uint32_t format_status) +{ + uint32_t fault = format_status & 0xc030000; + + //dbg("MMU TLB MISS accessing 0x%08x\r\nFS = 0x%08x\r\nPC = 0x%08x\r\n", fault_address, format_status, pc); + // flush_and_invalidate_caches(); + + switch (fault) + { + /* if we have a real TLB miss, map the offending page */ + + case 0x04010000: /* TLB miss on opword of instruction fetch */ + case 0x04020000: /* TLB miss on extension word of instruction fetch */ + dbg("MMU ITLB MISS accessing 0x%08x\r\n" + "FS = 0x%08x\r\n" + "MMUSR = 0x%08x\r\n" + "PC = 0x%08x\r\n", + fault_address, format_status, mmu_sr, pc); + dbg("fault = 0x%08x\r\n", fault); + + if (!mmu_map_instruction_page(pc, 0)) + { + dbg("ITLB miss bus error\r\n"); + return 1; /* bus error */ + } + +#ifdef _NOT_USED_ + /* due to prefetch, it makes sense to map the next adjacent page also for ITLBs */ + if (pc + SIZE_DEFAULT < TARGET_ADDRESS) + { + /* + * only do this if the next page is still valid RAM + */ + if (!mmu_map_instruction_page(pc + MMU_DEFAULT_PAGE_SIZE, 0)) + { + dbg("ITLB next page bus error\r\n"); + return 1; /* bus error */ + } + } +#endif /* _NOT_USED_ */ + break; + + case 0x08020000: /* TLB miss on data write */ + case 0x0c020000: /* TLB miss on data read or read-modify-write */ + dbg("MMU DTLB MISS accessing 0x%08x\r\n" + "FS = 0x%08x\r\n" + "MMUSR = 0x%08x\r\n" + "PC = 0x%08x\r\n", + fault_address, format_status, mmu_sr, pc); + dbg("fault = 0x%08x\r\n", fault); + + if (!mmu_map_data_page(fault_address, 0)) + { + dbg("DTLB miss bus error\r\n"); + return 1; /* bus error */ + } + break; + + case 0x0c010000: + case 0x08010000: + dbg("privilege violation accessing 0x%08x\r\n" + "FS = 0x%08x\r\n" + "MMUSR = 0x%08x\r\n" + "PC = 0x%08x\r\n", + fault_address, format_status, mmu_sr, pc); + dbg("fault = 0x%08x\r\n", fault); +#ifdef _DOES_NOT_WORK_ + /* + * check if its one of our "special cases" and map a user page on top of it if user + * mode access should be allowed + */ + if (fault_address >= 1024 && fault_address < 0x00100000) /* ST-RAM */ + { + struct mmu_page_descriptor flags = + { + .cache_mode = CACHE_COPYBACK, + .supervisor_protect = 0, + .read = 1, + .write = 1, + .execute = 1, + .global = 1, + .locked = 0 + }; + + uint32_t virt = fault_address & ~(SIZE_1K - 1); + uint32_t phys = (fault_address & (~(SIZE_1K - 1))) + 0x60000000; + dbg("mapping helper page virt=0x%08x to phys=0x%08x\r\n", virt, phys); + if (!mmu_map_page(virt, phys, MMU_PAGE_SIZE_1K, 0, &flags)) + { + dbg("privilege violation (bus error)\r\n"); + return 1; + } + } +#endif + return 1; + break; + + /* else issue a bus error */ + default: + dbg("bus error accessing 0x%08x\r\n" + "FS = 0x%08x\r\n" + "MMUSR = 0x%08x\r\n" + "PC = 0x%08x\r\n", + fault_address, format_status, mmu_sr, pc); + dbg("fault = 0x%08x\r\n", fault); + return 1; /* signal bus error to caller */ + } +#ifdef DBG_MMU + xprintf("\r\n"); +#endif /* DBG_MMU */ + + return 0; /* signal TLB miss handled to caller */ +} + + +/* TODO: implement */ + +/* + * API-exposed, externally callable MMU functions + */ + + +/* + * lock data page(s) with address space id asid from address virt to virt + size. + * + * ASID probably needs an explanation - this is the "address space id" managed by + * the MMU. + * If its value range would be large enough, this could directly map to a PID + * in MiNT. Unfortunately, the Coldfire MMU only allows an 8 bit value for ASID + * (with 0 already occupied for the super user/root process and the Firebee video + * subsystem occupying another one), so we are left with 253 distinct values. + * MMU software needs to implement some kind of mapping and LRU scheme which will + * lead to a throwaway of all mappings for processes not seen for a while (and thus + * to undeterministic response/task switching times when such processes are activated + * again). + * + * FIXME: There is no check for "too many locked pages", currently. + * + * return: 0 if failed (page not in translation table), 1 otherwise + */ +uint32_t mmu_map_data_page_locked(uint32_t virt, uint32_t size, int asid) +{ + const uint32_t size_mask = ~ (SIZE_DEFAULT - 1); /* pagesize */ + int page_index = (virt & size_mask) / SIZE_DEFAULT; /* index into page_descriptor array */ + struct mmu_page_descriptor_ram *page = &pages[page_index]; /* attributes of page to map */ + int i = 0; + + while (page_index * SIZE_DEFAULT < virt + size) + { + if (page->locked) + { + dbg("page at %p is already locked. Nothing to do\r\n", virt); + } + else + { + page->locked = 1; + mmu_map_data_page(virt, 0); + i++; + } + virt += SIZE_DEFAULT; + } + + dbg("%d pages locked\r\n", i); + + return 1; /* success */ +} + +/* + * the opposite: unlock data page(s) with address space id asid from address virt to virt + size_t + * + * return: 0 if failed (page not found), 1 otherwise + */ +uint32_t mmu_unlock_data_page(uint32_t address, uint32_t size, int asid) +{ + int curr_asid; + const uint32_t size_mask = ~ (SIZE_DEFAULT - 1); + int page_index = (address & size_mask) / SIZE_DEFAULT; /* index into page descriptor array */ + struct mmu_page_descriptor_ram *page = &pages[page_index]; + + curr_asid = set_asid(asid); /* set asid to the one to search for */ + + /* TODO: check for pages[] array bounds */ + + while (page_index * SIZE_DEFAULT < address + size) + { + MCF_MMU_MMUAR = address + page->supervisor_protect; + MCF_MMU_MMUOR = MCF_MMU_MMUOR_STLB | /* search TLB */ + MCF_MMU_MMUOR_ADR | + MCF_MMU_MMUOR_RW; + if (MCF_MMU_MMUSR & MCF_MMU_MMUSR_HIT) /* found */ + { +#ifdef DEBUG + uint32_t tlb_aa = MCF_MMU_MMUOR >> 16; /* MMU internal allocation address for TLB */ +#endif /* DBG_MMU */ + + MCF_MMU_MMUDR &= ~MCF_MMU_MMUDR_LK; /* clear lock bit */ + MCF_MMU_MMUOR = MCF_MMU_MMUOR_UAA | + MCF_MMU_MMUOR_ACC; /* update TLB */ + + dbg("DTLB %d unlocked\r\n", tlb_aa); + } + else + { + dbg("%p doesn't seem to be locked??\r\n"); + } + page_index++; + } + set_asid(curr_asid); + + return 1; /* success */ +} + +uint32_t mmu_report_locked_pages(uint32_t *num_itlb, uint32_t *num_dtlb) +{ + int i; + int li = 0; + int ld = 0; + + /* Coldfire V4e allocation addresses run from 0 to 63 */ + + for (i = 0; i < 31; i++) /* 0-31 = ITLB AA */ + { + MCF_MMU_MMUAR = i; + MCF_MMU_MMUOR = MCF_MMU_MMUOR_STLB | + MCF_MMU_MMUOR_ITLB | + MCF_MMU_MMUOR_RW; /* search ITLB */ + + if (MCF_MMU_MMUTR & MCF_MMU_MMUTR_V) + { + /* entry is valid */ + if (MCF_MMU_MMUDR & MCF_MMU_MMUDR_LK) + { + li++; + } + } + + } + for (i = 32; i < 64; i++) /* 32-63 = DTLB AA */ + { + MCF_MMU_MMUAR = i; + MCF_MMU_MMUOR = MCF_MMU_MMUOR_STLB | + MCF_MMU_MMUOR_RW; /* search ITLB */ + + if (MCF_MMU_MMUTR & MCF_MMU_MMUTR_V) + { + /* entry is valid */ + if (MCF_MMU_MMUDR & MCF_MMU_MMUDR_LK) + { + ld++; + } + } + } + + *num_itlb = li; + *num_dtlb = ld; + + return 1; /* success */ +} + +uint32_t mmu_report_pagesize(void) +{ + return SIZE_DEFAULT; +} + diff --git a/sys/startcf.S b/sys/startcf.S new file mode 100644 index 0000000..656296f --- /dev/null +++ b/sys/startcf.S @@ -0,0 +1,76 @@ + +// +// This object file must be the first to be linked, +// so it will be placed at the very beginning of the ROM. +// + + .equ MCF_MMU_MMUCR, __MMUBAR + 0 + + .globl _rom_header + .globl _rom_entry + + .extern _initialize_hardware + .extern _rt_mbar + +/* ROM header */ +_rom_header: + // + // The first long is supposed to be the initial SP. + // We replace it by bra.s to allow running the ROM from the first byte. + // Then we add a fake jmp instruction for pretty disassembly. + // + bra.s _rom_entry // Short jump to the real entry point + .short 0x4ef9 // Fake jmp instruction + // The second long is the initial PC + .long _rom_entry // Real entry point + +/* ROM entry point */ +_rom_entry: + // disable interrupts + move.w #0x2700,sr + +#if !defined(MACHINE_M54455) // MCF54455 does not have the MBAR register + /* Initialize MBAR */ + move.l #__MBAR,d0 + movec d0,MBAR + move.l d0,_rt_mbar +#endif + + /* mmu off */ + move.l #__MMUBAR+1,d0 + movec d0,MMUBAR + + clr.l d0 + move.l d0,MCF_MMU_MMUCR + nop + +#if !defined(MACHINE_M54455) // MCF54455 does not have RAMBAR0 and RAMBAR1 registers */ + + // Initialize RAMBARs: locate SRAM and validate it + move.l #__RAMBAR0 + 0x7,d0 // supervisor only + movec d0,RAMBAR0 + move.l #__RAMBAR1 + 0x1,d0 + movec d0,RAMBAR1 +#else + move.l #__RAMBAR0 + 0x7,d0 + movec d0,RAMBAR +#endif + + // set stack pointer to end of SRAM + lea __SUP_SP,a7 + move.l #0,(sp) + + // Initialize the processor caches. + // The instruction cache is fully enabled. + // The data cache is enabled, but cache-inhibited by default. + // Later, the MMU will fully activate the data cache for specific areas. + // It is important to enable both caches now, otherwise cpushl would hang. + + move.l #0xa50c8120,d0 + movec d0,cacr + andi.l #0xfefbfeff,d0 // Clear invalidate bits + move.l d0,_rt_cacr + + // initialize any hardware specific issues + bra _initialize_hardware + diff --git a/sys/sysinit.c b/sys/sysinit.c new file mode 100644 index 0000000..0b4ec56 --- /dev/null +++ b/sys/sysinit.c @@ -0,0 +1,1147 @@ +/* + * File: sysinit.c + * Purpose: Power-on Reset configuration of the Firebee board. + * + * Notes: + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Copyright 2010 - 2012 F. Aschwanden + * Copyright 2011 - 2012 V. Riviere + * Copyright 2012 M. Froeschle + * + */ + +#include +#include "MCF5475.h" +#include "startcf.h" +#include "cache.h" +#include "sysinit.h" +#include "pci.h" +#include "bas_printf.h" +#include "bas_string.h" +#include "bas_types.h" +#include "wait.h" +#include "util.h" +#include "version.h" +#if defined(MACHINE_FIREBEE) +#include "firebee.h" +#elif defined(MACHINE_M5484LITE) +#include "m5484l.h" +#elif defined(MACHINE_M54455) +#include "m54455.h" +#else +#error "unknown machine" +#endif /* MACHINE_M5484LITE */ +#include "dma.h" +#include "mod_devicetable.h" +#include "pci_ids.h" +#include "driver_mem.h" +#include "usb.h" +#include "video.h" + +// #define DEBUG +#include "debug.h" + +#define UNUSED(x) (void)(x) /* Unused variable */ + +bool fpga_configured = false; /* for FPGA JTAG configuration */ + +extern volatile long _VRAM; /* start address of video ram from linker script */ + +/* + * init SLICE TIMER 0 + * all = 32.538 sec = 30.736mHz + * BYT0 = 127.1ms/tick = 7.876Hz offset 0 + * BYT1 = 496.5us/tick = 2.014kHz offset 1 + * BYT2 = 1.939us/tick = 515.6kHz offset 2 + * BYT3 = 7.576ns/tick = 132.00MHz offset 3/ + * count down!!! 132MHz!!! + */ +static void init_slt(void) +{ + xprintf("slice timer initialization: "); + MCF_SLT0_STCNT = 0xffffffff; + MCF_SLT0_SCR = MCF_SLT_SCR_TEN | MCF_SLT_SCR_RUN; /* enable and run continuously */ + xprintf("finished\r\n"); +} + +/* + * init GPIO general purpose I/O module + */ +static void init_gpio(void) +{ + /* + * pad register P.S.:FBCTL and FBCS set correctly at reset + */ + + /* + * configure all four 547x GPIO module DMA pins: + * + * /DACK1 - DMA acknowledge 1 + * /DACK0 - DMA acknowledge 0 + * /DREQ1 - DMA request 1 + * /DREQ0 - DMA request 0 + * + * for DMA operation + */ + MCF_PAD_PAR_DMA = MCF_PAD_PAR_DMA_PAR_DACK0(0x3) | + MCF_PAD_PAR_DMA_PAR_DACK1(0x3) | + MCF_PAD_PAR_DMA_PAR_DREQ1(0x3) | + MCF_PAD_PAR_DMA_PAR_DREQ0(0x3); + + /* + * configure FEC0 pin assignment on GPIO module as FEC0 + * configure FEC1 pin assignment (PAR_E17, PAR_E1MII) as GPIO, + * /IRQ5 and /IRQ6 from GPIO (needs to be disabled on EPORT module, which also can + * use those INTs). + */ + MCF_PAD_PAR_FECI2CIRQ = MCF_PAD_PAR_FECI2CIRQ_PAR_E07 | + MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII | + MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO | + MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC | + MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO | + MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC | + MCF_PAD_PAR_FECI2CIRQ_PAR_SDA | + MCF_PAD_PAR_FECI2CIRQ_PAR_SCL | + MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ6 | + MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ5; + + /* + * configure PCI Grant pin assignment on GPIO module: + * + * /PCIBG4 used as FlexBus /TBST + * /PCIBG3 used as general purpose I/O + * /PCIBG2 used as /PCIBG2 + * /PCIBG1 used as /PCIBG1 + * /PCIBG0 used as /PCIBG0 + */ +#if defined(MACHINE_FIREBEE) + MCF_PAD_PAR_PCIBG = MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST | + MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO | + MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 | + MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 | + MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0; +#elif defined(MACHINE_M5484LITE) + MCF_PAD_PAR_PCIBG = MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4 | + MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3 | + MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 | + MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 | + MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0; +#endif /* MACHINE_FIREBEE */ + + /* + * configure PCI request pin assignment on GPIO module: + * /PCIBR4 as /IRQ4 + * /PCIBR3 as GPIO (PIC) + * /PCIBR2 as /PCIBR2 + * /PCIBR1 as /PCIBR1 + * /PCIBR0 as /PCIBR0 + */ +#if defined(MACHINE_FIREBEE) + MCF_PAD_PAR_PCIBR = MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4 | + MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO | + MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 | + MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 | + MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0; +#elif defined(MACHINE_M5484LITE) + MCF_PAD_PAR_PCIBR = MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4 | + MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3 | + MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 | + MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 | + MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0; +#endif /* MACHINE_FIREBEE */ + + /* + * configure PSC3 pin assignment on GPIO module: + * /PSC3CTS as /PSC3PTS + * /PSC3RTS as /PSC3RTS + * PSC3RXD as PSC3RXD + * PSC3TXD as PSC3TXD + */ + + MCF_PAD_PAR_PSC3 = MCF_PAD_PAR_PSC3_PAR_TXD3 | MCF_PAD_PAR_PSC3_PAR_RXD3; + + /* + * Configure PSC1 pin assignment on GPIO module: + * - all pins configured for serial interface operation + */ + + MCF_PAD_PAR_PSC1 = MCF_PAD_PAR_PSC1_PAR_CTS1_CTS | + MCF_PAD_PAR_PSC1_PAR_RTS1_RTS | + MCF_PAD_PAR_PSC1_PAR_RXD1 | + MCF_PAD_PAR_PSC1_PAR_TXD1; + + /* + * Configure PSC0 Pin Assignment on GPIO module: + * - all pins configured for serial interface operation + */ + + MCF_PAD_PAR_PSC0 = MCF_PAD_PAR_PSC0_PAR_CTS0_CTS | + MCF_PAD_PAR_PSC0_PAR_RTS0_RTS | + MCF_PAD_PAR_PSC0_PAR_RXD0 | + MCF_PAD_PAR_PSC0_PAR_TXD0; + + /* + * Configure all DSPI pins on the GPIO module for there primary function + */ + MCF_PAD_PAR_DSPI = MCF_PAD_PAR_DSPI_PAR_SOUT(MCF_PAD_PAR_DSPI_PAR_SOUT_SOUT) | + MCF_PAD_PAR_DSPI_PAR_SIN(MCF_PAD_PAR_DSPI_PAR_SIN_SIN) | + MCF_PAD_PAR_DSPI_PAR_SCK(MCF_PAD_PAR_DSPI_PAR_SCK_SCK) | + MCF_PAD_PAR_DSPI_PAR_CS0(MCF_PAD_PAR_DSPI_PAR_CS0_DSPICS0) | + MCF_PAD_PAR_DSPI_PAR_CS2(MCF_PAD_PAR_DSPI_PAR_CS2_DSPICS2) | + MCF_PAD_PAR_DSPI_PAR_CS3(MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3) | + MCF_PAD_PAR_DSPI_PAR_CS5; + + MCF_PAD_PAR_TIMER = MCF_PAD_PAR_TIMER_PAR_TIN3(MCF_PAD_PAR_TIMER_PAR_TIN3_IRQ3) | + MCF_PAD_PAR_TIMER_PAR_TOUT3 | + MCF_PAD_PAR_TIMER_PAR_TIN2(MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2) | + MCF_PAD_PAR_TIMER_PAR_TOUT2; +} + +/* + * init serial + */ +static void init_serial(void) +{ + /* PSC0: SER1 */ + MCF_PSC0_PSCSICR = 0; /* PSC control register: select UART mode */ + MCF_PSC0_PSCCSR = 0xDD; /* use TX and RX baud rate from PSC timer */ + MCF_PSC0_PSCCTUR = 0x00; /* =\ */ +#if defined(MACHINE_FIREBEE) + MCF_PSC0_PSCCTLR = 36; /* divide sys_clk by 36 => BAUD RATE = 115200 bps */ +#endif +#if defined(MACHINE_M5484LITE) + MCF_PSC0_PSCCTLR = 27; /* LITE board has 100 MHz sys_clk only */ +#endif + MCF_PSC0_PSCCR = 0x20; /* reset receiver and RxFIFO */ + MCF_PSC0_PSCCR = 0x30; /* reset transmitter and TxFIFO */ + MCF_PSC0_PSCCR = 0x40; /* reset all error status */ + MCF_PSC0_PSCCR = 0x50; /* reset break change interrupt */ + MCF_PSC0_PSCCR = 0x10; /* reset MR pointer */ + MCF_PSC0_PSCIMR = 0x8700; /* enable input port change interrupt, enable delta break interrupt, */ + /* enable receiver interrupt/request, enable transceiver interrupt/request */ + + MCF_PSC0_PSCACR = 0x03; /* enable state change of CTS */ + MCF_PSC0_PSCMR1 = 0xb3; /* 8 bit, no parity */ + MCF_PSC0_PSCMR2 = 0x07; /* 1 stop bit */ + MCF_PSC0_PSCRFCR = 0x0F; + MCF_PSC0_PSCTFCR = 0x0F; + MCF_PSC0_PSCRFAR = 0x00F0; + MCF_PSC0_PSCTFAR = 0x00F0; + MCF_PSC0_PSCOPSET = 0x01; + MCF_PSC0_PSCCR = 0x05; + +#if defined(MACHINE_FIREBEE) /* PSC3 is not connected to anything on the LITE board */ + /* PSC3: PIC */ + MCF_PSC3_PSCSICR = 0; // UART + MCF_PSC3_PSCCSR = 0xDD; + MCF_PSC3_PSCCTUR = 0x00; + MCF_PSC3_PSCCTLR = 36; // BAUD RATE = 115200 + MCF_PSC3_PSCCR = 0x20; + MCF_PSC3_PSCCR = 0x30; + MCF_PSC3_PSCCR = 0x40; + MCF_PSC3_PSCCR = 0x50; + MCF_PSC3_PSCCR = 0x10; + MCF_PSC3_PSCIMR = 0x0200; // receiver interrupt enable + MCF_PSC3_PSCACR = 0x03; + MCF_PSC3_PSCMR1 = 0xb3; + MCF_PSC3_PSCMR2 = 0x07; + MCF_PSC3_PSCRFCR = 0x0F; + MCF_PSC3_PSCTFCR = 0x0F; + MCF_PSC3_PSCRFAR = 0x00F0; + MCF_PSC3_PSCTFAR = 0x00F0; + MCF_PSC3_PSCOPSET = 0x01; + MCF_PSC3_PSCCR = 0x05; +#endif /* MACHINE_FIREBEE */ + + xprintf("\r\nserial interfaces initialization: finished\r\n"); +} + +/********************************************************************/ +/* Initialize DDR DIMMs on the EVB board */ +/********************************************************************/ +static bool init_ddram(void) +{ + xprintf("SDRAM controller initialization: "); + + /* + * Check to see if the SDRAM has already been initialized + * by a run control tool + */ + if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) { + /* Basic configuration and initialization */ + + /* + * SB_E (Bits 9-8): 10 <=> 7.6 mA (SDCKE) + * SB_C (Bits 7-6): 10 <=> 7.6 mA (SDRAM Clocks) + * SB_A (Bits 5-4): 10 <=> 7.6 mA (RAS, CAS, SDWE, SDADDR[12:0], and SDBA) + * SB_S (Bits 3-2): 10 <=> 7.6 mA (SDRDQS) + * SB_D (Bits 1-0): 10 <=> 7.6 mA (SDRDQS) + * + * -> lowest setting the Coldfire SDRAM controller allows + */ + MCF_SDRAMC_SDRAMDS = 0x000002AA;/* SDRAMDS configuration */ + +#if defined(MACHINE_FIREBEE) + MCF_SDRAMC_CS0CFG = 0x0000001A; /* SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) */ + MCF_SDRAMC_CS1CFG = 0x0800001A; /* SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) */ + MCF_SDRAMC_CS2CFG = 0x1000001A; /* SDRAM CS2 configuration (128Mbytes 1000_0000 - 07FF_FFFF) */ + MCF_SDRAMC_CS3CFG = 0x1800001A; /* SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) */ + + /* + * + */ + MCF_SDRAMC_SDCFG1 = MCF_SDRAMC_SDCFG1_WTLAT(3) /* Write latency */ + | MCF_SDRAMC_SDCFG1_REF2ACT(8) /* Refresh to Active Delay */ + | MCF_SDRAMC_SDCFG1_PRE2ACT(2) /* Precharge to Active Delay */ + | MCF_SDRAMC_SDCFG1_ACT2RW(2) /* Active to Read/Write Delay */ + | MCF_SDRAMC_SDCFG1_RDLAT(6) /* Read CAS latency */ + | MCF_SDRAMC_SDCFG1_SWT2RD(3) /* Single Write to Read/Write/Precharge delay */ + | MCF_SDRAMC_SDCFG1_SRD2RW(7); /* Single Read to Read/Write/Precharge delay */ + + MCF_SDRAMC_SDCFG2 = MCF_SDRAMC_SDCFG2_BL(7) /* Burst Length */ + | MCF_SDRAMC_SDCFG2_BRD2WT(7) /* Burst Read to Write delay */ + | MCF_SDRAMC_SDCFG2_BWT2RW(6) /* Burst Write to Read/Write/Precharge delay */ + | MCF_SDRAMC_SDCFG2_BRD2PRE(4); /* Burst Read to Read/Precharge delay */ + + + MCF_SDRAMC_SDCR = MCF_SDRAMC_SDCR_IPALL /* initiate Precharge All command */ + | MCF_SDRAMC_SDCR_RCNT(13) /* Refresh Count (= (x + 1) * 64 */ + | MCF_SDRAMC_SDCR_MUX(1) /* Muxing control */ + | MCF_SDRAMC_SDCR_DDR + | MCF_SDRAMC_SDCR_CKE + | MCF_SDRAMC_SDCR_MODE_EN; + + MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_CMD /* Generate an LMR/LEMR command */ + | MCF_SDRAMC_SDMR_AD(0) /* Address */ + | MCF_SDRAMC_SDMR_BNKAD(1); /* LEMR */ + MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_CMD /* Generate an LMR/LEMR command */ + | MCF_SDRAMC_SDMR_AD(0x123) + | MCF_SDRAMC_SDMR_BNKAD(0); /* LMR */ + + MCF_SDRAMC_SDCR = 0xE10D0002; /* SDCR + IPALL */ + MCF_SDRAMC_SDCR = 0xE10D0004; /* SDCR + IREF (first refresh) */ + MCF_SDRAMC_SDCR = 0xE10D0004; /* SDCR + IREF (second refresh) */ + MCF_SDRAMC_SDMR = 0x008D0000; /* SDMR (write to LMR) */ + MCF_SDRAMC_SDCR = 0x710D0F00; /* SDCR (lock SDMR and enable refresh) */ + +#elif defined(MACHINE_M5484LITE) + MCF_SDRAMC_CS0CFG = 0x00000019; /* SDRAM CS0 configuration (64 Mbytes 0000_0000 - 03FF_FFFF) */ + MCF_SDRAMC_CS1CFG = 0x00000000; /* SDRAM CS1 configuration - off */ + MCF_SDRAMC_CS2CFG = 0x00000000; /* SDRAM CS2 configuration - off */ + MCF_SDRAMC_CS3CFG = 0x00000000; /* SDRAM CS3 configuration - off */ + + + /* + * + */ + MCF_SDRAMC_SDCFG1 = MCF_SDRAMC_SDCFG1_WTLAT(3) /* Write latency */ + | MCF_SDRAMC_SDCFG1_REF2ACT(8) /* Refresh to Active Delay */ + | MCF_SDRAMC_SDCFG1_PRE2ACT(2) /* Precharge to Active Delay */ + | MCF_SDRAMC_SDCFG1_ACT2RW(2) /* Active to Read/Write Delay */ + | MCF_SDRAMC_SDCFG1_RDLAT(6) /* Read CAS latency */ + | MCF_SDRAMC_SDCFG1_SWT2RD(3) /* Single Write to Read/Write/Precharge delay */ + | MCF_SDRAMC_SDCFG1_SRD2RW(7); /* Single Read to Read/Write/Precharge delay */ + + MCF_SDRAMC_SDCFG2 = MCF_SDRAMC_SDCFG2_BL(7) /* Burst Length */ + | MCF_SDRAMC_SDCFG2_BRD2WT(7) /* Burst Read to Write delay */ + | MCF_SDRAMC_SDCFG2_BWT2RW(6) /* Burst Write to Read/Write/Precharge delay */ + | MCF_SDRAMC_SDCFG2_BRD2PRE(4); /* Burst Read to Read/Precharge delay */ + + + MCF_SDRAMC_SDCR = MCF_SDRAMC_SDCR_IPALL /* initiate Precharge All command */ + | MCF_SDRAMC_SDCR_RCNT(13) /* Refresh Count (= (x + 1) * 64 */ + | MCF_SDRAMC_SDCR_MUX(1) /* Muxing control */ + | MCF_SDRAMC_SDCR_DDR + | MCF_SDRAMC_SDCR_CKE + | MCF_SDRAMC_SDCR_MODE_EN; + + MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_CMD /* Generate an LMR/LEMR command */ + | MCF_SDRAMC_SDMR_AD(0) /* Address */ + | MCF_SDRAMC_SDMR_BNKAD(1); /* LEMR */ + MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_CMD /* Generate an LMR/LEMR command */ + | MCF_SDRAMC_SDMR_AD(0x123) + | MCF_SDRAMC_SDMR_BNKAD(0); /* LMR */ + + MCF_SDRAMC_SDCR = 0xE10D0002; /* SDCR + IPALL */ + MCF_SDRAMC_SDCR = 0xE10D0004; /* SDCR + IREF (first refresh) */ + MCF_SDRAMC_SDCR = 0xE10D0004; /* SDCR + IREF (second refresh) */ + MCF_SDRAMC_SDMR = 0x008D0000; /* SDMR (write to LMR) */ + MCF_SDRAMC_SDCR = 0x710D0F00; /* SDCR (lock SDMR and enable refresh) */ + +#endif /* MACHINE_FIREBEE */ + + xprintf("finished\r\n"); + + return true; + } + else + { + xprintf("skipped. Already initialized (running from RAM)\r\n"); + } + return false; +} + +/* + * initialize FlexBus chip select registers + */ +static void init_fbcs() +{ + xprintf("FlexBus chip select registers initialization: "); + + /* Flash */ + MCF_FBCS0_CSAR = MCF_FBCS_CSAR_BA(BOOTFLASH_BASE_ADDRESS); /* flash base address */ + MCF_FBCS0_CSCR = MCF_FBCS_CSCR_PS_16 | /* 16 bit word access */ + MCF_FBCS_CSCR_WS(8)| /* 6 wait states */ + MCF_FBCS_CSCR_AA | /* auto /TA acknowledge */ + MCF_FBCS_CSCR_ASET(1) | /* assert chip select on second rising edge after address assertion */ + MCF_FBCS_CSCR_RDAH(1); /* chip errata SECF077 */ + MCF_FBCS0_CSMR = BOOTFLASH_BAM | + MCF_FBCS_CSMR_V; /* enable */ + + +#if defined(MACHINE_FIREBEE) /* FBC setup for FireBee */ + MCF_FBCS1_CSAR = MCF_FBCS_CSAR_BA(0xFFF00000); /* ATARI I/O address range */ + MCF_FBCS1_CSCR = MCF_FBCS_CSCR_PS_16 /* 16BIT PORT */ + | MCF_FBCS_CSCR_WS(32) /* 32 wait states */ +// | MCF_FBCS_CSCR_BSTR /* burst read enable */ +// | MCF_FBCS_CSCR_BSTW /* burst write enable */ + | MCF_FBCS_CSCR_AA; /* auto /TA acknowledge */ + MCF_FBCS1_CSMR = MCF_FBCS_CSMR_BAM_1M | MCF_FBCS_CSMR_V; + + MCF_FBCS2_CSAR = MCF_FBCS_CSAR_BA(0xF0000000); /* Firebee new I/O address range */ + MCF_FBCS2_CSCR = MCF_FBCS_CSCR_PS_32 /* 32BIT PORT */ + | MCF_FBCS_CSCR_WS(32) /* 4 wait states */ + | MCF_FBCS_CSCR_AA; /* auto /TA acknowledge */ + MCF_FBCS2_CSMR = (MCF_FBCS_CSMR_BAM_128M /* F000'0000-F7FF'FFFF */ + | MCF_FBCS_CSMR_V); + + MCF_FBCS3_CSAR = MCF_FBCS_CSAR_BA(0xF8000000); /* Firebee SRAM */ + MCF_FBCS3_CSCR = MCF_FBCS_CSCR_PS_16 /* 16 bit port */ + | MCF_FBCS_CSCR_WS(32) /* 0 wait states */ + | MCF_FBCS_CSCR_AA; /* auto /TA acknowledge */ + MCF_FBCS3_CSMR = (MCF_FBCS_CSMR_BAM_64M /* F800'0000-FBFF'FFFF */ + | MCF_FBCS_CSMR_V); + + /* + * Note: burst read/write settings of the following FBCS are purely "cosmetical". + * The Coldfire FlexBus only "bursts" on a smaller port size than 32 bit up to 32 bit, + * i.e. it can burst on an 8 bit port up to 4 burst cycles or two on a 16 bit port. + * Enabling burst on a 32 bit port has no effect (unfortunately). + */ + MCF_FBCS4_CSAR = MCF_FBCS_CSAR_BA(0x40000000); /* video ram area, FB_CS4 not used, decoded on FPGA */ + MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32 /* 32 bit port */ + | MCF_FBCS_CSCR_WS(32) /* 0 wait states */ + | MCF_FBCS_CSCR_AA /* /TA auto acknowledge */ + | MCF_FBCS_CSCR_BSTR /* burst read enable */ + | MCF_FBCS_CSCR_BSTW; /* burst write enable */ + MCF_FBCS4_CSMR = MCF_FBCS_CSMR_BAM_1G /* 4000'0000-7FFF'FFFF */ + | MCF_FBCS_CSMR_V; + + /* disable FBCS5 on Firebee */ + MCF_FBCS5_CSAR = 0x0; + MCF_FBCS5_CSCR = MCF_FBCS_CSCR_PS_8 + | MCF_FBCS_CSCR_BSTR + | MCF_FBCS_CSCR_BSTW + | MCF_FBCS_CSCR_RDAH(1); /* chip errata SECF077 */ + MCF_FBCS5_CSMR = MCF_FBCS_CSMR_BAM_1G; + //| MCF_FBCS_CSMR_V; +#elif defined(MACHINE_M5484LITE) + /* disable other FBCS for now */ + MCF_FBCS1_CSMR = 0; + MCF_FBCS2_CSMR = 0; + MCF_FBCS3_CSMR = 0; + MCF_FBCS4_CSMR = 0; + + /* + * the FireEngine needs AA for its CPLD accessed registers + */ + MCF_FBCS5_CSAR = MCF_FBCS_CSAR_BA(0x60000000); + MCF_FBCS5_CSCR = MCF_FBCS_CSCR_PS_16 | /* CPLD access 16 bit wide */ + MCF_FBCS_CSCR_WS(32) | /* 32 wait states */ + MCF_FBCS_CSCR_ASET(1) | /* chip select on second rising clock edge */ + MCF_FBCS_CSCR_AA; /* auto acknowledge */ + MCF_FBCS5_CSMR = MCF_FBCS_CSMR_BAM_256M | /* maps 0x60000000 to 0x68000000 */ + MCF_FBCS_CSMR_V; +#endif /* MACHINE_FIREBEE */ + + xprintf("finished\r\n"); +} + +#ifdef MACHINE_FIREBEE +static void wait_pll(void) +{ + int32_t trgt = MCF_SLT0_SCNT - 100000; + do + { + ; + } while ((* (volatile int16_t *) 0xf0000800 < 0) && MCF_SLT0_SCNT > trgt); +} + +static volatile uint8_t *pll_base = (volatile uint8_t *) 0xf0000600; + +static void init_pll(void) +{ + xprintf("FPGA PLL initialization: "); + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x48) = 27; /* loopfilter r */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x08) = 1; /* charge pump 1 */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x00) = 12; /* N counter high = 12 */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x40) = 12; /* N counter low = 12 */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x114) = 1; /* ck1 bypass */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x118) = 1; /* ck2 bypass */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x11c) = 1; /* ck3 bypass */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x10) = 1; /* ck0 high = 1 */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x50) = 1; /* ck0 low = 1 */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x144) = 1; /* M odd division */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x44) = 1; /* M low = 1 */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x04) = 145; /* M high = 145 = 146 MHz */ + + wait_pll(); + + * (volatile uint8_t *) 0xf0000800 = 0; /* set */ + + xprintf("finished\r\n"); +} + +/* + * INIT VIDEO DDR RAM + */ +static void init_video_ddr(void) { + xprintf("init video RAM: "); + + * (volatile uint16_t *) 0xf0000400 = 0xb; /* set cke = 1, cs=1, config = 1 */ + NOP(); + + _VRAM = 0x00050400; /* IPALL */ + NOP(); + + _VRAM = 0x00072000; /* load EMR pll on */ + NOP(); + + _VRAM = 0x00070122; /* load MR: reset pll, cl=2, burst=4lw */ + NOP(); + + _VRAM = 0x00050400; /* IPALL */ + NOP(); + + _VRAM = 0x00060000; /* auto refresh */ + NOP(); + + _VRAM = 0x00060000; /* auto refresh */ + NOP(); + + /* FIXME: what's this? */ + _VRAM = 0000070022; /* load MR dll on */ + NOP(); + + * (uint32_t *) 0xf0000400 = 0x01070082; /* fifo on, refresh on, ddrcs und cke on, video dac on, Falcon shift mode on */ + + xprintf("finished\r\n"); +} +#endif /* MACHINE_FIREBEE */ + +/* + * probe for NEC compatible USB host controller and install if found + */ +void init_usb(void) +{ + extern struct pci_device_id ohci_usb_pci_table[]; + extern struct pci_device_id ehci_usb_pci_table[]; + struct pci_device_id *board; + int32_t handle; + int usb_found = 0; + int index = 0; + + /* + * disabled for now + */ + return; + + inf("USB controller initialization:\r\n"); + + do + { + handle = pci_find_classcode(PCI_CLASS_SERIAL_USB | PCI_FIND_BASE_CLASS | PCI_FIND_SUB_CLASS, index++); + dbg("handle 0x%02x\r\n", handle); + if (handle > 0) + { + long id; + long pci_class; + + xprintf("serial USB found at bus=0x%x, dev=0x%x, fnc=0x%x (0x%x)\r\n", + PCI_BUS_FROM_HANDLE(handle), + PCI_DEVICE_FROM_HANDLE(handle), + PCI_FUNCTION_FROM_HANDLE(handle), + handle); + id = swpl(pci_read_config_longword(handle, PCIIDR)); + pci_class = swpl(pci_read_config_longword(handle, PCIREV)); + + if (pci_class >> 8 == PCI_CLASS_SERIAL_USB_EHCI) + { + board = ehci_usb_pci_table; + while (board->vendor) + { + if ((board->vendor == PCI_VENDOR_ID(id)) && board->device == PCI_DEVICE_ID(id)) + { + if (usb_init(handle, board) >= 0) + { + usb_found++; + } + } + board++; + } + } + if (pci_class >> 8 == PCI_CLASS_SERIAL_USB_OHCI) + { + board = ohci_usb_pci_table; + while (board->vendor) + { + if ((board->vendor == PCI_VENDOR_ID(id)) && board->device == PCI_DEVICE_ID(id)) + { + if (usb_init(handle, board) >= 0) + usb_found++; + } + board++; + } + } + } + } while (handle >= 0); + + xprintf("finished (found %d USB controller(s))\r\n", usb_found); +} + +#if defined(MACHINE_FIREBEE) + +static bool i2c_transfer_finished(void) +{ + if (MCF_I2C_I2SR & MCF_I2C_I2SR_IIF) + return true; + + return false; +} + +static void wait_i2c_transfer_finished(void) +{ + waitfor(1000, i2c_transfer_finished); /* wait until interrupt bit has been set */ + MCF_I2C_I2SR &= ~MCF_I2C_I2SR_IIF; /* clear interrupt bit (byte transfer finished */ +} + +static bool i2c_bus_free(void) +{ + return (MCF_I2C_I2SR & MCF_I2C_I2SR_IBB); +} + +/* + * TFP410 (DVI) on + */ +static void dvi_on(void) +{ + uint8_t receivedByte; + uint8_t dummyByte; /* only used for a dummy read */ + int num_tries = 0; + + xprintf("DVI digital video output initialization: "); + + MCF_I2C_I2FDR = 0x3c; /* divide system clock by 1280: 100kHz standard */ + + do + { + /* disable all i2c interrupt routing targets */ + MCF_I2C_I2ICR = 0x0; // ~(MCF_I2C_I2ICR_IE | MCF_I2C_I2ICR_RE | MCF_I2C_I2ICR_TE | MCF_I2C_I2ICR_BNBE); + + /* disable i2c, disable i2c interrupts, slave, receive, i2c = acknowledge, no repeat start */ + MCF_I2C_I2CR = 0x0; + + /* repeat start, transmit acknowledge */ + MCF_I2C_I2CR = MCF_I2C_I2CR_RSTA | MCF_I2C_I2CR_TXAK; + + receivedByte = MCF_I2C_I2DR; /* read a byte */ + MCF_I2C_I2SR = 0x0; /* clear status register */ + MCF_I2C_I2CR = 0x0; /* clear control register */ + + MCF_I2C_I2ICR = MCF_I2C_I2ICR_IE; /* route i2c interrupts to cpu */ + + /* i2c enable, master mode, transmit acknowledge */ + MCF_I2C_I2CR = MCF_I2C_I2CR_IEN | MCF_I2C_I2CR_MSTA | MCF_I2C_I2CR_MTX; + + MCF_I2C_I2DR = 0x7a; /* send data: address of TFP410 */ + wait_i2c_transfer_finished(); + + if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) /* next try if no acknowledge */ + goto try_again; + + MCF_I2C_I2DR = 0x00; /* send data: SUB ADRESS 0 */ + wait_i2c_transfer_finished(); + + MCF_I2C_I2CR |= MCF_I2C_I2CR_RSTA; /* repeat start */ + MCF_I2C_I2DR = 0x7b; /* begin read */ + + wait_i2c_transfer_finished(); + if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) /* next try if no acknowledge */ + goto try_again; + +#ifdef _NOT_USED_ + MCH_I2C_I2CR &= ~MCF_I2C_I2CR_MTX; /* FIXME: not clear where this came from ... */ +#endif /* _NOT_USED_ */ + MCF_I2C_I2CR &= 0xef; /* ... this actually disables the I2C module... */ + dummyByte = MCF_I2C_I2DR; /* dummy read */ + + wait_i2c_transfer_finished(); + + MCF_I2C_I2CR |= MCF_I2C_I2CR_TXAK; /* transmit acknowledge enable */ + receivedByte = MCF_I2C_I2DR; /* read a byte */ + + wait_i2c_transfer_finished(); + + MCF_I2C_I2CR = MCF_I2C_I2CR_IEN; /* stop */ + + dummyByte = MCF_I2C_I2DR; // dummy read + + if (receivedByte != 0x4c) + goto try_again; + + MCF_I2C_I2CR = 0x0; // stop + MCF_I2C_I2SR = 0x0; // clear sr + + waitfor(10000, i2c_bus_free); + + MCF_I2C_I2CR = 0xb0; // on tx master + MCF_I2C_I2DR = 0x7A; + + wait_i2c_transfer_finished(); + + if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) + goto try_again; + + MCF_I2C_I2DR = 0x08; // SUB ADRESS 8 + + wait_i2c_transfer_finished(); + + MCF_I2C_I2DR = 0xbf; // ctl1: power on, T:M:D:S: enable + + wait_i2c_transfer_finished(); + + MCF_I2C_I2CR = 0x80; // stop + dummyByte = MCF_I2C_I2DR; // dummy read + MCF_I2C_I2SR = 0x0; // clear sr + + waitfor(10000, i2c_bus_free); + + MCF_I2C_I2CR = 0xb0; + MCF_I2C_I2DR = 0x7A; + + wait_i2c_transfer_finished(); + + if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) + goto try_again; + + MCF_I2C_I2DR = 0x08; // SUB ADRESS 8 + + wait_i2c_transfer_finished(); + + MCF_I2C_I2CR |= 0x4; // repeat start + MCF_I2C_I2DR = 0x7b; // beginn read + + wait_i2c_transfer_finished(); + + if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) + goto try_again; + + MCF_I2C_I2CR &= 0xef; // switch to rx + dummyByte = MCF_I2C_I2DR; // dummy read + + wait_i2c_transfer_finished(); + MCF_I2C_I2CR |= 0x08; // txak=1 + + wait(50); + + receivedByte = MCF_I2C_I2DR; + + wait_i2c_transfer_finished(); + + MCF_I2C_I2CR = 0x80; // stop + + dummyByte = MCF_I2C_I2DR; // dummy read + +try_again: + num_tries++; + } while ((receivedByte != 0xbf) && (num_tries < 10)); + + if (num_tries >= 10) + { + xprintf("FAILED!\r\n"); + } + else + { + xprintf("finished\r\n"); + } + UNUSED(dummyByte); + // Avoid warning +} + + +/* + * AC97 + */ +static void init_ac97(void) +{ + // PSC2: AC97 ---------- + int i; + int zm; + int va; + int vb; + int vc; + + xprintf("AC97 sound chip initialization: "); + MCF_PAD_PAR_PSC2 = MCF_PAD_PAR_PSC2_PAR_RTS2_RTS // PSC2=TX,RX BCLK,CTS->AC'97 + | MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK + | MCF_PAD_PAR_PSC2_PAR_TXD2 + | MCF_PAD_PAR_PSC2_PAR_RXD2; + MCF_PSC2_PSCMR1 = 0x0; + MCF_PSC2_PSCMR2 = 0x0; + MCF_PSC2_PSCIMR = 0x0300; + MCF_PSC2_PSCSICR = 0x03; //AC97 + MCF_PSC2_PSCRFCR = 0x0f000000; + MCF_PSC2_PSCTFCR = 0x0f000000; + MCF_PSC2_PSCRFAR = 0x00F0; + MCF_PSC2_PSCTFAR = 0x00F0; + + for (zm = 0; zm < 100000; zm++) // wiederholen bis synchron + { + MCF_PSC2_PSCCR = 0x20; + MCF_PSC2_PSCCR = 0x30; + MCF_PSC2_PSCCR = 0x40; + MCF_PSC2_PSCCR = 0x05; + + // MASTER VOLUME -0dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x02000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + + for (i = 2; i < 13; i++) + { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } + + // read register + MCF_PSC2_PSCTB_AC97 = 0xc0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x82000000; //SLOT1:master volume + + for (i = 2; i < 13; i++) + { + MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT2-12:RD REG ALLES 0 + } + wait(50); + + va = MCF_PSC2_PSCTB_AC97; + if ((va & 0x80000fff) == 0x80000800) { + vb = MCF_PSC2_PSCTB_AC97; + vc = MCF_PSC2_PSCTB_AC97; + + /* FIXME: that looks more than suspicious (Fredi?) */ + /* fixed with parentheses to avoid compiler warnings, but this looks still more than wrong to me */ + if (((va & 0xE0000fff) == 0xE0000800) & (vb == 0x02000000) & (vc == 0x00000000)) { + goto livo; + } + } + } + xprintf(" NOT"); +livo: + // AUX VOLUME ->-0dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x16000000; //SLOT1:WR REG AUX VOLUME adr 0x16 + MCF_PSC2_PSCTB_AC97 = 0x06060000; //SLOT1:VOLUME + for (i = 3; i < 13; i++) { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } + + // line in VOLUME +12dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x10000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + for (i = 2; i < 13; i++) { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } + // cd in VOLUME 0dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x12000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + for (i = 2; i < 13; i++) { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } + // mono out VOLUME 0dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x06000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + for (i = 3; i < 13; i++) { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } + MCF_PSC2_PSCTFCR |= MCF_PSC_PSCTFCR_WFR; //set EOF + MCF_PSC2_PSCTB_AC97 = 0x00000000; //last data + xprintf(" finished\r\n"); +} +#endif /* MACHINE_FIREBEE */ + +/* Symbols from the linker script */ + +extern uint8_t _STRAM_END[]; +#define STRAM_END ((uint32_t)_STRAM_END) + +extern uint8_t _FIRETOS[]; +#define FIRETOS ((uint32_t)_FIRETOS) /* where FireTOS is stored in flash */ + +extern uint8_t _BAS_LMA[]; +#define BAS_LMA (&_BAS_LMA[0]) /* where the BaS is stored in flash */ + +extern uint8_t _BAS_IN_RAM[]; +#define BAS_IN_RAM (&_BAS_IN_RAM[0]) /* where the BaS is run in RAM */ + +extern uint8_t _BAS_SIZE[]; +#define BAS_SIZE ((uint32_t)_BAS_SIZE) /* size of the BaS, in bytes */ + +extern uint8_t _FASTRAM_END[]; +#define FASTRAM_END ((uint32_t)_FASTRAM_END) + +extern uint8_t _BAS_RESIDENT_TEXT[]; +#define BAS_RESIDENT_TEXT ((uint32_t) _BAS_RESIDENT_TEXT) + +extern uint8_t _BAS_RESIDENT_TEXT_SIZE[]; +#define BAS_RESIDENT_TEXT_SIZE ((uint32_t) _BAS_RESIDENT_TEXT_SIZE) + +static void clear_bss_segment(void) +{ + extern uint8_t _BAS_BSS_START[]; + uint8_t * BAS_BSS_START = &_BAS_BSS_START[0]; + extern uint8_t _BAS_BSS_END[]; + uint8_t *BAS_BSS_END = &_BAS_BSS_END[0]; + + bzero(BAS_BSS_START, BAS_BSS_END - BAS_BSS_START + 1); +} + +void initialize_hardware(void) +{ + /* Test for FireTOS switch: DIP switch #5 up */ +#ifdef _NOT_USED_ // #if defined(MACHINE_FIREBEE) + if (!(DIP_SWITCH & (1 << 6))) { + /* Minimal hardware initialization */ + init_gpio(); + init_serial(); + init_slt(); + init_fbcs(); + init_ddram(); + init_fpga(); + + /* Validate ST RAM */ + * (volatile uint32_t *) 0x42e = STRAM_END; /* phystop TOS system variable */ + * (volatile uint32_t *) 0x420 = 0x752019f3; /* memvalid TOS system variable */ + * (volatile uint32_t *) 0x43a = 0x237698aa; /* memval2 TOS system variable */ + * (volatile uint32_t *) 0x51a = 0x5555aaaa; /* memval3 TOS system variable */ + + /* TT-RAM */ + + xprintf("FASTRAM_END = %p\r\n", FASTRAM_END); + * (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */ + * (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */ + + /* Jump into FireTOS */ + typedef void void_func(void); + void_func* FireTOS = (void_func*) FIRETOS; + FireTOS(); // Should never return + return; + } +#endif /* MACHINE_FIREBEE */ + init_gpio(); + init_serial(); + + xprintf("\n\n"); + xprintf("%s BASIS system (BaS) v %d.%d (%s, %s)\r\n\r\n", +#if defined(MACHINE_FIREBEE) + "Firebee" +#elif MACHINE_M5484LITE + "m5484 LITEKIT" +#else + "unknown platform" +#endif + , MAJOR_VERSION, MINOR_VERSION, __DATE__, __TIME__); + + /* + * Determine cause(s) of Reset + */ + if (MCF_SIU_RSR & MCF_SIU_RSR_RST) + xprintf("Reset. Cause: External Reset\r\n"); + if (MCF_SIU_RSR & MCF_SIU_RSR_RSTWD) + xprintf("Reset. Cause: Watchdog Timer Reset\n"); + if (MCF_SIU_RSR & MCF_SIU_RSR_RSTJTG) + xprintf("Reset. Cause: BDM/JTAG Reset\r\n"); + + /* + * Clear the Reset Status Register + */ + MCF_SIU_RSR = (MCF_SIU_RSR_RST + | MCF_SIU_RSR_RSTWD + | MCF_SIU_RSR_RSTJTG); + + /* + * Determine which processor we are running on + */ + xprintf("JTAGID: "); + switch (MCF_SIU_JTAGID & MCF_SIU_JTAGID_PROCESSOR) + { + case MCF_SIU_JTAGID_MCF5485: + xprintf("MCF5485"); + break; + case MCF_SIU_JTAGID_MCF5484: + xprintf("MCF5484"); + break; + case MCF_SIU_JTAGID_MCF5483: + xprintf("MCF5483"); + break; + case MCF_SIU_JTAGID_MCF5482: + xprintf("MCF5482"); + break; + case MCF_SIU_JTAGID_MCF5481: + xprintf("MCF5481"); + break; + case MCF_SIU_JTAGID_MCF5480: + xprintf("MCF5480"); + break; + case MCF_SIU_JTAGID_MCF5475: + xprintf("MCF5475"); + break; + case MCF_SIU_JTAGID_MCF5474: + xprintf("MCF5474"); + break; + case MCF_SIU_JTAGID_MCF5473: + xprintf("MCF5473"); + break; + case MCF_SIU_JTAGID_MCF5472: + xprintf("MCF5472"); + break; + case MCF_SIU_JTAGID_MCF5471: + xprintf("MCF5471"); + break; + case MCF_SIU_JTAGID_MCF5470: + xprintf("MCF5470"); + break; + } + + /* + * Determine the processor revision + */ + xprintf(" (revision %d)\r\n", ((MCF_SIU_JTAGID & MCF_SIU_JTAGID_REV) >> 28)); + + /* make sure MMU is disabled */ + MCF_MMU_MMUCR = 0; /* MMU off */ + NOP(); /* force pipeline sync */ + + init_slt(); + init_fbcs(); + init_ddram(); + +#if defined(MACHINE_M5484LITE) + dbg("Fire Engine Control register: %02x\r\n", * (uint8_t *) 0x61000000); + dbg("Fire Engine interrupt register: %02x\r\n", * (uint8_t *) 0x62000000); + dbg("Fire Engine interrupt mask register: %02x\r\n", * (uint8_t *) 0x63000000); + dbg("Fire Engine power management register: %02x\r\n", * (uint8_t *) 0x64000000); + dbg("Fire Engine EEPROM SPI register: %02x\r\n", * (uint8_t *) 0x65000000); + dbg("Fire Engine Flash register: %02x\r\n", * (uint8_t *) 0x66000000); + dbg("Fire Engine CPLD revision register: %02x\r\n", * (uint8_t *) 0x67000000); + dbg("Fire Engine Hardware revision register:%02x\r\n", * (uint8_t *) 0x68000000); + + dbg("write control register 0x%02x\r\n", 1 << 7); + * (uint8_t *) 0x61000000 = 1 << 7; + dbg("Fire Engine Control register: %02x\r\n", * (uint8_t *) 0x61000000); +#endif /* MACHINE_M5484LITE */ + + /* + * install (preliminary) exception vectors + */ + setup_vectors(); + +#ifdef _NOT_USED_ + /* make sure the handlers are called */ + __asm__ __volatile__("dc.w 0xafff"); /* should trigger a line-A exception */ +#endif /* _NOT_USED_ */ + + + /* + * save the planet (and reduce case heat): disable clocks of unused SOC modules + */ + MCF_CLOCK_SPCR = 0xffffffff & ~( + 0 | /* leave memory clock enabled */ + 0 | /* leave PCI clock enabled */ + 0 | /* leave FlexBus clock enabled */ + MCF_CLOCK_SPCR_CAN0EN | /* disable CAN0 */ + 0 | /* leave DMA clock enabled */ + 0 | /* leave FEC0 clock enabled */ + MCF_CLOCK_SPCR_FEC1EN | /* disable FEC1 */ + MCF_CLOCK_SPCR_USBEN | /* disable USB slave */ + 0 | /* leave PSC clock enabled */ + MCF_CLOCK_SPCR_CAN1EN | /* disable CAN1 */ + MCF_CLOCK_SPCR_CRYENA | /* disable crypto clock A */ + MCF_CLOCK_SPCR_CRYENB | /* disable crypto clock B */ + 0 /* leave core clock enabled */ + ); + + /* the following only makes sense _after_ DDRAM has been initialized */ + clear_bss_segment(); + xprintf(".bss segment cleared\r\n"); + + if (BAS_LMA != BAS_IN_RAM) + { + memcpy((void *) BAS_IN_RAM, BAS_LMA, BAS_SIZE); + + /* we have copied a code area, so flush the caches */ + flush_and_invalidate_caches(); + + } + +#if defined(MACHINE_FIREBEE) + fpga_configured = init_fpga(); + + init_pll(); + init_video_ddr(); + dvi_on(); + init_ac97(); +#endif /* MACHINE_FIREBEE */ + driver_mem_init(); + + /* jump into the BaS */ + extern void BaS(void); + BaS(); +} diff --git a/tos/Makefile b/tos/Makefile new file mode 100644 index 0000000..c51142f --- /dev/null +++ b/tos/Makefile @@ -0,0 +1,37 @@ +.PHONY: tos +.PHONY: jtagwait +.PHONY: bascook +.PHONY: vmem_test +.PHONY: pci_test +.PHONY: pci_mem +.PHONY: fpga_test +tos: jtagwait bascook vmem_test pci_test pci_mem fpga_test + +jtagwait: + @$(MAKE) -s -C $@ + +bascook: + @$(MAKE) -s -C $@ + +vmem_test: + @$(MAKE) -s -C $@ + +pci_test: + @$(MAKE) -s -C $@ + +pci_mem: + @$(MAKE) -s -C $@ + +fpga_test: + @$(MAKE) -s -C $@ + +.PHONY: clean +clean: + @(cd jtagwait; $(MAKE) -s clean) + @(cd bascook; $(MAKE) -s clean) + @(cd vmem_test; $(MAKE) -s clean) + @(cd pci_test; $(MAKE) -s clean) + @(cd pci_mem; $(MAKE) -s clean) + @(cd fpga_test; $(MAKE) -s clean) + + diff --git a/tos/bascook/Makefile b/tos/bascook/Makefile new file mode 100755 index 0000000..b2e2b88 --- /dev/null +++ b/tos/bascook/Makefile @@ -0,0 +1,101 @@ +CROSS=Y + +CROSSBINDIR_IS_Y=m68k-atari-mint- +CROSSBINDIR_IS_N= + +CROSSBINDIR=$(CROSSBINDIR_IS_$(CROSS)) + +UNAME := $(shell uname) +ifeq ($(CROSS), Y) +ifeq ($(UNAME),Linux) +PREFIX=m68k-atari-mint +HATARI=hatari +else +PREFIX=m68k-atari-mint +HATARI=/usr/local/bin/hatari +endif +else +PREFIX=/usr +endif + +DEPEND=depend +TOPDIR= ../.. + +BAS_INCLUDE=-I$(TOPDIR)/../BaS_gcc/include + +LIBCMINI=$(TOPDIR)/../libcmini/libcmini + +INCLUDE=-I$(LIBCMINI)/include $(BAS_INCLUDE) -nostdlib +LIBS=-lcmini -nostdlib -lgcc +CC=$(PREFIX)/bin/gcc + +CC=$(CROSSBINDIR)gcc +STRIP=$(CROSSBINDIR)strip +STACK=$(CROSSBINDIR)stack + +APP=bascook.prg +TEST_APP=$(APP) + +CFLAGS=\ + -Os\ + -g\ + -Wl,-Map,mapfile\ + -Wall + +SRCDIR=sources + +CSRCS=\ + $(SRCDIR)/bascook.c +ASRCS= + +COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS))) +AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS))) +OBJS=$(COBJS) $(AOBJS) + +TRGTDIRS=. +OBJDIRS=$(patsubst %,%/objs,$(TRGTDIRS)) + +# +# multilib flags. These must match m68k-atari-mint-gcc -print-multi-lib output +# +$(APP):CFLAGS += -mcpu=5475 + +all: $(TEST_APP) + +# +# generate pattern rules for multilib object files. +# +define CC_TEMPLATE +$(1)/objs/%.o:$(SRCDIR)/%.c + @echo CC $$< + @$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@ + +$(1)/objs/%.o:$(SRCDIR)/%.S + @echo CC $$< + @$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@ + +$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS)) +$(1)/$(APP): $$($(1)_OBJS) + @echo CC $$< + @$(CC) $$(CFLAGS) -o $$@ $(LIBCMINI)/m5475/startup.o $$($(1)_OBJS) -L$(LIBCMINI)/m5475 $(LIBS) + @$(STRIP) $$@ +endef +$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR)))) + +$(DEPEND): $(ASRCS) $(CSRCS) + @-rm -f $(DEPEND) + @for d in $(TRGTDIRS);\ + do $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e "s#^\(.*\).o:#$$d/objs/\1.o:#" >> $(DEPEND); \ + done + + +clean: + @rm -f $(patsubst %,%/objs/*.o,$(TRGTDIRS)) $(patsubst %,%/$(APP),$(TRGTDIRS)) + @rm -f $(DEPEND) mapfile + +.PHONY: printvars +printvars: + @$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V)))) +ifneq (clean,$(MAKECMDGOALS)) +-include $(DEPEND) +endif diff --git a/tos/bascook/sources/bascook.c b/tos/bascook/sources/bascook.c new file mode 100644 index 0000000..8fa4e1c --- /dev/null +++ b/tos/bascook/sources/bascook.c @@ -0,0 +1,175 @@ +#include +#include +#include +#include + +#include "driver_vec.h" + +struct driver_table *get_bas_drivers(void) +{ + struct driver_table *ret = NULL; + + __asm__ __volatile__( + " bra.s do_trap \n\t" + " .dc.l 0x5f424153 \n\t" // '_BAS' + "do_trap: trap #0 \n\t" + " move.l d0,%[ret] \n\t" + : [ret] "=m" (ret) /* output */ + : /* no inputs */ + : /* clobbered */ + ); + + return ret; +} + +/* + * temporarily replace the trap 0 handler with this so we can avoid + * getting caught by BaS versions that don't understand the driver interface + * exposure call. + * If we get here, we have a BaS version that doesn't support the trap 0 interface + */ +static void __attribute__((interrupt)) trap0_catcher(void) +{ + __asm__ __volatile__( + " clr.l d0 \n\t" // return 0 to indicate not supported + : + : + : + ); +} + +static uint32_t cookieptr(void) +{ + return * (uint32_t *) 0x5a0L; +} + +void setcookie(uint32_t cookie, uint32_t value) +{ + uint32_t *cookiejar = (uint32_t *) Supexec(cookieptr); + int num_slots; + int max_slots; + + num_slots = max_slots = 0; + do + { + if (cookiejar[0] == cookie) + { + cookiejar[1] = value; + return; + } + cookiejar = &(cookiejar[2]); + num_slots++; + } while (cookiejar[-2]); + + /* + * Here we are at the end of the list and did not find our cookie. + * Let's check if there is any space left and append our value to the + * list if so. If not, we are lost (extending the cookie jar does only + * work from TSRs) + */ + if (cookiejar[-1]) + { + max_slots = cookiejar[-1]; + } + + if (max_slots > num_slots) + { + /* relief, there is space left, extend the list */ + cookiejar[0] = cookiejar[-2]; + cookiejar[1] = cookiejar[-1]; + /* add the new element */ + cookiejar[-2] = cookie; + cookiejar[-1] = value; + } + else + printf("cannot set cookie, cookie jar is full!\r\n"); +} + +#define COOKIE_DMAC 0x444d4143L /* FireTOS DMA API cookie ("DMAC") */ +#define COOKIE_BAS_ 0x4241535fL /* BAS_ cookie (points to driver table struct */ + +static char *dt_to_str(enum driver_type dt) +{ + switch (dt) + { + case BLOCKDEV_DRIVER: return "generic block device driver"; + case CHARDEV_DRIVER: return "generic character device driver"; + case VIDEO_DRIVER: return "video/framebuffer driver"; + case XHDI_DRIVER: return "XHDI compatible hard disk driver"; + case MCD_DRIVER: return "multichannel DMA driver"; + case PCI_DRIVER: return "PCI interface driver"; + case MMU_DRIVER: return "MMU lock/unlock pages driver"; + case PCI_NATIVE_DRIVER: return "PCI interface native driver"; + default: return "unknown driver type"; + } +} + +static void set_driver_cookies(void) +{ + struct driver_table *dt; + void *old_vector; + char **sysbase = (char **) 0x4f2; + uint32_t sig; + + sig = * (long *)((*sysbase) + 0x2c); + + /* + * first check if we are on EmuTOS, FireTOS want's to do everything itself + */ + if (sig == 0x45544f53) + { + old_vector = Setexc(0x20, trap0_catcher); /* set our own temporarily */ + dt = get_bas_drivers(); /* trap #0 */ + (void) Setexc(0x20, old_vector); /* restore original vector */ + + if (dt) + { + struct generic_interface *ifc = &dt->interfaces[0]; + + printf("BaS driver table found at %p, BaS version is %d.%d\r\n", dt, + dt->bas_version, dt->bas_revision); + + while (ifc->type != END_OF_DRIVERS) + { + printf("driver \"%s (%s)\" found,\r\n" + "interface type is %d (%s),\r\n" + "version %d.%d\r\n\r\n", + ifc->name, ifc->description, ifc->type, dt_to_str(ifc->type), + ifc->version, ifc->revision); + if (ifc->type == MCD_DRIVER) + { + setcookie(COOKIE_DMAC, (uint32_t) ifc->interface.dma); + printf("\r\nDMAC cookie set to %p\r\n", ifc->interface.dma); + } + ifc++; + } + + /* + * set cookie to be able to find the driver table later on + */ + setcookie(COOKIE_BAS_, (uint32_t) dt); + printf("BAS_ cookie set to %p\r\n", dt); + } + else + { + printf("driver table not found.\r\n"); + } + } + else + { + printf("not running on EmuTOS,\r\n(signature 0x%04x instead of 0x%04x\r\n", + (uint32_t) sig, 0x45544f53); + } +} + +int main(int argc, char *argv[]) +{ + (void) Cconws("retrieve BaS driver interface\r\n"); + + Supexec(set_driver_cookies); + + while (Cconis()) Cconin(); /* eat keys */ + + return 0; +} + diff --git a/tos/fpga_test/Makefile b/tos/fpga_test/Makefile new file mode 100755 index 0000000..e8b381e --- /dev/null +++ b/tos/fpga_test/Makefile @@ -0,0 +1,109 @@ +CROSS=Y + +CROSSBINDIR_IS_Y=m68k-atari-mint- +CROSSBINDIR_IS_N= + +CROSSBINDIR=$(CROSSBINDIR_IS_$(CROSS)) + +UNAME := $(shell uname) +ifeq ($(CROSS), Y) +ifeq ($(UNAME),Linux) +PREFIX=m68k-atari-mint +HATARI=hatari +else +PREFIX=m68k-atari-mint +HATARI=/usr/local/bin/hatari +endif +else +PREFIX=/usr +endif + +DEPEND=depend +TOPDIR = ../.. + +LIBCMINI=$(TOPDIR)/../libcmini/libcmini + +INCLUDE=-I$(LIBCMINI)/include -nostdlib -I$(TOPDIR)/include +LIBS=-lcmini -nostdlib -lgcc -L$(TOPDIR)/firebee -lbas +CC=$(PREFIX)/bin/gcc + +CC=$(CROSSBINDIR)gcc +STRIP=$(CROSSBINDIR)strip +STACK=$(CROSSBINDIR)stack + +APP=fpga_test.prg +TEST_APP=$(APP) + +CFLAGS=\ + -O0\ + -g\ + -Wl,-Map,mapfile\ + -Wl,--defsym -Wl,__MBAR=0xff000000\ + -Wl,--defsym -Wl,__MMUBAR=0xff040000\ + -Wl,--defsym -Wl,__FPGA_JTAG_LOADED=0xff101000\ + -Wl,--defsym -Wl,__FPGA_JTAG_VALID=0xff101004\ + -Wl,--defsym -Wl,__VRAM=0x60000000\ + -Wall + +SRCDIR=sources +INCDIR=include +INCLUDE+=-I$(INCDIR) + +CSRCS=\ + $(SRCDIR)/fpga_test.c \ + $(SRCDIR)/ser_printf.c + +ASRCS= + +COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS))) +AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS))) +OBJS=$(COBJS) $(AOBJS) + +TRGTDIRS=./m5475 ./m5475/mshort +OBJDIRS=$(patsubst %,%/objs,$(TRGTDIRS)) + +# +# multilib flags. These must match m68k-atari-mint-gcc -print-multi-lib output +# +m5475/$(APP):CFLAGS += -mcpu=5475 +m5475/mshort/$(APP): CFLAGS += -mcpu=5475 -mshort + +all:$(patsubst %,%/$(APP),$(TRGTDIRS)) +# +# generate pattern rules for multilib object files. +# +define CC_TEMPLATE +$(1)/objs/%.o:$(SRCDIR)/%.c + @echo CC $$< + @$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@ + +$(1)/objs/%.o:$(SRCDIR)/%.S + @echo CC $$< + @$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@ + +$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS)) +$(1)/$(APP): $$($(1)_OBJS) + @echo CC $$@ + @$(CC) $$(CFLAGS) -o $$@ $(LIBCMINI)/$(1)/startup.o $$($(1)_OBJS) -L$(LIBCMINI)/$(1) $(LIBS) + #$(STRIP) $$@ +endef +$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR)))) + +$(DEPEND): $(ASRCS) $(CSRCS) + @-rm -f $(DEPEND) + @for d in $(TRGTDIRS);\ + do $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e "s#^\(.*\).o:#$$d/objs/\1.o:#" >> $(DEPEND); \ + done + + +clean: + @rm -f $(patsubst %,%/objs/*.o,$(TRGTDIRS)) $(patsubst %,%/$(APP),$(TRGTDIRS)) + @rm -f $(DEPEND) mapfile + +.PHONY: printvars +printvars: + @$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V)))) + +ifneq (clean,$(MAKECMDGOALS)) +-include $(DEPEND) +endif diff --git a/tos/fpga_test/sources/fpga_test.c b/tos/fpga_test/sources/fpga_test.c new file mode 100644 index 0000000..6350e01 --- /dev/null +++ b/tos/fpga_test/sources/fpga_test.c @@ -0,0 +1,491 @@ +#include +#include +#include +#include + +#include "bas_printf.h" +#include "MCF5475.h" +#include "driver_vec.h" + +#define FPGA_CONFIG (1 << 2) +#define FPGA_CONF_DONE (1 << 5) + +#define SRAM1_START 0xff101000 +#define SRAM1_END SRAM1_START + 0x1000 +#define SAFE_STACK SRAM1_END - 4 + +#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory") + +#define SYSCLK 132000 + +long bas_start = 0xe0000000; + +volatile uint16_t *FB_CS1 = (volatile uint16_t *) 0xfff00000; /* "classic" ATARI I/O registers */ +volatile uint32_t *FB_CS2 = (volatile uint32_t *) 0xf0000000; /* FireBee 32 bit I/O registers */ +volatile uint16_t *FB_CS3 = (volatile uint16_t *) 0xf8000000; /* FireBee SRAM */ +volatile uint32_t *FB_CS4 = (uint32_t *) 0x40000000; /* FireBee SD RAM */ + +const long sdram_size = 128 * 1024L * 1024L; + +static void init_ddr_ram(void) +{ + xprintf("init video RAM: "); + + FB_CS2[0x100] = 0xb; /* set cke = 1, cs=1, config = 1 */ + NOP(); + + FB_CS4[0] = 0x00050400; /* IPALL */ + NOP(); + + FB_CS4[0] = 0x00072000; /* load EMR pll on */ + NOP(); + + FB_CS4[0] = 0x00070122; /* load MR: reset pll, cl=2, burst=4lw */ + NOP(); + + FB_CS4[0] = 0x00050400; /* IPALL */ + NOP(); + + FB_CS4[0] = 0x00060000; /* auto refresh */ + NOP(); + + FB_CS4[0] = 0x00060000; /* auto refresh */ + NOP(); + + /* FIXME: what's this? */ + FB_CS4[0] = 0000070022; /* load MR dll on */ + NOP(); + + FB_CS2[0x100] = 0x01070082; /* fifo on, refresh on, ddrcs und cke on, video dac on, Falcon shift mode on */ + + xprintf("finished\r\n"); +} + + +bool verify_ddr_ram(uint32_t value) +{ + volatile uint32_t *lp; + volatile uint16_t *wp; + uint32_t rl; + uint16_t rw; + + lp = FB_CS4; + + /* + * write/read longs + */ + lp = FB_CS4; + do + { + *lp = value; + xprintf("W: 0x%08x R: 0x%08x\r", value, rl = *lp); + + if (rl != value) + { + xprintf("\nvalidation error at %p: written = 0x%08x, read = 0x%08x\r\n", lp, value, rl); + + return false; + } + } while (lp++ <= FB_CS4 + sdram_size - 1); + + wp = (uint16_t *) FB_CS4; + + /* + * write/read words + */ + wp = (uint16_t *) FB_CS4; + do + { + *wp = (uint16_t) value; + + xprintf("W: 0x%04x R: 0x%04x\r", value, rw = *wp); + + if (rw != value) + { + xprintf("\nvalidation error at %p: written = 0x%04x, read = 0x%04x\r\n", wp, value, rw); + + return false; + } + } while (wp++ <= (uint16_t *) FB_CS4 + sdram_size - 1); + + + return true; +} + +bool verify_longaddr(volatile uint32_t * const addr, uint32_t value) +{ + *addr = value; + + xprintf("W: 0x%08x R: 0x%08x\r", value, *addr); + + if (value != *addr) + { + xprintf("validation error at %p: written = 0x%08x, read = 0x%08x\r\n", addr, value, *addr); + + xprintf("\r\n"); + + return false; + } + + return true; +} + +bool verify_long(volatile uint32_t * const addr, uint32_t low_value, uint32_t high_value) +{ + uint32_t i; + + for (i = low_value; i <= high_value; i++) + if (verify_longaddr(addr, i) == false) + { + xprintf("verify of %p failed: 0x%08x written, 0x%08x read\r\n", + addr, i, *addr); + + return false; + } + return true; +} + +void firebee_io_test(void) +{ + volatile uint32_t *ACP_VCTR = &FB_CS2[0x100]; /* 0xf000400 */ + volatile uint32_t *CCR = &FB_CS2[0x101]; /* 0xf000401 - FireBee mode border color */ + volatile uint32_t *ATARI_HH = &FB_CS2[0x104]; /* 0xf000410 */ + volatile uint32_t *ATARI_VH = &FB_CS2[0x105]; /* 0xf000414 */ + volatile uint32_t *ATARI_HL = &FB_CS2[0x106]; /* 0xf000418 */ + volatile uint32_t *ATARI_VL = &FB_CS2[0x107]; /* 0xf00041c */ + + volatile uint32_t *VIDEO_PLL_CONFIG = &FB_CS2[0x180]; /* 0xf000600 */ + volatile uint32_t *VIDEO_PLL_RECONFIG = &FB_CS2[0x200]; /* 0xf000800 */ + + xprintf("verify ACP_VCTR register\r\n"); + verify_long(ACP_VCTR, 0, 0x1ff); + + xprintf("verify CCR register\r\n"); + verify_long(CCR, 0, 0x1ff); + + xprintf("verify ATARI_HH register\r\n"); + verify_long(ATARI_HH, 0, 0x1ff); + + xprintf("verify ATARI_VH register\r\n"); + verify_long(ATARI_VH, 0, 0x1ff); + + xprintf("verify ATARI_HL register\r\n"); + verify_long(ATARI_HL, 0, 0x1ff); + + xprintf("verify ATARI_VL register\r\n"); + verify_long(ATARI_VL, 0, 0x1ff); + + xprintf("verify VIDEO_PLL_CONFIG register\r\n"); + verify_long(VIDEO_PLL_CONFIG, 0, 0x1ff); + + xprintf("verify VIDEO_PLL_RECONFIG register\r\n"); + verify_long(VIDEO_PLL_RECONFIG, 0, 0x1ff); +} + +bool verify_wordaddr(volatile uint16_t * const addr, uint16_t value) +{ + long rvalue; + *addr = value; + + if (value != (rvalue = *addr)) + { + xprintf("validation error at %p, wrote 0x%04x, read 0x%04x\r\n", addr, value, rvalue); + + xprintf("\r\n"); + + return false; + } + + return true; +} + +bool verify_word(volatile uint16_t * const addr, uint16_t low_value, uint16_t high_value) +{ + uint16_t i; + + for (i = low_value; i <= high_value; i++) + if (verify_wordaddr(addr, i) == false) + { + xprintf("verify of %p failed: 0x%04x written, 0x%04x read\r\n", + addr, i, *addr); + return false; + } + + return true; +} + +bool verify_byteaddr(volatile uint8_t * const addr, uint8_t value) +{ + uint8_t rvalue; + *addr = value; + + if (value != (rvalue = *addr)) + { + xprintf("validation error at %p, wrote 0x%02x, read 0x%02x\r\n", addr, value, rvalue); + + xprintf("\r\n"); + + return false; + } + + return true; +} + +bool verify_byte(volatile uint8_t * const addr, uint8_t low_value, uint8_t high_value) +{ + int8_t i; + + for (i = low_value; i <= high_value; i++) + if (verify_byteaddr(addr, i) == false) + { + xprintf("verify of %p failed: 0x%02x written, 0x%02x read\r\n", + addr, i, *addr); + return false; + } + + return true; +} + +void falcon_io_test(void) +{ + int i; + + volatile uint16_t *SYS_CTR = &FB_CS1[0x7c003]; /* 0xffff8006 */ + + volatile uint8_t *VIDEO_ADR_HI = ((volatile uint8_t *) &FB_CS1[0x7c100]) + 1; /* 0xffff8201 */ + volatile uint8_t *VIDEO_ADR_MI = ((volatile uint8_t *) &FB_CS1[0x7c101]) + 1; /* 0xffff8203 */ + volatile uint8_t *VIDEO_ADR_LO = ((volatile uint8_t *) &FB_CS1[0x7c106]) + 1; /* 0xffff820d */ + + volatile uint8_t *VIDEO_CNT_HI = ((volatile uint8_t *) &FB_CS1[0x7c102]) + 1; /* 0xffff8205 */ + volatile uint8_t *VIDEO_CNT_MI = ((volatile uint8_t *) &FB_CS1[0x7c103]) + 1; /* 0xffff8207 */ + volatile uint8_t *VIDEO_CNT_LO = ((volatile uint8_t *) &FB_CS1[0x7c104]) + 1; /* 0xffff8209 */ + + volatile uint8_t *SYNC_MODE = ((volatile uint8_t *) &FB_CS1[0x7c105]) + 1; /* 0xffff8006 */ + + volatile uint16_t *VDL_LOF = &FB_CS1[0x7c107]; /* 0xffff820e */ + volatile uint16_t *VDL_LWD = &FB_CS1[0x7c108]; /* 0xffff8210 */ + volatile uint16_t *VDL_HHT = &FB_CS1[0x7c141]; /* 0xffff8282 */ + volatile uint16_t *VDL_HBB = &FB_CS1[0x7c142]; /* 0xffff8284 */ + volatile uint16_t *VDL_HBE = &FB_CS1[0x7c143]; /* 0xffff8286 */ + volatile uint16_t *VDL_HDB = &FB_CS1[0x7c144]; /* 0xffff8288 */ + volatile uint16_t *VDL_HDE = &FB_CS1[0x7c145]; /* 0xffff828a */ + volatile uint16_t *VDL_HSS = &FB_CS1[0x7c146]; /* 0xffff828c */ + + volatile uint16_t *VDL_VFT = &FB_CS1[0x7c151]; /* 0xffff82a2 */ + volatile uint16_t *VDL_VBB = &FB_CS1[0x7c152]; /* 0xffff82a4 */ + volatile uint16_t *VDL_VBE = &FB_CS1[0x7c153]; /* 0xffff82a6 */ + volatile uint16_t *VDL_VDB = &FB_CS1[0x7c154]; /* 0xffff82a8 */ + volatile uint16_t *VDL_VDE = &FB_CS1[0x7c155]; /* 0xffff82aa */ + volatile uint16_t *VDL_VSS = &FB_CS1[0x7c156]; /* 0xffff82ac */ + volatile uint16_t *VDL_VCT = &FB_CS1[0x7c160]; /* 0xffff82c0 */ + volatile uint16_t *VDL_VMD = &FB_CS1[0x7c161]; /* 0xffff82c2 */ + + /* ST palette registers */ + volatile uint8_t *st_palette = (volatile uint8_t *) &FB_CS1[0x7c120]; /* 0xffff8240 */ + + /* Falcon palette registers */ + volatile uint8_t *falcon_palette = (volatile uint8_t *) &FB_CS1[0x7cc00]; /* 0xffff9800 */ + + xprintf("verify VIDEO_ADR_XX registers\r\n"); + verify_byte(VIDEO_ADR_HI, 0x00, 0xff); + verify_byte(VIDEO_ADR_MI, 0x00, 0xff); + verify_byte(VIDEO_ADR_LO, 0x00, 0xff); + + xprintf("verify VIDEO_CNT_XX registers\r\n"); + verify_byte(VIDEO_CNT_HI, 0x00, 0xff); + verify_byte(VIDEO_CNT_MI, 0x00, 0xff); + verify_byte(VIDEO_CNT_LO, 0x00, 0xff); + + xprintf("verify SYNC_MODE register\r\n"); + verify_byte(SYNC_MODE, 0x00, 0xff); + + xprintf("verify SYS_CTR register\r\n"); + verify_word(SYS_CTR, 0, 0x1ff); + + for (i = 0; i < 16 * 2; i += 2) + { + xprintf("verify ST palette register %d\r\n", i / 2); + verify_byte(&st_palette[i], i / 2, i / 2); + verify_byte(&st_palette[i], i / 2, i / 2); /* do two consecutive tests here because of RAM latency */ + } + + for (i = 0; i < 255 * 2; i += 2) + { + xprintf("verify Falcon palette register %d\r\n", i / 2); + verify_byte(&falcon_palette[i], i / 2, i / 2); + verify_byte(&falcon_palette[i], i / 2, i / 2); /* do two consecutive tests here because of FPGA RAM latency */ + } + + xprintf("verify LOF register\r\n"); + verify_word(VDL_LOF, 0, 0x1ff); + + xprintf("verify LWD register \r\n"); + verify_word(VDL_LWD, 0, 0x1ff); + + xprintf("verify HHT register\r\n"); + verify_word(VDL_HHT, 0, 0x1ff); + + xprintf("verify HBB register\r\n"); + verify_word(VDL_HBB, 0, 0x1ff); + + xprintf("verify HBE register\r\n"); + verify_word(VDL_HBE, 0, 0x1ff); + + xprintf("verify HDB register\r\n"); + verify_word(VDL_HDB, 0, 0x1ff); + + xprintf("verify HDE register\r\n"); + verify_word(VDL_HDE, 0, 0x1ff); + + xprintf("verify HSS register\r\n"); + verify_word(VDL_HSS, 0, 0x1ff); + + + xprintf("verify VFT register\r\n"); + verify_word(VDL_VFT, 0, 0x1ff); + + xprintf("verify VBB register\r\n"); + verify_word(VDL_VBB, 0, 0x1ff); + + xprintf("verify VBE register\r\n"); + verify_word(VDL_VBE, 0, 0x1ff); + + xprintf("verify VDB register\r\n"); + verify_word(VDL_VDB, 0, 0x1ff); + + xprintf("verify VDE register\r\n"); + verify_word(VDL_VDE, 0, 0x1ff); + + xprintf("verify VSS register\r\n"); + verify_word(VDL_VSS, 0, 0x1ff); + + xprintf("verify VCT register\r\n"); + verify_word(VDL_VCT, 0, 0x1ff); + + xprintf("verify VMD register\r\n"); + verify_word(VDL_VMD, 0, 0x1ff); +} + +void do_tests(void) +{ + xprintf("start tests:\r\n"); + + xprintf("Falcon I/O test\r\n"); + falcon_io_test(); + + xprintf("FireBee I/O test\r\n"); + firebee_io_test(); + + init_ddr_ram(); + verify_ddr_ram(0xaaaaaaaa); + verify_ddr_ram(0x55555555); +} + + +void wait_for_jtag(void) +{ + long i; + + /* set supervisor stack to end of SRAM1 */ + __asm__ __volatile__ ( + " move #0x2700,sr\n\t" /* disable interrupts */ + " move.l %[stack],d0\n\t" /* 4KB on-chip core SRAM1 */ + " move.l d0,sp\n\t" /* set stack pointer */ + : + : [stack] "i" (SAFE_STACK) + : "d0", "cc" /* clobber */ + ); + + MCF_EPORT_EPIER = 0x0; /* disable EPORT interrupts */ + MCF_INTC_IMRL = 0xffffffff; + MCF_INTC_IMRH = 0xffffffff; /* disable interrupt controller */ + + MCF_MMU_MMUCR &= ~MCF_MMU_MMUCR_EN; /* disable MMU */ + + xprintf("relocated supervisor stack, disabled interrupts and disabled MMU\r\n"); + + /* + * configure FEC1L port directions to enable external JTAG configuration download to FPGA + */ + MCF_GPIO_PDDR_FEC1L = 0 | + MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4; /* bit 4 = LED => output */ + /* all other bits = input */ + + /* + * configure DSPI_CS3 as GPIO input to avoid the MCU driving against the FPGA blink + */ + MCF_PAD_PAR_DSPI &= ~MCF_PAD_PAR_DSPI_PAR_CS3(MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3); + /* + * now that GPIO ports have been switched to input, we can poll for FPGA config + * started from the JTAG interface (CONF_DONE goes low) and finish (CONF_DONE goes high) + */ + xprintf("waiting for JTAG configuration start\r\n"); + while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load started */ + + xprintf("waiting for JTAG configuration to finish\r\n"); + while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load finished */ + + xprintf("JTAG configuration finished.\r\n"); + + /* wait */ + xprintf("wait a little to let things settle...\r\n"); + for (i = 0; i < 100000L; i++); + + xprintf("disable caches\r\n"); + __asm__ __volatile( + "move.l #0x01000000,d0 \r\n" + "movec d0,CACR \r\n" + : /* no output */ + : /* no input */ + : "d0", "memory"); + + /* begin of tests */ + + do_tests(); + + xprintf("wait a little to let things settle...\r\n"); + for (i = 0; i < 100000L; i++); + + xprintf("INFO: endless loop now. Press reset to reboot\r\n"); + while (1) + ; +} + +int main(int argc, char *argv[]) +{ + printf("FPGA JTAG configuration support\r\n"); + printf("test FPGA DDR RAM controller\r\n"); + printf("\xbd 2014 M. Fr\x94schle\r\n"); + + printf("You may now savely load a new FPGA configuration through the JTAG interface\r\n" + "and your FireBee will reboot once finished using that new configuration.\r\n"); + if (argc == 2) + { + /* + * we got an argument. This is supposed to be the address that we need to jump to after JTAG + * configuration has been finished. Meant to support BaS in RAM testing + */ + char *addr_str = argv[1]; + char *addr = NULL; + char *end = NULL; + + addr = (char *) strtol(addr_str, &end, 16); + if (addr != NULL && addr <= (char *) 0xe0000000 && addr >= (char *) 0x10000000) + { + /* + * seems to be a valid address + */ + bas_start = (long) addr; + + printf("BaS start address set to %p\r\n", (void *) bas_start); + } + else + { + printf("\r\nNote: BaS start address %p not valid. Stick to %p.\r\n", addr, (void *) bas_start); + } + } + Supexec(wait_for_jtag); + + return 0; /* just to make the compiler happy, we will never return */ +} + diff --git a/tos/fpga_test/sources/ser_printf.c b/tos/fpga_test/sources/ser_printf.c new file mode 100755 index 0000000..2b3dd95 --- /dev/null +++ b/tos/fpga_test/sources/ser_printf.c @@ -0,0 +1,480 @@ + +/* + * tc.printf.c: A public-domain, minimal printf/sprintf routine that prints + * through the putchar() routine. Feel free to use for + * anything... -- 7/17/87 Paul Placeway + */ +/*- + * Copyright (c) 1980, 1991 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +#include +#include "MCF5475.h" +#include "bas_printf.h" +#include "bas_string.h" + +/* + * Lexical definitions. + * + * All lexical space is allocated dynamically. + * The eighth/sixteenth bit of characters is used to prevent recognition, + * and eventually stripped. + */ +#define META 0200 +#define ASCII 0177 +#define QUOTE ((char) 0200) /* Eighth char bit used for 'ing */ +#define TRIM 0177 /* Mask to strip quote bit */ +#define UNDER 0000000 /* No extra bits to do both */ +#define BOLD 0000000 /* Bold flag */ +#define STANDOUT META /* Standout flag */ +#define LITERAL 0000000 /* Literal character flag */ +#define ATTRIBUTES 0200 /* The bits used for attributes */ +#define CHAR 0000177 /* Mask to mask out the character */ + +#define INF 32766 /* should be bigger than any field to print */ + +static char snil[] = "(nil)"; + +bool conoutstat(void) +{ + bool stat; + + stat = MCF_PSC0_PSCSR & MCF_PSC_PSCSR_TXRDY; /* TX FIFO can take data */ + + return stat; +} + +bool coninstat(void) +{ + bool stat; + + stat = MCF_PSC0_PSCSR & MCF_PSC_PSCSR_RXRDY; /* RX FIFO has data available */ + + return stat; +} + +void xputchar(int c) +{ + do { ; } while (!conoutstat()); + MCF_PSC_PSCRB_8BIT(0) = (char) c; +} + +char xgetchar(void) +{ + char c; + + do { ; } while (!coninstat()); + c = MCF_PSC_PSCTB_8BIT(0); + + return c; +} + +static void doprnt(void (*addchar)(int), const char *sfmt, va_list ap) +{ + char buf[128]; + char *bp; + const char *f; + float flt; + long l; + unsigned long u; + int i; + int fmt; + unsigned char pad = ' '; + int flush_left = 0; + int f_width = 0; + int prec = INF; + int hash = 0; + int do_long = 0; + int sign = 0; + int attributes = 0; + + f = sfmt; + for (; *f; f++) + { + if (*f != '%') + { + /* then just out the char */ + (*addchar)((int) (((unsigned char) *f) | attributes)); + } + else + { + f++; /* skip the % */ + + if (*f == '-') + { /* minus: flush left */ + flush_left = 1; + f++; + } + + if (*f == '0' || *f == '.') + { + /* padding with 0 rather than blank */ + pad = '0'; + f++; + } + if (*f == '*') + { + /* field width */ + f_width = va_arg(ap, int); + f++; + } + else if (isdigit((unsigned char)*f)) + { + f_width = atoi(f); + while (isdigit((unsigned char)*f)) + f++; /* skip the digits */ + } + + if (*f == '.') + { /* precision */ + f++; + if (*f == '*') + { + prec = va_arg(ap, int); + f++; + } + else if (isdigit((unsigned char)*f)) + { + prec = atoi(f); + while (isdigit((unsigned char)*f)) + f++; /* skip the digits */ + } + } + + if (*f == '#') + { /* alternate form */ + hash = 1; + f++; + } + + if (*f == 'l') + { /* long format */ + do_long++; + f++; + if (*f == 'l') + { + do_long++; + f++; + } + } + + fmt = (unsigned char) *f; + if (fmt != 'S' && fmt != 'Q' && isupper(fmt)) + { + do_long = 1; + fmt = tolower(fmt); + } + bp = buf; + switch (fmt) + { /* do the format */ + case 'd': + switch (do_long) + { + case 0: + l = (long) (va_arg(ap, int)); + break; + case 1: + default: + l = va_arg(ap, long); + break; + } + + if (l < 0) + { + sign = 1; + l = -l; + } + do + { + *bp++ = (char) (l % 10) + '0'; + } while ((l /= 10) > 0); + if (sign) + *bp++ = '-'; + f_width = f_width - (int) (bp - buf); + if (!flush_left) + while (f_width-- > 0) + (*addchar)((int) (pad | attributes)); + for (bp--; bp >= buf; bp--) + (*addchar)((int) (((unsigned char) *bp) | attributes)); + if (flush_left) + while (f_width-- > 0) + (*addchar)((int) (' ' | attributes)); + break; + + case 'f': + /* this is actually more than stupid, but does work for now */ + flt = (float) (va_arg(ap, double)); /* beware: va_arg() extends float to double! */ + if (flt < 0) + { + sign = 1; + flt = -flt; + } + { + int quotient, remainder; + + quotient = (int) flt; + remainder = (flt - quotient) * 10E5; + + for (i = 0; i < 6; i++) + { + *bp++ = (char) (remainder % 10) + '0'; + remainder /= 10; + } + *bp++ = '.'; + do + { + *bp++ = (char) (quotient % 10) + '0'; + } while ((quotient /= 10) > 0); + if (sign) + *bp++ = '-'; + f_width = f_width - (int) (bp - buf); + if (!flush_left) + while (f_width-- > 0) + (*addchar)((int) (pad | attributes)); + for (bp--; bp >= buf; bp--) + (*addchar)((int) (((unsigned char) *bp) | attributes)); + if (flush_left) + while (f_width-- > 0) + (*addchar)((int) (' ' | attributes)); + } + break; + + case 'p': + do_long = 1; + hash = 1; + fmt = 'x'; + /* no break */ + case 'o': + case 'x': + case 'u': + switch (do_long) + { + case 0: + u = (unsigned long) (va_arg(ap, unsigned int)); + break; + case 1: + default: + u = va_arg(ap, unsigned long); + break; + } + if (fmt == 'u') + { /* unsigned decimal */ + do + { + *bp++ = (char) (u % 10) + '0'; + } while ((u /= 10) > 0); + } + else if (fmt == 'o') + { /* octal */ + do + { + *bp++ = (char) (u % 8) + '0'; + } while ((u /= 8) > 0); + if (hash) + *bp++ = '0'; + } + else if (fmt == 'x') + { /* hex */ + do + { + i = (int) (u % 16); + if (i < 10) + *bp++ = i + '0'; + else + *bp++ = i - 10 + 'a'; + } while ((u /= 16) > 0); + if (hash) + { + *bp++ = 'x'; + *bp++ = '0'; + } + } + i = f_width - (int) (bp - buf); + if (!flush_left) + while (i-- > 0) + (*addchar)((int) (pad | attributes)); + for (bp--; bp >= buf; bp--) + (*addchar)((int) (((unsigned char) *bp) | attributes)); + if (flush_left) + while (i-- > 0) + (*addchar)((int) (' ' | attributes)); + break; + + case 'c': + i = va_arg(ap, int); + (*addchar)((int) (i | attributes)); + break; + + case 'S': + case 'Q': + case 's': + case 'q': + bp = va_arg(ap, char *); + if (!bp) + bp = snil; + f_width = f_width - strlen((char *) bp); + if (!flush_left) + while (f_width-- > 0) + (*addchar)((int) (pad | attributes)); + for (i = 0; *bp && i < prec; i++) + { + if (fmt == 'q' && (*bp & QUOTE)) + (*addchar)((int) ('\\' | attributes)); + (*addchar)( + (int) (((unsigned char) *bp & TRIM) | attributes)); + bp++; + } + if (flush_left) + while (f_width-- > 0) + (*addchar)((int) (' ' | attributes)); + break; + + case 'a': + attributes = va_arg(ap, int); + break; + + case '%': + (*addchar)((int) ('%' | attributes)); + break; + + default: + break; + } + flush_left = 0, f_width = 0, prec = INF, hash = 0, do_long = 0; + sign = 0; + pad = ' '; + } + } +} + +static char *xstring, *xestring; + +void xaddchar(int c) +{ + if (xestring == xstring) + *xstring = '\0'; + else + *xstring++ = (char) c; +} + +int sprintf(char *str, const char *format, ...) +{ + va_list va; + va_start(va, format); + + xstring = str; + + doprnt(xaddchar, format, va); + va_end(va); + *xstring++ = '\0'; + + return 0; +} + +void xsnprintf(char *str, size_t size, const char *fmt, ...) +{ + va_list va; + va_start(va, fmt); + + xstring = str; + xestring = str + size - 1; + doprnt(xaddchar, fmt, va); + va_end(va); + *xstring++ = '\0'; +} + +void xprintf(const char *fmt, ...) +{ + va_list va; + va_start(va, fmt); + doprnt(xputchar, fmt, va); + va_end(va); +} + +void xvprintf(const char *fmt, va_list va) +{ + doprnt(xputchar, fmt, va); +} + +void xvsnprintf(char *str, size_t size, const char *fmt, va_list va) +{ + xstring = str; + xestring = str + size - 1; + doprnt(xaddchar, fmt, va); + *xstring++ = '\0'; +} + + +void display_progress() +{ + static int _progress_index; + char progress_char[] = "|/-\\"; + + xputchar(progress_char[_progress_index++ % strlen(progress_char)]); + xputchar('\r'); +} + +void hexdump(uint8_t buffer[], int size) +{ + int i; + int line = 0; + volatile uint8_t *bp = buffer; + + while (bp < buffer + size) { + volatile uint8_t *lbp = bp; + + xprintf("%08x ", line); + + for (i = 0; i < 16; i++) { + uint8_t c = *lbp++; + if (bp + i > buffer + size) { + break; + } + xprintf("%02x ", c); + } + + lbp = bp; + for (i = 0; i < 16; i++) { + volatile int8_t c = *lbp++; + + if (bp + i > buffer + size) { + break; + } + if (c > ' ' && c < '~') { + xprintf("%c", c); + } else { + xprintf("."); + } + } + xprintf("\r\n"); + + bp += 16; + line += 16; + } +} diff --git a/tos/fpga_test/vmem_test.config b/tos/fpga_test/vmem_test.config new file mode 100644 index 0000000..8cec188 --- /dev/null +++ b/tos/fpga_test/vmem_test.config @@ -0,0 +1 @@ +// ADD PREDEFINED MACROS HERE! diff --git a/tos/fpga_test/vmem_test.creator b/tos/fpga_test/vmem_test.creator new file mode 100644 index 0000000..e94cbbd --- /dev/null +++ b/tos/fpga_test/vmem_test.creator @@ -0,0 +1 @@ +[General] diff --git a/tos/fpga_test/vmem_test.files b/tos/fpga_test/vmem_test.files new file mode 100644 index 0000000..d4c5c1a --- /dev/null +++ b/tos/fpga_test/vmem_test.files @@ -0,0 +1,7 @@ +include/driver_vec.h +sources/jtagwait.c +Makefile +sources/bas_printf.c +sources/bas_string.c +sources/printf_helper.S +sources/vmem_test.c diff --git a/tos/fpga_test/vmem_test.includes b/tos/fpga_test/vmem_test.includes new file mode 100644 index 0000000..0e46827 --- /dev/null +++ b/tos/fpga_test/vmem_test.includes @@ -0,0 +1,2 @@ +include +/usr/m68k-atari-mint/include diff --git a/tos/jtagwait/Makefile b/tos/jtagwait/Makefile new file mode 100755 index 0000000..d893b33 --- /dev/null +++ b/tos/jtagwait/Makefile @@ -0,0 +1,108 @@ +CROSS=Y + +CROSSBINDIR_IS_Y=m68k-atari-mint- +CROSSBINDIR_IS_N= + +CROSSBINDIR=$(CROSSBINDIR_IS_$(CROSS)) + +UNAME := $(shell uname) +ifeq ($(CROSS), Y) +ifeq ($(UNAME),Linux) +PREFIX=m68k-atari-mint +HATARI=hatari +else +PREFIX=m68k-atari-mint +HATARI=/usr/local/bin/hatari +endif +else +PREFIX=/usr +endif + +DEPEND=depend +TOPDIR = ../.. + +LIBCMINI=$(TOPDIR)/../libcmini/libcmini + +INCLUDE=-I$(LIBCMINI)/include -nostdlib +LIBS=-lcmini -nostdlib -lgcc +CC=$(PREFIX)/bin/gcc + +CC=$(CROSSBINDIR)gcc +STRIP=$(CROSSBINDIR)strip +STACK=$(CROSSBINDIR)stack + +APP=jtagwait.prg +TEST_APP=$(APP) + +CFLAGS=\ + -O0\ + -g\ + -Wl,-Map,mapfile\ + -Wl,--defsym -Wl,__MBAR=0xff000000\ + -Wl,--defsym -Wl,__MMUBAR=0xff040000\ + -Wl,--defsym -Wl,__FPGA_JTAG_LOADED=0xff101000\ + -Wl,--defsym -Wl,__FPGA_JTAG_VALID=0xff101004\ + -Wall + +SRCDIR=sources +INCDIR=include +INCLUDE+=-I$(INCDIR) + +CSRCS=\ + $(SRCDIR)/jtagwait.c \ + $(SRCDIR)/bas_printf.c + +ASRCS=$(SRCDIR)/printf_helper.S + +COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS))) +AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS))) +OBJS=$(COBJS) $(AOBJS) + +TRGTDIRS=./m5475 ./m5475/mshort +OBJDIRS=$(patsubst %,%/objs,$(TRGTDIRS)) + +# +# multilib flags. These must match m68k-atari-mint-gcc -print-multi-lib output +# +m5475/$(APP):CFLAGS += -mcpu=5475 +m5475/mshort/$(APP): CFLAGS += -mcpu=5475 -mshort + +all:$(patsubst %,%/$(APP),$(TRGTDIRS)) +# +# generate pattern rules for multilib object files. +# +define CC_TEMPLATE +$(1)/objs/%.o:$(SRCDIR)/%.c + @echo CC $$< + @$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@ + +$(1)/objs/%.o:$(SRCDIR)/%.S + @echo CC $$< + @$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@ + +$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS)) +$(1)/$(APP): $$($(1)_OBJS) + @echo CC $$@ + @$(CC) $$(CFLAGS) -o $$@ $(LIBCMINI)/$(1)/startup.o $$($(1)_OBJS) -L$(LIBCMINI)/$(1) $(LIBS) + @$(STRIP) $$@ +endef +$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR)))) + +$(DEPEND): $(ASRCS) $(CSRCS) + @-rm -f $(DEPEND) + @for d in $(TRGTDIRS);\ + do $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e "s#^\(.*\).o:#$$d/objs/\1.o:#" >> $(DEPEND); \ + done + + +clean: + @rm -f $(patsubst %,%/objs/*.o,$(TRGTDIRS)) $(patsubst %,%/$(APP),$(TRGTDIRS)) + @rm -f $(DEPEND) mapfile + +.PHONY: printvars +printvars: + @$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V)))) + +ifneq (clean,$(MAKECMDGOALS)) +-include $(DEPEND) +endif diff --git a/tos/jtagwait/include/MCF5475.h b/tos/jtagwait/include/MCF5475.h new file mode 100644 index 0000000..5ab1750 --- /dev/null +++ b/tos/jtagwait/include/MCF5475.h @@ -0,0 +1,67 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_H__ +#define __MCF5475_H__ + +#include +/*** + * MCF5475 Derivative Memory map definitions from linker command files: + * __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE + * linker symbols must be defined in the linker command file. + */ + +typedef uint32_t __attribute__((__may_alias__)) uint32_t_a; /* a type to avoid gcc's complaints about pointer aliasing */ + +extern uint8_t _MBAR[]; +extern uint8_t _MMUBAR[]; +extern uint8_t _RAMBAR0[]; +extern uint8_t _RAMBAR0_SIZE[]; +extern uint8_t _RAMBAR1[]; +extern uint8_t _RAMBAR1_SIZE[]; + +#define MBAR_ADDRESS (uint32_t)_MBAR +#define MMUBAR_ADDRESS (uint32_t)_MMUBAR +#define RAMBAR0_ADDRESS (uint32_t)_RAMBAR0 +#define RAMBAR0_SIZE (uint32_t)_RAMBAR0_SIZE +#define RAMBAR1_ADDRESS (uint32_t)_RAMBAR1 +#define RAMBAR1_SIZE (uint32_t)_RAMBAR1_SIZE + + +#include "MCF5475_SIU.h" +#include "MCF5475_MMU.h" +#include "MCF5475_SDRAMC.h" +#include "MCF5475_XLB.h" +#include "MCF5475_CLOCK.h" +#include "MCF5475_FBCS.h" +#include "MCF5475_INTC.h" +#include "MCF5475_GPT.h" +#include "MCF5475_SLT.h" +#include "MCF5475_GPIO.h" +#include "MCF5475_PAD.h" +#include "MCF5475_PCI.h" +#include "MCF5475_PCIARB.h" +#include "MCF5475_EPORT.h" +#include "MCF5475_CTM.h" +#include "MCF5475_DMA.h" +#include "MCF5475_PSC.h" +#include "MCF5475_DSPI.h" +#include "MCF5475_I2C.h" +#include "MCF5475_FEC.h" +#include "MCF5475_USB.h" +#include "MCF5475_SRAM.h" +#include "MCF5475_SEC.h" + +#endif /* __MCF5475_H__ */ diff --git a/tos/jtagwait/include/MCF5475_CLOCK.h b/tos/jtagwait/include/MCF5475_CLOCK.h new file mode 100644 index 0000000..4603098 --- /dev/null +++ b/tos/jtagwait/include/MCF5475_CLOCK.h @@ -0,0 +1,47 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_CLOCK_H__ +#define __MCF5475_CLOCK_H__ + + +/********************************************************************* +* +* Clock Module (CLOCK) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CLOCK_SPCR (*(volatile uint32_t*)(&_MBAR[0x300])) + + +/* Bit definitions and macros for MCF_CLOCK_SPCR */ +#define MCF_CLOCK_SPCR_MEMEN (0x1) +#define MCF_CLOCK_SPCR_PCIEN (0x2) +#define MCF_CLOCK_SPCR_FBEN (0x4) +#define MCF_CLOCK_SPCR_CAN0EN (0x8) +#define MCF_CLOCK_SPCR_DMAEN (0x10) +#define MCF_CLOCK_SPCR_FEC0EN (0x20) +#define MCF_CLOCK_SPCR_FEC1EN (0x40) +#define MCF_CLOCK_SPCR_USBEN (0x80) +#define MCF_CLOCK_SPCR_PSCEN (0x200) +#define MCF_CLOCK_SPCR_CAN1EN (0x800) +#define MCF_CLOCK_SPCR_CRYENA (0x1000) +#define MCF_CLOCK_SPCR_CRYENB (0x2000) +#define MCF_CLOCK_SPCR_COREN (0x4000) +#define MCF_CLOCK_SPCR_PLLK (0x80000000) + + +#endif /* __MCF5475_CLOCK_H__ */ diff --git a/tos/jtagwait/include/MCF5475_CTM.h b/tos/jtagwait/include/MCF5475_CTM.h new file mode 100644 index 0000000..5ba86e4 --- /dev/null +++ b/tos/jtagwait/include/MCF5475_CTM.h @@ -0,0 +1,76 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_CTM_H__ +#define __MCF5475_CTM_H__ + + +/********************************************************************* +* +* Comm Timer Module (CTM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CTM_CTCR0 (*(volatile uint32_t*)(&_MBAR[0x7F00])) +#define MCF_CTM_CTCR1 (*(volatile uint32_t*)(&_MBAR[0x7F04])) +#define MCF_CTM_CTCR2 (*(volatile uint32_t*)(&_MBAR[0x7F08])) +#define MCF_CTM_CTCR3 (*(volatile uint32_t*)(&_MBAR[0x7F0C])) +#define MCF_CTM_CTCR4 (*(volatile uint32_t*)(&_MBAR[0x7F10])) +#define MCF_CTM_CTCR5 (*(volatile uint32_t*)(&_MBAR[0x7F14])) +#define MCF_CTM_CTCR6 (*(volatile uint32_t*)(&_MBAR[0x7F18])) +#define MCF_CTM_CTCR7 (*(volatile uint32_t*)(&_MBAR[0x7F1C])) +#define MCF_CTM_CTCRF(x) (*(volatile uint32_t*)(&_MBAR[0x7F00 + ((x)*0x4)])) +#define MCF_CTM_CTCRV(x) (*(volatile uint32_t*)(&_MBAR[0x7F10 + ((x-4)*0x4)])) + + +/* Bit definitions and macros for MCF_CTM_CTCRF */ +#define MCF_CTM_CTCRF_CRV(x) (((x)&0xFFFF)<<0) +#define MCF_CTM_CTCRF_S(x) (((x)&0xF)<<0x10) +#define MCF_CTM_CTCRF_S_CLK_1 (0) +#define MCF_CTM_CTCRF_S_CLK_2 (0x10000) +#define MCF_CTM_CTCRF_S_CLK_4 (0x20000) +#define MCF_CTM_CTCRF_S_CLK_8 (0x30000) +#define MCF_CTM_CTCRF_S_CLK_16 (0x40000) +#define MCF_CTM_CTCRF_S_CLK_32 (0x50000) +#define MCF_CTM_CTCRF_S_CLK_64 (0x60000) +#define MCF_CTM_CTCRF_S_CLK_128 (0x70000) +#define MCF_CTM_CTCRF_S_CLK_256 (0x80000) +#define MCF_CTM_CTCRF_S_CLK_EXT (0x90000) +#define MCF_CTM_CTCRF_PCT(x) (((x)&0x7)<<0x14) +#define MCF_CTM_CTCRF_PCT_100 (0) +#define MCF_CTM_CTCRF_PCT_50 (0x100000) +#define MCF_CTM_CTCRF_PCT_25 (0x200000) +#define MCF_CTM_CTCRF_PCT_12p5 (0x300000) +#define MCF_CTM_CTCRF_PCT_6p25 (0x400000) +#define MCF_CTM_CTCRF_PCT_OFF (0x500000) +#define MCF_CTM_CTCRF_M (0x800000) +#define MCF_CTM_CTCRF_IM (0x1000000) +#define MCF_CTM_CTCRF_I (0x80000000) + +/* Bit definitions and macros for MCF_CTM_CTCRV */ +#define MCF_CTM_CTCRV_CRV(x) (((x)&0xFFFFFF)<<0) +#define MCF_CTM_CTCRV_PCT(x) (((x)&0x7)<<0x18) +#define MCF_CTM_CTCRV_PCT_100 (0) +#define MCF_CTM_CTCRV_PCT_50 (0x1000000) +#define MCF_CTM_CTCRV_PCT_25 (0x2000000) +#define MCF_CTM_CTCRV_PCT_12p5 (0x3000000) +#define MCF_CTM_CTCRV_PCT_6p25 (0x4000000) +#define MCF_CTM_CTCRV_PCT_OFF (0x5000000) +#define MCF_CTM_CTCRV_M (0x8000000) +#define MCF_CTM_CTCRV_S (0x10000000) + + +#endif /* __MCF5475_CTM_H__ */ diff --git a/tos/jtagwait/include/MCF5475_DMA.h b/tos/jtagwait/include/MCF5475_DMA.h new file mode 100644 index 0000000..4e6f916 --- /dev/null +++ b/tos/jtagwait/include/MCF5475_DMA.h @@ -0,0 +1,234 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_DMA_H__ +#define __MCF5475_DMA_H__ + + +/********************************************************************* +* +* Multichannel DMA (DMA) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DMA_TASKBAR (*(volatile uint32_t*)(&_MBAR[0x8000])) +#define MCF_DMA_CP (*(volatile uint32_t*)(&_MBAR[0x8004])) +#define MCF_DMA_EP (*(volatile uint32_t*)(&_MBAR[0x8008])) +#define MCF_DMA_VP (*(volatile uint32_t*)(&_MBAR[0x800C])) +#define MCF_DMA_PTD (*(volatile uint32_t*)(&_MBAR[0x8010])) +#define MCF_DMA_DIPR (*(volatile uint32_t*)(&_MBAR[0x8014])) +#define MCF_DMA_DIMR (*(volatile uint32_t*)(&_MBAR[0x8018])) +#define MCF_DMA_TCR0 (*(volatile uint16_t*)(&_MBAR[0x801C])) +#define MCF_DMA_TCR1 (*(volatile uint16_t*)(&_MBAR[0x801E])) +#define MCF_DMA_TCR2 (*(volatile uint16_t*)(&_MBAR[0x8020])) +#define MCF_DMA_TCR3 (*(volatile uint16_t*)(&_MBAR[0x8022])) +#define MCF_DMA_TCR4 (*(volatile uint16_t*)(&_MBAR[0x8024])) +#define MCF_DMA_TCR5 (*(volatile uint16_t*)(&_MBAR[0x8026])) +#define MCF_DMA_TCR6 (*(volatile uint16_t*)(&_MBAR[0x8028])) +#define MCF_DMA_TCR7 (*(volatile uint16_t*)(&_MBAR[0x802A])) +#define MCF_DMA_TCR8 (*(volatile uint16_t*)(&_MBAR[0x802C])) +#define MCF_DMA_TCR9 (*(volatile uint16_t*)(&_MBAR[0x802E])) +#define MCF_DMA_TCR10 (*(volatile uint16_t*)(&_MBAR[0x8030])) +#define MCF_DMA_TCR11 (*(volatile uint16_t*)(&_MBAR[0x8032])) +#define MCF_DMA_TCR12 (*(volatile uint16_t*)(&_MBAR[0x8034])) +#define MCF_DMA_TCR13 (*(volatile uint16_t*)(&_MBAR[0x8036])) +#define MCF_DMA_TCR14 (*(volatile uint16_t*)(&_MBAR[0x8038])) +#define MCF_DMA_TCR15 (*(volatile uint16_t*)(&_MBAR[0x803A])) +#define MCF_DMA_PRIOR0 (*(volatile uint8_t *)(&_MBAR[0x803C])) +#define MCF_DMA_PRIOR1 (*(volatile uint8_t *)(&_MBAR[0x803D])) +#define MCF_DMA_PRIOR2 (*(volatile uint8_t *)(&_MBAR[0x803E])) +#define MCF_DMA_PRIOR3 (*(volatile uint8_t *)(&_MBAR[0x803F])) +#define MCF_DMA_PRIOR4 (*(volatile uint8_t *)(&_MBAR[0x8040])) +#define MCF_DMA_PRIOR5 (*(volatile uint8_t *)(&_MBAR[0x8041])) +#define MCF_DMA_PRIOR6 (*(volatile uint8_t *)(&_MBAR[0x8042])) +#define MCF_DMA_PRIOR7 (*(volatile uint8_t *)(&_MBAR[0x8043])) +#define MCF_DMA_PRIOR8 (*(volatile uint8_t *)(&_MBAR[0x8044])) +#define MCF_DMA_PRIOR9 (*(volatile uint8_t *)(&_MBAR[0x8045])) +#define MCF_DMA_PRIOR10 (*(volatile uint8_t *)(&_MBAR[0x8046])) +#define MCF_DMA_PRIOR11 (*(volatile uint8_t *)(&_MBAR[0x8047])) +#define MCF_DMA_PRIOR12 (*(volatile uint8_t *)(&_MBAR[0x8048])) +#define MCF_DMA_PRIOR13 (*(volatile uint8_t *)(&_MBAR[0x8049])) +#define MCF_DMA_PRIOR14 (*(volatile uint8_t *)(&_MBAR[0x804A])) +#define MCF_DMA_PRIOR15 (*(volatile uint8_t *)(&_MBAR[0x804B])) +#define MCF_DMA_PRIOR16 (*(volatile uint8_t *)(&_MBAR[0x804C])) +#define MCF_DMA_PRIOR17 (*(volatile uint8_t *)(&_MBAR[0x804D])) +#define MCF_DMA_PRIOR18 (*(volatile uint8_t *)(&_MBAR[0x804E])) +#define MCF_DMA_PRIOR19 (*(volatile uint8_t *)(&_MBAR[0x804F])) +#define MCF_DMA_PRIOR20 (*(volatile uint8_t *)(&_MBAR[0x8050])) +#define MCF_DMA_PRIOR21 (*(volatile uint8_t *)(&_MBAR[0x8051])) +#define MCF_DMA_PRIOR22 (*(volatile uint8_t *)(&_MBAR[0x8052])) +#define MCF_DMA_PRIOR23 (*(volatile uint8_t *)(&_MBAR[0x8053])) +#define MCF_DMA_PRIOR24 (*(volatile uint8_t *)(&_MBAR[0x8054])) +#define MCF_DMA_PRIOR25 (*(volatile uint8_t *)(&_MBAR[0x8055])) +#define MCF_DMA_PRIOR26 (*(volatile uint8_t *)(&_MBAR[0x8056])) +#define MCF_DMA_PRIOR27 (*(volatile uint8_t *)(&_MBAR[0x8057])) +#define MCF_DMA_PRIOR28 (*(volatile uint8_t *)(&_MBAR[0x8058])) +#define MCF_DMA_PRIOR29 (*(volatile uint8_t *)(&_MBAR[0x8059])) +#define MCF_DMA_PRIOR30 (*(volatile uint8_t *)(&_MBAR[0x805A])) +#define MCF_DMA_PRIOR31 (*(volatile uint8_t *)(&_MBAR[0x805B])) +#define MCF_DMA_IMCR (*(volatile uint32_t*)(&_MBAR[0x805C])) +#define MCF_DMA_TSKSZ0 (*(volatile uint32_t*)(&_MBAR[0x8060])) +#define MCF_DMA_TSKSZ1 (*(volatile uint32_t*)(&_MBAR[0x8064])) +#define MCF_DMA_DBGCOMP0 (*(volatile uint32_t*)(&_MBAR[0x8070])) +#define MCF_DMA_DBGCOMP2 (*(volatile uint32_t*)(&_MBAR[0x8074])) +#define MCF_DMA_DBGCTL (*(volatile uint32_t*)(&_MBAR[0x8078])) +#define MCF_DMA_TCR(x) (*(volatile uint16_t*)(&_MBAR[0x801C + ((x)*0x2)])) +#define MCF_DMA_PRIOR(x) (*(volatile uint8_t *)(&_MBAR[0x803C + ((x)*0x1)])) + + +/* Bit definitions and macros for MCF_DMA_TASKBAR */ +#define MCF_DMA_TASKBAR_TASK_BASE_ADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_CP */ +#define MCF_DMA_CP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_EP */ +#define MCF_DMA_EP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_VP */ +#define MCF_DMA_VP_VARIABLE_POINTER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_PTD */ +#define MCF_DMA_PTD_PCTL0 (0x1) +#define MCF_DMA_PTD_PCTL1 (0x2) +#define MCF_DMA_PTD_PCTL13 (0x2000) +#define MCF_DMA_PTD_PCTL14 (0x4000) +#define MCF_DMA_PTD_PCTL15 (0x8000) + +/* Bit definitions and macros for MCF_DMA_DIPR */ +#define MCF_DMA_DIPR_TASK(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DIMR */ +#define MCF_DMA_DIMR_TASK(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_TCR */ +#define MCF_DMA_TCR_ASTSKNUM(x) (((x)&0xF)<<0) +#define MCF_DMA_TCR_HLDINITNUM (0x20) +#define MCF_DMA_TCR_HIPRITSKEN (0x40) +#define MCF_DMA_TCR_ASTRT (0x80) +#define MCF_DMA_TCR_INITNUM(x) (((x)&0x1F)<<0x8) +#define MCF_DMA_TCR_ALWINIT (0x2000) +#define MCF_DMA_TCR_V (0x4000) +#define MCF_DMA_TCR_EN (0x8000) + +/* Bit definitions and macros for MCF_DMA_PRIOR */ +#define MCF_DMA_PRIOR_PRI(x) (((x)&0x7)<<0) +#define MCF_DMA_PRIOR_HLD (0x80) + +/* Bit definitions and macros for MCF_DMA_IMCR */ +#define MCF_DMA_IMCR_IMC16(x) (((x)&0x3)<<0) +#define MCF_DMA_IMCR_IMC17(x) (((x)&0x3)<<0x2) +#define MCF_DMA_IMCR_IMC18(x) (((x)&0x3)<<0x4) +#define MCF_DMA_IMCR_IMC19(x) (((x)&0x3)<<0x6) +#define MCF_DMA_IMCR_IMC20(x) (((x)&0x3)<<0x8) +#define MCF_DMA_IMCR_IMC21(x) (((x)&0x3)<<0xA) +#define MCF_DMA_IMCR_IMC22(x) (((x)&0x3)<<0xC) +#define MCF_DMA_IMCR_IMC23(x) (((x)&0x3)<<0xE) +#define MCF_DMA_IMCR_IMC24(x) (((x)&0x3)<<0x10) +#define MCF_DMA_IMCR_IMC25(x) (((x)&0x3)<<0x12) +#define MCF_DMA_IMCR_IMC26(x) (((x)&0x3)<<0x14) +#define MCF_DMA_IMCR_IMC27(x) (((x)&0x3)<<0x16) +#define MCF_DMA_IMCR_IMC28(x) (((x)&0x3)<<0x18) +#define MCF_DMA_IMCR_IMC29(x) (((x)&0x3)<<0x1A) +#define MCF_DMA_IMCR_IMC30(x) (((x)&0x3)<<0x1C) +#define MCF_DMA_IMCR_IMC31(x) (((x)&0x3)<<0x1E) + + +#define MCF_DMA_IMCR_IMC16_FEC0RX (0x00000000) +#define MCF_DMA_IMCR_IMC17_FEC0TX (0x00000000) +#define MCF_DMA_IMCR_IMC18_FEC0RX (0x00000020) +#define MCF_DMA_IMCR_IMC19_FEC0TX (0x00000080) +#define MCF_DMA_IMCR_IMC20_FEC1RX (0x00000100) +#define MCF_DMA_IMCR_IMC21_DREQ1 (0x00000000) +#define MCF_DMA_IMCR_IMC21_FEC1TX (0x00000400) +#define MCF_DMA_IMCR_IMC22_FEC0RX (0x00001000) +#define MCF_DMA_IMCR_IMC23_FEC0TX (0x00004000) +#define MCF_DMA_IMCR_IMC24_CTM0 (0x00010000) +#define MCF_DMA_IMCR_IMC24_FEC1RX (0x00020000) +#define MCF_DMA_IMCR_IMC25_CTM1 (0x00040000) +#define MCF_DMA_IMCR_IMC25_FEC1TX (0x00080000) +#define MCF_DMA_IMCR_IMC26_USBEP4 (0x00000000) +#define MCF_DMA_IMCR_IMC26_CTM2 (0x00200000) +#define MCF_DMA_IMCR_IMC27_USBEP5 (0x00000000) +#define MCF_DMA_IMCR_IMC27_CTM3 (0x00800000) +#define MCF_DMA_IMCR_IMC28_USBEP6 (0x00000000) +#define MCF_DMA_IMCR_IMC28_CTM4 (0x01000000) +#define MCF_DMA_IMCR_IMC28_DREQ1 (0x02000000) +#define MCF_DMA_IMCR_IMC28_PSC2RX (0x03000000) +#define MCF_DMA_IMCR_IMC29_DREQ1 (0x04000000) +#define MCF_DMA_IMCR_IMC29_CTM5 (0x08000000) +#define MCF_DMA_IMCR_IMC29_PSC2TX (0x0C000000) +#define MCF_DMA_IMCR_IMC30_FEC1RX (0x00000000) +#define MCF_DMA_IMCR_IMC30_CTM6 (0x10000000) +#define MCF_DMA_IMCR_IMC30_PSC3RX (0x30000000) +#define MCF_DMA_IMCR_IMC31_FEC1TX (0x00000000) +#define MCF_DMA_IMCR_IMC31_CTM7 (0x80000000) +#define MCF_DMA_IMCR_IMC31_PSC3TX (0xC0000000) + +/* Bit definitions and macros for MCF_DMA_TSKSZ0 */ +#define MCF_DMA_TSKSZ0_DSTSZ7(x) (((x)&0x3)<<0) +#define MCF_DMA_TSKSZ0_SRCSZ7(x) (((x)&0x3)<<0x2) +#define MCF_DMA_TSKSZ0_DSTSZ6(x) (((x)&0x3)<<0x4) +#define MCF_DMA_TSKSZ0_SRCSZ6(x) (((x)&0x3)<<0x6) +#define MCF_DMA_TSKSZ0_DSTSZ5(x) (((x)&0x3)<<0x8) +#define MCF_DMA_TSKSZ0_SRCSZ5(x) (((x)&0x3)<<0xA) +#define MCF_DMA_TSKSZ0_DSTSZ4(x) (((x)&0x3)<<0xC) +#define MCF_DMA_TSKSZ0_SRCSZ4(x) (((x)&0x3)<<0xE) +#define MCF_DMA_TSKSZ0_DSTSZ3(x) (((x)&0x3)<<0x10) +#define MCF_DMA_TSKSZ0_SRCSZ3(x) (((x)&0x3)<<0x12) +#define MCF_DMA_TSKSZ0_DSTSZ2(x) (((x)&0x3)<<0x14) +#define MCF_DMA_TSKSZ0_SRCSZ2(x) (((x)&0x3)<<0x16) +#define MCF_DMA_TSKSZ0_DSTSZ1(x) (((x)&0x3)<<0x18) +#define MCF_DMA_TSKSZ0_SRCSZ1(x) (((x)&0x3)<<0x1A) +#define MCF_DMA_TSKSZ0_DSTSZ0(x) (((x)&0x3)<<0x1C) +#define MCF_DMA_TSKSZ0_SRCSZ0(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_DMA_TSKSZ1 */ +#define MCF_DMA_TSKSZ1_DSTSZ15(x) (((x)&0x3)<<0) +#define MCF_DMA_TSKSZ1_SRCSZ15(x) (((x)&0x3)<<0x2) +#define MCF_DMA_TSKSZ1_DSTSZ14(x) (((x)&0x3)<<0x4) +#define MCF_DMA_TSKSZ1_SRCSZ14(x) (((x)&0x3)<<0x6) +#define MCF_DMA_TSKSZ1_DSTSZ13(x) (((x)&0x3)<<0x8) +#define MCF_DMA_TSKSZ1_SRCSZ13(x) (((x)&0x3)<<0xA) +#define MCF_DMA_TSKSZ1_DSTSZ12(x) (((x)&0x3)<<0xC) +#define MCF_DMA_TSKSZ1_SRCSZ12(x) (((x)&0x3)<<0xE) +#define MCF_DMA_TSKSZ1_DSTSZ11(x) (((x)&0x3)<<0x10) +#define MCF_DMA_TSKSZ1_SRCSZ11(x) (((x)&0x3)<<0x12) +#define MCF_DMA_TSKSZ1_DSTSZ10(x) (((x)&0x3)<<0x14) +#define MCF_DMA_TSKSZ1_SRCSZ10(x) (((x)&0x3)<<0x16) +#define MCF_DMA_TSKSZ1_DSTSZ9(x) (((x)&0x3)<<0x18) +#define MCF_DMA_TSKSZ1_SRCSZ9(x) (((x)&0x3)<<0x1A) +#define MCF_DMA_TSKSZ1_DSTSZ8(x) (((x)&0x3)<<0x1C) +#define MCF_DMA_TSKSZ1_SRCSZ8(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_DMA_DBGCOMP0 */ +#define MCF_DMA_DBGCOMP0_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DBGCOMP2 */ +#define MCF_DMA_DBGCOMP2_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DBGCTL */ +#define MCF_DMA_DBGCTL_I (0x2) +#define MCF_DMA_DBGCTL_E (0x4) +#define MCF_DMA_DBGCTL_AND_OR (0x80) +#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_2(x) (((x)&0x7)<<0x8) +#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_1(x) (((x)&0x7)<<0xB) +#define MCF_DMA_DBGCTL_B (0x4000) +#define MCF_DMA_DBGCTL_AA (0x8000) +#define MCF_DMA_DBGCTL_BLOCK_TASKS(x) (((x)&0xFFFF)<<0x10) + + +#endif /* __MCF5475_DMA_H__ */ diff --git a/tos/jtagwait/include/MCF5475_DSPI.h b/tos/jtagwait/include/MCF5475_DSPI.h new file mode 100644 index 0000000..76cac28 --- /dev/null +++ b/tos/jtagwait/include/MCF5475_DSPI.h @@ -0,0 +1,150 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_DSPI_H__ +#define __MCF5475_DSPI_H__ + + +/********************************************************************* +* +* DMA Serial Peripheral Interface (DSPI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DSPI_DMCR (*(volatile uint32_t*)(&_MBAR[0x8A00])) +#define MCF_DSPI_DTCR (*(volatile uint32_t*)(&_MBAR[0x8A08])) +#define MCF_DSPI_DCTAR0 (*(volatile uint32_t*)(&_MBAR[0x8A0C])) +#define MCF_DSPI_DCTAR1 (*(volatile uint32_t*)(&_MBAR[0x8A10])) +#define MCF_DSPI_DCTAR2 (*(volatile uint32_t*)(&_MBAR[0x8A14])) +#define MCF_DSPI_DCTAR3 (*(volatile uint32_t*)(&_MBAR[0x8A18])) +#define MCF_DSPI_DCTAR4 (*(volatile uint32_t*)(&_MBAR[0x8A1C])) +#define MCF_DSPI_DCTAR5 (*(volatile uint32_t*)(&_MBAR[0x8A20])) +#define MCF_DSPI_DCTAR6 (*(volatile uint32_t*)(&_MBAR[0x8A24])) +#define MCF_DSPI_DCTAR7 (*(volatile uint32_t*)(&_MBAR[0x8A28])) +#define MCF_DSPI_DSR (*(volatile uint32_t*)(&_MBAR[0x8A2C])) +#define MCF_DSPI_DIRSR (*(volatile uint32_t*)(&_MBAR[0x8A30])) +#define MCF_DSPI_DTFR (*(volatile uint32_t*)(&_MBAR[0x8A34])) +#define MCF_DSPI_DRFR (*(volatile uint32_t*)(&_MBAR[0x8A38])) +#define MCF_DSPI_DTFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A3C])) +#define MCF_DSPI_DTFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A40])) +#define MCF_DSPI_DTFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A44])) +#define MCF_DSPI_DTFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A48])) +#define MCF_DSPI_DRFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A7C])) +#define MCF_DSPI_DRFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A80])) +#define MCF_DSPI_DRFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A84])) +#define MCF_DSPI_DRFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A88])) +#define MCF_DSPI_DCTAR(x) (*(volatile uint32_t*)(&_MBAR[0x8A0C + ((x)*0x4)])) +#define MCF_DSPI_DTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A3C + ((x)*0x4)])) +#define MCF_DSPI_DRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A7C + ((x)*0x4)])) + + +/* Bit definitions and macros for MCF_DSPI_DMCR */ +#define MCF_DSPI_DMCR_HALT (0x1) +#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x3)<<0x8) +#define MCF_DSPI_DMCR_SMPL_PT_0CLK (0) +#define MCF_DSPI_DMCR_SMPL_PT_1CLK (0x100) +#define MCF_DSPI_DMCR_SMPL_PT_2CLK (0x200) +#define MCF_DSPI_DMCR_CRXF (0x400) +#define MCF_DSPI_DMCR_CTXF (0x800) +#define MCF_DSPI_DMCR_DRXF (0x1000) +#define MCF_DSPI_DMCR_DTXF (0x2000) +#define MCF_DSPI_DMCR_CSIS0 (0x10000) +#define MCF_DSPI_DMCR_CSIS2 (0x40000) +#define MCF_DSPI_DMCR_CSIS3 (0x80000) +#define MCF_DSPI_DMCR_CSIS5 (0x200000) +#define MCF_DSPI_DMCR_ROOE (0x1000000) +#define MCF_DSPI_DMCR_PCSSE (0x2000000) +#define MCF_DSPI_DMCR_MTFE (0x4000000) +#define MCF_DSPI_DMCR_FRZ (0x8000000) +#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x3)<<0x1C) +#define MCF_DSPI_DMCR_CSCK (0x40000000) +#define MCF_DSPI_DMCR_MSTR (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DTCR */ +#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_DSPI_DCTAR */ +#define MCF_DSPI_DCTAR_BR(x) (((x)&0xF)<<0) +#define MCF_DSPI_DCTAR_DT(x) (((x)&0xF)<<0x4) +#define MCF_DSPI_DCTAR_ASC(x) (((x)&0xF)<<0x8) +#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0xF)<<0xC) +#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x3)<<0x10) +#define MCF_DSPI_DCTAR_PBR_1CLK (0) +#define MCF_DSPI_DCTAR_PBR_3CLK (0x10000) +#define MCF_DSPI_DCTAR_PBR_5CLK (0x20000) +#define MCF_DSPI_DCTAR_PBR_7CLK (0x30000) +#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x3)<<0x12) +#define MCF_DSPI_DCTAR_PDT_1CLK (0) +#define MCF_DSPI_DCTAR_PDT_3CLK (0x40000) +#define MCF_DSPI_DCTAR_PDT_5CLK (0x80000) +#define MCF_DSPI_DCTAR_PDT_7CLK (0xC0000) +#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x3)<<0x14) +#define MCF_DSPI_DCTAR_PASC_1CLK (0) +#define MCF_DSPI_DCTAR_PASC_3CLK (0x100000) +#define MCF_DSPI_DCTAR_PASC_5CLK (0x200000) +#define MCF_DSPI_DCTAR_PASC_7CLK (0x300000) +#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x3)<<0x16) +#define MCF_DSPI_DCTAR_LSBFE (0x1000000) +#define MCF_DSPI_DCTAR_CPHA (0x2000000) +#define MCF_DSPI_DCTAR_CPOL (0x4000000) +#define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0xF)<<0x1B) + +/* Bit definitions and macros for MCF_DSPI_DSR */ +#define MCF_DSPI_DSR_RXPTR(x) (((x)&0xF)<<0) +#define MCF_DSPI_DSR_RXCTR(x) (((x)&0xF)<<0x4) +#define MCF_DSPI_DSR_TXPTR(x) (((x)&0xF)<<0x8) +#define MCF_DSPI_DSR_TXCTR(x) (((x)&0xF)<<0xC) +#define MCF_DSPI_DSR_RFDF (0x20000) +#define MCF_DSPI_DSR_RFOF (0x80000) +#define MCF_DSPI_DSR_TFFF (0x2000000) +#define MCF_DSPI_DSR_TFUF (0x8000000) +#define MCF_DSPI_DSR_EOQF (0x10000000) +#define MCF_DSPI_DSR_TXRXS (0x40000000) +#define MCF_DSPI_DSR_TCF (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DIRSR */ +#define MCF_DSPI_DIRSR_RFDFS (0x10000) +#define MCF_DSPI_DIRSR_RFDFE (0x20000) +#define MCF_DSPI_DIRSR_RFOFE (0x80000) +#define MCF_DSPI_DIRSR_TFFFS (0x1000000) +#define MCF_DSPI_DIRSR_TFFFE (0x2000000) +#define MCF_DSPI_DIRSR_TFUFE (0x8000000) +#define MCF_DSPI_DIRSR_EOQFE (0x10000000) +#define MCF_DSPI_DIRSR_TCFE (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DTFR */ +#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0xFFFF)<<0) +#define MCF_DSPI_DTFR_CS0 (0x10000) +#define MCF_DSPI_DTFR_CS2 (0x40000) +#define MCF_DSPI_DTFR_CS3 (0x80000) +#define MCF_DSPI_DTFR_CS5 (0x200000) +#define MCF_DSPI_DTFR_CTCNT (0x4000000) +#define MCF_DSPI_DTFR_EOQ (0x8000000) +#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x7)<<0x1C) +#define MCF_DSPI_DTFR_CONT (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DRFR */ +#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_DSPI_DTFDR */ +#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0xFFFF)<<0) +#define MCF_DSPI_DTFDR_TXCMD(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_DSPI_DRFDR */ +#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0xFFFF)<<0) + + +#endif /* __MCF5475_DSPI_H__ */ diff --git a/tos/jtagwait/include/MCF5475_EPORT.h b/tos/jtagwait/include/MCF5475_EPORT.h new file mode 100644 index 0000000..6506196 --- /dev/null +++ b/tos/jtagwait/include/MCF5475_EPORT.h @@ -0,0 +1,123 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_EPORT_H__ +#define __MCF5475_EPORT_H__ + + +/********************************************************************* +* +* Edge Port Module (EPORT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_EPORT_EPPAR (*(volatile uint16_t*)(&_MBAR[0xF00])) +#define MCF_EPORT_EPDDR (*(volatile uint8_t *)(&_MBAR[0xF04])) +#define MCF_EPORT_EPIER (*(volatile uint8_t *)(&_MBAR[0xF05])) +#define MCF_EPORT_EPDR (*(volatile uint8_t *)(&_MBAR[0xF08])) +#define MCF_EPORT_EPPDR (*(volatile uint8_t *)(&_MBAR[0xF09])) +#define MCF_EPORT_EPFR (*(volatile uint8_t *)(&_MBAR[0xF0C])) + + + +/* Bit definitions and macros for MCF_EPORT_EPPAR */ +#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2) +#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4) +#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8) +#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC) +#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4) +#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10) +#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20) +#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30) +#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6) +#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40) +#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80) +#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0) +#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8) +#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100) +#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200) +#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300) +#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA) +#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400) +#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800) +#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00) +#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC) +#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) +#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) +#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) +#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE) +#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) +#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) +#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) +#define MCF_EPORT_EPPAR_LEVEL (0) +#define MCF_EPORT_EPPAR_RISING (0x1) +#define MCF_EPORT_EPPAR_FALLING (0x2) +#define MCF_EPORT_EPPAR_BOTH (0x3) + +/* Bit definitions and macros for MCF_EPORT_EPDDR */ +#define MCF_EPORT_EPDDR_EPDD1 (0x2) +#define MCF_EPORT_EPDDR_EPDD2 (0x4) +#define MCF_EPORT_EPDDR_EPDD3 (0x8) +#define MCF_EPORT_EPDDR_EPDD4 (0x10) +#define MCF_EPORT_EPDDR_EPDD5 (0x20) +#define MCF_EPORT_EPDDR_EPDD6 (0x40) +#define MCF_EPORT_EPDDR_EPDD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPIER */ +#define MCF_EPORT_EPIER_EPIE1 (0x2) +#define MCF_EPORT_EPIER_EPIE2 (0x4) +#define MCF_EPORT_EPIER_EPIE3 (0x8) +#define MCF_EPORT_EPIER_EPIE4 (0x10) +#define MCF_EPORT_EPIER_EPIE5 (0x20) +#define MCF_EPORT_EPIER_EPIE6 (0x40) +#define MCF_EPORT_EPIER_EPIE7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPDR */ +#define MCF_EPORT_EPDR_EPD1 (0x2) +#define MCF_EPORT_EPDR_EPD2 (0x4) +#define MCF_EPORT_EPDR_EPD3 (0x8) +#define MCF_EPORT_EPDR_EPD4 (0x10) +#define MCF_EPORT_EPDR_EPD5 (0x20) +#define MCF_EPORT_EPDR_EPD6 (0x40) +#define MCF_EPORT_EPDR_EPD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPPDR */ +#define MCF_EPORT_EPPDR_EPPD1 (0x2) +#define MCF_EPORT_EPPDR_EPPD2 (0x4) +#define MCF_EPORT_EPPDR_EPPD3 (0x8) +#define MCF_EPORT_EPPDR_EPPD4 (0x10) +#define MCF_EPORT_EPPDR_EPPD5 (0x20) +#define MCF_EPORT_EPPDR_EPPD6 (0x40) +#define MCF_EPORT_EPPDR_EPPD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPFR */ +#define MCF_EPORT_EPFR_EPF1 (0x2) +#define MCF_EPORT_EPFR_EPF2 (0x4) +#define MCF_EPORT_EPFR_EPF3 (0x8) +#define MCF_EPORT_EPFR_EPF4 (0x10) +#define MCF_EPORT_EPFR_EPF5 (0x20) +#define MCF_EPORT_EPFR_EPF6 (0x40) +#define MCF_EPORT_EPFR_EPF7 (0x80) + + +#endif /* __MCF5475_EPORT_H__ */ diff --git a/tos/jtagwait/include/MCF5475_FBCS.h b/tos/jtagwait/include/MCF5475_FBCS.h new file mode 100644 index 0000000..37daf00 --- /dev/null +++ b/tos/jtagwait/include/MCF5475_FBCS.h @@ -0,0 +1,100 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_FBCS_H__ +#define __MCF5475_FBCS_H__ + + +/********************************************************************* +* +* FlexBus Chip Select Module (FBCS) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_FBCS0_CSAR (*(volatile uint32_t*)(&_MBAR[0x500])) +#define MCF_FBCS0_CSMR (*(volatile uint32_t*)(&_MBAR[0x504])) +#define MCF_FBCS0_CSCR (*(volatile uint32_t*)(&_MBAR[0x508])) + +#define MCF_FBCS1_CSAR (*(volatile uint32_t*)(&_MBAR[0x50C])) +#define MCF_FBCS1_CSMR (*(volatile uint32_t*)(&_MBAR[0x510])) +#define MCF_FBCS1_CSCR (*(volatile uint32_t*)(&_MBAR[0x514])) + +#define MCF_FBCS2_CSAR (*(volatile uint32_t*)(&_MBAR[0x518])) +#define MCF_FBCS2_CSMR (*(volatile uint32_t*)(&_MBAR[0x51C])) +#define MCF_FBCS2_CSCR (*(volatile uint32_t*)(&_MBAR[0x520])) + +#define MCF_FBCS3_CSAR (*(volatile uint32_t*)(&_MBAR[0x524])) +#define MCF_FBCS3_CSMR (*(volatile uint32_t*)(&_MBAR[0x528])) +#define MCF_FBCS3_CSCR (*(volatile uint32_t*)(&_MBAR[0x52C])) + +#define MCF_FBCS4_CSAR (*(volatile uint32_t*)(&_MBAR[0x530])) +#define MCF_FBCS4_CSMR (*(volatile uint32_t*)(&_MBAR[0x534])) +#define MCF_FBCS4_CSCR (*(volatile uint32_t*)(&_MBAR[0x538])) + +#define MCF_FBCS5_CSAR (*(volatile uint32_t*)(&_MBAR[0x53C])) +#define MCF_FBCS5_CSMR (*(volatile uint32_t*)(&_MBAR[0x540])) +#define MCF_FBCS5_CSCR (*(volatile uint32_t*)(&_MBAR[0x544])) + +#define MCF_FBCS_CSAR(x) (*(volatile uint32_t*)(&_MBAR[0x500 + ((x)*0xC)])) +#define MCF_FBCS_CSMR(x) (*(volatile uint32_t*)(&_MBAR[0x504 + ((x)*0xC)])) +#define MCF_FBCS_CSCR(x) (*(volatile uint32_t*)(&_MBAR[0x508 + ((x)*0xC)])) + + +/* Bit definitions and macros for MCF_FBCS_CSAR */ +#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) + +/* Bit definitions and macros for MCF_FBCS_CSMR */ +#define MCF_FBCS_CSMR_V (0x1) +#define MCF_FBCS_CSMR_WP (0x100) +#define MCF_FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<0x10) +#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) +#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) +#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) +#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) +#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) +#define MCF_FBCS_CSMR_BAM_256M (0xFFF0000) +#define MCF_FBCS_CSMR_BAM_128M (0x7FF0000) +#define MCF_FBCS_CSMR_BAM_64M (0x3FF0000) +#define MCF_FBCS_CSMR_BAM_32M (0x1FF0000) +#define MCF_FBCS_CSMR_BAM_16M (0xFF0000) +#define MCF_FBCS_CSMR_BAM_8M (0x7F0000) +#define MCF_FBCS_CSMR_BAM_4M (0x3F0000) +#define MCF_FBCS_CSMR_BAM_2M (0x1F0000) +#define MCF_FBCS_CSMR_BAM_1M (0xF0000) +#define MCF_FBCS_CSMR_BAM_1024K (0xF0000) +#define MCF_FBCS_CSMR_BAM_512K (0x70000) +#define MCF_FBCS_CSMR_BAM_256K (0x30000) +#define MCF_FBCS_CSMR_BAM_128K (0x10000) +#define MCF_FBCS_CSMR_BAM_64K (0) + +/* Bit definitions and macros for MCF_FBCS_CSCR */ +#define MCF_FBCS_CSCR_BSTW (0x8) +#define MCF_FBCS_CSCR_BSTR (0x10) +#define MCF_FBCS_CSCR_BEM (0x20) +#define MCF_FBCS_CSCR_PS(x) (((x)&0x3)<<0x6) +#define MCF_FBCS_CSCR_PS_32 (0) +#define MCF_FBCS_CSCR_PS_8 (0x40) +#define MCF_FBCS_CSCR_PS_16 (0x80) +#define MCF_FBCS_CSCR_AA (0x100) +#define MCF_FBCS_CSCR_WS(x) (((x)&0x3F)<<0xA) +#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x3)<<0x10) +#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x3)<<0x12) +#define MCF_FBCS_CSCR_ASET(x) (((x)&0x3)<<0x14) +#define MCF_FBCS_CSCR_SWSEN (0x800000) +#define MCF_FBCS_CSCR_SWS(x) (((x)&0x3F)<<0x1A) + + +#endif /* __MCF5475_FBCS_H__ */ diff --git a/tos/jtagwait/include/MCF5475_FEC.h b/tos/jtagwait/include/MCF5475_FEC.h new file mode 100644 index 0000000..fdd9403 --- /dev/null +++ b/tos/jtagwait/include/MCF5475_FEC.h @@ -0,0 +1,680 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_FEC_H__ +#define __MCF5475_FEC_H__ + + +/********************************************************************* +* +* Fast Ethernet Controller(FEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_FEC0_EIR (*(volatile uint32_t*)(&_MBAR[0x9004])) +#define MCF_FEC0_EIMR (*(volatile uint32_t*)(&_MBAR[0x9008])) +#define MCF_FEC0_ECR (*(volatile uint32_t*)(&_MBAR[0x9024])) +#define MCF_FEC0_MMFR (*(volatile uint32_t*)(&_MBAR[0x9040])) +#define MCF_FEC0_MSCR (*(volatile uint32_t*)(&_MBAR[0x9044])) +#define MCF_FEC0_MIBC (*(volatile uint32_t*)(&_MBAR[0x9064])) +#define MCF_FEC0_RCR (*(volatile uint32_t*)(&_MBAR[0x9084])) +#define MCF_FEC0_RHR (*(volatile uint32_t*)(&_MBAR[0x9088])) +#define MCF_FEC0_TCR (*(volatile uint32_t*)(&_MBAR[0x90C4])) +#define MCF_FEC0_PALR (*(volatile uint32_t*)(&_MBAR[0x90E4])) +#define MCF_FEC0_PAHR (*(volatile uint32_t*)(&_MBAR[0x90E8])) +#define MCF_FEC0_OPD (*(volatile uint32_t*)(&_MBAR[0x90EC])) +#define MCF_FEC0_IAUR (*(volatile uint32_t*)(&_MBAR[0x9118])) +#define MCF_FEC0_IALR (*(volatile uint32_t*)(&_MBAR[0x911C])) +#define MCF_FEC0_GAUR (*(volatile uint32_t*)(&_MBAR[0x9120])) +#define MCF_FEC0_GALR (*(volatile uint32_t*)(&_MBAR[0x9124])) +#define MCF_FEC0_FECTFWR (*(volatile uint32_t*)(&_MBAR[0x9144])) +#define MCF_FEC0_FECRFDR (*(volatile uint32_t*)(&_MBAR[0x9184])) +#define MCF_FEC0_FECRFSR (*(volatile uint32_t*)(&_MBAR[0x9188])) +#define MCF_FEC0_FECRFCR (*(volatile uint32_t*)(&_MBAR[0x918C])) +#define MCF_FEC0_FECRLRFP (*(volatile uint32_t*)(&_MBAR[0x9190])) +#define MCF_FEC0_FECRLWFP (*(volatile uint32_t*)(&_MBAR[0x9194])) +#define MCF_FEC0_FECRFAR (*(volatile uint32_t*)(&_MBAR[0x9198])) +#define MCF_FEC0_FECRFRP (*(volatile uint32_t*)(&_MBAR[0x919C])) +#define MCF_FEC0_FECRFWP (*(volatile uint32_t*)(&_MBAR[0x91A0])) +#define MCF_FEC0_FECTFDR (*(volatile uint32_t*)(&_MBAR[0x91A4])) +#define MCF_FEC0_FECTFSR (*(volatile uint32_t*)(&_MBAR[0x91A8])) +#define MCF_FEC0_FECTFCR (*(volatile uint32_t*)(&_MBAR[0x91AC])) +#define MCF_FEC0_FECTLRFP (*(volatile uint32_t*)(&_MBAR[0x91B0])) +#define MCF_FEC0_FECTLWFP (*(volatile uint32_t*)(&_MBAR[0x91B4])) +#define MCF_FEC0_FECTFAR (*(volatile uint32_t*)(&_MBAR[0x91B8])) +#define MCF_FEC0_FECTFRP (*(volatile uint32_t*)(&_MBAR[0x91BC])) +#define MCF_FEC0_FECTFWP (*(volatile uint32_t*)(&_MBAR[0x91C0])) +#define MCF_FEC0_FECFRST (*(volatile uint32_t*)(&_MBAR[0x91C4])) +#define MCF_FEC0_FECCTCWR (*(volatile uint32_t*)(&_MBAR[0x91C8])) +#define MCF_FEC0_RMON_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9200])) +#define MCF_FEC0_RMON_T_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9204])) +#define MCF_FEC0_RMON_T_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9208])) +#define MCF_FEC0_RMON_T_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x920C])) +#define MCF_FEC0_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9210])) +#define MCF_FEC0_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9214])) +#define MCF_FEC0_RMON_T_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9218])) +#define MCF_FEC0_RMON_T_FRAG (*(volatile uint32_t*)(&_MBAR[0x921C])) +#define MCF_FEC0_RMON_T_JAB (*(volatile uint32_t*)(&_MBAR[0x9220])) +#define MCF_FEC0_RMON_T_COL (*(volatile uint32_t*)(&_MBAR[0x9224])) +#define MCF_FEC0_RMON_T_P64 (*(volatile uint32_t*)(&_MBAR[0x9228])) +#define MCF_FEC0_RMON_T_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x922C])) +#define MCF_FEC0_RMON_T_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9230])) +#define MCF_FEC0_RMON_T_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9234])) +#define MCF_FEC0_RMON_T_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9238])) +#define MCF_FEC0_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x923C])) +#define MCF_FEC0_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9240])) +#define MCF_FEC0_RMON_T_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9244])) +#define MCF_FEC0_IEEE_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9248])) +#define MCF_FEC0_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x924C])) +#define MCF_FEC0_IEEE_T_1COL (*(volatile uint32_t*)(&_MBAR[0x9250])) +#define MCF_FEC0_IEEE_T_MCOL (*(volatile uint32_t*)(&_MBAR[0x9254])) +#define MCF_FEC0_IEEE_T_DEF (*(volatile uint32_t*)(&_MBAR[0x9258])) +#define MCF_FEC0_IEEE_T_LCOL (*(volatile uint32_t*)(&_MBAR[0x925C])) +#define MCF_FEC0_IEEE_T_EXCOL (*(volatile uint32_t*)(&_MBAR[0x9260])) +#define MCF_FEC0_IEEE_T_MACERR (*(volatile uint32_t*)(&_MBAR[0x9264])) +#define MCF_FEC0_IEEE_T_CSERR (*(volatile uint32_t*)(&_MBAR[0x9268])) +#define MCF_FEC0_IEEE_T_SQE (*(volatile uint32_t*)(&_MBAR[0x926C])) +#define MCF_FEC0_IEEE_T_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9270])) +#define MCF_FEC0_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9274])) +#define MCF_FEC0_RMON_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9280])) +#define MCF_FEC0_RMON_R_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9284])) +#define MCF_FEC0_RMON_R_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9288])) +#define MCF_FEC0_RMON_R_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x928C])) +#define MCF_FEC0_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9290])) +#define MCF_FEC0_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9294])) +#define MCF_FEC0_RMON_R_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9298])) +#define MCF_FEC0_RMON_R_FRAG (*(volatile uint32_t*)(&_MBAR[0x929C])) +#define MCF_FEC0_RMON_R_JAB (*(volatile uint32_t*)(&_MBAR[0x92A0])) +#define MCF_FEC0_RMON_R_RESVD_0 (*(volatile uint32_t*)(&_MBAR[0x92A4])) +#define MCF_FEC0_RMON_R_P64 (*(volatile uint32_t*)(&_MBAR[0x92A8])) +#define MCF_FEC0_RMON_R_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x92AC])) +#define MCF_FEC0_RMON_R_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x92B0])) +#define MCF_FEC0_RMON_R_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x92B4])) +#define MCF_FEC0_RMON_R_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x92B8])) +#define MCF_FEC0_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x92BC])) +#define MCF_FEC0_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x92C0])) +#define MCF_FEC0_RMON_R_OCTETS (*(volatile uint32_t*)(&_MBAR[0x92C4])) +#define MCF_FEC0_IEEE_R_DROP (*(volatile uint32_t*)(&_MBAR[0x92C8])) +#define MCF_FEC0_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x92CC])) +#define MCF_FEC0_IEEE_R_CRC (*(volatile uint32_t*)(&_MBAR[0x92D0])) +#define MCF_FEC0_IEEE_R_ALIGN (*(volatile uint32_t*)(&_MBAR[0x92D4])) +#define MCF_FEC0_IEEE_R_MACERR (*(volatile uint32_t*)(&_MBAR[0x92D8])) +#define MCF_FEC0_IEEE_R_FDXFC (*(volatile uint32_t*)(&_MBAR[0x92DC])) +#define MCF_FEC0_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x92E0])) + +#define MCF_FEC1_EIR (*(volatile uint32_t*)(&_MBAR[0x9804])) +#define MCF_FEC1_EIMR (*(volatile uint32_t*)(&_MBAR[0x9808])) +#define MCF_FEC1_ECR (*(volatile uint32_t*)(&_MBAR[0x9824])) +#define MCF_FEC1_MMFR (*(volatile uint32_t*)(&_MBAR[0x9840])) +#define MCF_FEC1_MSCR (*(volatile uint32_t*)(&_MBAR[0x9844])) +#define MCF_FEC1_MIBC (*(volatile uint32_t*)(&_MBAR[0x9864])) +#define MCF_FEC1_RCR (*(volatile uint32_t*)(&_MBAR[0x9884])) +#define MCF_FEC1_RHR (*(volatile uint32_t*)(&_MBAR[0x9888])) +#define MCF_FEC1_TCR (*(volatile uint32_t*)(&_MBAR[0x98C4])) +#define MCF_FEC1_PALR (*(volatile uint32_t*)(&_MBAR[0x98E4])) +#define MCF_FEC1_PAHR (*(volatile uint32_t*)(&_MBAR[0x98E8])) +#define MCF_FEC1_OPD (*(volatile uint32_t*)(&_MBAR[0x98EC])) +#define MCF_FEC1_IAUR (*(volatile uint32_t*)(&_MBAR[0x9918])) +#define MCF_FEC1_IALR (*(volatile uint32_t*)(&_MBAR[0x991C])) +#define MCF_FEC1_GAUR (*(volatile uint32_t*)(&_MBAR[0x9920])) +#define MCF_FEC1_GALR (*(volatile uint32_t*)(&_MBAR[0x9924])) +#define MCF_FEC1_FECTFWR (*(volatile uint32_t*)(&_MBAR[0x9944])) +#define MCF_FEC1_FECRFDR (*(volatile uint32_t*)(&_MBAR[0x9984])) +#define MCF_FEC1_FECRFSR (*(volatile uint32_t*)(&_MBAR[0x9988])) +#define MCF_FEC1_FECRFCR (*(volatile uint32_t*)(&_MBAR[0x998C])) +#define MCF_FEC1_FECRLRFP (*(volatile uint32_t*)(&_MBAR[0x9990])) +#define MCF_FEC1_FECRLWFP (*(volatile uint32_t*)(&_MBAR[0x9994])) +#define MCF_FEC1_FECRFAR (*(volatile uint32_t*)(&_MBAR[0x9998])) +#define MCF_FEC1_FECRFRP (*(volatile uint32_t*)(&_MBAR[0x999C])) +#define MCF_FEC1_FECRFWP (*(volatile uint32_t*)(&_MBAR[0x99A0])) +#define MCF_FEC1_FECTFDR (*(volatile uint32_t*)(&_MBAR[0x99A4])) +#define MCF_FEC1_FECTFSR (*(volatile uint32_t*)(&_MBAR[0x99A8])) +#define MCF_FEC1_FECTFCR (*(volatile uint32_t*)(&_MBAR[0x99AC])) +#define MCF_FEC1_FECTLRFP (*(volatile uint32_t*)(&_MBAR[0x99B0])) +#define MCF_FEC1_FECTLWFP (*(volatile uint32_t*)(&_MBAR[0x99B4])) +#define MCF_FEC1_FECTFAR (*(volatile uint32_t*)(&_MBAR[0x99B8])) +#define MCF_FEC1_FECTFRP (*(volatile uint32_t*)(&_MBAR[0x99BC])) +#define MCF_FEC1_FECTFWP (*(volatile uint32_t*)(&_MBAR[0x99C0])) +#define MCF_FEC1_FECFRST (*(volatile uint32_t*)(&_MBAR[0x99C4])) +#define MCF_FEC1_FECCTCWR (*(volatile uint32_t*)(&_MBAR[0x99C8])) +#define MCF_FEC1_RMON_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9A00])) +#define MCF_FEC1_RMON_T_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9A04])) +#define MCF_FEC1_RMON_T_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A08])) +#define MCF_FEC1_RMON_T_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A0C])) +#define MCF_FEC1_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9A10])) +#define MCF_FEC1_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A14])) +#define MCF_FEC1_RMON_T_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A18])) +#define MCF_FEC1_RMON_T_FRAG (*(volatile uint32_t*)(&_MBAR[0x9A1C])) +#define MCF_FEC1_RMON_T_JAB (*(volatile uint32_t*)(&_MBAR[0x9A20])) +#define MCF_FEC1_RMON_T_COL (*(volatile uint32_t*)(&_MBAR[0x9A24])) +#define MCF_FEC1_RMON_T_P64 (*(volatile uint32_t*)(&_MBAR[0x9A28])) +#define MCF_FEC1_RMON_T_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x9A2C])) +#define MCF_FEC1_RMON_T_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9A30])) +#define MCF_FEC1_RMON_T_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9A34])) +#define MCF_FEC1_RMON_T_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9A38])) +#define MCF_FEC1_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x9A3C])) +#define MCF_FEC1_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9A40])) +#define MCF_FEC1_RMON_T_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9A44])) +#define MCF_FEC1_IEEE_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9A48])) +#define MCF_FEC1_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x9A4C])) +#define MCF_FEC1_IEEE_T_1COL (*(volatile uint32_t*)(&_MBAR[0x9A50])) +#define MCF_FEC1_IEEE_T_MCOL (*(volatile uint32_t*)(&_MBAR[0x9A54])) +#define MCF_FEC1_IEEE_T_DEF (*(volatile uint32_t*)(&_MBAR[0x9A58])) +#define MCF_FEC1_IEEE_T_LCOL (*(volatile uint32_t*)(&_MBAR[0x9A5C])) +#define MCF_FEC1_IEEE_T_EXCOL (*(volatile uint32_t*)(&_MBAR[0x9A60])) +#define MCF_FEC1_IEEE_T_MACERR (*(volatile uint32_t*)(&_MBAR[0x9A64])) +#define MCF_FEC1_IEEE_T_CSERR (*(volatile uint32_t*)(&_MBAR[0x9A68])) +#define MCF_FEC1_IEEE_T_SQE (*(volatile uint32_t*)(&_MBAR[0x9A6C])) +#define MCF_FEC1_IEEE_T_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9A70])) +#define MCF_FEC1_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9A74])) +#define MCF_FEC1_RMON_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9A80])) +#define MCF_FEC1_RMON_R_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9A84])) +#define MCF_FEC1_RMON_R_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A88])) +#define MCF_FEC1_RMON_R_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A8C])) +#define MCF_FEC1_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9A90])) +#define MCF_FEC1_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A94])) +#define MCF_FEC1_RMON_R_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A98])) +#define MCF_FEC1_RMON_R_FRAG (*(volatile uint32_t*)(&_MBAR[0x9A9C])) +#define MCF_FEC1_RMON_R_JAB (*(volatile uint32_t*)(&_MBAR[0x9AA0])) +#define MCF_FEC1_RMON_R_RESVD_0 (*(volatile uint32_t*)(&_MBAR[0x9AA4])) +#define MCF_FEC1_RMON_R_P64 (*(volatile uint32_t*)(&_MBAR[0x9AA8])) +#define MCF_FEC1_RMON_R_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x9AAC])) +#define MCF_FEC1_RMON_R_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9AB0])) +#define MCF_FEC1_RMON_R_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9AB4])) +#define MCF_FEC1_RMON_R_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9AB8])) +#define MCF_FEC1_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x9ABC])) +#define MCF_FEC1_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9AC0])) +#define MCF_FEC1_RMON_R_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9AC4])) +#define MCF_FEC1_IEEE_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9AC8])) +#define MCF_FEC1_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x9ACC])) +#define MCF_FEC1_IEEE_R_CRC (*(volatile uint32_t*)(&_MBAR[0x9AD0])) +#define MCF_FEC1_IEEE_R_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9AD4])) +#define MCF_FEC1_IEEE_R_MACERR (*(volatile uint32_t*)(&_MBAR[0x9AD8])) +#define MCF_FEC1_IEEE_R_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9ADC])) +#define MCF_FEC1_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9AE0])) + +#define MCF_FEC_EIR(x) (*(volatile uint32_t*)(&_MBAR[0x9004 + ((x)*0x800)])) +#define MCF_FEC_EIMR(x) (*(volatile uint32_t*)(&_MBAR[0x9008 + ((x)*0x800)])) +#define MCF_FEC_ECR(x) (*(volatile uint32_t*)(&_MBAR[0x9024 + ((x)*0x800)])) +#define MCF_FEC_MMFR(x) (*(volatile uint32_t*)(&_MBAR[0x9040 + ((x)*0x800)])) +#define MCF_FEC_MSCR(x) (*(volatile uint32_t*)(&_MBAR[0x9044 + ((x)*0x800)])) +#define MCF_FEC_MIBC(x) (*(volatile uint32_t*)(&_MBAR[0x9064 + ((x)*0x800)])) +#define MCF_FEC_RCR(x) (*(volatile uint32_t*)(&_MBAR[0x9084 + ((x)*0x800)])) +#define MCF_FEC_RHR(x) (*(volatile uint32_t*)(&_MBAR[0x9088 + ((x)*0x800)])) +#define MCF_FEC_TCR(x) (*(volatile uint32_t*)(&_MBAR[0x90C4 + ((x)*0x800)])) +#define MCF_FEC_PALR(x) (*(volatile uint32_t*)(&_MBAR[0x90E4 + ((x)*0x800)])) +#define MCF_FEC_PAHR(x) (*(volatile uint32_t*)(&_MBAR[0x90E8 + ((x)*0x800)])) +#define MCF_FEC_OPD(x) (*(volatile uint32_t*)(&_MBAR[0x90EC + ((x)*0x800)])) +#define MCF_FEC_IAUR(x) (*(volatile uint32_t*)(&_MBAR[0x9118 + ((x)*0x800)])) +#define MCF_FEC_IALR(x) (*(volatile uint32_t*)(&_MBAR[0x911C + ((x)*0x800)])) +#define MCF_FEC_GAUR(x) (*(volatile uint32_t*)(&_MBAR[0x9120 + ((x)*0x800)])) +#define MCF_FEC_GALR(x) (*(volatile uint32_t*)(&_MBAR[0x9124 + ((x)*0x800)])) +#define MCF_FEC_FECTFWR(x) (*(volatile uint32_t*)(&_MBAR[0x9144 + ((x)*0x800)])) +#define MCF_FEC_FECRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x9184 + ((x)*0x800)])) +#define MCF_FEC_FECRFSR(x) (*(volatile uint32_t*)(&_MBAR[0x9188 + ((x)*0x800)])) +#define MCF_FEC_FECRFCR(x) (*(volatile uint32_t*)(&_MBAR[0x918C + ((x)*0x800)])) +#define MCF_FEC_FECRLRFP(x) (*(volatile uint32_t*)(&_MBAR[0x9190 + ((x)*0x800)])) +#define MCF_FEC_FECRLWFP(x) (*(volatile uint32_t*)(&_MBAR[0x9194 + ((x)*0x800)])) +#define MCF_FEC_FECRFAR(x) (*(volatile uint32_t*)(&_MBAR[0x9198 + ((x)*0x800)])) +#define MCF_FEC_FECRFRP(x) (*(volatile uint32_t*)(&_MBAR[0x919C + ((x)*0x800)])) +#define MCF_FEC_FECRFWP(x) (*(volatile uint32_t*)(&_MBAR[0x91A0 + ((x)*0x800)])) +#define MCF_FEC_FECTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x91A4 + ((x)*0x800)])) +#define MCF_FEC_FECTFSR(x) (*(volatile uint32_t*)(&_MBAR[0x91A8 + ((x)*0x800)])) +#define MCF_FEC_FECTFCR(x) (*(volatile uint32_t*)(&_MBAR[0x91AC + ((x)*0x800)])) +#define MCF_FEC_FECTLRFP(x) (*(volatile uint32_t*)(&_MBAR[0x91B0 + ((x)*0x800)])) +#define MCF_FEC_FECTLWFP(x) (*(volatile uint32_t*)(&_MBAR[0x91B4 + ((x)*0x800)])) +#define MCF_FEC_FECTFAR(x) (*(volatile uint32_t*)(&_MBAR[0x91B8 + ((x)*0x800)])) +#define MCF_FEC_FECTFRP(x) (*(volatile uint32_t*)(&_MBAR[0x91BC + ((x)*0x800)])) +#define MCF_FEC_FECTFWP(x) (*(volatile uint32_t*)(&_MBAR[0x91C0 + ((x)*0x800)])) +#define MCF_FEC_FECFRST(x) (*(volatile uint32_t*)(&_MBAR[0x91C4 + ((x)*0x800)])) +#define MCF_FEC_FECCTCWR(x) (*(volatile uint32_t*)(&_MBAR[0x91C8 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9200 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_PACKETS(x) (*(volatile uint32_t*)(&_MBAR[0x9204 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_BC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x9208 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_MC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x920C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x9210 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9214 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_OVERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9218 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_FRAG(x) (*(volatile uint32_t*)(&_MBAR[0x921C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_JAB(x) (*(volatile uint32_t*)(&_MBAR[0x9220 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_COL(x) (*(volatile uint32_t*)(&_MBAR[0x9224 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P64(x) (*(volatile uint32_t*)(&_MBAR[0x9228 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P65TO127(x) (*(volatile uint32_t*)(&_MBAR[0x922C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P128TO255(x) (*(volatile uint32_t*)(&_MBAR[0x9230 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P256TO511(x) (*(volatile uint32_t*)(&_MBAR[0x9234 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P512TO1023(x) (*(volatile uint32_t*)(&_MBAR[0x9238 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P1024TO2047(x) (*(volatile uint32_t*)(&_MBAR[0x923C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P_GTE2048(x) (*(volatile uint32_t*)(&_MBAR[0x9240 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_OCTETS(x) (*(volatile uint32_t*)(&_MBAR[0x9244 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9248 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(volatile uint32_t*)(&_MBAR[0x924C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_1COL(x) (*(volatile uint32_t*)(&_MBAR[0x9250 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_MCOL(x) (*(volatile uint32_t*)(&_MBAR[0x9254 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_DEF(x) (*(volatile uint32_t*)(&_MBAR[0x9258 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_LCOL(x) (*(volatile uint32_t*)(&_MBAR[0x925C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_EXCOL(x) (*(volatile uint32_t*)(&_MBAR[0x9260 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_MACERR(x) (*(volatile uint32_t*)(&_MBAR[0x9264 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_CSERR(x) (*(volatile uint32_t*)(&_MBAR[0x9268 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_SQE(x) (*(volatile uint32_t*)(&_MBAR[0x926C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_FDXFC(x) (*(volatile uint32_t*)(&_MBAR[0x9270 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(volatile uint32_t*)(&_MBAR[0x9274 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9280 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_PACKETS(x) (*(volatile uint32_t*)(&_MBAR[0x9284 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_BC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x9288 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_MC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x928C + ((x)*0x800)])) +#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x9290 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9294 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_OVERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9298 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_FRAG(x) (*(volatile uint32_t*)(&_MBAR[0x929C + ((x)*0x800)])) +#define MCF_FEC_RMON_R_JAB(x) (*(volatile uint32_t*)(&_MBAR[0x92A0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_RESVD_0(x) (*(volatile uint32_t*)(&_MBAR[0x92A4 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P64(x) (*(volatile uint32_t*)(&_MBAR[0x92A8 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P65TO127(x) (*(volatile uint32_t*)(&_MBAR[0x92AC + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P128TO255(x) (*(volatile uint32_t*)(&_MBAR[0x92B0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P256TO511(x) (*(volatile uint32_t*)(&_MBAR[0x92B4 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P512TO1023(x) (*(volatile uint32_t*)(&_MBAR[0x92B8 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P1024TO2047(x) (*(volatile uint32_t*)(&_MBAR[0x92BC + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P_GTE2048(x) (*(volatile uint32_t*)(&_MBAR[0x92C0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_OCTETS(x) (*(volatile uint32_t*)(&_MBAR[0x92C4 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x92C8 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(volatile uint32_t*)(&_MBAR[0x92CC + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_CRC(x) (*(volatile uint32_t*)(&_MBAR[0x92D0 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x92D4 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_MACERR(x) (*(volatile uint32_t*)(&_MBAR[0x92D8 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_FDXFC(x) (*(volatile uint32_t*)(&_MBAR[0x92DC + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(volatile uint32_t*)(&_MBAR[0x92E0 + ((x)*0x800)])) + + +/* Bit definitions and macros for MCF_FEC_EIR */ +#define MCF_FEC_EIR_RFERR (0x20000) +#define MCF_FEC_EIR_XFERR (0x40000) +#define MCF_FEC_EIR_XFUN (0x80000) +#define MCF_FEC_EIR_RL (0x100000) +#define MCF_FEC_EIR_LC (0x200000) +#define MCF_FEC_EIR_MII (0x800000) +#define MCF_FEC_EIR_TXF (0x8000000) +#define MCF_FEC_EIR_GRA (0x10000000) +#define MCF_FEC_EIR_BABT (0x20000000) +#define MCF_FEC_EIR_BABR (0x40000000) +#define MCF_FEC_EIR_HBERR (0x80000000) +#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF_FEC_EIMR */ +#define MCF_FEC_EIMR_RFERR (0x20000) +#define MCF_FEC_EIMR_XFERR (0x40000) +#define MCF_FEC_EIMR_XFUN (0x80000) +#define MCF_FEC_EIMR_RL (0x100000) +#define MCF_FEC_EIMR_LC (0x200000) +#define MCF_FEC_EIMR_MII (0x800000) +#define MCF_FEC_EIMR_TXF (0x8000000) +#define MCF_FEC_EIMR_GRA (0x10000000) +#define MCF_FEC_EIMR_BABT (0x20000000) +#define MCF_FEC_EIMR_BABR (0x40000000) +#define MCF_FEC_EIMR_HBERR (0x80000000) +#define MCF_FEC_EIMR_MASK_ALL (0) +#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF_FEC_ECR */ +#define MCF_FEC_ECR_RESET (0x1) +#define MCF_FEC_ECR_ETHER_EN (0x2) + +/* Bit definitions and macros for MCF_FEC_MMFR */ +#define MCF_FEC_MMFR_DATA(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_MMFR_TA(x) (((x)&0x3)<<0x10) +#define MCF_FEC_MMFR_TA_10 (0x20000) +#define MCF_FEC_MMFR_RA(x) (((x)&0x1F)<<0x12) +#define MCF_FEC_MMFR_PA(x) (((x)&0x1F)<<0x17) +#define MCF_FEC_MMFR_OP(x) (((x)&0x3)<<0x1C) +#define MCF_FEC_MMFR_OP_READ (0x20000000) +#define MCF_FEC_MMFR_OP_WRITE (0x10000000) +#define MCF_FEC_MMFR_ST(x) (((x)&0x3)<<0x1E) +#define MCF_FEC_MMFR_ST_01 (0x40000000) + +/* Bit definitions and macros for MCF_FEC_MSCR */ +#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1) +#define MCF_FEC_MSCR_DIS_PREAMBLE (0x80) +#define MCF_FEC_MSCR_MII_SPEED_133 (0x1B<<0x1) +#define MCF_FEC_MSCR_MII_SPEED_120 (0x18<<0x1) +#define MCF_FEC_MSCR_MII_SPEED_66 (0xE<<0x1) +#define MCF_FEC_MSCR_MII_SPEED_60 (0xC<<0x1) + +/* Bit definitions and macros for MCF_FEC_MIBC */ +#define MCF_FEC_MIBC_MIB_IDLE (0x40000000) +#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000) + +/* Bit definitions and macros for MCF_FEC_RCR */ +#define MCF_FEC_RCR_LOOP (0x1) +#define MCF_FEC_RCR_DRT (0x2) +#define MCF_FEC_RCR_MII_MODE (0x4) +#define MCF_FEC_RCR_PROM (0x8) +#define MCF_FEC_RCR_BC_REJ (0x10) +#define MCF_FEC_RCR_FCE (0x20) +#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<0x10) + +/* Bit definitions and macros for MCF_FEC_RHR */ +#define MCF_FEC_RHR_HASH(x) (((x)&0x3F)<<0x18) +#define MCF_FEC_RHR_MULTCAST (0x40000000) +#define MCF_FEC_RHR_FCE (0x80000000) + +/* Bit definitions and macros for MCF_FEC_TCR */ +#define MCF_FEC_TCR_GTS (0x1) +#define MCF_FEC_TCR_HBC (0x2) +#define MCF_FEC_TCR_FDEN (0x4) +#define MCF_FEC_TCR_TFC_PAUSE (0x8) +#define MCF_FEC_TCR_RFC_PAUSE (0x10) + +/* Bit definitions and macros for MCF_FEC_PALR */ +#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_PAHR */ +#define MCF_FEC_PAHR_TYPE(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_PAHR_PADDR2(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_FEC_OPD */ +#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_OPD_OPCODE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_FEC_IAUR */ +#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IALR */ +#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_GAUR */ +#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_GALR */ +#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFWR */ +#define MCF_FEC_FECTFWR_X_WMRK(x) (((x)&0xF)<<0) +#define MCF_FEC_FECTFWR_X_WMRK_64 (0) +#define MCF_FEC_FECTFWR_X_WMRK_128 (0x1) +#define MCF_FEC_FECTFWR_X_WMRK_192 (0x2) +#define MCF_FEC_FECTFWR_X_WMRK_256 (0x3) +#define MCF_FEC_FECTFWR_X_WMRK_320 (0x4) +#define MCF_FEC_FECTFWR_X_WMRK_384 (0x5) +#define MCF_FEC_FECTFWR_X_WMRK_448 (0x6) +#define MCF_FEC_FECTFWR_X_WMRK_512 (0x7) +#define MCF_FEC_FECTFWR_X_WMRK_576 (0x8) +#define MCF_FEC_FECTFWR_X_WMRK_640 (0x9) +#define MCF_FEC_FECTFWR_X_WMRK_704 (0xA) +#define MCF_FEC_FECTFWR_X_WMRK_768 (0xB) +#define MCF_FEC_FECTFWR_X_WMRK_832 (0xC) +#define MCF_FEC_FECTFWR_X_WMRK_896 (0xD) +#define MCF_FEC_FECTFWR_X_WMRK_960 (0xE) +#define MCF_FEC_FECTFWR_X_WMRK_1024 (0xF) + +/* Bit definitions and macros for MCF_FEC_FECRFDR */ +#define MCF_FEC_FECRFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFSR */ +#define MCF_FEC_FECRFSR_EMT (0x10000) +#define MCF_FEC_FECRFSR_ALARM (0x20000) +#define MCF_FEC_FECRFSR_FU (0x40000) +#define MCF_FEC_FECRFSR_FRMRDY (0x80000) +#define MCF_FEC_FECRFSR_OF (0x100000) +#define MCF_FEC_FECRFSR_UF (0x200000) +#define MCF_FEC_FECRFSR_RXW (0x400000) +#define MCF_FEC_FECRFSR_FAE (0x800000) +#define MCF_FEC_FECRFSR_FRM(x) (((x)&0xF)<<0x18) +#define MCF_FEC_FECRFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_FEC_FECRFCR */ +#define MCF_FEC_FECRFCR_COUNTER(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_FECRFCR_OF_MSK (0x80000) +#define MCF_FEC_FECRFCR_UF_MSK (0x100000) +#define MCF_FEC_FECRFCR_RXW_MSK (0x200000) +#define MCF_FEC_FECRFCR_FAE_MSK (0x400000) +#define MCF_FEC_FECRFCR_IP_MSK (0x800000) +#define MCF_FEC_FECRFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_FEC_FECRFCR_FRMEN (0x8000000) +#define MCF_FEC_FECRFCR_TIMER (0x10000000) + +/* Bit definitions and macros for MCF_FEC_FECRLRFP */ +#define MCF_FEC_FECRLRFP_LRFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRLWFP */ +#define MCF_FEC_FECRLWFP_LWFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFAR */ +#define MCF_FEC_FECRFAR_ALARM(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFRP */ +#define MCF_FEC_FECRFRP_READ(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFWP */ +#define MCF_FEC_FECRFWP_WRITE(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFDR */ +#define MCF_FEC_FECTFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFSR */ +#define MCF_FEC_FECTFSR_EMT (0x10000) +#define MCF_FEC_FECTFSR_ALARM (0x20000) +#define MCF_FEC_FECTFSR_FU (0x40000) +#define MCF_FEC_FECTFSR_FRMRDY (0x80000) +#define MCF_FEC_FECTFSR_OF (0x100000) +#define MCF_FEC_FECTFSR_UF (0x200000) +#define MCF_FEC_FECTFSR_FAE (0x800000) +#define MCF_FEC_FECTFSR_FRM(x) (((x)&0xF)<<0x18) +#define MCF_FEC_FECTFSR_TXW (0x40000000) +#define MCF_FEC_FECTFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_FEC_FECTFCR */ +#define MCF_FEC_FECTFCR_RESERVED (0x200000) +#define MCF_FEC_FECTFCR_COUNTER(x) (((x)&0xFFFF)<<0|0x200000) +#define MCF_FEC_FECTFCR_TXW_MASK (0x240000) +#define MCF_FEC_FECTFCR_OF_MSK (0x280000) +#define MCF_FEC_FECTFCR_UF_MSK (0x300000) +#define MCF_FEC_FECTFCR_FAE_MSK (0x600000) +#define MCF_FEC_FECTFCR_IP_MSK (0xA00000) +#define MCF_FEC_FECTFCR_GR(x) (((x)&0x7)<<0x18|0x200000) +#define MCF_FEC_FECTFCR_FRMEN (0x8200000) +#define MCF_FEC_FECTFCR_TIMER (0x10200000) +#define MCF_FEC_FECTFCR_WFR (0x20200000) +#define MCF_FEC_FECTFCR_WCTL (0x40200000) + +/* Bit definitions and macros for MCF_FEC_FECTLRFP */ +#define MCF_FEC_FECTLRFP_LRFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTLWFP */ +#define MCF_FEC_FECTLWFP_LWFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFAR */ +#define MCF_FEC_FECTFAR_ALARM(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFRP */ +#define MCF_FEC_FECTFRP_READ(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFWP */ +#define MCF_FEC_FECTFWP_WRITE(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECFRST */ +#define MCF_FEC_FECFRST_RST_CTL (0x1000000) +#define MCF_FEC_FECFRST_SW_RST (0x2000000) + +/* Bit definitions and macros for MCF_FEC_FECCTCWR */ +#define MCF_FEC_FECCTCWR_TFCW (0x1000000) +#define MCF_FEC_FECCTCWR_CRC (0x2000000) + +/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */ +#define MCF_FEC_RMON_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */ +#define MCF_FEC_RMON_T_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */ +#define MCF_FEC_RMON_T_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */ +#define MCF_FEC_RMON_T_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */ +#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */ +#define MCF_FEC_RMON_T_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */ +#define MCF_FEC_RMON_T_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */ +#define MCF_FEC_RMON_T_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */ +#define MCF_FEC_RMON_T_JAB_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_COL */ +#define MCF_FEC_RMON_T_COL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */ +#define MCF_FEC_RMON_T_P64_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */ +#define MCF_FEC_RMON_T_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */ +#define MCF_FEC_RMON_T_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */ +#define MCF_FEC_RMON_T_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */ +#define MCF_FEC_RMON_T_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */ +#define MCF_FEC_RMON_T_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */ +#define MCF_FEC_RMON_T_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */ +#define MCF_FEC_RMON_T_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */ +#define MCF_FEC_IEEE_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */ +#define MCF_FEC_IEEE_T_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */ +#define MCF_FEC_IEEE_T_1COL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */ +#define MCF_FEC_IEEE_T_MCOL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */ +#define MCF_FEC_IEEE_T_DEF_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */ +#define MCF_FEC_IEEE_T_LCOL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */ +#define MCF_FEC_IEEE_T_EXCOL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */ +#define MCF_FEC_IEEE_T_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */ +#define MCF_FEC_IEEE_T_CSERR_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */ +#define MCF_FEC_IEEE_T_SQE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */ +#define MCF_FEC_IEEE_T_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */ +#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_DROP */ +#define MCF_FEC_RMON_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */ +#define MCF_FEC_RMON_R_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */ +#define MCF_FEC_RMON_R_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */ +#define MCF_FEC_RMON_R_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */ +#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */ +#define MCF_FEC_RMON_R_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */ +#define MCF_FEC_RMON_R_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */ +#define MCF_FEC_RMON_R_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */ +#define MCF_FEC_RMON_R_JAB_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */ +#define MCF_FEC_RMON_R_RESVD_0_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */ +#define MCF_FEC_RMON_R_P64_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */ +#define MCF_FEC_RMON_R_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */ +#define MCF_FEC_RMON_R_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */ +#define MCF_FEC_RMON_R_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */ +#define MCF_FEC_RMON_R_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */ +#define MCF_FEC_RMON_R_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */ +#define MCF_FEC_RMON_R_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */ +#define MCF_FEC_RMON_R_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */ +#define MCF_FEC_IEEE_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */ +#define MCF_FEC_IEEE_R_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */ +#define MCF_FEC_IEEE_R_CRC_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */ +#define MCF_FEC_IEEE_R_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */ +#define MCF_FEC_IEEE_R_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */ +#define MCF_FEC_IEEE_R_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */ +#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + + +#endif /* __MCF5475_FEC_H__ */ diff --git a/tos/jtagwait/include/MCF5475_GPIO.h b/tos/jtagwait/include/MCF5475_GPIO.h new file mode 100644 index 0000000..5dd2583 --- /dev/null +++ b/tos/jtagwait/include/MCF5475_GPIO.h @@ -0,0 +1,543 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_GPIO_H__ +#define __MCF5475_GPIO_H__ + + +/********************************************************************* +* +* General Purpose I/O (GPIO) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPIO_PODR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA00])) +#define MCF_GPIO_PDDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA10])) +#define MCF_GPIO_PPDSDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA20])) +#define MCF_GPIO_PCLRR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA30])) + +#define MCF_GPIO_PODR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA01])) +#define MCF_GPIO_PDDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA11])) +#define MCF_GPIO_PPDSDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA21])) +#define MCF_GPIO_PCLRR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA31])) + +#define MCF_GPIO_PODR_DMA (*(volatile uint8_t *)(&_MBAR[0xA02])) +#define MCF_GPIO_PDDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA12])) +#define MCF_GPIO_PPDSDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA22])) +#define MCF_GPIO_PCLRR_DMA (*(volatile uint8_t *)(&_MBAR[0xA32])) + +#define MCF_GPIO_PODR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA04])) +#define MCF_GPIO_PDDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA14])) +#define MCF_GPIO_PPDSDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA24])) +#define MCF_GPIO_PCLRR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA34])) + +#define MCF_GPIO_PODR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA05])) +#define MCF_GPIO_PDDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA15])) +#define MCF_GPIO_PPDSDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA25])) +#define MCF_GPIO_PCLRR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA35])) + +#define MCF_GPIO_PODR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA06])) +#define MCF_GPIO_PDDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA16])) +#define MCF_GPIO_PPDSDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA26])) +#define MCF_GPIO_PCLRR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA36])) + +#define MCF_GPIO_PODR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA07])) +#define MCF_GPIO_PDDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA17])) +#define MCF_GPIO_PPDSDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA27])) +#define MCF_GPIO_PCLRR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA37])) + +#define MCF_GPIO_PODR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA08])) +#define MCF_GPIO_PDDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA18])) +#define MCF_GPIO_PPDSDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA28])) +#define MCF_GPIO_PCLRR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA38])) + +#define MCF_GPIO_PODR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA09])) +#define MCF_GPIO_PDDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA19])) +#define MCF_GPIO_PPDSDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA29])) +#define MCF_GPIO_PCLRR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA39])) + +#define MCF_GPIO_PODR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA0A])) +#define MCF_GPIO_PDDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA1A])) +#define MCF_GPIO_PPDSDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA2A])) +#define MCF_GPIO_PCLRR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA3A])) + +#define MCF_GPIO2_PODR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA0C])) +#define MCF_GPIO2_PDDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA1C])) +#define MCF_GPIO2_PPDSDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA2C])) +#define MCF_GPIO2_PCLRR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA3C])) + +#define MCF_GPIO0_PODR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA0D])) +#define MCF_GPIO0_PDDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA1D])) +#define MCF_GPIO0_PPDSDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA2D])) +#define MCF_GPIO0_PCLRR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA3D])) + +#define MCF_GPIO_PODR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA0E])) +#define MCF_GPIO_PDDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA1E])) +#define MCF_GPIO_PPDSDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA2E])) +#define MCF_GPIO_PCLRR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA3E])) + + + +/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */ +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x1) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x2) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x4) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x8) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */ +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x1) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x2) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x4) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x8) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */ +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x1) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x2) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x4) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x8) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */ +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x1) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x2) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x4) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x8) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */ +#define MCF_GPIO_PODR_FBCS_PODR_FBCS1 (0x2) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS2 (0x4) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS3 (0x8) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS4 (0x10) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */ +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x2) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x4) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x8) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */ +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x2) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x4) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x8) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */ +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x2) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x4) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x8) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PODR_DMA */ +#define MCF_GPIO_PODR_DMA_PODR_DMA0 (0x1) +#define MCF_GPIO_PODR_DMA_PODR_DMA1 (0x2) +#define MCF_GPIO_PODR_DMA_PODR_DMA2 (0x4) +#define MCF_GPIO_PODR_DMA_PODR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */ +#define MCF_GPIO_PDDR_DMA_PDDR_DMA0 (0x1) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA1 (0x2) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA2 (0x4) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */ +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x1) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x2) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x4) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */ +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x1) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x2) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x4) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */ +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x1) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x2) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x4) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x8) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */ +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x1) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x2) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x4) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x8) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */ +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x1) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x2) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x4) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x8) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */ +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x1) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x2) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x4) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x8) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */ +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x1) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x2) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x4) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x8) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */ +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x1) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x2) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x4) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x8) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */ +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x1) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x2) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x4) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x8) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */ +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x1) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1 (0x2) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x4) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x8) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4 (0x10) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5 (0x20) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6 (0x40) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */ +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x1) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x2) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x4) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x8) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */ +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x1) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x2) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x4) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x8) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */ +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x1) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x2) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x4) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x8) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */ +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x1) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x2) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x4) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3 (0x8) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4 (0x10) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */ +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x1) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x2) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x4) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x8) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */ +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x1) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x2) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x4) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x8) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */ +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x1) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x2) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x4) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x8) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */ +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x1) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x2) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x4) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x8) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4 (0x10) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x1) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x2) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x4) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x1) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x2) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x4) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x1) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x2) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x4) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */ +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x1) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x2) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x4) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x8) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */ +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x1) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x2) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x4) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x8) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */ +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x1) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x2) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x4) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x8) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */ +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0 (0x1) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1 (0x2) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2 (0x4) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x8) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */ +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x1) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x2) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x4) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x8) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */ +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x1) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x2) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x4) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x8) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */ +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x1) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x2) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x4) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x8) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */ +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x1) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x2) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x4) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3 (0x8) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */ +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */ +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */ +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */ +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */ +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */ +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */ +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */ +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */ +#define MCF_GPIO_PODR_DSPI_PODR_DSPI0 (0x1) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI1 (0x2) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI2 (0x4) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI3 (0x8) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI4 (0x10) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI5 (0x20) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */ +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x1) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x2) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x4) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x8) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */ +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x1) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x2) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x4) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x8) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4 (0x10) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */ +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x1) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x2) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x4) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x8) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40) + + +#endif /* __MCF5475_GPIO_H__ */ diff --git a/tos/jtagwait/include/MCF5475_GPT.h b/tos/jtagwait/include/MCF5475_GPT.h new file mode 100644 index 0000000..f9fbc98 --- /dev/null +++ b/tos/jtagwait/include/MCF5475_GPT.h @@ -0,0 +1,100 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_GPT_H__ +#define __MCF5475_GPT_H__ + + +/********************************************************************* +* +* General Purpose Timers (GPT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPT0_GMS (*(volatile uint32_t*)(&_MBAR[0x800])) +#define MCF_GPT0_GCIR (*(volatile uint32_t*)(&_MBAR[0x804])) +#define MCF_GPT0_GPWM (*(volatile uint32_t*)(&_MBAR[0x808])) +#define MCF_GPT0_GSR (*(volatile uint32_t*)(&_MBAR[0x80C])) + +#define MCF_GPT1_GMS (*(volatile uint32_t*)(&_MBAR[0x810])) +#define MCF_GPT1_GCIR (*(volatile uint32_t*)(&_MBAR[0x814])) +#define MCF_GPT1_GPWM (*(volatile uint32_t*)(&_MBAR[0x818])) +#define MCF_GPT1_GSR (*(volatile uint32_t*)(&_MBAR[0x81C])) + +#define MCF_GPT2_GMS (*(volatile uint32_t*)(&_MBAR[0x820])) +#define MCF_GPT2_GCIR (*(volatile uint32_t*)(&_MBAR[0x824])) +#define MCF_GPT2_GPWM (*(volatile uint32_t*)(&_MBAR[0x828])) +#define MCF_GPT2_GSR (*(volatile uint32_t*)(&_MBAR[0x82C])) + +#define MCF_GPT3_GMS (*(volatile uint32_t*)(&_MBAR[0x830])) +#define MCF_GPT3_GCIR (*(volatile uint32_t*)(&_MBAR[0x834])) +#define MCF_GPT3_GPWM (*(volatile uint32_t*)(&_MBAR[0x838])) +#define MCF_GPT3_GSR (*(volatile uint32_t*)(&_MBAR[0x83C])) + +#define MCF_GPT_GMS(x) (*(volatile uint32_t*)(&_MBAR[0x800 + ((x)*0x10)])) +#define MCF_GPT_GCIR(x) (*(volatile uint32_t*)(&_MBAR[0x804 + ((x)*0x10)])) +#define MCF_GPT_GPWM(x) (*(volatile uint32_t*)(&_MBAR[0x808 + ((x)*0x10)])) +#define MCF_GPT_GSR(x) (*(volatile uint32_t*)(&_MBAR[0x80C + ((x)*0x10)])) + + +/* Bit definitions and macros for MCF_GPT_GMS */ +#define MCF_GPT_GMS_TMS(x) (((x)&0x7)<<0) +#define MCF_GPT_GMS_TMS_DISABLE (0) +#define MCF_GPT_GMS_TMS_INCAPT (0x1) +#define MCF_GPT_GMS_TMS_OUTCAPT (0x2) +#define MCF_GPT_GMS_TMS_PWM (0x3) +#define MCF_GPT_GMS_TMS_GPIO (0x4) +#define MCF_GPT_GMS_GPIO(x) (((x)&0x3)<<0x4) +#define MCF_GPT_GMS_GPIO_INPUT (0) +#define MCF_GPT_GMS_GPIO_OUTLO (0x20) +#define MCF_GPT_GMS_GPIO_OUTHI (0x30) +#define MCF_GPT_GMS_IEN (0x100) +#define MCF_GPT_GMS_OD (0x200) +#define MCF_GPT_GMS_SC (0x400) +#define MCF_GPT_GMS_CE (0x1000) +#define MCF_GPT_GMS_WDEN (0x8000) +#define MCF_GPT_GMS_ICT(x) (((x)&0x3)<<0x10) +#define MCF_GPT_GMS_ICT_ANY (0) +#define MCF_GPT_GMS_ICT_RISE (0x10000) +#define MCF_GPT_GMS_ICT_FALL (0x20000) +#define MCF_GPT_GMS_ICT_PULSE (0x30000) +#define MCF_GPT_GMS_OCT(x) (((x)&0x3)<<0x14) +#define MCF_GPT_GMS_OCT_FRCLOW (0) +#define MCF_GPT_GMS_OCT_PULSEHI (0x100000) +#define MCF_GPT_GMS_OCT_PULSELO (0x200000) +#define MCF_GPT_GMS_OCT_TOGGLE (0x300000) +#define MCF_GPT_GMS_OCPW(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_GPT_GCIR */ +#define MCF_GPT_GCIR_CNT(x) (((x)&0xFFFF)<<0) +#define MCF_GPT_GCIR_PRE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_GPT_GPWM */ +#define MCF_GPT_GPWM_LOAD (0x1) +#define MCF_GPT_GPWM_PWMOP (0x100) +#define MCF_GPT_GPWM_WIDTH(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_GPT_GSR */ +#define MCF_GPT_GSR_CAPT (0x1) +#define MCF_GPT_GSR_COMP (0x2) +#define MCF_GPT_GSR_PWMP (0x4) +#define MCF_GPT_GSR_TEXP (0x8) +#define MCF_GPT_GSR_PIN (0x100) +#define MCF_GPT_GSR_OVF(x) (((x)&0x7)<<0xC) +#define MCF_GPT_GSR_CAPTURE(x) (((x)&0xFFFF)<<0x10) + + +#endif /* __MCF5475_GPT_H__ */ diff --git a/tos/jtagwait/include/MCF5475_I2C.h b/tos/jtagwait/include/MCF5475_I2C.h new file mode 100644 index 0000000..1e8a85b --- /dev/null +++ b/tos/jtagwait/include/MCF5475_I2C.h @@ -0,0 +1,69 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_I2C_H__ +#define __MCF5475_I2C_H__ + + +/********************************************************************* +* +* I2C Module (I2C) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_I2C_I2ADR (*(volatile uint8_t *)(&_MBAR[0x8F00])) +#define MCF_I2C_I2FDR (*(volatile uint8_t *)(&_MBAR[0x8F04])) +#define MCF_I2C_I2CR (*(volatile uint8_t *)(&_MBAR[0x8F08])) +#define MCF_I2C_I2SR (*(volatile uint8_t *)(&_MBAR[0x8F0C])) +#define MCF_I2C_I2DR (*(volatile uint8_t *)(&_MBAR[0x8F10])) +#define MCF_I2C_I2ICR (*(volatile uint8_t *)(&_MBAR[0x8F20])) + + + +/* Bit definitions and macros for MCF_I2C_I2ADR */ +#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1) + +/* Bit definitions and macros for MCF_I2C_I2FDR */ +#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) + +/* Bit definitions and macros for MCF_I2C_I2CR */ +#define MCF_I2C_I2CR_RSTA (0x4) +#define MCF_I2C_I2CR_TXAK (0x8) +#define MCF_I2C_I2CR_MTX (0x10) +#define MCF_I2C_I2CR_MSTA (0x20) +#define MCF_I2C_I2CR_IIEN (0x40) +#define MCF_I2C_I2CR_IEN (0x80) + +/* Bit definitions and macros for MCF_I2C_I2SR */ +#define MCF_I2C_I2SR_RXAK (0x1) +#define MCF_I2C_I2SR_IIF (0x2) +#define MCF_I2C_I2SR_SRW (0x4) +#define MCF_I2C_I2SR_IAL (0x10) +#define MCF_I2C_I2SR_IBB (0x20) +#define MCF_I2C_I2SR_IAAS (0x40) +#define MCF_I2C_I2SR_ICF (0x80) + +/* Bit definitions and macros for MCF_I2C_I2DR */ +#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_I2C_I2ICR */ +#define MCF_I2C_I2ICR_IE (0x1) +#define MCF_I2C_I2ICR_RE (0x2) +#define MCF_I2C_I2ICR_TE (0x4) +#define MCF_I2C_I2ICR_BNBE (0x8) + + +#endif /* __MCF5475_I2C_H__ */ diff --git a/tos/jtagwait/include/MCF5475_INTC.h b/tos/jtagwait/include/MCF5475_INTC.h new file mode 100644 index 0000000..61265ed --- /dev/null +++ b/tos/jtagwait/include/MCF5475_INTC.h @@ -0,0 +1,331 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_INTC_H__ +#define __MCF5475_INTC_H__ + + +/********************************************************************* +* +* Interrupt Controller (INTC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_INTC_IPRH (*(volatile uint32_t*)(&_MBAR[0x700])) +#define MCF_INTC_IPRL (*(volatile uint32_t*)(&_MBAR[0x704])) +#define MCF_INTC_IMRH (*(volatile uint32_t*)(&_MBAR[0x708])) +#define MCF_INTC_IMRL (*(volatile uint32_t*)(&_MBAR[0x70C])) +#define MCF_INTC_INTFRCH (*(volatile uint32_t*)(&_MBAR[0x710])) +#define MCF_INTC_INTFRCL (*(volatile uint32_t*)(&_MBAR[0x714])) +#define MCF_INTC_IRLR (*(volatile uint8_t *)(&_MBAR[0x718])) +#define MCF_INTC_IACKLPR (*(volatile uint8_t *)(&_MBAR[0x719])) +#define MCF_INTC_ICR01 (*(volatile uint8_t *)(&_MBAR[0x741])) +#define MCF_INTC_ICR02 (*(volatile uint8_t *)(&_MBAR[0x742])) +#define MCF_INTC_ICR03 (*(volatile uint8_t *)(&_MBAR[0x743])) +#define MCF_INTC_ICR04 (*(volatile uint8_t *)(&_MBAR[0x744])) +#define MCF_INTC_ICR05 (*(volatile uint8_t *)(&_MBAR[0x745])) +#define MCF_INTC_ICR06 (*(volatile uint8_t *)(&_MBAR[0x746])) +#define MCF_INTC_ICR07 (*(volatile uint8_t *)(&_MBAR[0x747])) +#define MCF_INTC_ICR08 (*(volatile uint8_t *)(&_MBAR[0x748])) +#define MCF_INTC_ICR09 (*(volatile uint8_t *)(&_MBAR[0x749])) +#define MCF_INTC_ICR10 (*(volatile uint8_t *)(&_MBAR[0x74A])) +#define MCF_INTC_ICR11 (*(volatile uint8_t *)(&_MBAR[0x74B])) +#define MCF_INTC_ICR12 (*(volatile uint8_t *)(&_MBAR[0x74C])) +#define MCF_INTC_ICR13 (*(volatile uint8_t *)(&_MBAR[0x74D])) +#define MCF_INTC_ICR14 (*(volatile uint8_t *)(&_MBAR[0x74E])) +#define MCF_INTC_ICR15 (*(volatile uint8_t *)(&_MBAR[0x74F])) +#define MCF_INTC_ICR16 (*(volatile uint8_t *)(&_MBAR[0x750])) +#define MCF_INTC_ICR17 (*(volatile uint8_t *)(&_MBAR[0x751])) +#define MCF_INTC_ICR18 (*(volatile uint8_t *)(&_MBAR[0x752])) +#define MCF_INTC_ICR19 (*(volatile uint8_t *)(&_MBAR[0x753])) +#define MCF_INTC_ICR20 (*(volatile uint8_t *)(&_MBAR[0x754])) +#define MCF_INTC_ICR21 (*(volatile uint8_t *)(&_MBAR[0x755])) +#define MCF_INTC_ICR22 (*(volatile uint8_t *)(&_MBAR[0x756])) +#define MCF_INTC_ICR23 (*(volatile uint8_t *)(&_MBAR[0x757])) +#define MCF_INTC_ICR24 (*(volatile uint8_t *)(&_MBAR[0x758])) +#define MCF_INTC_ICR25 (*(volatile uint8_t *)(&_MBAR[0x759])) +#define MCF_INTC_ICR26 (*(volatile uint8_t *)(&_MBAR[0x75A])) +#define MCF_INTC_ICR27 (*(volatile uint8_t *)(&_MBAR[0x75B])) +#define MCF_INTC_ICR28 (*(volatile uint8_t *)(&_MBAR[0x75C])) +#define MCF_INTC_ICR29 (*(volatile uint8_t *)(&_MBAR[0x75D])) +#define MCF_INTC_ICR30 (*(volatile uint8_t *)(&_MBAR[0x75E])) +#define MCF_INTC_ICR31 (*(volatile uint8_t *)(&_MBAR[0x75F])) +#define MCF_INTC_ICR32 (*(volatile uint8_t *)(&_MBAR[0x760])) +#define MCF_INTC_ICR33 (*(volatile uint8_t *)(&_MBAR[0x761])) +#define MCF_INTC_ICR34 (*(volatile uint8_t *)(&_MBAR[0x762])) +#define MCF_INTC_ICR35 (*(volatile uint8_t *)(&_MBAR[0x763])) +#define MCF_INTC_ICR36 (*(volatile uint8_t *)(&_MBAR[0x764])) +#define MCF_INTC_ICR37 (*(volatile uint8_t *)(&_MBAR[0x765])) +#define MCF_INTC_ICR38 (*(volatile uint8_t *)(&_MBAR[0x766])) +#define MCF_INTC_ICR39 (*(volatile uint8_t *)(&_MBAR[0x767])) +#define MCF_INTC_ICR40 (*(volatile uint8_t *)(&_MBAR[0x768])) +#define MCF_INTC_ICR41 (*(volatile uint8_t *)(&_MBAR[0x769])) +#define MCF_INTC_ICR42 (*(volatile uint8_t *)(&_MBAR[0x76A])) +#define MCF_INTC_ICR43 (*(volatile uint8_t *)(&_MBAR[0x76B])) +#define MCF_INTC_ICR44 (*(volatile uint8_t *)(&_MBAR[0x76C])) +#define MCF_INTC_ICR45 (*(volatile uint8_t *)(&_MBAR[0x76D])) +#define MCF_INTC_ICR46 (*(volatile uint8_t *)(&_MBAR[0x76E])) +#define MCF_INTC_ICR47 (*(volatile uint8_t *)(&_MBAR[0x76F])) +#define MCF_INTC_ICR48 (*(volatile uint8_t *)(&_MBAR[0x770])) +#define MCF_INTC_ICR49 (*(volatile uint8_t *)(&_MBAR[0x771])) +#define MCF_INTC_ICR50 (*(volatile uint8_t *)(&_MBAR[0x772])) +#define MCF_INTC_ICR51 (*(volatile uint8_t *)(&_MBAR[0x773])) +#define MCF_INTC_ICR52 (*(volatile uint8_t *)(&_MBAR[0x774])) +#define MCF_INTC_ICR53 (*(volatile uint8_t *)(&_MBAR[0x775])) +#define MCF_INTC_ICR54 (*(volatile uint8_t *)(&_MBAR[0x776])) +#define MCF_INTC_ICR55 (*(volatile uint8_t *)(&_MBAR[0x777])) +#define MCF_INTC_ICR56 (*(volatile uint8_t *)(&_MBAR[0x778])) +#define MCF_INTC_ICR57 (*(volatile uint8_t *)(&_MBAR[0x779])) +#define MCF_INTC_ICR58 (*(volatile uint8_t *)(&_MBAR[0x77A])) +#define MCF_INTC_ICR59 (*(volatile uint8_t *)(&_MBAR[0x77B])) +#define MCF_INTC_ICR60 (*(volatile uint8_t *)(&_MBAR[0x77C])) +#define MCF_INTC_ICR61 (*(volatile uint8_t *)(&_MBAR[0x77D])) +#define MCF_INTC_ICR62 (*(volatile uint8_t *)(&_MBAR[0x77E])) +#define MCF_INTC_ICR63 (*(volatile uint8_t *)(&_MBAR[0x77F])) +#define MCF_INTC_SWIACK (*(volatile uint8_t *)(&_MBAR[0x7E0])) +#define MCF_INTC_L1IACK (*(volatile uint8_t *)(&_MBAR[0x7E4])) +#define MCF_INTC_L2IACK (*(volatile uint8_t *)(&_MBAR[0x7E8])) +#define MCF_INTC_L3IACK (*(volatile uint8_t *)(&_MBAR[0x7EC])) +#define MCF_INTC_L4IACK (*(volatile uint8_t *)(&_MBAR[0x7F0])) +#define MCF_INTC_L5IACK (*(volatile uint8_t *)(&_MBAR[0x7F4])) +#define MCF_INTC_L6IACK (*(volatile uint8_t *)(&_MBAR[0x7F8])) +#define MCF_INTC_L7IACK (*(volatile uint8_t *)(&_MBAR[0x7FC])) +#define MCF_INTC_ICR(x) (*(volatile uint8_t *)(&_MBAR[0x741 + ((x-1)*0x1)])) +#define MCF_INTC_LIACK(x) (*(volatile uint8_t *)(&_MBAR[0x7E4 + ((x-1)*0x4)])) + + + +/* Bit definitions and macros for MCF_INTC_IPRH */ +#define MCF_INTC_IPRH_INT32 (0x1) +#define MCF_INTC_IPRH_INT33 (0x2) +#define MCF_INTC_IPRH_INT34 (0x4) +#define MCF_INTC_IPRH_INT35 (0x8) +#define MCF_INTC_IPRH_INT36 (0x10) +#define MCF_INTC_IPRH_INT37 (0x20) +#define MCF_INTC_IPRH_INT38 (0x40) +#define MCF_INTC_IPRH_INT39 (0x80) +#define MCF_INTC_IPRH_INT40 (0x100) +#define MCF_INTC_IPRH_INT41 (0x200) +#define MCF_INTC_IPRH_INT42 (0x400) +#define MCF_INTC_IPRH_INT43 (0x800) +#define MCF_INTC_IPRH_INT44 (0x1000) +#define MCF_INTC_IPRH_INT45 (0x2000) +#define MCF_INTC_IPRH_INT46 (0x4000) +#define MCF_INTC_IPRH_INT47 (0x8000) +#define MCF_INTC_IPRH_INT48 (0x10000) +#define MCF_INTC_IPRH_INT49 (0x20000) +#define MCF_INTC_IPRH_INT50 (0x40000) +#define MCF_INTC_IPRH_INT51 (0x80000) +#define MCF_INTC_IPRH_INT52 (0x100000) +#define MCF_INTC_IPRH_INT53 (0x200000) +#define MCF_INTC_IPRH_INT54 (0x400000) +#define MCF_INTC_IPRH_INT55 (0x800000) +#define MCF_INTC_IPRH_INT56 (0x1000000) +#define MCF_INTC_IPRH_INT57 (0x2000000) +#define MCF_INTC_IPRH_INT58 (0x4000000) +#define MCF_INTC_IPRH_INT59 (0x8000000) +#define MCF_INTC_IPRH_INT60 (0x10000000) +#define MCF_INTC_IPRH_INT61 (0x20000000) +#define MCF_INTC_IPRH_INT62 (0x40000000) +#define MCF_INTC_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IPRL */ +#define MCF_INTC_IPRL_INT1 (0x2) +#define MCF_INTC_IPRL_INT2 (0x4) +#define MCF_INTC_IPRL_INT3 (0x8) +#define MCF_INTC_IPRL_INT4 (0x10) +#define MCF_INTC_IPRL_INT5 (0x20) +#define MCF_INTC_IPRL_INT6 (0x40) +#define MCF_INTC_IPRL_INT7 (0x80) +#define MCF_INTC_IPRL_INT8 (0x100) +#define MCF_INTC_IPRL_INT9 (0x200) +#define MCF_INTC_IPRL_INT10 (0x400) +#define MCF_INTC_IPRL_INT11 (0x800) +#define MCF_INTC_IPRL_INT12 (0x1000) +#define MCF_INTC_IPRL_INT13 (0x2000) +#define MCF_INTC_IPRL_INT14 (0x4000) +#define MCF_INTC_IPRL_INT15 (0x8000) +#define MCF_INTC_IPRL_INT16 (0x10000) +#define MCF_INTC_IPRL_INT17 (0x20000) +#define MCF_INTC_IPRL_INT18 (0x40000) +#define MCF_INTC_IPRL_INT19 (0x80000) +#define MCF_INTC_IPRL_INT20 (0x100000) +#define MCF_INTC_IPRL_INT21 (0x200000) +#define MCF_INTC_IPRL_INT22 (0x400000) +#define MCF_INTC_IPRL_INT23 (0x800000) +#define MCF_INTC_IPRL_INT24 (0x1000000) +#define MCF_INTC_IPRL_INT25 (0x2000000) +#define MCF_INTC_IPRL_INT26 (0x4000000) +#define MCF_INTC_IPRL_INT27 (0x8000000) +#define MCF_INTC_IPRL_INT28 (0x10000000) +#define MCF_INTC_IPRL_INT29 (0x20000000) +#define MCF_INTC_IPRL_INT30 (0x40000000) +#define MCF_INTC_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRH */ +#define MCF_INTC_IMRH_INT_MASK32 (0x1) +#define MCF_INTC_IMRH_INT_MASK33 (0x2) +#define MCF_INTC_IMRH_INT_MASK34 (0x4) +#define MCF_INTC_IMRH_INT_MASK35 (0x8) +#define MCF_INTC_IMRH_INT_MASK36 (0x10) +#define MCF_INTC_IMRH_INT_MASK37 (0x20) +#define MCF_INTC_IMRH_INT_MASK38 (0x40) +#define MCF_INTC_IMRH_INT_MASK39 (0x80) +#define MCF_INTC_IMRH_INT_MASK40 (0x100) +#define MCF_INTC_IMRH_INT_MASK41 (0x200) +#define MCF_INTC_IMRH_INT_MASK42 (0x400) +#define MCF_INTC_IMRH_INT_MASK43 (0x800) +#define MCF_INTC_IMRH_INT_MASK44 (0x1000) +#define MCF_INTC_IMRH_INT_MASK45 (0x2000) +#define MCF_INTC_IMRH_INT_MASK46 (0x4000) +#define MCF_INTC_IMRH_INT_MASK47 (0x8000) +#define MCF_INTC_IMRH_INT_MASK48 (0x10000) +#define MCF_INTC_IMRH_INT_MASK49 (0x20000) +#define MCF_INTC_IMRH_INT_MASK50 (0x40000) +#define MCF_INTC_IMRH_INT_MASK51 (0x80000) +#define MCF_INTC_IMRH_INT_MASK52 (0x100000) +#define MCF_INTC_IMRH_INT_MASK53 (0x200000) +#define MCF_INTC_IMRH_INT_MASK54 (0x400000) +#define MCF_INTC_IMRH_INT_MASK55 (0x800000) +#define MCF_INTC_IMRH_INT_MASK56 (0x1000000) +#define MCF_INTC_IMRH_INT_MASK57 (0x2000000) +#define MCF_INTC_IMRH_INT_MASK58 (0x4000000) +#define MCF_INTC_IMRH_INT_MASK59 (0x8000000) +#define MCF_INTC_IMRH_INT_MASK60 (0x10000000) +#define MCF_INTC_IMRH_INT_MASK61 (0x20000000) +#define MCF_INTC_IMRH_INT_MASK62 (0x40000000) +#define MCF_INTC_IMRH_INT_MASK63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRL */ +#define MCF_INTC_IMRL_MASKALL (0x1) +#define MCF_INTC_IMRL_INT_MASK1 (0x2) +#define MCF_INTC_IMRL_INT_MASK2 (0x4) +#define MCF_INTC_IMRL_INT_MASK3 (0x8) +#define MCF_INTC_IMRL_INT_MASK4 (0x10) +#define MCF_INTC_IMRL_INT_MASK5 (0x20) +#define MCF_INTC_IMRL_INT_MASK6 (0x40) +#define MCF_INTC_IMRL_INT_MASK7 (0x80) +#define MCF_INTC_IMRL_INT_MASK8 (0x100) +#define MCF_INTC_IMRL_INT_MASK9 (0x200) +#define MCF_INTC_IMRL_INT_MASK10 (0x400) +#define MCF_INTC_IMRL_INT_MASK11 (0x800) +#define MCF_INTC_IMRL_INT_MASK12 (0x1000) +#define MCF_INTC_IMRL_INT_MASK13 (0x2000) +#define MCF_INTC_IMRL_INT_MASK14 (0x4000) +#define MCF_INTC_IMRL_INT_MASK15 (0x8000) +#define MCF_INTC_IMRL_INT_MASK16 (0x10000) +#define MCF_INTC_IMRL_INT_MASK17 (0x20000) +#define MCF_INTC_IMRL_INT_MASK18 (0x40000) +#define MCF_INTC_IMRL_INT_MASK19 (0x80000) +#define MCF_INTC_IMRL_INT_MASK20 (0x100000) +#define MCF_INTC_IMRL_INT_MASK21 (0x200000) +#define MCF_INTC_IMRL_INT_MASK22 (0x400000) +#define MCF_INTC_IMRL_INT_MASK23 (0x800000) +#define MCF_INTC_IMRL_INT_MASK24 (0x1000000) +#define MCF_INTC_IMRL_INT_MASK25 (0x2000000) +#define MCF_INTC_IMRL_INT_MASK26 (0x4000000) +#define MCF_INTC_IMRL_INT_MASK27 (0x8000000) +#define MCF_INTC_IMRL_INT_MASK28 (0x10000000) +#define MCF_INTC_IMRL_INT_MASK29 (0x20000000) +#define MCF_INTC_IMRL_INT_MASK30 (0x40000000) +#define MCF_INTC_IMRL_INT_MASK31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCH */ +#define MCF_INTC_INTFRCH_INTFRC32 (0x1) +#define MCF_INTC_INTFRCH_INTFRC33 (0x2) +#define MCF_INTC_INTFRCH_INTFRC34 (0x4) +#define MCF_INTC_INTFRCH_INTFRC35 (0x8) +#define MCF_INTC_INTFRCH_INTFRC36 (0x10) +#define MCF_INTC_INTFRCH_INTFRC37 (0x20) +#define MCF_INTC_INTFRCH_INTFRC38 (0x40) +#define MCF_INTC_INTFRCH_INTFRC39 (0x80) +#define MCF_INTC_INTFRCH_INTFRC40 (0x100) +#define MCF_INTC_INTFRCH_INTFRC41 (0x200) +#define MCF_INTC_INTFRCH_INTFRC42 (0x400) +#define MCF_INTC_INTFRCH_INTFRC43 (0x800) +#define MCF_INTC_INTFRCH_INTFRC44 (0x1000) +#define MCF_INTC_INTFRCH_INTFRC45 (0x2000) +#define MCF_INTC_INTFRCH_INTFRC46 (0x4000) +#define MCF_INTC_INTFRCH_INTFRC47 (0x8000) +#define MCF_INTC_INTFRCH_INTFRC48 (0x10000) +#define MCF_INTC_INTFRCH_INTFRC49 (0x20000) +#define MCF_INTC_INTFRCH_INTFRC50 (0x40000) +#define MCF_INTC_INTFRCH_INTFRC51 (0x80000) +#define MCF_INTC_INTFRCH_INTFRC52 (0x100000) +#define MCF_INTC_INTFRCH_INTFRC53 (0x200000) +#define MCF_INTC_INTFRCH_INTFRC54 (0x400000) +#define MCF_INTC_INTFRCH_INTFRC55 (0x800000) +#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000) +#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000) +#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000) +#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000) +#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) +#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) +#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) +#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCL */ +#define MCF_INTC_INTFRCL_INTFRC1 (0x2) +#define MCF_INTC_INTFRCL_INTFRC2 (0x4) +#define MCF_INTC_INTFRCL_INTFRC3 (0x8) +#define MCF_INTC_INTFRCL_INTFRC4 (0x10) +#define MCF_INTC_INTFRCL_INTFRC5 (0x20) +#define MCF_INTC_INTFRCL_INTFRC6 (0x40) +#define MCF_INTC_INTFRCL_INTFRC7 (0x80) +#define MCF_INTC_INTFRCL_INTFRC8 (0x100) +#define MCF_INTC_INTFRCL_INTFRC9 (0x200) +#define MCF_INTC_INTFRCL_INTFRC10 (0x400) +#define MCF_INTC_INTFRCL_INTFRC11 (0x800) +#define MCF_INTC_INTFRCL_INTFRC12 (0x1000) +#define MCF_INTC_INTFRCL_INTFRC13 (0x2000) +#define MCF_INTC_INTFRCL_INTFRC14 (0x4000) +#define MCF_INTC_INTFRCL_INTFRC15 (0x8000) +#define MCF_INTC_INTFRCL_INTFRC16 (0x10000) +#define MCF_INTC_INTFRCL_INTFRC17 (0x20000) +#define MCF_INTC_INTFRCL_INTFRC18 (0x40000) +#define MCF_INTC_INTFRCL_INTFRC19 (0x80000) +#define MCF_INTC_INTFRCL_INTFRC20 (0x100000) +#define MCF_INTC_INTFRCL_INTFRC21 (0x200000) +#define MCF_INTC_INTFRCL_INTFRC22 (0x400000) +#define MCF_INTC_INTFRCL_INTFRC23 (0x800000) +#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000) +#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000) +#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000) +#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000) +#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) +#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) +#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) +#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IRLR */ +#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1) + +/* Bit definitions and macros for MCF_INTC_IACKLPR */ +#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0) +#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4) + +/* Bit definitions and macros for MCF_INTC_ICR */ +#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0) +#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3) + +/* Bit definitions and macros for MCF_INTC_SWIACK */ +#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_INTC_LIACK */ +#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) + + +#endif /* __MCF5475_INTC_H__ */ diff --git a/tos/jtagwait/include/MCF5475_MMU.h b/tos/jtagwait/include/MCF5475_MMU.h new file mode 100644 index 0000000..334ad28 --- /dev/null +++ b/tos/jtagwait/include/MCF5475_MMU.h @@ -0,0 +1,79 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_MMU_H__ +#define __MCF5475_MMU_H__ + + +/********************************************************************* +* +* Memory Management Unit (MMU) +* +*********************************************************************/ + +/* Register read/write macros */ + +/* note the uint32_t_a - this is to avoid gcc warnings about pointer aliasing */ +#define MCF_MMU_MMUCR (*(volatile uint32_t_a*)(&_MMUBAR[0])) +#define MCF_MMU_MMUOR (*(volatile uint32_t_a*)(&_MMUBAR[0x4])) +#define MCF_MMU_MMUSR (*(volatile uint32_t_a*)(&_MMUBAR[0x8])) +#define MCF_MMU_MMUAR (*(volatile uint32_t_a*)(&_MMUBAR[0x10])) +#define MCF_MMU_MMUTR (*(volatile uint32_t_a*)(&_MMUBAR[0x14])) +#define MCF_MMU_MMUDR (*(volatile uint32_t_a*)(&_MMUBAR[0x18])) + + +/* Bit definitions and macros for MCF_MMU_MMUCR */ +#define MCF_MMU_MMUCR_EN (0x1) +#define MCF_MMU_MMUCR_ASM (0x2) + +/* Bit definitions and macros for MCF_MMU_MMUOR */ +#define MCF_MMU_MMUOR_UAA (0x1) +#define MCF_MMU_MMUOR_ACC (0x2) +#define MCF_MMU_MMUOR_RW (0x4) +#define MCF_MMU_MMUOR_ADR (0x8) +#define MCF_MMU_MMUOR_ITLB (0x10) +#define MCF_MMU_MMUOR_CAS (0x20) +#define MCF_MMU_MMUOR_CNL (0x40) +#define MCF_MMU_MMUOR_CA (0x80) +#define MCF_MMU_MMUOR_STLB (0x100) +#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_MMU_MMUSR */ +#define MCF_MMU_MMUSR_HIT (0x2) +#define MCF_MMU_MMUSR_WF (0x8) +#define MCF_MMU_MMUSR_RF (0x10) +#define MCF_MMU_MMUSR_SPF (0x20) + +/* Bit definitions and macros for MCF_MMU_MMUAR */ +#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MMU_MMUTR */ +#define MCF_MMU_MMUTR_V (0x1) +#define MCF_MMU_MMUTR_SG (0x2) +#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2) +#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA) + +/* Bit definitions and macros for MCF_MMU_MMUDR */ +#define MCF_MMU_MMUDR_LK (0x2) +#define MCF_MMU_MMUDR_X (0x4) +#define MCF_MMU_MMUDR_W (0x8) +#define MCF_MMU_MMUDR_R (0x10) +#define MCF_MMU_MMUDR_SP (0x20) +#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6) +#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8) +#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA) + + +#endif /* __MCF5475_MMU_H__ */ diff --git a/tos/jtagwait/include/MCF5475_PAD.h b/tos/jtagwait/include/MCF5475_PAD.h new file mode 100644 index 0000000..1d87e2e --- /dev/null +++ b/tos/jtagwait/include/MCF5475_PAD.h @@ -0,0 +1,233 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PAD_H__ +#define __MCF5475_PAD_H__ + + +/********************************************************************* +* +* Common GPIO +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PAD_PAR_FBCTL (*(volatile uint16_t*)(&_MBAR[0xA40])) +#define MCF_PAD_PAR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA42])) +#define MCF_PAD_PAR_DMA (*(volatile uint8_t *)(&_MBAR[0xA43])) +#define MCF_PAD_PAR_FECI2CIRQ (*(volatile uint16_t*)(&_MBAR[0xA44])) +#define MCF_PAD_PAR_PCIBG (*(volatile uint16_t*)(&_MBAR[0xA48])) +#define MCF_PAD_PAR_PCIBR (*(volatile uint16_t*)(&_MBAR[0xA4A])) +#define MCF_PAD_PAR_PSC3 (*(volatile uint8_t *)(&_MBAR[0xA4C])) +#define MCF_PAD_PAR_PSC2 (*(volatile uint8_t *)(&_MBAR[0xA4D])) +#define MCF_PAD_PAR_PSC1 (*(volatile uint8_t *)(&_MBAR[0xA4E])) +#define MCF_PAD_PAR_PSC0 (*(volatile uint8_t *)(&_MBAR[0xA4F])) +#define MCF_PAD_PAR_DSPI (*(volatile uint16_t*)(&_MBAR[0xA50])) +#define MCF_PAD_PAR_TIMER (*(volatile uint8_t *)(&_MBAR[0xA52])) + + +/* Bit definitions and macros for MCF_PAD_PAR_FBCTL */ +#define MCF_PAD_PAR_FBCTL_PAR_ALE(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_FBCTL_PAR_ALE_GPIO (0) +#define MCF_PAD_PAR_FBCTL_PAR_ALE_TBST (0x2) +#define MCF_PAD_PAR_FBCTL_PAR_ALE_ALE (0x3) +#define MCF_PAD_PAR_FBCTL_PAR_TA (0x4) +#define MCF_PAD_PAR_FBCTL_PAR_RWB(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_FBCTL_PAR_RWB_GPIO (0) +#define MCF_PAD_PAR_FBCTL_PAR_RWB_TBST (0x20) +#define MCF_PAD_PAR_FBCTL_PAR_RWB_RW (0x30) +#define MCF_PAD_PAR_FBCTL_PAR_OE (0x40) +#define MCF_PAD_PAR_FBCTL_PAR_BWE0 (0x100) +#define MCF_PAD_PAR_FBCTL_PAR_BWE1 (0x400) +#define MCF_PAD_PAR_FBCTL_PAR_BWE2 (0x1000) +#define MCF_PAD_PAR_FBCTL_PAR_BWE3 (0x4000) + +/* Bit definitions and macros for MCF_PAD_PAR_FBCS */ +#define MCF_PAD_PAR_FBCS_PAR_CS1 (0x2) +#define MCF_PAD_PAR_FBCS_PAR_CS2 (0x4) +#define MCF_PAD_PAR_FBCS_PAR_CS3 (0x8) +#define MCF_PAD_PAR_FBCS_PAR_CS4 (0x10) +#define MCF_PAD_PAR_FBCS_PAR_CS5 (0x20) + +/* Bit definitions and macros for MCF_PAD_PAR_DMA */ +#define MCF_PAD_PAR_DMA_PAR_DREQ0(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_DMA_PAR_DREQ0_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DREQ0_TIN0 (0x2) +#define MCF_PAD_PAR_DMA_PAR_DREQ0_DREQ0 (0x3) +#define MCF_PAD_PAR_DMA_PAR_DREQ1(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_IRQ1 (0x4) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_TIN1 (0x8) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_DREQ1 (0xC) +#define MCF_PAD_PAR_DMA_PAR_DACK0(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_DMA_PAR_DACK0_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DACK0_TOUT0 (0x20) +#define MCF_PAD_PAR_DMA_PAR_DACK0_DACK0 (0x30) +#define MCF_PAD_PAR_DMA_PAR_DACK1(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_DMA_PAR_DACK1_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DACK1_TOUT1 (0x80) +#define MCF_PAD_PAR_DMA_PAR_DACK1_DACK1 (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_FECI2CIRQ */ +#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ5 (0x1) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ6 (0x2) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_SCL (0x4) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_SDA (0x8) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x80) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC (0xC0) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x200) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO (0x300) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MII (0x400) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E17 (0x800) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC (0x1000) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII (0x4000) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E07 (0x8000) + +/* Bit definitions and macros for MCF_PAD_PAR_PCIBG */ +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_TOUT0 (0x2) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0 (0x3) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_TOUT1 (0x8) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 (0xC) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_TOUT2 (0x20) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 (0x30) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_TOUT3 (0x80) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3 (0xC0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST (0x200) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4 (0x300) + +/* Bit definitions and macros for MCF_PAD_PAR_PCIBR */ +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_TIN0 (0x2) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0 (0x3) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_TIN1 (0x8) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 (0xC) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_TIN2 (0x20) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 (0x30) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_TIN3 (0x80) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3 (0xC0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4 (0x200) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4 (0x300) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC3 */ +#define MCF_PAD_PAR_PSC3_PAR_TXD3 (0x4) +#define MCF_PAD_PAR_PSC3_PAR_RXD3 (0x8) +#define MCF_PAD_PAR_PSC3_PAR_RTS3(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC3_PAR_RTS3_GPIO (0) +#define MCF_PAD_PAR_PSC3_PAR_RTS3_FSYNC (0x20) +#define MCF_PAD_PAR_PSC3_PAR_RTS3_RTS (0x30) +#define MCF_PAD_PAR_PSC3_PAR_CTS3(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC3_PAR_CTS3_GPIO (0) +#define MCF_PAD_PAR_PSC3_PAR_CTS3_BCLK (0x80) +#define MCF_PAD_PAR_PSC3_PAR_CTS3_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC2 */ +#define MCF_PAD_PAR_PSC2_PAR_TXD2 (0x4) +#define MCF_PAD_PAR_PSC2_PAR_RXD2 (0x8) +#define MCF_PAD_PAR_PSC2_PAR_RTS2(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC2_PAR_RTS2_GPIO (0) +#define MCF_PAD_PAR_PSC2_PAR_RTS2_FSYNC (0x20) +#define MCF_PAD_PAR_PSC2_PAR_RTS2_RTS (0x30) +#define MCF_PAD_PAR_PSC2_PAR_CTS2(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC2_PAR_CTS2_GPIO (0) +#define MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK (0x80) +#define MCF_PAD_PAR_PSC2_PAR_CTS2_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC1 */ +#define MCF_PAD_PAR_PSC1_PAR_TXD1 (0x4) +#define MCF_PAD_PAR_PSC1_PAR_RXD1 (0x8) +#define MCF_PAD_PAR_PSC1_PAR_RTS1(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC1_PAR_RTS1_GPIO (0) +#define MCF_PAD_PAR_PSC1_PAR_RTS1_FSYNC (0x20) +#define MCF_PAD_PAR_PSC1_PAR_RTS1_RTS (0x30) +#define MCF_PAD_PAR_PSC1_PAR_CTS1(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC1_PAR_CTS1_GPIO (0) +#define MCF_PAD_PAR_PSC1_PAR_CTS1_BCLK (0x80) +#define MCF_PAD_PAR_PSC1_PAR_CTS1_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC0 */ +#define MCF_PAD_PAR_PSC0_PAR_TXD0 (0x4) +#define MCF_PAD_PAR_PSC0_PAR_RXD0 (0x8) +#define MCF_PAD_PAR_PSC0_PAR_RTS0(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC0_PAR_RTS0_GPIO (0) +#define MCF_PAD_PAR_PSC0_PAR_RTS0_FSYNC (0x20) +#define MCF_PAD_PAR_PSC0_PAR_RTS0_RTS (0x30) +#define MCF_PAD_PAR_PSC0_PAR_CTS0(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC0_PAR_CTS0_GPIO (0) +#define MCF_PAD_PAR_PSC0_PAR_CTS0_BCLK (0x80) +#define MCF_PAD_PAR_PSC0_PAR_CTS0_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_DSPI */ +#define MCF_PAD_PAR_DSPI_PAR_SOUT(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_DSPI_PAR_SOUT_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_SOUT_TXD (0x2) +#define MCF_PAD_PAR_DSPI_PAR_SOUT_SOUT (0x3) +#define MCF_PAD_PAR_DSPI_PAR_SIN(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_DSPI_PAR_SIN_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_SIN_RXD (0x8) +#define MCF_PAD_PAR_DSPI_PAR_SIN_SIN (0xC) +#define MCF_PAD_PAR_DSPI_PAR_SCK(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_DSPI_PAR_SCK_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_SCK_BCLK (0x10) +#define MCF_PAD_PAR_DSPI_PAR_SCK_CTS (0x20) +#define MCF_PAD_PAR_DSPI_PAR_SCK_SCK (0x30) +#define MCF_PAD_PAR_DSPI_PAR_CS0(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_DSPI_PAR_CS0_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_CS0_FSYNC (0x40) +#define MCF_PAD_PAR_DSPI_PAR_CS0_RTS (0x80) +#define MCF_PAD_PAR_DSPI_PAR_CS0_DSPICS0 (0xC0) +#define MCF_PAD_PAR_DSPI_PAR_CS2(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_DSPI_PAR_CS2_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_CS2_TOUT2 (0x200) +#define MCF_PAD_PAR_DSPI_PAR_CS2_DSPICS2 (0x300) +#define MCF_PAD_PAR_DSPI_PAR_CS3(x) (((x)&0x3)<<0xA) +#define MCF_PAD_PAR_DSPI_PAR_CS3_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_CS3_TOUT3 (0x800) +#define MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3 (0xC00) +#define MCF_PAD_PAR_DSPI_PAR_CS5 (0x1000) + +/* Bit definitions and macros for MCF_PAD_PAR_TIMER */ +#define MCF_PAD_PAR_TIMER_PAR_TOUT2 (0x1) +#define MCF_PAD_PAR_TIMER_PAR_TIN2(x) (((x)&0x3)<<0x1) +#define MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2 (0x4) +#define MCF_PAD_PAR_TIMER_PAR_TIN2_TIN2 (0x6) +#define MCF_PAD_PAR_TIMER_PAR_TOUT3 (0x8) +#define MCF_PAD_PAR_TIMER_PAR_TIN3(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_TIMER_PAR_TIN3_IRQ3 (0x20) +#define MCF_PAD_PAR_TIMER_PAR_TIN3_TIN3 (0x30) + + +#endif /* __MCF5475_PAD_H__ */ diff --git a/tos/jtagwait/include/MCF5475_PCI.h b/tos/jtagwait/include/MCF5475_PCI.h new file mode 100644 index 0000000..3eb3341 --- /dev/null +++ b/tos/jtagwait/include/MCF5475_PCI.h @@ -0,0 +1,376 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PCI_H__ +#define __MCF5475_PCI_H__ + + +/********************************************************************* +* +* PCI Bus Controller (PCI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PCI_PCIIDR (*(volatile uint32_t*)(&_MBAR[0xB00])) +#define MCF_PCI_PCISCR (*(volatile uint32_t*)(&_MBAR[0xB04])) +#define MCF_PCI_PCICCRIR (*(volatile uint32_t*)(&_MBAR[0xB08])) +#define MCF_PCI_PCICR1 (*(volatile uint32_t*)(&_MBAR[0xB0C])) +#define MCF_PCI_PCIBAR0 (*(volatile uint32_t*)(&_MBAR[0xB10])) +#define MCF_PCI_PCIBAR1 (*(volatile uint32_t*)(&_MBAR[0xB14])) +#define MCF_PCI_PCICCPR (*(volatile uint32_t*)(&_MBAR[0xB28])) +#define MCF_PCI_PCISID (*(volatile uint32_t*)(&_MBAR[0xB2C])) +#define MCF_PCI_PCICR2 (*(volatile uint32_t*)(&_MBAR[0xB3C])) +#define MCF_PCI_PCIGSCR (*(volatile uint32_t*)(&_MBAR[0xB60])) +#define MCF_PCI_PCITBATR0 (*(volatile uint32_t*)(&_MBAR[0xB64])) +#define MCF_PCI_PCITBATR1 (*(volatile uint32_t*)(&_MBAR[0xB68])) +#define MCF_PCI_PCITCR (*(volatile uint32_t*)(&_MBAR[0xB6C])) +#define MCF_PCI_PCIIW0BTAR (*(volatile uint32_t*)(&_MBAR[0xB70])) +#define MCF_PCI_PCIIW1BTAR (*(volatile uint32_t*)(&_MBAR[0xB74])) +#define MCF_PCI_PCIIW2BTAR (*(volatile uint32_t*)(&_MBAR[0xB78])) +#define MCF_PCI_PCIIWCR (*(volatile uint32_t*)(&_MBAR[0xB80])) +#define MCF_PCI_PCIICR (*(volatile uint32_t*)(&_MBAR[0xB84])) +#define MCF_PCI_PCIISR (*(volatile uint32_t*)(&_MBAR[0xB88])) +#define MCF_PCI_PCICAR (*(volatile uint32_t*)(&_MBAR[0xBF8])) +#define MCF_PCI_PCITPSR (*(volatile uint32_t*)(&_MBAR[0x8400])) +#define MCF_PCI_PCITSAR (*(volatile uint32_t*)(&_MBAR[0x8404])) +#define MCF_PCI_PCITTCR (*(volatile uint32_t*)(&_MBAR[0x8408])) +#define MCF_PCI_PCITER (*(volatile uint32_t*)(&_MBAR[0x840C])) +#define MCF_PCI_PCITNAR (*(volatile uint32_t*)(&_MBAR[0x8410])) +#define MCF_PCI_PCITLWR (*(volatile uint32_t*)(&_MBAR[0x8414])) +#define MCF_PCI_PCITDCR (*(volatile uint32_t*)(&_MBAR[0x8418])) +#define MCF_PCI_PCITSR (*(volatile uint32_t*)(&_MBAR[0x841C])) +#define MCF_PCI_PCITFDR (*(volatile uint32_t*)(&_MBAR[0x8440])) +#define MCF_PCI_PCITFSR (*(volatile uint32_t*)(&_MBAR[0x8444])) +#define MCF_PCI_PCITFCR (*(volatile uint32_t*)(&_MBAR[0x8448])) +#define MCF_PCI_PCITFAR (*(volatile uint32_t*)(&_MBAR[0x844C])) +#define MCF_PCI_PCITFRPR (*(volatile uint32_t*)(&_MBAR[0x8450])) +#define MCF_PCI_PCITFWPR (*(volatile uint32_t*)(&_MBAR[0x8454])) +#define MCF_PCI_PCIRPSR (*(volatile uint32_t*)(&_MBAR[0x8480])) +#define MCF_PCI_PCIRSAR (*(volatile uint32_t*)(&_MBAR[0x8484])) +#define MCF_PCI_PCIRTCR (*(volatile uint32_t*)(&_MBAR[0x8488])) +#define MCF_PCI_PCIRER (*(volatile uint32_t*)(&_MBAR[0x848C])) +#define MCF_PCI_PCIRNAR (*(volatile uint32_t*)(&_MBAR[0x8490])) +#define MCF_PCI_PCIRDCR (*(volatile uint32_t*)(&_MBAR[0x8498])) +#define MCF_PCI_PCIRSR (*(volatile uint32_t*)(&_MBAR[0x849C])) +#define MCF_PCI_PCIRFDR (*(volatile uint32_t*)(&_MBAR[0x84C0])) +#define MCF_PCI_PCIRFSR (*(volatile uint32_t*)(&_MBAR[0x84C4])) +#define MCF_PCI_PCIRFCR (*(volatile uint32_t*)(&_MBAR[0x84C8])) +#define MCF_PCI_PCIRFAR (*(volatile uint32_t*)(&_MBAR[0x84CC])) +#define MCF_PCI_PCIRFRPR (*(volatile uint32_t*)(&_MBAR[0x84D0])) +#define MCF_PCI_PCIRFWPR (*(volatile uint32_t*)(&_MBAR[0x84D4])) + + +/* Bit definitions and macros for MCF_PCI_PCIIDR */ +#define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCISCR */ +#define MCF_PCI_PCISCR_IO (0x1) +#define MCF_PCI_PCISCR_M (0x2) +#define MCF_PCI_PCISCR_B (0x4) +#define MCF_PCI_PCISCR_SP (0x8) +#define MCF_PCI_PCISCR_MW (0x10) +#define MCF_PCI_PCISCR_V (0x20) +#define MCF_PCI_PCISCR_PER (0x40) +#define MCF_PCI_PCISCR_ST (0x80) +#define MCF_PCI_PCISCR_S (0x100) +#define MCF_PCI_PCISCR_F (0x200) +#define MCF_PCI_PCISCR_C (0x100000) +#define MCF_PCI_PCISCR_66M (0x200000) +#define MCF_PCI_PCISCR_R (0x400000) +#define MCF_PCI_PCISCR_FC (0x800000) +#define MCF_PCI_PCISCR_DP (0x1000000) +#define MCF_PCI_PCISCR_DT(x) (((x)&0x3)<<0x19) +#define MCF_PCI_PCISCR_TS (0x8000000) +#define MCF_PCI_PCISCR_TR (0x10000000) +#define MCF_PCI_PCISCR_MA (0x20000000) +#define MCF_PCI_PCISCR_SE (0x40000000) +#define MCF_PCI_PCISCR_PE (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCICCRIR */ +#define MCF_PCI_PCICCRIR_REVISIONID(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0xFFFFFF)<<0x8) + +/* Bit definitions and macros for MCF_PCI_PCICR1 */ +#define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICR1_BIST(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIBAR0 */ +#define MCF_PCI_PCIBAR0_IOM (0x1) +#define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x3)<<0x1) +#define MCF_PCI_PCIBAR0_PREF (0x8) +#define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x3FFF)<<0x12) + +/* Bit definitions and macros for MCF_PCI_PCIBAR1 */ +#define MCF_PCI_PCIBAR1_IOM (0x1) +#define MCF_PCI_PCIBAR1_RANGE(x) (((x)&0x3)<<0x1) +#define MCF_PCI_PCIBAR1_PREF (0x8) +#define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_PCI_PCICCPR */ +#define MCF_PCI_PCICCPR_PCICCP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCISID */ +#define MCF_PCI_PCISID_VENDORID(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCICR2 */ +#define MCF_PCI_PCICR2_INTLINE(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICR2_INTPIN(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCICR2_MINGNT(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIGSCR */ +#define MCF_PCI_PCIGSCR_PR (0x1) +#define MCF_PCI_PCIGSCR_SEE (0x1000) +#define MCF_PCI_PCIGSCR_PEE (0x2000) +#define MCF_PCI_PCIGSCR_CLKINRESERVED(x) (((x)&0x7)<<0x10) +#define MCF_PCI_PCIGSCR_XLB2CLKIN(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCIGSCR_SE (0x10000000) +#define MCF_PCI_PCIGSCR_PE (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCITBATR0 */ +#define MCF_PCI_PCITBATR0_EN (0x1) +#define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x3FFF)<<0x12) + +/* Bit definitions and macros for MCF_PCI_PCITBATR1 */ +#define MCF_PCI_PCITBATR1_EN (0x1) +#define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_PCI_PCITCR */ +#define MCF_PCI_PCITCR_P (0x10000) +#define MCF_PCI_PCITCR_LD (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */ +#define MCF_PCI_PCIIW0BTAR_WTA0(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW0BTAR_WAM0(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW0BTAR_WBA0(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */ +#define MCF_PCI_PCIIW1BTAR_WTA1(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW1BTAR_WAM1(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW1BTAR_WBA1(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */ +#define MCF_PCI_PCIIW2BTAR_WTA2(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW2BTAR_WAM2(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW2BTAR_WBA2(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIWCR */ +#define MCF_PCI_PCIIWCR_WINCTRL2_E (0x100) +#define MCF_PCI_PCIIWCR_WINCTRL2_PRC(x) (((x)&0x3)<<0x9) +#define MCF_PCI_PCIIWCR_WINCTRL2_IOM (0x800) +#define MCF_PCI_PCIIWCR_WINCTRL1_E (0x10000) +#define MCF_PCI_PCIIWCR_WINCTRL1_PRC(x) (((x)&0x3)<<0x11) +#define MCF_PCI_PCIIWCR_WINCTRL1_IOM (0x80000) +#define MCF_PCI_PCIIWCR_WINCTRL0_E (0x1000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_PRC(x) (((x)&0x3)<<0x19) +#define MCF_PCI_PCIIWCR_WINCTRL0_IOM (0x8000000) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x100) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x300) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x500) +#define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x900) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x10000) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x30000) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x50000) +#define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x90000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x1000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x3000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x5000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x9000000) + +/* Bit definitions and macros for MCF_PCI_PCIICR */ +#define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCIICR_TAE (0x1000000) +#define MCF_PCI_PCIICR_IAE (0x2000000) +#define MCF_PCI_PCIICR_REE (0x4000000) + +/* Bit definitions and macros for MCF_PCI_PCIISR */ +#define MCF_PCI_PCIISR_TA (0x1000000) +#define MCF_PCI_PCIISR_IA (0x2000000) +#define MCF_PCI_PCIISR_RE (0x4000000) + +/* Bit definitions and macros for MCF_PCI_PCICAR */ +#define MCF_PCI_PCICAR_DWORD(x) (((x)&0x3F)<<0x2) +#define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x1F)<<0xB) +#define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICAR_E (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITPSR */ +#define MCF_PCI_PCITPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCITSAR */ +#define MCF_PCI_PCITSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITTCR */ +#define MCF_PCI_PCITTCR_DI (0x1) +#define MCF_PCI_PCITTCR_W (0x10) +#define MCF_PCI_PCITTCR_MAXBEATS(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCITTCR_MAXRETRY(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCITTCR_PCICMD(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCITER */ +#define MCF_PCI_PCITER_NE (0x10000) +#define MCF_PCI_PCITER_IAE (0x20000) +#define MCF_PCI_PCITER_TAE (0x40000) +#define MCF_PCI_PCITER_RE (0x80000) +#define MCF_PCI_PCITER_SE (0x100000) +#define MCF_PCI_PCITER_FEE (0x200000) +#define MCF_PCI_PCITER_ME (0x1000000) +#define MCF_PCI_PCITER_BE (0x8000000) +#define MCF_PCI_PCITER_CM (0x10000000) +#define MCF_PCI_PCITER_RF (0x40000000) +#define MCF_PCI_PCITER_RC (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITNAR */ +#define MCF_PCI_PCITNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITLWR */ +#define MCF_PCI_PCITLWR_LASTWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITDCR */ +#define MCF_PCI_PCITDCR_PKTSDONE(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCITDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCITSR */ +#define MCF_PCI_PCITSR_IA (0x10000) +#define MCF_PCI_PCITSR_TA (0x20000) +#define MCF_PCI_PCITSR_RE (0x40000) +#define MCF_PCI_PCITSR_SE (0x80000) +#define MCF_PCI_PCITSR_FE (0x100000) +#define MCF_PCI_PCITSR_BE1 (0x200000) +#define MCF_PCI_PCITSR_BE2 (0x400000) +#define MCF_PCI_PCITSR_BE3 (0x800000) +#define MCF_PCI_PCITSR_NT (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCITFDR */ +#define MCF_PCI_PCITFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFSR */ +#define MCF_PCI_PCITFSR_EMPTY (0x10000) +#define MCF_PCI_PCITFSR_ALARM (0x20000) +#define MCF_PCI_PCITFSR_FULL (0x40000) +#define MCF_PCI_PCITFSR_FR (0x80000) +#define MCF_PCI_PCITFSR_OF (0x100000) +#define MCF_PCI_PCITFSR_UF (0x200000) +#define MCF_PCI_PCITFSR_RXW (0x400000) +#define MCF_PCI_PCITFSR_FAE (0x800000) +#define MCF_PCI_PCITFSR_TXW (0x40000000) +#define MCF_PCI_PCITFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITFCR */ +#define MCF_PCI_PCITFCR_TXW_MASK (0x40000) +#define MCF_PCI_PCITFCR_OF_MASK (0x80000) +#define MCF_PCI_PCITFCR_UF_MASK (0x100000) +#define MCF_PCI_PCITFCR_RXW_MASK (0x200000) +#define MCF_PCI_PCITFCR_FAE_MASK (0x400000) +#define MCF_PCI_PCITFCR_IP_MASK (0x800000) +#define MCF_PCI_PCITFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCITFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCITFAR */ +#define MCF_PCI_PCITFAR_ALARM(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFRPR */ +#define MCF_PCI_PCITFRPR_READPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFWPR */ +#define MCF_PCI_PCITFWPR_WRITEPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRPSR */ +#define MCF_PCI_PCIRPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCIRSAR */ +#define MCF_PCI_PCIRSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRTCR */ +#define MCF_PCI_PCIRTCR_DI (0x1) +#define MCF_PCI_PCIRTCR_W (0x10) +#define MCF_PCI_PCIRTCR_MAXBEATS(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCIRTCR_FB (0x1000) +#define MCF_PCI_PCIRTCR_MAXRETRY(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIRTCR_PCICMD(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIRER */ +#define MCF_PCI_PCIRER_NE (0x10000) +#define MCF_PCI_PCIRER_IAE (0x20000) +#define MCF_PCI_PCIRER_TAE (0x40000) +#define MCF_PCI_PCIRER_RE (0x80000) +#define MCF_PCI_PCIRER_SE (0x100000) +#define MCF_PCI_PCIRER_FEE (0x200000) +#define MCF_PCI_PCIRER_ME (0x1000000) +#define MCF_PCI_PCIRER_BE (0x8000000) +#define MCF_PCI_PCIRER_CM (0x10000000) +#define MCF_PCI_PCIRER_FE (0x20000000) +#define MCF_PCI_PCIRER_RF (0x40000000) +#define MCF_PCI_PCIRER_RC (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCIRNAR */ +#define MCF_PCI_PCIRNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRDCR */ +#define MCF_PCI_PCIRDCR_PKTSDONE(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCIRDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCIRSR */ +#define MCF_PCI_PCIRSR_IA (0x10000) +#define MCF_PCI_PCIRSR_TA (0x20000) +#define MCF_PCI_PCIRSR_RE (0x40000) +#define MCF_PCI_PCIRSR_SE (0x80000) +#define MCF_PCI_PCIRSR_FE (0x100000) +#define MCF_PCI_PCIRSR_BE1 (0x200000) +#define MCF_PCI_PCIRSR_BE2 (0x400000) +#define MCF_PCI_PCIRSR_BE3 (0x800000) +#define MCF_PCI_PCIRSR_NT (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFDR */ +#define MCF_PCI_PCIRFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFSR */ +#define MCF_PCI_PCIRFSR_EMPTY (0x10000) +#define MCF_PCI_PCIRFSR_ALARM (0x20000) +#define MCF_PCI_PCIRFSR_FULL (0x40000) +#define MCF_PCI_PCIRFSR_FR (0x80000) +#define MCF_PCI_PCIRFSR_OF (0x100000) +#define MCF_PCI_PCIRFSR_UF (0x200000) +#define MCF_PCI_PCIRFSR_RXW (0x400000) +#define MCF_PCI_PCIRFSR_FAE (0x800000) +#define MCF_PCI_PCIRFSR_TXW (0x40000000) +#define MCF_PCI_PCIRFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFCR */ +#define MCF_PCI_PCIRFCR_TXW_MASK (0x40000) +#define MCF_PCI_PCIRFCR_OF_MASK (0x80000) +#define MCF_PCI_PCIRFCR_UF_MASK (0x100000) +#define MCF_PCI_PCIRFCR_RXW_MASK (0x200000) +#define MCF_PCI_PCIRFCR_FAE_MASK (0x400000) +#define MCF_PCI_PCIRFCR_IP_MASK (0x800000) +#define MCF_PCI_PCIRFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCIRFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFAR */ +#define MCF_PCI_PCIRFAR_ALARM(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFRPR */ +#define MCF_PCI_PCIRFRPR_READPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFWPR */ +#define MCF_PCI_PCIRFWPR_WRITEPTR(x) (((x)&0x7F)<<0) + + +#endif /* __MCF5475_PCI_H__ */ diff --git a/tos/jtagwait/include/MCF5475_PCIARB.h b/tos/jtagwait/include/MCF5475_PCIARB.h new file mode 100644 index 0000000..9e8c05b --- /dev/null +++ b/tos/jtagwait/include/MCF5475_PCIARB.h @@ -0,0 +1,43 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PCIARB_H__ +#define __MCF5475_PCIARB_H__ + + +/********************************************************************* +* +* PCI Bus Arbiter Module (PCIARB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PCIARB_PACR (*(volatile uint32_t*)(&_MBAR[0xC00])) +#define MCF_PCIARB_PASR (*(volatile uint32_t*)(&_MBAR[0xC04])) + + +/* Bit definitions and macros for MCF_PCIARB_PACR */ +#define MCF_PCIARB_PACR_INTMPRI (0x1) +#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x1F)<<0x1) +#define MCF_PCIARB_PACR_INTMINTEN (0x10000) +#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x1F)<<0x11) +#define MCF_PCIARB_PACR_DS (0x80000000) + +/* Bit definitions and macros for MCF_PCIARB_PASR */ +#define MCF_PCIARB_PASR_ITLMBK (0x10000) +#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x1F)<<0x11) + + +#endif /* __MCF5475_PCIARB_H__ */ diff --git a/tos/jtagwait/include/MCF5475_PSC.h b/tos/jtagwait/include/MCF5475_PSC.h new file mode 100644 index 0000000..ffa9f3e --- /dev/null +++ b/tos/jtagwait/include/MCF5475_PSC.h @@ -0,0 +1,527 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PSC_H__ +#define __MCF5475_PSC_H__ + + +/********************************************************************* +* +* Programmable Serial Controller (PSC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PSC0_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8600])) +#define MCF_PSC0_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8600])) +#define MCF_PSC0_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8604])) +#define MCF_PSC0_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8604])) +#define MCF_PSC0_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8608])) +#define MCF_PSC0_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8610])) +#define MCF_PSC0_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8610])) +#define MCF_PSC0_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8614])) +#define MCF_PSC0_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8614])) +#define MCF_PSC0_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8618])) +#define MCF_PSC0_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x861C])) +#define MCF_PSC0_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8634])) +#define MCF_PSC0_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8638])) +#define MCF_PSC0_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x863C])) +#define MCF_PSC0_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8640])) +#define MCF_PSC0_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8644])) +#define MCF_PSC0_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8648])) +#define MCF_PSC0_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x864C])) +#define MCF_PSC0_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8650])) +#define MCF_PSC0_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8654])) +#define MCF_PSC0_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8658])) +#define MCF_PSC0_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x865C])) +#define MCF_PSC0_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8660])) +#define MCF_PSC0_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8664])) +#define MCF_PSC0_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8668])) +#define MCF_PSC0_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x866E])) +#define MCF_PSC0_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8672])) +#define MCF_PSC0_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8676])) +#define MCF_PSC0_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x867A])) +#define MCF_PSC0_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x867E])) +#define MCF_PSC0_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8680])) +#define MCF_PSC0_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8684])) +#define MCF_PSC0_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8688])) +#define MCF_PSC0_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x868E])) +#define MCF_PSC0_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8692])) +#define MCF_PSC0_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8696])) +#define MCF_PSC0_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x869A])) +#define MCF_PSC0_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x869E])) + +#define MCF_PSC1_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8700])) +#define MCF_PSC1_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8700])) +#define MCF_PSC1_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8704])) +#define MCF_PSC1_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8704])) +#define MCF_PSC1_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8708])) +#define MCF_PSC1_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8710])) +#define MCF_PSC1_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8710])) +#define MCF_PSC1_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8714])) +#define MCF_PSC1_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8714])) +#define MCF_PSC1_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8718])) +#define MCF_PSC1_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x871C])) +#define MCF_PSC1_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8734])) +#define MCF_PSC1_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8738])) +#define MCF_PSC1_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x873C])) +#define MCF_PSC1_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8740])) +#define MCF_PSC1_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8744])) +#define MCF_PSC1_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8748])) +#define MCF_PSC1_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x874C])) +#define MCF_PSC1_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8750])) +#define MCF_PSC1_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8754])) +#define MCF_PSC1_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8758])) +#define MCF_PSC1_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x875C])) +#define MCF_PSC1_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8760])) +#define MCF_PSC1_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8764])) +#define MCF_PSC1_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8768])) +#define MCF_PSC1_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x876E])) +#define MCF_PSC1_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8772])) +#define MCF_PSC1_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8776])) +#define MCF_PSC1_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x877A])) +#define MCF_PSC1_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x877E])) +#define MCF_PSC1_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8780])) +#define MCF_PSC1_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8784])) +#define MCF_PSC1_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8788])) +#define MCF_PSC1_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x878E])) +#define MCF_PSC1_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8792])) +#define MCF_PSC1_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8796])) +#define MCF_PSC1_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x879A])) +#define MCF_PSC1_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x879E])) + +#define MCF_PSC2_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8800])) +#define MCF_PSC2_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8800])) +#define MCF_PSC2_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8804])) +#define MCF_PSC2_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8804])) +#define MCF_PSC2_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8808])) +#define MCF_PSC2_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8810])) +#define MCF_PSC2_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8810])) +#define MCF_PSC2_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8814])) +#define MCF_PSC2_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8814])) +#define MCF_PSC2_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8818])) +#define MCF_PSC2_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x881C])) +#define MCF_PSC2_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8834])) +#define MCF_PSC2_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8838])) +#define MCF_PSC2_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x883C])) +#define MCF_PSC2_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8840])) +#define MCF_PSC2_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8844])) +#define MCF_PSC2_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8848])) +#define MCF_PSC2_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x884C])) +#define MCF_PSC2_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8850])) +#define MCF_PSC2_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8854])) +#define MCF_PSC2_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8858])) +#define MCF_PSC2_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x885C])) +#define MCF_PSC2_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8860])) +#define MCF_PSC2_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8864])) +#define MCF_PSC2_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8868])) +#define MCF_PSC2_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x886E])) +#define MCF_PSC2_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8872])) +#define MCF_PSC2_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8876])) +#define MCF_PSC2_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x887A])) +#define MCF_PSC2_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x887E])) +#define MCF_PSC2_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8880])) +#define MCF_PSC2_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8884])) +#define MCF_PSC2_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8888])) +#define MCF_PSC2_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x888E])) +#define MCF_PSC2_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8892])) +#define MCF_PSC2_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8896])) +#define MCF_PSC2_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x889A])) +#define MCF_PSC2_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x889E])) + +#define MCF_PSC3_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8900])) +#define MCF_PSC3_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8900])) +#define MCF_PSC3_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8904])) +#define MCF_PSC3_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8904])) +#define MCF_PSC3_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8908])) +#define MCF_PSC3_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8910])) +#define MCF_PSC3_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8910])) +#define MCF_PSC3_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8914])) +#define MCF_PSC3_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8914])) +#define MCF_PSC3_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8918])) +#define MCF_PSC3_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x891C])) +#define MCF_PSC3_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8934])) +#define MCF_PSC3_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8938])) +#define MCF_PSC3_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x893C])) +#define MCF_PSC3_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8940])) +#define MCF_PSC3_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8944])) +#define MCF_PSC3_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8948])) +#define MCF_PSC3_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x894C])) +#define MCF_PSC3_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8950])) +#define MCF_PSC3_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8954])) +#define MCF_PSC3_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8958])) +#define MCF_PSC3_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x895C])) +#define MCF_PSC3_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8960])) +#define MCF_PSC3_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8964])) +#define MCF_PSC3_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8968])) +#define MCF_PSC3_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x896E])) +#define MCF_PSC3_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8972])) +#define MCF_PSC3_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8976])) +#define MCF_PSC3_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x897A])) +#define MCF_PSC3_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x897E])) +#define MCF_PSC3_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8980])) +#define MCF_PSC3_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8984])) +#define MCF_PSC3_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8988])) +#define MCF_PSC3_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x898E])) +#define MCF_PSC3_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8992])) +#define MCF_PSC3_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8996])) +#define MCF_PSC3_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x899A])) +#define MCF_PSC3_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x899E])) + +#define MCF_PSC_PSCMR(x) (*(volatile uint8_t *)(&_MBAR[0x8600 + ((x)*0x100)])) +#define MCF_PSC_PSCCSR(x) (*(volatile uint8_t *)(&_MBAR[0x8604 + ((x)*0x100)])) +#define MCF_PSC_PSCSR(x) (*(volatile uint16_t*)(&_MBAR[0x8604 + ((x)*0x100)])) +#define MCF_PSC_PSCCR(x) (*(volatile uint8_t *)(&_MBAR[0x8608 + ((x)*0x100)])) +#define MCF_PSC_PSCRB_8BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_8BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCRB_16BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_16BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCRB_AC97(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_AC97(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCIPCR(x) (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)])) +#define MCF_PSC_PSCACR(x) (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)])) +#define MCF_PSC_PSCIMR(x) (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)])) +#define MCF_PSC_PSCISR(x) (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)])) +#define MCF_PSC_PSCCTUR(x) (*(volatile uint8_t *)(&_MBAR[0x8618 + ((x)*0x100)])) +#define MCF_PSC_PSCCTLR(x) (*(volatile uint8_t *)(&_MBAR[0x861C + ((x)*0x100)])) +#define MCF_PSC_PSCIP(x) (*(volatile uint8_t *)(&_MBAR[0x8634 + ((x)*0x100)])) +#define MCF_PSC_PSCOPSET(x) (*(volatile uint8_t *)(&_MBAR[0x8638 + ((x)*0x100)])) +#define MCF_PSC_PSCOPRESET(x) (*(volatile uint8_t *)(&_MBAR[0x863C + ((x)*0x100)])) +#define MCF_PSC_PSCSICR(x) (*(volatile uint8_t *)(&_MBAR[0x8640 + ((x)*0x100)])) +#define MCF_PSC_PSCIRCR1(x) (*(volatile uint8_t *)(&_MBAR[0x8644 + ((x)*0x100)])) +#define MCF_PSC_PSCIRCR2(x) (*(volatile uint8_t *)(&_MBAR[0x8648 + ((x)*0x100)])) +#define MCF_PSC_PSCIRSDR(x) (*(volatile uint8_t *)(&_MBAR[0x864C + ((x)*0x100)])) +#define MCF_PSC_PSCIRMDR(x) (*(volatile uint8_t *)(&_MBAR[0x8650 + ((x)*0x100)])) +#define MCF_PSC_PSCIRFDR(x) (*(volatile uint8_t *)(&_MBAR[0x8654 + ((x)*0x100)])) +#define MCF_PSC_PSCRFCNT(x) (*(volatile uint16_t*)(&_MBAR[0x8658 + ((x)*0x100)])) +#define MCF_PSC_PSCTFCNT(x) (*(volatile uint16_t*)(&_MBAR[0x865C + ((x)*0x100)])) +#define MCF_PSC_PSCRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8660 + ((x)*0x100)])) +#define MCF_PSC_PSCRFSR(x) (*(volatile uint16_t*)(&_MBAR[0x8664 + ((x)*0x100)])) +#define MCF_PSC_PSCRFCR(x) (*(volatile uint32_t*)(&_MBAR[0x8668 + ((x)*0x100)])) +#define MCF_PSC_PSCRFAR(x) (*(volatile uint16_t*)(&_MBAR[0x866E + ((x)*0x100)])) +#define MCF_PSC_PSCRFRP(x) (*(volatile uint16_t*)(&_MBAR[0x8672 + ((x)*0x100)])) +#define MCF_PSC_PSCRFWP(x) (*(volatile uint16_t*)(&_MBAR[0x8676 + ((x)*0x100)])) +#define MCF_PSC_PSCRLRFP(x) (*(volatile uint16_t*)(&_MBAR[0x867A + ((x)*0x100)])) +#define MCF_PSC_PSCRLWFP(x) (*(volatile uint16_t*)(&_MBAR[0x867E + ((x)*0x100)])) +#define MCF_PSC_PSCTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8680 + ((x)*0x100)])) +#define MCF_PSC_PSCTFSR(x) (*(volatile uint16_t*)(&_MBAR[0x8684 + ((x)*0x100)])) +#define MCF_PSC_PSCTFCR(x) (*(volatile uint32_t*)(&_MBAR[0x8688 + ((x)*0x100)])) +#define MCF_PSC_PSCTFAR(x) (*(volatile uint16_t*)(&_MBAR[0x868E + ((x)*0x100)])) +#define MCF_PSC_PSCTFRP(x) (*(volatile uint16_t*)(&_MBAR[0x8692 + ((x)*0x100)])) +#define MCF_PSC_PSCTFWP(x) (*(volatile uint16_t*)(&_MBAR[0x8696 + ((x)*0x100)])) +#define MCF_PSC_PSCTLRFP(x) (*(volatile uint16_t*)(&_MBAR[0x869A + ((x)*0x100)])) +#define MCF_PSC_PSCTLWFP(x) (*(volatile uint16_t*)(&_MBAR[0x869E + ((x)*0x100)])) + +/* Bit definitions and macros for MCF_PSC_PSCMR */ +#define MCF_PSC_PSCMR_SB(x) (((x)&0xF)<<0) +#define MCF_PSC_PSCMR_TXCTS (0x10) +#define MCF_PSC_PSCMR_TXRTS (0x20) +#define MCF_PSC_PSCMR_CM(x) (((x)&0x3)<<0x6) +#define MCF_PSC_PSCMR_CM_NORMAL (0) +#define MCF_PSC_PSCMR_CM_ECHO (0x40) +#define MCF_PSC_PSCMR_CM_LOCAL_LOOP (0x80) +#define MCF_PSC_PSCMR_CM_REMOTE_LOOP (0xC0) +#define MCF_PSC_PSCMR_SB_STOP_BITS_1 (0x7) +#define MCF_PSC_PSCMR_SB_STOP_BITS_15 (0x8) +#define MCF_PSC_PSCMR_SB_STOP_BITS_2 (0xF) +#define MCF_PSC_PSCMR_PM_MULTI_ADDR (0x1C) +#define MCF_PSC_PSCMR_PM_MULTI_DATA (0x18) +#define MCF_PSC_PSCMR_PM_NONE (0x10) +#define MCF_PSC_PSCMR_PM_FORCE_HI (0xC) +#define MCF_PSC_PSCMR_PM_FORCE_LO (0x8) +#define MCF_PSC_PSCMR_PM_ODD (0x4) +#define MCF_PSC_PSCMR_PM_EVEN (0) +#define MCF_PSC_PSCMR_BC(x) (((x)&0x3)<<0) +#define MCF_PSC_PSCMR_BC_5 (0) +#define MCF_PSC_PSCMR_BC_6 (0x1) +#define MCF_PSC_PSCMR_BC_7 (0x2) +#define MCF_PSC_PSCMR_BC_8 (0x3) +#define MCF_PSC_PSCMR_PT (0x4) +#define MCF_PSC_PSCMR_PM(x) (((x)&0x3)<<0x3) +#define MCF_PSC_PSCMR_ERR (0x20) +#define MCF_PSC_PSCMR_RXIRQ_FU (0x40) +#define MCF_PSC_PSCMR_RXRTS (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCCSR */ +#define MCF_PSC_PSCCSR_TCSEL(x) (((x)&0xF)<<0) +#define MCF_PSC_PSCCSR_RCSEL(x) (((x)&0xF)<<0x4) +#define MCF_PSC_PSCCSR_TCSEL_SYS_CLK (0x0D) +#define MCF_PSC_PSCCSR_TCSEL_CTM16 (0x0E) +#define MCF_PSC_PSCCSR_TCSEL_CTM (0x0F) +#define MCF_PSC_PSCCSR_RCSEL_SYS_CLK (0xD0) +#define MCF_PSC_PSCCSR_RCSEL_CTM16 (0xE0) +#define MCF_PSC_PSCCSR_RCSEL_CTM (0xF0) + +/* Bit definitions and macros for MCF_PSC_PSCSR */ +#define MCF_PSC_PSCSR_ERR (0x40) +#define MCF_PSC_PSCSR_CDE_DEOF (0x80) +#define MCF_PSC_PSCSR_RXRDY (0x100) +#define MCF_PSC_PSCSR_FU (0x200) +#define MCF_PSC_PSCSR_TXRDY (0x400) +#define MCF_PSC_PSCSR_TXEMP_URERR (0x800) +#define MCF_PSC_PSCSR_OE (0x1000) +#define MCF_PSC_PSCSR_PE_CRCERR (0x2000) +#define MCF_PSC_PSCSR_FE_PHYERR (0x4000) +#define MCF_PSC_PSCSR_RB_NEOF (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCCR */ +#define MCF_PSC_PSCCR_RXC(x) (((x)&0x3)<<0) +#define MCF_PSC_PSCCR_RX_ENABLED (0x1) +#define MCF_PSC_PSCCR_RX_DISABLED (0x2) +#define MCF_PSC_PSCCR_TXC(x) (((x)&0x3)<<0x2) +#define MCF_PSC_PSCCR_TX_ENABLED (0x4) +#define MCF_PSC_PSCCR_TX_DISABLED (0x8) +#define MCF_PSC_PSCCR_MISC(x) (((x)&0x7)<<0x4) +#define MCF_PSC_PSCCR_NONE (0) +#define MCF_PSC_PSCCR_RESET_MR (0x10) +#define MCF_PSC_PSCCR_RESET_RX (0x20) +#define MCF_PSC_PSCCR_RESET_TX (0x30) +#define MCF_PSC_PSCCR_RESET_ERROR (0x40) +#define MCF_PSC_PSCCR_RESET_BKCHGINT (0x50) +#define MCF_PSC_PSCCR_START_BREAK (0x60) +#define MCF_PSC_PSCCR_STOP_BREAK (0x70) + +/* Bit definitions and macros for MCF_PSC_PSCRB_8BIT */ +#define MCF_PSC_PSCRB_8BIT_RB3(x) (((x)&0xFF)<<0) +#define MCF_PSC_PSCRB_8BIT_RB2(x) (((x)&0xFF)<<0x8) +#define MCF_PSC_PSCRB_8BIT_RB1(x) (((x)&0xFF)<<0x10) +#define MCF_PSC_PSCRB_8BIT_RB0(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PSC_PSCTB_8BIT */ +#define MCF_PSC_PSCTB_8BIT_TB3(x) (((x)&0xFF)<<0) +#define MCF_PSC_PSCTB_8BIT_TB2(x) (((x)&0xFF)<<0x8) +#define MCF_PSC_PSCTB_8BIT_TB1(x) (((x)&0xFF)<<0x10) +#define MCF_PSC_PSCTB_8BIT_TB0(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PSC_PSCRB_16BIT */ +#define MCF_PSC_PSCRB_16BIT_RB1(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCRB_16BIT_RB0(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PSC_PSCTB_16BIT */ +#define MCF_PSC_PSCTB_16BIT_TB1(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCTB_16BIT_TB0(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PSC_PSCRB_AC97 */ +#define MCF_PSC_PSCRB_AC97_SOF (0x800) +#define MCF_PSC_PSCRB_AC97_RB(x) (((x)&0xFFFFF)<<0xC) + +/* Bit definitions and macros for MCF_PSC_PSCTB_AC97 */ +#define MCF_PSC_PSCTB_AC97_TB(x) (((x)&0xFFFFF)<<0xC) + +/* Bit definitions and macros for MCF_PSC_PSCIPCR */ +#define MCF_PSC_PSCIPCR_RESERVED (0xC) +#define MCF_PSC_PSCIPCR_CTS (0xD) +#define MCF_PSC_PSCIPCR_D_CTS (0x1C) +#define MCF_PSC_PSCIPCR_SYNC (0x8C) + +/* Bit definitions and macros for MCF_PSC_PSCACR */ +#define MCF_PSC_PSCACR_IEC0 (0x1) + +/* Bit definitions and macros for MCF_PSC_PSCIMR */ +#define MCF_PSC_PSCIMR_ERR (0x40) +#define MCF_PSC_PSCIMR_DEOF (0x80) +#define MCF_PSC_PSCIMR_TXRDY (0x100) +#define MCF_PSC_PSCIMR_RXRDY_FU (0x200) +#define MCF_PSC_PSCIMR_DB (0x400) +#define MCF_PSC_PSCIMR_IPC (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCISR */ +#define MCF_PSC_PSCISR_ERR (0x40) +#define MCF_PSC_PSCISR_DEOF (0x80) +#define MCF_PSC_PSCISR_TXRDY (0x100) +#define MCF_PSC_PSCISR_RXRDY_FU (0x200) +#define MCF_PSC_PSCISR_DB (0x400) +#define MCF_PSC_PSCISR_IPC (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCCTUR */ +#define MCF_PSC_PSCCTUR_CT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCCTLR */ +#define MCF_PSC_PSCCTLR_CT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCIP */ +#define MCF_PSC_PSCIP_CTS (0x1) +#define MCF_PSC_PSCIP_TGL (0x40) +#define MCF_PSC_PSCIP_LPWR_B (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCOPSET */ +#define MCF_PSC_PSCOPSET_RTS (0x1) + +/* Bit definitions and macros for MCF_PSC_PSCOPRESET */ +#define MCF_PSC_PSCOPRESET_RTS (0x1) + +/* Bit definitions and macros for MCF_PSC_PSCSICR */ +#define MCF_PSC_PSCSICR_SIM(x) (((x)&0x7)<<0) +#define MCF_PSC_PSCSICR_SIM_UART (0) +#define MCF_PSC_PSCSICR_SIM_MODEM8 (0x1) +#define MCF_PSC_PSCSICR_SIM_MODEM16 (0x2) +#define MCF_PSC_PSCSICR_SIM_AC97 (0x3) +#define MCF_PSC_PSCSICR_SIM_SIR (0x4) +#define MCF_PSC_PSCSICR_SIM_MIR (0x5) +#define MCF_PSC_PSCSICR_SIM_FIR (0x6) +#define MCF_PSC_PSCSICR_SHDIR (0x10) +#define MCF_PSC_PSCSICR_DTS1 (0x20) +#define MCF_PSC_PSCSICR_AWR (0x40) +#define MCF_PSC_PSCSICR_ACRB (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCIRCR1 */ +#define MCF_PSC_PSCIRCR1_SPUL (0x1) +#define MCF_PSC_PSCIRCR1_SIPEN (0x2) +#define MCF_PSC_PSCIRCR1_FD (0x4) + +/* Bit definitions and macros for MCF_PSC_PSCIRCR2 */ +#define MCF_PSC_PSCIRCR2_NXTEOF (0x1) +#define MCF_PSC_PSCIRCR2_ABORT (0x2) +#define MCF_PSC_PSCIRCR2_SIPREQ (0x4) + +/* Bit definitions and macros for MCF_PSC_PSCIRSDR */ +#define MCF_PSC_PSCIRSDR_IRSTIM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCIRMDR */ +#define MCF_PSC_PSCIRMDR_M_FDIV(x) (((x)&0x7F)<<0) +#define MCF_PSC_PSCIRMDR_FREQ (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCIRFDR */ +#define MCF_PSC_PSCIRFDR_F_FDIV(x) (((x)&0xF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFCNT */ +#define MCF_PSC_PSCRFCNT_CNT(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFCNT */ +#define MCF_PSC_PSCTFCNT_CNT(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFDR */ +#define MCF_PSC_PSCRFDR_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFSR */ +#define MCF_PSC_PSCRFSR_EMT (0x1) +#define MCF_PSC_PSCRFSR_ALARM (0x2) +#define MCF_PSC_PSCRFSR_FU (0x4) +#define MCF_PSC_PSCRFSR_FRMRDY (0x8) +#define MCF_PSC_PSCRFSR_OF (0x10) +#define MCF_PSC_PSCRFSR_UF (0x20) +#define MCF_PSC_PSCRFSR_RXW (0x40) +#define MCF_PSC_PSCRFSR_FAE (0x80) +#define MCF_PSC_PSCRFSR_FRM(x) (((x)&0xF)<<0x8) +#define MCF_PSC_PSCRFSR_FRM_BYTE0 (0x800) +#define MCF_PSC_PSCRFSR_FRM_BYTE1 (0x400) +#define MCF_PSC_PSCRFSR_FRM_BYTE2 (0x200) +#define MCF_PSC_PSCRFSR_FRM_BYTE3 (0x100) +#define MCF_PSC_PSCRFSR_TAG(x) (((x)&0x3)<<0xC) +#define MCF_PSC_PSCRFSR_TXW (0x4000) +#define MCF_PSC_PSCRFSR_IP (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCRFCR */ +#define MCF_PSC_PSCRFCR_CNTR(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCRFCR_TXW_MSK (0x40000) +#define MCF_PSC_PSCRFCR_OF_MSK (0x80000) +#define MCF_PSC_PSCRFCR_UF_MSK (0x100000) +#define MCF_PSC_PSCRFCR_RXW_MSK (0x200000) +#define MCF_PSC_PSCRFCR_FAE_MSK (0x400000) +#define MCF_PSC_PSCRFCR_IP_MSK (0x800000) +#define MCF_PSC_PSCRFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PSC_PSCRFCR_FRMEN (0x8000000) +#define MCF_PSC_PSCRFCR_TIMER (0x10000000) + +/* Bit definitions and macros for MCF_PSC_PSCRFAR */ +#define MCF_PSC_PSCRFAR_ALARM(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFRP */ +#define MCF_PSC_PSCRFRP_READ(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFWP */ +#define MCF_PSC_PSCRFWP_WRITE(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRLRFP */ +#define MCF_PSC_PSCRLRFP_LRFP(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRLWFP */ +#define MCF_PSC_PSCRLWFP_LWFP(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFDR */ +#define MCF_PSC_PSCTFDR_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFSR */ +#define MCF_PSC_PSCTFSR_EMT (0x1) +#define MCF_PSC_PSCTFSR_ALARM (0x2) +#define MCF_PSC_PSCTFSR_FU (0x4) +#define MCF_PSC_PSCTFSR_FRMRDY (0x8) +#define MCF_PSC_PSCTFSR_OF (0x10) +#define MCF_PSC_PSCTFSR_UF (0x20) +#define MCF_PSC_PSCTFSR_RXW (0x40) +#define MCF_PSC_PSCTFSR_FAE (0x80) +#define MCF_PSC_PSCTFSR_FRM(x) (((x)&0xF)<<0x8) +#define MCF_PSC_PSCTFSR_FRM_BYTE0 (0x800) +#define MCF_PSC_PSCTFSR_FRM_BYTE1 (0x400) +#define MCF_PSC_PSCTFSR_FRM_BYTE2 (0x200) +#define MCF_PSC_PSCTFSR_FRM_BYTE3 (0x100) +#define MCF_PSC_PSCTFSR_TAG(x) (((x)&0x3)<<0xC) +#define MCF_PSC_PSCTFSR_TXW (0x4000) +#define MCF_PSC_PSCTFSR_IP (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCTFCR */ +#define MCF_PSC_PSCTFCR_CNTR(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCTFCR_TXW_MSK (0x40000) +#define MCF_PSC_PSCTFCR_OF_MSK (0x80000) +#define MCF_PSC_PSCTFCR_UF_MSK (0x100000) +#define MCF_PSC_PSCTFCR_RXW_MSK (0x200000) +#define MCF_PSC_PSCTFCR_FAE_MSK (0x400000) +#define MCF_PSC_PSCTFCR_IP_MSK (0x800000) +#define MCF_PSC_PSCTFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PSC_PSCTFCR_FRMEN (0x8000000) +#define MCF_PSC_PSCTFCR_TIMER (0x10000000) +#define MCF_PSC_PSCTFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PSC_PSCTFAR */ +#define MCF_PSC_PSCTFAR_ALARM(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFRP */ +#define MCF_PSC_PSCTFRP_READ(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFWP */ +#define MCF_PSC_PSCTFWP_WRITE(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTLRFP */ +#define MCF_PSC_PSCTLRFP_LRFP(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTLWFP */ +#define MCF_PSC_PSCTLWFP_LWFP(x) (((x)&0x1FF)<<0) + + +#endif /* __MCF5475_PSC_H__ */ diff --git a/tos/jtagwait/include/MCF5475_SDRAMC.h b/tos/jtagwait/include/MCF5475_SDRAMC.h new file mode 100644 index 0000000..6cdbd68 --- /dev/null +++ b/tos/jtagwait/include/MCF5475_SDRAMC.h @@ -0,0 +1,106 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SDRAMC_H__ +#define __MCF5475_SDRAMC_H__ + + +/********************************************************************* +* +* Synchronous DRAM Controller (SDRAMC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SDRAMC_SDRAMDS (*(volatile uint32_t*)(&_MBAR[0x4])) +#define MCF_SDRAMC_CS0CFG (*(volatile uint32_t*)(&_MBAR[0x20])) +#define MCF_SDRAMC_CS1CFG (*(volatile uint32_t*)(&_MBAR[0x24])) +#define MCF_SDRAMC_CS2CFG (*(volatile uint32_t*)(&_MBAR[0x28])) +#define MCF_SDRAMC_CS3CFG (*(volatile uint32_t*)(&_MBAR[0x2C])) +#define MCF_SDRAMC_SDMR (*(volatile uint32_t*)(&_MBAR[0x100])) +#define MCF_SDRAMC_SDCR (*(volatile uint32_t*)(&_MBAR[0x104])) +#define MCF_SDRAMC_SDCFG1 (*(volatile uint32_t*)(&_MBAR[0x108])) +#define MCF_SDRAMC_SDCFG2 (*(volatile uint32_t*)(&_MBAR[0x10C])) +#define MCF_SDRAMC_CSCFG(x) (*(volatile uint32_t*)(&_MBAR[0x20 + ((x)*0x4)])) + + +/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */ +#define MCF_SDRAMC_SDRAMDS_SB_D(x) (((x)&0x3)<<0) +#define MCF_SDRAMC_SDRAMDS_SB_S(x) (((x)&0x3)<<0x2) +#define MCF_SDRAMC_SDRAMDS_SB_A(x) (((x)&0x3)<<0x4) +#define MCF_SDRAMC_SDRAMDS_SB_C(x) (((x)&0x3)<<0x6) +#define MCF_SDRAMC_SDRAMDS_SB_E(x) (((x)&0x3)<<0x8) +#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA (0) +#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA (0x1) +#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA (0x2) +#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE (0x3) + +/* Bit definitions and macros for MCF_SDRAMC_CSCFG */ +#define MCF_SDRAMC_CSCFG_CSSZ(x) (((x)&0x1F)<<0) +#define MCF_SDRAMC_CSCFG_CSSZ_DISABLED (0) +#define MCF_SDRAMC_CSCFG_CSSZ_1MBYTE (0x13) +#define MCF_SDRAMC_CSCFG_CSSZ_2MBYTE (0x14) +#define MCF_SDRAMC_CSCFG_CSSZ_4MBYTE (0x15) +#define MCF_SDRAMC_CSCFG_CSSZ_8MBYTE (0x16) +#define MCF_SDRAMC_CSCFG_CSSZ_16MBYTE (0x17) +#define MCF_SDRAMC_CSCFG_CSSZ_32MBYTE (0x18) +#define MCF_SDRAMC_CSCFG_CSSZ_64MBYTE (0x19) +#define MCF_SDRAMC_CSCFG_CSSZ_128MBYTE (0x1A) +#define MCF_SDRAMC_CSCFG_CSSZ_256MBYTE (0x1B) +#define MCF_SDRAMC_CSCFG_CSSZ_512MBYTE (0x1C) +#define MCF_SDRAMC_CSCFG_CSSZ_1GBYTE (0x1D) +#define MCF_SDRAMC_CSCFG_CSSZ_2GBYTE (0x1E) +#define MCF_SDRAMC_CSCFG_CSSZ_4GBYTE (0x1F) +#define MCF_SDRAMC_CSCFG_CSBA(x) (((x)&0xFFF)<<0x14) +#define MCF_SDRAMC_CSCFG_BA(x) ((x)&0xFFF00000) + +/* Bit definitions and macros for MCF_SDRAMC_SDMR */ +#define MCF_SDRAMC_SDMR_CMD (0x10000) +#define MCF_SDRAMC_SDMR_AD(x) (((x)&0xFFF)<<0x12) +#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x3)<<0x1E) +#define MCF_SDRAMC_SDMR_BK_LMR (0) +#define MCF_SDRAMC_SDMR_BK_LEMR (0x40000000) + +/* Bit definitions and macros for MCF_SDRAMC_SDCR */ +#define MCF_SDRAMC_SDCR_IPALL (0x2) +#define MCF_SDRAMC_SDCR_IREF (0x4) +#define MCF_SDRAMC_SDCR_BUFF (0x10) +#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0xF)<<0x8) +#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x3F)<<0x10) +#define MCF_SDRAMC_SDCR_DRIVE (0x400000) +#define MCF_SDRAMC_SDCR_AP (0x800000) +#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x3)<<0x18) +#define MCF_SDRAMC_SDCR_REF (0x10000000) +#define MCF_SDRAMC_SDCR_DDR (0x20000000) +#define MCF_SDRAMC_SDCR_CKE (0x40000000) +#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) + +/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ +#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x7)<<0x4) +#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0xF)<<0x8) +#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x7)<<0xC) +#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x7)<<0x10) +#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0xF)<<0x14) +#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x7)<<0x18) +#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0xF)<<0x1C) + +/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */ +#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0xF)<<0x10) +#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0xF)<<0x14) +#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0xF)<<0x18) +#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0xF)<<0x1C) + + +#endif /* __MCF5475_SDRAMC_H__ */ diff --git a/tos/jtagwait/include/MCF5475_SEC.h b/tos/jtagwait/include/MCF5475_SEC.h new file mode 100644 index 0000000..8deff0b --- /dev/null +++ b/tos/jtagwait/include/MCF5475_SEC.h @@ -0,0 +1,398 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SEC_H__ +#define __MCF5475_SEC_H__ + + +/********************************************************************* +* +* Integrated Security Engine (SEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SEC_EUACRH (*(volatile uint32_t*)(&_MBAR[0x21000])) +#define MCF_SEC_EUACRL (*(volatile uint32_t*)(&_MBAR[0x21004])) +#define MCF_SEC_SIMRH (*(volatile uint32_t*)(&_MBAR[0x21008])) +#define MCF_SEC_SIMRL (*(volatile uint32_t*)(&_MBAR[0x2100C])) +#define MCF_SEC_SISRH (*(volatile uint32_t*)(&_MBAR[0x21010])) +#define MCF_SEC_SISRL (*(volatile uint32_t*)(&_MBAR[0x21014])) +#define MCF_SEC_SICRH (*(volatile uint32_t*)(&_MBAR[0x21018])) +#define MCF_SEC_SICRL (*(volatile uint32_t*)(&_MBAR[0x2101C])) +#define MCF_SEC_SIDR (*(volatile uint32_t*)(&_MBAR[0x21020])) +#define MCF_SEC_EUASRH (*(volatile uint32_t*)(&_MBAR[0x21028])) +#define MCF_SEC_EUASRL (*(volatile uint32_t*)(&_MBAR[0x2102C])) +#define MCF_SEC_SMCR (*(volatile uint32_t*)(&_MBAR[0x21030])) +#define MCF_SEC_MEAR (*(volatile uint32_t*)(&_MBAR[0x21038])) +#define MCF_SEC_CCCR0 (*(volatile uint32_t*)(&_MBAR[0x2200C])) +#define MCF_SEC_CCPSRH0 (*(volatile uint32_t*)(&_MBAR[0x22010])) +#define MCF_SEC_CCPSRL0 (*(volatile uint32_t*)(&_MBAR[0x22014])) +#define MCF_SEC_CDPR0 (*(volatile uint32_t*)(&_MBAR[0x22044])) +#define MCF_SEC_FR0 (*(volatile uint32_t*)(&_MBAR[0x2204C])) +#define MCF_SEC_CCCR1 (*(volatile uint32_t*)(&_MBAR[0x2300C])) +#define MCF_SEC_CCPSRH1 (*(volatile uint32_t*)(&_MBAR[0x23010])) +#define MCF_SEC_CCPSRL1 (*(volatile uint32_t*)(&_MBAR[0x23014])) +#define MCF_SEC_CDPR1 (*(volatile uint32_t*)(&_MBAR[0x23044])) +#define MCF_SEC_FR1 (*(volatile uint32_t*)(&_MBAR[0x2304C])) +#define MCF_SEC_AFRCR (*(volatile uint32_t*)(&_MBAR[0x28018])) +#define MCF_SEC_AFSR (*(volatile uint32_t*)(&_MBAR[0x28028])) +#define MCF_SEC_AFISR (*(volatile uint32_t*)(&_MBAR[0x28030])) +#define MCF_SEC_AFIMR (*(volatile uint32_t*)(&_MBAR[0x28038])) +#define MCF_SEC_DRCR (*(volatile uint32_t*)(&_MBAR[0x2A018])) +#define MCF_SEC_DSR (*(volatile uint32_t*)(&_MBAR[0x2A028])) +#define MCF_SEC_DISR (*(volatile uint32_t*)(&_MBAR[0x2A030])) +#define MCF_SEC_DIMR (*(volatile uint32_t*)(&_MBAR[0x2A038])) +#define MCF_SEC_MDRCR (*(volatile uint32_t*)(&_MBAR[0x2C018])) +#define MCF_SEC_MDSR (*(volatile uint32_t*)(&_MBAR[0x2C028])) +#define MCF_SEC_MDISR (*(volatile uint32_t*)(&_MBAR[0x2C030])) +#define MCF_SEC_MDIMR (*(volatile uint32_t*)(&_MBAR[0x2C038])) +#define MCF_SEC_RNGRCR (*(volatile uint32_t*)(&_MBAR[0x2E018])) +#define MCF_SEC_RNGSR (*(volatile uint32_t*)(&_MBAR[0x2E028])) +#define MCF_SEC_RNGISR (*(volatile uint32_t*)(&_MBAR[0x2E030])) +#define MCF_SEC_RNGIMR (*(volatile uint32_t*)(&_MBAR[0x2E038])) +#define MCF_SEC_AESRCR (*(volatile uint32_t*)(&_MBAR[0x32018])) +#define MCF_SEC_AESSR (*(volatile uint32_t*)(&_MBAR[0x32028])) +#define MCF_SEC_AESISR (*(volatile uint32_t*)(&_MBAR[0x32030])) +#define MCF_SEC_AESIMR (*(volatile uint32_t*)(&_MBAR[0x32038])) +#define MCF_SEC_CCCRn(x) (*(volatile uint32_t*)(&_MBAR[0x2200C + ((x)*0x1000)])) +#define MCF_SEC_CCPSRHn(x) (*(volatile uint32_t*)(&_MBAR[0x22010 + ((x)*0x1000)])) +#define MCF_SEC_CCPSRLn(x) (*(volatile uint32_t*)(&_MBAR[0x22014 + ((x)*0x1000)])) +#define MCF_SEC_CDPRn(x) (*(volatile uint32_t*)(&_MBAR[0x22044 + ((x)*0x1000)])) +#define MCF_SEC_FRn(x) (*(volatile uint32_t*)(&_MBAR[0x2204C + ((x)*0x1000)])) + + +/* Bit definitions and macros for MCF_SEC_EUACRH */ +#define MCF_SEC_EUACRH_AFEU(x) (((x)&0xF)<<0) +#define MCF_SEC_EUACRH_AFFEU_NOASSIGN (0) +#define MCF_SEC_EUACRH_AFFEU_CHA0 (0x1) +#define MCF_SEC_EUACRH_AFFEU_CHA1 (0x2) +#define MCF_SEC_EUACRH_MDEU(x) (((x)&0xF)<<0x8) +#define MCF_SEC_EUACRH_MDEU_NOASSIGN (0) +#define MCF_SEC_EUACRH_MDEU_CHA0 (0x100) +#define MCF_SEC_EUACRH_MDEU_CHA1 (0x200) +#define MCF_SEC_EUACRH_RNG(x) (((x)&0xF)<<0x18) +#define MCF_SEC_EUACRH_RNG_NOASSIGN (0) +#define MCF_SEC_EUACRH_RNG_CHA0 (0x1000000) +#define MCF_SEC_EUACRH_RNG_CHA1 (0x2000000) + +/* Bit definitions and macros for MCF_SEC_EUACRL */ +#define MCF_SEC_EUACRL_AESU(x) (((x)&0xF)<<0x10) +#define MCF_SEC_EUACRL_AESU_NOASSIGN (0) +#define MCF_SEC_EUACRL_AESU_CHA0 (0x10000) +#define MCF_SEC_EUACRL_AESU_CHA1 (0x20000) +#define MCF_SEC_EUACRL_DEU(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SEC_SIMRH */ +#define MCF_SEC_SIMRH_AERR (0x8000000) +#define MCF_SEC_SIMRH_CHA_0_DN (0x10000000) +#define MCF_SEC_SIMRH_CHA_0_ERR (0x20000000) +#define MCF_SEC_SIMRH_CHA_1_DN (0x40000000) +#define MCF_SEC_SIMRH_CHA_1_ERR (0x80000000) + +/* Bit definitions and macros for MCF_SEC_SIMRL */ +#define MCF_SEC_SIMRL_TEA (0x40) +#define MCF_SEC_SIMRL_DEU_DN (0x100) +#define MCF_SEC_SIMRL_DEU_ERR (0x200) +#define MCF_SEC_SIMRL_AESU_DN (0x1000) +#define MCF_SEC_SIMRL_AESU_ERR (0x2000) +#define MCF_SEC_SIMRL_MDEU_DN (0x10000) +#define MCF_SEC_SIMRL_MDEU_ERR (0x20000) +#define MCF_SEC_SIMRL_AFEU_DN (0x100000) +#define MCF_SEC_SIMRL_AFEU_ERR (0x200000) +#define MCF_SEC_SIMRL_RNG_DN (0x1000000) +#define MCF_SEC_SIMRL_RNG_ERR (0x2000000) + +/* Bit definitions and macros for MCF_SEC_SISRH */ +#define MCF_SEC_SISRH_AERR (0x8000000) +#define MCF_SEC_SISRH_CHA_0_DN (0x10000000) +#define MCF_SEC_SISRH_CHA_0_ERR (0x20000000) +#define MCF_SEC_SISRH_CHA_1_DN (0x40000000) +#define MCF_SEC_SISRH_CHA_1_ERR (0x80000000) + +/* Bit definitions and macros for MCF_SEC_SISRL */ +#define MCF_SEC_SISRL_TEA (0x40) +#define MCF_SEC_SISRL_DEU_DN (0x100) +#define MCF_SEC_SISRL_DEU_ERR (0x200) +#define MCF_SEC_SISRL_AESU_DN (0x1000) +#define MCF_SEC_SISRL_AESU_ERR (0x2000) +#define MCF_SEC_SISRL_MDEU_DN (0x10000) +#define MCF_SEC_SISRL_MDEU_ERR (0x20000) +#define MCF_SEC_SISRL_AFEU_DN (0x100000) +#define MCF_SEC_SISRL_AFEU_ERR (0x200000) +#define MCF_SEC_SISRL_RNG_DN (0x1000000) +#define MCF_SEC_SISRL_RNG_ERR (0x2000000) + +/* Bit definitions and macros for MCF_SEC_SICRH */ +#define MCF_SEC_SICRH_AERR (0x8000000) +#define MCF_SEC_SICRH_CHA_0_DN (0x10000000) +#define MCF_SEC_SICRH_CHA_0_ERR (0x20000000) +#define MCF_SEC_SICRH_CHA_1_DN (0x40000000) +#define MCF_SEC_SICRH_CHA_1_ERR (0x80000000) + +/* Bit definitions and macros for MCF_SEC_SICRL */ +#define MCF_SEC_SICRL_TEA (0x40) +#define MCF_SEC_SICRL_DEU_DN (0x100) +#define MCF_SEC_SICRL_DEU_ERR (0x200) +#define MCF_SEC_SICRL_AESU_DN (0x1000) +#define MCF_SEC_SICRL_AESU_ERR (0x2000) +#define MCF_SEC_SICRL_MDEU_DN (0x10000) +#define MCF_SEC_SICRL_MDEU_ERR (0x20000) +#define MCF_SEC_SICRL_AFEU_DN (0x100000) +#define MCF_SEC_SICRL_AFEU_ERR (0x200000) +#define MCF_SEC_SICRL_RNG_DN (0x1000000) +#define MCF_SEC_SICRL_RNG_ERR (0x2000000) + +/* Bit definitions and macros for MCF_SEC_SIDR */ +#define MCF_SEC_SIDR_VERSION(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_EUASRH */ +#define MCF_SEC_EUASRH_AFEU(x) (((x)&0xF)<<0) +#define MCF_SEC_EUASRH_MDEU(x) (((x)&0xF)<<0x8) +#define MCF_SEC_EUASRH_RNG(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SEC_EUASRL */ +#define MCF_SEC_EUASRL_AESU(x) (((x)&0xF)<<0x10) +#define MCF_SEC_EUASRL_DEU(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SEC_SMCR */ +#define MCF_SEC_SMCR_CURR_CHAN(x) (((x)&0xF)<<0x4) +#define MCF_SEC_SMCR_CURR_CHAN_1 (0x10) +#define MCF_SEC_SMCR_CURR_CHAN_2 (0x20) +#define MCF_SEC_SMCR_SWR (0x1000000) + +/* Bit definitions and macros for MCF_SEC_MEAR */ +#define MCF_SEC_MEAR_ADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_CCCRn */ +#define MCF_SEC_CCCRn_RST (0x1) +#define MCF_SEC_CCCRn_CDIE (0x2) +#define MCF_SEC_CCCRn_NT (0x4) +#define MCF_SEC_CCCRn_NE (0x8) +#define MCF_SEC_CCCRn_WE (0x10) +#define MCF_SEC_CCCRn_BURST_SIZE(x) (((x)&0x7)<<0x8) +#define MCF_SEC_CCCRn_BURST_SIZE_2 (0) +#define MCF_SEC_CCCRn_BURST_SIZE_8 (0x100) +#define MCF_SEC_CCCRn_BURST_SIZE_16 (0x200) +#define MCF_SEC_CCCRn_BURST_SIZE_24 (0x300) +#define MCF_SEC_CCCRn_BURST_SIZE_32 (0x400) +#define MCF_SEC_CCCRn_BURST_SIZE_40 (0x500) +#define MCF_SEC_CCCRn_BURST_SIZE_48 (0x600) +#define MCF_SEC_CCCRn_BURST_SIZE_56 (0x700) + +/* Bit definitions and macros for MCF_SEC_CCPSRHn */ +#define MCF_SEC_CCPSRHn_STATE(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_SEC_CCPSRLn */ +#define MCF_SEC_CCPSRLn_PAIR_PTR(x) (((x)&0xFF)<<0) +#define MCF_SEC_CCPSRLn_EUERR (0x100) +#define MCF_SEC_CCPSRLn_SERR (0x200) +#define MCF_SEC_CCPSRLn_DERR (0x400) +#define MCF_SEC_CCPSRLn_PERR (0x1000) +#define MCF_SEC_CCPSRLn_TEA (0x2000) +#define MCF_SEC_CCPSRLn_SD (0x10000) +#define MCF_SEC_CCPSRLn_PD (0x20000) +#define MCF_SEC_CCPSRLn_SRD (0x40000) +#define MCF_SEC_CCPSRLn_PRD (0x80000) +#define MCF_SEC_CCPSRLn_SG (0x100000) +#define MCF_SEC_CCPSRLn_PG (0x200000) +#define MCF_SEC_CCPSRLn_SR (0x400000) +#define MCF_SEC_CCPSRLn_PR (0x800000) +#define MCF_SEC_CCPSRLn_MO (0x1000000) +#define MCF_SEC_CCPSRLn_MI (0x2000000) +#define MCF_SEC_CCPSRLn_STAT (0x4000000) + +/* Bit definitions and macros for MCF_SEC_CDPRn */ +#define MCF_SEC_CDPRn_CDP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_FRn */ +#define MCF_SEC_FRn_FETCH_ADDR(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_AFRCR */ +#define MCF_SEC_AFRCR_SR (0x1000000) +#define MCF_SEC_AFRCR_MI (0x2000000) +#define MCF_SEC_AFRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_AFSR */ +#define MCF_SEC_AFSR_RD (0x1000000) +#define MCF_SEC_AFSR_ID (0x2000000) +#define MCF_SEC_AFSR_IE (0x4000000) +#define MCF_SEC_AFSR_OFR (0x8000000) +#define MCF_SEC_AFSR_IFW (0x10000000) +#define MCF_SEC_AFSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_AFISR */ +#define MCF_SEC_AFISR_DSE (0x10000) +#define MCF_SEC_AFISR_KSE (0x20000) +#define MCF_SEC_AFISR_CE (0x40000) +#define MCF_SEC_AFISR_ERE (0x80000) +#define MCF_SEC_AFISR_IE (0x100000) +#define MCF_SEC_AFISR_OFU (0x2000000) +#define MCF_SEC_AFISR_IFO (0x4000000) +#define MCF_SEC_AFISR_IFE (0x10000000) +#define MCF_SEC_AFISR_OFE (0x20000000) +#define MCF_SEC_AFISR_AE (0x40000000) +#define MCF_SEC_AFISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_AFIMR */ +#define MCF_SEC_AFIMR_DSE (0x10000) +#define MCF_SEC_AFIMR_KSE (0x20000) +#define MCF_SEC_AFIMR_CE (0x40000) +#define MCF_SEC_AFIMR_ERE (0x80000) +#define MCF_SEC_AFIMR_IE (0x100000) +#define MCF_SEC_AFIMR_OFU (0x2000000) +#define MCF_SEC_AFIMR_IFO (0x4000000) +#define MCF_SEC_AFIMR_IFE (0x10000000) +#define MCF_SEC_AFIMR_OFE (0x20000000) +#define MCF_SEC_AFIMR_AE (0x40000000) +#define MCF_SEC_AFIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_DRCR */ +#define MCF_SEC_DRCR_SR (0x1000000) +#define MCF_SEC_DRCR_MI (0x2000000) +#define MCF_SEC_DRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_DSR */ +#define MCF_SEC_DSR_RD (0x1000000) +#define MCF_SEC_DSR_ID (0x2000000) +#define MCF_SEC_DSR_IE (0x4000000) +#define MCF_SEC_DSR_OFR (0x8000000) +#define MCF_SEC_DSR_IFW (0x10000000) +#define MCF_SEC_DSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_DISR */ +#define MCF_SEC_DISR_DSE (0x10000) +#define MCF_SEC_DISR_KSE (0x20000) +#define MCF_SEC_DISR_CE (0x40000) +#define MCF_SEC_DISR_ERE (0x80000) +#define MCF_SEC_DISR_IE (0x100000) +#define MCF_SEC_DISR_KPE (0x200000) +#define MCF_SEC_DISR_OFU (0x2000000) +#define MCF_SEC_DISR_IFO (0x4000000) +#define MCF_SEC_DISR_IFE (0x10000000) +#define MCF_SEC_DISR_OFE (0x20000000) +#define MCF_SEC_DISR_AE (0x40000000) +#define MCF_SEC_DISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_DIMR */ +#define MCF_SEC_DIMR_DSE (0x10000) +#define MCF_SEC_DIMR_KSE (0x20000) +#define MCF_SEC_DIMR_CE (0x40000) +#define MCF_SEC_DIMR_ERE (0x80000) +#define MCF_SEC_DIMR_IE (0x100000) +#define MCF_SEC_DIMR_KPE (0x200000) +#define MCF_SEC_DIMR_OFU (0x2000000) +#define MCF_SEC_DIMR_IFO (0x4000000) +#define MCF_SEC_DIMR_IFE (0x10000000) +#define MCF_SEC_DIMR_OFE (0x20000000) +#define MCF_SEC_DIMR_AE (0x40000000) +#define MCF_SEC_DIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_MDRCR */ +#define MCF_SEC_MDRCR_SR (0x1000000) +#define MCF_SEC_MDRCR_MI (0x2000000) +#define MCF_SEC_MDRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_MDSR */ +#define MCF_SEC_MDSR_RD (0x1000000) +#define MCF_SEC_MDSR_ID (0x2000000) +#define MCF_SEC_MDSR_IE (0x4000000) +#define MCF_SEC_MDSR_IFW (0x10000000) +#define MCF_SEC_MDSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_MDISR */ +#define MCF_SEC_MDISR_DSE (0x10000) +#define MCF_SEC_MDISR_KSE (0x20000) +#define MCF_SEC_MDISR_CE (0x40000) +#define MCF_SEC_MDISR_ERE (0x80000) +#define MCF_SEC_MDISR_IE (0x100000) +#define MCF_SEC_MDISR_IFO (0x4000000) +#define MCF_SEC_MDISR_AE (0x40000000) +#define MCF_SEC_MDISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_MDIMR */ +#define MCF_SEC_MDIMR_DSE (0x10000) +#define MCF_SEC_MDIMR_KSE (0x20000) +#define MCF_SEC_MDIMR_CE (0x40000) +#define MCF_SEC_MDIMR_ERE (0x80000) +#define MCF_SEC_MDIMR_IE (0x100000) +#define MCF_SEC_MDIMR_IFO (0x4000000) +#define MCF_SEC_MDIMR_AE (0x40000000) +#define MCF_SEC_MDIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_RNGRCR */ +#define MCF_SEC_RNGRCR_SR (0x1000000) +#define MCF_SEC_RNGRCR_MI (0x2000000) +#define MCF_SEC_RNGRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_RNGSR */ +#define MCF_SEC_RNGSR_RD (0x1000000) +#define MCF_SEC_RNGSR_IE (0x4000000) +#define MCF_SEC_RNGSR_OFR (0x8000000) +#define MCF_SEC_RNGSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_RNGISR */ +#define MCF_SEC_RNGISR_IE (0x100000) +#define MCF_SEC_RNGISR_OFU (0x2000000) +#define MCF_SEC_RNGISR_AE (0x40000000) +#define MCF_SEC_RNGISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_RNGIMR */ +#define MCF_SEC_RNGIMR_IE (0x100000) +#define MCF_SEC_RNGIMR_OFU (0x2000000) +#define MCF_SEC_RNGIMR_AE (0x40000000) +#define MCF_SEC_RNGIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_AESRCR */ +#define MCF_SEC_AESRCR_SR (0x1000000) +#define MCF_SEC_AESRCR_MI (0x2000000) +#define MCF_SEC_AESRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_AESSR */ +#define MCF_SEC_AESSR_RD (0x1000000) +#define MCF_SEC_AESSR_ID (0x2000000) +#define MCF_SEC_AESSR_IE (0x4000000) +#define MCF_SEC_AESSR_OFR (0x8000000) +#define MCF_SEC_AESSR_IFW (0x10000000) +#define MCF_SEC_AESSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_AESISR */ +#define MCF_SEC_AESISR_DSE (0x10000) +#define MCF_SEC_AESISR_KSE (0x20000) +#define MCF_SEC_AESISR_CE (0x40000) +#define MCF_SEC_AESISR_ERE (0x80000) +#define MCF_SEC_AESISR_IE (0x100000) +#define MCF_SEC_AESISR_OFU (0x2000000) +#define MCF_SEC_AESISR_IFO (0x4000000) +#define MCF_SEC_AESISR_IFE (0x10000000) +#define MCF_SEC_AESISR_OFE (0x20000000) +#define MCF_SEC_AESISR_AE (0x40000000) +#define MCF_SEC_AESISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_AESIMR */ +#define MCF_SEC_AESIMR_DSE (0x10000) +#define MCF_SEC_AESIMR_KSE (0x20000) +#define MCF_SEC_AESIMR_CE (0x40000) +#define MCF_SEC_AESIMR_ERE (0x80000) +#define MCF_SEC_AESIMR_IE (0x100000) +#define MCF_SEC_AESIMR_OFU (0x2000000) +#define MCF_SEC_AESIMR_IFO (0x4000000) +#define MCF_SEC_AESIMR_IFE (0x10000000) +#define MCF_SEC_AESIMR_OFE (0x20000000) +#define MCF_SEC_AESIMR_AE (0x40000000) +#define MCF_SEC_AESIMR_ME (0x80000000) + + +#endif /* __MCF5475_SEC_H__ */ diff --git a/tos/jtagwait/include/MCF5475_SIU.h b/tos/jtagwait/include/MCF5475_SIU.h new file mode 100644 index 0000000..efb2896 --- /dev/null +++ b/tos/jtagwait/include/MCF5475_SIU.h @@ -0,0 +1,67 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SIU_H__ +#define __MCF5475_SIU_H__ + + +/********************************************************************* +* +* System Integration Unit (SIU) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SIU_SBCR (*(volatile uint32_t*)(&_MBAR[0x10])) +#define MCF_SIU_SECSACR (*(volatile uint32_t*)(&_MBAR[0x38])) +#define MCF_SIU_RSR (*(volatile uint32_t*)(&_MBAR[0x44])) +#define MCF_SIU_JTAGID (*(volatile uint32_t*)(&_MBAR[0x50])) + + +/* Bit definitions and macros for MCF_SIU_SBCR */ +#define MCF_SIU_SBCR_PIN2DSPI (0x8000000) +#define MCF_SIU_SBCR_DMA2CPU (0x10000000) +#define MCF_SIU_SBCR_CPU2DMA (0x20000000) +#define MCF_SIU_SBCR_PIN2DMA (0x40000000) +#define MCF_SIU_SBCR_PIN2CPU (0x80000000) + +/* Bit definitions and macros for MCF_SIU_SECSACR */ +#define MCF_SIU_SECSACR_SEQEN (0x1) + +/* Bit definitions and macros for MCF_SIU_RSR */ +#define MCF_SIU_RSR_RST (0x1) +#define MCF_SIU_RSR_RSTWD (0x2) +#define MCF_SIU_RSR_RSTJTG (0x8) + +/* Bit definitions and macros for MCF_SIU_JTAGID */ +#define MCF_SIU_JTAGID_JTAGID(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SIU_JTAGID */ +#define MCF_SIU_JTAGID_REV (0xF0000000) +#define MCF_SIU_JTAGID_PROCESSOR (0x0FFFFFFF) +#define MCF_SIU_JTAGID_MCF5485 (0x0800C01D) +#define MCF_SIU_JTAGID_MCF5484 (0x0800D01D) +#define MCF_SIU_JTAGID_MCF5483 (0x0800E01D) +#define MCF_SIU_JTAGID_MCF5482 (0x0800F01D) +#define MCF_SIU_JTAGID_MCF5481 (0x0801001D) +#define MCF_SIU_JTAGID_MCF5480 (0x0801101D) +#define MCF_SIU_JTAGID_MCF5475 (0x0801201D) +#define MCF_SIU_JTAGID_MCF5474 (0x0801301D) +#define MCF_SIU_JTAGID_MCF5473 (0x0801401D) +#define MCF_SIU_JTAGID_MCF5472 (0x0801501D) +#define MCF_SIU_JTAGID_MCF5471 (0x0801601D) +#define MCF_SIU_JTAGID_MCF5470 (0x0801701D) + +#endif /* __MCF5475_SIU_H__ */ diff --git a/tos/jtagwait/include/MCF5475_SLT.h b/tos/jtagwait/include/MCF5475_SLT.h new file mode 100644 index 0000000..20e8558 --- /dev/null +++ b/tos/jtagwait/include/MCF5475_SLT.h @@ -0,0 +1,59 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SLT_H__ +#define __MCF5475_SLT_H__ + + +/********************************************************************* +* +* Slice Timers (SLT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SLT0_STCNT (*(volatile uint32_t*)(&_MBAR[0x900])) +#define MCF_SLT0_SCR (*(volatile uint32_t*)(&_MBAR[0x904])) +#define MCF_SLT0_SCNT (*(volatile uint32_t*)(&_MBAR[0x908])) +#define MCF_SLT0_SSR (*(volatile uint32_t*)(&_MBAR[0x90C])) + +#define MCF_SLT1_STCNT (*(volatile uint32_t*)(&_MBAR[0x910])) +#define MCF_SLT1_SCR (*(volatile uint32_t*)(&_MBAR[0x914])) +#define MCF_SLT1_SCNT (*(volatile uint32_t*)(&_MBAR[0x918])) +#define MCF_SLT1_SSR (*(volatile uint32_t*)(&_MBAR[0x91C])) + +#define MCF_SLT_STCNT(x) (*(volatile uint32_t*)(&_MBAR[0x900 + ((x)*0x10)])) +#define MCF_SLT_SCR(x) (*(volatile uint32_t*)(&_MBAR[0x904 + ((x)*0x10)])) +#define MCF_SLT_SCNT(x) (*(volatile int32_t*)(&_MBAR[0x908 + ((x)*0x10)])) +#define MCF_SLT_SSR(x) (*(volatile uint32_t*)(&_MBAR[0x90C + ((x)*0x10)])) + + +/* Bit definitions and macros for MCF_SLT_STCNT */ +#define MCF_SLT_STCNT_TC(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SLT_SCR */ +#define MCF_SLT_SCR_TEN (0x1000000) +#define MCF_SLT_SCR_IEN (0x2000000) +#define MCF_SLT_SCR_RUN (0x4000000) + +/* Bit definitions and macros for MCF_SLT_SCNT */ +#define MCF_SLT_SCNT_CNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SLT_SSR */ +#define MCF_SLT_SSR_ST (0x1000000) +#define MCF_SLT_SSR_BE (0x2000000) + + +#endif /* __MCF5475_SLT_H__ */ diff --git a/tos/jtagwait/include/MCF5475_SRAM.h b/tos/jtagwait/include/MCF5475_SRAM.h new file mode 100644 index 0000000..d111f13 --- /dev/null +++ b/tos/jtagwait/include/MCF5475_SRAM.h @@ -0,0 +1,62 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SRAM_H__ +#define __MCF5475_SRAM_H__ + + +/********************************************************************* +* +* System SRAM Module (SRAM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SRAM_SSCR (*(volatile uint32_t*)(&__MBAR[0x1FFC0])) +#define MCF_SRAM_TCCR (*(volatile uint32_t*)(&__MBAR[0x1FFC4])) +#define MCF_SRAM_TCCRDR (*(volatile uint32_t*)(&__MBAR[0x1FFC8])) +#define MCF_SRAM_TCCRDW (*(volatile uint32_t*)(&__MBAR[0x1FFCC])) +#define MCF_SRAM_TCCRSEC (*(volatile uint32_t*)(&__MBAR[0x1FFD0])) + + +/* Bit definitions and macros for MCF_SRAM_SSCR */ +#define MCF_SRAM_SSCR_INLV (0x10000) + +/* Bit definitions and macros for MCF_SRAM_TCCR */ +#define MCF_SRAM_TCCR_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCR_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCR_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCR_BANK3_TC(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SRAM_TCCRDR */ +#define MCF_SRAM_TCCRDR_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCRDR_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCRDR_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCRDR_BANK3_TC(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SRAM_TCCRDW */ +#define MCF_SRAM_TCCRDW_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCRDW_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCRDW_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCRDW_BANK3_TC(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SRAM_TCCRSEC */ +#define MCF_SRAM_TCCRSEC_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCRSEC_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCRSEC_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCRSEC_BANK3_TC(x) (((x)&0xF)<<0x18) + + +#endif /* __MCF5475_SRAM_H__ */ diff --git a/tos/jtagwait/include/MCF5475_USB.h b/tos/jtagwait/include/MCF5475_USB.h new file mode 100644 index 0000000..c60273c --- /dev/null +++ b/tos/jtagwait/include/MCF5475_USB.h @@ -0,0 +1,554 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_USB_H__ +#define __MCF5475_USB_H__ + + +/********************************************************************* +* +* Universal Serial Bus Interface (USB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_USB_USBAISR (*(volatile uint8_t *)(&__MBAR[0xB000])) +#define MCF_USB_USBAIMR (*(volatile uint8_t *)(&__MBAR[0xB001])) +#define MCF_USB_EPINFO (*(volatile uint8_t *)(&__MBAR[0xB003])) +#define MCF_USB_CFGR (*(volatile uint8_t *)(&__MBAR[0xB004])) +#define MCF_USB_CFGAR (*(volatile uint8_t *)(&__MBAR[0xB005])) +#define MCF_USB_SPEEDR (*(volatile uint8_t *)(&__MBAR[0xB006])) +#define MCF_USB_FRMNUMR (*(volatile uint16_t*)(&__MBAR[0xB00E])) +#define MCF_USB_EPTNR (*(volatile uint16_t*)(&__MBAR[0xB010])) +#define MCF_USB_IFUR (*(volatile uint16_t*)(&__MBAR[0xB014])) +#define MCF_USB_IFR0 (*(volatile uint16_t*)(&__MBAR[0xB040])) +#define MCF_USB_IFR1 (*(volatile uint16_t*)(&__MBAR[0xB042])) +#define MCF_USB_IFR2 (*(volatile uint16_t*)(&__MBAR[0xB044])) +#define MCF_USB_IFR3 (*(volatile uint16_t*)(&__MBAR[0xB046])) +#define MCF_USB_IFR4 (*(volatile uint16_t*)(&__MBAR[0xB048])) +#define MCF_USB_IFR5 (*(volatile uint16_t*)(&__MBAR[0xB04A])) +#define MCF_USB_IFR6 (*(volatile uint16_t*)(&__MBAR[0xB04C])) +#define MCF_USB_IFR7 (*(volatile uint16_t*)(&__MBAR[0xB04E])) +#define MCF_USB_IFR8 (*(volatile uint16_t*)(&__MBAR[0xB050])) +#define MCF_USB_IFR9 (*(volatile uint16_t*)(&__MBAR[0xB052])) +#define MCF_USB_IFR10 (*(volatile uint16_t*)(&__MBAR[0xB054])) +#define MCF_USB_IFR11 (*(volatile uint16_t*)(&__MBAR[0xB056])) +#define MCF_USB_IFR12 (*(volatile uint16_t*)(&__MBAR[0xB058])) +#define MCF_USB_IFR13 (*(volatile uint16_t*)(&__MBAR[0xB05A])) +#define MCF_USB_IFR14 (*(volatile uint16_t*)(&__MBAR[0xB05C])) +#define MCF_USB_IFR15 (*(volatile uint16_t*)(&__MBAR[0xB05E])) +#define MCF_USB_IFR16 (*(volatile uint16_t*)(&__MBAR[0xB060])) +#define MCF_USB_IFR17 (*(volatile uint16_t*)(&__MBAR[0xB062])) +#define MCF_USB_IFR18 (*(volatile uint16_t*)(&__MBAR[0xB064])) +#define MCF_USB_IFR19 (*(volatile uint16_t*)(&__MBAR[0xB066])) +#define MCF_USB_IFR20 (*(volatile uint16_t*)(&__MBAR[0xB068])) +#define MCF_USB_IFR21 (*(volatile uint16_t*)(&__MBAR[0xB06A])) +#define MCF_USB_IFR22 (*(volatile uint16_t*)(&__MBAR[0xB06C])) +#define MCF_USB_IFR23 (*(volatile uint16_t*)(&__MBAR[0xB06E])) +#define MCF_USB_IFR24 (*(volatile uint16_t*)(&__MBAR[0xB070])) +#define MCF_USB_IFR25 (*(volatile uint16_t*)(&__MBAR[0xB072])) +#define MCF_USB_IFR26 (*(volatile uint16_t*)(&__MBAR[0xB074])) +#define MCF_USB_IFR27 (*(volatile uint16_t*)(&__MBAR[0xB076])) +#define MCF_USB_IFR28 (*(volatile uint16_t*)(&__MBAR[0xB078])) +#define MCF_USB_IFR29 (*(volatile uint16_t*)(&__MBAR[0xB07A])) +#define MCF_USB_IFR30 (*(volatile uint16_t*)(&__MBAR[0xB07C])) +#define MCF_USB_IFR31 (*(volatile uint16_t*)(&__MBAR[0xB07E])) +#define MCF_USB_PPCNT (*(volatile uint16_t*)(&__MBAR[0xB080])) +#define MCF_USB_DPCNT (*(volatile uint16_t*)(&__MBAR[0xB082])) +#define MCF_USB_CRCECNT (*(volatile uint16_t*)(&__MBAR[0xB084])) +#define MCF_USB_BSECNT (*(volatile uint16_t*)(&__MBAR[0xB086])) +#define MCF_USB_PIDECNT (*(volatile uint16_t*)(&__MBAR[0xB088])) +#define MCF_USB_FRMECNT (*(volatile uint16_t*)(&__MBAR[0xB08A])) +#define MCF_USB_TXPCNT (*(volatile uint16_t*)(&__MBAR[0xB08C])) +#define MCF_USB_CNTOVR (*(volatile uint8_t *)(&__MBAR[0xB08E])) +#define MCF_USB_EP0ACR (*(volatile uint8_t *)(&__MBAR[0xB101])) +#define MCF_USB_EP0MPSR (*(volatile uint16_t*)(&__MBAR[0xB102])) +#define MCF_USB_EP0IFR (*(volatile uint8_t *)(&__MBAR[0xB104])) +#define MCF_USB_EP0SR (*(volatile uint8_t *)(&__MBAR[0xB105])) +#define MCF_USB_BMRTR (*(volatile uint8_t *)(&__MBAR[0xB106])) +#define MCF_USB_BRTR (*(volatile uint8_t *)(&__MBAR[0xB107])) +#define MCF_USB_WVALUER (*(volatile uint16_t*)(&__MBAR[0xB108])) +#define MCF_USB_WINDEXR (*(volatile uint16_t*)(&__MBAR[0xB10A])) +#define MCF_USB_WLENGTHR (*(volatile uint16_t*)(&__MBAR[0xB10C])) +#define MCF_USB_EP1OUTACR (*(volatile uint8_t *)(&__MBAR[0xB131])) +#define MCF_USB_EP1OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB132])) +#define MCF_USB_EP1OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB134])) +#define MCF_USB_EP1OUTSR (*(volatile uint8_t *)(&__MBAR[0xB135])) +#define MCF_USB_EP1OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB13E])) +#define MCF_USB_EP1INACR (*(volatile uint8_t *)(&__MBAR[0xB149])) +#define MCF_USB_EP1INMPSR (*(volatile uint16_t*)(&__MBAR[0xB14A])) +#define MCF_USB_EP1INIFR (*(volatile uint8_t *)(&__MBAR[0xB14C])) +#define MCF_USB_EP1INSR (*(volatile uint8_t *)(&__MBAR[0xB14D])) +#define MCF_USB_EP1INSFR (*(volatile uint16_t*)(&__MBAR[0xB156])) +#define MCF_USB_EP2OUTACR (*(volatile uint8_t *)(&__MBAR[0xB161])) +#define MCF_USB_EP2OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB162])) +#define MCF_USB_EP2OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB164])) +#define MCF_USB_EP2OUTSR (*(volatile uint8_t *)(&__MBAR[0xB165])) +#define MCF_USB_EP2OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB16E])) +#define MCF_USB_EP2INACR (*(volatile uint8_t *)(&__MBAR[0xB179])) +#define MCF_USB_EP2INMPSR (*(volatile uint16_t*)(&__MBAR[0xB17A])) +#define MCF_USB_EP2INIFR (*(volatile uint8_t *)(&__MBAR[0xB17C])) +#define MCF_USB_EP2INSR (*(volatile uint8_t *)(&__MBAR[0xB17D])) +#define MCF_USB_EP2INSFR (*(volatile uint16_t*)(&__MBAR[0xB186])) +#define MCF_USB_EP3OUTACR (*(volatile uint8_t *)(&__MBAR[0xB191])) +#define MCF_USB_EP3OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB192])) +#define MCF_USB_EP3OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB194])) +#define MCF_USB_EP3OUTSR (*(volatile uint8_t *)(&__MBAR[0xB195])) +#define MCF_USB_EP3OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB19E])) +#define MCF_USB_EP3INACR (*(volatile uint8_t *)(&__MBAR[0xB1A9])) +#define MCF_USB_EP3INMPSR (*(volatile uint16_t*)(&__MBAR[0xB1AA])) +#define MCF_USB_EP3INIFR (*(volatile uint8_t *)(&__MBAR[0xB1AC])) +#define MCF_USB_EP3INSR (*(volatile uint8_t *)(&__MBAR[0xB1AD])) +#define MCF_USB_EP3INSFR (*(volatile uint16_t*)(&__MBAR[0xB1B6])) +#define MCF_USB_EP4OUTACR (*(volatile uint8_t *)(&__MBAR[0xB1C1])) +#define MCF_USB_EP4OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB1C2])) +#define MCF_USB_EP4OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB1C4])) +#define MCF_USB_EP4OUTSR (*(volatile uint8_t *)(&__MBAR[0xB1C5])) +#define MCF_USB_EP4OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB1CE])) +#define MCF_USB_EP4INACR (*(volatile uint8_t *)(&__MBAR[0xB1D9])) +#define MCF_USB_EP4INMPSR (*(volatile uint16_t*)(&__MBAR[0xB1DA])) +#define MCF_USB_EP4INIFR (*(volatile uint8_t *)(&__MBAR[0xB1DC])) +#define MCF_USB_EP4INSR (*(volatile uint8_t *)(&__MBAR[0xB1DD])) +#define MCF_USB_EP4INSFR (*(volatile uint16_t*)(&__MBAR[0xB1E6])) +#define MCF_USB_EP5OUTACR (*(volatile uint8_t *)(&__MBAR[0xB1F1])) +#define MCF_USB_EP5OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB1F2])) +#define MCF_USB_EP5OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB1F4])) +#define MCF_USB_EP5OUTSR (*(volatile uint8_t *)(&__MBAR[0xB1F5])) +#define MCF_USB_EP5OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB1FE])) +#define MCF_USB_EP5INACR (*(volatile uint8_t *)(&__MBAR[0xB209])) +#define MCF_USB_EP5INMPSR (*(volatile uint16_t*)(&__MBAR[0xB20A])) +#define MCF_USB_EP5INIFR (*(volatile uint8_t *)(&__MBAR[0xB20C])) +#define MCF_USB_EP5INSR (*(volatile uint8_t *)(&__MBAR[0xB20D])) +#define MCF_USB_EP5INSFR (*(volatile uint16_t*)(&__MBAR[0xB216])) +#define MCF_USB_EP6OUTACR (*(volatile uint8_t *)(&__MBAR[0xB221])) +#define MCF_USB_EP6OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB222])) +#define MCF_USB_EP6OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB224])) +#define MCF_USB_EP6OUTSR (*(volatile uint8_t *)(&__MBAR[0xB225])) +#define MCF_USB_EP6OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB22E])) +#define MCF_USB_EP6INACR (*(volatile uint8_t *)(&__MBAR[0xB239])) +#define MCF_USB_EP6INMPSR (*(volatile uint16_t*)(&__MBAR[0xB23A])) +#define MCF_USB_EP6INIFR (*(volatile uint8_t *)(&__MBAR[0xB23C])) +#define MCF_USB_EP6INSR (*(volatile uint8_t *)(&__MBAR[0xB23D])) +#define MCF_USB_EP6INSFR (*(volatile uint16_t*)(&__MBAR[0xB246])) +#define MCF_USB_USBSR (*(volatile uint32_t*)(&__MBAR[0xB400])) +#define MCF_USB_USBCR (*(volatile uint32_t*)(&__MBAR[0xB404])) +#define MCF_USB_DRAMCR (*(volatile uint32_t*)(&__MBAR[0xB408])) +#define MCF_USB_DRAMDR (*(volatile uint32_t*)(&__MBAR[0xB40C])) +#define MCF_USB_USBISR (*(volatile uint32_t*)(&__MBAR[0xB410])) +#define MCF_USB_USBIMR (*(volatile uint32_t*)(&__MBAR[0xB414])) +#define MCF_USB_EP0STAT (*(volatile uint32_t*)(&__MBAR[0xB440])) +#define MCF_USB_EP0ISR (*(volatile uint32_t*)(&__MBAR[0xB444])) +#define MCF_USB_EP0IMR (*(volatile uint32_t*)(&__MBAR[0xB448])) +#define MCF_USB_EP0FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB44C])) +#define MCF_USB_EP0FDR (*(volatile uint32_t*)(&__MBAR[0xB450])) +#define MCF_USB_EP0FSR (*(volatile uint32_t*)(&__MBAR[0xB454])) +#define MCF_USB_EP0FCR (*(volatile uint32_t*)(&__MBAR[0xB458])) +#define MCF_USB_EP0FAR (*(volatile uint32_t*)(&__MBAR[0xB45C])) +#define MCF_USB_EP0FRP (*(volatile uint32_t*)(&__MBAR[0xB460])) +#define MCF_USB_EP0FWP (*(volatile uint32_t*)(&__MBAR[0xB464])) +#define MCF_USB_EP0LRFP (*(volatile uint32_t*)(&__MBAR[0xB468])) +#define MCF_USB_EP0LWFP (*(volatile uint32_t*)(&__MBAR[0xB46C])) +#define MCF_USB_EP1STAT (*(volatile uint32_t*)(&__MBAR[0xB470])) +#define MCF_USB_EP1ISR (*(volatile uint32_t*)(&__MBAR[0xB474])) +#define MCF_USB_EP1IMR (*(volatile uint32_t*)(&__MBAR[0xB478])) +#define MCF_USB_EP1FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB47C])) +#define MCF_USB_EP1FDR (*(volatile uint32_t*)(&__MBAR[0xB480])) +#define MCF_USB_EP1FSR (*(volatile uint32_t*)(&__MBAR[0xB484])) +#define MCF_USB_EP1FCR (*(volatile uint32_t*)(&__MBAR[0xB488])) +#define MCF_USB_EP1FAR (*(volatile uint32_t*)(&__MBAR[0xB48C])) +#define MCF_USB_EP1FRP (*(volatile uint32_t*)(&__MBAR[0xB490])) +#define MCF_USB_EP1FWP (*(volatile uint32_t*)(&__MBAR[0xB494])) +#define MCF_USB_EP1LRFP (*(volatile uint32_t*)(&__MBAR[0xB498])) +#define MCF_USB_EP1LWFP (*(volatile uint32_t*)(&__MBAR[0xB49C])) +#define MCF_USB_EP2STAT (*(volatile uint32_t*)(&__MBAR[0xB4A0])) +#define MCF_USB_EP2ISR (*(volatile uint32_t*)(&__MBAR[0xB4A4])) +#define MCF_USB_EP2IMR (*(volatile uint32_t*)(&__MBAR[0xB4A8])) +#define MCF_USB_EP2FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB4AC])) +#define MCF_USB_EP2FDR (*(volatile uint32_t*)(&__MBAR[0xB4B0])) +#define MCF_USB_EP2FSR (*(volatile uint32_t*)(&__MBAR[0xB4B4])) +#define MCF_USB_EP2FCR (*(volatile uint32_t*)(&__MBAR[0xB4B8])) +#define MCF_USB_EP2FAR (*(volatile uint32_t*)(&__MBAR[0xB4BC])) +#define MCF_USB_EP2FRP (*(volatile uint32_t*)(&__MBAR[0xB4C0])) +#define MCF_USB_EP2FWP (*(volatile uint32_t*)(&__MBAR[0xB4C4])) +#define MCF_USB_EP2LRFP (*(volatile uint32_t*)(&__MBAR[0xB4C8])) +#define MCF_USB_EP2LWFP (*(volatile uint32_t*)(&__MBAR[0xB4CC])) +#define MCF_USB_EP3STAT (*(volatile uint32_t*)(&__MBAR[0xB4D0])) +#define MCF_USB_EP3ISR (*(volatile uint32_t*)(&__MBAR[0xB4D4])) +#define MCF_USB_EP3IMR (*(volatile uint32_t*)(&__MBAR[0xB4D8])) +#define MCF_USB_EP3FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB4DC])) +#define MCF_USB_EP3FDR (*(volatile uint32_t*)(&__MBAR[0xB4E0])) +#define MCF_USB_EP3FSR (*(volatile uint32_t*)(&__MBAR[0xB4E4])) +#define MCF_USB_EP3FCR (*(volatile uint32_t*)(&__MBAR[0xB4E8])) +#define MCF_USB_EP3FAR (*(volatile uint32_t*)(&__MBAR[0xB4EC])) +#define MCF_USB_EP3FRP (*(volatile uint32_t*)(&__MBAR[0xB4F0])) +#define MCF_USB_EP3FWP (*(volatile uint32_t*)(&__MBAR[0xB4F4])) +#define MCF_USB_EP3LRFP (*(volatile uint32_t*)(&__MBAR[0xB4F8])) +#define MCF_USB_EP3LWFP (*(volatile uint32_t*)(&__MBAR[0xB4FC])) +#define MCF_USB_EP4STAT (*(volatile uint32_t*)(&__MBAR[0xB500])) +#define MCF_USB_EP4ISR (*(volatile uint32_t*)(&__MBAR[0xB504])) +#define MCF_USB_EP4IMR (*(volatile uint32_t*)(&__MBAR[0xB508])) +#define MCF_USB_EP4FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB50C])) +#define MCF_USB_EP4FDR (*(volatile uint32_t*)(&__MBAR[0xB510])) +#define MCF_USB_EP4FSR (*(volatile uint32_t*)(&__MBAR[0xB514])) +#define MCF_USB_EP4FCR (*(volatile uint32_t*)(&__MBAR[0xB518])) +#define MCF_USB_EP4FAR (*(volatile uint32_t*)(&__MBAR[0xB51C])) +#define MCF_USB_EP4FRP (*(volatile uint32_t*)(&__MBAR[0xB520])) +#define MCF_USB_EP4FWP (*(volatile uint32_t*)(&__MBAR[0xB524])) +#define MCF_USB_EP4LRFP (*(volatile uint32_t*)(&__MBAR[0xB528])) +#define MCF_USB_EP4LWFP (*(volatile uint32_t*)(&__MBAR[0xB52C])) +#define MCF_USB_EP5STAT (*(volatile uint32_t*)(&__MBAR[0xB530])) +#define MCF_USB_EP5ISR (*(volatile uint32_t*)(&__MBAR[0xB534])) +#define MCF_USB_EP5IMR (*(volatile uint32_t*)(&__MBAR[0xB538])) +#define MCF_USB_EP5FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB53C])) +#define MCF_USB_EP5FDR (*(volatile uint32_t*)(&__MBAR[0xB540])) +#define MCF_USB_EP5FSR (*(volatile uint32_t*)(&__MBAR[0xB544])) +#define MCF_USB_EP5FCR (*(volatile uint32_t*)(&__MBAR[0xB548])) +#define MCF_USB_EP5FAR (*(volatile uint32_t*)(&__MBAR[0xB54C])) +#define MCF_USB_EP5FRP (*(volatile uint32_t*)(&__MBAR[0xB550])) +#define MCF_USB_EP5FWP (*(volatile uint32_t*)(&__MBAR[0xB554])) +#define MCF_USB_EP5LRFP (*(volatile uint32_t*)(&__MBAR[0xB558])) +#define MCF_USB_EP5LWFP (*(volatile uint32_t*)(&__MBAR[0xB55C])) +#define MCF_USB_EP6STAT (*(volatile uint32_t*)(&__MBAR[0xB560])) +#define MCF_USB_EP6ISR (*(volatile uint32_t*)(&__MBAR[0xB564])) +#define MCF_USB_EP6IMR (*(volatile uint32_t*)(&__MBAR[0xB568])) +#define MCF_USB_EP6FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB56C])) +#define MCF_USB_EP6FDR (*(volatile uint32_t*)(&__MBAR[0xB570])) +#define MCF_USB_EP6FSR (*(volatile uint32_t*)(&__MBAR[0xB574])) +#define MCF_USB_EP6FCR (*(volatile uint32_t*)(&__MBAR[0xB578])) +#define MCF_USB_EP6FAR (*(volatile uint32_t*)(&__MBAR[0xB57C])) +#define MCF_USB_EP6FRP (*(volatile uint32_t*)(&__MBAR[0xB580])) +#define MCF_USB_EP6FWP (*(volatile uint32_t*)(&__MBAR[0xB584])) +#define MCF_USB_EP6LRFP (*(volatile uint32_t*)(&__MBAR[0xB588])) +#define MCF_USB_EP6LWFP (*(volatile uint32_t*)(&__MBAR[0xB58C])) +#define MCF_USB_IFR(x) (*(volatile uint16_t*)(&__MBAR[0xB040 + ((x)*0x2)])) +#define MCF_USB_EPOUTACR(x) (*(volatile uint8_t *)(&__MBAR[0xB131 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTMPSR(x) (*(volatile uint16_t*)(&__MBAR[0xB132 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTIFR(x) (*(volatile uint8_t *)(&__MBAR[0xB134 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTSR(x) (*(volatile uint8_t *)(&__MBAR[0xB135 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTSFR(x) (*(volatile uint16_t*)(&__MBAR[0xB13E + ((x-1)*0x30)])) +#define MCF_USB_EPINACR(x) (*(volatile uint8_t *)(&__MBAR[0xB149 + ((x-1)*0x30)])) +#define MCF_USB_EPINMPSR(x) (*(volatile uint16_t*)(&__MBAR[0xB14A + ((x-1)*0x30)])) +#define MCF_USB_EPINIFR(x) (*(volatile uint8_t *)(&__MBAR[0xB14C + ((x-1)*0x30)])) +#define MCF_USB_EPINSR(x) (*(volatile uint8_t *)(&__MBAR[0xB14D + ((x-1)*0x30)])) +#define MCF_USB_EPINSFR(x) (*(volatile uint16_t*)(&__MBAR[0xB156 + ((x-1)*0x30)])) +#define MCF_USB_EPSTAT(x) (*(volatile uint32_t*)(&__MBAR[0xB440 + ((x)*0x30)])) +#define MCF_USB_EPISR(x) (*(volatile uint32_t*)(&__MBAR[0xB444 + ((x)*0x30)])) +#define MCF_USB_EPIMR(x) (*(volatile uint32_t*)(&__MBAR[0xB448 + ((x)*0x30)])) +#define MCF_USB_EPFRCFGR(x) (*(volatile uint32_t*)(&__MBAR[0xB44C + ((x)*0x30)])) +#define MCF_USB_EPFDR(x) (*(volatile uint32_t*)(&__MBAR[0xB450 + ((x)*0x30)])) +#define MCF_USB_EPFSR(x) (*(volatile uint32_t*)(&__MBAR[0xB454 + ((x)*0x30)])) +#define MCF_USB_EPFCR(x) (*(volatile uint32_t*)(&__MBAR[0xB458 + ((x)*0x30)])) +#define MCF_USB_EPFAR(x) (*(volatile uint32_t*)(&__MBAR[0xB45C + ((x)*0x30)])) +#define MCF_USB_EPFRP(x) (*(volatile uint32_t*)(&__MBAR[0xB460 + ((x)*0x30)])) +#define MCF_USB_EPFWP(x) (*(volatile uint32_t*)(&__MBAR[0xB464 + ((x)*0x30)])) +#define MCF_USB_EPLRFP(x) (*(volatile uint32_t*)(&__MBAR[0xB468 + ((x)*0x30)])) +#define MCF_USB_EPLWFP(x) (*(volatile uint32_t*)(&__MBAR[0xB46C + ((x)*0x30)])) + + +/* Bit definitions and macros for MCF_USB_USBAISR */ +#define MCF_USB_USBAISR_SETUP (0x1) +#define MCF_USB_USBAISR_IN (0x2) +#define MCF_USB_USBAISR_OUT (0x4) +#define MCF_USB_USBAISR_EPHALT (0x8) +#define MCF_USB_USBAISR_TRANSERR (0x10) +#define MCF_USB_USBAISR_ACK (0x20) +#define MCF_USB_USBAISR_CTROVFL (0x40) +#define MCF_USB_USBAISR_EPSTALL (0x80) + +/* Bit definitions and macros for MCF_USB_USBAIMR */ +#define MCF_USB_USBAIMR_SETUPEN (0x1) +#define MCF_USB_USBAIMR_INEN (0x2) +#define MCF_USB_USBAIMR_OUTEN (0x4) +#define MCF_USB_USBAIMR_EPHALTEN (0x8) +#define MCF_USB_USBAIMR_TRANSERREN (0x10) +#define MCF_USB_USBAIMR_ACKEN (0x20) +#define MCF_USB_USBAIMR_CTROVFLEN (0x40) +#define MCF_USB_USBAIMR_EPSTALLEN (0x80) + +/* Bit definitions and macros for MCF_USB_EPINFO */ +#define MCF_USB_EPINFO_EPDIR (0x1) +#define MCF_USB_EPINFO_EPNUM(x) (((x)&0x7)<<0x1) + +/* Bit definitions and macros for MCF_USB_CFGR */ +#define MCF_USB_CFGR_Configuration_Value(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_CFGAR */ +#define MCF_USB_CFGAR_RESERVED (0xA0) +#define MCF_USB_CFGAR_RMTWKEUP (0xE0) + +/* Bit definitions and macros for MCF_USB_SPEEDR */ +#define MCF_USB_SPEEDR_SPEED(x) (((x)&0x3)<<0) + +/* Bit definitions and macros for MCF_USB_FRMNUMR */ +#define MCF_USB_FRMNUMR_FRMNUM(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPTNR */ +#define MCF_USB_EPTNR_EP1T(x) (((x)&0x3)<<0) +#define MCF_USB_EPTNR_EP2T(x) (((x)&0x3)<<0x2) +#define MCF_USB_EPTNR_EP3T(x) (((x)&0x3)<<0x4) +#define MCF_USB_EPTNR_EP4T(x) (((x)&0x3)<<0x6) +#define MCF_USB_EPTNR_EP5T(x) (((x)&0x3)<<0x8) +#define MCF_USB_EPTNR_EP6T(x) (((x)&0x3)<<0xA) +#define MCF_USB_EPTNR_EPnT1 (0) +#define MCF_USB_EPTNR_EPnT2 (0x1) +#define MCF_USB_EPTNR_EPnT3 (0x2) + +/* Bit definitions and macros for MCF_USB_IFUR */ +#define MCF_USB_IFUR_ALTSET(x) (((x)&0xFF)<<0) +#define MCF_USB_IFUR_IFNUM(x) (((x)&0xFF)<<0x8) + +/* Bit definitions and macros for MCF_USB_IFR */ +#define MCF_USB_IFR_ALTSET(x) (((x)&0xFF)<<0) +#define MCF_USB_IFR_IFNUM(x) (((x)&0xFF)<<0x8) + +/* Bit definitions and macros for MCF_USB_PPCNT */ +#define MCF_USB_PPCNT_PPCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_DPCNT */ +#define MCF_USB_DPCNT_DPCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_CRCECNT */ +#define MCF_USB_CRCECNT_CRCECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_BSECNT */ +#define MCF_USB_BSECNT_BSECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_PIDECNT */ +#define MCF_USB_PIDECNT_PIDECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_FRMECNT */ +#define MCF_USB_FRMECNT_FRMECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_TXPCNT */ +#define MCF_USB_TXPCNT_TXPCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_CNTOVR */ +#define MCF_USB_CNTOVR_PPCNT (0x1) +#define MCF_USB_CNTOVR_DPCNT (0x2) +#define MCF_USB_CNTOVR_CRCECNT (0x4) +#define MCF_USB_CNTOVR_BSECNT (0x8) +#define MCF_USB_CNTOVR_PIDECNT (0x10) +#define MCF_USB_CNTOVR_FRMECNT (0x20) +#define MCF_USB_CNTOVR_TXPCNT (0x40) + +/* Bit definitions and macros for MCF_USB_EP0ACR */ +#define MCF_USB_EP0ACR_TTYPE(x) (((x)&0x3)<<0) +#define MCF_USB_EP0ACR_TTYPE_CTRL (0) +#define MCF_USB_EP0ACR_TTYPE_ISOC (0x1) +#define MCF_USB_EP0ACR_TTYPE_BULK (0x2) +#define MCF_USB_EP0ACR_TTYPE_INT (0x3) + +/* Bit definitions and macros for MCF_USB_EP0MPSR */ +#define MCF_USB_EP0MPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0) +#define MCF_USB_EP0MPSR_ADDTRANS(x) (((x)&0x3)<<0xB) + +/* Bit definitions and macros for MCF_USB_EP0IFR */ +#define MCF_USB_EP0IFR_IFNUM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_EP0SR */ +#define MCF_USB_EP0SR_HALT (0x1) +#define MCF_USB_EP0SR_ACTIVE (0x2) +#define MCF_USB_EP0SR_PSTALL (0x4) +#define MCF_USB_EP0SR_CCOMP (0x8) +#define MCF_USB_EP0SR_TXZERO (0x20) +#define MCF_USB_EP0SR_INT (0x80) + +/* Bit definitions and macros for MCF_USB_BMRTR */ +#define MCF_USB_BMRTR_REC(x) (((x)&0x1F)<<0) +#define MCF_USB_BMRTR_REC_DEVICE (0) +#define MCF_USB_BMRTR_REC_INTERFACE (0x1) +#define MCF_USB_BMRTR_REC_ENDPOINT (0x2) +#define MCF_USB_BMRTR_REC_OTHER (0x3) +#define MCF_USB_BMRTR_TYPE(x) (((x)&0x3)<<0x5) +#define MCF_USB_BMRTR_TYPE_STANDARD (0) +#define MCF_USB_BMRTR_TYPE_CLASS (0x20) +#define MCF_USB_BMRTR_TYPE_VENDOR (0x40) +#define MCF_USB_BMRTR_DIR (0x80) + +/* Bit definitions and macros for MCF_USB_BRTR */ +#define MCF_USB_BRTR_BREQ(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_WVALUER */ +#define MCF_USB_WVALUER_WVALUE(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_WINDEXR */ +#define MCF_USB_WINDEXR_WINDEX(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_WLENGTHR */ +#define MCF_USB_WLENGTHR_WLENGTH(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPOUTACR */ +#define MCF_USB_EPOUTACR_TTYPE(x) (((x)&0x3)<<0) +#define MCF_USB_EPOUTACR_TTYPE_ISOC (0x1) +#define MCF_USB_EPOUTACR_TTYPE_BULK (0x2) +#define MCF_USB_EPOUTACR_TTYPE_INT (0x3) + +/* Bit definitions and macros for MCF_USB_EPOUTMPSR */ +#define MCF_USB_EPOUTMPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0) +#define MCF_USB_EPOUTMPSR_ADDTRANS(x) (((x)&0x3)<<0xB) + +/* Bit definitions and macros for MCF_USB_EPOUTIFR */ +#define MCF_USB_EPOUTIFR_IFNUM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPOUTSR */ +#define MCF_USB_EPOUTSR_HALT (0x1) +#define MCF_USB_EPOUTSR_ACTIVE (0x2) +#define MCF_USB_EPOUTSR_PSTALL (0x4) +#define MCF_USB_EPOUTSR_CCOMP (0x8) +#define MCF_USB_EPOUTSR_TXZERO (0x20) +#define MCF_USB_EPOUTSR_INT (0x80) + +/* Bit definitions and macros for MCF_USB_EPOUTSFR */ +#define MCF_USB_EPOUTSFR_FRMNUM(x) (((x)&0x7FF)<<0) + +/* Bit definitions and macros for MCF_USB_EPINACR */ +#define MCF_USB_EPINACR_TTYPE(x) (((x)&0x3)<<0) +#define MCF_USB_EPINACR_TTYPE_ISOC (0x1) +#define MCF_USB_EPINACR_TTYPE_BULK (0x2) +#define MCF_USB_EPINACR_TTYPE_INT (0x3) + +/* Bit definitions and macros for MCF_USB_EPINMPSR */ +#define MCF_USB_EPINMPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0) +#define MCF_USB_EPINMPSR_ADDTRANS(x) (((x)&0x3)<<0xB) + +/* Bit definitions and macros for MCF_USB_EPINIFR */ +#define MCF_USB_EPINIFR_IFNUM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPINSR */ +#define MCF_USB_EPINSR_HALT (0x1) +#define MCF_USB_EPINSR_ACTIVE (0x2) +#define MCF_USB_EPINSR_PSTALL (0x4) +#define MCF_USB_EPINSR_CCOMP (0x8) +#define MCF_USB_EPINSR_TXZERO (0x20) +#define MCF_USB_EPINSR_INT (0x80) + +/* Bit definitions and macros for MCF_USB_EPINSFR */ +#define MCF_USB_EPINSFR_FRMNUM(x) (((x)&0x7FF)<<0) + +/* Bit definitions and macros for MCF_USB_USBSR */ +#define MCF_USB_USBSR_ISOERREP(x) (((x)&0xF)<<0) +#define MCF_USB_USBSR_SUSP (0x80) + +/* Bit definitions and macros for MCF_USB_USBCR */ +#define MCF_USB_USBCR_RESUME (0x1) +#define MCF_USB_USBCR_APPLOCK (0x2) +#define MCF_USB_USBCR_RST (0x4) +#define MCF_USB_USBCR_RAMEN (0x8) +#define MCF_USB_USBCR_RAMSPLIT (0x20) + +/* Bit definitions and macros for MCF_USB_DRAMCR */ +#define MCF_USB_DRAMCR_DADR(x) (((x)&0x3FF)<<0) +#define MCF_USB_DRAMCR_DSIZE(x) (((x)&0x7FF)<<0x10) +#define MCF_USB_DRAMCR_BSY (0x40000000) +#define MCF_USB_DRAMCR_START (0x80000000) + +/* Bit definitions and macros for MCF_USB_DRAMDR */ +#define MCF_USB_DRAMDR_DDAT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_USBISR */ +#define MCF_USB_USBISR_ISOERR (0x1) +#define MCF_USB_USBISR_FTUNLCK (0x2) +#define MCF_USB_USBISR_SUSP (0x4) +#define MCF_USB_USBISR_RES (0x8) +#define MCF_USB_USBISR_UPDSOF (0x10) +#define MCF_USB_USBISR_RSTSTOP (0x20) +#define MCF_USB_USBISR_SOF (0x40) +#define MCF_USB_USBISR_MSOF (0x80) + +/* Bit definitions and macros for MCF_USB_USBIMR */ +#define MCF_USB_USBIMR_ISOERR (0x1) +#define MCF_USB_USBIMR_FTUNLCK (0x2) +#define MCF_USB_USBIMR_SUSP (0x4) +#define MCF_USB_USBIMR_RES (0x8) +#define MCF_USB_USBIMR_UPDSOF (0x10) +#define MCF_USB_USBIMR_RSTSTOP (0x20) +#define MCF_USB_USBIMR_SOF (0x40) +#define MCF_USB_USBIMR_MSOF (0x80) + +/* Bit definitions and macros for MCF_USB_EPSTAT */ +#define MCF_USB_EPSTAT_RST (0x1) +#define MCF_USB_EPSTAT_FLUSH (0x2) +#define MCF_USB_EPSTAT_DIR (0x80) +#define MCF_USB_EPSTAT_BYTECNT(x) (((x)&0xFFF)<<0x10) + +/* Bit definitions and macros for MCF_USB_EPISR */ +#define MCF_USB_EPISR_EOF (0x1) +#define MCF_USB_EPISR_EOT (0x4) +#define MCF_USB_EPISR_FIFOLO (0x10) +#define MCF_USB_EPISR_FIFOHI (0x20) +#define MCF_USB_EPISR_ERR (0x40) +#define MCF_USB_EPISR_EMT (0x80) +#define MCF_USB_EPISR_FU (0x100) + +/* Bit definitions and macros for MCF_USB_EPIMR */ +#define MCF_USB_EPIMR_EOF (0x1) +#define MCF_USB_EPIMR_EOT (0x4) +#define MCF_USB_EPIMR_FIFOLO (0x10) +#define MCF_USB_EPIMR_FIFOHI (0x20) +#define MCF_USB_EPIMR_ERR (0x40) +#define MCF_USB_EPIMR_EMT (0x80) +#define MCF_USB_EPIMR_FU (0x100) + +/* Bit definitions and macros for MCF_USB_EPFRCFGR */ +#define MCF_USB_EPFRCFGR_DEPTH(x) (((x)&0x1FFF)<<0) +#define MCF_USB_EPFRCFGR_BASE(x) (((x)&0xFFF)<<0x10) + +/* Bit definitions and macros for MCF_USB_EPFDR */ +#define MCF_USB_EPFDR_RX_TXDATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPFSR */ +#define MCF_USB_EPFSR_EMT (0x10000) +#define MCF_USB_EPFSR_ALRM (0x20000) +#define MCF_USB_EPFSR_FU (0x40000) +#define MCF_USB_EPFSR_FR (0x80000) +#define MCF_USB_EPFSR_OF (0x100000) +#define MCF_USB_EPFSR_UF (0x200000) +#define MCF_USB_EPFSR_RXW (0x400000) +#define MCF_USB_EPFSR_FAE (0x800000) +#define MCF_USB_EPFSR_FRM(x) (((x)&0xF)<<0x18) +#define MCF_USB_EPFSR_TXW (0x40000000) +#define MCF_USB_EPFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_USB_EPFCR */ +#define MCF_USB_EPFCR_COUNTER(x) (((x)&0xFFFF)<<0) +#define MCF_USB_EPFCR_TXWMSK (0x40000) +#define MCF_USB_EPFCR_OFMSK (0x80000) +#define MCF_USB_EPFCR_UFMSK (0x100000) +#define MCF_USB_EPFCR_RXWMSK (0x200000) +#define MCF_USB_EPFCR_FAEMSK (0x400000) +#define MCF_USB_EPFCR_IPMSK (0x800000) +#define MCF_USB_EPFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_USB_EPFCR_FRM (0x8000000) +#define MCF_USB_EPFCR_TMR (0x10000000) +#define MCF_USB_EPFCR_WFR (0x20000000) +#define MCF_USB_EPFCR_SHAD (0x80000000) + +/* Bit definitions and macros for MCF_USB_EPFAR */ +#define MCF_USB_EPFAR_ALRMP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPFRP */ +#define MCF_USB_EPFRP_RP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPFWP */ +#define MCF_USB_EPFWP_WP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPLRFP */ +#define MCF_USB_EPLRFP_LRFP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPLWFP */ +#define MCF_USB_EPLWFP_LWFP(x) (((x)&0xFFF)<<0) + + +#endif /* __MCF5475_USB_H__ */ diff --git a/tos/jtagwait/include/MCF5475_XLB.h b/tos/jtagwait/include/MCF5475_XLB.h new file mode 100644 index 0000000..af25ae7 --- /dev/null +++ b/tos/jtagwait/include/MCF5475_XLB.h @@ -0,0 +1,101 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_XLB_H__ +#define __MCF5475_XLB_H__ + + +/********************************************************************* +* +* XL Bus Arbiter (XLB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_XLB_XARB_CFG (*(volatile uint32_t*)(&_MBAR[0x240])) +#define MCF_XLB_XARB_VER (*(volatile uint32_t*)(&_MBAR[0x244])) +#define MCF_XLB_XARB_SR (*(volatile uint32_t*)(&_MBAR[0x248])) +#define MCF_XLB_XARB_IMR (*(volatile uint32_t*)(&_MBAR[0x24C])) +#define MCF_XLB_XARB_ADRCAP (*(volatile uint32_t*)(&_MBAR[0x250])) +#define MCF_XLB_XARB_SIGCAP (*(volatile uint32_t*)(&_MBAR[0x254])) +#define MCF_XLB_XARB_ADRTO (*(volatile uint32_t*)(&_MBAR[0x258])) +#define MCF_XLB_XARB_DATTO (*(volatile uint32_t*)(&_MBAR[0x25C])) +#define MCF_XLB_XARB_BUSTO (*(volatile uint32_t*)(&_MBAR[0x260])) +#define MCF_XLB_XARB_PRIEN (*(volatile uint32_t*)(&_MBAR[0x264])) +#define MCF_XLB_XARB_PRI (*(volatile uint32_t*)(&_MBAR[0x268])) + + +/* Bit definitions and macros for MCF_XLB_XARB_CFG */ +#define MCF_XLB_XARB_CFG_AT (0x2) +#define MCF_XLB_XARB_CFG_DT (0x4) +#define MCF_XLB_XARB_CFG_BA (0x8) +#define MCF_XLB_XARB_CFG_PM(x) (((x)&0x3)<<0x5) +#define MCF_XLB_XARB_CFG_SP(x) (((x)&0x7)<<0x8) +#define MCF_XLB_XARB_CFG_PLDIS (0x80000000) + +/* Bit definitions and macros for MCF_XLB_XARB_VER */ +#define MCF_XLB_XARB_VER_VER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_SR */ +#define MCF_XLB_XARB_SR_AT (0x1) +#define MCF_XLB_XARB_SR_DT (0x2) +#define MCF_XLB_XARB_SR_BA (0x4) +#define MCF_XLB_XARB_SR_TTM (0x8) +#define MCF_XLB_XARB_SR_ECW (0x10) +#define MCF_XLB_XARB_SR_TTR (0x20) +#define MCF_XLB_XARB_SR_TTA (0x40) +#define MCF_XLB_XARB_SR_MM (0x80) +#define MCF_XLB_XARB_SR_SEA (0x100) + +/* Bit definitions and macros for MCF_XLB_XARB_IMR */ +#define MCF_XLB_XARB_IMR_ATE (0x1) +#define MCF_XLB_XARB_IMR_DTE (0x2) +#define MCF_XLB_XARB_IMR_BAE (0x4) +#define MCF_XLB_XARB_IMR_TTME (0x8) +#define MCF_XLB_XARB_IMR_ECWE (0x10) +#define MCF_XLB_XARB_IMR_TTRE (0x20) +#define MCF_XLB_XARB_IMR_TTAE (0x40) +#define MCF_XLB_XARB_IMR_MME (0x80) +#define MCF_XLB_XARB_IMR_SEAE (0x100) + +/* Bit definitions and macros for MCF_XLB_XARB_ADRCAP */ +#define MCF_XLB_XARB_ADRCAP_ADRCAP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_SIGCAP */ +#define MCF_XLB_XARB_SIGCAP_TT(x) (((x)&0x1F)<<0) +#define MCF_XLB_XARB_SIGCAP_TBST (0x20) +#define MCF_XLB_XARB_SIGCAP_TSIZ(x) (((x)&0x7)<<0x7) + +/* Bit definitions and macros for MCF_XLB_XARB_ADRTO */ +#define MCF_XLB_XARB_ADRTO_ADRTO(x) (((x)&0xFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_DATTO */ +#define MCF_XLB_XARB_DATTO_DATTO(x) (((x)&0xFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_BUSTO */ +#define MCF_XLB_XARB_BUSTO_BUSTO(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_PRIEN */ +#define MCF_XLB_XARB_PRIEN_M0 (0x1) +#define MCF_XLB_XARB_PRIEN_M2 (0x4) +#define MCF_XLB_XARB_PRIEN_M3 (0x8) + +/* Bit definitions and macros for MCF_XLB_XARB_PRI */ +#define MCF_XLB_XARB_PRI_M0P(x) (((x)&0x7)<<0) +#define MCF_XLB_XARB_PRI_M2P(x) (((x)&0x7)<<0x8) +#define MCF_XLB_XARB_PRI_M3P(x) (((x)&0x7)<<0xC) + + +#endif /* __MCF5475_XLB_H__ */ diff --git a/tos/jtagwait/include/bas_printf.h b/tos/jtagwait/include/bas_printf.h new file mode 100644 index 0000000..5b42c28 --- /dev/null +++ b/tos/jtagwait/include/bas_printf.h @@ -0,0 +1,35 @@ +/* + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + */ + +#ifndef _BAS_PRINTF_H_ +#define _BAS_PRINTF_H_ +#include +#include + +extern void xvsnprintf(char *str, size_t size, const char *fmt, va_list va); +extern void xvprintf(const char *fmt, va_list va); +extern void xprintf(const char *fmt, ...); +extern void xsnprintf(char *str, size_t size, const char *fmt, ...); +extern void xputchar(int c); +extern int sprintf(char *str, const char *format, ...); + + +extern void display_progress(void); +extern void hexdump(uint8_t buffer[], int size); +#endif /* _BAS_PRINTF_H_ */ diff --git a/tos/jtagwait/include/bas_string.h b/tos/jtagwait/include/bas_string.h new file mode 100644 index 0000000..c743c95 --- /dev/null +++ b/tos/jtagwait/include/bas_string.h @@ -0,0 +1,47 @@ +/* + * bas_string.h + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 26.02.2013 + * Author: Markus Fröschle + */ + +#ifndef BAS_STRING_H_ +#define BAS_STRING_H_ + +#include + +extern int strncmp(const char *s1, const char *s2, size_t max); +extern char *strcpy(char *dst, const char *src); +char *strncpy(char *dst, const char *src, size_t max); +extern int strcmp(const char *s1, const char *s2); +extern size_t strlen(const char *str); +extern char *strcat(char *dst, const char *src); +extern char *strncat(char *dst, const char *src, size_t max); +extern int atoi(const char *c); +extern void *memcpy(void *dst, const void *src, size_t n); +extern void *memset(void *s, int c, size_t n); +extern int memcmp(const void *s1, const void *s2, size_t max); +extern void bzero(void *s, size_t n); + +#define isdigit(c) (((c) >= '0') && ((c) <= '9')) +#define isupper(c) ((c) >= 'A' && ((c) <= 'Z')) +#define islower(c) ((c) >= 'a' && ((c) <= 'z')) +#define isalpha(c) (isupper((c)) || islower(c)) +#define tolower(c) (isupper(c) ? ((c) + 'a' - 'A') : (c)) + +#endif /* BAS_STRING_H_ */ diff --git a/tos/jtagwait/include/driver_vec.h b/tos/jtagwait/include/driver_vec.h new file mode 100644 index 0000000..8b9352a --- /dev/null +++ b/tos/jtagwait/include/driver_vec.h @@ -0,0 +1,125 @@ +/* + * driver_vec.h + * + * Interface for exposure of BaS drivers to the OS + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 24.10.2013 + * Author: Markus Fröschle + */ + +#ifndef _DRIVER_VEC_H_ +#define _DRIVER_VEC_H_ + + +enum driver_type +{ + END_OF_DRIVERS, /* marks end of driver list */ + BLOCKDEV_DRIVER, + CHARDEV_DRIVER, + VIDEO_DRIVER, + XHDI_DRIVER, + MCD_DRIVER, +}; + +struct generic_driver_interface +{ + uint32_t (*init)(void); + uint32_t (*read)(void *buf, size_t count); + uint32_t (*write)(const void *buf, size_t count); + uint32_t (*ioctl)(uint32_t request, ...); +}; + + +/* Chained buffer descriptor */ +typedef volatile struct MCD_bufDesc_struct MCD_bufDesc; +struct MCD_bufDesc_struct { + uint32_t flags; /* flags describing the DMA */ + uint32_t csumResult; /* checksum from checksumming performed since last checksum reset */ + int8_t *srcAddr; /* the address to move data from */ + int8_t *destAddr; /* the address to move data to */ + int8_t *lastDestAddr; /* the last address written to */ + uint32_t dmaSize; /* the number of bytes to transfer independent of the transfer size */ + MCD_bufDesc *next; /* next buffer descriptor in chain */ + uint32_t info; /* private information about this descriptor; DMA does not affect it */ +}; + +/* Progress Query struct */ +typedef volatile struct MCD_XferProg_struct { + int8_t *lastSrcAddr; /* the most-recent or last, post-increment source address */ + int8_t *lastDestAddr; /* the most-recent or last, post-increment destination address */ + uint32_t dmaSize; /* the amount of data transferred for the current buffer */ + MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */ +} MCD_XferProg; + +struct dma_driver_interface +{ + int32_t version; + int32_t magic; + int32_t (*dma_set_initiator)(int initiator); + uint32_t (*dma_get_initiator)(int requestor); + void (*dma_free_initiator)(int requestor); + int32_t (*dma_set_channel)(int requestor, void (*handler)(void)); + int (*dma_get_channel)(int requestor); + void (*dma_free_channel)(int requestor); + void (*dma_clear_channel)(int channel); + int (*MCD_startDma)(int channel, int8_t *srcAddr, int16_t srcIncr, int8_t *destAddr, int16_t destIncr, + uint32_t dmaSize, uint32_t xferSize, uint32_t initiator, int32_t priority, uint32_t flags, + uint32_t funcDesc); + int (*MCD_dmaStatus)(int channel); + int (*MCD_XferProgrQuery)(int channel, MCD_XferProg *progRep); + int (*MCD_killDma)(int channel); + int (*MCD_continDma)(int channel); + int (*MCD_pauseDma)(int channel); + int (*MCD_resumeDma)(int channel); + int (*MCD_csumQuery)(int channel, uint32_t *csum); + void *(*dma_malloc)(long amount); + int (*dma_free)(void *addr); +}; + +struct xhdi_driver_interface +{ + uint32_t (*xhdivec)(); +}; + +union interface +{ + struct generic_driver_interface *gdi; + struct xhdi_driver_interface *xhdi; + struct dma_driver_interface *dma; +}; + +struct generic_interface +{ + enum driver_type type; + char name[16]; + char description[64]; + int version; + int revision; + union interface interface; +}; + +struct driver_table +{ + uint32_t bas_version; + uint32_t bas_revision; + uint32_t (*remove_handler)(); /* calling this will disable the BaS' hook into trap #0 */ + struct generic_interface *interfaces; +}; + + +#endif /* _DRIVER_VEC_H_ */ diff --git a/tos/jtagwait/jtagwait.config b/tos/jtagwait/jtagwait.config new file mode 100644 index 0000000..8cec188 --- /dev/null +++ b/tos/jtagwait/jtagwait.config @@ -0,0 +1 @@ +// ADD PREDEFINED MACROS HERE! diff --git a/tos/jtagwait/jtagwait.creator b/tos/jtagwait/jtagwait.creator new file mode 100644 index 0000000..e94cbbd --- /dev/null +++ b/tos/jtagwait/jtagwait.creator @@ -0,0 +1 @@ +[General] diff --git a/tos/jtagwait/jtagwait.creator.user b/tos/jtagwait/jtagwait.creator.user new file mode 100644 index 0000000..6304715 --- /dev/null +++ b/tos/jtagwait/jtagwait.creator.user @@ -0,0 +1,186 @@ + + + + + + ProjectExplorer.Project.ActiveTarget + 0 + + + ProjectExplorer.Project.EditorSettings + + true + false + true + + Cpp + + CppGlobal + + + + QmlJS + + QmlJSGlobal + + + 2 + UTF-8 + false + 4 + false + true + 1 + true + 0 + true + 0 + 8 + true + 1 + true + true + true + true + + + + ProjectExplorer.Project.PluginSettings + + + + ProjectExplorer.Project.Target.0 + + Desktop + Desktop + {8a828d48-5359-4872-acb6-81070c6b7c12} + 0 + 0 + 0 + + /home/mfro/Dokumente/Development/workspace/jtagwait + + + + all + + false + + + true + Make + + GenericProjectManager.GenericMakeStep + + 1 + Build + + ProjectExplorer.BuildSteps.Build + + + + + clean + + true + + + true + Make + + GenericProjectManager.GenericMakeStep + + 1 + Clean + + ProjectExplorer.BuildSteps.Clean + + 2 + false + + Default + Default + GenericProjectManager.GenericBuildConfiguration + + 1 + + + 0 + Deploy + + ProjectExplorer.BuildSteps.Deploy + + 1 + Deploy locally + + ProjectExplorer.DefaultDeployConfiguration + + 1 + + + + false + false + false + false + true + 0.01 + 10 + true + 1 + 25 + + 1 + true + false + true + valgrind + + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + + 2 + + + + false + %{buildDir} + Custom Executable + + ProjectExplorer.CustomExecutableRunConfiguration + 3768 + true + false + false + false + true + + 1 + + + + ProjectExplorer.Project.TargetCount + 1 + + + ProjectExplorer.Project.Updater.EnvironmentId + {d01d0a15-4efd-4fa2-8e2c-f26845794427} + + + ProjectExplorer.Project.Updater.FileVersion + 15 + + diff --git a/tos/jtagwait/jtagwait.files b/tos/jtagwait/jtagwait.files new file mode 100644 index 0000000..198470f --- /dev/null +++ b/tos/jtagwait/jtagwait.files @@ -0,0 +1,3 @@ +include/driver_vec.h +sources/jtagwait.c +Makefile diff --git a/tos/jtagwait/jtagwait.includes b/tos/jtagwait/jtagwait.includes new file mode 100644 index 0000000..2996fba --- /dev/null +++ b/tos/jtagwait/jtagwait.includes @@ -0,0 +1 @@ +include \ No newline at end of file diff --git a/tos/jtagwait/sources/bas_printf.c b/tos/jtagwait/sources/bas_printf.c new file mode 100644 index 0000000..ea87bdf --- /dev/null +++ b/tos/jtagwait/sources/bas_printf.c @@ -0,0 +1,460 @@ +/* + * tc.printf.c: A public-domain, minimal printf/sprintf routine that prints + * through the putchar() routine. Feel free to use for + * anything... -- 7/17/87 Paul Placeway + */ +/*- + * Copyright (c) 1980, 1991 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +#include "MCF5475.h" +#include "bas_printf.h" +#include "bas_string.h" + +/* + * Lexical definitions. + * + * All lexical space is allocated dynamically. + * The eighth/sixteenth bit of characters is used to prevent recognition, + * and eventually stripped. + */ +#define META 0200 +#define ASCII 0177 +#define QUOTE ((char) 0200) /* Eighth char bit used for 'ing */ +#define TRIM 0177 /* Mask to strip quote bit */ +#define UNDER 0000000 /* No extra bits to do both */ +#define BOLD 0000000 /* Bold flag */ +#define STANDOUT META /* Standout flag */ +#define LITERAL 0000000 /* Literal character flag */ +#define ATTRIBUTES 0200 /* The bits used for attributes */ +#define CHAR 0000177 /* Mask to mask out the character */ + +#define INF 32766 /* should be bigger than any field to print */ + +static char snil[] = "(nil)"; + +void xputchar(int c) +{ + __asm__ __volatile__ + ( + " .extern printf_helper\n\t" + " move.b %0,d0\n\t" + " bsr printf_helper\n\t" + /* output */: + /* input */: "r" (c) + /* clobber */: "d0","d2","a0","memory" + ); +} + +static void doprnt(void (*addchar)(int), const char *sfmt, va_list ap) +{ + char buf[128]; + char *bp; + const char *f; + float flt; + long l; + unsigned long u; + int i; + int fmt; + unsigned char pad = ' '; + int flush_left = 0; + int f_width = 0; + int prec = INF; + int hash = 0; + int do_long = 0; + int sign = 0; + int attributes = 0; + + f = sfmt; + for (; *f; f++) + { + if (*f != '%') + { + /* then just out the char */ + (*addchar)((int) (((unsigned char) *f) | attributes)); + } + else + { + f++; /* skip the % */ + + if (*f == '-') + { + /* minus: flush left */ + flush_left = 1; + f++; + } + + if (*f == '0' || *f == '.') + { + /* padding with 0 rather than blank */ + pad = '0'; + f++; + } + if (*f == '*') + { + /* field width */ + + f_width = va_arg(ap, int); + f++; + } + else if (isdigit((unsigned char) *f)) + { + f_width = atoi(f); + while (isdigit((unsigned char) *f)) + f++; /* skip the digits */ + } + + if (*f == '.') + { /* precision */ + f++; + if (*f == '*') + { + prec = va_arg(ap, int); + f++; + } + else if (isdigit((unsigned char)*f)) + { + prec = atoi(f); + while (isdigit((unsigned char)*f)) + f++; /* skip the digits */ + } + } + + if (*f == '#') + { /* alternate form */ + hash = 1; + f++; + } + + if (*f == 'l') + { /* long format */ + do_long++; + f++; + if (*f == 'l') + { + do_long++; + f++; + } + } + + fmt = (unsigned char) *f; + if (fmt != 'S' && fmt != 'Q' && isupper(fmt)) + { + do_long = 1; + fmt = tolower(fmt); + } + bp = buf; + switch (fmt) + { /* do the format */ + case 'd': + switch (do_long) + { + case 0: + l = (long) (va_arg(ap, int)); + break; + case 1: + default: + l = va_arg(ap, long); + break; + } + + if (l < 0) + { + sign = 1; + l = -l; + } + do + { + *bp++ = (char) (l % 10) + '0'; + } while ((l /= 10) > 0); + if (sign) + *bp++ = '-'; + f_width = f_width - (int) (bp - buf); + if (!flush_left) + while (f_width-- > 0) + (*addchar)((int) (pad | attributes)); + for (bp--; bp >= buf; bp--) + (*addchar)((int) (((unsigned char) *bp) | attributes)); + if (flush_left) + while (f_width-- > 0) + (*addchar)((int) (' ' | attributes)); + break; + + case 'f': + /* this is actually more than stupid, but does work for now */ + flt = (float) (va_arg(ap, double)); /* beware: va_arg() extends float to double! */ + if (flt < 0) + { + sign = 1; + flt = -flt; + } + { + int quotient, remainder; + + quotient = (int) flt; + remainder = (flt - quotient) * 10E5; + + for (i = 0; i < 6; i++) + { + *bp++ = (char) (remainder % 10) + '0'; + remainder /= 10; + } + *bp++ = '.'; + do + { + *bp++ = (char) (quotient % 10) + '0'; + } while ((quotient /= 10) > 0); + if (sign) + *bp++ = '-'; + f_width = f_width - (int) (bp - buf); + if (!flush_left) + while (f_width-- > 0) + (*addchar)((int) (pad | attributes)); + for (bp--; bp >= buf; bp--) + (*addchar)((int) (((unsigned char) *bp) | attributes)); + if (flush_left) + while (f_width-- > 0) + (*addchar)((int) (' ' | attributes)); + } + break; + + case 'p': + do_long = 1; + hash = 1; + fmt = 'x'; + /* no break */ + case 'o': + case 'x': + case 'u': + switch (do_long) + { + case 0: + u = (unsigned long) (va_arg(ap, unsigned int)); + break; + case 1: + default: + u = va_arg(ap, unsigned long); + break; + } + if (fmt == 'u') + { /* unsigned decimal */ + do + { + *bp++ = (char) (u % 10) + '0'; + } while ((u /= 10) > 0); + } + else if (fmt == 'o') + { /* octal */ + do + { + *bp++ = (char) (u % 8) + '0'; + } while ((u /= 8) > 0); + if (hash) + *bp++ = '0'; + } + else if (fmt == 'x') + { /* hex */ + do + { + i = (int) (u % 16); + if (i < 10) + *bp++ = i + '0'; + else + *bp++ = i - 10 + 'a'; + } while ((u /= 16) > 0); + if (hash) + { + *bp++ = 'x'; + *bp++ = '0'; + } + } + i = f_width - (int) (bp - buf); + if (!flush_left) + while (i-- > 0) + (*addchar)((int) (pad | attributes)); + for (bp--; bp >= buf; bp--) + (*addchar)((int) (((unsigned char) *bp) | attributes)); + if (flush_left) + while (i-- > 0) + (*addchar)((int) (' ' | attributes)); + break; + + case 'c': + i = va_arg(ap, int); + (*addchar)((int) (i | attributes)); + break; + + case 'S': + case 'Q': + case 's': + case 'q': + bp = va_arg(ap, char *); + if (!bp) + bp = snil; + f_width = f_width - strlen((char *) bp); + if (!flush_left) + while (f_width-- > 0) + (*addchar)((int) (pad | attributes)); + for (i = 0; *bp && i < prec; i++) + { + if (fmt == 'q' && (*bp & QUOTE)) + (*addchar)((int) ('\\' | attributes)); + (*addchar)( + (int) (((unsigned char) *bp & TRIM) | attributes)); + bp++; + } + if (flush_left) + while (f_width-- > 0) + (*addchar)((int) (' ' | attributes)); + break; + + case 'a': + attributes = va_arg(ap, int); + break; + + case '%': + (*addchar)((int) ('%' | attributes)); + break; + + default: + break; + } + flush_left = 0, f_width = 0, prec = INF, hash = 0, do_long = 0; + sign = 0; + pad = ' '; + } + } +} + +static char *xstring, *xestring; + +void xaddchar(int c) +{ + if (xestring == xstring) + *xstring = '\0'; + else + *xstring++ = (char) c; +} + +int sprintf(char *str, const char *format, ...) +{ + va_list va; + va_start(va, format); + + xstring = str; + + doprnt(xaddchar, format, va); + va_end(va); + *xstring++ = '\0'; + + return 0; +} + +void xsnprintf(char *str, size_t size, const char *fmt, ...) +{ + va_list va; + + va_start(va, fmt); + + xstring = str; + xestring = str + size - 1; + doprnt(xaddchar, fmt, va); + va_end(va); + *xstring++ = '\0'; +} + +void xprintf(const char *fmt, ...) +{ + va_list va; + + va_start(va, fmt); + doprnt(xputchar, fmt, va); + va_end(va); +} + +void xvprintf(const char *fmt, va_list va) +{ + doprnt(xputchar, fmt, va); +} + +void xvsnprintf(char *str, size_t size, const char *fmt, va_list va) +{ + xstring = str; + xestring = str + size - 1; + doprnt(xaddchar, fmt, va); + *xstring++ = '\0'; +} + + +void display_progress() +{ + static int _progress_index; + char progress_char[] = "|/-\\"; + + xputchar(progress_char[_progress_index++ % strlen(progress_char)]); + xputchar('\r'); +} + +void hexdump(uint8_t buffer[], int size) +{ + int i; + int line = 0; + uint8_t *bp = buffer; + + while (bp < buffer + size) { + uint8_t *lbp = bp; + + xprintf("%08x ", line); + + for (i = 0; i < 16; i++) { + if (bp + i > buffer + size) { + break; + } + xprintf("%02x ", (uint8_t) *lbp++); + } + + lbp = bp; + for (i = 0; i < 16; i++) { + int8_t c = *lbp++; + + if (bp + i > buffer + size) { + break; + } + if (c > ' ' && c < '~') { + xprintf("%c", c); + } else { + xprintf("."); + } + } + xprintf("\r\n"); + + bp += 16; + line += 16; + } +} diff --git a/tos/jtagwait/sources/bas_string.c b/tos/jtagwait/sources/bas_string.c new file mode 100644 index 0000000..3960638 --- /dev/null +++ b/tos/jtagwait/sources/bas_string.c @@ -0,0 +1,156 @@ +/* + * bas_string.c + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 26.02.2013 + * Author: Markus Fröschle + */ + +#include "bas_types.h" +#include +#include "bas_string.h" + +void *memcpy(void *dst, const void *src, size_t n) +{ + uint8_t *to = dst; + + while (to < (uint8_t *) dst + n) + *to++ = * (uint8_t *) src++; + + return dst; +} + +void bzero(void *s, size_t n) +{ + size_t i; + + for (i = 0; i < n; i++) + ((unsigned char *) s)[i] = '\0'; +} + +void *memset(void *s, int c, size_t n) +{ + uint8_t *dst = s; + + do + { + *dst++ = c; + } while ((dst - (uint8_t *) s) < n); + + return s; +} + + +int memcmp(const void *s1, const void *s2, size_t max) +{ + int i; + int cmp; + + for (i = 0; i < max; i++) + { + cmp = (* (const char *) s1 - * (const char *) s2); + if (cmp != 0) return cmp; + } + return cmp; +} + +int strcmp(const char *s1, const char *s2) +{ + int i; + int cmp; + + for (i = 0; *s1++ && *s2++; i++) + { + cmp = (*s1 - *s2); + if (cmp != 0) return cmp; + } + return cmp; +} + +int strncmp(const char *s1, const char *s2, size_t max) +{ + int i; + int cmp; + + for (i = 0; i < max && *s1++ && *s2++; i++); + { + cmp = (*s1 - *s2); + if (cmp != 0) return cmp; + } + return cmp; +} + +char *strcpy(char *dst, const char *src) +{ + char *ptr = dst; + + while ((*dst++ = *src++) != '\0'); + return ptr; +} + +char *strncpy(char *dst, const char *src, size_t max) +{ + char *ptr = dst; + + while ((*dst++ = *src++) != '\0' && max-- >= 0); + return ptr; +} + +int atoi(const char *c) +{ + int value = 0; + while (isdigit(*c)) + { + value *= 10; + value += (int) (*c - '0'); + c++; + } + return value; +} + +size_t strlen(const char *s) +{ + const char *start = s; + + while (*s++); + + return s - start - 1; +} + + +char *strcat(char *dst, const char *src) +{ + char *ret = dst; + dst = &dst[strlen(dst)]; + while ((*dst++ = *src++) != '\0'); + return ret; +} + +char *strncat(char *dst, const char *src, size_t max) +{ + size_t i; + char *ret = dst; + + dst = &dst[strlen(dst)]; + for (i = 0; i < max && *src; i++) + { + *dst++ = *src++; + } + *dst++ = '\0'; + + return ret; +} diff --git a/tos/jtagwait/sources/jtagwait.c b/tos/jtagwait/sources/jtagwait.c new file mode 100644 index 0000000..f9426bc --- /dev/null +++ b/tos/jtagwait/sources/jtagwait.c @@ -0,0 +1,123 @@ +#include +#include +#include +#include + +#include "bas_printf.h" +#include "MCF5475.h" +#include "driver_vec.h" + +extern uint32_t _FPGA_JTAG_LOADED; +extern uint32_t _FPGA_JTAG_VALID; + +#define VALID_JTAG 0xaffeaffe + +#define FPGA_CONFIG (1 << 2) +#define FPGA_CONF_DONE (1 << 5) + +#define SRAM1_START 0xff101000 +#define SRAM1_END SRAM1_START + 0x1000 +#define SAFE_STACK SRAM1_END - 4 + +#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory") + +long bas_start = 0xe0000000; + + +void wait_for_jtag(void) +{ + int i; + + /* set supervisor stack to end of SRAM1 */ + __asm__ __volatile__ ( + " move #0x2700,sr\n\t" /* disable interrupts */ + " move.l %[stack],d0\n\t" /* 4KB on-chip core SRAM1 */ + " move.l d0,sp\n\t" /* set stack pointer */ + : + : [stack] "i" (SAFE_STACK) + : "d0", "cc" /* clobber */ + ); + + MCF_EPORT_EPIER = 0x0; /* disable EPORT interrupts */ + MCF_INTC_IMRL = 0xffffffff; + MCF_INTC_IMRH = 0xffffffff; /* disable interrupt controller */ + + MCF_MMU_MMUCR &= ~MCF_MMU_MMUCR_EN; /* disable MMU */ + + xprintf("relocated supervisor stack, disabled interrupts and disabled MMU\r\n"); + + /* + * configure FEC1L port directions to enable external JTAG configuration download to FPGA + */ + MCF_GPIO_PDDR_FEC1L = 0 | + MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4; /* bit 4 = LED => output */ + /* all other bits = input */ + + /* + * configure DSPI_CS3 as GPIO input to avoid the MCU driving against the FPGA blink + */ + MCF_PAD_PAR_DSPI &= ~MCF_PAD_PAR_DSPI_PAR_CS3(MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3); + /* + * now that GPIO ports have been switched to input, we can poll for FPGA config + * started from the JTAG interface (CONF_DONE goes low) and finish (CONF_DONE goes high) + */ + xprintf("waiting for JTAG configuration start\r\n"); + while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load started */ + + xprintf("waiting for JTAG configuration to finish\r\n"); + while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load finished */ + + xprintf("JTAG configuration finished.\r\n"); + _FPGA_JTAG_LOADED = 1; /* indicate jtag loaded FPGA config to BaS */ + _FPGA_JTAG_VALID = VALID_JTAG; /* set magic word to indicate _FPGA_JTAG_LOADED is valid */ + + /* wait */ + xprintf("wait a little to let things settle...\r\n"); + for (i = 0; i < 100000; i++); + xprintf("reset and restart..."); + + __asm__ __volatile__( + " jmp (%[bas_start])\n\t" + : /* no output */ + : [bas_start] "a" (bas_start) + : /* clobber not needed */ + ); +} + +int main(int argc, char *argv[]) +{ + printf("\033E\r\nFPGA JTAG configuration support\r\n"); + printf("\xbd 2014 M. Fr\x94schle\r\n"); + + printf("You may now savely load a new FPGA configuration through the JTAG interface\r\n" + "and your Firebee will reboot once finished using that new configuration.\r\n"); + if (argc == 2) + { + /* + * we got an argument. This is supposed to be the address that we need to jump to after JTAG + * configuration has been finished. Meant to support BaS in RAM testing + */ + char *addr_str = argv[1]; + char *addr = NULL; + char *end = NULL; + + addr = (char *) strtol(addr_str, &end, 16); + if (addr != NULL && addr <= (char *) 0xe0000000 && addr >= (char *) 0x10000000) + { + /* + * seems to be a valid address + */ + bas_start = (long) addr; + + printf("BaS start address set to %p\r\n", (void *) bas_start); + } + else + { + printf("\r\nNote: BaS start address %p not valid. Stick to %p.\r\n", addr, (void *) bas_start); + } + } + Supexec(wait_for_jtag); + + return 0; /* just to make the compiler happy, we will never return */ +} + diff --git a/tos/jtagwait/sources/printf_helper.S b/tos/jtagwait/sources/printf_helper.S new file mode 100644 index 0000000..7d8eec1 --- /dev/null +++ b/tos/jtagwait/sources/printf_helper.S @@ -0,0 +1,38 @@ +/* + * printf_helper.S + * + * assembler trampoline to let printf (compiled -mpcrel) indirectly reference __MBAR + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Copyright 2010 - 2012 F. Aschwanden + * Copyright 2011 - 2012 V. Riviere + * Copyright 2012 M. Froeschle + */ + + + .global printf_helper +printf_helper: + .extern __MBAR +.wait_txready: + move.w __MBAR+0x8604,d2 // PSCSCR0 status register + btst #10,d2 // space left in TX fifo? + beq.s .wait_txready // no, loop + lea __MBAR+0x860C,a0 // PSCSTB0 transmitter buffer register + move.b d0,(a0) // send byte + rts + +// vim: set syntax=asm68k : diff --git a/tos/pci_mem/Makefile b/tos/pci_mem/Makefile new file mode 100755 index 0000000..d0862c3 --- /dev/null +++ b/tos/pci_mem/Makefile @@ -0,0 +1,105 @@ +CROSS=Y + +CROSSBINDIR_IS_Y=m68k-atari-mint- +CROSSBINDIR_IS_N= + +CROSSBINDIR=$(CROSSBINDIR_IS_$(CROSS)) + +UNAME := $(shell uname) +ifeq ($(CROSS), Y) +ifeq ($(UNAME),Linux) +PREFIX=m68k-atari-mint +HATARI=hatari +else +PREFIX=m68k-atari-mint +HATARI=/usr/local/bin/hatari +endif +else +PREFIX=/usr +endif + +DEPEND=depend +TOPDIR = ../.. + +LIBCMINI=$(TOPDIR)/../libcmini/libcmini + +INCLUDE=-I$(LIBCMINI)/include -nostdlib +LIBS=-lcmini -nostdlib -lgcc +CC=$(PREFIX)/bin/gcc + +CC=$(CROSSBINDIR)gcc +STRIP=$(CROSSBINDIR)strip +STACK=$(CROSSBINDIR)stack + +APP=pci_mem.prg +TEST_APP=$(APP) + +CFLAGS=\ + -O0\ + -g\ + -Wl,-Map,mapfile\ + -Wl,--defsym -Wl,__MBAR=0xff000000\ + -Wl,--defsym -Wl,__MMUBAR=0xff040000\ + -Wl,--defsym -Wl,__FPGA_JTAG_LOADED=0xff101000\ + -Wl,--defsym -Wl,__FPGA_JTAG_VALID=0xff101004\ + -Wl,--defsym -Wl,__VRAM=0x60000000\ + -Wall + +SRCDIR=sources +INCDIR=include +INCLUDE+=-I$(INCDIR) + +CSRCS=\ + $(SRCDIR)/pci_mem.c + +ASRCS= + +COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS))) +AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS))) +OBJS=$(COBJS) $(AOBJS) + +TRGTDIRS=./m5475 ./m5475/mshort +OBJDIRS=$(patsubst %,%/objs,$(TRGTDIRS)) + +# +# multilib flags. These must match m68k-atari-mint-gcc -print-multi-lib output +# +m5475/$(APP):CFLAGS += -mcpu=5475 +m5475/mshort/$(APP): CFLAGS += -mcpu=5475 -mshort + +all:$(patsubst %,%/$(APP),$(TRGTDIRS)) +# +# generate pattern rules for multilib object files. +# +define CC_TEMPLATE +$(1)/objs/%.o:$(SRCDIR)/%.c + $(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@ + +$(1)/objs/%.o:$(SRCDIR)/%.S + $(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@ + +$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS)) +$(1)/$(APP): $$($(1)_OBJS) + $(CC) $$(CFLAGS) -o $$@ $(LIBCMINI)/$(1)/startup.o $$($(1)_OBJS) -L$(LIBCMINI)/$(1) $(LIBS) + $(STRIP) $$@ +endef +$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR)))) + +$(DEPEND): $(ASRCS) $(CSRCS) + -rm -f $(DEPEND) + for d in $(TRGTDIRS);\ + do $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e "s#^\(.*\).o:#$$d/objs/\1.o:#" >> $(DEPEND); \ + done + + +clean: + @rm -f $(patsubst %,%/objs/*.o,$(TRGTDIRS)) $(patsubst %,%/$(APP),$(TRGTDIRS)) + @rm -f $(DEPEND) mapfile + +.PHONY: printvars +printvars: + @$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V)))) + +ifneq (clean,$(MAKECMDGOALS)) +-include $(DEPEND) +endif diff --git a/tos/pci_mem/include/MCF5475.h b/tos/pci_mem/include/MCF5475.h new file mode 100644 index 0000000..5ab1750 --- /dev/null +++ b/tos/pci_mem/include/MCF5475.h @@ -0,0 +1,67 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_H__ +#define __MCF5475_H__ + +#include +/*** + * MCF5475 Derivative Memory map definitions from linker command files: + * __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE + * linker symbols must be defined in the linker command file. + */ + +typedef uint32_t __attribute__((__may_alias__)) uint32_t_a; /* a type to avoid gcc's complaints about pointer aliasing */ + +extern uint8_t _MBAR[]; +extern uint8_t _MMUBAR[]; +extern uint8_t _RAMBAR0[]; +extern uint8_t _RAMBAR0_SIZE[]; +extern uint8_t _RAMBAR1[]; +extern uint8_t _RAMBAR1_SIZE[]; + +#define MBAR_ADDRESS (uint32_t)_MBAR +#define MMUBAR_ADDRESS (uint32_t)_MMUBAR +#define RAMBAR0_ADDRESS (uint32_t)_RAMBAR0 +#define RAMBAR0_SIZE (uint32_t)_RAMBAR0_SIZE +#define RAMBAR1_ADDRESS (uint32_t)_RAMBAR1 +#define RAMBAR1_SIZE (uint32_t)_RAMBAR1_SIZE + + +#include "MCF5475_SIU.h" +#include "MCF5475_MMU.h" +#include "MCF5475_SDRAMC.h" +#include "MCF5475_XLB.h" +#include "MCF5475_CLOCK.h" +#include "MCF5475_FBCS.h" +#include "MCF5475_INTC.h" +#include "MCF5475_GPT.h" +#include "MCF5475_SLT.h" +#include "MCF5475_GPIO.h" +#include "MCF5475_PAD.h" +#include "MCF5475_PCI.h" +#include "MCF5475_PCIARB.h" +#include "MCF5475_EPORT.h" +#include "MCF5475_CTM.h" +#include "MCF5475_DMA.h" +#include "MCF5475_PSC.h" +#include "MCF5475_DSPI.h" +#include "MCF5475_I2C.h" +#include "MCF5475_FEC.h" +#include "MCF5475_USB.h" +#include "MCF5475_SRAM.h" +#include "MCF5475_SEC.h" + +#endif /* __MCF5475_H__ */ diff --git a/tos/pci_mem/include/MCF5475_CLOCK.h b/tos/pci_mem/include/MCF5475_CLOCK.h new file mode 100644 index 0000000..4603098 --- /dev/null +++ b/tos/pci_mem/include/MCF5475_CLOCK.h @@ -0,0 +1,47 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_CLOCK_H__ +#define __MCF5475_CLOCK_H__ + + +/********************************************************************* +* +* Clock Module (CLOCK) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CLOCK_SPCR (*(volatile uint32_t*)(&_MBAR[0x300])) + + +/* Bit definitions and macros for MCF_CLOCK_SPCR */ +#define MCF_CLOCK_SPCR_MEMEN (0x1) +#define MCF_CLOCK_SPCR_PCIEN (0x2) +#define MCF_CLOCK_SPCR_FBEN (0x4) +#define MCF_CLOCK_SPCR_CAN0EN (0x8) +#define MCF_CLOCK_SPCR_DMAEN (0x10) +#define MCF_CLOCK_SPCR_FEC0EN (0x20) +#define MCF_CLOCK_SPCR_FEC1EN (0x40) +#define MCF_CLOCK_SPCR_USBEN (0x80) +#define MCF_CLOCK_SPCR_PSCEN (0x200) +#define MCF_CLOCK_SPCR_CAN1EN (0x800) +#define MCF_CLOCK_SPCR_CRYENA (0x1000) +#define MCF_CLOCK_SPCR_CRYENB (0x2000) +#define MCF_CLOCK_SPCR_COREN (0x4000) +#define MCF_CLOCK_SPCR_PLLK (0x80000000) + + +#endif /* __MCF5475_CLOCK_H__ */ diff --git a/tos/pci_mem/include/MCF5475_CTM.h b/tos/pci_mem/include/MCF5475_CTM.h new file mode 100644 index 0000000..5ba86e4 --- /dev/null +++ b/tos/pci_mem/include/MCF5475_CTM.h @@ -0,0 +1,76 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_CTM_H__ +#define __MCF5475_CTM_H__ + + +/********************************************************************* +* +* Comm Timer Module (CTM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CTM_CTCR0 (*(volatile uint32_t*)(&_MBAR[0x7F00])) +#define MCF_CTM_CTCR1 (*(volatile uint32_t*)(&_MBAR[0x7F04])) +#define MCF_CTM_CTCR2 (*(volatile uint32_t*)(&_MBAR[0x7F08])) +#define MCF_CTM_CTCR3 (*(volatile uint32_t*)(&_MBAR[0x7F0C])) +#define MCF_CTM_CTCR4 (*(volatile uint32_t*)(&_MBAR[0x7F10])) +#define MCF_CTM_CTCR5 (*(volatile uint32_t*)(&_MBAR[0x7F14])) +#define MCF_CTM_CTCR6 (*(volatile uint32_t*)(&_MBAR[0x7F18])) +#define MCF_CTM_CTCR7 (*(volatile uint32_t*)(&_MBAR[0x7F1C])) +#define MCF_CTM_CTCRF(x) (*(volatile uint32_t*)(&_MBAR[0x7F00 + ((x)*0x4)])) +#define MCF_CTM_CTCRV(x) (*(volatile uint32_t*)(&_MBAR[0x7F10 + ((x-4)*0x4)])) + + +/* Bit definitions and macros for MCF_CTM_CTCRF */ +#define MCF_CTM_CTCRF_CRV(x) (((x)&0xFFFF)<<0) +#define MCF_CTM_CTCRF_S(x) (((x)&0xF)<<0x10) +#define MCF_CTM_CTCRF_S_CLK_1 (0) +#define MCF_CTM_CTCRF_S_CLK_2 (0x10000) +#define MCF_CTM_CTCRF_S_CLK_4 (0x20000) +#define MCF_CTM_CTCRF_S_CLK_8 (0x30000) +#define MCF_CTM_CTCRF_S_CLK_16 (0x40000) +#define MCF_CTM_CTCRF_S_CLK_32 (0x50000) +#define MCF_CTM_CTCRF_S_CLK_64 (0x60000) +#define MCF_CTM_CTCRF_S_CLK_128 (0x70000) +#define MCF_CTM_CTCRF_S_CLK_256 (0x80000) +#define MCF_CTM_CTCRF_S_CLK_EXT (0x90000) +#define MCF_CTM_CTCRF_PCT(x) (((x)&0x7)<<0x14) +#define MCF_CTM_CTCRF_PCT_100 (0) +#define MCF_CTM_CTCRF_PCT_50 (0x100000) +#define MCF_CTM_CTCRF_PCT_25 (0x200000) +#define MCF_CTM_CTCRF_PCT_12p5 (0x300000) +#define MCF_CTM_CTCRF_PCT_6p25 (0x400000) +#define MCF_CTM_CTCRF_PCT_OFF (0x500000) +#define MCF_CTM_CTCRF_M (0x800000) +#define MCF_CTM_CTCRF_IM (0x1000000) +#define MCF_CTM_CTCRF_I (0x80000000) + +/* Bit definitions and macros for MCF_CTM_CTCRV */ +#define MCF_CTM_CTCRV_CRV(x) (((x)&0xFFFFFF)<<0) +#define MCF_CTM_CTCRV_PCT(x) (((x)&0x7)<<0x18) +#define MCF_CTM_CTCRV_PCT_100 (0) +#define MCF_CTM_CTCRV_PCT_50 (0x1000000) +#define MCF_CTM_CTCRV_PCT_25 (0x2000000) +#define MCF_CTM_CTCRV_PCT_12p5 (0x3000000) +#define MCF_CTM_CTCRV_PCT_6p25 (0x4000000) +#define MCF_CTM_CTCRV_PCT_OFF (0x5000000) +#define MCF_CTM_CTCRV_M (0x8000000) +#define MCF_CTM_CTCRV_S (0x10000000) + + +#endif /* __MCF5475_CTM_H__ */ diff --git a/tos/pci_mem/include/MCF5475_DMA.h b/tos/pci_mem/include/MCF5475_DMA.h new file mode 100644 index 0000000..4e6f916 --- /dev/null +++ b/tos/pci_mem/include/MCF5475_DMA.h @@ -0,0 +1,234 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_DMA_H__ +#define __MCF5475_DMA_H__ + + +/********************************************************************* +* +* Multichannel DMA (DMA) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DMA_TASKBAR (*(volatile uint32_t*)(&_MBAR[0x8000])) +#define MCF_DMA_CP (*(volatile uint32_t*)(&_MBAR[0x8004])) +#define MCF_DMA_EP (*(volatile uint32_t*)(&_MBAR[0x8008])) +#define MCF_DMA_VP (*(volatile uint32_t*)(&_MBAR[0x800C])) +#define MCF_DMA_PTD (*(volatile uint32_t*)(&_MBAR[0x8010])) +#define MCF_DMA_DIPR (*(volatile uint32_t*)(&_MBAR[0x8014])) +#define MCF_DMA_DIMR (*(volatile uint32_t*)(&_MBAR[0x8018])) +#define MCF_DMA_TCR0 (*(volatile uint16_t*)(&_MBAR[0x801C])) +#define MCF_DMA_TCR1 (*(volatile uint16_t*)(&_MBAR[0x801E])) +#define MCF_DMA_TCR2 (*(volatile uint16_t*)(&_MBAR[0x8020])) +#define MCF_DMA_TCR3 (*(volatile uint16_t*)(&_MBAR[0x8022])) +#define MCF_DMA_TCR4 (*(volatile uint16_t*)(&_MBAR[0x8024])) +#define MCF_DMA_TCR5 (*(volatile uint16_t*)(&_MBAR[0x8026])) +#define MCF_DMA_TCR6 (*(volatile uint16_t*)(&_MBAR[0x8028])) +#define MCF_DMA_TCR7 (*(volatile uint16_t*)(&_MBAR[0x802A])) +#define MCF_DMA_TCR8 (*(volatile uint16_t*)(&_MBAR[0x802C])) +#define MCF_DMA_TCR9 (*(volatile uint16_t*)(&_MBAR[0x802E])) +#define MCF_DMA_TCR10 (*(volatile uint16_t*)(&_MBAR[0x8030])) +#define MCF_DMA_TCR11 (*(volatile uint16_t*)(&_MBAR[0x8032])) +#define MCF_DMA_TCR12 (*(volatile uint16_t*)(&_MBAR[0x8034])) +#define MCF_DMA_TCR13 (*(volatile uint16_t*)(&_MBAR[0x8036])) +#define MCF_DMA_TCR14 (*(volatile uint16_t*)(&_MBAR[0x8038])) +#define MCF_DMA_TCR15 (*(volatile uint16_t*)(&_MBAR[0x803A])) +#define MCF_DMA_PRIOR0 (*(volatile uint8_t *)(&_MBAR[0x803C])) +#define MCF_DMA_PRIOR1 (*(volatile uint8_t *)(&_MBAR[0x803D])) +#define MCF_DMA_PRIOR2 (*(volatile uint8_t *)(&_MBAR[0x803E])) +#define MCF_DMA_PRIOR3 (*(volatile uint8_t *)(&_MBAR[0x803F])) +#define MCF_DMA_PRIOR4 (*(volatile uint8_t *)(&_MBAR[0x8040])) +#define MCF_DMA_PRIOR5 (*(volatile uint8_t *)(&_MBAR[0x8041])) +#define MCF_DMA_PRIOR6 (*(volatile uint8_t *)(&_MBAR[0x8042])) +#define MCF_DMA_PRIOR7 (*(volatile uint8_t *)(&_MBAR[0x8043])) +#define MCF_DMA_PRIOR8 (*(volatile uint8_t *)(&_MBAR[0x8044])) +#define MCF_DMA_PRIOR9 (*(volatile uint8_t *)(&_MBAR[0x8045])) +#define MCF_DMA_PRIOR10 (*(volatile uint8_t *)(&_MBAR[0x8046])) +#define MCF_DMA_PRIOR11 (*(volatile uint8_t *)(&_MBAR[0x8047])) +#define MCF_DMA_PRIOR12 (*(volatile uint8_t *)(&_MBAR[0x8048])) +#define MCF_DMA_PRIOR13 (*(volatile uint8_t *)(&_MBAR[0x8049])) +#define MCF_DMA_PRIOR14 (*(volatile uint8_t *)(&_MBAR[0x804A])) +#define MCF_DMA_PRIOR15 (*(volatile uint8_t *)(&_MBAR[0x804B])) +#define MCF_DMA_PRIOR16 (*(volatile uint8_t *)(&_MBAR[0x804C])) +#define MCF_DMA_PRIOR17 (*(volatile uint8_t *)(&_MBAR[0x804D])) +#define MCF_DMA_PRIOR18 (*(volatile uint8_t *)(&_MBAR[0x804E])) +#define MCF_DMA_PRIOR19 (*(volatile uint8_t *)(&_MBAR[0x804F])) +#define MCF_DMA_PRIOR20 (*(volatile uint8_t *)(&_MBAR[0x8050])) +#define MCF_DMA_PRIOR21 (*(volatile uint8_t *)(&_MBAR[0x8051])) +#define MCF_DMA_PRIOR22 (*(volatile uint8_t *)(&_MBAR[0x8052])) +#define MCF_DMA_PRIOR23 (*(volatile uint8_t *)(&_MBAR[0x8053])) +#define MCF_DMA_PRIOR24 (*(volatile uint8_t *)(&_MBAR[0x8054])) +#define MCF_DMA_PRIOR25 (*(volatile uint8_t *)(&_MBAR[0x8055])) +#define MCF_DMA_PRIOR26 (*(volatile uint8_t *)(&_MBAR[0x8056])) +#define MCF_DMA_PRIOR27 (*(volatile uint8_t *)(&_MBAR[0x8057])) +#define MCF_DMA_PRIOR28 (*(volatile uint8_t *)(&_MBAR[0x8058])) +#define MCF_DMA_PRIOR29 (*(volatile uint8_t *)(&_MBAR[0x8059])) +#define MCF_DMA_PRIOR30 (*(volatile uint8_t *)(&_MBAR[0x805A])) +#define MCF_DMA_PRIOR31 (*(volatile uint8_t *)(&_MBAR[0x805B])) +#define MCF_DMA_IMCR (*(volatile uint32_t*)(&_MBAR[0x805C])) +#define MCF_DMA_TSKSZ0 (*(volatile uint32_t*)(&_MBAR[0x8060])) +#define MCF_DMA_TSKSZ1 (*(volatile uint32_t*)(&_MBAR[0x8064])) +#define MCF_DMA_DBGCOMP0 (*(volatile uint32_t*)(&_MBAR[0x8070])) +#define MCF_DMA_DBGCOMP2 (*(volatile uint32_t*)(&_MBAR[0x8074])) +#define MCF_DMA_DBGCTL (*(volatile uint32_t*)(&_MBAR[0x8078])) +#define MCF_DMA_TCR(x) (*(volatile uint16_t*)(&_MBAR[0x801C + ((x)*0x2)])) +#define MCF_DMA_PRIOR(x) (*(volatile uint8_t *)(&_MBAR[0x803C + ((x)*0x1)])) + + +/* Bit definitions and macros for MCF_DMA_TASKBAR */ +#define MCF_DMA_TASKBAR_TASK_BASE_ADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_CP */ +#define MCF_DMA_CP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_EP */ +#define MCF_DMA_EP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_VP */ +#define MCF_DMA_VP_VARIABLE_POINTER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_PTD */ +#define MCF_DMA_PTD_PCTL0 (0x1) +#define MCF_DMA_PTD_PCTL1 (0x2) +#define MCF_DMA_PTD_PCTL13 (0x2000) +#define MCF_DMA_PTD_PCTL14 (0x4000) +#define MCF_DMA_PTD_PCTL15 (0x8000) + +/* Bit definitions and macros for MCF_DMA_DIPR */ +#define MCF_DMA_DIPR_TASK(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DIMR */ +#define MCF_DMA_DIMR_TASK(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_TCR */ +#define MCF_DMA_TCR_ASTSKNUM(x) (((x)&0xF)<<0) +#define MCF_DMA_TCR_HLDINITNUM (0x20) +#define MCF_DMA_TCR_HIPRITSKEN (0x40) +#define MCF_DMA_TCR_ASTRT (0x80) +#define MCF_DMA_TCR_INITNUM(x) (((x)&0x1F)<<0x8) +#define MCF_DMA_TCR_ALWINIT (0x2000) +#define MCF_DMA_TCR_V (0x4000) +#define MCF_DMA_TCR_EN (0x8000) + +/* Bit definitions and macros for MCF_DMA_PRIOR */ +#define MCF_DMA_PRIOR_PRI(x) (((x)&0x7)<<0) +#define MCF_DMA_PRIOR_HLD (0x80) + +/* Bit definitions and macros for MCF_DMA_IMCR */ +#define MCF_DMA_IMCR_IMC16(x) (((x)&0x3)<<0) +#define MCF_DMA_IMCR_IMC17(x) (((x)&0x3)<<0x2) +#define MCF_DMA_IMCR_IMC18(x) (((x)&0x3)<<0x4) +#define MCF_DMA_IMCR_IMC19(x) (((x)&0x3)<<0x6) +#define MCF_DMA_IMCR_IMC20(x) (((x)&0x3)<<0x8) +#define MCF_DMA_IMCR_IMC21(x) (((x)&0x3)<<0xA) +#define MCF_DMA_IMCR_IMC22(x) (((x)&0x3)<<0xC) +#define MCF_DMA_IMCR_IMC23(x) (((x)&0x3)<<0xE) +#define MCF_DMA_IMCR_IMC24(x) (((x)&0x3)<<0x10) +#define MCF_DMA_IMCR_IMC25(x) (((x)&0x3)<<0x12) +#define MCF_DMA_IMCR_IMC26(x) (((x)&0x3)<<0x14) +#define MCF_DMA_IMCR_IMC27(x) (((x)&0x3)<<0x16) +#define MCF_DMA_IMCR_IMC28(x) (((x)&0x3)<<0x18) +#define MCF_DMA_IMCR_IMC29(x) (((x)&0x3)<<0x1A) +#define MCF_DMA_IMCR_IMC30(x) (((x)&0x3)<<0x1C) +#define MCF_DMA_IMCR_IMC31(x) (((x)&0x3)<<0x1E) + + +#define MCF_DMA_IMCR_IMC16_FEC0RX (0x00000000) +#define MCF_DMA_IMCR_IMC17_FEC0TX (0x00000000) +#define MCF_DMA_IMCR_IMC18_FEC0RX (0x00000020) +#define MCF_DMA_IMCR_IMC19_FEC0TX (0x00000080) +#define MCF_DMA_IMCR_IMC20_FEC1RX (0x00000100) +#define MCF_DMA_IMCR_IMC21_DREQ1 (0x00000000) +#define MCF_DMA_IMCR_IMC21_FEC1TX (0x00000400) +#define MCF_DMA_IMCR_IMC22_FEC0RX (0x00001000) +#define MCF_DMA_IMCR_IMC23_FEC0TX (0x00004000) +#define MCF_DMA_IMCR_IMC24_CTM0 (0x00010000) +#define MCF_DMA_IMCR_IMC24_FEC1RX (0x00020000) +#define MCF_DMA_IMCR_IMC25_CTM1 (0x00040000) +#define MCF_DMA_IMCR_IMC25_FEC1TX (0x00080000) +#define MCF_DMA_IMCR_IMC26_USBEP4 (0x00000000) +#define MCF_DMA_IMCR_IMC26_CTM2 (0x00200000) +#define MCF_DMA_IMCR_IMC27_USBEP5 (0x00000000) +#define MCF_DMA_IMCR_IMC27_CTM3 (0x00800000) +#define MCF_DMA_IMCR_IMC28_USBEP6 (0x00000000) +#define MCF_DMA_IMCR_IMC28_CTM4 (0x01000000) +#define MCF_DMA_IMCR_IMC28_DREQ1 (0x02000000) +#define MCF_DMA_IMCR_IMC28_PSC2RX (0x03000000) +#define MCF_DMA_IMCR_IMC29_DREQ1 (0x04000000) +#define MCF_DMA_IMCR_IMC29_CTM5 (0x08000000) +#define MCF_DMA_IMCR_IMC29_PSC2TX (0x0C000000) +#define MCF_DMA_IMCR_IMC30_FEC1RX (0x00000000) +#define MCF_DMA_IMCR_IMC30_CTM6 (0x10000000) +#define MCF_DMA_IMCR_IMC30_PSC3RX (0x30000000) +#define MCF_DMA_IMCR_IMC31_FEC1TX (0x00000000) +#define MCF_DMA_IMCR_IMC31_CTM7 (0x80000000) +#define MCF_DMA_IMCR_IMC31_PSC3TX (0xC0000000) + +/* Bit definitions and macros for MCF_DMA_TSKSZ0 */ +#define MCF_DMA_TSKSZ0_DSTSZ7(x) (((x)&0x3)<<0) +#define MCF_DMA_TSKSZ0_SRCSZ7(x) (((x)&0x3)<<0x2) +#define MCF_DMA_TSKSZ0_DSTSZ6(x) (((x)&0x3)<<0x4) +#define MCF_DMA_TSKSZ0_SRCSZ6(x) (((x)&0x3)<<0x6) +#define MCF_DMA_TSKSZ0_DSTSZ5(x) (((x)&0x3)<<0x8) +#define MCF_DMA_TSKSZ0_SRCSZ5(x) (((x)&0x3)<<0xA) +#define MCF_DMA_TSKSZ0_DSTSZ4(x) (((x)&0x3)<<0xC) +#define MCF_DMA_TSKSZ0_SRCSZ4(x) (((x)&0x3)<<0xE) +#define MCF_DMA_TSKSZ0_DSTSZ3(x) (((x)&0x3)<<0x10) +#define MCF_DMA_TSKSZ0_SRCSZ3(x) (((x)&0x3)<<0x12) +#define MCF_DMA_TSKSZ0_DSTSZ2(x) (((x)&0x3)<<0x14) +#define MCF_DMA_TSKSZ0_SRCSZ2(x) (((x)&0x3)<<0x16) +#define MCF_DMA_TSKSZ0_DSTSZ1(x) (((x)&0x3)<<0x18) +#define MCF_DMA_TSKSZ0_SRCSZ1(x) (((x)&0x3)<<0x1A) +#define MCF_DMA_TSKSZ0_DSTSZ0(x) (((x)&0x3)<<0x1C) +#define MCF_DMA_TSKSZ0_SRCSZ0(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_DMA_TSKSZ1 */ +#define MCF_DMA_TSKSZ1_DSTSZ15(x) (((x)&0x3)<<0) +#define MCF_DMA_TSKSZ1_SRCSZ15(x) (((x)&0x3)<<0x2) +#define MCF_DMA_TSKSZ1_DSTSZ14(x) (((x)&0x3)<<0x4) +#define MCF_DMA_TSKSZ1_SRCSZ14(x) (((x)&0x3)<<0x6) +#define MCF_DMA_TSKSZ1_DSTSZ13(x) (((x)&0x3)<<0x8) +#define MCF_DMA_TSKSZ1_SRCSZ13(x) (((x)&0x3)<<0xA) +#define MCF_DMA_TSKSZ1_DSTSZ12(x) (((x)&0x3)<<0xC) +#define MCF_DMA_TSKSZ1_SRCSZ12(x) (((x)&0x3)<<0xE) +#define MCF_DMA_TSKSZ1_DSTSZ11(x) (((x)&0x3)<<0x10) +#define MCF_DMA_TSKSZ1_SRCSZ11(x) (((x)&0x3)<<0x12) +#define MCF_DMA_TSKSZ1_DSTSZ10(x) (((x)&0x3)<<0x14) +#define MCF_DMA_TSKSZ1_SRCSZ10(x) (((x)&0x3)<<0x16) +#define MCF_DMA_TSKSZ1_DSTSZ9(x) (((x)&0x3)<<0x18) +#define MCF_DMA_TSKSZ1_SRCSZ9(x) (((x)&0x3)<<0x1A) +#define MCF_DMA_TSKSZ1_DSTSZ8(x) (((x)&0x3)<<0x1C) +#define MCF_DMA_TSKSZ1_SRCSZ8(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_DMA_DBGCOMP0 */ +#define MCF_DMA_DBGCOMP0_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DBGCOMP2 */ +#define MCF_DMA_DBGCOMP2_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DBGCTL */ +#define MCF_DMA_DBGCTL_I (0x2) +#define MCF_DMA_DBGCTL_E (0x4) +#define MCF_DMA_DBGCTL_AND_OR (0x80) +#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_2(x) (((x)&0x7)<<0x8) +#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_1(x) (((x)&0x7)<<0xB) +#define MCF_DMA_DBGCTL_B (0x4000) +#define MCF_DMA_DBGCTL_AA (0x8000) +#define MCF_DMA_DBGCTL_BLOCK_TASKS(x) (((x)&0xFFFF)<<0x10) + + +#endif /* __MCF5475_DMA_H__ */ diff --git a/tos/pci_mem/include/MCF5475_DSPI.h b/tos/pci_mem/include/MCF5475_DSPI.h new file mode 100644 index 0000000..76cac28 --- /dev/null +++ b/tos/pci_mem/include/MCF5475_DSPI.h @@ -0,0 +1,150 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_DSPI_H__ +#define __MCF5475_DSPI_H__ + + +/********************************************************************* +* +* DMA Serial Peripheral Interface (DSPI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DSPI_DMCR (*(volatile uint32_t*)(&_MBAR[0x8A00])) +#define MCF_DSPI_DTCR (*(volatile uint32_t*)(&_MBAR[0x8A08])) +#define MCF_DSPI_DCTAR0 (*(volatile uint32_t*)(&_MBAR[0x8A0C])) +#define MCF_DSPI_DCTAR1 (*(volatile uint32_t*)(&_MBAR[0x8A10])) +#define MCF_DSPI_DCTAR2 (*(volatile uint32_t*)(&_MBAR[0x8A14])) +#define MCF_DSPI_DCTAR3 (*(volatile uint32_t*)(&_MBAR[0x8A18])) +#define MCF_DSPI_DCTAR4 (*(volatile uint32_t*)(&_MBAR[0x8A1C])) +#define MCF_DSPI_DCTAR5 (*(volatile uint32_t*)(&_MBAR[0x8A20])) +#define MCF_DSPI_DCTAR6 (*(volatile uint32_t*)(&_MBAR[0x8A24])) +#define MCF_DSPI_DCTAR7 (*(volatile uint32_t*)(&_MBAR[0x8A28])) +#define MCF_DSPI_DSR (*(volatile uint32_t*)(&_MBAR[0x8A2C])) +#define MCF_DSPI_DIRSR (*(volatile uint32_t*)(&_MBAR[0x8A30])) +#define MCF_DSPI_DTFR (*(volatile uint32_t*)(&_MBAR[0x8A34])) +#define MCF_DSPI_DRFR (*(volatile uint32_t*)(&_MBAR[0x8A38])) +#define MCF_DSPI_DTFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A3C])) +#define MCF_DSPI_DTFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A40])) +#define MCF_DSPI_DTFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A44])) +#define MCF_DSPI_DTFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A48])) +#define MCF_DSPI_DRFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A7C])) +#define MCF_DSPI_DRFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A80])) +#define MCF_DSPI_DRFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A84])) +#define MCF_DSPI_DRFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A88])) +#define MCF_DSPI_DCTAR(x) (*(volatile uint32_t*)(&_MBAR[0x8A0C + ((x)*0x4)])) +#define MCF_DSPI_DTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A3C + ((x)*0x4)])) +#define MCF_DSPI_DRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A7C + ((x)*0x4)])) + + +/* Bit definitions and macros for MCF_DSPI_DMCR */ +#define MCF_DSPI_DMCR_HALT (0x1) +#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x3)<<0x8) +#define MCF_DSPI_DMCR_SMPL_PT_0CLK (0) +#define MCF_DSPI_DMCR_SMPL_PT_1CLK (0x100) +#define MCF_DSPI_DMCR_SMPL_PT_2CLK (0x200) +#define MCF_DSPI_DMCR_CRXF (0x400) +#define MCF_DSPI_DMCR_CTXF (0x800) +#define MCF_DSPI_DMCR_DRXF (0x1000) +#define MCF_DSPI_DMCR_DTXF (0x2000) +#define MCF_DSPI_DMCR_CSIS0 (0x10000) +#define MCF_DSPI_DMCR_CSIS2 (0x40000) +#define MCF_DSPI_DMCR_CSIS3 (0x80000) +#define MCF_DSPI_DMCR_CSIS5 (0x200000) +#define MCF_DSPI_DMCR_ROOE (0x1000000) +#define MCF_DSPI_DMCR_PCSSE (0x2000000) +#define MCF_DSPI_DMCR_MTFE (0x4000000) +#define MCF_DSPI_DMCR_FRZ (0x8000000) +#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x3)<<0x1C) +#define MCF_DSPI_DMCR_CSCK (0x40000000) +#define MCF_DSPI_DMCR_MSTR (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DTCR */ +#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_DSPI_DCTAR */ +#define MCF_DSPI_DCTAR_BR(x) (((x)&0xF)<<0) +#define MCF_DSPI_DCTAR_DT(x) (((x)&0xF)<<0x4) +#define MCF_DSPI_DCTAR_ASC(x) (((x)&0xF)<<0x8) +#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0xF)<<0xC) +#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x3)<<0x10) +#define MCF_DSPI_DCTAR_PBR_1CLK (0) +#define MCF_DSPI_DCTAR_PBR_3CLK (0x10000) +#define MCF_DSPI_DCTAR_PBR_5CLK (0x20000) +#define MCF_DSPI_DCTAR_PBR_7CLK (0x30000) +#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x3)<<0x12) +#define MCF_DSPI_DCTAR_PDT_1CLK (0) +#define MCF_DSPI_DCTAR_PDT_3CLK (0x40000) +#define MCF_DSPI_DCTAR_PDT_5CLK (0x80000) +#define MCF_DSPI_DCTAR_PDT_7CLK (0xC0000) +#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x3)<<0x14) +#define MCF_DSPI_DCTAR_PASC_1CLK (0) +#define MCF_DSPI_DCTAR_PASC_3CLK (0x100000) +#define MCF_DSPI_DCTAR_PASC_5CLK (0x200000) +#define MCF_DSPI_DCTAR_PASC_7CLK (0x300000) +#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x3)<<0x16) +#define MCF_DSPI_DCTAR_LSBFE (0x1000000) +#define MCF_DSPI_DCTAR_CPHA (0x2000000) +#define MCF_DSPI_DCTAR_CPOL (0x4000000) +#define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0xF)<<0x1B) + +/* Bit definitions and macros for MCF_DSPI_DSR */ +#define MCF_DSPI_DSR_RXPTR(x) (((x)&0xF)<<0) +#define MCF_DSPI_DSR_RXCTR(x) (((x)&0xF)<<0x4) +#define MCF_DSPI_DSR_TXPTR(x) (((x)&0xF)<<0x8) +#define MCF_DSPI_DSR_TXCTR(x) (((x)&0xF)<<0xC) +#define MCF_DSPI_DSR_RFDF (0x20000) +#define MCF_DSPI_DSR_RFOF (0x80000) +#define MCF_DSPI_DSR_TFFF (0x2000000) +#define MCF_DSPI_DSR_TFUF (0x8000000) +#define MCF_DSPI_DSR_EOQF (0x10000000) +#define MCF_DSPI_DSR_TXRXS (0x40000000) +#define MCF_DSPI_DSR_TCF (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DIRSR */ +#define MCF_DSPI_DIRSR_RFDFS (0x10000) +#define MCF_DSPI_DIRSR_RFDFE (0x20000) +#define MCF_DSPI_DIRSR_RFOFE (0x80000) +#define MCF_DSPI_DIRSR_TFFFS (0x1000000) +#define MCF_DSPI_DIRSR_TFFFE (0x2000000) +#define MCF_DSPI_DIRSR_TFUFE (0x8000000) +#define MCF_DSPI_DIRSR_EOQFE (0x10000000) +#define MCF_DSPI_DIRSR_TCFE (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DTFR */ +#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0xFFFF)<<0) +#define MCF_DSPI_DTFR_CS0 (0x10000) +#define MCF_DSPI_DTFR_CS2 (0x40000) +#define MCF_DSPI_DTFR_CS3 (0x80000) +#define MCF_DSPI_DTFR_CS5 (0x200000) +#define MCF_DSPI_DTFR_CTCNT (0x4000000) +#define MCF_DSPI_DTFR_EOQ (0x8000000) +#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x7)<<0x1C) +#define MCF_DSPI_DTFR_CONT (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DRFR */ +#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_DSPI_DTFDR */ +#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0xFFFF)<<0) +#define MCF_DSPI_DTFDR_TXCMD(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_DSPI_DRFDR */ +#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0xFFFF)<<0) + + +#endif /* __MCF5475_DSPI_H__ */ diff --git a/tos/pci_mem/include/MCF5475_EPORT.h b/tos/pci_mem/include/MCF5475_EPORT.h new file mode 100644 index 0000000..6506196 --- /dev/null +++ b/tos/pci_mem/include/MCF5475_EPORT.h @@ -0,0 +1,123 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_EPORT_H__ +#define __MCF5475_EPORT_H__ + + +/********************************************************************* +* +* Edge Port Module (EPORT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_EPORT_EPPAR (*(volatile uint16_t*)(&_MBAR[0xF00])) +#define MCF_EPORT_EPDDR (*(volatile uint8_t *)(&_MBAR[0xF04])) +#define MCF_EPORT_EPIER (*(volatile uint8_t *)(&_MBAR[0xF05])) +#define MCF_EPORT_EPDR (*(volatile uint8_t *)(&_MBAR[0xF08])) +#define MCF_EPORT_EPPDR (*(volatile uint8_t *)(&_MBAR[0xF09])) +#define MCF_EPORT_EPFR (*(volatile uint8_t *)(&_MBAR[0xF0C])) + + + +/* Bit definitions and macros for MCF_EPORT_EPPAR */ +#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2) +#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4) +#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8) +#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC) +#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4) +#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10) +#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20) +#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30) +#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6) +#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40) +#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80) +#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0) +#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8) +#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100) +#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200) +#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300) +#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA) +#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400) +#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800) +#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00) +#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC) +#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) +#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) +#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) +#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE) +#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) +#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) +#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) +#define MCF_EPORT_EPPAR_LEVEL (0) +#define MCF_EPORT_EPPAR_RISING (0x1) +#define MCF_EPORT_EPPAR_FALLING (0x2) +#define MCF_EPORT_EPPAR_BOTH (0x3) + +/* Bit definitions and macros for MCF_EPORT_EPDDR */ +#define MCF_EPORT_EPDDR_EPDD1 (0x2) +#define MCF_EPORT_EPDDR_EPDD2 (0x4) +#define MCF_EPORT_EPDDR_EPDD3 (0x8) +#define MCF_EPORT_EPDDR_EPDD4 (0x10) +#define MCF_EPORT_EPDDR_EPDD5 (0x20) +#define MCF_EPORT_EPDDR_EPDD6 (0x40) +#define MCF_EPORT_EPDDR_EPDD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPIER */ +#define MCF_EPORT_EPIER_EPIE1 (0x2) +#define MCF_EPORT_EPIER_EPIE2 (0x4) +#define MCF_EPORT_EPIER_EPIE3 (0x8) +#define MCF_EPORT_EPIER_EPIE4 (0x10) +#define MCF_EPORT_EPIER_EPIE5 (0x20) +#define MCF_EPORT_EPIER_EPIE6 (0x40) +#define MCF_EPORT_EPIER_EPIE7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPDR */ +#define MCF_EPORT_EPDR_EPD1 (0x2) +#define MCF_EPORT_EPDR_EPD2 (0x4) +#define MCF_EPORT_EPDR_EPD3 (0x8) +#define MCF_EPORT_EPDR_EPD4 (0x10) +#define MCF_EPORT_EPDR_EPD5 (0x20) +#define MCF_EPORT_EPDR_EPD6 (0x40) +#define MCF_EPORT_EPDR_EPD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPPDR */ +#define MCF_EPORT_EPPDR_EPPD1 (0x2) +#define MCF_EPORT_EPPDR_EPPD2 (0x4) +#define MCF_EPORT_EPPDR_EPPD3 (0x8) +#define MCF_EPORT_EPPDR_EPPD4 (0x10) +#define MCF_EPORT_EPPDR_EPPD5 (0x20) +#define MCF_EPORT_EPPDR_EPPD6 (0x40) +#define MCF_EPORT_EPPDR_EPPD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPFR */ +#define MCF_EPORT_EPFR_EPF1 (0x2) +#define MCF_EPORT_EPFR_EPF2 (0x4) +#define MCF_EPORT_EPFR_EPF3 (0x8) +#define MCF_EPORT_EPFR_EPF4 (0x10) +#define MCF_EPORT_EPFR_EPF5 (0x20) +#define MCF_EPORT_EPFR_EPF6 (0x40) +#define MCF_EPORT_EPFR_EPF7 (0x80) + + +#endif /* __MCF5475_EPORT_H__ */ diff --git a/tos/pci_mem/include/MCF5475_FBCS.h b/tos/pci_mem/include/MCF5475_FBCS.h new file mode 100644 index 0000000..37daf00 --- /dev/null +++ b/tos/pci_mem/include/MCF5475_FBCS.h @@ -0,0 +1,100 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_FBCS_H__ +#define __MCF5475_FBCS_H__ + + +/********************************************************************* +* +* FlexBus Chip Select Module (FBCS) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_FBCS0_CSAR (*(volatile uint32_t*)(&_MBAR[0x500])) +#define MCF_FBCS0_CSMR (*(volatile uint32_t*)(&_MBAR[0x504])) +#define MCF_FBCS0_CSCR (*(volatile uint32_t*)(&_MBAR[0x508])) + +#define MCF_FBCS1_CSAR (*(volatile uint32_t*)(&_MBAR[0x50C])) +#define MCF_FBCS1_CSMR (*(volatile uint32_t*)(&_MBAR[0x510])) +#define MCF_FBCS1_CSCR (*(volatile uint32_t*)(&_MBAR[0x514])) + +#define MCF_FBCS2_CSAR (*(volatile uint32_t*)(&_MBAR[0x518])) +#define MCF_FBCS2_CSMR (*(volatile uint32_t*)(&_MBAR[0x51C])) +#define MCF_FBCS2_CSCR (*(volatile uint32_t*)(&_MBAR[0x520])) + +#define MCF_FBCS3_CSAR (*(volatile uint32_t*)(&_MBAR[0x524])) +#define MCF_FBCS3_CSMR (*(volatile uint32_t*)(&_MBAR[0x528])) +#define MCF_FBCS3_CSCR (*(volatile uint32_t*)(&_MBAR[0x52C])) + +#define MCF_FBCS4_CSAR (*(volatile uint32_t*)(&_MBAR[0x530])) +#define MCF_FBCS4_CSMR (*(volatile uint32_t*)(&_MBAR[0x534])) +#define MCF_FBCS4_CSCR (*(volatile uint32_t*)(&_MBAR[0x538])) + +#define MCF_FBCS5_CSAR (*(volatile uint32_t*)(&_MBAR[0x53C])) +#define MCF_FBCS5_CSMR (*(volatile uint32_t*)(&_MBAR[0x540])) +#define MCF_FBCS5_CSCR (*(volatile uint32_t*)(&_MBAR[0x544])) + +#define MCF_FBCS_CSAR(x) (*(volatile uint32_t*)(&_MBAR[0x500 + ((x)*0xC)])) +#define MCF_FBCS_CSMR(x) (*(volatile uint32_t*)(&_MBAR[0x504 + ((x)*0xC)])) +#define MCF_FBCS_CSCR(x) (*(volatile uint32_t*)(&_MBAR[0x508 + ((x)*0xC)])) + + +/* Bit definitions and macros for MCF_FBCS_CSAR */ +#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) + +/* Bit definitions and macros for MCF_FBCS_CSMR */ +#define MCF_FBCS_CSMR_V (0x1) +#define MCF_FBCS_CSMR_WP (0x100) +#define MCF_FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<0x10) +#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) +#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) +#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) +#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) +#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) +#define MCF_FBCS_CSMR_BAM_256M (0xFFF0000) +#define MCF_FBCS_CSMR_BAM_128M (0x7FF0000) +#define MCF_FBCS_CSMR_BAM_64M (0x3FF0000) +#define MCF_FBCS_CSMR_BAM_32M (0x1FF0000) +#define MCF_FBCS_CSMR_BAM_16M (0xFF0000) +#define MCF_FBCS_CSMR_BAM_8M (0x7F0000) +#define MCF_FBCS_CSMR_BAM_4M (0x3F0000) +#define MCF_FBCS_CSMR_BAM_2M (0x1F0000) +#define MCF_FBCS_CSMR_BAM_1M (0xF0000) +#define MCF_FBCS_CSMR_BAM_1024K (0xF0000) +#define MCF_FBCS_CSMR_BAM_512K (0x70000) +#define MCF_FBCS_CSMR_BAM_256K (0x30000) +#define MCF_FBCS_CSMR_BAM_128K (0x10000) +#define MCF_FBCS_CSMR_BAM_64K (0) + +/* Bit definitions and macros for MCF_FBCS_CSCR */ +#define MCF_FBCS_CSCR_BSTW (0x8) +#define MCF_FBCS_CSCR_BSTR (0x10) +#define MCF_FBCS_CSCR_BEM (0x20) +#define MCF_FBCS_CSCR_PS(x) (((x)&0x3)<<0x6) +#define MCF_FBCS_CSCR_PS_32 (0) +#define MCF_FBCS_CSCR_PS_8 (0x40) +#define MCF_FBCS_CSCR_PS_16 (0x80) +#define MCF_FBCS_CSCR_AA (0x100) +#define MCF_FBCS_CSCR_WS(x) (((x)&0x3F)<<0xA) +#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x3)<<0x10) +#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x3)<<0x12) +#define MCF_FBCS_CSCR_ASET(x) (((x)&0x3)<<0x14) +#define MCF_FBCS_CSCR_SWSEN (0x800000) +#define MCF_FBCS_CSCR_SWS(x) (((x)&0x3F)<<0x1A) + + +#endif /* __MCF5475_FBCS_H__ */ diff --git a/tos/pci_mem/include/MCF5475_FEC.h b/tos/pci_mem/include/MCF5475_FEC.h new file mode 100644 index 0000000..fdd9403 --- /dev/null +++ b/tos/pci_mem/include/MCF5475_FEC.h @@ -0,0 +1,680 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_FEC_H__ +#define __MCF5475_FEC_H__ + + +/********************************************************************* +* +* Fast Ethernet Controller(FEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_FEC0_EIR (*(volatile uint32_t*)(&_MBAR[0x9004])) +#define MCF_FEC0_EIMR (*(volatile uint32_t*)(&_MBAR[0x9008])) +#define MCF_FEC0_ECR (*(volatile uint32_t*)(&_MBAR[0x9024])) +#define MCF_FEC0_MMFR (*(volatile uint32_t*)(&_MBAR[0x9040])) +#define MCF_FEC0_MSCR (*(volatile uint32_t*)(&_MBAR[0x9044])) +#define MCF_FEC0_MIBC (*(volatile uint32_t*)(&_MBAR[0x9064])) +#define MCF_FEC0_RCR (*(volatile uint32_t*)(&_MBAR[0x9084])) +#define MCF_FEC0_RHR (*(volatile uint32_t*)(&_MBAR[0x9088])) +#define MCF_FEC0_TCR (*(volatile uint32_t*)(&_MBAR[0x90C4])) +#define MCF_FEC0_PALR (*(volatile uint32_t*)(&_MBAR[0x90E4])) +#define MCF_FEC0_PAHR (*(volatile uint32_t*)(&_MBAR[0x90E8])) +#define MCF_FEC0_OPD (*(volatile uint32_t*)(&_MBAR[0x90EC])) +#define MCF_FEC0_IAUR (*(volatile uint32_t*)(&_MBAR[0x9118])) +#define MCF_FEC0_IALR (*(volatile uint32_t*)(&_MBAR[0x911C])) +#define MCF_FEC0_GAUR (*(volatile uint32_t*)(&_MBAR[0x9120])) +#define MCF_FEC0_GALR (*(volatile uint32_t*)(&_MBAR[0x9124])) +#define MCF_FEC0_FECTFWR (*(volatile uint32_t*)(&_MBAR[0x9144])) +#define MCF_FEC0_FECRFDR (*(volatile uint32_t*)(&_MBAR[0x9184])) +#define MCF_FEC0_FECRFSR (*(volatile uint32_t*)(&_MBAR[0x9188])) +#define MCF_FEC0_FECRFCR (*(volatile uint32_t*)(&_MBAR[0x918C])) +#define MCF_FEC0_FECRLRFP (*(volatile uint32_t*)(&_MBAR[0x9190])) +#define MCF_FEC0_FECRLWFP (*(volatile uint32_t*)(&_MBAR[0x9194])) +#define MCF_FEC0_FECRFAR (*(volatile uint32_t*)(&_MBAR[0x9198])) +#define MCF_FEC0_FECRFRP (*(volatile uint32_t*)(&_MBAR[0x919C])) +#define MCF_FEC0_FECRFWP (*(volatile uint32_t*)(&_MBAR[0x91A0])) +#define MCF_FEC0_FECTFDR (*(volatile uint32_t*)(&_MBAR[0x91A4])) +#define MCF_FEC0_FECTFSR (*(volatile uint32_t*)(&_MBAR[0x91A8])) +#define MCF_FEC0_FECTFCR (*(volatile uint32_t*)(&_MBAR[0x91AC])) +#define MCF_FEC0_FECTLRFP (*(volatile uint32_t*)(&_MBAR[0x91B0])) +#define MCF_FEC0_FECTLWFP (*(volatile uint32_t*)(&_MBAR[0x91B4])) +#define MCF_FEC0_FECTFAR (*(volatile uint32_t*)(&_MBAR[0x91B8])) +#define MCF_FEC0_FECTFRP (*(volatile uint32_t*)(&_MBAR[0x91BC])) +#define MCF_FEC0_FECTFWP (*(volatile uint32_t*)(&_MBAR[0x91C0])) +#define MCF_FEC0_FECFRST (*(volatile uint32_t*)(&_MBAR[0x91C4])) +#define MCF_FEC0_FECCTCWR (*(volatile uint32_t*)(&_MBAR[0x91C8])) +#define MCF_FEC0_RMON_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9200])) +#define MCF_FEC0_RMON_T_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9204])) +#define MCF_FEC0_RMON_T_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9208])) +#define MCF_FEC0_RMON_T_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x920C])) +#define MCF_FEC0_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9210])) +#define MCF_FEC0_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9214])) +#define MCF_FEC0_RMON_T_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9218])) +#define MCF_FEC0_RMON_T_FRAG (*(volatile uint32_t*)(&_MBAR[0x921C])) +#define MCF_FEC0_RMON_T_JAB (*(volatile uint32_t*)(&_MBAR[0x9220])) +#define MCF_FEC0_RMON_T_COL (*(volatile uint32_t*)(&_MBAR[0x9224])) +#define MCF_FEC0_RMON_T_P64 (*(volatile uint32_t*)(&_MBAR[0x9228])) +#define MCF_FEC0_RMON_T_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x922C])) +#define MCF_FEC0_RMON_T_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9230])) +#define MCF_FEC0_RMON_T_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9234])) +#define MCF_FEC0_RMON_T_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9238])) +#define MCF_FEC0_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x923C])) +#define MCF_FEC0_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9240])) +#define MCF_FEC0_RMON_T_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9244])) +#define MCF_FEC0_IEEE_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9248])) +#define MCF_FEC0_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x924C])) +#define MCF_FEC0_IEEE_T_1COL (*(volatile uint32_t*)(&_MBAR[0x9250])) +#define MCF_FEC0_IEEE_T_MCOL (*(volatile uint32_t*)(&_MBAR[0x9254])) +#define MCF_FEC0_IEEE_T_DEF (*(volatile uint32_t*)(&_MBAR[0x9258])) +#define MCF_FEC0_IEEE_T_LCOL (*(volatile uint32_t*)(&_MBAR[0x925C])) +#define MCF_FEC0_IEEE_T_EXCOL (*(volatile uint32_t*)(&_MBAR[0x9260])) +#define MCF_FEC0_IEEE_T_MACERR (*(volatile uint32_t*)(&_MBAR[0x9264])) +#define MCF_FEC0_IEEE_T_CSERR (*(volatile uint32_t*)(&_MBAR[0x9268])) +#define MCF_FEC0_IEEE_T_SQE (*(volatile uint32_t*)(&_MBAR[0x926C])) +#define MCF_FEC0_IEEE_T_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9270])) +#define MCF_FEC0_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9274])) +#define MCF_FEC0_RMON_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9280])) +#define MCF_FEC0_RMON_R_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9284])) +#define MCF_FEC0_RMON_R_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9288])) +#define MCF_FEC0_RMON_R_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x928C])) +#define MCF_FEC0_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9290])) +#define MCF_FEC0_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9294])) +#define MCF_FEC0_RMON_R_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9298])) +#define MCF_FEC0_RMON_R_FRAG (*(volatile uint32_t*)(&_MBAR[0x929C])) +#define MCF_FEC0_RMON_R_JAB (*(volatile uint32_t*)(&_MBAR[0x92A0])) +#define MCF_FEC0_RMON_R_RESVD_0 (*(volatile uint32_t*)(&_MBAR[0x92A4])) +#define MCF_FEC0_RMON_R_P64 (*(volatile uint32_t*)(&_MBAR[0x92A8])) +#define MCF_FEC0_RMON_R_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x92AC])) +#define MCF_FEC0_RMON_R_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x92B0])) +#define MCF_FEC0_RMON_R_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x92B4])) +#define MCF_FEC0_RMON_R_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x92B8])) +#define MCF_FEC0_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x92BC])) +#define MCF_FEC0_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x92C0])) +#define MCF_FEC0_RMON_R_OCTETS (*(volatile uint32_t*)(&_MBAR[0x92C4])) +#define MCF_FEC0_IEEE_R_DROP (*(volatile uint32_t*)(&_MBAR[0x92C8])) +#define MCF_FEC0_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x92CC])) +#define MCF_FEC0_IEEE_R_CRC (*(volatile uint32_t*)(&_MBAR[0x92D0])) +#define MCF_FEC0_IEEE_R_ALIGN (*(volatile uint32_t*)(&_MBAR[0x92D4])) +#define MCF_FEC0_IEEE_R_MACERR (*(volatile uint32_t*)(&_MBAR[0x92D8])) +#define MCF_FEC0_IEEE_R_FDXFC (*(volatile uint32_t*)(&_MBAR[0x92DC])) +#define MCF_FEC0_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x92E0])) + +#define MCF_FEC1_EIR (*(volatile uint32_t*)(&_MBAR[0x9804])) +#define MCF_FEC1_EIMR (*(volatile uint32_t*)(&_MBAR[0x9808])) +#define MCF_FEC1_ECR (*(volatile uint32_t*)(&_MBAR[0x9824])) +#define MCF_FEC1_MMFR (*(volatile uint32_t*)(&_MBAR[0x9840])) +#define MCF_FEC1_MSCR (*(volatile uint32_t*)(&_MBAR[0x9844])) +#define MCF_FEC1_MIBC (*(volatile uint32_t*)(&_MBAR[0x9864])) +#define MCF_FEC1_RCR (*(volatile uint32_t*)(&_MBAR[0x9884])) +#define MCF_FEC1_RHR (*(volatile uint32_t*)(&_MBAR[0x9888])) +#define MCF_FEC1_TCR (*(volatile uint32_t*)(&_MBAR[0x98C4])) +#define MCF_FEC1_PALR (*(volatile uint32_t*)(&_MBAR[0x98E4])) +#define MCF_FEC1_PAHR (*(volatile uint32_t*)(&_MBAR[0x98E8])) +#define MCF_FEC1_OPD (*(volatile uint32_t*)(&_MBAR[0x98EC])) +#define MCF_FEC1_IAUR (*(volatile uint32_t*)(&_MBAR[0x9918])) +#define MCF_FEC1_IALR (*(volatile uint32_t*)(&_MBAR[0x991C])) +#define MCF_FEC1_GAUR (*(volatile uint32_t*)(&_MBAR[0x9920])) +#define MCF_FEC1_GALR (*(volatile uint32_t*)(&_MBAR[0x9924])) +#define MCF_FEC1_FECTFWR (*(volatile uint32_t*)(&_MBAR[0x9944])) +#define MCF_FEC1_FECRFDR (*(volatile uint32_t*)(&_MBAR[0x9984])) +#define MCF_FEC1_FECRFSR (*(volatile uint32_t*)(&_MBAR[0x9988])) +#define MCF_FEC1_FECRFCR (*(volatile uint32_t*)(&_MBAR[0x998C])) +#define MCF_FEC1_FECRLRFP (*(volatile uint32_t*)(&_MBAR[0x9990])) +#define MCF_FEC1_FECRLWFP (*(volatile uint32_t*)(&_MBAR[0x9994])) +#define MCF_FEC1_FECRFAR (*(volatile uint32_t*)(&_MBAR[0x9998])) +#define MCF_FEC1_FECRFRP (*(volatile uint32_t*)(&_MBAR[0x999C])) +#define MCF_FEC1_FECRFWP (*(volatile uint32_t*)(&_MBAR[0x99A0])) +#define MCF_FEC1_FECTFDR (*(volatile uint32_t*)(&_MBAR[0x99A4])) +#define MCF_FEC1_FECTFSR (*(volatile uint32_t*)(&_MBAR[0x99A8])) +#define MCF_FEC1_FECTFCR (*(volatile uint32_t*)(&_MBAR[0x99AC])) +#define MCF_FEC1_FECTLRFP (*(volatile uint32_t*)(&_MBAR[0x99B0])) +#define MCF_FEC1_FECTLWFP (*(volatile uint32_t*)(&_MBAR[0x99B4])) +#define MCF_FEC1_FECTFAR (*(volatile uint32_t*)(&_MBAR[0x99B8])) +#define MCF_FEC1_FECTFRP (*(volatile uint32_t*)(&_MBAR[0x99BC])) +#define MCF_FEC1_FECTFWP (*(volatile uint32_t*)(&_MBAR[0x99C0])) +#define MCF_FEC1_FECFRST (*(volatile uint32_t*)(&_MBAR[0x99C4])) +#define MCF_FEC1_FECCTCWR (*(volatile uint32_t*)(&_MBAR[0x99C8])) +#define MCF_FEC1_RMON_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9A00])) +#define MCF_FEC1_RMON_T_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9A04])) +#define MCF_FEC1_RMON_T_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A08])) +#define MCF_FEC1_RMON_T_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A0C])) +#define MCF_FEC1_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9A10])) +#define MCF_FEC1_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A14])) +#define MCF_FEC1_RMON_T_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A18])) +#define MCF_FEC1_RMON_T_FRAG (*(volatile uint32_t*)(&_MBAR[0x9A1C])) +#define MCF_FEC1_RMON_T_JAB (*(volatile uint32_t*)(&_MBAR[0x9A20])) +#define MCF_FEC1_RMON_T_COL (*(volatile uint32_t*)(&_MBAR[0x9A24])) +#define MCF_FEC1_RMON_T_P64 (*(volatile uint32_t*)(&_MBAR[0x9A28])) +#define MCF_FEC1_RMON_T_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x9A2C])) +#define MCF_FEC1_RMON_T_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9A30])) +#define MCF_FEC1_RMON_T_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9A34])) +#define MCF_FEC1_RMON_T_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9A38])) +#define MCF_FEC1_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x9A3C])) +#define MCF_FEC1_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9A40])) +#define MCF_FEC1_RMON_T_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9A44])) +#define MCF_FEC1_IEEE_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9A48])) +#define MCF_FEC1_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x9A4C])) +#define MCF_FEC1_IEEE_T_1COL (*(volatile uint32_t*)(&_MBAR[0x9A50])) +#define MCF_FEC1_IEEE_T_MCOL (*(volatile uint32_t*)(&_MBAR[0x9A54])) +#define MCF_FEC1_IEEE_T_DEF (*(volatile uint32_t*)(&_MBAR[0x9A58])) +#define MCF_FEC1_IEEE_T_LCOL (*(volatile uint32_t*)(&_MBAR[0x9A5C])) +#define MCF_FEC1_IEEE_T_EXCOL (*(volatile uint32_t*)(&_MBAR[0x9A60])) +#define MCF_FEC1_IEEE_T_MACERR (*(volatile uint32_t*)(&_MBAR[0x9A64])) +#define MCF_FEC1_IEEE_T_CSERR (*(volatile uint32_t*)(&_MBAR[0x9A68])) +#define MCF_FEC1_IEEE_T_SQE (*(volatile uint32_t*)(&_MBAR[0x9A6C])) +#define MCF_FEC1_IEEE_T_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9A70])) +#define MCF_FEC1_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9A74])) +#define MCF_FEC1_RMON_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9A80])) +#define MCF_FEC1_RMON_R_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9A84])) +#define MCF_FEC1_RMON_R_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A88])) +#define MCF_FEC1_RMON_R_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A8C])) +#define MCF_FEC1_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9A90])) +#define MCF_FEC1_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A94])) +#define MCF_FEC1_RMON_R_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A98])) +#define MCF_FEC1_RMON_R_FRAG (*(volatile uint32_t*)(&_MBAR[0x9A9C])) +#define MCF_FEC1_RMON_R_JAB (*(volatile uint32_t*)(&_MBAR[0x9AA0])) +#define MCF_FEC1_RMON_R_RESVD_0 (*(volatile uint32_t*)(&_MBAR[0x9AA4])) +#define MCF_FEC1_RMON_R_P64 (*(volatile uint32_t*)(&_MBAR[0x9AA8])) +#define MCF_FEC1_RMON_R_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x9AAC])) +#define MCF_FEC1_RMON_R_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9AB0])) +#define MCF_FEC1_RMON_R_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9AB4])) +#define MCF_FEC1_RMON_R_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9AB8])) +#define MCF_FEC1_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x9ABC])) +#define MCF_FEC1_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9AC0])) +#define MCF_FEC1_RMON_R_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9AC4])) +#define MCF_FEC1_IEEE_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9AC8])) +#define MCF_FEC1_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x9ACC])) +#define MCF_FEC1_IEEE_R_CRC (*(volatile uint32_t*)(&_MBAR[0x9AD0])) +#define MCF_FEC1_IEEE_R_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9AD4])) +#define MCF_FEC1_IEEE_R_MACERR (*(volatile uint32_t*)(&_MBAR[0x9AD8])) +#define MCF_FEC1_IEEE_R_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9ADC])) +#define MCF_FEC1_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9AE0])) + +#define MCF_FEC_EIR(x) (*(volatile uint32_t*)(&_MBAR[0x9004 + ((x)*0x800)])) +#define MCF_FEC_EIMR(x) (*(volatile uint32_t*)(&_MBAR[0x9008 + ((x)*0x800)])) +#define MCF_FEC_ECR(x) (*(volatile uint32_t*)(&_MBAR[0x9024 + ((x)*0x800)])) +#define MCF_FEC_MMFR(x) (*(volatile uint32_t*)(&_MBAR[0x9040 + ((x)*0x800)])) +#define MCF_FEC_MSCR(x) (*(volatile uint32_t*)(&_MBAR[0x9044 + ((x)*0x800)])) +#define MCF_FEC_MIBC(x) (*(volatile uint32_t*)(&_MBAR[0x9064 + ((x)*0x800)])) +#define MCF_FEC_RCR(x) (*(volatile uint32_t*)(&_MBAR[0x9084 + ((x)*0x800)])) +#define MCF_FEC_RHR(x) (*(volatile uint32_t*)(&_MBAR[0x9088 + ((x)*0x800)])) +#define MCF_FEC_TCR(x) (*(volatile uint32_t*)(&_MBAR[0x90C4 + ((x)*0x800)])) +#define MCF_FEC_PALR(x) (*(volatile uint32_t*)(&_MBAR[0x90E4 + ((x)*0x800)])) +#define MCF_FEC_PAHR(x) (*(volatile uint32_t*)(&_MBAR[0x90E8 + ((x)*0x800)])) +#define MCF_FEC_OPD(x) (*(volatile uint32_t*)(&_MBAR[0x90EC + ((x)*0x800)])) +#define MCF_FEC_IAUR(x) (*(volatile uint32_t*)(&_MBAR[0x9118 + ((x)*0x800)])) +#define MCF_FEC_IALR(x) (*(volatile uint32_t*)(&_MBAR[0x911C + ((x)*0x800)])) +#define MCF_FEC_GAUR(x) (*(volatile uint32_t*)(&_MBAR[0x9120 + ((x)*0x800)])) +#define MCF_FEC_GALR(x) (*(volatile uint32_t*)(&_MBAR[0x9124 + ((x)*0x800)])) +#define MCF_FEC_FECTFWR(x) (*(volatile uint32_t*)(&_MBAR[0x9144 + ((x)*0x800)])) +#define MCF_FEC_FECRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x9184 + ((x)*0x800)])) +#define MCF_FEC_FECRFSR(x) (*(volatile uint32_t*)(&_MBAR[0x9188 + ((x)*0x800)])) +#define MCF_FEC_FECRFCR(x) (*(volatile uint32_t*)(&_MBAR[0x918C + ((x)*0x800)])) +#define MCF_FEC_FECRLRFP(x) (*(volatile uint32_t*)(&_MBAR[0x9190 + ((x)*0x800)])) +#define MCF_FEC_FECRLWFP(x) (*(volatile uint32_t*)(&_MBAR[0x9194 + ((x)*0x800)])) +#define MCF_FEC_FECRFAR(x) (*(volatile uint32_t*)(&_MBAR[0x9198 + ((x)*0x800)])) +#define MCF_FEC_FECRFRP(x) (*(volatile uint32_t*)(&_MBAR[0x919C + ((x)*0x800)])) +#define MCF_FEC_FECRFWP(x) (*(volatile uint32_t*)(&_MBAR[0x91A0 + ((x)*0x800)])) +#define MCF_FEC_FECTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x91A4 + ((x)*0x800)])) +#define MCF_FEC_FECTFSR(x) (*(volatile uint32_t*)(&_MBAR[0x91A8 + ((x)*0x800)])) +#define MCF_FEC_FECTFCR(x) (*(volatile uint32_t*)(&_MBAR[0x91AC + ((x)*0x800)])) +#define MCF_FEC_FECTLRFP(x) (*(volatile uint32_t*)(&_MBAR[0x91B0 + ((x)*0x800)])) +#define MCF_FEC_FECTLWFP(x) (*(volatile uint32_t*)(&_MBAR[0x91B4 + ((x)*0x800)])) +#define MCF_FEC_FECTFAR(x) (*(volatile uint32_t*)(&_MBAR[0x91B8 + ((x)*0x800)])) +#define MCF_FEC_FECTFRP(x) (*(volatile uint32_t*)(&_MBAR[0x91BC + ((x)*0x800)])) +#define MCF_FEC_FECTFWP(x) (*(volatile uint32_t*)(&_MBAR[0x91C0 + ((x)*0x800)])) +#define MCF_FEC_FECFRST(x) (*(volatile uint32_t*)(&_MBAR[0x91C4 + ((x)*0x800)])) +#define MCF_FEC_FECCTCWR(x) (*(volatile uint32_t*)(&_MBAR[0x91C8 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9200 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_PACKETS(x) (*(volatile uint32_t*)(&_MBAR[0x9204 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_BC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x9208 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_MC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x920C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x9210 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9214 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_OVERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9218 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_FRAG(x) (*(volatile uint32_t*)(&_MBAR[0x921C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_JAB(x) (*(volatile uint32_t*)(&_MBAR[0x9220 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_COL(x) (*(volatile uint32_t*)(&_MBAR[0x9224 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P64(x) (*(volatile uint32_t*)(&_MBAR[0x9228 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P65TO127(x) (*(volatile uint32_t*)(&_MBAR[0x922C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P128TO255(x) (*(volatile uint32_t*)(&_MBAR[0x9230 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P256TO511(x) (*(volatile uint32_t*)(&_MBAR[0x9234 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P512TO1023(x) (*(volatile uint32_t*)(&_MBAR[0x9238 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P1024TO2047(x) (*(volatile uint32_t*)(&_MBAR[0x923C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P_GTE2048(x) (*(volatile uint32_t*)(&_MBAR[0x9240 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_OCTETS(x) (*(volatile uint32_t*)(&_MBAR[0x9244 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9248 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(volatile uint32_t*)(&_MBAR[0x924C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_1COL(x) (*(volatile uint32_t*)(&_MBAR[0x9250 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_MCOL(x) (*(volatile uint32_t*)(&_MBAR[0x9254 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_DEF(x) (*(volatile uint32_t*)(&_MBAR[0x9258 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_LCOL(x) (*(volatile uint32_t*)(&_MBAR[0x925C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_EXCOL(x) (*(volatile uint32_t*)(&_MBAR[0x9260 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_MACERR(x) (*(volatile uint32_t*)(&_MBAR[0x9264 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_CSERR(x) (*(volatile uint32_t*)(&_MBAR[0x9268 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_SQE(x) (*(volatile uint32_t*)(&_MBAR[0x926C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_FDXFC(x) (*(volatile uint32_t*)(&_MBAR[0x9270 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(volatile uint32_t*)(&_MBAR[0x9274 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9280 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_PACKETS(x) (*(volatile uint32_t*)(&_MBAR[0x9284 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_BC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x9288 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_MC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x928C + ((x)*0x800)])) +#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x9290 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9294 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_OVERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9298 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_FRAG(x) (*(volatile uint32_t*)(&_MBAR[0x929C + ((x)*0x800)])) +#define MCF_FEC_RMON_R_JAB(x) (*(volatile uint32_t*)(&_MBAR[0x92A0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_RESVD_0(x) (*(volatile uint32_t*)(&_MBAR[0x92A4 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P64(x) (*(volatile uint32_t*)(&_MBAR[0x92A8 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P65TO127(x) (*(volatile uint32_t*)(&_MBAR[0x92AC + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P128TO255(x) (*(volatile uint32_t*)(&_MBAR[0x92B0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P256TO511(x) (*(volatile uint32_t*)(&_MBAR[0x92B4 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P512TO1023(x) (*(volatile uint32_t*)(&_MBAR[0x92B8 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P1024TO2047(x) (*(volatile uint32_t*)(&_MBAR[0x92BC + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P_GTE2048(x) (*(volatile uint32_t*)(&_MBAR[0x92C0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_OCTETS(x) (*(volatile uint32_t*)(&_MBAR[0x92C4 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x92C8 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(volatile uint32_t*)(&_MBAR[0x92CC + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_CRC(x) (*(volatile uint32_t*)(&_MBAR[0x92D0 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x92D4 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_MACERR(x) (*(volatile uint32_t*)(&_MBAR[0x92D8 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_FDXFC(x) (*(volatile uint32_t*)(&_MBAR[0x92DC + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(volatile uint32_t*)(&_MBAR[0x92E0 + ((x)*0x800)])) + + +/* Bit definitions and macros for MCF_FEC_EIR */ +#define MCF_FEC_EIR_RFERR (0x20000) +#define MCF_FEC_EIR_XFERR (0x40000) +#define MCF_FEC_EIR_XFUN (0x80000) +#define MCF_FEC_EIR_RL (0x100000) +#define MCF_FEC_EIR_LC (0x200000) +#define MCF_FEC_EIR_MII (0x800000) +#define MCF_FEC_EIR_TXF (0x8000000) +#define MCF_FEC_EIR_GRA (0x10000000) +#define MCF_FEC_EIR_BABT (0x20000000) +#define MCF_FEC_EIR_BABR (0x40000000) +#define MCF_FEC_EIR_HBERR (0x80000000) +#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF_FEC_EIMR */ +#define MCF_FEC_EIMR_RFERR (0x20000) +#define MCF_FEC_EIMR_XFERR (0x40000) +#define MCF_FEC_EIMR_XFUN (0x80000) +#define MCF_FEC_EIMR_RL (0x100000) +#define MCF_FEC_EIMR_LC (0x200000) +#define MCF_FEC_EIMR_MII (0x800000) +#define MCF_FEC_EIMR_TXF (0x8000000) +#define MCF_FEC_EIMR_GRA (0x10000000) +#define MCF_FEC_EIMR_BABT (0x20000000) +#define MCF_FEC_EIMR_BABR (0x40000000) +#define MCF_FEC_EIMR_HBERR (0x80000000) +#define MCF_FEC_EIMR_MASK_ALL (0) +#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF_FEC_ECR */ +#define MCF_FEC_ECR_RESET (0x1) +#define MCF_FEC_ECR_ETHER_EN (0x2) + +/* Bit definitions and macros for MCF_FEC_MMFR */ +#define MCF_FEC_MMFR_DATA(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_MMFR_TA(x) (((x)&0x3)<<0x10) +#define MCF_FEC_MMFR_TA_10 (0x20000) +#define MCF_FEC_MMFR_RA(x) (((x)&0x1F)<<0x12) +#define MCF_FEC_MMFR_PA(x) (((x)&0x1F)<<0x17) +#define MCF_FEC_MMFR_OP(x) (((x)&0x3)<<0x1C) +#define MCF_FEC_MMFR_OP_READ (0x20000000) +#define MCF_FEC_MMFR_OP_WRITE (0x10000000) +#define MCF_FEC_MMFR_ST(x) (((x)&0x3)<<0x1E) +#define MCF_FEC_MMFR_ST_01 (0x40000000) + +/* Bit definitions and macros for MCF_FEC_MSCR */ +#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1) +#define MCF_FEC_MSCR_DIS_PREAMBLE (0x80) +#define MCF_FEC_MSCR_MII_SPEED_133 (0x1B<<0x1) +#define MCF_FEC_MSCR_MII_SPEED_120 (0x18<<0x1) +#define MCF_FEC_MSCR_MII_SPEED_66 (0xE<<0x1) +#define MCF_FEC_MSCR_MII_SPEED_60 (0xC<<0x1) + +/* Bit definitions and macros for MCF_FEC_MIBC */ +#define MCF_FEC_MIBC_MIB_IDLE (0x40000000) +#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000) + +/* Bit definitions and macros for MCF_FEC_RCR */ +#define MCF_FEC_RCR_LOOP (0x1) +#define MCF_FEC_RCR_DRT (0x2) +#define MCF_FEC_RCR_MII_MODE (0x4) +#define MCF_FEC_RCR_PROM (0x8) +#define MCF_FEC_RCR_BC_REJ (0x10) +#define MCF_FEC_RCR_FCE (0x20) +#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<0x10) + +/* Bit definitions and macros for MCF_FEC_RHR */ +#define MCF_FEC_RHR_HASH(x) (((x)&0x3F)<<0x18) +#define MCF_FEC_RHR_MULTCAST (0x40000000) +#define MCF_FEC_RHR_FCE (0x80000000) + +/* Bit definitions and macros for MCF_FEC_TCR */ +#define MCF_FEC_TCR_GTS (0x1) +#define MCF_FEC_TCR_HBC (0x2) +#define MCF_FEC_TCR_FDEN (0x4) +#define MCF_FEC_TCR_TFC_PAUSE (0x8) +#define MCF_FEC_TCR_RFC_PAUSE (0x10) + +/* Bit definitions and macros for MCF_FEC_PALR */ +#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_PAHR */ +#define MCF_FEC_PAHR_TYPE(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_PAHR_PADDR2(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_FEC_OPD */ +#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_OPD_OPCODE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_FEC_IAUR */ +#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IALR */ +#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_GAUR */ +#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_GALR */ +#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFWR */ +#define MCF_FEC_FECTFWR_X_WMRK(x) (((x)&0xF)<<0) +#define MCF_FEC_FECTFWR_X_WMRK_64 (0) +#define MCF_FEC_FECTFWR_X_WMRK_128 (0x1) +#define MCF_FEC_FECTFWR_X_WMRK_192 (0x2) +#define MCF_FEC_FECTFWR_X_WMRK_256 (0x3) +#define MCF_FEC_FECTFWR_X_WMRK_320 (0x4) +#define MCF_FEC_FECTFWR_X_WMRK_384 (0x5) +#define MCF_FEC_FECTFWR_X_WMRK_448 (0x6) +#define MCF_FEC_FECTFWR_X_WMRK_512 (0x7) +#define MCF_FEC_FECTFWR_X_WMRK_576 (0x8) +#define MCF_FEC_FECTFWR_X_WMRK_640 (0x9) +#define MCF_FEC_FECTFWR_X_WMRK_704 (0xA) +#define MCF_FEC_FECTFWR_X_WMRK_768 (0xB) +#define MCF_FEC_FECTFWR_X_WMRK_832 (0xC) +#define MCF_FEC_FECTFWR_X_WMRK_896 (0xD) +#define MCF_FEC_FECTFWR_X_WMRK_960 (0xE) +#define MCF_FEC_FECTFWR_X_WMRK_1024 (0xF) + +/* Bit definitions and macros for MCF_FEC_FECRFDR */ +#define MCF_FEC_FECRFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFSR */ +#define MCF_FEC_FECRFSR_EMT (0x10000) +#define MCF_FEC_FECRFSR_ALARM (0x20000) +#define MCF_FEC_FECRFSR_FU (0x40000) +#define MCF_FEC_FECRFSR_FRMRDY (0x80000) +#define MCF_FEC_FECRFSR_OF (0x100000) +#define MCF_FEC_FECRFSR_UF (0x200000) +#define MCF_FEC_FECRFSR_RXW (0x400000) +#define MCF_FEC_FECRFSR_FAE (0x800000) +#define MCF_FEC_FECRFSR_FRM(x) (((x)&0xF)<<0x18) +#define MCF_FEC_FECRFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_FEC_FECRFCR */ +#define MCF_FEC_FECRFCR_COUNTER(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_FECRFCR_OF_MSK (0x80000) +#define MCF_FEC_FECRFCR_UF_MSK (0x100000) +#define MCF_FEC_FECRFCR_RXW_MSK (0x200000) +#define MCF_FEC_FECRFCR_FAE_MSK (0x400000) +#define MCF_FEC_FECRFCR_IP_MSK (0x800000) +#define MCF_FEC_FECRFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_FEC_FECRFCR_FRMEN (0x8000000) +#define MCF_FEC_FECRFCR_TIMER (0x10000000) + +/* Bit definitions and macros for MCF_FEC_FECRLRFP */ +#define MCF_FEC_FECRLRFP_LRFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRLWFP */ +#define MCF_FEC_FECRLWFP_LWFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFAR */ +#define MCF_FEC_FECRFAR_ALARM(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFRP */ +#define MCF_FEC_FECRFRP_READ(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFWP */ +#define MCF_FEC_FECRFWP_WRITE(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFDR */ +#define MCF_FEC_FECTFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFSR */ +#define MCF_FEC_FECTFSR_EMT (0x10000) +#define MCF_FEC_FECTFSR_ALARM (0x20000) +#define MCF_FEC_FECTFSR_FU (0x40000) +#define MCF_FEC_FECTFSR_FRMRDY (0x80000) +#define MCF_FEC_FECTFSR_OF (0x100000) +#define MCF_FEC_FECTFSR_UF (0x200000) +#define MCF_FEC_FECTFSR_FAE (0x800000) +#define MCF_FEC_FECTFSR_FRM(x) (((x)&0xF)<<0x18) +#define MCF_FEC_FECTFSR_TXW (0x40000000) +#define MCF_FEC_FECTFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_FEC_FECTFCR */ +#define MCF_FEC_FECTFCR_RESERVED (0x200000) +#define MCF_FEC_FECTFCR_COUNTER(x) (((x)&0xFFFF)<<0|0x200000) +#define MCF_FEC_FECTFCR_TXW_MASK (0x240000) +#define MCF_FEC_FECTFCR_OF_MSK (0x280000) +#define MCF_FEC_FECTFCR_UF_MSK (0x300000) +#define MCF_FEC_FECTFCR_FAE_MSK (0x600000) +#define MCF_FEC_FECTFCR_IP_MSK (0xA00000) +#define MCF_FEC_FECTFCR_GR(x) (((x)&0x7)<<0x18|0x200000) +#define MCF_FEC_FECTFCR_FRMEN (0x8200000) +#define MCF_FEC_FECTFCR_TIMER (0x10200000) +#define MCF_FEC_FECTFCR_WFR (0x20200000) +#define MCF_FEC_FECTFCR_WCTL (0x40200000) + +/* Bit definitions and macros for MCF_FEC_FECTLRFP */ +#define MCF_FEC_FECTLRFP_LRFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTLWFP */ +#define MCF_FEC_FECTLWFP_LWFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFAR */ +#define MCF_FEC_FECTFAR_ALARM(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFRP */ +#define MCF_FEC_FECTFRP_READ(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFWP */ +#define MCF_FEC_FECTFWP_WRITE(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECFRST */ +#define MCF_FEC_FECFRST_RST_CTL (0x1000000) +#define MCF_FEC_FECFRST_SW_RST (0x2000000) + +/* Bit definitions and macros for MCF_FEC_FECCTCWR */ +#define MCF_FEC_FECCTCWR_TFCW (0x1000000) +#define MCF_FEC_FECCTCWR_CRC (0x2000000) + +/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */ +#define MCF_FEC_RMON_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */ +#define MCF_FEC_RMON_T_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */ +#define MCF_FEC_RMON_T_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */ +#define MCF_FEC_RMON_T_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */ +#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */ +#define MCF_FEC_RMON_T_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */ +#define MCF_FEC_RMON_T_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */ +#define MCF_FEC_RMON_T_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */ +#define MCF_FEC_RMON_T_JAB_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_COL */ +#define MCF_FEC_RMON_T_COL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */ +#define MCF_FEC_RMON_T_P64_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */ +#define MCF_FEC_RMON_T_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */ +#define MCF_FEC_RMON_T_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */ +#define MCF_FEC_RMON_T_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */ +#define MCF_FEC_RMON_T_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */ +#define MCF_FEC_RMON_T_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */ +#define MCF_FEC_RMON_T_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */ +#define MCF_FEC_RMON_T_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */ +#define MCF_FEC_IEEE_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */ +#define MCF_FEC_IEEE_T_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */ +#define MCF_FEC_IEEE_T_1COL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */ +#define MCF_FEC_IEEE_T_MCOL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */ +#define MCF_FEC_IEEE_T_DEF_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */ +#define MCF_FEC_IEEE_T_LCOL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */ +#define MCF_FEC_IEEE_T_EXCOL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */ +#define MCF_FEC_IEEE_T_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */ +#define MCF_FEC_IEEE_T_CSERR_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */ +#define MCF_FEC_IEEE_T_SQE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */ +#define MCF_FEC_IEEE_T_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */ +#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_DROP */ +#define MCF_FEC_RMON_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */ +#define MCF_FEC_RMON_R_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */ +#define MCF_FEC_RMON_R_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */ +#define MCF_FEC_RMON_R_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */ +#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */ +#define MCF_FEC_RMON_R_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */ +#define MCF_FEC_RMON_R_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */ +#define MCF_FEC_RMON_R_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */ +#define MCF_FEC_RMON_R_JAB_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */ +#define MCF_FEC_RMON_R_RESVD_0_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */ +#define MCF_FEC_RMON_R_P64_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */ +#define MCF_FEC_RMON_R_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */ +#define MCF_FEC_RMON_R_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */ +#define MCF_FEC_RMON_R_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */ +#define MCF_FEC_RMON_R_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */ +#define MCF_FEC_RMON_R_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */ +#define MCF_FEC_RMON_R_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */ +#define MCF_FEC_RMON_R_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */ +#define MCF_FEC_IEEE_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */ +#define MCF_FEC_IEEE_R_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */ +#define MCF_FEC_IEEE_R_CRC_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */ +#define MCF_FEC_IEEE_R_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */ +#define MCF_FEC_IEEE_R_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */ +#define MCF_FEC_IEEE_R_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */ +#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + + +#endif /* __MCF5475_FEC_H__ */ diff --git a/tos/pci_mem/include/MCF5475_GPIO.h b/tos/pci_mem/include/MCF5475_GPIO.h new file mode 100644 index 0000000..5dd2583 --- /dev/null +++ b/tos/pci_mem/include/MCF5475_GPIO.h @@ -0,0 +1,543 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_GPIO_H__ +#define __MCF5475_GPIO_H__ + + +/********************************************************************* +* +* General Purpose I/O (GPIO) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPIO_PODR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA00])) +#define MCF_GPIO_PDDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA10])) +#define MCF_GPIO_PPDSDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA20])) +#define MCF_GPIO_PCLRR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA30])) + +#define MCF_GPIO_PODR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA01])) +#define MCF_GPIO_PDDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA11])) +#define MCF_GPIO_PPDSDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA21])) +#define MCF_GPIO_PCLRR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA31])) + +#define MCF_GPIO_PODR_DMA (*(volatile uint8_t *)(&_MBAR[0xA02])) +#define MCF_GPIO_PDDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA12])) +#define MCF_GPIO_PPDSDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA22])) +#define MCF_GPIO_PCLRR_DMA (*(volatile uint8_t *)(&_MBAR[0xA32])) + +#define MCF_GPIO_PODR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA04])) +#define MCF_GPIO_PDDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA14])) +#define MCF_GPIO_PPDSDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA24])) +#define MCF_GPIO_PCLRR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA34])) + +#define MCF_GPIO_PODR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA05])) +#define MCF_GPIO_PDDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA15])) +#define MCF_GPIO_PPDSDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA25])) +#define MCF_GPIO_PCLRR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA35])) + +#define MCF_GPIO_PODR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA06])) +#define MCF_GPIO_PDDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA16])) +#define MCF_GPIO_PPDSDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA26])) +#define MCF_GPIO_PCLRR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA36])) + +#define MCF_GPIO_PODR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA07])) +#define MCF_GPIO_PDDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA17])) +#define MCF_GPIO_PPDSDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA27])) +#define MCF_GPIO_PCLRR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA37])) + +#define MCF_GPIO_PODR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA08])) +#define MCF_GPIO_PDDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA18])) +#define MCF_GPIO_PPDSDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA28])) +#define MCF_GPIO_PCLRR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA38])) + +#define MCF_GPIO_PODR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA09])) +#define MCF_GPIO_PDDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA19])) +#define MCF_GPIO_PPDSDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA29])) +#define MCF_GPIO_PCLRR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA39])) + +#define MCF_GPIO_PODR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA0A])) +#define MCF_GPIO_PDDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA1A])) +#define MCF_GPIO_PPDSDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA2A])) +#define MCF_GPIO_PCLRR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA3A])) + +#define MCF_GPIO2_PODR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA0C])) +#define MCF_GPIO2_PDDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA1C])) +#define MCF_GPIO2_PPDSDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA2C])) +#define MCF_GPIO2_PCLRR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA3C])) + +#define MCF_GPIO0_PODR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA0D])) +#define MCF_GPIO0_PDDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA1D])) +#define MCF_GPIO0_PPDSDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA2D])) +#define MCF_GPIO0_PCLRR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA3D])) + +#define MCF_GPIO_PODR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA0E])) +#define MCF_GPIO_PDDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA1E])) +#define MCF_GPIO_PPDSDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA2E])) +#define MCF_GPIO_PCLRR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA3E])) + + + +/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */ +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x1) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x2) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x4) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x8) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */ +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x1) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x2) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x4) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x8) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */ +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x1) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x2) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x4) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x8) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */ +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x1) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x2) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x4) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x8) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */ +#define MCF_GPIO_PODR_FBCS_PODR_FBCS1 (0x2) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS2 (0x4) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS3 (0x8) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS4 (0x10) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */ +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x2) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x4) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x8) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */ +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x2) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x4) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x8) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */ +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x2) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x4) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x8) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PODR_DMA */ +#define MCF_GPIO_PODR_DMA_PODR_DMA0 (0x1) +#define MCF_GPIO_PODR_DMA_PODR_DMA1 (0x2) +#define MCF_GPIO_PODR_DMA_PODR_DMA2 (0x4) +#define MCF_GPIO_PODR_DMA_PODR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */ +#define MCF_GPIO_PDDR_DMA_PDDR_DMA0 (0x1) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA1 (0x2) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA2 (0x4) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */ +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x1) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x2) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x4) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */ +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x1) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x2) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x4) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */ +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x1) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x2) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x4) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x8) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */ +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x1) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x2) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x4) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x8) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */ +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x1) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x2) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x4) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x8) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */ +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x1) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x2) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x4) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x8) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */ +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x1) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x2) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x4) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x8) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */ +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x1) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x2) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x4) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x8) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */ +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x1) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x2) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x4) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x8) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */ +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x1) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1 (0x2) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x4) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x8) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4 (0x10) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5 (0x20) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6 (0x40) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */ +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x1) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x2) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x4) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x8) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */ +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x1) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x2) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x4) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x8) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */ +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x1) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x2) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x4) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x8) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */ +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x1) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x2) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x4) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3 (0x8) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4 (0x10) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */ +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x1) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x2) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x4) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x8) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */ +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x1) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x2) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x4) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x8) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */ +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x1) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x2) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x4) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x8) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */ +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x1) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x2) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x4) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x8) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4 (0x10) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x1) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x2) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x4) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x1) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x2) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x4) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x1) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x2) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x4) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */ +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x1) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x2) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x4) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x8) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */ +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x1) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x2) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x4) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x8) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */ +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x1) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x2) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x4) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x8) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */ +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0 (0x1) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1 (0x2) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2 (0x4) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x8) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */ +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x1) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x2) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x4) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x8) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */ +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x1) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x2) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x4) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x8) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */ +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x1) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x2) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x4) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x8) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */ +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x1) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x2) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x4) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3 (0x8) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */ +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */ +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */ +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */ +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */ +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */ +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */ +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */ +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */ +#define MCF_GPIO_PODR_DSPI_PODR_DSPI0 (0x1) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI1 (0x2) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI2 (0x4) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI3 (0x8) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI4 (0x10) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI5 (0x20) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */ +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x1) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x2) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x4) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x8) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */ +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x1) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x2) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x4) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x8) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4 (0x10) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */ +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x1) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x2) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x4) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x8) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40) + + +#endif /* __MCF5475_GPIO_H__ */ diff --git a/tos/pci_mem/include/MCF5475_GPT.h b/tos/pci_mem/include/MCF5475_GPT.h new file mode 100644 index 0000000..f9fbc98 --- /dev/null +++ b/tos/pci_mem/include/MCF5475_GPT.h @@ -0,0 +1,100 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_GPT_H__ +#define __MCF5475_GPT_H__ + + +/********************************************************************* +* +* General Purpose Timers (GPT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPT0_GMS (*(volatile uint32_t*)(&_MBAR[0x800])) +#define MCF_GPT0_GCIR (*(volatile uint32_t*)(&_MBAR[0x804])) +#define MCF_GPT0_GPWM (*(volatile uint32_t*)(&_MBAR[0x808])) +#define MCF_GPT0_GSR (*(volatile uint32_t*)(&_MBAR[0x80C])) + +#define MCF_GPT1_GMS (*(volatile uint32_t*)(&_MBAR[0x810])) +#define MCF_GPT1_GCIR (*(volatile uint32_t*)(&_MBAR[0x814])) +#define MCF_GPT1_GPWM (*(volatile uint32_t*)(&_MBAR[0x818])) +#define MCF_GPT1_GSR (*(volatile uint32_t*)(&_MBAR[0x81C])) + +#define MCF_GPT2_GMS (*(volatile uint32_t*)(&_MBAR[0x820])) +#define MCF_GPT2_GCIR (*(volatile uint32_t*)(&_MBAR[0x824])) +#define MCF_GPT2_GPWM (*(volatile uint32_t*)(&_MBAR[0x828])) +#define MCF_GPT2_GSR (*(volatile uint32_t*)(&_MBAR[0x82C])) + +#define MCF_GPT3_GMS (*(volatile uint32_t*)(&_MBAR[0x830])) +#define MCF_GPT3_GCIR (*(volatile uint32_t*)(&_MBAR[0x834])) +#define MCF_GPT3_GPWM (*(volatile uint32_t*)(&_MBAR[0x838])) +#define MCF_GPT3_GSR (*(volatile uint32_t*)(&_MBAR[0x83C])) + +#define MCF_GPT_GMS(x) (*(volatile uint32_t*)(&_MBAR[0x800 + ((x)*0x10)])) +#define MCF_GPT_GCIR(x) (*(volatile uint32_t*)(&_MBAR[0x804 + ((x)*0x10)])) +#define MCF_GPT_GPWM(x) (*(volatile uint32_t*)(&_MBAR[0x808 + ((x)*0x10)])) +#define MCF_GPT_GSR(x) (*(volatile uint32_t*)(&_MBAR[0x80C + ((x)*0x10)])) + + +/* Bit definitions and macros for MCF_GPT_GMS */ +#define MCF_GPT_GMS_TMS(x) (((x)&0x7)<<0) +#define MCF_GPT_GMS_TMS_DISABLE (0) +#define MCF_GPT_GMS_TMS_INCAPT (0x1) +#define MCF_GPT_GMS_TMS_OUTCAPT (0x2) +#define MCF_GPT_GMS_TMS_PWM (0x3) +#define MCF_GPT_GMS_TMS_GPIO (0x4) +#define MCF_GPT_GMS_GPIO(x) (((x)&0x3)<<0x4) +#define MCF_GPT_GMS_GPIO_INPUT (0) +#define MCF_GPT_GMS_GPIO_OUTLO (0x20) +#define MCF_GPT_GMS_GPIO_OUTHI (0x30) +#define MCF_GPT_GMS_IEN (0x100) +#define MCF_GPT_GMS_OD (0x200) +#define MCF_GPT_GMS_SC (0x400) +#define MCF_GPT_GMS_CE (0x1000) +#define MCF_GPT_GMS_WDEN (0x8000) +#define MCF_GPT_GMS_ICT(x) (((x)&0x3)<<0x10) +#define MCF_GPT_GMS_ICT_ANY (0) +#define MCF_GPT_GMS_ICT_RISE (0x10000) +#define MCF_GPT_GMS_ICT_FALL (0x20000) +#define MCF_GPT_GMS_ICT_PULSE (0x30000) +#define MCF_GPT_GMS_OCT(x) (((x)&0x3)<<0x14) +#define MCF_GPT_GMS_OCT_FRCLOW (0) +#define MCF_GPT_GMS_OCT_PULSEHI (0x100000) +#define MCF_GPT_GMS_OCT_PULSELO (0x200000) +#define MCF_GPT_GMS_OCT_TOGGLE (0x300000) +#define MCF_GPT_GMS_OCPW(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_GPT_GCIR */ +#define MCF_GPT_GCIR_CNT(x) (((x)&0xFFFF)<<0) +#define MCF_GPT_GCIR_PRE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_GPT_GPWM */ +#define MCF_GPT_GPWM_LOAD (0x1) +#define MCF_GPT_GPWM_PWMOP (0x100) +#define MCF_GPT_GPWM_WIDTH(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_GPT_GSR */ +#define MCF_GPT_GSR_CAPT (0x1) +#define MCF_GPT_GSR_COMP (0x2) +#define MCF_GPT_GSR_PWMP (0x4) +#define MCF_GPT_GSR_TEXP (0x8) +#define MCF_GPT_GSR_PIN (0x100) +#define MCF_GPT_GSR_OVF(x) (((x)&0x7)<<0xC) +#define MCF_GPT_GSR_CAPTURE(x) (((x)&0xFFFF)<<0x10) + + +#endif /* __MCF5475_GPT_H__ */ diff --git a/tos/pci_mem/include/MCF5475_I2C.h b/tos/pci_mem/include/MCF5475_I2C.h new file mode 100644 index 0000000..1e8a85b --- /dev/null +++ b/tos/pci_mem/include/MCF5475_I2C.h @@ -0,0 +1,69 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_I2C_H__ +#define __MCF5475_I2C_H__ + + +/********************************************************************* +* +* I2C Module (I2C) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_I2C_I2ADR (*(volatile uint8_t *)(&_MBAR[0x8F00])) +#define MCF_I2C_I2FDR (*(volatile uint8_t *)(&_MBAR[0x8F04])) +#define MCF_I2C_I2CR (*(volatile uint8_t *)(&_MBAR[0x8F08])) +#define MCF_I2C_I2SR (*(volatile uint8_t *)(&_MBAR[0x8F0C])) +#define MCF_I2C_I2DR (*(volatile uint8_t *)(&_MBAR[0x8F10])) +#define MCF_I2C_I2ICR (*(volatile uint8_t *)(&_MBAR[0x8F20])) + + + +/* Bit definitions and macros for MCF_I2C_I2ADR */ +#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1) + +/* Bit definitions and macros for MCF_I2C_I2FDR */ +#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) + +/* Bit definitions and macros for MCF_I2C_I2CR */ +#define MCF_I2C_I2CR_RSTA (0x4) +#define MCF_I2C_I2CR_TXAK (0x8) +#define MCF_I2C_I2CR_MTX (0x10) +#define MCF_I2C_I2CR_MSTA (0x20) +#define MCF_I2C_I2CR_IIEN (0x40) +#define MCF_I2C_I2CR_IEN (0x80) + +/* Bit definitions and macros for MCF_I2C_I2SR */ +#define MCF_I2C_I2SR_RXAK (0x1) +#define MCF_I2C_I2SR_IIF (0x2) +#define MCF_I2C_I2SR_SRW (0x4) +#define MCF_I2C_I2SR_IAL (0x10) +#define MCF_I2C_I2SR_IBB (0x20) +#define MCF_I2C_I2SR_IAAS (0x40) +#define MCF_I2C_I2SR_ICF (0x80) + +/* Bit definitions and macros for MCF_I2C_I2DR */ +#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_I2C_I2ICR */ +#define MCF_I2C_I2ICR_IE (0x1) +#define MCF_I2C_I2ICR_RE (0x2) +#define MCF_I2C_I2ICR_TE (0x4) +#define MCF_I2C_I2ICR_BNBE (0x8) + + +#endif /* __MCF5475_I2C_H__ */ diff --git a/tos/pci_mem/include/MCF5475_INTC.h b/tos/pci_mem/include/MCF5475_INTC.h new file mode 100644 index 0000000..61265ed --- /dev/null +++ b/tos/pci_mem/include/MCF5475_INTC.h @@ -0,0 +1,331 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_INTC_H__ +#define __MCF5475_INTC_H__ + + +/********************************************************************* +* +* Interrupt Controller (INTC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_INTC_IPRH (*(volatile uint32_t*)(&_MBAR[0x700])) +#define MCF_INTC_IPRL (*(volatile uint32_t*)(&_MBAR[0x704])) +#define MCF_INTC_IMRH (*(volatile uint32_t*)(&_MBAR[0x708])) +#define MCF_INTC_IMRL (*(volatile uint32_t*)(&_MBAR[0x70C])) +#define MCF_INTC_INTFRCH (*(volatile uint32_t*)(&_MBAR[0x710])) +#define MCF_INTC_INTFRCL (*(volatile uint32_t*)(&_MBAR[0x714])) +#define MCF_INTC_IRLR (*(volatile uint8_t *)(&_MBAR[0x718])) +#define MCF_INTC_IACKLPR (*(volatile uint8_t *)(&_MBAR[0x719])) +#define MCF_INTC_ICR01 (*(volatile uint8_t *)(&_MBAR[0x741])) +#define MCF_INTC_ICR02 (*(volatile uint8_t *)(&_MBAR[0x742])) +#define MCF_INTC_ICR03 (*(volatile uint8_t *)(&_MBAR[0x743])) +#define MCF_INTC_ICR04 (*(volatile uint8_t *)(&_MBAR[0x744])) +#define MCF_INTC_ICR05 (*(volatile uint8_t *)(&_MBAR[0x745])) +#define MCF_INTC_ICR06 (*(volatile uint8_t *)(&_MBAR[0x746])) +#define MCF_INTC_ICR07 (*(volatile uint8_t *)(&_MBAR[0x747])) +#define MCF_INTC_ICR08 (*(volatile uint8_t *)(&_MBAR[0x748])) +#define MCF_INTC_ICR09 (*(volatile uint8_t *)(&_MBAR[0x749])) +#define MCF_INTC_ICR10 (*(volatile uint8_t *)(&_MBAR[0x74A])) +#define MCF_INTC_ICR11 (*(volatile uint8_t *)(&_MBAR[0x74B])) +#define MCF_INTC_ICR12 (*(volatile uint8_t *)(&_MBAR[0x74C])) +#define MCF_INTC_ICR13 (*(volatile uint8_t *)(&_MBAR[0x74D])) +#define MCF_INTC_ICR14 (*(volatile uint8_t *)(&_MBAR[0x74E])) +#define MCF_INTC_ICR15 (*(volatile uint8_t *)(&_MBAR[0x74F])) +#define MCF_INTC_ICR16 (*(volatile uint8_t *)(&_MBAR[0x750])) +#define MCF_INTC_ICR17 (*(volatile uint8_t *)(&_MBAR[0x751])) +#define MCF_INTC_ICR18 (*(volatile uint8_t *)(&_MBAR[0x752])) +#define MCF_INTC_ICR19 (*(volatile uint8_t *)(&_MBAR[0x753])) +#define MCF_INTC_ICR20 (*(volatile uint8_t *)(&_MBAR[0x754])) +#define MCF_INTC_ICR21 (*(volatile uint8_t *)(&_MBAR[0x755])) +#define MCF_INTC_ICR22 (*(volatile uint8_t *)(&_MBAR[0x756])) +#define MCF_INTC_ICR23 (*(volatile uint8_t *)(&_MBAR[0x757])) +#define MCF_INTC_ICR24 (*(volatile uint8_t *)(&_MBAR[0x758])) +#define MCF_INTC_ICR25 (*(volatile uint8_t *)(&_MBAR[0x759])) +#define MCF_INTC_ICR26 (*(volatile uint8_t *)(&_MBAR[0x75A])) +#define MCF_INTC_ICR27 (*(volatile uint8_t *)(&_MBAR[0x75B])) +#define MCF_INTC_ICR28 (*(volatile uint8_t *)(&_MBAR[0x75C])) +#define MCF_INTC_ICR29 (*(volatile uint8_t *)(&_MBAR[0x75D])) +#define MCF_INTC_ICR30 (*(volatile uint8_t *)(&_MBAR[0x75E])) +#define MCF_INTC_ICR31 (*(volatile uint8_t *)(&_MBAR[0x75F])) +#define MCF_INTC_ICR32 (*(volatile uint8_t *)(&_MBAR[0x760])) +#define MCF_INTC_ICR33 (*(volatile uint8_t *)(&_MBAR[0x761])) +#define MCF_INTC_ICR34 (*(volatile uint8_t *)(&_MBAR[0x762])) +#define MCF_INTC_ICR35 (*(volatile uint8_t *)(&_MBAR[0x763])) +#define MCF_INTC_ICR36 (*(volatile uint8_t *)(&_MBAR[0x764])) +#define MCF_INTC_ICR37 (*(volatile uint8_t *)(&_MBAR[0x765])) +#define MCF_INTC_ICR38 (*(volatile uint8_t *)(&_MBAR[0x766])) +#define MCF_INTC_ICR39 (*(volatile uint8_t *)(&_MBAR[0x767])) +#define MCF_INTC_ICR40 (*(volatile uint8_t *)(&_MBAR[0x768])) +#define MCF_INTC_ICR41 (*(volatile uint8_t *)(&_MBAR[0x769])) +#define MCF_INTC_ICR42 (*(volatile uint8_t *)(&_MBAR[0x76A])) +#define MCF_INTC_ICR43 (*(volatile uint8_t *)(&_MBAR[0x76B])) +#define MCF_INTC_ICR44 (*(volatile uint8_t *)(&_MBAR[0x76C])) +#define MCF_INTC_ICR45 (*(volatile uint8_t *)(&_MBAR[0x76D])) +#define MCF_INTC_ICR46 (*(volatile uint8_t *)(&_MBAR[0x76E])) +#define MCF_INTC_ICR47 (*(volatile uint8_t *)(&_MBAR[0x76F])) +#define MCF_INTC_ICR48 (*(volatile uint8_t *)(&_MBAR[0x770])) +#define MCF_INTC_ICR49 (*(volatile uint8_t *)(&_MBAR[0x771])) +#define MCF_INTC_ICR50 (*(volatile uint8_t *)(&_MBAR[0x772])) +#define MCF_INTC_ICR51 (*(volatile uint8_t *)(&_MBAR[0x773])) +#define MCF_INTC_ICR52 (*(volatile uint8_t *)(&_MBAR[0x774])) +#define MCF_INTC_ICR53 (*(volatile uint8_t *)(&_MBAR[0x775])) +#define MCF_INTC_ICR54 (*(volatile uint8_t *)(&_MBAR[0x776])) +#define MCF_INTC_ICR55 (*(volatile uint8_t *)(&_MBAR[0x777])) +#define MCF_INTC_ICR56 (*(volatile uint8_t *)(&_MBAR[0x778])) +#define MCF_INTC_ICR57 (*(volatile uint8_t *)(&_MBAR[0x779])) +#define MCF_INTC_ICR58 (*(volatile uint8_t *)(&_MBAR[0x77A])) +#define MCF_INTC_ICR59 (*(volatile uint8_t *)(&_MBAR[0x77B])) +#define MCF_INTC_ICR60 (*(volatile uint8_t *)(&_MBAR[0x77C])) +#define MCF_INTC_ICR61 (*(volatile uint8_t *)(&_MBAR[0x77D])) +#define MCF_INTC_ICR62 (*(volatile uint8_t *)(&_MBAR[0x77E])) +#define MCF_INTC_ICR63 (*(volatile uint8_t *)(&_MBAR[0x77F])) +#define MCF_INTC_SWIACK (*(volatile uint8_t *)(&_MBAR[0x7E0])) +#define MCF_INTC_L1IACK (*(volatile uint8_t *)(&_MBAR[0x7E4])) +#define MCF_INTC_L2IACK (*(volatile uint8_t *)(&_MBAR[0x7E8])) +#define MCF_INTC_L3IACK (*(volatile uint8_t *)(&_MBAR[0x7EC])) +#define MCF_INTC_L4IACK (*(volatile uint8_t *)(&_MBAR[0x7F0])) +#define MCF_INTC_L5IACK (*(volatile uint8_t *)(&_MBAR[0x7F4])) +#define MCF_INTC_L6IACK (*(volatile uint8_t *)(&_MBAR[0x7F8])) +#define MCF_INTC_L7IACK (*(volatile uint8_t *)(&_MBAR[0x7FC])) +#define MCF_INTC_ICR(x) (*(volatile uint8_t *)(&_MBAR[0x741 + ((x-1)*0x1)])) +#define MCF_INTC_LIACK(x) (*(volatile uint8_t *)(&_MBAR[0x7E4 + ((x-1)*0x4)])) + + + +/* Bit definitions and macros for MCF_INTC_IPRH */ +#define MCF_INTC_IPRH_INT32 (0x1) +#define MCF_INTC_IPRH_INT33 (0x2) +#define MCF_INTC_IPRH_INT34 (0x4) +#define MCF_INTC_IPRH_INT35 (0x8) +#define MCF_INTC_IPRH_INT36 (0x10) +#define MCF_INTC_IPRH_INT37 (0x20) +#define MCF_INTC_IPRH_INT38 (0x40) +#define MCF_INTC_IPRH_INT39 (0x80) +#define MCF_INTC_IPRH_INT40 (0x100) +#define MCF_INTC_IPRH_INT41 (0x200) +#define MCF_INTC_IPRH_INT42 (0x400) +#define MCF_INTC_IPRH_INT43 (0x800) +#define MCF_INTC_IPRH_INT44 (0x1000) +#define MCF_INTC_IPRH_INT45 (0x2000) +#define MCF_INTC_IPRH_INT46 (0x4000) +#define MCF_INTC_IPRH_INT47 (0x8000) +#define MCF_INTC_IPRH_INT48 (0x10000) +#define MCF_INTC_IPRH_INT49 (0x20000) +#define MCF_INTC_IPRH_INT50 (0x40000) +#define MCF_INTC_IPRH_INT51 (0x80000) +#define MCF_INTC_IPRH_INT52 (0x100000) +#define MCF_INTC_IPRH_INT53 (0x200000) +#define MCF_INTC_IPRH_INT54 (0x400000) +#define MCF_INTC_IPRH_INT55 (0x800000) +#define MCF_INTC_IPRH_INT56 (0x1000000) +#define MCF_INTC_IPRH_INT57 (0x2000000) +#define MCF_INTC_IPRH_INT58 (0x4000000) +#define MCF_INTC_IPRH_INT59 (0x8000000) +#define MCF_INTC_IPRH_INT60 (0x10000000) +#define MCF_INTC_IPRH_INT61 (0x20000000) +#define MCF_INTC_IPRH_INT62 (0x40000000) +#define MCF_INTC_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IPRL */ +#define MCF_INTC_IPRL_INT1 (0x2) +#define MCF_INTC_IPRL_INT2 (0x4) +#define MCF_INTC_IPRL_INT3 (0x8) +#define MCF_INTC_IPRL_INT4 (0x10) +#define MCF_INTC_IPRL_INT5 (0x20) +#define MCF_INTC_IPRL_INT6 (0x40) +#define MCF_INTC_IPRL_INT7 (0x80) +#define MCF_INTC_IPRL_INT8 (0x100) +#define MCF_INTC_IPRL_INT9 (0x200) +#define MCF_INTC_IPRL_INT10 (0x400) +#define MCF_INTC_IPRL_INT11 (0x800) +#define MCF_INTC_IPRL_INT12 (0x1000) +#define MCF_INTC_IPRL_INT13 (0x2000) +#define MCF_INTC_IPRL_INT14 (0x4000) +#define MCF_INTC_IPRL_INT15 (0x8000) +#define MCF_INTC_IPRL_INT16 (0x10000) +#define MCF_INTC_IPRL_INT17 (0x20000) +#define MCF_INTC_IPRL_INT18 (0x40000) +#define MCF_INTC_IPRL_INT19 (0x80000) +#define MCF_INTC_IPRL_INT20 (0x100000) +#define MCF_INTC_IPRL_INT21 (0x200000) +#define MCF_INTC_IPRL_INT22 (0x400000) +#define MCF_INTC_IPRL_INT23 (0x800000) +#define MCF_INTC_IPRL_INT24 (0x1000000) +#define MCF_INTC_IPRL_INT25 (0x2000000) +#define MCF_INTC_IPRL_INT26 (0x4000000) +#define MCF_INTC_IPRL_INT27 (0x8000000) +#define MCF_INTC_IPRL_INT28 (0x10000000) +#define MCF_INTC_IPRL_INT29 (0x20000000) +#define MCF_INTC_IPRL_INT30 (0x40000000) +#define MCF_INTC_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRH */ +#define MCF_INTC_IMRH_INT_MASK32 (0x1) +#define MCF_INTC_IMRH_INT_MASK33 (0x2) +#define MCF_INTC_IMRH_INT_MASK34 (0x4) +#define MCF_INTC_IMRH_INT_MASK35 (0x8) +#define MCF_INTC_IMRH_INT_MASK36 (0x10) +#define MCF_INTC_IMRH_INT_MASK37 (0x20) +#define MCF_INTC_IMRH_INT_MASK38 (0x40) +#define MCF_INTC_IMRH_INT_MASK39 (0x80) +#define MCF_INTC_IMRH_INT_MASK40 (0x100) +#define MCF_INTC_IMRH_INT_MASK41 (0x200) +#define MCF_INTC_IMRH_INT_MASK42 (0x400) +#define MCF_INTC_IMRH_INT_MASK43 (0x800) +#define MCF_INTC_IMRH_INT_MASK44 (0x1000) +#define MCF_INTC_IMRH_INT_MASK45 (0x2000) +#define MCF_INTC_IMRH_INT_MASK46 (0x4000) +#define MCF_INTC_IMRH_INT_MASK47 (0x8000) +#define MCF_INTC_IMRH_INT_MASK48 (0x10000) +#define MCF_INTC_IMRH_INT_MASK49 (0x20000) +#define MCF_INTC_IMRH_INT_MASK50 (0x40000) +#define MCF_INTC_IMRH_INT_MASK51 (0x80000) +#define MCF_INTC_IMRH_INT_MASK52 (0x100000) +#define MCF_INTC_IMRH_INT_MASK53 (0x200000) +#define MCF_INTC_IMRH_INT_MASK54 (0x400000) +#define MCF_INTC_IMRH_INT_MASK55 (0x800000) +#define MCF_INTC_IMRH_INT_MASK56 (0x1000000) +#define MCF_INTC_IMRH_INT_MASK57 (0x2000000) +#define MCF_INTC_IMRH_INT_MASK58 (0x4000000) +#define MCF_INTC_IMRH_INT_MASK59 (0x8000000) +#define MCF_INTC_IMRH_INT_MASK60 (0x10000000) +#define MCF_INTC_IMRH_INT_MASK61 (0x20000000) +#define MCF_INTC_IMRH_INT_MASK62 (0x40000000) +#define MCF_INTC_IMRH_INT_MASK63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRL */ +#define MCF_INTC_IMRL_MASKALL (0x1) +#define MCF_INTC_IMRL_INT_MASK1 (0x2) +#define MCF_INTC_IMRL_INT_MASK2 (0x4) +#define MCF_INTC_IMRL_INT_MASK3 (0x8) +#define MCF_INTC_IMRL_INT_MASK4 (0x10) +#define MCF_INTC_IMRL_INT_MASK5 (0x20) +#define MCF_INTC_IMRL_INT_MASK6 (0x40) +#define MCF_INTC_IMRL_INT_MASK7 (0x80) +#define MCF_INTC_IMRL_INT_MASK8 (0x100) +#define MCF_INTC_IMRL_INT_MASK9 (0x200) +#define MCF_INTC_IMRL_INT_MASK10 (0x400) +#define MCF_INTC_IMRL_INT_MASK11 (0x800) +#define MCF_INTC_IMRL_INT_MASK12 (0x1000) +#define MCF_INTC_IMRL_INT_MASK13 (0x2000) +#define MCF_INTC_IMRL_INT_MASK14 (0x4000) +#define MCF_INTC_IMRL_INT_MASK15 (0x8000) +#define MCF_INTC_IMRL_INT_MASK16 (0x10000) +#define MCF_INTC_IMRL_INT_MASK17 (0x20000) +#define MCF_INTC_IMRL_INT_MASK18 (0x40000) +#define MCF_INTC_IMRL_INT_MASK19 (0x80000) +#define MCF_INTC_IMRL_INT_MASK20 (0x100000) +#define MCF_INTC_IMRL_INT_MASK21 (0x200000) +#define MCF_INTC_IMRL_INT_MASK22 (0x400000) +#define MCF_INTC_IMRL_INT_MASK23 (0x800000) +#define MCF_INTC_IMRL_INT_MASK24 (0x1000000) +#define MCF_INTC_IMRL_INT_MASK25 (0x2000000) +#define MCF_INTC_IMRL_INT_MASK26 (0x4000000) +#define MCF_INTC_IMRL_INT_MASK27 (0x8000000) +#define MCF_INTC_IMRL_INT_MASK28 (0x10000000) +#define MCF_INTC_IMRL_INT_MASK29 (0x20000000) +#define MCF_INTC_IMRL_INT_MASK30 (0x40000000) +#define MCF_INTC_IMRL_INT_MASK31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCH */ +#define MCF_INTC_INTFRCH_INTFRC32 (0x1) +#define MCF_INTC_INTFRCH_INTFRC33 (0x2) +#define MCF_INTC_INTFRCH_INTFRC34 (0x4) +#define MCF_INTC_INTFRCH_INTFRC35 (0x8) +#define MCF_INTC_INTFRCH_INTFRC36 (0x10) +#define MCF_INTC_INTFRCH_INTFRC37 (0x20) +#define MCF_INTC_INTFRCH_INTFRC38 (0x40) +#define MCF_INTC_INTFRCH_INTFRC39 (0x80) +#define MCF_INTC_INTFRCH_INTFRC40 (0x100) +#define MCF_INTC_INTFRCH_INTFRC41 (0x200) +#define MCF_INTC_INTFRCH_INTFRC42 (0x400) +#define MCF_INTC_INTFRCH_INTFRC43 (0x800) +#define MCF_INTC_INTFRCH_INTFRC44 (0x1000) +#define MCF_INTC_INTFRCH_INTFRC45 (0x2000) +#define MCF_INTC_INTFRCH_INTFRC46 (0x4000) +#define MCF_INTC_INTFRCH_INTFRC47 (0x8000) +#define MCF_INTC_INTFRCH_INTFRC48 (0x10000) +#define MCF_INTC_INTFRCH_INTFRC49 (0x20000) +#define MCF_INTC_INTFRCH_INTFRC50 (0x40000) +#define MCF_INTC_INTFRCH_INTFRC51 (0x80000) +#define MCF_INTC_INTFRCH_INTFRC52 (0x100000) +#define MCF_INTC_INTFRCH_INTFRC53 (0x200000) +#define MCF_INTC_INTFRCH_INTFRC54 (0x400000) +#define MCF_INTC_INTFRCH_INTFRC55 (0x800000) +#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000) +#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000) +#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000) +#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000) +#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) +#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) +#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) +#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCL */ +#define MCF_INTC_INTFRCL_INTFRC1 (0x2) +#define MCF_INTC_INTFRCL_INTFRC2 (0x4) +#define MCF_INTC_INTFRCL_INTFRC3 (0x8) +#define MCF_INTC_INTFRCL_INTFRC4 (0x10) +#define MCF_INTC_INTFRCL_INTFRC5 (0x20) +#define MCF_INTC_INTFRCL_INTFRC6 (0x40) +#define MCF_INTC_INTFRCL_INTFRC7 (0x80) +#define MCF_INTC_INTFRCL_INTFRC8 (0x100) +#define MCF_INTC_INTFRCL_INTFRC9 (0x200) +#define MCF_INTC_INTFRCL_INTFRC10 (0x400) +#define MCF_INTC_INTFRCL_INTFRC11 (0x800) +#define MCF_INTC_INTFRCL_INTFRC12 (0x1000) +#define MCF_INTC_INTFRCL_INTFRC13 (0x2000) +#define MCF_INTC_INTFRCL_INTFRC14 (0x4000) +#define MCF_INTC_INTFRCL_INTFRC15 (0x8000) +#define MCF_INTC_INTFRCL_INTFRC16 (0x10000) +#define MCF_INTC_INTFRCL_INTFRC17 (0x20000) +#define MCF_INTC_INTFRCL_INTFRC18 (0x40000) +#define MCF_INTC_INTFRCL_INTFRC19 (0x80000) +#define MCF_INTC_INTFRCL_INTFRC20 (0x100000) +#define MCF_INTC_INTFRCL_INTFRC21 (0x200000) +#define MCF_INTC_INTFRCL_INTFRC22 (0x400000) +#define MCF_INTC_INTFRCL_INTFRC23 (0x800000) +#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000) +#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000) +#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000) +#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000) +#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) +#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) +#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) +#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IRLR */ +#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1) + +/* Bit definitions and macros for MCF_INTC_IACKLPR */ +#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0) +#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4) + +/* Bit definitions and macros for MCF_INTC_ICR */ +#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0) +#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3) + +/* Bit definitions and macros for MCF_INTC_SWIACK */ +#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_INTC_LIACK */ +#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) + + +#endif /* __MCF5475_INTC_H__ */ diff --git a/tos/pci_mem/include/MCF5475_MMU.h b/tos/pci_mem/include/MCF5475_MMU.h new file mode 100644 index 0000000..334ad28 --- /dev/null +++ b/tos/pci_mem/include/MCF5475_MMU.h @@ -0,0 +1,79 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_MMU_H__ +#define __MCF5475_MMU_H__ + + +/********************************************************************* +* +* Memory Management Unit (MMU) +* +*********************************************************************/ + +/* Register read/write macros */ + +/* note the uint32_t_a - this is to avoid gcc warnings about pointer aliasing */ +#define MCF_MMU_MMUCR (*(volatile uint32_t_a*)(&_MMUBAR[0])) +#define MCF_MMU_MMUOR (*(volatile uint32_t_a*)(&_MMUBAR[0x4])) +#define MCF_MMU_MMUSR (*(volatile uint32_t_a*)(&_MMUBAR[0x8])) +#define MCF_MMU_MMUAR (*(volatile uint32_t_a*)(&_MMUBAR[0x10])) +#define MCF_MMU_MMUTR (*(volatile uint32_t_a*)(&_MMUBAR[0x14])) +#define MCF_MMU_MMUDR (*(volatile uint32_t_a*)(&_MMUBAR[0x18])) + + +/* Bit definitions and macros for MCF_MMU_MMUCR */ +#define MCF_MMU_MMUCR_EN (0x1) +#define MCF_MMU_MMUCR_ASM (0x2) + +/* Bit definitions and macros for MCF_MMU_MMUOR */ +#define MCF_MMU_MMUOR_UAA (0x1) +#define MCF_MMU_MMUOR_ACC (0x2) +#define MCF_MMU_MMUOR_RW (0x4) +#define MCF_MMU_MMUOR_ADR (0x8) +#define MCF_MMU_MMUOR_ITLB (0x10) +#define MCF_MMU_MMUOR_CAS (0x20) +#define MCF_MMU_MMUOR_CNL (0x40) +#define MCF_MMU_MMUOR_CA (0x80) +#define MCF_MMU_MMUOR_STLB (0x100) +#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_MMU_MMUSR */ +#define MCF_MMU_MMUSR_HIT (0x2) +#define MCF_MMU_MMUSR_WF (0x8) +#define MCF_MMU_MMUSR_RF (0x10) +#define MCF_MMU_MMUSR_SPF (0x20) + +/* Bit definitions and macros for MCF_MMU_MMUAR */ +#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MMU_MMUTR */ +#define MCF_MMU_MMUTR_V (0x1) +#define MCF_MMU_MMUTR_SG (0x2) +#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2) +#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA) + +/* Bit definitions and macros for MCF_MMU_MMUDR */ +#define MCF_MMU_MMUDR_LK (0x2) +#define MCF_MMU_MMUDR_X (0x4) +#define MCF_MMU_MMUDR_W (0x8) +#define MCF_MMU_MMUDR_R (0x10) +#define MCF_MMU_MMUDR_SP (0x20) +#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6) +#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8) +#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA) + + +#endif /* __MCF5475_MMU_H__ */ diff --git a/tos/pci_mem/include/MCF5475_PAD.h b/tos/pci_mem/include/MCF5475_PAD.h new file mode 100644 index 0000000..1d87e2e --- /dev/null +++ b/tos/pci_mem/include/MCF5475_PAD.h @@ -0,0 +1,233 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PAD_H__ +#define __MCF5475_PAD_H__ + + +/********************************************************************* +* +* Common GPIO +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PAD_PAR_FBCTL (*(volatile uint16_t*)(&_MBAR[0xA40])) +#define MCF_PAD_PAR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA42])) +#define MCF_PAD_PAR_DMA (*(volatile uint8_t *)(&_MBAR[0xA43])) +#define MCF_PAD_PAR_FECI2CIRQ (*(volatile uint16_t*)(&_MBAR[0xA44])) +#define MCF_PAD_PAR_PCIBG (*(volatile uint16_t*)(&_MBAR[0xA48])) +#define MCF_PAD_PAR_PCIBR (*(volatile uint16_t*)(&_MBAR[0xA4A])) +#define MCF_PAD_PAR_PSC3 (*(volatile uint8_t *)(&_MBAR[0xA4C])) +#define MCF_PAD_PAR_PSC2 (*(volatile uint8_t *)(&_MBAR[0xA4D])) +#define MCF_PAD_PAR_PSC1 (*(volatile uint8_t *)(&_MBAR[0xA4E])) +#define MCF_PAD_PAR_PSC0 (*(volatile uint8_t *)(&_MBAR[0xA4F])) +#define MCF_PAD_PAR_DSPI (*(volatile uint16_t*)(&_MBAR[0xA50])) +#define MCF_PAD_PAR_TIMER (*(volatile uint8_t *)(&_MBAR[0xA52])) + + +/* Bit definitions and macros for MCF_PAD_PAR_FBCTL */ +#define MCF_PAD_PAR_FBCTL_PAR_ALE(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_FBCTL_PAR_ALE_GPIO (0) +#define MCF_PAD_PAR_FBCTL_PAR_ALE_TBST (0x2) +#define MCF_PAD_PAR_FBCTL_PAR_ALE_ALE (0x3) +#define MCF_PAD_PAR_FBCTL_PAR_TA (0x4) +#define MCF_PAD_PAR_FBCTL_PAR_RWB(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_FBCTL_PAR_RWB_GPIO (0) +#define MCF_PAD_PAR_FBCTL_PAR_RWB_TBST (0x20) +#define MCF_PAD_PAR_FBCTL_PAR_RWB_RW (0x30) +#define MCF_PAD_PAR_FBCTL_PAR_OE (0x40) +#define MCF_PAD_PAR_FBCTL_PAR_BWE0 (0x100) +#define MCF_PAD_PAR_FBCTL_PAR_BWE1 (0x400) +#define MCF_PAD_PAR_FBCTL_PAR_BWE2 (0x1000) +#define MCF_PAD_PAR_FBCTL_PAR_BWE3 (0x4000) + +/* Bit definitions and macros for MCF_PAD_PAR_FBCS */ +#define MCF_PAD_PAR_FBCS_PAR_CS1 (0x2) +#define MCF_PAD_PAR_FBCS_PAR_CS2 (0x4) +#define MCF_PAD_PAR_FBCS_PAR_CS3 (0x8) +#define MCF_PAD_PAR_FBCS_PAR_CS4 (0x10) +#define MCF_PAD_PAR_FBCS_PAR_CS5 (0x20) + +/* Bit definitions and macros for MCF_PAD_PAR_DMA */ +#define MCF_PAD_PAR_DMA_PAR_DREQ0(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_DMA_PAR_DREQ0_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DREQ0_TIN0 (0x2) +#define MCF_PAD_PAR_DMA_PAR_DREQ0_DREQ0 (0x3) +#define MCF_PAD_PAR_DMA_PAR_DREQ1(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_IRQ1 (0x4) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_TIN1 (0x8) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_DREQ1 (0xC) +#define MCF_PAD_PAR_DMA_PAR_DACK0(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_DMA_PAR_DACK0_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DACK0_TOUT0 (0x20) +#define MCF_PAD_PAR_DMA_PAR_DACK0_DACK0 (0x30) +#define MCF_PAD_PAR_DMA_PAR_DACK1(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_DMA_PAR_DACK1_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DACK1_TOUT1 (0x80) +#define MCF_PAD_PAR_DMA_PAR_DACK1_DACK1 (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_FECI2CIRQ */ +#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ5 (0x1) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ6 (0x2) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_SCL (0x4) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_SDA (0x8) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x80) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC (0xC0) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x200) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO (0x300) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MII (0x400) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E17 (0x800) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC (0x1000) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII (0x4000) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E07 (0x8000) + +/* Bit definitions and macros for MCF_PAD_PAR_PCIBG */ +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_TOUT0 (0x2) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0 (0x3) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_TOUT1 (0x8) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 (0xC) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_TOUT2 (0x20) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 (0x30) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_TOUT3 (0x80) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3 (0xC0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST (0x200) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4 (0x300) + +/* Bit definitions and macros for MCF_PAD_PAR_PCIBR */ +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_TIN0 (0x2) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0 (0x3) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_TIN1 (0x8) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 (0xC) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_TIN2 (0x20) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 (0x30) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_TIN3 (0x80) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3 (0xC0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4 (0x200) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4 (0x300) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC3 */ +#define MCF_PAD_PAR_PSC3_PAR_TXD3 (0x4) +#define MCF_PAD_PAR_PSC3_PAR_RXD3 (0x8) +#define MCF_PAD_PAR_PSC3_PAR_RTS3(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC3_PAR_RTS3_GPIO (0) +#define MCF_PAD_PAR_PSC3_PAR_RTS3_FSYNC (0x20) +#define MCF_PAD_PAR_PSC3_PAR_RTS3_RTS (0x30) +#define MCF_PAD_PAR_PSC3_PAR_CTS3(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC3_PAR_CTS3_GPIO (0) +#define MCF_PAD_PAR_PSC3_PAR_CTS3_BCLK (0x80) +#define MCF_PAD_PAR_PSC3_PAR_CTS3_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC2 */ +#define MCF_PAD_PAR_PSC2_PAR_TXD2 (0x4) +#define MCF_PAD_PAR_PSC2_PAR_RXD2 (0x8) +#define MCF_PAD_PAR_PSC2_PAR_RTS2(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC2_PAR_RTS2_GPIO (0) +#define MCF_PAD_PAR_PSC2_PAR_RTS2_FSYNC (0x20) +#define MCF_PAD_PAR_PSC2_PAR_RTS2_RTS (0x30) +#define MCF_PAD_PAR_PSC2_PAR_CTS2(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC2_PAR_CTS2_GPIO (0) +#define MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK (0x80) +#define MCF_PAD_PAR_PSC2_PAR_CTS2_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC1 */ +#define MCF_PAD_PAR_PSC1_PAR_TXD1 (0x4) +#define MCF_PAD_PAR_PSC1_PAR_RXD1 (0x8) +#define MCF_PAD_PAR_PSC1_PAR_RTS1(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC1_PAR_RTS1_GPIO (0) +#define MCF_PAD_PAR_PSC1_PAR_RTS1_FSYNC (0x20) +#define MCF_PAD_PAR_PSC1_PAR_RTS1_RTS (0x30) +#define MCF_PAD_PAR_PSC1_PAR_CTS1(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC1_PAR_CTS1_GPIO (0) +#define MCF_PAD_PAR_PSC1_PAR_CTS1_BCLK (0x80) +#define MCF_PAD_PAR_PSC1_PAR_CTS1_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC0 */ +#define MCF_PAD_PAR_PSC0_PAR_TXD0 (0x4) +#define MCF_PAD_PAR_PSC0_PAR_RXD0 (0x8) +#define MCF_PAD_PAR_PSC0_PAR_RTS0(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC0_PAR_RTS0_GPIO (0) +#define MCF_PAD_PAR_PSC0_PAR_RTS0_FSYNC (0x20) +#define MCF_PAD_PAR_PSC0_PAR_RTS0_RTS (0x30) +#define MCF_PAD_PAR_PSC0_PAR_CTS0(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC0_PAR_CTS0_GPIO (0) +#define MCF_PAD_PAR_PSC0_PAR_CTS0_BCLK (0x80) +#define MCF_PAD_PAR_PSC0_PAR_CTS0_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_DSPI */ +#define MCF_PAD_PAR_DSPI_PAR_SOUT(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_DSPI_PAR_SOUT_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_SOUT_TXD (0x2) +#define MCF_PAD_PAR_DSPI_PAR_SOUT_SOUT (0x3) +#define MCF_PAD_PAR_DSPI_PAR_SIN(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_DSPI_PAR_SIN_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_SIN_RXD (0x8) +#define MCF_PAD_PAR_DSPI_PAR_SIN_SIN (0xC) +#define MCF_PAD_PAR_DSPI_PAR_SCK(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_DSPI_PAR_SCK_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_SCK_BCLK (0x10) +#define MCF_PAD_PAR_DSPI_PAR_SCK_CTS (0x20) +#define MCF_PAD_PAR_DSPI_PAR_SCK_SCK (0x30) +#define MCF_PAD_PAR_DSPI_PAR_CS0(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_DSPI_PAR_CS0_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_CS0_FSYNC (0x40) +#define MCF_PAD_PAR_DSPI_PAR_CS0_RTS (0x80) +#define MCF_PAD_PAR_DSPI_PAR_CS0_DSPICS0 (0xC0) +#define MCF_PAD_PAR_DSPI_PAR_CS2(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_DSPI_PAR_CS2_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_CS2_TOUT2 (0x200) +#define MCF_PAD_PAR_DSPI_PAR_CS2_DSPICS2 (0x300) +#define MCF_PAD_PAR_DSPI_PAR_CS3(x) (((x)&0x3)<<0xA) +#define MCF_PAD_PAR_DSPI_PAR_CS3_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_CS3_TOUT3 (0x800) +#define MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3 (0xC00) +#define MCF_PAD_PAR_DSPI_PAR_CS5 (0x1000) + +/* Bit definitions and macros for MCF_PAD_PAR_TIMER */ +#define MCF_PAD_PAR_TIMER_PAR_TOUT2 (0x1) +#define MCF_PAD_PAR_TIMER_PAR_TIN2(x) (((x)&0x3)<<0x1) +#define MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2 (0x4) +#define MCF_PAD_PAR_TIMER_PAR_TIN2_TIN2 (0x6) +#define MCF_PAD_PAR_TIMER_PAR_TOUT3 (0x8) +#define MCF_PAD_PAR_TIMER_PAR_TIN3(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_TIMER_PAR_TIN3_IRQ3 (0x20) +#define MCF_PAD_PAR_TIMER_PAR_TIN3_TIN3 (0x30) + + +#endif /* __MCF5475_PAD_H__ */ diff --git a/tos/pci_mem/include/MCF5475_PCI.h b/tos/pci_mem/include/MCF5475_PCI.h new file mode 100644 index 0000000..3eb3341 --- /dev/null +++ b/tos/pci_mem/include/MCF5475_PCI.h @@ -0,0 +1,376 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PCI_H__ +#define __MCF5475_PCI_H__ + + +/********************************************************************* +* +* PCI Bus Controller (PCI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PCI_PCIIDR (*(volatile uint32_t*)(&_MBAR[0xB00])) +#define MCF_PCI_PCISCR (*(volatile uint32_t*)(&_MBAR[0xB04])) +#define MCF_PCI_PCICCRIR (*(volatile uint32_t*)(&_MBAR[0xB08])) +#define MCF_PCI_PCICR1 (*(volatile uint32_t*)(&_MBAR[0xB0C])) +#define MCF_PCI_PCIBAR0 (*(volatile uint32_t*)(&_MBAR[0xB10])) +#define MCF_PCI_PCIBAR1 (*(volatile uint32_t*)(&_MBAR[0xB14])) +#define MCF_PCI_PCICCPR (*(volatile uint32_t*)(&_MBAR[0xB28])) +#define MCF_PCI_PCISID (*(volatile uint32_t*)(&_MBAR[0xB2C])) +#define MCF_PCI_PCICR2 (*(volatile uint32_t*)(&_MBAR[0xB3C])) +#define MCF_PCI_PCIGSCR (*(volatile uint32_t*)(&_MBAR[0xB60])) +#define MCF_PCI_PCITBATR0 (*(volatile uint32_t*)(&_MBAR[0xB64])) +#define MCF_PCI_PCITBATR1 (*(volatile uint32_t*)(&_MBAR[0xB68])) +#define MCF_PCI_PCITCR (*(volatile uint32_t*)(&_MBAR[0xB6C])) +#define MCF_PCI_PCIIW0BTAR (*(volatile uint32_t*)(&_MBAR[0xB70])) +#define MCF_PCI_PCIIW1BTAR (*(volatile uint32_t*)(&_MBAR[0xB74])) +#define MCF_PCI_PCIIW2BTAR (*(volatile uint32_t*)(&_MBAR[0xB78])) +#define MCF_PCI_PCIIWCR (*(volatile uint32_t*)(&_MBAR[0xB80])) +#define MCF_PCI_PCIICR (*(volatile uint32_t*)(&_MBAR[0xB84])) +#define MCF_PCI_PCIISR (*(volatile uint32_t*)(&_MBAR[0xB88])) +#define MCF_PCI_PCICAR (*(volatile uint32_t*)(&_MBAR[0xBF8])) +#define MCF_PCI_PCITPSR (*(volatile uint32_t*)(&_MBAR[0x8400])) +#define MCF_PCI_PCITSAR (*(volatile uint32_t*)(&_MBAR[0x8404])) +#define MCF_PCI_PCITTCR (*(volatile uint32_t*)(&_MBAR[0x8408])) +#define MCF_PCI_PCITER (*(volatile uint32_t*)(&_MBAR[0x840C])) +#define MCF_PCI_PCITNAR (*(volatile uint32_t*)(&_MBAR[0x8410])) +#define MCF_PCI_PCITLWR (*(volatile uint32_t*)(&_MBAR[0x8414])) +#define MCF_PCI_PCITDCR (*(volatile uint32_t*)(&_MBAR[0x8418])) +#define MCF_PCI_PCITSR (*(volatile uint32_t*)(&_MBAR[0x841C])) +#define MCF_PCI_PCITFDR (*(volatile uint32_t*)(&_MBAR[0x8440])) +#define MCF_PCI_PCITFSR (*(volatile uint32_t*)(&_MBAR[0x8444])) +#define MCF_PCI_PCITFCR (*(volatile uint32_t*)(&_MBAR[0x8448])) +#define MCF_PCI_PCITFAR (*(volatile uint32_t*)(&_MBAR[0x844C])) +#define MCF_PCI_PCITFRPR (*(volatile uint32_t*)(&_MBAR[0x8450])) +#define MCF_PCI_PCITFWPR (*(volatile uint32_t*)(&_MBAR[0x8454])) +#define MCF_PCI_PCIRPSR (*(volatile uint32_t*)(&_MBAR[0x8480])) +#define MCF_PCI_PCIRSAR (*(volatile uint32_t*)(&_MBAR[0x8484])) +#define MCF_PCI_PCIRTCR (*(volatile uint32_t*)(&_MBAR[0x8488])) +#define MCF_PCI_PCIRER (*(volatile uint32_t*)(&_MBAR[0x848C])) +#define MCF_PCI_PCIRNAR (*(volatile uint32_t*)(&_MBAR[0x8490])) +#define MCF_PCI_PCIRDCR (*(volatile uint32_t*)(&_MBAR[0x8498])) +#define MCF_PCI_PCIRSR (*(volatile uint32_t*)(&_MBAR[0x849C])) +#define MCF_PCI_PCIRFDR (*(volatile uint32_t*)(&_MBAR[0x84C0])) +#define MCF_PCI_PCIRFSR (*(volatile uint32_t*)(&_MBAR[0x84C4])) +#define MCF_PCI_PCIRFCR (*(volatile uint32_t*)(&_MBAR[0x84C8])) +#define MCF_PCI_PCIRFAR (*(volatile uint32_t*)(&_MBAR[0x84CC])) +#define MCF_PCI_PCIRFRPR (*(volatile uint32_t*)(&_MBAR[0x84D0])) +#define MCF_PCI_PCIRFWPR (*(volatile uint32_t*)(&_MBAR[0x84D4])) + + +/* Bit definitions and macros for MCF_PCI_PCIIDR */ +#define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCISCR */ +#define MCF_PCI_PCISCR_IO (0x1) +#define MCF_PCI_PCISCR_M (0x2) +#define MCF_PCI_PCISCR_B (0x4) +#define MCF_PCI_PCISCR_SP (0x8) +#define MCF_PCI_PCISCR_MW (0x10) +#define MCF_PCI_PCISCR_V (0x20) +#define MCF_PCI_PCISCR_PER (0x40) +#define MCF_PCI_PCISCR_ST (0x80) +#define MCF_PCI_PCISCR_S (0x100) +#define MCF_PCI_PCISCR_F (0x200) +#define MCF_PCI_PCISCR_C (0x100000) +#define MCF_PCI_PCISCR_66M (0x200000) +#define MCF_PCI_PCISCR_R (0x400000) +#define MCF_PCI_PCISCR_FC (0x800000) +#define MCF_PCI_PCISCR_DP (0x1000000) +#define MCF_PCI_PCISCR_DT(x) (((x)&0x3)<<0x19) +#define MCF_PCI_PCISCR_TS (0x8000000) +#define MCF_PCI_PCISCR_TR (0x10000000) +#define MCF_PCI_PCISCR_MA (0x20000000) +#define MCF_PCI_PCISCR_SE (0x40000000) +#define MCF_PCI_PCISCR_PE (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCICCRIR */ +#define MCF_PCI_PCICCRIR_REVISIONID(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0xFFFFFF)<<0x8) + +/* Bit definitions and macros for MCF_PCI_PCICR1 */ +#define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICR1_BIST(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIBAR0 */ +#define MCF_PCI_PCIBAR0_IOM (0x1) +#define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x3)<<0x1) +#define MCF_PCI_PCIBAR0_PREF (0x8) +#define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x3FFF)<<0x12) + +/* Bit definitions and macros for MCF_PCI_PCIBAR1 */ +#define MCF_PCI_PCIBAR1_IOM (0x1) +#define MCF_PCI_PCIBAR1_RANGE(x) (((x)&0x3)<<0x1) +#define MCF_PCI_PCIBAR1_PREF (0x8) +#define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_PCI_PCICCPR */ +#define MCF_PCI_PCICCPR_PCICCP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCISID */ +#define MCF_PCI_PCISID_VENDORID(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCICR2 */ +#define MCF_PCI_PCICR2_INTLINE(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICR2_INTPIN(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCICR2_MINGNT(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIGSCR */ +#define MCF_PCI_PCIGSCR_PR (0x1) +#define MCF_PCI_PCIGSCR_SEE (0x1000) +#define MCF_PCI_PCIGSCR_PEE (0x2000) +#define MCF_PCI_PCIGSCR_CLKINRESERVED(x) (((x)&0x7)<<0x10) +#define MCF_PCI_PCIGSCR_XLB2CLKIN(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCIGSCR_SE (0x10000000) +#define MCF_PCI_PCIGSCR_PE (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCITBATR0 */ +#define MCF_PCI_PCITBATR0_EN (0x1) +#define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x3FFF)<<0x12) + +/* Bit definitions and macros for MCF_PCI_PCITBATR1 */ +#define MCF_PCI_PCITBATR1_EN (0x1) +#define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_PCI_PCITCR */ +#define MCF_PCI_PCITCR_P (0x10000) +#define MCF_PCI_PCITCR_LD (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */ +#define MCF_PCI_PCIIW0BTAR_WTA0(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW0BTAR_WAM0(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW0BTAR_WBA0(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */ +#define MCF_PCI_PCIIW1BTAR_WTA1(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW1BTAR_WAM1(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW1BTAR_WBA1(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */ +#define MCF_PCI_PCIIW2BTAR_WTA2(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW2BTAR_WAM2(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW2BTAR_WBA2(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIWCR */ +#define MCF_PCI_PCIIWCR_WINCTRL2_E (0x100) +#define MCF_PCI_PCIIWCR_WINCTRL2_PRC(x) (((x)&0x3)<<0x9) +#define MCF_PCI_PCIIWCR_WINCTRL2_IOM (0x800) +#define MCF_PCI_PCIIWCR_WINCTRL1_E (0x10000) +#define MCF_PCI_PCIIWCR_WINCTRL1_PRC(x) (((x)&0x3)<<0x11) +#define MCF_PCI_PCIIWCR_WINCTRL1_IOM (0x80000) +#define MCF_PCI_PCIIWCR_WINCTRL0_E (0x1000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_PRC(x) (((x)&0x3)<<0x19) +#define MCF_PCI_PCIIWCR_WINCTRL0_IOM (0x8000000) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x100) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x300) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x500) +#define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x900) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x10000) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x30000) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x50000) +#define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x90000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x1000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x3000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x5000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x9000000) + +/* Bit definitions and macros for MCF_PCI_PCIICR */ +#define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCIICR_TAE (0x1000000) +#define MCF_PCI_PCIICR_IAE (0x2000000) +#define MCF_PCI_PCIICR_REE (0x4000000) + +/* Bit definitions and macros for MCF_PCI_PCIISR */ +#define MCF_PCI_PCIISR_TA (0x1000000) +#define MCF_PCI_PCIISR_IA (0x2000000) +#define MCF_PCI_PCIISR_RE (0x4000000) + +/* Bit definitions and macros for MCF_PCI_PCICAR */ +#define MCF_PCI_PCICAR_DWORD(x) (((x)&0x3F)<<0x2) +#define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x1F)<<0xB) +#define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICAR_E (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITPSR */ +#define MCF_PCI_PCITPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCITSAR */ +#define MCF_PCI_PCITSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITTCR */ +#define MCF_PCI_PCITTCR_DI (0x1) +#define MCF_PCI_PCITTCR_W (0x10) +#define MCF_PCI_PCITTCR_MAXBEATS(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCITTCR_MAXRETRY(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCITTCR_PCICMD(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCITER */ +#define MCF_PCI_PCITER_NE (0x10000) +#define MCF_PCI_PCITER_IAE (0x20000) +#define MCF_PCI_PCITER_TAE (0x40000) +#define MCF_PCI_PCITER_RE (0x80000) +#define MCF_PCI_PCITER_SE (0x100000) +#define MCF_PCI_PCITER_FEE (0x200000) +#define MCF_PCI_PCITER_ME (0x1000000) +#define MCF_PCI_PCITER_BE (0x8000000) +#define MCF_PCI_PCITER_CM (0x10000000) +#define MCF_PCI_PCITER_RF (0x40000000) +#define MCF_PCI_PCITER_RC (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITNAR */ +#define MCF_PCI_PCITNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITLWR */ +#define MCF_PCI_PCITLWR_LASTWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITDCR */ +#define MCF_PCI_PCITDCR_PKTSDONE(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCITDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCITSR */ +#define MCF_PCI_PCITSR_IA (0x10000) +#define MCF_PCI_PCITSR_TA (0x20000) +#define MCF_PCI_PCITSR_RE (0x40000) +#define MCF_PCI_PCITSR_SE (0x80000) +#define MCF_PCI_PCITSR_FE (0x100000) +#define MCF_PCI_PCITSR_BE1 (0x200000) +#define MCF_PCI_PCITSR_BE2 (0x400000) +#define MCF_PCI_PCITSR_BE3 (0x800000) +#define MCF_PCI_PCITSR_NT (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCITFDR */ +#define MCF_PCI_PCITFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFSR */ +#define MCF_PCI_PCITFSR_EMPTY (0x10000) +#define MCF_PCI_PCITFSR_ALARM (0x20000) +#define MCF_PCI_PCITFSR_FULL (0x40000) +#define MCF_PCI_PCITFSR_FR (0x80000) +#define MCF_PCI_PCITFSR_OF (0x100000) +#define MCF_PCI_PCITFSR_UF (0x200000) +#define MCF_PCI_PCITFSR_RXW (0x400000) +#define MCF_PCI_PCITFSR_FAE (0x800000) +#define MCF_PCI_PCITFSR_TXW (0x40000000) +#define MCF_PCI_PCITFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITFCR */ +#define MCF_PCI_PCITFCR_TXW_MASK (0x40000) +#define MCF_PCI_PCITFCR_OF_MASK (0x80000) +#define MCF_PCI_PCITFCR_UF_MASK (0x100000) +#define MCF_PCI_PCITFCR_RXW_MASK (0x200000) +#define MCF_PCI_PCITFCR_FAE_MASK (0x400000) +#define MCF_PCI_PCITFCR_IP_MASK (0x800000) +#define MCF_PCI_PCITFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCITFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCITFAR */ +#define MCF_PCI_PCITFAR_ALARM(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFRPR */ +#define MCF_PCI_PCITFRPR_READPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFWPR */ +#define MCF_PCI_PCITFWPR_WRITEPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRPSR */ +#define MCF_PCI_PCIRPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCIRSAR */ +#define MCF_PCI_PCIRSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRTCR */ +#define MCF_PCI_PCIRTCR_DI (0x1) +#define MCF_PCI_PCIRTCR_W (0x10) +#define MCF_PCI_PCIRTCR_MAXBEATS(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCIRTCR_FB (0x1000) +#define MCF_PCI_PCIRTCR_MAXRETRY(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIRTCR_PCICMD(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIRER */ +#define MCF_PCI_PCIRER_NE (0x10000) +#define MCF_PCI_PCIRER_IAE (0x20000) +#define MCF_PCI_PCIRER_TAE (0x40000) +#define MCF_PCI_PCIRER_RE (0x80000) +#define MCF_PCI_PCIRER_SE (0x100000) +#define MCF_PCI_PCIRER_FEE (0x200000) +#define MCF_PCI_PCIRER_ME (0x1000000) +#define MCF_PCI_PCIRER_BE (0x8000000) +#define MCF_PCI_PCIRER_CM (0x10000000) +#define MCF_PCI_PCIRER_FE (0x20000000) +#define MCF_PCI_PCIRER_RF (0x40000000) +#define MCF_PCI_PCIRER_RC (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCIRNAR */ +#define MCF_PCI_PCIRNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRDCR */ +#define MCF_PCI_PCIRDCR_PKTSDONE(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCIRDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCIRSR */ +#define MCF_PCI_PCIRSR_IA (0x10000) +#define MCF_PCI_PCIRSR_TA (0x20000) +#define MCF_PCI_PCIRSR_RE (0x40000) +#define MCF_PCI_PCIRSR_SE (0x80000) +#define MCF_PCI_PCIRSR_FE (0x100000) +#define MCF_PCI_PCIRSR_BE1 (0x200000) +#define MCF_PCI_PCIRSR_BE2 (0x400000) +#define MCF_PCI_PCIRSR_BE3 (0x800000) +#define MCF_PCI_PCIRSR_NT (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFDR */ +#define MCF_PCI_PCIRFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFSR */ +#define MCF_PCI_PCIRFSR_EMPTY (0x10000) +#define MCF_PCI_PCIRFSR_ALARM (0x20000) +#define MCF_PCI_PCIRFSR_FULL (0x40000) +#define MCF_PCI_PCIRFSR_FR (0x80000) +#define MCF_PCI_PCIRFSR_OF (0x100000) +#define MCF_PCI_PCIRFSR_UF (0x200000) +#define MCF_PCI_PCIRFSR_RXW (0x400000) +#define MCF_PCI_PCIRFSR_FAE (0x800000) +#define MCF_PCI_PCIRFSR_TXW (0x40000000) +#define MCF_PCI_PCIRFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFCR */ +#define MCF_PCI_PCIRFCR_TXW_MASK (0x40000) +#define MCF_PCI_PCIRFCR_OF_MASK (0x80000) +#define MCF_PCI_PCIRFCR_UF_MASK (0x100000) +#define MCF_PCI_PCIRFCR_RXW_MASK (0x200000) +#define MCF_PCI_PCIRFCR_FAE_MASK (0x400000) +#define MCF_PCI_PCIRFCR_IP_MASK (0x800000) +#define MCF_PCI_PCIRFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCIRFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFAR */ +#define MCF_PCI_PCIRFAR_ALARM(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFRPR */ +#define MCF_PCI_PCIRFRPR_READPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFWPR */ +#define MCF_PCI_PCIRFWPR_WRITEPTR(x) (((x)&0x7F)<<0) + + +#endif /* __MCF5475_PCI_H__ */ diff --git a/tos/pci_mem/include/MCF5475_PCIARB.h b/tos/pci_mem/include/MCF5475_PCIARB.h new file mode 100644 index 0000000..9e8c05b --- /dev/null +++ b/tos/pci_mem/include/MCF5475_PCIARB.h @@ -0,0 +1,43 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PCIARB_H__ +#define __MCF5475_PCIARB_H__ + + +/********************************************************************* +* +* PCI Bus Arbiter Module (PCIARB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PCIARB_PACR (*(volatile uint32_t*)(&_MBAR[0xC00])) +#define MCF_PCIARB_PASR (*(volatile uint32_t*)(&_MBAR[0xC04])) + + +/* Bit definitions and macros for MCF_PCIARB_PACR */ +#define MCF_PCIARB_PACR_INTMPRI (0x1) +#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x1F)<<0x1) +#define MCF_PCIARB_PACR_INTMINTEN (0x10000) +#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x1F)<<0x11) +#define MCF_PCIARB_PACR_DS (0x80000000) + +/* Bit definitions and macros for MCF_PCIARB_PASR */ +#define MCF_PCIARB_PASR_ITLMBK (0x10000) +#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x1F)<<0x11) + + +#endif /* __MCF5475_PCIARB_H__ */ diff --git a/tos/pci_mem/include/MCF5475_PSC.h b/tos/pci_mem/include/MCF5475_PSC.h new file mode 100644 index 0000000..ffa9f3e --- /dev/null +++ b/tos/pci_mem/include/MCF5475_PSC.h @@ -0,0 +1,527 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PSC_H__ +#define __MCF5475_PSC_H__ + + +/********************************************************************* +* +* Programmable Serial Controller (PSC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PSC0_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8600])) +#define MCF_PSC0_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8600])) +#define MCF_PSC0_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8604])) +#define MCF_PSC0_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8604])) +#define MCF_PSC0_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8608])) +#define MCF_PSC0_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8610])) +#define MCF_PSC0_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8610])) +#define MCF_PSC0_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8614])) +#define MCF_PSC0_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8614])) +#define MCF_PSC0_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8618])) +#define MCF_PSC0_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x861C])) +#define MCF_PSC0_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8634])) +#define MCF_PSC0_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8638])) +#define MCF_PSC0_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x863C])) +#define MCF_PSC0_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8640])) +#define MCF_PSC0_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8644])) +#define MCF_PSC0_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8648])) +#define MCF_PSC0_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x864C])) +#define MCF_PSC0_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8650])) +#define MCF_PSC0_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8654])) +#define MCF_PSC0_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8658])) +#define MCF_PSC0_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x865C])) +#define MCF_PSC0_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8660])) +#define MCF_PSC0_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8664])) +#define MCF_PSC0_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8668])) +#define MCF_PSC0_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x866E])) +#define MCF_PSC0_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8672])) +#define MCF_PSC0_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8676])) +#define MCF_PSC0_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x867A])) +#define MCF_PSC0_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x867E])) +#define MCF_PSC0_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8680])) +#define MCF_PSC0_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8684])) +#define MCF_PSC0_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8688])) +#define MCF_PSC0_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x868E])) +#define MCF_PSC0_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8692])) +#define MCF_PSC0_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8696])) +#define MCF_PSC0_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x869A])) +#define MCF_PSC0_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x869E])) + +#define MCF_PSC1_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8700])) +#define MCF_PSC1_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8700])) +#define MCF_PSC1_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8704])) +#define MCF_PSC1_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8704])) +#define MCF_PSC1_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8708])) +#define MCF_PSC1_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8710])) +#define MCF_PSC1_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8710])) +#define MCF_PSC1_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8714])) +#define MCF_PSC1_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8714])) +#define MCF_PSC1_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8718])) +#define MCF_PSC1_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x871C])) +#define MCF_PSC1_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8734])) +#define MCF_PSC1_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8738])) +#define MCF_PSC1_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x873C])) +#define MCF_PSC1_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8740])) +#define MCF_PSC1_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8744])) +#define MCF_PSC1_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8748])) +#define MCF_PSC1_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x874C])) +#define MCF_PSC1_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8750])) +#define MCF_PSC1_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8754])) +#define MCF_PSC1_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8758])) +#define MCF_PSC1_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x875C])) +#define MCF_PSC1_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8760])) +#define MCF_PSC1_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8764])) +#define MCF_PSC1_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8768])) +#define MCF_PSC1_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x876E])) +#define MCF_PSC1_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8772])) +#define MCF_PSC1_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8776])) +#define MCF_PSC1_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x877A])) +#define MCF_PSC1_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x877E])) +#define MCF_PSC1_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8780])) +#define MCF_PSC1_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8784])) +#define MCF_PSC1_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8788])) +#define MCF_PSC1_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x878E])) +#define MCF_PSC1_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8792])) +#define MCF_PSC1_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8796])) +#define MCF_PSC1_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x879A])) +#define MCF_PSC1_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x879E])) + +#define MCF_PSC2_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8800])) +#define MCF_PSC2_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8800])) +#define MCF_PSC2_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8804])) +#define MCF_PSC2_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8804])) +#define MCF_PSC2_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8808])) +#define MCF_PSC2_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8810])) +#define MCF_PSC2_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8810])) +#define MCF_PSC2_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8814])) +#define MCF_PSC2_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8814])) +#define MCF_PSC2_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8818])) +#define MCF_PSC2_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x881C])) +#define MCF_PSC2_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8834])) +#define MCF_PSC2_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8838])) +#define MCF_PSC2_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x883C])) +#define MCF_PSC2_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8840])) +#define MCF_PSC2_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8844])) +#define MCF_PSC2_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8848])) +#define MCF_PSC2_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x884C])) +#define MCF_PSC2_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8850])) +#define MCF_PSC2_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8854])) +#define MCF_PSC2_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8858])) +#define MCF_PSC2_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x885C])) +#define MCF_PSC2_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8860])) +#define MCF_PSC2_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8864])) +#define MCF_PSC2_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8868])) +#define MCF_PSC2_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x886E])) +#define MCF_PSC2_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8872])) +#define MCF_PSC2_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8876])) +#define MCF_PSC2_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x887A])) +#define MCF_PSC2_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x887E])) +#define MCF_PSC2_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8880])) +#define MCF_PSC2_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8884])) +#define MCF_PSC2_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8888])) +#define MCF_PSC2_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x888E])) +#define MCF_PSC2_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8892])) +#define MCF_PSC2_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8896])) +#define MCF_PSC2_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x889A])) +#define MCF_PSC2_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x889E])) + +#define MCF_PSC3_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8900])) +#define MCF_PSC3_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8900])) +#define MCF_PSC3_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8904])) +#define MCF_PSC3_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8904])) +#define MCF_PSC3_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8908])) +#define MCF_PSC3_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8910])) +#define MCF_PSC3_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8910])) +#define MCF_PSC3_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8914])) +#define MCF_PSC3_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8914])) +#define MCF_PSC3_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8918])) +#define MCF_PSC3_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x891C])) +#define MCF_PSC3_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8934])) +#define MCF_PSC3_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8938])) +#define MCF_PSC3_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x893C])) +#define MCF_PSC3_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8940])) +#define MCF_PSC3_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8944])) +#define MCF_PSC3_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8948])) +#define MCF_PSC3_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x894C])) +#define MCF_PSC3_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8950])) +#define MCF_PSC3_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8954])) +#define MCF_PSC3_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8958])) +#define MCF_PSC3_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x895C])) +#define MCF_PSC3_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8960])) +#define MCF_PSC3_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8964])) +#define MCF_PSC3_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8968])) +#define MCF_PSC3_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x896E])) +#define MCF_PSC3_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8972])) +#define MCF_PSC3_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8976])) +#define MCF_PSC3_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x897A])) +#define MCF_PSC3_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x897E])) +#define MCF_PSC3_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8980])) +#define MCF_PSC3_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8984])) +#define MCF_PSC3_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8988])) +#define MCF_PSC3_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x898E])) +#define MCF_PSC3_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8992])) +#define MCF_PSC3_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8996])) +#define MCF_PSC3_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x899A])) +#define MCF_PSC3_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x899E])) + +#define MCF_PSC_PSCMR(x) (*(volatile uint8_t *)(&_MBAR[0x8600 + ((x)*0x100)])) +#define MCF_PSC_PSCCSR(x) (*(volatile uint8_t *)(&_MBAR[0x8604 + ((x)*0x100)])) +#define MCF_PSC_PSCSR(x) (*(volatile uint16_t*)(&_MBAR[0x8604 + ((x)*0x100)])) +#define MCF_PSC_PSCCR(x) (*(volatile uint8_t *)(&_MBAR[0x8608 + ((x)*0x100)])) +#define MCF_PSC_PSCRB_8BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_8BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCRB_16BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_16BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCRB_AC97(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_AC97(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCIPCR(x) (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)])) +#define MCF_PSC_PSCACR(x) (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)])) +#define MCF_PSC_PSCIMR(x) (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)])) +#define MCF_PSC_PSCISR(x) (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)])) +#define MCF_PSC_PSCCTUR(x) (*(volatile uint8_t *)(&_MBAR[0x8618 + ((x)*0x100)])) +#define MCF_PSC_PSCCTLR(x) (*(volatile uint8_t *)(&_MBAR[0x861C + ((x)*0x100)])) +#define MCF_PSC_PSCIP(x) (*(volatile uint8_t *)(&_MBAR[0x8634 + ((x)*0x100)])) +#define MCF_PSC_PSCOPSET(x) (*(volatile uint8_t *)(&_MBAR[0x8638 + ((x)*0x100)])) +#define MCF_PSC_PSCOPRESET(x) (*(volatile uint8_t *)(&_MBAR[0x863C + ((x)*0x100)])) +#define MCF_PSC_PSCSICR(x) (*(volatile uint8_t *)(&_MBAR[0x8640 + ((x)*0x100)])) +#define MCF_PSC_PSCIRCR1(x) (*(volatile uint8_t *)(&_MBAR[0x8644 + ((x)*0x100)])) +#define MCF_PSC_PSCIRCR2(x) (*(volatile uint8_t *)(&_MBAR[0x8648 + ((x)*0x100)])) +#define MCF_PSC_PSCIRSDR(x) (*(volatile uint8_t *)(&_MBAR[0x864C + ((x)*0x100)])) +#define MCF_PSC_PSCIRMDR(x) (*(volatile uint8_t *)(&_MBAR[0x8650 + ((x)*0x100)])) +#define MCF_PSC_PSCIRFDR(x) (*(volatile uint8_t *)(&_MBAR[0x8654 + ((x)*0x100)])) +#define MCF_PSC_PSCRFCNT(x) (*(volatile uint16_t*)(&_MBAR[0x8658 + ((x)*0x100)])) +#define MCF_PSC_PSCTFCNT(x) (*(volatile uint16_t*)(&_MBAR[0x865C + ((x)*0x100)])) +#define MCF_PSC_PSCRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8660 + ((x)*0x100)])) +#define MCF_PSC_PSCRFSR(x) (*(volatile uint16_t*)(&_MBAR[0x8664 + ((x)*0x100)])) +#define MCF_PSC_PSCRFCR(x) (*(volatile uint32_t*)(&_MBAR[0x8668 + ((x)*0x100)])) +#define MCF_PSC_PSCRFAR(x) (*(volatile uint16_t*)(&_MBAR[0x866E + ((x)*0x100)])) +#define MCF_PSC_PSCRFRP(x) (*(volatile uint16_t*)(&_MBAR[0x8672 + ((x)*0x100)])) +#define MCF_PSC_PSCRFWP(x) (*(volatile uint16_t*)(&_MBAR[0x8676 + ((x)*0x100)])) +#define MCF_PSC_PSCRLRFP(x) (*(volatile uint16_t*)(&_MBAR[0x867A + ((x)*0x100)])) +#define MCF_PSC_PSCRLWFP(x) (*(volatile uint16_t*)(&_MBAR[0x867E + ((x)*0x100)])) +#define MCF_PSC_PSCTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8680 + ((x)*0x100)])) +#define MCF_PSC_PSCTFSR(x) (*(volatile uint16_t*)(&_MBAR[0x8684 + ((x)*0x100)])) +#define MCF_PSC_PSCTFCR(x) (*(volatile uint32_t*)(&_MBAR[0x8688 + ((x)*0x100)])) +#define MCF_PSC_PSCTFAR(x) (*(volatile uint16_t*)(&_MBAR[0x868E + ((x)*0x100)])) +#define MCF_PSC_PSCTFRP(x) (*(volatile uint16_t*)(&_MBAR[0x8692 + ((x)*0x100)])) +#define MCF_PSC_PSCTFWP(x) (*(volatile uint16_t*)(&_MBAR[0x8696 + ((x)*0x100)])) +#define MCF_PSC_PSCTLRFP(x) (*(volatile uint16_t*)(&_MBAR[0x869A + ((x)*0x100)])) +#define MCF_PSC_PSCTLWFP(x) (*(volatile uint16_t*)(&_MBAR[0x869E + ((x)*0x100)])) + +/* Bit definitions and macros for MCF_PSC_PSCMR */ +#define MCF_PSC_PSCMR_SB(x) (((x)&0xF)<<0) +#define MCF_PSC_PSCMR_TXCTS (0x10) +#define MCF_PSC_PSCMR_TXRTS (0x20) +#define MCF_PSC_PSCMR_CM(x) (((x)&0x3)<<0x6) +#define MCF_PSC_PSCMR_CM_NORMAL (0) +#define MCF_PSC_PSCMR_CM_ECHO (0x40) +#define MCF_PSC_PSCMR_CM_LOCAL_LOOP (0x80) +#define MCF_PSC_PSCMR_CM_REMOTE_LOOP (0xC0) +#define MCF_PSC_PSCMR_SB_STOP_BITS_1 (0x7) +#define MCF_PSC_PSCMR_SB_STOP_BITS_15 (0x8) +#define MCF_PSC_PSCMR_SB_STOP_BITS_2 (0xF) +#define MCF_PSC_PSCMR_PM_MULTI_ADDR (0x1C) +#define MCF_PSC_PSCMR_PM_MULTI_DATA (0x18) +#define MCF_PSC_PSCMR_PM_NONE (0x10) +#define MCF_PSC_PSCMR_PM_FORCE_HI (0xC) +#define MCF_PSC_PSCMR_PM_FORCE_LO (0x8) +#define MCF_PSC_PSCMR_PM_ODD (0x4) +#define MCF_PSC_PSCMR_PM_EVEN (0) +#define MCF_PSC_PSCMR_BC(x) (((x)&0x3)<<0) +#define MCF_PSC_PSCMR_BC_5 (0) +#define MCF_PSC_PSCMR_BC_6 (0x1) +#define MCF_PSC_PSCMR_BC_7 (0x2) +#define MCF_PSC_PSCMR_BC_8 (0x3) +#define MCF_PSC_PSCMR_PT (0x4) +#define MCF_PSC_PSCMR_PM(x) (((x)&0x3)<<0x3) +#define MCF_PSC_PSCMR_ERR (0x20) +#define MCF_PSC_PSCMR_RXIRQ_FU (0x40) +#define MCF_PSC_PSCMR_RXRTS (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCCSR */ +#define MCF_PSC_PSCCSR_TCSEL(x) (((x)&0xF)<<0) +#define MCF_PSC_PSCCSR_RCSEL(x) (((x)&0xF)<<0x4) +#define MCF_PSC_PSCCSR_TCSEL_SYS_CLK (0x0D) +#define MCF_PSC_PSCCSR_TCSEL_CTM16 (0x0E) +#define MCF_PSC_PSCCSR_TCSEL_CTM (0x0F) +#define MCF_PSC_PSCCSR_RCSEL_SYS_CLK (0xD0) +#define MCF_PSC_PSCCSR_RCSEL_CTM16 (0xE0) +#define MCF_PSC_PSCCSR_RCSEL_CTM (0xF0) + +/* Bit definitions and macros for MCF_PSC_PSCSR */ +#define MCF_PSC_PSCSR_ERR (0x40) +#define MCF_PSC_PSCSR_CDE_DEOF (0x80) +#define MCF_PSC_PSCSR_RXRDY (0x100) +#define MCF_PSC_PSCSR_FU (0x200) +#define MCF_PSC_PSCSR_TXRDY (0x400) +#define MCF_PSC_PSCSR_TXEMP_URERR (0x800) +#define MCF_PSC_PSCSR_OE (0x1000) +#define MCF_PSC_PSCSR_PE_CRCERR (0x2000) +#define MCF_PSC_PSCSR_FE_PHYERR (0x4000) +#define MCF_PSC_PSCSR_RB_NEOF (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCCR */ +#define MCF_PSC_PSCCR_RXC(x) (((x)&0x3)<<0) +#define MCF_PSC_PSCCR_RX_ENABLED (0x1) +#define MCF_PSC_PSCCR_RX_DISABLED (0x2) +#define MCF_PSC_PSCCR_TXC(x) (((x)&0x3)<<0x2) +#define MCF_PSC_PSCCR_TX_ENABLED (0x4) +#define MCF_PSC_PSCCR_TX_DISABLED (0x8) +#define MCF_PSC_PSCCR_MISC(x) (((x)&0x7)<<0x4) +#define MCF_PSC_PSCCR_NONE (0) +#define MCF_PSC_PSCCR_RESET_MR (0x10) +#define MCF_PSC_PSCCR_RESET_RX (0x20) +#define MCF_PSC_PSCCR_RESET_TX (0x30) +#define MCF_PSC_PSCCR_RESET_ERROR (0x40) +#define MCF_PSC_PSCCR_RESET_BKCHGINT (0x50) +#define MCF_PSC_PSCCR_START_BREAK (0x60) +#define MCF_PSC_PSCCR_STOP_BREAK (0x70) + +/* Bit definitions and macros for MCF_PSC_PSCRB_8BIT */ +#define MCF_PSC_PSCRB_8BIT_RB3(x) (((x)&0xFF)<<0) +#define MCF_PSC_PSCRB_8BIT_RB2(x) (((x)&0xFF)<<0x8) +#define MCF_PSC_PSCRB_8BIT_RB1(x) (((x)&0xFF)<<0x10) +#define MCF_PSC_PSCRB_8BIT_RB0(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PSC_PSCTB_8BIT */ +#define MCF_PSC_PSCTB_8BIT_TB3(x) (((x)&0xFF)<<0) +#define MCF_PSC_PSCTB_8BIT_TB2(x) (((x)&0xFF)<<0x8) +#define MCF_PSC_PSCTB_8BIT_TB1(x) (((x)&0xFF)<<0x10) +#define MCF_PSC_PSCTB_8BIT_TB0(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PSC_PSCRB_16BIT */ +#define MCF_PSC_PSCRB_16BIT_RB1(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCRB_16BIT_RB0(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PSC_PSCTB_16BIT */ +#define MCF_PSC_PSCTB_16BIT_TB1(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCTB_16BIT_TB0(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PSC_PSCRB_AC97 */ +#define MCF_PSC_PSCRB_AC97_SOF (0x800) +#define MCF_PSC_PSCRB_AC97_RB(x) (((x)&0xFFFFF)<<0xC) + +/* Bit definitions and macros for MCF_PSC_PSCTB_AC97 */ +#define MCF_PSC_PSCTB_AC97_TB(x) (((x)&0xFFFFF)<<0xC) + +/* Bit definitions and macros for MCF_PSC_PSCIPCR */ +#define MCF_PSC_PSCIPCR_RESERVED (0xC) +#define MCF_PSC_PSCIPCR_CTS (0xD) +#define MCF_PSC_PSCIPCR_D_CTS (0x1C) +#define MCF_PSC_PSCIPCR_SYNC (0x8C) + +/* Bit definitions and macros for MCF_PSC_PSCACR */ +#define MCF_PSC_PSCACR_IEC0 (0x1) + +/* Bit definitions and macros for MCF_PSC_PSCIMR */ +#define MCF_PSC_PSCIMR_ERR (0x40) +#define MCF_PSC_PSCIMR_DEOF (0x80) +#define MCF_PSC_PSCIMR_TXRDY (0x100) +#define MCF_PSC_PSCIMR_RXRDY_FU (0x200) +#define MCF_PSC_PSCIMR_DB (0x400) +#define MCF_PSC_PSCIMR_IPC (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCISR */ +#define MCF_PSC_PSCISR_ERR (0x40) +#define MCF_PSC_PSCISR_DEOF (0x80) +#define MCF_PSC_PSCISR_TXRDY (0x100) +#define MCF_PSC_PSCISR_RXRDY_FU (0x200) +#define MCF_PSC_PSCISR_DB (0x400) +#define MCF_PSC_PSCISR_IPC (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCCTUR */ +#define MCF_PSC_PSCCTUR_CT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCCTLR */ +#define MCF_PSC_PSCCTLR_CT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCIP */ +#define MCF_PSC_PSCIP_CTS (0x1) +#define MCF_PSC_PSCIP_TGL (0x40) +#define MCF_PSC_PSCIP_LPWR_B (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCOPSET */ +#define MCF_PSC_PSCOPSET_RTS (0x1) + +/* Bit definitions and macros for MCF_PSC_PSCOPRESET */ +#define MCF_PSC_PSCOPRESET_RTS (0x1) + +/* Bit definitions and macros for MCF_PSC_PSCSICR */ +#define MCF_PSC_PSCSICR_SIM(x) (((x)&0x7)<<0) +#define MCF_PSC_PSCSICR_SIM_UART (0) +#define MCF_PSC_PSCSICR_SIM_MODEM8 (0x1) +#define MCF_PSC_PSCSICR_SIM_MODEM16 (0x2) +#define MCF_PSC_PSCSICR_SIM_AC97 (0x3) +#define MCF_PSC_PSCSICR_SIM_SIR (0x4) +#define MCF_PSC_PSCSICR_SIM_MIR (0x5) +#define MCF_PSC_PSCSICR_SIM_FIR (0x6) +#define MCF_PSC_PSCSICR_SHDIR (0x10) +#define MCF_PSC_PSCSICR_DTS1 (0x20) +#define MCF_PSC_PSCSICR_AWR (0x40) +#define MCF_PSC_PSCSICR_ACRB (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCIRCR1 */ +#define MCF_PSC_PSCIRCR1_SPUL (0x1) +#define MCF_PSC_PSCIRCR1_SIPEN (0x2) +#define MCF_PSC_PSCIRCR1_FD (0x4) + +/* Bit definitions and macros for MCF_PSC_PSCIRCR2 */ +#define MCF_PSC_PSCIRCR2_NXTEOF (0x1) +#define MCF_PSC_PSCIRCR2_ABORT (0x2) +#define MCF_PSC_PSCIRCR2_SIPREQ (0x4) + +/* Bit definitions and macros for MCF_PSC_PSCIRSDR */ +#define MCF_PSC_PSCIRSDR_IRSTIM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCIRMDR */ +#define MCF_PSC_PSCIRMDR_M_FDIV(x) (((x)&0x7F)<<0) +#define MCF_PSC_PSCIRMDR_FREQ (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCIRFDR */ +#define MCF_PSC_PSCIRFDR_F_FDIV(x) (((x)&0xF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFCNT */ +#define MCF_PSC_PSCRFCNT_CNT(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFCNT */ +#define MCF_PSC_PSCTFCNT_CNT(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFDR */ +#define MCF_PSC_PSCRFDR_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFSR */ +#define MCF_PSC_PSCRFSR_EMT (0x1) +#define MCF_PSC_PSCRFSR_ALARM (0x2) +#define MCF_PSC_PSCRFSR_FU (0x4) +#define MCF_PSC_PSCRFSR_FRMRDY (0x8) +#define MCF_PSC_PSCRFSR_OF (0x10) +#define MCF_PSC_PSCRFSR_UF (0x20) +#define MCF_PSC_PSCRFSR_RXW (0x40) +#define MCF_PSC_PSCRFSR_FAE (0x80) +#define MCF_PSC_PSCRFSR_FRM(x) (((x)&0xF)<<0x8) +#define MCF_PSC_PSCRFSR_FRM_BYTE0 (0x800) +#define MCF_PSC_PSCRFSR_FRM_BYTE1 (0x400) +#define MCF_PSC_PSCRFSR_FRM_BYTE2 (0x200) +#define MCF_PSC_PSCRFSR_FRM_BYTE3 (0x100) +#define MCF_PSC_PSCRFSR_TAG(x) (((x)&0x3)<<0xC) +#define MCF_PSC_PSCRFSR_TXW (0x4000) +#define MCF_PSC_PSCRFSR_IP (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCRFCR */ +#define MCF_PSC_PSCRFCR_CNTR(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCRFCR_TXW_MSK (0x40000) +#define MCF_PSC_PSCRFCR_OF_MSK (0x80000) +#define MCF_PSC_PSCRFCR_UF_MSK (0x100000) +#define MCF_PSC_PSCRFCR_RXW_MSK (0x200000) +#define MCF_PSC_PSCRFCR_FAE_MSK (0x400000) +#define MCF_PSC_PSCRFCR_IP_MSK (0x800000) +#define MCF_PSC_PSCRFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PSC_PSCRFCR_FRMEN (0x8000000) +#define MCF_PSC_PSCRFCR_TIMER (0x10000000) + +/* Bit definitions and macros for MCF_PSC_PSCRFAR */ +#define MCF_PSC_PSCRFAR_ALARM(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFRP */ +#define MCF_PSC_PSCRFRP_READ(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFWP */ +#define MCF_PSC_PSCRFWP_WRITE(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRLRFP */ +#define MCF_PSC_PSCRLRFP_LRFP(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRLWFP */ +#define MCF_PSC_PSCRLWFP_LWFP(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFDR */ +#define MCF_PSC_PSCTFDR_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFSR */ +#define MCF_PSC_PSCTFSR_EMT (0x1) +#define MCF_PSC_PSCTFSR_ALARM (0x2) +#define MCF_PSC_PSCTFSR_FU (0x4) +#define MCF_PSC_PSCTFSR_FRMRDY (0x8) +#define MCF_PSC_PSCTFSR_OF (0x10) +#define MCF_PSC_PSCTFSR_UF (0x20) +#define MCF_PSC_PSCTFSR_RXW (0x40) +#define MCF_PSC_PSCTFSR_FAE (0x80) +#define MCF_PSC_PSCTFSR_FRM(x) (((x)&0xF)<<0x8) +#define MCF_PSC_PSCTFSR_FRM_BYTE0 (0x800) +#define MCF_PSC_PSCTFSR_FRM_BYTE1 (0x400) +#define MCF_PSC_PSCTFSR_FRM_BYTE2 (0x200) +#define MCF_PSC_PSCTFSR_FRM_BYTE3 (0x100) +#define MCF_PSC_PSCTFSR_TAG(x) (((x)&0x3)<<0xC) +#define MCF_PSC_PSCTFSR_TXW (0x4000) +#define MCF_PSC_PSCTFSR_IP (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCTFCR */ +#define MCF_PSC_PSCTFCR_CNTR(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCTFCR_TXW_MSK (0x40000) +#define MCF_PSC_PSCTFCR_OF_MSK (0x80000) +#define MCF_PSC_PSCTFCR_UF_MSK (0x100000) +#define MCF_PSC_PSCTFCR_RXW_MSK (0x200000) +#define MCF_PSC_PSCTFCR_FAE_MSK (0x400000) +#define MCF_PSC_PSCTFCR_IP_MSK (0x800000) +#define MCF_PSC_PSCTFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PSC_PSCTFCR_FRMEN (0x8000000) +#define MCF_PSC_PSCTFCR_TIMER (0x10000000) +#define MCF_PSC_PSCTFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PSC_PSCTFAR */ +#define MCF_PSC_PSCTFAR_ALARM(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFRP */ +#define MCF_PSC_PSCTFRP_READ(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFWP */ +#define MCF_PSC_PSCTFWP_WRITE(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTLRFP */ +#define MCF_PSC_PSCTLRFP_LRFP(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTLWFP */ +#define MCF_PSC_PSCTLWFP_LWFP(x) (((x)&0x1FF)<<0) + + +#endif /* __MCF5475_PSC_H__ */ diff --git a/tos/pci_mem/include/MCF5475_SDRAMC.h b/tos/pci_mem/include/MCF5475_SDRAMC.h new file mode 100644 index 0000000..6cdbd68 --- /dev/null +++ b/tos/pci_mem/include/MCF5475_SDRAMC.h @@ -0,0 +1,106 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SDRAMC_H__ +#define __MCF5475_SDRAMC_H__ + + +/********************************************************************* +* +* Synchronous DRAM Controller (SDRAMC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SDRAMC_SDRAMDS (*(volatile uint32_t*)(&_MBAR[0x4])) +#define MCF_SDRAMC_CS0CFG (*(volatile uint32_t*)(&_MBAR[0x20])) +#define MCF_SDRAMC_CS1CFG (*(volatile uint32_t*)(&_MBAR[0x24])) +#define MCF_SDRAMC_CS2CFG (*(volatile uint32_t*)(&_MBAR[0x28])) +#define MCF_SDRAMC_CS3CFG (*(volatile uint32_t*)(&_MBAR[0x2C])) +#define MCF_SDRAMC_SDMR (*(volatile uint32_t*)(&_MBAR[0x100])) +#define MCF_SDRAMC_SDCR (*(volatile uint32_t*)(&_MBAR[0x104])) +#define MCF_SDRAMC_SDCFG1 (*(volatile uint32_t*)(&_MBAR[0x108])) +#define MCF_SDRAMC_SDCFG2 (*(volatile uint32_t*)(&_MBAR[0x10C])) +#define MCF_SDRAMC_CSCFG(x) (*(volatile uint32_t*)(&_MBAR[0x20 + ((x)*0x4)])) + + +/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */ +#define MCF_SDRAMC_SDRAMDS_SB_D(x) (((x)&0x3)<<0) +#define MCF_SDRAMC_SDRAMDS_SB_S(x) (((x)&0x3)<<0x2) +#define MCF_SDRAMC_SDRAMDS_SB_A(x) (((x)&0x3)<<0x4) +#define MCF_SDRAMC_SDRAMDS_SB_C(x) (((x)&0x3)<<0x6) +#define MCF_SDRAMC_SDRAMDS_SB_E(x) (((x)&0x3)<<0x8) +#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA (0) +#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA (0x1) +#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA (0x2) +#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE (0x3) + +/* Bit definitions and macros for MCF_SDRAMC_CSCFG */ +#define MCF_SDRAMC_CSCFG_CSSZ(x) (((x)&0x1F)<<0) +#define MCF_SDRAMC_CSCFG_CSSZ_DISABLED (0) +#define MCF_SDRAMC_CSCFG_CSSZ_1MBYTE (0x13) +#define MCF_SDRAMC_CSCFG_CSSZ_2MBYTE (0x14) +#define MCF_SDRAMC_CSCFG_CSSZ_4MBYTE (0x15) +#define MCF_SDRAMC_CSCFG_CSSZ_8MBYTE (0x16) +#define MCF_SDRAMC_CSCFG_CSSZ_16MBYTE (0x17) +#define MCF_SDRAMC_CSCFG_CSSZ_32MBYTE (0x18) +#define MCF_SDRAMC_CSCFG_CSSZ_64MBYTE (0x19) +#define MCF_SDRAMC_CSCFG_CSSZ_128MBYTE (0x1A) +#define MCF_SDRAMC_CSCFG_CSSZ_256MBYTE (0x1B) +#define MCF_SDRAMC_CSCFG_CSSZ_512MBYTE (0x1C) +#define MCF_SDRAMC_CSCFG_CSSZ_1GBYTE (0x1D) +#define MCF_SDRAMC_CSCFG_CSSZ_2GBYTE (0x1E) +#define MCF_SDRAMC_CSCFG_CSSZ_4GBYTE (0x1F) +#define MCF_SDRAMC_CSCFG_CSBA(x) (((x)&0xFFF)<<0x14) +#define MCF_SDRAMC_CSCFG_BA(x) ((x)&0xFFF00000) + +/* Bit definitions and macros for MCF_SDRAMC_SDMR */ +#define MCF_SDRAMC_SDMR_CMD (0x10000) +#define MCF_SDRAMC_SDMR_AD(x) (((x)&0xFFF)<<0x12) +#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x3)<<0x1E) +#define MCF_SDRAMC_SDMR_BK_LMR (0) +#define MCF_SDRAMC_SDMR_BK_LEMR (0x40000000) + +/* Bit definitions and macros for MCF_SDRAMC_SDCR */ +#define MCF_SDRAMC_SDCR_IPALL (0x2) +#define MCF_SDRAMC_SDCR_IREF (0x4) +#define MCF_SDRAMC_SDCR_BUFF (0x10) +#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0xF)<<0x8) +#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x3F)<<0x10) +#define MCF_SDRAMC_SDCR_DRIVE (0x400000) +#define MCF_SDRAMC_SDCR_AP (0x800000) +#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x3)<<0x18) +#define MCF_SDRAMC_SDCR_REF (0x10000000) +#define MCF_SDRAMC_SDCR_DDR (0x20000000) +#define MCF_SDRAMC_SDCR_CKE (0x40000000) +#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) + +/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ +#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x7)<<0x4) +#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0xF)<<0x8) +#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x7)<<0xC) +#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x7)<<0x10) +#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0xF)<<0x14) +#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x7)<<0x18) +#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0xF)<<0x1C) + +/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */ +#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0xF)<<0x10) +#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0xF)<<0x14) +#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0xF)<<0x18) +#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0xF)<<0x1C) + + +#endif /* __MCF5475_SDRAMC_H__ */ diff --git a/tos/pci_mem/include/MCF5475_SEC.h b/tos/pci_mem/include/MCF5475_SEC.h new file mode 100644 index 0000000..8deff0b --- /dev/null +++ b/tos/pci_mem/include/MCF5475_SEC.h @@ -0,0 +1,398 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SEC_H__ +#define __MCF5475_SEC_H__ + + +/********************************************************************* +* +* Integrated Security Engine (SEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SEC_EUACRH (*(volatile uint32_t*)(&_MBAR[0x21000])) +#define MCF_SEC_EUACRL (*(volatile uint32_t*)(&_MBAR[0x21004])) +#define MCF_SEC_SIMRH (*(volatile uint32_t*)(&_MBAR[0x21008])) +#define MCF_SEC_SIMRL (*(volatile uint32_t*)(&_MBAR[0x2100C])) +#define MCF_SEC_SISRH (*(volatile uint32_t*)(&_MBAR[0x21010])) +#define MCF_SEC_SISRL (*(volatile uint32_t*)(&_MBAR[0x21014])) +#define MCF_SEC_SICRH (*(volatile uint32_t*)(&_MBAR[0x21018])) +#define MCF_SEC_SICRL (*(volatile uint32_t*)(&_MBAR[0x2101C])) +#define MCF_SEC_SIDR (*(volatile uint32_t*)(&_MBAR[0x21020])) +#define MCF_SEC_EUASRH (*(volatile uint32_t*)(&_MBAR[0x21028])) +#define MCF_SEC_EUASRL (*(volatile uint32_t*)(&_MBAR[0x2102C])) +#define MCF_SEC_SMCR (*(volatile uint32_t*)(&_MBAR[0x21030])) +#define MCF_SEC_MEAR (*(volatile uint32_t*)(&_MBAR[0x21038])) +#define MCF_SEC_CCCR0 (*(volatile uint32_t*)(&_MBAR[0x2200C])) +#define MCF_SEC_CCPSRH0 (*(volatile uint32_t*)(&_MBAR[0x22010])) +#define MCF_SEC_CCPSRL0 (*(volatile uint32_t*)(&_MBAR[0x22014])) +#define MCF_SEC_CDPR0 (*(volatile uint32_t*)(&_MBAR[0x22044])) +#define MCF_SEC_FR0 (*(volatile uint32_t*)(&_MBAR[0x2204C])) +#define MCF_SEC_CCCR1 (*(volatile uint32_t*)(&_MBAR[0x2300C])) +#define MCF_SEC_CCPSRH1 (*(volatile uint32_t*)(&_MBAR[0x23010])) +#define MCF_SEC_CCPSRL1 (*(volatile uint32_t*)(&_MBAR[0x23014])) +#define MCF_SEC_CDPR1 (*(volatile uint32_t*)(&_MBAR[0x23044])) +#define MCF_SEC_FR1 (*(volatile uint32_t*)(&_MBAR[0x2304C])) +#define MCF_SEC_AFRCR (*(volatile uint32_t*)(&_MBAR[0x28018])) +#define MCF_SEC_AFSR (*(volatile uint32_t*)(&_MBAR[0x28028])) +#define MCF_SEC_AFISR (*(volatile uint32_t*)(&_MBAR[0x28030])) +#define MCF_SEC_AFIMR (*(volatile uint32_t*)(&_MBAR[0x28038])) +#define MCF_SEC_DRCR (*(volatile uint32_t*)(&_MBAR[0x2A018])) +#define MCF_SEC_DSR (*(volatile uint32_t*)(&_MBAR[0x2A028])) +#define MCF_SEC_DISR (*(volatile uint32_t*)(&_MBAR[0x2A030])) +#define MCF_SEC_DIMR (*(volatile uint32_t*)(&_MBAR[0x2A038])) +#define MCF_SEC_MDRCR (*(volatile uint32_t*)(&_MBAR[0x2C018])) +#define MCF_SEC_MDSR (*(volatile uint32_t*)(&_MBAR[0x2C028])) +#define MCF_SEC_MDISR (*(volatile uint32_t*)(&_MBAR[0x2C030])) +#define MCF_SEC_MDIMR (*(volatile uint32_t*)(&_MBAR[0x2C038])) +#define MCF_SEC_RNGRCR (*(volatile uint32_t*)(&_MBAR[0x2E018])) +#define MCF_SEC_RNGSR (*(volatile uint32_t*)(&_MBAR[0x2E028])) +#define MCF_SEC_RNGISR (*(volatile uint32_t*)(&_MBAR[0x2E030])) +#define MCF_SEC_RNGIMR (*(volatile uint32_t*)(&_MBAR[0x2E038])) +#define MCF_SEC_AESRCR (*(volatile uint32_t*)(&_MBAR[0x32018])) +#define MCF_SEC_AESSR (*(volatile uint32_t*)(&_MBAR[0x32028])) +#define MCF_SEC_AESISR (*(volatile uint32_t*)(&_MBAR[0x32030])) +#define MCF_SEC_AESIMR (*(volatile uint32_t*)(&_MBAR[0x32038])) +#define MCF_SEC_CCCRn(x) (*(volatile uint32_t*)(&_MBAR[0x2200C + ((x)*0x1000)])) +#define MCF_SEC_CCPSRHn(x) (*(volatile uint32_t*)(&_MBAR[0x22010 + ((x)*0x1000)])) +#define MCF_SEC_CCPSRLn(x) (*(volatile uint32_t*)(&_MBAR[0x22014 + ((x)*0x1000)])) +#define MCF_SEC_CDPRn(x) (*(volatile uint32_t*)(&_MBAR[0x22044 + ((x)*0x1000)])) +#define MCF_SEC_FRn(x) (*(volatile uint32_t*)(&_MBAR[0x2204C + ((x)*0x1000)])) + + +/* Bit definitions and macros for MCF_SEC_EUACRH */ +#define MCF_SEC_EUACRH_AFEU(x) (((x)&0xF)<<0) +#define MCF_SEC_EUACRH_AFFEU_NOASSIGN (0) +#define MCF_SEC_EUACRH_AFFEU_CHA0 (0x1) +#define MCF_SEC_EUACRH_AFFEU_CHA1 (0x2) +#define MCF_SEC_EUACRH_MDEU(x) (((x)&0xF)<<0x8) +#define MCF_SEC_EUACRH_MDEU_NOASSIGN (0) +#define MCF_SEC_EUACRH_MDEU_CHA0 (0x100) +#define MCF_SEC_EUACRH_MDEU_CHA1 (0x200) +#define MCF_SEC_EUACRH_RNG(x) (((x)&0xF)<<0x18) +#define MCF_SEC_EUACRH_RNG_NOASSIGN (0) +#define MCF_SEC_EUACRH_RNG_CHA0 (0x1000000) +#define MCF_SEC_EUACRH_RNG_CHA1 (0x2000000) + +/* Bit definitions and macros for MCF_SEC_EUACRL */ +#define MCF_SEC_EUACRL_AESU(x) (((x)&0xF)<<0x10) +#define MCF_SEC_EUACRL_AESU_NOASSIGN (0) +#define MCF_SEC_EUACRL_AESU_CHA0 (0x10000) +#define MCF_SEC_EUACRL_AESU_CHA1 (0x20000) +#define MCF_SEC_EUACRL_DEU(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SEC_SIMRH */ +#define MCF_SEC_SIMRH_AERR (0x8000000) +#define MCF_SEC_SIMRH_CHA_0_DN (0x10000000) +#define MCF_SEC_SIMRH_CHA_0_ERR (0x20000000) +#define MCF_SEC_SIMRH_CHA_1_DN (0x40000000) +#define MCF_SEC_SIMRH_CHA_1_ERR (0x80000000) + +/* Bit definitions and macros for MCF_SEC_SIMRL */ +#define MCF_SEC_SIMRL_TEA (0x40) +#define MCF_SEC_SIMRL_DEU_DN (0x100) +#define MCF_SEC_SIMRL_DEU_ERR (0x200) +#define MCF_SEC_SIMRL_AESU_DN (0x1000) +#define MCF_SEC_SIMRL_AESU_ERR (0x2000) +#define MCF_SEC_SIMRL_MDEU_DN (0x10000) +#define MCF_SEC_SIMRL_MDEU_ERR (0x20000) +#define MCF_SEC_SIMRL_AFEU_DN (0x100000) +#define MCF_SEC_SIMRL_AFEU_ERR (0x200000) +#define MCF_SEC_SIMRL_RNG_DN (0x1000000) +#define MCF_SEC_SIMRL_RNG_ERR (0x2000000) + +/* Bit definitions and macros for MCF_SEC_SISRH */ +#define MCF_SEC_SISRH_AERR (0x8000000) +#define MCF_SEC_SISRH_CHA_0_DN (0x10000000) +#define MCF_SEC_SISRH_CHA_0_ERR (0x20000000) +#define MCF_SEC_SISRH_CHA_1_DN (0x40000000) +#define MCF_SEC_SISRH_CHA_1_ERR (0x80000000) + +/* Bit definitions and macros for MCF_SEC_SISRL */ +#define MCF_SEC_SISRL_TEA (0x40) +#define MCF_SEC_SISRL_DEU_DN (0x100) +#define MCF_SEC_SISRL_DEU_ERR (0x200) +#define MCF_SEC_SISRL_AESU_DN (0x1000) +#define MCF_SEC_SISRL_AESU_ERR (0x2000) +#define MCF_SEC_SISRL_MDEU_DN (0x10000) +#define MCF_SEC_SISRL_MDEU_ERR (0x20000) +#define MCF_SEC_SISRL_AFEU_DN (0x100000) +#define MCF_SEC_SISRL_AFEU_ERR (0x200000) +#define MCF_SEC_SISRL_RNG_DN (0x1000000) +#define MCF_SEC_SISRL_RNG_ERR (0x2000000) + +/* Bit definitions and macros for MCF_SEC_SICRH */ +#define MCF_SEC_SICRH_AERR (0x8000000) +#define MCF_SEC_SICRH_CHA_0_DN (0x10000000) +#define MCF_SEC_SICRH_CHA_0_ERR (0x20000000) +#define MCF_SEC_SICRH_CHA_1_DN (0x40000000) +#define MCF_SEC_SICRH_CHA_1_ERR (0x80000000) + +/* Bit definitions and macros for MCF_SEC_SICRL */ +#define MCF_SEC_SICRL_TEA (0x40) +#define MCF_SEC_SICRL_DEU_DN (0x100) +#define MCF_SEC_SICRL_DEU_ERR (0x200) +#define MCF_SEC_SICRL_AESU_DN (0x1000) +#define MCF_SEC_SICRL_AESU_ERR (0x2000) +#define MCF_SEC_SICRL_MDEU_DN (0x10000) +#define MCF_SEC_SICRL_MDEU_ERR (0x20000) +#define MCF_SEC_SICRL_AFEU_DN (0x100000) +#define MCF_SEC_SICRL_AFEU_ERR (0x200000) +#define MCF_SEC_SICRL_RNG_DN (0x1000000) +#define MCF_SEC_SICRL_RNG_ERR (0x2000000) + +/* Bit definitions and macros for MCF_SEC_SIDR */ +#define MCF_SEC_SIDR_VERSION(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_EUASRH */ +#define MCF_SEC_EUASRH_AFEU(x) (((x)&0xF)<<0) +#define MCF_SEC_EUASRH_MDEU(x) (((x)&0xF)<<0x8) +#define MCF_SEC_EUASRH_RNG(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SEC_EUASRL */ +#define MCF_SEC_EUASRL_AESU(x) (((x)&0xF)<<0x10) +#define MCF_SEC_EUASRL_DEU(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SEC_SMCR */ +#define MCF_SEC_SMCR_CURR_CHAN(x) (((x)&0xF)<<0x4) +#define MCF_SEC_SMCR_CURR_CHAN_1 (0x10) +#define MCF_SEC_SMCR_CURR_CHAN_2 (0x20) +#define MCF_SEC_SMCR_SWR (0x1000000) + +/* Bit definitions and macros for MCF_SEC_MEAR */ +#define MCF_SEC_MEAR_ADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_CCCRn */ +#define MCF_SEC_CCCRn_RST (0x1) +#define MCF_SEC_CCCRn_CDIE (0x2) +#define MCF_SEC_CCCRn_NT (0x4) +#define MCF_SEC_CCCRn_NE (0x8) +#define MCF_SEC_CCCRn_WE (0x10) +#define MCF_SEC_CCCRn_BURST_SIZE(x) (((x)&0x7)<<0x8) +#define MCF_SEC_CCCRn_BURST_SIZE_2 (0) +#define MCF_SEC_CCCRn_BURST_SIZE_8 (0x100) +#define MCF_SEC_CCCRn_BURST_SIZE_16 (0x200) +#define MCF_SEC_CCCRn_BURST_SIZE_24 (0x300) +#define MCF_SEC_CCCRn_BURST_SIZE_32 (0x400) +#define MCF_SEC_CCCRn_BURST_SIZE_40 (0x500) +#define MCF_SEC_CCCRn_BURST_SIZE_48 (0x600) +#define MCF_SEC_CCCRn_BURST_SIZE_56 (0x700) + +/* Bit definitions and macros for MCF_SEC_CCPSRHn */ +#define MCF_SEC_CCPSRHn_STATE(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_SEC_CCPSRLn */ +#define MCF_SEC_CCPSRLn_PAIR_PTR(x) (((x)&0xFF)<<0) +#define MCF_SEC_CCPSRLn_EUERR (0x100) +#define MCF_SEC_CCPSRLn_SERR (0x200) +#define MCF_SEC_CCPSRLn_DERR (0x400) +#define MCF_SEC_CCPSRLn_PERR (0x1000) +#define MCF_SEC_CCPSRLn_TEA (0x2000) +#define MCF_SEC_CCPSRLn_SD (0x10000) +#define MCF_SEC_CCPSRLn_PD (0x20000) +#define MCF_SEC_CCPSRLn_SRD (0x40000) +#define MCF_SEC_CCPSRLn_PRD (0x80000) +#define MCF_SEC_CCPSRLn_SG (0x100000) +#define MCF_SEC_CCPSRLn_PG (0x200000) +#define MCF_SEC_CCPSRLn_SR (0x400000) +#define MCF_SEC_CCPSRLn_PR (0x800000) +#define MCF_SEC_CCPSRLn_MO (0x1000000) +#define MCF_SEC_CCPSRLn_MI (0x2000000) +#define MCF_SEC_CCPSRLn_STAT (0x4000000) + +/* Bit definitions and macros for MCF_SEC_CDPRn */ +#define MCF_SEC_CDPRn_CDP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_FRn */ +#define MCF_SEC_FRn_FETCH_ADDR(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_AFRCR */ +#define MCF_SEC_AFRCR_SR (0x1000000) +#define MCF_SEC_AFRCR_MI (0x2000000) +#define MCF_SEC_AFRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_AFSR */ +#define MCF_SEC_AFSR_RD (0x1000000) +#define MCF_SEC_AFSR_ID (0x2000000) +#define MCF_SEC_AFSR_IE (0x4000000) +#define MCF_SEC_AFSR_OFR (0x8000000) +#define MCF_SEC_AFSR_IFW (0x10000000) +#define MCF_SEC_AFSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_AFISR */ +#define MCF_SEC_AFISR_DSE (0x10000) +#define MCF_SEC_AFISR_KSE (0x20000) +#define MCF_SEC_AFISR_CE (0x40000) +#define MCF_SEC_AFISR_ERE (0x80000) +#define MCF_SEC_AFISR_IE (0x100000) +#define MCF_SEC_AFISR_OFU (0x2000000) +#define MCF_SEC_AFISR_IFO (0x4000000) +#define MCF_SEC_AFISR_IFE (0x10000000) +#define MCF_SEC_AFISR_OFE (0x20000000) +#define MCF_SEC_AFISR_AE (0x40000000) +#define MCF_SEC_AFISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_AFIMR */ +#define MCF_SEC_AFIMR_DSE (0x10000) +#define MCF_SEC_AFIMR_KSE (0x20000) +#define MCF_SEC_AFIMR_CE (0x40000) +#define MCF_SEC_AFIMR_ERE (0x80000) +#define MCF_SEC_AFIMR_IE (0x100000) +#define MCF_SEC_AFIMR_OFU (0x2000000) +#define MCF_SEC_AFIMR_IFO (0x4000000) +#define MCF_SEC_AFIMR_IFE (0x10000000) +#define MCF_SEC_AFIMR_OFE (0x20000000) +#define MCF_SEC_AFIMR_AE (0x40000000) +#define MCF_SEC_AFIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_DRCR */ +#define MCF_SEC_DRCR_SR (0x1000000) +#define MCF_SEC_DRCR_MI (0x2000000) +#define MCF_SEC_DRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_DSR */ +#define MCF_SEC_DSR_RD (0x1000000) +#define MCF_SEC_DSR_ID (0x2000000) +#define MCF_SEC_DSR_IE (0x4000000) +#define MCF_SEC_DSR_OFR (0x8000000) +#define MCF_SEC_DSR_IFW (0x10000000) +#define MCF_SEC_DSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_DISR */ +#define MCF_SEC_DISR_DSE (0x10000) +#define MCF_SEC_DISR_KSE (0x20000) +#define MCF_SEC_DISR_CE (0x40000) +#define MCF_SEC_DISR_ERE (0x80000) +#define MCF_SEC_DISR_IE (0x100000) +#define MCF_SEC_DISR_KPE (0x200000) +#define MCF_SEC_DISR_OFU (0x2000000) +#define MCF_SEC_DISR_IFO (0x4000000) +#define MCF_SEC_DISR_IFE (0x10000000) +#define MCF_SEC_DISR_OFE (0x20000000) +#define MCF_SEC_DISR_AE (0x40000000) +#define MCF_SEC_DISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_DIMR */ +#define MCF_SEC_DIMR_DSE (0x10000) +#define MCF_SEC_DIMR_KSE (0x20000) +#define MCF_SEC_DIMR_CE (0x40000) +#define MCF_SEC_DIMR_ERE (0x80000) +#define MCF_SEC_DIMR_IE (0x100000) +#define MCF_SEC_DIMR_KPE (0x200000) +#define MCF_SEC_DIMR_OFU (0x2000000) +#define MCF_SEC_DIMR_IFO (0x4000000) +#define MCF_SEC_DIMR_IFE (0x10000000) +#define MCF_SEC_DIMR_OFE (0x20000000) +#define MCF_SEC_DIMR_AE (0x40000000) +#define MCF_SEC_DIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_MDRCR */ +#define MCF_SEC_MDRCR_SR (0x1000000) +#define MCF_SEC_MDRCR_MI (0x2000000) +#define MCF_SEC_MDRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_MDSR */ +#define MCF_SEC_MDSR_RD (0x1000000) +#define MCF_SEC_MDSR_ID (0x2000000) +#define MCF_SEC_MDSR_IE (0x4000000) +#define MCF_SEC_MDSR_IFW (0x10000000) +#define MCF_SEC_MDSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_MDISR */ +#define MCF_SEC_MDISR_DSE (0x10000) +#define MCF_SEC_MDISR_KSE (0x20000) +#define MCF_SEC_MDISR_CE (0x40000) +#define MCF_SEC_MDISR_ERE (0x80000) +#define MCF_SEC_MDISR_IE (0x100000) +#define MCF_SEC_MDISR_IFO (0x4000000) +#define MCF_SEC_MDISR_AE (0x40000000) +#define MCF_SEC_MDISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_MDIMR */ +#define MCF_SEC_MDIMR_DSE (0x10000) +#define MCF_SEC_MDIMR_KSE (0x20000) +#define MCF_SEC_MDIMR_CE (0x40000) +#define MCF_SEC_MDIMR_ERE (0x80000) +#define MCF_SEC_MDIMR_IE (0x100000) +#define MCF_SEC_MDIMR_IFO (0x4000000) +#define MCF_SEC_MDIMR_AE (0x40000000) +#define MCF_SEC_MDIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_RNGRCR */ +#define MCF_SEC_RNGRCR_SR (0x1000000) +#define MCF_SEC_RNGRCR_MI (0x2000000) +#define MCF_SEC_RNGRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_RNGSR */ +#define MCF_SEC_RNGSR_RD (0x1000000) +#define MCF_SEC_RNGSR_IE (0x4000000) +#define MCF_SEC_RNGSR_OFR (0x8000000) +#define MCF_SEC_RNGSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_RNGISR */ +#define MCF_SEC_RNGISR_IE (0x100000) +#define MCF_SEC_RNGISR_OFU (0x2000000) +#define MCF_SEC_RNGISR_AE (0x40000000) +#define MCF_SEC_RNGISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_RNGIMR */ +#define MCF_SEC_RNGIMR_IE (0x100000) +#define MCF_SEC_RNGIMR_OFU (0x2000000) +#define MCF_SEC_RNGIMR_AE (0x40000000) +#define MCF_SEC_RNGIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_AESRCR */ +#define MCF_SEC_AESRCR_SR (0x1000000) +#define MCF_SEC_AESRCR_MI (0x2000000) +#define MCF_SEC_AESRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_AESSR */ +#define MCF_SEC_AESSR_RD (0x1000000) +#define MCF_SEC_AESSR_ID (0x2000000) +#define MCF_SEC_AESSR_IE (0x4000000) +#define MCF_SEC_AESSR_OFR (0x8000000) +#define MCF_SEC_AESSR_IFW (0x10000000) +#define MCF_SEC_AESSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_AESISR */ +#define MCF_SEC_AESISR_DSE (0x10000) +#define MCF_SEC_AESISR_KSE (0x20000) +#define MCF_SEC_AESISR_CE (0x40000) +#define MCF_SEC_AESISR_ERE (0x80000) +#define MCF_SEC_AESISR_IE (0x100000) +#define MCF_SEC_AESISR_OFU (0x2000000) +#define MCF_SEC_AESISR_IFO (0x4000000) +#define MCF_SEC_AESISR_IFE (0x10000000) +#define MCF_SEC_AESISR_OFE (0x20000000) +#define MCF_SEC_AESISR_AE (0x40000000) +#define MCF_SEC_AESISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_AESIMR */ +#define MCF_SEC_AESIMR_DSE (0x10000) +#define MCF_SEC_AESIMR_KSE (0x20000) +#define MCF_SEC_AESIMR_CE (0x40000) +#define MCF_SEC_AESIMR_ERE (0x80000) +#define MCF_SEC_AESIMR_IE (0x100000) +#define MCF_SEC_AESIMR_OFU (0x2000000) +#define MCF_SEC_AESIMR_IFO (0x4000000) +#define MCF_SEC_AESIMR_IFE (0x10000000) +#define MCF_SEC_AESIMR_OFE (0x20000000) +#define MCF_SEC_AESIMR_AE (0x40000000) +#define MCF_SEC_AESIMR_ME (0x80000000) + + +#endif /* __MCF5475_SEC_H__ */ diff --git a/tos/pci_mem/include/MCF5475_SIU.h b/tos/pci_mem/include/MCF5475_SIU.h new file mode 100644 index 0000000..efb2896 --- /dev/null +++ b/tos/pci_mem/include/MCF5475_SIU.h @@ -0,0 +1,67 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SIU_H__ +#define __MCF5475_SIU_H__ + + +/********************************************************************* +* +* System Integration Unit (SIU) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SIU_SBCR (*(volatile uint32_t*)(&_MBAR[0x10])) +#define MCF_SIU_SECSACR (*(volatile uint32_t*)(&_MBAR[0x38])) +#define MCF_SIU_RSR (*(volatile uint32_t*)(&_MBAR[0x44])) +#define MCF_SIU_JTAGID (*(volatile uint32_t*)(&_MBAR[0x50])) + + +/* Bit definitions and macros for MCF_SIU_SBCR */ +#define MCF_SIU_SBCR_PIN2DSPI (0x8000000) +#define MCF_SIU_SBCR_DMA2CPU (0x10000000) +#define MCF_SIU_SBCR_CPU2DMA (0x20000000) +#define MCF_SIU_SBCR_PIN2DMA (0x40000000) +#define MCF_SIU_SBCR_PIN2CPU (0x80000000) + +/* Bit definitions and macros for MCF_SIU_SECSACR */ +#define MCF_SIU_SECSACR_SEQEN (0x1) + +/* Bit definitions and macros for MCF_SIU_RSR */ +#define MCF_SIU_RSR_RST (0x1) +#define MCF_SIU_RSR_RSTWD (0x2) +#define MCF_SIU_RSR_RSTJTG (0x8) + +/* Bit definitions and macros for MCF_SIU_JTAGID */ +#define MCF_SIU_JTAGID_JTAGID(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SIU_JTAGID */ +#define MCF_SIU_JTAGID_REV (0xF0000000) +#define MCF_SIU_JTAGID_PROCESSOR (0x0FFFFFFF) +#define MCF_SIU_JTAGID_MCF5485 (0x0800C01D) +#define MCF_SIU_JTAGID_MCF5484 (0x0800D01D) +#define MCF_SIU_JTAGID_MCF5483 (0x0800E01D) +#define MCF_SIU_JTAGID_MCF5482 (0x0800F01D) +#define MCF_SIU_JTAGID_MCF5481 (0x0801001D) +#define MCF_SIU_JTAGID_MCF5480 (0x0801101D) +#define MCF_SIU_JTAGID_MCF5475 (0x0801201D) +#define MCF_SIU_JTAGID_MCF5474 (0x0801301D) +#define MCF_SIU_JTAGID_MCF5473 (0x0801401D) +#define MCF_SIU_JTAGID_MCF5472 (0x0801501D) +#define MCF_SIU_JTAGID_MCF5471 (0x0801601D) +#define MCF_SIU_JTAGID_MCF5470 (0x0801701D) + +#endif /* __MCF5475_SIU_H__ */ diff --git a/tos/pci_mem/include/MCF5475_SLT.h b/tos/pci_mem/include/MCF5475_SLT.h new file mode 100644 index 0000000..20e8558 --- /dev/null +++ b/tos/pci_mem/include/MCF5475_SLT.h @@ -0,0 +1,59 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SLT_H__ +#define __MCF5475_SLT_H__ + + +/********************************************************************* +* +* Slice Timers (SLT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SLT0_STCNT (*(volatile uint32_t*)(&_MBAR[0x900])) +#define MCF_SLT0_SCR (*(volatile uint32_t*)(&_MBAR[0x904])) +#define MCF_SLT0_SCNT (*(volatile uint32_t*)(&_MBAR[0x908])) +#define MCF_SLT0_SSR (*(volatile uint32_t*)(&_MBAR[0x90C])) + +#define MCF_SLT1_STCNT (*(volatile uint32_t*)(&_MBAR[0x910])) +#define MCF_SLT1_SCR (*(volatile uint32_t*)(&_MBAR[0x914])) +#define MCF_SLT1_SCNT (*(volatile uint32_t*)(&_MBAR[0x918])) +#define MCF_SLT1_SSR (*(volatile uint32_t*)(&_MBAR[0x91C])) + +#define MCF_SLT_STCNT(x) (*(volatile uint32_t*)(&_MBAR[0x900 + ((x)*0x10)])) +#define MCF_SLT_SCR(x) (*(volatile uint32_t*)(&_MBAR[0x904 + ((x)*0x10)])) +#define MCF_SLT_SCNT(x) (*(volatile int32_t*)(&_MBAR[0x908 + ((x)*0x10)])) +#define MCF_SLT_SSR(x) (*(volatile uint32_t*)(&_MBAR[0x90C + ((x)*0x10)])) + + +/* Bit definitions and macros for MCF_SLT_STCNT */ +#define MCF_SLT_STCNT_TC(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SLT_SCR */ +#define MCF_SLT_SCR_TEN (0x1000000) +#define MCF_SLT_SCR_IEN (0x2000000) +#define MCF_SLT_SCR_RUN (0x4000000) + +/* Bit definitions and macros for MCF_SLT_SCNT */ +#define MCF_SLT_SCNT_CNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SLT_SSR */ +#define MCF_SLT_SSR_ST (0x1000000) +#define MCF_SLT_SSR_BE (0x2000000) + + +#endif /* __MCF5475_SLT_H__ */ diff --git a/tos/pci_mem/include/MCF5475_SRAM.h b/tos/pci_mem/include/MCF5475_SRAM.h new file mode 100644 index 0000000..d111f13 --- /dev/null +++ b/tos/pci_mem/include/MCF5475_SRAM.h @@ -0,0 +1,62 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SRAM_H__ +#define __MCF5475_SRAM_H__ + + +/********************************************************************* +* +* System SRAM Module (SRAM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SRAM_SSCR (*(volatile uint32_t*)(&__MBAR[0x1FFC0])) +#define MCF_SRAM_TCCR (*(volatile uint32_t*)(&__MBAR[0x1FFC4])) +#define MCF_SRAM_TCCRDR (*(volatile uint32_t*)(&__MBAR[0x1FFC8])) +#define MCF_SRAM_TCCRDW (*(volatile uint32_t*)(&__MBAR[0x1FFCC])) +#define MCF_SRAM_TCCRSEC (*(volatile uint32_t*)(&__MBAR[0x1FFD0])) + + +/* Bit definitions and macros for MCF_SRAM_SSCR */ +#define MCF_SRAM_SSCR_INLV (0x10000) + +/* Bit definitions and macros for MCF_SRAM_TCCR */ +#define MCF_SRAM_TCCR_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCR_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCR_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCR_BANK3_TC(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SRAM_TCCRDR */ +#define MCF_SRAM_TCCRDR_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCRDR_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCRDR_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCRDR_BANK3_TC(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SRAM_TCCRDW */ +#define MCF_SRAM_TCCRDW_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCRDW_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCRDW_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCRDW_BANK3_TC(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SRAM_TCCRSEC */ +#define MCF_SRAM_TCCRSEC_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCRSEC_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCRSEC_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCRSEC_BANK3_TC(x) (((x)&0xF)<<0x18) + + +#endif /* __MCF5475_SRAM_H__ */ diff --git a/tos/pci_mem/include/MCF5475_USB.h b/tos/pci_mem/include/MCF5475_USB.h new file mode 100644 index 0000000..c60273c --- /dev/null +++ b/tos/pci_mem/include/MCF5475_USB.h @@ -0,0 +1,554 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_USB_H__ +#define __MCF5475_USB_H__ + + +/********************************************************************* +* +* Universal Serial Bus Interface (USB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_USB_USBAISR (*(volatile uint8_t *)(&__MBAR[0xB000])) +#define MCF_USB_USBAIMR (*(volatile uint8_t *)(&__MBAR[0xB001])) +#define MCF_USB_EPINFO (*(volatile uint8_t *)(&__MBAR[0xB003])) +#define MCF_USB_CFGR (*(volatile uint8_t *)(&__MBAR[0xB004])) +#define MCF_USB_CFGAR (*(volatile uint8_t *)(&__MBAR[0xB005])) +#define MCF_USB_SPEEDR (*(volatile uint8_t *)(&__MBAR[0xB006])) +#define MCF_USB_FRMNUMR (*(volatile uint16_t*)(&__MBAR[0xB00E])) +#define MCF_USB_EPTNR (*(volatile uint16_t*)(&__MBAR[0xB010])) +#define MCF_USB_IFUR (*(volatile uint16_t*)(&__MBAR[0xB014])) +#define MCF_USB_IFR0 (*(volatile uint16_t*)(&__MBAR[0xB040])) +#define MCF_USB_IFR1 (*(volatile uint16_t*)(&__MBAR[0xB042])) +#define MCF_USB_IFR2 (*(volatile uint16_t*)(&__MBAR[0xB044])) +#define MCF_USB_IFR3 (*(volatile uint16_t*)(&__MBAR[0xB046])) +#define MCF_USB_IFR4 (*(volatile uint16_t*)(&__MBAR[0xB048])) +#define MCF_USB_IFR5 (*(volatile uint16_t*)(&__MBAR[0xB04A])) +#define MCF_USB_IFR6 (*(volatile uint16_t*)(&__MBAR[0xB04C])) +#define MCF_USB_IFR7 (*(volatile uint16_t*)(&__MBAR[0xB04E])) +#define MCF_USB_IFR8 (*(volatile uint16_t*)(&__MBAR[0xB050])) +#define MCF_USB_IFR9 (*(volatile uint16_t*)(&__MBAR[0xB052])) +#define MCF_USB_IFR10 (*(volatile uint16_t*)(&__MBAR[0xB054])) +#define MCF_USB_IFR11 (*(volatile uint16_t*)(&__MBAR[0xB056])) +#define MCF_USB_IFR12 (*(volatile uint16_t*)(&__MBAR[0xB058])) +#define MCF_USB_IFR13 (*(volatile uint16_t*)(&__MBAR[0xB05A])) +#define MCF_USB_IFR14 (*(volatile uint16_t*)(&__MBAR[0xB05C])) +#define MCF_USB_IFR15 (*(volatile uint16_t*)(&__MBAR[0xB05E])) +#define MCF_USB_IFR16 (*(volatile uint16_t*)(&__MBAR[0xB060])) +#define MCF_USB_IFR17 (*(volatile uint16_t*)(&__MBAR[0xB062])) +#define MCF_USB_IFR18 (*(volatile uint16_t*)(&__MBAR[0xB064])) +#define MCF_USB_IFR19 (*(volatile uint16_t*)(&__MBAR[0xB066])) +#define MCF_USB_IFR20 (*(volatile uint16_t*)(&__MBAR[0xB068])) +#define MCF_USB_IFR21 (*(volatile uint16_t*)(&__MBAR[0xB06A])) +#define MCF_USB_IFR22 (*(volatile uint16_t*)(&__MBAR[0xB06C])) +#define MCF_USB_IFR23 (*(volatile uint16_t*)(&__MBAR[0xB06E])) +#define MCF_USB_IFR24 (*(volatile uint16_t*)(&__MBAR[0xB070])) +#define MCF_USB_IFR25 (*(volatile uint16_t*)(&__MBAR[0xB072])) +#define MCF_USB_IFR26 (*(volatile uint16_t*)(&__MBAR[0xB074])) +#define MCF_USB_IFR27 (*(volatile uint16_t*)(&__MBAR[0xB076])) +#define MCF_USB_IFR28 (*(volatile uint16_t*)(&__MBAR[0xB078])) +#define MCF_USB_IFR29 (*(volatile uint16_t*)(&__MBAR[0xB07A])) +#define MCF_USB_IFR30 (*(volatile uint16_t*)(&__MBAR[0xB07C])) +#define MCF_USB_IFR31 (*(volatile uint16_t*)(&__MBAR[0xB07E])) +#define MCF_USB_PPCNT (*(volatile uint16_t*)(&__MBAR[0xB080])) +#define MCF_USB_DPCNT (*(volatile uint16_t*)(&__MBAR[0xB082])) +#define MCF_USB_CRCECNT (*(volatile uint16_t*)(&__MBAR[0xB084])) +#define MCF_USB_BSECNT (*(volatile uint16_t*)(&__MBAR[0xB086])) +#define MCF_USB_PIDECNT (*(volatile uint16_t*)(&__MBAR[0xB088])) +#define MCF_USB_FRMECNT (*(volatile uint16_t*)(&__MBAR[0xB08A])) +#define MCF_USB_TXPCNT (*(volatile uint16_t*)(&__MBAR[0xB08C])) +#define MCF_USB_CNTOVR (*(volatile uint8_t *)(&__MBAR[0xB08E])) +#define MCF_USB_EP0ACR (*(volatile uint8_t *)(&__MBAR[0xB101])) +#define MCF_USB_EP0MPSR (*(volatile uint16_t*)(&__MBAR[0xB102])) +#define MCF_USB_EP0IFR (*(volatile uint8_t *)(&__MBAR[0xB104])) +#define MCF_USB_EP0SR (*(volatile uint8_t *)(&__MBAR[0xB105])) +#define MCF_USB_BMRTR (*(volatile uint8_t *)(&__MBAR[0xB106])) +#define MCF_USB_BRTR (*(volatile uint8_t *)(&__MBAR[0xB107])) +#define MCF_USB_WVALUER (*(volatile uint16_t*)(&__MBAR[0xB108])) +#define MCF_USB_WINDEXR (*(volatile uint16_t*)(&__MBAR[0xB10A])) +#define MCF_USB_WLENGTHR (*(volatile uint16_t*)(&__MBAR[0xB10C])) +#define MCF_USB_EP1OUTACR (*(volatile uint8_t *)(&__MBAR[0xB131])) +#define MCF_USB_EP1OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB132])) +#define MCF_USB_EP1OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB134])) +#define MCF_USB_EP1OUTSR (*(volatile uint8_t *)(&__MBAR[0xB135])) +#define MCF_USB_EP1OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB13E])) +#define MCF_USB_EP1INACR (*(volatile uint8_t *)(&__MBAR[0xB149])) +#define MCF_USB_EP1INMPSR (*(volatile uint16_t*)(&__MBAR[0xB14A])) +#define MCF_USB_EP1INIFR (*(volatile uint8_t *)(&__MBAR[0xB14C])) +#define MCF_USB_EP1INSR (*(volatile uint8_t *)(&__MBAR[0xB14D])) +#define MCF_USB_EP1INSFR (*(volatile uint16_t*)(&__MBAR[0xB156])) +#define MCF_USB_EP2OUTACR (*(volatile uint8_t *)(&__MBAR[0xB161])) +#define MCF_USB_EP2OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB162])) +#define MCF_USB_EP2OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB164])) +#define MCF_USB_EP2OUTSR (*(volatile uint8_t *)(&__MBAR[0xB165])) +#define MCF_USB_EP2OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB16E])) +#define MCF_USB_EP2INACR (*(volatile uint8_t *)(&__MBAR[0xB179])) +#define MCF_USB_EP2INMPSR (*(volatile uint16_t*)(&__MBAR[0xB17A])) +#define MCF_USB_EP2INIFR (*(volatile uint8_t *)(&__MBAR[0xB17C])) +#define MCF_USB_EP2INSR (*(volatile uint8_t *)(&__MBAR[0xB17D])) +#define MCF_USB_EP2INSFR (*(volatile uint16_t*)(&__MBAR[0xB186])) +#define MCF_USB_EP3OUTACR (*(volatile uint8_t *)(&__MBAR[0xB191])) +#define MCF_USB_EP3OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB192])) +#define MCF_USB_EP3OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB194])) +#define MCF_USB_EP3OUTSR (*(volatile uint8_t *)(&__MBAR[0xB195])) +#define MCF_USB_EP3OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB19E])) +#define MCF_USB_EP3INACR (*(volatile uint8_t *)(&__MBAR[0xB1A9])) +#define MCF_USB_EP3INMPSR (*(volatile uint16_t*)(&__MBAR[0xB1AA])) +#define MCF_USB_EP3INIFR (*(volatile uint8_t *)(&__MBAR[0xB1AC])) +#define MCF_USB_EP3INSR (*(volatile uint8_t *)(&__MBAR[0xB1AD])) +#define MCF_USB_EP3INSFR (*(volatile uint16_t*)(&__MBAR[0xB1B6])) +#define MCF_USB_EP4OUTACR (*(volatile uint8_t *)(&__MBAR[0xB1C1])) +#define MCF_USB_EP4OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB1C2])) +#define MCF_USB_EP4OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB1C4])) +#define MCF_USB_EP4OUTSR (*(volatile uint8_t *)(&__MBAR[0xB1C5])) +#define MCF_USB_EP4OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB1CE])) +#define MCF_USB_EP4INACR (*(volatile uint8_t *)(&__MBAR[0xB1D9])) +#define MCF_USB_EP4INMPSR (*(volatile uint16_t*)(&__MBAR[0xB1DA])) +#define MCF_USB_EP4INIFR (*(volatile uint8_t *)(&__MBAR[0xB1DC])) +#define MCF_USB_EP4INSR (*(volatile uint8_t *)(&__MBAR[0xB1DD])) +#define MCF_USB_EP4INSFR (*(volatile uint16_t*)(&__MBAR[0xB1E6])) +#define MCF_USB_EP5OUTACR (*(volatile uint8_t *)(&__MBAR[0xB1F1])) +#define MCF_USB_EP5OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB1F2])) +#define MCF_USB_EP5OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB1F4])) +#define MCF_USB_EP5OUTSR (*(volatile uint8_t *)(&__MBAR[0xB1F5])) +#define MCF_USB_EP5OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB1FE])) +#define MCF_USB_EP5INACR (*(volatile uint8_t *)(&__MBAR[0xB209])) +#define MCF_USB_EP5INMPSR (*(volatile uint16_t*)(&__MBAR[0xB20A])) +#define MCF_USB_EP5INIFR (*(volatile uint8_t *)(&__MBAR[0xB20C])) +#define MCF_USB_EP5INSR (*(volatile uint8_t *)(&__MBAR[0xB20D])) +#define MCF_USB_EP5INSFR (*(volatile uint16_t*)(&__MBAR[0xB216])) +#define MCF_USB_EP6OUTACR (*(volatile uint8_t *)(&__MBAR[0xB221])) +#define MCF_USB_EP6OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB222])) +#define MCF_USB_EP6OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB224])) +#define MCF_USB_EP6OUTSR (*(volatile uint8_t *)(&__MBAR[0xB225])) +#define MCF_USB_EP6OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB22E])) +#define MCF_USB_EP6INACR (*(volatile uint8_t *)(&__MBAR[0xB239])) +#define MCF_USB_EP6INMPSR (*(volatile uint16_t*)(&__MBAR[0xB23A])) +#define MCF_USB_EP6INIFR (*(volatile uint8_t *)(&__MBAR[0xB23C])) +#define MCF_USB_EP6INSR (*(volatile uint8_t *)(&__MBAR[0xB23D])) +#define MCF_USB_EP6INSFR (*(volatile uint16_t*)(&__MBAR[0xB246])) +#define MCF_USB_USBSR (*(volatile uint32_t*)(&__MBAR[0xB400])) +#define MCF_USB_USBCR (*(volatile uint32_t*)(&__MBAR[0xB404])) +#define MCF_USB_DRAMCR (*(volatile uint32_t*)(&__MBAR[0xB408])) +#define MCF_USB_DRAMDR (*(volatile uint32_t*)(&__MBAR[0xB40C])) +#define MCF_USB_USBISR (*(volatile uint32_t*)(&__MBAR[0xB410])) +#define MCF_USB_USBIMR (*(volatile uint32_t*)(&__MBAR[0xB414])) +#define MCF_USB_EP0STAT (*(volatile uint32_t*)(&__MBAR[0xB440])) +#define MCF_USB_EP0ISR (*(volatile uint32_t*)(&__MBAR[0xB444])) +#define MCF_USB_EP0IMR (*(volatile uint32_t*)(&__MBAR[0xB448])) +#define MCF_USB_EP0FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB44C])) +#define MCF_USB_EP0FDR (*(volatile uint32_t*)(&__MBAR[0xB450])) +#define MCF_USB_EP0FSR (*(volatile uint32_t*)(&__MBAR[0xB454])) +#define MCF_USB_EP0FCR (*(volatile uint32_t*)(&__MBAR[0xB458])) +#define MCF_USB_EP0FAR (*(volatile uint32_t*)(&__MBAR[0xB45C])) +#define MCF_USB_EP0FRP (*(volatile uint32_t*)(&__MBAR[0xB460])) +#define MCF_USB_EP0FWP (*(volatile uint32_t*)(&__MBAR[0xB464])) +#define MCF_USB_EP0LRFP (*(volatile uint32_t*)(&__MBAR[0xB468])) +#define MCF_USB_EP0LWFP (*(volatile uint32_t*)(&__MBAR[0xB46C])) +#define MCF_USB_EP1STAT (*(volatile uint32_t*)(&__MBAR[0xB470])) +#define MCF_USB_EP1ISR (*(volatile uint32_t*)(&__MBAR[0xB474])) +#define MCF_USB_EP1IMR (*(volatile uint32_t*)(&__MBAR[0xB478])) +#define MCF_USB_EP1FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB47C])) +#define MCF_USB_EP1FDR (*(volatile uint32_t*)(&__MBAR[0xB480])) +#define MCF_USB_EP1FSR (*(volatile uint32_t*)(&__MBAR[0xB484])) +#define MCF_USB_EP1FCR (*(volatile uint32_t*)(&__MBAR[0xB488])) +#define MCF_USB_EP1FAR (*(volatile uint32_t*)(&__MBAR[0xB48C])) +#define MCF_USB_EP1FRP (*(volatile uint32_t*)(&__MBAR[0xB490])) +#define MCF_USB_EP1FWP (*(volatile uint32_t*)(&__MBAR[0xB494])) +#define MCF_USB_EP1LRFP (*(volatile uint32_t*)(&__MBAR[0xB498])) +#define MCF_USB_EP1LWFP (*(volatile uint32_t*)(&__MBAR[0xB49C])) +#define MCF_USB_EP2STAT (*(volatile uint32_t*)(&__MBAR[0xB4A0])) +#define MCF_USB_EP2ISR (*(volatile uint32_t*)(&__MBAR[0xB4A4])) +#define MCF_USB_EP2IMR (*(volatile uint32_t*)(&__MBAR[0xB4A8])) +#define MCF_USB_EP2FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB4AC])) +#define MCF_USB_EP2FDR (*(volatile uint32_t*)(&__MBAR[0xB4B0])) +#define MCF_USB_EP2FSR (*(volatile uint32_t*)(&__MBAR[0xB4B4])) +#define MCF_USB_EP2FCR (*(volatile uint32_t*)(&__MBAR[0xB4B8])) +#define MCF_USB_EP2FAR (*(volatile uint32_t*)(&__MBAR[0xB4BC])) +#define MCF_USB_EP2FRP (*(volatile uint32_t*)(&__MBAR[0xB4C0])) +#define MCF_USB_EP2FWP (*(volatile uint32_t*)(&__MBAR[0xB4C4])) +#define MCF_USB_EP2LRFP (*(volatile uint32_t*)(&__MBAR[0xB4C8])) +#define MCF_USB_EP2LWFP (*(volatile uint32_t*)(&__MBAR[0xB4CC])) +#define MCF_USB_EP3STAT (*(volatile uint32_t*)(&__MBAR[0xB4D0])) +#define MCF_USB_EP3ISR (*(volatile uint32_t*)(&__MBAR[0xB4D4])) +#define MCF_USB_EP3IMR (*(volatile uint32_t*)(&__MBAR[0xB4D8])) +#define MCF_USB_EP3FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB4DC])) +#define MCF_USB_EP3FDR (*(volatile uint32_t*)(&__MBAR[0xB4E0])) +#define MCF_USB_EP3FSR (*(volatile uint32_t*)(&__MBAR[0xB4E4])) +#define MCF_USB_EP3FCR (*(volatile uint32_t*)(&__MBAR[0xB4E8])) +#define MCF_USB_EP3FAR (*(volatile uint32_t*)(&__MBAR[0xB4EC])) +#define MCF_USB_EP3FRP (*(volatile uint32_t*)(&__MBAR[0xB4F0])) +#define MCF_USB_EP3FWP (*(volatile uint32_t*)(&__MBAR[0xB4F4])) +#define MCF_USB_EP3LRFP (*(volatile uint32_t*)(&__MBAR[0xB4F8])) +#define MCF_USB_EP3LWFP (*(volatile uint32_t*)(&__MBAR[0xB4FC])) +#define MCF_USB_EP4STAT (*(volatile uint32_t*)(&__MBAR[0xB500])) +#define MCF_USB_EP4ISR (*(volatile uint32_t*)(&__MBAR[0xB504])) +#define MCF_USB_EP4IMR (*(volatile uint32_t*)(&__MBAR[0xB508])) +#define MCF_USB_EP4FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB50C])) +#define MCF_USB_EP4FDR (*(volatile uint32_t*)(&__MBAR[0xB510])) +#define MCF_USB_EP4FSR (*(volatile uint32_t*)(&__MBAR[0xB514])) +#define MCF_USB_EP4FCR (*(volatile uint32_t*)(&__MBAR[0xB518])) +#define MCF_USB_EP4FAR (*(volatile uint32_t*)(&__MBAR[0xB51C])) +#define MCF_USB_EP4FRP (*(volatile uint32_t*)(&__MBAR[0xB520])) +#define MCF_USB_EP4FWP (*(volatile uint32_t*)(&__MBAR[0xB524])) +#define MCF_USB_EP4LRFP (*(volatile uint32_t*)(&__MBAR[0xB528])) +#define MCF_USB_EP4LWFP (*(volatile uint32_t*)(&__MBAR[0xB52C])) +#define MCF_USB_EP5STAT (*(volatile uint32_t*)(&__MBAR[0xB530])) +#define MCF_USB_EP5ISR (*(volatile uint32_t*)(&__MBAR[0xB534])) +#define MCF_USB_EP5IMR (*(volatile uint32_t*)(&__MBAR[0xB538])) +#define MCF_USB_EP5FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB53C])) +#define MCF_USB_EP5FDR (*(volatile uint32_t*)(&__MBAR[0xB540])) +#define MCF_USB_EP5FSR (*(volatile uint32_t*)(&__MBAR[0xB544])) +#define MCF_USB_EP5FCR (*(volatile uint32_t*)(&__MBAR[0xB548])) +#define MCF_USB_EP5FAR (*(volatile uint32_t*)(&__MBAR[0xB54C])) +#define MCF_USB_EP5FRP (*(volatile uint32_t*)(&__MBAR[0xB550])) +#define MCF_USB_EP5FWP (*(volatile uint32_t*)(&__MBAR[0xB554])) +#define MCF_USB_EP5LRFP (*(volatile uint32_t*)(&__MBAR[0xB558])) +#define MCF_USB_EP5LWFP (*(volatile uint32_t*)(&__MBAR[0xB55C])) +#define MCF_USB_EP6STAT (*(volatile uint32_t*)(&__MBAR[0xB560])) +#define MCF_USB_EP6ISR (*(volatile uint32_t*)(&__MBAR[0xB564])) +#define MCF_USB_EP6IMR (*(volatile uint32_t*)(&__MBAR[0xB568])) +#define MCF_USB_EP6FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB56C])) +#define MCF_USB_EP6FDR (*(volatile uint32_t*)(&__MBAR[0xB570])) +#define MCF_USB_EP6FSR (*(volatile uint32_t*)(&__MBAR[0xB574])) +#define MCF_USB_EP6FCR (*(volatile uint32_t*)(&__MBAR[0xB578])) +#define MCF_USB_EP6FAR (*(volatile uint32_t*)(&__MBAR[0xB57C])) +#define MCF_USB_EP6FRP (*(volatile uint32_t*)(&__MBAR[0xB580])) +#define MCF_USB_EP6FWP (*(volatile uint32_t*)(&__MBAR[0xB584])) +#define MCF_USB_EP6LRFP (*(volatile uint32_t*)(&__MBAR[0xB588])) +#define MCF_USB_EP6LWFP (*(volatile uint32_t*)(&__MBAR[0xB58C])) +#define MCF_USB_IFR(x) (*(volatile uint16_t*)(&__MBAR[0xB040 + ((x)*0x2)])) +#define MCF_USB_EPOUTACR(x) (*(volatile uint8_t *)(&__MBAR[0xB131 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTMPSR(x) (*(volatile uint16_t*)(&__MBAR[0xB132 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTIFR(x) (*(volatile uint8_t *)(&__MBAR[0xB134 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTSR(x) (*(volatile uint8_t *)(&__MBAR[0xB135 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTSFR(x) (*(volatile uint16_t*)(&__MBAR[0xB13E + ((x-1)*0x30)])) +#define MCF_USB_EPINACR(x) (*(volatile uint8_t *)(&__MBAR[0xB149 + ((x-1)*0x30)])) +#define MCF_USB_EPINMPSR(x) (*(volatile uint16_t*)(&__MBAR[0xB14A + ((x-1)*0x30)])) +#define MCF_USB_EPINIFR(x) (*(volatile uint8_t *)(&__MBAR[0xB14C + ((x-1)*0x30)])) +#define MCF_USB_EPINSR(x) (*(volatile uint8_t *)(&__MBAR[0xB14D + ((x-1)*0x30)])) +#define MCF_USB_EPINSFR(x) (*(volatile uint16_t*)(&__MBAR[0xB156 + ((x-1)*0x30)])) +#define MCF_USB_EPSTAT(x) (*(volatile uint32_t*)(&__MBAR[0xB440 + ((x)*0x30)])) +#define MCF_USB_EPISR(x) (*(volatile uint32_t*)(&__MBAR[0xB444 + ((x)*0x30)])) +#define MCF_USB_EPIMR(x) (*(volatile uint32_t*)(&__MBAR[0xB448 + ((x)*0x30)])) +#define MCF_USB_EPFRCFGR(x) (*(volatile uint32_t*)(&__MBAR[0xB44C + ((x)*0x30)])) +#define MCF_USB_EPFDR(x) (*(volatile uint32_t*)(&__MBAR[0xB450 + ((x)*0x30)])) +#define MCF_USB_EPFSR(x) (*(volatile uint32_t*)(&__MBAR[0xB454 + ((x)*0x30)])) +#define MCF_USB_EPFCR(x) (*(volatile uint32_t*)(&__MBAR[0xB458 + ((x)*0x30)])) +#define MCF_USB_EPFAR(x) (*(volatile uint32_t*)(&__MBAR[0xB45C + ((x)*0x30)])) +#define MCF_USB_EPFRP(x) (*(volatile uint32_t*)(&__MBAR[0xB460 + ((x)*0x30)])) +#define MCF_USB_EPFWP(x) (*(volatile uint32_t*)(&__MBAR[0xB464 + ((x)*0x30)])) +#define MCF_USB_EPLRFP(x) (*(volatile uint32_t*)(&__MBAR[0xB468 + ((x)*0x30)])) +#define MCF_USB_EPLWFP(x) (*(volatile uint32_t*)(&__MBAR[0xB46C + ((x)*0x30)])) + + +/* Bit definitions and macros for MCF_USB_USBAISR */ +#define MCF_USB_USBAISR_SETUP (0x1) +#define MCF_USB_USBAISR_IN (0x2) +#define MCF_USB_USBAISR_OUT (0x4) +#define MCF_USB_USBAISR_EPHALT (0x8) +#define MCF_USB_USBAISR_TRANSERR (0x10) +#define MCF_USB_USBAISR_ACK (0x20) +#define MCF_USB_USBAISR_CTROVFL (0x40) +#define MCF_USB_USBAISR_EPSTALL (0x80) + +/* Bit definitions and macros for MCF_USB_USBAIMR */ +#define MCF_USB_USBAIMR_SETUPEN (0x1) +#define MCF_USB_USBAIMR_INEN (0x2) +#define MCF_USB_USBAIMR_OUTEN (0x4) +#define MCF_USB_USBAIMR_EPHALTEN (0x8) +#define MCF_USB_USBAIMR_TRANSERREN (0x10) +#define MCF_USB_USBAIMR_ACKEN (0x20) +#define MCF_USB_USBAIMR_CTROVFLEN (0x40) +#define MCF_USB_USBAIMR_EPSTALLEN (0x80) + +/* Bit definitions and macros for MCF_USB_EPINFO */ +#define MCF_USB_EPINFO_EPDIR (0x1) +#define MCF_USB_EPINFO_EPNUM(x) (((x)&0x7)<<0x1) + +/* Bit definitions and macros for MCF_USB_CFGR */ +#define MCF_USB_CFGR_Configuration_Value(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_CFGAR */ +#define MCF_USB_CFGAR_RESERVED (0xA0) +#define MCF_USB_CFGAR_RMTWKEUP (0xE0) + +/* Bit definitions and macros for MCF_USB_SPEEDR */ +#define MCF_USB_SPEEDR_SPEED(x) (((x)&0x3)<<0) + +/* Bit definitions and macros for MCF_USB_FRMNUMR */ +#define MCF_USB_FRMNUMR_FRMNUM(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPTNR */ +#define MCF_USB_EPTNR_EP1T(x) (((x)&0x3)<<0) +#define MCF_USB_EPTNR_EP2T(x) (((x)&0x3)<<0x2) +#define MCF_USB_EPTNR_EP3T(x) (((x)&0x3)<<0x4) +#define MCF_USB_EPTNR_EP4T(x) (((x)&0x3)<<0x6) +#define MCF_USB_EPTNR_EP5T(x) (((x)&0x3)<<0x8) +#define MCF_USB_EPTNR_EP6T(x) (((x)&0x3)<<0xA) +#define MCF_USB_EPTNR_EPnT1 (0) +#define MCF_USB_EPTNR_EPnT2 (0x1) +#define MCF_USB_EPTNR_EPnT3 (0x2) + +/* Bit definitions and macros for MCF_USB_IFUR */ +#define MCF_USB_IFUR_ALTSET(x) (((x)&0xFF)<<0) +#define MCF_USB_IFUR_IFNUM(x) (((x)&0xFF)<<0x8) + +/* Bit definitions and macros for MCF_USB_IFR */ +#define MCF_USB_IFR_ALTSET(x) (((x)&0xFF)<<0) +#define MCF_USB_IFR_IFNUM(x) (((x)&0xFF)<<0x8) + +/* Bit definitions and macros for MCF_USB_PPCNT */ +#define MCF_USB_PPCNT_PPCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_DPCNT */ +#define MCF_USB_DPCNT_DPCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_CRCECNT */ +#define MCF_USB_CRCECNT_CRCECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_BSECNT */ +#define MCF_USB_BSECNT_BSECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_PIDECNT */ +#define MCF_USB_PIDECNT_PIDECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_FRMECNT */ +#define MCF_USB_FRMECNT_FRMECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_TXPCNT */ +#define MCF_USB_TXPCNT_TXPCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_CNTOVR */ +#define MCF_USB_CNTOVR_PPCNT (0x1) +#define MCF_USB_CNTOVR_DPCNT (0x2) +#define MCF_USB_CNTOVR_CRCECNT (0x4) +#define MCF_USB_CNTOVR_BSECNT (0x8) +#define MCF_USB_CNTOVR_PIDECNT (0x10) +#define MCF_USB_CNTOVR_FRMECNT (0x20) +#define MCF_USB_CNTOVR_TXPCNT (0x40) + +/* Bit definitions and macros for MCF_USB_EP0ACR */ +#define MCF_USB_EP0ACR_TTYPE(x) (((x)&0x3)<<0) +#define MCF_USB_EP0ACR_TTYPE_CTRL (0) +#define MCF_USB_EP0ACR_TTYPE_ISOC (0x1) +#define MCF_USB_EP0ACR_TTYPE_BULK (0x2) +#define MCF_USB_EP0ACR_TTYPE_INT (0x3) + +/* Bit definitions and macros for MCF_USB_EP0MPSR */ +#define MCF_USB_EP0MPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0) +#define MCF_USB_EP0MPSR_ADDTRANS(x) (((x)&0x3)<<0xB) + +/* Bit definitions and macros for MCF_USB_EP0IFR */ +#define MCF_USB_EP0IFR_IFNUM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_EP0SR */ +#define MCF_USB_EP0SR_HALT (0x1) +#define MCF_USB_EP0SR_ACTIVE (0x2) +#define MCF_USB_EP0SR_PSTALL (0x4) +#define MCF_USB_EP0SR_CCOMP (0x8) +#define MCF_USB_EP0SR_TXZERO (0x20) +#define MCF_USB_EP0SR_INT (0x80) + +/* Bit definitions and macros for MCF_USB_BMRTR */ +#define MCF_USB_BMRTR_REC(x) (((x)&0x1F)<<0) +#define MCF_USB_BMRTR_REC_DEVICE (0) +#define MCF_USB_BMRTR_REC_INTERFACE (0x1) +#define MCF_USB_BMRTR_REC_ENDPOINT (0x2) +#define MCF_USB_BMRTR_REC_OTHER (0x3) +#define MCF_USB_BMRTR_TYPE(x) (((x)&0x3)<<0x5) +#define MCF_USB_BMRTR_TYPE_STANDARD (0) +#define MCF_USB_BMRTR_TYPE_CLASS (0x20) +#define MCF_USB_BMRTR_TYPE_VENDOR (0x40) +#define MCF_USB_BMRTR_DIR (0x80) + +/* Bit definitions and macros for MCF_USB_BRTR */ +#define MCF_USB_BRTR_BREQ(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_WVALUER */ +#define MCF_USB_WVALUER_WVALUE(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_WINDEXR */ +#define MCF_USB_WINDEXR_WINDEX(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_WLENGTHR */ +#define MCF_USB_WLENGTHR_WLENGTH(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPOUTACR */ +#define MCF_USB_EPOUTACR_TTYPE(x) (((x)&0x3)<<0) +#define MCF_USB_EPOUTACR_TTYPE_ISOC (0x1) +#define MCF_USB_EPOUTACR_TTYPE_BULK (0x2) +#define MCF_USB_EPOUTACR_TTYPE_INT (0x3) + +/* Bit definitions and macros for MCF_USB_EPOUTMPSR */ +#define MCF_USB_EPOUTMPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0) +#define MCF_USB_EPOUTMPSR_ADDTRANS(x) (((x)&0x3)<<0xB) + +/* Bit definitions and macros for MCF_USB_EPOUTIFR */ +#define MCF_USB_EPOUTIFR_IFNUM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPOUTSR */ +#define MCF_USB_EPOUTSR_HALT (0x1) +#define MCF_USB_EPOUTSR_ACTIVE (0x2) +#define MCF_USB_EPOUTSR_PSTALL (0x4) +#define MCF_USB_EPOUTSR_CCOMP (0x8) +#define MCF_USB_EPOUTSR_TXZERO (0x20) +#define MCF_USB_EPOUTSR_INT (0x80) + +/* Bit definitions and macros for MCF_USB_EPOUTSFR */ +#define MCF_USB_EPOUTSFR_FRMNUM(x) (((x)&0x7FF)<<0) + +/* Bit definitions and macros for MCF_USB_EPINACR */ +#define MCF_USB_EPINACR_TTYPE(x) (((x)&0x3)<<0) +#define MCF_USB_EPINACR_TTYPE_ISOC (0x1) +#define MCF_USB_EPINACR_TTYPE_BULK (0x2) +#define MCF_USB_EPINACR_TTYPE_INT (0x3) + +/* Bit definitions and macros for MCF_USB_EPINMPSR */ +#define MCF_USB_EPINMPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0) +#define MCF_USB_EPINMPSR_ADDTRANS(x) (((x)&0x3)<<0xB) + +/* Bit definitions and macros for MCF_USB_EPINIFR */ +#define MCF_USB_EPINIFR_IFNUM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPINSR */ +#define MCF_USB_EPINSR_HALT (0x1) +#define MCF_USB_EPINSR_ACTIVE (0x2) +#define MCF_USB_EPINSR_PSTALL (0x4) +#define MCF_USB_EPINSR_CCOMP (0x8) +#define MCF_USB_EPINSR_TXZERO (0x20) +#define MCF_USB_EPINSR_INT (0x80) + +/* Bit definitions and macros for MCF_USB_EPINSFR */ +#define MCF_USB_EPINSFR_FRMNUM(x) (((x)&0x7FF)<<0) + +/* Bit definitions and macros for MCF_USB_USBSR */ +#define MCF_USB_USBSR_ISOERREP(x) (((x)&0xF)<<0) +#define MCF_USB_USBSR_SUSP (0x80) + +/* Bit definitions and macros for MCF_USB_USBCR */ +#define MCF_USB_USBCR_RESUME (0x1) +#define MCF_USB_USBCR_APPLOCK (0x2) +#define MCF_USB_USBCR_RST (0x4) +#define MCF_USB_USBCR_RAMEN (0x8) +#define MCF_USB_USBCR_RAMSPLIT (0x20) + +/* Bit definitions and macros for MCF_USB_DRAMCR */ +#define MCF_USB_DRAMCR_DADR(x) (((x)&0x3FF)<<0) +#define MCF_USB_DRAMCR_DSIZE(x) (((x)&0x7FF)<<0x10) +#define MCF_USB_DRAMCR_BSY (0x40000000) +#define MCF_USB_DRAMCR_START (0x80000000) + +/* Bit definitions and macros for MCF_USB_DRAMDR */ +#define MCF_USB_DRAMDR_DDAT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_USBISR */ +#define MCF_USB_USBISR_ISOERR (0x1) +#define MCF_USB_USBISR_FTUNLCK (0x2) +#define MCF_USB_USBISR_SUSP (0x4) +#define MCF_USB_USBISR_RES (0x8) +#define MCF_USB_USBISR_UPDSOF (0x10) +#define MCF_USB_USBISR_RSTSTOP (0x20) +#define MCF_USB_USBISR_SOF (0x40) +#define MCF_USB_USBISR_MSOF (0x80) + +/* Bit definitions and macros for MCF_USB_USBIMR */ +#define MCF_USB_USBIMR_ISOERR (0x1) +#define MCF_USB_USBIMR_FTUNLCK (0x2) +#define MCF_USB_USBIMR_SUSP (0x4) +#define MCF_USB_USBIMR_RES (0x8) +#define MCF_USB_USBIMR_UPDSOF (0x10) +#define MCF_USB_USBIMR_RSTSTOP (0x20) +#define MCF_USB_USBIMR_SOF (0x40) +#define MCF_USB_USBIMR_MSOF (0x80) + +/* Bit definitions and macros for MCF_USB_EPSTAT */ +#define MCF_USB_EPSTAT_RST (0x1) +#define MCF_USB_EPSTAT_FLUSH (0x2) +#define MCF_USB_EPSTAT_DIR (0x80) +#define MCF_USB_EPSTAT_BYTECNT(x) (((x)&0xFFF)<<0x10) + +/* Bit definitions and macros for MCF_USB_EPISR */ +#define MCF_USB_EPISR_EOF (0x1) +#define MCF_USB_EPISR_EOT (0x4) +#define MCF_USB_EPISR_FIFOLO (0x10) +#define MCF_USB_EPISR_FIFOHI (0x20) +#define MCF_USB_EPISR_ERR (0x40) +#define MCF_USB_EPISR_EMT (0x80) +#define MCF_USB_EPISR_FU (0x100) + +/* Bit definitions and macros for MCF_USB_EPIMR */ +#define MCF_USB_EPIMR_EOF (0x1) +#define MCF_USB_EPIMR_EOT (0x4) +#define MCF_USB_EPIMR_FIFOLO (0x10) +#define MCF_USB_EPIMR_FIFOHI (0x20) +#define MCF_USB_EPIMR_ERR (0x40) +#define MCF_USB_EPIMR_EMT (0x80) +#define MCF_USB_EPIMR_FU (0x100) + +/* Bit definitions and macros for MCF_USB_EPFRCFGR */ +#define MCF_USB_EPFRCFGR_DEPTH(x) (((x)&0x1FFF)<<0) +#define MCF_USB_EPFRCFGR_BASE(x) (((x)&0xFFF)<<0x10) + +/* Bit definitions and macros for MCF_USB_EPFDR */ +#define MCF_USB_EPFDR_RX_TXDATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPFSR */ +#define MCF_USB_EPFSR_EMT (0x10000) +#define MCF_USB_EPFSR_ALRM (0x20000) +#define MCF_USB_EPFSR_FU (0x40000) +#define MCF_USB_EPFSR_FR (0x80000) +#define MCF_USB_EPFSR_OF (0x100000) +#define MCF_USB_EPFSR_UF (0x200000) +#define MCF_USB_EPFSR_RXW (0x400000) +#define MCF_USB_EPFSR_FAE (0x800000) +#define MCF_USB_EPFSR_FRM(x) (((x)&0xF)<<0x18) +#define MCF_USB_EPFSR_TXW (0x40000000) +#define MCF_USB_EPFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_USB_EPFCR */ +#define MCF_USB_EPFCR_COUNTER(x) (((x)&0xFFFF)<<0) +#define MCF_USB_EPFCR_TXWMSK (0x40000) +#define MCF_USB_EPFCR_OFMSK (0x80000) +#define MCF_USB_EPFCR_UFMSK (0x100000) +#define MCF_USB_EPFCR_RXWMSK (0x200000) +#define MCF_USB_EPFCR_FAEMSK (0x400000) +#define MCF_USB_EPFCR_IPMSK (0x800000) +#define MCF_USB_EPFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_USB_EPFCR_FRM (0x8000000) +#define MCF_USB_EPFCR_TMR (0x10000000) +#define MCF_USB_EPFCR_WFR (0x20000000) +#define MCF_USB_EPFCR_SHAD (0x80000000) + +/* Bit definitions and macros for MCF_USB_EPFAR */ +#define MCF_USB_EPFAR_ALRMP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPFRP */ +#define MCF_USB_EPFRP_RP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPFWP */ +#define MCF_USB_EPFWP_WP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPLRFP */ +#define MCF_USB_EPLRFP_LRFP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPLWFP */ +#define MCF_USB_EPLWFP_LWFP(x) (((x)&0xFFF)<<0) + + +#endif /* __MCF5475_USB_H__ */ diff --git a/tos/pci_mem/include/MCF5475_XLB.h b/tos/pci_mem/include/MCF5475_XLB.h new file mode 100644 index 0000000..af25ae7 --- /dev/null +++ b/tos/pci_mem/include/MCF5475_XLB.h @@ -0,0 +1,101 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_XLB_H__ +#define __MCF5475_XLB_H__ + + +/********************************************************************* +* +* XL Bus Arbiter (XLB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_XLB_XARB_CFG (*(volatile uint32_t*)(&_MBAR[0x240])) +#define MCF_XLB_XARB_VER (*(volatile uint32_t*)(&_MBAR[0x244])) +#define MCF_XLB_XARB_SR (*(volatile uint32_t*)(&_MBAR[0x248])) +#define MCF_XLB_XARB_IMR (*(volatile uint32_t*)(&_MBAR[0x24C])) +#define MCF_XLB_XARB_ADRCAP (*(volatile uint32_t*)(&_MBAR[0x250])) +#define MCF_XLB_XARB_SIGCAP (*(volatile uint32_t*)(&_MBAR[0x254])) +#define MCF_XLB_XARB_ADRTO (*(volatile uint32_t*)(&_MBAR[0x258])) +#define MCF_XLB_XARB_DATTO (*(volatile uint32_t*)(&_MBAR[0x25C])) +#define MCF_XLB_XARB_BUSTO (*(volatile uint32_t*)(&_MBAR[0x260])) +#define MCF_XLB_XARB_PRIEN (*(volatile uint32_t*)(&_MBAR[0x264])) +#define MCF_XLB_XARB_PRI (*(volatile uint32_t*)(&_MBAR[0x268])) + + +/* Bit definitions and macros for MCF_XLB_XARB_CFG */ +#define MCF_XLB_XARB_CFG_AT (0x2) +#define MCF_XLB_XARB_CFG_DT (0x4) +#define MCF_XLB_XARB_CFG_BA (0x8) +#define MCF_XLB_XARB_CFG_PM(x) (((x)&0x3)<<0x5) +#define MCF_XLB_XARB_CFG_SP(x) (((x)&0x7)<<0x8) +#define MCF_XLB_XARB_CFG_PLDIS (0x80000000) + +/* Bit definitions and macros for MCF_XLB_XARB_VER */ +#define MCF_XLB_XARB_VER_VER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_SR */ +#define MCF_XLB_XARB_SR_AT (0x1) +#define MCF_XLB_XARB_SR_DT (0x2) +#define MCF_XLB_XARB_SR_BA (0x4) +#define MCF_XLB_XARB_SR_TTM (0x8) +#define MCF_XLB_XARB_SR_ECW (0x10) +#define MCF_XLB_XARB_SR_TTR (0x20) +#define MCF_XLB_XARB_SR_TTA (0x40) +#define MCF_XLB_XARB_SR_MM (0x80) +#define MCF_XLB_XARB_SR_SEA (0x100) + +/* Bit definitions and macros for MCF_XLB_XARB_IMR */ +#define MCF_XLB_XARB_IMR_ATE (0x1) +#define MCF_XLB_XARB_IMR_DTE (0x2) +#define MCF_XLB_XARB_IMR_BAE (0x4) +#define MCF_XLB_XARB_IMR_TTME (0x8) +#define MCF_XLB_XARB_IMR_ECWE (0x10) +#define MCF_XLB_XARB_IMR_TTRE (0x20) +#define MCF_XLB_XARB_IMR_TTAE (0x40) +#define MCF_XLB_XARB_IMR_MME (0x80) +#define MCF_XLB_XARB_IMR_SEAE (0x100) + +/* Bit definitions and macros for MCF_XLB_XARB_ADRCAP */ +#define MCF_XLB_XARB_ADRCAP_ADRCAP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_SIGCAP */ +#define MCF_XLB_XARB_SIGCAP_TT(x) (((x)&0x1F)<<0) +#define MCF_XLB_XARB_SIGCAP_TBST (0x20) +#define MCF_XLB_XARB_SIGCAP_TSIZ(x) (((x)&0x7)<<0x7) + +/* Bit definitions and macros for MCF_XLB_XARB_ADRTO */ +#define MCF_XLB_XARB_ADRTO_ADRTO(x) (((x)&0xFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_DATTO */ +#define MCF_XLB_XARB_DATTO_DATTO(x) (((x)&0xFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_BUSTO */ +#define MCF_XLB_XARB_BUSTO_BUSTO(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_PRIEN */ +#define MCF_XLB_XARB_PRIEN_M0 (0x1) +#define MCF_XLB_XARB_PRIEN_M2 (0x4) +#define MCF_XLB_XARB_PRIEN_M3 (0x8) + +/* Bit definitions and macros for MCF_XLB_XARB_PRI */ +#define MCF_XLB_XARB_PRI_M0P(x) (((x)&0x7)<<0) +#define MCF_XLB_XARB_PRI_M2P(x) (((x)&0x7)<<0x8) +#define MCF_XLB_XARB_PRI_M3P(x) (((x)&0x7)<<0xC) + + +#endif /* __MCF5475_XLB_H__ */ diff --git a/tos/pci_mem/include/bas_string.h b/tos/pci_mem/include/bas_string.h new file mode 100644 index 0000000..c743c95 --- /dev/null +++ b/tos/pci_mem/include/bas_string.h @@ -0,0 +1,47 @@ +/* + * bas_string.h + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 26.02.2013 + * Author: Markus Fröschle + */ + +#ifndef BAS_STRING_H_ +#define BAS_STRING_H_ + +#include + +extern int strncmp(const char *s1, const char *s2, size_t max); +extern char *strcpy(char *dst, const char *src); +char *strncpy(char *dst, const char *src, size_t max); +extern int strcmp(const char *s1, const char *s2); +extern size_t strlen(const char *str); +extern char *strcat(char *dst, const char *src); +extern char *strncat(char *dst, const char *src, size_t max); +extern int atoi(const char *c); +extern void *memcpy(void *dst, const void *src, size_t n); +extern void *memset(void *s, int c, size_t n); +extern int memcmp(const void *s1, const void *s2, size_t max); +extern void bzero(void *s, size_t n); + +#define isdigit(c) (((c) >= '0') && ((c) <= '9')) +#define isupper(c) ((c) >= 'A' && ((c) <= 'Z')) +#define islower(c) ((c) >= 'a' && ((c) <= 'z')) +#define isalpha(c) (isupper((c)) || islower(c)) +#define tolower(c) (isupper(c) ? ((c) + 'a' - 'A') : (c)) + +#endif /* BAS_STRING_H_ */ diff --git a/tos/pci_mem/include/bas_types.h b/tos/pci_mem/include/bas_types.h new file mode 100644 index 0000000..4f692a1 --- /dev/null +++ b/tos/pci_mem/include/bas_types.h @@ -0,0 +1,35 @@ +/* + * bas_types.h + * + * Created on: 17.11.2012 + * Author: mfro + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Copyright 2010 - 2012 F. Aschwanden + * Copyright 2011 - 2012 V. Riviere + * Copyright 2012 M. Froeschle + * + */ + +#ifndef BAS_TYPES_H_ +#define BAS_TYPES_H_ + +#include +#include +#include /* for sizeof() etc. */ + +#endif /* BAS_TYPES_H_ */ diff --git a/tos/pci_mem/include/driver_vec.h b/tos/pci_mem/include/driver_vec.h new file mode 100644 index 0000000..06220ef --- /dev/null +++ b/tos/pci_mem/include/driver_vec.h @@ -0,0 +1,319 @@ +/* + * driver_vec.h + * + * Interface for exposure of BaS drivers to the OS + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 24.10.2013 + * Author: Markus Fröschle + */ + +#ifndef _DRIVER_VEC_H_ +#define _DRIVER_VEC_H_ + +#include "pci.h" + +enum driver_type +{ + BLOCKDEV_DRIVER, + CHARDEV_DRIVER, + XHDI_DRIVER, + MCD_DRIVER, + VIDEO_DRIVER, + PCI_DRIVER, + MMU_DRIVER, + PCI_NATIVE_DRIVER, + END_OF_DRIVERS = 0xffffffffL, /* marks end of driver list */ +}; + +struct generic_driver_interface +{ + uint32_t (*init)(void); + uint32_t (*read)(void *buf, size_t count); + uint32_t (*write)(const void *buf, size_t count); + uint32_t (*ioctl)(uint32_t request, ...); +}; + +struct dma_driver_interface +{ + int32_t version; + int32_t magic; + int (*dma_set_initiator)(int initiator); + uint32_t (*dma_get_initiator)(int requestor); + void (*dma_free_initiator)(int requestor); + int (*dma_set_channel)(int requestor, void (*handler)(void)); + int (*dma_get_channel)(int requestor); + void (*dma_free_channel)(int requestor); + void (*dma_clear_channel)(int channel); + int (*MCD_startDma)(long channel, + int8_t *srcAddr, unsigned int srcIncr, int8_t *destAddr, unsigned int destIncr, + unsigned int dmaSize, unsigned int xferSize, unsigned int initiator, int priority, + unsigned int flags, unsigned int funcDesc); + int32_t (*MCD_dmaStatus)(int32_t channel); + int32_t (*MCD_XferProgrQuery)(int32_t channel, /* MCD_XferProg */ void *progRep); + int32_t (*MCD_killDma)(int32_t channel); + int32_t (*MCD_continDma)(int32_t channel); + int32_t (*MCD_pauseDma)(int32_t channel); + int32_t (*MCD_resumeDma)(int32_t channel); + int32_t (*MCD_csumQuery)(int32_t channel, uint32_t *csum); + void *(*dma_malloc)(uint32_t amount); + int32_t (*dma_free)(void *addr); +}; + +struct xhdi_driver_interface +{ + uint32_t (*xhdivec)(); +}; + +/* + * Interpretation of offset for color fields: All offsets are from the right, + * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you + * can use the offset as right argument to <<). A pixel afterwards is a bit + * stream and is written to video memory as that unmodified. This implies + * big-endian byte order if bits_per_pixel is greater than 8. + */ +struct fb_bitfield +{ + unsigned long offset; /* beginning of bitfield */ + unsigned long length; /* length of bitfield */ + unsigned long msb_right; /* != 0 : Most significant bit is */ + /* right */ +}; + +/* + * the following structures define the interface to the BaS-builtin-framebuffer video driver + */ +struct fb_var_screeninfo +{ + unsigned long xres; /* visible resolution */ + unsigned long yres; + unsigned long xres_virtual; /* virtual resolution */ + unsigned long yres_virtual; + unsigned long xoffset; /* offset from virtual to visible */ + unsigned long yoffset; /* resolution */ + + unsigned long bits_per_pixel; /* guess what */ + unsigned long grayscale; /* != 0 Graylevels instead of colors */ + + struct fb_bitfield red; /* bitfield in fb mem if true color, */ + struct fb_bitfield green; /* else only length is significant */ + struct fb_bitfield blue; + struct fb_bitfield transp; /* transparency */ + + unsigned long nonstd; /* != 0 Non standard pixel format */ + + unsigned long activate; /* see FB_ACTIVATE_* */ + + unsigned long height; /* height of picture in mm */ + unsigned long width; /* width of picture in mm */ + + unsigned long accel_flags; /* (OBSOLETE) see fb_info.flags */ + + /* Timing: All values in pixclocks, except pixclock (of course) */ + unsigned long pixclock; /* pixel clock in ps (pico seconds) */ + unsigned long left_margin; /* time from sync to picture */ + unsigned long right_margin; /* time from picture to sync */ + unsigned long upper_margin; /* time from sync to picture */ + unsigned long lower_margin; + unsigned long hsync_len; /* length of horizontal sync */ + unsigned long vsync_len; /* length of vertical sync */ + unsigned long sync; /* see FB_SYNC_* */ + unsigned long vmode; /* see FB_VMODE_* */ + unsigned long rotate; /* angle we rotate counter clockwise */ + unsigned long refresh; + unsigned long reserved[4]; /* Reserved for future compatibility */ +}; + +struct fb_fix_screeninfo +{ + char id[16]; /* identification string eg "TT Builtin" */ + unsigned long smem_start; /* Start of frame buffer mem */ + /* (physical address) */ + unsigned long smem_len; /* Length of frame buffer mem */ + unsigned long type; /* see FB_TYPE_* */ + unsigned long type_aux; /* Interleave for interleaved Planes */ + unsigned long visual; /* see FB_VISUAL_* */ + unsigned short xpanstep; /* zero if no hardware panning */ + unsigned short ypanstep; /* zero if no hardware panning */ + unsigned short ywrapstep; /* zero if no hardware ywrap */ + unsigned long line_length; /* length of a line in bytes */ + unsigned long mmio_start; /* Start of Memory Mapped I/O */ + /* (physical address) */ + unsigned long mmio_len; /* Length of Memory Mapped I/O */ + unsigned long accel; /* Indicate to driver which */ + /* specific chip/card we have */ + unsigned short reserved[3]; /* Reserved for future compatibility */ +}; + +struct fb_chroma +{ + unsigned long redx; /* in fraction of 1024 */ + unsigned long greenx; + unsigned long bluex; + unsigned long whitex; + unsigned long redy; + unsigned long greeny; + unsigned long bluey; + unsigned long whitey; +}; + +struct fb_monspecs +{ + struct fb_chroma chroma; + struct fb_videomode *modedb; /* mode database */ + unsigned char manufacturer[4]; /* Manufacturer */ + unsigned char monitor[14]; /* Monitor String */ + unsigned char serial_no[14]; /* Serial Number */ + unsigned char ascii[14]; /* ? */ + unsigned long modedb_len; /* mode database length */ + unsigned long model; /* Monitor Model */ + unsigned long serial; /* Serial Number - Integer */ + unsigned long year; /* Year manufactured */ + unsigned long week; /* Week Manufactured */ + unsigned long hfmin; /* hfreq lower limit (Hz) */ + unsigned long hfmax; /* hfreq upper limit (Hz) */ + unsigned long dclkmin; /* pixelclock lower limit (Hz) */ + unsigned long dclkmax; /* pixelclock upper limit (Hz) */ + unsigned short input; /* display type - see FB_DISP_* */ + unsigned short dpms; /* DPMS support - see FB_DPMS_ */ + unsigned short signal; /* Signal Type - see FB_SIGNAL_* */ + unsigned short vfmin; /* vfreq lower limit (Hz) */ + unsigned short vfmax; /* vfreq upper limit (Hz) */ + unsigned short gamma; /* Gamma - in fractions of 100 */ + unsigned short gtf : 1; /* supports GTF */ + unsigned short misc; /* Misc flags - see FB_MISC_* */ + unsigned char version; /* EDID version... */ + unsigned char revision; /* ...and revision */ + unsigned char max_x; /* Maximum horizontal size (cm) */ + unsigned char max_y; /* Maximum vertical size (cm) */ +}; + +struct framebuffer_driver_interface +{ + struct fb_info **framebuffer_info; /* pointer to an fb_info struct (defined in include/fb.h) */ +}; + + +struct pci_bios_interface +{ + uint32_t subjar; + uint32_t version; + /* Although we declare this functions as standard gcc functions (cdecl), + * they expect parameters inside registers (fastcall) unsupported by gcc m68k. + * Caller will take care of parameters passing convention. + */ + int32_t (*find_pci_device)(uint32_t id, uint16_t index); + int32_t (*find_pci_classcode)(uint32_t class, uint16_t index); + int32_t (*read_config_byte)(int32_t handle, uint16_t reg, uint8_t *address); + int32_t (*read_config_word)(int32_t handle, uint16_t reg, uint16_t *address); + int32_t (*read_config_longword)(int32_t handle, uint16_t reg, uint32_t *address); + uint8_t (*fast_read_config_byte)(int32_t handle, uint16_t reg); + uint16_t (*fast_read_config_word)(int32_t handle, uint16_t reg); + uint32_t (*fast_read_config_longword)(int32_t handle, uint16_t reg); + int32_t (*write_config_byte)(int32_t handle, uint16_t reg, uint16_t val); + int32_t (*write_config_word)(int32_t handle, uint16_t reg, uint16_t val); + int32_t (*write_config_longword)(int32_t handle, uint16_t reg, uint32_t val); + int32_t (*hook_interrupt)(int32_t handle, uint32_t *routine, uint32_t *parameter); + int32_t (*unhook_interrupt)(int32_t handle); + int32_t (*special_cycle)(uint16_t bus, uint32_t data); + int32_t (*get_routing)(int32_t handle); + int32_t (*set_interrupt)(int32_t handle); + int32_t (*get_resource)(int32_t handle); + int32_t (*get_card_used)(int32_t handle, uint32_t *address); + int32_t (*set_card_used)(int32_t handle, uint32_t *callback); + int32_t (*read_mem_byte)(int32_t handle, uint32_t offset, uint8_t *address); + int32_t (*read_mem_word)(int32_t handle, uint32_t offset, uint16_t *address); + int32_t (*read_mem_longword)(int32_t handle, uint32_t offset, uint32_t *address); + uint8_t (*fast_read_mem_byte)(int32_t handle, uint32_t offset); + uint16_t (*fast_read_mem_word)(int32_t handle, uint32_t offset); + uint32_t (*fast_read_mem_longword)(int32_t handle, uint32_t offset); + int32_t (*write_mem_byte)(int32_t handle, uint32_t offset, uint16_t val); + int32_t (*write_mem_word)(int32_t handle, uint32_t offset, uint16_t val); + int32_t (*write_mem_longword)(int32_t handle, uint32_t offset, uint32_t val); + int32_t (*read_io_byte)(int32_t handle, uint32_t offset, uint8_t *address); + int32_t (*read_io_word)(int32_t handle, uint32_t offset, uint16_t *address); + int32_t (*read_io_longword)(int32_t handle, uint32_t offset, uint32_t *address); + uint8_t (*fast_read_io_byte)(int32_t handle, uint32_t offset); + uint16_t (*fast_read_io_word)(int32_t handle, uint32_t offset); + uint32_t (*fast_read_io_longword)(int32_t handle, uint32_t offset); + int32_t (*write_io_byte)(int32_t handle, uint32_t offset, uint16_t val); + int32_t (*write_io_word)(int32_t handle, uint32_t offset, uint16_t val); + int32_t (*write_io_longword)(int32_t handle, uint32_t offset, uint32_t val); + int32_t (*get_machine_id)(void); + int32_t (*get_pagesize)(void); + int32_t (*virt_to_bus)(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer); + int32_t (*bus_to_virt)(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer); + int32_t (*virt_to_phys)(uint32_t address, PCI_CONV_ADR *pointer); + int32_t (*phys_to_virt)(uint32_t address, PCI_CONV_ADR *pointer); + // int32_t reserved[2]; +}; + +struct mmu_driver_interface +{ + int32_t (*map_page_locked)(uint32_t address, uint32_t length, int asid); + int32_t (*unlock_page)(uint32_t address, uint32_t length, int asid); + int32_t (*report_locked_pages)(uint32_t *num_itlb, uint32_t *num_dtlb); + uint32_t (*report_pagesize)(void); +}; + +struct pci_native_driver_interface +{ + uint32_t (*pci_read_config_longword)(int32_t handle, int offset); + uint16_t (*pci_read_config_word)(int32_t handle, int offset); + uint8_t (*pci_read_config_byte)(int32_t handle, int offset); + + int32_t (*pci_write_config_longword)(int32_t handle, int offset, uint32_t value); + int32_t (*pci_write_config_word)(int32_t handle, int offset, uint16_t value); + int32_t (*pci_write_config_byte)(int32_t handle, int offset, uint8_t value); + int32_t (*pci_hook_interrupt)(int32_t handle, void *handler, void *parameter); + int32_t (*pci_unhook_interrupt)(int32_t handle); + int32_t (*pci_find_device)(uint16_t device_id, uint16_t vendor_id, int index); + int32_t (*pci_find_classcode)(uint32_t classcode, int index); + struct pci_rd * (*pci_get_resource)(int32_t handle); +}; + +union interface +{ + struct generic_driver_interface *gdi; + struct xhdi_driver_interface *xhdi; + struct dma_driver_interface *dma; + struct framebuffer_driver_interface *fb; + struct pci_bios_interface *pci; + struct mmu_driver_interface *mmu; + struct pci_native_driver_interface *pci_native; +}; + +struct generic_interface +{ + enum driver_type type; + char name[16]; + char description[64]; + int version; + int revision; + union interface interface; +}; + +struct driver_table +{ + uint32_t bas_version; + uint32_t bas_revision; + void (*remove_handler)(void); /* calling this will disable the BaS' hook into trap #0 */ + struct generic_interface *interfaces; +}; + + +#endif /* _DRIVER_VEC_H_ */ diff --git a/tos/pci_mem/include/pci.h b/tos/pci_mem/include/pci.h new file mode 100644 index 0000000..b912dd6 --- /dev/null +++ b/tos/pci_mem/include/pci.h @@ -0,0 +1,360 @@ +#ifndef _PCI_H_ +#define _PCI_H_ + +/* + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 26.02.2013 + * Author: Markus Fröschle + */ + +#include +#include "util.h" /* for swpX() */ + +#define PCI_MEMORY_OFFSET 0x80000000 +#define PCI_MEMORY_SIZE 0x40000000 /* 1 GByte PCI memory window */ +#define PCI_IO_OFFSET 0xD0000000 +#define PCI_IO_SIZE 0x10000000 /* 256 MByte PCI I/O window */ + +#define PCI_LANESWAP_B(x) (x ^ 3) +#define PCI_LANESWAP_W(x) (x ^ 2) +#define PCI_LANESWAP_L(x) (x) /* for completeness only */ +/* + * Note: the byte offsets are in little endian format, so for pci_xxx_config_byte() + * accesses to hit the right offset, you'll need to wrap them into PCI_LANESWAP_B() + * and for pci_xxx_config_word() into PCI_LANESWAP_W() + */ +#define PCIIDR 0x00 /* PCI Configuration ID Register */ +#define PCICSR 0x04 /* PCI Command/Status Register */ +#define PCICR 0x06 /* PCI Command Register */ +#define PCISR 0x04 /* PCI Status Register */ +#define PCIREV 0x0B /* PCI Revision ID Register */ +#define PCICCR 0x08 /* PCI Class Code Register */ +#define PCICLSR 0x0F /* PCI Cache Line Size Register */ +#define PCILTR 0x0E /* PCI Latency Timer Register */ +#define PCIHTR 0x0D /* PCI Header Type Register */ +#define PCIBISTR 0x0C /* PCI Build-In Self Test Register */ + +#define PCIBAR0 0x10 /* PCI Base Address Register for Memory + Accesses to Local, Runtime, and DMA */ +#define PCIBAR1 0x14 /* PCI Base Address Register for I/O + Accesses to Local, Runtime, and DMA */ +#define PCIBAR2 0x18 /* PCI Base Address Register for Memory + Accesses to Local Address Space 0 */ +#define PCIBAR3 0x1C /* PCI Base Address Register for Memory + Accesses to Local Address Space 1 */ +#define PCIBAR4 0x20 /* PCI Base Address Register, reserved */ +#define PCIBAR5 0x24 /* PCI Base Address Register, reserved */ +#define PCICIS 0x28 /* PCI Cardbus CIS Pointer, not support*/ +#define PCISVID 0x2E /* PCI Subsystem Vendor ID */ +#define PCISID 0x2D /* PCI Subsystem ID */ +#define PCIERBAR 0x30 /* PCI Expansion ROM Base Register */ +#define CAP_PTR 0x34 /* New Capability Pointer */ +#define PCIILR 0x3F /* PCI Interrupt Line Register */ +#define PCIIPR 0x3E /* PCI Interrupt Pin Register */ +#define PCIMGR 0x3D /* PCI Min_Gnt Register */ +#define PCIMLR 0x3C /* PCI Max_Lat Register */ +#define PMCAPID 0x40 /* Power Management Capability ID */ +#define PMNEXT 0x41 /* Power Management Next Capability + Pointer */ +#define PMC 0x42 /* Power Management Capabilities */ +#define PMCSR 0x44 /* Power Management Control/Status */ +#define PMCSR_BSE 0x46 /* PMCSR Bridge Support Extensions */ +#define PMDATA 0x47 /* Power Management Data */ +#define HS_CNTL 0x48 /* Hot Swap Control */ +#define HS_NEXT 0x49 /* Hot Swap Next Capability Pointer */ +#define HS_CSR 0x4A /* Hot Swap Control/Status */ +#define PVPDCNTL 0x4C /* PCI Vital Product Data Control */ +#define PVPD_NEXT 0x4D /* PCI Vital Product Data Next + Capability Pointer */ +#define PVPDAD 0x4E /* PCI Vital Product Data Address */ +#define PVPDATA 0x50 /* PCI VPD Data */ + +/* + * bit definitions for PCICSR lower half (Command Register) + */ +#define PCICR_IO (1 << 0) /* if set: device responds to I/O space accesses */ +#define PCICR_MEMORY (1 << 1) /* if set: device responds to memory space accesses */ +#define PCICR_MASTER (1 << 2) /* if set: device is master */ +#define PCICR_SPECIAL (1 << 3) /* if set: device reacts on special cycles */ +#define PCICR_MEMWI (1 << 4) /* if set: device deals with memory write and invalidate */ +#define PCICR_VGA_SNOOP (1 << 5) /* if set: capable of palette snoop */ +#define PCICR_PERR (1 << 6) /* if set: reacts to parity errors */ +#define PCICR_STEPPING (1 << 7) /* if set: stepping enabled */ +#define PCICR_SERR (1 << 8) /* if set: SERR pin enabled */ +#define PCICR_FAST_BTOB_E (1 << 9) /* if set: fast back-to-back enabled */ +#define PCICR_INT_DISABLE (1 << 10) /* if set: disable interrupts from this device */ +/* + * bit definitions for PCICSR upper half (Status Register) + */ +#define PCISR_INTERRUPT (1 << 3) /* device requested interrupt */ +#define PCISR_CAPABILITIES (1 << 4) /* if set, capabilities pointer is valid */ +#define PCISR_66MHZ (1 << 5) /* 66 MHz capable */ +#define PCISR_UDF (1 << 6) /* UDF supported */ +#define PCISR_FAST_BTOB (1 << 7) /* Fast back-to-back enabled */ +#define PCISR_DPARITY_ERROR (1 << 8) /* data parity error detected */ + +#define PCISR_T_ABORT_S (1 << 11) /* target abort signaled */ +#define PCISR_T_ABORT_R (1 << 12) /* target abort received */ +#define PCISR_M_ABORT_R (1 << 13) /* master abort received */ +#define PCISR_S_ERROR_S (1 << 14) /* system error signaled */ +#define PCISR_PARITY_ERR (1 << 15) /* data parity error */ + +/* Header type 1 (PCI-to-PCI bridges) */ +#define PCI_PRIMARY_BUS 0x1B /* Primary bus number */ +#define PCI_SECONDARY_BUS 0x1A /* Secondary bus number */ +#define PCI_SUBORDINATE_BUS 0x19 /* Highest bus number behind the bridge */ +#define PCI_SEC_LATENCY_TIMER 0x18 /* Latency timer for secondary interface */ +#define PCI_IO_BASE 0x1C /* I/O range behind the bridge */ +#define PCI_IO_LIMIT 0x1D +#define PCI_SEC_STATUS 0x1C /* Secondary status register, only bit 14 used */ +#define PCI_MEMORY_BASE 0x20 /* Memory range behind */ +#define PCI_MEMORY_LIMIT 0x22 +#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ +#define PCI_PREF_MEMORY_LIMIT 0x26 +#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ +#define PCI_PREF_LIMIT_UPPER32 0x2C +#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ +#define PCI_IO_LIMIT_UPPER16 0x32 +#define PCI_BRIDGE_CONTROL 0x3E /* Bridge Control */ + +struct pci_rd /* structure of resource descriptor */ +{ + unsigned short next; /* length of the following structure */ + unsigned short flags; /* type of resource and misc. flags */ + unsigned long start; /* start-address of resource */ + unsigned long length; /* length of resource */ + unsigned long offset; /* offset PCI to phys. CPU Address */ + unsigned long dmaoffset; /* offset for DMA-transfers */ +}; + +typedef struct /* structure of address conversion */ +{ + unsigned long adr; /* calculated address (CPU<->PCI) */ + unsigned long len; /* length of memory range */ +} PCI_CONV_ADR; + +/******************************************************************************/ +/* PCI-BIOS Error Codes */ +/******************************************************************************/ +#define PCI_SUCCESSFUL 0 /* everything's fine */ +#define PCI_FUNC_NOT_SUPPORTED -2 /* function not supported */ +#define PCI_BAD_VENDOR_ID -3 /* wrong Vendor ID */ +#define PCI_DEVICE_NOT_FOUND -4 /* PCI-Device not found */ +#define PCI_BAD_REGISTER_NUMBER -5 /* wrong register number */ +#define PCI_SET_FAILED -6 /* reserved for later use */ +#define PCI_BUFFER_TOO_SMALL -7 /* reserved for later use */ +#define PCI_GENERAL_ERROR -8 /* general BIOS error code */ +#define PCI_BAD_HANDLE -9 /* wrong/unknown PCI-handle */ + +/******************************************************************************/ +/* Flags used in Resource-Descriptor */ +/******************************************************************************/ +#define FLG_IO 0x4000 /* Ressource in IO range */ +#define FLG_ROM 0x2000 /* Expansion ROM */ +#define FLG_LAST 0x8000 /* last ressource */ +#define FLG_8BIT 0x0100 /* 8 bit accesses allowed */ +#define FLG_16BIT 0x0200 /* 16 bit accesses allowed */ +#define FLG_32BIT 0x0400 /* 32 bit accesses allowed */ +#define FLG_ENDMASK 0x000F /* mask for byte ordering */ + +/******************************************************************************/ +/* Values used in FLG_ENDMASK for Byte Ordering */ +/******************************************************************************/ +#define ORD_MOTOROLA 0 /* Motorola (big endian) */ +#define ORD_INTEL_AS 1 /* Intel (little endian), addr.swapped */ +#define ORD_INTEL_LS 2 /* Intel (little endian), lane swapped */ +#define ORD_UNKNOWN 15 /* unknown (BIOS-calls allowed only) */ + +/******************************************************************************/ +/* Status Info used in Device-Descriptor */ +/******************************************************************************/ +#define DEVICE_FREE 0 /* Device is not used */ +#define DEVICE_USED 1 /* Device is used by another driver */ +#define DEVICE_CALLBACK 2 /* used, but driver can be cancelled */ +#define DEVICE_AVAILABLE 3 /* used, not available */ +#define NO_DEVICE -1 /* no device detected */ + +/* PCI configuration space macros */ + +/* register 0x00 macros */ +#define PCI_DEVICE_ID(i) (uint16_t)(((i) & 0xffff0000) >> 16) +#define PCI_VENDOR_ID(i) (uint16_t) ((i) & 0xffff) + +/* register 0x04 macros */ +#define PCI_STATUS(i) ((i) & 0xffff) +#define PCI_COMMAND(i) (((i) >> 16) & 0xffff) + +/* register 0x08 macros */ +#define PCI_CLASS_CODE(i) (((i) & 0xff000000) >> 24) +#define PCI_SUBCLASS(i) (((i) & 0x00ff0000) >> 16) +#define PCI_PROG_IF(i) (((i) & 0x0000ff00) >> 8) +#define PCI_REVISION_ID(i) (((i) & 0x000000ff)) + +/* register 0x0c macros */ +#define PCI_BIST(i) (((i) & 0xff000000) >> 24) +#define PCI_HEADER_TYPE(i) (((i) & 0x00ff0000) >> 16) +#define PCI_LAT_TIMER(i) (((i) & 0x0000ff00) >> 8) +#define PCI_CACHELINE_SIZE(i) (((i) & 0x000000ff)) + +/* register 0x2c macros */ +#define PCI_SUBSYS_ID(i) ((i) & 0xffff0000) >> 16) +#define PCI_SUBSYS_VID(i) ((i) & 0xffff)) + +/* register 0x34 macros */ +#define PCI_CAPABILITIES(i) ((i) & 0xff) + +/* register 0x3c macros */ +#define PCI_MAX_LATENCY(i) (((i) & 0xff000000) >> 24) +#define PCI_MIN_GRANT(i) (((i) & 0xff0000) >> 16) +#define PCI_INTERRUPT_PIN(i) (((i) & 0xff00) >> 8) +#define PCI_INTERRUPT_LINE(i) (((i)) & 0xff) + +#define IS_PCI_MEM_BAR(i) ((i) & 1) == 0 +#define IS_PCI_IO_BAR(i) ((i) & 1) == 1 +#define PCI_MEMBAR_TYPE(i) (((i) & 0x6) >> 1) +#define PCI_IOBAR_ADR(i) (((i) & 0xfffffffc)) +#define PCI_MEMBAR_ADR(i) (((i) & 0xfffffff0)) + +extern void init_eport(void); +extern void init_xlbus_arbiter(void); +extern void init_pci(void); +extern int pci_handle2index(int32_t handle); + +extern int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index); +extern int32_t pci_find_classcode(uint32_t classcode, int index); + +extern int32_t pci_get_interrupt_cause(void); +extern int32_t pci_call_interrupt_chain(int32_t handle, int32_t data); + +/* + * match bits for pci_find_classcode() + */ +#define PCI_FIND_BASE_CLASS (1 << 26) +#define PCI_FIND_SUB_CLASS (1 << 25) +#define PCI_FIND_PROG_IF (1 << 24) + +extern uint32_t pci_read_config_longword(int32_t handle, int offset); +extern uint16_t pci_read_config_word(int32_t handle, int offset); +extern uint8_t pci_read_config_byte(int32_t handle, int offset); + +extern int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t value); +extern int32_t pci_write_config_word(int32_t handle, int offset, uint16_t value); +extern int32_t pci_write_config_byte(int32_t handle, int offset, uint8_t value); + +typedef int (*pci_interrupt_handler)(int param); + +extern int32_t pci_hook_interrupt(int32_t handle, void *handler, void *parameter); +extern int32_t pci_unhook_interrupt(int32_t handle); + +extern struct pci_rd *pci_get_resource(int32_t handle); + +/* + * Not implemented PCI_BIOS functions + */ +extern uint8_t pci_fast_read_config_byte(int32_t handle, uint16_t reg); +extern uint16_t pci_fast_read_config_word(int32_t handle, uint16_t reg); +extern uint32_t pci_fast_read_config_longword(int32_t handle, uint16_t reg); +extern int32_t pci_special_cycle(uint16_t bus, uint32_t data); +extern int32_t pci_get_routing(int32_t handle); +extern int32_t pci_set_interrupt(int32_t handle); +extern int32_t pci_get_card_used(int32_t handle, uint32_t *address); +extern int32_t pci_set_card_used(int32_t handle, uint32_t *callback); +extern int32_t pci_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address); +extern int32_t pci_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address); +extern int32_t pci_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address); +extern uint8_t pci_fast_read_mem_byte(int32_t handle, uint32_t offset); +extern uint16_t pci_fast_read_mem_word(int32_t handle, uint32_t offset); +extern uint32_t pci_fast_read_mem_longword(int32_t handle, uint32_t offset); +extern int32_t pci_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val); +extern int32_t pci_write_mem_word(int32_t handle, uint32_t offset, uint16_t val); +extern int32_t pci_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val); +extern int32_t pci_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address); +extern int32_t pci_read_io_word(int32_t handle, uint32_t offset, uint16_t *address); +extern int32_t pci_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address); +extern uint8_t pci_fast_read_io_byte(int32_t handle, uint32_t offset); +extern uint16_t pci_fast_read_io_word(int32_t handle, uint32_t offset); +extern uint32_t pci_fast_read_io_longword(int32_t handle, uint32_t offset); +extern int32_t pci_write_io_byte(int32_t handle, uint32_t offset, uint16_t val); +extern int32_t pci_write_io_word(int32_t handle, uint32_t offset, uint16_t val); +extern int32_t pci_write_io_longword(int32_t handle, uint32_t offset, uint32_t val); +extern int32_t pci_get_machine_id(void); +extern int32_t pci_get_pagesize(void); +extern int32_t pci_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer); +extern int32_t pci_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer); +extern int32_t pci_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer); +extern int32_t pci_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer); + +/* + * prototypes for PCI wrapper routines + */ +extern int32_t wrapper_find_pci_device(uint32_t id, uint16_t index); +extern int32_t wrapper_find_pci_classcode(uint32_t class, uint16_t index); +extern int32_t wrapper_read_config_byte(int32_t handle, uint16_t reg, uint8_t *address); +extern int32_t wrapper_read_config_word(int32_t handle, uint16_t reg, uint16_t *address); +extern int32_t wrapper_read_config_longword(int32_t handle, uint16_t reg, uint32_t *address); +extern uint8_t wrapper_fast_read_config_byte(int32_t handle, uint16_t reg); +extern uint16_t wrapper_fast_read_config_word(int32_t handle, uint16_t reg); +extern uint32_t wrapper_fast_read_config_longword(int32_t handle, uint16_t reg); +extern int32_t wrapper_write_config_byte(int32_t handle, uint16_t reg, uint16_t val); +extern int32_t wrapper_write_config_word(int32_t handle, uint16_t reg, uint16_t val); +extern int32_t wrapper_write_config_longword(int32_t handle, uint16_t reg, uint32_t val); +extern int32_t wrapper_hook_interrupt(int32_t handle, uint32_t *routine, uint32_t *parameter); +extern int32_t wrapper_unhook_interrupt(int32_t handle); +extern int32_t wrapper_special_cycle(uint16_t bus, uint32_t data); +extern int32_t wrapper_get_routing(int32_t handle); +extern int32_t wrapper_set_interrupt(int32_t handle); +extern int32_t wrapper_get_resource(int32_t handle); +extern int32_t wrapper_get_card_used(int32_t handle, uint32_t *address); +extern int32_t wrapper_set_card_used(int32_t handle, uint32_t *callback); +extern int32_t wrapper_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address); +extern int32_t wrapper_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address); +extern int32_t wrapper_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address); +extern uint8_t wrapper_fast_read_mem_byte(int32_t handle, uint32_t offset); +extern uint16_t wrapper_fast_read_mem_word(int32_t handle, uint32_t offset); +extern uint32_t wrapper_fast_read_mem_longword(int32_t handle, uint32_t offset); +extern int32_t wrapper_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val); +extern int32_t wrapper_write_mem_word(int32_t handle, uint32_t offset, uint16_t val); +extern int32_t wrapper_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val); +extern int32_t wrapper_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address); +extern int32_t wrapper_read_io_word(int32_t handle, uint32_t offset, uint16_t *address); +extern int32_t wrapper_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address); +extern uint8_t wrapper_fast_read_io_byte(int32_t handle, uint32_t offset); +extern uint16_t wrapper_fast_read_io_word(int32_t handle, uint32_t offset); +extern uint32_t wrapper_fast_read_io_longword(int32_t handle, uint32_t offset); +extern int32_t wrapper_write_io_byte(int32_t handle, uint32_t offset, uint16_t val); +extern int32_t wrapper_write_io_word(int32_t handle, uint32_t offset, uint16_t val); +extern int32_t wrapper_write_io_longword(int32_t handle, uint32_t offset, uint32_t val); +extern int32_t wrapper_get_machine_id(void); +extern int32_t wrapper_get_pagesize(void); +extern int32_t wrapper_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer); +extern int32_t wrapper_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer); +extern int32_t wrapper_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer); +extern int32_t wrapper_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer); + +#define PCI_MK_CONF_ADDR(bus, device, function) (MCF_PCI_PCICAR_E | \ + ((bus) << 16) | \ + ((device << 8) | \ + (function)) + +#define PCI_HANDLE(bus, slot, function) (0 | ((bus & 0xff) << 10 | (slot & 0x1f) << 3 | (function & 7))) +#define PCI_BUS_FROM_HANDLE(h) (((h) & 0xff00) >> 10) +#define PCI_DEVICE_FROM_HANDLE(h) (((h) & 0xf8) >> 3) +#define PCI_FUNCTION_FROM_HANDLE(h) (((h) & 0x7)) + +extern void pci_dump_registers(int32_t handle); + +#endif /* _PCI_H_ */ diff --git a/tos/pci_mem/include/util.h b/tos/pci_mem/include/util.h new file mode 100644 index 0000000..355c1ac --- /dev/null +++ b/tos/pci_mem/include/util.h @@ -0,0 +1,128 @@ +/* + * util.h + * + * Byteswapping macros lend from EmuTOS sources + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 27.10.2013 + * Author: mfro + */ + +#ifndef UTIL_H_ +#define UTIL_H_ + +#include + +#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory") + +/* + * uint16_t swpw(uint16_t val); + * swap endianess of val, 16 bits only. + */ +static inline uint16_t swpw(uint16_t w) +{ + return (w << 8) | (w >> 8); +} + +/* + * uint32_t swpl(uint32_t val); + * swap endianess of val, 32 bits only. + * e.g. ABCD => DCBA + */ +static inline uint32_t swpl(uint32_t l) +{ + return ((l & 0xff000000) >> 24) | ((l & 0x00ff0000) >> 8) | + ((l & 0x0000ff00) << 8) | (l << 24); +} + + +/* + * WORD swpw2(ULONG val); + * swap endianness of val, treated as two 16-bit words. + * e.g. ABCD => BADC + */ + +#define swpw2(a) \ + __extension__ \ + ({unsigned long _tmp; \ + __asm__ __volatile__ \ + ("move.b (%1),%0\n\t" \ + "move.b 1(%1),(%1)\n\t" \ + "move.b %0,1(%1)\n\t" \ + "move.b 2(%1),%0\n\t" \ + "move.b 3(%1),2(%1)\n\t" \ + "move.b %0,3(%1)" \ + : "=d"(_tmp) /* outputs */ \ + : "a"(&a) /* inputs */ \ + : "cc", "memory" /* clobbered */ \ + ); \ + }) + +/* + * WORD set_sr(WORD new); + * sets sr to the new value, and return the old sr value + */ + +#define set_sr(a) \ +__extension__ \ +({short _r, _a = (a); \ + __asm__ __volatile__ \ + ("move.w sr,%0\n\t" \ + "move.w %1,sr" \ + : "=&d"(_r) /* outputs */ \ + : "nd"(_a) /* inputs */ \ + : "cc", "memory" /* clobbered */ \ + ); \ + _r; \ +}) + + +/* + * WORD get_sr(void); + * returns the current value of sr. + */ + +#define get_sr() \ +__extension__ \ +({short _r; \ + __asm__ volatile \ + ("move.w sr,%0" \ + : "=dm"(_r) /* outputs */ \ + : /* inputs */ \ + : "cc", "memory" /* clobbered */ \ + ); \ + _r; \ +}) + + + +/* + * void regsafe_call(void *addr) + * Saves all registers to the stack, calls the function + * that addr points to, and restores the registers afterwards. + */ +#define regsafe_call(addr) \ +__extension__ \ +({__asm__ volatile ("lea -60(sp),sp\n\t" \ + "movem.l d0-d7/a0-a6,(sp)"); \ + ((void (*) (void)) addr)(); \ + __asm__ volatile ("movem.l (sp),d0-d7/a0-a6\n\t" \ + "lea 60(sp),sp"); \ +}) + + +#endif /* UTIL_H_ */ diff --git a/tos/pci_mem/pci_mem.config b/tos/pci_mem/pci_mem.config new file mode 100644 index 0000000..8cec188 --- /dev/null +++ b/tos/pci_mem/pci_mem.config @@ -0,0 +1 @@ +// ADD PREDEFINED MACROS HERE! diff --git a/tos/pci_mem/pci_mem.creator b/tos/pci_mem/pci_mem.creator new file mode 100644 index 0000000..e94cbbd --- /dev/null +++ b/tos/pci_mem/pci_mem.creator @@ -0,0 +1 @@ +[General] diff --git a/tos/pci_mem/pci_mem.files b/tos/pci_mem/pci_mem.files new file mode 100644 index 0000000..893c36e --- /dev/null +++ b/tos/pci_mem/pci_mem.files @@ -0,0 +1,6 @@ +include/driver_vec.h +Makefile +sources/bas_printf.c +sources/bas_string.c +sources/printf_helper.S +sources/pci_mem.c diff --git a/tos/pci_mem/pci_mem.includes b/tos/pci_mem/pci_mem.includes new file mode 100644 index 0000000..0e46827 --- /dev/null +++ b/tos/pci_mem/pci_mem.includes @@ -0,0 +1,2 @@ +include +/usr/m68k-atari-mint/include diff --git a/tos/pci_mem/sources/pci_mem.c b/tos/pci_mem/sources/pci_mem.c new file mode 100644 index 0000000..7bfea44 --- /dev/null +++ b/tos/pci_mem/sources/pci_mem.c @@ -0,0 +1,181 @@ +#include +#include +#include +#include +#include + +#include "MCF5475.h" +#include "driver_vec.h" +#include "pci.h" + +#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory") + +#define SYSCLK 132000 + + +int i; + +void add_mem(struct pci_native_driver_interface *pci) +{ + int32_t handle; + int16_t index = 0; + +#define PCI_READ_CONFIG_LONGWORD(a, b) (*pci->pci_read_config_longword)(a, b) +#define PCI_WRITE_CONFIG_LONGWORD(a, b) (*pci->pci_write_config_longword)(a, b) +#define PCI_FIND_DEVICE(a, b, c) (*pci->pci_find_device)(a, b, c) +#define PCI_GET_RESOURCE(a) (*pci->pci_get_resource)(a) + + printf("find ATI graphics card\r\n"); + + handle = PCI_FIND_DEVICE(0x5159, 0x1002, index); + if (handle > 0) + { + struct pci_rd *rd; + + printf("ATI device with handle 0x%02x found\r\n", (unsigned int) handle); + rd = PCI_GET_RESOURCE(handle); /* get resource descriptor for ATI graphics card */ + printf("rd=%p\r\n", rd); + printf("start=%lx, length=%lx, flags=%x\r\n", rd->start, rd->length, rd->flags); + + if (rd != NULL) + { + if (rd->start != 0L && rd->length > 0x04000000 && + !(rd->flags & FLG_IO) && !(rd->flags & FLG_ROM)) + { + int32_t err; + + if ((err = Maddalt(0x04000000 /* rd->start + 0x7C000000UL */, rd->length)) > 0) + { + printf("%ld MBytes of additional memory added to system at %p\r\n", + (long) (rd->length / 1024 / 1024), (void *) 0x04000000 /* rd->start + 0x7C000000 */); + return; + } + else + { + fprintf(stderr, "Maddalt() returned error code %ld\r\n", (long) err); + exit(1); + } + } + } + else + { + fprintf(stderr, "no resource descriptor for handle 0x%02x found", (unsigned int) handle); + exit(1); + } + } + else + { + fprintf(stderr, "no ATI graphics card found\r\n"); + exit(1); + } + +} + +/* + * temporarily replace the trap 0 handler with this so we can avoid + * getting caught by BaS versions that don't understand the driver interface + * exposure call. + * If we get here, we have a BaS version that doesn't support the trap 0 interface + */ +static void __attribute__((interrupt)) trap0_catcher(void) +{ + __asm__ __volatile__( + " clr.l d0 \n\t" // return 0 to indicate not supported + : + : + : + ); +} + +struct driver_table *get_bas_drivers(void) +{ + struct driver_table *ret = NULL; + void *old_vector; + + old_vector = Setexc(0x20, trap0_catcher); /* set our own temporarily */ + + __asm__ __volatile__( + " bra.s do_trap \n\t" + " .dc.l 0x5f424153 \n\t" // '_BAS' + "do_trap: trap #0 \n\t" + " move.l d0,%[ret] \n\t" + : [ret] "=m" (ret) /* output */ + : /* no inputs */ + : /* clobbered */ + ); + (void) Setexc(0x20, old_vector); /* restore original vector */ + + return ret; +} + +void pci_mem(void) +{ + struct driver_table *bas_drivers; + struct generic_interface *ifc; + bool pci_driver_found = false; + struct pci_native_driver_interface *pci_driver = NULL; + + bas_drivers = get_bas_drivers(); + + /* + * trap0_catcher should return 0L on failure, for some reason FireTOS + * returns -1L on a trap #0. Anyway, ... + */ + if (bas_drivers != NULL && bas_drivers != (void *) -1L) + { + printf("BaS driver vector: %p\r\n", bas_drivers); + printf("BaS version: %ld.%02ld\r\n", (long) bas_drivers->bas_version, (long) bas_drivers->bas_revision); + } + else + { + printf("BaS driver retrieval not supported\r\n"); + printf("(old BaS version or FireTOS?)\r\n"); + exit(1); + } + + ifc = bas_drivers->interfaces; + + do { + struct generic_interface *pci_driver_interface = NULL; + + printf("interface type: %ld\r\n", (long) ifc[i].type); + printf("interface version: %ld.%02ld\r\n", (long) ifc[i].version, (long) ifc[i].revision); + printf("interface name: %s\r\n", ifc[i].name); + printf("interface description: %s\r\n", ifc[i].description); + + if (ifc[i].type == PCI_NATIVE_DRIVER) + { + pci_driver_found = true; + + if (!pci_driver_interface || (ifc[i].version > pci_driver_interface->version || + (ifc[i].version == pci_driver_interface->version && ifc[i].revision > pci_driver_interface->revision))) + { + /* + * either no PCI driver interface found yet or with lower version or with lower version and higher revision + * + * replace it + */ + pci_driver = ifc[i].interface.pci_native; + pci_driver_interface = &ifc[i]; + printf("PCI native driver interface v%d.%02d found\r\n", pci_driver_interface->version, pci_driver_interface->revision); + printf("replaced old with newer driver version\r\n"); + } + } + } while (ifc[++i].type != END_OF_DRIVERS); + + if (pci_driver_found) + { + add_mem(pci_driver); + } +} + +int main(int argc, char *argv[]) +{ + printf("PCI Memory Adder\r\n"); + printf("\xbd 2016 M. Fr\x94schle\r\n"); + + Supexec(pci_mem); + + return 0; /* just to make the compiler happy, we will never return */ +} + diff --git a/tos/pci_test/Makefile b/tos/pci_test/Makefile new file mode 100755 index 0000000..fb8b857 --- /dev/null +++ b/tos/pci_test/Makefile @@ -0,0 +1,109 @@ +CROSS=Y + +CROSSBINDIR_IS_Y=m68k-atari-mint- +CROSSBINDIR_IS_N= + +CROSSBINDIR=$(CROSSBINDIR_IS_$(CROSS)) + +UNAME := $(shell uname) +ifeq ($(CROSS), Y) +ifeq ($(UNAME),Linux) +PREFIX=m68k-atari-mint +HATARI=hatari +else +PREFIX=m68k-atari-mint +HATARI=/usr/local/bin/hatari +endif +else +PREFIX=/usr +endif + +DEPEND=depend +TOPDIR = ../.. + +LIBCMINI=$(TOPDIR)/../libcmini/libcmini + +INCLUDE=-I$(LIBCMINI)/include -nostdlib +LIBS=-lcmini -nostdlib -lgcc +CC=$(PREFIX)/bin/gcc + +CC=$(CROSSBINDIR)gcc +STRIP=$(CROSSBINDIR)strip +STACK=$(CROSSBINDIR)stack + +APP=pci_test.prg +TEST_APP=$(APP) + +CFLAGS=\ + -O2\ + -fomit-frame-pointer \ + -g\ + -Wl,-Map,mapfile\ + -Wl,--defsym -Wl,__MBAR=0xff000000\ + -Wl,--defsym -Wl,__MMUBAR=0xff040000\ + -Wl,--defsym -Wl,__FPGA_JTAG_LOADED=0xff101000\ + -Wl,--defsym -Wl,__FPGA_JTAG_VALID=0xff101004\ + -Wl,--defsym -Wl,__VRAM=0x60000000\ + -Wall + +SRCDIR=sources +INCDIR=include +INCLUDE+=-I$(INCDIR) + +CSRCS=\ + $(SRCDIR)/pci_test.c + +ASRCS= + +COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS))) +AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS))) +OBJS=$(COBJS) $(AOBJS) + +TRGTDIRS=./m5475 ./m5475/mshort +OBJDIRS=$(patsubst %,%/objs,$(TRGTDIRS)) + +# +# multilib flags. These must match m68k-atari-mint-gcc -print-multi-lib output +# +m5475/$(APP):CFLAGS += -mcpu=5475 +m5475/mshort/$(APP): CFLAGS += -mcpu=5475 -mshort + +all:$(patsubst %,%/$(APP),$(TRGTDIRS)) +# +# generate pattern rules for multilib object files. +# +define CC_TEMPLATE +$(1)/objs/%.o:$(SRCDIR)/%.c + @echo CC $$< + @$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@ + +$(1)/objs/%.o:$(SRCDIR)/%.S + @echo CC $$< + @$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@ + +$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS)) +$(1)/$(APP): $$($(1)_OBJS) + @echo CC $$@ + @$(CC) $$(CFLAGS) -o $$@ $(LIBCMINI)/$(1)/startup.o $$($(1)_OBJS) -L$(LIBCMINI)/$(1) $(LIBS) + #@$(STRIP) $$@ +endef +$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR)))) + +$(DEPEND): $(ASRCS) $(CSRCS) + @-rm -f $(DEPEND) + @for d in $(TRGTDIRS);\ + do $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e "s#^\(.*\).o:#$$d/objs/\1.o:#" >> $(DEPEND); \ + done + + +clean: + @rm -f $(patsubst %,%/objs/*.o,$(TRGTDIRS)) $(patsubst %,%/$(APP),$(TRGTDIRS)) + @rm -f $(DEPEND) mapfile + +.PHONY: printvars +printvars: + @$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V)))) + +ifneq (clean,$(MAKECMDGOALS)) +-include $(DEPEND) +endif diff --git a/tos/pci_test/include/MCF5475.h b/tos/pci_test/include/MCF5475.h new file mode 100644 index 0000000..5ab1750 --- /dev/null +++ b/tos/pci_test/include/MCF5475.h @@ -0,0 +1,67 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_H__ +#define __MCF5475_H__ + +#include +/*** + * MCF5475 Derivative Memory map definitions from linker command files: + * __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE + * linker symbols must be defined in the linker command file. + */ + +typedef uint32_t __attribute__((__may_alias__)) uint32_t_a; /* a type to avoid gcc's complaints about pointer aliasing */ + +extern uint8_t _MBAR[]; +extern uint8_t _MMUBAR[]; +extern uint8_t _RAMBAR0[]; +extern uint8_t _RAMBAR0_SIZE[]; +extern uint8_t _RAMBAR1[]; +extern uint8_t _RAMBAR1_SIZE[]; + +#define MBAR_ADDRESS (uint32_t)_MBAR +#define MMUBAR_ADDRESS (uint32_t)_MMUBAR +#define RAMBAR0_ADDRESS (uint32_t)_RAMBAR0 +#define RAMBAR0_SIZE (uint32_t)_RAMBAR0_SIZE +#define RAMBAR1_ADDRESS (uint32_t)_RAMBAR1 +#define RAMBAR1_SIZE (uint32_t)_RAMBAR1_SIZE + + +#include "MCF5475_SIU.h" +#include "MCF5475_MMU.h" +#include "MCF5475_SDRAMC.h" +#include "MCF5475_XLB.h" +#include "MCF5475_CLOCK.h" +#include "MCF5475_FBCS.h" +#include "MCF5475_INTC.h" +#include "MCF5475_GPT.h" +#include "MCF5475_SLT.h" +#include "MCF5475_GPIO.h" +#include "MCF5475_PAD.h" +#include "MCF5475_PCI.h" +#include "MCF5475_PCIARB.h" +#include "MCF5475_EPORT.h" +#include "MCF5475_CTM.h" +#include "MCF5475_DMA.h" +#include "MCF5475_PSC.h" +#include "MCF5475_DSPI.h" +#include "MCF5475_I2C.h" +#include "MCF5475_FEC.h" +#include "MCF5475_USB.h" +#include "MCF5475_SRAM.h" +#include "MCF5475_SEC.h" + +#endif /* __MCF5475_H__ */ diff --git a/tos/pci_test/include/MCF5475_CLOCK.h b/tos/pci_test/include/MCF5475_CLOCK.h new file mode 100644 index 0000000..4603098 --- /dev/null +++ b/tos/pci_test/include/MCF5475_CLOCK.h @@ -0,0 +1,47 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_CLOCK_H__ +#define __MCF5475_CLOCK_H__ + + +/********************************************************************* +* +* Clock Module (CLOCK) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CLOCK_SPCR (*(volatile uint32_t*)(&_MBAR[0x300])) + + +/* Bit definitions and macros for MCF_CLOCK_SPCR */ +#define MCF_CLOCK_SPCR_MEMEN (0x1) +#define MCF_CLOCK_SPCR_PCIEN (0x2) +#define MCF_CLOCK_SPCR_FBEN (0x4) +#define MCF_CLOCK_SPCR_CAN0EN (0x8) +#define MCF_CLOCK_SPCR_DMAEN (0x10) +#define MCF_CLOCK_SPCR_FEC0EN (0x20) +#define MCF_CLOCK_SPCR_FEC1EN (0x40) +#define MCF_CLOCK_SPCR_USBEN (0x80) +#define MCF_CLOCK_SPCR_PSCEN (0x200) +#define MCF_CLOCK_SPCR_CAN1EN (0x800) +#define MCF_CLOCK_SPCR_CRYENA (0x1000) +#define MCF_CLOCK_SPCR_CRYENB (0x2000) +#define MCF_CLOCK_SPCR_COREN (0x4000) +#define MCF_CLOCK_SPCR_PLLK (0x80000000) + + +#endif /* __MCF5475_CLOCK_H__ */ diff --git a/tos/pci_test/include/MCF5475_CTM.h b/tos/pci_test/include/MCF5475_CTM.h new file mode 100644 index 0000000..5ba86e4 --- /dev/null +++ b/tos/pci_test/include/MCF5475_CTM.h @@ -0,0 +1,76 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_CTM_H__ +#define __MCF5475_CTM_H__ + + +/********************************************************************* +* +* Comm Timer Module (CTM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CTM_CTCR0 (*(volatile uint32_t*)(&_MBAR[0x7F00])) +#define MCF_CTM_CTCR1 (*(volatile uint32_t*)(&_MBAR[0x7F04])) +#define MCF_CTM_CTCR2 (*(volatile uint32_t*)(&_MBAR[0x7F08])) +#define MCF_CTM_CTCR3 (*(volatile uint32_t*)(&_MBAR[0x7F0C])) +#define MCF_CTM_CTCR4 (*(volatile uint32_t*)(&_MBAR[0x7F10])) +#define MCF_CTM_CTCR5 (*(volatile uint32_t*)(&_MBAR[0x7F14])) +#define MCF_CTM_CTCR6 (*(volatile uint32_t*)(&_MBAR[0x7F18])) +#define MCF_CTM_CTCR7 (*(volatile uint32_t*)(&_MBAR[0x7F1C])) +#define MCF_CTM_CTCRF(x) (*(volatile uint32_t*)(&_MBAR[0x7F00 + ((x)*0x4)])) +#define MCF_CTM_CTCRV(x) (*(volatile uint32_t*)(&_MBAR[0x7F10 + ((x-4)*0x4)])) + + +/* Bit definitions and macros for MCF_CTM_CTCRF */ +#define MCF_CTM_CTCRF_CRV(x) (((x)&0xFFFF)<<0) +#define MCF_CTM_CTCRF_S(x) (((x)&0xF)<<0x10) +#define MCF_CTM_CTCRF_S_CLK_1 (0) +#define MCF_CTM_CTCRF_S_CLK_2 (0x10000) +#define MCF_CTM_CTCRF_S_CLK_4 (0x20000) +#define MCF_CTM_CTCRF_S_CLK_8 (0x30000) +#define MCF_CTM_CTCRF_S_CLK_16 (0x40000) +#define MCF_CTM_CTCRF_S_CLK_32 (0x50000) +#define MCF_CTM_CTCRF_S_CLK_64 (0x60000) +#define MCF_CTM_CTCRF_S_CLK_128 (0x70000) +#define MCF_CTM_CTCRF_S_CLK_256 (0x80000) +#define MCF_CTM_CTCRF_S_CLK_EXT (0x90000) +#define MCF_CTM_CTCRF_PCT(x) (((x)&0x7)<<0x14) +#define MCF_CTM_CTCRF_PCT_100 (0) +#define MCF_CTM_CTCRF_PCT_50 (0x100000) +#define MCF_CTM_CTCRF_PCT_25 (0x200000) +#define MCF_CTM_CTCRF_PCT_12p5 (0x300000) +#define MCF_CTM_CTCRF_PCT_6p25 (0x400000) +#define MCF_CTM_CTCRF_PCT_OFF (0x500000) +#define MCF_CTM_CTCRF_M (0x800000) +#define MCF_CTM_CTCRF_IM (0x1000000) +#define MCF_CTM_CTCRF_I (0x80000000) + +/* Bit definitions and macros for MCF_CTM_CTCRV */ +#define MCF_CTM_CTCRV_CRV(x) (((x)&0xFFFFFF)<<0) +#define MCF_CTM_CTCRV_PCT(x) (((x)&0x7)<<0x18) +#define MCF_CTM_CTCRV_PCT_100 (0) +#define MCF_CTM_CTCRV_PCT_50 (0x1000000) +#define MCF_CTM_CTCRV_PCT_25 (0x2000000) +#define MCF_CTM_CTCRV_PCT_12p5 (0x3000000) +#define MCF_CTM_CTCRV_PCT_6p25 (0x4000000) +#define MCF_CTM_CTCRV_PCT_OFF (0x5000000) +#define MCF_CTM_CTCRV_M (0x8000000) +#define MCF_CTM_CTCRV_S (0x10000000) + + +#endif /* __MCF5475_CTM_H__ */ diff --git a/tos/pci_test/include/MCF5475_DMA.h b/tos/pci_test/include/MCF5475_DMA.h new file mode 100644 index 0000000..4e6f916 --- /dev/null +++ b/tos/pci_test/include/MCF5475_DMA.h @@ -0,0 +1,234 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_DMA_H__ +#define __MCF5475_DMA_H__ + + +/********************************************************************* +* +* Multichannel DMA (DMA) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DMA_TASKBAR (*(volatile uint32_t*)(&_MBAR[0x8000])) +#define MCF_DMA_CP (*(volatile uint32_t*)(&_MBAR[0x8004])) +#define MCF_DMA_EP (*(volatile uint32_t*)(&_MBAR[0x8008])) +#define MCF_DMA_VP (*(volatile uint32_t*)(&_MBAR[0x800C])) +#define MCF_DMA_PTD (*(volatile uint32_t*)(&_MBAR[0x8010])) +#define MCF_DMA_DIPR (*(volatile uint32_t*)(&_MBAR[0x8014])) +#define MCF_DMA_DIMR (*(volatile uint32_t*)(&_MBAR[0x8018])) +#define MCF_DMA_TCR0 (*(volatile uint16_t*)(&_MBAR[0x801C])) +#define MCF_DMA_TCR1 (*(volatile uint16_t*)(&_MBAR[0x801E])) +#define MCF_DMA_TCR2 (*(volatile uint16_t*)(&_MBAR[0x8020])) +#define MCF_DMA_TCR3 (*(volatile uint16_t*)(&_MBAR[0x8022])) +#define MCF_DMA_TCR4 (*(volatile uint16_t*)(&_MBAR[0x8024])) +#define MCF_DMA_TCR5 (*(volatile uint16_t*)(&_MBAR[0x8026])) +#define MCF_DMA_TCR6 (*(volatile uint16_t*)(&_MBAR[0x8028])) +#define MCF_DMA_TCR7 (*(volatile uint16_t*)(&_MBAR[0x802A])) +#define MCF_DMA_TCR8 (*(volatile uint16_t*)(&_MBAR[0x802C])) +#define MCF_DMA_TCR9 (*(volatile uint16_t*)(&_MBAR[0x802E])) +#define MCF_DMA_TCR10 (*(volatile uint16_t*)(&_MBAR[0x8030])) +#define MCF_DMA_TCR11 (*(volatile uint16_t*)(&_MBAR[0x8032])) +#define MCF_DMA_TCR12 (*(volatile uint16_t*)(&_MBAR[0x8034])) +#define MCF_DMA_TCR13 (*(volatile uint16_t*)(&_MBAR[0x8036])) +#define MCF_DMA_TCR14 (*(volatile uint16_t*)(&_MBAR[0x8038])) +#define MCF_DMA_TCR15 (*(volatile uint16_t*)(&_MBAR[0x803A])) +#define MCF_DMA_PRIOR0 (*(volatile uint8_t *)(&_MBAR[0x803C])) +#define MCF_DMA_PRIOR1 (*(volatile uint8_t *)(&_MBAR[0x803D])) +#define MCF_DMA_PRIOR2 (*(volatile uint8_t *)(&_MBAR[0x803E])) +#define MCF_DMA_PRIOR3 (*(volatile uint8_t *)(&_MBAR[0x803F])) +#define MCF_DMA_PRIOR4 (*(volatile uint8_t *)(&_MBAR[0x8040])) +#define MCF_DMA_PRIOR5 (*(volatile uint8_t *)(&_MBAR[0x8041])) +#define MCF_DMA_PRIOR6 (*(volatile uint8_t *)(&_MBAR[0x8042])) +#define MCF_DMA_PRIOR7 (*(volatile uint8_t *)(&_MBAR[0x8043])) +#define MCF_DMA_PRIOR8 (*(volatile uint8_t *)(&_MBAR[0x8044])) +#define MCF_DMA_PRIOR9 (*(volatile uint8_t *)(&_MBAR[0x8045])) +#define MCF_DMA_PRIOR10 (*(volatile uint8_t *)(&_MBAR[0x8046])) +#define MCF_DMA_PRIOR11 (*(volatile uint8_t *)(&_MBAR[0x8047])) +#define MCF_DMA_PRIOR12 (*(volatile uint8_t *)(&_MBAR[0x8048])) +#define MCF_DMA_PRIOR13 (*(volatile uint8_t *)(&_MBAR[0x8049])) +#define MCF_DMA_PRIOR14 (*(volatile uint8_t *)(&_MBAR[0x804A])) +#define MCF_DMA_PRIOR15 (*(volatile uint8_t *)(&_MBAR[0x804B])) +#define MCF_DMA_PRIOR16 (*(volatile uint8_t *)(&_MBAR[0x804C])) +#define MCF_DMA_PRIOR17 (*(volatile uint8_t *)(&_MBAR[0x804D])) +#define MCF_DMA_PRIOR18 (*(volatile uint8_t *)(&_MBAR[0x804E])) +#define MCF_DMA_PRIOR19 (*(volatile uint8_t *)(&_MBAR[0x804F])) +#define MCF_DMA_PRIOR20 (*(volatile uint8_t *)(&_MBAR[0x8050])) +#define MCF_DMA_PRIOR21 (*(volatile uint8_t *)(&_MBAR[0x8051])) +#define MCF_DMA_PRIOR22 (*(volatile uint8_t *)(&_MBAR[0x8052])) +#define MCF_DMA_PRIOR23 (*(volatile uint8_t *)(&_MBAR[0x8053])) +#define MCF_DMA_PRIOR24 (*(volatile uint8_t *)(&_MBAR[0x8054])) +#define MCF_DMA_PRIOR25 (*(volatile uint8_t *)(&_MBAR[0x8055])) +#define MCF_DMA_PRIOR26 (*(volatile uint8_t *)(&_MBAR[0x8056])) +#define MCF_DMA_PRIOR27 (*(volatile uint8_t *)(&_MBAR[0x8057])) +#define MCF_DMA_PRIOR28 (*(volatile uint8_t *)(&_MBAR[0x8058])) +#define MCF_DMA_PRIOR29 (*(volatile uint8_t *)(&_MBAR[0x8059])) +#define MCF_DMA_PRIOR30 (*(volatile uint8_t *)(&_MBAR[0x805A])) +#define MCF_DMA_PRIOR31 (*(volatile uint8_t *)(&_MBAR[0x805B])) +#define MCF_DMA_IMCR (*(volatile uint32_t*)(&_MBAR[0x805C])) +#define MCF_DMA_TSKSZ0 (*(volatile uint32_t*)(&_MBAR[0x8060])) +#define MCF_DMA_TSKSZ1 (*(volatile uint32_t*)(&_MBAR[0x8064])) +#define MCF_DMA_DBGCOMP0 (*(volatile uint32_t*)(&_MBAR[0x8070])) +#define MCF_DMA_DBGCOMP2 (*(volatile uint32_t*)(&_MBAR[0x8074])) +#define MCF_DMA_DBGCTL (*(volatile uint32_t*)(&_MBAR[0x8078])) +#define MCF_DMA_TCR(x) (*(volatile uint16_t*)(&_MBAR[0x801C + ((x)*0x2)])) +#define MCF_DMA_PRIOR(x) (*(volatile uint8_t *)(&_MBAR[0x803C + ((x)*0x1)])) + + +/* Bit definitions and macros for MCF_DMA_TASKBAR */ +#define MCF_DMA_TASKBAR_TASK_BASE_ADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_CP */ +#define MCF_DMA_CP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_EP */ +#define MCF_DMA_EP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_VP */ +#define MCF_DMA_VP_VARIABLE_POINTER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_PTD */ +#define MCF_DMA_PTD_PCTL0 (0x1) +#define MCF_DMA_PTD_PCTL1 (0x2) +#define MCF_DMA_PTD_PCTL13 (0x2000) +#define MCF_DMA_PTD_PCTL14 (0x4000) +#define MCF_DMA_PTD_PCTL15 (0x8000) + +/* Bit definitions and macros for MCF_DMA_DIPR */ +#define MCF_DMA_DIPR_TASK(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DIMR */ +#define MCF_DMA_DIMR_TASK(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_TCR */ +#define MCF_DMA_TCR_ASTSKNUM(x) (((x)&0xF)<<0) +#define MCF_DMA_TCR_HLDINITNUM (0x20) +#define MCF_DMA_TCR_HIPRITSKEN (0x40) +#define MCF_DMA_TCR_ASTRT (0x80) +#define MCF_DMA_TCR_INITNUM(x) (((x)&0x1F)<<0x8) +#define MCF_DMA_TCR_ALWINIT (0x2000) +#define MCF_DMA_TCR_V (0x4000) +#define MCF_DMA_TCR_EN (0x8000) + +/* Bit definitions and macros for MCF_DMA_PRIOR */ +#define MCF_DMA_PRIOR_PRI(x) (((x)&0x7)<<0) +#define MCF_DMA_PRIOR_HLD (0x80) + +/* Bit definitions and macros for MCF_DMA_IMCR */ +#define MCF_DMA_IMCR_IMC16(x) (((x)&0x3)<<0) +#define MCF_DMA_IMCR_IMC17(x) (((x)&0x3)<<0x2) +#define MCF_DMA_IMCR_IMC18(x) (((x)&0x3)<<0x4) +#define MCF_DMA_IMCR_IMC19(x) (((x)&0x3)<<0x6) +#define MCF_DMA_IMCR_IMC20(x) (((x)&0x3)<<0x8) +#define MCF_DMA_IMCR_IMC21(x) (((x)&0x3)<<0xA) +#define MCF_DMA_IMCR_IMC22(x) (((x)&0x3)<<0xC) +#define MCF_DMA_IMCR_IMC23(x) (((x)&0x3)<<0xE) +#define MCF_DMA_IMCR_IMC24(x) (((x)&0x3)<<0x10) +#define MCF_DMA_IMCR_IMC25(x) (((x)&0x3)<<0x12) +#define MCF_DMA_IMCR_IMC26(x) (((x)&0x3)<<0x14) +#define MCF_DMA_IMCR_IMC27(x) (((x)&0x3)<<0x16) +#define MCF_DMA_IMCR_IMC28(x) (((x)&0x3)<<0x18) +#define MCF_DMA_IMCR_IMC29(x) (((x)&0x3)<<0x1A) +#define MCF_DMA_IMCR_IMC30(x) (((x)&0x3)<<0x1C) +#define MCF_DMA_IMCR_IMC31(x) (((x)&0x3)<<0x1E) + + +#define MCF_DMA_IMCR_IMC16_FEC0RX (0x00000000) +#define MCF_DMA_IMCR_IMC17_FEC0TX (0x00000000) +#define MCF_DMA_IMCR_IMC18_FEC0RX (0x00000020) +#define MCF_DMA_IMCR_IMC19_FEC0TX (0x00000080) +#define MCF_DMA_IMCR_IMC20_FEC1RX (0x00000100) +#define MCF_DMA_IMCR_IMC21_DREQ1 (0x00000000) +#define MCF_DMA_IMCR_IMC21_FEC1TX (0x00000400) +#define MCF_DMA_IMCR_IMC22_FEC0RX (0x00001000) +#define MCF_DMA_IMCR_IMC23_FEC0TX (0x00004000) +#define MCF_DMA_IMCR_IMC24_CTM0 (0x00010000) +#define MCF_DMA_IMCR_IMC24_FEC1RX (0x00020000) +#define MCF_DMA_IMCR_IMC25_CTM1 (0x00040000) +#define MCF_DMA_IMCR_IMC25_FEC1TX (0x00080000) +#define MCF_DMA_IMCR_IMC26_USBEP4 (0x00000000) +#define MCF_DMA_IMCR_IMC26_CTM2 (0x00200000) +#define MCF_DMA_IMCR_IMC27_USBEP5 (0x00000000) +#define MCF_DMA_IMCR_IMC27_CTM3 (0x00800000) +#define MCF_DMA_IMCR_IMC28_USBEP6 (0x00000000) +#define MCF_DMA_IMCR_IMC28_CTM4 (0x01000000) +#define MCF_DMA_IMCR_IMC28_DREQ1 (0x02000000) +#define MCF_DMA_IMCR_IMC28_PSC2RX (0x03000000) +#define MCF_DMA_IMCR_IMC29_DREQ1 (0x04000000) +#define MCF_DMA_IMCR_IMC29_CTM5 (0x08000000) +#define MCF_DMA_IMCR_IMC29_PSC2TX (0x0C000000) +#define MCF_DMA_IMCR_IMC30_FEC1RX (0x00000000) +#define MCF_DMA_IMCR_IMC30_CTM6 (0x10000000) +#define MCF_DMA_IMCR_IMC30_PSC3RX (0x30000000) +#define MCF_DMA_IMCR_IMC31_FEC1TX (0x00000000) +#define MCF_DMA_IMCR_IMC31_CTM7 (0x80000000) +#define MCF_DMA_IMCR_IMC31_PSC3TX (0xC0000000) + +/* Bit definitions and macros for MCF_DMA_TSKSZ0 */ +#define MCF_DMA_TSKSZ0_DSTSZ7(x) (((x)&0x3)<<0) +#define MCF_DMA_TSKSZ0_SRCSZ7(x) (((x)&0x3)<<0x2) +#define MCF_DMA_TSKSZ0_DSTSZ6(x) (((x)&0x3)<<0x4) +#define MCF_DMA_TSKSZ0_SRCSZ6(x) (((x)&0x3)<<0x6) +#define MCF_DMA_TSKSZ0_DSTSZ5(x) (((x)&0x3)<<0x8) +#define MCF_DMA_TSKSZ0_SRCSZ5(x) (((x)&0x3)<<0xA) +#define MCF_DMA_TSKSZ0_DSTSZ4(x) (((x)&0x3)<<0xC) +#define MCF_DMA_TSKSZ0_SRCSZ4(x) (((x)&0x3)<<0xE) +#define MCF_DMA_TSKSZ0_DSTSZ3(x) (((x)&0x3)<<0x10) +#define MCF_DMA_TSKSZ0_SRCSZ3(x) (((x)&0x3)<<0x12) +#define MCF_DMA_TSKSZ0_DSTSZ2(x) (((x)&0x3)<<0x14) +#define MCF_DMA_TSKSZ0_SRCSZ2(x) (((x)&0x3)<<0x16) +#define MCF_DMA_TSKSZ0_DSTSZ1(x) (((x)&0x3)<<0x18) +#define MCF_DMA_TSKSZ0_SRCSZ1(x) (((x)&0x3)<<0x1A) +#define MCF_DMA_TSKSZ0_DSTSZ0(x) (((x)&0x3)<<0x1C) +#define MCF_DMA_TSKSZ0_SRCSZ0(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_DMA_TSKSZ1 */ +#define MCF_DMA_TSKSZ1_DSTSZ15(x) (((x)&0x3)<<0) +#define MCF_DMA_TSKSZ1_SRCSZ15(x) (((x)&0x3)<<0x2) +#define MCF_DMA_TSKSZ1_DSTSZ14(x) (((x)&0x3)<<0x4) +#define MCF_DMA_TSKSZ1_SRCSZ14(x) (((x)&0x3)<<0x6) +#define MCF_DMA_TSKSZ1_DSTSZ13(x) (((x)&0x3)<<0x8) +#define MCF_DMA_TSKSZ1_SRCSZ13(x) (((x)&0x3)<<0xA) +#define MCF_DMA_TSKSZ1_DSTSZ12(x) (((x)&0x3)<<0xC) +#define MCF_DMA_TSKSZ1_SRCSZ12(x) (((x)&0x3)<<0xE) +#define MCF_DMA_TSKSZ1_DSTSZ11(x) (((x)&0x3)<<0x10) +#define MCF_DMA_TSKSZ1_SRCSZ11(x) (((x)&0x3)<<0x12) +#define MCF_DMA_TSKSZ1_DSTSZ10(x) (((x)&0x3)<<0x14) +#define MCF_DMA_TSKSZ1_SRCSZ10(x) (((x)&0x3)<<0x16) +#define MCF_DMA_TSKSZ1_DSTSZ9(x) (((x)&0x3)<<0x18) +#define MCF_DMA_TSKSZ1_SRCSZ9(x) (((x)&0x3)<<0x1A) +#define MCF_DMA_TSKSZ1_DSTSZ8(x) (((x)&0x3)<<0x1C) +#define MCF_DMA_TSKSZ1_SRCSZ8(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_DMA_DBGCOMP0 */ +#define MCF_DMA_DBGCOMP0_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DBGCOMP2 */ +#define MCF_DMA_DBGCOMP2_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DBGCTL */ +#define MCF_DMA_DBGCTL_I (0x2) +#define MCF_DMA_DBGCTL_E (0x4) +#define MCF_DMA_DBGCTL_AND_OR (0x80) +#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_2(x) (((x)&0x7)<<0x8) +#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_1(x) (((x)&0x7)<<0xB) +#define MCF_DMA_DBGCTL_B (0x4000) +#define MCF_DMA_DBGCTL_AA (0x8000) +#define MCF_DMA_DBGCTL_BLOCK_TASKS(x) (((x)&0xFFFF)<<0x10) + + +#endif /* __MCF5475_DMA_H__ */ diff --git a/tos/pci_test/include/MCF5475_DSPI.h b/tos/pci_test/include/MCF5475_DSPI.h new file mode 100644 index 0000000..76cac28 --- /dev/null +++ b/tos/pci_test/include/MCF5475_DSPI.h @@ -0,0 +1,150 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_DSPI_H__ +#define __MCF5475_DSPI_H__ + + +/********************************************************************* +* +* DMA Serial Peripheral Interface (DSPI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DSPI_DMCR (*(volatile uint32_t*)(&_MBAR[0x8A00])) +#define MCF_DSPI_DTCR (*(volatile uint32_t*)(&_MBAR[0x8A08])) +#define MCF_DSPI_DCTAR0 (*(volatile uint32_t*)(&_MBAR[0x8A0C])) +#define MCF_DSPI_DCTAR1 (*(volatile uint32_t*)(&_MBAR[0x8A10])) +#define MCF_DSPI_DCTAR2 (*(volatile uint32_t*)(&_MBAR[0x8A14])) +#define MCF_DSPI_DCTAR3 (*(volatile uint32_t*)(&_MBAR[0x8A18])) +#define MCF_DSPI_DCTAR4 (*(volatile uint32_t*)(&_MBAR[0x8A1C])) +#define MCF_DSPI_DCTAR5 (*(volatile uint32_t*)(&_MBAR[0x8A20])) +#define MCF_DSPI_DCTAR6 (*(volatile uint32_t*)(&_MBAR[0x8A24])) +#define MCF_DSPI_DCTAR7 (*(volatile uint32_t*)(&_MBAR[0x8A28])) +#define MCF_DSPI_DSR (*(volatile uint32_t*)(&_MBAR[0x8A2C])) +#define MCF_DSPI_DIRSR (*(volatile uint32_t*)(&_MBAR[0x8A30])) +#define MCF_DSPI_DTFR (*(volatile uint32_t*)(&_MBAR[0x8A34])) +#define MCF_DSPI_DRFR (*(volatile uint32_t*)(&_MBAR[0x8A38])) +#define MCF_DSPI_DTFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A3C])) +#define MCF_DSPI_DTFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A40])) +#define MCF_DSPI_DTFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A44])) +#define MCF_DSPI_DTFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A48])) +#define MCF_DSPI_DRFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A7C])) +#define MCF_DSPI_DRFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A80])) +#define MCF_DSPI_DRFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A84])) +#define MCF_DSPI_DRFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A88])) +#define MCF_DSPI_DCTAR(x) (*(volatile uint32_t*)(&_MBAR[0x8A0C + ((x)*0x4)])) +#define MCF_DSPI_DTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A3C + ((x)*0x4)])) +#define MCF_DSPI_DRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A7C + ((x)*0x4)])) + + +/* Bit definitions and macros for MCF_DSPI_DMCR */ +#define MCF_DSPI_DMCR_HALT (0x1) +#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x3)<<0x8) +#define MCF_DSPI_DMCR_SMPL_PT_0CLK (0) +#define MCF_DSPI_DMCR_SMPL_PT_1CLK (0x100) +#define MCF_DSPI_DMCR_SMPL_PT_2CLK (0x200) +#define MCF_DSPI_DMCR_CRXF (0x400) +#define MCF_DSPI_DMCR_CTXF (0x800) +#define MCF_DSPI_DMCR_DRXF (0x1000) +#define MCF_DSPI_DMCR_DTXF (0x2000) +#define MCF_DSPI_DMCR_CSIS0 (0x10000) +#define MCF_DSPI_DMCR_CSIS2 (0x40000) +#define MCF_DSPI_DMCR_CSIS3 (0x80000) +#define MCF_DSPI_DMCR_CSIS5 (0x200000) +#define MCF_DSPI_DMCR_ROOE (0x1000000) +#define MCF_DSPI_DMCR_PCSSE (0x2000000) +#define MCF_DSPI_DMCR_MTFE (0x4000000) +#define MCF_DSPI_DMCR_FRZ (0x8000000) +#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x3)<<0x1C) +#define MCF_DSPI_DMCR_CSCK (0x40000000) +#define MCF_DSPI_DMCR_MSTR (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DTCR */ +#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_DSPI_DCTAR */ +#define MCF_DSPI_DCTAR_BR(x) (((x)&0xF)<<0) +#define MCF_DSPI_DCTAR_DT(x) (((x)&0xF)<<0x4) +#define MCF_DSPI_DCTAR_ASC(x) (((x)&0xF)<<0x8) +#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0xF)<<0xC) +#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x3)<<0x10) +#define MCF_DSPI_DCTAR_PBR_1CLK (0) +#define MCF_DSPI_DCTAR_PBR_3CLK (0x10000) +#define MCF_DSPI_DCTAR_PBR_5CLK (0x20000) +#define MCF_DSPI_DCTAR_PBR_7CLK (0x30000) +#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x3)<<0x12) +#define MCF_DSPI_DCTAR_PDT_1CLK (0) +#define MCF_DSPI_DCTAR_PDT_3CLK (0x40000) +#define MCF_DSPI_DCTAR_PDT_5CLK (0x80000) +#define MCF_DSPI_DCTAR_PDT_7CLK (0xC0000) +#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x3)<<0x14) +#define MCF_DSPI_DCTAR_PASC_1CLK (0) +#define MCF_DSPI_DCTAR_PASC_3CLK (0x100000) +#define MCF_DSPI_DCTAR_PASC_5CLK (0x200000) +#define MCF_DSPI_DCTAR_PASC_7CLK (0x300000) +#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x3)<<0x16) +#define MCF_DSPI_DCTAR_LSBFE (0x1000000) +#define MCF_DSPI_DCTAR_CPHA (0x2000000) +#define MCF_DSPI_DCTAR_CPOL (0x4000000) +#define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0xF)<<0x1B) + +/* Bit definitions and macros for MCF_DSPI_DSR */ +#define MCF_DSPI_DSR_RXPTR(x) (((x)&0xF)<<0) +#define MCF_DSPI_DSR_RXCTR(x) (((x)&0xF)<<0x4) +#define MCF_DSPI_DSR_TXPTR(x) (((x)&0xF)<<0x8) +#define MCF_DSPI_DSR_TXCTR(x) (((x)&0xF)<<0xC) +#define MCF_DSPI_DSR_RFDF (0x20000) +#define MCF_DSPI_DSR_RFOF (0x80000) +#define MCF_DSPI_DSR_TFFF (0x2000000) +#define MCF_DSPI_DSR_TFUF (0x8000000) +#define MCF_DSPI_DSR_EOQF (0x10000000) +#define MCF_DSPI_DSR_TXRXS (0x40000000) +#define MCF_DSPI_DSR_TCF (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DIRSR */ +#define MCF_DSPI_DIRSR_RFDFS (0x10000) +#define MCF_DSPI_DIRSR_RFDFE (0x20000) +#define MCF_DSPI_DIRSR_RFOFE (0x80000) +#define MCF_DSPI_DIRSR_TFFFS (0x1000000) +#define MCF_DSPI_DIRSR_TFFFE (0x2000000) +#define MCF_DSPI_DIRSR_TFUFE (0x8000000) +#define MCF_DSPI_DIRSR_EOQFE (0x10000000) +#define MCF_DSPI_DIRSR_TCFE (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DTFR */ +#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0xFFFF)<<0) +#define MCF_DSPI_DTFR_CS0 (0x10000) +#define MCF_DSPI_DTFR_CS2 (0x40000) +#define MCF_DSPI_DTFR_CS3 (0x80000) +#define MCF_DSPI_DTFR_CS5 (0x200000) +#define MCF_DSPI_DTFR_CTCNT (0x4000000) +#define MCF_DSPI_DTFR_EOQ (0x8000000) +#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x7)<<0x1C) +#define MCF_DSPI_DTFR_CONT (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DRFR */ +#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_DSPI_DTFDR */ +#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0xFFFF)<<0) +#define MCF_DSPI_DTFDR_TXCMD(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_DSPI_DRFDR */ +#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0xFFFF)<<0) + + +#endif /* __MCF5475_DSPI_H__ */ diff --git a/tos/pci_test/include/MCF5475_EPORT.h b/tos/pci_test/include/MCF5475_EPORT.h new file mode 100644 index 0000000..6506196 --- /dev/null +++ b/tos/pci_test/include/MCF5475_EPORT.h @@ -0,0 +1,123 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_EPORT_H__ +#define __MCF5475_EPORT_H__ + + +/********************************************************************* +* +* Edge Port Module (EPORT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_EPORT_EPPAR (*(volatile uint16_t*)(&_MBAR[0xF00])) +#define MCF_EPORT_EPDDR (*(volatile uint8_t *)(&_MBAR[0xF04])) +#define MCF_EPORT_EPIER (*(volatile uint8_t *)(&_MBAR[0xF05])) +#define MCF_EPORT_EPDR (*(volatile uint8_t *)(&_MBAR[0xF08])) +#define MCF_EPORT_EPPDR (*(volatile uint8_t *)(&_MBAR[0xF09])) +#define MCF_EPORT_EPFR (*(volatile uint8_t *)(&_MBAR[0xF0C])) + + + +/* Bit definitions and macros for MCF_EPORT_EPPAR */ +#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2) +#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4) +#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8) +#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC) +#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4) +#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10) +#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20) +#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30) +#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6) +#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40) +#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80) +#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0) +#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8) +#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100) +#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200) +#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300) +#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA) +#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400) +#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800) +#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00) +#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC) +#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) +#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) +#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) +#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE) +#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) +#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) +#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) +#define MCF_EPORT_EPPAR_LEVEL (0) +#define MCF_EPORT_EPPAR_RISING (0x1) +#define MCF_EPORT_EPPAR_FALLING (0x2) +#define MCF_EPORT_EPPAR_BOTH (0x3) + +/* Bit definitions and macros for MCF_EPORT_EPDDR */ +#define MCF_EPORT_EPDDR_EPDD1 (0x2) +#define MCF_EPORT_EPDDR_EPDD2 (0x4) +#define MCF_EPORT_EPDDR_EPDD3 (0x8) +#define MCF_EPORT_EPDDR_EPDD4 (0x10) +#define MCF_EPORT_EPDDR_EPDD5 (0x20) +#define MCF_EPORT_EPDDR_EPDD6 (0x40) +#define MCF_EPORT_EPDDR_EPDD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPIER */ +#define MCF_EPORT_EPIER_EPIE1 (0x2) +#define MCF_EPORT_EPIER_EPIE2 (0x4) +#define MCF_EPORT_EPIER_EPIE3 (0x8) +#define MCF_EPORT_EPIER_EPIE4 (0x10) +#define MCF_EPORT_EPIER_EPIE5 (0x20) +#define MCF_EPORT_EPIER_EPIE6 (0x40) +#define MCF_EPORT_EPIER_EPIE7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPDR */ +#define MCF_EPORT_EPDR_EPD1 (0x2) +#define MCF_EPORT_EPDR_EPD2 (0x4) +#define MCF_EPORT_EPDR_EPD3 (0x8) +#define MCF_EPORT_EPDR_EPD4 (0x10) +#define MCF_EPORT_EPDR_EPD5 (0x20) +#define MCF_EPORT_EPDR_EPD6 (0x40) +#define MCF_EPORT_EPDR_EPD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPPDR */ +#define MCF_EPORT_EPPDR_EPPD1 (0x2) +#define MCF_EPORT_EPPDR_EPPD2 (0x4) +#define MCF_EPORT_EPPDR_EPPD3 (0x8) +#define MCF_EPORT_EPPDR_EPPD4 (0x10) +#define MCF_EPORT_EPPDR_EPPD5 (0x20) +#define MCF_EPORT_EPPDR_EPPD6 (0x40) +#define MCF_EPORT_EPPDR_EPPD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPFR */ +#define MCF_EPORT_EPFR_EPF1 (0x2) +#define MCF_EPORT_EPFR_EPF2 (0x4) +#define MCF_EPORT_EPFR_EPF3 (0x8) +#define MCF_EPORT_EPFR_EPF4 (0x10) +#define MCF_EPORT_EPFR_EPF5 (0x20) +#define MCF_EPORT_EPFR_EPF6 (0x40) +#define MCF_EPORT_EPFR_EPF7 (0x80) + + +#endif /* __MCF5475_EPORT_H__ */ diff --git a/tos/pci_test/include/MCF5475_FBCS.h b/tos/pci_test/include/MCF5475_FBCS.h new file mode 100644 index 0000000..37daf00 --- /dev/null +++ b/tos/pci_test/include/MCF5475_FBCS.h @@ -0,0 +1,100 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_FBCS_H__ +#define __MCF5475_FBCS_H__ + + +/********************************************************************* +* +* FlexBus Chip Select Module (FBCS) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_FBCS0_CSAR (*(volatile uint32_t*)(&_MBAR[0x500])) +#define MCF_FBCS0_CSMR (*(volatile uint32_t*)(&_MBAR[0x504])) +#define MCF_FBCS0_CSCR (*(volatile uint32_t*)(&_MBAR[0x508])) + +#define MCF_FBCS1_CSAR (*(volatile uint32_t*)(&_MBAR[0x50C])) +#define MCF_FBCS1_CSMR (*(volatile uint32_t*)(&_MBAR[0x510])) +#define MCF_FBCS1_CSCR (*(volatile uint32_t*)(&_MBAR[0x514])) + +#define MCF_FBCS2_CSAR (*(volatile uint32_t*)(&_MBAR[0x518])) +#define MCF_FBCS2_CSMR (*(volatile uint32_t*)(&_MBAR[0x51C])) +#define MCF_FBCS2_CSCR (*(volatile uint32_t*)(&_MBAR[0x520])) + +#define MCF_FBCS3_CSAR (*(volatile uint32_t*)(&_MBAR[0x524])) +#define MCF_FBCS3_CSMR (*(volatile uint32_t*)(&_MBAR[0x528])) +#define MCF_FBCS3_CSCR (*(volatile uint32_t*)(&_MBAR[0x52C])) + +#define MCF_FBCS4_CSAR (*(volatile uint32_t*)(&_MBAR[0x530])) +#define MCF_FBCS4_CSMR (*(volatile uint32_t*)(&_MBAR[0x534])) +#define MCF_FBCS4_CSCR (*(volatile uint32_t*)(&_MBAR[0x538])) + +#define MCF_FBCS5_CSAR (*(volatile uint32_t*)(&_MBAR[0x53C])) +#define MCF_FBCS5_CSMR (*(volatile uint32_t*)(&_MBAR[0x540])) +#define MCF_FBCS5_CSCR (*(volatile uint32_t*)(&_MBAR[0x544])) + +#define MCF_FBCS_CSAR(x) (*(volatile uint32_t*)(&_MBAR[0x500 + ((x)*0xC)])) +#define MCF_FBCS_CSMR(x) (*(volatile uint32_t*)(&_MBAR[0x504 + ((x)*0xC)])) +#define MCF_FBCS_CSCR(x) (*(volatile uint32_t*)(&_MBAR[0x508 + ((x)*0xC)])) + + +/* Bit definitions and macros for MCF_FBCS_CSAR */ +#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) + +/* Bit definitions and macros for MCF_FBCS_CSMR */ +#define MCF_FBCS_CSMR_V (0x1) +#define MCF_FBCS_CSMR_WP (0x100) +#define MCF_FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<0x10) +#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) +#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) +#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) +#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) +#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) +#define MCF_FBCS_CSMR_BAM_256M (0xFFF0000) +#define MCF_FBCS_CSMR_BAM_128M (0x7FF0000) +#define MCF_FBCS_CSMR_BAM_64M (0x3FF0000) +#define MCF_FBCS_CSMR_BAM_32M (0x1FF0000) +#define MCF_FBCS_CSMR_BAM_16M (0xFF0000) +#define MCF_FBCS_CSMR_BAM_8M (0x7F0000) +#define MCF_FBCS_CSMR_BAM_4M (0x3F0000) +#define MCF_FBCS_CSMR_BAM_2M (0x1F0000) +#define MCF_FBCS_CSMR_BAM_1M (0xF0000) +#define MCF_FBCS_CSMR_BAM_1024K (0xF0000) +#define MCF_FBCS_CSMR_BAM_512K (0x70000) +#define MCF_FBCS_CSMR_BAM_256K (0x30000) +#define MCF_FBCS_CSMR_BAM_128K (0x10000) +#define MCF_FBCS_CSMR_BAM_64K (0) + +/* Bit definitions and macros for MCF_FBCS_CSCR */ +#define MCF_FBCS_CSCR_BSTW (0x8) +#define MCF_FBCS_CSCR_BSTR (0x10) +#define MCF_FBCS_CSCR_BEM (0x20) +#define MCF_FBCS_CSCR_PS(x) (((x)&0x3)<<0x6) +#define MCF_FBCS_CSCR_PS_32 (0) +#define MCF_FBCS_CSCR_PS_8 (0x40) +#define MCF_FBCS_CSCR_PS_16 (0x80) +#define MCF_FBCS_CSCR_AA (0x100) +#define MCF_FBCS_CSCR_WS(x) (((x)&0x3F)<<0xA) +#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x3)<<0x10) +#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x3)<<0x12) +#define MCF_FBCS_CSCR_ASET(x) (((x)&0x3)<<0x14) +#define MCF_FBCS_CSCR_SWSEN (0x800000) +#define MCF_FBCS_CSCR_SWS(x) (((x)&0x3F)<<0x1A) + + +#endif /* __MCF5475_FBCS_H__ */ diff --git a/tos/pci_test/include/MCF5475_FEC.h b/tos/pci_test/include/MCF5475_FEC.h new file mode 100644 index 0000000..fdd9403 --- /dev/null +++ b/tos/pci_test/include/MCF5475_FEC.h @@ -0,0 +1,680 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_FEC_H__ +#define __MCF5475_FEC_H__ + + +/********************************************************************* +* +* Fast Ethernet Controller(FEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_FEC0_EIR (*(volatile uint32_t*)(&_MBAR[0x9004])) +#define MCF_FEC0_EIMR (*(volatile uint32_t*)(&_MBAR[0x9008])) +#define MCF_FEC0_ECR (*(volatile uint32_t*)(&_MBAR[0x9024])) +#define MCF_FEC0_MMFR (*(volatile uint32_t*)(&_MBAR[0x9040])) +#define MCF_FEC0_MSCR (*(volatile uint32_t*)(&_MBAR[0x9044])) +#define MCF_FEC0_MIBC (*(volatile uint32_t*)(&_MBAR[0x9064])) +#define MCF_FEC0_RCR (*(volatile uint32_t*)(&_MBAR[0x9084])) +#define MCF_FEC0_RHR (*(volatile uint32_t*)(&_MBAR[0x9088])) +#define MCF_FEC0_TCR (*(volatile uint32_t*)(&_MBAR[0x90C4])) +#define MCF_FEC0_PALR (*(volatile uint32_t*)(&_MBAR[0x90E4])) +#define MCF_FEC0_PAHR (*(volatile uint32_t*)(&_MBAR[0x90E8])) +#define MCF_FEC0_OPD (*(volatile uint32_t*)(&_MBAR[0x90EC])) +#define MCF_FEC0_IAUR (*(volatile uint32_t*)(&_MBAR[0x9118])) +#define MCF_FEC0_IALR (*(volatile uint32_t*)(&_MBAR[0x911C])) +#define MCF_FEC0_GAUR (*(volatile uint32_t*)(&_MBAR[0x9120])) +#define MCF_FEC0_GALR (*(volatile uint32_t*)(&_MBAR[0x9124])) +#define MCF_FEC0_FECTFWR (*(volatile uint32_t*)(&_MBAR[0x9144])) +#define MCF_FEC0_FECRFDR (*(volatile uint32_t*)(&_MBAR[0x9184])) +#define MCF_FEC0_FECRFSR (*(volatile uint32_t*)(&_MBAR[0x9188])) +#define MCF_FEC0_FECRFCR (*(volatile uint32_t*)(&_MBAR[0x918C])) +#define MCF_FEC0_FECRLRFP (*(volatile uint32_t*)(&_MBAR[0x9190])) +#define MCF_FEC0_FECRLWFP (*(volatile uint32_t*)(&_MBAR[0x9194])) +#define MCF_FEC0_FECRFAR (*(volatile uint32_t*)(&_MBAR[0x9198])) +#define MCF_FEC0_FECRFRP (*(volatile uint32_t*)(&_MBAR[0x919C])) +#define MCF_FEC0_FECRFWP (*(volatile uint32_t*)(&_MBAR[0x91A0])) +#define MCF_FEC0_FECTFDR (*(volatile uint32_t*)(&_MBAR[0x91A4])) +#define MCF_FEC0_FECTFSR (*(volatile uint32_t*)(&_MBAR[0x91A8])) +#define MCF_FEC0_FECTFCR (*(volatile uint32_t*)(&_MBAR[0x91AC])) +#define MCF_FEC0_FECTLRFP (*(volatile uint32_t*)(&_MBAR[0x91B0])) +#define MCF_FEC0_FECTLWFP (*(volatile uint32_t*)(&_MBAR[0x91B4])) +#define MCF_FEC0_FECTFAR (*(volatile uint32_t*)(&_MBAR[0x91B8])) +#define MCF_FEC0_FECTFRP (*(volatile uint32_t*)(&_MBAR[0x91BC])) +#define MCF_FEC0_FECTFWP (*(volatile uint32_t*)(&_MBAR[0x91C0])) +#define MCF_FEC0_FECFRST (*(volatile uint32_t*)(&_MBAR[0x91C4])) +#define MCF_FEC0_FECCTCWR (*(volatile uint32_t*)(&_MBAR[0x91C8])) +#define MCF_FEC0_RMON_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9200])) +#define MCF_FEC0_RMON_T_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9204])) +#define MCF_FEC0_RMON_T_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9208])) +#define MCF_FEC0_RMON_T_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x920C])) +#define MCF_FEC0_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9210])) +#define MCF_FEC0_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9214])) +#define MCF_FEC0_RMON_T_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9218])) +#define MCF_FEC0_RMON_T_FRAG (*(volatile uint32_t*)(&_MBAR[0x921C])) +#define MCF_FEC0_RMON_T_JAB (*(volatile uint32_t*)(&_MBAR[0x9220])) +#define MCF_FEC0_RMON_T_COL (*(volatile uint32_t*)(&_MBAR[0x9224])) +#define MCF_FEC0_RMON_T_P64 (*(volatile uint32_t*)(&_MBAR[0x9228])) +#define MCF_FEC0_RMON_T_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x922C])) +#define MCF_FEC0_RMON_T_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9230])) +#define MCF_FEC0_RMON_T_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9234])) +#define MCF_FEC0_RMON_T_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9238])) +#define MCF_FEC0_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x923C])) +#define MCF_FEC0_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9240])) +#define MCF_FEC0_RMON_T_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9244])) +#define MCF_FEC0_IEEE_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9248])) +#define MCF_FEC0_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x924C])) +#define MCF_FEC0_IEEE_T_1COL (*(volatile uint32_t*)(&_MBAR[0x9250])) +#define MCF_FEC0_IEEE_T_MCOL (*(volatile uint32_t*)(&_MBAR[0x9254])) +#define MCF_FEC0_IEEE_T_DEF (*(volatile uint32_t*)(&_MBAR[0x9258])) +#define MCF_FEC0_IEEE_T_LCOL (*(volatile uint32_t*)(&_MBAR[0x925C])) +#define MCF_FEC0_IEEE_T_EXCOL (*(volatile uint32_t*)(&_MBAR[0x9260])) +#define MCF_FEC0_IEEE_T_MACERR (*(volatile uint32_t*)(&_MBAR[0x9264])) +#define MCF_FEC0_IEEE_T_CSERR (*(volatile uint32_t*)(&_MBAR[0x9268])) +#define MCF_FEC0_IEEE_T_SQE (*(volatile uint32_t*)(&_MBAR[0x926C])) +#define MCF_FEC0_IEEE_T_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9270])) +#define MCF_FEC0_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9274])) +#define MCF_FEC0_RMON_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9280])) +#define MCF_FEC0_RMON_R_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9284])) +#define MCF_FEC0_RMON_R_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9288])) +#define MCF_FEC0_RMON_R_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x928C])) +#define MCF_FEC0_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9290])) +#define MCF_FEC0_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9294])) +#define MCF_FEC0_RMON_R_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9298])) +#define MCF_FEC0_RMON_R_FRAG (*(volatile uint32_t*)(&_MBAR[0x929C])) +#define MCF_FEC0_RMON_R_JAB (*(volatile uint32_t*)(&_MBAR[0x92A0])) +#define MCF_FEC0_RMON_R_RESVD_0 (*(volatile uint32_t*)(&_MBAR[0x92A4])) +#define MCF_FEC0_RMON_R_P64 (*(volatile uint32_t*)(&_MBAR[0x92A8])) +#define MCF_FEC0_RMON_R_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x92AC])) +#define MCF_FEC0_RMON_R_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x92B0])) +#define MCF_FEC0_RMON_R_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x92B4])) +#define MCF_FEC0_RMON_R_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x92B8])) +#define MCF_FEC0_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x92BC])) +#define MCF_FEC0_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x92C0])) +#define MCF_FEC0_RMON_R_OCTETS (*(volatile uint32_t*)(&_MBAR[0x92C4])) +#define MCF_FEC0_IEEE_R_DROP (*(volatile uint32_t*)(&_MBAR[0x92C8])) +#define MCF_FEC0_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x92CC])) +#define MCF_FEC0_IEEE_R_CRC (*(volatile uint32_t*)(&_MBAR[0x92D0])) +#define MCF_FEC0_IEEE_R_ALIGN (*(volatile uint32_t*)(&_MBAR[0x92D4])) +#define MCF_FEC0_IEEE_R_MACERR (*(volatile uint32_t*)(&_MBAR[0x92D8])) +#define MCF_FEC0_IEEE_R_FDXFC (*(volatile uint32_t*)(&_MBAR[0x92DC])) +#define MCF_FEC0_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x92E0])) + +#define MCF_FEC1_EIR (*(volatile uint32_t*)(&_MBAR[0x9804])) +#define MCF_FEC1_EIMR (*(volatile uint32_t*)(&_MBAR[0x9808])) +#define MCF_FEC1_ECR (*(volatile uint32_t*)(&_MBAR[0x9824])) +#define MCF_FEC1_MMFR (*(volatile uint32_t*)(&_MBAR[0x9840])) +#define MCF_FEC1_MSCR (*(volatile uint32_t*)(&_MBAR[0x9844])) +#define MCF_FEC1_MIBC (*(volatile uint32_t*)(&_MBAR[0x9864])) +#define MCF_FEC1_RCR (*(volatile uint32_t*)(&_MBAR[0x9884])) +#define MCF_FEC1_RHR (*(volatile uint32_t*)(&_MBAR[0x9888])) +#define MCF_FEC1_TCR (*(volatile uint32_t*)(&_MBAR[0x98C4])) +#define MCF_FEC1_PALR (*(volatile uint32_t*)(&_MBAR[0x98E4])) +#define MCF_FEC1_PAHR (*(volatile uint32_t*)(&_MBAR[0x98E8])) +#define MCF_FEC1_OPD (*(volatile uint32_t*)(&_MBAR[0x98EC])) +#define MCF_FEC1_IAUR (*(volatile uint32_t*)(&_MBAR[0x9918])) +#define MCF_FEC1_IALR (*(volatile uint32_t*)(&_MBAR[0x991C])) +#define MCF_FEC1_GAUR (*(volatile uint32_t*)(&_MBAR[0x9920])) +#define MCF_FEC1_GALR (*(volatile uint32_t*)(&_MBAR[0x9924])) +#define MCF_FEC1_FECTFWR (*(volatile uint32_t*)(&_MBAR[0x9944])) +#define MCF_FEC1_FECRFDR (*(volatile uint32_t*)(&_MBAR[0x9984])) +#define MCF_FEC1_FECRFSR (*(volatile uint32_t*)(&_MBAR[0x9988])) +#define MCF_FEC1_FECRFCR (*(volatile uint32_t*)(&_MBAR[0x998C])) +#define MCF_FEC1_FECRLRFP (*(volatile uint32_t*)(&_MBAR[0x9990])) +#define MCF_FEC1_FECRLWFP (*(volatile uint32_t*)(&_MBAR[0x9994])) +#define MCF_FEC1_FECRFAR (*(volatile uint32_t*)(&_MBAR[0x9998])) +#define MCF_FEC1_FECRFRP (*(volatile uint32_t*)(&_MBAR[0x999C])) +#define MCF_FEC1_FECRFWP (*(volatile uint32_t*)(&_MBAR[0x99A0])) +#define MCF_FEC1_FECTFDR (*(volatile uint32_t*)(&_MBAR[0x99A4])) +#define MCF_FEC1_FECTFSR (*(volatile uint32_t*)(&_MBAR[0x99A8])) +#define MCF_FEC1_FECTFCR (*(volatile uint32_t*)(&_MBAR[0x99AC])) +#define MCF_FEC1_FECTLRFP (*(volatile uint32_t*)(&_MBAR[0x99B0])) +#define MCF_FEC1_FECTLWFP (*(volatile uint32_t*)(&_MBAR[0x99B4])) +#define MCF_FEC1_FECTFAR (*(volatile uint32_t*)(&_MBAR[0x99B8])) +#define MCF_FEC1_FECTFRP (*(volatile uint32_t*)(&_MBAR[0x99BC])) +#define MCF_FEC1_FECTFWP (*(volatile uint32_t*)(&_MBAR[0x99C0])) +#define MCF_FEC1_FECFRST (*(volatile uint32_t*)(&_MBAR[0x99C4])) +#define MCF_FEC1_FECCTCWR (*(volatile uint32_t*)(&_MBAR[0x99C8])) +#define MCF_FEC1_RMON_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9A00])) +#define MCF_FEC1_RMON_T_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9A04])) +#define MCF_FEC1_RMON_T_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A08])) +#define MCF_FEC1_RMON_T_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A0C])) +#define MCF_FEC1_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9A10])) +#define MCF_FEC1_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A14])) +#define MCF_FEC1_RMON_T_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A18])) +#define MCF_FEC1_RMON_T_FRAG (*(volatile uint32_t*)(&_MBAR[0x9A1C])) +#define MCF_FEC1_RMON_T_JAB (*(volatile uint32_t*)(&_MBAR[0x9A20])) +#define MCF_FEC1_RMON_T_COL (*(volatile uint32_t*)(&_MBAR[0x9A24])) +#define MCF_FEC1_RMON_T_P64 (*(volatile uint32_t*)(&_MBAR[0x9A28])) +#define MCF_FEC1_RMON_T_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x9A2C])) +#define MCF_FEC1_RMON_T_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9A30])) +#define MCF_FEC1_RMON_T_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9A34])) +#define MCF_FEC1_RMON_T_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9A38])) +#define MCF_FEC1_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x9A3C])) +#define MCF_FEC1_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9A40])) +#define MCF_FEC1_RMON_T_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9A44])) +#define MCF_FEC1_IEEE_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9A48])) +#define MCF_FEC1_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x9A4C])) +#define MCF_FEC1_IEEE_T_1COL (*(volatile uint32_t*)(&_MBAR[0x9A50])) +#define MCF_FEC1_IEEE_T_MCOL (*(volatile uint32_t*)(&_MBAR[0x9A54])) +#define MCF_FEC1_IEEE_T_DEF (*(volatile uint32_t*)(&_MBAR[0x9A58])) +#define MCF_FEC1_IEEE_T_LCOL (*(volatile uint32_t*)(&_MBAR[0x9A5C])) +#define MCF_FEC1_IEEE_T_EXCOL (*(volatile uint32_t*)(&_MBAR[0x9A60])) +#define MCF_FEC1_IEEE_T_MACERR (*(volatile uint32_t*)(&_MBAR[0x9A64])) +#define MCF_FEC1_IEEE_T_CSERR (*(volatile uint32_t*)(&_MBAR[0x9A68])) +#define MCF_FEC1_IEEE_T_SQE (*(volatile uint32_t*)(&_MBAR[0x9A6C])) +#define MCF_FEC1_IEEE_T_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9A70])) +#define MCF_FEC1_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9A74])) +#define MCF_FEC1_RMON_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9A80])) +#define MCF_FEC1_RMON_R_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9A84])) +#define MCF_FEC1_RMON_R_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A88])) +#define MCF_FEC1_RMON_R_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A8C])) +#define MCF_FEC1_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9A90])) +#define MCF_FEC1_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A94])) +#define MCF_FEC1_RMON_R_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A98])) +#define MCF_FEC1_RMON_R_FRAG (*(volatile uint32_t*)(&_MBAR[0x9A9C])) +#define MCF_FEC1_RMON_R_JAB (*(volatile uint32_t*)(&_MBAR[0x9AA0])) +#define MCF_FEC1_RMON_R_RESVD_0 (*(volatile uint32_t*)(&_MBAR[0x9AA4])) +#define MCF_FEC1_RMON_R_P64 (*(volatile uint32_t*)(&_MBAR[0x9AA8])) +#define MCF_FEC1_RMON_R_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x9AAC])) +#define MCF_FEC1_RMON_R_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9AB0])) +#define MCF_FEC1_RMON_R_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9AB4])) +#define MCF_FEC1_RMON_R_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9AB8])) +#define MCF_FEC1_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x9ABC])) +#define MCF_FEC1_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9AC0])) +#define MCF_FEC1_RMON_R_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9AC4])) +#define MCF_FEC1_IEEE_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9AC8])) +#define MCF_FEC1_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x9ACC])) +#define MCF_FEC1_IEEE_R_CRC (*(volatile uint32_t*)(&_MBAR[0x9AD0])) +#define MCF_FEC1_IEEE_R_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9AD4])) +#define MCF_FEC1_IEEE_R_MACERR (*(volatile uint32_t*)(&_MBAR[0x9AD8])) +#define MCF_FEC1_IEEE_R_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9ADC])) +#define MCF_FEC1_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9AE0])) + +#define MCF_FEC_EIR(x) (*(volatile uint32_t*)(&_MBAR[0x9004 + ((x)*0x800)])) +#define MCF_FEC_EIMR(x) (*(volatile uint32_t*)(&_MBAR[0x9008 + ((x)*0x800)])) +#define MCF_FEC_ECR(x) (*(volatile uint32_t*)(&_MBAR[0x9024 + ((x)*0x800)])) +#define MCF_FEC_MMFR(x) (*(volatile uint32_t*)(&_MBAR[0x9040 + ((x)*0x800)])) +#define MCF_FEC_MSCR(x) (*(volatile uint32_t*)(&_MBAR[0x9044 + ((x)*0x800)])) +#define MCF_FEC_MIBC(x) (*(volatile uint32_t*)(&_MBAR[0x9064 + ((x)*0x800)])) +#define MCF_FEC_RCR(x) (*(volatile uint32_t*)(&_MBAR[0x9084 + ((x)*0x800)])) +#define MCF_FEC_RHR(x) (*(volatile uint32_t*)(&_MBAR[0x9088 + ((x)*0x800)])) +#define MCF_FEC_TCR(x) (*(volatile uint32_t*)(&_MBAR[0x90C4 + ((x)*0x800)])) +#define MCF_FEC_PALR(x) (*(volatile uint32_t*)(&_MBAR[0x90E4 + ((x)*0x800)])) +#define MCF_FEC_PAHR(x) (*(volatile uint32_t*)(&_MBAR[0x90E8 + ((x)*0x800)])) +#define MCF_FEC_OPD(x) (*(volatile uint32_t*)(&_MBAR[0x90EC + ((x)*0x800)])) +#define MCF_FEC_IAUR(x) (*(volatile uint32_t*)(&_MBAR[0x9118 + ((x)*0x800)])) +#define MCF_FEC_IALR(x) (*(volatile uint32_t*)(&_MBAR[0x911C + ((x)*0x800)])) +#define MCF_FEC_GAUR(x) (*(volatile uint32_t*)(&_MBAR[0x9120 + ((x)*0x800)])) +#define MCF_FEC_GALR(x) (*(volatile uint32_t*)(&_MBAR[0x9124 + ((x)*0x800)])) +#define MCF_FEC_FECTFWR(x) (*(volatile uint32_t*)(&_MBAR[0x9144 + ((x)*0x800)])) +#define MCF_FEC_FECRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x9184 + ((x)*0x800)])) +#define MCF_FEC_FECRFSR(x) (*(volatile uint32_t*)(&_MBAR[0x9188 + ((x)*0x800)])) +#define MCF_FEC_FECRFCR(x) (*(volatile uint32_t*)(&_MBAR[0x918C + ((x)*0x800)])) +#define MCF_FEC_FECRLRFP(x) (*(volatile uint32_t*)(&_MBAR[0x9190 + ((x)*0x800)])) +#define MCF_FEC_FECRLWFP(x) (*(volatile uint32_t*)(&_MBAR[0x9194 + ((x)*0x800)])) +#define MCF_FEC_FECRFAR(x) (*(volatile uint32_t*)(&_MBAR[0x9198 + ((x)*0x800)])) +#define MCF_FEC_FECRFRP(x) (*(volatile uint32_t*)(&_MBAR[0x919C + ((x)*0x800)])) +#define MCF_FEC_FECRFWP(x) (*(volatile uint32_t*)(&_MBAR[0x91A0 + ((x)*0x800)])) +#define MCF_FEC_FECTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x91A4 + ((x)*0x800)])) +#define MCF_FEC_FECTFSR(x) (*(volatile uint32_t*)(&_MBAR[0x91A8 + ((x)*0x800)])) +#define MCF_FEC_FECTFCR(x) (*(volatile uint32_t*)(&_MBAR[0x91AC + ((x)*0x800)])) +#define MCF_FEC_FECTLRFP(x) (*(volatile uint32_t*)(&_MBAR[0x91B0 + ((x)*0x800)])) +#define MCF_FEC_FECTLWFP(x) (*(volatile uint32_t*)(&_MBAR[0x91B4 + ((x)*0x800)])) +#define MCF_FEC_FECTFAR(x) (*(volatile uint32_t*)(&_MBAR[0x91B8 + ((x)*0x800)])) +#define MCF_FEC_FECTFRP(x) (*(volatile uint32_t*)(&_MBAR[0x91BC + ((x)*0x800)])) +#define MCF_FEC_FECTFWP(x) (*(volatile uint32_t*)(&_MBAR[0x91C0 + ((x)*0x800)])) +#define MCF_FEC_FECFRST(x) (*(volatile uint32_t*)(&_MBAR[0x91C4 + ((x)*0x800)])) +#define MCF_FEC_FECCTCWR(x) (*(volatile uint32_t*)(&_MBAR[0x91C8 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9200 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_PACKETS(x) (*(volatile uint32_t*)(&_MBAR[0x9204 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_BC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x9208 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_MC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x920C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x9210 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9214 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_OVERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9218 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_FRAG(x) (*(volatile uint32_t*)(&_MBAR[0x921C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_JAB(x) (*(volatile uint32_t*)(&_MBAR[0x9220 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_COL(x) (*(volatile uint32_t*)(&_MBAR[0x9224 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P64(x) (*(volatile uint32_t*)(&_MBAR[0x9228 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P65TO127(x) (*(volatile uint32_t*)(&_MBAR[0x922C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P128TO255(x) (*(volatile uint32_t*)(&_MBAR[0x9230 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P256TO511(x) (*(volatile uint32_t*)(&_MBAR[0x9234 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P512TO1023(x) (*(volatile uint32_t*)(&_MBAR[0x9238 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P1024TO2047(x) (*(volatile uint32_t*)(&_MBAR[0x923C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P_GTE2048(x) (*(volatile uint32_t*)(&_MBAR[0x9240 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_OCTETS(x) (*(volatile uint32_t*)(&_MBAR[0x9244 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9248 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(volatile uint32_t*)(&_MBAR[0x924C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_1COL(x) (*(volatile uint32_t*)(&_MBAR[0x9250 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_MCOL(x) (*(volatile uint32_t*)(&_MBAR[0x9254 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_DEF(x) (*(volatile uint32_t*)(&_MBAR[0x9258 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_LCOL(x) (*(volatile uint32_t*)(&_MBAR[0x925C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_EXCOL(x) (*(volatile uint32_t*)(&_MBAR[0x9260 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_MACERR(x) (*(volatile uint32_t*)(&_MBAR[0x9264 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_CSERR(x) (*(volatile uint32_t*)(&_MBAR[0x9268 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_SQE(x) (*(volatile uint32_t*)(&_MBAR[0x926C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_FDXFC(x) (*(volatile uint32_t*)(&_MBAR[0x9270 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(volatile uint32_t*)(&_MBAR[0x9274 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9280 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_PACKETS(x) (*(volatile uint32_t*)(&_MBAR[0x9284 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_BC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x9288 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_MC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x928C + ((x)*0x800)])) +#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x9290 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9294 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_OVERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9298 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_FRAG(x) (*(volatile uint32_t*)(&_MBAR[0x929C + ((x)*0x800)])) +#define MCF_FEC_RMON_R_JAB(x) (*(volatile uint32_t*)(&_MBAR[0x92A0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_RESVD_0(x) (*(volatile uint32_t*)(&_MBAR[0x92A4 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P64(x) (*(volatile uint32_t*)(&_MBAR[0x92A8 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P65TO127(x) (*(volatile uint32_t*)(&_MBAR[0x92AC + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P128TO255(x) (*(volatile uint32_t*)(&_MBAR[0x92B0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P256TO511(x) (*(volatile uint32_t*)(&_MBAR[0x92B4 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P512TO1023(x) (*(volatile uint32_t*)(&_MBAR[0x92B8 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P1024TO2047(x) (*(volatile uint32_t*)(&_MBAR[0x92BC + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P_GTE2048(x) (*(volatile uint32_t*)(&_MBAR[0x92C0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_OCTETS(x) (*(volatile uint32_t*)(&_MBAR[0x92C4 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x92C8 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(volatile uint32_t*)(&_MBAR[0x92CC + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_CRC(x) (*(volatile uint32_t*)(&_MBAR[0x92D0 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x92D4 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_MACERR(x) (*(volatile uint32_t*)(&_MBAR[0x92D8 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_FDXFC(x) (*(volatile uint32_t*)(&_MBAR[0x92DC + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(volatile uint32_t*)(&_MBAR[0x92E0 + ((x)*0x800)])) + + +/* Bit definitions and macros for MCF_FEC_EIR */ +#define MCF_FEC_EIR_RFERR (0x20000) +#define MCF_FEC_EIR_XFERR (0x40000) +#define MCF_FEC_EIR_XFUN (0x80000) +#define MCF_FEC_EIR_RL (0x100000) +#define MCF_FEC_EIR_LC (0x200000) +#define MCF_FEC_EIR_MII (0x800000) +#define MCF_FEC_EIR_TXF (0x8000000) +#define MCF_FEC_EIR_GRA (0x10000000) +#define MCF_FEC_EIR_BABT (0x20000000) +#define MCF_FEC_EIR_BABR (0x40000000) +#define MCF_FEC_EIR_HBERR (0x80000000) +#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF_FEC_EIMR */ +#define MCF_FEC_EIMR_RFERR (0x20000) +#define MCF_FEC_EIMR_XFERR (0x40000) +#define MCF_FEC_EIMR_XFUN (0x80000) +#define MCF_FEC_EIMR_RL (0x100000) +#define MCF_FEC_EIMR_LC (0x200000) +#define MCF_FEC_EIMR_MII (0x800000) +#define MCF_FEC_EIMR_TXF (0x8000000) +#define MCF_FEC_EIMR_GRA (0x10000000) +#define MCF_FEC_EIMR_BABT (0x20000000) +#define MCF_FEC_EIMR_BABR (0x40000000) +#define MCF_FEC_EIMR_HBERR (0x80000000) +#define MCF_FEC_EIMR_MASK_ALL (0) +#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF_FEC_ECR */ +#define MCF_FEC_ECR_RESET (0x1) +#define MCF_FEC_ECR_ETHER_EN (0x2) + +/* Bit definitions and macros for MCF_FEC_MMFR */ +#define MCF_FEC_MMFR_DATA(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_MMFR_TA(x) (((x)&0x3)<<0x10) +#define MCF_FEC_MMFR_TA_10 (0x20000) +#define MCF_FEC_MMFR_RA(x) (((x)&0x1F)<<0x12) +#define MCF_FEC_MMFR_PA(x) (((x)&0x1F)<<0x17) +#define MCF_FEC_MMFR_OP(x) (((x)&0x3)<<0x1C) +#define MCF_FEC_MMFR_OP_READ (0x20000000) +#define MCF_FEC_MMFR_OP_WRITE (0x10000000) +#define MCF_FEC_MMFR_ST(x) (((x)&0x3)<<0x1E) +#define MCF_FEC_MMFR_ST_01 (0x40000000) + +/* Bit definitions and macros for MCF_FEC_MSCR */ +#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1) +#define MCF_FEC_MSCR_DIS_PREAMBLE (0x80) +#define MCF_FEC_MSCR_MII_SPEED_133 (0x1B<<0x1) +#define MCF_FEC_MSCR_MII_SPEED_120 (0x18<<0x1) +#define MCF_FEC_MSCR_MII_SPEED_66 (0xE<<0x1) +#define MCF_FEC_MSCR_MII_SPEED_60 (0xC<<0x1) + +/* Bit definitions and macros for MCF_FEC_MIBC */ +#define MCF_FEC_MIBC_MIB_IDLE (0x40000000) +#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000) + +/* Bit definitions and macros for MCF_FEC_RCR */ +#define MCF_FEC_RCR_LOOP (0x1) +#define MCF_FEC_RCR_DRT (0x2) +#define MCF_FEC_RCR_MII_MODE (0x4) +#define MCF_FEC_RCR_PROM (0x8) +#define MCF_FEC_RCR_BC_REJ (0x10) +#define MCF_FEC_RCR_FCE (0x20) +#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<0x10) + +/* Bit definitions and macros for MCF_FEC_RHR */ +#define MCF_FEC_RHR_HASH(x) (((x)&0x3F)<<0x18) +#define MCF_FEC_RHR_MULTCAST (0x40000000) +#define MCF_FEC_RHR_FCE (0x80000000) + +/* Bit definitions and macros for MCF_FEC_TCR */ +#define MCF_FEC_TCR_GTS (0x1) +#define MCF_FEC_TCR_HBC (0x2) +#define MCF_FEC_TCR_FDEN (0x4) +#define MCF_FEC_TCR_TFC_PAUSE (0x8) +#define MCF_FEC_TCR_RFC_PAUSE (0x10) + +/* Bit definitions and macros for MCF_FEC_PALR */ +#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_PAHR */ +#define MCF_FEC_PAHR_TYPE(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_PAHR_PADDR2(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_FEC_OPD */ +#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_OPD_OPCODE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_FEC_IAUR */ +#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IALR */ +#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_GAUR */ +#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_GALR */ +#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFWR */ +#define MCF_FEC_FECTFWR_X_WMRK(x) (((x)&0xF)<<0) +#define MCF_FEC_FECTFWR_X_WMRK_64 (0) +#define MCF_FEC_FECTFWR_X_WMRK_128 (0x1) +#define MCF_FEC_FECTFWR_X_WMRK_192 (0x2) +#define MCF_FEC_FECTFWR_X_WMRK_256 (0x3) +#define MCF_FEC_FECTFWR_X_WMRK_320 (0x4) +#define MCF_FEC_FECTFWR_X_WMRK_384 (0x5) +#define MCF_FEC_FECTFWR_X_WMRK_448 (0x6) +#define MCF_FEC_FECTFWR_X_WMRK_512 (0x7) +#define MCF_FEC_FECTFWR_X_WMRK_576 (0x8) +#define MCF_FEC_FECTFWR_X_WMRK_640 (0x9) +#define MCF_FEC_FECTFWR_X_WMRK_704 (0xA) +#define MCF_FEC_FECTFWR_X_WMRK_768 (0xB) +#define MCF_FEC_FECTFWR_X_WMRK_832 (0xC) +#define MCF_FEC_FECTFWR_X_WMRK_896 (0xD) +#define MCF_FEC_FECTFWR_X_WMRK_960 (0xE) +#define MCF_FEC_FECTFWR_X_WMRK_1024 (0xF) + +/* Bit definitions and macros for MCF_FEC_FECRFDR */ +#define MCF_FEC_FECRFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFSR */ +#define MCF_FEC_FECRFSR_EMT (0x10000) +#define MCF_FEC_FECRFSR_ALARM (0x20000) +#define MCF_FEC_FECRFSR_FU (0x40000) +#define MCF_FEC_FECRFSR_FRMRDY (0x80000) +#define MCF_FEC_FECRFSR_OF (0x100000) +#define MCF_FEC_FECRFSR_UF (0x200000) +#define MCF_FEC_FECRFSR_RXW (0x400000) +#define MCF_FEC_FECRFSR_FAE (0x800000) +#define MCF_FEC_FECRFSR_FRM(x) (((x)&0xF)<<0x18) +#define MCF_FEC_FECRFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_FEC_FECRFCR */ +#define MCF_FEC_FECRFCR_COUNTER(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_FECRFCR_OF_MSK (0x80000) +#define MCF_FEC_FECRFCR_UF_MSK (0x100000) +#define MCF_FEC_FECRFCR_RXW_MSK (0x200000) +#define MCF_FEC_FECRFCR_FAE_MSK (0x400000) +#define MCF_FEC_FECRFCR_IP_MSK (0x800000) +#define MCF_FEC_FECRFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_FEC_FECRFCR_FRMEN (0x8000000) +#define MCF_FEC_FECRFCR_TIMER (0x10000000) + +/* Bit definitions and macros for MCF_FEC_FECRLRFP */ +#define MCF_FEC_FECRLRFP_LRFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRLWFP */ +#define MCF_FEC_FECRLWFP_LWFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFAR */ +#define MCF_FEC_FECRFAR_ALARM(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFRP */ +#define MCF_FEC_FECRFRP_READ(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFWP */ +#define MCF_FEC_FECRFWP_WRITE(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFDR */ +#define MCF_FEC_FECTFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFSR */ +#define MCF_FEC_FECTFSR_EMT (0x10000) +#define MCF_FEC_FECTFSR_ALARM (0x20000) +#define MCF_FEC_FECTFSR_FU (0x40000) +#define MCF_FEC_FECTFSR_FRMRDY (0x80000) +#define MCF_FEC_FECTFSR_OF (0x100000) +#define MCF_FEC_FECTFSR_UF (0x200000) +#define MCF_FEC_FECTFSR_FAE (0x800000) +#define MCF_FEC_FECTFSR_FRM(x) (((x)&0xF)<<0x18) +#define MCF_FEC_FECTFSR_TXW (0x40000000) +#define MCF_FEC_FECTFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_FEC_FECTFCR */ +#define MCF_FEC_FECTFCR_RESERVED (0x200000) +#define MCF_FEC_FECTFCR_COUNTER(x) (((x)&0xFFFF)<<0|0x200000) +#define MCF_FEC_FECTFCR_TXW_MASK (0x240000) +#define MCF_FEC_FECTFCR_OF_MSK (0x280000) +#define MCF_FEC_FECTFCR_UF_MSK (0x300000) +#define MCF_FEC_FECTFCR_FAE_MSK (0x600000) +#define MCF_FEC_FECTFCR_IP_MSK (0xA00000) +#define MCF_FEC_FECTFCR_GR(x) (((x)&0x7)<<0x18|0x200000) +#define MCF_FEC_FECTFCR_FRMEN (0x8200000) +#define MCF_FEC_FECTFCR_TIMER (0x10200000) +#define MCF_FEC_FECTFCR_WFR (0x20200000) +#define MCF_FEC_FECTFCR_WCTL (0x40200000) + +/* Bit definitions and macros for MCF_FEC_FECTLRFP */ +#define MCF_FEC_FECTLRFP_LRFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTLWFP */ +#define MCF_FEC_FECTLWFP_LWFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFAR */ +#define MCF_FEC_FECTFAR_ALARM(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFRP */ +#define MCF_FEC_FECTFRP_READ(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFWP */ +#define MCF_FEC_FECTFWP_WRITE(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECFRST */ +#define MCF_FEC_FECFRST_RST_CTL (0x1000000) +#define MCF_FEC_FECFRST_SW_RST (0x2000000) + +/* Bit definitions and macros for MCF_FEC_FECCTCWR */ +#define MCF_FEC_FECCTCWR_TFCW (0x1000000) +#define MCF_FEC_FECCTCWR_CRC (0x2000000) + +/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */ +#define MCF_FEC_RMON_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */ +#define MCF_FEC_RMON_T_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */ +#define MCF_FEC_RMON_T_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */ +#define MCF_FEC_RMON_T_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */ +#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */ +#define MCF_FEC_RMON_T_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */ +#define MCF_FEC_RMON_T_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */ +#define MCF_FEC_RMON_T_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */ +#define MCF_FEC_RMON_T_JAB_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_COL */ +#define MCF_FEC_RMON_T_COL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */ +#define MCF_FEC_RMON_T_P64_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */ +#define MCF_FEC_RMON_T_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */ +#define MCF_FEC_RMON_T_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */ +#define MCF_FEC_RMON_T_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */ +#define MCF_FEC_RMON_T_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */ +#define MCF_FEC_RMON_T_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */ +#define MCF_FEC_RMON_T_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */ +#define MCF_FEC_RMON_T_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */ +#define MCF_FEC_IEEE_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */ +#define MCF_FEC_IEEE_T_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */ +#define MCF_FEC_IEEE_T_1COL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */ +#define MCF_FEC_IEEE_T_MCOL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */ +#define MCF_FEC_IEEE_T_DEF_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */ +#define MCF_FEC_IEEE_T_LCOL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */ +#define MCF_FEC_IEEE_T_EXCOL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */ +#define MCF_FEC_IEEE_T_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */ +#define MCF_FEC_IEEE_T_CSERR_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */ +#define MCF_FEC_IEEE_T_SQE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */ +#define MCF_FEC_IEEE_T_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */ +#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_DROP */ +#define MCF_FEC_RMON_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */ +#define MCF_FEC_RMON_R_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */ +#define MCF_FEC_RMON_R_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */ +#define MCF_FEC_RMON_R_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */ +#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */ +#define MCF_FEC_RMON_R_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */ +#define MCF_FEC_RMON_R_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */ +#define MCF_FEC_RMON_R_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */ +#define MCF_FEC_RMON_R_JAB_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */ +#define MCF_FEC_RMON_R_RESVD_0_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */ +#define MCF_FEC_RMON_R_P64_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */ +#define MCF_FEC_RMON_R_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */ +#define MCF_FEC_RMON_R_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */ +#define MCF_FEC_RMON_R_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */ +#define MCF_FEC_RMON_R_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */ +#define MCF_FEC_RMON_R_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */ +#define MCF_FEC_RMON_R_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */ +#define MCF_FEC_RMON_R_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */ +#define MCF_FEC_IEEE_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */ +#define MCF_FEC_IEEE_R_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */ +#define MCF_FEC_IEEE_R_CRC_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */ +#define MCF_FEC_IEEE_R_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */ +#define MCF_FEC_IEEE_R_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */ +#define MCF_FEC_IEEE_R_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */ +#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + + +#endif /* __MCF5475_FEC_H__ */ diff --git a/tos/pci_test/include/MCF5475_GPIO.h b/tos/pci_test/include/MCF5475_GPIO.h new file mode 100644 index 0000000..5dd2583 --- /dev/null +++ b/tos/pci_test/include/MCF5475_GPIO.h @@ -0,0 +1,543 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_GPIO_H__ +#define __MCF5475_GPIO_H__ + + +/********************************************************************* +* +* General Purpose I/O (GPIO) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPIO_PODR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA00])) +#define MCF_GPIO_PDDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA10])) +#define MCF_GPIO_PPDSDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA20])) +#define MCF_GPIO_PCLRR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA30])) + +#define MCF_GPIO_PODR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA01])) +#define MCF_GPIO_PDDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA11])) +#define MCF_GPIO_PPDSDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA21])) +#define MCF_GPIO_PCLRR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA31])) + +#define MCF_GPIO_PODR_DMA (*(volatile uint8_t *)(&_MBAR[0xA02])) +#define MCF_GPIO_PDDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA12])) +#define MCF_GPIO_PPDSDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA22])) +#define MCF_GPIO_PCLRR_DMA (*(volatile uint8_t *)(&_MBAR[0xA32])) + +#define MCF_GPIO_PODR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA04])) +#define MCF_GPIO_PDDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA14])) +#define MCF_GPIO_PPDSDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA24])) +#define MCF_GPIO_PCLRR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA34])) + +#define MCF_GPIO_PODR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA05])) +#define MCF_GPIO_PDDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA15])) +#define MCF_GPIO_PPDSDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA25])) +#define MCF_GPIO_PCLRR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA35])) + +#define MCF_GPIO_PODR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA06])) +#define MCF_GPIO_PDDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA16])) +#define MCF_GPIO_PPDSDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA26])) +#define MCF_GPIO_PCLRR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA36])) + +#define MCF_GPIO_PODR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA07])) +#define MCF_GPIO_PDDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA17])) +#define MCF_GPIO_PPDSDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA27])) +#define MCF_GPIO_PCLRR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA37])) + +#define MCF_GPIO_PODR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA08])) +#define MCF_GPIO_PDDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA18])) +#define MCF_GPIO_PPDSDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA28])) +#define MCF_GPIO_PCLRR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA38])) + +#define MCF_GPIO_PODR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA09])) +#define MCF_GPIO_PDDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA19])) +#define MCF_GPIO_PPDSDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA29])) +#define MCF_GPIO_PCLRR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA39])) + +#define MCF_GPIO_PODR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA0A])) +#define MCF_GPIO_PDDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA1A])) +#define MCF_GPIO_PPDSDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA2A])) +#define MCF_GPIO_PCLRR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA3A])) + +#define MCF_GPIO2_PODR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA0C])) +#define MCF_GPIO2_PDDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA1C])) +#define MCF_GPIO2_PPDSDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA2C])) +#define MCF_GPIO2_PCLRR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA3C])) + +#define MCF_GPIO0_PODR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA0D])) +#define MCF_GPIO0_PDDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA1D])) +#define MCF_GPIO0_PPDSDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA2D])) +#define MCF_GPIO0_PCLRR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA3D])) + +#define MCF_GPIO_PODR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA0E])) +#define MCF_GPIO_PDDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA1E])) +#define MCF_GPIO_PPDSDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA2E])) +#define MCF_GPIO_PCLRR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA3E])) + + + +/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */ +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x1) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x2) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x4) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x8) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */ +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x1) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x2) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x4) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x8) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */ +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x1) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x2) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x4) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x8) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */ +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x1) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x2) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x4) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x8) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */ +#define MCF_GPIO_PODR_FBCS_PODR_FBCS1 (0x2) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS2 (0x4) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS3 (0x8) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS4 (0x10) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */ +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x2) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x4) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x8) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */ +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x2) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x4) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x8) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */ +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x2) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x4) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x8) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PODR_DMA */ +#define MCF_GPIO_PODR_DMA_PODR_DMA0 (0x1) +#define MCF_GPIO_PODR_DMA_PODR_DMA1 (0x2) +#define MCF_GPIO_PODR_DMA_PODR_DMA2 (0x4) +#define MCF_GPIO_PODR_DMA_PODR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */ +#define MCF_GPIO_PDDR_DMA_PDDR_DMA0 (0x1) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA1 (0x2) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA2 (0x4) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */ +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x1) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x2) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x4) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */ +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x1) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x2) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x4) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */ +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x1) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x2) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x4) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x8) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */ +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x1) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x2) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x4) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x8) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */ +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x1) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x2) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x4) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x8) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */ +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x1) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x2) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x4) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x8) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */ +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x1) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x2) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x4) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x8) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */ +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x1) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x2) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x4) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x8) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */ +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x1) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x2) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x4) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x8) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */ +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x1) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1 (0x2) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x4) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x8) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4 (0x10) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5 (0x20) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6 (0x40) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */ +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x1) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x2) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x4) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x8) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */ +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x1) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x2) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x4) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x8) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */ +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x1) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x2) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x4) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x8) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */ +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x1) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x2) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x4) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3 (0x8) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4 (0x10) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */ +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x1) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x2) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x4) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x8) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */ +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x1) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x2) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x4) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x8) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */ +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x1) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x2) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x4) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x8) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */ +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x1) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x2) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x4) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x8) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4 (0x10) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x1) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x2) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x4) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x1) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x2) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x4) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x1) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x2) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x4) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */ +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x1) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x2) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x4) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x8) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */ +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x1) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x2) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x4) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x8) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */ +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x1) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x2) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x4) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x8) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */ +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0 (0x1) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1 (0x2) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2 (0x4) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x8) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */ +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x1) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x2) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x4) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x8) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */ +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x1) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x2) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x4) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x8) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */ +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x1) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x2) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x4) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x8) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */ +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x1) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x2) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x4) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3 (0x8) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */ +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */ +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */ +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */ +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */ +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */ +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */ +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */ +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */ +#define MCF_GPIO_PODR_DSPI_PODR_DSPI0 (0x1) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI1 (0x2) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI2 (0x4) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI3 (0x8) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI4 (0x10) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI5 (0x20) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */ +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x1) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x2) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x4) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x8) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */ +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x1) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x2) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x4) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x8) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4 (0x10) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */ +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x1) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x2) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x4) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x8) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40) + + +#endif /* __MCF5475_GPIO_H__ */ diff --git a/tos/pci_test/include/MCF5475_GPT.h b/tos/pci_test/include/MCF5475_GPT.h new file mode 100644 index 0000000..f9fbc98 --- /dev/null +++ b/tos/pci_test/include/MCF5475_GPT.h @@ -0,0 +1,100 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_GPT_H__ +#define __MCF5475_GPT_H__ + + +/********************************************************************* +* +* General Purpose Timers (GPT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPT0_GMS (*(volatile uint32_t*)(&_MBAR[0x800])) +#define MCF_GPT0_GCIR (*(volatile uint32_t*)(&_MBAR[0x804])) +#define MCF_GPT0_GPWM (*(volatile uint32_t*)(&_MBAR[0x808])) +#define MCF_GPT0_GSR (*(volatile uint32_t*)(&_MBAR[0x80C])) + +#define MCF_GPT1_GMS (*(volatile uint32_t*)(&_MBAR[0x810])) +#define MCF_GPT1_GCIR (*(volatile uint32_t*)(&_MBAR[0x814])) +#define MCF_GPT1_GPWM (*(volatile uint32_t*)(&_MBAR[0x818])) +#define MCF_GPT1_GSR (*(volatile uint32_t*)(&_MBAR[0x81C])) + +#define MCF_GPT2_GMS (*(volatile uint32_t*)(&_MBAR[0x820])) +#define MCF_GPT2_GCIR (*(volatile uint32_t*)(&_MBAR[0x824])) +#define MCF_GPT2_GPWM (*(volatile uint32_t*)(&_MBAR[0x828])) +#define MCF_GPT2_GSR (*(volatile uint32_t*)(&_MBAR[0x82C])) + +#define MCF_GPT3_GMS (*(volatile uint32_t*)(&_MBAR[0x830])) +#define MCF_GPT3_GCIR (*(volatile uint32_t*)(&_MBAR[0x834])) +#define MCF_GPT3_GPWM (*(volatile uint32_t*)(&_MBAR[0x838])) +#define MCF_GPT3_GSR (*(volatile uint32_t*)(&_MBAR[0x83C])) + +#define MCF_GPT_GMS(x) (*(volatile uint32_t*)(&_MBAR[0x800 + ((x)*0x10)])) +#define MCF_GPT_GCIR(x) (*(volatile uint32_t*)(&_MBAR[0x804 + ((x)*0x10)])) +#define MCF_GPT_GPWM(x) (*(volatile uint32_t*)(&_MBAR[0x808 + ((x)*0x10)])) +#define MCF_GPT_GSR(x) (*(volatile uint32_t*)(&_MBAR[0x80C + ((x)*0x10)])) + + +/* Bit definitions and macros for MCF_GPT_GMS */ +#define MCF_GPT_GMS_TMS(x) (((x)&0x7)<<0) +#define MCF_GPT_GMS_TMS_DISABLE (0) +#define MCF_GPT_GMS_TMS_INCAPT (0x1) +#define MCF_GPT_GMS_TMS_OUTCAPT (0x2) +#define MCF_GPT_GMS_TMS_PWM (0x3) +#define MCF_GPT_GMS_TMS_GPIO (0x4) +#define MCF_GPT_GMS_GPIO(x) (((x)&0x3)<<0x4) +#define MCF_GPT_GMS_GPIO_INPUT (0) +#define MCF_GPT_GMS_GPIO_OUTLO (0x20) +#define MCF_GPT_GMS_GPIO_OUTHI (0x30) +#define MCF_GPT_GMS_IEN (0x100) +#define MCF_GPT_GMS_OD (0x200) +#define MCF_GPT_GMS_SC (0x400) +#define MCF_GPT_GMS_CE (0x1000) +#define MCF_GPT_GMS_WDEN (0x8000) +#define MCF_GPT_GMS_ICT(x) (((x)&0x3)<<0x10) +#define MCF_GPT_GMS_ICT_ANY (0) +#define MCF_GPT_GMS_ICT_RISE (0x10000) +#define MCF_GPT_GMS_ICT_FALL (0x20000) +#define MCF_GPT_GMS_ICT_PULSE (0x30000) +#define MCF_GPT_GMS_OCT(x) (((x)&0x3)<<0x14) +#define MCF_GPT_GMS_OCT_FRCLOW (0) +#define MCF_GPT_GMS_OCT_PULSEHI (0x100000) +#define MCF_GPT_GMS_OCT_PULSELO (0x200000) +#define MCF_GPT_GMS_OCT_TOGGLE (0x300000) +#define MCF_GPT_GMS_OCPW(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_GPT_GCIR */ +#define MCF_GPT_GCIR_CNT(x) (((x)&0xFFFF)<<0) +#define MCF_GPT_GCIR_PRE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_GPT_GPWM */ +#define MCF_GPT_GPWM_LOAD (0x1) +#define MCF_GPT_GPWM_PWMOP (0x100) +#define MCF_GPT_GPWM_WIDTH(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_GPT_GSR */ +#define MCF_GPT_GSR_CAPT (0x1) +#define MCF_GPT_GSR_COMP (0x2) +#define MCF_GPT_GSR_PWMP (0x4) +#define MCF_GPT_GSR_TEXP (0x8) +#define MCF_GPT_GSR_PIN (0x100) +#define MCF_GPT_GSR_OVF(x) (((x)&0x7)<<0xC) +#define MCF_GPT_GSR_CAPTURE(x) (((x)&0xFFFF)<<0x10) + + +#endif /* __MCF5475_GPT_H__ */ diff --git a/tos/pci_test/include/MCF5475_I2C.h b/tos/pci_test/include/MCF5475_I2C.h new file mode 100644 index 0000000..1e8a85b --- /dev/null +++ b/tos/pci_test/include/MCF5475_I2C.h @@ -0,0 +1,69 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_I2C_H__ +#define __MCF5475_I2C_H__ + + +/********************************************************************* +* +* I2C Module (I2C) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_I2C_I2ADR (*(volatile uint8_t *)(&_MBAR[0x8F00])) +#define MCF_I2C_I2FDR (*(volatile uint8_t *)(&_MBAR[0x8F04])) +#define MCF_I2C_I2CR (*(volatile uint8_t *)(&_MBAR[0x8F08])) +#define MCF_I2C_I2SR (*(volatile uint8_t *)(&_MBAR[0x8F0C])) +#define MCF_I2C_I2DR (*(volatile uint8_t *)(&_MBAR[0x8F10])) +#define MCF_I2C_I2ICR (*(volatile uint8_t *)(&_MBAR[0x8F20])) + + + +/* Bit definitions and macros for MCF_I2C_I2ADR */ +#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1) + +/* Bit definitions and macros for MCF_I2C_I2FDR */ +#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) + +/* Bit definitions and macros for MCF_I2C_I2CR */ +#define MCF_I2C_I2CR_RSTA (0x4) +#define MCF_I2C_I2CR_TXAK (0x8) +#define MCF_I2C_I2CR_MTX (0x10) +#define MCF_I2C_I2CR_MSTA (0x20) +#define MCF_I2C_I2CR_IIEN (0x40) +#define MCF_I2C_I2CR_IEN (0x80) + +/* Bit definitions and macros for MCF_I2C_I2SR */ +#define MCF_I2C_I2SR_RXAK (0x1) +#define MCF_I2C_I2SR_IIF (0x2) +#define MCF_I2C_I2SR_SRW (0x4) +#define MCF_I2C_I2SR_IAL (0x10) +#define MCF_I2C_I2SR_IBB (0x20) +#define MCF_I2C_I2SR_IAAS (0x40) +#define MCF_I2C_I2SR_ICF (0x80) + +/* Bit definitions and macros for MCF_I2C_I2DR */ +#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_I2C_I2ICR */ +#define MCF_I2C_I2ICR_IE (0x1) +#define MCF_I2C_I2ICR_RE (0x2) +#define MCF_I2C_I2ICR_TE (0x4) +#define MCF_I2C_I2ICR_BNBE (0x8) + + +#endif /* __MCF5475_I2C_H__ */ diff --git a/tos/pci_test/include/MCF5475_INTC.h b/tos/pci_test/include/MCF5475_INTC.h new file mode 100644 index 0000000..61265ed --- /dev/null +++ b/tos/pci_test/include/MCF5475_INTC.h @@ -0,0 +1,331 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_INTC_H__ +#define __MCF5475_INTC_H__ + + +/********************************************************************* +* +* Interrupt Controller (INTC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_INTC_IPRH (*(volatile uint32_t*)(&_MBAR[0x700])) +#define MCF_INTC_IPRL (*(volatile uint32_t*)(&_MBAR[0x704])) +#define MCF_INTC_IMRH (*(volatile uint32_t*)(&_MBAR[0x708])) +#define MCF_INTC_IMRL (*(volatile uint32_t*)(&_MBAR[0x70C])) +#define MCF_INTC_INTFRCH (*(volatile uint32_t*)(&_MBAR[0x710])) +#define MCF_INTC_INTFRCL (*(volatile uint32_t*)(&_MBAR[0x714])) +#define MCF_INTC_IRLR (*(volatile uint8_t *)(&_MBAR[0x718])) +#define MCF_INTC_IACKLPR (*(volatile uint8_t *)(&_MBAR[0x719])) +#define MCF_INTC_ICR01 (*(volatile uint8_t *)(&_MBAR[0x741])) +#define MCF_INTC_ICR02 (*(volatile uint8_t *)(&_MBAR[0x742])) +#define MCF_INTC_ICR03 (*(volatile uint8_t *)(&_MBAR[0x743])) +#define MCF_INTC_ICR04 (*(volatile uint8_t *)(&_MBAR[0x744])) +#define MCF_INTC_ICR05 (*(volatile uint8_t *)(&_MBAR[0x745])) +#define MCF_INTC_ICR06 (*(volatile uint8_t *)(&_MBAR[0x746])) +#define MCF_INTC_ICR07 (*(volatile uint8_t *)(&_MBAR[0x747])) +#define MCF_INTC_ICR08 (*(volatile uint8_t *)(&_MBAR[0x748])) +#define MCF_INTC_ICR09 (*(volatile uint8_t *)(&_MBAR[0x749])) +#define MCF_INTC_ICR10 (*(volatile uint8_t *)(&_MBAR[0x74A])) +#define MCF_INTC_ICR11 (*(volatile uint8_t *)(&_MBAR[0x74B])) +#define MCF_INTC_ICR12 (*(volatile uint8_t *)(&_MBAR[0x74C])) +#define MCF_INTC_ICR13 (*(volatile uint8_t *)(&_MBAR[0x74D])) +#define MCF_INTC_ICR14 (*(volatile uint8_t *)(&_MBAR[0x74E])) +#define MCF_INTC_ICR15 (*(volatile uint8_t *)(&_MBAR[0x74F])) +#define MCF_INTC_ICR16 (*(volatile uint8_t *)(&_MBAR[0x750])) +#define MCF_INTC_ICR17 (*(volatile uint8_t *)(&_MBAR[0x751])) +#define MCF_INTC_ICR18 (*(volatile uint8_t *)(&_MBAR[0x752])) +#define MCF_INTC_ICR19 (*(volatile uint8_t *)(&_MBAR[0x753])) +#define MCF_INTC_ICR20 (*(volatile uint8_t *)(&_MBAR[0x754])) +#define MCF_INTC_ICR21 (*(volatile uint8_t *)(&_MBAR[0x755])) +#define MCF_INTC_ICR22 (*(volatile uint8_t *)(&_MBAR[0x756])) +#define MCF_INTC_ICR23 (*(volatile uint8_t *)(&_MBAR[0x757])) +#define MCF_INTC_ICR24 (*(volatile uint8_t *)(&_MBAR[0x758])) +#define MCF_INTC_ICR25 (*(volatile uint8_t *)(&_MBAR[0x759])) +#define MCF_INTC_ICR26 (*(volatile uint8_t *)(&_MBAR[0x75A])) +#define MCF_INTC_ICR27 (*(volatile uint8_t *)(&_MBAR[0x75B])) +#define MCF_INTC_ICR28 (*(volatile uint8_t *)(&_MBAR[0x75C])) +#define MCF_INTC_ICR29 (*(volatile uint8_t *)(&_MBAR[0x75D])) +#define MCF_INTC_ICR30 (*(volatile uint8_t *)(&_MBAR[0x75E])) +#define MCF_INTC_ICR31 (*(volatile uint8_t *)(&_MBAR[0x75F])) +#define MCF_INTC_ICR32 (*(volatile uint8_t *)(&_MBAR[0x760])) +#define MCF_INTC_ICR33 (*(volatile uint8_t *)(&_MBAR[0x761])) +#define MCF_INTC_ICR34 (*(volatile uint8_t *)(&_MBAR[0x762])) +#define MCF_INTC_ICR35 (*(volatile uint8_t *)(&_MBAR[0x763])) +#define MCF_INTC_ICR36 (*(volatile uint8_t *)(&_MBAR[0x764])) +#define MCF_INTC_ICR37 (*(volatile uint8_t *)(&_MBAR[0x765])) +#define MCF_INTC_ICR38 (*(volatile uint8_t *)(&_MBAR[0x766])) +#define MCF_INTC_ICR39 (*(volatile uint8_t *)(&_MBAR[0x767])) +#define MCF_INTC_ICR40 (*(volatile uint8_t *)(&_MBAR[0x768])) +#define MCF_INTC_ICR41 (*(volatile uint8_t *)(&_MBAR[0x769])) +#define MCF_INTC_ICR42 (*(volatile uint8_t *)(&_MBAR[0x76A])) +#define MCF_INTC_ICR43 (*(volatile uint8_t *)(&_MBAR[0x76B])) +#define MCF_INTC_ICR44 (*(volatile uint8_t *)(&_MBAR[0x76C])) +#define MCF_INTC_ICR45 (*(volatile uint8_t *)(&_MBAR[0x76D])) +#define MCF_INTC_ICR46 (*(volatile uint8_t *)(&_MBAR[0x76E])) +#define MCF_INTC_ICR47 (*(volatile uint8_t *)(&_MBAR[0x76F])) +#define MCF_INTC_ICR48 (*(volatile uint8_t *)(&_MBAR[0x770])) +#define MCF_INTC_ICR49 (*(volatile uint8_t *)(&_MBAR[0x771])) +#define MCF_INTC_ICR50 (*(volatile uint8_t *)(&_MBAR[0x772])) +#define MCF_INTC_ICR51 (*(volatile uint8_t *)(&_MBAR[0x773])) +#define MCF_INTC_ICR52 (*(volatile uint8_t *)(&_MBAR[0x774])) +#define MCF_INTC_ICR53 (*(volatile uint8_t *)(&_MBAR[0x775])) +#define MCF_INTC_ICR54 (*(volatile uint8_t *)(&_MBAR[0x776])) +#define MCF_INTC_ICR55 (*(volatile uint8_t *)(&_MBAR[0x777])) +#define MCF_INTC_ICR56 (*(volatile uint8_t *)(&_MBAR[0x778])) +#define MCF_INTC_ICR57 (*(volatile uint8_t *)(&_MBAR[0x779])) +#define MCF_INTC_ICR58 (*(volatile uint8_t *)(&_MBAR[0x77A])) +#define MCF_INTC_ICR59 (*(volatile uint8_t *)(&_MBAR[0x77B])) +#define MCF_INTC_ICR60 (*(volatile uint8_t *)(&_MBAR[0x77C])) +#define MCF_INTC_ICR61 (*(volatile uint8_t *)(&_MBAR[0x77D])) +#define MCF_INTC_ICR62 (*(volatile uint8_t *)(&_MBAR[0x77E])) +#define MCF_INTC_ICR63 (*(volatile uint8_t *)(&_MBAR[0x77F])) +#define MCF_INTC_SWIACK (*(volatile uint8_t *)(&_MBAR[0x7E0])) +#define MCF_INTC_L1IACK (*(volatile uint8_t *)(&_MBAR[0x7E4])) +#define MCF_INTC_L2IACK (*(volatile uint8_t *)(&_MBAR[0x7E8])) +#define MCF_INTC_L3IACK (*(volatile uint8_t *)(&_MBAR[0x7EC])) +#define MCF_INTC_L4IACK (*(volatile uint8_t *)(&_MBAR[0x7F0])) +#define MCF_INTC_L5IACK (*(volatile uint8_t *)(&_MBAR[0x7F4])) +#define MCF_INTC_L6IACK (*(volatile uint8_t *)(&_MBAR[0x7F8])) +#define MCF_INTC_L7IACK (*(volatile uint8_t *)(&_MBAR[0x7FC])) +#define MCF_INTC_ICR(x) (*(volatile uint8_t *)(&_MBAR[0x741 + ((x-1)*0x1)])) +#define MCF_INTC_LIACK(x) (*(volatile uint8_t *)(&_MBAR[0x7E4 + ((x-1)*0x4)])) + + + +/* Bit definitions and macros for MCF_INTC_IPRH */ +#define MCF_INTC_IPRH_INT32 (0x1) +#define MCF_INTC_IPRH_INT33 (0x2) +#define MCF_INTC_IPRH_INT34 (0x4) +#define MCF_INTC_IPRH_INT35 (0x8) +#define MCF_INTC_IPRH_INT36 (0x10) +#define MCF_INTC_IPRH_INT37 (0x20) +#define MCF_INTC_IPRH_INT38 (0x40) +#define MCF_INTC_IPRH_INT39 (0x80) +#define MCF_INTC_IPRH_INT40 (0x100) +#define MCF_INTC_IPRH_INT41 (0x200) +#define MCF_INTC_IPRH_INT42 (0x400) +#define MCF_INTC_IPRH_INT43 (0x800) +#define MCF_INTC_IPRH_INT44 (0x1000) +#define MCF_INTC_IPRH_INT45 (0x2000) +#define MCF_INTC_IPRH_INT46 (0x4000) +#define MCF_INTC_IPRH_INT47 (0x8000) +#define MCF_INTC_IPRH_INT48 (0x10000) +#define MCF_INTC_IPRH_INT49 (0x20000) +#define MCF_INTC_IPRH_INT50 (0x40000) +#define MCF_INTC_IPRH_INT51 (0x80000) +#define MCF_INTC_IPRH_INT52 (0x100000) +#define MCF_INTC_IPRH_INT53 (0x200000) +#define MCF_INTC_IPRH_INT54 (0x400000) +#define MCF_INTC_IPRH_INT55 (0x800000) +#define MCF_INTC_IPRH_INT56 (0x1000000) +#define MCF_INTC_IPRH_INT57 (0x2000000) +#define MCF_INTC_IPRH_INT58 (0x4000000) +#define MCF_INTC_IPRH_INT59 (0x8000000) +#define MCF_INTC_IPRH_INT60 (0x10000000) +#define MCF_INTC_IPRH_INT61 (0x20000000) +#define MCF_INTC_IPRH_INT62 (0x40000000) +#define MCF_INTC_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IPRL */ +#define MCF_INTC_IPRL_INT1 (0x2) +#define MCF_INTC_IPRL_INT2 (0x4) +#define MCF_INTC_IPRL_INT3 (0x8) +#define MCF_INTC_IPRL_INT4 (0x10) +#define MCF_INTC_IPRL_INT5 (0x20) +#define MCF_INTC_IPRL_INT6 (0x40) +#define MCF_INTC_IPRL_INT7 (0x80) +#define MCF_INTC_IPRL_INT8 (0x100) +#define MCF_INTC_IPRL_INT9 (0x200) +#define MCF_INTC_IPRL_INT10 (0x400) +#define MCF_INTC_IPRL_INT11 (0x800) +#define MCF_INTC_IPRL_INT12 (0x1000) +#define MCF_INTC_IPRL_INT13 (0x2000) +#define MCF_INTC_IPRL_INT14 (0x4000) +#define MCF_INTC_IPRL_INT15 (0x8000) +#define MCF_INTC_IPRL_INT16 (0x10000) +#define MCF_INTC_IPRL_INT17 (0x20000) +#define MCF_INTC_IPRL_INT18 (0x40000) +#define MCF_INTC_IPRL_INT19 (0x80000) +#define MCF_INTC_IPRL_INT20 (0x100000) +#define MCF_INTC_IPRL_INT21 (0x200000) +#define MCF_INTC_IPRL_INT22 (0x400000) +#define MCF_INTC_IPRL_INT23 (0x800000) +#define MCF_INTC_IPRL_INT24 (0x1000000) +#define MCF_INTC_IPRL_INT25 (0x2000000) +#define MCF_INTC_IPRL_INT26 (0x4000000) +#define MCF_INTC_IPRL_INT27 (0x8000000) +#define MCF_INTC_IPRL_INT28 (0x10000000) +#define MCF_INTC_IPRL_INT29 (0x20000000) +#define MCF_INTC_IPRL_INT30 (0x40000000) +#define MCF_INTC_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRH */ +#define MCF_INTC_IMRH_INT_MASK32 (0x1) +#define MCF_INTC_IMRH_INT_MASK33 (0x2) +#define MCF_INTC_IMRH_INT_MASK34 (0x4) +#define MCF_INTC_IMRH_INT_MASK35 (0x8) +#define MCF_INTC_IMRH_INT_MASK36 (0x10) +#define MCF_INTC_IMRH_INT_MASK37 (0x20) +#define MCF_INTC_IMRH_INT_MASK38 (0x40) +#define MCF_INTC_IMRH_INT_MASK39 (0x80) +#define MCF_INTC_IMRH_INT_MASK40 (0x100) +#define MCF_INTC_IMRH_INT_MASK41 (0x200) +#define MCF_INTC_IMRH_INT_MASK42 (0x400) +#define MCF_INTC_IMRH_INT_MASK43 (0x800) +#define MCF_INTC_IMRH_INT_MASK44 (0x1000) +#define MCF_INTC_IMRH_INT_MASK45 (0x2000) +#define MCF_INTC_IMRH_INT_MASK46 (0x4000) +#define MCF_INTC_IMRH_INT_MASK47 (0x8000) +#define MCF_INTC_IMRH_INT_MASK48 (0x10000) +#define MCF_INTC_IMRH_INT_MASK49 (0x20000) +#define MCF_INTC_IMRH_INT_MASK50 (0x40000) +#define MCF_INTC_IMRH_INT_MASK51 (0x80000) +#define MCF_INTC_IMRH_INT_MASK52 (0x100000) +#define MCF_INTC_IMRH_INT_MASK53 (0x200000) +#define MCF_INTC_IMRH_INT_MASK54 (0x400000) +#define MCF_INTC_IMRH_INT_MASK55 (0x800000) +#define MCF_INTC_IMRH_INT_MASK56 (0x1000000) +#define MCF_INTC_IMRH_INT_MASK57 (0x2000000) +#define MCF_INTC_IMRH_INT_MASK58 (0x4000000) +#define MCF_INTC_IMRH_INT_MASK59 (0x8000000) +#define MCF_INTC_IMRH_INT_MASK60 (0x10000000) +#define MCF_INTC_IMRH_INT_MASK61 (0x20000000) +#define MCF_INTC_IMRH_INT_MASK62 (0x40000000) +#define MCF_INTC_IMRH_INT_MASK63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRL */ +#define MCF_INTC_IMRL_MASKALL (0x1) +#define MCF_INTC_IMRL_INT_MASK1 (0x2) +#define MCF_INTC_IMRL_INT_MASK2 (0x4) +#define MCF_INTC_IMRL_INT_MASK3 (0x8) +#define MCF_INTC_IMRL_INT_MASK4 (0x10) +#define MCF_INTC_IMRL_INT_MASK5 (0x20) +#define MCF_INTC_IMRL_INT_MASK6 (0x40) +#define MCF_INTC_IMRL_INT_MASK7 (0x80) +#define MCF_INTC_IMRL_INT_MASK8 (0x100) +#define MCF_INTC_IMRL_INT_MASK9 (0x200) +#define MCF_INTC_IMRL_INT_MASK10 (0x400) +#define MCF_INTC_IMRL_INT_MASK11 (0x800) +#define MCF_INTC_IMRL_INT_MASK12 (0x1000) +#define MCF_INTC_IMRL_INT_MASK13 (0x2000) +#define MCF_INTC_IMRL_INT_MASK14 (0x4000) +#define MCF_INTC_IMRL_INT_MASK15 (0x8000) +#define MCF_INTC_IMRL_INT_MASK16 (0x10000) +#define MCF_INTC_IMRL_INT_MASK17 (0x20000) +#define MCF_INTC_IMRL_INT_MASK18 (0x40000) +#define MCF_INTC_IMRL_INT_MASK19 (0x80000) +#define MCF_INTC_IMRL_INT_MASK20 (0x100000) +#define MCF_INTC_IMRL_INT_MASK21 (0x200000) +#define MCF_INTC_IMRL_INT_MASK22 (0x400000) +#define MCF_INTC_IMRL_INT_MASK23 (0x800000) +#define MCF_INTC_IMRL_INT_MASK24 (0x1000000) +#define MCF_INTC_IMRL_INT_MASK25 (0x2000000) +#define MCF_INTC_IMRL_INT_MASK26 (0x4000000) +#define MCF_INTC_IMRL_INT_MASK27 (0x8000000) +#define MCF_INTC_IMRL_INT_MASK28 (0x10000000) +#define MCF_INTC_IMRL_INT_MASK29 (0x20000000) +#define MCF_INTC_IMRL_INT_MASK30 (0x40000000) +#define MCF_INTC_IMRL_INT_MASK31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCH */ +#define MCF_INTC_INTFRCH_INTFRC32 (0x1) +#define MCF_INTC_INTFRCH_INTFRC33 (0x2) +#define MCF_INTC_INTFRCH_INTFRC34 (0x4) +#define MCF_INTC_INTFRCH_INTFRC35 (0x8) +#define MCF_INTC_INTFRCH_INTFRC36 (0x10) +#define MCF_INTC_INTFRCH_INTFRC37 (0x20) +#define MCF_INTC_INTFRCH_INTFRC38 (0x40) +#define MCF_INTC_INTFRCH_INTFRC39 (0x80) +#define MCF_INTC_INTFRCH_INTFRC40 (0x100) +#define MCF_INTC_INTFRCH_INTFRC41 (0x200) +#define MCF_INTC_INTFRCH_INTFRC42 (0x400) +#define MCF_INTC_INTFRCH_INTFRC43 (0x800) +#define MCF_INTC_INTFRCH_INTFRC44 (0x1000) +#define MCF_INTC_INTFRCH_INTFRC45 (0x2000) +#define MCF_INTC_INTFRCH_INTFRC46 (0x4000) +#define MCF_INTC_INTFRCH_INTFRC47 (0x8000) +#define MCF_INTC_INTFRCH_INTFRC48 (0x10000) +#define MCF_INTC_INTFRCH_INTFRC49 (0x20000) +#define MCF_INTC_INTFRCH_INTFRC50 (0x40000) +#define MCF_INTC_INTFRCH_INTFRC51 (0x80000) +#define MCF_INTC_INTFRCH_INTFRC52 (0x100000) +#define MCF_INTC_INTFRCH_INTFRC53 (0x200000) +#define MCF_INTC_INTFRCH_INTFRC54 (0x400000) +#define MCF_INTC_INTFRCH_INTFRC55 (0x800000) +#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000) +#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000) +#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000) +#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000) +#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) +#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) +#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) +#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCL */ +#define MCF_INTC_INTFRCL_INTFRC1 (0x2) +#define MCF_INTC_INTFRCL_INTFRC2 (0x4) +#define MCF_INTC_INTFRCL_INTFRC3 (0x8) +#define MCF_INTC_INTFRCL_INTFRC4 (0x10) +#define MCF_INTC_INTFRCL_INTFRC5 (0x20) +#define MCF_INTC_INTFRCL_INTFRC6 (0x40) +#define MCF_INTC_INTFRCL_INTFRC7 (0x80) +#define MCF_INTC_INTFRCL_INTFRC8 (0x100) +#define MCF_INTC_INTFRCL_INTFRC9 (0x200) +#define MCF_INTC_INTFRCL_INTFRC10 (0x400) +#define MCF_INTC_INTFRCL_INTFRC11 (0x800) +#define MCF_INTC_INTFRCL_INTFRC12 (0x1000) +#define MCF_INTC_INTFRCL_INTFRC13 (0x2000) +#define MCF_INTC_INTFRCL_INTFRC14 (0x4000) +#define MCF_INTC_INTFRCL_INTFRC15 (0x8000) +#define MCF_INTC_INTFRCL_INTFRC16 (0x10000) +#define MCF_INTC_INTFRCL_INTFRC17 (0x20000) +#define MCF_INTC_INTFRCL_INTFRC18 (0x40000) +#define MCF_INTC_INTFRCL_INTFRC19 (0x80000) +#define MCF_INTC_INTFRCL_INTFRC20 (0x100000) +#define MCF_INTC_INTFRCL_INTFRC21 (0x200000) +#define MCF_INTC_INTFRCL_INTFRC22 (0x400000) +#define MCF_INTC_INTFRCL_INTFRC23 (0x800000) +#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000) +#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000) +#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000) +#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000) +#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) +#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) +#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) +#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IRLR */ +#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1) + +/* Bit definitions and macros for MCF_INTC_IACKLPR */ +#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0) +#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4) + +/* Bit definitions and macros for MCF_INTC_ICR */ +#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0) +#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3) + +/* Bit definitions and macros for MCF_INTC_SWIACK */ +#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_INTC_LIACK */ +#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) + + +#endif /* __MCF5475_INTC_H__ */ diff --git a/tos/pci_test/include/MCF5475_MMU.h b/tos/pci_test/include/MCF5475_MMU.h new file mode 100644 index 0000000..334ad28 --- /dev/null +++ b/tos/pci_test/include/MCF5475_MMU.h @@ -0,0 +1,79 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_MMU_H__ +#define __MCF5475_MMU_H__ + + +/********************************************************************* +* +* Memory Management Unit (MMU) +* +*********************************************************************/ + +/* Register read/write macros */ + +/* note the uint32_t_a - this is to avoid gcc warnings about pointer aliasing */ +#define MCF_MMU_MMUCR (*(volatile uint32_t_a*)(&_MMUBAR[0])) +#define MCF_MMU_MMUOR (*(volatile uint32_t_a*)(&_MMUBAR[0x4])) +#define MCF_MMU_MMUSR (*(volatile uint32_t_a*)(&_MMUBAR[0x8])) +#define MCF_MMU_MMUAR (*(volatile uint32_t_a*)(&_MMUBAR[0x10])) +#define MCF_MMU_MMUTR (*(volatile uint32_t_a*)(&_MMUBAR[0x14])) +#define MCF_MMU_MMUDR (*(volatile uint32_t_a*)(&_MMUBAR[0x18])) + + +/* Bit definitions and macros for MCF_MMU_MMUCR */ +#define MCF_MMU_MMUCR_EN (0x1) +#define MCF_MMU_MMUCR_ASM (0x2) + +/* Bit definitions and macros for MCF_MMU_MMUOR */ +#define MCF_MMU_MMUOR_UAA (0x1) +#define MCF_MMU_MMUOR_ACC (0x2) +#define MCF_MMU_MMUOR_RW (0x4) +#define MCF_MMU_MMUOR_ADR (0x8) +#define MCF_MMU_MMUOR_ITLB (0x10) +#define MCF_MMU_MMUOR_CAS (0x20) +#define MCF_MMU_MMUOR_CNL (0x40) +#define MCF_MMU_MMUOR_CA (0x80) +#define MCF_MMU_MMUOR_STLB (0x100) +#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_MMU_MMUSR */ +#define MCF_MMU_MMUSR_HIT (0x2) +#define MCF_MMU_MMUSR_WF (0x8) +#define MCF_MMU_MMUSR_RF (0x10) +#define MCF_MMU_MMUSR_SPF (0x20) + +/* Bit definitions and macros for MCF_MMU_MMUAR */ +#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MMU_MMUTR */ +#define MCF_MMU_MMUTR_V (0x1) +#define MCF_MMU_MMUTR_SG (0x2) +#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2) +#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA) + +/* Bit definitions and macros for MCF_MMU_MMUDR */ +#define MCF_MMU_MMUDR_LK (0x2) +#define MCF_MMU_MMUDR_X (0x4) +#define MCF_MMU_MMUDR_W (0x8) +#define MCF_MMU_MMUDR_R (0x10) +#define MCF_MMU_MMUDR_SP (0x20) +#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6) +#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8) +#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA) + + +#endif /* __MCF5475_MMU_H__ */ diff --git a/tos/pci_test/include/MCF5475_PAD.h b/tos/pci_test/include/MCF5475_PAD.h new file mode 100644 index 0000000..1d87e2e --- /dev/null +++ b/tos/pci_test/include/MCF5475_PAD.h @@ -0,0 +1,233 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PAD_H__ +#define __MCF5475_PAD_H__ + + +/********************************************************************* +* +* Common GPIO +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PAD_PAR_FBCTL (*(volatile uint16_t*)(&_MBAR[0xA40])) +#define MCF_PAD_PAR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA42])) +#define MCF_PAD_PAR_DMA (*(volatile uint8_t *)(&_MBAR[0xA43])) +#define MCF_PAD_PAR_FECI2CIRQ (*(volatile uint16_t*)(&_MBAR[0xA44])) +#define MCF_PAD_PAR_PCIBG (*(volatile uint16_t*)(&_MBAR[0xA48])) +#define MCF_PAD_PAR_PCIBR (*(volatile uint16_t*)(&_MBAR[0xA4A])) +#define MCF_PAD_PAR_PSC3 (*(volatile uint8_t *)(&_MBAR[0xA4C])) +#define MCF_PAD_PAR_PSC2 (*(volatile uint8_t *)(&_MBAR[0xA4D])) +#define MCF_PAD_PAR_PSC1 (*(volatile uint8_t *)(&_MBAR[0xA4E])) +#define MCF_PAD_PAR_PSC0 (*(volatile uint8_t *)(&_MBAR[0xA4F])) +#define MCF_PAD_PAR_DSPI (*(volatile uint16_t*)(&_MBAR[0xA50])) +#define MCF_PAD_PAR_TIMER (*(volatile uint8_t *)(&_MBAR[0xA52])) + + +/* Bit definitions and macros for MCF_PAD_PAR_FBCTL */ +#define MCF_PAD_PAR_FBCTL_PAR_ALE(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_FBCTL_PAR_ALE_GPIO (0) +#define MCF_PAD_PAR_FBCTL_PAR_ALE_TBST (0x2) +#define MCF_PAD_PAR_FBCTL_PAR_ALE_ALE (0x3) +#define MCF_PAD_PAR_FBCTL_PAR_TA (0x4) +#define MCF_PAD_PAR_FBCTL_PAR_RWB(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_FBCTL_PAR_RWB_GPIO (0) +#define MCF_PAD_PAR_FBCTL_PAR_RWB_TBST (0x20) +#define MCF_PAD_PAR_FBCTL_PAR_RWB_RW (0x30) +#define MCF_PAD_PAR_FBCTL_PAR_OE (0x40) +#define MCF_PAD_PAR_FBCTL_PAR_BWE0 (0x100) +#define MCF_PAD_PAR_FBCTL_PAR_BWE1 (0x400) +#define MCF_PAD_PAR_FBCTL_PAR_BWE2 (0x1000) +#define MCF_PAD_PAR_FBCTL_PAR_BWE3 (0x4000) + +/* Bit definitions and macros for MCF_PAD_PAR_FBCS */ +#define MCF_PAD_PAR_FBCS_PAR_CS1 (0x2) +#define MCF_PAD_PAR_FBCS_PAR_CS2 (0x4) +#define MCF_PAD_PAR_FBCS_PAR_CS3 (0x8) +#define MCF_PAD_PAR_FBCS_PAR_CS4 (0x10) +#define MCF_PAD_PAR_FBCS_PAR_CS5 (0x20) + +/* Bit definitions and macros for MCF_PAD_PAR_DMA */ +#define MCF_PAD_PAR_DMA_PAR_DREQ0(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_DMA_PAR_DREQ0_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DREQ0_TIN0 (0x2) +#define MCF_PAD_PAR_DMA_PAR_DREQ0_DREQ0 (0x3) +#define MCF_PAD_PAR_DMA_PAR_DREQ1(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_IRQ1 (0x4) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_TIN1 (0x8) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_DREQ1 (0xC) +#define MCF_PAD_PAR_DMA_PAR_DACK0(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_DMA_PAR_DACK0_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DACK0_TOUT0 (0x20) +#define MCF_PAD_PAR_DMA_PAR_DACK0_DACK0 (0x30) +#define MCF_PAD_PAR_DMA_PAR_DACK1(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_DMA_PAR_DACK1_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DACK1_TOUT1 (0x80) +#define MCF_PAD_PAR_DMA_PAR_DACK1_DACK1 (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_FECI2CIRQ */ +#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ5 (0x1) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ6 (0x2) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_SCL (0x4) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_SDA (0x8) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x80) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC (0xC0) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x200) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO (0x300) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MII (0x400) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E17 (0x800) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC (0x1000) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII (0x4000) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E07 (0x8000) + +/* Bit definitions and macros for MCF_PAD_PAR_PCIBG */ +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_TOUT0 (0x2) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0 (0x3) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_TOUT1 (0x8) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 (0xC) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_TOUT2 (0x20) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 (0x30) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_TOUT3 (0x80) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3 (0xC0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST (0x200) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4 (0x300) + +/* Bit definitions and macros for MCF_PAD_PAR_PCIBR */ +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_TIN0 (0x2) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0 (0x3) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_TIN1 (0x8) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 (0xC) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_TIN2 (0x20) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 (0x30) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_TIN3 (0x80) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3 (0xC0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4 (0x200) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4 (0x300) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC3 */ +#define MCF_PAD_PAR_PSC3_PAR_TXD3 (0x4) +#define MCF_PAD_PAR_PSC3_PAR_RXD3 (0x8) +#define MCF_PAD_PAR_PSC3_PAR_RTS3(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC3_PAR_RTS3_GPIO (0) +#define MCF_PAD_PAR_PSC3_PAR_RTS3_FSYNC (0x20) +#define MCF_PAD_PAR_PSC3_PAR_RTS3_RTS (0x30) +#define MCF_PAD_PAR_PSC3_PAR_CTS3(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC3_PAR_CTS3_GPIO (0) +#define MCF_PAD_PAR_PSC3_PAR_CTS3_BCLK (0x80) +#define MCF_PAD_PAR_PSC3_PAR_CTS3_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC2 */ +#define MCF_PAD_PAR_PSC2_PAR_TXD2 (0x4) +#define MCF_PAD_PAR_PSC2_PAR_RXD2 (0x8) +#define MCF_PAD_PAR_PSC2_PAR_RTS2(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC2_PAR_RTS2_GPIO (0) +#define MCF_PAD_PAR_PSC2_PAR_RTS2_FSYNC (0x20) +#define MCF_PAD_PAR_PSC2_PAR_RTS2_RTS (0x30) +#define MCF_PAD_PAR_PSC2_PAR_CTS2(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC2_PAR_CTS2_GPIO (0) +#define MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK (0x80) +#define MCF_PAD_PAR_PSC2_PAR_CTS2_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC1 */ +#define MCF_PAD_PAR_PSC1_PAR_TXD1 (0x4) +#define MCF_PAD_PAR_PSC1_PAR_RXD1 (0x8) +#define MCF_PAD_PAR_PSC1_PAR_RTS1(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC1_PAR_RTS1_GPIO (0) +#define MCF_PAD_PAR_PSC1_PAR_RTS1_FSYNC (0x20) +#define MCF_PAD_PAR_PSC1_PAR_RTS1_RTS (0x30) +#define MCF_PAD_PAR_PSC1_PAR_CTS1(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC1_PAR_CTS1_GPIO (0) +#define MCF_PAD_PAR_PSC1_PAR_CTS1_BCLK (0x80) +#define MCF_PAD_PAR_PSC1_PAR_CTS1_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC0 */ +#define MCF_PAD_PAR_PSC0_PAR_TXD0 (0x4) +#define MCF_PAD_PAR_PSC0_PAR_RXD0 (0x8) +#define MCF_PAD_PAR_PSC0_PAR_RTS0(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC0_PAR_RTS0_GPIO (0) +#define MCF_PAD_PAR_PSC0_PAR_RTS0_FSYNC (0x20) +#define MCF_PAD_PAR_PSC0_PAR_RTS0_RTS (0x30) +#define MCF_PAD_PAR_PSC0_PAR_CTS0(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC0_PAR_CTS0_GPIO (0) +#define MCF_PAD_PAR_PSC0_PAR_CTS0_BCLK (0x80) +#define MCF_PAD_PAR_PSC0_PAR_CTS0_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_DSPI */ +#define MCF_PAD_PAR_DSPI_PAR_SOUT(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_DSPI_PAR_SOUT_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_SOUT_TXD (0x2) +#define MCF_PAD_PAR_DSPI_PAR_SOUT_SOUT (0x3) +#define MCF_PAD_PAR_DSPI_PAR_SIN(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_DSPI_PAR_SIN_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_SIN_RXD (0x8) +#define MCF_PAD_PAR_DSPI_PAR_SIN_SIN (0xC) +#define MCF_PAD_PAR_DSPI_PAR_SCK(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_DSPI_PAR_SCK_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_SCK_BCLK (0x10) +#define MCF_PAD_PAR_DSPI_PAR_SCK_CTS (0x20) +#define MCF_PAD_PAR_DSPI_PAR_SCK_SCK (0x30) +#define MCF_PAD_PAR_DSPI_PAR_CS0(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_DSPI_PAR_CS0_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_CS0_FSYNC (0x40) +#define MCF_PAD_PAR_DSPI_PAR_CS0_RTS (0x80) +#define MCF_PAD_PAR_DSPI_PAR_CS0_DSPICS0 (0xC0) +#define MCF_PAD_PAR_DSPI_PAR_CS2(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_DSPI_PAR_CS2_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_CS2_TOUT2 (0x200) +#define MCF_PAD_PAR_DSPI_PAR_CS2_DSPICS2 (0x300) +#define MCF_PAD_PAR_DSPI_PAR_CS3(x) (((x)&0x3)<<0xA) +#define MCF_PAD_PAR_DSPI_PAR_CS3_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_CS3_TOUT3 (0x800) +#define MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3 (0xC00) +#define MCF_PAD_PAR_DSPI_PAR_CS5 (0x1000) + +/* Bit definitions and macros for MCF_PAD_PAR_TIMER */ +#define MCF_PAD_PAR_TIMER_PAR_TOUT2 (0x1) +#define MCF_PAD_PAR_TIMER_PAR_TIN2(x) (((x)&0x3)<<0x1) +#define MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2 (0x4) +#define MCF_PAD_PAR_TIMER_PAR_TIN2_TIN2 (0x6) +#define MCF_PAD_PAR_TIMER_PAR_TOUT3 (0x8) +#define MCF_PAD_PAR_TIMER_PAR_TIN3(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_TIMER_PAR_TIN3_IRQ3 (0x20) +#define MCF_PAD_PAR_TIMER_PAR_TIN3_TIN3 (0x30) + + +#endif /* __MCF5475_PAD_H__ */ diff --git a/tos/pci_test/include/MCF5475_PCI.h b/tos/pci_test/include/MCF5475_PCI.h new file mode 100644 index 0000000..3eb3341 --- /dev/null +++ b/tos/pci_test/include/MCF5475_PCI.h @@ -0,0 +1,376 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PCI_H__ +#define __MCF5475_PCI_H__ + + +/********************************************************************* +* +* PCI Bus Controller (PCI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PCI_PCIIDR (*(volatile uint32_t*)(&_MBAR[0xB00])) +#define MCF_PCI_PCISCR (*(volatile uint32_t*)(&_MBAR[0xB04])) +#define MCF_PCI_PCICCRIR (*(volatile uint32_t*)(&_MBAR[0xB08])) +#define MCF_PCI_PCICR1 (*(volatile uint32_t*)(&_MBAR[0xB0C])) +#define MCF_PCI_PCIBAR0 (*(volatile uint32_t*)(&_MBAR[0xB10])) +#define MCF_PCI_PCIBAR1 (*(volatile uint32_t*)(&_MBAR[0xB14])) +#define MCF_PCI_PCICCPR (*(volatile uint32_t*)(&_MBAR[0xB28])) +#define MCF_PCI_PCISID (*(volatile uint32_t*)(&_MBAR[0xB2C])) +#define MCF_PCI_PCICR2 (*(volatile uint32_t*)(&_MBAR[0xB3C])) +#define MCF_PCI_PCIGSCR (*(volatile uint32_t*)(&_MBAR[0xB60])) +#define MCF_PCI_PCITBATR0 (*(volatile uint32_t*)(&_MBAR[0xB64])) +#define MCF_PCI_PCITBATR1 (*(volatile uint32_t*)(&_MBAR[0xB68])) +#define MCF_PCI_PCITCR (*(volatile uint32_t*)(&_MBAR[0xB6C])) +#define MCF_PCI_PCIIW0BTAR (*(volatile uint32_t*)(&_MBAR[0xB70])) +#define MCF_PCI_PCIIW1BTAR (*(volatile uint32_t*)(&_MBAR[0xB74])) +#define MCF_PCI_PCIIW2BTAR (*(volatile uint32_t*)(&_MBAR[0xB78])) +#define MCF_PCI_PCIIWCR (*(volatile uint32_t*)(&_MBAR[0xB80])) +#define MCF_PCI_PCIICR (*(volatile uint32_t*)(&_MBAR[0xB84])) +#define MCF_PCI_PCIISR (*(volatile uint32_t*)(&_MBAR[0xB88])) +#define MCF_PCI_PCICAR (*(volatile uint32_t*)(&_MBAR[0xBF8])) +#define MCF_PCI_PCITPSR (*(volatile uint32_t*)(&_MBAR[0x8400])) +#define MCF_PCI_PCITSAR (*(volatile uint32_t*)(&_MBAR[0x8404])) +#define MCF_PCI_PCITTCR (*(volatile uint32_t*)(&_MBAR[0x8408])) +#define MCF_PCI_PCITER (*(volatile uint32_t*)(&_MBAR[0x840C])) +#define MCF_PCI_PCITNAR (*(volatile uint32_t*)(&_MBAR[0x8410])) +#define MCF_PCI_PCITLWR (*(volatile uint32_t*)(&_MBAR[0x8414])) +#define MCF_PCI_PCITDCR (*(volatile uint32_t*)(&_MBAR[0x8418])) +#define MCF_PCI_PCITSR (*(volatile uint32_t*)(&_MBAR[0x841C])) +#define MCF_PCI_PCITFDR (*(volatile uint32_t*)(&_MBAR[0x8440])) +#define MCF_PCI_PCITFSR (*(volatile uint32_t*)(&_MBAR[0x8444])) +#define MCF_PCI_PCITFCR (*(volatile uint32_t*)(&_MBAR[0x8448])) +#define MCF_PCI_PCITFAR (*(volatile uint32_t*)(&_MBAR[0x844C])) +#define MCF_PCI_PCITFRPR (*(volatile uint32_t*)(&_MBAR[0x8450])) +#define MCF_PCI_PCITFWPR (*(volatile uint32_t*)(&_MBAR[0x8454])) +#define MCF_PCI_PCIRPSR (*(volatile uint32_t*)(&_MBAR[0x8480])) +#define MCF_PCI_PCIRSAR (*(volatile uint32_t*)(&_MBAR[0x8484])) +#define MCF_PCI_PCIRTCR (*(volatile uint32_t*)(&_MBAR[0x8488])) +#define MCF_PCI_PCIRER (*(volatile uint32_t*)(&_MBAR[0x848C])) +#define MCF_PCI_PCIRNAR (*(volatile uint32_t*)(&_MBAR[0x8490])) +#define MCF_PCI_PCIRDCR (*(volatile uint32_t*)(&_MBAR[0x8498])) +#define MCF_PCI_PCIRSR (*(volatile uint32_t*)(&_MBAR[0x849C])) +#define MCF_PCI_PCIRFDR (*(volatile uint32_t*)(&_MBAR[0x84C0])) +#define MCF_PCI_PCIRFSR (*(volatile uint32_t*)(&_MBAR[0x84C4])) +#define MCF_PCI_PCIRFCR (*(volatile uint32_t*)(&_MBAR[0x84C8])) +#define MCF_PCI_PCIRFAR (*(volatile uint32_t*)(&_MBAR[0x84CC])) +#define MCF_PCI_PCIRFRPR (*(volatile uint32_t*)(&_MBAR[0x84D0])) +#define MCF_PCI_PCIRFWPR (*(volatile uint32_t*)(&_MBAR[0x84D4])) + + +/* Bit definitions and macros for MCF_PCI_PCIIDR */ +#define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCISCR */ +#define MCF_PCI_PCISCR_IO (0x1) +#define MCF_PCI_PCISCR_M (0x2) +#define MCF_PCI_PCISCR_B (0x4) +#define MCF_PCI_PCISCR_SP (0x8) +#define MCF_PCI_PCISCR_MW (0x10) +#define MCF_PCI_PCISCR_V (0x20) +#define MCF_PCI_PCISCR_PER (0x40) +#define MCF_PCI_PCISCR_ST (0x80) +#define MCF_PCI_PCISCR_S (0x100) +#define MCF_PCI_PCISCR_F (0x200) +#define MCF_PCI_PCISCR_C (0x100000) +#define MCF_PCI_PCISCR_66M (0x200000) +#define MCF_PCI_PCISCR_R (0x400000) +#define MCF_PCI_PCISCR_FC (0x800000) +#define MCF_PCI_PCISCR_DP (0x1000000) +#define MCF_PCI_PCISCR_DT(x) (((x)&0x3)<<0x19) +#define MCF_PCI_PCISCR_TS (0x8000000) +#define MCF_PCI_PCISCR_TR (0x10000000) +#define MCF_PCI_PCISCR_MA (0x20000000) +#define MCF_PCI_PCISCR_SE (0x40000000) +#define MCF_PCI_PCISCR_PE (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCICCRIR */ +#define MCF_PCI_PCICCRIR_REVISIONID(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0xFFFFFF)<<0x8) + +/* Bit definitions and macros for MCF_PCI_PCICR1 */ +#define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICR1_BIST(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIBAR0 */ +#define MCF_PCI_PCIBAR0_IOM (0x1) +#define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x3)<<0x1) +#define MCF_PCI_PCIBAR0_PREF (0x8) +#define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x3FFF)<<0x12) + +/* Bit definitions and macros for MCF_PCI_PCIBAR1 */ +#define MCF_PCI_PCIBAR1_IOM (0x1) +#define MCF_PCI_PCIBAR1_RANGE(x) (((x)&0x3)<<0x1) +#define MCF_PCI_PCIBAR1_PREF (0x8) +#define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_PCI_PCICCPR */ +#define MCF_PCI_PCICCPR_PCICCP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCISID */ +#define MCF_PCI_PCISID_VENDORID(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCICR2 */ +#define MCF_PCI_PCICR2_INTLINE(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICR2_INTPIN(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCICR2_MINGNT(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIGSCR */ +#define MCF_PCI_PCIGSCR_PR (0x1) +#define MCF_PCI_PCIGSCR_SEE (0x1000) +#define MCF_PCI_PCIGSCR_PEE (0x2000) +#define MCF_PCI_PCIGSCR_CLKINRESERVED(x) (((x)&0x7)<<0x10) +#define MCF_PCI_PCIGSCR_XLB2CLKIN(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCIGSCR_SE (0x10000000) +#define MCF_PCI_PCIGSCR_PE (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCITBATR0 */ +#define MCF_PCI_PCITBATR0_EN (0x1) +#define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x3FFF)<<0x12) + +/* Bit definitions and macros for MCF_PCI_PCITBATR1 */ +#define MCF_PCI_PCITBATR1_EN (0x1) +#define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_PCI_PCITCR */ +#define MCF_PCI_PCITCR_P (0x10000) +#define MCF_PCI_PCITCR_LD (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */ +#define MCF_PCI_PCIIW0BTAR_WTA0(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW0BTAR_WAM0(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW0BTAR_WBA0(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */ +#define MCF_PCI_PCIIW1BTAR_WTA1(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW1BTAR_WAM1(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW1BTAR_WBA1(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */ +#define MCF_PCI_PCIIW2BTAR_WTA2(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW2BTAR_WAM2(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW2BTAR_WBA2(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIWCR */ +#define MCF_PCI_PCIIWCR_WINCTRL2_E (0x100) +#define MCF_PCI_PCIIWCR_WINCTRL2_PRC(x) (((x)&0x3)<<0x9) +#define MCF_PCI_PCIIWCR_WINCTRL2_IOM (0x800) +#define MCF_PCI_PCIIWCR_WINCTRL1_E (0x10000) +#define MCF_PCI_PCIIWCR_WINCTRL1_PRC(x) (((x)&0x3)<<0x11) +#define MCF_PCI_PCIIWCR_WINCTRL1_IOM (0x80000) +#define MCF_PCI_PCIIWCR_WINCTRL0_E (0x1000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_PRC(x) (((x)&0x3)<<0x19) +#define MCF_PCI_PCIIWCR_WINCTRL0_IOM (0x8000000) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x100) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x300) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x500) +#define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x900) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x10000) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x30000) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x50000) +#define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x90000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x1000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x3000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x5000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x9000000) + +/* Bit definitions and macros for MCF_PCI_PCIICR */ +#define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCIICR_TAE (0x1000000) +#define MCF_PCI_PCIICR_IAE (0x2000000) +#define MCF_PCI_PCIICR_REE (0x4000000) + +/* Bit definitions and macros for MCF_PCI_PCIISR */ +#define MCF_PCI_PCIISR_TA (0x1000000) +#define MCF_PCI_PCIISR_IA (0x2000000) +#define MCF_PCI_PCIISR_RE (0x4000000) + +/* Bit definitions and macros for MCF_PCI_PCICAR */ +#define MCF_PCI_PCICAR_DWORD(x) (((x)&0x3F)<<0x2) +#define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x1F)<<0xB) +#define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICAR_E (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITPSR */ +#define MCF_PCI_PCITPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCITSAR */ +#define MCF_PCI_PCITSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITTCR */ +#define MCF_PCI_PCITTCR_DI (0x1) +#define MCF_PCI_PCITTCR_W (0x10) +#define MCF_PCI_PCITTCR_MAXBEATS(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCITTCR_MAXRETRY(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCITTCR_PCICMD(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCITER */ +#define MCF_PCI_PCITER_NE (0x10000) +#define MCF_PCI_PCITER_IAE (0x20000) +#define MCF_PCI_PCITER_TAE (0x40000) +#define MCF_PCI_PCITER_RE (0x80000) +#define MCF_PCI_PCITER_SE (0x100000) +#define MCF_PCI_PCITER_FEE (0x200000) +#define MCF_PCI_PCITER_ME (0x1000000) +#define MCF_PCI_PCITER_BE (0x8000000) +#define MCF_PCI_PCITER_CM (0x10000000) +#define MCF_PCI_PCITER_RF (0x40000000) +#define MCF_PCI_PCITER_RC (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITNAR */ +#define MCF_PCI_PCITNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITLWR */ +#define MCF_PCI_PCITLWR_LASTWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITDCR */ +#define MCF_PCI_PCITDCR_PKTSDONE(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCITDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCITSR */ +#define MCF_PCI_PCITSR_IA (0x10000) +#define MCF_PCI_PCITSR_TA (0x20000) +#define MCF_PCI_PCITSR_RE (0x40000) +#define MCF_PCI_PCITSR_SE (0x80000) +#define MCF_PCI_PCITSR_FE (0x100000) +#define MCF_PCI_PCITSR_BE1 (0x200000) +#define MCF_PCI_PCITSR_BE2 (0x400000) +#define MCF_PCI_PCITSR_BE3 (0x800000) +#define MCF_PCI_PCITSR_NT (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCITFDR */ +#define MCF_PCI_PCITFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFSR */ +#define MCF_PCI_PCITFSR_EMPTY (0x10000) +#define MCF_PCI_PCITFSR_ALARM (0x20000) +#define MCF_PCI_PCITFSR_FULL (0x40000) +#define MCF_PCI_PCITFSR_FR (0x80000) +#define MCF_PCI_PCITFSR_OF (0x100000) +#define MCF_PCI_PCITFSR_UF (0x200000) +#define MCF_PCI_PCITFSR_RXW (0x400000) +#define MCF_PCI_PCITFSR_FAE (0x800000) +#define MCF_PCI_PCITFSR_TXW (0x40000000) +#define MCF_PCI_PCITFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITFCR */ +#define MCF_PCI_PCITFCR_TXW_MASK (0x40000) +#define MCF_PCI_PCITFCR_OF_MASK (0x80000) +#define MCF_PCI_PCITFCR_UF_MASK (0x100000) +#define MCF_PCI_PCITFCR_RXW_MASK (0x200000) +#define MCF_PCI_PCITFCR_FAE_MASK (0x400000) +#define MCF_PCI_PCITFCR_IP_MASK (0x800000) +#define MCF_PCI_PCITFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCITFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCITFAR */ +#define MCF_PCI_PCITFAR_ALARM(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFRPR */ +#define MCF_PCI_PCITFRPR_READPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFWPR */ +#define MCF_PCI_PCITFWPR_WRITEPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRPSR */ +#define MCF_PCI_PCIRPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCIRSAR */ +#define MCF_PCI_PCIRSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRTCR */ +#define MCF_PCI_PCIRTCR_DI (0x1) +#define MCF_PCI_PCIRTCR_W (0x10) +#define MCF_PCI_PCIRTCR_MAXBEATS(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCIRTCR_FB (0x1000) +#define MCF_PCI_PCIRTCR_MAXRETRY(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIRTCR_PCICMD(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIRER */ +#define MCF_PCI_PCIRER_NE (0x10000) +#define MCF_PCI_PCIRER_IAE (0x20000) +#define MCF_PCI_PCIRER_TAE (0x40000) +#define MCF_PCI_PCIRER_RE (0x80000) +#define MCF_PCI_PCIRER_SE (0x100000) +#define MCF_PCI_PCIRER_FEE (0x200000) +#define MCF_PCI_PCIRER_ME (0x1000000) +#define MCF_PCI_PCIRER_BE (0x8000000) +#define MCF_PCI_PCIRER_CM (0x10000000) +#define MCF_PCI_PCIRER_FE (0x20000000) +#define MCF_PCI_PCIRER_RF (0x40000000) +#define MCF_PCI_PCIRER_RC (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCIRNAR */ +#define MCF_PCI_PCIRNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRDCR */ +#define MCF_PCI_PCIRDCR_PKTSDONE(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCIRDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCIRSR */ +#define MCF_PCI_PCIRSR_IA (0x10000) +#define MCF_PCI_PCIRSR_TA (0x20000) +#define MCF_PCI_PCIRSR_RE (0x40000) +#define MCF_PCI_PCIRSR_SE (0x80000) +#define MCF_PCI_PCIRSR_FE (0x100000) +#define MCF_PCI_PCIRSR_BE1 (0x200000) +#define MCF_PCI_PCIRSR_BE2 (0x400000) +#define MCF_PCI_PCIRSR_BE3 (0x800000) +#define MCF_PCI_PCIRSR_NT (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFDR */ +#define MCF_PCI_PCIRFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFSR */ +#define MCF_PCI_PCIRFSR_EMPTY (0x10000) +#define MCF_PCI_PCIRFSR_ALARM (0x20000) +#define MCF_PCI_PCIRFSR_FULL (0x40000) +#define MCF_PCI_PCIRFSR_FR (0x80000) +#define MCF_PCI_PCIRFSR_OF (0x100000) +#define MCF_PCI_PCIRFSR_UF (0x200000) +#define MCF_PCI_PCIRFSR_RXW (0x400000) +#define MCF_PCI_PCIRFSR_FAE (0x800000) +#define MCF_PCI_PCIRFSR_TXW (0x40000000) +#define MCF_PCI_PCIRFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFCR */ +#define MCF_PCI_PCIRFCR_TXW_MASK (0x40000) +#define MCF_PCI_PCIRFCR_OF_MASK (0x80000) +#define MCF_PCI_PCIRFCR_UF_MASK (0x100000) +#define MCF_PCI_PCIRFCR_RXW_MASK (0x200000) +#define MCF_PCI_PCIRFCR_FAE_MASK (0x400000) +#define MCF_PCI_PCIRFCR_IP_MASK (0x800000) +#define MCF_PCI_PCIRFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCIRFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFAR */ +#define MCF_PCI_PCIRFAR_ALARM(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFRPR */ +#define MCF_PCI_PCIRFRPR_READPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFWPR */ +#define MCF_PCI_PCIRFWPR_WRITEPTR(x) (((x)&0x7F)<<0) + + +#endif /* __MCF5475_PCI_H__ */ diff --git a/tos/pci_test/include/MCF5475_PCIARB.h b/tos/pci_test/include/MCF5475_PCIARB.h new file mode 100644 index 0000000..9e8c05b --- /dev/null +++ b/tos/pci_test/include/MCF5475_PCIARB.h @@ -0,0 +1,43 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PCIARB_H__ +#define __MCF5475_PCIARB_H__ + + +/********************************************************************* +* +* PCI Bus Arbiter Module (PCIARB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PCIARB_PACR (*(volatile uint32_t*)(&_MBAR[0xC00])) +#define MCF_PCIARB_PASR (*(volatile uint32_t*)(&_MBAR[0xC04])) + + +/* Bit definitions and macros for MCF_PCIARB_PACR */ +#define MCF_PCIARB_PACR_INTMPRI (0x1) +#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x1F)<<0x1) +#define MCF_PCIARB_PACR_INTMINTEN (0x10000) +#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x1F)<<0x11) +#define MCF_PCIARB_PACR_DS (0x80000000) + +/* Bit definitions and macros for MCF_PCIARB_PASR */ +#define MCF_PCIARB_PASR_ITLMBK (0x10000) +#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x1F)<<0x11) + + +#endif /* __MCF5475_PCIARB_H__ */ diff --git a/tos/pci_test/include/MCF5475_PSC.h b/tos/pci_test/include/MCF5475_PSC.h new file mode 100644 index 0000000..ffa9f3e --- /dev/null +++ b/tos/pci_test/include/MCF5475_PSC.h @@ -0,0 +1,527 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PSC_H__ +#define __MCF5475_PSC_H__ + + +/********************************************************************* +* +* Programmable Serial Controller (PSC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PSC0_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8600])) +#define MCF_PSC0_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8600])) +#define MCF_PSC0_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8604])) +#define MCF_PSC0_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8604])) +#define MCF_PSC0_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8608])) +#define MCF_PSC0_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8610])) +#define MCF_PSC0_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8610])) +#define MCF_PSC0_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8614])) +#define MCF_PSC0_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8614])) +#define MCF_PSC0_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8618])) +#define MCF_PSC0_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x861C])) +#define MCF_PSC0_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8634])) +#define MCF_PSC0_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8638])) +#define MCF_PSC0_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x863C])) +#define MCF_PSC0_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8640])) +#define MCF_PSC0_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8644])) +#define MCF_PSC0_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8648])) +#define MCF_PSC0_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x864C])) +#define MCF_PSC0_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8650])) +#define MCF_PSC0_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8654])) +#define MCF_PSC0_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8658])) +#define MCF_PSC0_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x865C])) +#define MCF_PSC0_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8660])) +#define MCF_PSC0_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8664])) +#define MCF_PSC0_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8668])) +#define MCF_PSC0_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x866E])) +#define MCF_PSC0_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8672])) +#define MCF_PSC0_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8676])) +#define MCF_PSC0_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x867A])) +#define MCF_PSC0_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x867E])) +#define MCF_PSC0_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8680])) +#define MCF_PSC0_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8684])) +#define MCF_PSC0_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8688])) +#define MCF_PSC0_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x868E])) +#define MCF_PSC0_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8692])) +#define MCF_PSC0_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8696])) +#define MCF_PSC0_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x869A])) +#define MCF_PSC0_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x869E])) + +#define MCF_PSC1_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8700])) +#define MCF_PSC1_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8700])) +#define MCF_PSC1_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8704])) +#define MCF_PSC1_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8704])) +#define MCF_PSC1_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8708])) +#define MCF_PSC1_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8710])) +#define MCF_PSC1_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8710])) +#define MCF_PSC1_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8714])) +#define MCF_PSC1_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8714])) +#define MCF_PSC1_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8718])) +#define MCF_PSC1_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x871C])) +#define MCF_PSC1_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8734])) +#define MCF_PSC1_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8738])) +#define MCF_PSC1_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x873C])) +#define MCF_PSC1_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8740])) +#define MCF_PSC1_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8744])) +#define MCF_PSC1_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8748])) +#define MCF_PSC1_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x874C])) +#define MCF_PSC1_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8750])) +#define MCF_PSC1_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8754])) +#define MCF_PSC1_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8758])) +#define MCF_PSC1_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x875C])) +#define MCF_PSC1_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8760])) +#define MCF_PSC1_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8764])) +#define MCF_PSC1_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8768])) +#define MCF_PSC1_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x876E])) +#define MCF_PSC1_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8772])) +#define MCF_PSC1_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8776])) +#define MCF_PSC1_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x877A])) +#define MCF_PSC1_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x877E])) +#define MCF_PSC1_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8780])) +#define MCF_PSC1_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8784])) +#define MCF_PSC1_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8788])) +#define MCF_PSC1_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x878E])) +#define MCF_PSC1_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8792])) +#define MCF_PSC1_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8796])) +#define MCF_PSC1_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x879A])) +#define MCF_PSC1_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x879E])) + +#define MCF_PSC2_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8800])) +#define MCF_PSC2_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8800])) +#define MCF_PSC2_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8804])) +#define MCF_PSC2_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8804])) +#define MCF_PSC2_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8808])) +#define MCF_PSC2_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8810])) +#define MCF_PSC2_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8810])) +#define MCF_PSC2_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8814])) +#define MCF_PSC2_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8814])) +#define MCF_PSC2_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8818])) +#define MCF_PSC2_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x881C])) +#define MCF_PSC2_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8834])) +#define MCF_PSC2_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8838])) +#define MCF_PSC2_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x883C])) +#define MCF_PSC2_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8840])) +#define MCF_PSC2_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8844])) +#define MCF_PSC2_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8848])) +#define MCF_PSC2_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x884C])) +#define MCF_PSC2_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8850])) +#define MCF_PSC2_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8854])) +#define MCF_PSC2_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8858])) +#define MCF_PSC2_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x885C])) +#define MCF_PSC2_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8860])) +#define MCF_PSC2_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8864])) +#define MCF_PSC2_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8868])) +#define MCF_PSC2_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x886E])) +#define MCF_PSC2_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8872])) +#define MCF_PSC2_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8876])) +#define MCF_PSC2_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x887A])) +#define MCF_PSC2_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x887E])) +#define MCF_PSC2_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8880])) +#define MCF_PSC2_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8884])) +#define MCF_PSC2_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8888])) +#define MCF_PSC2_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x888E])) +#define MCF_PSC2_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8892])) +#define MCF_PSC2_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8896])) +#define MCF_PSC2_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x889A])) +#define MCF_PSC2_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x889E])) + +#define MCF_PSC3_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8900])) +#define MCF_PSC3_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8900])) +#define MCF_PSC3_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8904])) +#define MCF_PSC3_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8904])) +#define MCF_PSC3_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8908])) +#define MCF_PSC3_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8910])) +#define MCF_PSC3_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8910])) +#define MCF_PSC3_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8914])) +#define MCF_PSC3_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8914])) +#define MCF_PSC3_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8918])) +#define MCF_PSC3_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x891C])) +#define MCF_PSC3_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8934])) +#define MCF_PSC3_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8938])) +#define MCF_PSC3_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x893C])) +#define MCF_PSC3_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8940])) +#define MCF_PSC3_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8944])) +#define MCF_PSC3_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8948])) +#define MCF_PSC3_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x894C])) +#define MCF_PSC3_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8950])) +#define MCF_PSC3_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8954])) +#define MCF_PSC3_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8958])) +#define MCF_PSC3_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x895C])) +#define MCF_PSC3_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8960])) +#define MCF_PSC3_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8964])) +#define MCF_PSC3_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8968])) +#define MCF_PSC3_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x896E])) +#define MCF_PSC3_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8972])) +#define MCF_PSC3_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8976])) +#define MCF_PSC3_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x897A])) +#define MCF_PSC3_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x897E])) +#define MCF_PSC3_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8980])) +#define MCF_PSC3_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8984])) +#define MCF_PSC3_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8988])) +#define MCF_PSC3_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x898E])) +#define MCF_PSC3_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8992])) +#define MCF_PSC3_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8996])) +#define MCF_PSC3_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x899A])) +#define MCF_PSC3_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x899E])) + +#define MCF_PSC_PSCMR(x) (*(volatile uint8_t *)(&_MBAR[0x8600 + ((x)*0x100)])) +#define MCF_PSC_PSCCSR(x) (*(volatile uint8_t *)(&_MBAR[0x8604 + ((x)*0x100)])) +#define MCF_PSC_PSCSR(x) (*(volatile uint16_t*)(&_MBAR[0x8604 + ((x)*0x100)])) +#define MCF_PSC_PSCCR(x) (*(volatile uint8_t *)(&_MBAR[0x8608 + ((x)*0x100)])) +#define MCF_PSC_PSCRB_8BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_8BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCRB_16BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_16BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCRB_AC97(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_AC97(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCIPCR(x) (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)])) +#define MCF_PSC_PSCACR(x) (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)])) +#define MCF_PSC_PSCIMR(x) (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)])) +#define MCF_PSC_PSCISR(x) (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)])) +#define MCF_PSC_PSCCTUR(x) (*(volatile uint8_t *)(&_MBAR[0x8618 + ((x)*0x100)])) +#define MCF_PSC_PSCCTLR(x) (*(volatile uint8_t *)(&_MBAR[0x861C + ((x)*0x100)])) +#define MCF_PSC_PSCIP(x) (*(volatile uint8_t *)(&_MBAR[0x8634 + ((x)*0x100)])) +#define MCF_PSC_PSCOPSET(x) (*(volatile uint8_t *)(&_MBAR[0x8638 + ((x)*0x100)])) +#define MCF_PSC_PSCOPRESET(x) (*(volatile uint8_t *)(&_MBAR[0x863C + ((x)*0x100)])) +#define MCF_PSC_PSCSICR(x) (*(volatile uint8_t *)(&_MBAR[0x8640 + ((x)*0x100)])) +#define MCF_PSC_PSCIRCR1(x) (*(volatile uint8_t *)(&_MBAR[0x8644 + ((x)*0x100)])) +#define MCF_PSC_PSCIRCR2(x) (*(volatile uint8_t *)(&_MBAR[0x8648 + ((x)*0x100)])) +#define MCF_PSC_PSCIRSDR(x) (*(volatile uint8_t *)(&_MBAR[0x864C + ((x)*0x100)])) +#define MCF_PSC_PSCIRMDR(x) (*(volatile uint8_t *)(&_MBAR[0x8650 + ((x)*0x100)])) +#define MCF_PSC_PSCIRFDR(x) (*(volatile uint8_t *)(&_MBAR[0x8654 + ((x)*0x100)])) +#define MCF_PSC_PSCRFCNT(x) (*(volatile uint16_t*)(&_MBAR[0x8658 + ((x)*0x100)])) +#define MCF_PSC_PSCTFCNT(x) (*(volatile uint16_t*)(&_MBAR[0x865C + ((x)*0x100)])) +#define MCF_PSC_PSCRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8660 + ((x)*0x100)])) +#define MCF_PSC_PSCRFSR(x) (*(volatile uint16_t*)(&_MBAR[0x8664 + ((x)*0x100)])) +#define MCF_PSC_PSCRFCR(x) (*(volatile uint32_t*)(&_MBAR[0x8668 + ((x)*0x100)])) +#define MCF_PSC_PSCRFAR(x) (*(volatile uint16_t*)(&_MBAR[0x866E + ((x)*0x100)])) +#define MCF_PSC_PSCRFRP(x) (*(volatile uint16_t*)(&_MBAR[0x8672 + ((x)*0x100)])) +#define MCF_PSC_PSCRFWP(x) (*(volatile uint16_t*)(&_MBAR[0x8676 + ((x)*0x100)])) +#define MCF_PSC_PSCRLRFP(x) (*(volatile uint16_t*)(&_MBAR[0x867A + ((x)*0x100)])) +#define MCF_PSC_PSCRLWFP(x) (*(volatile uint16_t*)(&_MBAR[0x867E + ((x)*0x100)])) +#define MCF_PSC_PSCTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8680 + ((x)*0x100)])) +#define MCF_PSC_PSCTFSR(x) (*(volatile uint16_t*)(&_MBAR[0x8684 + ((x)*0x100)])) +#define MCF_PSC_PSCTFCR(x) (*(volatile uint32_t*)(&_MBAR[0x8688 + ((x)*0x100)])) +#define MCF_PSC_PSCTFAR(x) (*(volatile uint16_t*)(&_MBAR[0x868E + ((x)*0x100)])) +#define MCF_PSC_PSCTFRP(x) (*(volatile uint16_t*)(&_MBAR[0x8692 + ((x)*0x100)])) +#define MCF_PSC_PSCTFWP(x) (*(volatile uint16_t*)(&_MBAR[0x8696 + ((x)*0x100)])) +#define MCF_PSC_PSCTLRFP(x) (*(volatile uint16_t*)(&_MBAR[0x869A + ((x)*0x100)])) +#define MCF_PSC_PSCTLWFP(x) (*(volatile uint16_t*)(&_MBAR[0x869E + ((x)*0x100)])) + +/* Bit definitions and macros for MCF_PSC_PSCMR */ +#define MCF_PSC_PSCMR_SB(x) (((x)&0xF)<<0) +#define MCF_PSC_PSCMR_TXCTS (0x10) +#define MCF_PSC_PSCMR_TXRTS (0x20) +#define MCF_PSC_PSCMR_CM(x) (((x)&0x3)<<0x6) +#define MCF_PSC_PSCMR_CM_NORMAL (0) +#define MCF_PSC_PSCMR_CM_ECHO (0x40) +#define MCF_PSC_PSCMR_CM_LOCAL_LOOP (0x80) +#define MCF_PSC_PSCMR_CM_REMOTE_LOOP (0xC0) +#define MCF_PSC_PSCMR_SB_STOP_BITS_1 (0x7) +#define MCF_PSC_PSCMR_SB_STOP_BITS_15 (0x8) +#define MCF_PSC_PSCMR_SB_STOP_BITS_2 (0xF) +#define MCF_PSC_PSCMR_PM_MULTI_ADDR (0x1C) +#define MCF_PSC_PSCMR_PM_MULTI_DATA (0x18) +#define MCF_PSC_PSCMR_PM_NONE (0x10) +#define MCF_PSC_PSCMR_PM_FORCE_HI (0xC) +#define MCF_PSC_PSCMR_PM_FORCE_LO (0x8) +#define MCF_PSC_PSCMR_PM_ODD (0x4) +#define MCF_PSC_PSCMR_PM_EVEN (0) +#define MCF_PSC_PSCMR_BC(x) (((x)&0x3)<<0) +#define MCF_PSC_PSCMR_BC_5 (0) +#define MCF_PSC_PSCMR_BC_6 (0x1) +#define MCF_PSC_PSCMR_BC_7 (0x2) +#define MCF_PSC_PSCMR_BC_8 (0x3) +#define MCF_PSC_PSCMR_PT (0x4) +#define MCF_PSC_PSCMR_PM(x) (((x)&0x3)<<0x3) +#define MCF_PSC_PSCMR_ERR (0x20) +#define MCF_PSC_PSCMR_RXIRQ_FU (0x40) +#define MCF_PSC_PSCMR_RXRTS (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCCSR */ +#define MCF_PSC_PSCCSR_TCSEL(x) (((x)&0xF)<<0) +#define MCF_PSC_PSCCSR_RCSEL(x) (((x)&0xF)<<0x4) +#define MCF_PSC_PSCCSR_TCSEL_SYS_CLK (0x0D) +#define MCF_PSC_PSCCSR_TCSEL_CTM16 (0x0E) +#define MCF_PSC_PSCCSR_TCSEL_CTM (0x0F) +#define MCF_PSC_PSCCSR_RCSEL_SYS_CLK (0xD0) +#define MCF_PSC_PSCCSR_RCSEL_CTM16 (0xE0) +#define MCF_PSC_PSCCSR_RCSEL_CTM (0xF0) + +/* Bit definitions and macros for MCF_PSC_PSCSR */ +#define MCF_PSC_PSCSR_ERR (0x40) +#define MCF_PSC_PSCSR_CDE_DEOF (0x80) +#define MCF_PSC_PSCSR_RXRDY (0x100) +#define MCF_PSC_PSCSR_FU (0x200) +#define MCF_PSC_PSCSR_TXRDY (0x400) +#define MCF_PSC_PSCSR_TXEMP_URERR (0x800) +#define MCF_PSC_PSCSR_OE (0x1000) +#define MCF_PSC_PSCSR_PE_CRCERR (0x2000) +#define MCF_PSC_PSCSR_FE_PHYERR (0x4000) +#define MCF_PSC_PSCSR_RB_NEOF (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCCR */ +#define MCF_PSC_PSCCR_RXC(x) (((x)&0x3)<<0) +#define MCF_PSC_PSCCR_RX_ENABLED (0x1) +#define MCF_PSC_PSCCR_RX_DISABLED (0x2) +#define MCF_PSC_PSCCR_TXC(x) (((x)&0x3)<<0x2) +#define MCF_PSC_PSCCR_TX_ENABLED (0x4) +#define MCF_PSC_PSCCR_TX_DISABLED (0x8) +#define MCF_PSC_PSCCR_MISC(x) (((x)&0x7)<<0x4) +#define MCF_PSC_PSCCR_NONE (0) +#define MCF_PSC_PSCCR_RESET_MR (0x10) +#define MCF_PSC_PSCCR_RESET_RX (0x20) +#define MCF_PSC_PSCCR_RESET_TX (0x30) +#define MCF_PSC_PSCCR_RESET_ERROR (0x40) +#define MCF_PSC_PSCCR_RESET_BKCHGINT (0x50) +#define MCF_PSC_PSCCR_START_BREAK (0x60) +#define MCF_PSC_PSCCR_STOP_BREAK (0x70) + +/* Bit definitions and macros for MCF_PSC_PSCRB_8BIT */ +#define MCF_PSC_PSCRB_8BIT_RB3(x) (((x)&0xFF)<<0) +#define MCF_PSC_PSCRB_8BIT_RB2(x) (((x)&0xFF)<<0x8) +#define MCF_PSC_PSCRB_8BIT_RB1(x) (((x)&0xFF)<<0x10) +#define MCF_PSC_PSCRB_8BIT_RB0(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PSC_PSCTB_8BIT */ +#define MCF_PSC_PSCTB_8BIT_TB3(x) (((x)&0xFF)<<0) +#define MCF_PSC_PSCTB_8BIT_TB2(x) (((x)&0xFF)<<0x8) +#define MCF_PSC_PSCTB_8BIT_TB1(x) (((x)&0xFF)<<0x10) +#define MCF_PSC_PSCTB_8BIT_TB0(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PSC_PSCRB_16BIT */ +#define MCF_PSC_PSCRB_16BIT_RB1(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCRB_16BIT_RB0(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PSC_PSCTB_16BIT */ +#define MCF_PSC_PSCTB_16BIT_TB1(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCTB_16BIT_TB0(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PSC_PSCRB_AC97 */ +#define MCF_PSC_PSCRB_AC97_SOF (0x800) +#define MCF_PSC_PSCRB_AC97_RB(x) (((x)&0xFFFFF)<<0xC) + +/* Bit definitions and macros for MCF_PSC_PSCTB_AC97 */ +#define MCF_PSC_PSCTB_AC97_TB(x) (((x)&0xFFFFF)<<0xC) + +/* Bit definitions and macros for MCF_PSC_PSCIPCR */ +#define MCF_PSC_PSCIPCR_RESERVED (0xC) +#define MCF_PSC_PSCIPCR_CTS (0xD) +#define MCF_PSC_PSCIPCR_D_CTS (0x1C) +#define MCF_PSC_PSCIPCR_SYNC (0x8C) + +/* Bit definitions and macros for MCF_PSC_PSCACR */ +#define MCF_PSC_PSCACR_IEC0 (0x1) + +/* Bit definitions and macros for MCF_PSC_PSCIMR */ +#define MCF_PSC_PSCIMR_ERR (0x40) +#define MCF_PSC_PSCIMR_DEOF (0x80) +#define MCF_PSC_PSCIMR_TXRDY (0x100) +#define MCF_PSC_PSCIMR_RXRDY_FU (0x200) +#define MCF_PSC_PSCIMR_DB (0x400) +#define MCF_PSC_PSCIMR_IPC (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCISR */ +#define MCF_PSC_PSCISR_ERR (0x40) +#define MCF_PSC_PSCISR_DEOF (0x80) +#define MCF_PSC_PSCISR_TXRDY (0x100) +#define MCF_PSC_PSCISR_RXRDY_FU (0x200) +#define MCF_PSC_PSCISR_DB (0x400) +#define MCF_PSC_PSCISR_IPC (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCCTUR */ +#define MCF_PSC_PSCCTUR_CT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCCTLR */ +#define MCF_PSC_PSCCTLR_CT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCIP */ +#define MCF_PSC_PSCIP_CTS (0x1) +#define MCF_PSC_PSCIP_TGL (0x40) +#define MCF_PSC_PSCIP_LPWR_B (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCOPSET */ +#define MCF_PSC_PSCOPSET_RTS (0x1) + +/* Bit definitions and macros for MCF_PSC_PSCOPRESET */ +#define MCF_PSC_PSCOPRESET_RTS (0x1) + +/* Bit definitions and macros for MCF_PSC_PSCSICR */ +#define MCF_PSC_PSCSICR_SIM(x) (((x)&0x7)<<0) +#define MCF_PSC_PSCSICR_SIM_UART (0) +#define MCF_PSC_PSCSICR_SIM_MODEM8 (0x1) +#define MCF_PSC_PSCSICR_SIM_MODEM16 (0x2) +#define MCF_PSC_PSCSICR_SIM_AC97 (0x3) +#define MCF_PSC_PSCSICR_SIM_SIR (0x4) +#define MCF_PSC_PSCSICR_SIM_MIR (0x5) +#define MCF_PSC_PSCSICR_SIM_FIR (0x6) +#define MCF_PSC_PSCSICR_SHDIR (0x10) +#define MCF_PSC_PSCSICR_DTS1 (0x20) +#define MCF_PSC_PSCSICR_AWR (0x40) +#define MCF_PSC_PSCSICR_ACRB (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCIRCR1 */ +#define MCF_PSC_PSCIRCR1_SPUL (0x1) +#define MCF_PSC_PSCIRCR1_SIPEN (0x2) +#define MCF_PSC_PSCIRCR1_FD (0x4) + +/* Bit definitions and macros for MCF_PSC_PSCIRCR2 */ +#define MCF_PSC_PSCIRCR2_NXTEOF (0x1) +#define MCF_PSC_PSCIRCR2_ABORT (0x2) +#define MCF_PSC_PSCIRCR2_SIPREQ (0x4) + +/* Bit definitions and macros for MCF_PSC_PSCIRSDR */ +#define MCF_PSC_PSCIRSDR_IRSTIM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCIRMDR */ +#define MCF_PSC_PSCIRMDR_M_FDIV(x) (((x)&0x7F)<<0) +#define MCF_PSC_PSCIRMDR_FREQ (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCIRFDR */ +#define MCF_PSC_PSCIRFDR_F_FDIV(x) (((x)&0xF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFCNT */ +#define MCF_PSC_PSCRFCNT_CNT(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFCNT */ +#define MCF_PSC_PSCTFCNT_CNT(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFDR */ +#define MCF_PSC_PSCRFDR_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFSR */ +#define MCF_PSC_PSCRFSR_EMT (0x1) +#define MCF_PSC_PSCRFSR_ALARM (0x2) +#define MCF_PSC_PSCRFSR_FU (0x4) +#define MCF_PSC_PSCRFSR_FRMRDY (0x8) +#define MCF_PSC_PSCRFSR_OF (0x10) +#define MCF_PSC_PSCRFSR_UF (0x20) +#define MCF_PSC_PSCRFSR_RXW (0x40) +#define MCF_PSC_PSCRFSR_FAE (0x80) +#define MCF_PSC_PSCRFSR_FRM(x) (((x)&0xF)<<0x8) +#define MCF_PSC_PSCRFSR_FRM_BYTE0 (0x800) +#define MCF_PSC_PSCRFSR_FRM_BYTE1 (0x400) +#define MCF_PSC_PSCRFSR_FRM_BYTE2 (0x200) +#define MCF_PSC_PSCRFSR_FRM_BYTE3 (0x100) +#define MCF_PSC_PSCRFSR_TAG(x) (((x)&0x3)<<0xC) +#define MCF_PSC_PSCRFSR_TXW (0x4000) +#define MCF_PSC_PSCRFSR_IP (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCRFCR */ +#define MCF_PSC_PSCRFCR_CNTR(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCRFCR_TXW_MSK (0x40000) +#define MCF_PSC_PSCRFCR_OF_MSK (0x80000) +#define MCF_PSC_PSCRFCR_UF_MSK (0x100000) +#define MCF_PSC_PSCRFCR_RXW_MSK (0x200000) +#define MCF_PSC_PSCRFCR_FAE_MSK (0x400000) +#define MCF_PSC_PSCRFCR_IP_MSK (0x800000) +#define MCF_PSC_PSCRFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PSC_PSCRFCR_FRMEN (0x8000000) +#define MCF_PSC_PSCRFCR_TIMER (0x10000000) + +/* Bit definitions and macros for MCF_PSC_PSCRFAR */ +#define MCF_PSC_PSCRFAR_ALARM(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFRP */ +#define MCF_PSC_PSCRFRP_READ(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFWP */ +#define MCF_PSC_PSCRFWP_WRITE(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRLRFP */ +#define MCF_PSC_PSCRLRFP_LRFP(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRLWFP */ +#define MCF_PSC_PSCRLWFP_LWFP(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFDR */ +#define MCF_PSC_PSCTFDR_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFSR */ +#define MCF_PSC_PSCTFSR_EMT (0x1) +#define MCF_PSC_PSCTFSR_ALARM (0x2) +#define MCF_PSC_PSCTFSR_FU (0x4) +#define MCF_PSC_PSCTFSR_FRMRDY (0x8) +#define MCF_PSC_PSCTFSR_OF (0x10) +#define MCF_PSC_PSCTFSR_UF (0x20) +#define MCF_PSC_PSCTFSR_RXW (0x40) +#define MCF_PSC_PSCTFSR_FAE (0x80) +#define MCF_PSC_PSCTFSR_FRM(x) (((x)&0xF)<<0x8) +#define MCF_PSC_PSCTFSR_FRM_BYTE0 (0x800) +#define MCF_PSC_PSCTFSR_FRM_BYTE1 (0x400) +#define MCF_PSC_PSCTFSR_FRM_BYTE2 (0x200) +#define MCF_PSC_PSCTFSR_FRM_BYTE3 (0x100) +#define MCF_PSC_PSCTFSR_TAG(x) (((x)&0x3)<<0xC) +#define MCF_PSC_PSCTFSR_TXW (0x4000) +#define MCF_PSC_PSCTFSR_IP (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCTFCR */ +#define MCF_PSC_PSCTFCR_CNTR(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCTFCR_TXW_MSK (0x40000) +#define MCF_PSC_PSCTFCR_OF_MSK (0x80000) +#define MCF_PSC_PSCTFCR_UF_MSK (0x100000) +#define MCF_PSC_PSCTFCR_RXW_MSK (0x200000) +#define MCF_PSC_PSCTFCR_FAE_MSK (0x400000) +#define MCF_PSC_PSCTFCR_IP_MSK (0x800000) +#define MCF_PSC_PSCTFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PSC_PSCTFCR_FRMEN (0x8000000) +#define MCF_PSC_PSCTFCR_TIMER (0x10000000) +#define MCF_PSC_PSCTFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PSC_PSCTFAR */ +#define MCF_PSC_PSCTFAR_ALARM(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFRP */ +#define MCF_PSC_PSCTFRP_READ(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFWP */ +#define MCF_PSC_PSCTFWP_WRITE(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTLRFP */ +#define MCF_PSC_PSCTLRFP_LRFP(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTLWFP */ +#define MCF_PSC_PSCTLWFP_LWFP(x) (((x)&0x1FF)<<0) + + +#endif /* __MCF5475_PSC_H__ */ diff --git a/tos/pci_test/include/MCF5475_SDRAMC.h b/tos/pci_test/include/MCF5475_SDRAMC.h new file mode 100644 index 0000000..6cdbd68 --- /dev/null +++ b/tos/pci_test/include/MCF5475_SDRAMC.h @@ -0,0 +1,106 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SDRAMC_H__ +#define __MCF5475_SDRAMC_H__ + + +/********************************************************************* +* +* Synchronous DRAM Controller (SDRAMC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SDRAMC_SDRAMDS (*(volatile uint32_t*)(&_MBAR[0x4])) +#define MCF_SDRAMC_CS0CFG (*(volatile uint32_t*)(&_MBAR[0x20])) +#define MCF_SDRAMC_CS1CFG (*(volatile uint32_t*)(&_MBAR[0x24])) +#define MCF_SDRAMC_CS2CFG (*(volatile uint32_t*)(&_MBAR[0x28])) +#define MCF_SDRAMC_CS3CFG (*(volatile uint32_t*)(&_MBAR[0x2C])) +#define MCF_SDRAMC_SDMR (*(volatile uint32_t*)(&_MBAR[0x100])) +#define MCF_SDRAMC_SDCR (*(volatile uint32_t*)(&_MBAR[0x104])) +#define MCF_SDRAMC_SDCFG1 (*(volatile uint32_t*)(&_MBAR[0x108])) +#define MCF_SDRAMC_SDCFG2 (*(volatile uint32_t*)(&_MBAR[0x10C])) +#define MCF_SDRAMC_CSCFG(x) (*(volatile uint32_t*)(&_MBAR[0x20 + ((x)*0x4)])) + + +/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */ +#define MCF_SDRAMC_SDRAMDS_SB_D(x) (((x)&0x3)<<0) +#define MCF_SDRAMC_SDRAMDS_SB_S(x) (((x)&0x3)<<0x2) +#define MCF_SDRAMC_SDRAMDS_SB_A(x) (((x)&0x3)<<0x4) +#define MCF_SDRAMC_SDRAMDS_SB_C(x) (((x)&0x3)<<0x6) +#define MCF_SDRAMC_SDRAMDS_SB_E(x) (((x)&0x3)<<0x8) +#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA (0) +#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA (0x1) +#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA (0x2) +#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE (0x3) + +/* Bit definitions and macros for MCF_SDRAMC_CSCFG */ +#define MCF_SDRAMC_CSCFG_CSSZ(x) (((x)&0x1F)<<0) +#define MCF_SDRAMC_CSCFG_CSSZ_DISABLED (0) +#define MCF_SDRAMC_CSCFG_CSSZ_1MBYTE (0x13) +#define MCF_SDRAMC_CSCFG_CSSZ_2MBYTE (0x14) +#define MCF_SDRAMC_CSCFG_CSSZ_4MBYTE (0x15) +#define MCF_SDRAMC_CSCFG_CSSZ_8MBYTE (0x16) +#define MCF_SDRAMC_CSCFG_CSSZ_16MBYTE (0x17) +#define MCF_SDRAMC_CSCFG_CSSZ_32MBYTE (0x18) +#define MCF_SDRAMC_CSCFG_CSSZ_64MBYTE (0x19) +#define MCF_SDRAMC_CSCFG_CSSZ_128MBYTE (0x1A) +#define MCF_SDRAMC_CSCFG_CSSZ_256MBYTE (0x1B) +#define MCF_SDRAMC_CSCFG_CSSZ_512MBYTE (0x1C) +#define MCF_SDRAMC_CSCFG_CSSZ_1GBYTE (0x1D) +#define MCF_SDRAMC_CSCFG_CSSZ_2GBYTE (0x1E) +#define MCF_SDRAMC_CSCFG_CSSZ_4GBYTE (0x1F) +#define MCF_SDRAMC_CSCFG_CSBA(x) (((x)&0xFFF)<<0x14) +#define MCF_SDRAMC_CSCFG_BA(x) ((x)&0xFFF00000) + +/* Bit definitions and macros for MCF_SDRAMC_SDMR */ +#define MCF_SDRAMC_SDMR_CMD (0x10000) +#define MCF_SDRAMC_SDMR_AD(x) (((x)&0xFFF)<<0x12) +#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x3)<<0x1E) +#define MCF_SDRAMC_SDMR_BK_LMR (0) +#define MCF_SDRAMC_SDMR_BK_LEMR (0x40000000) + +/* Bit definitions and macros for MCF_SDRAMC_SDCR */ +#define MCF_SDRAMC_SDCR_IPALL (0x2) +#define MCF_SDRAMC_SDCR_IREF (0x4) +#define MCF_SDRAMC_SDCR_BUFF (0x10) +#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0xF)<<0x8) +#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x3F)<<0x10) +#define MCF_SDRAMC_SDCR_DRIVE (0x400000) +#define MCF_SDRAMC_SDCR_AP (0x800000) +#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x3)<<0x18) +#define MCF_SDRAMC_SDCR_REF (0x10000000) +#define MCF_SDRAMC_SDCR_DDR (0x20000000) +#define MCF_SDRAMC_SDCR_CKE (0x40000000) +#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) + +/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ +#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x7)<<0x4) +#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0xF)<<0x8) +#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x7)<<0xC) +#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x7)<<0x10) +#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0xF)<<0x14) +#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x7)<<0x18) +#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0xF)<<0x1C) + +/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */ +#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0xF)<<0x10) +#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0xF)<<0x14) +#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0xF)<<0x18) +#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0xF)<<0x1C) + + +#endif /* __MCF5475_SDRAMC_H__ */ diff --git a/tos/pci_test/include/MCF5475_SEC.h b/tos/pci_test/include/MCF5475_SEC.h new file mode 100644 index 0000000..8deff0b --- /dev/null +++ b/tos/pci_test/include/MCF5475_SEC.h @@ -0,0 +1,398 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SEC_H__ +#define __MCF5475_SEC_H__ + + +/********************************************************************* +* +* Integrated Security Engine (SEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SEC_EUACRH (*(volatile uint32_t*)(&_MBAR[0x21000])) +#define MCF_SEC_EUACRL (*(volatile uint32_t*)(&_MBAR[0x21004])) +#define MCF_SEC_SIMRH (*(volatile uint32_t*)(&_MBAR[0x21008])) +#define MCF_SEC_SIMRL (*(volatile uint32_t*)(&_MBAR[0x2100C])) +#define MCF_SEC_SISRH (*(volatile uint32_t*)(&_MBAR[0x21010])) +#define MCF_SEC_SISRL (*(volatile uint32_t*)(&_MBAR[0x21014])) +#define MCF_SEC_SICRH (*(volatile uint32_t*)(&_MBAR[0x21018])) +#define MCF_SEC_SICRL (*(volatile uint32_t*)(&_MBAR[0x2101C])) +#define MCF_SEC_SIDR (*(volatile uint32_t*)(&_MBAR[0x21020])) +#define MCF_SEC_EUASRH (*(volatile uint32_t*)(&_MBAR[0x21028])) +#define MCF_SEC_EUASRL (*(volatile uint32_t*)(&_MBAR[0x2102C])) +#define MCF_SEC_SMCR (*(volatile uint32_t*)(&_MBAR[0x21030])) +#define MCF_SEC_MEAR (*(volatile uint32_t*)(&_MBAR[0x21038])) +#define MCF_SEC_CCCR0 (*(volatile uint32_t*)(&_MBAR[0x2200C])) +#define MCF_SEC_CCPSRH0 (*(volatile uint32_t*)(&_MBAR[0x22010])) +#define MCF_SEC_CCPSRL0 (*(volatile uint32_t*)(&_MBAR[0x22014])) +#define MCF_SEC_CDPR0 (*(volatile uint32_t*)(&_MBAR[0x22044])) +#define MCF_SEC_FR0 (*(volatile uint32_t*)(&_MBAR[0x2204C])) +#define MCF_SEC_CCCR1 (*(volatile uint32_t*)(&_MBAR[0x2300C])) +#define MCF_SEC_CCPSRH1 (*(volatile uint32_t*)(&_MBAR[0x23010])) +#define MCF_SEC_CCPSRL1 (*(volatile uint32_t*)(&_MBAR[0x23014])) +#define MCF_SEC_CDPR1 (*(volatile uint32_t*)(&_MBAR[0x23044])) +#define MCF_SEC_FR1 (*(volatile uint32_t*)(&_MBAR[0x2304C])) +#define MCF_SEC_AFRCR (*(volatile uint32_t*)(&_MBAR[0x28018])) +#define MCF_SEC_AFSR (*(volatile uint32_t*)(&_MBAR[0x28028])) +#define MCF_SEC_AFISR (*(volatile uint32_t*)(&_MBAR[0x28030])) +#define MCF_SEC_AFIMR (*(volatile uint32_t*)(&_MBAR[0x28038])) +#define MCF_SEC_DRCR (*(volatile uint32_t*)(&_MBAR[0x2A018])) +#define MCF_SEC_DSR (*(volatile uint32_t*)(&_MBAR[0x2A028])) +#define MCF_SEC_DISR (*(volatile uint32_t*)(&_MBAR[0x2A030])) +#define MCF_SEC_DIMR (*(volatile uint32_t*)(&_MBAR[0x2A038])) +#define MCF_SEC_MDRCR (*(volatile uint32_t*)(&_MBAR[0x2C018])) +#define MCF_SEC_MDSR (*(volatile uint32_t*)(&_MBAR[0x2C028])) +#define MCF_SEC_MDISR (*(volatile uint32_t*)(&_MBAR[0x2C030])) +#define MCF_SEC_MDIMR (*(volatile uint32_t*)(&_MBAR[0x2C038])) +#define MCF_SEC_RNGRCR (*(volatile uint32_t*)(&_MBAR[0x2E018])) +#define MCF_SEC_RNGSR (*(volatile uint32_t*)(&_MBAR[0x2E028])) +#define MCF_SEC_RNGISR (*(volatile uint32_t*)(&_MBAR[0x2E030])) +#define MCF_SEC_RNGIMR (*(volatile uint32_t*)(&_MBAR[0x2E038])) +#define MCF_SEC_AESRCR (*(volatile uint32_t*)(&_MBAR[0x32018])) +#define MCF_SEC_AESSR (*(volatile uint32_t*)(&_MBAR[0x32028])) +#define MCF_SEC_AESISR (*(volatile uint32_t*)(&_MBAR[0x32030])) +#define MCF_SEC_AESIMR (*(volatile uint32_t*)(&_MBAR[0x32038])) +#define MCF_SEC_CCCRn(x) (*(volatile uint32_t*)(&_MBAR[0x2200C + ((x)*0x1000)])) +#define MCF_SEC_CCPSRHn(x) (*(volatile uint32_t*)(&_MBAR[0x22010 + ((x)*0x1000)])) +#define MCF_SEC_CCPSRLn(x) (*(volatile uint32_t*)(&_MBAR[0x22014 + ((x)*0x1000)])) +#define MCF_SEC_CDPRn(x) (*(volatile uint32_t*)(&_MBAR[0x22044 + ((x)*0x1000)])) +#define MCF_SEC_FRn(x) (*(volatile uint32_t*)(&_MBAR[0x2204C + ((x)*0x1000)])) + + +/* Bit definitions and macros for MCF_SEC_EUACRH */ +#define MCF_SEC_EUACRH_AFEU(x) (((x)&0xF)<<0) +#define MCF_SEC_EUACRH_AFFEU_NOASSIGN (0) +#define MCF_SEC_EUACRH_AFFEU_CHA0 (0x1) +#define MCF_SEC_EUACRH_AFFEU_CHA1 (0x2) +#define MCF_SEC_EUACRH_MDEU(x) (((x)&0xF)<<0x8) +#define MCF_SEC_EUACRH_MDEU_NOASSIGN (0) +#define MCF_SEC_EUACRH_MDEU_CHA0 (0x100) +#define MCF_SEC_EUACRH_MDEU_CHA1 (0x200) +#define MCF_SEC_EUACRH_RNG(x) (((x)&0xF)<<0x18) +#define MCF_SEC_EUACRH_RNG_NOASSIGN (0) +#define MCF_SEC_EUACRH_RNG_CHA0 (0x1000000) +#define MCF_SEC_EUACRH_RNG_CHA1 (0x2000000) + +/* Bit definitions and macros for MCF_SEC_EUACRL */ +#define MCF_SEC_EUACRL_AESU(x) (((x)&0xF)<<0x10) +#define MCF_SEC_EUACRL_AESU_NOASSIGN (0) +#define MCF_SEC_EUACRL_AESU_CHA0 (0x10000) +#define MCF_SEC_EUACRL_AESU_CHA1 (0x20000) +#define MCF_SEC_EUACRL_DEU(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SEC_SIMRH */ +#define MCF_SEC_SIMRH_AERR (0x8000000) +#define MCF_SEC_SIMRH_CHA_0_DN (0x10000000) +#define MCF_SEC_SIMRH_CHA_0_ERR (0x20000000) +#define MCF_SEC_SIMRH_CHA_1_DN (0x40000000) +#define MCF_SEC_SIMRH_CHA_1_ERR (0x80000000) + +/* Bit definitions and macros for MCF_SEC_SIMRL */ +#define MCF_SEC_SIMRL_TEA (0x40) +#define MCF_SEC_SIMRL_DEU_DN (0x100) +#define MCF_SEC_SIMRL_DEU_ERR (0x200) +#define MCF_SEC_SIMRL_AESU_DN (0x1000) +#define MCF_SEC_SIMRL_AESU_ERR (0x2000) +#define MCF_SEC_SIMRL_MDEU_DN (0x10000) +#define MCF_SEC_SIMRL_MDEU_ERR (0x20000) +#define MCF_SEC_SIMRL_AFEU_DN (0x100000) +#define MCF_SEC_SIMRL_AFEU_ERR (0x200000) +#define MCF_SEC_SIMRL_RNG_DN (0x1000000) +#define MCF_SEC_SIMRL_RNG_ERR (0x2000000) + +/* Bit definitions and macros for MCF_SEC_SISRH */ +#define MCF_SEC_SISRH_AERR (0x8000000) +#define MCF_SEC_SISRH_CHA_0_DN (0x10000000) +#define MCF_SEC_SISRH_CHA_0_ERR (0x20000000) +#define MCF_SEC_SISRH_CHA_1_DN (0x40000000) +#define MCF_SEC_SISRH_CHA_1_ERR (0x80000000) + +/* Bit definitions and macros for MCF_SEC_SISRL */ +#define MCF_SEC_SISRL_TEA (0x40) +#define MCF_SEC_SISRL_DEU_DN (0x100) +#define MCF_SEC_SISRL_DEU_ERR (0x200) +#define MCF_SEC_SISRL_AESU_DN (0x1000) +#define MCF_SEC_SISRL_AESU_ERR (0x2000) +#define MCF_SEC_SISRL_MDEU_DN (0x10000) +#define MCF_SEC_SISRL_MDEU_ERR (0x20000) +#define MCF_SEC_SISRL_AFEU_DN (0x100000) +#define MCF_SEC_SISRL_AFEU_ERR (0x200000) +#define MCF_SEC_SISRL_RNG_DN (0x1000000) +#define MCF_SEC_SISRL_RNG_ERR (0x2000000) + +/* Bit definitions and macros for MCF_SEC_SICRH */ +#define MCF_SEC_SICRH_AERR (0x8000000) +#define MCF_SEC_SICRH_CHA_0_DN (0x10000000) +#define MCF_SEC_SICRH_CHA_0_ERR (0x20000000) +#define MCF_SEC_SICRH_CHA_1_DN (0x40000000) +#define MCF_SEC_SICRH_CHA_1_ERR (0x80000000) + +/* Bit definitions and macros for MCF_SEC_SICRL */ +#define MCF_SEC_SICRL_TEA (0x40) +#define MCF_SEC_SICRL_DEU_DN (0x100) +#define MCF_SEC_SICRL_DEU_ERR (0x200) +#define MCF_SEC_SICRL_AESU_DN (0x1000) +#define MCF_SEC_SICRL_AESU_ERR (0x2000) +#define MCF_SEC_SICRL_MDEU_DN (0x10000) +#define MCF_SEC_SICRL_MDEU_ERR (0x20000) +#define MCF_SEC_SICRL_AFEU_DN (0x100000) +#define MCF_SEC_SICRL_AFEU_ERR (0x200000) +#define MCF_SEC_SICRL_RNG_DN (0x1000000) +#define MCF_SEC_SICRL_RNG_ERR (0x2000000) + +/* Bit definitions and macros for MCF_SEC_SIDR */ +#define MCF_SEC_SIDR_VERSION(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_EUASRH */ +#define MCF_SEC_EUASRH_AFEU(x) (((x)&0xF)<<0) +#define MCF_SEC_EUASRH_MDEU(x) (((x)&0xF)<<0x8) +#define MCF_SEC_EUASRH_RNG(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SEC_EUASRL */ +#define MCF_SEC_EUASRL_AESU(x) (((x)&0xF)<<0x10) +#define MCF_SEC_EUASRL_DEU(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SEC_SMCR */ +#define MCF_SEC_SMCR_CURR_CHAN(x) (((x)&0xF)<<0x4) +#define MCF_SEC_SMCR_CURR_CHAN_1 (0x10) +#define MCF_SEC_SMCR_CURR_CHAN_2 (0x20) +#define MCF_SEC_SMCR_SWR (0x1000000) + +/* Bit definitions and macros for MCF_SEC_MEAR */ +#define MCF_SEC_MEAR_ADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_CCCRn */ +#define MCF_SEC_CCCRn_RST (0x1) +#define MCF_SEC_CCCRn_CDIE (0x2) +#define MCF_SEC_CCCRn_NT (0x4) +#define MCF_SEC_CCCRn_NE (0x8) +#define MCF_SEC_CCCRn_WE (0x10) +#define MCF_SEC_CCCRn_BURST_SIZE(x) (((x)&0x7)<<0x8) +#define MCF_SEC_CCCRn_BURST_SIZE_2 (0) +#define MCF_SEC_CCCRn_BURST_SIZE_8 (0x100) +#define MCF_SEC_CCCRn_BURST_SIZE_16 (0x200) +#define MCF_SEC_CCCRn_BURST_SIZE_24 (0x300) +#define MCF_SEC_CCCRn_BURST_SIZE_32 (0x400) +#define MCF_SEC_CCCRn_BURST_SIZE_40 (0x500) +#define MCF_SEC_CCCRn_BURST_SIZE_48 (0x600) +#define MCF_SEC_CCCRn_BURST_SIZE_56 (0x700) + +/* Bit definitions and macros for MCF_SEC_CCPSRHn */ +#define MCF_SEC_CCPSRHn_STATE(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_SEC_CCPSRLn */ +#define MCF_SEC_CCPSRLn_PAIR_PTR(x) (((x)&0xFF)<<0) +#define MCF_SEC_CCPSRLn_EUERR (0x100) +#define MCF_SEC_CCPSRLn_SERR (0x200) +#define MCF_SEC_CCPSRLn_DERR (0x400) +#define MCF_SEC_CCPSRLn_PERR (0x1000) +#define MCF_SEC_CCPSRLn_TEA (0x2000) +#define MCF_SEC_CCPSRLn_SD (0x10000) +#define MCF_SEC_CCPSRLn_PD (0x20000) +#define MCF_SEC_CCPSRLn_SRD (0x40000) +#define MCF_SEC_CCPSRLn_PRD (0x80000) +#define MCF_SEC_CCPSRLn_SG (0x100000) +#define MCF_SEC_CCPSRLn_PG (0x200000) +#define MCF_SEC_CCPSRLn_SR (0x400000) +#define MCF_SEC_CCPSRLn_PR (0x800000) +#define MCF_SEC_CCPSRLn_MO (0x1000000) +#define MCF_SEC_CCPSRLn_MI (0x2000000) +#define MCF_SEC_CCPSRLn_STAT (0x4000000) + +/* Bit definitions and macros for MCF_SEC_CDPRn */ +#define MCF_SEC_CDPRn_CDP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_FRn */ +#define MCF_SEC_FRn_FETCH_ADDR(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_AFRCR */ +#define MCF_SEC_AFRCR_SR (0x1000000) +#define MCF_SEC_AFRCR_MI (0x2000000) +#define MCF_SEC_AFRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_AFSR */ +#define MCF_SEC_AFSR_RD (0x1000000) +#define MCF_SEC_AFSR_ID (0x2000000) +#define MCF_SEC_AFSR_IE (0x4000000) +#define MCF_SEC_AFSR_OFR (0x8000000) +#define MCF_SEC_AFSR_IFW (0x10000000) +#define MCF_SEC_AFSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_AFISR */ +#define MCF_SEC_AFISR_DSE (0x10000) +#define MCF_SEC_AFISR_KSE (0x20000) +#define MCF_SEC_AFISR_CE (0x40000) +#define MCF_SEC_AFISR_ERE (0x80000) +#define MCF_SEC_AFISR_IE (0x100000) +#define MCF_SEC_AFISR_OFU (0x2000000) +#define MCF_SEC_AFISR_IFO (0x4000000) +#define MCF_SEC_AFISR_IFE (0x10000000) +#define MCF_SEC_AFISR_OFE (0x20000000) +#define MCF_SEC_AFISR_AE (0x40000000) +#define MCF_SEC_AFISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_AFIMR */ +#define MCF_SEC_AFIMR_DSE (0x10000) +#define MCF_SEC_AFIMR_KSE (0x20000) +#define MCF_SEC_AFIMR_CE (0x40000) +#define MCF_SEC_AFIMR_ERE (0x80000) +#define MCF_SEC_AFIMR_IE (0x100000) +#define MCF_SEC_AFIMR_OFU (0x2000000) +#define MCF_SEC_AFIMR_IFO (0x4000000) +#define MCF_SEC_AFIMR_IFE (0x10000000) +#define MCF_SEC_AFIMR_OFE (0x20000000) +#define MCF_SEC_AFIMR_AE (0x40000000) +#define MCF_SEC_AFIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_DRCR */ +#define MCF_SEC_DRCR_SR (0x1000000) +#define MCF_SEC_DRCR_MI (0x2000000) +#define MCF_SEC_DRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_DSR */ +#define MCF_SEC_DSR_RD (0x1000000) +#define MCF_SEC_DSR_ID (0x2000000) +#define MCF_SEC_DSR_IE (0x4000000) +#define MCF_SEC_DSR_OFR (0x8000000) +#define MCF_SEC_DSR_IFW (0x10000000) +#define MCF_SEC_DSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_DISR */ +#define MCF_SEC_DISR_DSE (0x10000) +#define MCF_SEC_DISR_KSE (0x20000) +#define MCF_SEC_DISR_CE (0x40000) +#define MCF_SEC_DISR_ERE (0x80000) +#define MCF_SEC_DISR_IE (0x100000) +#define MCF_SEC_DISR_KPE (0x200000) +#define MCF_SEC_DISR_OFU (0x2000000) +#define MCF_SEC_DISR_IFO (0x4000000) +#define MCF_SEC_DISR_IFE (0x10000000) +#define MCF_SEC_DISR_OFE (0x20000000) +#define MCF_SEC_DISR_AE (0x40000000) +#define MCF_SEC_DISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_DIMR */ +#define MCF_SEC_DIMR_DSE (0x10000) +#define MCF_SEC_DIMR_KSE (0x20000) +#define MCF_SEC_DIMR_CE (0x40000) +#define MCF_SEC_DIMR_ERE (0x80000) +#define MCF_SEC_DIMR_IE (0x100000) +#define MCF_SEC_DIMR_KPE (0x200000) +#define MCF_SEC_DIMR_OFU (0x2000000) +#define MCF_SEC_DIMR_IFO (0x4000000) +#define MCF_SEC_DIMR_IFE (0x10000000) +#define MCF_SEC_DIMR_OFE (0x20000000) +#define MCF_SEC_DIMR_AE (0x40000000) +#define MCF_SEC_DIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_MDRCR */ +#define MCF_SEC_MDRCR_SR (0x1000000) +#define MCF_SEC_MDRCR_MI (0x2000000) +#define MCF_SEC_MDRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_MDSR */ +#define MCF_SEC_MDSR_RD (0x1000000) +#define MCF_SEC_MDSR_ID (0x2000000) +#define MCF_SEC_MDSR_IE (0x4000000) +#define MCF_SEC_MDSR_IFW (0x10000000) +#define MCF_SEC_MDSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_MDISR */ +#define MCF_SEC_MDISR_DSE (0x10000) +#define MCF_SEC_MDISR_KSE (0x20000) +#define MCF_SEC_MDISR_CE (0x40000) +#define MCF_SEC_MDISR_ERE (0x80000) +#define MCF_SEC_MDISR_IE (0x100000) +#define MCF_SEC_MDISR_IFO (0x4000000) +#define MCF_SEC_MDISR_AE (0x40000000) +#define MCF_SEC_MDISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_MDIMR */ +#define MCF_SEC_MDIMR_DSE (0x10000) +#define MCF_SEC_MDIMR_KSE (0x20000) +#define MCF_SEC_MDIMR_CE (0x40000) +#define MCF_SEC_MDIMR_ERE (0x80000) +#define MCF_SEC_MDIMR_IE (0x100000) +#define MCF_SEC_MDIMR_IFO (0x4000000) +#define MCF_SEC_MDIMR_AE (0x40000000) +#define MCF_SEC_MDIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_RNGRCR */ +#define MCF_SEC_RNGRCR_SR (0x1000000) +#define MCF_SEC_RNGRCR_MI (0x2000000) +#define MCF_SEC_RNGRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_RNGSR */ +#define MCF_SEC_RNGSR_RD (0x1000000) +#define MCF_SEC_RNGSR_IE (0x4000000) +#define MCF_SEC_RNGSR_OFR (0x8000000) +#define MCF_SEC_RNGSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_RNGISR */ +#define MCF_SEC_RNGISR_IE (0x100000) +#define MCF_SEC_RNGISR_OFU (0x2000000) +#define MCF_SEC_RNGISR_AE (0x40000000) +#define MCF_SEC_RNGISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_RNGIMR */ +#define MCF_SEC_RNGIMR_IE (0x100000) +#define MCF_SEC_RNGIMR_OFU (0x2000000) +#define MCF_SEC_RNGIMR_AE (0x40000000) +#define MCF_SEC_RNGIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_AESRCR */ +#define MCF_SEC_AESRCR_SR (0x1000000) +#define MCF_SEC_AESRCR_MI (0x2000000) +#define MCF_SEC_AESRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_AESSR */ +#define MCF_SEC_AESSR_RD (0x1000000) +#define MCF_SEC_AESSR_ID (0x2000000) +#define MCF_SEC_AESSR_IE (0x4000000) +#define MCF_SEC_AESSR_OFR (0x8000000) +#define MCF_SEC_AESSR_IFW (0x10000000) +#define MCF_SEC_AESSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_AESISR */ +#define MCF_SEC_AESISR_DSE (0x10000) +#define MCF_SEC_AESISR_KSE (0x20000) +#define MCF_SEC_AESISR_CE (0x40000) +#define MCF_SEC_AESISR_ERE (0x80000) +#define MCF_SEC_AESISR_IE (0x100000) +#define MCF_SEC_AESISR_OFU (0x2000000) +#define MCF_SEC_AESISR_IFO (0x4000000) +#define MCF_SEC_AESISR_IFE (0x10000000) +#define MCF_SEC_AESISR_OFE (0x20000000) +#define MCF_SEC_AESISR_AE (0x40000000) +#define MCF_SEC_AESISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_AESIMR */ +#define MCF_SEC_AESIMR_DSE (0x10000) +#define MCF_SEC_AESIMR_KSE (0x20000) +#define MCF_SEC_AESIMR_CE (0x40000) +#define MCF_SEC_AESIMR_ERE (0x80000) +#define MCF_SEC_AESIMR_IE (0x100000) +#define MCF_SEC_AESIMR_OFU (0x2000000) +#define MCF_SEC_AESIMR_IFO (0x4000000) +#define MCF_SEC_AESIMR_IFE (0x10000000) +#define MCF_SEC_AESIMR_OFE (0x20000000) +#define MCF_SEC_AESIMR_AE (0x40000000) +#define MCF_SEC_AESIMR_ME (0x80000000) + + +#endif /* __MCF5475_SEC_H__ */ diff --git a/tos/pci_test/include/MCF5475_SIU.h b/tos/pci_test/include/MCF5475_SIU.h new file mode 100644 index 0000000..efb2896 --- /dev/null +++ b/tos/pci_test/include/MCF5475_SIU.h @@ -0,0 +1,67 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SIU_H__ +#define __MCF5475_SIU_H__ + + +/********************************************************************* +* +* System Integration Unit (SIU) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SIU_SBCR (*(volatile uint32_t*)(&_MBAR[0x10])) +#define MCF_SIU_SECSACR (*(volatile uint32_t*)(&_MBAR[0x38])) +#define MCF_SIU_RSR (*(volatile uint32_t*)(&_MBAR[0x44])) +#define MCF_SIU_JTAGID (*(volatile uint32_t*)(&_MBAR[0x50])) + + +/* Bit definitions and macros for MCF_SIU_SBCR */ +#define MCF_SIU_SBCR_PIN2DSPI (0x8000000) +#define MCF_SIU_SBCR_DMA2CPU (0x10000000) +#define MCF_SIU_SBCR_CPU2DMA (0x20000000) +#define MCF_SIU_SBCR_PIN2DMA (0x40000000) +#define MCF_SIU_SBCR_PIN2CPU (0x80000000) + +/* Bit definitions and macros for MCF_SIU_SECSACR */ +#define MCF_SIU_SECSACR_SEQEN (0x1) + +/* Bit definitions and macros for MCF_SIU_RSR */ +#define MCF_SIU_RSR_RST (0x1) +#define MCF_SIU_RSR_RSTWD (0x2) +#define MCF_SIU_RSR_RSTJTG (0x8) + +/* Bit definitions and macros for MCF_SIU_JTAGID */ +#define MCF_SIU_JTAGID_JTAGID(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SIU_JTAGID */ +#define MCF_SIU_JTAGID_REV (0xF0000000) +#define MCF_SIU_JTAGID_PROCESSOR (0x0FFFFFFF) +#define MCF_SIU_JTAGID_MCF5485 (0x0800C01D) +#define MCF_SIU_JTAGID_MCF5484 (0x0800D01D) +#define MCF_SIU_JTAGID_MCF5483 (0x0800E01D) +#define MCF_SIU_JTAGID_MCF5482 (0x0800F01D) +#define MCF_SIU_JTAGID_MCF5481 (0x0801001D) +#define MCF_SIU_JTAGID_MCF5480 (0x0801101D) +#define MCF_SIU_JTAGID_MCF5475 (0x0801201D) +#define MCF_SIU_JTAGID_MCF5474 (0x0801301D) +#define MCF_SIU_JTAGID_MCF5473 (0x0801401D) +#define MCF_SIU_JTAGID_MCF5472 (0x0801501D) +#define MCF_SIU_JTAGID_MCF5471 (0x0801601D) +#define MCF_SIU_JTAGID_MCF5470 (0x0801701D) + +#endif /* __MCF5475_SIU_H__ */ diff --git a/tos/pci_test/include/MCF5475_SLT.h b/tos/pci_test/include/MCF5475_SLT.h new file mode 100644 index 0000000..20e8558 --- /dev/null +++ b/tos/pci_test/include/MCF5475_SLT.h @@ -0,0 +1,59 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SLT_H__ +#define __MCF5475_SLT_H__ + + +/********************************************************************* +* +* Slice Timers (SLT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SLT0_STCNT (*(volatile uint32_t*)(&_MBAR[0x900])) +#define MCF_SLT0_SCR (*(volatile uint32_t*)(&_MBAR[0x904])) +#define MCF_SLT0_SCNT (*(volatile uint32_t*)(&_MBAR[0x908])) +#define MCF_SLT0_SSR (*(volatile uint32_t*)(&_MBAR[0x90C])) + +#define MCF_SLT1_STCNT (*(volatile uint32_t*)(&_MBAR[0x910])) +#define MCF_SLT1_SCR (*(volatile uint32_t*)(&_MBAR[0x914])) +#define MCF_SLT1_SCNT (*(volatile uint32_t*)(&_MBAR[0x918])) +#define MCF_SLT1_SSR (*(volatile uint32_t*)(&_MBAR[0x91C])) + +#define MCF_SLT_STCNT(x) (*(volatile uint32_t*)(&_MBAR[0x900 + ((x)*0x10)])) +#define MCF_SLT_SCR(x) (*(volatile uint32_t*)(&_MBAR[0x904 + ((x)*0x10)])) +#define MCF_SLT_SCNT(x) (*(volatile int32_t*)(&_MBAR[0x908 + ((x)*0x10)])) +#define MCF_SLT_SSR(x) (*(volatile uint32_t*)(&_MBAR[0x90C + ((x)*0x10)])) + + +/* Bit definitions and macros for MCF_SLT_STCNT */ +#define MCF_SLT_STCNT_TC(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SLT_SCR */ +#define MCF_SLT_SCR_TEN (0x1000000) +#define MCF_SLT_SCR_IEN (0x2000000) +#define MCF_SLT_SCR_RUN (0x4000000) + +/* Bit definitions and macros for MCF_SLT_SCNT */ +#define MCF_SLT_SCNT_CNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SLT_SSR */ +#define MCF_SLT_SSR_ST (0x1000000) +#define MCF_SLT_SSR_BE (0x2000000) + + +#endif /* __MCF5475_SLT_H__ */ diff --git a/tos/pci_test/include/MCF5475_SRAM.h b/tos/pci_test/include/MCF5475_SRAM.h new file mode 100644 index 0000000..d111f13 --- /dev/null +++ b/tos/pci_test/include/MCF5475_SRAM.h @@ -0,0 +1,62 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SRAM_H__ +#define __MCF5475_SRAM_H__ + + +/********************************************************************* +* +* System SRAM Module (SRAM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SRAM_SSCR (*(volatile uint32_t*)(&__MBAR[0x1FFC0])) +#define MCF_SRAM_TCCR (*(volatile uint32_t*)(&__MBAR[0x1FFC4])) +#define MCF_SRAM_TCCRDR (*(volatile uint32_t*)(&__MBAR[0x1FFC8])) +#define MCF_SRAM_TCCRDW (*(volatile uint32_t*)(&__MBAR[0x1FFCC])) +#define MCF_SRAM_TCCRSEC (*(volatile uint32_t*)(&__MBAR[0x1FFD0])) + + +/* Bit definitions and macros for MCF_SRAM_SSCR */ +#define MCF_SRAM_SSCR_INLV (0x10000) + +/* Bit definitions and macros for MCF_SRAM_TCCR */ +#define MCF_SRAM_TCCR_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCR_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCR_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCR_BANK3_TC(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SRAM_TCCRDR */ +#define MCF_SRAM_TCCRDR_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCRDR_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCRDR_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCRDR_BANK3_TC(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SRAM_TCCRDW */ +#define MCF_SRAM_TCCRDW_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCRDW_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCRDW_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCRDW_BANK3_TC(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SRAM_TCCRSEC */ +#define MCF_SRAM_TCCRSEC_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCRSEC_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCRSEC_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCRSEC_BANK3_TC(x) (((x)&0xF)<<0x18) + + +#endif /* __MCF5475_SRAM_H__ */ diff --git a/tos/pci_test/include/MCF5475_USB.h b/tos/pci_test/include/MCF5475_USB.h new file mode 100644 index 0000000..c60273c --- /dev/null +++ b/tos/pci_test/include/MCF5475_USB.h @@ -0,0 +1,554 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_USB_H__ +#define __MCF5475_USB_H__ + + +/********************************************************************* +* +* Universal Serial Bus Interface (USB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_USB_USBAISR (*(volatile uint8_t *)(&__MBAR[0xB000])) +#define MCF_USB_USBAIMR (*(volatile uint8_t *)(&__MBAR[0xB001])) +#define MCF_USB_EPINFO (*(volatile uint8_t *)(&__MBAR[0xB003])) +#define MCF_USB_CFGR (*(volatile uint8_t *)(&__MBAR[0xB004])) +#define MCF_USB_CFGAR (*(volatile uint8_t *)(&__MBAR[0xB005])) +#define MCF_USB_SPEEDR (*(volatile uint8_t *)(&__MBAR[0xB006])) +#define MCF_USB_FRMNUMR (*(volatile uint16_t*)(&__MBAR[0xB00E])) +#define MCF_USB_EPTNR (*(volatile uint16_t*)(&__MBAR[0xB010])) +#define MCF_USB_IFUR (*(volatile uint16_t*)(&__MBAR[0xB014])) +#define MCF_USB_IFR0 (*(volatile uint16_t*)(&__MBAR[0xB040])) +#define MCF_USB_IFR1 (*(volatile uint16_t*)(&__MBAR[0xB042])) +#define MCF_USB_IFR2 (*(volatile uint16_t*)(&__MBAR[0xB044])) +#define MCF_USB_IFR3 (*(volatile uint16_t*)(&__MBAR[0xB046])) +#define MCF_USB_IFR4 (*(volatile uint16_t*)(&__MBAR[0xB048])) +#define MCF_USB_IFR5 (*(volatile uint16_t*)(&__MBAR[0xB04A])) +#define MCF_USB_IFR6 (*(volatile uint16_t*)(&__MBAR[0xB04C])) +#define MCF_USB_IFR7 (*(volatile uint16_t*)(&__MBAR[0xB04E])) +#define MCF_USB_IFR8 (*(volatile uint16_t*)(&__MBAR[0xB050])) +#define MCF_USB_IFR9 (*(volatile uint16_t*)(&__MBAR[0xB052])) +#define MCF_USB_IFR10 (*(volatile uint16_t*)(&__MBAR[0xB054])) +#define MCF_USB_IFR11 (*(volatile uint16_t*)(&__MBAR[0xB056])) +#define MCF_USB_IFR12 (*(volatile uint16_t*)(&__MBAR[0xB058])) +#define MCF_USB_IFR13 (*(volatile uint16_t*)(&__MBAR[0xB05A])) +#define MCF_USB_IFR14 (*(volatile uint16_t*)(&__MBAR[0xB05C])) +#define MCF_USB_IFR15 (*(volatile uint16_t*)(&__MBAR[0xB05E])) +#define MCF_USB_IFR16 (*(volatile uint16_t*)(&__MBAR[0xB060])) +#define MCF_USB_IFR17 (*(volatile uint16_t*)(&__MBAR[0xB062])) +#define MCF_USB_IFR18 (*(volatile uint16_t*)(&__MBAR[0xB064])) +#define MCF_USB_IFR19 (*(volatile uint16_t*)(&__MBAR[0xB066])) +#define MCF_USB_IFR20 (*(volatile uint16_t*)(&__MBAR[0xB068])) +#define MCF_USB_IFR21 (*(volatile uint16_t*)(&__MBAR[0xB06A])) +#define MCF_USB_IFR22 (*(volatile uint16_t*)(&__MBAR[0xB06C])) +#define MCF_USB_IFR23 (*(volatile uint16_t*)(&__MBAR[0xB06E])) +#define MCF_USB_IFR24 (*(volatile uint16_t*)(&__MBAR[0xB070])) +#define MCF_USB_IFR25 (*(volatile uint16_t*)(&__MBAR[0xB072])) +#define MCF_USB_IFR26 (*(volatile uint16_t*)(&__MBAR[0xB074])) +#define MCF_USB_IFR27 (*(volatile uint16_t*)(&__MBAR[0xB076])) +#define MCF_USB_IFR28 (*(volatile uint16_t*)(&__MBAR[0xB078])) +#define MCF_USB_IFR29 (*(volatile uint16_t*)(&__MBAR[0xB07A])) +#define MCF_USB_IFR30 (*(volatile uint16_t*)(&__MBAR[0xB07C])) +#define MCF_USB_IFR31 (*(volatile uint16_t*)(&__MBAR[0xB07E])) +#define MCF_USB_PPCNT (*(volatile uint16_t*)(&__MBAR[0xB080])) +#define MCF_USB_DPCNT (*(volatile uint16_t*)(&__MBAR[0xB082])) +#define MCF_USB_CRCECNT (*(volatile uint16_t*)(&__MBAR[0xB084])) +#define MCF_USB_BSECNT (*(volatile uint16_t*)(&__MBAR[0xB086])) +#define MCF_USB_PIDECNT (*(volatile uint16_t*)(&__MBAR[0xB088])) +#define MCF_USB_FRMECNT (*(volatile uint16_t*)(&__MBAR[0xB08A])) +#define MCF_USB_TXPCNT (*(volatile uint16_t*)(&__MBAR[0xB08C])) +#define MCF_USB_CNTOVR (*(volatile uint8_t *)(&__MBAR[0xB08E])) +#define MCF_USB_EP0ACR (*(volatile uint8_t *)(&__MBAR[0xB101])) +#define MCF_USB_EP0MPSR (*(volatile uint16_t*)(&__MBAR[0xB102])) +#define MCF_USB_EP0IFR (*(volatile uint8_t *)(&__MBAR[0xB104])) +#define MCF_USB_EP0SR (*(volatile uint8_t *)(&__MBAR[0xB105])) +#define MCF_USB_BMRTR (*(volatile uint8_t *)(&__MBAR[0xB106])) +#define MCF_USB_BRTR (*(volatile uint8_t *)(&__MBAR[0xB107])) +#define MCF_USB_WVALUER (*(volatile uint16_t*)(&__MBAR[0xB108])) +#define MCF_USB_WINDEXR (*(volatile uint16_t*)(&__MBAR[0xB10A])) +#define MCF_USB_WLENGTHR (*(volatile uint16_t*)(&__MBAR[0xB10C])) +#define MCF_USB_EP1OUTACR (*(volatile uint8_t *)(&__MBAR[0xB131])) +#define MCF_USB_EP1OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB132])) +#define MCF_USB_EP1OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB134])) +#define MCF_USB_EP1OUTSR (*(volatile uint8_t *)(&__MBAR[0xB135])) +#define MCF_USB_EP1OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB13E])) +#define MCF_USB_EP1INACR (*(volatile uint8_t *)(&__MBAR[0xB149])) +#define MCF_USB_EP1INMPSR (*(volatile uint16_t*)(&__MBAR[0xB14A])) +#define MCF_USB_EP1INIFR (*(volatile uint8_t *)(&__MBAR[0xB14C])) +#define MCF_USB_EP1INSR (*(volatile uint8_t *)(&__MBAR[0xB14D])) +#define MCF_USB_EP1INSFR (*(volatile uint16_t*)(&__MBAR[0xB156])) +#define MCF_USB_EP2OUTACR (*(volatile uint8_t *)(&__MBAR[0xB161])) +#define MCF_USB_EP2OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB162])) +#define MCF_USB_EP2OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB164])) +#define MCF_USB_EP2OUTSR (*(volatile uint8_t *)(&__MBAR[0xB165])) +#define MCF_USB_EP2OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB16E])) +#define MCF_USB_EP2INACR (*(volatile uint8_t *)(&__MBAR[0xB179])) +#define MCF_USB_EP2INMPSR (*(volatile uint16_t*)(&__MBAR[0xB17A])) +#define MCF_USB_EP2INIFR (*(volatile uint8_t *)(&__MBAR[0xB17C])) +#define MCF_USB_EP2INSR (*(volatile uint8_t *)(&__MBAR[0xB17D])) +#define MCF_USB_EP2INSFR (*(volatile uint16_t*)(&__MBAR[0xB186])) +#define MCF_USB_EP3OUTACR (*(volatile uint8_t *)(&__MBAR[0xB191])) +#define MCF_USB_EP3OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB192])) +#define MCF_USB_EP3OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB194])) +#define MCF_USB_EP3OUTSR (*(volatile uint8_t *)(&__MBAR[0xB195])) +#define MCF_USB_EP3OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB19E])) +#define MCF_USB_EP3INACR (*(volatile uint8_t *)(&__MBAR[0xB1A9])) +#define MCF_USB_EP3INMPSR (*(volatile uint16_t*)(&__MBAR[0xB1AA])) +#define MCF_USB_EP3INIFR (*(volatile uint8_t *)(&__MBAR[0xB1AC])) +#define MCF_USB_EP3INSR (*(volatile uint8_t *)(&__MBAR[0xB1AD])) +#define MCF_USB_EP3INSFR (*(volatile uint16_t*)(&__MBAR[0xB1B6])) +#define MCF_USB_EP4OUTACR (*(volatile uint8_t *)(&__MBAR[0xB1C1])) +#define MCF_USB_EP4OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB1C2])) +#define MCF_USB_EP4OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB1C4])) +#define MCF_USB_EP4OUTSR (*(volatile uint8_t *)(&__MBAR[0xB1C5])) +#define MCF_USB_EP4OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB1CE])) +#define MCF_USB_EP4INACR (*(volatile uint8_t *)(&__MBAR[0xB1D9])) +#define MCF_USB_EP4INMPSR (*(volatile uint16_t*)(&__MBAR[0xB1DA])) +#define MCF_USB_EP4INIFR (*(volatile uint8_t *)(&__MBAR[0xB1DC])) +#define MCF_USB_EP4INSR (*(volatile uint8_t *)(&__MBAR[0xB1DD])) +#define MCF_USB_EP4INSFR (*(volatile uint16_t*)(&__MBAR[0xB1E6])) +#define MCF_USB_EP5OUTACR (*(volatile uint8_t *)(&__MBAR[0xB1F1])) +#define MCF_USB_EP5OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB1F2])) +#define MCF_USB_EP5OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB1F4])) +#define MCF_USB_EP5OUTSR (*(volatile uint8_t *)(&__MBAR[0xB1F5])) +#define MCF_USB_EP5OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB1FE])) +#define MCF_USB_EP5INACR (*(volatile uint8_t *)(&__MBAR[0xB209])) +#define MCF_USB_EP5INMPSR (*(volatile uint16_t*)(&__MBAR[0xB20A])) +#define MCF_USB_EP5INIFR (*(volatile uint8_t *)(&__MBAR[0xB20C])) +#define MCF_USB_EP5INSR (*(volatile uint8_t *)(&__MBAR[0xB20D])) +#define MCF_USB_EP5INSFR (*(volatile uint16_t*)(&__MBAR[0xB216])) +#define MCF_USB_EP6OUTACR (*(volatile uint8_t *)(&__MBAR[0xB221])) +#define MCF_USB_EP6OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB222])) +#define MCF_USB_EP6OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB224])) +#define MCF_USB_EP6OUTSR (*(volatile uint8_t *)(&__MBAR[0xB225])) +#define MCF_USB_EP6OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB22E])) +#define MCF_USB_EP6INACR (*(volatile uint8_t *)(&__MBAR[0xB239])) +#define MCF_USB_EP6INMPSR (*(volatile uint16_t*)(&__MBAR[0xB23A])) +#define MCF_USB_EP6INIFR (*(volatile uint8_t *)(&__MBAR[0xB23C])) +#define MCF_USB_EP6INSR (*(volatile uint8_t *)(&__MBAR[0xB23D])) +#define MCF_USB_EP6INSFR (*(volatile uint16_t*)(&__MBAR[0xB246])) +#define MCF_USB_USBSR (*(volatile uint32_t*)(&__MBAR[0xB400])) +#define MCF_USB_USBCR (*(volatile uint32_t*)(&__MBAR[0xB404])) +#define MCF_USB_DRAMCR (*(volatile uint32_t*)(&__MBAR[0xB408])) +#define MCF_USB_DRAMDR (*(volatile uint32_t*)(&__MBAR[0xB40C])) +#define MCF_USB_USBISR (*(volatile uint32_t*)(&__MBAR[0xB410])) +#define MCF_USB_USBIMR (*(volatile uint32_t*)(&__MBAR[0xB414])) +#define MCF_USB_EP0STAT (*(volatile uint32_t*)(&__MBAR[0xB440])) +#define MCF_USB_EP0ISR (*(volatile uint32_t*)(&__MBAR[0xB444])) +#define MCF_USB_EP0IMR (*(volatile uint32_t*)(&__MBAR[0xB448])) +#define MCF_USB_EP0FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB44C])) +#define MCF_USB_EP0FDR (*(volatile uint32_t*)(&__MBAR[0xB450])) +#define MCF_USB_EP0FSR (*(volatile uint32_t*)(&__MBAR[0xB454])) +#define MCF_USB_EP0FCR (*(volatile uint32_t*)(&__MBAR[0xB458])) +#define MCF_USB_EP0FAR (*(volatile uint32_t*)(&__MBAR[0xB45C])) +#define MCF_USB_EP0FRP (*(volatile uint32_t*)(&__MBAR[0xB460])) +#define MCF_USB_EP0FWP (*(volatile uint32_t*)(&__MBAR[0xB464])) +#define MCF_USB_EP0LRFP (*(volatile uint32_t*)(&__MBAR[0xB468])) +#define MCF_USB_EP0LWFP (*(volatile uint32_t*)(&__MBAR[0xB46C])) +#define MCF_USB_EP1STAT (*(volatile uint32_t*)(&__MBAR[0xB470])) +#define MCF_USB_EP1ISR (*(volatile uint32_t*)(&__MBAR[0xB474])) +#define MCF_USB_EP1IMR (*(volatile uint32_t*)(&__MBAR[0xB478])) +#define MCF_USB_EP1FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB47C])) +#define MCF_USB_EP1FDR (*(volatile uint32_t*)(&__MBAR[0xB480])) +#define MCF_USB_EP1FSR (*(volatile uint32_t*)(&__MBAR[0xB484])) +#define MCF_USB_EP1FCR (*(volatile uint32_t*)(&__MBAR[0xB488])) +#define MCF_USB_EP1FAR (*(volatile uint32_t*)(&__MBAR[0xB48C])) +#define MCF_USB_EP1FRP (*(volatile uint32_t*)(&__MBAR[0xB490])) +#define MCF_USB_EP1FWP (*(volatile uint32_t*)(&__MBAR[0xB494])) +#define MCF_USB_EP1LRFP (*(volatile uint32_t*)(&__MBAR[0xB498])) +#define MCF_USB_EP1LWFP (*(volatile uint32_t*)(&__MBAR[0xB49C])) +#define MCF_USB_EP2STAT (*(volatile uint32_t*)(&__MBAR[0xB4A0])) +#define MCF_USB_EP2ISR (*(volatile uint32_t*)(&__MBAR[0xB4A4])) +#define MCF_USB_EP2IMR (*(volatile uint32_t*)(&__MBAR[0xB4A8])) +#define MCF_USB_EP2FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB4AC])) +#define MCF_USB_EP2FDR (*(volatile uint32_t*)(&__MBAR[0xB4B0])) +#define MCF_USB_EP2FSR (*(volatile uint32_t*)(&__MBAR[0xB4B4])) +#define MCF_USB_EP2FCR (*(volatile uint32_t*)(&__MBAR[0xB4B8])) +#define MCF_USB_EP2FAR (*(volatile uint32_t*)(&__MBAR[0xB4BC])) +#define MCF_USB_EP2FRP (*(volatile uint32_t*)(&__MBAR[0xB4C0])) +#define MCF_USB_EP2FWP (*(volatile uint32_t*)(&__MBAR[0xB4C4])) +#define MCF_USB_EP2LRFP (*(volatile uint32_t*)(&__MBAR[0xB4C8])) +#define MCF_USB_EP2LWFP (*(volatile uint32_t*)(&__MBAR[0xB4CC])) +#define MCF_USB_EP3STAT (*(volatile uint32_t*)(&__MBAR[0xB4D0])) +#define MCF_USB_EP3ISR (*(volatile uint32_t*)(&__MBAR[0xB4D4])) +#define MCF_USB_EP3IMR (*(volatile uint32_t*)(&__MBAR[0xB4D8])) +#define MCF_USB_EP3FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB4DC])) +#define MCF_USB_EP3FDR (*(volatile uint32_t*)(&__MBAR[0xB4E0])) +#define MCF_USB_EP3FSR (*(volatile uint32_t*)(&__MBAR[0xB4E4])) +#define MCF_USB_EP3FCR (*(volatile uint32_t*)(&__MBAR[0xB4E8])) +#define MCF_USB_EP3FAR (*(volatile uint32_t*)(&__MBAR[0xB4EC])) +#define MCF_USB_EP3FRP (*(volatile uint32_t*)(&__MBAR[0xB4F0])) +#define MCF_USB_EP3FWP (*(volatile uint32_t*)(&__MBAR[0xB4F4])) +#define MCF_USB_EP3LRFP (*(volatile uint32_t*)(&__MBAR[0xB4F8])) +#define MCF_USB_EP3LWFP (*(volatile uint32_t*)(&__MBAR[0xB4FC])) +#define MCF_USB_EP4STAT (*(volatile uint32_t*)(&__MBAR[0xB500])) +#define MCF_USB_EP4ISR (*(volatile uint32_t*)(&__MBAR[0xB504])) +#define MCF_USB_EP4IMR (*(volatile uint32_t*)(&__MBAR[0xB508])) +#define MCF_USB_EP4FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB50C])) +#define MCF_USB_EP4FDR (*(volatile uint32_t*)(&__MBAR[0xB510])) +#define MCF_USB_EP4FSR (*(volatile uint32_t*)(&__MBAR[0xB514])) +#define MCF_USB_EP4FCR (*(volatile uint32_t*)(&__MBAR[0xB518])) +#define MCF_USB_EP4FAR (*(volatile uint32_t*)(&__MBAR[0xB51C])) +#define MCF_USB_EP4FRP (*(volatile uint32_t*)(&__MBAR[0xB520])) +#define MCF_USB_EP4FWP (*(volatile uint32_t*)(&__MBAR[0xB524])) +#define MCF_USB_EP4LRFP (*(volatile uint32_t*)(&__MBAR[0xB528])) +#define MCF_USB_EP4LWFP (*(volatile uint32_t*)(&__MBAR[0xB52C])) +#define MCF_USB_EP5STAT (*(volatile uint32_t*)(&__MBAR[0xB530])) +#define MCF_USB_EP5ISR (*(volatile uint32_t*)(&__MBAR[0xB534])) +#define MCF_USB_EP5IMR (*(volatile uint32_t*)(&__MBAR[0xB538])) +#define MCF_USB_EP5FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB53C])) +#define MCF_USB_EP5FDR (*(volatile uint32_t*)(&__MBAR[0xB540])) +#define MCF_USB_EP5FSR (*(volatile uint32_t*)(&__MBAR[0xB544])) +#define MCF_USB_EP5FCR (*(volatile uint32_t*)(&__MBAR[0xB548])) +#define MCF_USB_EP5FAR (*(volatile uint32_t*)(&__MBAR[0xB54C])) +#define MCF_USB_EP5FRP (*(volatile uint32_t*)(&__MBAR[0xB550])) +#define MCF_USB_EP5FWP (*(volatile uint32_t*)(&__MBAR[0xB554])) +#define MCF_USB_EP5LRFP (*(volatile uint32_t*)(&__MBAR[0xB558])) +#define MCF_USB_EP5LWFP (*(volatile uint32_t*)(&__MBAR[0xB55C])) +#define MCF_USB_EP6STAT (*(volatile uint32_t*)(&__MBAR[0xB560])) +#define MCF_USB_EP6ISR (*(volatile uint32_t*)(&__MBAR[0xB564])) +#define MCF_USB_EP6IMR (*(volatile uint32_t*)(&__MBAR[0xB568])) +#define MCF_USB_EP6FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB56C])) +#define MCF_USB_EP6FDR (*(volatile uint32_t*)(&__MBAR[0xB570])) +#define MCF_USB_EP6FSR (*(volatile uint32_t*)(&__MBAR[0xB574])) +#define MCF_USB_EP6FCR (*(volatile uint32_t*)(&__MBAR[0xB578])) +#define MCF_USB_EP6FAR (*(volatile uint32_t*)(&__MBAR[0xB57C])) +#define MCF_USB_EP6FRP (*(volatile uint32_t*)(&__MBAR[0xB580])) +#define MCF_USB_EP6FWP (*(volatile uint32_t*)(&__MBAR[0xB584])) +#define MCF_USB_EP6LRFP (*(volatile uint32_t*)(&__MBAR[0xB588])) +#define MCF_USB_EP6LWFP (*(volatile uint32_t*)(&__MBAR[0xB58C])) +#define MCF_USB_IFR(x) (*(volatile uint16_t*)(&__MBAR[0xB040 + ((x)*0x2)])) +#define MCF_USB_EPOUTACR(x) (*(volatile uint8_t *)(&__MBAR[0xB131 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTMPSR(x) (*(volatile uint16_t*)(&__MBAR[0xB132 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTIFR(x) (*(volatile uint8_t *)(&__MBAR[0xB134 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTSR(x) (*(volatile uint8_t *)(&__MBAR[0xB135 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTSFR(x) (*(volatile uint16_t*)(&__MBAR[0xB13E + ((x-1)*0x30)])) +#define MCF_USB_EPINACR(x) (*(volatile uint8_t *)(&__MBAR[0xB149 + ((x-1)*0x30)])) +#define MCF_USB_EPINMPSR(x) (*(volatile uint16_t*)(&__MBAR[0xB14A + ((x-1)*0x30)])) +#define MCF_USB_EPINIFR(x) (*(volatile uint8_t *)(&__MBAR[0xB14C + ((x-1)*0x30)])) +#define MCF_USB_EPINSR(x) (*(volatile uint8_t *)(&__MBAR[0xB14D + ((x-1)*0x30)])) +#define MCF_USB_EPINSFR(x) (*(volatile uint16_t*)(&__MBAR[0xB156 + ((x-1)*0x30)])) +#define MCF_USB_EPSTAT(x) (*(volatile uint32_t*)(&__MBAR[0xB440 + ((x)*0x30)])) +#define MCF_USB_EPISR(x) (*(volatile uint32_t*)(&__MBAR[0xB444 + ((x)*0x30)])) +#define MCF_USB_EPIMR(x) (*(volatile uint32_t*)(&__MBAR[0xB448 + ((x)*0x30)])) +#define MCF_USB_EPFRCFGR(x) (*(volatile uint32_t*)(&__MBAR[0xB44C + ((x)*0x30)])) +#define MCF_USB_EPFDR(x) (*(volatile uint32_t*)(&__MBAR[0xB450 + ((x)*0x30)])) +#define MCF_USB_EPFSR(x) (*(volatile uint32_t*)(&__MBAR[0xB454 + ((x)*0x30)])) +#define MCF_USB_EPFCR(x) (*(volatile uint32_t*)(&__MBAR[0xB458 + ((x)*0x30)])) +#define MCF_USB_EPFAR(x) (*(volatile uint32_t*)(&__MBAR[0xB45C + ((x)*0x30)])) +#define MCF_USB_EPFRP(x) (*(volatile uint32_t*)(&__MBAR[0xB460 + ((x)*0x30)])) +#define MCF_USB_EPFWP(x) (*(volatile uint32_t*)(&__MBAR[0xB464 + ((x)*0x30)])) +#define MCF_USB_EPLRFP(x) (*(volatile uint32_t*)(&__MBAR[0xB468 + ((x)*0x30)])) +#define MCF_USB_EPLWFP(x) (*(volatile uint32_t*)(&__MBAR[0xB46C + ((x)*0x30)])) + + +/* Bit definitions and macros for MCF_USB_USBAISR */ +#define MCF_USB_USBAISR_SETUP (0x1) +#define MCF_USB_USBAISR_IN (0x2) +#define MCF_USB_USBAISR_OUT (0x4) +#define MCF_USB_USBAISR_EPHALT (0x8) +#define MCF_USB_USBAISR_TRANSERR (0x10) +#define MCF_USB_USBAISR_ACK (0x20) +#define MCF_USB_USBAISR_CTROVFL (0x40) +#define MCF_USB_USBAISR_EPSTALL (0x80) + +/* Bit definitions and macros for MCF_USB_USBAIMR */ +#define MCF_USB_USBAIMR_SETUPEN (0x1) +#define MCF_USB_USBAIMR_INEN (0x2) +#define MCF_USB_USBAIMR_OUTEN (0x4) +#define MCF_USB_USBAIMR_EPHALTEN (0x8) +#define MCF_USB_USBAIMR_TRANSERREN (0x10) +#define MCF_USB_USBAIMR_ACKEN (0x20) +#define MCF_USB_USBAIMR_CTROVFLEN (0x40) +#define MCF_USB_USBAIMR_EPSTALLEN (0x80) + +/* Bit definitions and macros for MCF_USB_EPINFO */ +#define MCF_USB_EPINFO_EPDIR (0x1) +#define MCF_USB_EPINFO_EPNUM(x) (((x)&0x7)<<0x1) + +/* Bit definitions and macros for MCF_USB_CFGR */ +#define MCF_USB_CFGR_Configuration_Value(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_CFGAR */ +#define MCF_USB_CFGAR_RESERVED (0xA0) +#define MCF_USB_CFGAR_RMTWKEUP (0xE0) + +/* Bit definitions and macros for MCF_USB_SPEEDR */ +#define MCF_USB_SPEEDR_SPEED(x) (((x)&0x3)<<0) + +/* Bit definitions and macros for MCF_USB_FRMNUMR */ +#define MCF_USB_FRMNUMR_FRMNUM(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPTNR */ +#define MCF_USB_EPTNR_EP1T(x) (((x)&0x3)<<0) +#define MCF_USB_EPTNR_EP2T(x) (((x)&0x3)<<0x2) +#define MCF_USB_EPTNR_EP3T(x) (((x)&0x3)<<0x4) +#define MCF_USB_EPTNR_EP4T(x) (((x)&0x3)<<0x6) +#define MCF_USB_EPTNR_EP5T(x) (((x)&0x3)<<0x8) +#define MCF_USB_EPTNR_EP6T(x) (((x)&0x3)<<0xA) +#define MCF_USB_EPTNR_EPnT1 (0) +#define MCF_USB_EPTNR_EPnT2 (0x1) +#define MCF_USB_EPTNR_EPnT3 (0x2) + +/* Bit definitions and macros for MCF_USB_IFUR */ +#define MCF_USB_IFUR_ALTSET(x) (((x)&0xFF)<<0) +#define MCF_USB_IFUR_IFNUM(x) (((x)&0xFF)<<0x8) + +/* Bit definitions and macros for MCF_USB_IFR */ +#define MCF_USB_IFR_ALTSET(x) (((x)&0xFF)<<0) +#define MCF_USB_IFR_IFNUM(x) (((x)&0xFF)<<0x8) + +/* Bit definitions and macros for MCF_USB_PPCNT */ +#define MCF_USB_PPCNT_PPCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_DPCNT */ +#define MCF_USB_DPCNT_DPCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_CRCECNT */ +#define MCF_USB_CRCECNT_CRCECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_BSECNT */ +#define MCF_USB_BSECNT_BSECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_PIDECNT */ +#define MCF_USB_PIDECNT_PIDECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_FRMECNT */ +#define MCF_USB_FRMECNT_FRMECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_TXPCNT */ +#define MCF_USB_TXPCNT_TXPCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_CNTOVR */ +#define MCF_USB_CNTOVR_PPCNT (0x1) +#define MCF_USB_CNTOVR_DPCNT (0x2) +#define MCF_USB_CNTOVR_CRCECNT (0x4) +#define MCF_USB_CNTOVR_BSECNT (0x8) +#define MCF_USB_CNTOVR_PIDECNT (0x10) +#define MCF_USB_CNTOVR_FRMECNT (0x20) +#define MCF_USB_CNTOVR_TXPCNT (0x40) + +/* Bit definitions and macros for MCF_USB_EP0ACR */ +#define MCF_USB_EP0ACR_TTYPE(x) (((x)&0x3)<<0) +#define MCF_USB_EP0ACR_TTYPE_CTRL (0) +#define MCF_USB_EP0ACR_TTYPE_ISOC (0x1) +#define MCF_USB_EP0ACR_TTYPE_BULK (0x2) +#define MCF_USB_EP0ACR_TTYPE_INT (0x3) + +/* Bit definitions and macros for MCF_USB_EP0MPSR */ +#define MCF_USB_EP0MPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0) +#define MCF_USB_EP0MPSR_ADDTRANS(x) (((x)&0x3)<<0xB) + +/* Bit definitions and macros for MCF_USB_EP0IFR */ +#define MCF_USB_EP0IFR_IFNUM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_EP0SR */ +#define MCF_USB_EP0SR_HALT (0x1) +#define MCF_USB_EP0SR_ACTIVE (0x2) +#define MCF_USB_EP0SR_PSTALL (0x4) +#define MCF_USB_EP0SR_CCOMP (0x8) +#define MCF_USB_EP0SR_TXZERO (0x20) +#define MCF_USB_EP0SR_INT (0x80) + +/* Bit definitions and macros for MCF_USB_BMRTR */ +#define MCF_USB_BMRTR_REC(x) (((x)&0x1F)<<0) +#define MCF_USB_BMRTR_REC_DEVICE (0) +#define MCF_USB_BMRTR_REC_INTERFACE (0x1) +#define MCF_USB_BMRTR_REC_ENDPOINT (0x2) +#define MCF_USB_BMRTR_REC_OTHER (0x3) +#define MCF_USB_BMRTR_TYPE(x) (((x)&0x3)<<0x5) +#define MCF_USB_BMRTR_TYPE_STANDARD (0) +#define MCF_USB_BMRTR_TYPE_CLASS (0x20) +#define MCF_USB_BMRTR_TYPE_VENDOR (0x40) +#define MCF_USB_BMRTR_DIR (0x80) + +/* Bit definitions and macros for MCF_USB_BRTR */ +#define MCF_USB_BRTR_BREQ(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_WVALUER */ +#define MCF_USB_WVALUER_WVALUE(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_WINDEXR */ +#define MCF_USB_WINDEXR_WINDEX(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_WLENGTHR */ +#define MCF_USB_WLENGTHR_WLENGTH(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPOUTACR */ +#define MCF_USB_EPOUTACR_TTYPE(x) (((x)&0x3)<<0) +#define MCF_USB_EPOUTACR_TTYPE_ISOC (0x1) +#define MCF_USB_EPOUTACR_TTYPE_BULK (0x2) +#define MCF_USB_EPOUTACR_TTYPE_INT (0x3) + +/* Bit definitions and macros for MCF_USB_EPOUTMPSR */ +#define MCF_USB_EPOUTMPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0) +#define MCF_USB_EPOUTMPSR_ADDTRANS(x) (((x)&0x3)<<0xB) + +/* Bit definitions and macros for MCF_USB_EPOUTIFR */ +#define MCF_USB_EPOUTIFR_IFNUM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPOUTSR */ +#define MCF_USB_EPOUTSR_HALT (0x1) +#define MCF_USB_EPOUTSR_ACTIVE (0x2) +#define MCF_USB_EPOUTSR_PSTALL (0x4) +#define MCF_USB_EPOUTSR_CCOMP (0x8) +#define MCF_USB_EPOUTSR_TXZERO (0x20) +#define MCF_USB_EPOUTSR_INT (0x80) + +/* Bit definitions and macros for MCF_USB_EPOUTSFR */ +#define MCF_USB_EPOUTSFR_FRMNUM(x) (((x)&0x7FF)<<0) + +/* Bit definitions and macros for MCF_USB_EPINACR */ +#define MCF_USB_EPINACR_TTYPE(x) (((x)&0x3)<<0) +#define MCF_USB_EPINACR_TTYPE_ISOC (0x1) +#define MCF_USB_EPINACR_TTYPE_BULK (0x2) +#define MCF_USB_EPINACR_TTYPE_INT (0x3) + +/* Bit definitions and macros for MCF_USB_EPINMPSR */ +#define MCF_USB_EPINMPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0) +#define MCF_USB_EPINMPSR_ADDTRANS(x) (((x)&0x3)<<0xB) + +/* Bit definitions and macros for MCF_USB_EPINIFR */ +#define MCF_USB_EPINIFR_IFNUM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPINSR */ +#define MCF_USB_EPINSR_HALT (0x1) +#define MCF_USB_EPINSR_ACTIVE (0x2) +#define MCF_USB_EPINSR_PSTALL (0x4) +#define MCF_USB_EPINSR_CCOMP (0x8) +#define MCF_USB_EPINSR_TXZERO (0x20) +#define MCF_USB_EPINSR_INT (0x80) + +/* Bit definitions and macros for MCF_USB_EPINSFR */ +#define MCF_USB_EPINSFR_FRMNUM(x) (((x)&0x7FF)<<0) + +/* Bit definitions and macros for MCF_USB_USBSR */ +#define MCF_USB_USBSR_ISOERREP(x) (((x)&0xF)<<0) +#define MCF_USB_USBSR_SUSP (0x80) + +/* Bit definitions and macros for MCF_USB_USBCR */ +#define MCF_USB_USBCR_RESUME (0x1) +#define MCF_USB_USBCR_APPLOCK (0x2) +#define MCF_USB_USBCR_RST (0x4) +#define MCF_USB_USBCR_RAMEN (0x8) +#define MCF_USB_USBCR_RAMSPLIT (0x20) + +/* Bit definitions and macros for MCF_USB_DRAMCR */ +#define MCF_USB_DRAMCR_DADR(x) (((x)&0x3FF)<<0) +#define MCF_USB_DRAMCR_DSIZE(x) (((x)&0x7FF)<<0x10) +#define MCF_USB_DRAMCR_BSY (0x40000000) +#define MCF_USB_DRAMCR_START (0x80000000) + +/* Bit definitions and macros for MCF_USB_DRAMDR */ +#define MCF_USB_DRAMDR_DDAT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_USBISR */ +#define MCF_USB_USBISR_ISOERR (0x1) +#define MCF_USB_USBISR_FTUNLCK (0x2) +#define MCF_USB_USBISR_SUSP (0x4) +#define MCF_USB_USBISR_RES (0x8) +#define MCF_USB_USBISR_UPDSOF (0x10) +#define MCF_USB_USBISR_RSTSTOP (0x20) +#define MCF_USB_USBISR_SOF (0x40) +#define MCF_USB_USBISR_MSOF (0x80) + +/* Bit definitions and macros for MCF_USB_USBIMR */ +#define MCF_USB_USBIMR_ISOERR (0x1) +#define MCF_USB_USBIMR_FTUNLCK (0x2) +#define MCF_USB_USBIMR_SUSP (0x4) +#define MCF_USB_USBIMR_RES (0x8) +#define MCF_USB_USBIMR_UPDSOF (0x10) +#define MCF_USB_USBIMR_RSTSTOP (0x20) +#define MCF_USB_USBIMR_SOF (0x40) +#define MCF_USB_USBIMR_MSOF (0x80) + +/* Bit definitions and macros for MCF_USB_EPSTAT */ +#define MCF_USB_EPSTAT_RST (0x1) +#define MCF_USB_EPSTAT_FLUSH (0x2) +#define MCF_USB_EPSTAT_DIR (0x80) +#define MCF_USB_EPSTAT_BYTECNT(x) (((x)&0xFFF)<<0x10) + +/* Bit definitions and macros for MCF_USB_EPISR */ +#define MCF_USB_EPISR_EOF (0x1) +#define MCF_USB_EPISR_EOT (0x4) +#define MCF_USB_EPISR_FIFOLO (0x10) +#define MCF_USB_EPISR_FIFOHI (0x20) +#define MCF_USB_EPISR_ERR (0x40) +#define MCF_USB_EPISR_EMT (0x80) +#define MCF_USB_EPISR_FU (0x100) + +/* Bit definitions and macros for MCF_USB_EPIMR */ +#define MCF_USB_EPIMR_EOF (0x1) +#define MCF_USB_EPIMR_EOT (0x4) +#define MCF_USB_EPIMR_FIFOLO (0x10) +#define MCF_USB_EPIMR_FIFOHI (0x20) +#define MCF_USB_EPIMR_ERR (0x40) +#define MCF_USB_EPIMR_EMT (0x80) +#define MCF_USB_EPIMR_FU (0x100) + +/* Bit definitions and macros for MCF_USB_EPFRCFGR */ +#define MCF_USB_EPFRCFGR_DEPTH(x) (((x)&0x1FFF)<<0) +#define MCF_USB_EPFRCFGR_BASE(x) (((x)&0xFFF)<<0x10) + +/* Bit definitions and macros for MCF_USB_EPFDR */ +#define MCF_USB_EPFDR_RX_TXDATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPFSR */ +#define MCF_USB_EPFSR_EMT (0x10000) +#define MCF_USB_EPFSR_ALRM (0x20000) +#define MCF_USB_EPFSR_FU (0x40000) +#define MCF_USB_EPFSR_FR (0x80000) +#define MCF_USB_EPFSR_OF (0x100000) +#define MCF_USB_EPFSR_UF (0x200000) +#define MCF_USB_EPFSR_RXW (0x400000) +#define MCF_USB_EPFSR_FAE (0x800000) +#define MCF_USB_EPFSR_FRM(x) (((x)&0xF)<<0x18) +#define MCF_USB_EPFSR_TXW (0x40000000) +#define MCF_USB_EPFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_USB_EPFCR */ +#define MCF_USB_EPFCR_COUNTER(x) (((x)&0xFFFF)<<0) +#define MCF_USB_EPFCR_TXWMSK (0x40000) +#define MCF_USB_EPFCR_OFMSK (0x80000) +#define MCF_USB_EPFCR_UFMSK (0x100000) +#define MCF_USB_EPFCR_RXWMSK (0x200000) +#define MCF_USB_EPFCR_FAEMSK (0x400000) +#define MCF_USB_EPFCR_IPMSK (0x800000) +#define MCF_USB_EPFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_USB_EPFCR_FRM (0x8000000) +#define MCF_USB_EPFCR_TMR (0x10000000) +#define MCF_USB_EPFCR_WFR (0x20000000) +#define MCF_USB_EPFCR_SHAD (0x80000000) + +/* Bit definitions and macros for MCF_USB_EPFAR */ +#define MCF_USB_EPFAR_ALRMP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPFRP */ +#define MCF_USB_EPFRP_RP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPFWP */ +#define MCF_USB_EPFWP_WP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPLRFP */ +#define MCF_USB_EPLRFP_LRFP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPLWFP */ +#define MCF_USB_EPLWFP_LWFP(x) (((x)&0xFFF)<<0) + + +#endif /* __MCF5475_USB_H__ */ diff --git a/tos/pci_test/include/MCF5475_XLB.h b/tos/pci_test/include/MCF5475_XLB.h new file mode 100644 index 0000000..af25ae7 --- /dev/null +++ b/tos/pci_test/include/MCF5475_XLB.h @@ -0,0 +1,101 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_XLB_H__ +#define __MCF5475_XLB_H__ + + +/********************************************************************* +* +* XL Bus Arbiter (XLB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_XLB_XARB_CFG (*(volatile uint32_t*)(&_MBAR[0x240])) +#define MCF_XLB_XARB_VER (*(volatile uint32_t*)(&_MBAR[0x244])) +#define MCF_XLB_XARB_SR (*(volatile uint32_t*)(&_MBAR[0x248])) +#define MCF_XLB_XARB_IMR (*(volatile uint32_t*)(&_MBAR[0x24C])) +#define MCF_XLB_XARB_ADRCAP (*(volatile uint32_t*)(&_MBAR[0x250])) +#define MCF_XLB_XARB_SIGCAP (*(volatile uint32_t*)(&_MBAR[0x254])) +#define MCF_XLB_XARB_ADRTO (*(volatile uint32_t*)(&_MBAR[0x258])) +#define MCF_XLB_XARB_DATTO (*(volatile uint32_t*)(&_MBAR[0x25C])) +#define MCF_XLB_XARB_BUSTO (*(volatile uint32_t*)(&_MBAR[0x260])) +#define MCF_XLB_XARB_PRIEN (*(volatile uint32_t*)(&_MBAR[0x264])) +#define MCF_XLB_XARB_PRI (*(volatile uint32_t*)(&_MBAR[0x268])) + + +/* Bit definitions and macros for MCF_XLB_XARB_CFG */ +#define MCF_XLB_XARB_CFG_AT (0x2) +#define MCF_XLB_XARB_CFG_DT (0x4) +#define MCF_XLB_XARB_CFG_BA (0x8) +#define MCF_XLB_XARB_CFG_PM(x) (((x)&0x3)<<0x5) +#define MCF_XLB_XARB_CFG_SP(x) (((x)&0x7)<<0x8) +#define MCF_XLB_XARB_CFG_PLDIS (0x80000000) + +/* Bit definitions and macros for MCF_XLB_XARB_VER */ +#define MCF_XLB_XARB_VER_VER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_SR */ +#define MCF_XLB_XARB_SR_AT (0x1) +#define MCF_XLB_XARB_SR_DT (0x2) +#define MCF_XLB_XARB_SR_BA (0x4) +#define MCF_XLB_XARB_SR_TTM (0x8) +#define MCF_XLB_XARB_SR_ECW (0x10) +#define MCF_XLB_XARB_SR_TTR (0x20) +#define MCF_XLB_XARB_SR_TTA (0x40) +#define MCF_XLB_XARB_SR_MM (0x80) +#define MCF_XLB_XARB_SR_SEA (0x100) + +/* Bit definitions and macros for MCF_XLB_XARB_IMR */ +#define MCF_XLB_XARB_IMR_ATE (0x1) +#define MCF_XLB_XARB_IMR_DTE (0x2) +#define MCF_XLB_XARB_IMR_BAE (0x4) +#define MCF_XLB_XARB_IMR_TTME (0x8) +#define MCF_XLB_XARB_IMR_ECWE (0x10) +#define MCF_XLB_XARB_IMR_TTRE (0x20) +#define MCF_XLB_XARB_IMR_TTAE (0x40) +#define MCF_XLB_XARB_IMR_MME (0x80) +#define MCF_XLB_XARB_IMR_SEAE (0x100) + +/* Bit definitions and macros for MCF_XLB_XARB_ADRCAP */ +#define MCF_XLB_XARB_ADRCAP_ADRCAP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_SIGCAP */ +#define MCF_XLB_XARB_SIGCAP_TT(x) (((x)&0x1F)<<0) +#define MCF_XLB_XARB_SIGCAP_TBST (0x20) +#define MCF_XLB_XARB_SIGCAP_TSIZ(x) (((x)&0x7)<<0x7) + +/* Bit definitions and macros for MCF_XLB_XARB_ADRTO */ +#define MCF_XLB_XARB_ADRTO_ADRTO(x) (((x)&0xFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_DATTO */ +#define MCF_XLB_XARB_DATTO_DATTO(x) (((x)&0xFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_BUSTO */ +#define MCF_XLB_XARB_BUSTO_BUSTO(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_PRIEN */ +#define MCF_XLB_XARB_PRIEN_M0 (0x1) +#define MCF_XLB_XARB_PRIEN_M2 (0x4) +#define MCF_XLB_XARB_PRIEN_M3 (0x8) + +/* Bit definitions and macros for MCF_XLB_XARB_PRI */ +#define MCF_XLB_XARB_PRI_M0P(x) (((x)&0x7)<<0) +#define MCF_XLB_XARB_PRI_M2P(x) (((x)&0x7)<<0x8) +#define MCF_XLB_XARB_PRI_M3P(x) (((x)&0x7)<<0xC) + + +#endif /* __MCF5475_XLB_H__ */ diff --git a/tos/pci_test/include/bas_string.h b/tos/pci_test/include/bas_string.h new file mode 100644 index 0000000..c743c95 --- /dev/null +++ b/tos/pci_test/include/bas_string.h @@ -0,0 +1,47 @@ +/* + * bas_string.h + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 26.02.2013 + * Author: Markus Fröschle + */ + +#ifndef BAS_STRING_H_ +#define BAS_STRING_H_ + +#include + +extern int strncmp(const char *s1, const char *s2, size_t max); +extern char *strcpy(char *dst, const char *src); +char *strncpy(char *dst, const char *src, size_t max); +extern int strcmp(const char *s1, const char *s2); +extern size_t strlen(const char *str); +extern char *strcat(char *dst, const char *src); +extern char *strncat(char *dst, const char *src, size_t max); +extern int atoi(const char *c); +extern void *memcpy(void *dst, const void *src, size_t n); +extern void *memset(void *s, int c, size_t n); +extern int memcmp(const void *s1, const void *s2, size_t max); +extern void bzero(void *s, size_t n); + +#define isdigit(c) (((c) >= '0') && ((c) <= '9')) +#define isupper(c) ((c) >= 'A' && ((c) <= 'Z')) +#define islower(c) ((c) >= 'a' && ((c) <= 'z')) +#define isalpha(c) (isupper((c)) || islower(c)) +#define tolower(c) (isupper(c) ? ((c) + 'a' - 'A') : (c)) + +#endif /* BAS_STRING_H_ */ diff --git a/tos/pci_test/include/bas_types.h b/tos/pci_test/include/bas_types.h new file mode 100644 index 0000000..4f692a1 --- /dev/null +++ b/tos/pci_test/include/bas_types.h @@ -0,0 +1,35 @@ +/* + * bas_types.h + * + * Created on: 17.11.2012 + * Author: mfro + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Copyright 2010 - 2012 F. Aschwanden + * Copyright 2011 - 2012 V. Riviere + * Copyright 2012 M. Froeschle + * + */ + +#ifndef BAS_TYPES_H_ +#define BAS_TYPES_H_ + +#include +#include +#include /* for sizeof() etc. */ + +#endif /* BAS_TYPES_H_ */ diff --git a/tos/pci_test/include/driver_vec.h b/tos/pci_test/include/driver_vec.h new file mode 100644 index 0000000..06220ef --- /dev/null +++ b/tos/pci_test/include/driver_vec.h @@ -0,0 +1,319 @@ +/* + * driver_vec.h + * + * Interface for exposure of BaS drivers to the OS + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 24.10.2013 + * Author: Markus Fröschle + */ + +#ifndef _DRIVER_VEC_H_ +#define _DRIVER_VEC_H_ + +#include "pci.h" + +enum driver_type +{ + BLOCKDEV_DRIVER, + CHARDEV_DRIVER, + XHDI_DRIVER, + MCD_DRIVER, + VIDEO_DRIVER, + PCI_DRIVER, + MMU_DRIVER, + PCI_NATIVE_DRIVER, + END_OF_DRIVERS = 0xffffffffL, /* marks end of driver list */ +}; + +struct generic_driver_interface +{ + uint32_t (*init)(void); + uint32_t (*read)(void *buf, size_t count); + uint32_t (*write)(const void *buf, size_t count); + uint32_t (*ioctl)(uint32_t request, ...); +}; + +struct dma_driver_interface +{ + int32_t version; + int32_t magic; + int (*dma_set_initiator)(int initiator); + uint32_t (*dma_get_initiator)(int requestor); + void (*dma_free_initiator)(int requestor); + int (*dma_set_channel)(int requestor, void (*handler)(void)); + int (*dma_get_channel)(int requestor); + void (*dma_free_channel)(int requestor); + void (*dma_clear_channel)(int channel); + int (*MCD_startDma)(long channel, + int8_t *srcAddr, unsigned int srcIncr, int8_t *destAddr, unsigned int destIncr, + unsigned int dmaSize, unsigned int xferSize, unsigned int initiator, int priority, + unsigned int flags, unsigned int funcDesc); + int32_t (*MCD_dmaStatus)(int32_t channel); + int32_t (*MCD_XferProgrQuery)(int32_t channel, /* MCD_XferProg */ void *progRep); + int32_t (*MCD_killDma)(int32_t channel); + int32_t (*MCD_continDma)(int32_t channel); + int32_t (*MCD_pauseDma)(int32_t channel); + int32_t (*MCD_resumeDma)(int32_t channel); + int32_t (*MCD_csumQuery)(int32_t channel, uint32_t *csum); + void *(*dma_malloc)(uint32_t amount); + int32_t (*dma_free)(void *addr); +}; + +struct xhdi_driver_interface +{ + uint32_t (*xhdivec)(); +}; + +/* + * Interpretation of offset for color fields: All offsets are from the right, + * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you + * can use the offset as right argument to <<). A pixel afterwards is a bit + * stream and is written to video memory as that unmodified. This implies + * big-endian byte order if bits_per_pixel is greater than 8. + */ +struct fb_bitfield +{ + unsigned long offset; /* beginning of bitfield */ + unsigned long length; /* length of bitfield */ + unsigned long msb_right; /* != 0 : Most significant bit is */ + /* right */ +}; + +/* + * the following structures define the interface to the BaS-builtin-framebuffer video driver + */ +struct fb_var_screeninfo +{ + unsigned long xres; /* visible resolution */ + unsigned long yres; + unsigned long xres_virtual; /* virtual resolution */ + unsigned long yres_virtual; + unsigned long xoffset; /* offset from virtual to visible */ + unsigned long yoffset; /* resolution */ + + unsigned long bits_per_pixel; /* guess what */ + unsigned long grayscale; /* != 0 Graylevels instead of colors */ + + struct fb_bitfield red; /* bitfield in fb mem if true color, */ + struct fb_bitfield green; /* else only length is significant */ + struct fb_bitfield blue; + struct fb_bitfield transp; /* transparency */ + + unsigned long nonstd; /* != 0 Non standard pixel format */ + + unsigned long activate; /* see FB_ACTIVATE_* */ + + unsigned long height; /* height of picture in mm */ + unsigned long width; /* width of picture in mm */ + + unsigned long accel_flags; /* (OBSOLETE) see fb_info.flags */ + + /* Timing: All values in pixclocks, except pixclock (of course) */ + unsigned long pixclock; /* pixel clock in ps (pico seconds) */ + unsigned long left_margin; /* time from sync to picture */ + unsigned long right_margin; /* time from picture to sync */ + unsigned long upper_margin; /* time from sync to picture */ + unsigned long lower_margin; + unsigned long hsync_len; /* length of horizontal sync */ + unsigned long vsync_len; /* length of vertical sync */ + unsigned long sync; /* see FB_SYNC_* */ + unsigned long vmode; /* see FB_VMODE_* */ + unsigned long rotate; /* angle we rotate counter clockwise */ + unsigned long refresh; + unsigned long reserved[4]; /* Reserved for future compatibility */ +}; + +struct fb_fix_screeninfo +{ + char id[16]; /* identification string eg "TT Builtin" */ + unsigned long smem_start; /* Start of frame buffer mem */ + /* (physical address) */ + unsigned long smem_len; /* Length of frame buffer mem */ + unsigned long type; /* see FB_TYPE_* */ + unsigned long type_aux; /* Interleave for interleaved Planes */ + unsigned long visual; /* see FB_VISUAL_* */ + unsigned short xpanstep; /* zero if no hardware panning */ + unsigned short ypanstep; /* zero if no hardware panning */ + unsigned short ywrapstep; /* zero if no hardware ywrap */ + unsigned long line_length; /* length of a line in bytes */ + unsigned long mmio_start; /* Start of Memory Mapped I/O */ + /* (physical address) */ + unsigned long mmio_len; /* Length of Memory Mapped I/O */ + unsigned long accel; /* Indicate to driver which */ + /* specific chip/card we have */ + unsigned short reserved[3]; /* Reserved for future compatibility */ +}; + +struct fb_chroma +{ + unsigned long redx; /* in fraction of 1024 */ + unsigned long greenx; + unsigned long bluex; + unsigned long whitex; + unsigned long redy; + unsigned long greeny; + unsigned long bluey; + unsigned long whitey; +}; + +struct fb_monspecs +{ + struct fb_chroma chroma; + struct fb_videomode *modedb; /* mode database */ + unsigned char manufacturer[4]; /* Manufacturer */ + unsigned char monitor[14]; /* Monitor String */ + unsigned char serial_no[14]; /* Serial Number */ + unsigned char ascii[14]; /* ? */ + unsigned long modedb_len; /* mode database length */ + unsigned long model; /* Monitor Model */ + unsigned long serial; /* Serial Number - Integer */ + unsigned long year; /* Year manufactured */ + unsigned long week; /* Week Manufactured */ + unsigned long hfmin; /* hfreq lower limit (Hz) */ + unsigned long hfmax; /* hfreq upper limit (Hz) */ + unsigned long dclkmin; /* pixelclock lower limit (Hz) */ + unsigned long dclkmax; /* pixelclock upper limit (Hz) */ + unsigned short input; /* display type - see FB_DISP_* */ + unsigned short dpms; /* DPMS support - see FB_DPMS_ */ + unsigned short signal; /* Signal Type - see FB_SIGNAL_* */ + unsigned short vfmin; /* vfreq lower limit (Hz) */ + unsigned short vfmax; /* vfreq upper limit (Hz) */ + unsigned short gamma; /* Gamma - in fractions of 100 */ + unsigned short gtf : 1; /* supports GTF */ + unsigned short misc; /* Misc flags - see FB_MISC_* */ + unsigned char version; /* EDID version... */ + unsigned char revision; /* ...and revision */ + unsigned char max_x; /* Maximum horizontal size (cm) */ + unsigned char max_y; /* Maximum vertical size (cm) */ +}; + +struct framebuffer_driver_interface +{ + struct fb_info **framebuffer_info; /* pointer to an fb_info struct (defined in include/fb.h) */ +}; + + +struct pci_bios_interface +{ + uint32_t subjar; + uint32_t version; + /* Although we declare this functions as standard gcc functions (cdecl), + * they expect parameters inside registers (fastcall) unsupported by gcc m68k. + * Caller will take care of parameters passing convention. + */ + int32_t (*find_pci_device)(uint32_t id, uint16_t index); + int32_t (*find_pci_classcode)(uint32_t class, uint16_t index); + int32_t (*read_config_byte)(int32_t handle, uint16_t reg, uint8_t *address); + int32_t (*read_config_word)(int32_t handle, uint16_t reg, uint16_t *address); + int32_t (*read_config_longword)(int32_t handle, uint16_t reg, uint32_t *address); + uint8_t (*fast_read_config_byte)(int32_t handle, uint16_t reg); + uint16_t (*fast_read_config_word)(int32_t handle, uint16_t reg); + uint32_t (*fast_read_config_longword)(int32_t handle, uint16_t reg); + int32_t (*write_config_byte)(int32_t handle, uint16_t reg, uint16_t val); + int32_t (*write_config_word)(int32_t handle, uint16_t reg, uint16_t val); + int32_t (*write_config_longword)(int32_t handle, uint16_t reg, uint32_t val); + int32_t (*hook_interrupt)(int32_t handle, uint32_t *routine, uint32_t *parameter); + int32_t (*unhook_interrupt)(int32_t handle); + int32_t (*special_cycle)(uint16_t bus, uint32_t data); + int32_t (*get_routing)(int32_t handle); + int32_t (*set_interrupt)(int32_t handle); + int32_t (*get_resource)(int32_t handle); + int32_t (*get_card_used)(int32_t handle, uint32_t *address); + int32_t (*set_card_used)(int32_t handle, uint32_t *callback); + int32_t (*read_mem_byte)(int32_t handle, uint32_t offset, uint8_t *address); + int32_t (*read_mem_word)(int32_t handle, uint32_t offset, uint16_t *address); + int32_t (*read_mem_longword)(int32_t handle, uint32_t offset, uint32_t *address); + uint8_t (*fast_read_mem_byte)(int32_t handle, uint32_t offset); + uint16_t (*fast_read_mem_word)(int32_t handle, uint32_t offset); + uint32_t (*fast_read_mem_longword)(int32_t handle, uint32_t offset); + int32_t (*write_mem_byte)(int32_t handle, uint32_t offset, uint16_t val); + int32_t (*write_mem_word)(int32_t handle, uint32_t offset, uint16_t val); + int32_t (*write_mem_longword)(int32_t handle, uint32_t offset, uint32_t val); + int32_t (*read_io_byte)(int32_t handle, uint32_t offset, uint8_t *address); + int32_t (*read_io_word)(int32_t handle, uint32_t offset, uint16_t *address); + int32_t (*read_io_longword)(int32_t handle, uint32_t offset, uint32_t *address); + uint8_t (*fast_read_io_byte)(int32_t handle, uint32_t offset); + uint16_t (*fast_read_io_word)(int32_t handle, uint32_t offset); + uint32_t (*fast_read_io_longword)(int32_t handle, uint32_t offset); + int32_t (*write_io_byte)(int32_t handle, uint32_t offset, uint16_t val); + int32_t (*write_io_word)(int32_t handle, uint32_t offset, uint16_t val); + int32_t (*write_io_longword)(int32_t handle, uint32_t offset, uint32_t val); + int32_t (*get_machine_id)(void); + int32_t (*get_pagesize)(void); + int32_t (*virt_to_bus)(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer); + int32_t (*bus_to_virt)(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer); + int32_t (*virt_to_phys)(uint32_t address, PCI_CONV_ADR *pointer); + int32_t (*phys_to_virt)(uint32_t address, PCI_CONV_ADR *pointer); + // int32_t reserved[2]; +}; + +struct mmu_driver_interface +{ + int32_t (*map_page_locked)(uint32_t address, uint32_t length, int asid); + int32_t (*unlock_page)(uint32_t address, uint32_t length, int asid); + int32_t (*report_locked_pages)(uint32_t *num_itlb, uint32_t *num_dtlb); + uint32_t (*report_pagesize)(void); +}; + +struct pci_native_driver_interface +{ + uint32_t (*pci_read_config_longword)(int32_t handle, int offset); + uint16_t (*pci_read_config_word)(int32_t handle, int offset); + uint8_t (*pci_read_config_byte)(int32_t handle, int offset); + + int32_t (*pci_write_config_longword)(int32_t handle, int offset, uint32_t value); + int32_t (*pci_write_config_word)(int32_t handle, int offset, uint16_t value); + int32_t (*pci_write_config_byte)(int32_t handle, int offset, uint8_t value); + int32_t (*pci_hook_interrupt)(int32_t handle, void *handler, void *parameter); + int32_t (*pci_unhook_interrupt)(int32_t handle); + int32_t (*pci_find_device)(uint16_t device_id, uint16_t vendor_id, int index); + int32_t (*pci_find_classcode)(uint32_t classcode, int index); + struct pci_rd * (*pci_get_resource)(int32_t handle); +}; + +union interface +{ + struct generic_driver_interface *gdi; + struct xhdi_driver_interface *xhdi; + struct dma_driver_interface *dma; + struct framebuffer_driver_interface *fb; + struct pci_bios_interface *pci; + struct mmu_driver_interface *mmu; + struct pci_native_driver_interface *pci_native; +}; + +struct generic_interface +{ + enum driver_type type; + char name[16]; + char description[64]; + int version; + int revision; + union interface interface; +}; + +struct driver_table +{ + uint32_t bas_version; + uint32_t bas_revision; + void (*remove_handler)(void); /* calling this will disable the BaS' hook into trap #0 */ + struct generic_interface *interfaces; +}; + + +#endif /* _DRIVER_VEC_H_ */ diff --git a/tos/pci_test/include/pci.h b/tos/pci_test/include/pci.h new file mode 100644 index 0000000..b912dd6 --- /dev/null +++ b/tos/pci_test/include/pci.h @@ -0,0 +1,360 @@ +#ifndef _PCI_H_ +#define _PCI_H_ + +/* + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 26.02.2013 + * Author: Markus Fröschle + */ + +#include +#include "util.h" /* for swpX() */ + +#define PCI_MEMORY_OFFSET 0x80000000 +#define PCI_MEMORY_SIZE 0x40000000 /* 1 GByte PCI memory window */ +#define PCI_IO_OFFSET 0xD0000000 +#define PCI_IO_SIZE 0x10000000 /* 256 MByte PCI I/O window */ + +#define PCI_LANESWAP_B(x) (x ^ 3) +#define PCI_LANESWAP_W(x) (x ^ 2) +#define PCI_LANESWAP_L(x) (x) /* for completeness only */ +/* + * Note: the byte offsets are in little endian format, so for pci_xxx_config_byte() + * accesses to hit the right offset, you'll need to wrap them into PCI_LANESWAP_B() + * and for pci_xxx_config_word() into PCI_LANESWAP_W() + */ +#define PCIIDR 0x00 /* PCI Configuration ID Register */ +#define PCICSR 0x04 /* PCI Command/Status Register */ +#define PCICR 0x06 /* PCI Command Register */ +#define PCISR 0x04 /* PCI Status Register */ +#define PCIREV 0x0B /* PCI Revision ID Register */ +#define PCICCR 0x08 /* PCI Class Code Register */ +#define PCICLSR 0x0F /* PCI Cache Line Size Register */ +#define PCILTR 0x0E /* PCI Latency Timer Register */ +#define PCIHTR 0x0D /* PCI Header Type Register */ +#define PCIBISTR 0x0C /* PCI Build-In Self Test Register */ + +#define PCIBAR0 0x10 /* PCI Base Address Register for Memory + Accesses to Local, Runtime, and DMA */ +#define PCIBAR1 0x14 /* PCI Base Address Register for I/O + Accesses to Local, Runtime, and DMA */ +#define PCIBAR2 0x18 /* PCI Base Address Register for Memory + Accesses to Local Address Space 0 */ +#define PCIBAR3 0x1C /* PCI Base Address Register for Memory + Accesses to Local Address Space 1 */ +#define PCIBAR4 0x20 /* PCI Base Address Register, reserved */ +#define PCIBAR5 0x24 /* PCI Base Address Register, reserved */ +#define PCICIS 0x28 /* PCI Cardbus CIS Pointer, not support*/ +#define PCISVID 0x2E /* PCI Subsystem Vendor ID */ +#define PCISID 0x2D /* PCI Subsystem ID */ +#define PCIERBAR 0x30 /* PCI Expansion ROM Base Register */ +#define CAP_PTR 0x34 /* New Capability Pointer */ +#define PCIILR 0x3F /* PCI Interrupt Line Register */ +#define PCIIPR 0x3E /* PCI Interrupt Pin Register */ +#define PCIMGR 0x3D /* PCI Min_Gnt Register */ +#define PCIMLR 0x3C /* PCI Max_Lat Register */ +#define PMCAPID 0x40 /* Power Management Capability ID */ +#define PMNEXT 0x41 /* Power Management Next Capability + Pointer */ +#define PMC 0x42 /* Power Management Capabilities */ +#define PMCSR 0x44 /* Power Management Control/Status */ +#define PMCSR_BSE 0x46 /* PMCSR Bridge Support Extensions */ +#define PMDATA 0x47 /* Power Management Data */ +#define HS_CNTL 0x48 /* Hot Swap Control */ +#define HS_NEXT 0x49 /* Hot Swap Next Capability Pointer */ +#define HS_CSR 0x4A /* Hot Swap Control/Status */ +#define PVPDCNTL 0x4C /* PCI Vital Product Data Control */ +#define PVPD_NEXT 0x4D /* PCI Vital Product Data Next + Capability Pointer */ +#define PVPDAD 0x4E /* PCI Vital Product Data Address */ +#define PVPDATA 0x50 /* PCI VPD Data */ + +/* + * bit definitions for PCICSR lower half (Command Register) + */ +#define PCICR_IO (1 << 0) /* if set: device responds to I/O space accesses */ +#define PCICR_MEMORY (1 << 1) /* if set: device responds to memory space accesses */ +#define PCICR_MASTER (1 << 2) /* if set: device is master */ +#define PCICR_SPECIAL (1 << 3) /* if set: device reacts on special cycles */ +#define PCICR_MEMWI (1 << 4) /* if set: device deals with memory write and invalidate */ +#define PCICR_VGA_SNOOP (1 << 5) /* if set: capable of palette snoop */ +#define PCICR_PERR (1 << 6) /* if set: reacts to parity errors */ +#define PCICR_STEPPING (1 << 7) /* if set: stepping enabled */ +#define PCICR_SERR (1 << 8) /* if set: SERR pin enabled */ +#define PCICR_FAST_BTOB_E (1 << 9) /* if set: fast back-to-back enabled */ +#define PCICR_INT_DISABLE (1 << 10) /* if set: disable interrupts from this device */ +/* + * bit definitions for PCICSR upper half (Status Register) + */ +#define PCISR_INTERRUPT (1 << 3) /* device requested interrupt */ +#define PCISR_CAPABILITIES (1 << 4) /* if set, capabilities pointer is valid */ +#define PCISR_66MHZ (1 << 5) /* 66 MHz capable */ +#define PCISR_UDF (1 << 6) /* UDF supported */ +#define PCISR_FAST_BTOB (1 << 7) /* Fast back-to-back enabled */ +#define PCISR_DPARITY_ERROR (1 << 8) /* data parity error detected */ + +#define PCISR_T_ABORT_S (1 << 11) /* target abort signaled */ +#define PCISR_T_ABORT_R (1 << 12) /* target abort received */ +#define PCISR_M_ABORT_R (1 << 13) /* master abort received */ +#define PCISR_S_ERROR_S (1 << 14) /* system error signaled */ +#define PCISR_PARITY_ERR (1 << 15) /* data parity error */ + +/* Header type 1 (PCI-to-PCI bridges) */ +#define PCI_PRIMARY_BUS 0x1B /* Primary bus number */ +#define PCI_SECONDARY_BUS 0x1A /* Secondary bus number */ +#define PCI_SUBORDINATE_BUS 0x19 /* Highest bus number behind the bridge */ +#define PCI_SEC_LATENCY_TIMER 0x18 /* Latency timer for secondary interface */ +#define PCI_IO_BASE 0x1C /* I/O range behind the bridge */ +#define PCI_IO_LIMIT 0x1D +#define PCI_SEC_STATUS 0x1C /* Secondary status register, only bit 14 used */ +#define PCI_MEMORY_BASE 0x20 /* Memory range behind */ +#define PCI_MEMORY_LIMIT 0x22 +#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ +#define PCI_PREF_MEMORY_LIMIT 0x26 +#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ +#define PCI_PREF_LIMIT_UPPER32 0x2C +#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ +#define PCI_IO_LIMIT_UPPER16 0x32 +#define PCI_BRIDGE_CONTROL 0x3E /* Bridge Control */ + +struct pci_rd /* structure of resource descriptor */ +{ + unsigned short next; /* length of the following structure */ + unsigned short flags; /* type of resource and misc. flags */ + unsigned long start; /* start-address of resource */ + unsigned long length; /* length of resource */ + unsigned long offset; /* offset PCI to phys. CPU Address */ + unsigned long dmaoffset; /* offset for DMA-transfers */ +}; + +typedef struct /* structure of address conversion */ +{ + unsigned long adr; /* calculated address (CPU<->PCI) */ + unsigned long len; /* length of memory range */ +} PCI_CONV_ADR; + +/******************************************************************************/ +/* PCI-BIOS Error Codes */ +/******************************************************************************/ +#define PCI_SUCCESSFUL 0 /* everything's fine */ +#define PCI_FUNC_NOT_SUPPORTED -2 /* function not supported */ +#define PCI_BAD_VENDOR_ID -3 /* wrong Vendor ID */ +#define PCI_DEVICE_NOT_FOUND -4 /* PCI-Device not found */ +#define PCI_BAD_REGISTER_NUMBER -5 /* wrong register number */ +#define PCI_SET_FAILED -6 /* reserved for later use */ +#define PCI_BUFFER_TOO_SMALL -7 /* reserved for later use */ +#define PCI_GENERAL_ERROR -8 /* general BIOS error code */ +#define PCI_BAD_HANDLE -9 /* wrong/unknown PCI-handle */ + +/******************************************************************************/ +/* Flags used in Resource-Descriptor */ +/******************************************************************************/ +#define FLG_IO 0x4000 /* Ressource in IO range */ +#define FLG_ROM 0x2000 /* Expansion ROM */ +#define FLG_LAST 0x8000 /* last ressource */ +#define FLG_8BIT 0x0100 /* 8 bit accesses allowed */ +#define FLG_16BIT 0x0200 /* 16 bit accesses allowed */ +#define FLG_32BIT 0x0400 /* 32 bit accesses allowed */ +#define FLG_ENDMASK 0x000F /* mask for byte ordering */ + +/******************************************************************************/ +/* Values used in FLG_ENDMASK for Byte Ordering */ +/******************************************************************************/ +#define ORD_MOTOROLA 0 /* Motorola (big endian) */ +#define ORD_INTEL_AS 1 /* Intel (little endian), addr.swapped */ +#define ORD_INTEL_LS 2 /* Intel (little endian), lane swapped */ +#define ORD_UNKNOWN 15 /* unknown (BIOS-calls allowed only) */ + +/******************************************************************************/ +/* Status Info used in Device-Descriptor */ +/******************************************************************************/ +#define DEVICE_FREE 0 /* Device is not used */ +#define DEVICE_USED 1 /* Device is used by another driver */ +#define DEVICE_CALLBACK 2 /* used, but driver can be cancelled */ +#define DEVICE_AVAILABLE 3 /* used, not available */ +#define NO_DEVICE -1 /* no device detected */ + +/* PCI configuration space macros */ + +/* register 0x00 macros */ +#define PCI_DEVICE_ID(i) (uint16_t)(((i) & 0xffff0000) >> 16) +#define PCI_VENDOR_ID(i) (uint16_t) ((i) & 0xffff) + +/* register 0x04 macros */ +#define PCI_STATUS(i) ((i) & 0xffff) +#define PCI_COMMAND(i) (((i) >> 16) & 0xffff) + +/* register 0x08 macros */ +#define PCI_CLASS_CODE(i) (((i) & 0xff000000) >> 24) +#define PCI_SUBCLASS(i) (((i) & 0x00ff0000) >> 16) +#define PCI_PROG_IF(i) (((i) & 0x0000ff00) >> 8) +#define PCI_REVISION_ID(i) (((i) & 0x000000ff)) + +/* register 0x0c macros */ +#define PCI_BIST(i) (((i) & 0xff000000) >> 24) +#define PCI_HEADER_TYPE(i) (((i) & 0x00ff0000) >> 16) +#define PCI_LAT_TIMER(i) (((i) & 0x0000ff00) >> 8) +#define PCI_CACHELINE_SIZE(i) (((i) & 0x000000ff)) + +/* register 0x2c macros */ +#define PCI_SUBSYS_ID(i) ((i) & 0xffff0000) >> 16) +#define PCI_SUBSYS_VID(i) ((i) & 0xffff)) + +/* register 0x34 macros */ +#define PCI_CAPABILITIES(i) ((i) & 0xff) + +/* register 0x3c macros */ +#define PCI_MAX_LATENCY(i) (((i) & 0xff000000) >> 24) +#define PCI_MIN_GRANT(i) (((i) & 0xff0000) >> 16) +#define PCI_INTERRUPT_PIN(i) (((i) & 0xff00) >> 8) +#define PCI_INTERRUPT_LINE(i) (((i)) & 0xff) + +#define IS_PCI_MEM_BAR(i) ((i) & 1) == 0 +#define IS_PCI_IO_BAR(i) ((i) & 1) == 1 +#define PCI_MEMBAR_TYPE(i) (((i) & 0x6) >> 1) +#define PCI_IOBAR_ADR(i) (((i) & 0xfffffffc)) +#define PCI_MEMBAR_ADR(i) (((i) & 0xfffffff0)) + +extern void init_eport(void); +extern void init_xlbus_arbiter(void); +extern void init_pci(void); +extern int pci_handle2index(int32_t handle); + +extern int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index); +extern int32_t pci_find_classcode(uint32_t classcode, int index); + +extern int32_t pci_get_interrupt_cause(void); +extern int32_t pci_call_interrupt_chain(int32_t handle, int32_t data); + +/* + * match bits for pci_find_classcode() + */ +#define PCI_FIND_BASE_CLASS (1 << 26) +#define PCI_FIND_SUB_CLASS (1 << 25) +#define PCI_FIND_PROG_IF (1 << 24) + +extern uint32_t pci_read_config_longword(int32_t handle, int offset); +extern uint16_t pci_read_config_word(int32_t handle, int offset); +extern uint8_t pci_read_config_byte(int32_t handle, int offset); + +extern int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t value); +extern int32_t pci_write_config_word(int32_t handle, int offset, uint16_t value); +extern int32_t pci_write_config_byte(int32_t handle, int offset, uint8_t value); + +typedef int (*pci_interrupt_handler)(int param); + +extern int32_t pci_hook_interrupt(int32_t handle, void *handler, void *parameter); +extern int32_t pci_unhook_interrupt(int32_t handle); + +extern struct pci_rd *pci_get_resource(int32_t handle); + +/* + * Not implemented PCI_BIOS functions + */ +extern uint8_t pci_fast_read_config_byte(int32_t handle, uint16_t reg); +extern uint16_t pci_fast_read_config_word(int32_t handle, uint16_t reg); +extern uint32_t pci_fast_read_config_longword(int32_t handle, uint16_t reg); +extern int32_t pci_special_cycle(uint16_t bus, uint32_t data); +extern int32_t pci_get_routing(int32_t handle); +extern int32_t pci_set_interrupt(int32_t handle); +extern int32_t pci_get_card_used(int32_t handle, uint32_t *address); +extern int32_t pci_set_card_used(int32_t handle, uint32_t *callback); +extern int32_t pci_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address); +extern int32_t pci_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address); +extern int32_t pci_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address); +extern uint8_t pci_fast_read_mem_byte(int32_t handle, uint32_t offset); +extern uint16_t pci_fast_read_mem_word(int32_t handle, uint32_t offset); +extern uint32_t pci_fast_read_mem_longword(int32_t handle, uint32_t offset); +extern int32_t pci_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val); +extern int32_t pci_write_mem_word(int32_t handle, uint32_t offset, uint16_t val); +extern int32_t pci_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val); +extern int32_t pci_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address); +extern int32_t pci_read_io_word(int32_t handle, uint32_t offset, uint16_t *address); +extern int32_t pci_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address); +extern uint8_t pci_fast_read_io_byte(int32_t handle, uint32_t offset); +extern uint16_t pci_fast_read_io_word(int32_t handle, uint32_t offset); +extern uint32_t pci_fast_read_io_longword(int32_t handle, uint32_t offset); +extern int32_t pci_write_io_byte(int32_t handle, uint32_t offset, uint16_t val); +extern int32_t pci_write_io_word(int32_t handle, uint32_t offset, uint16_t val); +extern int32_t pci_write_io_longword(int32_t handle, uint32_t offset, uint32_t val); +extern int32_t pci_get_machine_id(void); +extern int32_t pci_get_pagesize(void); +extern int32_t pci_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer); +extern int32_t pci_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer); +extern int32_t pci_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer); +extern int32_t pci_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer); + +/* + * prototypes for PCI wrapper routines + */ +extern int32_t wrapper_find_pci_device(uint32_t id, uint16_t index); +extern int32_t wrapper_find_pci_classcode(uint32_t class, uint16_t index); +extern int32_t wrapper_read_config_byte(int32_t handle, uint16_t reg, uint8_t *address); +extern int32_t wrapper_read_config_word(int32_t handle, uint16_t reg, uint16_t *address); +extern int32_t wrapper_read_config_longword(int32_t handle, uint16_t reg, uint32_t *address); +extern uint8_t wrapper_fast_read_config_byte(int32_t handle, uint16_t reg); +extern uint16_t wrapper_fast_read_config_word(int32_t handle, uint16_t reg); +extern uint32_t wrapper_fast_read_config_longword(int32_t handle, uint16_t reg); +extern int32_t wrapper_write_config_byte(int32_t handle, uint16_t reg, uint16_t val); +extern int32_t wrapper_write_config_word(int32_t handle, uint16_t reg, uint16_t val); +extern int32_t wrapper_write_config_longword(int32_t handle, uint16_t reg, uint32_t val); +extern int32_t wrapper_hook_interrupt(int32_t handle, uint32_t *routine, uint32_t *parameter); +extern int32_t wrapper_unhook_interrupt(int32_t handle); +extern int32_t wrapper_special_cycle(uint16_t bus, uint32_t data); +extern int32_t wrapper_get_routing(int32_t handle); +extern int32_t wrapper_set_interrupt(int32_t handle); +extern int32_t wrapper_get_resource(int32_t handle); +extern int32_t wrapper_get_card_used(int32_t handle, uint32_t *address); +extern int32_t wrapper_set_card_used(int32_t handle, uint32_t *callback); +extern int32_t wrapper_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address); +extern int32_t wrapper_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address); +extern int32_t wrapper_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address); +extern uint8_t wrapper_fast_read_mem_byte(int32_t handle, uint32_t offset); +extern uint16_t wrapper_fast_read_mem_word(int32_t handle, uint32_t offset); +extern uint32_t wrapper_fast_read_mem_longword(int32_t handle, uint32_t offset); +extern int32_t wrapper_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val); +extern int32_t wrapper_write_mem_word(int32_t handle, uint32_t offset, uint16_t val); +extern int32_t wrapper_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val); +extern int32_t wrapper_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address); +extern int32_t wrapper_read_io_word(int32_t handle, uint32_t offset, uint16_t *address); +extern int32_t wrapper_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address); +extern uint8_t wrapper_fast_read_io_byte(int32_t handle, uint32_t offset); +extern uint16_t wrapper_fast_read_io_word(int32_t handle, uint32_t offset); +extern uint32_t wrapper_fast_read_io_longword(int32_t handle, uint32_t offset); +extern int32_t wrapper_write_io_byte(int32_t handle, uint32_t offset, uint16_t val); +extern int32_t wrapper_write_io_word(int32_t handle, uint32_t offset, uint16_t val); +extern int32_t wrapper_write_io_longword(int32_t handle, uint32_t offset, uint32_t val); +extern int32_t wrapper_get_machine_id(void); +extern int32_t wrapper_get_pagesize(void); +extern int32_t wrapper_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer); +extern int32_t wrapper_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer); +extern int32_t wrapper_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer); +extern int32_t wrapper_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer); + +#define PCI_MK_CONF_ADDR(bus, device, function) (MCF_PCI_PCICAR_E | \ + ((bus) << 16) | \ + ((device << 8) | \ + (function)) + +#define PCI_HANDLE(bus, slot, function) (0 | ((bus & 0xff) << 10 | (slot & 0x1f) << 3 | (function & 7))) +#define PCI_BUS_FROM_HANDLE(h) (((h) & 0xff00) >> 10) +#define PCI_DEVICE_FROM_HANDLE(h) (((h) & 0xf8) >> 3) +#define PCI_FUNCTION_FROM_HANDLE(h) (((h) & 0x7)) + +extern void pci_dump_registers(int32_t handle); + +#endif /* _PCI_H_ */ diff --git a/tos/pci_test/include/util.h b/tos/pci_test/include/util.h new file mode 100644 index 0000000..355c1ac --- /dev/null +++ b/tos/pci_test/include/util.h @@ -0,0 +1,128 @@ +/* + * util.h + * + * Byteswapping macros lend from EmuTOS sources + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 27.10.2013 + * Author: mfro + */ + +#ifndef UTIL_H_ +#define UTIL_H_ + +#include + +#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory") + +/* + * uint16_t swpw(uint16_t val); + * swap endianess of val, 16 bits only. + */ +static inline uint16_t swpw(uint16_t w) +{ + return (w << 8) | (w >> 8); +} + +/* + * uint32_t swpl(uint32_t val); + * swap endianess of val, 32 bits only. + * e.g. ABCD => DCBA + */ +static inline uint32_t swpl(uint32_t l) +{ + return ((l & 0xff000000) >> 24) | ((l & 0x00ff0000) >> 8) | + ((l & 0x0000ff00) << 8) | (l << 24); +} + + +/* + * WORD swpw2(ULONG val); + * swap endianness of val, treated as two 16-bit words. + * e.g. ABCD => BADC + */ + +#define swpw2(a) \ + __extension__ \ + ({unsigned long _tmp; \ + __asm__ __volatile__ \ + ("move.b (%1),%0\n\t" \ + "move.b 1(%1),(%1)\n\t" \ + "move.b %0,1(%1)\n\t" \ + "move.b 2(%1),%0\n\t" \ + "move.b 3(%1),2(%1)\n\t" \ + "move.b %0,3(%1)" \ + : "=d"(_tmp) /* outputs */ \ + : "a"(&a) /* inputs */ \ + : "cc", "memory" /* clobbered */ \ + ); \ + }) + +/* + * WORD set_sr(WORD new); + * sets sr to the new value, and return the old sr value + */ + +#define set_sr(a) \ +__extension__ \ +({short _r, _a = (a); \ + __asm__ __volatile__ \ + ("move.w sr,%0\n\t" \ + "move.w %1,sr" \ + : "=&d"(_r) /* outputs */ \ + : "nd"(_a) /* inputs */ \ + : "cc", "memory" /* clobbered */ \ + ); \ + _r; \ +}) + + +/* + * WORD get_sr(void); + * returns the current value of sr. + */ + +#define get_sr() \ +__extension__ \ +({short _r; \ + __asm__ volatile \ + ("move.w sr,%0" \ + : "=dm"(_r) /* outputs */ \ + : /* inputs */ \ + : "cc", "memory" /* clobbered */ \ + ); \ + _r; \ +}) + + + +/* + * void regsafe_call(void *addr) + * Saves all registers to the stack, calls the function + * that addr points to, and restores the registers afterwards. + */ +#define regsafe_call(addr) \ +__extension__ \ +({__asm__ volatile ("lea -60(sp),sp\n\t" \ + "movem.l d0-d7/a0-a6,(sp)"); \ + ((void (*) (void)) addr)(); \ + __asm__ volatile ("movem.l (sp),d0-d7/a0-a6\n\t" \ + "lea 60(sp),sp"); \ +}) + + +#endif /* UTIL_H_ */ diff --git a/tos/pci_test/pci_test.config b/tos/pci_test/pci_test.config new file mode 100644 index 0000000..8cec188 --- /dev/null +++ b/tos/pci_test/pci_test.config @@ -0,0 +1 @@ +// ADD PREDEFINED MACROS HERE! diff --git a/tos/pci_test/pci_test.creator b/tos/pci_test/pci_test.creator new file mode 100644 index 0000000..e94cbbd --- /dev/null +++ b/tos/pci_test/pci_test.creator @@ -0,0 +1 @@ +[General] diff --git a/tos/pci_test/pci_test.files b/tos/pci_test/pci_test.files new file mode 100644 index 0000000..e5b8568 --- /dev/null +++ b/tos/pci_test/pci_test.files @@ -0,0 +1,6 @@ +include/driver_vec.h +Makefile +sources/bas_printf.c +sources/bas_string.c +sources/printf_helper.S +sources/pci_test.c diff --git a/tos/pci_test/pci_test.includes b/tos/pci_test/pci_test.includes new file mode 100644 index 0000000..0e46827 --- /dev/null +++ b/tos/pci_test/pci_test.includes @@ -0,0 +1,2 @@ +include +/usr/m68k-atari-mint/include diff --git a/tos/pci_test/sources/pci_test.c b/tos/pci_test/sources/pci_test.c new file mode 100644 index 0000000..916a240 --- /dev/null +++ b/tos/pci_test/sources/pci_test.c @@ -0,0 +1,321 @@ +#include +#include +#include +#include +#include + +#include "MCF5475.h" +#include "driver_vec.h" +#include "pci.h" + +#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory") + +#define SYSCLK 132000 + +#define KB 1024UL +#define MB (KB * KB) + +volatile int32_t time, start, end; +int i; + +/* + * PCI device class descriptions displayed during PCI bus scan + */ +static struct pci_class +{ + int classcode; + char *description; +} pci_classes[] = +{ + { 0x00, "device was built prior definition of the class code field" }, + { 0x01, "Mass Storage Controller" }, + { 0x02, "Network Controller" }, + { 0x03, "Display Controller" }, + { 0x04, "Multimedia Controller" }, + { 0x05, "Memory Controller" }, + { 0x06, "Bridge Device" }, + { 0x07, "Simple Communication Controller" }, + { 0x08, "Base System Peripherial" }, + { 0x09, "Input Device" }, + { 0x0a, "Docking Station" }, + { 0x0b, "Processor" }, + { 0x0c, "Serial Bus Controller" }, + { 0x0d, "Wireless Controller" }, + { 0x0e, "Intelligent I/O Controller" }, + { 0x0f, "Satellite Communication Controller" }, + { 0x10, "Encryption/Decryption Controller" }, + { 0x11, "Data Acquisition and Signal Processing Controller" }, + { 0xff, "Device does not fit any defined class" }, +}; +static int num_pci_classes = sizeof(pci_classes) / sizeof(struct pci_class); + +/* + * retrieve device class (in cleartext) for a PCI classcode + */ +static char *device_class(int classcode) +{ + int i; + + for (i = 0; i < num_pci_classes; i++) + { + if (pci_classes[i].classcode == classcode) + { + return pci_classes[i].description; + } + } + return "unknown device class"; +} + +void hexdump(uint8_t buffer[], int size) +{ + int i; + int line = 0; + uint8_t *bp = buffer; + + while (bp < buffer + size) + { + uint8_t *lbp = bp; + + printf("%08lx ", (long) buffer + line); + + for (i = 0; i < 16; i++) + { + if (bp + i > buffer + size) + { + break; + } + printf("%02x ", (uint8_t) *lbp++); + } + + lbp = bp; + for (i = 0; i < 16; i++) + { + int8_t c = *lbp++; + + if (bp + i > buffer + size) + { + break; + } + if (c > ' ' && c < '~') + { + printf("%c", c); + } + else + { + printf("."); + } + } + printf("\r\n"); + + bp += 16; + line += 16; + } +} + +void do_tests(struct pci_native_driver_interface *pci) +{ +#define PCI_READ_CONFIG_LONGWORD(a, b) pci->pci_read_config_longword(a, b) +#define PCI_WRITE_CONFIG_LONGWORD(a, b) pci->pci_write_config_longword(a, b) + + + printf("enumerate PCI devices\r\n"); + + int16_t handle; + int16_t index = 0; + + printf("\r\nPCI bus scan...\r\n\r\n"); + printf(" Bus| Dev|Func|Vndr|D-ID|Hndl|\r\n"); + printf("----+----+----+----+----+----+\r\n"); + + handle = (*pci->pci_find_device)(0x0, 0xFFFF, index); + + while (handle > 0) + { + uint32_t value; + + value = swpl((*pci->pci_read_config_longword)(handle, PCIIDR)); + + printf(" %02x | %02x | %02x |%04x|%04x|%04x| %s (0x%02x, 0x%04x)\r\n", + PCI_BUS_FROM_HANDLE(handle), + PCI_DEVICE_FROM_HANDLE(handle), + PCI_FUNCTION_FROM_HANDLE(handle), + PCI_VENDOR_ID(value), PCI_DEVICE_ID(value), + handle, + device_class((*pci->pci_read_config_byte)(handle, PCI_LANESWAP_B(PCICCR))), + (*pci->pci_read_config_byte)(handle, PCI_LANESWAP_B(PCICCR)), + (*pci->pci_read_config_word)(handle, PCI_LANESWAP_W(PCICCR))); + + handle = (*pci->pci_find_device)(0x0, 0xFFFF, ++index); + } + + struct pci_rd *rd; + int flags; + + /* + * look for an ATI Radeon video card + */ + + // handle = 0xd8; + handle = (*pci->pci_find_device)(0x5159, 0x1002, 0); + if (handle > 0) + { + rd = (*pci->pci_get_resource)(handle); /* get resource descriptor for ATI graphics card */ + if (rd != NULL) + { + do + { + flags = rd->flags; + + printf("Start address: 0x%08lx\r\n", rd->start); + printf("Length: 0x%08lx\r\n", rd->length); + printf("Offset: 0x%08lx\r\n", rd->offset); + printf("DMA offset: 0x%08lx\r\n", rd->dmaoffset); + printf("FLAGS: %s%s%s%s%s%s%s\r\n", + flags & FLG_IO ? "FLG_IO, " : "", + flags & FLG_ROM ? "FLG_ROM, " : "", + flags & FLG_8BIT ? "FLG_8BIT, " : "", + flags & FLG_16BIT ? "FLG_16BIT, " : "", + flags & FLG_32BIT ? "FLG_32BIT, " : "", + (flags & FLG_ENDMASK) == ORD_MOTOROLA ? "ORD_MOTOROLA" : + (flags & FLG_ENDMASK) == ORD_INTEL_AS ? "ORD_INTEL_AS" : + (flags & FLG_ENDMASK) == ORD_INTEL_LS ? "ORD_INTEL_LS" : + (flags & FLG_ENDMASK) == ORD_UNKNOWN ? "ORD_UNKNOWN" : + "", ""); + printf("\r\n"); + + if (rd->start != 0L && rd->start == 0x80000000) + { + hexdump((uint8_t *) rd->start + rd->offset, 64); + + memset((uint8_t *) rd-> start + rd->offset, 0, 64 * MB); + + printf("memory cleared\r\n"); + hexdump((uint8_t *) rd->start + rd->offset, 64); + + memset((uint8_t *) rd->start + rd->offset, 0xaa, 64 * MB); + hexdump((uint8_t *) rd->start + rd->offset, 64); + } + + rd = (struct pci_rd *) (((uintptr_t) rd) + (uintptr_t) rd->next); + } while (!(flags & FLG_LAST)); + } + else + { + printf("resource descriptor for handle 0x%02x not found\r\n", handle); + } + } + else + fprintf(stderr, "card not found\r\n"); + + printf("\r\n...finished\r\n"); +} + +/* + * temporarily replace the trap 0 handler with this so we can avoid + * getting caught by BaS versions that don't understand the driver interface + * exposure call. + * If we get here, we have a BaS version that doesn't support the trap 0 interface + */ +static void __attribute__((interrupt)) trap0_catcher(void) +{ + __asm__ __volatile__( + " clr.l d0 \n\t" // return 0 to indicate not supported + : + : + : + ); +} + +struct driver_table *get_bas_drivers(void) +{ + struct driver_table *ret = NULL; + void *old_vector; + + old_vector = Setexc(0x20, trap0_catcher); /* set our own temporarily */ + + __asm__ __volatile__( + " bra.s do_trap \n\t" + " .dc.l 0x5f424153 \n\t" // '_BAS' + "do_trap: trap #0 \n\t" + " move.l d0,%[ret] \n\t" + : [ret] "=m" (ret) /* output */ + : /* no inputs */ + : /* clobbered */ + ); + (void) Setexc(0x20, old_vector); /* restore original vector */ + + return ret; +} + +void pci_test(void) +{ + struct driver_table *bas_drivers; + struct generic_interface *ifc; + bool pci_driver_found = false; + struct pci_native_driver_interface *pci_driver = NULL; + + bas_drivers = get_bas_drivers(); + + /* + * trap0_catcher should return 0L on failure, for some reason FireTOS + * returns -1L on a trap #0. Anyway, ... + */ + if (bas_drivers != NULL && bas_drivers != (void *) -1L) + { + printf("BaS driver vector: %p\r\n", bas_drivers); + printf("BaS version: %ld.%02ld\r\n", (long) bas_drivers->bas_version, (long) bas_drivers->bas_revision); + } + else + { + printf("BaS driver retrieval not supported\r\n"); + printf("(old BaS version or FireTOS?)\r\n"); + exit(1); + } + + ifc = bas_drivers->interfaces; + + do + { + struct generic_interface *pci_driver_interface = NULL; + + printf("interface type: %ld\r\n", (long) ifc[i].type); + printf("interface version: %ld.%02ld\r\n", (long) ifc[i].version, (long) ifc[i].revision); + printf("interface name: %s\r\n", ifc[i].name); + printf("interface description: %s\r\n", ifc[i].description); + + if (ifc[i].type == PCI_NATIVE_DRIVER) + { + pci_driver_found = true; + + if (!pci_driver_interface || (ifc[i].version > pci_driver_interface->version || + (ifc[i].version == pci_driver_interface->version && ifc[i].revision > pci_driver_interface->revision))) + { + /* + * either no PCI driver interface found yet or with lower version or with lower version and higher revision + * + * replace it + */ + pci_driver = ifc[i].interface.pci_native; + pci_driver_interface = &ifc[i]; + printf("PCI native driver interface v%d.%02d found\r\n", pci_driver_interface->version, pci_driver_interface->revision); + printf("replaced old with newer driver version\r\n"); + } + } + } while (ifc[++i].type != END_OF_DRIVERS); + + if (pci_driver_found) + { + do_tests(pci_driver); + } +} + +int main(int argc, char *argv[]) +{ + printf("PCI test routines\r\n"); + printf("\xbd 2014 M. Fr\x94schle\r\n"); + + Supexec(pci_test); + + return 0; /* just to make the compiler happy, we will never return */ +} + diff --git a/tos/pci_test/sources/printf_helper.S b/tos/pci_test/sources/printf_helper.S new file mode 100644 index 0000000..e0b5c10 --- /dev/null +++ b/tos/pci_test/sources/printf_helper.S @@ -0,0 +1,38 @@ +/* + * printf_helper.S + * + * assembler trampoline to let printf (compiled -mpcrel) indirectly reference __MBAR + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Copyright 2010 - 2012 F. Aschwanden + * Copyright 2011 - 2012 V. Riviere + * Copyright 2012 - 2025 M. Froeschle + */ + + + .globl printf_helper + +printf_helper: + .extern __MBAR + +.wait_txready: + move.w __MBAR+0x8604,d2 // PSCSCR0 status register + btst #10,d2 // space left in TX fifo? + beq.s .wait_txready // no, loop + lea __MBAR+0x860C,a0 // PSCSTB0 transmitter buffer register + move.b d0,(a0) // send byte + rts diff --git a/tos/vmem_test/Makefile b/tos/vmem_test/Makefile new file mode 100755 index 0000000..2668436 --- /dev/null +++ b/tos/vmem_test/Makefile @@ -0,0 +1,109 @@ +CROSS=Y + +CROSSBINDIR_IS_Y=m68k-atari-mint- +CROSSBINDIR_IS_N= + +CROSSBINDIR=$(CROSSBINDIR_IS_$(CROSS)) + +UNAME := $(shell uname) +ifeq ($(CROSS), Y) +ifeq ($(UNAME),Linux) +PREFIX=m68k-atari-mint +HATARI=hatari +else +PREFIX=m68k-atari-mint +HATARI=/usr/local/bin/hatari +endif +else +PREFIX=/usr +endif + +DEPEND=depend +TOPDIR = ../.. + +LIBCMINI=$(TOPDIR)/../libcmini/libcmini + +INCLUDE=-I$(LIBCMINI)/include -nostdlib +LIBS=-lcmini -nostdlib -lgcc +CC=$(PREFIX)/bin/gcc + +CC=$(CROSSBINDIR)gcc +STRIP=$(CROSSBINDIR)strip +STACK=$(CROSSBINDIR)stack + +APP=vmem_test.prg +TEST_APP=$(APP) + +CFLAGS=\ + -O0\ + -g\ + -Wl,-Map,mapfile\ + -Wl,--defsym -Wl,__MBAR=0xff000000\ + -Wl,--defsym -Wl,__MMUBAR=0xff040000\ + -Wl,--defsym -Wl,__FPGA_JTAG_LOADED=0xff101000\ + -Wl,--defsym -Wl,__FPGA_JTAG_VALID=0xff101004\ + -Wl,--defsym -Wl,__VRAM=0x60000000\ + -Wall + +SRCDIR=sources +INCDIR=include +INCLUDE+=-I$(INCDIR) + +CSRCS=\ + $(SRCDIR)/vmem_test.c \ + $(SRCDIR)/bas_printf.c + +ASRCS=$(SRCDIR)/printf_helper.S + +COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS))) +AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS))) +OBJS=$(COBJS) $(AOBJS) + +TRGTDIRS=./m5475 ./m5475/mshort +OBJDIRS=$(patsubst %,%/objs,$(TRGTDIRS)) + +# +# multilib flags. These must match m68k-atari-mint-gcc -print-multi-lib output +# +m5475/$(APP):CFLAGS += -mcpu=5475 +m5475/mshort/$(APP): CFLAGS += -mcpu=5475 -mshort + +all:$(patsubst %,%/$(APP),$(TRGTDIRS)) +# +# generate pattern rules for multilib object files. +# +define CC_TEMPLATE +$(1)/objs/%.o:$(SRCDIR)/%.c + @echo CC $$< + @$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@ + +$(1)/objs/%.o:$(SRCDIR)/%.S + @echo CC $$< + @$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@ + +$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS)) +$(1)/$(APP): $$($(1)_OBJS) + @echo CC $$@ + @$(CC) $$(CFLAGS) -o $$@ $(LIBCMINI)/$(1)/startup.o $$($(1)_OBJS) -L$(LIBCMINI)/$(1) $(LIBS) + @$(STRIP) $$@ +endef +$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR)))) + +$(DEPEND): $(ASRCS) $(CSRCS) + @-rm -f $(DEPEND) + @for d in $(TRGTDIRS);\ + do $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e "s#^\(.*\).o:#$$d/objs/\1.o:#" >> $(DEPEND); \ + done + + +clean: + @rm -f $(patsubst %,%/objs/*.o,$(TRGTDIRS)) $(patsubst %,%/$(APP),$(TRGTDIRS)) + @rm -f $(DEPEND) mapfile + +.PHONY: printvars +printvars: + @$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V)))) + +ifneq (clean,$(MAKECMDGOALS)) +-include $(DEPEND) +endif diff --git a/tos/vmem_test/include/MCF5475.h b/tos/vmem_test/include/MCF5475.h new file mode 100644 index 0000000..5ab1750 --- /dev/null +++ b/tos/vmem_test/include/MCF5475.h @@ -0,0 +1,67 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_H__ +#define __MCF5475_H__ + +#include +/*** + * MCF5475 Derivative Memory map definitions from linker command files: + * __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE + * linker symbols must be defined in the linker command file. + */ + +typedef uint32_t __attribute__((__may_alias__)) uint32_t_a; /* a type to avoid gcc's complaints about pointer aliasing */ + +extern uint8_t _MBAR[]; +extern uint8_t _MMUBAR[]; +extern uint8_t _RAMBAR0[]; +extern uint8_t _RAMBAR0_SIZE[]; +extern uint8_t _RAMBAR1[]; +extern uint8_t _RAMBAR1_SIZE[]; + +#define MBAR_ADDRESS (uint32_t)_MBAR +#define MMUBAR_ADDRESS (uint32_t)_MMUBAR +#define RAMBAR0_ADDRESS (uint32_t)_RAMBAR0 +#define RAMBAR0_SIZE (uint32_t)_RAMBAR0_SIZE +#define RAMBAR1_ADDRESS (uint32_t)_RAMBAR1 +#define RAMBAR1_SIZE (uint32_t)_RAMBAR1_SIZE + + +#include "MCF5475_SIU.h" +#include "MCF5475_MMU.h" +#include "MCF5475_SDRAMC.h" +#include "MCF5475_XLB.h" +#include "MCF5475_CLOCK.h" +#include "MCF5475_FBCS.h" +#include "MCF5475_INTC.h" +#include "MCF5475_GPT.h" +#include "MCF5475_SLT.h" +#include "MCF5475_GPIO.h" +#include "MCF5475_PAD.h" +#include "MCF5475_PCI.h" +#include "MCF5475_PCIARB.h" +#include "MCF5475_EPORT.h" +#include "MCF5475_CTM.h" +#include "MCF5475_DMA.h" +#include "MCF5475_PSC.h" +#include "MCF5475_DSPI.h" +#include "MCF5475_I2C.h" +#include "MCF5475_FEC.h" +#include "MCF5475_USB.h" +#include "MCF5475_SRAM.h" +#include "MCF5475_SEC.h" + +#endif /* __MCF5475_H__ */ diff --git a/tos/vmem_test/include/MCF5475_CLOCK.h b/tos/vmem_test/include/MCF5475_CLOCK.h new file mode 100644 index 0000000..4603098 --- /dev/null +++ b/tos/vmem_test/include/MCF5475_CLOCK.h @@ -0,0 +1,47 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_CLOCK_H__ +#define __MCF5475_CLOCK_H__ + + +/********************************************************************* +* +* Clock Module (CLOCK) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CLOCK_SPCR (*(volatile uint32_t*)(&_MBAR[0x300])) + + +/* Bit definitions and macros for MCF_CLOCK_SPCR */ +#define MCF_CLOCK_SPCR_MEMEN (0x1) +#define MCF_CLOCK_SPCR_PCIEN (0x2) +#define MCF_CLOCK_SPCR_FBEN (0x4) +#define MCF_CLOCK_SPCR_CAN0EN (0x8) +#define MCF_CLOCK_SPCR_DMAEN (0x10) +#define MCF_CLOCK_SPCR_FEC0EN (0x20) +#define MCF_CLOCK_SPCR_FEC1EN (0x40) +#define MCF_CLOCK_SPCR_USBEN (0x80) +#define MCF_CLOCK_SPCR_PSCEN (0x200) +#define MCF_CLOCK_SPCR_CAN1EN (0x800) +#define MCF_CLOCK_SPCR_CRYENA (0x1000) +#define MCF_CLOCK_SPCR_CRYENB (0x2000) +#define MCF_CLOCK_SPCR_COREN (0x4000) +#define MCF_CLOCK_SPCR_PLLK (0x80000000) + + +#endif /* __MCF5475_CLOCK_H__ */ diff --git a/tos/vmem_test/include/MCF5475_CTM.h b/tos/vmem_test/include/MCF5475_CTM.h new file mode 100644 index 0000000..5ba86e4 --- /dev/null +++ b/tos/vmem_test/include/MCF5475_CTM.h @@ -0,0 +1,76 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_CTM_H__ +#define __MCF5475_CTM_H__ + + +/********************************************************************* +* +* Comm Timer Module (CTM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CTM_CTCR0 (*(volatile uint32_t*)(&_MBAR[0x7F00])) +#define MCF_CTM_CTCR1 (*(volatile uint32_t*)(&_MBAR[0x7F04])) +#define MCF_CTM_CTCR2 (*(volatile uint32_t*)(&_MBAR[0x7F08])) +#define MCF_CTM_CTCR3 (*(volatile uint32_t*)(&_MBAR[0x7F0C])) +#define MCF_CTM_CTCR4 (*(volatile uint32_t*)(&_MBAR[0x7F10])) +#define MCF_CTM_CTCR5 (*(volatile uint32_t*)(&_MBAR[0x7F14])) +#define MCF_CTM_CTCR6 (*(volatile uint32_t*)(&_MBAR[0x7F18])) +#define MCF_CTM_CTCR7 (*(volatile uint32_t*)(&_MBAR[0x7F1C])) +#define MCF_CTM_CTCRF(x) (*(volatile uint32_t*)(&_MBAR[0x7F00 + ((x)*0x4)])) +#define MCF_CTM_CTCRV(x) (*(volatile uint32_t*)(&_MBAR[0x7F10 + ((x-4)*0x4)])) + + +/* Bit definitions and macros for MCF_CTM_CTCRF */ +#define MCF_CTM_CTCRF_CRV(x) (((x)&0xFFFF)<<0) +#define MCF_CTM_CTCRF_S(x) (((x)&0xF)<<0x10) +#define MCF_CTM_CTCRF_S_CLK_1 (0) +#define MCF_CTM_CTCRF_S_CLK_2 (0x10000) +#define MCF_CTM_CTCRF_S_CLK_4 (0x20000) +#define MCF_CTM_CTCRF_S_CLK_8 (0x30000) +#define MCF_CTM_CTCRF_S_CLK_16 (0x40000) +#define MCF_CTM_CTCRF_S_CLK_32 (0x50000) +#define MCF_CTM_CTCRF_S_CLK_64 (0x60000) +#define MCF_CTM_CTCRF_S_CLK_128 (0x70000) +#define MCF_CTM_CTCRF_S_CLK_256 (0x80000) +#define MCF_CTM_CTCRF_S_CLK_EXT (0x90000) +#define MCF_CTM_CTCRF_PCT(x) (((x)&0x7)<<0x14) +#define MCF_CTM_CTCRF_PCT_100 (0) +#define MCF_CTM_CTCRF_PCT_50 (0x100000) +#define MCF_CTM_CTCRF_PCT_25 (0x200000) +#define MCF_CTM_CTCRF_PCT_12p5 (0x300000) +#define MCF_CTM_CTCRF_PCT_6p25 (0x400000) +#define MCF_CTM_CTCRF_PCT_OFF (0x500000) +#define MCF_CTM_CTCRF_M (0x800000) +#define MCF_CTM_CTCRF_IM (0x1000000) +#define MCF_CTM_CTCRF_I (0x80000000) + +/* Bit definitions and macros for MCF_CTM_CTCRV */ +#define MCF_CTM_CTCRV_CRV(x) (((x)&0xFFFFFF)<<0) +#define MCF_CTM_CTCRV_PCT(x) (((x)&0x7)<<0x18) +#define MCF_CTM_CTCRV_PCT_100 (0) +#define MCF_CTM_CTCRV_PCT_50 (0x1000000) +#define MCF_CTM_CTCRV_PCT_25 (0x2000000) +#define MCF_CTM_CTCRV_PCT_12p5 (0x3000000) +#define MCF_CTM_CTCRV_PCT_6p25 (0x4000000) +#define MCF_CTM_CTCRV_PCT_OFF (0x5000000) +#define MCF_CTM_CTCRV_M (0x8000000) +#define MCF_CTM_CTCRV_S (0x10000000) + + +#endif /* __MCF5475_CTM_H__ */ diff --git a/tos/vmem_test/include/MCF5475_DMA.h b/tos/vmem_test/include/MCF5475_DMA.h new file mode 100644 index 0000000..4e6f916 --- /dev/null +++ b/tos/vmem_test/include/MCF5475_DMA.h @@ -0,0 +1,234 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_DMA_H__ +#define __MCF5475_DMA_H__ + + +/********************************************************************* +* +* Multichannel DMA (DMA) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DMA_TASKBAR (*(volatile uint32_t*)(&_MBAR[0x8000])) +#define MCF_DMA_CP (*(volatile uint32_t*)(&_MBAR[0x8004])) +#define MCF_DMA_EP (*(volatile uint32_t*)(&_MBAR[0x8008])) +#define MCF_DMA_VP (*(volatile uint32_t*)(&_MBAR[0x800C])) +#define MCF_DMA_PTD (*(volatile uint32_t*)(&_MBAR[0x8010])) +#define MCF_DMA_DIPR (*(volatile uint32_t*)(&_MBAR[0x8014])) +#define MCF_DMA_DIMR (*(volatile uint32_t*)(&_MBAR[0x8018])) +#define MCF_DMA_TCR0 (*(volatile uint16_t*)(&_MBAR[0x801C])) +#define MCF_DMA_TCR1 (*(volatile uint16_t*)(&_MBAR[0x801E])) +#define MCF_DMA_TCR2 (*(volatile uint16_t*)(&_MBAR[0x8020])) +#define MCF_DMA_TCR3 (*(volatile uint16_t*)(&_MBAR[0x8022])) +#define MCF_DMA_TCR4 (*(volatile uint16_t*)(&_MBAR[0x8024])) +#define MCF_DMA_TCR5 (*(volatile uint16_t*)(&_MBAR[0x8026])) +#define MCF_DMA_TCR6 (*(volatile uint16_t*)(&_MBAR[0x8028])) +#define MCF_DMA_TCR7 (*(volatile uint16_t*)(&_MBAR[0x802A])) +#define MCF_DMA_TCR8 (*(volatile uint16_t*)(&_MBAR[0x802C])) +#define MCF_DMA_TCR9 (*(volatile uint16_t*)(&_MBAR[0x802E])) +#define MCF_DMA_TCR10 (*(volatile uint16_t*)(&_MBAR[0x8030])) +#define MCF_DMA_TCR11 (*(volatile uint16_t*)(&_MBAR[0x8032])) +#define MCF_DMA_TCR12 (*(volatile uint16_t*)(&_MBAR[0x8034])) +#define MCF_DMA_TCR13 (*(volatile uint16_t*)(&_MBAR[0x8036])) +#define MCF_DMA_TCR14 (*(volatile uint16_t*)(&_MBAR[0x8038])) +#define MCF_DMA_TCR15 (*(volatile uint16_t*)(&_MBAR[0x803A])) +#define MCF_DMA_PRIOR0 (*(volatile uint8_t *)(&_MBAR[0x803C])) +#define MCF_DMA_PRIOR1 (*(volatile uint8_t *)(&_MBAR[0x803D])) +#define MCF_DMA_PRIOR2 (*(volatile uint8_t *)(&_MBAR[0x803E])) +#define MCF_DMA_PRIOR3 (*(volatile uint8_t *)(&_MBAR[0x803F])) +#define MCF_DMA_PRIOR4 (*(volatile uint8_t *)(&_MBAR[0x8040])) +#define MCF_DMA_PRIOR5 (*(volatile uint8_t *)(&_MBAR[0x8041])) +#define MCF_DMA_PRIOR6 (*(volatile uint8_t *)(&_MBAR[0x8042])) +#define MCF_DMA_PRIOR7 (*(volatile uint8_t *)(&_MBAR[0x8043])) +#define MCF_DMA_PRIOR8 (*(volatile uint8_t *)(&_MBAR[0x8044])) +#define MCF_DMA_PRIOR9 (*(volatile uint8_t *)(&_MBAR[0x8045])) +#define MCF_DMA_PRIOR10 (*(volatile uint8_t *)(&_MBAR[0x8046])) +#define MCF_DMA_PRIOR11 (*(volatile uint8_t *)(&_MBAR[0x8047])) +#define MCF_DMA_PRIOR12 (*(volatile uint8_t *)(&_MBAR[0x8048])) +#define MCF_DMA_PRIOR13 (*(volatile uint8_t *)(&_MBAR[0x8049])) +#define MCF_DMA_PRIOR14 (*(volatile uint8_t *)(&_MBAR[0x804A])) +#define MCF_DMA_PRIOR15 (*(volatile uint8_t *)(&_MBAR[0x804B])) +#define MCF_DMA_PRIOR16 (*(volatile uint8_t *)(&_MBAR[0x804C])) +#define MCF_DMA_PRIOR17 (*(volatile uint8_t *)(&_MBAR[0x804D])) +#define MCF_DMA_PRIOR18 (*(volatile uint8_t *)(&_MBAR[0x804E])) +#define MCF_DMA_PRIOR19 (*(volatile uint8_t *)(&_MBAR[0x804F])) +#define MCF_DMA_PRIOR20 (*(volatile uint8_t *)(&_MBAR[0x8050])) +#define MCF_DMA_PRIOR21 (*(volatile uint8_t *)(&_MBAR[0x8051])) +#define MCF_DMA_PRIOR22 (*(volatile uint8_t *)(&_MBAR[0x8052])) +#define MCF_DMA_PRIOR23 (*(volatile uint8_t *)(&_MBAR[0x8053])) +#define MCF_DMA_PRIOR24 (*(volatile uint8_t *)(&_MBAR[0x8054])) +#define MCF_DMA_PRIOR25 (*(volatile uint8_t *)(&_MBAR[0x8055])) +#define MCF_DMA_PRIOR26 (*(volatile uint8_t *)(&_MBAR[0x8056])) +#define MCF_DMA_PRIOR27 (*(volatile uint8_t *)(&_MBAR[0x8057])) +#define MCF_DMA_PRIOR28 (*(volatile uint8_t *)(&_MBAR[0x8058])) +#define MCF_DMA_PRIOR29 (*(volatile uint8_t *)(&_MBAR[0x8059])) +#define MCF_DMA_PRIOR30 (*(volatile uint8_t *)(&_MBAR[0x805A])) +#define MCF_DMA_PRIOR31 (*(volatile uint8_t *)(&_MBAR[0x805B])) +#define MCF_DMA_IMCR (*(volatile uint32_t*)(&_MBAR[0x805C])) +#define MCF_DMA_TSKSZ0 (*(volatile uint32_t*)(&_MBAR[0x8060])) +#define MCF_DMA_TSKSZ1 (*(volatile uint32_t*)(&_MBAR[0x8064])) +#define MCF_DMA_DBGCOMP0 (*(volatile uint32_t*)(&_MBAR[0x8070])) +#define MCF_DMA_DBGCOMP2 (*(volatile uint32_t*)(&_MBAR[0x8074])) +#define MCF_DMA_DBGCTL (*(volatile uint32_t*)(&_MBAR[0x8078])) +#define MCF_DMA_TCR(x) (*(volatile uint16_t*)(&_MBAR[0x801C + ((x)*0x2)])) +#define MCF_DMA_PRIOR(x) (*(volatile uint8_t *)(&_MBAR[0x803C + ((x)*0x1)])) + + +/* Bit definitions and macros for MCF_DMA_TASKBAR */ +#define MCF_DMA_TASKBAR_TASK_BASE_ADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_CP */ +#define MCF_DMA_CP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_EP */ +#define MCF_DMA_EP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_VP */ +#define MCF_DMA_VP_VARIABLE_POINTER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_PTD */ +#define MCF_DMA_PTD_PCTL0 (0x1) +#define MCF_DMA_PTD_PCTL1 (0x2) +#define MCF_DMA_PTD_PCTL13 (0x2000) +#define MCF_DMA_PTD_PCTL14 (0x4000) +#define MCF_DMA_PTD_PCTL15 (0x8000) + +/* Bit definitions and macros for MCF_DMA_DIPR */ +#define MCF_DMA_DIPR_TASK(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DIMR */ +#define MCF_DMA_DIMR_TASK(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_TCR */ +#define MCF_DMA_TCR_ASTSKNUM(x) (((x)&0xF)<<0) +#define MCF_DMA_TCR_HLDINITNUM (0x20) +#define MCF_DMA_TCR_HIPRITSKEN (0x40) +#define MCF_DMA_TCR_ASTRT (0x80) +#define MCF_DMA_TCR_INITNUM(x) (((x)&0x1F)<<0x8) +#define MCF_DMA_TCR_ALWINIT (0x2000) +#define MCF_DMA_TCR_V (0x4000) +#define MCF_DMA_TCR_EN (0x8000) + +/* Bit definitions and macros for MCF_DMA_PRIOR */ +#define MCF_DMA_PRIOR_PRI(x) (((x)&0x7)<<0) +#define MCF_DMA_PRIOR_HLD (0x80) + +/* Bit definitions and macros for MCF_DMA_IMCR */ +#define MCF_DMA_IMCR_IMC16(x) (((x)&0x3)<<0) +#define MCF_DMA_IMCR_IMC17(x) (((x)&0x3)<<0x2) +#define MCF_DMA_IMCR_IMC18(x) (((x)&0x3)<<0x4) +#define MCF_DMA_IMCR_IMC19(x) (((x)&0x3)<<0x6) +#define MCF_DMA_IMCR_IMC20(x) (((x)&0x3)<<0x8) +#define MCF_DMA_IMCR_IMC21(x) (((x)&0x3)<<0xA) +#define MCF_DMA_IMCR_IMC22(x) (((x)&0x3)<<0xC) +#define MCF_DMA_IMCR_IMC23(x) (((x)&0x3)<<0xE) +#define MCF_DMA_IMCR_IMC24(x) (((x)&0x3)<<0x10) +#define MCF_DMA_IMCR_IMC25(x) (((x)&0x3)<<0x12) +#define MCF_DMA_IMCR_IMC26(x) (((x)&0x3)<<0x14) +#define MCF_DMA_IMCR_IMC27(x) (((x)&0x3)<<0x16) +#define MCF_DMA_IMCR_IMC28(x) (((x)&0x3)<<0x18) +#define MCF_DMA_IMCR_IMC29(x) (((x)&0x3)<<0x1A) +#define MCF_DMA_IMCR_IMC30(x) (((x)&0x3)<<0x1C) +#define MCF_DMA_IMCR_IMC31(x) (((x)&0x3)<<0x1E) + + +#define MCF_DMA_IMCR_IMC16_FEC0RX (0x00000000) +#define MCF_DMA_IMCR_IMC17_FEC0TX (0x00000000) +#define MCF_DMA_IMCR_IMC18_FEC0RX (0x00000020) +#define MCF_DMA_IMCR_IMC19_FEC0TX (0x00000080) +#define MCF_DMA_IMCR_IMC20_FEC1RX (0x00000100) +#define MCF_DMA_IMCR_IMC21_DREQ1 (0x00000000) +#define MCF_DMA_IMCR_IMC21_FEC1TX (0x00000400) +#define MCF_DMA_IMCR_IMC22_FEC0RX (0x00001000) +#define MCF_DMA_IMCR_IMC23_FEC0TX (0x00004000) +#define MCF_DMA_IMCR_IMC24_CTM0 (0x00010000) +#define MCF_DMA_IMCR_IMC24_FEC1RX (0x00020000) +#define MCF_DMA_IMCR_IMC25_CTM1 (0x00040000) +#define MCF_DMA_IMCR_IMC25_FEC1TX (0x00080000) +#define MCF_DMA_IMCR_IMC26_USBEP4 (0x00000000) +#define MCF_DMA_IMCR_IMC26_CTM2 (0x00200000) +#define MCF_DMA_IMCR_IMC27_USBEP5 (0x00000000) +#define MCF_DMA_IMCR_IMC27_CTM3 (0x00800000) +#define MCF_DMA_IMCR_IMC28_USBEP6 (0x00000000) +#define MCF_DMA_IMCR_IMC28_CTM4 (0x01000000) +#define MCF_DMA_IMCR_IMC28_DREQ1 (0x02000000) +#define MCF_DMA_IMCR_IMC28_PSC2RX (0x03000000) +#define MCF_DMA_IMCR_IMC29_DREQ1 (0x04000000) +#define MCF_DMA_IMCR_IMC29_CTM5 (0x08000000) +#define MCF_DMA_IMCR_IMC29_PSC2TX (0x0C000000) +#define MCF_DMA_IMCR_IMC30_FEC1RX (0x00000000) +#define MCF_DMA_IMCR_IMC30_CTM6 (0x10000000) +#define MCF_DMA_IMCR_IMC30_PSC3RX (0x30000000) +#define MCF_DMA_IMCR_IMC31_FEC1TX (0x00000000) +#define MCF_DMA_IMCR_IMC31_CTM7 (0x80000000) +#define MCF_DMA_IMCR_IMC31_PSC3TX (0xC0000000) + +/* Bit definitions and macros for MCF_DMA_TSKSZ0 */ +#define MCF_DMA_TSKSZ0_DSTSZ7(x) (((x)&0x3)<<0) +#define MCF_DMA_TSKSZ0_SRCSZ7(x) (((x)&0x3)<<0x2) +#define MCF_DMA_TSKSZ0_DSTSZ6(x) (((x)&0x3)<<0x4) +#define MCF_DMA_TSKSZ0_SRCSZ6(x) (((x)&0x3)<<0x6) +#define MCF_DMA_TSKSZ0_DSTSZ5(x) (((x)&0x3)<<0x8) +#define MCF_DMA_TSKSZ0_SRCSZ5(x) (((x)&0x3)<<0xA) +#define MCF_DMA_TSKSZ0_DSTSZ4(x) (((x)&0x3)<<0xC) +#define MCF_DMA_TSKSZ0_SRCSZ4(x) (((x)&0x3)<<0xE) +#define MCF_DMA_TSKSZ0_DSTSZ3(x) (((x)&0x3)<<0x10) +#define MCF_DMA_TSKSZ0_SRCSZ3(x) (((x)&0x3)<<0x12) +#define MCF_DMA_TSKSZ0_DSTSZ2(x) (((x)&0x3)<<0x14) +#define MCF_DMA_TSKSZ0_SRCSZ2(x) (((x)&0x3)<<0x16) +#define MCF_DMA_TSKSZ0_DSTSZ1(x) (((x)&0x3)<<0x18) +#define MCF_DMA_TSKSZ0_SRCSZ1(x) (((x)&0x3)<<0x1A) +#define MCF_DMA_TSKSZ0_DSTSZ0(x) (((x)&0x3)<<0x1C) +#define MCF_DMA_TSKSZ0_SRCSZ0(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_DMA_TSKSZ1 */ +#define MCF_DMA_TSKSZ1_DSTSZ15(x) (((x)&0x3)<<0) +#define MCF_DMA_TSKSZ1_SRCSZ15(x) (((x)&0x3)<<0x2) +#define MCF_DMA_TSKSZ1_DSTSZ14(x) (((x)&0x3)<<0x4) +#define MCF_DMA_TSKSZ1_SRCSZ14(x) (((x)&0x3)<<0x6) +#define MCF_DMA_TSKSZ1_DSTSZ13(x) (((x)&0x3)<<0x8) +#define MCF_DMA_TSKSZ1_SRCSZ13(x) (((x)&0x3)<<0xA) +#define MCF_DMA_TSKSZ1_DSTSZ12(x) (((x)&0x3)<<0xC) +#define MCF_DMA_TSKSZ1_SRCSZ12(x) (((x)&0x3)<<0xE) +#define MCF_DMA_TSKSZ1_DSTSZ11(x) (((x)&0x3)<<0x10) +#define MCF_DMA_TSKSZ1_SRCSZ11(x) (((x)&0x3)<<0x12) +#define MCF_DMA_TSKSZ1_DSTSZ10(x) (((x)&0x3)<<0x14) +#define MCF_DMA_TSKSZ1_SRCSZ10(x) (((x)&0x3)<<0x16) +#define MCF_DMA_TSKSZ1_DSTSZ9(x) (((x)&0x3)<<0x18) +#define MCF_DMA_TSKSZ1_SRCSZ9(x) (((x)&0x3)<<0x1A) +#define MCF_DMA_TSKSZ1_DSTSZ8(x) (((x)&0x3)<<0x1C) +#define MCF_DMA_TSKSZ1_SRCSZ8(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_DMA_DBGCOMP0 */ +#define MCF_DMA_DBGCOMP0_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DBGCOMP2 */ +#define MCF_DMA_DBGCOMP2_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DBGCTL */ +#define MCF_DMA_DBGCTL_I (0x2) +#define MCF_DMA_DBGCTL_E (0x4) +#define MCF_DMA_DBGCTL_AND_OR (0x80) +#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_2(x) (((x)&0x7)<<0x8) +#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_1(x) (((x)&0x7)<<0xB) +#define MCF_DMA_DBGCTL_B (0x4000) +#define MCF_DMA_DBGCTL_AA (0x8000) +#define MCF_DMA_DBGCTL_BLOCK_TASKS(x) (((x)&0xFFFF)<<0x10) + + +#endif /* __MCF5475_DMA_H__ */ diff --git a/tos/vmem_test/include/MCF5475_DSPI.h b/tos/vmem_test/include/MCF5475_DSPI.h new file mode 100644 index 0000000..76cac28 --- /dev/null +++ b/tos/vmem_test/include/MCF5475_DSPI.h @@ -0,0 +1,150 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_DSPI_H__ +#define __MCF5475_DSPI_H__ + + +/********************************************************************* +* +* DMA Serial Peripheral Interface (DSPI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DSPI_DMCR (*(volatile uint32_t*)(&_MBAR[0x8A00])) +#define MCF_DSPI_DTCR (*(volatile uint32_t*)(&_MBAR[0x8A08])) +#define MCF_DSPI_DCTAR0 (*(volatile uint32_t*)(&_MBAR[0x8A0C])) +#define MCF_DSPI_DCTAR1 (*(volatile uint32_t*)(&_MBAR[0x8A10])) +#define MCF_DSPI_DCTAR2 (*(volatile uint32_t*)(&_MBAR[0x8A14])) +#define MCF_DSPI_DCTAR3 (*(volatile uint32_t*)(&_MBAR[0x8A18])) +#define MCF_DSPI_DCTAR4 (*(volatile uint32_t*)(&_MBAR[0x8A1C])) +#define MCF_DSPI_DCTAR5 (*(volatile uint32_t*)(&_MBAR[0x8A20])) +#define MCF_DSPI_DCTAR6 (*(volatile uint32_t*)(&_MBAR[0x8A24])) +#define MCF_DSPI_DCTAR7 (*(volatile uint32_t*)(&_MBAR[0x8A28])) +#define MCF_DSPI_DSR (*(volatile uint32_t*)(&_MBAR[0x8A2C])) +#define MCF_DSPI_DIRSR (*(volatile uint32_t*)(&_MBAR[0x8A30])) +#define MCF_DSPI_DTFR (*(volatile uint32_t*)(&_MBAR[0x8A34])) +#define MCF_DSPI_DRFR (*(volatile uint32_t*)(&_MBAR[0x8A38])) +#define MCF_DSPI_DTFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A3C])) +#define MCF_DSPI_DTFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A40])) +#define MCF_DSPI_DTFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A44])) +#define MCF_DSPI_DTFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A48])) +#define MCF_DSPI_DRFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A7C])) +#define MCF_DSPI_DRFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A80])) +#define MCF_DSPI_DRFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A84])) +#define MCF_DSPI_DRFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A88])) +#define MCF_DSPI_DCTAR(x) (*(volatile uint32_t*)(&_MBAR[0x8A0C + ((x)*0x4)])) +#define MCF_DSPI_DTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A3C + ((x)*0x4)])) +#define MCF_DSPI_DRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A7C + ((x)*0x4)])) + + +/* Bit definitions and macros for MCF_DSPI_DMCR */ +#define MCF_DSPI_DMCR_HALT (0x1) +#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x3)<<0x8) +#define MCF_DSPI_DMCR_SMPL_PT_0CLK (0) +#define MCF_DSPI_DMCR_SMPL_PT_1CLK (0x100) +#define MCF_DSPI_DMCR_SMPL_PT_2CLK (0x200) +#define MCF_DSPI_DMCR_CRXF (0x400) +#define MCF_DSPI_DMCR_CTXF (0x800) +#define MCF_DSPI_DMCR_DRXF (0x1000) +#define MCF_DSPI_DMCR_DTXF (0x2000) +#define MCF_DSPI_DMCR_CSIS0 (0x10000) +#define MCF_DSPI_DMCR_CSIS2 (0x40000) +#define MCF_DSPI_DMCR_CSIS3 (0x80000) +#define MCF_DSPI_DMCR_CSIS5 (0x200000) +#define MCF_DSPI_DMCR_ROOE (0x1000000) +#define MCF_DSPI_DMCR_PCSSE (0x2000000) +#define MCF_DSPI_DMCR_MTFE (0x4000000) +#define MCF_DSPI_DMCR_FRZ (0x8000000) +#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x3)<<0x1C) +#define MCF_DSPI_DMCR_CSCK (0x40000000) +#define MCF_DSPI_DMCR_MSTR (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DTCR */ +#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_DSPI_DCTAR */ +#define MCF_DSPI_DCTAR_BR(x) (((x)&0xF)<<0) +#define MCF_DSPI_DCTAR_DT(x) (((x)&0xF)<<0x4) +#define MCF_DSPI_DCTAR_ASC(x) (((x)&0xF)<<0x8) +#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0xF)<<0xC) +#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x3)<<0x10) +#define MCF_DSPI_DCTAR_PBR_1CLK (0) +#define MCF_DSPI_DCTAR_PBR_3CLK (0x10000) +#define MCF_DSPI_DCTAR_PBR_5CLK (0x20000) +#define MCF_DSPI_DCTAR_PBR_7CLK (0x30000) +#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x3)<<0x12) +#define MCF_DSPI_DCTAR_PDT_1CLK (0) +#define MCF_DSPI_DCTAR_PDT_3CLK (0x40000) +#define MCF_DSPI_DCTAR_PDT_5CLK (0x80000) +#define MCF_DSPI_DCTAR_PDT_7CLK (0xC0000) +#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x3)<<0x14) +#define MCF_DSPI_DCTAR_PASC_1CLK (0) +#define MCF_DSPI_DCTAR_PASC_3CLK (0x100000) +#define MCF_DSPI_DCTAR_PASC_5CLK (0x200000) +#define MCF_DSPI_DCTAR_PASC_7CLK (0x300000) +#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x3)<<0x16) +#define MCF_DSPI_DCTAR_LSBFE (0x1000000) +#define MCF_DSPI_DCTAR_CPHA (0x2000000) +#define MCF_DSPI_DCTAR_CPOL (0x4000000) +#define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0xF)<<0x1B) + +/* Bit definitions and macros for MCF_DSPI_DSR */ +#define MCF_DSPI_DSR_RXPTR(x) (((x)&0xF)<<0) +#define MCF_DSPI_DSR_RXCTR(x) (((x)&0xF)<<0x4) +#define MCF_DSPI_DSR_TXPTR(x) (((x)&0xF)<<0x8) +#define MCF_DSPI_DSR_TXCTR(x) (((x)&0xF)<<0xC) +#define MCF_DSPI_DSR_RFDF (0x20000) +#define MCF_DSPI_DSR_RFOF (0x80000) +#define MCF_DSPI_DSR_TFFF (0x2000000) +#define MCF_DSPI_DSR_TFUF (0x8000000) +#define MCF_DSPI_DSR_EOQF (0x10000000) +#define MCF_DSPI_DSR_TXRXS (0x40000000) +#define MCF_DSPI_DSR_TCF (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DIRSR */ +#define MCF_DSPI_DIRSR_RFDFS (0x10000) +#define MCF_DSPI_DIRSR_RFDFE (0x20000) +#define MCF_DSPI_DIRSR_RFOFE (0x80000) +#define MCF_DSPI_DIRSR_TFFFS (0x1000000) +#define MCF_DSPI_DIRSR_TFFFE (0x2000000) +#define MCF_DSPI_DIRSR_TFUFE (0x8000000) +#define MCF_DSPI_DIRSR_EOQFE (0x10000000) +#define MCF_DSPI_DIRSR_TCFE (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DTFR */ +#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0xFFFF)<<0) +#define MCF_DSPI_DTFR_CS0 (0x10000) +#define MCF_DSPI_DTFR_CS2 (0x40000) +#define MCF_DSPI_DTFR_CS3 (0x80000) +#define MCF_DSPI_DTFR_CS5 (0x200000) +#define MCF_DSPI_DTFR_CTCNT (0x4000000) +#define MCF_DSPI_DTFR_EOQ (0x8000000) +#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x7)<<0x1C) +#define MCF_DSPI_DTFR_CONT (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DRFR */ +#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_DSPI_DTFDR */ +#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0xFFFF)<<0) +#define MCF_DSPI_DTFDR_TXCMD(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_DSPI_DRFDR */ +#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0xFFFF)<<0) + + +#endif /* __MCF5475_DSPI_H__ */ diff --git a/tos/vmem_test/include/MCF5475_EPORT.h b/tos/vmem_test/include/MCF5475_EPORT.h new file mode 100644 index 0000000..6506196 --- /dev/null +++ b/tos/vmem_test/include/MCF5475_EPORT.h @@ -0,0 +1,123 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_EPORT_H__ +#define __MCF5475_EPORT_H__ + + +/********************************************************************* +* +* Edge Port Module (EPORT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_EPORT_EPPAR (*(volatile uint16_t*)(&_MBAR[0xF00])) +#define MCF_EPORT_EPDDR (*(volatile uint8_t *)(&_MBAR[0xF04])) +#define MCF_EPORT_EPIER (*(volatile uint8_t *)(&_MBAR[0xF05])) +#define MCF_EPORT_EPDR (*(volatile uint8_t *)(&_MBAR[0xF08])) +#define MCF_EPORT_EPPDR (*(volatile uint8_t *)(&_MBAR[0xF09])) +#define MCF_EPORT_EPFR (*(volatile uint8_t *)(&_MBAR[0xF0C])) + + + +/* Bit definitions and macros for MCF_EPORT_EPPAR */ +#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2) +#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4) +#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8) +#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC) +#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4) +#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10) +#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20) +#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30) +#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6) +#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40) +#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80) +#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0) +#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8) +#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100) +#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200) +#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300) +#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA) +#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400) +#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800) +#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00) +#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC) +#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) +#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) +#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) +#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE) +#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) +#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) +#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) +#define MCF_EPORT_EPPAR_LEVEL (0) +#define MCF_EPORT_EPPAR_RISING (0x1) +#define MCF_EPORT_EPPAR_FALLING (0x2) +#define MCF_EPORT_EPPAR_BOTH (0x3) + +/* Bit definitions and macros for MCF_EPORT_EPDDR */ +#define MCF_EPORT_EPDDR_EPDD1 (0x2) +#define MCF_EPORT_EPDDR_EPDD2 (0x4) +#define MCF_EPORT_EPDDR_EPDD3 (0x8) +#define MCF_EPORT_EPDDR_EPDD4 (0x10) +#define MCF_EPORT_EPDDR_EPDD5 (0x20) +#define MCF_EPORT_EPDDR_EPDD6 (0x40) +#define MCF_EPORT_EPDDR_EPDD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPIER */ +#define MCF_EPORT_EPIER_EPIE1 (0x2) +#define MCF_EPORT_EPIER_EPIE2 (0x4) +#define MCF_EPORT_EPIER_EPIE3 (0x8) +#define MCF_EPORT_EPIER_EPIE4 (0x10) +#define MCF_EPORT_EPIER_EPIE5 (0x20) +#define MCF_EPORT_EPIER_EPIE6 (0x40) +#define MCF_EPORT_EPIER_EPIE7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPDR */ +#define MCF_EPORT_EPDR_EPD1 (0x2) +#define MCF_EPORT_EPDR_EPD2 (0x4) +#define MCF_EPORT_EPDR_EPD3 (0x8) +#define MCF_EPORT_EPDR_EPD4 (0x10) +#define MCF_EPORT_EPDR_EPD5 (0x20) +#define MCF_EPORT_EPDR_EPD6 (0x40) +#define MCF_EPORT_EPDR_EPD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPPDR */ +#define MCF_EPORT_EPPDR_EPPD1 (0x2) +#define MCF_EPORT_EPPDR_EPPD2 (0x4) +#define MCF_EPORT_EPPDR_EPPD3 (0x8) +#define MCF_EPORT_EPPDR_EPPD4 (0x10) +#define MCF_EPORT_EPPDR_EPPD5 (0x20) +#define MCF_EPORT_EPPDR_EPPD6 (0x40) +#define MCF_EPORT_EPPDR_EPPD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPFR */ +#define MCF_EPORT_EPFR_EPF1 (0x2) +#define MCF_EPORT_EPFR_EPF2 (0x4) +#define MCF_EPORT_EPFR_EPF3 (0x8) +#define MCF_EPORT_EPFR_EPF4 (0x10) +#define MCF_EPORT_EPFR_EPF5 (0x20) +#define MCF_EPORT_EPFR_EPF6 (0x40) +#define MCF_EPORT_EPFR_EPF7 (0x80) + + +#endif /* __MCF5475_EPORT_H__ */ diff --git a/tos/vmem_test/include/MCF5475_FBCS.h b/tos/vmem_test/include/MCF5475_FBCS.h new file mode 100644 index 0000000..37daf00 --- /dev/null +++ b/tos/vmem_test/include/MCF5475_FBCS.h @@ -0,0 +1,100 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_FBCS_H__ +#define __MCF5475_FBCS_H__ + + +/********************************************************************* +* +* FlexBus Chip Select Module (FBCS) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_FBCS0_CSAR (*(volatile uint32_t*)(&_MBAR[0x500])) +#define MCF_FBCS0_CSMR (*(volatile uint32_t*)(&_MBAR[0x504])) +#define MCF_FBCS0_CSCR (*(volatile uint32_t*)(&_MBAR[0x508])) + +#define MCF_FBCS1_CSAR (*(volatile uint32_t*)(&_MBAR[0x50C])) +#define MCF_FBCS1_CSMR (*(volatile uint32_t*)(&_MBAR[0x510])) +#define MCF_FBCS1_CSCR (*(volatile uint32_t*)(&_MBAR[0x514])) + +#define MCF_FBCS2_CSAR (*(volatile uint32_t*)(&_MBAR[0x518])) +#define MCF_FBCS2_CSMR (*(volatile uint32_t*)(&_MBAR[0x51C])) +#define MCF_FBCS2_CSCR (*(volatile uint32_t*)(&_MBAR[0x520])) + +#define MCF_FBCS3_CSAR (*(volatile uint32_t*)(&_MBAR[0x524])) +#define MCF_FBCS3_CSMR (*(volatile uint32_t*)(&_MBAR[0x528])) +#define MCF_FBCS3_CSCR (*(volatile uint32_t*)(&_MBAR[0x52C])) + +#define MCF_FBCS4_CSAR (*(volatile uint32_t*)(&_MBAR[0x530])) +#define MCF_FBCS4_CSMR (*(volatile uint32_t*)(&_MBAR[0x534])) +#define MCF_FBCS4_CSCR (*(volatile uint32_t*)(&_MBAR[0x538])) + +#define MCF_FBCS5_CSAR (*(volatile uint32_t*)(&_MBAR[0x53C])) +#define MCF_FBCS5_CSMR (*(volatile uint32_t*)(&_MBAR[0x540])) +#define MCF_FBCS5_CSCR (*(volatile uint32_t*)(&_MBAR[0x544])) + +#define MCF_FBCS_CSAR(x) (*(volatile uint32_t*)(&_MBAR[0x500 + ((x)*0xC)])) +#define MCF_FBCS_CSMR(x) (*(volatile uint32_t*)(&_MBAR[0x504 + ((x)*0xC)])) +#define MCF_FBCS_CSCR(x) (*(volatile uint32_t*)(&_MBAR[0x508 + ((x)*0xC)])) + + +/* Bit definitions and macros for MCF_FBCS_CSAR */ +#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) + +/* Bit definitions and macros for MCF_FBCS_CSMR */ +#define MCF_FBCS_CSMR_V (0x1) +#define MCF_FBCS_CSMR_WP (0x100) +#define MCF_FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<0x10) +#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) +#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) +#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) +#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) +#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) +#define MCF_FBCS_CSMR_BAM_256M (0xFFF0000) +#define MCF_FBCS_CSMR_BAM_128M (0x7FF0000) +#define MCF_FBCS_CSMR_BAM_64M (0x3FF0000) +#define MCF_FBCS_CSMR_BAM_32M (0x1FF0000) +#define MCF_FBCS_CSMR_BAM_16M (0xFF0000) +#define MCF_FBCS_CSMR_BAM_8M (0x7F0000) +#define MCF_FBCS_CSMR_BAM_4M (0x3F0000) +#define MCF_FBCS_CSMR_BAM_2M (0x1F0000) +#define MCF_FBCS_CSMR_BAM_1M (0xF0000) +#define MCF_FBCS_CSMR_BAM_1024K (0xF0000) +#define MCF_FBCS_CSMR_BAM_512K (0x70000) +#define MCF_FBCS_CSMR_BAM_256K (0x30000) +#define MCF_FBCS_CSMR_BAM_128K (0x10000) +#define MCF_FBCS_CSMR_BAM_64K (0) + +/* Bit definitions and macros for MCF_FBCS_CSCR */ +#define MCF_FBCS_CSCR_BSTW (0x8) +#define MCF_FBCS_CSCR_BSTR (0x10) +#define MCF_FBCS_CSCR_BEM (0x20) +#define MCF_FBCS_CSCR_PS(x) (((x)&0x3)<<0x6) +#define MCF_FBCS_CSCR_PS_32 (0) +#define MCF_FBCS_CSCR_PS_8 (0x40) +#define MCF_FBCS_CSCR_PS_16 (0x80) +#define MCF_FBCS_CSCR_AA (0x100) +#define MCF_FBCS_CSCR_WS(x) (((x)&0x3F)<<0xA) +#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x3)<<0x10) +#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x3)<<0x12) +#define MCF_FBCS_CSCR_ASET(x) (((x)&0x3)<<0x14) +#define MCF_FBCS_CSCR_SWSEN (0x800000) +#define MCF_FBCS_CSCR_SWS(x) (((x)&0x3F)<<0x1A) + + +#endif /* __MCF5475_FBCS_H__ */ diff --git a/tos/vmem_test/include/MCF5475_FEC.h b/tos/vmem_test/include/MCF5475_FEC.h new file mode 100644 index 0000000..fdd9403 --- /dev/null +++ b/tos/vmem_test/include/MCF5475_FEC.h @@ -0,0 +1,680 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_FEC_H__ +#define __MCF5475_FEC_H__ + + +/********************************************************************* +* +* Fast Ethernet Controller(FEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_FEC0_EIR (*(volatile uint32_t*)(&_MBAR[0x9004])) +#define MCF_FEC0_EIMR (*(volatile uint32_t*)(&_MBAR[0x9008])) +#define MCF_FEC0_ECR (*(volatile uint32_t*)(&_MBAR[0x9024])) +#define MCF_FEC0_MMFR (*(volatile uint32_t*)(&_MBAR[0x9040])) +#define MCF_FEC0_MSCR (*(volatile uint32_t*)(&_MBAR[0x9044])) +#define MCF_FEC0_MIBC (*(volatile uint32_t*)(&_MBAR[0x9064])) +#define MCF_FEC0_RCR (*(volatile uint32_t*)(&_MBAR[0x9084])) +#define MCF_FEC0_RHR (*(volatile uint32_t*)(&_MBAR[0x9088])) +#define MCF_FEC0_TCR (*(volatile uint32_t*)(&_MBAR[0x90C4])) +#define MCF_FEC0_PALR (*(volatile uint32_t*)(&_MBAR[0x90E4])) +#define MCF_FEC0_PAHR (*(volatile uint32_t*)(&_MBAR[0x90E8])) +#define MCF_FEC0_OPD (*(volatile uint32_t*)(&_MBAR[0x90EC])) +#define MCF_FEC0_IAUR (*(volatile uint32_t*)(&_MBAR[0x9118])) +#define MCF_FEC0_IALR (*(volatile uint32_t*)(&_MBAR[0x911C])) +#define MCF_FEC0_GAUR (*(volatile uint32_t*)(&_MBAR[0x9120])) +#define MCF_FEC0_GALR (*(volatile uint32_t*)(&_MBAR[0x9124])) +#define MCF_FEC0_FECTFWR (*(volatile uint32_t*)(&_MBAR[0x9144])) +#define MCF_FEC0_FECRFDR (*(volatile uint32_t*)(&_MBAR[0x9184])) +#define MCF_FEC0_FECRFSR (*(volatile uint32_t*)(&_MBAR[0x9188])) +#define MCF_FEC0_FECRFCR (*(volatile uint32_t*)(&_MBAR[0x918C])) +#define MCF_FEC0_FECRLRFP (*(volatile uint32_t*)(&_MBAR[0x9190])) +#define MCF_FEC0_FECRLWFP (*(volatile uint32_t*)(&_MBAR[0x9194])) +#define MCF_FEC0_FECRFAR (*(volatile uint32_t*)(&_MBAR[0x9198])) +#define MCF_FEC0_FECRFRP (*(volatile uint32_t*)(&_MBAR[0x919C])) +#define MCF_FEC0_FECRFWP (*(volatile uint32_t*)(&_MBAR[0x91A0])) +#define MCF_FEC0_FECTFDR (*(volatile uint32_t*)(&_MBAR[0x91A4])) +#define MCF_FEC0_FECTFSR (*(volatile uint32_t*)(&_MBAR[0x91A8])) +#define MCF_FEC0_FECTFCR (*(volatile uint32_t*)(&_MBAR[0x91AC])) +#define MCF_FEC0_FECTLRFP (*(volatile uint32_t*)(&_MBAR[0x91B0])) +#define MCF_FEC0_FECTLWFP (*(volatile uint32_t*)(&_MBAR[0x91B4])) +#define MCF_FEC0_FECTFAR (*(volatile uint32_t*)(&_MBAR[0x91B8])) +#define MCF_FEC0_FECTFRP (*(volatile uint32_t*)(&_MBAR[0x91BC])) +#define MCF_FEC0_FECTFWP (*(volatile uint32_t*)(&_MBAR[0x91C0])) +#define MCF_FEC0_FECFRST (*(volatile uint32_t*)(&_MBAR[0x91C4])) +#define MCF_FEC0_FECCTCWR (*(volatile uint32_t*)(&_MBAR[0x91C8])) +#define MCF_FEC0_RMON_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9200])) +#define MCF_FEC0_RMON_T_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9204])) +#define MCF_FEC0_RMON_T_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9208])) +#define MCF_FEC0_RMON_T_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x920C])) +#define MCF_FEC0_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9210])) +#define MCF_FEC0_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9214])) +#define MCF_FEC0_RMON_T_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9218])) +#define MCF_FEC0_RMON_T_FRAG (*(volatile uint32_t*)(&_MBAR[0x921C])) +#define MCF_FEC0_RMON_T_JAB (*(volatile uint32_t*)(&_MBAR[0x9220])) +#define MCF_FEC0_RMON_T_COL (*(volatile uint32_t*)(&_MBAR[0x9224])) +#define MCF_FEC0_RMON_T_P64 (*(volatile uint32_t*)(&_MBAR[0x9228])) +#define MCF_FEC0_RMON_T_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x922C])) +#define MCF_FEC0_RMON_T_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9230])) +#define MCF_FEC0_RMON_T_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9234])) +#define MCF_FEC0_RMON_T_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9238])) +#define MCF_FEC0_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x923C])) +#define MCF_FEC0_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9240])) +#define MCF_FEC0_RMON_T_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9244])) +#define MCF_FEC0_IEEE_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9248])) +#define MCF_FEC0_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x924C])) +#define MCF_FEC0_IEEE_T_1COL (*(volatile uint32_t*)(&_MBAR[0x9250])) +#define MCF_FEC0_IEEE_T_MCOL (*(volatile uint32_t*)(&_MBAR[0x9254])) +#define MCF_FEC0_IEEE_T_DEF (*(volatile uint32_t*)(&_MBAR[0x9258])) +#define MCF_FEC0_IEEE_T_LCOL (*(volatile uint32_t*)(&_MBAR[0x925C])) +#define MCF_FEC0_IEEE_T_EXCOL (*(volatile uint32_t*)(&_MBAR[0x9260])) +#define MCF_FEC0_IEEE_T_MACERR (*(volatile uint32_t*)(&_MBAR[0x9264])) +#define MCF_FEC0_IEEE_T_CSERR (*(volatile uint32_t*)(&_MBAR[0x9268])) +#define MCF_FEC0_IEEE_T_SQE (*(volatile uint32_t*)(&_MBAR[0x926C])) +#define MCF_FEC0_IEEE_T_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9270])) +#define MCF_FEC0_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9274])) +#define MCF_FEC0_RMON_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9280])) +#define MCF_FEC0_RMON_R_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9284])) +#define MCF_FEC0_RMON_R_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9288])) +#define MCF_FEC0_RMON_R_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x928C])) +#define MCF_FEC0_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9290])) +#define MCF_FEC0_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9294])) +#define MCF_FEC0_RMON_R_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9298])) +#define MCF_FEC0_RMON_R_FRAG (*(volatile uint32_t*)(&_MBAR[0x929C])) +#define MCF_FEC0_RMON_R_JAB (*(volatile uint32_t*)(&_MBAR[0x92A0])) +#define MCF_FEC0_RMON_R_RESVD_0 (*(volatile uint32_t*)(&_MBAR[0x92A4])) +#define MCF_FEC0_RMON_R_P64 (*(volatile uint32_t*)(&_MBAR[0x92A8])) +#define MCF_FEC0_RMON_R_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x92AC])) +#define MCF_FEC0_RMON_R_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x92B0])) +#define MCF_FEC0_RMON_R_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x92B4])) +#define MCF_FEC0_RMON_R_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x92B8])) +#define MCF_FEC0_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x92BC])) +#define MCF_FEC0_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x92C0])) +#define MCF_FEC0_RMON_R_OCTETS (*(volatile uint32_t*)(&_MBAR[0x92C4])) +#define MCF_FEC0_IEEE_R_DROP (*(volatile uint32_t*)(&_MBAR[0x92C8])) +#define MCF_FEC0_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x92CC])) +#define MCF_FEC0_IEEE_R_CRC (*(volatile uint32_t*)(&_MBAR[0x92D0])) +#define MCF_FEC0_IEEE_R_ALIGN (*(volatile uint32_t*)(&_MBAR[0x92D4])) +#define MCF_FEC0_IEEE_R_MACERR (*(volatile uint32_t*)(&_MBAR[0x92D8])) +#define MCF_FEC0_IEEE_R_FDXFC (*(volatile uint32_t*)(&_MBAR[0x92DC])) +#define MCF_FEC0_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x92E0])) + +#define MCF_FEC1_EIR (*(volatile uint32_t*)(&_MBAR[0x9804])) +#define MCF_FEC1_EIMR (*(volatile uint32_t*)(&_MBAR[0x9808])) +#define MCF_FEC1_ECR (*(volatile uint32_t*)(&_MBAR[0x9824])) +#define MCF_FEC1_MMFR (*(volatile uint32_t*)(&_MBAR[0x9840])) +#define MCF_FEC1_MSCR (*(volatile uint32_t*)(&_MBAR[0x9844])) +#define MCF_FEC1_MIBC (*(volatile uint32_t*)(&_MBAR[0x9864])) +#define MCF_FEC1_RCR (*(volatile uint32_t*)(&_MBAR[0x9884])) +#define MCF_FEC1_RHR (*(volatile uint32_t*)(&_MBAR[0x9888])) +#define MCF_FEC1_TCR (*(volatile uint32_t*)(&_MBAR[0x98C4])) +#define MCF_FEC1_PALR (*(volatile uint32_t*)(&_MBAR[0x98E4])) +#define MCF_FEC1_PAHR (*(volatile uint32_t*)(&_MBAR[0x98E8])) +#define MCF_FEC1_OPD (*(volatile uint32_t*)(&_MBAR[0x98EC])) +#define MCF_FEC1_IAUR (*(volatile uint32_t*)(&_MBAR[0x9918])) +#define MCF_FEC1_IALR (*(volatile uint32_t*)(&_MBAR[0x991C])) +#define MCF_FEC1_GAUR (*(volatile uint32_t*)(&_MBAR[0x9920])) +#define MCF_FEC1_GALR (*(volatile uint32_t*)(&_MBAR[0x9924])) +#define MCF_FEC1_FECTFWR (*(volatile uint32_t*)(&_MBAR[0x9944])) +#define MCF_FEC1_FECRFDR (*(volatile uint32_t*)(&_MBAR[0x9984])) +#define MCF_FEC1_FECRFSR (*(volatile uint32_t*)(&_MBAR[0x9988])) +#define MCF_FEC1_FECRFCR (*(volatile uint32_t*)(&_MBAR[0x998C])) +#define MCF_FEC1_FECRLRFP (*(volatile uint32_t*)(&_MBAR[0x9990])) +#define MCF_FEC1_FECRLWFP (*(volatile uint32_t*)(&_MBAR[0x9994])) +#define MCF_FEC1_FECRFAR (*(volatile uint32_t*)(&_MBAR[0x9998])) +#define MCF_FEC1_FECRFRP (*(volatile uint32_t*)(&_MBAR[0x999C])) +#define MCF_FEC1_FECRFWP (*(volatile uint32_t*)(&_MBAR[0x99A0])) +#define MCF_FEC1_FECTFDR (*(volatile uint32_t*)(&_MBAR[0x99A4])) +#define MCF_FEC1_FECTFSR (*(volatile uint32_t*)(&_MBAR[0x99A8])) +#define MCF_FEC1_FECTFCR (*(volatile uint32_t*)(&_MBAR[0x99AC])) +#define MCF_FEC1_FECTLRFP (*(volatile uint32_t*)(&_MBAR[0x99B0])) +#define MCF_FEC1_FECTLWFP (*(volatile uint32_t*)(&_MBAR[0x99B4])) +#define MCF_FEC1_FECTFAR (*(volatile uint32_t*)(&_MBAR[0x99B8])) +#define MCF_FEC1_FECTFRP (*(volatile uint32_t*)(&_MBAR[0x99BC])) +#define MCF_FEC1_FECTFWP (*(volatile uint32_t*)(&_MBAR[0x99C0])) +#define MCF_FEC1_FECFRST (*(volatile uint32_t*)(&_MBAR[0x99C4])) +#define MCF_FEC1_FECCTCWR (*(volatile uint32_t*)(&_MBAR[0x99C8])) +#define MCF_FEC1_RMON_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9A00])) +#define MCF_FEC1_RMON_T_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9A04])) +#define MCF_FEC1_RMON_T_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A08])) +#define MCF_FEC1_RMON_T_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A0C])) +#define MCF_FEC1_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9A10])) +#define MCF_FEC1_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A14])) +#define MCF_FEC1_RMON_T_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A18])) +#define MCF_FEC1_RMON_T_FRAG (*(volatile uint32_t*)(&_MBAR[0x9A1C])) +#define MCF_FEC1_RMON_T_JAB (*(volatile uint32_t*)(&_MBAR[0x9A20])) +#define MCF_FEC1_RMON_T_COL (*(volatile uint32_t*)(&_MBAR[0x9A24])) +#define MCF_FEC1_RMON_T_P64 (*(volatile uint32_t*)(&_MBAR[0x9A28])) +#define MCF_FEC1_RMON_T_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x9A2C])) +#define MCF_FEC1_RMON_T_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9A30])) +#define MCF_FEC1_RMON_T_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9A34])) +#define MCF_FEC1_RMON_T_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9A38])) +#define MCF_FEC1_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x9A3C])) +#define MCF_FEC1_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9A40])) +#define MCF_FEC1_RMON_T_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9A44])) +#define MCF_FEC1_IEEE_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9A48])) +#define MCF_FEC1_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x9A4C])) +#define MCF_FEC1_IEEE_T_1COL (*(volatile uint32_t*)(&_MBAR[0x9A50])) +#define MCF_FEC1_IEEE_T_MCOL (*(volatile uint32_t*)(&_MBAR[0x9A54])) +#define MCF_FEC1_IEEE_T_DEF (*(volatile uint32_t*)(&_MBAR[0x9A58])) +#define MCF_FEC1_IEEE_T_LCOL (*(volatile uint32_t*)(&_MBAR[0x9A5C])) +#define MCF_FEC1_IEEE_T_EXCOL (*(volatile uint32_t*)(&_MBAR[0x9A60])) +#define MCF_FEC1_IEEE_T_MACERR (*(volatile uint32_t*)(&_MBAR[0x9A64])) +#define MCF_FEC1_IEEE_T_CSERR (*(volatile uint32_t*)(&_MBAR[0x9A68])) +#define MCF_FEC1_IEEE_T_SQE (*(volatile uint32_t*)(&_MBAR[0x9A6C])) +#define MCF_FEC1_IEEE_T_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9A70])) +#define MCF_FEC1_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9A74])) +#define MCF_FEC1_RMON_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9A80])) +#define MCF_FEC1_RMON_R_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9A84])) +#define MCF_FEC1_RMON_R_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A88])) +#define MCF_FEC1_RMON_R_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A8C])) +#define MCF_FEC1_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9A90])) +#define MCF_FEC1_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A94])) +#define MCF_FEC1_RMON_R_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A98])) +#define MCF_FEC1_RMON_R_FRAG (*(volatile uint32_t*)(&_MBAR[0x9A9C])) +#define MCF_FEC1_RMON_R_JAB (*(volatile uint32_t*)(&_MBAR[0x9AA0])) +#define MCF_FEC1_RMON_R_RESVD_0 (*(volatile uint32_t*)(&_MBAR[0x9AA4])) +#define MCF_FEC1_RMON_R_P64 (*(volatile uint32_t*)(&_MBAR[0x9AA8])) +#define MCF_FEC1_RMON_R_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x9AAC])) +#define MCF_FEC1_RMON_R_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9AB0])) +#define MCF_FEC1_RMON_R_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9AB4])) +#define MCF_FEC1_RMON_R_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9AB8])) +#define MCF_FEC1_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x9ABC])) +#define MCF_FEC1_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9AC0])) +#define MCF_FEC1_RMON_R_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9AC4])) +#define MCF_FEC1_IEEE_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9AC8])) +#define MCF_FEC1_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x9ACC])) +#define MCF_FEC1_IEEE_R_CRC (*(volatile uint32_t*)(&_MBAR[0x9AD0])) +#define MCF_FEC1_IEEE_R_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9AD4])) +#define MCF_FEC1_IEEE_R_MACERR (*(volatile uint32_t*)(&_MBAR[0x9AD8])) +#define MCF_FEC1_IEEE_R_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9ADC])) +#define MCF_FEC1_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9AE0])) + +#define MCF_FEC_EIR(x) (*(volatile uint32_t*)(&_MBAR[0x9004 + ((x)*0x800)])) +#define MCF_FEC_EIMR(x) (*(volatile uint32_t*)(&_MBAR[0x9008 + ((x)*0x800)])) +#define MCF_FEC_ECR(x) (*(volatile uint32_t*)(&_MBAR[0x9024 + ((x)*0x800)])) +#define MCF_FEC_MMFR(x) (*(volatile uint32_t*)(&_MBAR[0x9040 + ((x)*0x800)])) +#define MCF_FEC_MSCR(x) (*(volatile uint32_t*)(&_MBAR[0x9044 + ((x)*0x800)])) +#define MCF_FEC_MIBC(x) (*(volatile uint32_t*)(&_MBAR[0x9064 + ((x)*0x800)])) +#define MCF_FEC_RCR(x) (*(volatile uint32_t*)(&_MBAR[0x9084 + ((x)*0x800)])) +#define MCF_FEC_RHR(x) (*(volatile uint32_t*)(&_MBAR[0x9088 + ((x)*0x800)])) +#define MCF_FEC_TCR(x) (*(volatile uint32_t*)(&_MBAR[0x90C4 + ((x)*0x800)])) +#define MCF_FEC_PALR(x) (*(volatile uint32_t*)(&_MBAR[0x90E4 + ((x)*0x800)])) +#define MCF_FEC_PAHR(x) (*(volatile uint32_t*)(&_MBAR[0x90E8 + ((x)*0x800)])) +#define MCF_FEC_OPD(x) (*(volatile uint32_t*)(&_MBAR[0x90EC + ((x)*0x800)])) +#define MCF_FEC_IAUR(x) (*(volatile uint32_t*)(&_MBAR[0x9118 + ((x)*0x800)])) +#define MCF_FEC_IALR(x) (*(volatile uint32_t*)(&_MBAR[0x911C + ((x)*0x800)])) +#define MCF_FEC_GAUR(x) (*(volatile uint32_t*)(&_MBAR[0x9120 + ((x)*0x800)])) +#define MCF_FEC_GALR(x) (*(volatile uint32_t*)(&_MBAR[0x9124 + ((x)*0x800)])) +#define MCF_FEC_FECTFWR(x) (*(volatile uint32_t*)(&_MBAR[0x9144 + ((x)*0x800)])) +#define MCF_FEC_FECRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x9184 + ((x)*0x800)])) +#define MCF_FEC_FECRFSR(x) (*(volatile uint32_t*)(&_MBAR[0x9188 + ((x)*0x800)])) +#define MCF_FEC_FECRFCR(x) (*(volatile uint32_t*)(&_MBAR[0x918C + ((x)*0x800)])) +#define MCF_FEC_FECRLRFP(x) (*(volatile uint32_t*)(&_MBAR[0x9190 + ((x)*0x800)])) +#define MCF_FEC_FECRLWFP(x) (*(volatile uint32_t*)(&_MBAR[0x9194 + ((x)*0x800)])) +#define MCF_FEC_FECRFAR(x) (*(volatile uint32_t*)(&_MBAR[0x9198 + ((x)*0x800)])) +#define MCF_FEC_FECRFRP(x) (*(volatile uint32_t*)(&_MBAR[0x919C + ((x)*0x800)])) +#define MCF_FEC_FECRFWP(x) (*(volatile uint32_t*)(&_MBAR[0x91A0 + ((x)*0x800)])) +#define MCF_FEC_FECTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x91A4 + ((x)*0x800)])) +#define MCF_FEC_FECTFSR(x) (*(volatile uint32_t*)(&_MBAR[0x91A8 + ((x)*0x800)])) +#define MCF_FEC_FECTFCR(x) (*(volatile uint32_t*)(&_MBAR[0x91AC + ((x)*0x800)])) +#define MCF_FEC_FECTLRFP(x) (*(volatile uint32_t*)(&_MBAR[0x91B0 + ((x)*0x800)])) +#define MCF_FEC_FECTLWFP(x) (*(volatile uint32_t*)(&_MBAR[0x91B4 + ((x)*0x800)])) +#define MCF_FEC_FECTFAR(x) (*(volatile uint32_t*)(&_MBAR[0x91B8 + ((x)*0x800)])) +#define MCF_FEC_FECTFRP(x) (*(volatile uint32_t*)(&_MBAR[0x91BC + ((x)*0x800)])) +#define MCF_FEC_FECTFWP(x) (*(volatile uint32_t*)(&_MBAR[0x91C0 + ((x)*0x800)])) +#define MCF_FEC_FECFRST(x) (*(volatile uint32_t*)(&_MBAR[0x91C4 + ((x)*0x800)])) +#define MCF_FEC_FECCTCWR(x) (*(volatile uint32_t*)(&_MBAR[0x91C8 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9200 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_PACKETS(x) (*(volatile uint32_t*)(&_MBAR[0x9204 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_BC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x9208 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_MC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x920C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x9210 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9214 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_OVERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9218 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_FRAG(x) (*(volatile uint32_t*)(&_MBAR[0x921C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_JAB(x) (*(volatile uint32_t*)(&_MBAR[0x9220 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_COL(x) (*(volatile uint32_t*)(&_MBAR[0x9224 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P64(x) (*(volatile uint32_t*)(&_MBAR[0x9228 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P65TO127(x) (*(volatile uint32_t*)(&_MBAR[0x922C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P128TO255(x) (*(volatile uint32_t*)(&_MBAR[0x9230 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P256TO511(x) (*(volatile uint32_t*)(&_MBAR[0x9234 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P512TO1023(x) (*(volatile uint32_t*)(&_MBAR[0x9238 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P1024TO2047(x) (*(volatile uint32_t*)(&_MBAR[0x923C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P_GTE2048(x) (*(volatile uint32_t*)(&_MBAR[0x9240 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_OCTETS(x) (*(volatile uint32_t*)(&_MBAR[0x9244 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9248 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(volatile uint32_t*)(&_MBAR[0x924C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_1COL(x) (*(volatile uint32_t*)(&_MBAR[0x9250 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_MCOL(x) (*(volatile uint32_t*)(&_MBAR[0x9254 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_DEF(x) (*(volatile uint32_t*)(&_MBAR[0x9258 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_LCOL(x) (*(volatile uint32_t*)(&_MBAR[0x925C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_EXCOL(x) (*(volatile uint32_t*)(&_MBAR[0x9260 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_MACERR(x) (*(volatile uint32_t*)(&_MBAR[0x9264 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_CSERR(x) (*(volatile uint32_t*)(&_MBAR[0x9268 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_SQE(x) (*(volatile uint32_t*)(&_MBAR[0x926C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_FDXFC(x) (*(volatile uint32_t*)(&_MBAR[0x9270 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(volatile uint32_t*)(&_MBAR[0x9274 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9280 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_PACKETS(x) (*(volatile uint32_t*)(&_MBAR[0x9284 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_BC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x9288 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_MC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x928C + ((x)*0x800)])) +#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x9290 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9294 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_OVERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9298 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_FRAG(x) (*(volatile uint32_t*)(&_MBAR[0x929C + ((x)*0x800)])) +#define MCF_FEC_RMON_R_JAB(x) (*(volatile uint32_t*)(&_MBAR[0x92A0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_RESVD_0(x) (*(volatile uint32_t*)(&_MBAR[0x92A4 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P64(x) (*(volatile uint32_t*)(&_MBAR[0x92A8 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P65TO127(x) (*(volatile uint32_t*)(&_MBAR[0x92AC + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P128TO255(x) (*(volatile uint32_t*)(&_MBAR[0x92B0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P256TO511(x) (*(volatile uint32_t*)(&_MBAR[0x92B4 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P512TO1023(x) (*(volatile uint32_t*)(&_MBAR[0x92B8 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P1024TO2047(x) (*(volatile uint32_t*)(&_MBAR[0x92BC + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P_GTE2048(x) (*(volatile uint32_t*)(&_MBAR[0x92C0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_OCTETS(x) (*(volatile uint32_t*)(&_MBAR[0x92C4 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x92C8 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(volatile uint32_t*)(&_MBAR[0x92CC + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_CRC(x) (*(volatile uint32_t*)(&_MBAR[0x92D0 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x92D4 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_MACERR(x) (*(volatile uint32_t*)(&_MBAR[0x92D8 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_FDXFC(x) (*(volatile uint32_t*)(&_MBAR[0x92DC + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(volatile uint32_t*)(&_MBAR[0x92E0 + ((x)*0x800)])) + + +/* Bit definitions and macros for MCF_FEC_EIR */ +#define MCF_FEC_EIR_RFERR (0x20000) +#define MCF_FEC_EIR_XFERR (0x40000) +#define MCF_FEC_EIR_XFUN (0x80000) +#define MCF_FEC_EIR_RL (0x100000) +#define MCF_FEC_EIR_LC (0x200000) +#define MCF_FEC_EIR_MII (0x800000) +#define MCF_FEC_EIR_TXF (0x8000000) +#define MCF_FEC_EIR_GRA (0x10000000) +#define MCF_FEC_EIR_BABT (0x20000000) +#define MCF_FEC_EIR_BABR (0x40000000) +#define MCF_FEC_EIR_HBERR (0x80000000) +#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF_FEC_EIMR */ +#define MCF_FEC_EIMR_RFERR (0x20000) +#define MCF_FEC_EIMR_XFERR (0x40000) +#define MCF_FEC_EIMR_XFUN (0x80000) +#define MCF_FEC_EIMR_RL (0x100000) +#define MCF_FEC_EIMR_LC (0x200000) +#define MCF_FEC_EIMR_MII (0x800000) +#define MCF_FEC_EIMR_TXF (0x8000000) +#define MCF_FEC_EIMR_GRA (0x10000000) +#define MCF_FEC_EIMR_BABT (0x20000000) +#define MCF_FEC_EIMR_BABR (0x40000000) +#define MCF_FEC_EIMR_HBERR (0x80000000) +#define MCF_FEC_EIMR_MASK_ALL (0) +#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF_FEC_ECR */ +#define MCF_FEC_ECR_RESET (0x1) +#define MCF_FEC_ECR_ETHER_EN (0x2) + +/* Bit definitions and macros for MCF_FEC_MMFR */ +#define MCF_FEC_MMFR_DATA(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_MMFR_TA(x) (((x)&0x3)<<0x10) +#define MCF_FEC_MMFR_TA_10 (0x20000) +#define MCF_FEC_MMFR_RA(x) (((x)&0x1F)<<0x12) +#define MCF_FEC_MMFR_PA(x) (((x)&0x1F)<<0x17) +#define MCF_FEC_MMFR_OP(x) (((x)&0x3)<<0x1C) +#define MCF_FEC_MMFR_OP_READ (0x20000000) +#define MCF_FEC_MMFR_OP_WRITE (0x10000000) +#define MCF_FEC_MMFR_ST(x) (((x)&0x3)<<0x1E) +#define MCF_FEC_MMFR_ST_01 (0x40000000) + +/* Bit definitions and macros for MCF_FEC_MSCR */ +#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1) +#define MCF_FEC_MSCR_DIS_PREAMBLE (0x80) +#define MCF_FEC_MSCR_MII_SPEED_133 (0x1B<<0x1) +#define MCF_FEC_MSCR_MII_SPEED_120 (0x18<<0x1) +#define MCF_FEC_MSCR_MII_SPEED_66 (0xE<<0x1) +#define MCF_FEC_MSCR_MII_SPEED_60 (0xC<<0x1) + +/* Bit definitions and macros for MCF_FEC_MIBC */ +#define MCF_FEC_MIBC_MIB_IDLE (0x40000000) +#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000) + +/* Bit definitions and macros for MCF_FEC_RCR */ +#define MCF_FEC_RCR_LOOP (0x1) +#define MCF_FEC_RCR_DRT (0x2) +#define MCF_FEC_RCR_MII_MODE (0x4) +#define MCF_FEC_RCR_PROM (0x8) +#define MCF_FEC_RCR_BC_REJ (0x10) +#define MCF_FEC_RCR_FCE (0x20) +#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<0x10) + +/* Bit definitions and macros for MCF_FEC_RHR */ +#define MCF_FEC_RHR_HASH(x) (((x)&0x3F)<<0x18) +#define MCF_FEC_RHR_MULTCAST (0x40000000) +#define MCF_FEC_RHR_FCE (0x80000000) + +/* Bit definitions and macros for MCF_FEC_TCR */ +#define MCF_FEC_TCR_GTS (0x1) +#define MCF_FEC_TCR_HBC (0x2) +#define MCF_FEC_TCR_FDEN (0x4) +#define MCF_FEC_TCR_TFC_PAUSE (0x8) +#define MCF_FEC_TCR_RFC_PAUSE (0x10) + +/* Bit definitions and macros for MCF_FEC_PALR */ +#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_PAHR */ +#define MCF_FEC_PAHR_TYPE(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_PAHR_PADDR2(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_FEC_OPD */ +#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_OPD_OPCODE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_FEC_IAUR */ +#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IALR */ +#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_GAUR */ +#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_GALR */ +#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFWR */ +#define MCF_FEC_FECTFWR_X_WMRK(x) (((x)&0xF)<<0) +#define MCF_FEC_FECTFWR_X_WMRK_64 (0) +#define MCF_FEC_FECTFWR_X_WMRK_128 (0x1) +#define MCF_FEC_FECTFWR_X_WMRK_192 (0x2) +#define MCF_FEC_FECTFWR_X_WMRK_256 (0x3) +#define MCF_FEC_FECTFWR_X_WMRK_320 (0x4) +#define MCF_FEC_FECTFWR_X_WMRK_384 (0x5) +#define MCF_FEC_FECTFWR_X_WMRK_448 (0x6) +#define MCF_FEC_FECTFWR_X_WMRK_512 (0x7) +#define MCF_FEC_FECTFWR_X_WMRK_576 (0x8) +#define MCF_FEC_FECTFWR_X_WMRK_640 (0x9) +#define MCF_FEC_FECTFWR_X_WMRK_704 (0xA) +#define MCF_FEC_FECTFWR_X_WMRK_768 (0xB) +#define MCF_FEC_FECTFWR_X_WMRK_832 (0xC) +#define MCF_FEC_FECTFWR_X_WMRK_896 (0xD) +#define MCF_FEC_FECTFWR_X_WMRK_960 (0xE) +#define MCF_FEC_FECTFWR_X_WMRK_1024 (0xF) + +/* Bit definitions and macros for MCF_FEC_FECRFDR */ +#define MCF_FEC_FECRFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFSR */ +#define MCF_FEC_FECRFSR_EMT (0x10000) +#define MCF_FEC_FECRFSR_ALARM (0x20000) +#define MCF_FEC_FECRFSR_FU (0x40000) +#define MCF_FEC_FECRFSR_FRMRDY (0x80000) +#define MCF_FEC_FECRFSR_OF (0x100000) +#define MCF_FEC_FECRFSR_UF (0x200000) +#define MCF_FEC_FECRFSR_RXW (0x400000) +#define MCF_FEC_FECRFSR_FAE (0x800000) +#define MCF_FEC_FECRFSR_FRM(x) (((x)&0xF)<<0x18) +#define MCF_FEC_FECRFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_FEC_FECRFCR */ +#define MCF_FEC_FECRFCR_COUNTER(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_FECRFCR_OF_MSK (0x80000) +#define MCF_FEC_FECRFCR_UF_MSK (0x100000) +#define MCF_FEC_FECRFCR_RXW_MSK (0x200000) +#define MCF_FEC_FECRFCR_FAE_MSK (0x400000) +#define MCF_FEC_FECRFCR_IP_MSK (0x800000) +#define MCF_FEC_FECRFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_FEC_FECRFCR_FRMEN (0x8000000) +#define MCF_FEC_FECRFCR_TIMER (0x10000000) + +/* Bit definitions and macros for MCF_FEC_FECRLRFP */ +#define MCF_FEC_FECRLRFP_LRFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRLWFP */ +#define MCF_FEC_FECRLWFP_LWFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFAR */ +#define MCF_FEC_FECRFAR_ALARM(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFRP */ +#define MCF_FEC_FECRFRP_READ(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFWP */ +#define MCF_FEC_FECRFWP_WRITE(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFDR */ +#define MCF_FEC_FECTFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFSR */ +#define MCF_FEC_FECTFSR_EMT (0x10000) +#define MCF_FEC_FECTFSR_ALARM (0x20000) +#define MCF_FEC_FECTFSR_FU (0x40000) +#define MCF_FEC_FECTFSR_FRMRDY (0x80000) +#define MCF_FEC_FECTFSR_OF (0x100000) +#define MCF_FEC_FECTFSR_UF (0x200000) +#define MCF_FEC_FECTFSR_FAE (0x800000) +#define MCF_FEC_FECTFSR_FRM(x) (((x)&0xF)<<0x18) +#define MCF_FEC_FECTFSR_TXW (0x40000000) +#define MCF_FEC_FECTFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_FEC_FECTFCR */ +#define MCF_FEC_FECTFCR_RESERVED (0x200000) +#define MCF_FEC_FECTFCR_COUNTER(x) (((x)&0xFFFF)<<0|0x200000) +#define MCF_FEC_FECTFCR_TXW_MASK (0x240000) +#define MCF_FEC_FECTFCR_OF_MSK (0x280000) +#define MCF_FEC_FECTFCR_UF_MSK (0x300000) +#define MCF_FEC_FECTFCR_FAE_MSK (0x600000) +#define MCF_FEC_FECTFCR_IP_MSK (0xA00000) +#define MCF_FEC_FECTFCR_GR(x) (((x)&0x7)<<0x18|0x200000) +#define MCF_FEC_FECTFCR_FRMEN (0x8200000) +#define MCF_FEC_FECTFCR_TIMER (0x10200000) +#define MCF_FEC_FECTFCR_WFR (0x20200000) +#define MCF_FEC_FECTFCR_WCTL (0x40200000) + +/* Bit definitions and macros for MCF_FEC_FECTLRFP */ +#define MCF_FEC_FECTLRFP_LRFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTLWFP */ +#define MCF_FEC_FECTLWFP_LWFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFAR */ +#define MCF_FEC_FECTFAR_ALARM(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFRP */ +#define MCF_FEC_FECTFRP_READ(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFWP */ +#define MCF_FEC_FECTFWP_WRITE(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECFRST */ +#define MCF_FEC_FECFRST_RST_CTL (0x1000000) +#define MCF_FEC_FECFRST_SW_RST (0x2000000) + +/* Bit definitions and macros for MCF_FEC_FECCTCWR */ +#define MCF_FEC_FECCTCWR_TFCW (0x1000000) +#define MCF_FEC_FECCTCWR_CRC (0x2000000) + +/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */ +#define MCF_FEC_RMON_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */ +#define MCF_FEC_RMON_T_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */ +#define MCF_FEC_RMON_T_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */ +#define MCF_FEC_RMON_T_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */ +#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */ +#define MCF_FEC_RMON_T_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */ +#define MCF_FEC_RMON_T_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */ +#define MCF_FEC_RMON_T_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */ +#define MCF_FEC_RMON_T_JAB_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_COL */ +#define MCF_FEC_RMON_T_COL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */ +#define MCF_FEC_RMON_T_P64_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */ +#define MCF_FEC_RMON_T_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */ +#define MCF_FEC_RMON_T_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */ +#define MCF_FEC_RMON_T_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */ +#define MCF_FEC_RMON_T_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */ +#define MCF_FEC_RMON_T_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */ +#define MCF_FEC_RMON_T_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */ +#define MCF_FEC_RMON_T_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */ +#define MCF_FEC_IEEE_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */ +#define MCF_FEC_IEEE_T_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */ +#define MCF_FEC_IEEE_T_1COL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */ +#define MCF_FEC_IEEE_T_MCOL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */ +#define MCF_FEC_IEEE_T_DEF_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */ +#define MCF_FEC_IEEE_T_LCOL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */ +#define MCF_FEC_IEEE_T_EXCOL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */ +#define MCF_FEC_IEEE_T_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */ +#define MCF_FEC_IEEE_T_CSERR_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */ +#define MCF_FEC_IEEE_T_SQE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */ +#define MCF_FEC_IEEE_T_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */ +#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_DROP */ +#define MCF_FEC_RMON_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */ +#define MCF_FEC_RMON_R_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */ +#define MCF_FEC_RMON_R_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */ +#define MCF_FEC_RMON_R_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */ +#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */ +#define MCF_FEC_RMON_R_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */ +#define MCF_FEC_RMON_R_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */ +#define MCF_FEC_RMON_R_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */ +#define MCF_FEC_RMON_R_JAB_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */ +#define MCF_FEC_RMON_R_RESVD_0_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */ +#define MCF_FEC_RMON_R_P64_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */ +#define MCF_FEC_RMON_R_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */ +#define MCF_FEC_RMON_R_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */ +#define MCF_FEC_RMON_R_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */ +#define MCF_FEC_RMON_R_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */ +#define MCF_FEC_RMON_R_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */ +#define MCF_FEC_RMON_R_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */ +#define MCF_FEC_RMON_R_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */ +#define MCF_FEC_IEEE_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */ +#define MCF_FEC_IEEE_R_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */ +#define MCF_FEC_IEEE_R_CRC_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */ +#define MCF_FEC_IEEE_R_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */ +#define MCF_FEC_IEEE_R_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */ +#define MCF_FEC_IEEE_R_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */ +#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + + +#endif /* __MCF5475_FEC_H__ */ diff --git a/tos/vmem_test/include/MCF5475_GPIO.h b/tos/vmem_test/include/MCF5475_GPIO.h new file mode 100644 index 0000000..5dd2583 --- /dev/null +++ b/tos/vmem_test/include/MCF5475_GPIO.h @@ -0,0 +1,543 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_GPIO_H__ +#define __MCF5475_GPIO_H__ + + +/********************************************************************* +* +* General Purpose I/O (GPIO) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPIO_PODR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA00])) +#define MCF_GPIO_PDDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA10])) +#define MCF_GPIO_PPDSDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA20])) +#define MCF_GPIO_PCLRR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA30])) + +#define MCF_GPIO_PODR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA01])) +#define MCF_GPIO_PDDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA11])) +#define MCF_GPIO_PPDSDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA21])) +#define MCF_GPIO_PCLRR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA31])) + +#define MCF_GPIO_PODR_DMA (*(volatile uint8_t *)(&_MBAR[0xA02])) +#define MCF_GPIO_PDDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA12])) +#define MCF_GPIO_PPDSDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA22])) +#define MCF_GPIO_PCLRR_DMA (*(volatile uint8_t *)(&_MBAR[0xA32])) + +#define MCF_GPIO_PODR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA04])) +#define MCF_GPIO_PDDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA14])) +#define MCF_GPIO_PPDSDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA24])) +#define MCF_GPIO_PCLRR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA34])) + +#define MCF_GPIO_PODR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA05])) +#define MCF_GPIO_PDDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA15])) +#define MCF_GPIO_PPDSDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA25])) +#define MCF_GPIO_PCLRR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA35])) + +#define MCF_GPIO_PODR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA06])) +#define MCF_GPIO_PDDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA16])) +#define MCF_GPIO_PPDSDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA26])) +#define MCF_GPIO_PCLRR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA36])) + +#define MCF_GPIO_PODR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA07])) +#define MCF_GPIO_PDDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA17])) +#define MCF_GPIO_PPDSDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA27])) +#define MCF_GPIO_PCLRR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA37])) + +#define MCF_GPIO_PODR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA08])) +#define MCF_GPIO_PDDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA18])) +#define MCF_GPIO_PPDSDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA28])) +#define MCF_GPIO_PCLRR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA38])) + +#define MCF_GPIO_PODR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA09])) +#define MCF_GPIO_PDDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA19])) +#define MCF_GPIO_PPDSDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA29])) +#define MCF_GPIO_PCLRR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA39])) + +#define MCF_GPIO_PODR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA0A])) +#define MCF_GPIO_PDDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA1A])) +#define MCF_GPIO_PPDSDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA2A])) +#define MCF_GPIO_PCLRR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA3A])) + +#define MCF_GPIO2_PODR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA0C])) +#define MCF_GPIO2_PDDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA1C])) +#define MCF_GPIO2_PPDSDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA2C])) +#define MCF_GPIO2_PCLRR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA3C])) + +#define MCF_GPIO0_PODR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA0D])) +#define MCF_GPIO0_PDDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA1D])) +#define MCF_GPIO0_PPDSDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA2D])) +#define MCF_GPIO0_PCLRR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA3D])) + +#define MCF_GPIO_PODR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA0E])) +#define MCF_GPIO_PDDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA1E])) +#define MCF_GPIO_PPDSDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA2E])) +#define MCF_GPIO_PCLRR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA3E])) + + + +/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */ +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x1) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x2) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x4) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x8) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */ +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x1) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x2) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x4) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x8) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */ +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x1) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x2) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x4) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x8) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */ +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x1) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x2) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x4) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x8) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */ +#define MCF_GPIO_PODR_FBCS_PODR_FBCS1 (0x2) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS2 (0x4) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS3 (0x8) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS4 (0x10) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */ +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x2) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x4) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x8) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */ +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x2) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x4) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x8) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */ +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x2) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x4) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x8) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PODR_DMA */ +#define MCF_GPIO_PODR_DMA_PODR_DMA0 (0x1) +#define MCF_GPIO_PODR_DMA_PODR_DMA1 (0x2) +#define MCF_GPIO_PODR_DMA_PODR_DMA2 (0x4) +#define MCF_GPIO_PODR_DMA_PODR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */ +#define MCF_GPIO_PDDR_DMA_PDDR_DMA0 (0x1) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA1 (0x2) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA2 (0x4) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */ +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x1) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x2) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x4) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */ +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x1) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x2) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x4) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */ +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x1) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x2) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x4) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x8) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */ +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x1) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x2) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x4) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x8) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */ +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x1) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x2) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x4) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x8) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */ +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x1) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x2) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x4) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x8) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */ +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x1) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x2) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x4) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x8) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */ +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x1) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x2) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x4) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x8) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */ +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x1) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x2) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x4) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x8) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */ +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x1) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1 (0x2) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x4) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x8) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4 (0x10) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5 (0x20) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6 (0x40) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */ +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x1) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x2) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x4) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x8) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */ +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x1) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x2) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x4) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x8) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */ +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x1) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x2) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x4) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x8) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */ +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x1) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x2) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x4) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3 (0x8) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4 (0x10) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */ +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x1) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x2) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x4) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x8) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */ +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x1) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x2) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x4) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x8) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */ +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x1) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x2) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x4) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x8) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */ +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x1) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x2) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x4) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x8) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4 (0x10) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x1) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x2) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x4) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x1) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x2) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x4) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x1) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x2) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x4) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */ +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x1) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x2) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x4) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x8) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */ +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x1) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x2) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x4) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x8) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */ +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x1) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x2) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x4) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x8) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */ +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0 (0x1) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1 (0x2) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2 (0x4) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x8) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */ +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x1) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x2) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x4) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x8) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */ +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x1) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x2) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x4) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x8) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */ +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x1) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x2) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x4) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x8) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */ +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x1) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x2) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x4) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3 (0x8) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */ +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */ +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */ +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */ +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */ +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */ +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */ +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */ +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */ +#define MCF_GPIO_PODR_DSPI_PODR_DSPI0 (0x1) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI1 (0x2) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI2 (0x4) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI3 (0x8) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI4 (0x10) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI5 (0x20) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */ +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x1) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x2) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x4) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x8) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */ +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x1) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x2) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x4) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x8) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4 (0x10) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */ +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x1) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x2) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x4) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x8) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40) + + +#endif /* __MCF5475_GPIO_H__ */ diff --git a/tos/vmem_test/include/MCF5475_GPT.h b/tos/vmem_test/include/MCF5475_GPT.h new file mode 100644 index 0000000..f9fbc98 --- /dev/null +++ b/tos/vmem_test/include/MCF5475_GPT.h @@ -0,0 +1,100 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_GPT_H__ +#define __MCF5475_GPT_H__ + + +/********************************************************************* +* +* General Purpose Timers (GPT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPT0_GMS (*(volatile uint32_t*)(&_MBAR[0x800])) +#define MCF_GPT0_GCIR (*(volatile uint32_t*)(&_MBAR[0x804])) +#define MCF_GPT0_GPWM (*(volatile uint32_t*)(&_MBAR[0x808])) +#define MCF_GPT0_GSR (*(volatile uint32_t*)(&_MBAR[0x80C])) + +#define MCF_GPT1_GMS (*(volatile uint32_t*)(&_MBAR[0x810])) +#define MCF_GPT1_GCIR (*(volatile uint32_t*)(&_MBAR[0x814])) +#define MCF_GPT1_GPWM (*(volatile uint32_t*)(&_MBAR[0x818])) +#define MCF_GPT1_GSR (*(volatile uint32_t*)(&_MBAR[0x81C])) + +#define MCF_GPT2_GMS (*(volatile uint32_t*)(&_MBAR[0x820])) +#define MCF_GPT2_GCIR (*(volatile uint32_t*)(&_MBAR[0x824])) +#define MCF_GPT2_GPWM (*(volatile uint32_t*)(&_MBAR[0x828])) +#define MCF_GPT2_GSR (*(volatile uint32_t*)(&_MBAR[0x82C])) + +#define MCF_GPT3_GMS (*(volatile uint32_t*)(&_MBAR[0x830])) +#define MCF_GPT3_GCIR (*(volatile uint32_t*)(&_MBAR[0x834])) +#define MCF_GPT3_GPWM (*(volatile uint32_t*)(&_MBAR[0x838])) +#define MCF_GPT3_GSR (*(volatile uint32_t*)(&_MBAR[0x83C])) + +#define MCF_GPT_GMS(x) (*(volatile uint32_t*)(&_MBAR[0x800 + ((x)*0x10)])) +#define MCF_GPT_GCIR(x) (*(volatile uint32_t*)(&_MBAR[0x804 + ((x)*0x10)])) +#define MCF_GPT_GPWM(x) (*(volatile uint32_t*)(&_MBAR[0x808 + ((x)*0x10)])) +#define MCF_GPT_GSR(x) (*(volatile uint32_t*)(&_MBAR[0x80C + ((x)*0x10)])) + + +/* Bit definitions and macros for MCF_GPT_GMS */ +#define MCF_GPT_GMS_TMS(x) (((x)&0x7)<<0) +#define MCF_GPT_GMS_TMS_DISABLE (0) +#define MCF_GPT_GMS_TMS_INCAPT (0x1) +#define MCF_GPT_GMS_TMS_OUTCAPT (0x2) +#define MCF_GPT_GMS_TMS_PWM (0x3) +#define MCF_GPT_GMS_TMS_GPIO (0x4) +#define MCF_GPT_GMS_GPIO(x) (((x)&0x3)<<0x4) +#define MCF_GPT_GMS_GPIO_INPUT (0) +#define MCF_GPT_GMS_GPIO_OUTLO (0x20) +#define MCF_GPT_GMS_GPIO_OUTHI (0x30) +#define MCF_GPT_GMS_IEN (0x100) +#define MCF_GPT_GMS_OD (0x200) +#define MCF_GPT_GMS_SC (0x400) +#define MCF_GPT_GMS_CE (0x1000) +#define MCF_GPT_GMS_WDEN (0x8000) +#define MCF_GPT_GMS_ICT(x) (((x)&0x3)<<0x10) +#define MCF_GPT_GMS_ICT_ANY (0) +#define MCF_GPT_GMS_ICT_RISE (0x10000) +#define MCF_GPT_GMS_ICT_FALL (0x20000) +#define MCF_GPT_GMS_ICT_PULSE (0x30000) +#define MCF_GPT_GMS_OCT(x) (((x)&0x3)<<0x14) +#define MCF_GPT_GMS_OCT_FRCLOW (0) +#define MCF_GPT_GMS_OCT_PULSEHI (0x100000) +#define MCF_GPT_GMS_OCT_PULSELO (0x200000) +#define MCF_GPT_GMS_OCT_TOGGLE (0x300000) +#define MCF_GPT_GMS_OCPW(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_GPT_GCIR */ +#define MCF_GPT_GCIR_CNT(x) (((x)&0xFFFF)<<0) +#define MCF_GPT_GCIR_PRE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_GPT_GPWM */ +#define MCF_GPT_GPWM_LOAD (0x1) +#define MCF_GPT_GPWM_PWMOP (0x100) +#define MCF_GPT_GPWM_WIDTH(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_GPT_GSR */ +#define MCF_GPT_GSR_CAPT (0x1) +#define MCF_GPT_GSR_COMP (0x2) +#define MCF_GPT_GSR_PWMP (0x4) +#define MCF_GPT_GSR_TEXP (0x8) +#define MCF_GPT_GSR_PIN (0x100) +#define MCF_GPT_GSR_OVF(x) (((x)&0x7)<<0xC) +#define MCF_GPT_GSR_CAPTURE(x) (((x)&0xFFFF)<<0x10) + + +#endif /* __MCF5475_GPT_H__ */ diff --git a/tos/vmem_test/include/MCF5475_I2C.h b/tos/vmem_test/include/MCF5475_I2C.h new file mode 100644 index 0000000..1e8a85b --- /dev/null +++ b/tos/vmem_test/include/MCF5475_I2C.h @@ -0,0 +1,69 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_I2C_H__ +#define __MCF5475_I2C_H__ + + +/********************************************************************* +* +* I2C Module (I2C) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_I2C_I2ADR (*(volatile uint8_t *)(&_MBAR[0x8F00])) +#define MCF_I2C_I2FDR (*(volatile uint8_t *)(&_MBAR[0x8F04])) +#define MCF_I2C_I2CR (*(volatile uint8_t *)(&_MBAR[0x8F08])) +#define MCF_I2C_I2SR (*(volatile uint8_t *)(&_MBAR[0x8F0C])) +#define MCF_I2C_I2DR (*(volatile uint8_t *)(&_MBAR[0x8F10])) +#define MCF_I2C_I2ICR (*(volatile uint8_t *)(&_MBAR[0x8F20])) + + + +/* Bit definitions and macros for MCF_I2C_I2ADR */ +#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1) + +/* Bit definitions and macros for MCF_I2C_I2FDR */ +#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) + +/* Bit definitions and macros for MCF_I2C_I2CR */ +#define MCF_I2C_I2CR_RSTA (0x4) +#define MCF_I2C_I2CR_TXAK (0x8) +#define MCF_I2C_I2CR_MTX (0x10) +#define MCF_I2C_I2CR_MSTA (0x20) +#define MCF_I2C_I2CR_IIEN (0x40) +#define MCF_I2C_I2CR_IEN (0x80) + +/* Bit definitions and macros for MCF_I2C_I2SR */ +#define MCF_I2C_I2SR_RXAK (0x1) +#define MCF_I2C_I2SR_IIF (0x2) +#define MCF_I2C_I2SR_SRW (0x4) +#define MCF_I2C_I2SR_IAL (0x10) +#define MCF_I2C_I2SR_IBB (0x20) +#define MCF_I2C_I2SR_IAAS (0x40) +#define MCF_I2C_I2SR_ICF (0x80) + +/* Bit definitions and macros for MCF_I2C_I2DR */ +#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_I2C_I2ICR */ +#define MCF_I2C_I2ICR_IE (0x1) +#define MCF_I2C_I2ICR_RE (0x2) +#define MCF_I2C_I2ICR_TE (0x4) +#define MCF_I2C_I2ICR_BNBE (0x8) + + +#endif /* __MCF5475_I2C_H__ */ diff --git a/tos/vmem_test/include/MCF5475_INTC.h b/tos/vmem_test/include/MCF5475_INTC.h new file mode 100644 index 0000000..61265ed --- /dev/null +++ b/tos/vmem_test/include/MCF5475_INTC.h @@ -0,0 +1,331 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_INTC_H__ +#define __MCF5475_INTC_H__ + + +/********************************************************************* +* +* Interrupt Controller (INTC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_INTC_IPRH (*(volatile uint32_t*)(&_MBAR[0x700])) +#define MCF_INTC_IPRL (*(volatile uint32_t*)(&_MBAR[0x704])) +#define MCF_INTC_IMRH (*(volatile uint32_t*)(&_MBAR[0x708])) +#define MCF_INTC_IMRL (*(volatile uint32_t*)(&_MBAR[0x70C])) +#define MCF_INTC_INTFRCH (*(volatile uint32_t*)(&_MBAR[0x710])) +#define MCF_INTC_INTFRCL (*(volatile uint32_t*)(&_MBAR[0x714])) +#define MCF_INTC_IRLR (*(volatile uint8_t *)(&_MBAR[0x718])) +#define MCF_INTC_IACKLPR (*(volatile uint8_t *)(&_MBAR[0x719])) +#define MCF_INTC_ICR01 (*(volatile uint8_t *)(&_MBAR[0x741])) +#define MCF_INTC_ICR02 (*(volatile uint8_t *)(&_MBAR[0x742])) +#define MCF_INTC_ICR03 (*(volatile uint8_t *)(&_MBAR[0x743])) +#define MCF_INTC_ICR04 (*(volatile uint8_t *)(&_MBAR[0x744])) +#define MCF_INTC_ICR05 (*(volatile uint8_t *)(&_MBAR[0x745])) +#define MCF_INTC_ICR06 (*(volatile uint8_t *)(&_MBAR[0x746])) +#define MCF_INTC_ICR07 (*(volatile uint8_t *)(&_MBAR[0x747])) +#define MCF_INTC_ICR08 (*(volatile uint8_t *)(&_MBAR[0x748])) +#define MCF_INTC_ICR09 (*(volatile uint8_t *)(&_MBAR[0x749])) +#define MCF_INTC_ICR10 (*(volatile uint8_t *)(&_MBAR[0x74A])) +#define MCF_INTC_ICR11 (*(volatile uint8_t *)(&_MBAR[0x74B])) +#define MCF_INTC_ICR12 (*(volatile uint8_t *)(&_MBAR[0x74C])) +#define MCF_INTC_ICR13 (*(volatile uint8_t *)(&_MBAR[0x74D])) +#define MCF_INTC_ICR14 (*(volatile uint8_t *)(&_MBAR[0x74E])) +#define MCF_INTC_ICR15 (*(volatile uint8_t *)(&_MBAR[0x74F])) +#define MCF_INTC_ICR16 (*(volatile uint8_t *)(&_MBAR[0x750])) +#define MCF_INTC_ICR17 (*(volatile uint8_t *)(&_MBAR[0x751])) +#define MCF_INTC_ICR18 (*(volatile uint8_t *)(&_MBAR[0x752])) +#define MCF_INTC_ICR19 (*(volatile uint8_t *)(&_MBAR[0x753])) +#define MCF_INTC_ICR20 (*(volatile uint8_t *)(&_MBAR[0x754])) +#define MCF_INTC_ICR21 (*(volatile uint8_t *)(&_MBAR[0x755])) +#define MCF_INTC_ICR22 (*(volatile uint8_t *)(&_MBAR[0x756])) +#define MCF_INTC_ICR23 (*(volatile uint8_t *)(&_MBAR[0x757])) +#define MCF_INTC_ICR24 (*(volatile uint8_t *)(&_MBAR[0x758])) +#define MCF_INTC_ICR25 (*(volatile uint8_t *)(&_MBAR[0x759])) +#define MCF_INTC_ICR26 (*(volatile uint8_t *)(&_MBAR[0x75A])) +#define MCF_INTC_ICR27 (*(volatile uint8_t *)(&_MBAR[0x75B])) +#define MCF_INTC_ICR28 (*(volatile uint8_t *)(&_MBAR[0x75C])) +#define MCF_INTC_ICR29 (*(volatile uint8_t *)(&_MBAR[0x75D])) +#define MCF_INTC_ICR30 (*(volatile uint8_t *)(&_MBAR[0x75E])) +#define MCF_INTC_ICR31 (*(volatile uint8_t *)(&_MBAR[0x75F])) +#define MCF_INTC_ICR32 (*(volatile uint8_t *)(&_MBAR[0x760])) +#define MCF_INTC_ICR33 (*(volatile uint8_t *)(&_MBAR[0x761])) +#define MCF_INTC_ICR34 (*(volatile uint8_t *)(&_MBAR[0x762])) +#define MCF_INTC_ICR35 (*(volatile uint8_t *)(&_MBAR[0x763])) +#define MCF_INTC_ICR36 (*(volatile uint8_t *)(&_MBAR[0x764])) +#define MCF_INTC_ICR37 (*(volatile uint8_t *)(&_MBAR[0x765])) +#define MCF_INTC_ICR38 (*(volatile uint8_t *)(&_MBAR[0x766])) +#define MCF_INTC_ICR39 (*(volatile uint8_t *)(&_MBAR[0x767])) +#define MCF_INTC_ICR40 (*(volatile uint8_t *)(&_MBAR[0x768])) +#define MCF_INTC_ICR41 (*(volatile uint8_t *)(&_MBAR[0x769])) +#define MCF_INTC_ICR42 (*(volatile uint8_t *)(&_MBAR[0x76A])) +#define MCF_INTC_ICR43 (*(volatile uint8_t *)(&_MBAR[0x76B])) +#define MCF_INTC_ICR44 (*(volatile uint8_t *)(&_MBAR[0x76C])) +#define MCF_INTC_ICR45 (*(volatile uint8_t *)(&_MBAR[0x76D])) +#define MCF_INTC_ICR46 (*(volatile uint8_t *)(&_MBAR[0x76E])) +#define MCF_INTC_ICR47 (*(volatile uint8_t *)(&_MBAR[0x76F])) +#define MCF_INTC_ICR48 (*(volatile uint8_t *)(&_MBAR[0x770])) +#define MCF_INTC_ICR49 (*(volatile uint8_t *)(&_MBAR[0x771])) +#define MCF_INTC_ICR50 (*(volatile uint8_t *)(&_MBAR[0x772])) +#define MCF_INTC_ICR51 (*(volatile uint8_t *)(&_MBAR[0x773])) +#define MCF_INTC_ICR52 (*(volatile uint8_t *)(&_MBAR[0x774])) +#define MCF_INTC_ICR53 (*(volatile uint8_t *)(&_MBAR[0x775])) +#define MCF_INTC_ICR54 (*(volatile uint8_t *)(&_MBAR[0x776])) +#define MCF_INTC_ICR55 (*(volatile uint8_t *)(&_MBAR[0x777])) +#define MCF_INTC_ICR56 (*(volatile uint8_t *)(&_MBAR[0x778])) +#define MCF_INTC_ICR57 (*(volatile uint8_t *)(&_MBAR[0x779])) +#define MCF_INTC_ICR58 (*(volatile uint8_t *)(&_MBAR[0x77A])) +#define MCF_INTC_ICR59 (*(volatile uint8_t *)(&_MBAR[0x77B])) +#define MCF_INTC_ICR60 (*(volatile uint8_t *)(&_MBAR[0x77C])) +#define MCF_INTC_ICR61 (*(volatile uint8_t *)(&_MBAR[0x77D])) +#define MCF_INTC_ICR62 (*(volatile uint8_t *)(&_MBAR[0x77E])) +#define MCF_INTC_ICR63 (*(volatile uint8_t *)(&_MBAR[0x77F])) +#define MCF_INTC_SWIACK (*(volatile uint8_t *)(&_MBAR[0x7E0])) +#define MCF_INTC_L1IACK (*(volatile uint8_t *)(&_MBAR[0x7E4])) +#define MCF_INTC_L2IACK (*(volatile uint8_t *)(&_MBAR[0x7E8])) +#define MCF_INTC_L3IACK (*(volatile uint8_t *)(&_MBAR[0x7EC])) +#define MCF_INTC_L4IACK (*(volatile uint8_t *)(&_MBAR[0x7F0])) +#define MCF_INTC_L5IACK (*(volatile uint8_t *)(&_MBAR[0x7F4])) +#define MCF_INTC_L6IACK (*(volatile uint8_t *)(&_MBAR[0x7F8])) +#define MCF_INTC_L7IACK (*(volatile uint8_t *)(&_MBAR[0x7FC])) +#define MCF_INTC_ICR(x) (*(volatile uint8_t *)(&_MBAR[0x741 + ((x-1)*0x1)])) +#define MCF_INTC_LIACK(x) (*(volatile uint8_t *)(&_MBAR[0x7E4 + ((x-1)*0x4)])) + + + +/* Bit definitions and macros for MCF_INTC_IPRH */ +#define MCF_INTC_IPRH_INT32 (0x1) +#define MCF_INTC_IPRH_INT33 (0x2) +#define MCF_INTC_IPRH_INT34 (0x4) +#define MCF_INTC_IPRH_INT35 (0x8) +#define MCF_INTC_IPRH_INT36 (0x10) +#define MCF_INTC_IPRH_INT37 (0x20) +#define MCF_INTC_IPRH_INT38 (0x40) +#define MCF_INTC_IPRH_INT39 (0x80) +#define MCF_INTC_IPRH_INT40 (0x100) +#define MCF_INTC_IPRH_INT41 (0x200) +#define MCF_INTC_IPRH_INT42 (0x400) +#define MCF_INTC_IPRH_INT43 (0x800) +#define MCF_INTC_IPRH_INT44 (0x1000) +#define MCF_INTC_IPRH_INT45 (0x2000) +#define MCF_INTC_IPRH_INT46 (0x4000) +#define MCF_INTC_IPRH_INT47 (0x8000) +#define MCF_INTC_IPRH_INT48 (0x10000) +#define MCF_INTC_IPRH_INT49 (0x20000) +#define MCF_INTC_IPRH_INT50 (0x40000) +#define MCF_INTC_IPRH_INT51 (0x80000) +#define MCF_INTC_IPRH_INT52 (0x100000) +#define MCF_INTC_IPRH_INT53 (0x200000) +#define MCF_INTC_IPRH_INT54 (0x400000) +#define MCF_INTC_IPRH_INT55 (0x800000) +#define MCF_INTC_IPRH_INT56 (0x1000000) +#define MCF_INTC_IPRH_INT57 (0x2000000) +#define MCF_INTC_IPRH_INT58 (0x4000000) +#define MCF_INTC_IPRH_INT59 (0x8000000) +#define MCF_INTC_IPRH_INT60 (0x10000000) +#define MCF_INTC_IPRH_INT61 (0x20000000) +#define MCF_INTC_IPRH_INT62 (0x40000000) +#define MCF_INTC_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IPRL */ +#define MCF_INTC_IPRL_INT1 (0x2) +#define MCF_INTC_IPRL_INT2 (0x4) +#define MCF_INTC_IPRL_INT3 (0x8) +#define MCF_INTC_IPRL_INT4 (0x10) +#define MCF_INTC_IPRL_INT5 (0x20) +#define MCF_INTC_IPRL_INT6 (0x40) +#define MCF_INTC_IPRL_INT7 (0x80) +#define MCF_INTC_IPRL_INT8 (0x100) +#define MCF_INTC_IPRL_INT9 (0x200) +#define MCF_INTC_IPRL_INT10 (0x400) +#define MCF_INTC_IPRL_INT11 (0x800) +#define MCF_INTC_IPRL_INT12 (0x1000) +#define MCF_INTC_IPRL_INT13 (0x2000) +#define MCF_INTC_IPRL_INT14 (0x4000) +#define MCF_INTC_IPRL_INT15 (0x8000) +#define MCF_INTC_IPRL_INT16 (0x10000) +#define MCF_INTC_IPRL_INT17 (0x20000) +#define MCF_INTC_IPRL_INT18 (0x40000) +#define MCF_INTC_IPRL_INT19 (0x80000) +#define MCF_INTC_IPRL_INT20 (0x100000) +#define MCF_INTC_IPRL_INT21 (0x200000) +#define MCF_INTC_IPRL_INT22 (0x400000) +#define MCF_INTC_IPRL_INT23 (0x800000) +#define MCF_INTC_IPRL_INT24 (0x1000000) +#define MCF_INTC_IPRL_INT25 (0x2000000) +#define MCF_INTC_IPRL_INT26 (0x4000000) +#define MCF_INTC_IPRL_INT27 (0x8000000) +#define MCF_INTC_IPRL_INT28 (0x10000000) +#define MCF_INTC_IPRL_INT29 (0x20000000) +#define MCF_INTC_IPRL_INT30 (0x40000000) +#define MCF_INTC_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRH */ +#define MCF_INTC_IMRH_INT_MASK32 (0x1) +#define MCF_INTC_IMRH_INT_MASK33 (0x2) +#define MCF_INTC_IMRH_INT_MASK34 (0x4) +#define MCF_INTC_IMRH_INT_MASK35 (0x8) +#define MCF_INTC_IMRH_INT_MASK36 (0x10) +#define MCF_INTC_IMRH_INT_MASK37 (0x20) +#define MCF_INTC_IMRH_INT_MASK38 (0x40) +#define MCF_INTC_IMRH_INT_MASK39 (0x80) +#define MCF_INTC_IMRH_INT_MASK40 (0x100) +#define MCF_INTC_IMRH_INT_MASK41 (0x200) +#define MCF_INTC_IMRH_INT_MASK42 (0x400) +#define MCF_INTC_IMRH_INT_MASK43 (0x800) +#define MCF_INTC_IMRH_INT_MASK44 (0x1000) +#define MCF_INTC_IMRH_INT_MASK45 (0x2000) +#define MCF_INTC_IMRH_INT_MASK46 (0x4000) +#define MCF_INTC_IMRH_INT_MASK47 (0x8000) +#define MCF_INTC_IMRH_INT_MASK48 (0x10000) +#define MCF_INTC_IMRH_INT_MASK49 (0x20000) +#define MCF_INTC_IMRH_INT_MASK50 (0x40000) +#define MCF_INTC_IMRH_INT_MASK51 (0x80000) +#define MCF_INTC_IMRH_INT_MASK52 (0x100000) +#define MCF_INTC_IMRH_INT_MASK53 (0x200000) +#define MCF_INTC_IMRH_INT_MASK54 (0x400000) +#define MCF_INTC_IMRH_INT_MASK55 (0x800000) +#define MCF_INTC_IMRH_INT_MASK56 (0x1000000) +#define MCF_INTC_IMRH_INT_MASK57 (0x2000000) +#define MCF_INTC_IMRH_INT_MASK58 (0x4000000) +#define MCF_INTC_IMRH_INT_MASK59 (0x8000000) +#define MCF_INTC_IMRH_INT_MASK60 (0x10000000) +#define MCF_INTC_IMRH_INT_MASK61 (0x20000000) +#define MCF_INTC_IMRH_INT_MASK62 (0x40000000) +#define MCF_INTC_IMRH_INT_MASK63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRL */ +#define MCF_INTC_IMRL_MASKALL (0x1) +#define MCF_INTC_IMRL_INT_MASK1 (0x2) +#define MCF_INTC_IMRL_INT_MASK2 (0x4) +#define MCF_INTC_IMRL_INT_MASK3 (0x8) +#define MCF_INTC_IMRL_INT_MASK4 (0x10) +#define MCF_INTC_IMRL_INT_MASK5 (0x20) +#define MCF_INTC_IMRL_INT_MASK6 (0x40) +#define MCF_INTC_IMRL_INT_MASK7 (0x80) +#define MCF_INTC_IMRL_INT_MASK8 (0x100) +#define MCF_INTC_IMRL_INT_MASK9 (0x200) +#define MCF_INTC_IMRL_INT_MASK10 (0x400) +#define MCF_INTC_IMRL_INT_MASK11 (0x800) +#define MCF_INTC_IMRL_INT_MASK12 (0x1000) +#define MCF_INTC_IMRL_INT_MASK13 (0x2000) +#define MCF_INTC_IMRL_INT_MASK14 (0x4000) +#define MCF_INTC_IMRL_INT_MASK15 (0x8000) +#define MCF_INTC_IMRL_INT_MASK16 (0x10000) +#define MCF_INTC_IMRL_INT_MASK17 (0x20000) +#define MCF_INTC_IMRL_INT_MASK18 (0x40000) +#define MCF_INTC_IMRL_INT_MASK19 (0x80000) +#define MCF_INTC_IMRL_INT_MASK20 (0x100000) +#define MCF_INTC_IMRL_INT_MASK21 (0x200000) +#define MCF_INTC_IMRL_INT_MASK22 (0x400000) +#define MCF_INTC_IMRL_INT_MASK23 (0x800000) +#define MCF_INTC_IMRL_INT_MASK24 (0x1000000) +#define MCF_INTC_IMRL_INT_MASK25 (0x2000000) +#define MCF_INTC_IMRL_INT_MASK26 (0x4000000) +#define MCF_INTC_IMRL_INT_MASK27 (0x8000000) +#define MCF_INTC_IMRL_INT_MASK28 (0x10000000) +#define MCF_INTC_IMRL_INT_MASK29 (0x20000000) +#define MCF_INTC_IMRL_INT_MASK30 (0x40000000) +#define MCF_INTC_IMRL_INT_MASK31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCH */ +#define MCF_INTC_INTFRCH_INTFRC32 (0x1) +#define MCF_INTC_INTFRCH_INTFRC33 (0x2) +#define MCF_INTC_INTFRCH_INTFRC34 (0x4) +#define MCF_INTC_INTFRCH_INTFRC35 (0x8) +#define MCF_INTC_INTFRCH_INTFRC36 (0x10) +#define MCF_INTC_INTFRCH_INTFRC37 (0x20) +#define MCF_INTC_INTFRCH_INTFRC38 (0x40) +#define MCF_INTC_INTFRCH_INTFRC39 (0x80) +#define MCF_INTC_INTFRCH_INTFRC40 (0x100) +#define MCF_INTC_INTFRCH_INTFRC41 (0x200) +#define MCF_INTC_INTFRCH_INTFRC42 (0x400) +#define MCF_INTC_INTFRCH_INTFRC43 (0x800) +#define MCF_INTC_INTFRCH_INTFRC44 (0x1000) +#define MCF_INTC_INTFRCH_INTFRC45 (0x2000) +#define MCF_INTC_INTFRCH_INTFRC46 (0x4000) +#define MCF_INTC_INTFRCH_INTFRC47 (0x8000) +#define MCF_INTC_INTFRCH_INTFRC48 (0x10000) +#define MCF_INTC_INTFRCH_INTFRC49 (0x20000) +#define MCF_INTC_INTFRCH_INTFRC50 (0x40000) +#define MCF_INTC_INTFRCH_INTFRC51 (0x80000) +#define MCF_INTC_INTFRCH_INTFRC52 (0x100000) +#define MCF_INTC_INTFRCH_INTFRC53 (0x200000) +#define MCF_INTC_INTFRCH_INTFRC54 (0x400000) +#define MCF_INTC_INTFRCH_INTFRC55 (0x800000) +#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000) +#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000) +#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000) +#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000) +#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) +#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) +#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) +#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCL */ +#define MCF_INTC_INTFRCL_INTFRC1 (0x2) +#define MCF_INTC_INTFRCL_INTFRC2 (0x4) +#define MCF_INTC_INTFRCL_INTFRC3 (0x8) +#define MCF_INTC_INTFRCL_INTFRC4 (0x10) +#define MCF_INTC_INTFRCL_INTFRC5 (0x20) +#define MCF_INTC_INTFRCL_INTFRC6 (0x40) +#define MCF_INTC_INTFRCL_INTFRC7 (0x80) +#define MCF_INTC_INTFRCL_INTFRC8 (0x100) +#define MCF_INTC_INTFRCL_INTFRC9 (0x200) +#define MCF_INTC_INTFRCL_INTFRC10 (0x400) +#define MCF_INTC_INTFRCL_INTFRC11 (0x800) +#define MCF_INTC_INTFRCL_INTFRC12 (0x1000) +#define MCF_INTC_INTFRCL_INTFRC13 (0x2000) +#define MCF_INTC_INTFRCL_INTFRC14 (0x4000) +#define MCF_INTC_INTFRCL_INTFRC15 (0x8000) +#define MCF_INTC_INTFRCL_INTFRC16 (0x10000) +#define MCF_INTC_INTFRCL_INTFRC17 (0x20000) +#define MCF_INTC_INTFRCL_INTFRC18 (0x40000) +#define MCF_INTC_INTFRCL_INTFRC19 (0x80000) +#define MCF_INTC_INTFRCL_INTFRC20 (0x100000) +#define MCF_INTC_INTFRCL_INTFRC21 (0x200000) +#define MCF_INTC_INTFRCL_INTFRC22 (0x400000) +#define MCF_INTC_INTFRCL_INTFRC23 (0x800000) +#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000) +#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000) +#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000) +#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000) +#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) +#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) +#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) +#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IRLR */ +#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1) + +/* Bit definitions and macros for MCF_INTC_IACKLPR */ +#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0) +#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4) + +/* Bit definitions and macros for MCF_INTC_ICR */ +#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0) +#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3) + +/* Bit definitions and macros for MCF_INTC_SWIACK */ +#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_INTC_LIACK */ +#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) + + +#endif /* __MCF5475_INTC_H__ */ diff --git a/tos/vmem_test/include/MCF5475_MMU.h b/tos/vmem_test/include/MCF5475_MMU.h new file mode 100644 index 0000000..334ad28 --- /dev/null +++ b/tos/vmem_test/include/MCF5475_MMU.h @@ -0,0 +1,79 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_MMU_H__ +#define __MCF5475_MMU_H__ + + +/********************************************************************* +* +* Memory Management Unit (MMU) +* +*********************************************************************/ + +/* Register read/write macros */ + +/* note the uint32_t_a - this is to avoid gcc warnings about pointer aliasing */ +#define MCF_MMU_MMUCR (*(volatile uint32_t_a*)(&_MMUBAR[0])) +#define MCF_MMU_MMUOR (*(volatile uint32_t_a*)(&_MMUBAR[0x4])) +#define MCF_MMU_MMUSR (*(volatile uint32_t_a*)(&_MMUBAR[0x8])) +#define MCF_MMU_MMUAR (*(volatile uint32_t_a*)(&_MMUBAR[0x10])) +#define MCF_MMU_MMUTR (*(volatile uint32_t_a*)(&_MMUBAR[0x14])) +#define MCF_MMU_MMUDR (*(volatile uint32_t_a*)(&_MMUBAR[0x18])) + + +/* Bit definitions and macros for MCF_MMU_MMUCR */ +#define MCF_MMU_MMUCR_EN (0x1) +#define MCF_MMU_MMUCR_ASM (0x2) + +/* Bit definitions and macros for MCF_MMU_MMUOR */ +#define MCF_MMU_MMUOR_UAA (0x1) +#define MCF_MMU_MMUOR_ACC (0x2) +#define MCF_MMU_MMUOR_RW (0x4) +#define MCF_MMU_MMUOR_ADR (0x8) +#define MCF_MMU_MMUOR_ITLB (0x10) +#define MCF_MMU_MMUOR_CAS (0x20) +#define MCF_MMU_MMUOR_CNL (0x40) +#define MCF_MMU_MMUOR_CA (0x80) +#define MCF_MMU_MMUOR_STLB (0x100) +#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_MMU_MMUSR */ +#define MCF_MMU_MMUSR_HIT (0x2) +#define MCF_MMU_MMUSR_WF (0x8) +#define MCF_MMU_MMUSR_RF (0x10) +#define MCF_MMU_MMUSR_SPF (0x20) + +/* Bit definitions and macros for MCF_MMU_MMUAR */ +#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MMU_MMUTR */ +#define MCF_MMU_MMUTR_V (0x1) +#define MCF_MMU_MMUTR_SG (0x2) +#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2) +#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA) + +/* Bit definitions and macros for MCF_MMU_MMUDR */ +#define MCF_MMU_MMUDR_LK (0x2) +#define MCF_MMU_MMUDR_X (0x4) +#define MCF_MMU_MMUDR_W (0x8) +#define MCF_MMU_MMUDR_R (0x10) +#define MCF_MMU_MMUDR_SP (0x20) +#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6) +#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8) +#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA) + + +#endif /* __MCF5475_MMU_H__ */ diff --git a/tos/vmem_test/include/MCF5475_PAD.h b/tos/vmem_test/include/MCF5475_PAD.h new file mode 100644 index 0000000..1d87e2e --- /dev/null +++ b/tos/vmem_test/include/MCF5475_PAD.h @@ -0,0 +1,233 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PAD_H__ +#define __MCF5475_PAD_H__ + + +/********************************************************************* +* +* Common GPIO +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PAD_PAR_FBCTL (*(volatile uint16_t*)(&_MBAR[0xA40])) +#define MCF_PAD_PAR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA42])) +#define MCF_PAD_PAR_DMA (*(volatile uint8_t *)(&_MBAR[0xA43])) +#define MCF_PAD_PAR_FECI2CIRQ (*(volatile uint16_t*)(&_MBAR[0xA44])) +#define MCF_PAD_PAR_PCIBG (*(volatile uint16_t*)(&_MBAR[0xA48])) +#define MCF_PAD_PAR_PCIBR (*(volatile uint16_t*)(&_MBAR[0xA4A])) +#define MCF_PAD_PAR_PSC3 (*(volatile uint8_t *)(&_MBAR[0xA4C])) +#define MCF_PAD_PAR_PSC2 (*(volatile uint8_t *)(&_MBAR[0xA4D])) +#define MCF_PAD_PAR_PSC1 (*(volatile uint8_t *)(&_MBAR[0xA4E])) +#define MCF_PAD_PAR_PSC0 (*(volatile uint8_t *)(&_MBAR[0xA4F])) +#define MCF_PAD_PAR_DSPI (*(volatile uint16_t*)(&_MBAR[0xA50])) +#define MCF_PAD_PAR_TIMER (*(volatile uint8_t *)(&_MBAR[0xA52])) + + +/* Bit definitions and macros for MCF_PAD_PAR_FBCTL */ +#define MCF_PAD_PAR_FBCTL_PAR_ALE(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_FBCTL_PAR_ALE_GPIO (0) +#define MCF_PAD_PAR_FBCTL_PAR_ALE_TBST (0x2) +#define MCF_PAD_PAR_FBCTL_PAR_ALE_ALE (0x3) +#define MCF_PAD_PAR_FBCTL_PAR_TA (0x4) +#define MCF_PAD_PAR_FBCTL_PAR_RWB(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_FBCTL_PAR_RWB_GPIO (0) +#define MCF_PAD_PAR_FBCTL_PAR_RWB_TBST (0x20) +#define MCF_PAD_PAR_FBCTL_PAR_RWB_RW (0x30) +#define MCF_PAD_PAR_FBCTL_PAR_OE (0x40) +#define MCF_PAD_PAR_FBCTL_PAR_BWE0 (0x100) +#define MCF_PAD_PAR_FBCTL_PAR_BWE1 (0x400) +#define MCF_PAD_PAR_FBCTL_PAR_BWE2 (0x1000) +#define MCF_PAD_PAR_FBCTL_PAR_BWE3 (0x4000) + +/* Bit definitions and macros for MCF_PAD_PAR_FBCS */ +#define MCF_PAD_PAR_FBCS_PAR_CS1 (0x2) +#define MCF_PAD_PAR_FBCS_PAR_CS2 (0x4) +#define MCF_PAD_PAR_FBCS_PAR_CS3 (0x8) +#define MCF_PAD_PAR_FBCS_PAR_CS4 (0x10) +#define MCF_PAD_PAR_FBCS_PAR_CS5 (0x20) + +/* Bit definitions and macros for MCF_PAD_PAR_DMA */ +#define MCF_PAD_PAR_DMA_PAR_DREQ0(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_DMA_PAR_DREQ0_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DREQ0_TIN0 (0x2) +#define MCF_PAD_PAR_DMA_PAR_DREQ0_DREQ0 (0x3) +#define MCF_PAD_PAR_DMA_PAR_DREQ1(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_IRQ1 (0x4) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_TIN1 (0x8) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_DREQ1 (0xC) +#define MCF_PAD_PAR_DMA_PAR_DACK0(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_DMA_PAR_DACK0_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DACK0_TOUT0 (0x20) +#define MCF_PAD_PAR_DMA_PAR_DACK0_DACK0 (0x30) +#define MCF_PAD_PAR_DMA_PAR_DACK1(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_DMA_PAR_DACK1_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DACK1_TOUT1 (0x80) +#define MCF_PAD_PAR_DMA_PAR_DACK1_DACK1 (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_FECI2CIRQ */ +#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ5 (0x1) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ6 (0x2) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_SCL (0x4) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_SDA (0x8) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x80) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC (0xC0) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x200) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO (0x300) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MII (0x400) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E17 (0x800) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC (0x1000) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII (0x4000) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E07 (0x8000) + +/* Bit definitions and macros for MCF_PAD_PAR_PCIBG */ +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_TOUT0 (0x2) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0 (0x3) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_TOUT1 (0x8) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 (0xC) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_TOUT2 (0x20) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 (0x30) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_TOUT3 (0x80) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3 (0xC0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST (0x200) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4 (0x300) + +/* Bit definitions and macros for MCF_PAD_PAR_PCIBR */ +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_TIN0 (0x2) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0 (0x3) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_TIN1 (0x8) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 (0xC) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_TIN2 (0x20) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 (0x30) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_TIN3 (0x80) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3 (0xC0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4 (0x200) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4 (0x300) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC3 */ +#define MCF_PAD_PAR_PSC3_PAR_TXD3 (0x4) +#define MCF_PAD_PAR_PSC3_PAR_RXD3 (0x8) +#define MCF_PAD_PAR_PSC3_PAR_RTS3(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC3_PAR_RTS3_GPIO (0) +#define MCF_PAD_PAR_PSC3_PAR_RTS3_FSYNC (0x20) +#define MCF_PAD_PAR_PSC3_PAR_RTS3_RTS (0x30) +#define MCF_PAD_PAR_PSC3_PAR_CTS3(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC3_PAR_CTS3_GPIO (0) +#define MCF_PAD_PAR_PSC3_PAR_CTS3_BCLK (0x80) +#define MCF_PAD_PAR_PSC3_PAR_CTS3_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC2 */ +#define MCF_PAD_PAR_PSC2_PAR_TXD2 (0x4) +#define MCF_PAD_PAR_PSC2_PAR_RXD2 (0x8) +#define MCF_PAD_PAR_PSC2_PAR_RTS2(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC2_PAR_RTS2_GPIO (0) +#define MCF_PAD_PAR_PSC2_PAR_RTS2_FSYNC (0x20) +#define MCF_PAD_PAR_PSC2_PAR_RTS2_RTS (0x30) +#define MCF_PAD_PAR_PSC2_PAR_CTS2(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC2_PAR_CTS2_GPIO (0) +#define MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK (0x80) +#define MCF_PAD_PAR_PSC2_PAR_CTS2_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC1 */ +#define MCF_PAD_PAR_PSC1_PAR_TXD1 (0x4) +#define MCF_PAD_PAR_PSC1_PAR_RXD1 (0x8) +#define MCF_PAD_PAR_PSC1_PAR_RTS1(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC1_PAR_RTS1_GPIO (0) +#define MCF_PAD_PAR_PSC1_PAR_RTS1_FSYNC (0x20) +#define MCF_PAD_PAR_PSC1_PAR_RTS1_RTS (0x30) +#define MCF_PAD_PAR_PSC1_PAR_CTS1(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC1_PAR_CTS1_GPIO (0) +#define MCF_PAD_PAR_PSC1_PAR_CTS1_BCLK (0x80) +#define MCF_PAD_PAR_PSC1_PAR_CTS1_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC0 */ +#define MCF_PAD_PAR_PSC0_PAR_TXD0 (0x4) +#define MCF_PAD_PAR_PSC0_PAR_RXD0 (0x8) +#define MCF_PAD_PAR_PSC0_PAR_RTS0(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC0_PAR_RTS0_GPIO (0) +#define MCF_PAD_PAR_PSC0_PAR_RTS0_FSYNC (0x20) +#define MCF_PAD_PAR_PSC0_PAR_RTS0_RTS (0x30) +#define MCF_PAD_PAR_PSC0_PAR_CTS0(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC0_PAR_CTS0_GPIO (0) +#define MCF_PAD_PAR_PSC0_PAR_CTS0_BCLK (0x80) +#define MCF_PAD_PAR_PSC0_PAR_CTS0_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_DSPI */ +#define MCF_PAD_PAR_DSPI_PAR_SOUT(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_DSPI_PAR_SOUT_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_SOUT_TXD (0x2) +#define MCF_PAD_PAR_DSPI_PAR_SOUT_SOUT (0x3) +#define MCF_PAD_PAR_DSPI_PAR_SIN(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_DSPI_PAR_SIN_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_SIN_RXD (0x8) +#define MCF_PAD_PAR_DSPI_PAR_SIN_SIN (0xC) +#define MCF_PAD_PAR_DSPI_PAR_SCK(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_DSPI_PAR_SCK_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_SCK_BCLK (0x10) +#define MCF_PAD_PAR_DSPI_PAR_SCK_CTS (0x20) +#define MCF_PAD_PAR_DSPI_PAR_SCK_SCK (0x30) +#define MCF_PAD_PAR_DSPI_PAR_CS0(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_DSPI_PAR_CS0_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_CS0_FSYNC (0x40) +#define MCF_PAD_PAR_DSPI_PAR_CS0_RTS (0x80) +#define MCF_PAD_PAR_DSPI_PAR_CS0_DSPICS0 (0xC0) +#define MCF_PAD_PAR_DSPI_PAR_CS2(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_DSPI_PAR_CS2_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_CS2_TOUT2 (0x200) +#define MCF_PAD_PAR_DSPI_PAR_CS2_DSPICS2 (0x300) +#define MCF_PAD_PAR_DSPI_PAR_CS3(x) (((x)&0x3)<<0xA) +#define MCF_PAD_PAR_DSPI_PAR_CS3_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_CS3_TOUT3 (0x800) +#define MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3 (0xC00) +#define MCF_PAD_PAR_DSPI_PAR_CS5 (0x1000) + +/* Bit definitions and macros for MCF_PAD_PAR_TIMER */ +#define MCF_PAD_PAR_TIMER_PAR_TOUT2 (0x1) +#define MCF_PAD_PAR_TIMER_PAR_TIN2(x) (((x)&0x3)<<0x1) +#define MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2 (0x4) +#define MCF_PAD_PAR_TIMER_PAR_TIN2_TIN2 (0x6) +#define MCF_PAD_PAR_TIMER_PAR_TOUT3 (0x8) +#define MCF_PAD_PAR_TIMER_PAR_TIN3(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_TIMER_PAR_TIN3_IRQ3 (0x20) +#define MCF_PAD_PAR_TIMER_PAR_TIN3_TIN3 (0x30) + + +#endif /* __MCF5475_PAD_H__ */ diff --git a/tos/vmem_test/include/MCF5475_PCI.h b/tos/vmem_test/include/MCF5475_PCI.h new file mode 100644 index 0000000..3eb3341 --- /dev/null +++ b/tos/vmem_test/include/MCF5475_PCI.h @@ -0,0 +1,376 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PCI_H__ +#define __MCF5475_PCI_H__ + + +/********************************************************************* +* +* PCI Bus Controller (PCI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PCI_PCIIDR (*(volatile uint32_t*)(&_MBAR[0xB00])) +#define MCF_PCI_PCISCR (*(volatile uint32_t*)(&_MBAR[0xB04])) +#define MCF_PCI_PCICCRIR (*(volatile uint32_t*)(&_MBAR[0xB08])) +#define MCF_PCI_PCICR1 (*(volatile uint32_t*)(&_MBAR[0xB0C])) +#define MCF_PCI_PCIBAR0 (*(volatile uint32_t*)(&_MBAR[0xB10])) +#define MCF_PCI_PCIBAR1 (*(volatile uint32_t*)(&_MBAR[0xB14])) +#define MCF_PCI_PCICCPR (*(volatile uint32_t*)(&_MBAR[0xB28])) +#define MCF_PCI_PCISID (*(volatile uint32_t*)(&_MBAR[0xB2C])) +#define MCF_PCI_PCICR2 (*(volatile uint32_t*)(&_MBAR[0xB3C])) +#define MCF_PCI_PCIGSCR (*(volatile uint32_t*)(&_MBAR[0xB60])) +#define MCF_PCI_PCITBATR0 (*(volatile uint32_t*)(&_MBAR[0xB64])) +#define MCF_PCI_PCITBATR1 (*(volatile uint32_t*)(&_MBAR[0xB68])) +#define MCF_PCI_PCITCR (*(volatile uint32_t*)(&_MBAR[0xB6C])) +#define MCF_PCI_PCIIW0BTAR (*(volatile uint32_t*)(&_MBAR[0xB70])) +#define MCF_PCI_PCIIW1BTAR (*(volatile uint32_t*)(&_MBAR[0xB74])) +#define MCF_PCI_PCIIW2BTAR (*(volatile uint32_t*)(&_MBAR[0xB78])) +#define MCF_PCI_PCIIWCR (*(volatile uint32_t*)(&_MBAR[0xB80])) +#define MCF_PCI_PCIICR (*(volatile uint32_t*)(&_MBAR[0xB84])) +#define MCF_PCI_PCIISR (*(volatile uint32_t*)(&_MBAR[0xB88])) +#define MCF_PCI_PCICAR (*(volatile uint32_t*)(&_MBAR[0xBF8])) +#define MCF_PCI_PCITPSR (*(volatile uint32_t*)(&_MBAR[0x8400])) +#define MCF_PCI_PCITSAR (*(volatile uint32_t*)(&_MBAR[0x8404])) +#define MCF_PCI_PCITTCR (*(volatile uint32_t*)(&_MBAR[0x8408])) +#define MCF_PCI_PCITER (*(volatile uint32_t*)(&_MBAR[0x840C])) +#define MCF_PCI_PCITNAR (*(volatile uint32_t*)(&_MBAR[0x8410])) +#define MCF_PCI_PCITLWR (*(volatile uint32_t*)(&_MBAR[0x8414])) +#define MCF_PCI_PCITDCR (*(volatile uint32_t*)(&_MBAR[0x8418])) +#define MCF_PCI_PCITSR (*(volatile uint32_t*)(&_MBAR[0x841C])) +#define MCF_PCI_PCITFDR (*(volatile uint32_t*)(&_MBAR[0x8440])) +#define MCF_PCI_PCITFSR (*(volatile uint32_t*)(&_MBAR[0x8444])) +#define MCF_PCI_PCITFCR (*(volatile uint32_t*)(&_MBAR[0x8448])) +#define MCF_PCI_PCITFAR (*(volatile uint32_t*)(&_MBAR[0x844C])) +#define MCF_PCI_PCITFRPR (*(volatile uint32_t*)(&_MBAR[0x8450])) +#define MCF_PCI_PCITFWPR (*(volatile uint32_t*)(&_MBAR[0x8454])) +#define MCF_PCI_PCIRPSR (*(volatile uint32_t*)(&_MBAR[0x8480])) +#define MCF_PCI_PCIRSAR (*(volatile uint32_t*)(&_MBAR[0x8484])) +#define MCF_PCI_PCIRTCR (*(volatile uint32_t*)(&_MBAR[0x8488])) +#define MCF_PCI_PCIRER (*(volatile uint32_t*)(&_MBAR[0x848C])) +#define MCF_PCI_PCIRNAR (*(volatile uint32_t*)(&_MBAR[0x8490])) +#define MCF_PCI_PCIRDCR (*(volatile uint32_t*)(&_MBAR[0x8498])) +#define MCF_PCI_PCIRSR (*(volatile uint32_t*)(&_MBAR[0x849C])) +#define MCF_PCI_PCIRFDR (*(volatile uint32_t*)(&_MBAR[0x84C0])) +#define MCF_PCI_PCIRFSR (*(volatile uint32_t*)(&_MBAR[0x84C4])) +#define MCF_PCI_PCIRFCR (*(volatile uint32_t*)(&_MBAR[0x84C8])) +#define MCF_PCI_PCIRFAR (*(volatile uint32_t*)(&_MBAR[0x84CC])) +#define MCF_PCI_PCIRFRPR (*(volatile uint32_t*)(&_MBAR[0x84D0])) +#define MCF_PCI_PCIRFWPR (*(volatile uint32_t*)(&_MBAR[0x84D4])) + + +/* Bit definitions and macros for MCF_PCI_PCIIDR */ +#define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCISCR */ +#define MCF_PCI_PCISCR_IO (0x1) +#define MCF_PCI_PCISCR_M (0x2) +#define MCF_PCI_PCISCR_B (0x4) +#define MCF_PCI_PCISCR_SP (0x8) +#define MCF_PCI_PCISCR_MW (0x10) +#define MCF_PCI_PCISCR_V (0x20) +#define MCF_PCI_PCISCR_PER (0x40) +#define MCF_PCI_PCISCR_ST (0x80) +#define MCF_PCI_PCISCR_S (0x100) +#define MCF_PCI_PCISCR_F (0x200) +#define MCF_PCI_PCISCR_C (0x100000) +#define MCF_PCI_PCISCR_66M (0x200000) +#define MCF_PCI_PCISCR_R (0x400000) +#define MCF_PCI_PCISCR_FC (0x800000) +#define MCF_PCI_PCISCR_DP (0x1000000) +#define MCF_PCI_PCISCR_DT(x) (((x)&0x3)<<0x19) +#define MCF_PCI_PCISCR_TS (0x8000000) +#define MCF_PCI_PCISCR_TR (0x10000000) +#define MCF_PCI_PCISCR_MA (0x20000000) +#define MCF_PCI_PCISCR_SE (0x40000000) +#define MCF_PCI_PCISCR_PE (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCICCRIR */ +#define MCF_PCI_PCICCRIR_REVISIONID(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0xFFFFFF)<<0x8) + +/* Bit definitions and macros for MCF_PCI_PCICR1 */ +#define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICR1_BIST(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIBAR0 */ +#define MCF_PCI_PCIBAR0_IOM (0x1) +#define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x3)<<0x1) +#define MCF_PCI_PCIBAR0_PREF (0x8) +#define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x3FFF)<<0x12) + +/* Bit definitions and macros for MCF_PCI_PCIBAR1 */ +#define MCF_PCI_PCIBAR1_IOM (0x1) +#define MCF_PCI_PCIBAR1_RANGE(x) (((x)&0x3)<<0x1) +#define MCF_PCI_PCIBAR1_PREF (0x8) +#define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_PCI_PCICCPR */ +#define MCF_PCI_PCICCPR_PCICCP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCISID */ +#define MCF_PCI_PCISID_VENDORID(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCICR2 */ +#define MCF_PCI_PCICR2_INTLINE(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICR2_INTPIN(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCICR2_MINGNT(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIGSCR */ +#define MCF_PCI_PCIGSCR_PR (0x1) +#define MCF_PCI_PCIGSCR_SEE (0x1000) +#define MCF_PCI_PCIGSCR_PEE (0x2000) +#define MCF_PCI_PCIGSCR_CLKINRESERVED(x) (((x)&0x7)<<0x10) +#define MCF_PCI_PCIGSCR_XLB2CLKIN(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCIGSCR_SE (0x10000000) +#define MCF_PCI_PCIGSCR_PE (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCITBATR0 */ +#define MCF_PCI_PCITBATR0_EN (0x1) +#define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x3FFF)<<0x12) + +/* Bit definitions and macros for MCF_PCI_PCITBATR1 */ +#define MCF_PCI_PCITBATR1_EN (0x1) +#define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_PCI_PCITCR */ +#define MCF_PCI_PCITCR_P (0x10000) +#define MCF_PCI_PCITCR_LD (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */ +#define MCF_PCI_PCIIW0BTAR_WTA0(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW0BTAR_WAM0(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW0BTAR_WBA0(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */ +#define MCF_PCI_PCIIW1BTAR_WTA1(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW1BTAR_WAM1(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW1BTAR_WBA1(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */ +#define MCF_PCI_PCIIW2BTAR_WTA2(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW2BTAR_WAM2(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW2BTAR_WBA2(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIWCR */ +#define MCF_PCI_PCIIWCR_WINCTRL2_E (0x100) +#define MCF_PCI_PCIIWCR_WINCTRL2_PRC(x) (((x)&0x3)<<0x9) +#define MCF_PCI_PCIIWCR_WINCTRL2_IOM (0x800) +#define MCF_PCI_PCIIWCR_WINCTRL1_E (0x10000) +#define MCF_PCI_PCIIWCR_WINCTRL1_PRC(x) (((x)&0x3)<<0x11) +#define MCF_PCI_PCIIWCR_WINCTRL1_IOM (0x80000) +#define MCF_PCI_PCIIWCR_WINCTRL0_E (0x1000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_PRC(x) (((x)&0x3)<<0x19) +#define MCF_PCI_PCIIWCR_WINCTRL0_IOM (0x8000000) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x100) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x300) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x500) +#define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x900) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x10000) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x30000) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x50000) +#define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x90000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x1000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x3000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x5000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x9000000) + +/* Bit definitions and macros for MCF_PCI_PCIICR */ +#define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCIICR_TAE (0x1000000) +#define MCF_PCI_PCIICR_IAE (0x2000000) +#define MCF_PCI_PCIICR_REE (0x4000000) + +/* Bit definitions and macros for MCF_PCI_PCIISR */ +#define MCF_PCI_PCIISR_TA (0x1000000) +#define MCF_PCI_PCIISR_IA (0x2000000) +#define MCF_PCI_PCIISR_RE (0x4000000) + +/* Bit definitions and macros for MCF_PCI_PCICAR */ +#define MCF_PCI_PCICAR_DWORD(x) (((x)&0x3F)<<0x2) +#define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x1F)<<0xB) +#define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICAR_E (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITPSR */ +#define MCF_PCI_PCITPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCITSAR */ +#define MCF_PCI_PCITSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITTCR */ +#define MCF_PCI_PCITTCR_DI (0x1) +#define MCF_PCI_PCITTCR_W (0x10) +#define MCF_PCI_PCITTCR_MAXBEATS(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCITTCR_MAXRETRY(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCITTCR_PCICMD(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCITER */ +#define MCF_PCI_PCITER_NE (0x10000) +#define MCF_PCI_PCITER_IAE (0x20000) +#define MCF_PCI_PCITER_TAE (0x40000) +#define MCF_PCI_PCITER_RE (0x80000) +#define MCF_PCI_PCITER_SE (0x100000) +#define MCF_PCI_PCITER_FEE (0x200000) +#define MCF_PCI_PCITER_ME (0x1000000) +#define MCF_PCI_PCITER_BE (0x8000000) +#define MCF_PCI_PCITER_CM (0x10000000) +#define MCF_PCI_PCITER_RF (0x40000000) +#define MCF_PCI_PCITER_RC (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITNAR */ +#define MCF_PCI_PCITNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITLWR */ +#define MCF_PCI_PCITLWR_LASTWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITDCR */ +#define MCF_PCI_PCITDCR_PKTSDONE(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCITDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCITSR */ +#define MCF_PCI_PCITSR_IA (0x10000) +#define MCF_PCI_PCITSR_TA (0x20000) +#define MCF_PCI_PCITSR_RE (0x40000) +#define MCF_PCI_PCITSR_SE (0x80000) +#define MCF_PCI_PCITSR_FE (0x100000) +#define MCF_PCI_PCITSR_BE1 (0x200000) +#define MCF_PCI_PCITSR_BE2 (0x400000) +#define MCF_PCI_PCITSR_BE3 (0x800000) +#define MCF_PCI_PCITSR_NT (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCITFDR */ +#define MCF_PCI_PCITFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFSR */ +#define MCF_PCI_PCITFSR_EMPTY (0x10000) +#define MCF_PCI_PCITFSR_ALARM (0x20000) +#define MCF_PCI_PCITFSR_FULL (0x40000) +#define MCF_PCI_PCITFSR_FR (0x80000) +#define MCF_PCI_PCITFSR_OF (0x100000) +#define MCF_PCI_PCITFSR_UF (0x200000) +#define MCF_PCI_PCITFSR_RXW (0x400000) +#define MCF_PCI_PCITFSR_FAE (0x800000) +#define MCF_PCI_PCITFSR_TXW (0x40000000) +#define MCF_PCI_PCITFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITFCR */ +#define MCF_PCI_PCITFCR_TXW_MASK (0x40000) +#define MCF_PCI_PCITFCR_OF_MASK (0x80000) +#define MCF_PCI_PCITFCR_UF_MASK (0x100000) +#define MCF_PCI_PCITFCR_RXW_MASK (0x200000) +#define MCF_PCI_PCITFCR_FAE_MASK (0x400000) +#define MCF_PCI_PCITFCR_IP_MASK (0x800000) +#define MCF_PCI_PCITFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCITFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCITFAR */ +#define MCF_PCI_PCITFAR_ALARM(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFRPR */ +#define MCF_PCI_PCITFRPR_READPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFWPR */ +#define MCF_PCI_PCITFWPR_WRITEPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRPSR */ +#define MCF_PCI_PCIRPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCIRSAR */ +#define MCF_PCI_PCIRSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRTCR */ +#define MCF_PCI_PCIRTCR_DI (0x1) +#define MCF_PCI_PCIRTCR_W (0x10) +#define MCF_PCI_PCIRTCR_MAXBEATS(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCIRTCR_FB (0x1000) +#define MCF_PCI_PCIRTCR_MAXRETRY(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIRTCR_PCICMD(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIRER */ +#define MCF_PCI_PCIRER_NE (0x10000) +#define MCF_PCI_PCIRER_IAE (0x20000) +#define MCF_PCI_PCIRER_TAE (0x40000) +#define MCF_PCI_PCIRER_RE (0x80000) +#define MCF_PCI_PCIRER_SE (0x100000) +#define MCF_PCI_PCIRER_FEE (0x200000) +#define MCF_PCI_PCIRER_ME (0x1000000) +#define MCF_PCI_PCIRER_BE (0x8000000) +#define MCF_PCI_PCIRER_CM (0x10000000) +#define MCF_PCI_PCIRER_FE (0x20000000) +#define MCF_PCI_PCIRER_RF (0x40000000) +#define MCF_PCI_PCIRER_RC (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCIRNAR */ +#define MCF_PCI_PCIRNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRDCR */ +#define MCF_PCI_PCIRDCR_PKTSDONE(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCIRDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCIRSR */ +#define MCF_PCI_PCIRSR_IA (0x10000) +#define MCF_PCI_PCIRSR_TA (0x20000) +#define MCF_PCI_PCIRSR_RE (0x40000) +#define MCF_PCI_PCIRSR_SE (0x80000) +#define MCF_PCI_PCIRSR_FE (0x100000) +#define MCF_PCI_PCIRSR_BE1 (0x200000) +#define MCF_PCI_PCIRSR_BE2 (0x400000) +#define MCF_PCI_PCIRSR_BE3 (0x800000) +#define MCF_PCI_PCIRSR_NT (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFDR */ +#define MCF_PCI_PCIRFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFSR */ +#define MCF_PCI_PCIRFSR_EMPTY (0x10000) +#define MCF_PCI_PCIRFSR_ALARM (0x20000) +#define MCF_PCI_PCIRFSR_FULL (0x40000) +#define MCF_PCI_PCIRFSR_FR (0x80000) +#define MCF_PCI_PCIRFSR_OF (0x100000) +#define MCF_PCI_PCIRFSR_UF (0x200000) +#define MCF_PCI_PCIRFSR_RXW (0x400000) +#define MCF_PCI_PCIRFSR_FAE (0x800000) +#define MCF_PCI_PCIRFSR_TXW (0x40000000) +#define MCF_PCI_PCIRFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFCR */ +#define MCF_PCI_PCIRFCR_TXW_MASK (0x40000) +#define MCF_PCI_PCIRFCR_OF_MASK (0x80000) +#define MCF_PCI_PCIRFCR_UF_MASK (0x100000) +#define MCF_PCI_PCIRFCR_RXW_MASK (0x200000) +#define MCF_PCI_PCIRFCR_FAE_MASK (0x400000) +#define MCF_PCI_PCIRFCR_IP_MASK (0x800000) +#define MCF_PCI_PCIRFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCIRFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFAR */ +#define MCF_PCI_PCIRFAR_ALARM(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFRPR */ +#define MCF_PCI_PCIRFRPR_READPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFWPR */ +#define MCF_PCI_PCIRFWPR_WRITEPTR(x) (((x)&0x7F)<<0) + + +#endif /* __MCF5475_PCI_H__ */ diff --git a/tos/vmem_test/include/MCF5475_PCIARB.h b/tos/vmem_test/include/MCF5475_PCIARB.h new file mode 100644 index 0000000..9e8c05b --- /dev/null +++ b/tos/vmem_test/include/MCF5475_PCIARB.h @@ -0,0 +1,43 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PCIARB_H__ +#define __MCF5475_PCIARB_H__ + + +/********************************************************************* +* +* PCI Bus Arbiter Module (PCIARB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PCIARB_PACR (*(volatile uint32_t*)(&_MBAR[0xC00])) +#define MCF_PCIARB_PASR (*(volatile uint32_t*)(&_MBAR[0xC04])) + + +/* Bit definitions and macros for MCF_PCIARB_PACR */ +#define MCF_PCIARB_PACR_INTMPRI (0x1) +#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x1F)<<0x1) +#define MCF_PCIARB_PACR_INTMINTEN (0x10000) +#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x1F)<<0x11) +#define MCF_PCIARB_PACR_DS (0x80000000) + +/* Bit definitions and macros for MCF_PCIARB_PASR */ +#define MCF_PCIARB_PASR_ITLMBK (0x10000) +#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x1F)<<0x11) + + +#endif /* __MCF5475_PCIARB_H__ */ diff --git a/tos/vmem_test/include/MCF5475_PSC.h b/tos/vmem_test/include/MCF5475_PSC.h new file mode 100644 index 0000000..ffa9f3e --- /dev/null +++ b/tos/vmem_test/include/MCF5475_PSC.h @@ -0,0 +1,527 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PSC_H__ +#define __MCF5475_PSC_H__ + + +/********************************************************************* +* +* Programmable Serial Controller (PSC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PSC0_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8600])) +#define MCF_PSC0_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8600])) +#define MCF_PSC0_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8604])) +#define MCF_PSC0_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8604])) +#define MCF_PSC0_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8608])) +#define MCF_PSC0_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8610])) +#define MCF_PSC0_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8610])) +#define MCF_PSC0_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8614])) +#define MCF_PSC0_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8614])) +#define MCF_PSC0_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8618])) +#define MCF_PSC0_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x861C])) +#define MCF_PSC0_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8634])) +#define MCF_PSC0_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8638])) +#define MCF_PSC0_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x863C])) +#define MCF_PSC0_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8640])) +#define MCF_PSC0_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8644])) +#define MCF_PSC0_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8648])) +#define MCF_PSC0_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x864C])) +#define MCF_PSC0_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8650])) +#define MCF_PSC0_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8654])) +#define MCF_PSC0_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8658])) +#define MCF_PSC0_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x865C])) +#define MCF_PSC0_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8660])) +#define MCF_PSC0_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8664])) +#define MCF_PSC0_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8668])) +#define MCF_PSC0_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x866E])) +#define MCF_PSC0_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8672])) +#define MCF_PSC0_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8676])) +#define MCF_PSC0_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x867A])) +#define MCF_PSC0_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x867E])) +#define MCF_PSC0_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8680])) +#define MCF_PSC0_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8684])) +#define MCF_PSC0_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8688])) +#define MCF_PSC0_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x868E])) +#define MCF_PSC0_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8692])) +#define MCF_PSC0_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8696])) +#define MCF_PSC0_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x869A])) +#define MCF_PSC0_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x869E])) + +#define MCF_PSC1_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8700])) +#define MCF_PSC1_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8700])) +#define MCF_PSC1_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8704])) +#define MCF_PSC1_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8704])) +#define MCF_PSC1_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8708])) +#define MCF_PSC1_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8710])) +#define MCF_PSC1_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8710])) +#define MCF_PSC1_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8714])) +#define MCF_PSC1_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8714])) +#define MCF_PSC1_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8718])) +#define MCF_PSC1_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x871C])) +#define MCF_PSC1_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8734])) +#define MCF_PSC1_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8738])) +#define MCF_PSC1_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x873C])) +#define MCF_PSC1_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8740])) +#define MCF_PSC1_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8744])) +#define MCF_PSC1_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8748])) +#define MCF_PSC1_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x874C])) +#define MCF_PSC1_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8750])) +#define MCF_PSC1_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8754])) +#define MCF_PSC1_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8758])) +#define MCF_PSC1_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x875C])) +#define MCF_PSC1_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8760])) +#define MCF_PSC1_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8764])) +#define MCF_PSC1_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8768])) +#define MCF_PSC1_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x876E])) +#define MCF_PSC1_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8772])) +#define MCF_PSC1_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8776])) +#define MCF_PSC1_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x877A])) +#define MCF_PSC1_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x877E])) +#define MCF_PSC1_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8780])) +#define MCF_PSC1_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8784])) +#define MCF_PSC1_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8788])) +#define MCF_PSC1_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x878E])) +#define MCF_PSC1_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8792])) +#define MCF_PSC1_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8796])) +#define MCF_PSC1_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x879A])) +#define MCF_PSC1_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x879E])) + +#define MCF_PSC2_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8800])) +#define MCF_PSC2_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8800])) +#define MCF_PSC2_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8804])) +#define MCF_PSC2_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8804])) +#define MCF_PSC2_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8808])) +#define MCF_PSC2_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8810])) +#define MCF_PSC2_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8810])) +#define MCF_PSC2_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8814])) +#define MCF_PSC2_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8814])) +#define MCF_PSC2_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8818])) +#define MCF_PSC2_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x881C])) +#define MCF_PSC2_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8834])) +#define MCF_PSC2_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8838])) +#define MCF_PSC2_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x883C])) +#define MCF_PSC2_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8840])) +#define MCF_PSC2_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8844])) +#define MCF_PSC2_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8848])) +#define MCF_PSC2_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x884C])) +#define MCF_PSC2_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8850])) +#define MCF_PSC2_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8854])) +#define MCF_PSC2_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8858])) +#define MCF_PSC2_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x885C])) +#define MCF_PSC2_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8860])) +#define MCF_PSC2_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8864])) +#define MCF_PSC2_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8868])) +#define MCF_PSC2_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x886E])) +#define MCF_PSC2_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8872])) +#define MCF_PSC2_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8876])) +#define MCF_PSC2_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x887A])) +#define MCF_PSC2_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x887E])) +#define MCF_PSC2_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8880])) +#define MCF_PSC2_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8884])) +#define MCF_PSC2_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8888])) +#define MCF_PSC2_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x888E])) +#define MCF_PSC2_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8892])) +#define MCF_PSC2_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8896])) +#define MCF_PSC2_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x889A])) +#define MCF_PSC2_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x889E])) + +#define MCF_PSC3_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8900])) +#define MCF_PSC3_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8900])) +#define MCF_PSC3_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8904])) +#define MCF_PSC3_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8904])) +#define MCF_PSC3_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8908])) +#define MCF_PSC3_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8910])) +#define MCF_PSC3_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8910])) +#define MCF_PSC3_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8914])) +#define MCF_PSC3_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8914])) +#define MCF_PSC3_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8918])) +#define MCF_PSC3_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x891C])) +#define MCF_PSC3_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8934])) +#define MCF_PSC3_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8938])) +#define MCF_PSC3_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x893C])) +#define MCF_PSC3_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8940])) +#define MCF_PSC3_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8944])) +#define MCF_PSC3_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8948])) +#define MCF_PSC3_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x894C])) +#define MCF_PSC3_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8950])) +#define MCF_PSC3_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8954])) +#define MCF_PSC3_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8958])) +#define MCF_PSC3_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x895C])) +#define MCF_PSC3_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8960])) +#define MCF_PSC3_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8964])) +#define MCF_PSC3_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8968])) +#define MCF_PSC3_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x896E])) +#define MCF_PSC3_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8972])) +#define MCF_PSC3_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8976])) +#define MCF_PSC3_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x897A])) +#define MCF_PSC3_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x897E])) +#define MCF_PSC3_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8980])) +#define MCF_PSC3_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8984])) +#define MCF_PSC3_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8988])) +#define MCF_PSC3_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x898E])) +#define MCF_PSC3_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8992])) +#define MCF_PSC3_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8996])) +#define MCF_PSC3_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x899A])) +#define MCF_PSC3_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x899E])) + +#define MCF_PSC_PSCMR(x) (*(volatile uint8_t *)(&_MBAR[0x8600 + ((x)*0x100)])) +#define MCF_PSC_PSCCSR(x) (*(volatile uint8_t *)(&_MBAR[0x8604 + ((x)*0x100)])) +#define MCF_PSC_PSCSR(x) (*(volatile uint16_t*)(&_MBAR[0x8604 + ((x)*0x100)])) +#define MCF_PSC_PSCCR(x) (*(volatile uint8_t *)(&_MBAR[0x8608 + ((x)*0x100)])) +#define MCF_PSC_PSCRB_8BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_8BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCRB_16BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_16BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCRB_AC97(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_AC97(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCIPCR(x) (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)])) +#define MCF_PSC_PSCACR(x) (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)])) +#define MCF_PSC_PSCIMR(x) (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)])) +#define MCF_PSC_PSCISR(x) (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)])) +#define MCF_PSC_PSCCTUR(x) (*(volatile uint8_t *)(&_MBAR[0x8618 + ((x)*0x100)])) +#define MCF_PSC_PSCCTLR(x) (*(volatile uint8_t *)(&_MBAR[0x861C + ((x)*0x100)])) +#define MCF_PSC_PSCIP(x) (*(volatile uint8_t *)(&_MBAR[0x8634 + ((x)*0x100)])) +#define MCF_PSC_PSCOPSET(x) (*(volatile uint8_t *)(&_MBAR[0x8638 + ((x)*0x100)])) +#define MCF_PSC_PSCOPRESET(x) (*(volatile uint8_t *)(&_MBAR[0x863C + ((x)*0x100)])) +#define MCF_PSC_PSCSICR(x) (*(volatile uint8_t *)(&_MBAR[0x8640 + ((x)*0x100)])) +#define MCF_PSC_PSCIRCR1(x) (*(volatile uint8_t *)(&_MBAR[0x8644 + ((x)*0x100)])) +#define MCF_PSC_PSCIRCR2(x) (*(volatile uint8_t *)(&_MBAR[0x8648 + ((x)*0x100)])) +#define MCF_PSC_PSCIRSDR(x) (*(volatile uint8_t *)(&_MBAR[0x864C + ((x)*0x100)])) +#define MCF_PSC_PSCIRMDR(x) (*(volatile uint8_t *)(&_MBAR[0x8650 + ((x)*0x100)])) +#define MCF_PSC_PSCIRFDR(x) (*(volatile uint8_t *)(&_MBAR[0x8654 + ((x)*0x100)])) +#define MCF_PSC_PSCRFCNT(x) (*(volatile uint16_t*)(&_MBAR[0x8658 + ((x)*0x100)])) +#define MCF_PSC_PSCTFCNT(x) (*(volatile uint16_t*)(&_MBAR[0x865C + ((x)*0x100)])) +#define MCF_PSC_PSCRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8660 + ((x)*0x100)])) +#define MCF_PSC_PSCRFSR(x) (*(volatile uint16_t*)(&_MBAR[0x8664 + ((x)*0x100)])) +#define MCF_PSC_PSCRFCR(x) (*(volatile uint32_t*)(&_MBAR[0x8668 + ((x)*0x100)])) +#define MCF_PSC_PSCRFAR(x) (*(volatile uint16_t*)(&_MBAR[0x866E + ((x)*0x100)])) +#define MCF_PSC_PSCRFRP(x) (*(volatile uint16_t*)(&_MBAR[0x8672 + ((x)*0x100)])) +#define MCF_PSC_PSCRFWP(x) (*(volatile uint16_t*)(&_MBAR[0x8676 + ((x)*0x100)])) +#define MCF_PSC_PSCRLRFP(x) (*(volatile uint16_t*)(&_MBAR[0x867A + ((x)*0x100)])) +#define MCF_PSC_PSCRLWFP(x) (*(volatile uint16_t*)(&_MBAR[0x867E + ((x)*0x100)])) +#define MCF_PSC_PSCTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8680 + ((x)*0x100)])) +#define MCF_PSC_PSCTFSR(x) (*(volatile uint16_t*)(&_MBAR[0x8684 + ((x)*0x100)])) +#define MCF_PSC_PSCTFCR(x) (*(volatile uint32_t*)(&_MBAR[0x8688 + ((x)*0x100)])) +#define MCF_PSC_PSCTFAR(x) (*(volatile uint16_t*)(&_MBAR[0x868E + ((x)*0x100)])) +#define MCF_PSC_PSCTFRP(x) (*(volatile uint16_t*)(&_MBAR[0x8692 + ((x)*0x100)])) +#define MCF_PSC_PSCTFWP(x) (*(volatile uint16_t*)(&_MBAR[0x8696 + ((x)*0x100)])) +#define MCF_PSC_PSCTLRFP(x) (*(volatile uint16_t*)(&_MBAR[0x869A + ((x)*0x100)])) +#define MCF_PSC_PSCTLWFP(x) (*(volatile uint16_t*)(&_MBAR[0x869E + ((x)*0x100)])) + +/* Bit definitions and macros for MCF_PSC_PSCMR */ +#define MCF_PSC_PSCMR_SB(x) (((x)&0xF)<<0) +#define MCF_PSC_PSCMR_TXCTS (0x10) +#define MCF_PSC_PSCMR_TXRTS (0x20) +#define MCF_PSC_PSCMR_CM(x) (((x)&0x3)<<0x6) +#define MCF_PSC_PSCMR_CM_NORMAL (0) +#define MCF_PSC_PSCMR_CM_ECHO (0x40) +#define MCF_PSC_PSCMR_CM_LOCAL_LOOP (0x80) +#define MCF_PSC_PSCMR_CM_REMOTE_LOOP (0xC0) +#define MCF_PSC_PSCMR_SB_STOP_BITS_1 (0x7) +#define MCF_PSC_PSCMR_SB_STOP_BITS_15 (0x8) +#define MCF_PSC_PSCMR_SB_STOP_BITS_2 (0xF) +#define MCF_PSC_PSCMR_PM_MULTI_ADDR (0x1C) +#define MCF_PSC_PSCMR_PM_MULTI_DATA (0x18) +#define MCF_PSC_PSCMR_PM_NONE (0x10) +#define MCF_PSC_PSCMR_PM_FORCE_HI (0xC) +#define MCF_PSC_PSCMR_PM_FORCE_LO (0x8) +#define MCF_PSC_PSCMR_PM_ODD (0x4) +#define MCF_PSC_PSCMR_PM_EVEN (0) +#define MCF_PSC_PSCMR_BC(x) (((x)&0x3)<<0) +#define MCF_PSC_PSCMR_BC_5 (0) +#define MCF_PSC_PSCMR_BC_6 (0x1) +#define MCF_PSC_PSCMR_BC_7 (0x2) +#define MCF_PSC_PSCMR_BC_8 (0x3) +#define MCF_PSC_PSCMR_PT (0x4) +#define MCF_PSC_PSCMR_PM(x) (((x)&0x3)<<0x3) +#define MCF_PSC_PSCMR_ERR (0x20) +#define MCF_PSC_PSCMR_RXIRQ_FU (0x40) +#define MCF_PSC_PSCMR_RXRTS (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCCSR */ +#define MCF_PSC_PSCCSR_TCSEL(x) (((x)&0xF)<<0) +#define MCF_PSC_PSCCSR_RCSEL(x) (((x)&0xF)<<0x4) +#define MCF_PSC_PSCCSR_TCSEL_SYS_CLK (0x0D) +#define MCF_PSC_PSCCSR_TCSEL_CTM16 (0x0E) +#define MCF_PSC_PSCCSR_TCSEL_CTM (0x0F) +#define MCF_PSC_PSCCSR_RCSEL_SYS_CLK (0xD0) +#define MCF_PSC_PSCCSR_RCSEL_CTM16 (0xE0) +#define MCF_PSC_PSCCSR_RCSEL_CTM (0xF0) + +/* Bit definitions and macros for MCF_PSC_PSCSR */ +#define MCF_PSC_PSCSR_ERR (0x40) +#define MCF_PSC_PSCSR_CDE_DEOF (0x80) +#define MCF_PSC_PSCSR_RXRDY (0x100) +#define MCF_PSC_PSCSR_FU (0x200) +#define MCF_PSC_PSCSR_TXRDY (0x400) +#define MCF_PSC_PSCSR_TXEMP_URERR (0x800) +#define MCF_PSC_PSCSR_OE (0x1000) +#define MCF_PSC_PSCSR_PE_CRCERR (0x2000) +#define MCF_PSC_PSCSR_FE_PHYERR (0x4000) +#define MCF_PSC_PSCSR_RB_NEOF (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCCR */ +#define MCF_PSC_PSCCR_RXC(x) (((x)&0x3)<<0) +#define MCF_PSC_PSCCR_RX_ENABLED (0x1) +#define MCF_PSC_PSCCR_RX_DISABLED (0x2) +#define MCF_PSC_PSCCR_TXC(x) (((x)&0x3)<<0x2) +#define MCF_PSC_PSCCR_TX_ENABLED (0x4) +#define MCF_PSC_PSCCR_TX_DISABLED (0x8) +#define MCF_PSC_PSCCR_MISC(x) (((x)&0x7)<<0x4) +#define MCF_PSC_PSCCR_NONE (0) +#define MCF_PSC_PSCCR_RESET_MR (0x10) +#define MCF_PSC_PSCCR_RESET_RX (0x20) +#define MCF_PSC_PSCCR_RESET_TX (0x30) +#define MCF_PSC_PSCCR_RESET_ERROR (0x40) +#define MCF_PSC_PSCCR_RESET_BKCHGINT (0x50) +#define MCF_PSC_PSCCR_START_BREAK (0x60) +#define MCF_PSC_PSCCR_STOP_BREAK (0x70) + +/* Bit definitions and macros for MCF_PSC_PSCRB_8BIT */ +#define MCF_PSC_PSCRB_8BIT_RB3(x) (((x)&0xFF)<<0) +#define MCF_PSC_PSCRB_8BIT_RB2(x) (((x)&0xFF)<<0x8) +#define MCF_PSC_PSCRB_8BIT_RB1(x) (((x)&0xFF)<<0x10) +#define MCF_PSC_PSCRB_8BIT_RB0(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PSC_PSCTB_8BIT */ +#define MCF_PSC_PSCTB_8BIT_TB3(x) (((x)&0xFF)<<0) +#define MCF_PSC_PSCTB_8BIT_TB2(x) (((x)&0xFF)<<0x8) +#define MCF_PSC_PSCTB_8BIT_TB1(x) (((x)&0xFF)<<0x10) +#define MCF_PSC_PSCTB_8BIT_TB0(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PSC_PSCRB_16BIT */ +#define MCF_PSC_PSCRB_16BIT_RB1(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCRB_16BIT_RB0(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PSC_PSCTB_16BIT */ +#define MCF_PSC_PSCTB_16BIT_TB1(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCTB_16BIT_TB0(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PSC_PSCRB_AC97 */ +#define MCF_PSC_PSCRB_AC97_SOF (0x800) +#define MCF_PSC_PSCRB_AC97_RB(x) (((x)&0xFFFFF)<<0xC) + +/* Bit definitions and macros for MCF_PSC_PSCTB_AC97 */ +#define MCF_PSC_PSCTB_AC97_TB(x) (((x)&0xFFFFF)<<0xC) + +/* Bit definitions and macros for MCF_PSC_PSCIPCR */ +#define MCF_PSC_PSCIPCR_RESERVED (0xC) +#define MCF_PSC_PSCIPCR_CTS (0xD) +#define MCF_PSC_PSCIPCR_D_CTS (0x1C) +#define MCF_PSC_PSCIPCR_SYNC (0x8C) + +/* Bit definitions and macros for MCF_PSC_PSCACR */ +#define MCF_PSC_PSCACR_IEC0 (0x1) + +/* Bit definitions and macros for MCF_PSC_PSCIMR */ +#define MCF_PSC_PSCIMR_ERR (0x40) +#define MCF_PSC_PSCIMR_DEOF (0x80) +#define MCF_PSC_PSCIMR_TXRDY (0x100) +#define MCF_PSC_PSCIMR_RXRDY_FU (0x200) +#define MCF_PSC_PSCIMR_DB (0x400) +#define MCF_PSC_PSCIMR_IPC (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCISR */ +#define MCF_PSC_PSCISR_ERR (0x40) +#define MCF_PSC_PSCISR_DEOF (0x80) +#define MCF_PSC_PSCISR_TXRDY (0x100) +#define MCF_PSC_PSCISR_RXRDY_FU (0x200) +#define MCF_PSC_PSCISR_DB (0x400) +#define MCF_PSC_PSCISR_IPC (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCCTUR */ +#define MCF_PSC_PSCCTUR_CT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCCTLR */ +#define MCF_PSC_PSCCTLR_CT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCIP */ +#define MCF_PSC_PSCIP_CTS (0x1) +#define MCF_PSC_PSCIP_TGL (0x40) +#define MCF_PSC_PSCIP_LPWR_B (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCOPSET */ +#define MCF_PSC_PSCOPSET_RTS (0x1) + +/* Bit definitions and macros for MCF_PSC_PSCOPRESET */ +#define MCF_PSC_PSCOPRESET_RTS (0x1) + +/* Bit definitions and macros for MCF_PSC_PSCSICR */ +#define MCF_PSC_PSCSICR_SIM(x) (((x)&0x7)<<0) +#define MCF_PSC_PSCSICR_SIM_UART (0) +#define MCF_PSC_PSCSICR_SIM_MODEM8 (0x1) +#define MCF_PSC_PSCSICR_SIM_MODEM16 (0x2) +#define MCF_PSC_PSCSICR_SIM_AC97 (0x3) +#define MCF_PSC_PSCSICR_SIM_SIR (0x4) +#define MCF_PSC_PSCSICR_SIM_MIR (0x5) +#define MCF_PSC_PSCSICR_SIM_FIR (0x6) +#define MCF_PSC_PSCSICR_SHDIR (0x10) +#define MCF_PSC_PSCSICR_DTS1 (0x20) +#define MCF_PSC_PSCSICR_AWR (0x40) +#define MCF_PSC_PSCSICR_ACRB (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCIRCR1 */ +#define MCF_PSC_PSCIRCR1_SPUL (0x1) +#define MCF_PSC_PSCIRCR1_SIPEN (0x2) +#define MCF_PSC_PSCIRCR1_FD (0x4) + +/* Bit definitions and macros for MCF_PSC_PSCIRCR2 */ +#define MCF_PSC_PSCIRCR2_NXTEOF (0x1) +#define MCF_PSC_PSCIRCR2_ABORT (0x2) +#define MCF_PSC_PSCIRCR2_SIPREQ (0x4) + +/* Bit definitions and macros for MCF_PSC_PSCIRSDR */ +#define MCF_PSC_PSCIRSDR_IRSTIM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCIRMDR */ +#define MCF_PSC_PSCIRMDR_M_FDIV(x) (((x)&0x7F)<<0) +#define MCF_PSC_PSCIRMDR_FREQ (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCIRFDR */ +#define MCF_PSC_PSCIRFDR_F_FDIV(x) (((x)&0xF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFCNT */ +#define MCF_PSC_PSCRFCNT_CNT(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFCNT */ +#define MCF_PSC_PSCTFCNT_CNT(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFDR */ +#define MCF_PSC_PSCRFDR_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFSR */ +#define MCF_PSC_PSCRFSR_EMT (0x1) +#define MCF_PSC_PSCRFSR_ALARM (0x2) +#define MCF_PSC_PSCRFSR_FU (0x4) +#define MCF_PSC_PSCRFSR_FRMRDY (0x8) +#define MCF_PSC_PSCRFSR_OF (0x10) +#define MCF_PSC_PSCRFSR_UF (0x20) +#define MCF_PSC_PSCRFSR_RXW (0x40) +#define MCF_PSC_PSCRFSR_FAE (0x80) +#define MCF_PSC_PSCRFSR_FRM(x) (((x)&0xF)<<0x8) +#define MCF_PSC_PSCRFSR_FRM_BYTE0 (0x800) +#define MCF_PSC_PSCRFSR_FRM_BYTE1 (0x400) +#define MCF_PSC_PSCRFSR_FRM_BYTE2 (0x200) +#define MCF_PSC_PSCRFSR_FRM_BYTE3 (0x100) +#define MCF_PSC_PSCRFSR_TAG(x) (((x)&0x3)<<0xC) +#define MCF_PSC_PSCRFSR_TXW (0x4000) +#define MCF_PSC_PSCRFSR_IP (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCRFCR */ +#define MCF_PSC_PSCRFCR_CNTR(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCRFCR_TXW_MSK (0x40000) +#define MCF_PSC_PSCRFCR_OF_MSK (0x80000) +#define MCF_PSC_PSCRFCR_UF_MSK (0x100000) +#define MCF_PSC_PSCRFCR_RXW_MSK (0x200000) +#define MCF_PSC_PSCRFCR_FAE_MSK (0x400000) +#define MCF_PSC_PSCRFCR_IP_MSK (0x800000) +#define MCF_PSC_PSCRFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PSC_PSCRFCR_FRMEN (0x8000000) +#define MCF_PSC_PSCRFCR_TIMER (0x10000000) + +/* Bit definitions and macros for MCF_PSC_PSCRFAR */ +#define MCF_PSC_PSCRFAR_ALARM(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFRP */ +#define MCF_PSC_PSCRFRP_READ(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFWP */ +#define MCF_PSC_PSCRFWP_WRITE(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRLRFP */ +#define MCF_PSC_PSCRLRFP_LRFP(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRLWFP */ +#define MCF_PSC_PSCRLWFP_LWFP(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFDR */ +#define MCF_PSC_PSCTFDR_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFSR */ +#define MCF_PSC_PSCTFSR_EMT (0x1) +#define MCF_PSC_PSCTFSR_ALARM (0x2) +#define MCF_PSC_PSCTFSR_FU (0x4) +#define MCF_PSC_PSCTFSR_FRMRDY (0x8) +#define MCF_PSC_PSCTFSR_OF (0x10) +#define MCF_PSC_PSCTFSR_UF (0x20) +#define MCF_PSC_PSCTFSR_RXW (0x40) +#define MCF_PSC_PSCTFSR_FAE (0x80) +#define MCF_PSC_PSCTFSR_FRM(x) (((x)&0xF)<<0x8) +#define MCF_PSC_PSCTFSR_FRM_BYTE0 (0x800) +#define MCF_PSC_PSCTFSR_FRM_BYTE1 (0x400) +#define MCF_PSC_PSCTFSR_FRM_BYTE2 (0x200) +#define MCF_PSC_PSCTFSR_FRM_BYTE3 (0x100) +#define MCF_PSC_PSCTFSR_TAG(x) (((x)&0x3)<<0xC) +#define MCF_PSC_PSCTFSR_TXW (0x4000) +#define MCF_PSC_PSCTFSR_IP (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCTFCR */ +#define MCF_PSC_PSCTFCR_CNTR(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCTFCR_TXW_MSK (0x40000) +#define MCF_PSC_PSCTFCR_OF_MSK (0x80000) +#define MCF_PSC_PSCTFCR_UF_MSK (0x100000) +#define MCF_PSC_PSCTFCR_RXW_MSK (0x200000) +#define MCF_PSC_PSCTFCR_FAE_MSK (0x400000) +#define MCF_PSC_PSCTFCR_IP_MSK (0x800000) +#define MCF_PSC_PSCTFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PSC_PSCTFCR_FRMEN (0x8000000) +#define MCF_PSC_PSCTFCR_TIMER (0x10000000) +#define MCF_PSC_PSCTFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PSC_PSCTFAR */ +#define MCF_PSC_PSCTFAR_ALARM(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFRP */ +#define MCF_PSC_PSCTFRP_READ(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFWP */ +#define MCF_PSC_PSCTFWP_WRITE(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTLRFP */ +#define MCF_PSC_PSCTLRFP_LRFP(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTLWFP */ +#define MCF_PSC_PSCTLWFP_LWFP(x) (((x)&0x1FF)<<0) + + +#endif /* __MCF5475_PSC_H__ */ diff --git a/tos/vmem_test/include/MCF5475_SDRAMC.h b/tos/vmem_test/include/MCF5475_SDRAMC.h new file mode 100644 index 0000000..6cdbd68 --- /dev/null +++ b/tos/vmem_test/include/MCF5475_SDRAMC.h @@ -0,0 +1,106 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SDRAMC_H__ +#define __MCF5475_SDRAMC_H__ + + +/********************************************************************* +* +* Synchronous DRAM Controller (SDRAMC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SDRAMC_SDRAMDS (*(volatile uint32_t*)(&_MBAR[0x4])) +#define MCF_SDRAMC_CS0CFG (*(volatile uint32_t*)(&_MBAR[0x20])) +#define MCF_SDRAMC_CS1CFG (*(volatile uint32_t*)(&_MBAR[0x24])) +#define MCF_SDRAMC_CS2CFG (*(volatile uint32_t*)(&_MBAR[0x28])) +#define MCF_SDRAMC_CS3CFG (*(volatile uint32_t*)(&_MBAR[0x2C])) +#define MCF_SDRAMC_SDMR (*(volatile uint32_t*)(&_MBAR[0x100])) +#define MCF_SDRAMC_SDCR (*(volatile uint32_t*)(&_MBAR[0x104])) +#define MCF_SDRAMC_SDCFG1 (*(volatile uint32_t*)(&_MBAR[0x108])) +#define MCF_SDRAMC_SDCFG2 (*(volatile uint32_t*)(&_MBAR[0x10C])) +#define MCF_SDRAMC_CSCFG(x) (*(volatile uint32_t*)(&_MBAR[0x20 + ((x)*0x4)])) + + +/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */ +#define MCF_SDRAMC_SDRAMDS_SB_D(x) (((x)&0x3)<<0) +#define MCF_SDRAMC_SDRAMDS_SB_S(x) (((x)&0x3)<<0x2) +#define MCF_SDRAMC_SDRAMDS_SB_A(x) (((x)&0x3)<<0x4) +#define MCF_SDRAMC_SDRAMDS_SB_C(x) (((x)&0x3)<<0x6) +#define MCF_SDRAMC_SDRAMDS_SB_E(x) (((x)&0x3)<<0x8) +#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA (0) +#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA (0x1) +#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA (0x2) +#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE (0x3) + +/* Bit definitions and macros for MCF_SDRAMC_CSCFG */ +#define MCF_SDRAMC_CSCFG_CSSZ(x) (((x)&0x1F)<<0) +#define MCF_SDRAMC_CSCFG_CSSZ_DISABLED (0) +#define MCF_SDRAMC_CSCFG_CSSZ_1MBYTE (0x13) +#define MCF_SDRAMC_CSCFG_CSSZ_2MBYTE (0x14) +#define MCF_SDRAMC_CSCFG_CSSZ_4MBYTE (0x15) +#define MCF_SDRAMC_CSCFG_CSSZ_8MBYTE (0x16) +#define MCF_SDRAMC_CSCFG_CSSZ_16MBYTE (0x17) +#define MCF_SDRAMC_CSCFG_CSSZ_32MBYTE (0x18) +#define MCF_SDRAMC_CSCFG_CSSZ_64MBYTE (0x19) +#define MCF_SDRAMC_CSCFG_CSSZ_128MBYTE (0x1A) +#define MCF_SDRAMC_CSCFG_CSSZ_256MBYTE (0x1B) +#define MCF_SDRAMC_CSCFG_CSSZ_512MBYTE (0x1C) +#define MCF_SDRAMC_CSCFG_CSSZ_1GBYTE (0x1D) +#define MCF_SDRAMC_CSCFG_CSSZ_2GBYTE (0x1E) +#define MCF_SDRAMC_CSCFG_CSSZ_4GBYTE (0x1F) +#define MCF_SDRAMC_CSCFG_CSBA(x) (((x)&0xFFF)<<0x14) +#define MCF_SDRAMC_CSCFG_BA(x) ((x)&0xFFF00000) + +/* Bit definitions and macros for MCF_SDRAMC_SDMR */ +#define MCF_SDRAMC_SDMR_CMD (0x10000) +#define MCF_SDRAMC_SDMR_AD(x) (((x)&0xFFF)<<0x12) +#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x3)<<0x1E) +#define MCF_SDRAMC_SDMR_BK_LMR (0) +#define MCF_SDRAMC_SDMR_BK_LEMR (0x40000000) + +/* Bit definitions and macros for MCF_SDRAMC_SDCR */ +#define MCF_SDRAMC_SDCR_IPALL (0x2) +#define MCF_SDRAMC_SDCR_IREF (0x4) +#define MCF_SDRAMC_SDCR_BUFF (0x10) +#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0xF)<<0x8) +#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x3F)<<0x10) +#define MCF_SDRAMC_SDCR_DRIVE (0x400000) +#define MCF_SDRAMC_SDCR_AP (0x800000) +#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x3)<<0x18) +#define MCF_SDRAMC_SDCR_REF (0x10000000) +#define MCF_SDRAMC_SDCR_DDR (0x20000000) +#define MCF_SDRAMC_SDCR_CKE (0x40000000) +#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) + +/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ +#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x7)<<0x4) +#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0xF)<<0x8) +#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x7)<<0xC) +#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x7)<<0x10) +#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0xF)<<0x14) +#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x7)<<0x18) +#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0xF)<<0x1C) + +/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */ +#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0xF)<<0x10) +#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0xF)<<0x14) +#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0xF)<<0x18) +#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0xF)<<0x1C) + + +#endif /* __MCF5475_SDRAMC_H__ */ diff --git a/tos/vmem_test/include/MCF5475_SEC.h b/tos/vmem_test/include/MCF5475_SEC.h new file mode 100644 index 0000000..8deff0b --- /dev/null +++ b/tos/vmem_test/include/MCF5475_SEC.h @@ -0,0 +1,398 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SEC_H__ +#define __MCF5475_SEC_H__ + + +/********************************************************************* +* +* Integrated Security Engine (SEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SEC_EUACRH (*(volatile uint32_t*)(&_MBAR[0x21000])) +#define MCF_SEC_EUACRL (*(volatile uint32_t*)(&_MBAR[0x21004])) +#define MCF_SEC_SIMRH (*(volatile uint32_t*)(&_MBAR[0x21008])) +#define MCF_SEC_SIMRL (*(volatile uint32_t*)(&_MBAR[0x2100C])) +#define MCF_SEC_SISRH (*(volatile uint32_t*)(&_MBAR[0x21010])) +#define MCF_SEC_SISRL (*(volatile uint32_t*)(&_MBAR[0x21014])) +#define MCF_SEC_SICRH (*(volatile uint32_t*)(&_MBAR[0x21018])) +#define MCF_SEC_SICRL (*(volatile uint32_t*)(&_MBAR[0x2101C])) +#define MCF_SEC_SIDR (*(volatile uint32_t*)(&_MBAR[0x21020])) +#define MCF_SEC_EUASRH (*(volatile uint32_t*)(&_MBAR[0x21028])) +#define MCF_SEC_EUASRL (*(volatile uint32_t*)(&_MBAR[0x2102C])) +#define MCF_SEC_SMCR (*(volatile uint32_t*)(&_MBAR[0x21030])) +#define MCF_SEC_MEAR (*(volatile uint32_t*)(&_MBAR[0x21038])) +#define MCF_SEC_CCCR0 (*(volatile uint32_t*)(&_MBAR[0x2200C])) +#define MCF_SEC_CCPSRH0 (*(volatile uint32_t*)(&_MBAR[0x22010])) +#define MCF_SEC_CCPSRL0 (*(volatile uint32_t*)(&_MBAR[0x22014])) +#define MCF_SEC_CDPR0 (*(volatile uint32_t*)(&_MBAR[0x22044])) +#define MCF_SEC_FR0 (*(volatile uint32_t*)(&_MBAR[0x2204C])) +#define MCF_SEC_CCCR1 (*(volatile uint32_t*)(&_MBAR[0x2300C])) +#define MCF_SEC_CCPSRH1 (*(volatile uint32_t*)(&_MBAR[0x23010])) +#define MCF_SEC_CCPSRL1 (*(volatile uint32_t*)(&_MBAR[0x23014])) +#define MCF_SEC_CDPR1 (*(volatile uint32_t*)(&_MBAR[0x23044])) +#define MCF_SEC_FR1 (*(volatile uint32_t*)(&_MBAR[0x2304C])) +#define MCF_SEC_AFRCR (*(volatile uint32_t*)(&_MBAR[0x28018])) +#define MCF_SEC_AFSR (*(volatile uint32_t*)(&_MBAR[0x28028])) +#define MCF_SEC_AFISR (*(volatile uint32_t*)(&_MBAR[0x28030])) +#define MCF_SEC_AFIMR (*(volatile uint32_t*)(&_MBAR[0x28038])) +#define MCF_SEC_DRCR (*(volatile uint32_t*)(&_MBAR[0x2A018])) +#define MCF_SEC_DSR (*(volatile uint32_t*)(&_MBAR[0x2A028])) +#define MCF_SEC_DISR (*(volatile uint32_t*)(&_MBAR[0x2A030])) +#define MCF_SEC_DIMR (*(volatile uint32_t*)(&_MBAR[0x2A038])) +#define MCF_SEC_MDRCR (*(volatile uint32_t*)(&_MBAR[0x2C018])) +#define MCF_SEC_MDSR (*(volatile uint32_t*)(&_MBAR[0x2C028])) +#define MCF_SEC_MDISR (*(volatile uint32_t*)(&_MBAR[0x2C030])) +#define MCF_SEC_MDIMR (*(volatile uint32_t*)(&_MBAR[0x2C038])) +#define MCF_SEC_RNGRCR (*(volatile uint32_t*)(&_MBAR[0x2E018])) +#define MCF_SEC_RNGSR (*(volatile uint32_t*)(&_MBAR[0x2E028])) +#define MCF_SEC_RNGISR (*(volatile uint32_t*)(&_MBAR[0x2E030])) +#define MCF_SEC_RNGIMR (*(volatile uint32_t*)(&_MBAR[0x2E038])) +#define MCF_SEC_AESRCR (*(volatile uint32_t*)(&_MBAR[0x32018])) +#define MCF_SEC_AESSR (*(volatile uint32_t*)(&_MBAR[0x32028])) +#define MCF_SEC_AESISR (*(volatile uint32_t*)(&_MBAR[0x32030])) +#define MCF_SEC_AESIMR (*(volatile uint32_t*)(&_MBAR[0x32038])) +#define MCF_SEC_CCCRn(x) (*(volatile uint32_t*)(&_MBAR[0x2200C + ((x)*0x1000)])) +#define MCF_SEC_CCPSRHn(x) (*(volatile uint32_t*)(&_MBAR[0x22010 + ((x)*0x1000)])) +#define MCF_SEC_CCPSRLn(x) (*(volatile uint32_t*)(&_MBAR[0x22014 + ((x)*0x1000)])) +#define MCF_SEC_CDPRn(x) (*(volatile uint32_t*)(&_MBAR[0x22044 + ((x)*0x1000)])) +#define MCF_SEC_FRn(x) (*(volatile uint32_t*)(&_MBAR[0x2204C + ((x)*0x1000)])) + + +/* Bit definitions and macros for MCF_SEC_EUACRH */ +#define MCF_SEC_EUACRH_AFEU(x) (((x)&0xF)<<0) +#define MCF_SEC_EUACRH_AFFEU_NOASSIGN (0) +#define MCF_SEC_EUACRH_AFFEU_CHA0 (0x1) +#define MCF_SEC_EUACRH_AFFEU_CHA1 (0x2) +#define MCF_SEC_EUACRH_MDEU(x) (((x)&0xF)<<0x8) +#define MCF_SEC_EUACRH_MDEU_NOASSIGN (0) +#define MCF_SEC_EUACRH_MDEU_CHA0 (0x100) +#define MCF_SEC_EUACRH_MDEU_CHA1 (0x200) +#define MCF_SEC_EUACRH_RNG(x) (((x)&0xF)<<0x18) +#define MCF_SEC_EUACRH_RNG_NOASSIGN (0) +#define MCF_SEC_EUACRH_RNG_CHA0 (0x1000000) +#define MCF_SEC_EUACRH_RNG_CHA1 (0x2000000) + +/* Bit definitions and macros for MCF_SEC_EUACRL */ +#define MCF_SEC_EUACRL_AESU(x) (((x)&0xF)<<0x10) +#define MCF_SEC_EUACRL_AESU_NOASSIGN (0) +#define MCF_SEC_EUACRL_AESU_CHA0 (0x10000) +#define MCF_SEC_EUACRL_AESU_CHA1 (0x20000) +#define MCF_SEC_EUACRL_DEU(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SEC_SIMRH */ +#define MCF_SEC_SIMRH_AERR (0x8000000) +#define MCF_SEC_SIMRH_CHA_0_DN (0x10000000) +#define MCF_SEC_SIMRH_CHA_0_ERR (0x20000000) +#define MCF_SEC_SIMRH_CHA_1_DN (0x40000000) +#define MCF_SEC_SIMRH_CHA_1_ERR (0x80000000) + +/* Bit definitions and macros for MCF_SEC_SIMRL */ +#define MCF_SEC_SIMRL_TEA (0x40) +#define MCF_SEC_SIMRL_DEU_DN (0x100) +#define MCF_SEC_SIMRL_DEU_ERR (0x200) +#define MCF_SEC_SIMRL_AESU_DN (0x1000) +#define MCF_SEC_SIMRL_AESU_ERR (0x2000) +#define MCF_SEC_SIMRL_MDEU_DN (0x10000) +#define MCF_SEC_SIMRL_MDEU_ERR (0x20000) +#define MCF_SEC_SIMRL_AFEU_DN (0x100000) +#define MCF_SEC_SIMRL_AFEU_ERR (0x200000) +#define MCF_SEC_SIMRL_RNG_DN (0x1000000) +#define MCF_SEC_SIMRL_RNG_ERR (0x2000000) + +/* Bit definitions and macros for MCF_SEC_SISRH */ +#define MCF_SEC_SISRH_AERR (0x8000000) +#define MCF_SEC_SISRH_CHA_0_DN (0x10000000) +#define MCF_SEC_SISRH_CHA_0_ERR (0x20000000) +#define MCF_SEC_SISRH_CHA_1_DN (0x40000000) +#define MCF_SEC_SISRH_CHA_1_ERR (0x80000000) + +/* Bit definitions and macros for MCF_SEC_SISRL */ +#define MCF_SEC_SISRL_TEA (0x40) +#define MCF_SEC_SISRL_DEU_DN (0x100) +#define MCF_SEC_SISRL_DEU_ERR (0x200) +#define MCF_SEC_SISRL_AESU_DN (0x1000) +#define MCF_SEC_SISRL_AESU_ERR (0x2000) +#define MCF_SEC_SISRL_MDEU_DN (0x10000) +#define MCF_SEC_SISRL_MDEU_ERR (0x20000) +#define MCF_SEC_SISRL_AFEU_DN (0x100000) +#define MCF_SEC_SISRL_AFEU_ERR (0x200000) +#define MCF_SEC_SISRL_RNG_DN (0x1000000) +#define MCF_SEC_SISRL_RNG_ERR (0x2000000) + +/* Bit definitions and macros for MCF_SEC_SICRH */ +#define MCF_SEC_SICRH_AERR (0x8000000) +#define MCF_SEC_SICRH_CHA_0_DN (0x10000000) +#define MCF_SEC_SICRH_CHA_0_ERR (0x20000000) +#define MCF_SEC_SICRH_CHA_1_DN (0x40000000) +#define MCF_SEC_SICRH_CHA_1_ERR (0x80000000) + +/* Bit definitions and macros for MCF_SEC_SICRL */ +#define MCF_SEC_SICRL_TEA (0x40) +#define MCF_SEC_SICRL_DEU_DN (0x100) +#define MCF_SEC_SICRL_DEU_ERR (0x200) +#define MCF_SEC_SICRL_AESU_DN (0x1000) +#define MCF_SEC_SICRL_AESU_ERR (0x2000) +#define MCF_SEC_SICRL_MDEU_DN (0x10000) +#define MCF_SEC_SICRL_MDEU_ERR (0x20000) +#define MCF_SEC_SICRL_AFEU_DN (0x100000) +#define MCF_SEC_SICRL_AFEU_ERR (0x200000) +#define MCF_SEC_SICRL_RNG_DN (0x1000000) +#define MCF_SEC_SICRL_RNG_ERR (0x2000000) + +/* Bit definitions and macros for MCF_SEC_SIDR */ +#define MCF_SEC_SIDR_VERSION(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_EUASRH */ +#define MCF_SEC_EUASRH_AFEU(x) (((x)&0xF)<<0) +#define MCF_SEC_EUASRH_MDEU(x) (((x)&0xF)<<0x8) +#define MCF_SEC_EUASRH_RNG(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SEC_EUASRL */ +#define MCF_SEC_EUASRL_AESU(x) (((x)&0xF)<<0x10) +#define MCF_SEC_EUASRL_DEU(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SEC_SMCR */ +#define MCF_SEC_SMCR_CURR_CHAN(x) (((x)&0xF)<<0x4) +#define MCF_SEC_SMCR_CURR_CHAN_1 (0x10) +#define MCF_SEC_SMCR_CURR_CHAN_2 (0x20) +#define MCF_SEC_SMCR_SWR (0x1000000) + +/* Bit definitions and macros for MCF_SEC_MEAR */ +#define MCF_SEC_MEAR_ADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_CCCRn */ +#define MCF_SEC_CCCRn_RST (0x1) +#define MCF_SEC_CCCRn_CDIE (0x2) +#define MCF_SEC_CCCRn_NT (0x4) +#define MCF_SEC_CCCRn_NE (0x8) +#define MCF_SEC_CCCRn_WE (0x10) +#define MCF_SEC_CCCRn_BURST_SIZE(x) (((x)&0x7)<<0x8) +#define MCF_SEC_CCCRn_BURST_SIZE_2 (0) +#define MCF_SEC_CCCRn_BURST_SIZE_8 (0x100) +#define MCF_SEC_CCCRn_BURST_SIZE_16 (0x200) +#define MCF_SEC_CCCRn_BURST_SIZE_24 (0x300) +#define MCF_SEC_CCCRn_BURST_SIZE_32 (0x400) +#define MCF_SEC_CCCRn_BURST_SIZE_40 (0x500) +#define MCF_SEC_CCCRn_BURST_SIZE_48 (0x600) +#define MCF_SEC_CCCRn_BURST_SIZE_56 (0x700) + +/* Bit definitions and macros for MCF_SEC_CCPSRHn */ +#define MCF_SEC_CCPSRHn_STATE(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_SEC_CCPSRLn */ +#define MCF_SEC_CCPSRLn_PAIR_PTR(x) (((x)&0xFF)<<0) +#define MCF_SEC_CCPSRLn_EUERR (0x100) +#define MCF_SEC_CCPSRLn_SERR (0x200) +#define MCF_SEC_CCPSRLn_DERR (0x400) +#define MCF_SEC_CCPSRLn_PERR (0x1000) +#define MCF_SEC_CCPSRLn_TEA (0x2000) +#define MCF_SEC_CCPSRLn_SD (0x10000) +#define MCF_SEC_CCPSRLn_PD (0x20000) +#define MCF_SEC_CCPSRLn_SRD (0x40000) +#define MCF_SEC_CCPSRLn_PRD (0x80000) +#define MCF_SEC_CCPSRLn_SG (0x100000) +#define MCF_SEC_CCPSRLn_PG (0x200000) +#define MCF_SEC_CCPSRLn_SR (0x400000) +#define MCF_SEC_CCPSRLn_PR (0x800000) +#define MCF_SEC_CCPSRLn_MO (0x1000000) +#define MCF_SEC_CCPSRLn_MI (0x2000000) +#define MCF_SEC_CCPSRLn_STAT (0x4000000) + +/* Bit definitions and macros for MCF_SEC_CDPRn */ +#define MCF_SEC_CDPRn_CDP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_FRn */ +#define MCF_SEC_FRn_FETCH_ADDR(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_AFRCR */ +#define MCF_SEC_AFRCR_SR (0x1000000) +#define MCF_SEC_AFRCR_MI (0x2000000) +#define MCF_SEC_AFRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_AFSR */ +#define MCF_SEC_AFSR_RD (0x1000000) +#define MCF_SEC_AFSR_ID (0x2000000) +#define MCF_SEC_AFSR_IE (0x4000000) +#define MCF_SEC_AFSR_OFR (0x8000000) +#define MCF_SEC_AFSR_IFW (0x10000000) +#define MCF_SEC_AFSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_AFISR */ +#define MCF_SEC_AFISR_DSE (0x10000) +#define MCF_SEC_AFISR_KSE (0x20000) +#define MCF_SEC_AFISR_CE (0x40000) +#define MCF_SEC_AFISR_ERE (0x80000) +#define MCF_SEC_AFISR_IE (0x100000) +#define MCF_SEC_AFISR_OFU (0x2000000) +#define MCF_SEC_AFISR_IFO (0x4000000) +#define MCF_SEC_AFISR_IFE (0x10000000) +#define MCF_SEC_AFISR_OFE (0x20000000) +#define MCF_SEC_AFISR_AE (0x40000000) +#define MCF_SEC_AFISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_AFIMR */ +#define MCF_SEC_AFIMR_DSE (0x10000) +#define MCF_SEC_AFIMR_KSE (0x20000) +#define MCF_SEC_AFIMR_CE (0x40000) +#define MCF_SEC_AFIMR_ERE (0x80000) +#define MCF_SEC_AFIMR_IE (0x100000) +#define MCF_SEC_AFIMR_OFU (0x2000000) +#define MCF_SEC_AFIMR_IFO (0x4000000) +#define MCF_SEC_AFIMR_IFE (0x10000000) +#define MCF_SEC_AFIMR_OFE (0x20000000) +#define MCF_SEC_AFIMR_AE (0x40000000) +#define MCF_SEC_AFIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_DRCR */ +#define MCF_SEC_DRCR_SR (0x1000000) +#define MCF_SEC_DRCR_MI (0x2000000) +#define MCF_SEC_DRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_DSR */ +#define MCF_SEC_DSR_RD (0x1000000) +#define MCF_SEC_DSR_ID (0x2000000) +#define MCF_SEC_DSR_IE (0x4000000) +#define MCF_SEC_DSR_OFR (0x8000000) +#define MCF_SEC_DSR_IFW (0x10000000) +#define MCF_SEC_DSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_DISR */ +#define MCF_SEC_DISR_DSE (0x10000) +#define MCF_SEC_DISR_KSE (0x20000) +#define MCF_SEC_DISR_CE (0x40000) +#define MCF_SEC_DISR_ERE (0x80000) +#define MCF_SEC_DISR_IE (0x100000) +#define MCF_SEC_DISR_KPE (0x200000) +#define MCF_SEC_DISR_OFU (0x2000000) +#define MCF_SEC_DISR_IFO (0x4000000) +#define MCF_SEC_DISR_IFE (0x10000000) +#define MCF_SEC_DISR_OFE (0x20000000) +#define MCF_SEC_DISR_AE (0x40000000) +#define MCF_SEC_DISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_DIMR */ +#define MCF_SEC_DIMR_DSE (0x10000) +#define MCF_SEC_DIMR_KSE (0x20000) +#define MCF_SEC_DIMR_CE (0x40000) +#define MCF_SEC_DIMR_ERE (0x80000) +#define MCF_SEC_DIMR_IE (0x100000) +#define MCF_SEC_DIMR_KPE (0x200000) +#define MCF_SEC_DIMR_OFU (0x2000000) +#define MCF_SEC_DIMR_IFO (0x4000000) +#define MCF_SEC_DIMR_IFE (0x10000000) +#define MCF_SEC_DIMR_OFE (0x20000000) +#define MCF_SEC_DIMR_AE (0x40000000) +#define MCF_SEC_DIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_MDRCR */ +#define MCF_SEC_MDRCR_SR (0x1000000) +#define MCF_SEC_MDRCR_MI (0x2000000) +#define MCF_SEC_MDRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_MDSR */ +#define MCF_SEC_MDSR_RD (0x1000000) +#define MCF_SEC_MDSR_ID (0x2000000) +#define MCF_SEC_MDSR_IE (0x4000000) +#define MCF_SEC_MDSR_IFW (0x10000000) +#define MCF_SEC_MDSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_MDISR */ +#define MCF_SEC_MDISR_DSE (0x10000) +#define MCF_SEC_MDISR_KSE (0x20000) +#define MCF_SEC_MDISR_CE (0x40000) +#define MCF_SEC_MDISR_ERE (0x80000) +#define MCF_SEC_MDISR_IE (0x100000) +#define MCF_SEC_MDISR_IFO (0x4000000) +#define MCF_SEC_MDISR_AE (0x40000000) +#define MCF_SEC_MDISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_MDIMR */ +#define MCF_SEC_MDIMR_DSE (0x10000) +#define MCF_SEC_MDIMR_KSE (0x20000) +#define MCF_SEC_MDIMR_CE (0x40000) +#define MCF_SEC_MDIMR_ERE (0x80000) +#define MCF_SEC_MDIMR_IE (0x100000) +#define MCF_SEC_MDIMR_IFO (0x4000000) +#define MCF_SEC_MDIMR_AE (0x40000000) +#define MCF_SEC_MDIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_RNGRCR */ +#define MCF_SEC_RNGRCR_SR (0x1000000) +#define MCF_SEC_RNGRCR_MI (0x2000000) +#define MCF_SEC_RNGRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_RNGSR */ +#define MCF_SEC_RNGSR_RD (0x1000000) +#define MCF_SEC_RNGSR_IE (0x4000000) +#define MCF_SEC_RNGSR_OFR (0x8000000) +#define MCF_SEC_RNGSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_RNGISR */ +#define MCF_SEC_RNGISR_IE (0x100000) +#define MCF_SEC_RNGISR_OFU (0x2000000) +#define MCF_SEC_RNGISR_AE (0x40000000) +#define MCF_SEC_RNGISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_RNGIMR */ +#define MCF_SEC_RNGIMR_IE (0x100000) +#define MCF_SEC_RNGIMR_OFU (0x2000000) +#define MCF_SEC_RNGIMR_AE (0x40000000) +#define MCF_SEC_RNGIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_AESRCR */ +#define MCF_SEC_AESRCR_SR (0x1000000) +#define MCF_SEC_AESRCR_MI (0x2000000) +#define MCF_SEC_AESRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_AESSR */ +#define MCF_SEC_AESSR_RD (0x1000000) +#define MCF_SEC_AESSR_ID (0x2000000) +#define MCF_SEC_AESSR_IE (0x4000000) +#define MCF_SEC_AESSR_OFR (0x8000000) +#define MCF_SEC_AESSR_IFW (0x10000000) +#define MCF_SEC_AESSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_AESISR */ +#define MCF_SEC_AESISR_DSE (0x10000) +#define MCF_SEC_AESISR_KSE (0x20000) +#define MCF_SEC_AESISR_CE (0x40000) +#define MCF_SEC_AESISR_ERE (0x80000) +#define MCF_SEC_AESISR_IE (0x100000) +#define MCF_SEC_AESISR_OFU (0x2000000) +#define MCF_SEC_AESISR_IFO (0x4000000) +#define MCF_SEC_AESISR_IFE (0x10000000) +#define MCF_SEC_AESISR_OFE (0x20000000) +#define MCF_SEC_AESISR_AE (0x40000000) +#define MCF_SEC_AESISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_AESIMR */ +#define MCF_SEC_AESIMR_DSE (0x10000) +#define MCF_SEC_AESIMR_KSE (0x20000) +#define MCF_SEC_AESIMR_CE (0x40000) +#define MCF_SEC_AESIMR_ERE (0x80000) +#define MCF_SEC_AESIMR_IE (0x100000) +#define MCF_SEC_AESIMR_OFU (0x2000000) +#define MCF_SEC_AESIMR_IFO (0x4000000) +#define MCF_SEC_AESIMR_IFE (0x10000000) +#define MCF_SEC_AESIMR_OFE (0x20000000) +#define MCF_SEC_AESIMR_AE (0x40000000) +#define MCF_SEC_AESIMR_ME (0x80000000) + + +#endif /* __MCF5475_SEC_H__ */ diff --git a/tos/vmem_test/include/MCF5475_SIU.h b/tos/vmem_test/include/MCF5475_SIU.h new file mode 100644 index 0000000..efb2896 --- /dev/null +++ b/tos/vmem_test/include/MCF5475_SIU.h @@ -0,0 +1,67 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SIU_H__ +#define __MCF5475_SIU_H__ + + +/********************************************************************* +* +* System Integration Unit (SIU) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SIU_SBCR (*(volatile uint32_t*)(&_MBAR[0x10])) +#define MCF_SIU_SECSACR (*(volatile uint32_t*)(&_MBAR[0x38])) +#define MCF_SIU_RSR (*(volatile uint32_t*)(&_MBAR[0x44])) +#define MCF_SIU_JTAGID (*(volatile uint32_t*)(&_MBAR[0x50])) + + +/* Bit definitions and macros for MCF_SIU_SBCR */ +#define MCF_SIU_SBCR_PIN2DSPI (0x8000000) +#define MCF_SIU_SBCR_DMA2CPU (0x10000000) +#define MCF_SIU_SBCR_CPU2DMA (0x20000000) +#define MCF_SIU_SBCR_PIN2DMA (0x40000000) +#define MCF_SIU_SBCR_PIN2CPU (0x80000000) + +/* Bit definitions and macros for MCF_SIU_SECSACR */ +#define MCF_SIU_SECSACR_SEQEN (0x1) + +/* Bit definitions and macros for MCF_SIU_RSR */ +#define MCF_SIU_RSR_RST (0x1) +#define MCF_SIU_RSR_RSTWD (0x2) +#define MCF_SIU_RSR_RSTJTG (0x8) + +/* Bit definitions and macros for MCF_SIU_JTAGID */ +#define MCF_SIU_JTAGID_JTAGID(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SIU_JTAGID */ +#define MCF_SIU_JTAGID_REV (0xF0000000) +#define MCF_SIU_JTAGID_PROCESSOR (0x0FFFFFFF) +#define MCF_SIU_JTAGID_MCF5485 (0x0800C01D) +#define MCF_SIU_JTAGID_MCF5484 (0x0800D01D) +#define MCF_SIU_JTAGID_MCF5483 (0x0800E01D) +#define MCF_SIU_JTAGID_MCF5482 (0x0800F01D) +#define MCF_SIU_JTAGID_MCF5481 (0x0801001D) +#define MCF_SIU_JTAGID_MCF5480 (0x0801101D) +#define MCF_SIU_JTAGID_MCF5475 (0x0801201D) +#define MCF_SIU_JTAGID_MCF5474 (0x0801301D) +#define MCF_SIU_JTAGID_MCF5473 (0x0801401D) +#define MCF_SIU_JTAGID_MCF5472 (0x0801501D) +#define MCF_SIU_JTAGID_MCF5471 (0x0801601D) +#define MCF_SIU_JTAGID_MCF5470 (0x0801701D) + +#endif /* __MCF5475_SIU_H__ */ diff --git a/tos/vmem_test/include/MCF5475_SLT.h b/tos/vmem_test/include/MCF5475_SLT.h new file mode 100644 index 0000000..20e8558 --- /dev/null +++ b/tos/vmem_test/include/MCF5475_SLT.h @@ -0,0 +1,59 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SLT_H__ +#define __MCF5475_SLT_H__ + + +/********************************************************************* +* +* Slice Timers (SLT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SLT0_STCNT (*(volatile uint32_t*)(&_MBAR[0x900])) +#define MCF_SLT0_SCR (*(volatile uint32_t*)(&_MBAR[0x904])) +#define MCF_SLT0_SCNT (*(volatile uint32_t*)(&_MBAR[0x908])) +#define MCF_SLT0_SSR (*(volatile uint32_t*)(&_MBAR[0x90C])) + +#define MCF_SLT1_STCNT (*(volatile uint32_t*)(&_MBAR[0x910])) +#define MCF_SLT1_SCR (*(volatile uint32_t*)(&_MBAR[0x914])) +#define MCF_SLT1_SCNT (*(volatile uint32_t*)(&_MBAR[0x918])) +#define MCF_SLT1_SSR (*(volatile uint32_t*)(&_MBAR[0x91C])) + +#define MCF_SLT_STCNT(x) (*(volatile uint32_t*)(&_MBAR[0x900 + ((x)*0x10)])) +#define MCF_SLT_SCR(x) (*(volatile uint32_t*)(&_MBAR[0x904 + ((x)*0x10)])) +#define MCF_SLT_SCNT(x) (*(volatile int32_t*)(&_MBAR[0x908 + ((x)*0x10)])) +#define MCF_SLT_SSR(x) (*(volatile uint32_t*)(&_MBAR[0x90C + ((x)*0x10)])) + + +/* Bit definitions and macros for MCF_SLT_STCNT */ +#define MCF_SLT_STCNT_TC(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SLT_SCR */ +#define MCF_SLT_SCR_TEN (0x1000000) +#define MCF_SLT_SCR_IEN (0x2000000) +#define MCF_SLT_SCR_RUN (0x4000000) + +/* Bit definitions and macros for MCF_SLT_SCNT */ +#define MCF_SLT_SCNT_CNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SLT_SSR */ +#define MCF_SLT_SSR_ST (0x1000000) +#define MCF_SLT_SSR_BE (0x2000000) + + +#endif /* __MCF5475_SLT_H__ */ diff --git a/tos/vmem_test/include/MCF5475_SRAM.h b/tos/vmem_test/include/MCF5475_SRAM.h new file mode 100644 index 0000000..d111f13 --- /dev/null +++ b/tos/vmem_test/include/MCF5475_SRAM.h @@ -0,0 +1,62 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SRAM_H__ +#define __MCF5475_SRAM_H__ + + +/********************************************************************* +* +* System SRAM Module (SRAM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SRAM_SSCR (*(volatile uint32_t*)(&__MBAR[0x1FFC0])) +#define MCF_SRAM_TCCR (*(volatile uint32_t*)(&__MBAR[0x1FFC4])) +#define MCF_SRAM_TCCRDR (*(volatile uint32_t*)(&__MBAR[0x1FFC8])) +#define MCF_SRAM_TCCRDW (*(volatile uint32_t*)(&__MBAR[0x1FFCC])) +#define MCF_SRAM_TCCRSEC (*(volatile uint32_t*)(&__MBAR[0x1FFD0])) + + +/* Bit definitions and macros for MCF_SRAM_SSCR */ +#define MCF_SRAM_SSCR_INLV (0x10000) + +/* Bit definitions and macros for MCF_SRAM_TCCR */ +#define MCF_SRAM_TCCR_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCR_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCR_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCR_BANK3_TC(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SRAM_TCCRDR */ +#define MCF_SRAM_TCCRDR_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCRDR_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCRDR_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCRDR_BANK3_TC(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SRAM_TCCRDW */ +#define MCF_SRAM_TCCRDW_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCRDW_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCRDW_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCRDW_BANK3_TC(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SRAM_TCCRSEC */ +#define MCF_SRAM_TCCRSEC_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCRSEC_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCRSEC_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCRSEC_BANK3_TC(x) (((x)&0xF)<<0x18) + + +#endif /* __MCF5475_SRAM_H__ */ diff --git a/tos/vmem_test/include/MCF5475_USB.h b/tos/vmem_test/include/MCF5475_USB.h new file mode 100644 index 0000000..c60273c --- /dev/null +++ b/tos/vmem_test/include/MCF5475_USB.h @@ -0,0 +1,554 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_USB_H__ +#define __MCF5475_USB_H__ + + +/********************************************************************* +* +* Universal Serial Bus Interface (USB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_USB_USBAISR (*(volatile uint8_t *)(&__MBAR[0xB000])) +#define MCF_USB_USBAIMR (*(volatile uint8_t *)(&__MBAR[0xB001])) +#define MCF_USB_EPINFO (*(volatile uint8_t *)(&__MBAR[0xB003])) +#define MCF_USB_CFGR (*(volatile uint8_t *)(&__MBAR[0xB004])) +#define MCF_USB_CFGAR (*(volatile uint8_t *)(&__MBAR[0xB005])) +#define MCF_USB_SPEEDR (*(volatile uint8_t *)(&__MBAR[0xB006])) +#define MCF_USB_FRMNUMR (*(volatile uint16_t*)(&__MBAR[0xB00E])) +#define MCF_USB_EPTNR (*(volatile uint16_t*)(&__MBAR[0xB010])) +#define MCF_USB_IFUR (*(volatile uint16_t*)(&__MBAR[0xB014])) +#define MCF_USB_IFR0 (*(volatile uint16_t*)(&__MBAR[0xB040])) +#define MCF_USB_IFR1 (*(volatile uint16_t*)(&__MBAR[0xB042])) +#define MCF_USB_IFR2 (*(volatile uint16_t*)(&__MBAR[0xB044])) +#define MCF_USB_IFR3 (*(volatile uint16_t*)(&__MBAR[0xB046])) +#define MCF_USB_IFR4 (*(volatile uint16_t*)(&__MBAR[0xB048])) +#define MCF_USB_IFR5 (*(volatile uint16_t*)(&__MBAR[0xB04A])) +#define MCF_USB_IFR6 (*(volatile uint16_t*)(&__MBAR[0xB04C])) +#define MCF_USB_IFR7 (*(volatile uint16_t*)(&__MBAR[0xB04E])) +#define MCF_USB_IFR8 (*(volatile uint16_t*)(&__MBAR[0xB050])) +#define MCF_USB_IFR9 (*(volatile uint16_t*)(&__MBAR[0xB052])) +#define MCF_USB_IFR10 (*(volatile uint16_t*)(&__MBAR[0xB054])) +#define MCF_USB_IFR11 (*(volatile uint16_t*)(&__MBAR[0xB056])) +#define MCF_USB_IFR12 (*(volatile uint16_t*)(&__MBAR[0xB058])) +#define MCF_USB_IFR13 (*(volatile uint16_t*)(&__MBAR[0xB05A])) +#define MCF_USB_IFR14 (*(volatile uint16_t*)(&__MBAR[0xB05C])) +#define MCF_USB_IFR15 (*(volatile uint16_t*)(&__MBAR[0xB05E])) +#define MCF_USB_IFR16 (*(volatile uint16_t*)(&__MBAR[0xB060])) +#define MCF_USB_IFR17 (*(volatile uint16_t*)(&__MBAR[0xB062])) +#define MCF_USB_IFR18 (*(volatile uint16_t*)(&__MBAR[0xB064])) +#define MCF_USB_IFR19 (*(volatile uint16_t*)(&__MBAR[0xB066])) +#define MCF_USB_IFR20 (*(volatile uint16_t*)(&__MBAR[0xB068])) +#define MCF_USB_IFR21 (*(volatile uint16_t*)(&__MBAR[0xB06A])) +#define MCF_USB_IFR22 (*(volatile uint16_t*)(&__MBAR[0xB06C])) +#define MCF_USB_IFR23 (*(volatile uint16_t*)(&__MBAR[0xB06E])) +#define MCF_USB_IFR24 (*(volatile uint16_t*)(&__MBAR[0xB070])) +#define MCF_USB_IFR25 (*(volatile uint16_t*)(&__MBAR[0xB072])) +#define MCF_USB_IFR26 (*(volatile uint16_t*)(&__MBAR[0xB074])) +#define MCF_USB_IFR27 (*(volatile uint16_t*)(&__MBAR[0xB076])) +#define MCF_USB_IFR28 (*(volatile uint16_t*)(&__MBAR[0xB078])) +#define MCF_USB_IFR29 (*(volatile uint16_t*)(&__MBAR[0xB07A])) +#define MCF_USB_IFR30 (*(volatile uint16_t*)(&__MBAR[0xB07C])) +#define MCF_USB_IFR31 (*(volatile uint16_t*)(&__MBAR[0xB07E])) +#define MCF_USB_PPCNT (*(volatile uint16_t*)(&__MBAR[0xB080])) +#define MCF_USB_DPCNT (*(volatile uint16_t*)(&__MBAR[0xB082])) +#define MCF_USB_CRCECNT (*(volatile uint16_t*)(&__MBAR[0xB084])) +#define MCF_USB_BSECNT (*(volatile uint16_t*)(&__MBAR[0xB086])) +#define MCF_USB_PIDECNT (*(volatile uint16_t*)(&__MBAR[0xB088])) +#define MCF_USB_FRMECNT (*(volatile uint16_t*)(&__MBAR[0xB08A])) +#define MCF_USB_TXPCNT (*(volatile uint16_t*)(&__MBAR[0xB08C])) +#define MCF_USB_CNTOVR (*(volatile uint8_t *)(&__MBAR[0xB08E])) +#define MCF_USB_EP0ACR (*(volatile uint8_t *)(&__MBAR[0xB101])) +#define MCF_USB_EP0MPSR (*(volatile uint16_t*)(&__MBAR[0xB102])) +#define MCF_USB_EP0IFR (*(volatile uint8_t *)(&__MBAR[0xB104])) +#define MCF_USB_EP0SR (*(volatile uint8_t *)(&__MBAR[0xB105])) +#define MCF_USB_BMRTR (*(volatile uint8_t *)(&__MBAR[0xB106])) +#define MCF_USB_BRTR (*(volatile uint8_t *)(&__MBAR[0xB107])) +#define MCF_USB_WVALUER (*(volatile uint16_t*)(&__MBAR[0xB108])) +#define MCF_USB_WINDEXR (*(volatile uint16_t*)(&__MBAR[0xB10A])) +#define MCF_USB_WLENGTHR (*(volatile uint16_t*)(&__MBAR[0xB10C])) +#define MCF_USB_EP1OUTACR (*(volatile uint8_t *)(&__MBAR[0xB131])) +#define MCF_USB_EP1OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB132])) +#define MCF_USB_EP1OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB134])) +#define MCF_USB_EP1OUTSR (*(volatile uint8_t *)(&__MBAR[0xB135])) +#define MCF_USB_EP1OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB13E])) +#define MCF_USB_EP1INACR (*(volatile uint8_t *)(&__MBAR[0xB149])) +#define MCF_USB_EP1INMPSR (*(volatile uint16_t*)(&__MBAR[0xB14A])) +#define MCF_USB_EP1INIFR (*(volatile uint8_t *)(&__MBAR[0xB14C])) +#define MCF_USB_EP1INSR (*(volatile uint8_t *)(&__MBAR[0xB14D])) +#define MCF_USB_EP1INSFR (*(volatile uint16_t*)(&__MBAR[0xB156])) +#define MCF_USB_EP2OUTACR (*(volatile uint8_t *)(&__MBAR[0xB161])) +#define MCF_USB_EP2OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB162])) +#define MCF_USB_EP2OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB164])) +#define MCF_USB_EP2OUTSR (*(volatile uint8_t *)(&__MBAR[0xB165])) +#define MCF_USB_EP2OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB16E])) +#define MCF_USB_EP2INACR (*(volatile uint8_t *)(&__MBAR[0xB179])) +#define MCF_USB_EP2INMPSR (*(volatile uint16_t*)(&__MBAR[0xB17A])) +#define MCF_USB_EP2INIFR (*(volatile uint8_t *)(&__MBAR[0xB17C])) +#define MCF_USB_EP2INSR (*(volatile uint8_t *)(&__MBAR[0xB17D])) +#define MCF_USB_EP2INSFR (*(volatile uint16_t*)(&__MBAR[0xB186])) +#define MCF_USB_EP3OUTACR (*(volatile uint8_t *)(&__MBAR[0xB191])) +#define MCF_USB_EP3OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB192])) +#define MCF_USB_EP3OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB194])) +#define MCF_USB_EP3OUTSR (*(volatile uint8_t *)(&__MBAR[0xB195])) +#define MCF_USB_EP3OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB19E])) +#define MCF_USB_EP3INACR (*(volatile uint8_t *)(&__MBAR[0xB1A9])) +#define MCF_USB_EP3INMPSR (*(volatile uint16_t*)(&__MBAR[0xB1AA])) +#define MCF_USB_EP3INIFR (*(volatile uint8_t *)(&__MBAR[0xB1AC])) +#define MCF_USB_EP3INSR (*(volatile uint8_t *)(&__MBAR[0xB1AD])) +#define MCF_USB_EP3INSFR (*(volatile uint16_t*)(&__MBAR[0xB1B6])) +#define MCF_USB_EP4OUTACR (*(volatile uint8_t *)(&__MBAR[0xB1C1])) +#define MCF_USB_EP4OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB1C2])) +#define MCF_USB_EP4OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB1C4])) +#define MCF_USB_EP4OUTSR (*(volatile uint8_t *)(&__MBAR[0xB1C5])) +#define MCF_USB_EP4OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB1CE])) +#define MCF_USB_EP4INACR (*(volatile uint8_t *)(&__MBAR[0xB1D9])) +#define MCF_USB_EP4INMPSR (*(volatile uint16_t*)(&__MBAR[0xB1DA])) +#define MCF_USB_EP4INIFR (*(volatile uint8_t *)(&__MBAR[0xB1DC])) +#define MCF_USB_EP4INSR (*(volatile uint8_t *)(&__MBAR[0xB1DD])) +#define MCF_USB_EP4INSFR (*(volatile uint16_t*)(&__MBAR[0xB1E6])) +#define MCF_USB_EP5OUTACR (*(volatile uint8_t *)(&__MBAR[0xB1F1])) +#define MCF_USB_EP5OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB1F2])) +#define MCF_USB_EP5OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB1F4])) +#define MCF_USB_EP5OUTSR (*(volatile uint8_t *)(&__MBAR[0xB1F5])) +#define MCF_USB_EP5OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB1FE])) +#define MCF_USB_EP5INACR (*(volatile uint8_t *)(&__MBAR[0xB209])) +#define MCF_USB_EP5INMPSR (*(volatile uint16_t*)(&__MBAR[0xB20A])) +#define MCF_USB_EP5INIFR (*(volatile uint8_t *)(&__MBAR[0xB20C])) +#define MCF_USB_EP5INSR (*(volatile uint8_t *)(&__MBAR[0xB20D])) +#define MCF_USB_EP5INSFR (*(volatile uint16_t*)(&__MBAR[0xB216])) +#define MCF_USB_EP6OUTACR (*(volatile uint8_t *)(&__MBAR[0xB221])) +#define MCF_USB_EP6OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB222])) +#define MCF_USB_EP6OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB224])) +#define MCF_USB_EP6OUTSR (*(volatile uint8_t *)(&__MBAR[0xB225])) +#define MCF_USB_EP6OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB22E])) +#define MCF_USB_EP6INACR (*(volatile uint8_t *)(&__MBAR[0xB239])) +#define MCF_USB_EP6INMPSR (*(volatile uint16_t*)(&__MBAR[0xB23A])) +#define MCF_USB_EP6INIFR (*(volatile uint8_t *)(&__MBAR[0xB23C])) +#define MCF_USB_EP6INSR (*(volatile uint8_t *)(&__MBAR[0xB23D])) +#define MCF_USB_EP6INSFR (*(volatile uint16_t*)(&__MBAR[0xB246])) +#define MCF_USB_USBSR (*(volatile uint32_t*)(&__MBAR[0xB400])) +#define MCF_USB_USBCR (*(volatile uint32_t*)(&__MBAR[0xB404])) +#define MCF_USB_DRAMCR (*(volatile uint32_t*)(&__MBAR[0xB408])) +#define MCF_USB_DRAMDR (*(volatile uint32_t*)(&__MBAR[0xB40C])) +#define MCF_USB_USBISR (*(volatile uint32_t*)(&__MBAR[0xB410])) +#define MCF_USB_USBIMR (*(volatile uint32_t*)(&__MBAR[0xB414])) +#define MCF_USB_EP0STAT (*(volatile uint32_t*)(&__MBAR[0xB440])) +#define MCF_USB_EP0ISR (*(volatile uint32_t*)(&__MBAR[0xB444])) +#define MCF_USB_EP0IMR (*(volatile uint32_t*)(&__MBAR[0xB448])) +#define MCF_USB_EP0FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB44C])) +#define MCF_USB_EP0FDR (*(volatile uint32_t*)(&__MBAR[0xB450])) +#define MCF_USB_EP0FSR (*(volatile uint32_t*)(&__MBAR[0xB454])) +#define MCF_USB_EP0FCR (*(volatile uint32_t*)(&__MBAR[0xB458])) +#define MCF_USB_EP0FAR (*(volatile uint32_t*)(&__MBAR[0xB45C])) +#define MCF_USB_EP0FRP (*(volatile uint32_t*)(&__MBAR[0xB460])) +#define MCF_USB_EP0FWP (*(volatile uint32_t*)(&__MBAR[0xB464])) +#define MCF_USB_EP0LRFP (*(volatile uint32_t*)(&__MBAR[0xB468])) +#define MCF_USB_EP0LWFP (*(volatile uint32_t*)(&__MBAR[0xB46C])) +#define MCF_USB_EP1STAT (*(volatile uint32_t*)(&__MBAR[0xB470])) +#define MCF_USB_EP1ISR (*(volatile uint32_t*)(&__MBAR[0xB474])) +#define MCF_USB_EP1IMR (*(volatile uint32_t*)(&__MBAR[0xB478])) +#define MCF_USB_EP1FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB47C])) +#define MCF_USB_EP1FDR (*(volatile uint32_t*)(&__MBAR[0xB480])) +#define MCF_USB_EP1FSR (*(volatile uint32_t*)(&__MBAR[0xB484])) +#define MCF_USB_EP1FCR (*(volatile uint32_t*)(&__MBAR[0xB488])) +#define MCF_USB_EP1FAR (*(volatile uint32_t*)(&__MBAR[0xB48C])) +#define MCF_USB_EP1FRP (*(volatile uint32_t*)(&__MBAR[0xB490])) +#define MCF_USB_EP1FWP (*(volatile uint32_t*)(&__MBAR[0xB494])) +#define MCF_USB_EP1LRFP (*(volatile uint32_t*)(&__MBAR[0xB498])) +#define MCF_USB_EP1LWFP (*(volatile uint32_t*)(&__MBAR[0xB49C])) +#define MCF_USB_EP2STAT (*(volatile uint32_t*)(&__MBAR[0xB4A0])) +#define MCF_USB_EP2ISR (*(volatile uint32_t*)(&__MBAR[0xB4A4])) +#define MCF_USB_EP2IMR (*(volatile uint32_t*)(&__MBAR[0xB4A8])) +#define MCF_USB_EP2FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB4AC])) +#define MCF_USB_EP2FDR (*(volatile uint32_t*)(&__MBAR[0xB4B0])) +#define MCF_USB_EP2FSR (*(volatile uint32_t*)(&__MBAR[0xB4B4])) +#define MCF_USB_EP2FCR (*(volatile uint32_t*)(&__MBAR[0xB4B8])) +#define MCF_USB_EP2FAR (*(volatile uint32_t*)(&__MBAR[0xB4BC])) +#define MCF_USB_EP2FRP (*(volatile uint32_t*)(&__MBAR[0xB4C0])) +#define MCF_USB_EP2FWP (*(volatile uint32_t*)(&__MBAR[0xB4C4])) +#define MCF_USB_EP2LRFP (*(volatile uint32_t*)(&__MBAR[0xB4C8])) +#define MCF_USB_EP2LWFP (*(volatile uint32_t*)(&__MBAR[0xB4CC])) +#define MCF_USB_EP3STAT (*(volatile uint32_t*)(&__MBAR[0xB4D0])) +#define MCF_USB_EP3ISR (*(volatile uint32_t*)(&__MBAR[0xB4D4])) +#define MCF_USB_EP3IMR (*(volatile uint32_t*)(&__MBAR[0xB4D8])) +#define MCF_USB_EP3FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB4DC])) +#define MCF_USB_EP3FDR (*(volatile uint32_t*)(&__MBAR[0xB4E0])) +#define MCF_USB_EP3FSR (*(volatile uint32_t*)(&__MBAR[0xB4E4])) +#define MCF_USB_EP3FCR (*(volatile uint32_t*)(&__MBAR[0xB4E8])) +#define MCF_USB_EP3FAR (*(volatile uint32_t*)(&__MBAR[0xB4EC])) +#define MCF_USB_EP3FRP (*(volatile uint32_t*)(&__MBAR[0xB4F0])) +#define MCF_USB_EP3FWP (*(volatile uint32_t*)(&__MBAR[0xB4F4])) +#define MCF_USB_EP3LRFP (*(volatile uint32_t*)(&__MBAR[0xB4F8])) +#define MCF_USB_EP3LWFP (*(volatile uint32_t*)(&__MBAR[0xB4FC])) +#define MCF_USB_EP4STAT (*(volatile uint32_t*)(&__MBAR[0xB500])) +#define MCF_USB_EP4ISR (*(volatile uint32_t*)(&__MBAR[0xB504])) +#define MCF_USB_EP4IMR (*(volatile uint32_t*)(&__MBAR[0xB508])) +#define MCF_USB_EP4FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB50C])) +#define MCF_USB_EP4FDR (*(volatile uint32_t*)(&__MBAR[0xB510])) +#define MCF_USB_EP4FSR (*(volatile uint32_t*)(&__MBAR[0xB514])) +#define MCF_USB_EP4FCR (*(volatile uint32_t*)(&__MBAR[0xB518])) +#define MCF_USB_EP4FAR (*(volatile uint32_t*)(&__MBAR[0xB51C])) +#define MCF_USB_EP4FRP (*(volatile uint32_t*)(&__MBAR[0xB520])) +#define MCF_USB_EP4FWP (*(volatile uint32_t*)(&__MBAR[0xB524])) +#define MCF_USB_EP4LRFP (*(volatile uint32_t*)(&__MBAR[0xB528])) +#define MCF_USB_EP4LWFP (*(volatile uint32_t*)(&__MBAR[0xB52C])) +#define MCF_USB_EP5STAT (*(volatile uint32_t*)(&__MBAR[0xB530])) +#define MCF_USB_EP5ISR (*(volatile uint32_t*)(&__MBAR[0xB534])) +#define MCF_USB_EP5IMR (*(volatile uint32_t*)(&__MBAR[0xB538])) +#define MCF_USB_EP5FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB53C])) +#define MCF_USB_EP5FDR (*(volatile uint32_t*)(&__MBAR[0xB540])) +#define MCF_USB_EP5FSR (*(volatile uint32_t*)(&__MBAR[0xB544])) +#define MCF_USB_EP5FCR (*(volatile uint32_t*)(&__MBAR[0xB548])) +#define MCF_USB_EP5FAR (*(volatile uint32_t*)(&__MBAR[0xB54C])) +#define MCF_USB_EP5FRP (*(volatile uint32_t*)(&__MBAR[0xB550])) +#define MCF_USB_EP5FWP (*(volatile uint32_t*)(&__MBAR[0xB554])) +#define MCF_USB_EP5LRFP (*(volatile uint32_t*)(&__MBAR[0xB558])) +#define MCF_USB_EP5LWFP (*(volatile uint32_t*)(&__MBAR[0xB55C])) +#define MCF_USB_EP6STAT (*(volatile uint32_t*)(&__MBAR[0xB560])) +#define MCF_USB_EP6ISR (*(volatile uint32_t*)(&__MBAR[0xB564])) +#define MCF_USB_EP6IMR (*(volatile uint32_t*)(&__MBAR[0xB568])) +#define MCF_USB_EP6FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB56C])) +#define MCF_USB_EP6FDR (*(volatile uint32_t*)(&__MBAR[0xB570])) +#define MCF_USB_EP6FSR (*(volatile uint32_t*)(&__MBAR[0xB574])) +#define MCF_USB_EP6FCR (*(volatile uint32_t*)(&__MBAR[0xB578])) +#define MCF_USB_EP6FAR (*(volatile uint32_t*)(&__MBAR[0xB57C])) +#define MCF_USB_EP6FRP (*(volatile uint32_t*)(&__MBAR[0xB580])) +#define MCF_USB_EP6FWP (*(volatile uint32_t*)(&__MBAR[0xB584])) +#define MCF_USB_EP6LRFP (*(volatile uint32_t*)(&__MBAR[0xB588])) +#define MCF_USB_EP6LWFP (*(volatile uint32_t*)(&__MBAR[0xB58C])) +#define MCF_USB_IFR(x) (*(volatile uint16_t*)(&__MBAR[0xB040 + ((x)*0x2)])) +#define MCF_USB_EPOUTACR(x) (*(volatile uint8_t *)(&__MBAR[0xB131 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTMPSR(x) (*(volatile uint16_t*)(&__MBAR[0xB132 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTIFR(x) (*(volatile uint8_t *)(&__MBAR[0xB134 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTSR(x) (*(volatile uint8_t *)(&__MBAR[0xB135 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTSFR(x) (*(volatile uint16_t*)(&__MBAR[0xB13E + ((x-1)*0x30)])) +#define MCF_USB_EPINACR(x) (*(volatile uint8_t *)(&__MBAR[0xB149 + ((x-1)*0x30)])) +#define MCF_USB_EPINMPSR(x) (*(volatile uint16_t*)(&__MBAR[0xB14A + ((x-1)*0x30)])) +#define MCF_USB_EPINIFR(x) (*(volatile uint8_t *)(&__MBAR[0xB14C + ((x-1)*0x30)])) +#define MCF_USB_EPINSR(x) (*(volatile uint8_t *)(&__MBAR[0xB14D + ((x-1)*0x30)])) +#define MCF_USB_EPINSFR(x) (*(volatile uint16_t*)(&__MBAR[0xB156 + ((x-1)*0x30)])) +#define MCF_USB_EPSTAT(x) (*(volatile uint32_t*)(&__MBAR[0xB440 + ((x)*0x30)])) +#define MCF_USB_EPISR(x) (*(volatile uint32_t*)(&__MBAR[0xB444 + ((x)*0x30)])) +#define MCF_USB_EPIMR(x) (*(volatile uint32_t*)(&__MBAR[0xB448 + ((x)*0x30)])) +#define MCF_USB_EPFRCFGR(x) (*(volatile uint32_t*)(&__MBAR[0xB44C + ((x)*0x30)])) +#define MCF_USB_EPFDR(x) (*(volatile uint32_t*)(&__MBAR[0xB450 + ((x)*0x30)])) +#define MCF_USB_EPFSR(x) (*(volatile uint32_t*)(&__MBAR[0xB454 + ((x)*0x30)])) +#define MCF_USB_EPFCR(x) (*(volatile uint32_t*)(&__MBAR[0xB458 + ((x)*0x30)])) +#define MCF_USB_EPFAR(x) (*(volatile uint32_t*)(&__MBAR[0xB45C + ((x)*0x30)])) +#define MCF_USB_EPFRP(x) (*(volatile uint32_t*)(&__MBAR[0xB460 + ((x)*0x30)])) +#define MCF_USB_EPFWP(x) (*(volatile uint32_t*)(&__MBAR[0xB464 + ((x)*0x30)])) +#define MCF_USB_EPLRFP(x) (*(volatile uint32_t*)(&__MBAR[0xB468 + ((x)*0x30)])) +#define MCF_USB_EPLWFP(x) (*(volatile uint32_t*)(&__MBAR[0xB46C + ((x)*0x30)])) + + +/* Bit definitions and macros for MCF_USB_USBAISR */ +#define MCF_USB_USBAISR_SETUP (0x1) +#define MCF_USB_USBAISR_IN (0x2) +#define MCF_USB_USBAISR_OUT (0x4) +#define MCF_USB_USBAISR_EPHALT (0x8) +#define MCF_USB_USBAISR_TRANSERR (0x10) +#define MCF_USB_USBAISR_ACK (0x20) +#define MCF_USB_USBAISR_CTROVFL (0x40) +#define MCF_USB_USBAISR_EPSTALL (0x80) + +/* Bit definitions and macros for MCF_USB_USBAIMR */ +#define MCF_USB_USBAIMR_SETUPEN (0x1) +#define MCF_USB_USBAIMR_INEN (0x2) +#define MCF_USB_USBAIMR_OUTEN (0x4) +#define MCF_USB_USBAIMR_EPHALTEN (0x8) +#define MCF_USB_USBAIMR_TRANSERREN (0x10) +#define MCF_USB_USBAIMR_ACKEN (0x20) +#define MCF_USB_USBAIMR_CTROVFLEN (0x40) +#define MCF_USB_USBAIMR_EPSTALLEN (0x80) + +/* Bit definitions and macros for MCF_USB_EPINFO */ +#define MCF_USB_EPINFO_EPDIR (0x1) +#define MCF_USB_EPINFO_EPNUM(x) (((x)&0x7)<<0x1) + +/* Bit definitions and macros for MCF_USB_CFGR */ +#define MCF_USB_CFGR_Configuration_Value(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_CFGAR */ +#define MCF_USB_CFGAR_RESERVED (0xA0) +#define MCF_USB_CFGAR_RMTWKEUP (0xE0) + +/* Bit definitions and macros for MCF_USB_SPEEDR */ +#define MCF_USB_SPEEDR_SPEED(x) (((x)&0x3)<<0) + +/* Bit definitions and macros for MCF_USB_FRMNUMR */ +#define MCF_USB_FRMNUMR_FRMNUM(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPTNR */ +#define MCF_USB_EPTNR_EP1T(x) (((x)&0x3)<<0) +#define MCF_USB_EPTNR_EP2T(x) (((x)&0x3)<<0x2) +#define MCF_USB_EPTNR_EP3T(x) (((x)&0x3)<<0x4) +#define MCF_USB_EPTNR_EP4T(x) (((x)&0x3)<<0x6) +#define MCF_USB_EPTNR_EP5T(x) (((x)&0x3)<<0x8) +#define MCF_USB_EPTNR_EP6T(x) (((x)&0x3)<<0xA) +#define MCF_USB_EPTNR_EPnT1 (0) +#define MCF_USB_EPTNR_EPnT2 (0x1) +#define MCF_USB_EPTNR_EPnT3 (0x2) + +/* Bit definitions and macros for MCF_USB_IFUR */ +#define MCF_USB_IFUR_ALTSET(x) (((x)&0xFF)<<0) +#define MCF_USB_IFUR_IFNUM(x) (((x)&0xFF)<<0x8) + +/* Bit definitions and macros for MCF_USB_IFR */ +#define MCF_USB_IFR_ALTSET(x) (((x)&0xFF)<<0) +#define MCF_USB_IFR_IFNUM(x) (((x)&0xFF)<<0x8) + +/* Bit definitions and macros for MCF_USB_PPCNT */ +#define MCF_USB_PPCNT_PPCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_DPCNT */ +#define MCF_USB_DPCNT_DPCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_CRCECNT */ +#define MCF_USB_CRCECNT_CRCECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_BSECNT */ +#define MCF_USB_BSECNT_BSECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_PIDECNT */ +#define MCF_USB_PIDECNT_PIDECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_FRMECNT */ +#define MCF_USB_FRMECNT_FRMECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_TXPCNT */ +#define MCF_USB_TXPCNT_TXPCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_CNTOVR */ +#define MCF_USB_CNTOVR_PPCNT (0x1) +#define MCF_USB_CNTOVR_DPCNT (0x2) +#define MCF_USB_CNTOVR_CRCECNT (0x4) +#define MCF_USB_CNTOVR_BSECNT (0x8) +#define MCF_USB_CNTOVR_PIDECNT (0x10) +#define MCF_USB_CNTOVR_FRMECNT (0x20) +#define MCF_USB_CNTOVR_TXPCNT (0x40) + +/* Bit definitions and macros for MCF_USB_EP0ACR */ +#define MCF_USB_EP0ACR_TTYPE(x) (((x)&0x3)<<0) +#define MCF_USB_EP0ACR_TTYPE_CTRL (0) +#define MCF_USB_EP0ACR_TTYPE_ISOC (0x1) +#define MCF_USB_EP0ACR_TTYPE_BULK (0x2) +#define MCF_USB_EP0ACR_TTYPE_INT (0x3) + +/* Bit definitions and macros for MCF_USB_EP0MPSR */ +#define MCF_USB_EP0MPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0) +#define MCF_USB_EP0MPSR_ADDTRANS(x) (((x)&0x3)<<0xB) + +/* Bit definitions and macros for MCF_USB_EP0IFR */ +#define MCF_USB_EP0IFR_IFNUM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_EP0SR */ +#define MCF_USB_EP0SR_HALT (0x1) +#define MCF_USB_EP0SR_ACTIVE (0x2) +#define MCF_USB_EP0SR_PSTALL (0x4) +#define MCF_USB_EP0SR_CCOMP (0x8) +#define MCF_USB_EP0SR_TXZERO (0x20) +#define MCF_USB_EP0SR_INT (0x80) + +/* Bit definitions and macros for MCF_USB_BMRTR */ +#define MCF_USB_BMRTR_REC(x) (((x)&0x1F)<<0) +#define MCF_USB_BMRTR_REC_DEVICE (0) +#define MCF_USB_BMRTR_REC_INTERFACE (0x1) +#define MCF_USB_BMRTR_REC_ENDPOINT (0x2) +#define MCF_USB_BMRTR_REC_OTHER (0x3) +#define MCF_USB_BMRTR_TYPE(x) (((x)&0x3)<<0x5) +#define MCF_USB_BMRTR_TYPE_STANDARD (0) +#define MCF_USB_BMRTR_TYPE_CLASS (0x20) +#define MCF_USB_BMRTR_TYPE_VENDOR (0x40) +#define MCF_USB_BMRTR_DIR (0x80) + +/* Bit definitions and macros for MCF_USB_BRTR */ +#define MCF_USB_BRTR_BREQ(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_WVALUER */ +#define MCF_USB_WVALUER_WVALUE(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_WINDEXR */ +#define MCF_USB_WINDEXR_WINDEX(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_WLENGTHR */ +#define MCF_USB_WLENGTHR_WLENGTH(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPOUTACR */ +#define MCF_USB_EPOUTACR_TTYPE(x) (((x)&0x3)<<0) +#define MCF_USB_EPOUTACR_TTYPE_ISOC (0x1) +#define MCF_USB_EPOUTACR_TTYPE_BULK (0x2) +#define MCF_USB_EPOUTACR_TTYPE_INT (0x3) + +/* Bit definitions and macros for MCF_USB_EPOUTMPSR */ +#define MCF_USB_EPOUTMPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0) +#define MCF_USB_EPOUTMPSR_ADDTRANS(x) (((x)&0x3)<<0xB) + +/* Bit definitions and macros for MCF_USB_EPOUTIFR */ +#define MCF_USB_EPOUTIFR_IFNUM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPOUTSR */ +#define MCF_USB_EPOUTSR_HALT (0x1) +#define MCF_USB_EPOUTSR_ACTIVE (0x2) +#define MCF_USB_EPOUTSR_PSTALL (0x4) +#define MCF_USB_EPOUTSR_CCOMP (0x8) +#define MCF_USB_EPOUTSR_TXZERO (0x20) +#define MCF_USB_EPOUTSR_INT (0x80) + +/* Bit definitions and macros for MCF_USB_EPOUTSFR */ +#define MCF_USB_EPOUTSFR_FRMNUM(x) (((x)&0x7FF)<<0) + +/* Bit definitions and macros for MCF_USB_EPINACR */ +#define MCF_USB_EPINACR_TTYPE(x) (((x)&0x3)<<0) +#define MCF_USB_EPINACR_TTYPE_ISOC (0x1) +#define MCF_USB_EPINACR_TTYPE_BULK (0x2) +#define MCF_USB_EPINACR_TTYPE_INT (0x3) + +/* Bit definitions and macros for MCF_USB_EPINMPSR */ +#define MCF_USB_EPINMPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0) +#define MCF_USB_EPINMPSR_ADDTRANS(x) (((x)&0x3)<<0xB) + +/* Bit definitions and macros for MCF_USB_EPINIFR */ +#define MCF_USB_EPINIFR_IFNUM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPINSR */ +#define MCF_USB_EPINSR_HALT (0x1) +#define MCF_USB_EPINSR_ACTIVE (0x2) +#define MCF_USB_EPINSR_PSTALL (0x4) +#define MCF_USB_EPINSR_CCOMP (0x8) +#define MCF_USB_EPINSR_TXZERO (0x20) +#define MCF_USB_EPINSR_INT (0x80) + +/* Bit definitions and macros for MCF_USB_EPINSFR */ +#define MCF_USB_EPINSFR_FRMNUM(x) (((x)&0x7FF)<<0) + +/* Bit definitions and macros for MCF_USB_USBSR */ +#define MCF_USB_USBSR_ISOERREP(x) (((x)&0xF)<<0) +#define MCF_USB_USBSR_SUSP (0x80) + +/* Bit definitions and macros for MCF_USB_USBCR */ +#define MCF_USB_USBCR_RESUME (0x1) +#define MCF_USB_USBCR_APPLOCK (0x2) +#define MCF_USB_USBCR_RST (0x4) +#define MCF_USB_USBCR_RAMEN (0x8) +#define MCF_USB_USBCR_RAMSPLIT (0x20) + +/* Bit definitions and macros for MCF_USB_DRAMCR */ +#define MCF_USB_DRAMCR_DADR(x) (((x)&0x3FF)<<0) +#define MCF_USB_DRAMCR_DSIZE(x) (((x)&0x7FF)<<0x10) +#define MCF_USB_DRAMCR_BSY (0x40000000) +#define MCF_USB_DRAMCR_START (0x80000000) + +/* Bit definitions and macros for MCF_USB_DRAMDR */ +#define MCF_USB_DRAMDR_DDAT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_USBISR */ +#define MCF_USB_USBISR_ISOERR (0x1) +#define MCF_USB_USBISR_FTUNLCK (0x2) +#define MCF_USB_USBISR_SUSP (0x4) +#define MCF_USB_USBISR_RES (0x8) +#define MCF_USB_USBISR_UPDSOF (0x10) +#define MCF_USB_USBISR_RSTSTOP (0x20) +#define MCF_USB_USBISR_SOF (0x40) +#define MCF_USB_USBISR_MSOF (0x80) + +/* Bit definitions and macros for MCF_USB_USBIMR */ +#define MCF_USB_USBIMR_ISOERR (0x1) +#define MCF_USB_USBIMR_FTUNLCK (0x2) +#define MCF_USB_USBIMR_SUSP (0x4) +#define MCF_USB_USBIMR_RES (0x8) +#define MCF_USB_USBIMR_UPDSOF (0x10) +#define MCF_USB_USBIMR_RSTSTOP (0x20) +#define MCF_USB_USBIMR_SOF (0x40) +#define MCF_USB_USBIMR_MSOF (0x80) + +/* Bit definitions and macros for MCF_USB_EPSTAT */ +#define MCF_USB_EPSTAT_RST (0x1) +#define MCF_USB_EPSTAT_FLUSH (0x2) +#define MCF_USB_EPSTAT_DIR (0x80) +#define MCF_USB_EPSTAT_BYTECNT(x) (((x)&0xFFF)<<0x10) + +/* Bit definitions and macros for MCF_USB_EPISR */ +#define MCF_USB_EPISR_EOF (0x1) +#define MCF_USB_EPISR_EOT (0x4) +#define MCF_USB_EPISR_FIFOLO (0x10) +#define MCF_USB_EPISR_FIFOHI (0x20) +#define MCF_USB_EPISR_ERR (0x40) +#define MCF_USB_EPISR_EMT (0x80) +#define MCF_USB_EPISR_FU (0x100) + +/* Bit definitions and macros for MCF_USB_EPIMR */ +#define MCF_USB_EPIMR_EOF (0x1) +#define MCF_USB_EPIMR_EOT (0x4) +#define MCF_USB_EPIMR_FIFOLO (0x10) +#define MCF_USB_EPIMR_FIFOHI (0x20) +#define MCF_USB_EPIMR_ERR (0x40) +#define MCF_USB_EPIMR_EMT (0x80) +#define MCF_USB_EPIMR_FU (0x100) + +/* Bit definitions and macros for MCF_USB_EPFRCFGR */ +#define MCF_USB_EPFRCFGR_DEPTH(x) (((x)&0x1FFF)<<0) +#define MCF_USB_EPFRCFGR_BASE(x) (((x)&0xFFF)<<0x10) + +/* Bit definitions and macros for MCF_USB_EPFDR */ +#define MCF_USB_EPFDR_RX_TXDATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPFSR */ +#define MCF_USB_EPFSR_EMT (0x10000) +#define MCF_USB_EPFSR_ALRM (0x20000) +#define MCF_USB_EPFSR_FU (0x40000) +#define MCF_USB_EPFSR_FR (0x80000) +#define MCF_USB_EPFSR_OF (0x100000) +#define MCF_USB_EPFSR_UF (0x200000) +#define MCF_USB_EPFSR_RXW (0x400000) +#define MCF_USB_EPFSR_FAE (0x800000) +#define MCF_USB_EPFSR_FRM(x) (((x)&0xF)<<0x18) +#define MCF_USB_EPFSR_TXW (0x40000000) +#define MCF_USB_EPFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_USB_EPFCR */ +#define MCF_USB_EPFCR_COUNTER(x) (((x)&0xFFFF)<<0) +#define MCF_USB_EPFCR_TXWMSK (0x40000) +#define MCF_USB_EPFCR_OFMSK (0x80000) +#define MCF_USB_EPFCR_UFMSK (0x100000) +#define MCF_USB_EPFCR_RXWMSK (0x200000) +#define MCF_USB_EPFCR_FAEMSK (0x400000) +#define MCF_USB_EPFCR_IPMSK (0x800000) +#define MCF_USB_EPFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_USB_EPFCR_FRM (0x8000000) +#define MCF_USB_EPFCR_TMR (0x10000000) +#define MCF_USB_EPFCR_WFR (0x20000000) +#define MCF_USB_EPFCR_SHAD (0x80000000) + +/* Bit definitions and macros for MCF_USB_EPFAR */ +#define MCF_USB_EPFAR_ALRMP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPFRP */ +#define MCF_USB_EPFRP_RP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPFWP */ +#define MCF_USB_EPFWP_WP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPLRFP */ +#define MCF_USB_EPLRFP_LRFP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPLWFP */ +#define MCF_USB_EPLWFP_LWFP(x) (((x)&0xFFF)<<0) + + +#endif /* __MCF5475_USB_H__ */ diff --git a/tos/vmem_test/include/MCF5475_XLB.h b/tos/vmem_test/include/MCF5475_XLB.h new file mode 100644 index 0000000..af25ae7 --- /dev/null +++ b/tos/vmem_test/include/MCF5475_XLB.h @@ -0,0 +1,101 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_XLB_H__ +#define __MCF5475_XLB_H__ + + +/********************************************************************* +* +* XL Bus Arbiter (XLB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_XLB_XARB_CFG (*(volatile uint32_t*)(&_MBAR[0x240])) +#define MCF_XLB_XARB_VER (*(volatile uint32_t*)(&_MBAR[0x244])) +#define MCF_XLB_XARB_SR (*(volatile uint32_t*)(&_MBAR[0x248])) +#define MCF_XLB_XARB_IMR (*(volatile uint32_t*)(&_MBAR[0x24C])) +#define MCF_XLB_XARB_ADRCAP (*(volatile uint32_t*)(&_MBAR[0x250])) +#define MCF_XLB_XARB_SIGCAP (*(volatile uint32_t*)(&_MBAR[0x254])) +#define MCF_XLB_XARB_ADRTO (*(volatile uint32_t*)(&_MBAR[0x258])) +#define MCF_XLB_XARB_DATTO (*(volatile uint32_t*)(&_MBAR[0x25C])) +#define MCF_XLB_XARB_BUSTO (*(volatile uint32_t*)(&_MBAR[0x260])) +#define MCF_XLB_XARB_PRIEN (*(volatile uint32_t*)(&_MBAR[0x264])) +#define MCF_XLB_XARB_PRI (*(volatile uint32_t*)(&_MBAR[0x268])) + + +/* Bit definitions and macros for MCF_XLB_XARB_CFG */ +#define MCF_XLB_XARB_CFG_AT (0x2) +#define MCF_XLB_XARB_CFG_DT (0x4) +#define MCF_XLB_XARB_CFG_BA (0x8) +#define MCF_XLB_XARB_CFG_PM(x) (((x)&0x3)<<0x5) +#define MCF_XLB_XARB_CFG_SP(x) (((x)&0x7)<<0x8) +#define MCF_XLB_XARB_CFG_PLDIS (0x80000000) + +/* Bit definitions and macros for MCF_XLB_XARB_VER */ +#define MCF_XLB_XARB_VER_VER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_SR */ +#define MCF_XLB_XARB_SR_AT (0x1) +#define MCF_XLB_XARB_SR_DT (0x2) +#define MCF_XLB_XARB_SR_BA (0x4) +#define MCF_XLB_XARB_SR_TTM (0x8) +#define MCF_XLB_XARB_SR_ECW (0x10) +#define MCF_XLB_XARB_SR_TTR (0x20) +#define MCF_XLB_XARB_SR_TTA (0x40) +#define MCF_XLB_XARB_SR_MM (0x80) +#define MCF_XLB_XARB_SR_SEA (0x100) + +/* Bit definitions and macros for MCF_XLB_XARB_IMR */ +#define MCF_XLB_XARB_IMR_ATE (0x1) +#define MCF_XLB_XARB_IMR_DTE (0x2) +#define MCF_XLB_XARB_IMR_BAE (0x4) +#define MCF_XLB_XARB_IMR_TTME (0x8) +#define MCF_XLB_XARB_IMR_ECWE (0x10) +#define MCF_XLB_XARB_IMR_TTRE (0x20) +#define MCF_XLB_XARB_IMR_TTAE (0x40) +#define MCF_XLB_XARB_IMR_MME (0x80) +#define MCF_XLB_XARB_IMR_SEAE (0x100) + +/* Bit definitions and macros for MCF_XLB_XARB_ADRCAP */ +#define MCF_XLB_XARB_ADRCAP_ADRCAP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_SIGCAP */ +#define MCF_XLB_XARB_SIGCAP_TT(x) (((x)&0x1F)<<0) +#define MCF_XLB_XARB_SIGCAP_TBST (0x20) +#define MCF_XLB_XARB_SIGCAP_TSIZ(x) (((x)&0x7)<<0x7) + +/* Bit definitions and macros for MCF_XLB_XARB_ADRTO */ +#define MCF_XLB_XARB_ADRTO_ADRTO(x) (((x)&0xFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_DATTO */ +#define MCF_XLB_XARB_DATTO_DATTO(x) (((x)&0xFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_BUSTO */ +#define MCF_XLB_XARB_BUSTO_BUSTO(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_PRIEN */ +#define MCF_XLB_XARB_PRIEN_M0 (0x1) +#define MCF_XLB_XARB_PRIEN_M2 (0x4) +#define MCF_XLB_XARB_PRIEN_M3 (0x8) + +/* Bit definitions and macros for MCF_XLB_XARB_PRI */ +#define MCF_XLB_XARB_PRI_M0P(x) (((x)&0x7)<<0) +#define MCF_XLB_XARB_PRI_M2P(x) (((x)&0x7)<<0x8) +#define MCF_XLB_XARB_PRI_M3P(x) (((x)&0x7)<<0xC) + + +#endif /* __MCF5475_XLB_H__ */ diff --git a/tos/vmem_test/include/bas_printf.h b/tos/vmem_test/include/bas_printf.h new file mode 100644 index 0000000..ac44849 --- /dev/null +++ b/tos/vmem_test/include/bas_printf.h @@ -0,0 +1,35 @@ +/* + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + */ + +#ifndef _BAS_PRINTF_H_ +#define _BAS_PRINTF_H_ +#include +#include + +extern void xvsnprintf(char *str, size_t size, const char *fmt, va_list va); +extern void xvprintf(const char *fmt, va_list va); +extern void xprintf(const char *fmt, ...); +extern void xsnprintf(char *str, size_t size, const char *fmt, ...); +extern void xputchar(int c); +extern int sprintf(char *str, const char *format, ...); + + +extern void display_progress(void); +extern void hexdump(volatile uint8_t buffer[], int size); +#endif /* _BAS_PRINTF_H_ */ diff --git a/tos/vmem_test/include/bas_string.h b/tos/vmem_test/include/bas_string.h new file mode 100644 index 0000000..c743c95 --- /dev/null +++ b/tos/vmem_test/include/bas_string.h @@ -0,0 +1,47 @@ +/* + * bas_string.h + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 26.02.2013 + * Author: Markus Fröschle + */ + +#ifndef BAS_STRING_H_ +#define BAS_STRING_H_ + +#include + +extern int strncmp(const char *s1, const char *s2, size_t max); +extern char *strcpy(char *dst, const char *src); +char *strncpy(char *dst, const char *src, size_t max); +extern int strcmp(const char *s1, const char *s2); +extern size_t strlen(const char *str); +extern char *strcat(char *dst, const char *src); +extern char *strncat(char *dst, const char *src, size_t max); +extern int atoi(const char *c); +extern void *memcpy(void *dst, const void *src, size_t n); +extern void *memset(void *s, int c, size_t n); +extern int memcmp(const void *s1, const void *s2, size_t max); +extern void bzero(void *s, size_t n); + +#define isdigit(c) (((c) >= '0') && ((c) <= '9')) +#define isupper(c) ((c) >= 'A' && ((c) <= 'Z')) +#define islower(c) ((c) >= 'a' && ((c) <= 'z')) +#define isalpha(c) (isupper((c)) || islower(c)) +#define tolower(c) (isupper(c) ? ((c) + 'a' - 'A') : (c)) + +#endif /* BAS_STRING_H_ */ diff --git a/tos/vmem_test/include/driver_vec.h b/tos/vmem_test/include/driver_vec.h new file mode 100644 index 0000000..8b9352a --- /dev/null +++ b/tos/vmem_test/include/driver_vec.h @@ -0,0 +1,125 @@ +/* + * driver_vec.h + * + * Interface for exposure of BaS drivers to the OS + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 24.10.2013 + * Author: Markus Fröschle + */ + +#ifndef _DRIVER_VEC_H_ +#define _DRIVER_VEC_H_ + + +enum driver_type +{ + END_OF_DRIVERS, /* marks end of driver list */ + BLOCKDEV_DRIVER, + CHARDEV_DRIVER, + VIDEO_DRIVER, + XHDI_DRIVER, + MCD_DRIVER, +}; + +struct generic_driver_interface +{ + uint32_t (*init)(void); + uint32_t (*read)(void *buf, size_t count); + uint32_t (*write)(const void *buf, size_t count); + uint32_t (*ioctl)(uint32_t request, ...); +}; + + +/* Chained buffer descriptor */ +typedef volatile struct MCD_bufDesc_struct MCD_bufDesc; +struct MCD_bufDesc_struct { + uint32_t flags; /* flags describing the DMA */ + uint32_t csumResult; /* checksum from checksumming performed since last checksum reset */ + int8_t *srcAddr; /* the address to move data from */ + int8_t *destAddr; /* the address to move data to */ + int8_t *lastDestAddr; /* the last address written to */ + uint32_t dmaSize; /* the number of bytes to transfer independent of the transfer size */ + MCD_bufDesc *next; /* next buffer descriptor in chain */ + uint32_t info; /* private information about this descriptor; DMA does not affect it */ +}; + +/* Progress Query struct */ +typedef volatile struct MCD_XferProg_struct { + int8_t *lastSrcAddr; /* the most-recent or last, post-increment source address */ + int8_t *lastDestAddr; /* the most-recent or last, post-increment destination address */ + uint32_t dmaSize; /* the amount of data transferred for the current buffer */ + MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */ +} MCD_XferProg; + +struct dma_driver_interface +{ + int32_t version; + int32_t magic; + int32_t (*dma_set_initiator)(int initiator); + uint32_t (*dma_get_initiator)(int requestor); + void (*dma_free_initiator)(int requestor); + int32_t (*dma_set_channel)(int requestor, void (*handler)(void)); + int (*dma_get_channel)(int requestor); + void (*dma_free_channel)(int requestor); + void (*dma_clear_channel)(int channel); + int (*MCD_startDma)(int channel, int8_t *srcAddr, int16_t srcIncr, int8_t *destAddr, int16_t destIncr, + uint32_t dmaSize, uint32_t xferSize, uint32_t initiator, int32_t priority, uint32_t flags, + uint32_t funcDesc); + int (*MCD_dmaStatus)(int channel); + int (*MCD_XferProgrQuery)(int channel, MCD_XferProg *progRep); + int (*MCD_killDma)(int channel); + int (*MCD_continDma)(int channel); + int (*MCD_pauseDma)(int channel); + int (*MCD_resumeDma)(int channel); + int (*MCD_csumQuery)(int channel, uint32_t *csum); + void *(*dma_malloc)(long amount); + int (*dma_free)(void *addr); +}; + +struct xhdi_driver_interface +{ + uint32_t (*xhdivec)(); +}; + +union interface +{ + struct generic_driver_interface *gdi; + struct xhdi_driver_interface *xhdi; + struct dma_driver_interface *dma; +}; + +struct generic_interface +{ + enum driver_type type; + char name[16]; + char description[64]; + int version; + int revision; + union interface interface; +}; + +struct driver_table +{ + uint32_t bas_version; + uint32_t bas_revision; + uint32_t (*remove_handler)(); /* calling this will disable the BaS' hook into trap #0 */ + struct generic_interface *interfaces; +}; + + +#endif /* _DRIVER_VEC_H_ */ diff --git a/tos/vmem_test/sources/bas_printf.c b/tos/vmem_test/sources/bas_printf.c new file mode 100644 index 0000000..31691ce --- /dev/null +++ b/tos/vmem_test/sources/bas_printf.c @@ -0,0 +1,457 @@ +/* + * tc.printf.c: A public-domain, minimal printf/sprintf routine that prints + * through the putchar() routine. Feel free to use for + * anything... -- 7/17/87 Paul Placeway + */ +/*- + * Copyright (c) 1980, 1991 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +#include "MCF5475.h" +#include "bas_printf.h" +#include "bas_string.h" + +/* + * Lexical definitions. + * + * All lexical space is allocated dynamically. + * The eighth/sixteenth bit of characters is used to prevent recognition, + * and eventually stripped. + */ +#define META 0200 +#define ASCII 0177 +#define QUOTE ((char) 0200) /* Eighth char bit used for 'ing */ +#define TRIM 0177 /* Mask to strip quote bit */ +#define UNDER 0000000 /* No extra bits to do both */ +#define BOLD 0000000 /* Bold flag */ +#define STANDOUT META /* Standout flag */ +#define LITERAL 0000000 /* Literal character flag */ +#define ATTRIBUTES 0200 /* The bits used for attributes */ +#define CHAR 0000177 /* Mask to mask out the character */ + +#define INF 32766 /* should be bigger than any field to print */ + +static char snil[] = "(nil)"; + +void xputchar(int c) +{ + __asm__ __volatile__ + ( + ".extern printf_helper\n\t" + "move.b %0,d0\n\t" + "bsr printf_helper\n\t" + /* output */: + /* input */: "r" (c) + /* clobber */: "d0","d2","a0","memory" + ); +} + +static void doprnt(void (*addchar)(int), const char *sfmt, va_list ap) +{ + char buf[128]; + char *bp; + const char *f; + float flt; + long l; + unsigned long u; + int i; + int fmt; + unsigned char pad = ' '; + int flush_left = 0; + int f_width = 0; + int prec = INF; + int hash = 0; + int do_long = 0; + int sign = 0; + int attributes = 0; + + f = sfmt; + for (; *f; f++) + { + if (*f != '%') + { + /* then just out the char */ + (*addchar)((int) (((unsigned char) *f) | attributes)); + } + else + { + f++; /* skip the % */ + + if (*f == '-') + { /* minus: flush left */ + flush_left = 1; + f++; + } + + if (*f == '0' || *f == '.') + { + /* padding with 0 rather than blank */ + pad = '0'; + f++; + } + if (*f == '*') + { + /* field width */ + f_width = va_arg(ap, int); + f++; + } + else if (isdigit((unsigned char)*f)) + { + f_width = atoi(f); + while (isdigit((unsigned char)*f)) + f++; /* skip the digits */ + } + + if (*f == '.') + { /* precision */ + f++; + if (*f == '*') + { + prec = va_arg(ap, int); + f++; + } + else if (isdigit((unsigned char)*f)) + { + prec = atoi(f); + while (isdigit((unsigned char)*f)) + f++; /* skip the digits */ + } + } + + if (*f == '#') + { /* alternate form */ + hash = 1; + f++; + } + + if (*f == 'l') + { /* long format */ + do_long++; + f++; + if (*f == 'l') + { + do_long++; + f++; + } + } + + fmt = (unsigned char) *f; + if (fmt != 'S' && fmt != 'Q' && isupper(fmt)) + { + do_long = 1; + fmt = tolower(fmt); + } + bp = buf; + switch (fmt) + { /* do the format */ + case 'd': + switch (do_long) + { + case 0: + l = (long) (va_arg(ap, int)); + break; + case 1: + default: + l = va_arg(ap, long); + break; + } + + if (l < 0) + { + sign = 1; + l = -l; + } + do + { + *bp++ = (char) (l % 10) + '0'; + } while ((l /= 10) > 0); + if (sign) + *bp++ = '-'; + f_width = f_width - (int) (bp - buf); + if (!flush_left) + while (f_width-- > 0) + (*addchar)((int) (pad | attributes)); + for (bp--; bp >= buf; bp--) + (*addchar)((int) (((unsigned char) *bp) | attributes)); + if (flush_left) + while (f_width-- > 0) + (*addchar)((int) (' ' | attributes)); + break; + + case 'f': + /* this is actually more than stupid, but does work for now */ + flt = (float) (va_arg(ap, double)); /* beware: va_arg() extends float to double! */ + if (flt < 0) + { + sign = 1; + flt = -flt; + } + { + int quotient, remainder; + + quotient = (int) flt; + remainder = (flt - quotient) * 10E5; + + for (i = 0; i < 6; i++) + { + *bp++ = (char) (remainder % 10) + '0'; + remainder /= 10; + } + *bp++ = '.'; + do + { + *bp++ = (char) (quotient % 10) + '0'; + } while ((quotient /= 10) > 0); + if (sign) + *bp++ = '-'; + f_width = f_width - (int) (bp - buf); + if (!flush_left) + while (f_width-- > 0) + (*addchar)((int) (pad | attributes)); + for (bp--; bp >= buf; bp--) + (*addchar)((int) (((unsigned char) *bp) | attributes)); + if (flush_left) + while (f_width-- > 0) + (*addchar)((int) (' ' | attributes)); + } + break; + + case 'p': + do_long = 1; + hash = 1; + fmt = 'x'; + /* no break */ + case 'o': + case 'x': + case 'u': + switch (do_long) + { + case 0: + u = (unsigned long) (va_arg(ap, unsigned int)); + break; + case 1: + default: + u = va_arg(ap, unsigned long); + break; + } + if (fmt == 'u') + { /* unsigned decimal */ + do + { + *bp++ = (char) (u % 10) + '0'; + } while ((u /= 10) > 0); + } + else if (fmt == 'o') + { /* octal */ + do + { + *bp++ = (char) (u % 8) + '0'; + } while ((u /= 8) > 0); + if (hash) + *bp++ = '0'; + } + else if (fmt == 'x') + { /* hex */ + do + { + i = (int) (u % 16); + if (i < 10) + *bp++ = i + '0'; + else + *bp++ = i - 10 + 'a'; + } while ((u /= 16) > 0); + if (hash) + { + *bp++ = 'x'; + *bp++ = '0'; + } + } + i = f_width - (int) (bp - buf); + if (!flush_left) + while (i-- > 0) + (*addchar)((int) (pad | attributes)); + for (bp--; bp >= buf; bp--) + (*addchar)((int) (((unsigned char) *bp) | attributes)); + if (flush_left) + while (i-- > 0) + (*addchar)((int) (' ' | attributes)); + break; + + case 'c': + i = va_arg(ap, int); + (*addchar)((int) (i | attributes)); + break; + + case 'S': + case 'Q': + case 's': + case 'q': + bp = va_arg(ap, char *); + if (!bp) + bp = snil; + f_width = f_width - strlen((char *) bp); + if (!flush_left) + while (f_width-- > 0) + (*addchar)((int) (pad | attributes)); + for (i = 0; *bp && i < prec; i++) + { + if (fmt == 'q' && (*bp & QUOTE)) + (*addchar)((int) ('\\' | attributes)); + (*addchar)( + (int) (((unsigned char) *bp & TRIM) | attributes)); + bp++; + } + if (flush_left) + while (f_width-- > 0) + (*addchar)((int) (' ' | attributes)); + break; + + case 'a': + attributes = va_arg(ap, int); + break; + + case '%': + (*addchar)((int) ('%' | attributes)); + break; + + default: + break; + } + flush_left = 0, f_width = 0, prec = INF, hash = 0, do_long = 0; + sign = 0; + pad = ' '; + } + } +} + +static char *xstring, *xestring; + +void xaddchar(int c) +{ + if (xestring == xstring) + *xstring = '\0'; + else + *xstring++ = (char) c; +} + +int sprintf(char *str, const char *format, ...) +{ + va_list va; + va_start(va, format); + + xstring = str; + + doprnt(xaddchar, format, va); + va_end(va); + *xstring++ = '\0'; + + return 0; +} + +void xsnprintf(char *str, size_t size, const char *fmt, ...) +{ + va_list va; + va_start(va, fmt); + + xstring = str; + xestring = str + size - 1; + doprnt(xaddchar, fmt, va); + va_end(va); + *xstring++ = '\0'; +} + +void xprintf(const char *fmt, ...) +{ + va_list va; + va_start(va, fmt); + doprnt(xputchar, fmt, va); + va_end(va); +} + +void xvprintf(const char *fmt, va_list va) +{ + doprnt(xputchar, fmt, va); +} + +void xvsnprintf(char *str, size_t size, const char *fmt, va_list va) +{ + xstring = str; + xestring = str + size - 1; + doprnt(xaddchar, fmt, va); + *xstring++ = '\0'; +} + + +void display_progress() +{ + static int _progress_index; + char progress_char[] = "|/-\\"; + + xputchar(progress_char[_progress_index++ % strlen(progress_char)]); + xputchar('\r'); +} + +void hexdump(volatile uint8_t buffer[], int size) +{ + int i; + int line = 0; + volatile uint8_t *bp = buffer; + + while (bp < buffer + size) { + volatile uint8_t *lbp = bp; + + xprintf("%08x ", line); + + for (i = 0; i < 16; i++) { + uint8_t c = *lbp++; + if (bp + i > buffer + size) { + break; + } + xprintf("%02x ", c); + } + + lbp = bp; + for (i = 0; i < 16; i++) { + volatile int8_t c = *lbp++; + + if (bp + i > buffer + size) { + break; + } + if (c > ' ' && c < '~') { + xprintf("%c", c); + } else { + xprintf("."); + } + } + xprintf("\r\n"); + + bp += 16; + line += 16; + } +} diff --git a/tos/vmem_test/sources/bas_string.c b/tos/vmem_test/sources/bas_string.c new file mode 100644 index 0000000..b8d6a0f --- /dev/null +++ b/tos/vmem_test/sources/bas_string.c @@ -0,0 +1,156 @@ +/* + * bas_string.c + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 26.02.2013 + * Author: Markus Fröschle + */ + +#include "bas_types.h" +#include +#include "bas_string.h" + +void *memcpy(void *dst, const void *src, size_t n) +{ + uint8_t *to = dst; + + while (to < (uint8_t *) dst + n) + *to++ = * (uint8_t *) src++; + + return dst; +} + +void bzero(void *s, size_t n) +{ + size_t i; + + for (i = 0; i < n; i++) + ((unsigned char *) s)[i] = '\0'; +} + +void *memset(void *s, int c, size_t n) +{ + uint8_t *dst = s; + + do + { + *dst++ = c; + } while ((dst - (uint8_t *) s) < n); + + return s; +} + + +int memcmp(const void *s1, const void *s2, size_t max) +{ + int i; + int cmp; + + for (i = 0; i < max; i++) + { + cmp = (* (const char *) s1 - * (const char *) s2); + if (cmp != 0) return cmp; + } + return cmp; +} + +int strcmp(const char *s1, const char *s2) +{ + int i; + int cmp; + + for (i = 0; *s1++ && *s2++; i++) + { + cmp = (*s1 - *s2); + if (cmp != 0) return cmp; + } + return cmp; +} + +int strncmp(const char *s1, const char *s2, size_t max) +{ + int i; + int cmp; + + for (i = 0; i < max && *s1++ && *s2++; i++); + { + cmp = (*s1 - *s2); + if (cmp != 0) return cmp; + } + return cmp; +} + +char *strcpy(char *dst, const char *src) +{ + char *ptr = dst; + + while ((*dst++ = *src++) != '\0'); + return ptr; +} + +char *strncpy(char *dst, const char *src, size_t max) +{ + char *ptr = dst; + + while ((*dst++ = *src++) != '\0' && max-- >= 0); + return ptr; +} + +int atoi(const char *c) +{ + int value = 0; + while (isdigit(*c)) + { + value *= 10; + value += (int) (*c - '0'); + c++; + } + return value; +} + +size_t strlen(const char *s) +{ + const char *start = s; + + while (*s++); + + return s - start - 1; +} + + +char *strcat(char *dst, const char *src) +{ + char *ret = dst; + dst = &dst[strlen(dst)]; + while ((*dst++ = *src++) != '\0'); + return ret; +} + +char *strncat(char *dst, const char *src, size_t max) +{ + size_t i; + char *ret = dst; + + dst = &dst[strlen(dst)]; + for (i = 0; i < max && *src; i++) + { + *dst++ = *src++; + } + *dst++ = '\0'; + + return ret; +} diff --git a/tos/vmem_test/sources/printf_helper.S b/tos/vmem_test/sources/printf_helper.S new file mode 100644 index 0000000..e0b5c10 --- /dev/null +++ b/tos/vmem_test/sources/printf_helper.S @@ -0,0 +1,38 @@ +/* + * printf_helper.S + * + * assembler trampoline to let printf (compiled -mpcrel) indirectly reference __MBAR + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Copyright 2010 - 2012 F. Aschwanden + * Copyright 2011 - 2012 V. Riviere + * Copyright 2012 - 2025 M. Froeschle + */ + + + .globl printf_helper + +printf_helper: + .extern __MBAR + +.wait_txready: + move.w __MBAR+0x8604,d2 // PSCSCR0 status register + btst #10,d2 // space left in TX fifo? + beq.s .wait_txready // no, loop + lea __MBAR+0x860C,a0 // PSCSTB0 transmitter buffer register + move.b d0,(a0) // send byte + rts diff --git a/tos/vmem_test/sources/vmem_test.c b/tos/vmem_test/sources/vmem_test.c new file mode 100644 index 0000000..2730d07 --- /dev/null +++ b/tos/vmem_test/sources/vmem_test.c @@ -0,0 +1,390 @@ +#include +#include +#include +#include + +#include "bas_printf.h" +#include "MCF5475.h" +#include "driver_vec.h" + +#define FPGA_CONFIG (1 << 2) +#define FPGA_CONF_DONE (1 << 5) + +#define SRAM1_START 0xff101000 +#define SRAM1_END SRAM1_START + 0x1000 +#define SAFE_STACK SRAM1_END - 4 + +#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory") + +#define SYSCLK 132000 + +long bas_start = 0xe0000000; +extern volatile uint32_t _VRAM[]; + +volatile int32_t time, start, end; +int i; + +static void wait_pll(void) +{ + int32_t trgt = MCF_SLT0_SCNT - 100000; + do + { + ; + } while ((* (volatile int16_t *) 0xf0000800 < 0) && MCF_SLT0_SCNT > trgt); +} + +static volatile uint8_t *pll_base = (volatile uint8_t *) 0xf0000600; + +static void init_pll(void) +{ + xprintf("FPGA PLL initialization: "); + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x48) = 27; /* loopfilter r */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x08) = 1; /* charge pump 1 */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x00) = 12; /* N counter high = 12 */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x40) = 12; /* N counter low = 12 */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x114) = 1; /* ck1 bypass */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x118) = 1; /* ck2 bypass */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x11c) = 1; /* ck3 bypass */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x10) = 1; /* ck0 high = 1 */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x50) = 1; /* ck0 low = 1 */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x144) = 1; /* M odd division */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x44) = 1; /* M low = 1 */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x04) = 145; /* M high = 145 = 146 MHz */ + + wait_pll(); + + * (volatile uint8_t *) 0xf0000800 = 0; /* set */ + + xprintf("finished\r\n"); +} + +/* + * INIT VIDEO DDR RAM + */ +static void init_video_ddr(void) +{ + xprintf("init video RAM: "); + + * (volatile uint16_t *) 0xf0000400 = 0xb; /* set cke = 1, cs=1, config = 1 */ + NOP(); + + _VRAM[0] = 0x00050400; /* IPALL */ + NOP(); + + _VRAM[0] = 0x00072000; /* load EMR pll on */ + NOP(); + + _VRAM[0] = 0x00070122; /* load MR: reset pll, cl=2, burst=4lw */ + NOP(); + + _VRAM[0] = 0x00050400; /* IPALL */ + NOP(); + + _VRAM[0] = 0x00060000; /* auto refresh */ + NOP(); + + _VRAM[0] = 0x00060000; /* auto refresh */ + NOP(); + + /* FIXME: what's this? */ + _VRAM[0] = 0000070022; /* load MR dll on */ + NOP(); + + * (uint32_t *) 0xf0000400 = 0x01070002; /* fifo on, refresh on, ddrcs und cke on, video dac on */ + + xprintf("sys_ctr = 0x%08x\r\n", * (uint32_t *) 0xf0000400); + xprintf("finished\r\n"); +} + +void memmove_b(uint8_t *dst, volatile uint8_t *src, size_t size) +{ + while (--size) + { + *dst++ = *src++; + } +} + +void memmove_w(uint16_t *dst, volatile uint16_t *src, size_t size) +{ + size >>= 1; + + while (--size) + { + *dst++ = *src++; + } +} + +void memmove_l(uint32_t *dst, volatile uint32_t *src, size_t size) +{ + size >>= 2; + + while (--size) + { + *dst++ = *src++; + } +} + + +void do_tests(void) +{ + // uint32_t version; + const int buffer_size = 64; + uint8_t buffer[buffer_size * 4]; + + xprintf("initialize Firebee video PLL\r\n"); + init_pll(); + xprintf("finished\r\n"); + + xprintf("initialize video ddr memory\r\n"); + init_video_ddr(); + xprintf("finished\r\n"); + +#ifdef _NOT_USED_ + xprintf("try to read Configware version (only works on later configs)\r\n"); + version = * (uint32_t *) 0xffffffff; + + xprintf("version = 0x%08lx\r\n", version); +#endif /* _NOT_USED_ */ + + xprintf("try to access Firebee FPGA memory\r\n"); + + xprintf("write\r\n"); + start = MCF_SLT0_SCNT; + + /* + * fill 4 lines of video memory with 64 consecutive byte values + */ + for (i = 0; i < 64; i++) + { + ((uint8_t *) _VRAM)[i] = (uint32_t) i; + } + end = MCF_SLT0_SCNT; + time = (start - end) / (SYSCLK / 1000) / 1000; + + xprintf("finished (took %f seconds).\r\n", time / 1000.0); + + + /* + * read back video memory into local fast ram buffer + */ + + xprintf("read\r\n"); + start = MCF_SLT0_SCNT; + + /* + * read byte-wise + */ + xprintf("byte read\r\n"); + memmove_b(buffer, (uint8_t *) _VRAM, buffer_size); + end = MCF_SLT0_SCNT; + time = (start - end) / (SYSCLK / 1000) / 1000; + + xprintf("finished (took %f seconds).\r\n", time / 1000.0); + + hexdump(buffer, 64); + + + /* + * read word-wise + */ + xprintf("word read\r\n"); + memmove_w((uint16_t *) buffer, (uint16_t *) _VRAM, buffer_size); + end = MCF_SLT0_SCNT; + time = (start - end) / (SYSCLK / 1000) / 1000; + + xprintf("finished (took %f seconds).\r\n", time / 1000.0); + + hexdump(buffer, 64); + + /* + * read longword-wise + */ + xprintf("longword read\r\n"); + memmove_l((uint32_t *) buffer, (uint32_t *) _VRAM, buffer_size); + end = MCF_SLT0_SCNT; + time = (start - end) / (SYSCLK / 1000) / 1000; + + xprintf("finished (took %f seconds).\r\n", time / 1000.0); + + hexdump(buffer, 64); + + /* + * do some Firebee register tests + */ + + volatile uint8_t *dbasef = (volatile uint8_t *) 0xffff8200; + + xprintf("dbasef = 0x%02x\r\n", *dbasef); + *dbasef = 0x0; + xprintf("dbasef after clearing it = 0x%02x\r\n", *dbasef); + + volatile uint8_t *dbaseh = (volatile uint8_t *) 0xffff8201; + + xprintf("dbaseh = 0x%02x\r\n", *dbaseh); + *dbaseh = 0x0; + xprintf("dbaseh after clearing it = 0x%02x\r\n", *dbaseh); + + volatile uint8_t *dbasel = (volatile uint8_t *) 0xffff8203; + xprintf("dbasel = 0x%02x\r\n", *dbasel); + *dbasel = 0x0; + xprintf("dbasel after clearing it = 0x%02x\r\n", *dbasel); + + volatile uint8_t *dbaselow = (volatile uint8_t *) 0xffff820d; + xprintf("dbaselow = 0x%02x\r\n", *dbaselow); + *dbaselow = 0x0; + xprintf("dbaselow after clearing it = 0x%02x\r\n", *dbaselow); + + volatile uint16_t *linewidth = (volatile uint16_t *) 0xffff820e; + xprintf("linewidth = 0x%04x\r\n", *linewidth); + *linewidth = 0x0; + xprintf("linewidth after clearing it = 0x%04x\r\n", *linewidth); + *linewidth = 0x1234; + xprintf("linewidth after setting it to 0x1234 = 0x%04x\r\n", *linewidth); + + volatile uint16_t *vwrap = (volatile uint16_t *) 0xffff8210; + xprintf("VWRAP = 0x%04x\r\n", *vwrap); + *vwrap = 0; + xprintf("VWRAP after clearing it = 0x%04x\r\n", *vwrap); + *vwrap = 0x1234; + xprintf("VWRAP after setting it to 0x1234 = 0x%04x\r\n", *vwrap); +} + + + +void wait_for_jtag(void) +{ + long i; + + /* set supervisor stack to end of SRAM1 */ + __asm__ __volatile__ ( + " move #0x2700,sr\n\t" /* disable interrupts */ + " move.l %[stack],d0\n\t" /* 4KB on-chip core SRAM1 */ + " move.l d0,sp\n\t" /* set stack pointer */ + : + : [stack] "i" (SAFE_STACK) + : "d0", "cc" /* clobber */ + ); + + MCF_EPORT_EPIER = 0x0; /* disable EPORT interrupts */ + MCF_INTC_IMRL = 0xffffffff; + MCF_INTC_IMRH = 0xffffffff; /* disable interrupt controller */ + + MCF_MMU_MMUCR &= ~MCF_MMU_MMUCR_EN; /* disable MMU */ + + xprintf("relocated supervisor stack, disabled interrupts and disabled MMU\r\n"); + + /* + * configure FEC1L port directions to enable external JTAG configuration download to FPGA + */ + MCF_GPIO_PDDR_FEC1L = 0 | + MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4; /* bit 4 = LED => output */ + /* all other bits = input */ + + /* + * configure DSPI_CS3 as GPIO input to avoid the MCU driving against the FPGA blink + */ + MCF_PAD_PAR_DSPI &= ~MCF_PAD_PAR_DSPI_PAR_CS3(MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3); + /* + * now that GPIO ports have been switched to input, we can poll for FPGA config + * started from the JTAG interface (CONF_DONE goes low) and finish (CONF_DONE goes high) + */ + xprintf("waiting for JTAG configuration start\r\n"); + while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load started */ + + xprintf("waiting for JTAG configuration to finish\r\n"); + while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load finished */ + + xprintf("JTAG configuration finished.\r\n"); + + /* wait */ + xprintf("wait a little to let things settle...\r\n"); + for (i = 0; i < 100000L; i++); + + xprintf("disable caches\r\n"); + __asm__ __volatile( + "move.l #0x01000000,d0 \r\n" + "movec d0,CACR \r\n" + : /* no output */ + : /* no input */ + : "d0", "memory"); + + xprintf("init FPGA PLLs\r\n"); + init_pll(); + + xprintf("init video DDR RAM\r\n"); + init_video_ddr(); + + /* begin of tests */ + + do_tests(); + + xprintf("wait a little to let things settle...\r\n"); + for (i = 0; i < 100000L; i++); + + xprintf("INFO: endless loop now. Press reset to reboot\r\n"); + while (1) + ; +} + +int main(int argc, char *argv[]) +{ + printf("FPGA JTAG configuration support\r\n"); + printf("test FPGA DDR RAM controller\r\n"); + printf("\xbd 2014 M. F\x94schle\r\n"); + + printf("You may now savely load a new FPGA configuration through the JTAG interface\r\n" + "and your Firebee will reboot once finished using that new configuration.\r\n"); + if (argc == 2) + { + /* + * we got an argument. This is supposed to be the address that we need to jump to after JTAG + * configuration has been finished. Meant to support BaS in RAM testing + */ + char *addr_str = argv[1]; + char *addr = NULL; + char *end = NULL; + + addr = (char *) strtol(addr_str, &end, 16); + if (addr != NULL && addr <= (char *) 0xe0000000 && addr >= (char *) 0x10000000) + { + /* + * seems to be a valid address + */ + bas_start = (long) addr; + + printf("BaS start address set to %p\r\n", (void *) bas_start); + } + else + { + printf("\r\nNote: BaS start address %p not valid. Stick to %p.\r\n", addr, (void *) bas_start); + } + } + Supexec(wait_for_jtag); + + return 0; /* just to make the compiler happy, we will never return */ +} + diff --git a/tos/vmem_test/vmem_test.config b/tos/vmem_test/vmem_test.config new file mode 100644 index 0000000..8cec188 --- /dev/null +++ b/tos/vmem_test/vmem_test.config @@ -0,0 +1 @@ +// ADD PREDEFINED MACROS HERE! diff --git a/tos/vmem_test/vmem_test.creator b/tos/vmem_test/vmem_test.creator new file mode 100644 index 0000000..e94cbbd --- /dev/null +++ b/tos/vmem_test/vmem_test.creator @@ -0,0 +1 @@ +[General] diff --git a/tos/vmem_test/vmem_test.files b/tos/vmem_test/vmem_test.files new file mode 100644 index 0000000..d4c5c1a --- /dev/null +++ b/tos/vmem_test/vmem_test.files @@ -0,0 +1,7 @@ +include/driver_vec.h +sources/jtagwait.c +Makefile +sources/bas_printf.c +sources/bas_string.c +sources/printf_helper.S +sources/vmem_test.c diff --git a/tos/vmem_test/vmem_test.includes b/tos/vmem_test/vmem_test.includes new file mode 100644 index 0000000..0e46827 --- /dev/null +++ b/tos/vmem_test/vmem_test.includes @@ -0,0 +1,2 @@ +include +/usr/m68k-atari-mint/include diff --git a/usb/usb.c b/usb/usb.c new file mode 100644 index 0000000..c947bc4 --- /dev/null +++ b/usb/usb.c @@ -0,0 +1,1353 @@ +/* + * + * Most of this source has been derived from the Linux USB + * project: + * (C) Copyright Linus Torvalds 1999 + * (C) Copyright Johannes Erdfelt 1999-2001 + * (C) Copyright Andreas Gal 1999 + * (C) Copyright Gregory P. Smith 1999 + * (C) Copyright Deti Fliegl 1999 (new USB architecture) + * (C) Copyright Randy Dunlap 2000 + * (C) Copyright David Brownell 2000 (kernel hotplug, usb_device_id) + * (C) Copyright Yggdrasil Computing, Inc. 2000 + * (usb_device_id matching changes by Adam J. Richter) + * + * Adapted for U-Boot: + * (C) Copyright 2001 Denis Peter, MPL AG Switzerland + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * How it works: + * + * Since this is a bootloader, the devices will not be automatic + * (re)configured on hotplug, but after a restart of the USB the + * device should work. + * + * For each transfer (except "Interrupt") we wait for completion. + */ + +#include +#include "bas_string.h" +#include "bas_printf.h" +#include "util.h" /* for byte swap funcs */ +#include "wait.h" +#include +#include "usb.h" +#include "usb_hub.h" + +// #define DEBUG +#include "debug.h" + +struct hci +{ + /* ------- common part -------- */ + long handle; /* PCI BIOS */ + const struct pci_device_id *ent; + int usbnum; + /* ---- end of common part ---- */ +}; + +static struct usb_device *usb_dev; +int bus_index; +static int dev_index[USB_MAX_BUS]; +static struct hci *controller_priv[USB_MAX_BUS]; +static int asynch_allowed; +static struct devrequest *setup_packet; + +char usb_started; /* flag for the started/stopped USB status */ + + +/* + * some forward declarations... + */ +void usb_scan_devices(void *priv); + +/* + * Init USB device controller + */ +int usb_init(int32_t handle, const struct pci_device_id *ent) +{ + struct hci *priv; + int res = 0; + + bus_index = 0; + if (bus_index >= USB_MAX_BUS) + { + dbg("bus_index >= USB_MAX_BUS"); + return -1; + } + + dev_index[bus_index] = 0; + asynch_allowed = 1; + + if (handle && (ent != NULL)) + { + if (driver_mem_init()) + { + usb_started = 0; + dbg("driver_mem_init failed\r\n"); + + return -1; /* out of memory */ + } + + if (usb_dev == NULL) + { + usb_dev = (struct usb_device *) driver_mem_alloc(sizeof(struct usb_device) * USB_MAX_BUS * USB_MAX_DEVICE); + } + + if (usb_dev == NULL) + { + usb_started = 0; + + dbg("could not allocate memory\r\n"); + + return -1; /* out of memory */ + } + } + else /* restart */ + { + int i; + + res = 0; + for (i = 0; i < USB_MAX_BUS; i++) + { + if (controller_priv[i] != NULL) + { + long hdl = controller_priv[i]->handle; + + if (hdl) + { + res |= usb_init(handle, NULL); /* FIXME: recursive call!? */ + } + } + } + return res; + } + + usb_hub_reset(bus_index); + + /* init low_level USB */ + + switch(ent->class) + { + case PCI_CLASS_SERIAL_USB_UHCI: + //res = uhci_usb_lowlevel_init(handle, ent, &priv); + dbg("sorry, no uhci driver available\r\n"); + break; + + case PCI_CLASS_SERIAL_USB_OHCI: + dbg("initialize ohci host controller interface\r\n"); + res = ohci_usb_lowlevel_init(handle, ent, (void *) &priv); + break; + + case PCI_CLASS_SERIAL_USB_EHCI: + dbg("initialize ehci host controller interface\r\n"); + res = ehci_usb_lowlevel_init(handle, ent, (void *) &priv); + break; + + default: + res = -1; + break; + } + + if (!res) + { + /* + * if lowlevel init is OK, scan the bus for devices + * i.e. search HUBs and configure them + */ + if (setup_packet == NULL) + { + setup_packet = driver_mem_alloc(sizeof(struct devrequest)); + if (setup_packet == NULL) + { + usb_started = 0; + + dbg("could not allocate memory\r\n"); + + return -1; /* no memory, no USB */ + } + } + + xprintf("Scanning bus for devices... "); + + controller_priv[bus_index] = priv; + controller_priv[bus_index]->usbnum = bus_index; + + usb_scan_devices(priv); + bus_index++; + usb_started = 1; + + xprintf("done.\r\n"); + + return 0; + } + else + { + xprintf("\r\nError, couldn't init Lowlevel part\r\n"); + usb_started = 0; + + return -1; + } +} + +/* + * Stop USB. This stops the LowLevel Part and deregisters USB devices. + */ +int usb_stop(void) +{ + int i; + int res = 0; + + if (usb_started) + { + asynch_allowed = 1; + usb_started = 0; + usb_hub_reset(bus_index); + driver_mem_free(setup_packet); + for (i = 0; i < USB_MAX_BUS; i++) + { + struct hci *priv = controller_priv[i]; + if (priv != NULL) + { + switch(priv->ent->class) + { +#ifdef CONFIG_USB_UHCI + case PCI_CLASS_SERIAL_USB_UHCI: + res |= uhci_usb_lowlevel_stop(priv); + break; +#endif +#ifdef CONFIG_USB_OHCI + case PCI_CLASS_SERIAL_USB_OHCI: + res |= ohci_usb_lowlevel_stop(priv); + break; +#endif +#ifdef CONFIG_USB_EHCI + case PCI_CLASS_SERIAL_USB_EHCI: + res |= ehci_usb_lowlevel_stop(priv); + break; +#endif + } + } + } + bus_index = 0; + driver_mem_release(); /* release all driver mem */ + } + return res; +} + + +void usb_enable_interrupt(int enable) +{ + ohci_usb_enable_interrupt(enable); + ehci_usb_enable_interrupt(enable); +} + + +/* + * disables the asynch behaviour of the control message. This is used for data + * transfers that uses the exclusiv access to the control and bulk messages. + */ +void usb_disable_asynch(int disable) +{ + asynch_allowed = !disable; +} + +/* + * Message wrappers. + * + */ + +/* + * submits an Interrupt Message + */ +int usb_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval) +{ + struct hci *priv = (struct hci *) dev->priv_hcd; + int ret = 0; + + switch(priv->ent->class) + { + case PCI_CLASS_SERIAL_USB_OHCI: + ret = ohci_submit_int_msg(dev, pipe, buffer, transfer_len, interval); + break; + + case PCI_CLASS_SERIAL_USB_EHCI: + ret = ehci_submit_int_msg(dev, pipe, buffer, transfer_len, interval); + break; + + default: + ret = -1; + break; + } + return ret; +} + +/* + * submits a control message and waits for completion (at least timeout * 1ms) + * If timeout is 0, we don't wait for completion (used for example to set and + * clear keyboards LEDs). For data transfers, (storage transfers) we don't + * allow control messages with 0 timeout, by previousely resetting the flag + * asynch_allowed (usb_disable_asynch(1)). + * returns the transfered length if OK or -1 if error. The transfered length + * and the current status are stored in the dev->act_len and dev->status. + */ +int usb_control_msg(struct usb_device *dev, unsigned int pipe, + unsigned char request, unsigned char requesttype, + unsigned short value, unsigned short index, + void *data, unsigned short size, int timeout) +{ + struct hci *priv = (struct hci *) dev->priv_hcd; + + if ((timeout == 0) && (!asynch_allowed)) + { + /* request for a asynch control pipe is not allowed */ + + err("request for an async control pipe is not allowed\r\n"); + return -1; + } + + /* set setup command */ + setup_packet->requesttype = requesttype; + setup_packet->request = request; + setup_packet->value = swpw(value); + setup_packet->index = swpw(index); + setup_packet->length = swpw(size); + + dbg("request: 0x%X, requesttype: 0x%X, value 0x%X index 0x%X length 0x%X\r\n", request, requesttype, value, index, size); + + switch (priv->ent->class) + { + case PCI_CLASS_SERIAL_USB_OHCI: + dev->status = USB_ST_NOT_PROC; /* not yet processed */ + ohci_submit_control_msg(dev, pipe, data, size, setup_packet); + break; + + case PCI_CLASS_SERIAL_USB_EHCI: + dev->status = USB_ST_NOT_PROC; /* not yet processed */ + ehci_submit_control_msg(dev, pipe, data, size, setup_packet); + break; + + default: + return -1; + } + + if (timeout == 0) + { + return (int) size; + } + + if (dev->status != 0) + { + /* + * Let's wait a while for the timeout to elapse. + * It has no real use, but it keeps the interface happy. + */ + return -1; + } + return dev->act_len; +} + +/* + * submits bulk message, and waits for completion. returns 0 if Ok or + * -1 if Error. + * synchronous behavior + */ +int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, void *data, int len, int *actual_length, int timeout) +{ + struct hci *priv = (struct hci *) dev->priv_hcd; + + if (len < 0) + { + return -1; + } + + switch(priv->ent->class) + { + case PCI_CLASS_SERIAL_USB_OHCI: + dev->status = USB_ST_NOT_PROC; /* not yet processed */ + ohci_submit_bulk_msg(dev, pipe, data, len); + break; + + case PCI_CLASS_SERIAL_USB_EHCI: + dev->status = USB_ST_NOT_PROC; /* not yet processed */ + ehci_submit_bulk_msg(dev, pipe, data, len); + break; + + default: + return -1; + } + + while (timeout--) + { + if (!((volatile uint32_t) dev->status & USB_ST_NOT_PROC)) /* FIXME: this volatile does nothing! */ + break; + wait(1); + } + + *actual_length = dev->act_len; + + if (dev->status == 0) + { + return 0; + } + else + { + return -1; + } +} + + +/* + * Max Packet stuff + */ + +/* + * returns the max packet size, depending on the pipe direction and + * the configurations values + */ +int usb_maxpacket(struct usb_device *dev, uint32_t pipe) +{ + /* direction is out -> use emaxpacket out */ + if ((pipe & USB_DIR_IN) == 0) + { + return dev->epmaxpacketout[((pipe >> 15) & 0xf)]; + } + else + { + return dev->epmaxpacketin[((pipe >> 15) & 0xf)]; + } +} + +/* + * The routine usb_set_maxpacket_ep() is extracted from the loop of routine + * usb_set_maxpacket(), because the optimizer of GCC 4.x chokes on this routine + * when it is inlined in 1 single routine. What happens is that the register r3 + * is used as loop-count 'i', but gets overwritten later on. + * This is clearly a compiler bug, but it is easier to workaround it here than + * to update the compiler (Occurs with at least several GCC 4.{1,2},x + * CodeSourcery compilers like e.g. 2007q3, 2008q1, 2008q3 lite editions on ARM) + * + * We probably do not need that for Coldfire - at least I hope so. + */ +static void usb_set_maxpacket_ep(struct usb_device *dev, struct usb_endpoint_descriptor *ep) +{ + int b; + + b = ep->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + + if ((ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_CONTROL) + { + /* Control => bidirectional */ + dev->epmaxpacketout[b] = ep->wMaxPacketSize; + dev->epmaxpacketin[b] = ep->wMaxPacketSize; + dbg("##Control EP epmaxpacketout/in[%d] = %d\r\n", b, dev->epmaxpacketin[b]); + } + else + { + if ((ep->bEndpointAddress & 0x80) == 0) + { + /* OUT Endpoint */ + if (ep->wMaxPacketSize > dev->epmaxpacketout[b]) + { + dev->epmaxpacketout[b] = ep->wMaxPacketSize; + dbg("##EP epmaxpacketout[%d] = %d\r\n", b, dev->epmaxpacketout[b]); + } + } + else + { + /* IN Endpoint */ + if (ep->wMaxPacketSize > dev->epmaxpacketin[b]) + { + dev->epmaxpacketin[b] = ep->wMaxPacketSize; + dbg("##EP epmaxpacketin[%d] = %d\r\n", b, dev->epmaxpacketin[b]); + } + } /* if out */ + } /* if control */ +} + +/* + * set the max packed value of all endpoints in the given configuration + */ +int usb_set_maxpacket(struct usb_device *dev) +{ + int i; + int ii; + + for (i = 0; i < dev->config.bNumInterfaces; i++) + { + for (ii = 0; ii < dev->config.if_desc[i].bNumEndpoints; ii++) + { + usb_set_maxpacket_ep(dev,&dev->config.if_desc[i].ep_desc[ii]); + } + } + return 0; +} + +/* + * Parse the config, located in buffer, and fills the dev->config structure. + * Note that all little/big endian swapping are done automatically. + */ +int usb_parse_config(struct usb_device *dev, unsigned char *buffer, int cfgno) +{ + struct usb_descriptor_header *head; + int index; + int ifno; + int epno; + int curr_if_num; + + ifno = -1; + epno = -1; + curr_if_num = -1; + dev->configno = cfgno; + head = (struct usb_descriptor_header *) &buffer[0]; + + if (head->bDescriptorType != USB_DT_CONFIG) + { + dbg(" ERROR: NOT USB_CONFIG_DESC (0x%x instead of 0x%x)\r\n", head->bDescriptorType, USB_DT_CONFIG); + return -1; + } + memcpy(&dev->config, buffer, buffer[0]); + dev->config.wTotalLength = swpw(dev->config.wTotalLength); + dev->config.no_of_if = 0; + index = dev->config.bLength; + + /* + * Ok the first entry must be a configuration entry, + * now process the others + */ + head = (struct usb_descriptor_header *) &buffer[index]; + + while (index + 1 < dev->config.wTotalLength) + { + switch (head->bDescriptorType) + { + case USB_DT_INTERFACE: + if (((struct usb_interface_descriptor *) &buffer[index])->bInterfaceNumber != curr_if_num) + { + /* this is a new interface, copy new desc */ + ifno = dev->config.no_of_if; + dev->config.no_of_if++; + memcpy(&dev->config.if_desc[ifno], &buffer[index], buffer[index]); + dev->config.if_desc[ifno].no_of_ep = 0; + dev->config.if_desc[ifno].num_altsetting = 1; + curr_if_num = dev->config.if_desc[ifno].bInterfaceNumber; + } + else + { + /* found alternate setting for the interface */ + dev->config.if_desc[ifno].num_altsetting++; + } + break; + + case USB_DT_ENDPOINT: + epno = dev->config.if_desc[ifno].no_of_ep; + /* found an endpoint */ + dev->config.if_desc[ifno].no_of_ep++; + memcpy(&dev->config.if_desc[ifno].ep_desc[epno], &buffer[index], buffer[index]); + dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize = swpw(dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize); + dbg("if %d, ep %d\r\n", ifno, epno); + break; + + default: + if (head->bLength == 0) + return 1; + dbg("unknown Descriptor Type : %x\r\n", head->bDescriptorType); +#ifdef USB_DEBUG + { + unsigned char *ch; + int i; + + ch = (unsigned char *) head; + for (i = 0; i < head->bLength; i++) + { + dbg(" %02X", *ch++); + } + dbg("\r\n"); + } +#endif /* USB_DEBUG */ + break; + } + index += head->bLength; + head = (struct usb_descriptor_header *) &buffer[index]; + } + return 1; +} + +/* + * Clears an endpoint + * endp: endpoint number in bits 0-3; + * direction flag in bit 7 (1 = IN, 0 = OUT) + */ +int usb_clear_halt(struct usb_device *dev, int pipe) +{ + int result; + int endp = usb_pipeendpoint(pipe) | (usb_pipein(pipe) << 7); + + result = usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_CLEAR_FEATURE, USB_RECIP_ENDPOINT, 0, endp, NULL, 0, USB_CNTL_TIMEOUT * 3); + + /* don't clear if failed */ + if (result < 0) + { + return result; + } + + /* + * NOTE: we do not get status and verify reset was successful + * as some devices are reported to lock up upon this check.. + */ + usb_endpoint_running(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); + + /* toggle is reset on clear */ + usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 0); + + return 0; +} + +/* + * get_descriptor type + */ +int usb_get_descriptor(struct usb_device *dev, unsigned char type, unsigned char index, void *buf, int size) +{ + int res; + + dbg("dev=%d type=%d, index=%d\r\n", dev->devnum, type, index); + res = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + USB_REQ_GET_DESCRIPTOR, USB_DIR_IN, (type << 8) + index, 0, buf, size, USB_CNTL_TIMEOUT); + return res; +} + +/* + * gets configuration cfgno and store it in the buffer + */ +int usb_get_configuration_no(struct usb_device *dev, unsigned char *buffer, int cfgno) +{ + int result; + unsigned int tmp; + struct usb_config_descriptor *config; + + config = (struct usb_config_descriptor *) &buffer[0]; + result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, 9); + + if (result < 9) + { + if (result < 0) + { + dbg("unable to get descriptor, error %lX\r\n", dev->status); + } + else + { + dbg("config descriptor too short (expected %i, got %i)\n", 9, result); + } + return -1; + } + + tmp = swpw(config->wTotalLength); + + if (tmp > USB_BUFSIZ) + { + dbg("usb_get_configuration_no: failed to get descriptor - too long: %d\r\n", tmp); + return -1; + } + result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, tmp); + dbg("get_conf_no %d Result %d, wLength %d\r\n", cfgno, result, tmp); + + return result; +} + +/* + * set address of a device to the value in dev->devnum. + * This can only be done by addressing the device via the default address (0) + */ +int usb_set_address(struct usb_device *dev) +{ + int res; + + dbg("set address %d\r\n", dev->devnum); + res = usb_control_msg(dev, usb_snddefctrl(dev), USB_REQ_SET_ADDRESS, 0, (dev->devnum), 0, NULL, 0, USB_CNTL_TIMEOUT); + return res; +} + +/* + * set interface number to interface + */ +int usb_set_interface(struct usb_device *dev, int interface, int alternate) +{ + struct usb_interface_descriptor *if_face = NULL; + int ret, i; + + dbg("set interface number=%d (alternate=%d)\r\n", interface, alternate); + + for (i = 0; i < dev->config.bNumInterfaces; i++) + { + if (dev->config.if_desc[i].bInterfaceNumber == interface) + { + if_face = &dev->config.if_desc[i]; + + break; + } + } + + if (!if_face) + { + dbg("selecting invalid interface %d", interface); + + return -1; + } + + /* + * We should return now for devices with only one alternate setting. + * According to 9.4.10 of the Universal Serial Bus Specification + * Revision 2.0 such devices can return with a STALL. This results in + * some USB sticks timeouting during initialization and then being + * unusable in U-Boot. + */ + if (if_face->num_altsetting == 1) + { + return 0; + } + + ret = usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_SET_INTERFACE, USB_RECIP_INTERFACE, alternate, interface, NULL, 0, USB_CNTL_TIMEOUT * 5); + if (ret < 0) + { + return ret; + } + + return 0; +} + +/* + * set configuration number to configuration + */ +int usb_set_configuration(struct usb_device *dev, int configuration) +{ + int res; + + dbg("set configuration %d\r\n", configuration); + /* set setup command */ + res = usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_SET_CONFIGURATION, 0, configuration, 0, NULL, 0, USB_CNTL_TIMEOUT); + if (res == 0) + { + dev->toggle[0] = 0; + dev->toggle[1] = 0; + + return 0; + } + else + { + return -1; + } +} + +/* + * set protocol to protocol + */ +int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol) +{ + dbg("set protocol %d on interface %d\r\n", protocol, ifnum); + + return usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_SET_PROTOCOL, USB_TYPE_CLASS | USB_RECIP_INTERFACE, + protocol, ifnum, NULL, 0, USB_CNTL_TIMEOUT); +} + +/* + * set idle + */ +int usb_set_idle(struct usb_device *dev, int ifnum, int duration, int report_id) +{ + dbg("set if %d idle for %d (report id %d)\r\n", ifnum, duration, report_id); + + return usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_SET_IDLE, USB_TYPE_CLASS | USB_RECIP_INTERFACE, + (duration << 8) | report_id, ifnum, NULL, 0, USB_CNTL_TIMEOUT); +} + +/* + * get report + */ +int usb_get_report(struct usb_device *dev, int ifnum, unsigned char type, + unsigned char id, void *buf, int size) +{ + dbg("get report on if %d, type %d, id %d\r\n", ifnum, type, id); + + return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + USB_REQ_GET_REPORT, USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE, + (type << 8) + id, ifnum, buf, size, USB_CNTL_TIMEOUT); +} + +/* + * get class descriptor + */ +int usb_get_class_descriptor(struct usb_device *dev, int ifnum, + unsigned char type, unsigned char id, void *buf, int size) +{ + dbg("get class descriptor of if %d, type %d, id %d\r\n", ifnum, type, id); + + return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + USB_REQ_GET_DESCRIPTOR, USB_RECIP_INTERFACE | USB_DIR_IN, + (type << 8) + id, ifnum, buf, size, USB_CNTL_TIMEOUT); +} + +/* + * get string index in buffer + */ +int usb_get_string(struct usb_device *dev, unsigned short langid, unsigned char index, void *buf, int size) +{ + int i; + int result; + + for (i = 0; i < 3; ++i) + { + /* some devices are flaky */ + result = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), USB_REQ_GET_DESCRIPTOR, USB_DIR_IN, + (USB_DT_STRING << 8) + index, langid, buf, size, USB_CNTL_TIMEOUT); + if (result > 0) + { + break; + } + } + return result; +} + +static void usb_try_string_workarounds(unsigned char *buf, int *length) +{ + int newlength; + int oldlength = *length; + + for (newlength = 2; newlength + 1 < oldlength; newlength += 2) + { + char c = buf[newlength]; + + if ((c < ' ') || (c >= 127) || buf[newlength + 1]) + break; + } + + if (newlength > 2) + { + buf[0] = newlength; + *length = newlength; + } +} + +static int usb_string_sub(struct usb_device *dev, unsigned int langid, unsigned int index, unsigned char *buf) +{ + int rc; + + /* + * Try to read the string descriptor by asking for the maximum + * possible number of bytes + */ + rc = usb_get_string(dev, langid, index, buf, 255); + + /* + * If that failed try to read the descriptor length, then + * ask for just that many bytes + */ + if (rc < 2) + { + rc = usb_get_string(dev, langid, index, buf, 2); + if (rc == 2) + { + rc = usb_get_string(dev, langid, index, buf, buf[0]); + } + } + + if (rc >= 2) + { + if (!buf[0] && !buf[1]) + { + usb_try_string_workarounds(buf, &rc); + } + + /* There might be extra junk at the end of the descriptor */ + if (buf[0] < rc) + { + rc = buf[0]; + } + rc = rc - (rc & 1); /* force a multiple of two */ + } + + if (rc < 2) + { + rc = -1; + } + + return rc; +} + +/* + * usb_string: + * Get string index and translate it to ascii. + * returns string length (> 0) or error (< 0) + */ +int usb_string(struct usb_device *dev, int index, char *buf, size_t size) +{ + unsigned char *tbuf; + int error; + unsigned int u, idx; + + if (size <= 0 || !buf || !index) + { + return -1; + } + + buf[0] = 0; + tbuf = (unsigned char *) driver_mem_alloc(USB_BUFSIZ); + + if (tbuf == NULL) + { + dbg("usb_string: malloc failure\r\n"); + return -1; + } + + /* get langid for strings if it's not yet known */ + if (!dev->have_langid) + { + error = usb_string_sub(dev, 0, 0, tbuf); + if (error < 0) + { + err("error getting string descriptor 0 (error=%lx)\r\n", dev->status); + driver_mem_free(tbuf); + return -1; + } + else if (tbuf[0] < 4) + { + err("string descriptor 0 too short\r\n"); + driver_mem_free(tbuf); + return -1; + } + else + { + dev->have_langid = -1; + dev->string_langid = tbuf[2] | (tbuf[3] << 8); + /* always use the first langid listed */ + dbg("USB device number %d default language ID 0x%x\r\n", dev->devnum, dev->string_langid); + } + } + error = usb_string_sub(dev, dev->string_langid, index, tbuf); + if (error < 0) + { + err("failed to get lang id\r\n"); + driver_mem_free(tbuf); + return error; + } + + size--; /* leave room for trailing NULL char in output buffer */ + for (idx = 0, u = 2; u < error; u += 2) + { + if (idx >= size) + { + break; + } + if (tbuf[u + 1]) /* high byte */ + { + buf[idx++] = '?'; /* non-ASCII character */ + } + else + { + buf[idx++] = tbuf[u]; + } + } + buf[idx] = 0; + error = idx; + driver_mem_free(tbuf); + return error; +} + +/* + * USB device handling: + * the USB device are static allocated [USB_MAX_DEVICE]. + */ + +/* + * Something got disconnected. Get rid of it, and all of its children. + */ +void usb_disconnect(struct usb_device **pdev) +{ + struct usb_device *dev = *pdev; + if (dev != NULL) + { + int i; + + dbg("USB %d disconnect on device %d\r\n", dev->parent->usbnum, dev->parent->devnum); + dbg("USB %d disconnected, device number %d\r\n", dev->usbnum, dev->devnum); + + if (dev->deregister != NULL) + { + dev->deregister(dev); + } + + /* Free up all the children.. */ + for (i = 0; i < USB_MAXCHILDREN; i++) + { + if (dev->children[i] != NULL) + { + dbg("USB %d, disconnect children %d\r\n", dev->usbnum, dev->children[i]->devnum); + usb_disconnect(&dev->children[i]); + dev->children[i] = NULL; + } + } + + /* Free up the device itself, including its device number */ + if (dev->devnum > 0) + { + dev_index[dev->usbnum]--; + memset(dev, 0, sizeof(struct usb_device)); + dev->devnum = -1; + } + *pdev = NULL; + } +} + +/* + * returns a pointer to the device with the index [index]. + * if the device is not assigned (dev->devnum==-1) returns NULL + */ +struct usb_device *usb_get_dev_index(int index, int index_bus) +{ + struct usb_device *dev; + + if ((index_bus >= USB_MAX_BUS) || (index_bus < 0) + || (index >= USB_MAX_DEVICE) || (index < 0)) + { + return NULL; + } + + dev = &usb_dev[(index_bus * USB_MAX_DEVICE) + index]; + + if ((controller_priv[index_bus] == NULL) || (dev->devnum == -1)) + { + return NULL; + } + + return dev; +} + +/* + * returns a pointer of a new device structure or NULL, if + * no device struct is available + */ +struct usb_device *usb_alloc_new_device(int bus, void *priv) +{ + int i; + int index = dev_index[bus]; + struct usb_device *dev; + + dbg("USB %d new device %d\r\n", bus, index); + if (index >= USB_MAX_DEVICE) + { + dbg("ERROR, too many USB Devices, max=%d\r\n", USB_MAX_DEVICE); + return NULL; + } + + /* default Address is 0, real addresses start with 1 */ + dev = &usb_dev[(bus * USB_MAX_DEVICE) + index]; + dev->devnum = index + 1; + dev->maxchild = 0; + + for (i = 0; i < USB_MAXCHILDREN; dev->children[i++] = NULL) + ; + + dev->parent = NULL; + dev->priv_hcd = priv; + dev->usbnum = bus; + dev_index[bus]++; + + return dev; +} + +// #define CONFIG_LEGACY_USB_INIT_SEQ +/* + * By the time we get here, the device has gotten a new device ID + * and is in the default state. We need to identify the thing and + * get the ball rolling.. + * + * Returns 0 for success, != 0 for error. + */ +int usb_new_device(struct usb_device *dev) +{ + int addr; + int error; + int tmp; + unsigned char *tmpbuf; + +#ifndef CONFIG_LEGACY_USB_INIT_SEQ + struct usb_device_descriptor *desc; + int port = -1; + struct usb_device *parent = dev->parent; + unsigned short portstatus; +#endif + + if (dev == NULL) + { + err("called with NULL device\r\n"); + return 1; + } + + /* We still haven't set the Address yet */ + addr = dev->devnum; + dev->devnum = 0; + + tmpbuf = (unsigned char *) driver_mem_alloc(USB_BUFSIZ); + if (tmpbuf == NULL) + { + err("malloc failure\r\n"); + return 1; + } + +//#define CONFIG_LEGACY_USB_INIT_SEQ +#ifdef CONFIG_LEGACY_USB_INIT_SEQ + /* + * this is the old and known way of initializing devices, it is + * different than what Windows and Linux are doing. Windows and Linux + * both retrieve 64 bytes while reading the device descriptor + * Several USB stick devices report ERR: CTL_TIMEOUT, caused by an + * invalid header while reading 8 bytes as device descriptor. + */ + dev->descriptor.bMaxPacketSize0 = 8; /* Start off at 8 bytes */ + dev->maxpacketsize = PACKET_SIZE_8; + dev->epmaxpacketin[0] = 8; + dev->epmaxpacketout[0] = 8; + error = usb_get_descriptor(dev, USB_DT_DEVICE, 0, &dev->descriptor, 8); + if (err < 8) + { + err("\r\nUSB device not responding, giving up (status=%lX)\r\n", dev->status); + driver_mem_free(tmpbuf); + return 1; + } +#else + /* + * This is a Windows scheme of initialization sequence, with double + * reset of the device (Linux uses the same sequence) + * Some equipment is said to work only with such init sequence; this + * patch is based on the work by Alan Stern: + * http://sourceforge.net/mailarchive/forum.php? + * thread_id=5729457&forum_id=5398 + */ + + /* + * send 64-byte GET-DEVICE-DESCRIPTOR request. Since the descriptor is + * only 18 bytes long, this will terminate with a short packet. But if + * the maxpacket size is 8 or 16 the device may be waiting to transmit + * some more, or keeps on retransmitting the 8 byte header. + */ + desc = (struct usb_device_descriptor *) tmpbuf; + dev->descriptor.bMaxPacketSize0 = 64; /* Start off at 64 bytes */ + + /* Default to 64 byte max packet size */ + dev->maxpacketsize = PACKET_SIZE_64; + dev->epmaxpacketin[0] = 64; + dev->epmaxpacketout[0] = 64; + error = usb_get_descriptor(dev, USB_DT_DEVICE, 0, desc, 64); + + if (error < 0) + { + err("usb_new_device: usb_get_descriptor() failed\r\n"); + driver_mem_free(tmpbuf); + return 1; + } + dev->descriptor.bMaxPacketSize0 = desc->bMaxPacketSize0; + + /* find the port number we're at */ + if (parent) + { + int j; + for (j = 0; j < parent->maxchild; j++) + { + if (parent->children[j] == dev) + { + port = j; + break; + } + } + dbg("port = %d\r\n", port); + + if (port < 0) + { + err("usb_new_device: cannot locate device's port.\r\n"); + driver_mem_free(tmpbuf); + + return 1; + } + + /* reset the port for the second time */ + error = hub_port_reset(dev->parent, port, &portstatus); + if (error < 0) + { + err("\r\nCouldn't reset port %d\r\n", port); + driver_mem_free(tmpbuf); + + return 1; + } + } +#endif + dev->epmaxpacketin[0] = dev->descriptor.bMaxPacketSize0; + dev->epmaxpacketout[0] = dev->descriptor.bMaxPacketSize0; + + switch (dev->descriptor.bMaxPacketSize0) + { + case 8: dev->maxpacketsize = PACKET_SIZE_8; break; + case 16: dev->maxpacketsize = PACKET_SIZE_16; break; + case 32: dev->maxpacketsize = PACKET_SIZE_32; break; + case 64: dev->maxpacketsize = PACKET_SIZE_64; break; + } + + dev->devnum = addr; + error = usb_set_address(dev); /* set address */ + + if (error < 0) + { + err("\r\nUSB device not accepting new address (error=%lX)\r\n", dev->status); + driver_mem_free(tmpbuf); + + return 1; + } + + wait_us(10); /* Let the SET_ADDRESS settle */ + tmp = sizeof(dev->descriptor); + error = usb_get_descriptor(dev, USB_DT_DEVICE, 0, &dev->descriptor, sizeof(dev->descriptor)); + if (error < tmp) + { + if (error < 0) + { + err("unable to get device descriptor (error=%d)\r\n", error); + } + else + { + err("USB device descriptor short read (expected %i, got %i)\r\n", tmp, error); + } + driver_mem_free(tmpbuf); + + return 1; + } + + /* correct values */ + dev->descriptor.bcdUSB = swpw(dev->descriptor.bcdUSB); + dev->descriptor.idVendor = swpw(dev->descriptor.idVendor); + dev->descriptor.idProduct = swpw(dev->descriptor.idProduct); + dev->descriptor.bcdDevice = swpw(dev->descriptor.bcdDevice); + + dbg("vendor: 0x%x, prod: 0x%x, dev: 0x%x\r\n", + dev->descriptor.idVendor, dev->descriptor.idProduct, dev->descriptor.bcdDevice); + + /* only support for one config for now */ + usb_get_configuration_no(dev, &tmpbuf[0], 0); + usb_parse_config(dev, &tmpbuf[0], 0); + usb_set_maxpacket(dev); + + /* we set the default configuration here */ + if (usb_set_configuration(dev, dev->config.bConfigurationValue)) + { + dbg("failed to set default configuration len %d, status %lX\r\n", dev->act_len, dev->status); + driver_mem_free(tmpbuf); + + return -1; + } + dbg("new device strings: Manufacturer=%d, Product=%d, SerialNumber=%d\r\n", + dev->descriptor.iManufacturer, dev->descriptor.iProduct, + dev->descriptor.iSerialNumber); + + memset(dev->mf, 0, sizeof(dev->mf)); + memset(dev->prod, 0, sizeof(dev->prod)); + memset(dev->serial, 0, sizeof(dev->serial)); + + if (dev->descriptor.iManufacturer) + { + usb_string(dev, dev->descriptor.iManufacturer, dev->mf, sizeof(dev->mf)); + } + if (dev->descriptor.iProduct) + { + usb_string(dev, dev->descriptor.iProduct, dev->prod, sizeof(dev->prod)); + } + if (dev->descriptor.iSerialNumber) + { + usb_string(dev, dev->descriptor.iSerialNumber, dev->serial, sizeof(dev->serial)); + } + inf("Manufacturer %s\r\n", dev->mf); + inf("Product %s\r\n", dev->prod); + inf("SerialNumber %s\r\n", dev->serial); + + /* now probe if the device is a hub */ + usb_hub_probe(dev, 0); + driver_mem_free(tmpbuf); + + return 0; +} + +/* + * build device Tree + */ +void usb_scan_devices(void *priv) +{ + int i; + struct usb_device *dev; + + /* first make all devices unknown */ + for (i = 0; i < USB_MAX_DEVICE; i++) + { + memset(&usb_dev[(bus_index * USB_MAX_DEVICE) + i], 0, sizeof(struct usb_device)); + usb_dev[(bus_index * USB_MAX_DEVICE) + i].devnum = -1; + } + dev_index[bus_index] = 0; + + /* + * device 0 is always present (root hub, so let it analyze) + */ + dev = usb_alloc_new_device(bus_index, priv); + if (usb_new_device(dev)) + { + xprintf("No USB Device found\r\n"); + if (dev != NULL) + { + dev_index[bus_index]--; + } + } + else + { + xprintf("%d USB Device(s) found\r\n", dev_index[bus_index]); + } + + /* insert "driver" if possible */ + if (drv_usb_kbd_init() < 0) + { + xprintf("No USB keyboard found\r\n"); + } + else + { + xprintf("USB HID keyboard driver installed\r\n"); + } + + if (drv_usb_mouse_init() < 0) + { + xprintf("No USB mouse found\r\n"); + } + else + { + xprintf("USB HID mouse driver installed\r\n"); + } + xprintf("Scan end\r\n"); +} + diff --git a/usb/usb_hub.c b/usb/usb_hub.c new file mode 100644 index 0000000..851805e --- /dev/null +++ b/usb/usb_hub.c @@ -0,0 +1,624 @@ +/* + * HUB "Driver" + * Probes device for being a hub and configure it + */ + +#include +#include "bas_string.h" +#include "bas_printf.h" +#include "util.h" /* for byte swap funcs */ +#include "wait.h" +#include +#include "usb.h" +#include "usb_hub.h" + +// // #define DEBUG +#include "debug.h" + +static struct usb_hub_device hub_dev[USB_MAX_BUS][USB_MAX_HUB]; +static int usb_hub_index[USB_MAX_BUS]; + +int usb_get_hub_descriptor(struct usb_device *dev, void *data, int size) +{ + return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + USB_REQ_GET_DESCRIPTOR, USB_DIR_IN | USB_RT_HUB, USB_DT_HUB << 8, 0, data, size, USB_CNTL_TIMEOUT); +} + +int usb_clear_hub_feature(struct usb_device *dev, int feature) +{ + return usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_CLEAR_FEATURE, USB_RT_HUB, feature, 0, NULL, 0, USB_CNTL_TIMEOUT); +} + +int usb_clear_port_feature(struct usb_device *dev, int port, int feature) +{ + return usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_CLEAR_FEATURE, USB_RT_PORT, feature, port, NULL, 0, USB_CNTL_TIMEOUT); +} + +int usb_set_port_feature(struct usb_device *dev, int port, int feature) +{ + return usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_SET_FEATURE, USB_RT_PORT, feature, port, NULL, 0, USB_CNTL_TIMEOUT); +} + +int usb_get_hub_status(struct usb_device *dev, void *data) +{ + return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + USB_REQ_GET_STATUS, USB_DIR_IN | USB_RT_HUB, 0, 0, data, sizeof(struct usb_hub_status), USB_CNTL_TIMEOUT); +} + +int usb_get_port_status(struct usb_device *dev, int port, void *data) +{ + return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + USB_REQ_GET_STATUS, USB_DIR_IN | USB_RT_PORT, 0, port, data, sizeof(struct usb_hub_status), USB_CNTL_TIMEOUT); +} + +static void usb_hub_power_on(struct usb_hub_device *hub) +{ + int i; + struct usb_device *dev; + + dev = hub->pusb_dev; + /* Enable power to the ports */ + dbg("enabling power on all ports\r\n"); + for (i = 0; i < dev->maxchild; i++) + { + usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_POWER); + dbg("port %d returns %lx\r\n", i + 1, dev->status); + wait(hub->desc.bPwrOn2PwrGood * 2 * 1000); + } +} + +void usb_hub_reset(int bus_index) +{ + usb_hub_index[bus_index] = 0; +} + +struct usb_hub_device *usb_hub_allocate(void) +{ + if (usb_hub_index[bus_index] < USB_MAX_HUB) + { + return &hub_dev[bus_index][usb_hub_index[bus_index]++]; + } + + dbg("ERROR: USB_MAX_HUB (%d) reached\r\n", USB_MAX_HUB); + + return NULL; +} + +#define MAX_TRIES 5 + +static inline char *portspeed(int portstatus) +{ + if (portstatus & (1 << USB_PORT_FEAT_HIGHSPEED)) + { + return "480 Mb/s"; + } + else if (portstatus & (1 << USB_PORT_FEAT_LOWSPEED)) + { + return "1.5 Mb/s"; + } + else + { + return "12 Mb/s"; + } +} + +int hub_port_reset(struct usb_device *dev, int port, unsigned short *portstat) +{ + int tries; + struct usb_port_status portsts; + unsigned short portstatus, portchange; + + dbg(""); + dbg("hub_port_reset: resetting port %d...\r\n", port + 1); + + for (tries = 0; tries < MAX_TRIES; tries++) + { + usb_set_port_feature(dev, port + 1, USB_PORT_FEAT_RESET); + +#ifdef USB_POLL_HUB + if (pxCurrentTCB != NULL) + vTaskDelay((200 * configTICK_RATE_HZ) / 1000); + else +#endif + wait(10 * 1000); + if (usb_get_port_status(dev, port + 1, &portsts) < 0) + { + dbg("get_port_status failed status %lX\r\n", dev->status); + return -1; + } + + portstatus = swpw(portsts.wPortStatus); + portchange = swpw(portsts.wPortChange); + + dbg("USB %d portstatus 0x%x, change 0x%x, %s\r\n", dev->usbnum, portstatus, portchange, portspeed(portstatus)); + dbg("STAT_C_CONNECTION = %d STAT_CONNECTION = %d USB_PORT_STAT_ENABLE = %d\r\n", + (portchange & USB_PORT_STAT_C_CONNECTION) ? 1 : 0, + (portstatus & USB_PORT_STAT_CONNECTION) ? 1 : 0, + (portstatus & USB_PORT_STAT_ENABLE) ? 1 : 0); + + if ((portchange & USB_PORT_STAT_C_CONNECTION) || !(portstatus & USB_PORT_STAT_CONNECTION)) + { + return -1; + } + + if (portstatus & USB_PORT_STAT_ENABLE) + { + break; + } + +#ifdef USB_POLL_HUB + if (pxCurrentTCB != NULL) + vTaskDelay((200*configTICK_RATE_HZ)/1000); + else +#endif + wait(20 * 1000); + } + + if (tries == MAX_TRIES) + { + dbg("USB %d, cannot enable port %d after %d retries, disabling port.\r\n", dev->usbnum, port + 1, MAX_TRIES); + dbg("Maybe the USB cable is bad?\r\n"); + + return -1; + } + usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_C_RESET); + + *portstat = portstatus; + + return 0; +} + +void usb_hub_port_connect_change(struct usb_device *dev, int port) +{ + struct usb_device *usb; + struct usb_port_status portsts; + unsigned short portstatus; + + /* Check status */ + if (usb_get_port_status(dev, port + 1, &portsts) < 0) + { + dbg("USB %d get_port_status failed\r\n", dev->usbnum); + + return; + } + + portstatus = swpw(portsts.wPortStatus); +#ifdef USB_DEBUG + { + unsigned short portchange; + + portchange = swpw(portsts.wPortChange); + dbg("USB %d, portstatus %x, change %x, %s\r\n", dev->usbnum, portstatus, portchange, portspeed(portstatus)); + } +#endif /* USB_DEBUG */ + + /* Clear the connection change status */ + usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_C_CONNECTION); + + /* Disconnect any existing devices under this port */ + + if (((!(portstatus & USB_PORT_STAT_CONNECTION)) + && (!(portstatus & USB_PORT_STAT_ENABLE))) || (dev->children[port])) + { + dbg("USB %d port %i disconnected\r\n", dev->usbnum, port + 1); + usb_disconnect(&dev->children[port]); + + /* Return now if nothing is connected */ + if (!(portstatus & USB_PORT_STAT_CONNECTION)) + { + return; + } + } +#ifdef USB_POLL_HUB + if (pxCurrentTCB != NULL) + vTaskDelay((200*configTICK_RATE_HZ)/1000); + else +#endif + wait(2000); + /* Reset the port */ + if (hub_port_reset(dev, port, &portstatus) < 0) + { + dbg("USB %d cannot reset port %i!?\r\n", dev->usbnum, port + 1); + + return; + } +#ifdef USB_POLL_HUB + if (pxCurrentTCB != NULL) + vTaskDelay((200*configTICK_RATE_HZ)/1000); + else +#endif + wait(2000); + + /* Allocate a new device struct for it */ + usb = usb_alloc_new_device(dev->usbnum, dev->priv_hcd); + + if (portstatus & USB_PORT_STAT_HIGH_SPEED) + { + usb->speed = USB_SPEED_HIGH; + } + else if (portstatus & USB_PORT_STAT_LOW_SPEED) + { + usb->speed = USB_SPEED_LOW; + } + else + { + usb->speed = USB_SPEED_FULL; + } + + dbg("usb device = %p\r\n", usb); + dev->children[port] = usb; + usb->parent = dev; + + /* Run it through the hoops (find a driver, etc) */ + if (usb_new_device(usb)) + { + /* Woops, disable the port */ + dbg("USB %d hub: disabling port %d\r\n", dev->usbnum, port + 1); + usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_ENABLE); + } + +#ifdef USB_POLL_HUB + else if (pxCurrentTCB != NULL) + { + usb_kbd_register(usb); + usb_mouse_register(usb); +#ifdef CONFIG_USB_STORAGE + usb_stor_register(usb); +#endif /* CONFIG_USB_STORAGE */ + } +#endif +} + +static void usb_hub_events(struct usb_device *dev) +{ + int i; + struct usb_hub_device *hub = dev->hub; + + if (hub == NULL) + { + return; + } + + for (i = 0; i < dev->maxchild; i++) + { + struct usb_port_status portsts; + unsigned short portstatus, portchange; + + if (usb_get_port_status(dev, i + 1, &portsts) < 0) + { + dbg("get_port_status failed\r\n"); + + continue; + } + portstatus = swpw(portsts.wPortStatus); + portchange = swpw(portsts.wPortChange); + + dbg("USB %d Port %d Status %X Change %X\r\n", dev->usbnum, i + 1, portstatus, portchange); + + if (portchange & USB_PORT_STAT_C_CONNECTION) + { + dbg("USB %d port %d connection change\r\n", dev->usbnum, i + 1); + usb_hub_port_connect_change(dev, i); + } + + if (portchange & USB_PORT_STAT_C_ENABLE) + { + dbg("USB %d port %d enable change, status %x\r\n", dev->usbnum, i + 1, portstatus); + usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_C_ENABLE); + + /* + * EM interference sometimes causes bad shielded USB + * devices to be shutdown by the hub, this hack enables + * them again. Works at least with mouse driver + */ + if (!(portstatus & USB_PORT_STAT_ENABLE) && (portstatus & USB_PORT_STAT_CONNECTION) && ((dev->children[i]))) + { + dbg("USB %d already running port %i disabled by hub (EMI?), re-enabling...\r\n", dev->usbnum, i + 1); + usb_hub_port_connect_change(dev, i); + } + } + + if (portstatus & USB_PORT_STAT_SUSPEND) + { + dbg("USB %d port %d suspend change\r\n", dev->usbnum, i + 1); + usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_SUSPEND); + } + + if (portchange & USB_PORT_STAT_C_OVERCURRENT) + { + dbg("USB %d port %d over-current change\r\n", dev->usbnum, i + 1); + usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_C_OVER_CURRENT); + usb_hub_power_on(hub); + } + + if (portchange & USB_PORT_STAT_C_RESET) + { + dbg("USB %d port %d reset change\r\n", dev->usbnum, i + 1); + usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_C_RESET); + } + } /* end for i all ports */ +} + +#ifdef USB_POLL_HUB +void usb_poll_hub_task(void *pvParameters) +{ + int index_bus = 0; + portTickType timeout = configTICK_RATE_HZ/10; + if (pvParameters); + while(1) + { + if (xQueueAltReceive(queue_poll_hub, &index_bus, timeout) == pdPASS) + { + if ((index_bus >= 0) && (index_bus < USB_MAX_BUS) && (controller_priv[index_bus] != NULL)) + { + dbg("USB %d event change\r\n", index_bus); +#ifdef CONFIG_USB_INTERRUPT_POLLING + *vblsem = 0; +#endif + usb_hub_events(&usb_dev[index_bus * USB_MAX_DEVICE]); +#ifdef CONFIG_USB_INTERRUPT_POLLING + *vblsem = 1; +#endif + } + } + else /* timeout */ + { + int i; +#ifdef CONFIG_USB_INTERRUPT_POLLING + *vblsem = 0; +#endif + for (i = 0; i < USB_MAX_BUS ; i++) + { + if (controller_priv[i] != NULL) + usb_hub_events(&usb_dev[i * USB_MAX_DEVICE]); + } +#ifdef CONFIG_USB_INTERRUPT_POLLING + *vblsem = 1; +#endif + } + timeout = portMAX_DELAY; + } +} +#endif /* USB_POLL_HUB */ + +int usb_hub_configure(struct usb_device *dev) +{ + unsigned char *buffer; + unsigned char *bitmap; + struct usb_hub_descriptor *descriptor; + int i; + struct usb_hub_device *hub; + + /* "allocate" Hub device */ + hub = usb_hub_allocate(); + dev->hub = hub; + + if (hub == NULL) + { + dbg("could not allocate hub\r\n"); + + return -1; + } + + hub->pusb_dev = dev; + buffer = (unsigned char *) driver_mem_alloc(USB_BUFSIZ); + + if (buffer == NULL) + { + dbg("driver_mem_alloc() failure\r\n"); + return -1; + } + + /* Get the the hub descriptor */ + if (usb_get_hub_descriptor(dev, buffer, 4) < 0) + { + dbg("failed to get hub descriptor, giving up %lX\r\n", dev->status); + driver_mem_free(buffer); + return -1; + } + + dbg("bLength:0x%02X bDescriptorType:0x%02X bNbrPorts:0x%02X\r\n", buffer[0], buffer[1], buffer[2]); + descriptor = (struct usb_hub_descriptor *)buffer; + + /* silence compiler warning if USB_BUFSIZ is > 256 [= sizeof(char)] */ + i = descriptor->bLength; + + if (i > USB_BUFSIZ) + { + dbg("failed to get hub descriptor - too long: %d\r\n", descriptor->bLength); + driver_mem_free(buffer); + + return -1; + } + + if (usb_get_hub_descriptor(dev, buffer, descriptor->bLength) < 0) + { + dbg("failed to get hub descriptor 2nd giving up %lX\r\n", dev->status); + driver_mem_free(buffer); + + return -1; + } + + memcpy((unsigned char *) &hub->desc, buffer, descriptor->bLength); + + /* adjust 16bit values */ + hub->desc.wHubCharacteristics = swpw(descriptor->wHubCharacteristics); + + /* set the bitmap */ + bitmap = (unsigned char *) &hub->desc.DeviceRemovable[0]; + + /* devices not removable by default */ + + memset(bitmap, 0xff, (USB_MAXCHILDREN + 1 + 7) / 8); + bitmap = (unsigned char *) &hub->desc.PortPowerCtrlMask[0]; + memset(bitmap, 0xff, (USB_MAXCHILDREN + 1 + 7) / 8); /* PowerMask = 1B */ + + for (i = 0; i < ((hub->desc.bNbrPorts + 1 + 7) / 8); i++) + { + hub->desc.DeviceRemovable[i] = descriptor->DeviceRemovable[i]; + } + + for (i = 0; i < ((hub->desc.bNbrPorts + 1 + 7) / 8); i++) + { + hub->desc.DeviceRemovable[i] = descriptor->PortPowerCtrlMask[i]; + } + + dev->maxchild = descriptor->bNbrPorts; + dbg("USB %d, %d ports detected\r\n", dev->usbnum, dev->maxchild); + if (dev->maxchild >= 10) + { + dev->maxchild = 10; + } + + switch(hub->desc.wHubCharacteristics & HUB_CHAR_LPSM) + { + case 0x00: dbg("ganged power switching\r\n"); break; + case 0x01: dbg("individual port power switching\r\n"); break; + case 0x02: + case 0x03: dbg("unknown reserved power switching mode\r\n"); break; + } + + if (hub->desc.wHubCharacteristics & HUB_CHAR_COMPOUND) + { + dbg("part of a compound device\r\n"); + } + else + { + dbg("standalone hub\r\n"); + } + + switch(hub->desc.wHubCharacteristics & HUB_CHAR_OCPM) + { + case 0x00: dbg("global over-current protection\r\n"); break; + case 0x08: dbg("individual port over-current protection\r\n"); break; + case 0x10: + case 0x18: dbg("no over-current protection\r\n"); break; + } + + dbg("power on to power good time: %dms\r\n", descriptor->bPwrOn2PwrGood * 2); + dbg("hub controller current requirement: %dmA\r\n", descriptor->bHubContrCurrent); + + for (i = 0; i < dev->maxchild; i++) + { + dbg("USB %d port %d is%s removable\r\n", + dev->usbnum, i + 1, + hub->desc.DeviceRemovable[(i + 1) / 8] & (1 << ((i + 1) % 8)) ? " not" : ""); + } + + if (sizeof(struct usb_hub_status) > USB_BUFSIZ) + { + dbg("usb_hub_configure: failed to get Status - too long: %d\r\n", descriptor->bLength); + driver_mem_free(buffer); + + return -1; + } + + if (usb_get_hub_status(dev, buffer) < 0) + { + dbg("usb_hub_configure: failed to get Status %lX\r\n", dev->status); + driver_mem_free(buffer); + + return -1; + } + +#ifdef DEBUG_HUB + { + struct usb_hub_status *hubsts; + + hubsts = (struct usb_hub_status *) buffer; + dbg("get_hub_status returned status %X, change %X\r\n", + swpw(hubsts->wHubStatus), swpw(hubsts->wHubChange)); + dbg("local power source is %s\r\n", + (swpw(hubsts->wHubStatus) & HUB_STATUS_LOCAL_POWER) ? "lost (inactive)" : "good"); + dbg("%sover-current condition exists\r\n", + (swpw(hubsts->wHubStatus) & HUB_STATUS_OVERCURRENT) ? "" : "no "); + } +#endif /* USB_DEBUG */ + + usb_hub_power_on(hub); + +#ifdef USB_POLL_HUB + if ((queue_poll_hub == NULL) && (pxCurrentTCB != NULL)) + { + queue_poll_hub = xQueueCreate(64, sizeof(int)); + if (queue_poll_hub != NULL) + { + /* Create poll/event task */ + if (xTaskCreate(usb_poll_hub_task, (void *)"USBHub", configMINIMAL_STACK_SIZE, NULL, 16, NULL) != pdPASS) + { + vQueueDelete(queue_poll_hub); + queue_poll_hub = NULL; + } + } + vTaskDelay(configTICK_RATE_HZ); + } + if (queue_poll_hub == NULL) +#endif + + usb_hub_events(dev); + driver_mem_free(buffer); + + return 0; +} + +int usb_hub_probe(struct usb_device *dev, int ifnum) +{ + struct usb_interface_descriptor *iface; + struct usb_endpoint_descriptor *ep; + int ret; + + iface = &dev->config.if_desc[ifnum]; + + /* Is it a hub? */ + if (iface->bInterfaceClass != USB_CLASS_HUB) + { + dbg("iface->bInterfaceClass != USB_CLASS_HUB (%d), %d instead\r\n", USB_CLASS_HUB, iface->bInterfaceClass); + return 0; + } + + /* + * Some hubs have a subclass of 1, which AFAICT according to the + * specs is not defined, but it works + */ + if ((iface->bInterfaceSubClass != 0) && (iface->bInterfaceSubClass != 1)) + { + dbg("iface->bInterfaceSubClass != {0, 1} (%d instead)\r\n", iface->bInterfaceSubClass); + + return 0; + } + + /* Multiple endpoints? What kind of mutant ninja-hub is this? */ + if (iface->bNumEndpoints != 1) + { + dbg("iface->bNumEndpoints != 1 (%d instead)\r\n", iface->bNumEndpoints); + return 0; + } + + ep = &iface->ep_desc[0]; + + /* Output endpoint? Curiousier and curiousier.. */ + if (!(ep->bEndpointAddress & USB_DIR_IN)) + { + dbg("!(ep->bEndpointAddress != USB_DIR_IN (0x%x instead)\r\n", ep->bEndpointAddress); + + return 0; + } + + /* If it's not an interrupt endpoint, we'd better punt! */ + if ((ep->bmAttributes & 3) != 3) + { + return 0; + } + + /* We found a hub */ + dbg("USB %d hub found\r\n", dev->usbnum); + + ret = usb_hub_configure(dev); + + return ret; +} + + diff --git a/usb/usb_kbd.c b/usb/usb_kbd.c new file mode 100644 index 0000000..251dc48 --- /dev/null +++ b/usb/usb_kbd.c @@ -0,0 +1,1386 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland + * + * Part of this source has been derived from the Linux USB + * project. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include "usb.h" +#include "exceptions.h" + +// #define DEBUG +#include "debug.h" + +#ifdef USE_COUNTRYCODE +static int usb_kbd_get_hid_desc(struct usb_device *dev); +#endif + +/* under TOS Repeat keys are build by timer C so infinite (0) or 1000 is a good value */ +#define REPEAT_RATE 0 // 40 /* 40msec -> 25cps */ + +#define MAX_VALUE_LOOKUP 0x90 +#define MAX_VALUE_ATARI 0x75 + +#define NUM_LOCK 0x53 +#define CAPS_LOCK 0x39 +#define SCROLL_LOCK 0x47 + +/* Modifier bits */ +#define LEFT_CNTR 0 +#define LEFT_SHIFT 1 +#define LEFT_ALT 2 +#define LEFT_GUI 3 +#define RIGHT_CNTR 4 +#define RIGHT_SHIFT 5 +#define RIGHT_ALT 6 +#define RIGHT_GUI 7 + +/* HID bCountryCode */ +#define CC_NOT 0 +#define CC_ISO 13 +#define CC_USA 33 +#define CC_FRG 9 +#define CC_FRA 8 +#define CC_UK 32 +#define CC_SPA 25 +#define CC_ITA 14 +#define CC_SWE 29 +#define CC_SWF 27 +#define CC_SWG 28 + +/* Language cookie */ +#define USA 0 /* English */ +#define FRG 1 /* German */ +#define FRA 2 /* French */ +#define UK 3 /* English */ +#define SPA 4 /* Spanish */ +#define ITA 5 /* Italian */ +#define SWE 6 /* Swiss */ +#define SWF 7 /* Swiss French */ +#define SWG 8 /* Swiss German */ + +//extern _IOREC *iorec; +//extern void (**ikbdvec)(); + +static unsigned char *new_packet; +static unsigned char old_packet[8]; +static unsigned char num_lock; +static unsigned char caps_lock; +static unsigned char scroll_lock; +static unsigned char old_modifier; +static union +{ + struct + { + unsigned reserved1:3; + unsigned force_alt_shift:1; + unsigned right_shift_host:1; + unsigned left_shift_host:1; + unsigned alt_host:1; + unsigned ctrl_host:1; + unsigned key_forced:1; + unsigned reserved2:3; + unsigned altgr_usb:1; + unsigned shift_usb:1; + unsigned altgr_usb_break:1; + unsigned shift_usb_break:1; + } b; + unsigned short s; +} flags; + +static unsigned char *leds; +static int kbd_installed; + +static unsigned char usb_kbd_to_atari_scancode[] = +{ + // A(Q) B C D + 0x00, 0x00, 0x00, 0x00, 0x1E, 0x30, 0x2E, 0x20, + // E F G H I J K L + 0x12, 0x21, 0x22, 0x23, 0x17, 0x24, 0x25, 0x26, + // M(,) N O P Q(A) R S T + 0x32, 0x31, 0x18, 0x19, 0x10, 0x13, 0x1F, 0x14, + // U V W(Z) X Y Z(W) 1 2 + 0x16, 0x2F, 0x11, 0x2D, 0x15, 0x2C, 0x02, 0x03, + // 3 4 5 6 7 8 9 0 + 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, + // RET ESC BACK TAB SPACE -()) = [(^) + 0x1C, 0x01, 0x0E, 0x0F, 0x39, 0x0C, 0x0D, 0x1A, + // ]($) \(*) EUR1 ;(M) ' ` ,(;) .(:) + 0x1B, 0x2B, 0x2B, 0x27, 0x28, 0x5B, 0x33, 0x34, + // /(!) CAPS F1 F2 F3 F4 F5 F6 + 0x35, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, + // F7 F8 F9 F10 F11 F12 PrtSc ScLoc + 0x41, 0x42, 0x43, 0x44, 0x62, 0x61, 0x49, 0x4C, + //PAUSE INS HOME PgUp DEL END PgDn -> + 0x4F, 0x52, 0x47, 0x45, 0x53, 0x55, 0x46, 0x4D, + // <- DOWN UP NuLoc KP/ KP* KP- KP+ + 0x4B, 0x50, 0x48, 0x54, 0x65, 0x66, 0x4A, 0x4E, + // ENT KP1 KP2 KP3 KP4 KP5 KP6 KP7 + 0x72, 0x6D, 0x6E, 0x6F, 0x6A, 0x6B, 0x6C, 0x67, + // KP8 KP9 KP0 KP. >< APP POWER KP= + 0x68, 0x69, 0x70, 0x71, 0x60, 0x00, 0x00, 0x00, + // F13, F14, F15 F16 F17 F18 F19 F20 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // F21 F22 F23 F24 EXEC HELP MENU SEL + 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x60, 0x00, + // STOP AGAIN UNDO CUT COPY PASTE FIND MUTE + 0x00, 0x00, 0x61, 0x00, 0x00, 0x00, 0x00, 0x00, + //VolUp Vold_packetn + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + //LCTRL LSHFT LALT LGUI RCTRL RSHFT RALT RGUI + 0x1D, 0x2A, 0x38, 0x56, 0x1D, 0x36, 0x38, 0x57 // virtual codes +}; + +static unsigned char usb_kbd_to_atari_fr_modifier[] = +{ + /* This table can change host SHIFT & ALT states for each scancode, values */ + /* are in hexa : bit 7: 1 for a valid entry */ + /* bit 6: 1 for force CTRL */ + /* bit 5: ALT, bit 4: SHIFT states for the AltGR table */ + /* bit 3: ALT, bit 2: SHIFT states for the Shift table */ + /* bit 1: ALT, bit 0: SHIFT states for the Unshift table */ + // A(Q) B C D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // E F G H I J K L + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // M(,) N O P Q(A) R S T + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // U V W(Z) X Y Z(W) 1 2 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB4, + // 3 4 5 6 7 8 9 0 + 0x00, 0xB4, 0xA4, 0x94, 0x00, 0xA5, 0x84, 0xA4, + // RET ESC BACK TAB SPACE -()) = [(^) + 0x00, 0x00, 0x00, 0x00, 0x00, 0xA4, 0xB4, 0x00, + // ]($) \(*) ;(M) ' ` ,(;) .(:) + 0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // /(!) CAPS F1 F2 F3 F4 F5 F6 + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // F7 F8 F9 F10 F11 F12 PrtSc ScLoc + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xAA, 0x00, + //PAUSE INS HOME PgUp DEL END PgDn -> + 0x00, 0x00, 0x00, 0x95, 0x00, 0x95, 0x95, 0x00, + // <- DOWN UP NuLoc KP/ KP* KP- KP+ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // ENT KP1 KP2 KP3 KP4 KP5 KP6 KP7 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // KP8 KP9 KP0 KP. >< APP POWER KP= + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // F13, F14, F15 F16 F17 F18 F19 F20 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // F21 F22 F23 F24 EXEC HELP MENU SEL + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xBF, 0x00, + // STOP AGAIN UNDO CUT COPY PASTE FIND MUTE + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + //VolUp Vold_packetn + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + //LCTRL LSHFT LALT LGUI RCTRL RSHFT RALT RGUI + 0x00, 0x00, 0x00, 0xEA, 0x00, 0x00, 0x00, 0xEA +}; + +static unsigned char usb_kbd_to_atari_fr_unshift[] = +{ + // A(Q) B C D + 0x00, 0x00, 0x00, 0x00, 0x1E, 0x30, 0x2E, 0x20, + // E F G H I J K L + 0x12, 0x21, 0x22, 0x23, 0x17, 0x24, 0x25, 0x26, + // M(,) N O P Q(A) R S T + 0x32, 0x31, 0x18, 0x19, 0x10, 0x13, 0x1F, 0x14, + // U V W(Z) X Y Z(W) 1 2 + 0x16, 0x2F, 0x11, 0x2D, 0x15, 0x2C, 0x02, 0x03, + // 3 4 5 6 7 8 9 0 + 0x04, 0x05, 0x06, 0x0D, 0x08, 0x0D, 0x0A, 0x0B, + // RET ESC BACK TAB SPACE -()) = [(^) + 0x1C, 0x01, 0x0E, 0x0F, 0x39, 0x0C, 0x35, 0x1A, + // ]($) \(*) ;(M) ' ` ,(;) .(:) + 0x1B, 0x1B, 0x00, 0x27, 0x28, 0x00, 0x33, 0x34, + // /(!) CAPS F1 F2 F3 F4 F5 F6 + 0x09, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, + // F7 F8 F9 F10 F11 F12 PrtSc ScLoc + 0x41, 0x42, 0x43, 0x44, 0x62, 0x61, 0x62, 0x4C, + //PAUSE INS HOME PgUp DEL END PgDn -> + 0x4F, 0x52, 0x47, 0x45, 0x53, 0x47, 0x46, 0x4D, + // <- DOWN UP NuLoc KP/ KP* KP- KP+ + 0x4B, 0x50, 0x48, 0x00, 0x65, 0x66, 0x4A, 0x4E, + // ENT KP1 KP2 KP3 KP4 KP5 KP6 KP7 + 0x72, 0x6D, 0x6E, 0x6F, 0x6A, 0x6B, 0x6C, 0x67, + // KP8 KP9 KP0 KP. >< APP KP= + 0x68, 0x69, 0x70, 0x71, 0x60, 0x00, 0x00, 0x00, + // F13, F14, F15 F16 F17 F18 F19 F20 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // F21 F22 F23 F24 EXEC HELP MENU SEL + 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x60, 0x00, + // STOP AGAIN UNDO CUT COPY PASTE FIND MUTE + 0x00, 0x00, 0x61, 0x00, 0x00, 0x00, 0x00, 0x00, + //VolUp Vold_packetn + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + //LCTRL LSHFT LALT LGUI RCTRL RSHFT RALT RGUI + 0x1D, 0x2A, 0x38, 0x0F, 0x1D, 0x36, 0x00, 0x0F +}; + +static unsigned char usb_kbd_to_atari_fr_shift[] = +{ + /* Hexa values, 00: unused => use the Unshift table */ + /* FF: invalid => no scancode */ + // A(Q) B C D + 0x00, 0x00, 0x00, 0x00, 0x1E, 0x30, 0x2E, 0x20, + // E F G H I J K L + 0x12, 0x21, 0x22, 0x23, 0x17, 0x24, 0x25, 0x26, + // M(,) N O P Q(A) R S T + 0x32, 0x31, 0x18, 0x19, 0x10, 0x13, 0x1F, 0x14, + // U V W(Z) X Y Z(W) 1 2 + 0x16, 0x2F, 0x11, 0x2D, 0x15, 0x2C, 0x02, 0x03, + // 3 4 5 6 7 8 9 0 + 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, + // RET ESC BACK TAB SPACE -()) = [(^) + 0x1C, 0x01, 0x0E, 0x0F, 0x39, 0x0C, 0x35, 0x1A, + // ]($) \(*) ;(M) ' ` ,(;) .(:) + 0x29, 0xFF, 0x00, 0x27, 0x28, 0x00, 0x33, 0x34, + // /(!) CAPS F1 F2 F3 F4 F5 F6 + 0x07, 0x3A, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, + // F7 F8 F9 F10 F11 F12 PrtSc ScLoc + 0x5A, 0x5B, 0x5C, 0x5D, 0x62, 0x61, 0x62, 0x4C, + //PAUSE INS HOME PgUp DEL END PgDn -> + 0x4F, 0x52, 0x47, 0x48, 0x53, 0x47, 0x50, 0x4D, + // <- DOWN UP NuLoc KP/ KP* KP- KP+ + 0x4B, 0x50, 0x48, 0x00, 0x65, 0x66, 0x4A, 0x4E, + // ENT KP1 KP2 KP3 KP4 KP5 KP6 KP7 + 0x72, 0x6D, 0x6E, 0x6F, 0x6A, 0x6B, 0x6C, 0x67, + // KP8 KP9 KP0 KP. >< APP KP= + 0x68, 0x69, 0x70, 0x71, 0x60, 0x00, 0x00, 0x00, + // F13, F14, F15 F16 F17 F18 F19 F20 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // F21 F22 F23 F24 EXEC HELP MENU SEL + 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x60, 0x00, + // STOP AGAIN UNDO CUT COPY PASTE FIND MUTE + 0x00, 0x00, 0x61, 0x00, 0x00, 0x00, 0x00, 0x00, + //VolUp Vold_packetn + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + //LCTRL LSHFT LALT LGUI RCTRL RSHFT RALT RGUI + 0x1D, 0x2A, 0x38, 0x0F, 0x1D, 0x36, 0x00, 0x0F +}; + +static unsigned char usb_kbd_to_atari_fr_altgr[] = +{ + /* Hexa values, 00: unused => use the Unshift table */ + /* FF: invalid => no scancode */ + // A(Q) B C D + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + // E F G H I J K L + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + // M(,) N O P Q(A) R S T + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + // U V W(Z) X Y Z(W) 1 2 + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x2B, + // 3 4 5 6 7 8 9 0 + 0x2B, 0x1A, 0x1A, 0x2B, 0x29, 0x28, 0x1A, 0x2B, + // RET ESC BACK TAB SPACE -()) = [(^) + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x1B, 0x1B, 0xFF, + // ]($) \(*) ;(M) ' ` ,(;) .(:) + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + // /(!) CAPS F1 F2 F3 F4 F5 F6 + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + // F7 F8 F9 F10 F11 F12 PrtSc ScLoc + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + //PAUSE INS HOME PgUp DEL END PgDn -> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + // <- DOWN UP NuLoc KP/ KP* KP- KP+ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x4E, + // ENT KP1 KP2 KP3 KP4 KP5 KP6 KP7 + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + // KP8 KP9 KP0 KP. >< APP KP= + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + // F13, F14, F15 F16 F17 F18 F19 F20 + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + // F21 F22 F23 F24 EXEC HELP MENU SEL + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x62, 0xFF, 0xFF, + // STOP AGAIN UNDO CUT COPY PASTE FIND MUTE + 0xFF, 0xFF, 0x61, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + //VolUp Vold_packetn + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + //LCTRL LSHFT LALT LGUI RCTRL RSHFT RALT RGUI + 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0xFF +}; + +static unsigned char usb_kbd_to_atari_de_modifier[] = +{ + /* This table can change host SHIFT & ALT states for each scancode, values */ + /* are in hexa : bit 7: 1 for a valid entry */ + /* bit 6: 1 for force CTRL */ + /* bit 5: ALT, bit 4: SHIFT states for the AltGR table */ + /* bit 3: ALT, bit 2: SHIFT states for the Shift table */ + /* bit 1: ALT, bit 0: SHIFT states for the Unshift table */ + // A(Q) B C D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // E F G H I J K L + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // M(,) N O P Q(A) R S T + 0x00, 0x00, 0x00, 0x00, 0xA4, 0x00, 0x00, 0x00, + // U V W(Z) X Y Z(W) 1 2 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // 3 4 5 6 7 8 9 0 + 0x00, 0x00, 0x00, 0x00, 0xB4, 0xA4, 0xA4, 0xB4, + // RET ESC BACK TAB SPACE -()) = [(^) + 0x00, 0x00, 0x00, 0x00, 0x00, 0xB4, 0x00, 0x00, + // ]($) \(*) ;(M) ' ` ,(;) .(:) + 0x00, 0x80, 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, + // /(!) CAPS F1 F2 F3 F4 F5 F6 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // F7 F8 F9 F10 F11 F12 PrtSc ScLoc + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + //PAUSE INS HOME PgUp DEL END PgDn -> + 0x00, 0x00, 0x00, 0x81, 0x00, 0x95, 0x81, 0x00, + // <- DOWN UP NuLoc KP/ KP* KP- KP+ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // ENT KP1 KP2 KP3 KP4 KP5 KP6 KP7 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // KP8 KP9 KP0 KP. >< APP POWER KP= + 0x00, 0x00, 0x00, 0x00, 0x94, 0x00, 0x00, 0x00, + // F13, F14, F15 F16 F17 F18 F19 F20 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // F21 F22 F23 F24 EXEC HELP MENU SEL + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xBF, 0x00, + // STOP AGAIN UNDO CUT COPY PASTE FIND MUTE + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + //VolUp Vold_packetn + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + //LCTRL LSHFT LALT LGUI RCTRL RSHFT RALT RGUI + 0x00, 0x00, 0x00, 0xEA, 0x00, 0x00, 0x00, 0xEA +}; + +static unsigned char usb_kbd_to_atari_de_unshift[] = +{ + // A(Q) B C D + 0x00, 0x00, 0x00, 0x00, 0x1E, 0x30, 0x2E, 0x20, + // E F G H I J K L + 0x12, 0x21, 0x22, 0x23, 0x17, 0x24, 0x25, 0x26, + // M(,) N O P Q(A) R S T + 0x32, 0x31, 0x18, 0x19, 0x10, 0x13, 0x1F, 0x14, + // U V W(Z) X Y Z(W) 1 2 + 0x16, 0x2F, 0x11, 0x2D, 0x15, 0x2C, 0x02, 0x03, + // 3 4 5 6 7 8 9 0 + 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, + // RET ESC BACK TAB SPACE -()) = [(^) + 0x1C, 0x01, 0x0E, 0x0F, 0x39, 0x0C, 0x0D, 0x1A, + // ]($) \(*) ;(M) ' ` ,(;) .(:) + 0x1B, 0x29, 0x00, 0x27, 0x28, 0x29, 0x33, 0x34, + // /(!) CAPS F1 F2 F3 F4 F5 F6 + 0x35, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, + // F7 F8 F9 F10 F11 F12 PrtSc ScLoc + 0x41, 0x42, 0x43, 0x44, 0x63, 0x64, 0x62, 0x50, + //PAUSE INS HOME PgUp DEL END PgDn -> + 0x61, 0x52, 0x47, 0x48, 0x53, 0x47, 0x50, 0x4D, + // <- DOWN UP NuLoc KP/ KP* KP- KP+ + 0x4B, 0x50, 0x48, 0x54, 0x65, 0x66, 0x4A, 0x4E, + // ENT KP1 KP2 KP3 KP4 KP5 KP6 KP7 + 0x72, 0x6D, 0x6E, 0x6F, 0x6A, 0x6B, 0x6C, 0x67, + // KP8 KP9 KP0 KP. >< APP KP= + 0x68, 0x69, 0x70, 0x71, 0x60, 0x00, 0x00, 0x00, + // F13, F14, F15 F16 F17 F18 F19 F20 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // F21 F22 F23 F24 EXEC HELP MENU SEL + 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x60, 0x00, + // STOP AGAIN UNDO CUT COPY PASTE FIND MUTE + 0x00, 0x00, 0x61, 0x00, 0x00, 0x00, 0x00, 0x00, + //VolUp Vold_packetn + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + //LCTRL LSHFT LALT LGUI RCTRL RSHFT RALT RGUI + 0x1D, 0x2A, 0x38, 0x0F, 0x1D, 0x36, 0x00, 0x0F +}; + +static unsigned char usb_kbd_to_atari_de_shift[] = +{ + /* Hexa values, 00: unused => use the Unshift table */ + /* FF: invalid => no scancode */ + // A(Q) B C D + 0x00, 0x00, 0x00, 0x00, 0x1E, 0x30, 0x2E, 0x20, + // E F G H I J K L + 0x12, 0x21, 0x22, 0x23, 0x17, 0x24, 0x25, 0x26, + // M(,) N O P Q(A) R S T + 0x32, 0x31, 0x18, 0x19, 0x10, 0x13, 0x1F, 0x14, + // U V W(Z) X Y Z(W) 1 2 + 0x16, 0x2F, 0x11, 0x2D, 0x15, 0x2C, 0x02, 0x03, + // 3 4 5 6 7 8 9 0 + 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, + // RET ESC BACK TAB SPACE -()) = [(^) + 0x1C, 0x01, 0x0E, 0x0F, 0x39, 0x0C, 0x0D, 0x1A, + // ]($) \(*) ;(M) ' ` ,(;) .(:) + 0x1B, 0x0D, 0x00, 0x27, 0x28, 0x34, 0x33, 0x34, + // /(!) CAPS F1 F2 F3 F4 F5 F6 + 0x35, 0x3A, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, + // F7 F8 F9 F10 F11 F12 PrtSc ScLoc + 0x5A, 0x5B, 0x5C, 0x5D, 0x63, 0x64, 0x62, 0x50, + //PAUSE INS HOME PgUp DEL END PgDn -> + 0x61, 0x52, 0x47, 0x48, 0x53, 0x47, 0x50, 0x4D, + // <- DOWN UP NuLoc KP/ KP* KP- KP+ + 0x4B, 0x50, 0x48, 0x54, 0x65, 0x66, 0x4A, 0x4E, + // ENT KP1 KP2 KP3 KP4 KP5 KP6 KP7 + 0x72, 0x6D, 0x6E, 0x6F, 0x6A, 0x6B, 0x6C, 0x67, + // KP8 KP9 KP0 KP. >< APP KP= + 0x68, 0x69, 0x70, 0x71, 0x60, 0x00, 0x00, 0x00, + // F13, F14, F15 F16 F17 F18 F19 F20 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // F21 F22 F23 F24 EXEC HELP MENU SEL + 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x60, 0x00, + // STOP AGAIN UNDO CUT COPY PASTE FIND MUTE + 0x00, 0x00, 0x61, 0x00, 0x00, 0x00, 0x00, 0x00, + //VolUp Vold_packetn + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + //LCTRL LSHFT LALT LGUI RCTRL RSHFT RALT RGUI + 0x1D, 0x2A, 0x38, 0x0F, 0x1D, 0x36, 0x00, 0x0F +}; + +static unsigned char usb_kbd_to_atari_de_altgr[] = +{ + /* Hexa values, 00: unused => use the Unshift table */ + /* FF: invalid => no scancode */ + // A(Q) B C D + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + // E F G H I J K L + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + // M(,) N O P Q(A) R S T + 0xFF, 0xFF, 0xFF, 0xFF, 0x1A, 0xFF, 0xFF, 0xFF, + // U V W(Z) X Y Z(W) 1 2 + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + // 3 4 5 6 7 8 9 0 + 0xFF, 0xFF, 0xFF, 0xFF, 0x27, 0x27, 0x28, 0x28, + // RET ESC BACK TAB SPACE -()) = [(^) + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x1A, 0x2B, 0xFF, + // ]($) \(*) ;(M) ' ` ,(;) .(:) + 0x2B, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + // /(!) CAPS F1 F2 F3 F4 F5 F6 + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + // F7 F8 F9 F10 F11 F12 PrtSc ScLoc + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + //PAUSE INS HOME PgUp DEL END PgDn -> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + // <- DOWN UP NuLoc KP/ KP* KP- KP+ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x4E, + // ENT KP1 KP2 KP3 KP4 KP5 KP6 KP7 + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + // KP8 KP9 KP0 KP. >< APP KP= + 0xFF, 0xFF, 0xFF, 0xFF, 0x2B, 0xFF, 0xFF, 0xFF, + // F13, F14, F15 F16 F17 F18 F19 F20 + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + // F21 F22 F23 F24 EXEC HELP MENU SEL + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x62, 0xFF, 0xFF, + // STOP AGAIN UNDO CUT COPY PASTE FIND MUTE + 0xFF, 0xFF, 0x61, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + //VolUp Vold_packetn + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + //LCTRL LSHFT LALT LGUI RCTRL RSHFT RALT RGUI + 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0xFF +}; + +static void *memscan(void *addr, int c, int size) +{ + unsigned char *p = (unsigned char *) addr; + + while (size) + { + if (*p == (char) c) + return (void *) p; + p++; + size--; + } + return (void *) p; +} + +static int usb_kbd_probe(struct usb_device *dev, unsigned int ifnum); + +/* + * deregistering the keyboard + */ +int usb_kbd_deregister(struct usb_device *dev) +{ + dev->irq_handle = NULL; + + if (new_packet != NULL) + { + driver_mem_free(new_packet); + new_packet = NULL; + } + + if (leds != NULL) + { + driver_mem_free(leds); + leds = NULL; + } + kbd_installed = 0; + + dbg("USB KBD deregistered\r\n"); + + return 1; +} + +/* registering the keyboard */ +int usb_kbd_register(struct usb_device *dev) +{ + if(!kbd_installed && (dev->devnum != -1) && (usb_kbd_probe(dev, 0) == 1)) + { /* Ok, we found a keyboard */ + dbg("USB KBD found (USB: %d, devnum: %d)\r\n", dev->usbnum, dev->devnum); + num_lock = caps_lock = scroll_lock = old_modifier = 0; + flags.s = 0; + kbd_installed = 1; + dev->deregister = usb_kbd_deregister; + return 1; + } + /* no USB Keyboard found */ + return -1; +} + +/* search for keyboard and register it if found */ +int drv_usb_kbd_init(void) +{ + int i, j; + if(kbd_installed) + return -1; + /* scan all USB Devices */ + for(j = 0; j < USB_MAX_BUS; j++) + { + for(i = 0; i < USB_MAX_DEVICE; i++) + { + struct usb_device *dev = usb_get_dev_index(i, j); /* get device */ + if(dev == NULL) + break; + if(usb_kbd_register(dev) > 0) + return 1; + } + } + /* no USB Keyboard found */ + return -1; +} + +/************************************************************************** + * Low Level drivers + */ + +/* set the LEDs. Since this is used in the irq routine, the control job + is issued with a timeout of 0. This means, that the job is queued without + waiting for job completion */ + +static void usb_kbd_setled(struct usb_device *dev) +{ + struct usb_interface_descriptor *iface = &dev->config.if_desc[0]; + unsigned char *pleds = (unsigned char *)(((unsigned long)leds + 3) & ~3); + if(scroll_lock != 0) + *pleds = 4; + else + *pleds = 0; + if(caps_lock != 0) + *pleds |= 2; + if(num_lock != 0) + *pleds |= 1; + usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_SET_REPORT, USB_TYPE_CLASS | USB_RECIP_INTERFACE, 0x200, iface->bInterfaceNumber, pleds, 1, 0); +} + +static void usb_kbd_send_code(unsigned char code) +{ + //if((iorec != NULL) && (ikbdvec != NULL)) + // call_ikbdvec(code, iorec, ikbdvec); +} + +/* + * Translate the scancode + */ +static int usb_kbd_translate(unsigned char scancode, unsigned char modifier, int pressed) +{ + unsigned char keycode = 0; + unsigned char atari_modifier = 0; +#ifdef CONFIG_USB_INTERRUPT_POLLING + int level; +#endif + + int type = USA; + + (void) type; /* TODO: just for now - avoid compiler warning */ + dbg("USB KBD scancode: 0x%02x, modifier:0x%02x, pressed: %d\r\n", scancode, modifier, pressed); + flags.b.force_alt_shift = 0; + + if(scancode > MAX_VALUE_LOOKUP) + { + keycode = 0; + } + else + { + if(scancode == 0x8A) /* LEFT ALT */ + { + keycode = 0x38; /* Alt Atari */ + } + else + { + unsigned char *unshift_table = NULL; + unsigned char *shift_table = NULL; + unsigned char *altgr_table = NULL; + unsigned char *modifier_table = NULL; + unsigned long lang = USA; + + //USB_COOKIE *p = usb_get_cookie('_AKP'); + //if(p != NULL) + // lang = (p->v.l >> 8) & 0xFF; + +#ifdef USE_COUNTRYCODE + switch(usb_kbd_hid_desc.bCountryCode) + { + case CC_USA: lang = USA; break; + case CC_FRG: lang = FRG; break; + case CC_FRA: lang = FRA; break; + case CC_UK: lang = UK; break; + case CC_SPA: lang = SPA; break; + case CC_ITA: lang = ITA; break; + case CC_SWE: lang = SWE; break; + case CC_SWF: lang = SWF; break; + case CC_SWG: lang = SWG; break; + } +#endif + switch(lang) + { + case FRA: + case SWF: + unshift_table = usb_kbd_to_atari_fr_unshift; + shift_table = usb_kbd_to_atari_fr_shift; + altgr_table = usb_kbd_to_atari_fr_altgr; + modifier_table = usb_kbd_to_atari_fr_modifier; + type = FRA; + break; + + case FRG: + case SWG: + unshift_table = usb_kbd_to_atari_de_unshift; + shift_table = usb_kbd_to_atari_de_shift; + altgr_table = usb_kbd_to_atari_de_altgr; + modifier_table = usb_kbd_to_atari_de_modifier; + type = FRG; + break; + + default: + unshift_table = usb_kbd_to_atari_scancode; + break; + } + + if (modifier != old_modifier) + { + if (((modifier & (1 << LEFT_SHIFT)) != 0) || ((modifier & (1 << RIGHT_SHIFT)) != 0)) + { + if (!flags.b.shift_usb) + { + flags.b.shift_usb = 1; + flags.b.shift_usb_break = 1; + } + } + else + { + flags.b.shift_usb = 0; + } + + if ((modifier & (1 << RIGHT_ALT)) != 0) + { + if (!flags.b.altgr_usb) + { + flags.b.altgr_usb = 1; + flags.b.altgr_usb_break = 1; + } + } + else + { + flags.b.altgr_usb = 0; + } + old_modifier = modifier; + } + else if (pressed) + { + if (!flags.b.altgr_usb) + { + flags.b.altgr_usb_break = 0; + } + if (!flags.b.shift_usb) + { + flags.b.shift_usb_break = 0; + } + } + keycode = unshift_table[scancode]; + + if ((modifier & (1 << LEFT_ALT)) == 0) + { + /* + * This modifier table can change host SHIFT & ALT states for each scancode, values + * are in hexa : bit 7: 1 for a valid entry + * bit 6: 1 for force CTRL + * bit 5: ALT, bit 4: SHIFT states for the AltGR table + * bit 3: ALT, bit 2: SHIFT states for the Shift table + * bit 1: ALT, bit 0: SHIFT states for the Unshift table + */ + if (modifier_table != NULL) + { + atari_modifier = modifier_table[scancode]; + } + else + { + atari_modifier = 0; + } + + if ((atari_modifier & (1 << 7)) != 0) + { + flags.b.force_alt_shift = 1; + } + else + { + atari_modifier = 0; + } + + if (flags.b.altgr_usb_break) + { + if (altgr_table[scancode]) + { + keycode = altgr_table[scancode]; + if ((atari_modifier & (1 << 6)) != 0) + { + atari_modifier = (atari_modifier >> 4) | (atari_modifier & (1 << 6)); + } + else + { + atari_modifier >>= 4; + } + } + } + else if (flags.b.shift_usb_break) + { + if (shift_table[scancode]) + { + keycode = shift_table[scancode]; + if ((atari_modifier & (1 << 6)) != 0) + { + atari_modifier = (atari_modifier >> 2) | (atari_modifier & (1 << 6)); + } + else + { + atari_modifier >>= 2; + } + } + } + } + } + } + dbg("USB KBD atari-%s keycode:0x%02x, modifier:0x%02x, flags:0x%04x\r\n", (type == FRA) ? "fr" : (type == FRG) ? "de" : "us", keycode, atari_modifier, flags.s); + + if (keycode == 0x1D) /* CTRL */ + { + if(pressed) + flags.b.ctrl_host = 1; + else + flags.b.ctrl_host = 0; + } + if(keycode == 0x36) /* RSHIFT */ + { + if(pressed) + flags.b.right_shift_host = 1; + else + flags.b.right_shift_host = 0; + } + if(keycode == 0x2A) /* LSHIFT */ + { + if(pressed) + flags.b.left_shift_host = 1; + else + flags.b.left_shift_host = 0; + } +#ifdef CONFIG_USB_INTERRUPT_POLLING + level = set_ipl(7); /* mask interrupts for use call_ikbdvec() */ +#endif + if(pressed && (flags.b.force_alt_shift)) + { + flags.b.key_forced = 1; + if(((atari_modifier & (1 << 6)) != 0) && flags.b.ctrl_host) + usb_kbd_send_code(0x1D); /* CTRL */ + if((atari_modifier & (1 << 0)) == 0) + { + if(flags.b.left_shift_host) + usb_kbd_send_code(0xAA); /* !LSHIFT */ + if(flags.b.right_shift_host) + usb_kbd_send_code(0xB6); /* !RSHIFT */ + } + else + { + if(!flags.b.left_shift_host) + usb_kbd_send_code(0x2A); /* LSHIFT */ + if(!flags.b.right_shift_host && (keycode != 0x60)) /* < */ + usb_kbd_send_code(0x36); /* RSHIFT */ + } + if((atari_modifier & (1 << 1)) == 0) + { + if(flags.b.alt_host) + usb_kbd_send_code(0xB8); /* !ALT */ + } + else + { + if(!flags.b.alt_host) + usb_kbd_send_code(0x38); /* ALT */ + } + } + if ((keycode !=0) && (keycode <= MAX_VALUE_ATARI)) + usb_kbd_send_code(pressed ? keycode : keycode | 0x80); + if(!pressed && (flags.b.force_alt_shift)) + { + flags.b.key_forced = 0; + if(((atari_modifier & (1 << 6)) != 0) && flags.b.ctrl_host) + usb_kbd_send_code(0x9D); /* !CTRL */ + if((atari_modifier & (1 << 0)) == 0) + { + if(flags.b.left_shift_host) + usb_kbd_send_code(0x2A); /* LSHIFT */ + if(flags.b.right_shift_host) + usb_kbd_send_code(0x36); /* RSHIFT */ + } + else + { + if(!flags.b.left_shift_host) + usb_kbd_send_code(0xAA); /* !LSHIFT */ + if(!flags.b.right_shift_host) + usb_kbd_send_code(0xB6); /* !RSHIFT */ + } + if((atari_modifier & (1 << 1)) == 0) + { + if(flags.b.alt_host) + usb_kbd_send_code(0x38); /* ALT */ + } + else + { + if(!flags.b.alt_host) + usb_kbd_send_code(0xB8); /* !ALT */ + } + } +#ifdef CONFIG_USB_INTERRUPT_POLLING + set_ipl(level); +#endif + if (pressed == 1) + { + if(scancode == NUM_LOCK) + { + num_lock = ~num_lock; + return 1; + } + if(scancode == CAPS_LOCK) + { + caps_lock = ~caps_lock; + return 1; + } + if(scancode == SCROLL_LOCK) + { + scroll_lock = ~scroll_lock; + return 1; + } + } + return 0; +} + +/* Interrupt service routine */ +static int usb_kbd_irq(struct usb_device *dev) +{ + int i,res; + if((dev->irq_status != 0) || (dev->irq_act_len != 8)) + { + dbg("USB KBD error %lX, len %d\r\n",dev->irq_status,dev->irq_act_len); + return 1; + } + res = 0; + for(i = 2; i < 8; i++) + { + if(old_packet[i] > 3 && memscan(&new_packet[2], old_packet[i], 6) == &new_packet[8]) + { + res |= usb_kbd_translate(old_packet[i], new_packet[0], 0); + old_packet[0] = new_packet[0]; + } + if(new_packet[i] > 3 && memscan(&old_packet[2], new_packet[i], 6) == &old_packet[8]) + { + res |= usb_kbd_translate(new_packet[i], new_packet[0], 1); + old_packet[0] = new_packet[0]; + } + } + if(new_packet[0] != old_packet[0]) /* modifier change */ + { + unsigned char modifier_change = new_packet[0] ^ old_packet[0]; + if(modifier_change & (1 << LEFT_CNTR)) + res |= usb_kbd_translate(0x88, new_packet[0], (new_packet[0] & (1 << LEFT_CNTR)) ? 1 : 0); + if(modifier_change & (1 << LEFT_SHIFT)) + res |= usb_kbd_translate(0x89, new_packet[0], (new_packet[0] & (1 << LEFT_SHIFT)) ? 1 : 0); + if(modifier_change & (1 << LEFT_ALT)) + res |= usb_kbd_translate(0x8A, new_packet[0], (new_packet[0] & (1 << LEFT_ALT)) ? 1 : 0); + if(modifier_change & (1 << LEFT_GUI)) + res |= usb_kbd_translate(0x8B, new_packet[0], (new_packet[0] & (1 << LEFT_GUI)) ? 1 : 0); + if(modifier_change & (1 << RIGHT_CNTR)) + res |= usb_kbd_translate(0x8C, new_packet[0], (new_packet[0] & (1 << RIGHT_CNTR)) ? 1 : 0); + if(modifier_change & (1 << RIGHT_SHIFT)) + res |= usb_kbd_translate(0x8D, new_packet[0], (new_packet[0] & (1 << RIGHT_SHIFT)) ? 1 : 0); + if(modifier_change & (1 << RIGHT_ALT)) + res |= usb_kbd_translate(0x8E, new_packet[0], (new_packet[0] & (1 << RIGHT_ALT)) ? 1 : 0); + if(modifier_change & (1 << RIGHT_GUI)) + res |= usb_kbd_translate(0x8F, new_packet[0], (new_packet[0] & (1 << RIGHT_GUI)) ? 1 : 0); + } + if(res == 1) + usb_kbd_setled(dev); + memcpy(&old_packet[0], &new_packet[0], 8); + return 1; /* install IRQ Handler again */ +} + +/* + * probes the USB device dev for keyboard type + */ +static int usb_kbd_probe(struct usb_device *dev, unsigned int ifnum) +{ + struct usb_interface_descriptor *iface; + struct usb_endpoint_descriptor *ep; + int pipe; + int maxp; + + if (dev->descriptor.bNumConfigurations != 1) + { + dbg("device has more than one single configuration\r\n"); + + return 0; + } + + iface = &dev->config.if_desc[ifnum]; + + if (iface->bInterfaceClass != USB_CLASS_HID) + { + dbg("device is not a HID device\r\n"); + + return 0; + } + + if(iface->bInterfaceSubClass != 1) + { + dbg("device interface subclass != USB_SUB_HID_BOOT\r\n"); + + return 0; + } + + if (iface->bInterfaceProtocol != USB_PROT_HID_KEYBOARD) + { + dbg("device is not a keyboard\r\n"); + + return 0; + } + + if (iface->bNumEndpoints != 1) + { + dbg("device has %d endpoints instead of 1\r\n", iface->bNumEndpoints); + + return 0; + } + + ep = &iface->ep_desc[0]; + + if (!(ep->bEndpointAddress & 0x80)) + { + dbg("ep->bEndpointAddress & 0x80 = 0x%x\r\n", ep->bEndpointAddress & 0x80); + + return 0; + } + + if ((ep->bmAttributes & 3) != 3) + { + dbg("ep->bmAttributes & 3 != 3 (%d)\r\n", ep->bmAttributes & 3); + + return 0; + } + + leds = (unsigned char *) driver_mem_alloc(8); + + if (leds == NULL) + { + dbg("could not allocate memory for leds\r\n"); + + return 0; + } + + new_packet = (unsigned char *) driver_mem_alloc(8); + if (new_packet == NULL) + { + dbg("could not allocate memory for new_packed\r\n"); + + driver_mem_free(leds); + + return 0; + } + + dbg("USB KBD found, set protocol...\r\n"); + + /* ok, we found a USB Keyboard, install it */ +#ifdef USE_COUNTRYCODE + if(usb_kbd_get_hid_desc(dev) < 0) + usb_kbd_hid_desc.bCountryCode = CC_NOT; +#endif + + usb_set_protocol(dev, iface->bInterfaceNumber, 0); + + dbg("USB KBD found, set idle...\r\n"); + usb_set_idle(dev, iface->bInterfaceNumber, REPEAT_RATE, 0); + + memset(&new_packet[0], 0, 8); + memset(&old_packet[0], 0, 8); + + pipe = usb_rcvintpipe(dev, ep->bEndpointAddress); + + maxp = usb_maxpacket(dev, pipe); + + dev->irq_handle = usb_kbd_irq; + + dbg("USB KBD enable interrupt pipe (maxp: %d)...\r\n", maxp); + usb_submit_int_msg(dev, pipe, &new_packet[0], maxp > 8 ? 8 : maxp, ep->bInterval); + + return 1; +} + +#ifdef USE_COUNTRYCODE + +/* + * We parse each description item into this structure. Short items data + * values are expanded to 32-bit signed int, long items contain a pointer + * into the data area. + */ + +struct hid_item +{ + unsigned char format; + unsigned char size; + unsigned char type; + unsigned char tag; + union + { + unsigned char u_8; + char s_8; + unsigned short u_16; + short s_16; + unsigned long u_32; + long s_32; + unsigned char *longdata; + } data; +}; + +/* HID report item format */ +#define HID_ITEM_FORMAT_SHORT 0 +#define HID_ITEM_FORMAT_LONG 1 + +/* Special tag indicating long items */ +#define HID_ITEM_TAG_LONG 15 + +#ifdef USB_KBD_DEBUG + +void usb_kbd_display_hid(struct usb_hid_descriptor *hid) +{ + board_printf("USB_HID_DESC:\r\n"); + board_printf(" bLenght 0x%x\r\n",hid->bLength); + board_printf(" bcdHID 0x%x\r\n",hid->bcdHID); + board_printf(" bCountryCode %d\r\n",hid->bCountryCode); + board_printf(" bNumDescriptors 0x%x\r\n",hid->bNumDescriptors); + board_printf(" bReportDescriptorType 0x%x\r\n",hid->bReportDescriptorType); + board_printf(" wDescriptorLength 0x%x\r\n",hid->wDescriptorLength); +} + +/* + * Fetch a report description item from the data stream. We support long + * items, though they are not used yet. + */ + +static int fetch_item(unsigned char *start, unsigned char *end, struct hid_item *item) +{ + if((end - start) > 0) + { + unsigned char b = *start++; + item->type = (b >> 2) & 3; + item->tag = (b >> 4) & 15; + if(item->tag == HID_ITEM_TAG_LONG) + { + item->format = HID_ITEM_FORMAT_LONG; + if((end - start) >= 2) + { + item->size = *start++; + item->tag = *start++; + if((end - start) >= item->size) + { + item->data.longdata = start; + start += item->size; + return item->size; + } + } + } + else + { + item->format = HID_ITEM_FORMAT_SHORT; + item->size = b & 3; + switch(item->size) + { + case 0: + return item->size; + case 1: + if((end - start) >= 1) + { + item->data.u_8 = *start++; + return item->size; + } + break; + case 2: + if((end - start) >= 2) + { + item->data.u_16 = le16_to_cpu(*(unsigned short *)start); + start+=2; + return item->size; + } + case 3: + item->size++; + if((end - start) >= 4) + { + item->data.u_32 = le32_to_cpu(*(unsigned long *)start); + start+=4; + return item->size; + } + } + } + } + return -1; +} + +#endif /* USB_KBD_DEBUG */ + +/* + * HID report descriptor item type (prefix bit 2,3) + */ + +#define HID_ITEM_TYPE_MAIN 0 +#define HID_ITEM_TYPE_GLOBAL 1 +#define HID_ITEM_TYPE_LOCAL 2 +#define HID_ITEM_TYPE_RESERVED 3 +/* + * HID report descriptor main item tags + */ + +#define HID_MAIN_ITEM_TAG_INPUT 8 +#define HID_MAIN_ITEM_TAG_OUTPUT 9 +#define HID_MAIN_ITEM_TAG_FEATURE 11 +#define HID_MAIN_ITEM_TAG_BEGIN_COLLECTION 10 +#define HID_MAIN_ITEM_TAG_END_COLLECTION 12 +/* + * HID report descriptor main item contents + */ + +#define HID_MAIN_ITEM_CONSTANT 0x001 +#define HID_MAIN_ITEM_VARIABLE 0x002 +#define HID_MAIN_ITEM_RELATIVE 0x004 +#define HID_MAIN_ITEM_WRAP 0x008 +#define HID_MAIN_ITEM_NONLINEAR 0x010 +#define HID_MAIN_ITEM_NO_PREFERRED 0x020 +#define HID_MAIN_ITEM_NULL_STATE 0x040 +#define HID_MAIN_ITEM_VOLATILE 0x080 +#define HID_MAIN_ITEM_BUFFERED_BYTE 0x100 + +/* + * HID report descriptor collection item types + */ + +#define HID_COLLECTION_PHYSICAL 0 +#define HID_COLLECTION_APPLICATION 1 +#define HID_COLLECTION_LOGICAL 2 +/* + * HID report descriptor global item tags + */ + +#define HID_GLOBAL_ITEM_TAG_USAGE_PAGE 0 +#define HID_GLOBAL_ITEM_TAG_LOGICAL_MINIMUM 1 +#define HID_GLOBAL_ITEM_TAG_LOGICAL_MAXIMUM 2 +#define HID_GLOBAL_ITEM_TAG_PHYSICAL_MINIMUM 3 +#define HID_GLOBAL_ITEM_TAG_PHYSICAL_MAXIMUM 4 +#define HID_GLOBAL_ITEM_TAG_UNIT_EXPONENT 5 +#define HID_GLOBAL_ITEM_TAG_UNIT 6 +#define HID_GLOBAL_ITEM_TAG_REPORT_SIZE 7 +#define HID_GLOBAL_ITEM_TAG_REPORT_ID 8 +#define HID_GLOBAL_ITEM_TAG_REPORT_COUNT 9 +#define HID_GLOBAL_ITEM_TAG_PUSH 10 +#define HID_GLOBAL_ITEM_TAG_POP 11 + +/* + * HID report descriptor local item tags + */ + +#define HID_LOCAL_ITEM_TAG_USAGE 0 +#define HID_LOCAL_ITEM_TAG_USAGE_MINIMUM 1 +#define HID_LOCAL_ITEM_TAG_USAGE_MAXIMUM 2 +#define HID_LOCAL_ITEM_TAG_DESIGNATOR_INDEX 3 +#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MINIMUM 4 +#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MAXIMUM 5 +#define HID_LOCAL_ITEM_TAG_STRING_INDEX 7 +#define HID_LOCAL_ITEM_TAG_STRING_MINIMUM 8 +#define HID_LOCAL_ITEM_TAG_STRING_MAXIMUM 9 +#define HID_LOCAL_ITEM_TAG_DELIMITER 10 + +#ifdef USB_KBD_DEBUG +static void usb_kbd_show_item(struct hid_item *item) +{ + switch(item->type) + { + case HID_ITEM_TYPE_MAIN: + switch(item->tag) + { + case HID_MAIN_ITEM_TAG_INPUT: board_printf("Main Input"); break; + case HID_MAIN_ITEM_TAG_OUTPUT: board_printf("Main Output"); break; + case HID_MAIN_ITEM_TAG_FEATURE: board_printf("Main Feature"); break; + case HID_MAIN_ITEM_TAG_BEGIN_COLLECTION: board_printf("Main Begin Collection"); break; + case HID_MAIN_ITEM_TAG_END_COLLECTION: board_printf("Main End Collection"); break; + default: board_printf("Main reserved %d",item->tag); break; + } + break; + case HID_ITEM_TYPE_GLOBAL: + switch(item->tag) + { + case HID_GLOBAL_ITEM_TAG_USAGE_PAGE: board_printf("- Global Usage Page"); break; + case HID_GLOBAL_ITEM_TAG_LOGICAL_MINIMUM: board_printf("- Global Logical Minimum"); break; + case HID_GLOBAL_ITEM_TAG_LOGICAL_MAXIMUM: board_printf("- Global Logical Maximum"); break; + case HID_GLOBAL_ITEM_TAG_PHYSICAL_MINIMUM: board_printf("- Global physical Minimum"); break; + case HID_GLOBAL_ITEM_TAG_PHYSICAL_MAXIMUM: board_printf("- Global physical Maximum"); break; + case HID_GLOBAL_ITEM_TAG_UNIT_EXPONENT: board_printf("- Global Unit Exponent"); break; + case HID_GLOBAL_ITEM_TAG_UNIT: board_printf("- Global Unit"); break; + case HID_GLOBAL_ITEM_TAG_REPORT_SIZE: board_printf("- Global Report Size"); break; + case HID_GLOBAL_ITEM_TAG_REPORT_ID: board_printf("- Global Report ID"); break; + case HID_GLOBAL_ITEM_TAG_REPORT_COUNT: board_printf("- Global Report Count"); break; + case HID_GLOBAL_ITEM_TAG_PUSH: board_printf("- Global Push"); break; + case HID_GLOBAL_ITEM_TAG_POP: board_printf("- Global Pop"); break; + default: board_printf("- Global reserved %d",item->tag); break; + } + break; + case HID_ITEM_TYPE_LOCAL: + switch(item->tag) + { + case HID_LOCAL_ITEM_TAG_USAGE: board_printf("-- Local Usage"); break; + case HID_LOCAL_ITEM_TAG_USAGE_MINIMUM: board_printf("-- Local Usage Minimum"); break; + case HID_LOCAL_ITEM_TAG_USAGE_MAXIMUM: board_printf("-- Local Usage Maximum"); break; + case HID_LOCAL_ITEM_TAG_DESIGNATOR_INDEX: board_printf("-- Local Designator Index"); break; + case HID_LOCAL_ITEM_TAG_DESIGNATOR_MINIMUM: board_printf("-- Local Designator Minimum"); break; + case HID_LOCAL_ITEM_TAG_DESIGNATOR_MAXIMUM: board_printf("-- Local Designator Maximum"); break; + case HID_LOCAL_ITEM_TAG_STRING_INDEX: board_printf("-- Local String Index"); break; + case HID_LOCAL_ITEM_TAG_STRING_MINIMUM: board_printf("-- Local String Minimum"); break; + case HID_LOCAL_ITEM_TAG_STRING_MAXIMUM: board_printf("-- Local String Maximum"); break; + case HID_LOCAL_ITEM_TAG_DELIMITER: board_printf("-- Local Delimiter"); break; + default: board_printf("-- Local reserved %d",item->tag); break; + } + break; + default: + board_printf("--- reserved %d",item->type); + break; + } + board_printf(" "); + switch(item->size) + { + case 1: board_printf("%d",item->data.u_8); break; + case 2: board_printf("%d",item->data.u_16); break; + case 4: board_printf("%ld",item->data.u_32); break; + } + board_printf("\r\n"); +} +#endif /* USB_KBD_DEBUG */ + +static int usb_kbd_get_hid_desc(struct usb_device *dev) +{ + unsigned char *buffer = (unsigned char *)driver_mem_alloc(256); + struct usb_descriptor_header *head; + struct usb_config_descriptor *config; + int index, len; +#ifdef USB_KBD_DEBUG + int i; + unsigned char *start, *end; + struct hid_item item; +#endif + if(buffer == NULL) + return -1; + if(usb_get_configuration_no(dev, &buffer[0], 0) == -1) + { + driver_mem_free(buffer); + return -1; + } + head = (struct usb_descriptor_header *)&buffer[0]; + if(head->bDescriptorType!=USB_DT_CONFIG) + { + dbg(" ERROR: NOT USB_CONFIG_DESC %x\r\n",head->bDescriptorType); + driver_mem_free(buffer); + return -1; + } + index = head->bLength; + config = (struct usb_config_descriptor *)&buffer[0]; + len = le16_to_cpu(config->wTotalLength); + /* Ok the first entry must be a configuration entry, now process the others */ + head = (struct usb_descriptor_header *)&buffer[index]; + while(index+1 < len) + { + if(head->bDescriptorType == USB_DT_HID) + { + dbg("HID desc found\r\n"); + memcpy(&usb_kbd_hid_desc, &buffer[index],buffer[index]); + le16_to_cpus(&usb_kbd_hid_desc.bcdHID); + le16_to_cpus(&usb_kbd_hid_desc.wDescriptorLength); +#ifdef USB_KBD_DEBUG + usb_kbd_display_hid(&usb_kbd_hid_desc); +#endif + len = 0; + break; + } + index += head->bLength; + head = (struct usb_descriptor_header *)&buffer[index]; + } + if(len > 0) + { + driver_mem_free(buffer); + return -1; + } +#ifdef USB_KBD_DEBUG + len = usb_kbd_hid_desc.wDescriptorLength; + if((index = usb_get_class_descriptor(dev, 0, USB_DT_REPORT, 0, &buffer[0], len)) < 0) + { + dbg("reading report descriptor failed\r\n"); + driver_mem_free(buffer); + return -1; + } + dbg(" report descriptor (size %u, read %d)\r\n", len, index); + start = &buffer[0]; + end = &buffer[len]; + i = 0; + do + { + index = fetch_item(start, end, &item); + i += index; + i++; + if(index >= 0) + usb_kbd_show_item(&item); + start += index; + start++; + } + while(index >= 0); +#endif /* USB_KBD_DEBUG */ + driver_mem_free(buffer); + return 0; +} + +#endif /* USE_COUNTRYCODE */ + +/* + usb_get_report(dev, 0, 0, 1, &new_packet[0], 8); +*/ + diff --git a/usb/usb_mouse.c b/usb/usb_mouse.c new file mode 100644 index 0000000..89ae9d7 --- /dev/null +++ b/usb/usb_mouse.c @@ -0,0 +1,296 @@ +/* + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include "bas_printf.h" +#include "usb.h" +#include "exceptions.h" +#include "driver_mem.h" + +// // #define DEBUG +#include "debug.h" + +extern void ltoa(char *buf, long n, unsigned long base); +extern void call_mousevec(unsigned char *data, void (**mousevec)(void *)); +//extern void call_ikbdvec(unsigned char code, _IOREC *iorec, void (**ikbdvec)()); + +static unsigned char *new; +static unsigned char old[8]; +static int mouse_installed; + +/* forward declaration */ +static int usb_mouse_probe(struct usb_device *dev, unsigned int ifnum); + +/* deregistering the mouse */ +int usb_mouse_deregister(struct usb_device *dev) +{ + dev->irq_handle = NULL; + if (new != NULL) + { + driver_mem_free(new); + new = NULL; + } + mouse_installed = 0; + dbg("USB MOUSE deregister\r\n"); + return 1; +} + +/* registering the mouse */ +int usb_mouse_register(struct usb_device *dev) +{ + if (!mouse_installed && (dev->devnum != -1) && (usb_mouse_probe(dev, 0) == 1)) + { + /* Ok, we found a mouse */ + dbg("USB MOUSE found (USB: %d, devnum: %d)\r\n", dev->usbnum, dev->devnum); + mouse_installed = 1; + dev->deregister = usb_mouse_deregister; + return 1; + } + /* no USB Mouse found */ + return -1; +} + +/* search for mouse and register it if found */ +int drv_usb_mouse_init(void) +{ + int i; + int j; + + /* + * check if mouse is already initialized + */ + if (mouse_installed) + { + xprintf("USB mouse already initialized\r\n"); + + return -1; + } + + /* scan all USB Devices */ + for (j = 0; j < USB_MAX_BUS; j++) + { + for (i = 0; i < USB_MAX_DEVICE; i++) + { + struct usb_device *dev = usb_get_dev_index(i, j); /* get device */ + + if (dev == NULL) + { + break; + } + + xprintf("Try to register usb device %d,%d as mouse\r\n", i, j); + if (usb_mouse_register(dev) > 0) + return 1; + } + } + /* no USB Mouse found */ + return -1; +} + +/************************************************************************** + * Low Level drivers + */ +static void usb_kbd_send_code(unsigned char code) +{ + dbg("FIXME: usb_kbd_send_code 0x%x not implemented\r\n", code); +} + +/* Interrupt service routine */ +static int usb_mouse_irq(struct usb_device *dev) +{ +#ifdef CONFIG_USB_INTERRUPT_POLLING + int level; +#endif + int i, change = 0; + if ((dev->irq_status != 0) || (dev->irq_act_len < 3) || (dev->irq_act_len > 8)) + { + dbg("USB MOUSE error %lX, len %d\r\n", dev->irq_status, dev->irq_act_len); + return 1; + } + for (i = 0; i < dev->irq_act_len; i++) + { + if (new[i] != old[i]) + { + change = 1; + break; + } + } + if (change) + { + char wheel = 0, buttons, old_buttons; + dbg("USB MOUSE len:%d %02X %02X %02X %02X %02X %02X\r\n", dev->irq_act_len, new[0], new[1], new[2], new[3], new[4], new[5]); +#ifdef CONFIG_USB_INTERRUPT_POLLING + level = set_ipl(7); /* mask interrupts */ +#endif + if ((dev->irq_act_len >= 6) && (new[0] == 1)) /* report-ID */ + { + buttons = new[1]; + old_buttons = old[1]; + new[0] = ((new[1] & 1) << 1) + ((new[1] & 2) >> 1) + 0xF8; + new[1] = new[2]; + new[2] = new[3]; + wheel = new[4]; + } + else /* boot report */ + { + buttons = new[0]; + old_buttons = old[0]; + new[0] = ((new[0] & 1) << 1) + ((new[0] & 2) >> 1) + 0xF8; + if (dev->irq_act_len >= 3) + wheel = new[3]; + } + if ((buttons ^ old_buttons) & 4) /* 3rd button */ + { + if (buttons & 4) + { + usb_kbd_send_code(0x72); /* ENTER */ + usb_kbd_send_code(0xF2); + } + } + if (wheel != 0) /* actually like Eiffel */ + { +#define REPEAT_WHEEL 3 + int i; + if (wheel > 0) + { + for (i = 0; i < REPEAT_WHEEL; i++) + { + usb_kbd_send_code(0x48); /* UP */ + usb_kbd_send_code(0xC8); + } + } + else + { + for (i = 0; i < REPEAT_WHEEL; i++) + { + usb_kbd_send_code(0x50); /* DOWN */ + usb_kbd_send_code(0xD0); + } + } + } + xprintf("FIXME: call_mousevec(new, mousevec) not implemented\r\n"); + //if(mousevec != NULL) + //call_mousevec(new, mousevec); +#ifdef CONFIG_USB_INTERRUPT_POLLING + set_ipl(level); +#endif + old[0] = new[0]; + old[1] = new[1]; + old[2] = new[2]; + old[3] = new[3]; + old[4] = new[4]; + old[5] = new[5]; + } + return 1; /* install IRQ Handler again */ +} + +/* probes the USB device dev for mouse type */ +static int usb_mouse_probe(struct usb_device *dev, unsigned int ifnum) +{ + struct usb_interface_descriptor *iface; + struct usb_endpoint_descriptor *ep; + int pipe; + int maxp; + +#ifdef _NOT_USED_ + if (dev->descriptor.bNumConfigurations != 1) + { + dbg("dev->descriptor.bNumConfigurations != 1\r\n"); + + return 0; + } +#endif + + iface = &dev->config.if_desc[ifnum]; + + if (iface->bInterfaceClass != USB_CLASS_HID) + { + dbg("iface->bInterfaceClass != USB_CLASS_HID (%d instead)\r\n", iface->bInterfaceClass); + + return 0; + } + + + if (iface->bInterfaceSubClass != USB_SUB_HID_BOOT) + { + dbg("iface->bInterfaceSubClass != USB_SUB_HID_BOOT (%d instead)\r\n", iface->bInterfaceSubClass); + + return 0; + } + + if (iface->bInterfaceProtocol != USB_PROT_HID_MOUSE) + { + dbg("iface->bInterfaceProtocol != USB_PROT_HID_MOUSE (%d)\r\n", iface->bInterfaceProtocol); + + return 0; + } + + if (iface->bNumEndpoints != 1) + { + dbg("iface->bNumEndpoints != 1\r\n"); + + return 0; + } + + ep = &iface->ep_desc[0]; + + if (!(ep->bEndpointAddress & 0x80)) + { + dbg("! ep->bEndpointAddress & 0x80\r\n"); + + return 0; + } + + if ((ep->bmAttributes & 3) != 3) + { + dbg("ep->bmAttributes & 3 != 3\r\n"); + + return 0; + } + + new = (unsigned char *) driver_mem_alloc(8); + if (new == NULL) + { + dbg("new == NULL\r\n"); + + return 0; + } + + dbg("USB MOUSE found set protocol...\r\n"); + + /* ok, we found a USB Mouse, install it */ + pipe = usb_rcvintpipe(dev, ep->bEndpointAddress); + maxp = usb_maxpacket(dev, pipe); +// if(maxp < 6) +// usb_set_protocol(dev, iface->bInterfaceNumber, 0); /* boot */ +// else + usb_set_protocol(dev, iface->bInterfaceNumber, 1); /* report */ + dbg("USB MOUSE found set idle...\r\n"); + usb_set_idle(dev, iface->bInterfaceNumber, 0, 0); /* report infinite */ + memset(&new[0], 0, 8); + memset(&old[0], 0, 8); + dev->irq_handle = usb_mouse_irq; + dbg("USB MOUSE enable interrupt pipe (maxp: %d)...\r\n", maxp); + usb_submit_int_msg(dev, pipe, &new[0], maxp > 8 ? 8 : maxp, ep->bInterval); + return 1; +} + diff --git a/util/bas_printf.c b/util/bas_printf.c new file mode 100644 index 0000000..35afd81 --- /dev/null +++ b/util/bas_printf.c @@ -0,0 +1,479 @@ +/* + * tc.printf.c: A public-domain, minimal printf/sprintf routine that prints + * through the putchar() routine. Feel free to use for + * anything... -- 7/17/87 Paul Placeway + */ +/*- + * Copyright (c) 1980, 1991 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +#include +#include "MCF5475.h" +#include "bas_printf.h" +#include "bas_string.h" + +/* + * Lexical definitions. + * + * All lexical space is allocated dynamically. + * The eighth/sixteenth bit of characters is used to prevent recognition, + * and eventually stripped. + */ +#define META 0200 +#define ASCII 0177 +#define QUOTE ((char) 0200) /* Eighth char bit used for 'ing */ +#define TRIM 0177 /* Mask to strip quote bit */ +#define UNDER 0000000 /* No extra bits to do both */ +#define BOLD 0000000 /* Bold flag */ +#define STANDOUT META /* Standout flag */ +#define LITERAL 0000000 /* Literal character flag */ +#define ATTRIBUTES 0200 /* The bits used for attributes */ +#define CHAR 0000177 /* Mask to mask out the character */ + +#define INF 32766 /* should be bigger than any field to print */ + +static char snil[] = "(nil)"; + +bool conoutstat(void) +{ + bool stat; + + stat = MCF_PSC0_PSCSR & MCF_PSC_PSCSR_TXRDY; /* TX FIFO can take data */ + + return stat; +} + +bool coninstat(void) +{ + bool stat; + + stat = MCF_PSC0_PSCSR & MCF_PSC_PSCSR_RXRDY; /* RX FIFO has data available */ + + return stat; +} + +void xputchar(int c) +{ + do { ; } while (!conoutstat()); + MCF_PSC_PSCRB_8BIT(0) = (char) c; +} + +char xgetchar(void) +{ + char c; + + do { ; } while (!coninstat()); + c = MCF_PSC_PSCTB_8BIT(0); + + return c; +} + +static void doprnt(void (*addchar)(int), const char *sfmt, va_list ap) +{ + char buf[128]; + char *bp; + const char *f; + float flt; + long l; + unsigned long u; + int i; + int fmt; + unsigned char pad = ' '; + int flush_left = 0; + int f_width = 0; + int prec = INF; + int hash = 0; + int do_long = 0; + int sign = 0; + int attributes = 0; + + f = sfmt; + for (; *f; f++) + { + if (*f != '%') + { + /* then just out the char */ + (*addchar)((int) (((unsigned char) *f) | attributes)); + } + else + { + f++; /* skip the % */ + + if (*f == '-') + { /* minus: flush left */ + flush_left = 1; + f++; + } + + if (*f == '0' || *f == '.') + { + /* padding with 0 rather than blank */ + pad = '0'; + f++; + } + if (*f == '*') + { + /* field width */ + f_width = va_arg(ap, int); + f++; + } + else if (isdigit((unsigned char)*f)) + { + f_width = atoi(f); + while (isdigit((unsigned char)*f)) + f++; /* skip the digits */ + } + + if (*f == '.') + { /* precision */ + f++; + if (*f == '*') + { + prec = va_arg(ap, int); + f++; + } + else if (isdigit((unsigned char)*f)) + { + prec = atoi(f); + while (isdigit((unsigned char)*f)) + f++; /* skip the digits */ + } + } + + if (*f == '#') + { /* alternate form */ + hash = 1; + f++; + } + + if (*f == 'l') + { /* long format */ + do_long++; + f++; + if (*f == 'l') + { + do_long++; + f++; + } + } + + fmt = (unsigned char) *f; + if (fmt != 'S' && fmt != 'Q' && isupper(fmt)) + { + do_long = 1; + fmt = tolower(fmt); + } + bp = buf; + switch (fmt) + { /* do the format */ + case 'd': + switch (do_long) + { + case 0: + l = (long) (va_arg(ap, int)); + break; + case 1: + default: + l = va_arg(ap, long); + break; + } + + if (l < 0) + { + sign = 1; + l = -l; + } + do + { + *bp++ = (char) (l % 10) + '0'; + } while ((l /= 10) > 0); + if (sign) + *bp++ = '-'; + f_width = f_width - (int) (bp - buf); + if (!flush_left) + while (f_width-- > 0) + (*addchar)((int) (pad | attributes)); + for (bp--; bp >= buf; bp--) + (*addchar)((int) (((unsigned char) *bp) | attributes)); + if (flush_left) + while (f_width-- > 0) + (*addchar)((int) (' ' | attributes)); + break; + + case 'f': + /* this is actually more than stupid, but does work for now */ + flt = (float) (va_arg(ap, double)); /* beware: va_arg() extends float to double! */ + if (flt < 0) + { + sign = 1; + flt = -flt; + } + { + int quotient, remainder; + + quotient = (int) flt; + remainder = (flt - quotient) * 10E5; + + for (i = 0; i < 6; i++) + { + *bp++ = (char) (remainder % 10) + '0'; + remainder /= 10; + } + *bp++ = '.'; + do + { + *bp++ = (char) (quotient % 10) + '0'; + } while ((quotient /= 10) > 0); + if (sign) + *bp++ = '-'; + f_width = f_width - (int) (bp - buf); + if (!flush_left) + while (f_width-- > 0) + (*addchar)((int) (pad | attributes)); + for (bp--; bp >= buf; bp--) + (*addchar)((int) (((unsigned char) *bp) | attributes)); + if (flush_left) + while (f_width-- > 0) + (*addchar)((int) (' ' | attributes)); + } + break; + + case 'p': + do_long = 1; + hash = 1; + fmt = 'x'; + /* no break */ + case 'o': + case 'x': + case 'u': + switch (do_long) + { + case 0: + u = (unsigned long) (va_arg(ap, unsigned int)); + break; + case 1: + default: + u = va_arg(ap, unsigned long); + break; + } + if (fmt == 'u') + { /* unsigned decimal */ + do + { + *bp++ = (char) (u % 10) + '0'; + } while ((u /= 10) > 0); + } + else if (fmt == 'o') + { /* octal */ + do + { + *bp++ = (char) (u % 8) + '0'; + } while ((u /= 8) > 0); + if (hash) + *bp++ = '0'; + } + else if (fmt == 'x') + { /* hex */ + do + { + i = (int) (u % 16); + if (i < 10) + *bp++ = i + '0'; + else + *bp++ = i - 10 + 'a'; + } while ((u /= 16) > 0); + if (hash) + { + *bp++ = 'x'; + *bp++ = '0'; + } + } + i = f_width - (int) (bp - buf); + if (!flush_left) + while (i-- > 0) + (*addchar)((int) (pad | attributes)); + for (bp--; bp >= buf; bp--) + (*addchar)((int) (((unsigned char) *bp) | attributes)); + if (flush_left) + while (i-- > 0) + (*addchar)((int) (' ' | attributes)); + break; + + case 'c': + i = va_arg(ap, int); + (*addchar)((int) (i | attributes)); + break; + + case 'S': + case 'Q': + case 's': + case 'q': + bp = va_arg(ap, char *); + if (!bp) + bp = snil; + f_width = f_width - strlen((char *) bp); + if (!flush_left) + while (f_width-- > 0) + (*addchar)((int) (pad | attributes)); + for (i = 0; *bp && i < prec; i++) + { + if (fmt == 'q' && (*bp & QUOTE)) + (*addchar)((int) ('\\' | attributes)); + (*addchar)( + (int) (((unsigned char) *bp & TRIM) | attributes)); + bp++; + } + if (flush_left) + while (f_width-- > 0) + (*addchar)((int) (' ' | attributes)); + break; + + case 'a': + attributes = va_arg(ap, int); + break; + + case '%': + (*addchar)((int) ('%' | attributes)); + break; + + default: + break; + } + flush_left = 0, f_width = 0, prec = INF, hash = 0, do_long = 0; + sign = 0; + pad = ' '; + } + } +} + +static char *xstring, *xestring; + +void xaddchar(int c) +{ + if (xestring == xstring) + *xstring = '\0'; + else + *xstring++ = (char) c; +} + +int sprintf(char *str, const char *format, ...) +{ + va_list va; + va_start(va, format); + + xstring = str; + + doprnt(xaddchar, format, va); + va_end(va); + *xstring++ = '\0'; + + return 0; +} + +void xsnprintf(char *str, size_t size, const char *fmt, ...) +{ + va_list va; + va_start(va, fmt); + + xstring = str; + xestring = str + size - 1; + doprnt(xaddchar, fmt, va); + va_end(va); + *xstring++ = '\0'; +} + +void xprintf(const char *fmt, ...) +{ + va_list va; + va_start(va, fmt); + doprnt(xputchar, fmt, va); + va_end(va); +} + +void xvprintf(const char *fmt, va_list va) +{ + doprnt(xputchar, fmt, va); +} + +void xvsnprintf(char *str, size_t size, const char *fmt, va_list va) +{ + xstring = str; + xestring = str + size - 1; + doprnt(xaddchar, fmt, va); + *xstring++ = '\0'; +} + + +void display_progress() +{ + static int _progress_index; + char progress_char[] = "|/-\\"; + + xputchar(progress_char[_progress_index++ % strlen(progress_char)]); + xputchar('\r'); +} + +void hexdump(uint8_t buffer[], int size) +{ + int i; + int line = 0; + volatile uint8_t *bp = buffer; + + while (bp < buffer + size) { + volatile uint8_t *lbp = bp; + + xprintf("%08x ", line); + + for (i = 0; i < 16; i++) { + uint8_t c = *lbp++; + if (bp + i > buffer + size) { + break; + } + xprintf("%02x ", c); + } + + lbp = bp; + for (i = 0; i < 16; i++) { + volatile int8_t c = *lbp++; + + if (bp + i > buffer + size) { + break; + } + if (c > ' ' && c < '~') { + xprintf("%c", c); + } else { + xprintf("."); + } + } + xprintf("\r\n"); + + bp += 16; + line += 16; + } +} diff --git a/util/bas_string.c b/util/bas_string.c new file mode 100644 index 0000000..64bbe07 --- /dev/null +++ b/util/bas_string.c @@ -0,0 +1,166 @@ +/* + * bas_string.c + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 26.02.2013 + * Author: Markus Fröschle + */ + +#include "bas_types.h" +#include +#include "bas_string.h" + +void *memcpy(void *dst, const void *src, size_t n) +{ + uint8_t *to = dst; + + while (to < (uint8_t *) dst + n) + *to++ = * (uint8_t *) src++; + + return dst; +} + +void *memmove(void *dst, const void *src, size_t n) +{ + uint8_t *to = dst; + + while (to < (uint8_t *) dst + n) + *to++ = * (uint8_t *) src++; + + return dst; +} + +void bzero(void *s, size_t n) +{ + size_t i; + + for (i = 0; i < n; i++) + ((unsigned char *) s)[i] = '\0'; +} + +void *memset(void *s, int c, size_t n) +{ + uint8_t *dst = s; + + do + { + *dst++ = c; + } while ((dst - (uint8_t *) s) < n); + + return s; +} + + +int memcmp(const void *s1, const void *s2, size_t max) +{ + int i; + int cmp = 0; + + for (i = 0; i < max; i++) + { + cmp = (* (const char *) s1 - * (const char *) s2); + if (cmp != 0) return cmp; + } + return cmp; +} + +int strcmp(const char *s1, const char *s2) +{ + int i; + int cmp; + + for (i = 0; *s1++ && *s2++; i++) + { + cmp = (*s1 - *s2); + if (cmp != 0) return cmp; + } + return cmp; +} + +int strncmp(const char *s1, const char *s2, size_t max) +{ + int i; + int cmp = 0; + + for (i = 0; i < max && *s1++ && *s2++; i++) + { + cmp = (*s1 - *s2); + if (cmp != 0) return cmp; + } + return cmp; +} + +char *strcpy(char *dst, const char *src) +{ + char *ptr = dst; + + while ((*dst++ = *src++) != '\0'); + return ptr; +} + +char *strncpy(char *dst, const char *src, size_t max) +{ + char *ptr = dst; + + while ((*dst++ = *src++) != '\0' && max-- >= 0); + return ptr; +} + +int atoi(const char *c) +{ + int value = 0; + while (isdigit(*c)) + { + value *= 10; + value += (int) (*c - '0'); + c++; + } + return value; +} + +size_t strlen(const char *s) +{ + const char *start = s; + + while (*s++); + + return s - start - 1; +} + + +char *strcat(char *dst, const char *src) +{ + char *ret = dst; + dst = &dst[strlen(dst)]; + while ((*dst++ = *src++) != '\0'); + return ret; +} + +char *strncat(char *dst, const char *src, size_t max) +{ + size_t i; + char *ret = dst; + + dst = &dst[strlen(dst)]; + for (i = 0; i < max && *src; i++) + { + *dst++ = *src++; + } + *dst++ = '\0'; + + return ret; +} diff --git a/util/bcopy.S b/util/bcopy.S new file mode 100644 index 0000000..da28648 --- /dev/null +++ b/util/bcopy.S @@ -0,0 +1,352 @@ + +| new version of bcopy, memcpy and memmove +| handles overlap, odd/even alignment +| uses movem to copy 256 bytes blocks faster. +| Alexander Lehmann alexlehm@iti.informatik.th-darmstadt.de +| sortof inspired by jrbs bcopy + + .text + .even + .globl ___bcopy + .globl __bcopy + .globl _bcopy + .globl _memcpy + .globl _memmove + +| void *memcpy( void *dest, const void *src, size_t len ); +| void *memmove( void *dest, const void *src, size_t len ); +| returns dest +| functions are aliased + +#ifndef __SOZOBON__ +_memcpy: +_memmove: + movl sp@(4),a1 | dest + movl sp@(8),a0 | src + jra common | the rest is samea as bcopy +#else +| ___bcopy() is the base function below; for memcpy(), memmove() +| and bcopy(), we have to sneak a size_t into an unsigned long first. + +_memcpy: +_memmove: + movl sp@(4),a1 | dest + movl sp@(8),a0 | src + clrl d0 | here is the sneaky bit... + movw sp@(12),d0 | length + jra common2 | the rest is samea as bcopy + +_bcopy: + movl sp@(4),a0 | src + movl sp@(8),a1 | dest + clrl d0 | here is the sneaky bit... + movw sp@(12),d0 | length + jra common2 | the rest is samea as bcopy +#endif + +| void bcopy( const void *src, void *dest, size_t length ); +| void _bcopy( const void *src, void *dest, unsigned long length ); +| return value not used (returns src) +| functions are aliased (except for HSC -- sb) + +#ifndef __SOZOBON__ +_bcopy: +___bcopy: +#endif +__bcopy: + move.l 4(sp),a0 | src + move.l 8(sp),a1 | dest +common: move.l 12(sp),d0 | length +common2: + jeq exit | length==0? (size_t) + + | a0 src, a1 dest, d0.l length + move.l d2,-(sp) + + | overlay ? + cmp.l a0,a1 + jgt top_down + +#ifdef __mcoldfire__ + move.l a0,d1 | test for alignment + move.l a1,d2 + eor.l d2,d1 +#else + move.w a0,d1 | test for alignment + move.w a1,d2 + eor.w d2,d1 +#endif + btst #0,d1 | one odd one even ? + jne slow_copy + btst #0,d2 | both even ? + jeq both_even + move.b (a0)+,(a1)+ | copy one byte, now we are both even + subq.l #1,d0 +both_even: + moveq #0,d1 | save length less 256 + move.b d0,d1 + lsr.l #8,d0 | number of 256 bytes blocks + jeq less256 +#ifdef __mcoldfire__ + lea -10 * 4(sp),sp + movem.l d1/d3-d7/a2/a3/a5/a6,(sp) | d2 is already saved + | exclude a4 because of -mbaserel +copy256: + movem.l 0(a0),d1-d7/a2/a3/a5/a6 | copy 5*44+36=256 bytes + movem.l d1-d7/a2/a3/a5/a6,a1@ + movem.l 44(a0),d1-d7/a2/a3/a5/a6 + movem.l d1-d7/a2/a3/a5/a6,44(a1) + movem.l 88(a0),d1-d7/a2/a3/a5/a6 + movem.l d1-d7/a2/a3/a5/a6,88(a1) + movem.l 132(a0),d1-d7/a2/a3/a5/a6 + movem.l d1-d7/a2/a3/a5/a6,132(a1) + movem.l 176(a0),d1-d7/a2/a3/a5/a6 + movem.l d1-d7/a2/a3/a5/a6,176(a1) + movem.l 220(a0),d1-d7/a2-a3 + movem.l d1-d7/a2-a3,220(a1) + lea 256(a0),a0 +#else + movem.l d1/d3-d7/a2/a3/a5/a6,-(sp) | d2 is already saved + | exclude a4 because of -mbaserel +copy256: + movem.l (a0)+,d1-d7/a2/a3/a5/a6 | copy 5*44+36=256 bytes + movem.l d1-d7/a2/a3/a5/a6,(a1) + movem.l (a0)+,d1-d7/a2/a3/a5/a6 + movem.l d1-d7/a2/a3/a5/a6,44(a1) + movem.l (a0)+,d1-d7/a2/a3/a5/a6 + movem.l d1-d7/a2/a3/a5/a6,88(a1) + movem.l (a0)+,d1-d7/a2/a3/a5/a6 + movem.l d1-d7/a2/a3/a5/a6,132(a1) + movem.l (a0)+,d1-d7/a2/a3/a5/a6 + movem.l d1-d7/a2/a3/a5/a6,176(a1) + movem.l (a0)+,d1-d7/a2-a3 + movem.l d1-d7/a2-a3,220(a1) +#endif + lea a1@(256),a1 | increment dest, src is already + subql #1,d0 + jne copy256 | next, please +#ifdef __mcoldfire__ + movml sp@,d1/d3-d7/a2/a3/a5/a6 + lea sp@(40),sp +less256: | copy 16 bytes blocks + movl d1,d0 + lsrl #2,d0 | number of 4 bytes blocks + jeq less4 | less that 4 bytes left + movl d0,d2 + negl d2 + andil #3,d2 | d2 = number of bytes below 16 (-n)&3 + subql #1,d0 + lsrl #2,d0 | number of 16 bytes blocks minus 1, if d2==0 + addl d2,d2 | offset in code (movl two bytes) + jmp pc@(2,d2:l) | jmp into loop +#else + movml sp@+,d1/d3-d7/a2/a3/a5/a6 +less256: | copy 16 bytes blocks + movw d1,d0 + lsrw #2,d0 | number of 4 bytes blocks + jeq less4 | less that 4 bytes left + movw d0,d2 + negw d2 + andiw #3,d2 | d2 = number of bytes below 16 (-n)&3 + subqw #1,d0 + lsrw #2,d0 | number of 16 bytes blocks minus 1, if d2==0 + addw d2,d2 | offset in code (movl two bytes) + jmp pc@(2,d2:w) | jmp into loop +#endif +copy16: + movl a0@+,a1@+ + movl a0@+,a1@+ + movl a0@+,a1@+ + movl a0@+,a1@+ +#ifdef __mcoldfire__ + subql #1,d0 + bpl copy16 +#else + dbra d0,copy16 +#endif +less4: + btst #1,d1 + jeq less2 + movw a0@+,a1@+ +less2: + btst #0,d1 + jeq none + movb a0@,a1@ +none: +exit_d2: + movl sp@+,d2 +exit: + movl sp@(4),d0 | return dest (for memcpy only) + rts + +slow_copy: | byte by bytes copy +#ifdef __mcoldfire__ + movl d0,d1 + negl d1 + andil #7,d1 | d1 = number of bytes blow 8 (-n)&7 + addql #7,d0 + lsrl #3,d0 | number of 8 bytes block plus 1, if d1!=0 + addl d1,d1 | offset in code (movb two bytes) + jmp pc@(2,d1:l) | jump into loop +#else + movw d0,d1 + negw d1 + andiw #7,d1 | d1 = number of bytes blow 8 (-n)&7 + addql #7,d0 + lsrl #3,d0 | number of 8 bytes block plus 1, if d1!=0 + addw d1,d1 | offset in code (movb two bytes) + jmp pc@(2,d1:w) | jump into loop +#endif +scopy: + movb a0@+,a1@+ + movb a0@+,a1@+ + movb a0@+,a1@+ + movb a0@+,a1@+ + movb a0@+,a1@+ + movb a0@+,a1@+ + movb a0@+,a1@+ + movb a0@+,a1@+ + subql #1,d0 + jne scopy + jra exit_d2 + +top_down: + addl d0,a0 | a0 byte after end of src + addl d0,a1 | a1 byte after end of dest + +#ifdef __mcoldfire__ + movl a0,d1 | exact the same as above, only with predec + movl a1,d2 + eorl d2,d1 +#else + movw a0,d1 | exact the same as above, only with predec + movw a1,d2 + eorw d2,d1 +#endif + btst #0,d1 + jne slow_copy_d + + btst #0,d2 + jeq both_even_d + movb a0@-,a1@- + subql #1,d0 +both_even_d: + movq #0,d1 + movb d0,d1 + lsrl #8,d0 + jeq less256_d +#ifdef __mcoldfire__ + lea sp@(-40),sp + movml d1/d3-d7/a2/a3/a5/a6,sp@ +copy256_d: + movml a0@(-44),d1-d7/a2/a3/a5/a6 + movml d1-d7/a2/a3/a5/a6,a1@(-44) + movml a0@(-88),d1-d7/a2/a3/a5/a6 + movml d1-d7/a2/a3/a5/a6,a1@(-88) + movml a0@(-132),d1-d7/a2/a3/a5/a6 + movml d1-d7/a2/a3/a5/a6,a1@(-132) + movml a0@(-176),d1-d7/a2/a3/a5/a6 + movml d1-d7/a2/a3/a5/a6,a1@(-176) + movml a0@(-220),d1-d7/a2/a3/a5/a6 + movml d1-d7/a2/a3/a5/a6,a1@(-220) + movml a0@(-256),d1-d7/a2-a3 + movml d1-d7/a2-a3,a1@(-256) + lea a1@(-256),a1 +#else + movml d1/d3-d7/a2/a3/a5/a6,sp@- +copy256_d: + movml a0@(-44),d1-d7/a2/a3/a5/a6 + movml d1-d7/a2/a3/a5/a6,a1@- + movml a0@(-88),d1-d7/a2/a3/a5/a6 + movml d1-d7/a2/a3/a5/a6,a1@- + movml a0@(-132),d1-d7/a2/a3/a5/a6 + movml d1-d7/a2/a3/a5/a6,a1@- + movml a0@(-176),d1-d7/a2/a3/a5/a6 + movml d1-d7/a2/a3/a5/a6,a1@- + movml a0@(-220),d1-d7/a2/a3/a5/a6 + movml d1-d7/a2/a3/a5/a6,a1@- + movml a0@(-256),d1-d7/a2-a3 + movml d1-d7/a2-a3,a1@- +#endif + lea a0@(-256),a0 + subql #1,d0 + jne copy256_d +#ifdef __mcoldfire__ + movml sp@,d1/d3-d7/a2/a3/a5/a6 + lea sp@(40),sp +less256_d: + movl d1,d0 + lsrl #2,d0 + jeq less4_d + movl d0,d2 + negl d2 + andil #3,d2 + subql #1,d0 + lsrl #2,d0 + addl d2,d2 + jmp pc@(2,d2:l) +#else + movml sp@+,d1/d3-d7/a2/a3/a5/a6 +less256_d: + movw d1,d0 + lsrw #2,d0 + jeq less4_d + movw d0,d2 + negw d2 + andiw #3,d2 + subqw #1,d0 + lsrw #2,d0 + addw d2,d2 + jmp pc@(2,d2:w) +#endif +copy16_d: + movl a0@-,a1@- + movl a0@-,a1@- + movl a0@-,a1@- + movl a0@-,a1@- +#ifdef __mcoldfire__ + subql #1,d0 + bpl copy16_d +#else + dbra d0,copy16_d +#endif +less4_d: + btst #1,d1 + jeq less2_d + movw a0@-,a1@- +less2_d: + btst #0,d1 + jeq exit_d2 + movb a0@-,a1@- + jra exit_d2 +slow_copy_d: +#ifdef __mcoldfire__ + movl d0,d1 + negl d1 + andil #7,d1 + addql #7,d0 + lsrl #3,d0 + addl d1,d1 + jmp pc@(2,d1:l) +#else + movw d0,d1 + negw d1 + andiw #7,d1 + addql #7,d0 + lsrl #3,d0 + addw d1,d1 + jmp pc@(2,d1:w) +#endif +scopy_d: + movb a0@-,a1@- + movb a0@-,a1@- + movb a0@-,a1@- + movb a0@-,a1@- + movb a0@-,a1@- + movb a0@-,a1@- + movb a0@-,a1@- + movb a0@-,a1@- + subql #1,d0 + jne scopy_d + jra exit_d2 + diff --git a/util/conout.c b/util/conout.c new file mode 100755 index 0000000..8b307dd --- /dev/null +++ b/util/conout.c @@ -0,0 +1,576 @@ +/* + * conout.c - lowlevel color model dependent screen handling routines + * + * + * Copyright (C) 2004 by Authors (see below) + * Copyright (C) 2016 The EmuTOS development team + * + * Authors: + * MAD Martin Doering + * + * This file is distributed under the GPL, version 2 or at your + * option any later version. See doc/license.txt for details. + */ + +#include "conout.h" +#include "video.h" +#include "font.h" +#include "fb.h" +#include "bas_string.h" + +#define plane_offset 2 /* interleaved planes */ + +#define v_fnt_st fnt->first_ade +#define v_fnt_nd fnt->last_ade +#define v_off_ad fnt->off_table +#define v_bas_ad ((uint8_t *) info_fb->screen_base) + +uint8_t *v_cur_ad; /* cursor address */ +int8_t v_stat_0; /* console status byte */ +uint16_t v_cur_cx; +uint16_t v_cur_cy; +int8_t v_cur_tim; +uint16_t v_cel_mx; +uint16_t v_cel_my; +uint16_t v_cel_wr; +int16_t v_cur_of; +uint16_t v_cel_ht; +int8_t v_period; +const uint16_t *v_fnt_ad; +int16_t v_fbt_wr; +int16_t v_col_bg; +int16_t v_col_fg; +uint16_t v_fnt_wr; + + +#define v_planes (info_fb->var.bits_per_pixel) +extern struct fb_info *info_fb; +#define v_lin_wr (info_fb->var.width / 2) /* length of a screen line in words */ + +/* + * internal prototypes + */ +static void neg_cell(uint8_t *); +static uint8_t * cell_addr(int, int); +static void cell_xfer(uint8_t *, uint8_t *); +static bool next_cell(void); + + +/* + * char_addr - retrieve the address of the source cell + * + * + * Given an offset value. + * + * in: + * ch - source cell code + * + * out: + * pointer to first byte of source cell if code was valid + */ + +static uint8_t *char_addr(int16_t ch) +{ + uint16_t offs; + + /* test against limits */ + if (ch >= v_fnt_st) + { + if (ch <= v_fnt_nd) + { + /* getch offset from offset table */ + offs = v_off_ad[ch]; + offs >>= 3; /* convert from pixels to bytes. */ + + /* return valid address */ + return (uint8_t*) v_fnt_ad + offs; + } + } + + /* invalid code. no address returned */ + return NULL; +} + + + +/* + * ascii_out - prints an ascii character on the screen + * + * in: + * + * ch.w ascii code for character + */ + +void ascii_out(int ch) +{ + uint8_t * src, * dst; + bool visible; /* was the cursor visible? */ + + src = char_addr(ch); /* a0 -> get character source */ + if (src == NULL) + return; /* no valid character */ + + dst = v_cur_ad; /* a1 -> get destination */ + + visible = v_stat_0 & M_CVIS; /* test visibility bit */ + if ( visible ) { + neg_cell(v_cur_ad); /* delete cursor. */ + v_stat_0 &= ~M_CVIS; /* start of critical section */ + } + + /* put the cell out (this covers the cursor) */ + cell_xfer(src, dst); + + /* advance the cursor and update cursor address and coordinates */ + if (next_cell()) + { + uint8_t * cell; + + int y = v_cur_cy; + + /* perform cell carriage return. */ + cell = v_bas_ad + (uint32_t) v_cel_wr * y; + v_cur_cx = 0; /* set X to first cell in line */ + + /* perform cell line feed. */ + if ( y < v_cel_my ) + { + cell += v_cel_wr; /* move down one cell */ + v_cur_cy = y + 1; /* update cursor's y coordinate */ + } + else { + scroll_up(0); /* scroll from top of screen */ + } + v_cur_ad = cell; /* update cursor address */ + } + + /* if visible */ + if ( visible ) { + neg_cell(v_cur_ad); /* display cursor. */ + v_stat_0 |= M_CSTATE; /* set state flag (cursor on). */ + v_stat_0 |= M_CVIS; /* end of critical section. */ + + /* do not flash the cursor when it moves */ + if (v_stat_0 & M_CFLASH) { + v_cur_tim = v_period; /* reset the timer. */ + } + } +} + + + + +/* + * blank_out - Fills region with the background color. + * + * Fills a cell-word aligned region with the background color. + * + * The rectangular region is specified by a top/left cell x,y and a + * bottom/right cell x,y, inclusive. Routine assumes top/left x is + * even and bottom/right x is odd for cell-word alignment. This is, + * because this routine is heavily optimized for speed, by always + * blanking as much space as possible in one go. + * + * in: + * topx - top/left cell x position (must be even) + * topy - top/left cell y position + * botx - bottom/right cell x position (must be odd) + * boty - bottom/right cell y position + */ + +void blank_out(int topx, int topy, int botx, int boty) +{ + +} + + + +/* + * cell_addr - convert cell X,Y to a screen address. + * + * + * convert cell X,Y to a screen address. also clip cartesian coordinates + * to the limits of the current screen. + * + * latest update: + * + * 18-sep-84 + * in: + * + * d0.w cell X + * d1.w cell Y + * + * out: + * a1 points to first byte of cell + */ + +static uint8_t *cell_addr(int x, int y) +{ + int32_t disx, disy; + + /* check bounds against screen limits */ + if ( x >= v_cel_mx ) + x = v_cel_mx; /* clipped x */ + + if ( y >= v_cel_my ) + y = v_cel_my; /* clipped y */ + + /* X displacement = even(X) * v_planes + Xmod2 */ + disx = (int32_t)v_planes * (x & ~1); + if ( x & 1 ) { /* Xmod2 = 0 ? */ + disx++; /* Xmod2 = 1 */ + } + + /* Y displacement = Y // cell conversion factor */ + disy = (int32_t)v_cel_wr * y; + + /* + * cell address = screen base address + Y displacement + * + X displacement + offset from screen-begin (fix) + */ + return v_bas_ad + disy + disx + v_cur_of; +} + + + +/* + * cell_xfer - Performs a byte aligned block transfer. + * + * + * This routine performs a byte aligned block transfer for the purpose of + * manipulating monospaced byte-wide text. the routine maps a single-plane, + * arbitrarily-long byte-wide image to a multi-plane bit map. + * all transfers are byte aligned. + * + * in: + * a0.l points to contiguous source block (1 byte wide) + * a1.l points to destination (1st plane, top of block) + * + * out: + * a4 points to byte below this cell's bottom + */ + +static void cell_xfer(uint8_t * src, uint8_t * dst) +{ + uint8_t * src_sav, * dst_sav; + uint16_t fg; + uint16_t bg; + int fnt_wr, line_wr; + int plane; + + fnt_wr = v_fnt_wr; + line_wr = v_lin_wr; + + /* check for reversed foreground and background colors */ + if ( v_stat_0 & M_REVID) + { + fg = v_col_bg; + bg = v_col_fg; + } + else + { + fg = v_col_fg; + bg = v_col_bg; + } + + src_sav = src; + dst_sav = dst; + + for (plane = v_planes; plane--;) + { + int i; + + src = src_sav; /* reload src */ + dst = dst_sav; /* reload dst */ + + if (bg & 0x0001) + { + if (fg & 0x0001) + { + /* back:1 fore:1 => all ones */ + for (i = v_cel_ht; i--;) + { + *dst = 0xff; /* inject a block */ + dst += line_wr; + } + } + else + { + /* back:1 fore:0 => invert block */ + for (i = v_cel_ht; i--; ) + { + /* inject the inverted source block */ + *dst = ~*src; + dst += line_wr; + src += fnt_wr; + } + } + } + else { + if (fg & 0x0001) + { + /* back:0 fore:1 => direct substitution */ + for (i = v_cel_ht; i--;) + { + *dst = *src; + dst += line_wr; + src += fnt_wr; + } + } + else + { + /* back:0 fore:0 => all zeros */ + for (i = v_cel_ht; i--; ) + { + *dst = 0x00; /* inject a block */ + dst += line_wr; + } + } + } + + bg >>= 1; /* next background color bit */ + fg >>= 1; /* next foreground color bit */ + dst_sav += plane_offset; /* top of block in next plane */ + } +} + + + +/* + * move_cursor - move the cursor. + * + * move the cursor and update global parameters + * erase the old cursor (if necessary) and draw new cursor (if necessary) + * + * in: + * d0.w new cell X coordinate + * d1.w new cell Y coordinate + */ + +void move_cursor(int x, int y) +{ + /* update cell position */ + + /* clamp x,y to valid ranges */ + if (x < 0) + x = 0; + else if (x > v_cel_mx) + x = v_cel_mx; + + if (y < 0) + y = 0; + else if (y > v_cel_my) + y = v_cel_my; + + v_cur_cx = x; + v_cur_cy = y; + + /* is cursor visible? */ + if ( !(v_stat_0 & M_CVIS) ) { + /* not visible */ + v_cur_ad = cell_addr(x, y); /* just set new coordinates */ + return; /* and quit */ + } + + /* is cursor flashing? */ + if ( v_stat_0 & M_CFLASH ) { + v_stat_0 &= ~M_CVIS; /* yes, make invisible...semaphore. */ + + /* is cursor presently displayed ? */ + if ( !(v_stat_0 & M_CSTATE )) { + /* not displayed */ + v_cur_ad = cell_addr(x, y); /* just set new coordinates */ + + /* show the cursor when it moves */ + neg_cell(v_cur_ad); /* complement cursor. */ + v_stat_0 |= M_CSTATE; + v_cur_tim = v_period; /* reset the timer. */ + + v_stat_0 |= M_CVIS; /* end of critical section. */ + return; + } + } + + /* move the cursor after all special checks failed */ + neg_cell(v_cur_ad); /* erase present cursor */ + + v_cur_ad = cell_addr(x, y); /* fetch x and y coords. */ + neg_cell(v_cur_ad); /* complement cursor. */ + + /* do not flash the cursor when it moves */ + v_cur_tim = v_period; /* reset the timer. */ + + v_stat_0 |= M_CVIS; /* end of critical section. */ +} + + + +/* + * neg_cell - negates + * + * This routine negates the contents of an arbitrarily-tall byte-wide cell + * composed of an arbitrary number of (Atari-style) bit-planes. + * Cursor display can be accomplished via this procedure. Since a second + * negation restores the original cell condition, there is no need to save + * the contents beneath the cursor block. + * + * in: + * a1.l points to destination (1st plane, top of block) + * + * out: + */ + +static void neg_cell(uint8_t * cell) +{ + int plane, len; + int cell_len = v_cel_ht; + + v_stat_0 |= M_CRIT; /* start of critical section. */ + + for (plane = v_planes; plane--; ) { + uint8_t * addr = cell; /* top of current dest plane */ + + /* reset cell length counter */ + for (len = cell_len; len--; ) { + *addr = ~*addr; + addr += v_lin_wr; + } + cell += plane_offset; /* a1 -> top of block in next plane */ + } + v_stat_0 &= ~M_CRIT; /* end of critical section. */ +} + + + +/* + * invert_cell - negates the cells bits + * + * This routine negates the contents of an arbitrarily-tall byte-wide cell + * composed of an arbitrary number of (Atari-style) bit-planes. + * + * Wrapper for neg_cell(). + * + * in: + * x - cell X coordinate + * y - cell Y coordinate + */ + +void invert_cell(int x, int y) +{ + /* fetch x and y coords and invert cursor. */ + neg_cell(cell_addr(x, y)); +} + + + +/* + * next_cell - Return the next cell address. + * + * sets next cell address given the current position and screen constraints + * + * returns: + * false - no wrap condition exists + * true - CR LF required (position has not been updated) + */ + +static bool next_cell(void) +{ + /* check bounds against screen limits */ + if (v_cur_cx == v_cel_mx) + { + /* increment cell ptr */ + if (!(v_stat_0 & M_CEOL)) + { + /* overwrite in effect */ + return 0; /* no wrap condition exists */ + /* don't change cell parameters */ + } + + /* call carriage return routine */ + /* call line feed routine */ + return 1; /* indicate that CR LF is required */ + } + + v_cur_cx += 1; /* next cell to right */ + + /* if X is even, move to next word in the plane */ + if (v_cur_cx & 1) + { + /* x is odd */ + v_cur_ad += 1; /* a1 -> new cell */ + return 0; /* indicate no wrap needed */ + } + + /* new cell (1st plane), added offset to next word in plane */ + v_cur_ad += (v_planes << 1) - 1; + + return 0; /* indicate no wrap needed */ +} + + +/* + * scroll_up - Scroll upwards + * + * + * Scroll copies a source region as wide as the screen to an overlapping + * destination region on a one cell-height offset basis. Two entry points + * are provided: Partial-lower scroll-up, partial-lower scroll-down. + * Partial-lower screen operations require the cell y # indicating the + * top line where scrolling will take place. + * + * After the copy is performed, any non-overlapping area of the previous + * source region is "erased" by calling blank_out which fills the area + * with the background color. + * + * in: + * top_line - cell y of cell line to be used as top line in scroll + */ + +void scroll_up(int top_line) +{ + uint32_t count; + uint8_t * src, * dst; + + /* screen base addr + cell y nbr * cell wrap */ + dst = v_bas_ad + (uint32_t) top_line * v_cel_wr; + + /* form source address from cell wrap + base address */ + src = dst + v_cel_wr; + + /* form # of bytes to move */ + count = (uint32_t) v_cel_wr * (v_cel_my - top_line); + + /* move BYTEs of memory*/ + memmove(dst, src, count); + + /* exit thru blank out, bottom line cell address y to top/left cell */ + blank_out(0, v_cel_my , v_cel_mx, v_cel_my ); +} + + + +/* + * scroll_down - Scroll (partially) downwards + */ + +void scroll_down(int start_line) +{ + uint32_t count; + uint8_t * src, * dst; + + /* screen base addr + offset of start line */ + src = v_bas_ad + (uint32_t) start_line * v_cel_wr; + + /* form destination from source + cell wrap */ + dst = src + v_cel_wr; + + /* form # of bytes to move */ + count = (uint32_t) v_cel_wr * (v_cel_my - start_line); + + /* move BYTEs of memory*/ + memmove(dst, src, count); + + /* exit thru blank out */ + blank_out(0, start_line , v_cel_mx, start_line); +} + diff --git a/util/libgcc_helper.S b/util/libgcc_helper.S new file mode 100644 index 0000000..3f06506 --- /dev/null +++ b/util/libgcc_helper.S @@ -0,0 +1,70 @@ +// +// needed for ELF compilation of x86emu which uses 64 bit multiplication and division. This +// is implemented in libgcc.a. However, the ELF compiler emits leading underscores and libgcc +// is not compiled like that - we must reimplement the symbols. +// +// FIXME: This is a quirk and should be replaced by BaS' own implementation later +// + .global ___divdi3 + .extern __divdi3 +___divdi3: jmp __divdi3 + + .global ___muldi3 + .extern __muldi3 +___muldi3: jmp __muldi3 + + .global ___moddi3 + .extern __moddi3 +___moddi3: jmp __moddi3 + + .global ___udivdi3 + .extern __udivdi3 +___udivdi3: jmp __udivdi3 + + .global ___umoddi3 + .extern __umoddi3 +___umoddi3: jmp __umoddi3 + + .global ___divdf3 + .extern __divdf3 +___divdf3: jmp __divdf3 + + .global ___muldf3 + .extern __muldf3 +___muldf3: jmp __muldf3 + + .global ___subsf3 + .extern __subsf3 +___subsf3: jmp __subsf3 + + .global ___floatsidf + .extern __floatsidf +___floatsidf: jmp __floatsidf + + .global ___floatsisf + .extern __floatsisf +___floatsisf: jmp __floatsisf + + .global ___extendsfdf2 + .extern __extendsfdf2 +___extendsfdf2: jmp __extendsfdf2 + + .global ___floatunsidf + .extern __floatunsidf +___floatunsidf: jmp __floatunsidf + + .global ___truncdfsf2 + .extern __truncdfsf2 +___truncdfsf2: jmp __truncdfsf2 + + .global ___ltsf2 + .extern __ltsf2 +___ltsf2: jmp __ltsf2 + + .global ___fixdfsi + .extern __fixdfsi +___fixdfsi: jmp __fixdfsi + + .global ___fixsfsi + .extern __fixsfsi +___fixsfsi: jmp __fixsfsi diff --git a/util/setjmp.S b/util/setjmp.S new file mode 100644 index 0000000..cfb9787 --- /dev/null +++ b/util/setjmp.S @@ -0,0 +1,16 @@ + .globl _setjmp + .globl _longjmp + +_setjmp: move.l 4(sp),a0 // address of jmp_buf[] + move.l (sp),(a0) // save return address + movem.l d2-d7/a2-a7,4(a0) // save registers to jmp_buf + clr.l d0 + rts + +_longjmp: move.l 4(sp),a0 // address of jmp_buf[] + move.l 8(sp),d0 // value to return + jne not_0 // value may not be 0 + moveq.l #1,d0 +not_0: movem.l 4(a0),d2-d7/a2-a7 // restore registers + move.l (a0),(sp) // restore saved return address + rts diff --git a/util/wait.c b/util/wait.c new file mode 100644 index 0000000..e655251 --- /dev/null +++ b/util/wait.c @@ -0,0 +1,85 @@ +/* + * wait.c + * + * Created on: 10.12.2012 + * Author: mfro + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Copyright 2010 - 2012 F. Aschwanden + * Copyright 2011 - 2012 V. Riviere + * Copyright 2012 M. Froeschle + * + */ + +#include +#include +#include + +uint32_t get_timer(void) +{ + return MCF_SLT_SCNT(0); +} + +static uint32_t timer_value; + +void start_timeout(void) +{ + timer_value = get_timer(); +} + +bool end_timeout(uint32_t msec) +{ + msec *= SYSCLK; + + return (get_timer() - timer_value) < msec ? false : true; +} + +/* + * wait for the specified number of us on slice timer 0. Replaces the original routines that had + * the number of useconds to wait for hardcoded in their name. + */ +void wait(uint32_t us) +{ + int32_t target = MCF_SLT_SCNT(0) - (us * (SYSCLK / 1000)); + + while (MCF_SLT_SCNT(0) - target > 0); +} +void wait_us() __attribute__ ((weak, alias("wait"))); + +/* + * same as above, but with milliseconds wait time + */ +void wait_ms(uint32_t ms) +{ + wait(ms * 1000); +} +/* + * the same as above, with a checker function which gets called while + * busy waiting and allows for an early return if it returns true + */ +bool waitfor(uint32_t us, checker_func condition) +{ + int32_t target = MCF_SLT_SCNT(0) - (us * (SYSCLK / 1000)); + bool res; + + do + { + if ((res = (*condition)())) + return res; + } while (MCF_SLT_SCNT(0) - target > 0); + return false; +} diff --git a/video/fbmem.c b/video/fbmem.c new file mode 100644 index 0000000..922eb53 --- /dev/null +++ b/video/fbmem.c @@ -0,0 +1,203 @@ +/* + * fbmem.c + * + * Copyright (C) 1994 Martin Schaller + * + * 2001 - Documented with DocBook + * - Brad Douglas + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include "bas_types.h" +#include "bas_printf.h" +#include "bas_string.h" +#include "fb.h" +#include "radeonfb.h" +#include "driver_mem.h" +#include "bas_string.h" + +// #define DEBUG +#include "debug.h" + + +/* + * Frame buffer device initialization and setup routines + */ + + +int fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var) +{ + int32_t xoffset = var->xoffset; + int32_t yoffset = var->yoffset; + int32_t err; + + dbg("\r\n"); + if ((xoffset < 0) || (yoffset < 0) + || ((xoffset + info->var.xres) > info->var.xres_virtual)) + { + dbg("xoffset=%d, yoffset=%d, xres=%d, xres_virtual = %d\r\n", + xoffset, yoffset, info->var.xres, info->var.xres_virtual); + return -1; //-EINVAL; + } + + if ((err = info->fbops->fb_pan_display(var, info))) + { + dbg("fb_pan_display returned %d\r\n", err); + + return err; + } + + info->var.xoffset = var->xoffset; + info->var.yoffset = var->yoffset; + if (var->vmode & FB_VMODE_YWRAP) + info->var.vmode |= FB_VMODE_YWRAP; + else + info->var.vmode &= ~FB_VMODE_YWRAP; + + return 0; +} + +int fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var) +{ + int32_t err; + + dbg("var->activate = 0x%x\r\n", var->activate); + + if (var->activate & FB_ACTIVATE_INV_MODE) + { + dbg("invalid mode\r\n"); + + return !memcmp((char *) &info->var, (char *) var, sizeof(struct fb_var_screeninfo)); + } + + if ((var->activate & FB_ACTIVATE_FORCE) + || memcmp((char *) &info->var, (char *) var, sizeof(struct fb_var_screeninfo))) + { + if ((err = info->fbops->fb_check_var(var, info))) + { + dbg("fb_check_var failed\r\n"); + + return err; + } + + if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) + { + memcpy(&info->var, var, sizeof(struct fb_var_screeninfo)); + dbg("fb_set_par() = %p\r\n", info->fbops->fb_set_par); + info->fbops->fb_set_par(info); + fb_pan_display(info, &info->var); + } + } + + return 0; +} + +int fb_blank(struct fb_info *info, int blank) +{ + dbg("\r\n"); + if (blank > FB_BLANK_POWERDOWN) + blank = FB_BLANK_POWERDOWN; + + return info->fbops->fb_blank(blank, info); +} + +int fb_ioctl(struct fb_info *info, uint32_t cmd, uint32_t arg) +{ + struct fb_var_screeninfo var; + struct fb_fix_screeninfo fix; + void *argp = (void *) arg; + int32_t i; + + dbg("\r\n"); + switch(cmd) + { + case FBIOGET_VSCREENINFO: + memcpy(argp, &info->var, sizeof(var)); + + return 0; + + case FBIOPUT_VSCREENINFO: + memcpy(&var, argp, sizeof(var)); + i = fb_set_var(info, &var); + if (i) + return i; + memcpy(argp, &var, sizeof(var)); + + return 0; + + case FBIOGET_FSCREENINFO: + memcpy(argp, &info->fix, sizeof(fix)); + + return 0; + + case FBIOPAN_DISPLAY: + memcpy(&var, argp, sizeof(var)); + i = fb_pan_display(info, &var); + if (i) + return i; + memcpy(argp, &var, sizeof(var)); + + return 0; + + case FBIOBLANK: + i = fb_blank(info, arg); + return i; + + case FBIO_ALLOC: + return offscreen_alloc(info, arg); + + case FBIO_FREE: + return offscreen_free(info, (void *) arg); + + default: + return info->fbops->fb_ioctl(cmd, arg, info); + } +} + + +/** + * framebuffer_alloc - creates a new frame buffer info structure + * + * @size: size of driver private data, can be zero + * @dev: pointer to the device for this fb, this can be NULL + * + * Creates a new frame buffer info structure. Also reserves @size bytes + * for driver private data (info->par). info->par (if any) will be + * aligned to sizeof(long). + * + * Returns the new structure, or NULL if an error occured. + * + */ +struct fb_info *framebuffer_alloc(uint32_t size) +{ + /* changed for BaS_gcc: + * we do not allocate anything here anymore, info_fb is statically allocated in video.c + * This leads to the (not really existing) limitation that we only support one Radeon + * card in the system + */ + extern struct fb_info *info_fb; + + dbg("\r\n"); + + return info_fb; +} + +/** + * framebuffer_release - marks the structure available for freeing + * + * @info: frame buffer info structure + * + * Drop the reference count of the class_device embedded in the + * framebuffer info structure. + * + */ +void framebuffer_release(struct fb_info *info) +{ + dbg("\r\n"); + + driver_mem_free(info->par); +} + diff --git a/video/fbmodedb.c b/video/fbmodedb.c new file mode 100644 index 0000000..bbd6493 --- /dev/null +++ b/video/fbmodedb.c @@ -0,0 +1,605 @@ +/* + * fb_modedb.c -- Standard video mode database management + * + * Copyright (C) 1999 Geert Uytterhoeven + * + * 2001 - Documented with DocBook + * - Brad Douglas + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#include "fb.h" +#include "bas_types.h" +#include "bas_printf.h" +#include "bas_string.h" + +// #define DEBUG +#include "debug.h" + +#define name_matches(v, s, l) \ + ((v).name && !strncmp((s), (v).name, (l)) && strlen((v).name) == (l)) +#define res_matches(v, x, y) \ + ((v).xres == (x) && (v).yres == (y)) + +/* + * Standard video mode definitions (taken from XFree86) + */ + +#define DEFAULT_MODEDB_INDEX 0 + +const struct fb_videomode modedb[] = +{ + { + /* 640x400 @ 70 Hz, 31.5 kHz hsync */ + 70, 640, 400, 39721, 40, 24, 39, 9, 96, 2, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 640x480 @ 60 Hz, 31.5 kHz hsync */ + 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 800x600 @ 56 Hz, 35.15 kHz hsync */ + 56, 800, 600, 27777, 128, 24, 22, 1, 72, 2, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 1024x768 @ 87 Hz interlaced, 35.5 kHz hsync */ + 87, 1024, 768, 22271, 56, 24, 33, 8, 160, 8, + 0, FB_VMODE_INTERLACED + }, + { + /* 640x400 @ 85 Hz, 37.86 kHz hsync */ + 85, 640, 400, 31746, 96, 32, 41, 1, 64, 3, + FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED + }, + { + /* 640x480 @ 72 Hz, 36.5 kHz hsync */ + 72, 640, 480, 31746, 144, 40, 30, 8, 40, 3, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 640x480 @ 75 Hz, 37.50 kHz hsync */ + 75, 640, 480, 31746, 120, 16, 16, 1, 64, 3, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 800x600 @ 60 Hz, 37.8 kHz hsync */ + 60, 800, 600, 25000, 88, 40, 23, 1, 128, 4, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED + }, + { + /* 640x480 @ 85 Hz, 43.27 kHz hsync */ + 85, 640, 480, 27777, 80, 56, 25, 1, 56, 3, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 1152x864 @ 89 Hz interlaced, 44 kHz hsync */ + 69, 1152, 864, 15384, 96, 16, 110, 1, 216, 10, + 0, FB_VMODE_INTERLACED + }, + { + /* 800x600 @ 72 Hz, 48.0 kHz hsync */ + 72, 800, 600, 20000, 64, 56, 23, 37, 120, 6, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED + }, + { + /* 1024x768 @ 60 Hz, 48.4 kHz hsync */ + 60, 1024, 768, 15384, 168, 8, 29, 3, 144, 6, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 640x480 @ 100 Hz, 53.01 kHz hsync */ + 100, 640, 480, 21834, 96, 32, 36, 8, 96, 6, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 1152x864 @ 60 Hz, 53.5 kHz hsync */ + 60, 1152, 864, 11123, 208, 64, 16, 4, 256, 8, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 800x600 @ 85 Hz, 55.84 kHz hsync */ + 85, 800, 600, 16460, 160, 64, 36, 16, 64, 5, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 1024x768 @ 70 Hz, 56.5 kHz hsync */ + 70, 1024, 768, 13333, 144, 24, 29, 3, 136, 6, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 1280x1024 @ 87 Hz interlaced, 51 kHz hsync */ + 87, 1280, 1024, 12500, 56, 16, 128, 1, 216, 12, + 0, FB_VMODE_INTERLACED + }, + { + /* 800x600 @ 100 Hz, 64.02 kHz hsync */ + 100, 800, 600, 14357, 160, 64, 30, 4, 64, 6, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 1024x768 @ 76 Hz, 62.5 kHz hsync */ + 76, 1024, 768, 11764, 208, 8, 36, 16, 120, 3, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 1152x864 @ 70 Hz, 62.4 kHz hsync */ + 70, 1152, 864, 10869, 106, 56, 20, 1, 160, 10, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 1280x1024 @ 61 Hz, 64.2 kHz hsync */ + 61, 1280, 1024, 9090, 200, 48, 26, 1, 184, 3, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 1400x1050 @ 60Hz, 63.9 kHz hsync */ + 68, 1400, 1050, 9259, 136, 40, 13, 1, 112, 3, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 1400x1050 @ 75,107 Hz, 82,392 kHz +hsync +vsync*/ + 75, 1400, 1050, 9271, 120, 56, 13, 0, 112, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED + }, + { + /* 1400x1050 @ 60 Hz, ? kHz +hsync +vsync*/ + 60, 1400, 1050, 9259, 128, 40, 12, 0, 112, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED + }, + { + /* 1024x768 @ 85 Hz, 70.24 kHz hsync */ + 85, 1024, 768, 10111, 192, 32, 34, 14, 160, 6, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 1152x864 @ 78 Hz, 70.8 kHz hsync */ + 78, 1152, 864, 9090, 228, 88, 32, 0, 84, 12, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 1280x1024 @ 70 Hz, 74.59 kHz hsync */ + 70, 1280, 1024, 7905, 224, 32, 28, 8, 160, 8, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 1600x1200 @ 60Hz, 75.00 kHz hsync */ + 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED + }, + { + /* 1152x864 @ 84 Hz, 76.0 kHz hsync */ + 84, 1152, 864, 7407, 184, 312, 32, 0, 128, 12, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 1280x1024 @ 74 Hz, 78.85 kHz hsync */ + 74, 1280, 1024, 7407, 256, 32, 34, 3, 144, 3, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 1024x768 @ 100Hz, 80.21 kHz hsync */ + 100, 1024, 768, 8658, 192, 32, 21, 3, 192, 10, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 1280x1024 @ 76 Hz, 81.13 kHz hsync */ + 76, 1280, 1024, 7407, 248, 32, 34, 3, 104, 3, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 1600x1200 @ 70 Hz, 87.50 kHz hsync */ + 70, 1600, 1200, 5291, 304, 64, 46, 1, 192, 3, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 1152x864 @ 100 Hz, 89.62 kHz hsync */ + 100, 1152, 864, 7264, 224, 32, 17, 2, 128, 19, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 1280x1024 @ 85 Hz, 91.15 kHz hsync */ + 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED + }, + { + /* 1600x1200 @ 75 Hz, 93.75 kHz hsync */ + 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED + }, + { + /* 1600x1200 @ 85 Hz, 105.77 kHz hsync */ + 85, 1600, 1200, 4545, 272, 16, 37, 4, 192, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED + }, + { + /* 1280x1024 @ 100 Hz, 107.16 kHz hsync */ + 100, 1280, 1024, 5502, 256, 32, 26, 7, 128, 15, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 1800x1440 @ 64Hz, 96.15 kHz hsync */ + 64, 1800, 1440, 4347, 304, 96, 46, 1, 192, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED + }, + { + /* 1800x1440 @ 70Hz, 104.52 kHz hsync */ + 70, 1800, 1440, 4000, 304, 96, 46, 1, 192, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED + }, + { + /* 512x384 @ 78 Hz, 31.50 kHz hsync */ + 78, 512, 384, 49603, 48, 16, 16, 1, 64, 3, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 512x384 @ 85 Hz, 34.38 kHz hsync */ + 85, 512, 384, 45454, 48, 16, 16, 1, 64, 3, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 320x200 @ 70 Hz, 31.5 kHz hsync, 8:5 aspect ratio */ + 70, 320, 200, 79440, 16, 16, 20, 4, 48, 1, + 0, FB_VMODE_DOUBLE + }, + { + /* 320x240 @ 60 Hz, 31.5 kHz hsync, 4:3 aspect ratio */ + 60, 320, 240, 79440, 16, 16, 16, 5, 48, 1, + 0, FB_VMODE_DOUBLE + }, + { + /* 320x240 @ 72 Hz, 36.5 kHz hsync */ + 72, 320, 240, 63492, 16, 16, 16, 4, 48, 2, + 0, FB_VMODE_DOUBLE + }, + { + /* 400x300 @ 56 Hz, 35.2 kHz hsync, 4:3 aspect ratio */ + 56, 400, 300, 55555, 64, 16, 10, 1, 32, 1, + 0, FB_VMODE_DOUBLE + }, + { + /* 400x300 @ 60 Hz, 37.8 kHz hsync */ + 60, 400, 300, 50000, 48, 16, 11, 1, 64, 2, + 0, FB_VMODE_DOUBLE + }, + { + /* 400x300 @ 72 Hz, 48.0 kHz hsync */ + 72, 400, 300, 40000, 32, 24, 11, 19, 64, 3, + 0, FB_VMODE_DOUBLE + }, + { + /* 480x300 @ 56 Hz, 35.2 kHz hsync, 8:5 aspect ratio */ + 56, 480, 300, 46176, 80, 16, 10, 1, 40, 1, + 0, FB_VMODE_DOUBLE + }, + { + /* 480x300 @ 60 Hz, 37.8 kHz hsync */ + 60, 480, 300, 41858, 56, 16, 11, 1, 80, 2, + 0, FB_VMODE_DOUBLE + }, + { + /* 480x300 @ 63 Hz, 39.6 kHz hsync */ + 63, 480, 300, 40000, 56, 16, 11, 1, 80, 2, + 0, FB_VMODE_DOUBLE + }, + { + /* 480x300 @ 72 Hz, 48.0 kHz hsync */ + 72, 480, 300, 33386, 40, 24, 11, 19, 80, 3, + 0, FB_VMODE_DOUBLE + }, + { + /* 1920x1200 @ 60 Hz, 74.5 Khz hsync */ + 60, 1920, 1200, 5177, 128, 336, 1, 38, 208, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED + }, + { + /* 1152x768, 60 Hz, PowerBook G4 Titanium I and II */ + 60, 1152, 768, 14047, 158, 26, 29, 3, 136, 6, + FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED + }, + { + /* 1920x1080, 60 Hz, 1080pf */ + 60, 1920, 1080, 6741, 148, 44, 36, 4, 88, 5, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 1366x768, 60 Hz, 47.403 kHz hsync, WXGA 16:9 aspect ratio */ + 60, 1366, 768, 13806, 120, 10, 14, 3, 32, 5, + 0, FB_VMODE_NONINTERLACED + }, + { + /* 1280x800, 60 Hz, 47.403 kHz hsync, WXGA 16:10 aspect ratio */ + 60, 1280, 800, 12048, 200, 64, 24, 1, 136, 3, + 0, FB_VMODE_NONINTERLACED + }, +}; + +long total_modedb = sizeof(modedb) / sizeof(*modedb); + +const struct fb_videomode vesa_modes[] = +{ + /* 0 640x350-85 VESA */ + { 85, 640, 350, 31746, 96, 32, 60, 32, 64, 3, FB_SYNC_HOR_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA}, + /* 1 640x400-85 VESA */ + { 85, 640, 400, 31746, 96, 32, 41, 01, 64, 3, FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 2 720x400-85 VESA */ + { 85, 721, 400, 28169, 108, 36, 42, 01, 72, 3, FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 3 640x480-60 VESA */ + { 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2, 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 4 640x480-72 VESA */ + { 72, 640, 480, 31746, 128, 24, 29, 9, 40, 2, 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 5 640x480-75 VESA */ + { 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3, 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 6 640x480-85 VESA */ + { 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3, 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 7 800x600-56 VESA */ + { 56, 800, 600, 27777, 128, 24, 22, 01, 72, 2, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 8 800x600-60 VESA */ + { 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 9 800x600-72 VESA */ + { 72, 800, 600, 20000, 64, 56, 23, 37, 120, 6, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 10 800x600-75 VESA */ + { 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 11 800x600-85 VESA */ + { 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 12 1024x768i-43 VESA */ + { 53, 1024, 768, 22271, 56, 8, 41, 0, 176, 8, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_INTERLACED, FB_MODE_IS_VESA }, + /* 13 1024x768-60 VESA */ + { 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6, 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 14 1024x768-70 VESA */ + { 70, 1024, 768, 13333, 144, 24, 29, 3, 136, 6, 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 15 1024x768-75 VESA */ + { 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 16 1024x768-85 VESA */ + { 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 17 1152x864-75 VESA */ + { 75, 1153, 864, 9259, 256, 64, 32, 1, 128, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 18 1280x960-60 VESA */ + { 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 19 1280x960-85 VESA */ + { 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 20 1280x1024-60 VESA */ + { 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 21 1280x1024-75 VESA */ + { 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 22 1280x1024-85 VESA */ + { 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 23 1600x1200-60 VESA */ + { 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 24 1600x1200-65 VESA */ + { 65, 1600, 1200, 5698, 304, 64, 46, 1, 192, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 25 1600x1200-70 VESA */ + { 70, 1600, 1200, 5291, 304, 64, 46, 1, 192, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 26 1600x1200-75 VESA */ + { 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 27 1600x1200-85 VESA */ + { 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 28 1792x1344-60 VESA */ + { 60, 1792, 1344, 4882, 328, 128, 46, 1, 200, 3, FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 29 1792x1344-75 VESA */ + { 75, 1792, 1344, 3831, 352, 96, 69, 1, 216, 3, FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 30 1856x1392-60 VESA */ + { 60, 1856, 1392, 4580, 352, 96, 43, 1, 224, 3, FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 31 1856x1392-75 VESA */ + { 75, 1856, 1392, 3472, 352, 128, 104, 1, 224, 3, FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 32 1920x1440-60 VESA */ + { 60, 1920, 1440, 4273, 344, 128, 56, 1, 200, 3, FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 33 1920x1440-75 VESA */ + { 60, 1920, 1440, 3367, 352, 144, 56, 1, 224, 3, FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, +}; + +/** + * fb_try_mode - test a video mode + * @var: frame buffer user defined part of display + * @info: frame buffer info structure + * @mode: frame buffer video mode structure + * @bpp: color depth in bits per pixel + * + * Tries a video mode to test it's validity for device @info. + * + * Returns 1 on success. + * + */ + +static int32_t fb_try_mode(struct fb_var_screeninfo *var, struct fb_info *info, + const struct fb_videomode *mode, uint32_t bpp) +{ + int32_t err = 0; + + dbg("Trying mode %d x %d - %d @ %d\r\n", mode->xres, mode->yres, bpp, mode->refresh); + var->xres = mode->xres; + var->yres = mode->yres; + var->xres_virtual = mode->xres; + var->yres_virtual = mode->yres; + var->xoffset = 0; + var->yoffset = 0; + var->bits_per_pixel = bpp; + var->activate |= FB_ACTIVATE_TEST; + var->pixclock = mode->pixclock; + var->left_margin = mode->left_margin; + var->right_margin = mode->right_margin; + var->upper_margin = mode->upper_margin; + var->lower_margin = mode->lower_margin; + var->hsync_len = mode->hsync_len; + var->vsync_len = mode->vsync_len; + var->sync = mode->sync; + var->vmode = mode->vmode; + var->refresh = mode->refresh; + err = info->fbops->fb_check_var(var, info); + + var->activate &= ~FB_ACTIVATE_TEST; + + return err; +} + +/** + * fb_find_mode - finds a valid video mode + * @var: frame buffer user defined part of display + * @info: frame buffer info structure + * @resolution: fVDI structure mode_option + * @db: video mode database + * @dbsize: size of @db + * @default_mode: default video mode to fall back to + * @default_bpp: default color depth in bits per pixel + * + * Finds a suitable video mode, starting with the specified mode + * in @resolution with fallback to @default_mode. If + * @default_mode fails, all modes in the video mode database will + * be tried. + * + * Valid mode specifiers for @resolution: + * + * x[-][@] or + * [-][@] + * + * with , , and decimal numbers and + * a string. + * + * NOTE: The passed struct @var is _not_ cleared! This allows you + * to supply values for e.g. the grayscale and accel_flags fields. + * + * Returns zero for failure, 1 if using specified @resolution, + * 2 if using specified @resolution with an ignored refresh rate, + * 3 if default mode is used, 4 if fall back to any valid mode. + * + */ + +int fb_find_mode(struct fb_var_screeninfo *var, + struct fb_info *info, struct mode_option *resolution , + const struct fb_videomode *db, unsigned int dbsize, + const struct fb_videomode *default_mode, + unsigned int default_bpp) +{ + int i; + int abs; + int res_specified = 0; + int bpp_specified = 0; + int refresh_specified = 0; + unsigned int xres = 0; + unsigned int yres = 0; + unsigned int bpp = default_bpp; + unsigned int refresh = 0; + int yres_specified = 0; + unsigned long best; + unsigned long diff; + + dbg("fb_find_mode\r\n"); + + /* + * FIXME: temporarily use unused variables here to make compiler happy + */ + (void) yres_specified; + (void) bpp_specified; + + /* Set up defaults */ + if (!db) + { + dbg("fb_find_mode, use default modedb\r\n"); + if (resolution->used && (resolution->flags & MODE_VESA_FLAG)) + { + db = vesa_modes; + dbsize = sizeof(vesa_modes)/sizeof(*vesa_modes); + } + else + { + db = modedb; + dbsize = sizeof(modedb)/sizeof(*modedb); + } + } + if (!default_mode) + default_mode = &modedb[DEFAULT_MODEDB_INDEX]; + if (!default_bpp) + default_bpp = 8; + + /* Did the user specify a video mode? */ + if (resolution->used) /* fVDI mode */ + { + refresh = resolution->freq; + if (refresh) + refresh_specified = 1; + bpp = resolution->bpp; + if (resolution->flags & MODE_EMUL_MONO_FLAG) + bpp = 8; + if (bpp) + bpp_specified = 1; + yres = resolution->height; + if (yres) + yres_specified = 1; + xres = resolution->width; + if (xres) + res_specified = 1; + } + dbg("Trying specified video mode %d x %d\r\n", xres, yres); + + diff = refresh; + best = -1; + for (i = 0; i < dbsize; i++) + { + if (res_specified && res_matches(db[i], xres, yres)) + { + if (!fb_try_mode(var, info, &db[i], bpp)) + { + if (!refresh_specified || db[i].refresh == refresh) + return 1; + else + { + abs = db[i].refresh - refresh; + if (abs < 0) + abs = -abs; + if (diff > abs) + { + diff = abs; + best = i; + } + } + } + } + } + + if (best != -1) + { + fb_try_mode(var, info, &db[best], bpp); + return 2; + } + diff = xres + yres; + dbg("Trying best-fit modes\r\n"); + best = -1; + for (i = 0; i < dbsize; i++) + { + if (xres <= db[i].xres && yres <= db[i].yres) + { + dbg("Trying %d x %d\r\n", db[i].xres, db[i].yres); + + if (!fb_try_mode(var, info, &db[i], bpp)) + { + if (diff > (db[i].xres - xres) + (db[i].yres - yres)) + { + diff = (db[i].xres - xres) + (db[i].yres - yres); + best = i; + } + } + } + } + if (best != -1) + { + fb_try_mode(var, info, &db[best], bpp); + return 5; + } + dbg("Trying default video mode\r\n"); + if (!fb_try_mode(var, info, default_mode, default_bpp)) + return 3; + dbg("Trying all modes\r\n"); + for (i = 0; i < dbsize; i++) + { + if (!fb_try_mode(var, info, &db[i], default_bpp)) + return 4; + } + dbg("No valid mode found\r\n"); + return 0; +} diff --git a/video/fbmon.c b/video/fbmon.c new file mode 100644 index 0000000..edfc2e7 --- /dev/null +++ b/video/fbmon.c @@ -0,0 +1,1407 @@ +/* + * fbmon.c + * + * Copyright (C) 2002 James Simmons + * + * Credits: + * + * The EDID Parser is a conglomeration from the following sources: + * + * 1. SciTech SNAP Graphics Architecture + * Copyright (C) 1991-2002 SciTech Software, Inc. All rights reserved. + * + * 2. XFree86 4.3.0, interpret_edid.c + * Copyright 1998 by Egbert Eich + * + * 3. John Fremlin and + * Ani Joshi + * + * Generalized Timing Formula is derived from: + * + * GTF Spreadsheet by Andy Morrish (1/5/97) + * available at http://www.vesa.org + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + * + */ + +#include "bas_string.h" +#include "fb.h" +#include "edid.h" + +// #define DEBUG +#include "debug.h" + +/* + * EDID parser + */ + +#define FBMON_FIX_HEADER 1 +#define FBMON_FIX_INPUT 2 + +struct broken_edid +{ + unsigned char manufacturer[4]; + unsigned long model; + unsigned long fix; +}; + +static struct broken_edid brokendb[] = +{ + /* DEC FR-PCXAV-YZ */ + { + .manufacturer = "DEC", + .model = 0x073a, + .fix = FBMON_FIX_HEADER, + }, + /* ViewSonic PF775a */ + { + .manufacturer = "VSC", + .model = 0x5a44, + .fix = FBMON_FIX_INPUT, + }, +}; + +static const unsigned char edid_v1_header[] = +{ + 0x00, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x00 +}; + +static void copy_string(unsigned char *c, unsigned char *s) +{ + int32_t i; + c = c + 5; + for (i = 0; (i < 13 && *c != 0x0A); i++) + *(s++) = *(c++); + *s = 0; + + while (i-- && (*--s == 0x20)) + *s = 0; +} + +static int32_t check_edid(unsigned char *edid) +{ + unsigned char *block = edid + ID_MANUFACTURER_NAME; + unsigned char manufacturer[4]; + unsigned char *b; + unsigned long model; + int32_t i, fix = 0, ret = 0; + + manufacturer[0] = ((block[0] & 0x7c) >> 2) + '@'; + manufacturer[1] = ((block[0] & 0x03) << 3) + ((block[1] & 0xe0) >> 5) + '@'; + manufacturer[2] = (block[1] & 0x1f) + '@'; + manufacturer[3] = 0; + model = block[2] + (block[3] << 8); + + for (i = 0; i < sizeof(brokendb)/sizeof(*brokendb); i++) + { + if (manufacturer[0] == brokendb[i].manufacturer[0] && + manufacturer[1] == brokendb[i].manufacturer[1] && + manufacturer[2] == brokendb[i].manufacturer[2] && + manufacturer[3] == brokendb[i].manufacturer[3] && + brokendb[i].model == model) + { + fix = brokendb[i].fix; + break; + } + } + + switch (fix) + { + case FBMON_FIX_HEADER: + for (i = 0; i < 8; i++) + { + if(edid[i] != edid_v1_header[i]) + ret = fix; + } + break; + + case FBMON_FIX_INPUT: + b = edid + EDID_STRUCT_DISPLAY; + /* Only if display is GTF capable will + the input type be reset to analog */ + if (b[4] & 0x01 && b[0] & 0x80) + ret = fix; + break; + } + + return ret; +} + +static void fix_edid(unsigned char *edid, int32_t fix) +{ + unsigned char *b; + + switch (fix) + { + case FBMON_FIX_HEADER: + memcpy(edid, edid_v1_header, 8); + break; + + case FBMON_FIX_INPUT: + b = edid + EDID_STRUCT_DISPLAY; + b[0] &= ~0x80; + edid[127] += 0x80; + break; + } +} + +static int32_t edid_checksum(unsigned char *edid) +{ + unsigned char i, csum = 0, all_null = 0; + int err = 0; + int fix = check_edid(edid); + + if (fix) + fix_edid(edid, fix); + + for (i = 0; i < EDID_LENGTH; i++) + { + csum += edid[i]; + all_null |= edid[i]; + } + + if ((csum == 0x00) && all_null) + /* checksum passed, everything's good */ + err = 1; + + if (!err) + dbg("edid bad checksum\r\n"); + + return err; +} + +static int32_t edid_check_header(unsigned char *edid) +{ + int i; + int err = 1; + int fix = check_edid(edid); + + if (fix) + fix_edid(edid, fix); + + for (i = 0; i < 8; i++) + { + if (edid[i] != edid_v1_header[i]) + err = 0; + } + + if (!err) + dbg("edid bad header\r\n"); + + return err; +} + +static void parse_vendor_block(unsigned char *block, struct fb_monspecs *specs) +{ + specs->manufacturer[0] = ((block[0] & 0x7c) >> 2) + '@'; + specs->manufacturer[1] = ((block[0] & 0x03) << 3) + ((block[1] & 0xe0) >> 5) + '@'; + specs->manufacturer[2] = (block[1] & 0x1f) + '@'; + specs->manufacturer[3] = 0; + specs->model = block[2] + (block[3] << 8); + specs->serial = block[4] + (block[5] << 8) + (block[6] << 16) + (block[7] << 24); + specs->year = block[9] + 1990; + specs->week = block[8]; + dbg(" Manufacturer: %s\r\n", specs->manufacturer); + dbg(" Model: %s\r\n", specs->model); + dbg(" Serial#: %d\r\n", specs->serial); + dbg(" Year: %d\r\n", specs->year); + dbg(" Week %d\r\n", specs->week); +} + +static void get_dpms_capabilities(unsigned char flags, struct fb_monspecs *specs) +{ + specs->dpms = 0; + + if (flags & DPMS_ACTIVE_OFF) + specs->dpms |= FB_DPMS_ACTIVE_OFF; + + if (flags & DPMS_SUSPEND) + specs->dpms |= FB_DPMS_SUSPEND; + + if (flags & DPMS_STANDBY) + specs->dpms |= FB_DPMS_STANDBY; + + dbg(" DPMS: Active %s\r\n", (flags & DPMS_ACTIVE_OFF) ? "yes" : "no"); + dbg(" Suspend: %s\r\n", (flags & DPMS_SUSPEND) ? "yes" : "no"); + dbg(" Standby %s\r\n", (flags & DPMS_STANDBY) ? "yes\r\n" : "no\r\n"); +} + +static void get_chroma(unsigned char *block, struct fb_monspecs *specs) +{ + int tmp; + + /* Chromaticity data */ + tmp = ((block[5] & (3 << 6)) >> 6) | (block[0x7] << 2); + tmp *= 1000; + tmp += 512; + specs->chroma.redx = tmp/1024; + + dbg(" Chroma\r\n"); + dbg(" RedX: %d\r\n", specs->chroma.redx / 10); + tmp = ((block[5] & (3 << 4)) >> 4) | (block[0x8] << 2); + tmp *= 1000; + tmp += 512; + specs->chroma.redy = tmp/1024; + + dbg(" RedY: %d\r\n", specs->chroma.redy / 10); + tmp = ((block[5] & (3 << 2)) >> 2) | (block[0x9] << 2); + tmp *= 1000; + tmp += 512; + specs->chroma.greenx = tmp/1024; + + dbg(" GreenX: %d\r\n", specs->chroma.greenx / 10); + + tmp = (block[5] & 3) | (block[0xa] << 2); + tmp *= 1000; + tmp += 512; + specs->chroma.greeny = tmp / 1024; + dbg(" GreenY: %d\r\n", specs->chroma.greeny / 10); + tmp = ((block[6] & (3 << 6)) >> 6) | (block[0xb] << 2); + tmp *= 1000; + tmp += 512; + specs->chroma.bluex = tmp/1024; + dbg(" BlueX: %d\r\n", specs->chroma.bluex / 10); + tmp = ((block[6] & (3 << 4)) >> 4) | (block[0xc] << 2); + tmp *= 1000; + tmp += 512; + specs->chroma.bluey = tmp/1024; + + dbg(" BlueY: %d\r\n", specs->chroma.bluey / 10); + tmp = ((block[6] & (3 << 2)) >> 2) | (block[0xd] << 2); + tmp *= 1000; + tmp += 512; + specs->chroma.whitex = tmp/1024; + dbg(" WhiteX: %d\r\n", specs->chroma.whitex / 10); + + tmp = (block[6] & 3) | (block[0xe] << 2); + tmp *= 1000; + tmp += 512; + specs->chroma.whitey = tmp/1024; + dbg(" WhiteY: %d\r\n", specs->chroma.whitey / 10); +} + +static int edid_is_serial_block(unsigned char *block) +{ + if ((block[0] == 0x00) && (block[1] == 0x00) + && (block[2] == 0x00) && (block[3] == 0xff) && (block[4] == 0x00)) + return 1; + else + return 0; +} + +static int edid_is_ascii_block(unsigned char *block) +{ + if ((block[0] == 0x00) && (block[1] == 0x00) + && (block[2] == 0x00) && (block[3] == 0xfe) && (block[4] == 0x00)) + return 1; + else + return 0; +} + +static int edid_is_limits_block(unsigned char *block) +{ + if ((block[0] == 0x00) && (block[1] == 0x00) + && (block[2] == 0x00) && (block[3] == 0xfd) && (block[4] == 0x00)) + return 1; + else + return 0; +} + +static int edid_is_monitor_block(unsigned char *block) +{ + if ((block[0] == 0x00) && (block[1] == 0x00) + && (block[2] == 0x00) && (block[3] == 0xfc) && (block[4] == 0x00)) + return 1; + else + return 0; +} + +static void calc_mode_timings(int32_t xres, int32_t yres, int32_t refresh, struct fb_videomode *mode) +{ + struct fb_var_screeninfo var; + struct fb_info info; + + var.xres = xres; + var.yres = yres; + fb_get_mode(FB_VSYNCTIMINGS | FB_IGNOREMON, refresh, &var, &info); + mode->xres = xres; + mode->yres = yres; + mode->pixclock = var.pixclock; + mode->refresh = refresh; + mode->left_margin = var.left_margin; + mode->right_margin = var.right_margin; + mode->upper_margin = var.upper_margin; + mode->lower_margin = var.lower_margin; + mode->hsync_len = var.hsync_len; + mode->vsync_len = var.vsync_len; + mode->vmode = 0; + mode->sync = 0; +} + +static int get_est_timing(unsigned char *block, struct fb_videomode *mode) +{ + int num = 0; + unsigned char c; + + c = block[0]; + + if (c & 0x80) + { + calc_mode_timings(720, 400, 70, &mode[num]); + mode[num++].flag = FB_MODE_IS_CALCULATED; + dbg(" 720x400@70Hz\r\n"); + } + + if (c & 0x40) + { + calc_mode_timings(720, 400, 88, &mode[num]); + mode[num++].flag = FB_MODE_IS_CALCULATED; + dbg(" 720x400@88Hz\r\n"); + } + + if (c & 0x20) + { + mode[num++] = vesa_modes[3]; + dbg(" 640x480@60Hz\r\n"); + } + + if (c & 0x10) + { + calc_mode_timings(640, 480, 67, &mode[num]); + mode[num++].flag = FB_MODE_IS_CALCULATED; + dbg(" 640x480@67Hz\r\n"); + } + + if (c & 0x08) + { + mode[num++] = vesa_modes[4]; + dbg(" 640x480@72Hz\r\n"); + } + + if (c & 0x04) + { + mode[num++] = vesa_modes[5]; + dbg(" 640x480@75Hz\r\n"); + } + + if (c & 0x02) + { + mode[num++] = vesa_modes[7]; + dbg(" 800x600@56Hz\r\n"); + } + + if (c & 0x01) + { + mode[num++] = vesa_modes[8]; + dbg(" 800x600@60Hz\r\n"); + } + + c = block[1]; + + if (c & 0x80) + { + mode[num++] = vesa_modes[9]; + dbg(" 800x600@72Hz\r\n"); + } + + if (c & 0x40) + { + mode[num++] = vesa_modes[10]; + dbg(" 800x600@75Hz\r\n"); + } + + if (c & 0x20) + { + calc_mode_timings(832, 624, 75, &mode[num]); + mode[num++].flag = FB_MODE_IS_CALCULATED; + dbg(" 832x624@75Hz\r\n"); + } + + if (c & 0x10) + { + mode[num++] = vesa_modes[12]; + dbg(" 1024x768@87Hz Interlaced\r\n"); + } + + if (c & 0x08) + { + mode[num++] = vesa_modes[13]; + dbg(" 1024x768@60Hz\r\n"); + } + + if (c & 0x04) + { + mode[num++] = vesa_modes[14]; + dbg(" 1024x768@70Hz\r\n"); + } + + if (c & 0x02) + { + mode[num++] = vesa_modes[15]; + dbg(" 1024x768@75Hz\r\n"); + } + + if (c & 0x01) + { + mode[num++] = vesa_modes[21]; + dbg(" 1280x1024@75Hz\r\n"); + } + + c = block[2]; + + if (c & 0x80) + { + mode[num++] = vesa_modes[17]; + dbg(" 1152x870@75Hz\r\n"); + } + dbg(" Manufacturer's mask: 0x%02x\r\n", c & 0x7F); + + return num; +} + +static int get_std_timing(unsigned char *block, struct fb_videomode *mode) +{ + int xres; + int yres = 0; + int refresh; + int ratio; + int i; + + xres = (block[0] + 31) * 8; + + if (xres <= 256) + return 0; + + ratio = (block[1] & 0xc0) >> 6; + + switch(ratio) + { + case 0: + yres = xres; + break; + + case 1: + yres = (xres * 3) / 4; + break; + + case 2: + yres = (xres * 4) / 5; + break; + + case 3: + yres = (xres * 9) / 16; + break; + } + refresh = (block[1] & 0x3f) + 60; + dbg("%dx%d@ Hz\r\n",xres, yres, refresh); + + for (i = 0; i < VESA_MODEDB_SIZE; i++) + { + if (vesa_modes[i].xres == xres && vesa_modes[i].yres == yres && + vesa_modes[i].refresh == refresh) + { + *mode = vesa_modes[i]; + mode->flag |= FB_MODE_IS_STANDARD; + return 1; + } + } + calc_mode_timings(xres, yres, refresh, mode); + + return 1; +} + +static int get_dst_timing(unsigned char *block, struct fb_videomode *mode) +{ + int j; + int num = 0; + + for (j = 0; j < 6; j++, block+= STD_TIMING_DESCRIPTION_SIZE) + num += get_std_timing(block, &mode[num]); + + return num; +} + +static void get_detailed_timing(unsigned char *block, struct fb_videomode *mode) +{ + mode->xres = H_ACTIVE; + mode->yres = V_ACTIVE; + mode->pixclock = PIXEL_CLOCK; + mode->pixclock /= 1000; + mode->pixclock = KHZ2PICOS(mode->pixclock); + mode->right_margin = H_SYNC_OFFSET; + mode->left_margin = (H_ACTIVE + H_BLANKING) - (H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH); + mode->upper_margin = V_BLANKING - V_SYNC_OFFSET - V_SYNC_WIDTH; + mode->lower_margin = V_SYNC_OFFSET; + mode->hsync_len = H_SYNC_WIDTH; + mode->vsync_len = V_SYNC_WIDTH; + + if (HSYNC_POSITIVE) + mode->sync |= FB_SYNC_HOR_HIGH_ACT; + + if (VSYNC_POSITIVE) + mode->sync |= FB_SYNC_VERT_HIGH_ACT; + + mode->refresh = PIXEL_CLOCK / ((H_ACTIVE + H_BLANKING) * (V_ACTIVE + V_BLANKING)); + mode->vmode = 0; + mode->flag = FB_MODE_IS_DETAILED; + dbg("%d MHz 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\r\n", + PIXEL_CLOCK / 1000000, + H_ACTIVE, + H_ACTIVE + H_SYNC_OFFSET, + H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH, + H_ACTIVE + H_BLANKING, + V_ACTIVE, + V_ACTIVE + V_SYNC_OFFSET, + V_ACTIVE + V_SYNC_OFFSET + V_SYNC_WIDTH, + V_ACTIVE + V_BLANKING); + dbg("Hsync %s Vsync %s\r\n", + (HSYNC_POSITIVE) ? " +" : " -", + (VSYNC_POSITIVE) ? "+" : "-"); +} + +#define MAX_DB_ALLOC 100 +static struct fb_videomode tab_db[MAX_DB_ALLOC]; +static struct fb_videomode *db_used[MAX_DB_ALLOC]; + +static struct fb_videomode *alloc_db(int num) +{ + int i = 0; + + if (!num) + return NULL; + + while (i < MAX_DB_ALLOC) + { + if ((db_used[i] == NULL) && ((i + num) <= MAX_DB_ALLOC)) + { + int32_t j; /* search contiguous num db free */ + + for (j = 0; j < num; j++) + { + if (db_used[i + j] != NULL) + break; /* already used */ + } + if (j >= num) + { + struct fb_videomode *p = &tab_db[i]; + + for (j = 0; j < num; db_used[i+j] = p, j++); + + return p; + } + } + i++; + } + return NULL; +} + +static void free_db(struct fb_videomode *db) +{ + int32_t i; + + for (i = 0; i < MAX_DB_ALLOC; i++) + { + if (db_used[i] == db) + db_used[i] = NULL; + } +} + +/** + * fb_destroy_modedb - destroys mode database + * @modedb: mode database to destroy + * + * DESCRIPTION: + * Destroy mode database created by fb_create_modedb + */ +void fb_destroy_modedb(struct fb_videomode *modedb) +{ + // Funcs_free(modedb); + free_db(modedb); +} + +/** + * fb_create_modedb - create video mode database + * @edid: EDID data + * @dbsize: database size + * + * RETURNS: struct fb_videomode, @dbsize contains length of database + * + * DESCRIPTION: + * This function builds a mode database using the contents of the EDID + * data + */ +static struct fb_videomode *fb_create_modedb(unsigned char *edid, int *dbsize) +{ + struct fb_videomode *mode; + struct fb_videomode *m; + unsigned char *block; + int num = 0; + int i; + + // mode = Funcs_malloc(50 * sizeof(struct fb_videomode), 3); + mode = alloc_db(50); + + if (mode == NULL) + return NULL; + + memset(mode, 0, 50 * sizeof(struct fb_videomode)); + + if (edid == NULL || !edid_checksum(edid) || !edid_check_header(edid)) + { + fb_destroy_modedb(mode); + + return NULL; + } + *dbsize = 0; + dbg(" Supported VESA Modes\r\n"); + block = edid + ESTABLISHED_TIMING_1; + num += get_est_timing(block, &mode[num]); + dbg(" Standard Timings\r\n"); + block = edid + STD_TIMING_DESCRIPTIONS_START; + for (i = 0; i < STD_TIMING; i++, block += STD_TIMING_DESCRIPTION_SIZE) + num += get_std_timing(block, &mode[num]); + dbg(" Detailed Timings\r\n"); + block = edid + DETAILED_TIMING_DESCRIPTIONS_START; + for (i = 0; i < 4; i++, block+= DETAILED_TIMING_DESCRIPTION_SIZE) + { + int first = 1; + + if (block[0] == 0x00 && block[1] == 0x00) + { + if (block[3] == 0xfa) + num += get_dst_timing(block + 5, &mode[num]); + } + else + { + get_detailed_timing(block, &mode[num]); + if (first) + { + mode[num].flag |= FB_MODE_IS_FIRST; + first = 0; + } + num++; + } + } + + /* Yikes, EDID data is totally useless */ + if (!num) + { + fb_destroy_modedb(mode); + + return NULL; + } + *dbsize = num; + // m = Funcs_malloc(num * sizeof(struct fb_videomode), 3); + m = alloc_db(num); + if (!m) + return mode; + memcpy(m, mode, num * sizeof(struct fb_videomode)); + fb_destroy_modedb(mode); + + return m; +} + +static int fb_get_monitor_limits(unsigned char *edid, struct fb_monspecs *specs) +{ + int i; + int retval = 1; + unsigned char *block; + + block = edid + DETAILED_TIMING_DESCRIPTIONS_START; + dbg(" Monitor Operating Limits: "); + for (i = 0; i < 4; i++, block += DETAILED_TIMING_DESCRIPTION_SIZE) + { + if (edid_is_limits_block(block)) + { + specs->hfmin = H_MIN_RATE * 1000; + specs->hfmax = H_MAX_RATE * 1000; + specs->vfmin = V_MIN_RATE; + specs->vfmax = V_MAX_RATE; + specs->dclkmax = MAX_PIXEL_CLOCK * 1000000; + specs->gtf = (GTF_SUPPORT) ? 1 : 0; + retval = 0; + dbg("From EDID\r\n"); + break; + } + } + + /* estimate monitor limits based on modes supported */ + if (retval) + { + struct fb_videomode *modes; + int num_modes; + int i; + int hz; + int hscan; + int pixclock; + + modes = fb_create_modedb(edid, &num_modes); + if (!modes) + { + dbg("None Available\r\n"); + + return 1; + } + retval = 0; + for (i = 0; i < num_modes; i++) + { + hz = modes[i].refresh; + pixclock = PICOS2KHZ(modes[i].pixclock) * 1000; + hscan = (modes[i].yres * 105 * hz + 5000)/100; + if (specs->dclkmax == 0 || specs->dclkmax < pixclock) + specs->dclkmax = pixclock; + if (specs->dclkmin == 0 || specs->dclkmin > pixclock) + specs->dclkmin = pixclock; + if (specs->hfmax == 0 || specs->hfmax < hscan) + specs->hfmax = hscan; + if (specs->hfmin == 0 || specs->hfmin > hscan) + specs->hfmin = hscan; + if (specs->vfmax == 0 || specs->vfmax < hz) + specs->vfmax = hz; + if (specs->vfmin == 0 || specs->vfmin > hz) + specs->vfmin = hz; + } + dbg("Extrapolated\r\n"); + fb_destroy_modedb(modes); + } + dbg(" H: %d - %d kHz V: %d - %d kHz, DCLK: %d MHz\r\n", + specs->hfmin / 1000, + specs->hfmax / 1000, + specs->vfmin, + specs->vfmax, + specs->dclkmax / 1000000); + + return retval; +} + +static void get_monspecs(unsigned char *edid, struct fb_monspecs *specs) +{ + unsigned char c, *block; + + block = edid + EDID_STRUCT_DISPLAY; + fb_get_monitor_limits(edid, specs); + c = block[0] & 0x80; + specs->input = 0; + + if (c) + { + specs->input |= FB_DISP_DDI; + dbg(" Digital Display Input"); + } + else + { + switch ((block[0] & 0x60) >> 5) + { + case 0: + //dbg(" Analog Display Input: Input Voltage - 0.700V/0.300V"); + specs->input |= FB_DISP_ANA_700_300; + break; + + case 1: + //dbg("0.714V/0.286V"); + specs->input |= FB_DISP_ANA_714_286; + break; + + case 2: + //dbg("1.000V/0.400V"); + specs->input |= FB_DISP_ANA_1000_400; + break; + + case 3: + //dbg("0.700V/0.000V"); + specs->input |= FB_DISP_ANA_700_000; + break; + } + } + + // dbg("Sync: "); + c = block[0] & 0x10; + + if (c) + { + dbg(" Configurable signal level\r\n"); + } + + c = block[0] & 0x0f; + specs->signal = 0; + + if (c & 0x10) + { + //DPRINT("Blank to Blank "); + specs->signal |= FB_SIGNAL_BLANK_BLANK; + } + + if (c & 0x08) + { + //DPRINT("Separate "); + specs->signal |= FB_SIGNAL_SEPARATE; + } + + if (c & 0x04) + { + //DPRINT("Composite "); + specs->signal |= FB_SIGNAL_COMPOSITE; + } + + if (c & 0x02) + { + //DPRINT("Sync on Green "); + specs->signal |= FB_SIGNAL_SYNC_ON_GREEN; + } + + if (c & 0x01) + { + // DPRINT("Serration on "); + specs->signal |= FB_SIGNAL_SERRATION_ON; + } + specs->max_x = block[1]; + specs->max_y = block[2]; + + c = block[3]; + + specs->gamma = c+100; + dbg(" Gamma %d\r\n: ",specs->gamma / 100); + get_dpms_capabilities(block[4], specs); + + switch ((block[4] & 0x18) >> 3) + { + case 0: + dbg(" Monochrome/Grayscale\r\n"); + specs->input |= FB_DISP_MONO; + break; + + case 1: + dbg(" RGB Color Display\r\n"); + specs->input |= FB_DISP_RGB; + break; + + case 2: + dbg(" Non-RGB Multicolor Display\r\n"); + specs->input |= FB_DISP_MULTI; + break; + + default: + dbg(" Unknown\r\n"); + specs->input |= FB_DISP_UNKNOWN; + break; + } + get_chroma(block, specs); + specs->misc = 0; + c = block[4] & 0x7; + if (c & 0x04) + { + dbg(" Default color format is primary\r\n"); + specs->misc |= FB_MISC_PRIM_COLOR; + } + if (c & 0x02) + { + dbg(" First DETAILED Timing is preferred\r\n"); + specs->misc |= FB_MISC_1ST_DETAIL; + } + if (c & 0x01) + { + dbg(" Display is GTF capable\r\n"); + specs->gtf = 1; + } +} + +static int edid_is_timing_block(unsigned char *block) +{ + if ((block[0] != 0x00) || (block[1] != 0x00) + || (block[2] != 0x00) || (block[4] != 0x00)) + return 1; + else + return 0; +} + +int fb_parse_edid(unsigned char *edid, struct fb_var_screeninfo *var) +{ + int32_t i; + unsigned char *block; + + if (edid == NULL || var == NULL) + return 1; + if (!(edid_checksum(edid))) + return 1; + if (!(edid_check_header(edid))) + return 1; + block = edid + DETAILED_TIMING_DESCRIPTIONS_START; + for (i = 0; i < 4; i++, block += DETAILED_TIMING_DESCRIPTION_SIZE) + { + if (edid_is_timing_block(block)) + { + var->xres = var->xres_virtual = H_ACTIVE; + var->yres = var->yres_virtual = V_ACTIVE; + var->height = var->width = -1; + var->right_margin = H_SYNC_OFFSET; + var->left_margin = (H_ACTIVE + H_BLANKING) - (H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH); + var->upper_margin = V_BLANKING - V_SYNC_OFFSET - V_SYNC_WIDTH; + var->lower_margin = V_SYNC_OFFSET; + var->hsync_len = H_SYNC_WIDTH; + var->vsync_len = V_SYNC_WIDTH; + var->pixclock = PIXEL_CLOCK; + var->pixclock /= 1000; + var->pixclock = KHZ2PICOS(var->pixclock); + if (HSYNC_POSITIVE) + var->sync |= FB_SYNC_HOR_HIGH_ACT; + if (VSYNC_POSITIVE) + var->sync |= FB_SYNC_VERT_HIGH_ACT; + return 0; + } + } + dbg("edid no timing block\r\n"); + + return 1; +} + +void fb_edid_to_monspecs(unsigned char *edid, struct fb_monspecs *specs) +{ + unsigned char *block; + int i; + + if (edid == NULL) + return; + + if (!(edid_checksum(edid))) + return; + + if (!(edid_check_header(edid))) + return; + + if (specs->modedb != NULL) + fb_destroy_modedb(specs->modedb); + + memset(specs, 0, sizeof(struct fb_monspecs)); + specs->version = edid[EDID_STRUCT_VERSION]; + specs->revision = edid[EDID_STRUCT_REVISION]; + dbg("========================================\r\n"); + dbg("Display Information (EDID)\r\n"); + dbg("========================================\r\n"); + dbg(" EDID Version %d.%d\r\n", specs->version, specs->revision); + + parse_vendor_block(edid + ID_MANUFACTURER_NAME, specs); + block = edid + DETAILED_TIMING_DESCRIPTIONS_START; + for (i = 0; i < 4; i++, block += DETAILED_TIMING_DESCRIPTION_SIZE) + { + if (edid_is_serial_block(block)) + { + copy_string(block, specs->serial_no); + dbg(" Serial Number: %d\r\n", specs->serial_no); + } + else if (edid_is_ascii_block(block)) + { + copy_string(block, specs->ascii); + //DPRINT(" ASCII Block: "); + //DPRINT((void *)specs->ascii); + //DPRINT("\r\n"); + } + else if (edid_is_monitor_block(block)) + { + copy_string(block, specs->monitor); + //DPRINT(" Monitor Name: "); + //DPRINT((void *)specs->monitor); + //DPRINT("\r\n"); + } + } + //DPRINT(" Display Characteristics:\r\n"); + get_monspecs(edid, specs); + specs->modedb = fb_create_modedb(edid, (int *) &specs->modedb_len); + dbg("========================================\r\n"); +} + +/* + * VESA Generalized Timing Formula (GTF) + */ + +#define FLYBACK 550 +#define V_FRONTPORCH 1 +#define H_OFFSET 40 +#define H_SCALEFACTOR 20 +#define H_BLANKSCALE 128 +#define H_GRADIENT 600 +#define C_VAL 30 +#define M_VAL 300 + +struct __fb_timings +{ + unsigned long dclk; + unsigned long hfreq; + unsigned long vfreq; + unsigned long hactive; + unsigned long vactive; + unsigned long hblank; + unsigned long vblank; + unsigned long htotal; + unsigned long vtotal; +}; + +/** + * fb_get_vblank - get vertical blank time + * @hfreq: horizontal freq + * + * DESCRIPTION: + * vblank = right_margin + vsync_len + left_margin + * + * given: right_margin = 1 (V_FRONTPORCH) + * vsync_len = 3 + * flyback = 550 + * + * flyback * hfreq + * left_margin = --------------- - vsync_len + * 1000000 + */ +static unsigned long fb_get_vblank(unsigned long hfreq) +{ + unsigned long vblank; + + vblank = (hfreq * FLYBACK)/1000; + vblank = (vblank + 500)/1000; + return vblank + V_FRONTPORCH; +} + +/** + * fb_get_hblank_by_freq - get horizontal blank time given hfreq + * @hfreq: horizontal freq + * @xres: horizontal resolution in pixels + * + * DESCRIPTION: + * + * xres * duty_cycle + * hblank = ------------------ + * 100 - duty_cycle + * + * duty cycle = percent of htotal assigned to inactive display + * duty cycle = C - (M/Hfreq) + * + * where: C = ((offset - scale factor) * blank_scale) + * -------------------------------------- + scale factor + * 256 + * M = blank_scale * gradient + * + */ +static unsigned long fb_get_hblank_by_hfreq(unsigned long hfreq, unsigned long xres) +{ + unsigned long c_val, m_val, duty_cycle, hblank; + + c_val = (((H_OFFSET - H_SCALEFACTOR) * H_BLANKSCALE)/256 + H_SCALEFACTOR) * 1000; + m_val = (H_BLANKSCALE * H_GRADIENT)/256; + m_val = (m_val * 1000000)/hfreq; + duty_cycle = c_val - m_val; + hblank = (xres * duty_cycle)/(100000 - duty_cycle); + + return hblank; +} + +/* Quick integer square root using binomial theorem (from Dr. Dobbs journal) */ +static int32_t int32_t_sqrt(int32_t N) +{ + unsigned long l2, u, v, u2, n; + + if (N < 2) + return N; + u = N; + l2 = 0; + /* 1/2 * log_2 N = highest bit in the result */ + while ((u >>= 2)) + l2++; + u = 1L << l2; + v = u; + u2 = u << l2; + + while (l2--) + { + v >>= 1; + n = (u + u + v) << l2; + n += u2; + if (n <= N) + { + u += v; + u2 = n; + } + } + return u; +} + +/** + * fb_get_hblank_by_dclk - get horizontal blank time given pixelclock + * @dclk: pixelclock in Hz + * @xres: horizontal resolution in pixels + * + * DESCRIPTION: + * + * xres * duty_cycle + * hblank = ------------------ + * 100 - duty_cycle + * + * duty cycle = percent of htotal assigned to inactive display + * duty cycle = C - (M * h_period) + * + * where: h_period = SQRT(100 - C + (0.4 * xres * M)/dclk) + C - 100 + * ----------------------------------------------- + * 2 * M + * M = 300; + * C = 30; + + */ +static unsigned long fb_get_hblank_by_dclk(unsigned long dclk, unsigned long xres) +{ + unsigned long duty_cycle, h_period, hblank; + + dclk /= 1000; + h_period = 100 - C_VAL; + h_period *= h_period; + h_period += (M_VAL * xres * 2 * 1000)/(5 * dclk); + h_period *=10000; + h_period = int32_t_sqrt(h_period); + h_period -= (100 - C_VAL) * 100; + h_period *= 1000; + h_period /= 2 * M_VAL; + duty_cycle = C_VAL * 1000 - (M_VAL * h_period)/100; + hblank = (xres * duty_cycle)/(100000 - duty_cycle) + 8; + hblank &= ~15; + + return hblank; +} + +/** + * fb_get_hfreq - estimate hsync + * @vfreq: vertical refresh rate + * @yres: vertical resolution + * + * DESCRIPTION: + * + * (yres + front_port) * vfreq * 1000000 + * hfreq = ------------------------------------- + * (1000000 - (vfreq * FLYBACK) + * + */ + +static unsigned long fb_get_hfreq(unsigned long vfreq, unsigned long yres) +{ + unsigned long divisor, hfreq; + + divisor = (1000000 - (vfreq * FLYBACK))/1000; + hfreq = (yres + V_FRONTPORCH) * vfreq * 1000; + + return hfreq / divisor; +} + +static void fb_timings_vfreq(struct __fb_timings *timings) +{ + timings->hfreq = fb_get_hfreq(timings->vfreq, timings->vactive); + timings->vblank = fb_get_vblank(timings->hfreq); + timings->vtotal = timings->vactive + timings->vblank; + timings->hblank = fb_get_hblank_by_hfreq(timings->hfreq, + timings->hactive); + timings->htotal = timings->hactive + timings->hblank; + timings->dclk = timings->htotal * timings->hfreq; +} + +static void fb_timings_hfreq(struct __fb_timings *timings) +{ + timings->vblank = fb_get_vblank(timings->hfreq); + timings->vtotal = timings->vactive + timings->vblank; + timings->vfreq = timings->hfreq/timings->vtotal; + timings->hblank = fb_get_hblank_by_hfreq(timings->hfreq, timings->hactive); + timings->htotal = timings->hactive + timings->hblank; + timings->dclk = timings->htotal * timings->hfreq; +} + +static void fb_timings_dclk(struct __fb_timings *timings) +{ + timings->hblank = fb_get_hblank_by_dclk(timings->dclk, timings->hactive); + timings->htotal = timings->hactive + timings->hblank; + timings->hfreq = timings->dclk/timings->htotal; + timings->vblank = fb_get_vblank(timings->hfreq); + timings->vtotal = timings->vactive + timings->vblank; + timings->vfreq = timings->hfreq/timings->vtotal; +} + +/* + * fb_get_mode - calculates video mode using VESA GTF + * @flags: if: 0 - maximize vertical refresh rate + * 1 - vrefresh-driven calculation; + * 2 - hscan-driven calculation; + * 3 - pixelclock-driven calculation; + * @val: depending on @flags, ignored, vrefresh, hsync or pixelclock + * @var: pointer to fb_var_screeninfo + * @info: pointer to fb_info + * + * DESCRIPTION: + * Calculates video mode based on monitor specs using VESA GTF. + * The GTF is best for VESA GTF compliant monitors but is + * specifically formulated to work for older monitors as well. + * + * If @flag==0, the function will attempt to maximize the + * refresh rate. Otherwise, it will calculate timings based on + * the flag and accompanying value. + * + * If FB_IGNOREMON bit is set in @flags, monitor specs will be + * ignored and @var will be filled with the calculated timings. + * + * All calculations are based on the VESA GTF Spreadsheet + * available at VESA's public ftp (http://www.vesa.org). + * + * NOTES: + * The timings generated by the GTF will be different from VESA + * DMT. It might be a good idea to keep a table of standard + * VESA modes as well. The GTF may also not work for some displays, + * such as, and especially, analog TV. + * + * REQUIRES: + * A valid info->monspecs, otherwise 'safe numbers' will be used. + */ +int32_t fb_get_mode(int32_t flags, uint32_t val, struct fb_var_screeninfo *var, struct fb_info *info) +{ + struct __fb_timings timings; + unsigned long interlace = 1, dscan = 1; + unsigned long hfmin, hfmax, vfmin, vfmax, dclkmin, dclkmax; + + /* + * If monspecs are invalid, use values that are enough + * for 640x480@60 + */ + if (!info->monspecs.hfmax || !info->monspecs.vfmax + || !info->monspecs.dclkmax || info->monspecs.hfmax < info->monspecs.hfmin + || info->monspecs.vfmax < info->monspecs.vfmin || info->monspecs.dclkmax < info->monspecs.dclkmin) + { + hfmin = 29000; hfmax = 30000; + vfmin = 60; vfmax = 60; + dclkmin = 0; dclkmax = 25000000; + } + else + { + hfmin = info->monspecs.hfmin; + hfmax = info->monspecs.hfmax; + vfmin = info->monspecs.vfmin; + vfmax = info->monspecs.vfmax; + dclkmin = info->monspecs.dclkmin; + dclkmax = info->monspecs.dclkmax; + } + memset(&timings, 0, sizeof(struct __fb_timings)); + timings.hactive = var->xres; + timings.vactive = var->yres; + + if (var->vmode & FB_VMODE_INTERLACED) + { + timings.vactive /= 2; + interlace = 2; + } + + if (var->vmode & FB_VMODE_DOUBLE) + { + timings.vactive *= 2; + dscan = 2; + } + + switch (flags & ~FB_IGNOREMON) + { + case FB_MAXTIMINGS: /* maximize refresh rate */ + timings.hfreq = hfmax; + fb_timings_hfreq(&timings); + if (timings.vfreq > vfmax) + { + timings.vfreq = vfmax; + fb_timings_vfreq(&timings); + } + + if (timings.dclk > dclkmax) + { + timings.dclk = dclkmax; + fb_timings_dclk(&timings); + } + break; + + case FB_VSYNCTIMINGS: /* vrefresh driven */ + timings.vfreq = val; + fb_timings_vfreq(&timings); + break; + + case FB_HSYNCTIMINGS: /* hsync driven */ + timings.hfreq = val; + fb_timings_hfreq(&timings); + break; + + case FB_DCLKTIMINGS: /* pixelclock driven */ + timings.dclk = PICOS2KHZ(val) * 1000; + fb_timings_dclk(&timings); + break; + + default: + return -1; // -EINVAL; + } + if (!(flags & FB_IGNOREMON) + && (timings.vfreq < vfmin || timings.vfreq > vfmax + || timings.hfreq < hfmin || timings.hfreq > hfmax + || timings.dclk < dclkmin || timings.dclk > dclkmax)) + return -1; //-EINVAL; + + var->pixclock = KHZ2PICOS(timings.dclk/1000); + var->hsync_len = (timings.htotal * 8)/100; + var->right_margin = (timings.hblank/2) - var->hsync_len; + var->left_margin = timings.hblank - var->right_margin - var->hsync_len; + var->vsync_len = (3 * interlace)/dscan; + var->lower_margin = (1 * interlace)/dscan; + var->upper_margin = (timings.vblank * interlace)/dscan - (var->vsync_len + var->lower_margin); + + return 0; +} + +/* + * fb_validate_mode - validates var against monitor capabilities + * @var: pointer to fb_var_screeninfo + * @info: pointer to fb_info + * + * DESCRIPTION: + * Validates video mode against monitor capabilities specified in + * info->monspecs. + * + * REQUIRES: + * A valid info->monspecs. + */ +int32_t fb_validate_mode(const struct fb_var_screeninfo *var, struct fb_info *info) +{ + unsigned long hfreq, vfreq, htotal, vtotal, pixclock; + unsigned long hfmin, hfmax, vfmin, vfmax, dclkmin, dclkmax; + /* + * If monspecs are invalid, use values that are enough + * for 640x480@60 + */ + if (!info->monspecs.hfmax || !info->monspecs.vfmax || !info->monspecs.dclkmax + || info->monspecs.hfmax < info->monspecs.hfmin + || info->monspecs.vfmax < info->monspecs.vfmin + || info->monspecs.dclkmax < info->monspecs.dclkmin) + { + hfmin = 29000; hfmax = 30000; + vfmin = 60; vfmax = 60; + dclkmin = 0; dclkmax = 25000000; + } + else + { + hfmin = info->monspecs.hfmin; + hfmax = info->monspecs.hfmax; + vfmin = info->monspecs.vfmin; + vfmax = info->monspecs.vfmax; + dclkmin = info->monspecs.dclkmin; + dclkmax = info->monspecs.dclkmax; + } + if (!var->pixclock) + return -1; // -EINVAL; + + pixclock = PICOS2KHZ(var->pixclock) * 1000; + htotal = var->xres + var->right_margin + var->hsync_len + var->left_margin; + vtotal = var->yres + var->lower_margin + var->vsync_len + var->upper_margin; + if (var->vmode & FB_VMODE_INTERLACED) + vtotal /= 2; + if (var->vmode & FB_VMODE_DOUBLE) + vtotal *= 2; + hfreq = pixclock/htotal; + vfreq = hfreq/vtotal; + return (vfreq < vfmin || vfreq > vfmax || hfreq < hfmin || hfreq > hfmax + || pixclock < dclkmin || pixclock > dclkmax) ? -1 /* -EINVAL */ : 0; +} + diff --git a/video/fnt_st_8x16.c b/video/fnt_st_8x16.c new file mode 100644 index 0000000..1896aed --- /dev/null +++ b/video/fnt_st_8x16.c @@ -0,0 +1,339 @@ +/* + * fnt-8x16.c - 8x16 font for Atari ST encoding + * + * Copyright (C) 2001-2002 The EmuTOS development team + * + * This file is distributed under the GPL, version 2 or at your + * option any later version. See doc/license.txt for details. + */ + +#include "bas_types.h" +#include "font.h" + +static const uint16_t off_table[] = +{ + 0x0000, 0x0008, 0x0010, 0x0018, 0x0020, 0x0028, 0x0030, 0x0038, + 0x0040, 0x0048, 0x0050, 0x0058, 0x0060, 0x0068, 0x0070, 0x0078, + 0x0080, 0x0088, 0x0090, 0x0098, 0x00a0, 0x00a8, 0x00b0, 0x00b8, + 0x00c0, 0x00c8, 0x00d0, 0x00d8, 0x00e0, 0x00e8, 0x00f0, 0x00f8, + 0x0100, 0x0108, 0x0110, 0x0118, 0x0120, 0x0128, 0x0130, 0x0138, + 0x0140, 0x0148, 0x0150, 0x0158, 0x0160, 0x0168, 0x0170, 0x0178, + 0x0180, 0x0188, 0x0190, 0x0198, 0x01a0, 0x01a8, 0x01b0, 0x01b8, + 0x01c0, 0x01c8, 0x01d0, 0x01d8, 0x01e0, 0x01e8, 0x01f0, 0x01f8, + 0x0200, 0x0208, 0x0210, 0x0218, 0x0220, 0x0228, 0x0230, 0x0238, + 0x0240, 0x0248, 0x0250, 0x0258, 0x0260, 0x0268, 0x0270, 0x0278, + 0x0280, 0x0288, 0x0290, 0x0298, 0x02a0, 0x02a8, 0x02b0, 0x02b8, + 0x02c0, 0x02c8, 0x02d0, 0x02d8, 0x02e0, 0x02e8, 0x02f0, 0x02f8, + 0x0300, 0x0308, 0x0310, 0x0318, 0x0320, 0x0328, 0x0330, 0x0338, + 0x0340, 0x0348, 0x0350, 0x0358, 0x0360, 0x0368, 0x0370, 0x0378, + 0x0380, 0x0388, 0x0390, 0x0398, 0x03a0, 0x03a8, 0x03b0, 0x03b8, + 0x03c0, 0x03c8, 0x03d0, 0x03d8, 0x03e0, 0x03e8, 0x03f0, 0x03f8, + 0x0400, 0x0408, 0x0410, 0x0418, 0x0420, 0x0428, 0x0430, 0x0438, + 0x0440, 0x0448, 0x0450, 0x0458, 0x0460, 0x0468, 0x0470, 0x0478, + 0x0480, 0x0488, 0x0490, 0x0498, 0x04a0, 0x04a8, 0x04b0, 0x04b8, + 0x04c0, 0x04c8, 0x04d0, 0x04d8, 0x04e0, 0x04e8, 0x04f0, 0x04f8, + 0x0500, 0x0508, 0x0510, 0x0518, 0x0520, 0x0528, 0x0530, 0x0538, + 0x0540, 0x0548, 0x0550, 0x0558, 0x0560, 0x0568, 0x0570, 0x0578, + 0x0580, 0x0588, 0x0590, 0x0598, 0x05a0, 0x05a8, 0x05b0, 0x05b8, + 0x05c0, 0x05c8, 0x05d0, 0x05d8, 0x05e0, 0x05e8, 0x05f0, 0x05f8, + 0x0600, 0x0608, 0x0610, 0x0618, 0x0620, 0x0628, 0x0630, 0x0638, + 0x0640, 0x0648, 0x0650, 0x0658, 0x0660, 0x0668, 0x0670, 0x0678, + 0x0680, 0x0688, 0x0690, 0x0698, 0x06a0, 0x06a8, 0x06b0, 0x06b8, + 0x06c0, 0x06c8, 0x06d0, 0x06d8, 0x06e0, 0x06e8, 0x06f0, 0x06f8, + 0x0700, 0x0708, 0x0710, 0x0718, 0x0720, 0x0728, 0x0730, 0x0738, + 0x0740, 0x0748, 0x0750, 0x0758, 0x0760, 0x0768, 0x0770, 0x0778, + 0x0780, 0x0788, 0x0790, 0x0798, 0x07a0, 0x07a8, 0x07b0, 0x07b8, + 0x07c0, 0x07c8, 0x07d0, 0x07d8, 0x07e0, 0x07e8, 0x07f0, 0x07f8, + 0x0800, +}; + +static const uint16_t dat_table[] = +{ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1104, + 0x0000, 0x0000, 0x1800, 0x3800, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x4000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x003c, + 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x6032, 0x3200, 0x0000, 0x0000, 0x00f1, + 0x00f6, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x05a0, + 0x7c00, 0x7c7c, 0x007c, 0x7c7c, 0x7c7c, 0x0000, 0x0000, 0x0b28, + 0x0000, 0x0000, 0x1800, 0x7c00, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1000, + 0x6000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x000e, 0x18e0, 0x0000, + 0x0000, 0x0618, 0x0060, 0x1c00, 0x1800, 0x6000, 0x1860, 0x6666, + 0x0c00, 0x3e18, 0x0060, 0x1860, 0x0066, 0x6600, 0x0e00, 0x0000, + 0x0606, 0x0606, 0x3232, 0x0000, 0x0000, 0x0060, 0x6000, 0x0000, + 0x3232, 0x0100, 0x0000, 0x307a, 0x7a66, 0x0610, 0x0000, 0x005b, + 0x66f6, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x7c00, 0x001e, 0x0e00, 0x0000, + 0x0000, 0x0000, 0x0018, 0x0000, 0x3838, 0x0000, 0x0000, 0x00fe, + 0x0000, 0x0030, 0x0c7c, 0xfeee, 0x0100, 0x0008, 0x7838, 0x05a0, + 0xba02, 0x3a3a, 0x82b8, 0xb8ba, 0xbaba, 0x0078, 0x0000, 0x0dd8, + 0x0018, 0x6666, 0x3e66, 0x6c18, 0x0660, 0x6600, 0x0000, 0x0006, + 0x3c18, 0x3c7e, 0x0c7e, 0x1c7e, 0x3c3c, 0x0000, 0x0000, 0x003c, + 0x3818, 0x7c3c, 0x787e, 0x7e3e, 0x667e, 0x06cc, 0x60c6, 0x663c, + 0x7c3c, 0xf83e, 0x7e66, 0x66c6, 0x6666, 0x7e1e, 0x6078, 0x1000, + 0x7000, 0x6000, 0x0600, 0x0e00, 0x6018, 0x0cc0, 0x3800, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0018, 0x1830, 0x0000, + 0x3c66, 0x0c3c, 0x6630, 0x3600, 0x3c66, 0x3066, 0x3c30, 0x663c, + 0x1800, 0x7e3c, 0x6630, 0x3c30, 0x6666, 0x6618, 0x1e66, 0x180e, + 0x0c0c, 0x0c0c, 0x7a7a, 0x0000, 0x1800, 0x0020, 0x2000, 0x0000, + 0x7a7a, 0x3d00, 0x007e, 0x184c, 0x4c66, 0x0c7c, 0x7a7c, 0x7c5f, + 0x6666, 0x667c, 0x1e7e, 0x7e38, 0x1e7e, 0x6e3c, 0x3c7e, 0x6c1c, + 0xfe36, 0x7e6e, 0x3e7c, 0xd67e, 0x387e, 0x7e7e, 0x6e1c, 0x0000, + 0x0018, 0xfe00, 0xfe00, 0x0000, 0x103c, 0x383e, 0x1e10, 0x3e7c, + 0x0000, 0x6006, 0x0e18, 0x0000, 0x6c7c, 0x0000, 0x3030, 0x78fe, + 0x0018, 0x3c38, 0x1c38, 0xfec6, 0x013c, 0x000e, 0x4040, 0x05a0, + 0xc606, 0x0606, 0xc6c0, 0xc0c6, 0xc6c6, 0x0040, 0x0000, 0x0628, + 0x0018, 0x6666, 0x7e66, 0x6c18, 0x0c30, 0x6618, 0x0000, 0x0006, + 0x7e18, 0x7e7e, 0x0c7e, 0x3c7e, 0x7e7e, 0x0000, 0x0e00, 0xe07e, + 0x7c3c, 0x7e7e, 0x7c7e, 0x7e7e, 0x667e, 0x06cc, 0x60c6, 0x667e, + 0x7e7e, 0xfc7e, 0x7e66, 0x66c6, 0x6666, 0x7e1e, 0x6078, 0x3800, + 0x3800, 0x6000, 0x0600, 0x1e00, 0x6018, 0x0cc0, 0x3800, 0x0000, + 0x0000, 0x0000, 0x1800, 0x0000, 0x0000, 0x0018, 0x1830, 0x0000, + 0x7e66, 0x1866, 0x6618, 0x1c00, 0x6666, 0x1866, 0x6618, 0x1818, + 0x7e00, 0xf866, 0x6618, 0x6618, 0x6600, 0x0018, 0x3866, 0x3c1e, + 0x1818, 0x1818, 0x4c4c, 0x0000, 0x1800, 0x0020, 0x2018, 0x0000, + 0x4c4c, 0x7e00, 0x00fe, 0x0000, 0x0000, 0x1810, 0xcac6, 0xc655, + 0x0066, 0x767c, 0x1e7e, 0x7e38, 0x1e7e, 0x6e3c, 0x3e7e, 0x6e1c, + 0xfe36, 0x7e6e, 0x3e7e, 0xd67e, 0x387e, 0x3e7e, 0x6e36, 0x0000, + 0x003c, 0x7e00, 0xfe00, 0x0002, 0x107e, 0x6c20, 0x1010, 0x7efe, + 0x0018, 0x700e, 0x1918, 0x1802, 0x447c, 0x0000, 0x7848, 0x1800, + 0x003c, 0x242c, 0x34ba, 0xfed6, 0x0366, 0x180f, 0x7040, 0x05a0, + 0xc606, 0x0606, 0xc6c0, 0xc0c6, 0xc6c6, 0x0070, 0x0000, 0x07d0, + 0x0018, 0x66ff, 0x606c, 0x3818, 0x1c38, 0x3c18, 0x0000, 0x0006, + 0x6638, 0x660c, 0x1c60, 0x7006, 0x6666, 0x1818, 0x1c7e, 0x7066, + 0xe67e, 0x6666, 0x6e60, 0x6060, 0x6618, 0x06d8, 0x60ee, 0x6666, + 0x6666, 0xcc60, 0x1866, 0x66c6, 0x6666, 0x0c18, 0x6018, 0x3800, + 0x1c00, 0x6000, 0x0600, 0x1800, 0x6000, 0x00c0, 0x1800, 0x0000, + 0x0000, 0x0000, 0x1800, 0x0000, 0x0000, 0x0018, 0x1830, 0x0000, + 0x6600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3c3c, + 0x7e00, 0xd800, 0x0000, 0x0000, 0x003c, 0x663c, 0x3066, 0x6618, + 0x0000, 0x0000, 0x0000, 0x3c3c, 0x0000, 0x0023, 0x2318, 0x0000, + 0x0000, 0x6601, 0x00d8, 0x3c3c, 0x3c00, 0x0010, 0xca82, 0x8251, + 0xe666, 0x760c, 0x060c, 0x0618, 0x0466, 0x660c, 0x0606, 0x3e0c, + 0xfe36, 0x6666, 0x3e06, 0xd666, 0x1806, 0x3666, 0x6632, 0x0066, + 0x6266, 0x6202, 0x601e, 0x007e, 0x7c66, 0xc630, 0x7c7c, 0xe0c6, + 0x7e18, 0x381c, 0x1b18, 0x183e, 0x6c7c, 0x0000, 0x4818, 0x3000, + 0x0066, 0x24e6, 0x6792, 0xfc92, 0x03c3, 0x3c09, 0x4040, 0x0db0, + 0xc606, 0x0606, 0xc6c0, 0xc0c6, 0xc6c6, 0x7c40, 0x0000, 0x2e10, + 0x0018, 0x66ff, 0x600c, 0x3818, 0x1818, 0x3c18, 0x0000, 0x000c, + 0x6638, 0x660c, 0x1c60, 0x6006, 0x6666, 0x1818, 0x387e, 0x3866, + 0xc266, 0x6666, 0x6660, 0x6060, 0x6618, 0x06d8, 0x60ee, 0x7666, + 0x6666, 0xcc60, 0x1866, 0x66c6, 0x3c66, 0x0c18, 0x3018, 0x6c00, + 0x0c3c, 0x7c3c, 0x3e3c, 0x183e, 0x7c38, 0x0ccc, 0x186c, 0x3c3c, + 0x7c3e, 0x7c3e, 0x7e66, 0x66c6, 0x6666, 0x7e18, 0x1830, 0x6218, + 0x6666, 0x3c3c, 0x3c3c, 0x3c3c, 0x3c3c, 0x3c38, 0x3838, 0x7e7e, + 0x6076, 0xd83c, 0x3c3c, 0x6666, 0x667e, 0x667e, 0x3066, 0x6618, + 0x3c38, 0x3c66, 0x3c66, 0x3e7e, 0x1800, 0x0026, 0x2600, 0x0000, + 0x3c3c, 0x663d, 0x7ed8, 0x7e7e, 0x7e00, 0x0010, 0xcaba, 0xba00, + 0x6666, 0x3e0c, 0x060c, 0x6618, 0x0c66, 0x660c, 0x0606, 0x360c, + 0xc636, 0x6636, 0x0606, 0xd666, 0x1806, 0x3666, 0x7618, 0x10f7, + 0xf666, 0x607e, 0x3038, 0x66fc, 0xc642, 0xc618, 0xd6d6, 0xc0c6, + 0x7e18, 0x1c38, 0x1b18, 0x007c, 0x3838, 0x001f, 0x4830, 0x1800, + 0x00c3, 0x2483, 0xc1d6, 0xfcba, 0x0691, 0x3c08, 0x4038, 0x0db0, + 0x8202, 0x3a3a, 0xbab8, 0xb882, 0xbaba, 0x7e78, 0x0000, 0x39e0, + 0x0018, 0x6666, 0x7c18, 0x7018, 0x1818, 0xff7e, 0x007e, 0x000c, + 0x6618, 0x0c18, 0x3c7c, 0x600c, 0x3c7e, 0x1818, 0x7000, 0x1c0c, + 0xda66, 0x7e60, 0x667c, 0x7c6e, 0x7e18, 0x06f0, 0x60fe, 0x7666, + 0x6666, 0xcc70, 0x1866, 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0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x1800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +}; + +static struct font_head fnt_st_8x16 = { + 1, /* WORD font_id */ + 10, /* WORD point */ + "8x16 system font", /* BYTE name[32] */ + 0, /* WORD first_ade */ + 255, /* WORD last_ade */ + 13, /* UWORD top */ + 11, /* UWORD ascent */ + 8, /* UWORD half */ + 2, /* UWORD descent */ + 2, /* UWORD bottom */ + 7, /* UWORD max_char_width */ + 8, /* UWORD max_cell_width */ + 1, /* UWORD left_offset */ + 7, /* UWORD right_offset */ + 1, /* UWORD thicken */ + 1, /* UWORD ul_size */ + 0x5555, /* UWORD lighten */ + 0x5555, /* UWORD skew */ + F_STDFORM | F_MONOSPACE | F_DEFAULT, /* UWORD flags */ + 0, /* UBYTE *hor_table */ + off_table, /* UWORD *off_table */ + dat_table, /* UWORD *dat_table */ + 256, /* UWORD form_width */ + 16, /* UWORD form_height */ + 0, /* struct font * next_font */ + 0 /* UWORD next_seg */ +}; + +struct font_head *fnt = &fnt_st_8x16; diff --git a/video/offscreen.c b/video/offscreen.c new file mode 100644 index 0000000..7a86a7a --- /dev/null +++ b/video/offscreen.c @@ -0,0 +1,289 @@ +/* + * offscreen.c + * + * based from Emutos / BDOS + * + * Copyright (c) 2001 Lineo, Inc. + * + * Authors: Karl T. Braun, Martin Doering, Laurent Vogel + * + * This file is distributed under the GPL, version 2 or at your + * option any later version. + */ + +#include "bas_types.h" +#include "bas_string.h" +#include "fb.h" + +// #define DEBUG +#include "debug.h" + +/* MD - Memory Descriptor */ + +#define MD struct _md_ + +MD +{ + MD *m_link; + long m_start; + long m_length; + void *m_own; +}; + +/* MPB - Memory Partition Block */ + +#define MPB struct _mpb + +MPB +{ + MD *mp_mfl; + MD *mp_mal; + MD *mp_rover; +}; + +#define MAXMD 256 + +static MD tab_md[MAXMD]; +static MPB pmd; +static long wrap; + +static void *xmgetblk(void) +{ + int i; + for (i = 0; i < MAXMD; i++) + { + if(tab_md[i].m_own == NULL) + { + tab_md[i].m_own = (void*)1L; + return(&tab_md[i]); + } + } + return(NULL); +} + +static void xmfreblk(void *m) +{ + int i = (int)(((long)m - (long)tab_md) / sizeof(MD)); + if((i > 0) && (i < MAXMD)) + tab_md[i].m_own = NULL; +} + +static MD *ffit(long amount, MPB *mp) +{ + MD *p; + MD *q; + MD *p1; /* free list is composed of MD's */ + int maxflg; + long maxval; + if(amount != -1) + { +#if 1 + amount += (wrap - 1); + amount /= wrap; + amount *= wrap; /* screen line alignment */ +#else + amount += 15; /* 16 bytes alignment */ + amount &= 0xFFFFFFF0; +#endif + } + if ((q = mp->mp_rover) == 0) /* get rotating pointer */ + return(0) ; + maxval = 0; + maxflg = ((amount == -1) ? true : false) ; + p = q->m_link; /* start with next MD */ + do /* search the list for an MD with enough space */ + { + if (p == NULL) + { + /* at end of list, wrap back to start */ + q = (MD *) &mp->mp_mfl; /* q => mfl field */ + p = q->m_link; /* p => 1st MD */ + } + if ((!maxflg) && (p->m_length >= amount)) + { + /* big enough */ + if (p->m_length == amount) + q->m_link = p->m_link; /* take the whole thing */ + else + { + /* + * break it up - 1st allocate a new + * MD to describe the remainder + */ + p1 = xmgetblk(); + if (p1 == NULL) + return NULL; + + /* + * init new MD + */ + p1->m_length = p->m_length - amount; + p1->m_start = p->m_start + amount; + p1->m_link = p->m_link; + p->m_length = amount; /* adjust allocated block */ + q->m_link = p1; + } + + /* + * link allocated block into allocated list, + * mark owner of block, & adjust rover + */ + p->m_link = mp->mp_mal; + mp->mp_mal = p; + mp->mp_rover = (q == (MD *) &mp->mp_mfl ? q->m_link : q); + return p; /* got some */ + } + else if (p->m_length > maxval) + maxval = p->m_length; + p = (q = p)->m_link; + } + + while (q != mp->mp_rover); + + /* + * return either the max, or 0 (error) + */ + if (maxflg) + { + maxval -= 15; /* 16 bytes alignment */ + if (maxval < 0) + maxval = 0; + else + maxval &= 0xFFFFFFF0; + } + return maxflg ? (MD *) maxval : 0; +} + +static void freeit(MD *m, MPB *mp) +{ + MD *p; + MD *q = NULL; + + for (p = mp->mp_mfl; p; p = (q = p) -> m_link) + { + if (m->m_start <= p->m_start) + break; + } + m->m_link = p; + if (q) + q->m_link = m; + else + mp->mp_mfl = m; + if (!mp->mp_rover) + mp->mp_rover = m; + if (p) + { + if (m->m_start + m->m_length == p->m_start) + { + /* + * join to higher neighbor + */ + m->m_length += p->m_length; + m->m_link = p->m_link; + if (p == mp->mp_rover) + mp->mp_rover = m; + xmfreblk(p); + } + } + if (q) + { + if (q->m_start + q->m_length == m->m_start) + { + /* join to lower neighbor */ + q->m_length += m->m_length; + q->m_link = m->m_link; + if (m == mp->mp_rover) + mp->mp_rover = q; + xmfreblk(m); + } + } +} + +long offscreen_free(struct fb_info *info, void *addr) +{ + MD *p; + MD **q; + MPB *mpb; + + dbg("%p\r\n", addr); + + //*vblsem = 0; + mpb = &pmd; + for (p = *(q = &mpb->mp_mal); p; p = *(q = &p->m_link)) + { + if (addr == (void *) p->m_start) + break; + } + if(!p) + { + // *vblsem = 1; + return -1; //(EFAULT); + } + *q = p->m_link; + freeit(p,mpb); + //*vblsem = 1; + return 0; +} + +long offscreen_alloc(struct fb_info *info, long amount) +{ + long ret; + MD *m; + + + // *vblsem = 0; + if (amount == -1L) + { + ret = (long) ffit(-1L, &pmd); + // *vblsem = 1; + return ret; + } + if (amount <= 0 ) + { + // *vblsem = 1; + return(0); + } + if ((amount & 1)) + amount++; + m = ffit(amount, &pmd); + if (m == NULL) + { + return(0); + } + ret = (long)m->m_start; + // *vblsem = 1; + return(ret); +} + +long offscren_reserved(struct fb_info *info) +{ + return (long) info->ram_base + (long) info->ram_size; +} + +void offscreen_init(struct fb_info *info) +{ + long size_screen; + long max_offscreen_size; + + wrap = (long) info->var.xres_virtual * (long) (info->var.bits_per_pixel / 8); + size_screen = (long) info->var.yres_virtual * wrap; + if (!size_screen) + size_screen = (long) info->screen_size; + + pmd.mp_mfl = pmd.mp_rover = &tab_md[0]; + tab_md[0].m_link = (MD *) NULL; + tab_md[0].m_start = (long)((unsigned long) info->ram_base + (unsigned long) size_screen); + tab_md[0].m_length = (long) info->ram_size - size_screen; + tab_md[0].m_own = (void *)1L; + + max_offscreen_size = ((long) info->var.xres_virtual * 8192L * (long)(info->var.bits_per_pixel / 8)) - size_screen; + if (max_offscreen_size < 0) + max_offscreen_size = 0; + if (tab_md[0].m_length > max_offscreen_size) + tab_md[0].m_length = max_offscreen_size; + + dbg("offscreen_init start %p, length %ld, ram size %ld\r\n", + tab_md[0].m_start, tab_md[0].m_length, (long) info->ram_size); + pmd.mp_mal = (MD *) NULL; +} + diff --git a/video/vdi_fill.c b/video/vdi_fill.c new file mode 100644 index 0000000..6b789a9 --- /dev/null +++ b/video/vdi_fill.c @@ -0,0 +1,1112 @@ +/* + * + * + * Copyright 1982 by Digital Research Inc. All rights reserved. + * Copyright 1999 by Caldera, Inc. and Authors: + * Copyright 2002-2013 The EmuTOS development team + * + * This file is distributed under the GPL, version 2 or at your + * option any later version. See doc/license.txt for details. + */ + + + +#include "config.h" +#include "portab.h" +#include "vdi_defs.h" +#include "tosvars.h" +#include "lineavars.h" + +#define EMPTY 0xffff +#define DOWN_FLAG 0x8000 +#define QSIZE 200 +#define QMAX QSIZE-1 + + + +#define ABS(v) (v & 0x7FFF) + + + +/* prototypes */ +static void crunch_queue(void); +static BOOL clipbox(Vwk * vwk, Rect * rect); + + + +/* Global variables */ +static UWORD search_color; /* the color of the border */ + + +/* some kind of stack for the segments to fill */ +static WORD queue[QSIZE]; /* storage for the seed points */ +static WORD qbottom; /* the bottom of the queue (zero) */ +static WORD qtop; /* points top seed +3 */ +static WORD qptr; /* points to the active point */ +static WORD qtmp; +static WORD qhole; /* an empty space in the queue */ + + +/* the storage for the used defined fill pattern */ +const UWORD ROM_UD_PATRN[16] = { + 0x07E0, 0x0FF0, 0x1FD8, 0x1808, 0x1808, 0x1008, 0x1E78, 0x1348, + 0x1108, 0x0810, 0x0B70, 0x0650, 0x07A0, 0x1E20, 0x1BC0, 0x1800 +}; + +static const UWORD OEMMSKPAT = 7; +static const UWORD OEMPAT[128] = { + /* Brick */ + 0xFFFF, 0x8080, 0x8080, 0x8080, 0xFFFF, 0x0808, 0x0808, 0x0808, + /* Diagonal Bricks */ + 0x2020, 0x4040, 0x8080, 0x4141, 0x2222, 0x1414, 0x0808, 0x1010, + /* Grass */ + 0x0000, 0x0000, 0x1010, 0x2828, 0x0000, 0x0000, 0x0101, 0x8282, + /* Trees */ + 0x0202, 0x0202, 0xAAAA, 0x5050, 0x2020, 0x2020, 0xAAAA, 0x0505, + /* Dashed x's */ + 0x4040, 0x8080, 0x0000, 0x0808, 0x0404, 0x0202, 0x0000, 0x2020, + /* Cobble Stones */ + 0x6606, 0xC6C6, 0xD8D8, 0x1818, 0x8181, 0x8DB1, 0x0C33, 0x6000, + /* Sand */ + 0x0000, 0x0000, 0x0400, 0x0000, 0x0010, 0x0000, 0x8000, 0x0000, + /* Rough Weave */ + 0xF8F8, 0x6C6C, 0xC6C6, 0x8F8F, 0x1F1F, 0x3636, 0x6363, 0xF1F1, + /* Quilt */ + 0xAAAA, 0x0000, 0x8888, 0x1414, 0x2222, 0x4141, 0x8888, 0x0000, + /* Paterned Cross */ + 0x0808, 0x0000, 0xAAAA, 0x0000, 0x0808, 0x0000, 0x8888, 0x0000, + /* Balls */ + 0x7777, 0x9898, 0xF8F8, 0xF8F8, 0x7777, 0x8989, 0x8F8F, 0x8F8F, + /* Verticle Scales */ + 0x8080, 0x8080, 0x4141, 0x3E3E, 0x0808, 0x0808, 0x1414, 0xE3E3, + /* Diagonal scales */ + 0x8181, 0x4242, 0x2424, 0x1818, 0x0606, 0x0101, 0x8080, 0x8080, + /* Checker Board */ + 0xF0F0, 0xF0F0, 0xF0F0, 0xF0F0, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, + /* Filled Diamond */ + 0x0808, 0x1C1C, 0x3E3E, 0x7F7F, 0xFFFF, 0x7F7F, 0x3E3E, 0x1C1C, + /* Herringbone */ + 0x1111, 0x2222, 0x4444, 0xFFFF, 0x8888, 0x4444, 0x2222, 0xFFFF +}; + +static const UWORD DITHRMSK = 3; /* mask off all but four scans */ +static const UWORD DITHER[32] = { + 0x0000, 0x4444, 0x0000, 0x1111, /* intensity level 2 */ + 0x0000, 0x5555, 0x0000, 0x5555, /* intensity level 4 */ + 0x8888, 0x5555, 0x2222, 0x5555, /* intensity level 6 */ + 0xAAAA, 0x5555, 0xAAAA, 0x5555, /* intensity level 8 */ + 0xAAAA, 0xDDDD, 0xAAAA, 0x7777, /* intensity level 10 */ + 0xAAAA, 0xFFFF, 0xAAAA, 0xFFFF, /* intensity level 12 */ + 0xEEEE, 0xFFFF, 0xBBBB, 0xFFFF, /* intensity level 14 */ + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF /* intensity level 16 */ +}; + +static const UWORD HAT_0_MSK = 7; +static const UWORD HATCH0[48] = { + /* narrow spaced + 45 */ + 0x0101, 0x0202, 0x0404, 0x0808, 0x1010, 0x2020, 0x4040, 0x8080, + /* medium spaced thick 45 deg */ + 0x6060, 0xC0C0, 0x8181, 0x0303, 0x0606, 0x0C0C, 0x1818, 0x3030, + /* medium +-45 deg */ + 0x4242, 0x8181, 0x8181, 0x4242, 0x2424, 0x1818, 0x1818, 0x2424, + /* medium spaced vertical */ + 0x8080, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080, + /* medium spaced horizontal */ + 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* medium spaced cross */ + 0xFFFF, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080 +}; + +static const UWORD HAT_1_MSK = 0xF; +static const UWORD HATCH1[96] = { + /* wide +45 deg */ + 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, + 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000, + /* widely spaced thick 45 deg */ + 0x8003, 0x0007, 0x000E, 0x001C, 0x0038, 0x0070, 0x00E0, 0x01C0, + 0x0380, 0x0700, 0x0E00, 0x1C00, 0x3800, 0x7000, 0x0E000, 0x0C001, + /* widely +- 45 deg */ + 0x8001, 0x4002, 0x2004, 0x1008, 0x0810, 0x0420, 0x0240, 0x0180, + 0x0180, 0x0240, 0x0420, 0x0810, 0x1008, 0x2004, 0x4002, 0x8001, + /* widely spaced vertical */ + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + /* widely spaced horizontal */ + 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* widely spaced horizontal/vert cross */ + 0xFFFF, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080, + 0xFFFF, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080, +}; + +const UWORD HOLLOW = 0; +const UWORD SOLID = 0xFFFF; + + + +/* + * dsf_udpat - Update pattern + */ + +void +dsf_udpat(Vwk * vwk) +{ + WORD *sp, *dp, i, count; + + count = CONTRL[3]; + + if (count == 16) + vwk->multifill = 0; /* Single Plane Pattern */ + else if (count == (INQ_TAB[4] * 16)) + vwk->multifill = 1; /* Valid Multi-plane pattern */ + else + return; /* Invalid pattern, return */ + + sp = INTIN; + dp = &vwk->ud_patrn[0]; + for (i = 0; i < count; i++) + *dp++ = *sp++; +} + + + +/* + * _vsf_interior - Set fill style + */ + +void +_vsf_interior(Vwk * vwk) +{ + WORD fs; + + CONTRL[4] = 1; + fs = *INTIN; + if ((fs > MX_FIL_STYLE) || (fs < 0)) + fs = 0; + *INTOUT = vwk->fill_style = fs; + st_fl_ptr(vwk); +} + + + +/* S_FILL_INDEX: */ +void +_vsf_style(Vwk * vwk) +{ + WORD fi; + + CONTRL[4] = 1; + fi = *INTIN; + + if (vwk->fill_style == 2) { + if ((fi > MX_FIL_PAT_INDEX) || (fi < 1)) + fi = 1; + } else { + if ((fi > MX_FIL_HAT_INDEX) || (fi < 1)) + fi = 1; + } + vwk->fill_index = (*INTOUT = fi) - 1; + st_fl_ptr(vwk); +} + + + +/* S_FILL_COLOR: */ +void +_vsf_color(Vwk * vwk) +{ + WORD fc; + + *(CONTRL + 4) = 1; + fc = *INTIN; + if ((fc >= DEV_TAB[13]) || (fc < 0)) + fc = 1; + + *INTOUT = fc; + vwk->fill_color = MAP_COL[fc]; +} + + + +/* ST_FILLPERIMETER: */ +void +_vsf_perimeter(Vwk * vwk) +{ + WORD *int_out; + + int_out = INTOUT; + + if (*INTIN == 0) { + *int_out = 0; + vwk->fill_per = FALSE; + } else { + *(int_out) = 1; + vwk->fill_per = TRUE; + } + CONTRL[4] = 1; +} + + +/* + * dr_recfl - draw filled rectangle + */ + +void +dr_recfl(Vwk * vwk) +{ + Rect * rect = (Rect*)PTSIN; + + if (vwk->clip) + if (!clipbox(vwk, rect)) + return; + + /* do the real work... */ + draw_rect(vwk, rect, vwk->fill_color); +} + + + +/* + * _v_cellarray - Draw a square of sqares (just color devices) + */ +void +_v_cellarray(Vwk * vwk) +{ + /* not implemented */ +} + + + +/* + * _vq_cellarray - + */ +void +_vq_cellarray(Vwk * vwk) +{ + /* not implemented */ +} + + + +/* + * vql_attr - Inquire current fill area attributes + */ + +void +vqf_attr(Vwk * vwk) +{ + WORD *pointer; + + pointer = INTOUT; + *pointer++ = vwk->fill_style; + *pointer++ = REV_MAP_COL[vwk->fill_color]; + *pointer++ = vwk->fill_index + 1; + *pointer++ = vwk->wrt_mode + 1; + *pointer = vwk->fill_per; + + CONTRL[4] = 5; +} + + + +/* + * st_fl_ptr - set fill pattern? + */ + +void +st_fl_ptr(Vwk * vwk) +{ + WORD fi, pm; + const UWORD *pp = NULL; + + fi = vwk->fill_index; + pm = 0; + switch (vwk->fill_style) { + case 0: + pp = &HOLLOW; + break; + + case 1: + pp = &SOLID; + break; + + case 2: + if (fi < 8) { + pm = DITHRMSK; + pp = &DITHER[fi * (pm + 1)]; + } else { + pm = OEMMSKPAT; + pp = &OEMPAT[(fi - 8) * (pm + 1)]; + } + break; + case 3: + if (fi < 6) { + pm = HAT_0_MSK; + pp = &HATCH0[fi * (pm + 1)]; + } else { + pm = HAT_1_MSK; + pp = &HATCH1[(fi - 6) * (pm + 1)]; + } + break; + case 4: + pm = 0x000f; + pp = (UWORD *)&vwk->ud_patrn[0]; + break; + } + vwk->patptr = (UWORD *)pp; + vwk->patmsk = pm; +} + + + +/* + * bub_sort - sorts an array of words + * + * This routine bubble-sorts an array of words into ascending order. + * + * input: + * buf - ptr to start of array. + * count - number of words in array. + */ + +static void +bub_sort (WORD * buf, WORD count) +{ + int i, j; + + for (i = count-1; i > 0; i--) { + WORD * ptr = buf; /* reset pointer to the array */ + for (j = 0; j < i; j++) { + WORD val = *ptr++; /* word */ /* get next value */ + if ( val > *ptr ) { /* yes - do nothing */ + *(ptr-1) = *ptr; /* word */ /* nope - swap them */ + *ptr = val; /* word */ + } + } + } +} + + + +/* + * clc_flit - draw a filled polygon + * + * (Sutherland and Hodgman Polygon Clipping Algorithm) + * + * For each non-horizontal scanline crossing poly, do: + * - find intersection points of scan line with poly edges. + * - Sort intersections left to right + * - Draw pixels between each pair of points (x coords) on the scan line + */ +/* + * the buffer used by clc_flit() has been temporarily moved from the + * stack to a local static area. this avoids some cases of stack + * overflow when the VDI is called from the AES (and the stack is the + * small one located in the UDA). this fix allows GemAmigo to run. + * + * this change restores the situation that existed in the original + * DRI code, when clc_flit() was written in assembler; the buffer + * was moved to the stack when clc_flit() was re-implemented in C. + */ +#define MAX_INTERSECTIONS 256 +static WORD fill_buffer[MAX_INTERSECTIONS]; + +void +clc_flit (const VwkAttrib * attr, const VwkClip * clipper, const Point * point, WORD y, int vectors) +{ +// WORD fill_buffer[256]; /* must be 256 words or it will fail */ + WORD * bufptr; /* point to array of x-values. */ + int intersections; /* count of intersections */ + int i; + + /* Initialize the pointers and counters. */ + intersections = 0; /* reset counter */ + bufptr = fill_buffer; + + /* find intersection points of scan line with poly edges. */ + for (i = vectors - 1; i >= 0; i--) { + WORD x1, x2, y1, y2, dy; + + x1 = point->x; /* fetch x-value of 1st endpoint. */ + y1 = point->y; /* fetch y-value of 1st endpoint. */ + point++; + x2 = point->x; /* fetch x-value of 2nd endpoint. */ + y2 = point->y; /* fetch y-value of 2nd endpoint. */ + + /* if the current vector is horizontal, ignore it. */ + dy = y2 - y1; + if ( dy ) { + LONG dy1, dy2; + + /* fetch scan-line y. */ + dy1 = y - y1; /* d4 - delta y1. */ + dy2 = y - y2; /* d3 - delta y2. */ + + /* + * Determine whether the current vector intersects with the scan + * line we wish to draw. This test is performed by computing the + * y-deltas of the two endpoints from the scan line. + * If both deltas have the same sign, then the line does + * not intersect and can be ignored. The origin for this + * test is found in Newman and Sproull. + */ + if ((dy1 < 0) != (dy2 < 0)) { + int dx = (x2 - x1) << 1; /* so we can round by adding 1 below */ + if (++intersections > MAX_INTERSECTIONS) + break; + /* fill edge buffer with x-values */ + if ( dx < 0 ) { + *bufptr++ = ((dy2 * dx / dy + 1) >> 1) + x2; + } + else { + *bufptr++ = ((dy1 * dx / dy + 1) >> 1) + x1; + } + } + } + } + + /* + * All of the points of intersection have now been found. If there + * were none then there is nothing more to do. Otherwise, sort the + * list of points of intersection in ascending order. + * (The list contains only the x-coordinates of the points.) + */ + + /* anything to do? */ + if (intersections == 0) + return; + + /* bubblesort the intersections, if it makes sense */ + if ( intersections > 1 ) + bub_sort(fill_buffer, intersections); + + if (attr->clip) { + /* Clipping is in force. Once the endpoints of the line segment have */ + /* been adjusted for the border, clip them to the left and right sides */ + /* of the clipping rectangle. */ + + /* The x-coordinates of each line segment are adjusted so that the */ + /* border of the figure will not be drawn with the fill pattern. */ + + /* loop through buffered points */ + WORD * ptr = fill_buffer; + for (i = intersections / 2 - 1; i >= 0; i--) { + WORD x1, x2; + Rect rect; + + /* grab a pair of adjusted intersections */ + x1 = *ptr++ + 1; + x2 = *ptr++ - 1; + + /* do nothing, if starting point greater than ending point */ + if ( x1 > x2 ) + continue; + + if ( x1 < clipper->xmn_clip ) { + if ( x2 < clipper->xmn_clip ) + continue; /* entire segment clipped left */ + x1 = clipper->xmn_clip; /* clip left end of line */ + } + + if ( x2 > clipper->xmx_clip ) { + if ( x1 > clipper->xmx_clip ) + continue; /* entire segment clippped */ + x2 = clipper->xmx_clip; /* clip right end of line */ + } + rect.x1 = x1; + rect.y1 = y; + rect.x2 = x2; + rect.y2 = y; + + /* rectangle fill routine draws horizontal line */ + draw_rect_common(attr, &rect); + } + } + else { + /* Clipping is not in force. Draw from point to point. */ + + /* This code has been modified from the version in the screen driver. */ + /* The x-coordinates of each line segment are adjusted so that the */ + /* border of the figure will not be drawn with the fill pattern. If */ + /* the starting point is greater than the ending point then nothing is */ + /* done. */ + + /* loop through buffered points */ + WORD * ptr = fill_buffer; + for (i = intersections / 2 - 1; i >= 0; i--) { + WORD x1, x2; + Rect rect; + + /* grab a pair of adjusted endpoints */ + x1 = *ptr++ + 1 ; /* word */ + x2 = *ptr++ - 1 ; /* word */ + + /* If starting point greater than ending point, nothing is done. */ /* is start still to left of end? */ + if ( x1 <= x2 ) { + rect.x1 = x1; + rect.y1 = y; + rect.x2 = x2; + rect.y2 = y; + + /* rectangle fill routine draws horizontal line */ + draw_rect_common(attr, &rect); + } + } + } +} + + +/* + * polygon - draw a filled polygon + */ + +void +polygon(Vwk * vwk, Point * ptsin, int count) +{ + WORD i, k, y; + WORD fill_maxy, fill_miny; + Point * point, * ptsget, * ptsput; + VwkClip *clipper; + VwkAttrib attr; + + LSTLIN = FALSE; + + /* find out the total min and max y values */ + point = ptsin; + fill_maxy = fill_miny = point->y; + for (i = count - 1; i > 0; i--) { + point++; + k = point->y; + + if (k < fill_miny) + fill_miny = k; + else + if (k > fill_maxy) + fill_maxy = k; + } + + if (vwk->clip) { + if (fill_miny < vwk->ymn_clip) { + if (fill_maxy >= vwk->ymn_clip) { + /* polygon starts before clip */ + fill_miny = vwk->ymn_clip - 1; /* polygon partial overlap */ + if (fill_miny < 1) + fill_miny = 1; + } else + return; /* polygon entirely before clip */ + } + if (fill_maxy > vwk->ymx_clip) { + if (fill_miny <= vwk->ymx_clip) /* polygon ends after clip */ + fill_maxy = vwk->ymx_clip; /* polygon partial overlap */ + else + return; /* polygon entirely after clip */ + } + } + + /* close the polygon, connect last and first point */ + ptsget = ptsin; + ptsput = ptsin + count; + ptsput->x = ptsget->x; + ptsput->y = ptsget->y; + + /* cast structure needed by clc_flit */ + clipper = VDI_CLIP(vwk); + /* copy data needed by clc_flit -> draw_rect_common */ + Vwk2Attrib(vwk, &attr, vwk->fill_color); + + /* really draw it */ + for (y = fill_maxy; y > fill_miny; y--) { + clc_flit(&attr, clipper, ptsin, y, count); + } + if (vwk->fill_per == TRUE) { + LN_MASK = 0xffff; + polyline(vwk, ptsin, count+1, vwk->fill_color); + } +} + + + +/* + * _v_fillarea - Fill an area + */ + +void +_v_fillarea(Vwk * vwk) +{ + Point * point = (Point*)PTSIN; + int count = CONTRL[1]; + +#if 0 +#if HAVE_BEZIER + /* check, if we want to draw a filled bezier curve */ + if (CONTRL[5] == 13 && vwk->bez_qual ) + v_bez_fill(vwk, point, count); + else +#endif +#endif + polygon(vwk, point, count); +} + + + +/* + * clipbox - Just clips and copies the inputs for use by "rectfill" + * + * input: + * X1 = x coord of upper left corner. + * Y1 = y coord of upper left corner. + * X2 = x coord of lower right corner. + * Y2 = y coord of lower right corner. + * vwk->clip = clipping flag. (0 => no clipping.) + * vwk->xmn_clip = x clipping minimum. + * vwk->xmx_clip = x clipping maximum. + * vwk->ymn_clip = y clipping minimum. + * vwk->ymx_clip = y clipping maximum. + * + * output: + * X1 = x coord of upper left corner. + * Y1 = y coord of upper left corner. + * X2 = x coord of lower right corner. + * Y2 = y coord of lower right corner. + */ + +static BOOL +clipbox(Vwk * vwk, Rect * rect) +{ + WORD x1, y1, x2, y2; + + x1 = rect->x1; + y1 = rect->y1; + x2 = rect->x2; + y2 = rect->y2; + + /* clip x coordinates */ + if ( x1 < vwk->xmn_clip) { + if (x2 < vwk->xmn_clip) { + return(FALSE); /* clipped box is null */ + } + rect->x1 = vwk->xmn_clip; + } + if ( x2 > vwk->xmx_clip) { + if (x1 > vwk->xmx_clip) { + return(FALSE); /* clipped box is null */ + } + rect->x2 = vwk->xmx_clip; + } + /* clip y coordinates */ + if ( y1 < vwk->ymn_clip) { + if (y2 < vwk->ymn_clip) { + return(FALSE); /* clipped box is null */ + } + rect->y1 = vwk->ymn_clip; + } + if ( y2 > vwk->ymx_clip) { + if (y1 > vwk->ymx_clip) { + return(FALSE); /* clipped box is null */ + } + rect->y2 = vwk->ymx_clip; + } + return (TRUE); +} + + +/* + * get_color - Get color value of requested pixel. + */ +static UWORD +get_color (UWORD mask, UWORD * addr) +{ + UWORD color = 0; /* clear the pixel value accumulator. */ + WORD plane = v_planes; + + while(1) { + /* test the bit. */ + if ( *--addr & mask ) + color |= 1; /* if 1, set color accumulator bit. */ + + if ( --plane == 0 ) + break; + + color <<= 1; /* shift accumulator for next bit_plane. */ + } + + return color; /* this is the color we are searching for */ +} + +/* + * pixelread - gets a pixel's color index value + * + * input: + * PTSIN(0) = x coordinate. + * PTSIN(1) = y coordinate. + * output: + * pixel value + */ + +static UWORD +pixelread(const WORD x, const WORD y) +{ + UWORD *addr; + UWORD mask; + + /* convert x,y to start adress and bit mask */ + addr = get_start_addr(x, y); + addr += v_planes; /* start at highest-order bit_plane */ + mask = 0x8000 >> (x&0xf); /* initial bit position in WORD */ + + return get_color(mask, addr); /* return the composed color value */ +} + +static UWORD +search_to_right (Vwk * vwk, WORD x, UWORD mask, const UWORD search_col, UWORD * addr) +{ + /* is x coord < x resolution ? */ + while( x++ < vwk->xmx_clip ) { + UWORD color; + + /* need to jump over interleaved bit_plane? */ + mask = mask >> 1 | mask << 15; /* roll right */ + if ( mask & 0x8000 ) + addr += v_planes; + + /* search, while pixel color != search color */ + color = get_color(mask, addr); + if ( search_col != color ) { + break; + } + + } + + return x - 1; /* output x coord -1 to endxright. */ +} + +static UWORD +search_to_left (Vwk * vwk, WORD x, UWORD mask, const UWORD search_col, UWORD * addr) +{ + /* Now, search to the left. */ + while (x-- > vwk->xmn_clip) { + UWORD color; + + /* need to jump over interleaved bit_plane? */ + mask = mask >> 15 | mask << 1; /* roll left */ + if ( mask & 0x0001 ) + addr -= v_planes; + + /* search, while pixel color != search color */ + color = get_color(mask, addr); + if ( search_col != color ) + break; + + } + + return x + 1; /* output x coord + 1 to endxleft. */ +} + +/* + * end_pts - find the endpoints of a section of solid color + * + * (for the _seed_fill routine.) + * + * input: 4(sp) = xstart. + * 6(sp) = ystart. + * 8(sp) = ptr to endxleft. + * C(sp) = ptr to endxright. + * + * output: endxleft := left endpoint of solid color. + * endxright := right endpoint of solid color. + * d0 := success flag. + * 0 => no endpoints or xstart on edge. + * 1 => endpoints found. + * seed_type indicates the type of fill + */ + +static WORD +end_pts(Vwk * vwk, WORD x, WORD y, WORD *xleftout, WORD *xrightout, + BOOL seed_type) +{ + UWORD color; + UWORD * addr; + UWORD mask; + + /* see, if we are in the y clipping range */ + if ( y < vwk->ymn_clip || y > vwk->ymx_clip) + return 0; + + /* convert x,y to start adress and bit mask */ + addr = get_start_addr(x, y); + addr += v_planes; /* start at highest-order bit_plane */ + mask = 0x8000 >> (x & 0x000f); /* fetch the pixel mask. */ + + /* get search color and the left and right end */ + color = get_color (mask, addr); + *xrightout = search_to_right (vwk, x, mask, color, addr); + *xleftout = search_to_left (vwk, x, mask, color, addr); + + /* see, if the whole found segment is of search color? */ + if ( color != search_color ) { + return seed_type ^ 1; /* return segment not of search color */ + } + return seed_type ^ 0; /* return segment is of search color */ +} + +/* Prototypes local to this module */ +static WORD +get_seed(Vwk * vwk, WORD xin, WORD yin, WORD *xleftout, WORD *xrightout, + BOOL seed_type); + + +void +d_contourfill(Vwk * vwk) +{ + WORD newxleft; /* ends of line at oldy + */ + WORD newxright; /* the current direction */ + WORD oldxleft; /* left end of line at oldy */ + WORD oldxright; /* right end */ + WORD oldy; /* the previous scan line */ + WORD xleft; /* temporary endpoints */ + WORD xright; /* */ + WORD direction; /* is next scan line up or down */ + BOOL notdone; /* does seedpoint==search_color */ + BOOL gotseed; /* a seed was put in the Q */ + BOOL seed_type; /* indicates the type of fill */ + + xleft = PTSIN[0]; + oldy = PTSIN[1]; + + if (xleft < vwk->xmn_clip || xleft > vwk->xmx_clip || + oldy < vwk->ymn_clip || oldy > vwk->ymx_clip) + return; + + search_color = INTIN[0]; + + if ((WORD)search_color < 0) { + search_color = pixelread(xleft,oldy); + seed_type = 1; + } else { + const WORD plane_mask[] = { 1, 3, 7, 15 }; + + /* Range check the color and convert the index to a pixel value */ + if (search_color >= DEV_TAB[13]) + return; + + /* + * We mandate that white is all bits on. Since this yields 15 + * in rom, we must limit it to how many planes there really are. + * Anding with the mask is only necessary when the driver supports + * move than one resolution. + */ + search_color = + (MAP_COL[search_color] & plane_mask[INQ_TAB[4] - 1]); + seed_type = 0; + } + + /* Initialize the line drawing parameters */ + LSTLIN = FALSE; + + notdone = end_pts(vwk, xleft, oldy, &oldxleft, &oldxright, seed_type); + + qptr = qbottom = 0; + qtop = 3; /* one above highest seed point */ + queue[0] = (oldy | DOWN_FLAG); + queue[1] = oldxleft; + queue[2] = oldxright; /* stuff a point going down into the Q */ + + if (notdone) { + /* couldn't get point out of Q or draw it */ + while (1) { + Rect rect; + + direction = (oldy & DOWN_FLAG) ? 1 : -1; + gotseed = get_seed(vwk, oldxleft, (oldy + direction), + &newxleft, &newxright, seed_type); + + if ((newxleft < (oldxleft - 1)) && gotseed) { + xleft = oldxleft; + while (xleft > newxleft) { + --xleft; + get_seed(vwk, xleft, oldy ^ DOWN_FLAG, + &xleft, &xright, seed_type); + } + } + while (newxright < oldxright) { + ++newxright; + gotseed = get_seed(vwk, newxright, oldy + direction, + &xleft, &newxright, seed_type); + } + if ((newxright > (oldxright + 1)) && gotseed) { + xright = oldxright; + while (xright < newxright) { + ++xright; + get_seed(vwk, xright, oldy ^ DOWN_FLAG, + &xleft, &xright, seed_type); + } + } + + /* Eventually jump out here */ + if (qtop == qbottom) + break; + + while (queue[qptr] == EMPTY) { + qptr += 3; + if (qptr == qtop) + qptr = qbottom; + } + + oldy = queue[qptr]; + queue[qptr++] = EMPTY; + oldxleft = queue[qptr++]; + oldxright = queue[qptr++]; + if (qptr == qtop) + crunch_queue(); + + rect.x1 = oldxleft; + rect.y1 = ABS(oldy); + rect.x2 = oldxright; + rect.y2 = ABS(oldy); + + /* rectangle fill routine draws horizontal line */ + draw_rect(vwk, &rect, vwk->fill_color); + } + } +} /* end of fill() */ + +/* + * crunch_queue - move qtop down to remove unused seeds + */ +static void +crunch_queue(void) +{ + while ((queue[qtop - 3] == EMPTY) && (qtop > qbottom)) + qtop -= 3; + if (qptr >= qtop) + qptr = qbottom; +} + +/* + * get_seed - put seeds into Q, if (xin,yin) is not of search_color + */ +static WORD +get_seed(Vwk * vwk, WORD xin, WORD yin, WORD *xleftout, WORD *xrightout, + BOOL seed_type) +{ + if (end_pts(vwk, xin, ABS(yin), xleftout, xrightout, seed_type)) { + /* false if of search_color */ + for (qtmp = qbottom, qhole = EMPTY; qtmp < qtop; qtmp += 3) { + /* see, if we ran into another seed */ + if ( ((queue[qtmp] ^ DOWN_FLAG) == yin) && (queue[qtmp] != EMPTY) && + (queue[qtmp + 1] == *xleftout) ) + + { + /* we ran into another seed so remove it and fill the line */ + Rect rect; + + rect.x1 = *xleftout; + rect.y1 = ABS(yin); + rect.x2 = *xrightout; + rect.y2 = ABS(yin); + + /* rectangle fill routine draws horizontal line */ + draw_rect(vwk, &rect, vwk->fill_color); + + queue[qtmp] = EMPTY; + if ((qtmp + 3) == qtop) + crunch_queue(); + return 0; + } + if ((queue[qtmp] == EMPTY) && (qhole == EMPTY)) + qhole = qtmp; + } + + if (qhole == EMPTY) { + if ((qtop += 3) > QMAX) { + qtmp = qbottom; + qtop -= 3; + } + } else + qtmp = qhole; + + queue[qtmp++] = yin; /* put the y and endpoints in the Q */ + queue[qtmp++] = *xleftout; + queue[qtmp] = *xrightout; + return 1; /* we put a seed in the Q */ + } + + return 0; /* we didnt put a seed in the Q */ +} + + + +void +_v_get_pixel(Vwk * vwk) +{ + WORD pel; + WORD *int_out; + const WORD x = PTSIN[0]; /* fetch x coord. */ + const WORD y = PTSIN[1]; /* fetch y coord. */ + + /* Get the requested pixel */ + pel = (WORD)pixelread(x,y); + + int_out = INTOUT; + *int_out++ = pel; + + *int_out = REV_MAP_COL[pel]; + CONTRL[4] = 2; +} + + + +/* + * get_pix - gets a pixel (just for linea!) + * + * input: + * PTSIN(0) = x coordinate. + * PTSIN(1) = y coordinate. + * output: + * pixel value + */ +WORD +get_pix(void) +{ + /* return the composed color value */ + return pixelread(PTSIN[0], PTSIN[1]); +} + +/* + * put_pix - plot a pixel (just for linea!) + * + * input: + * INTIN(0) = pixel value. + * PTSIN(0) = x coordinate. + * PTSIN(1) = y coordinate. + */ +void +put_pix(void) +{ + UWORD *addr; + UWORD color; + UWORD mask; + int plane; + + const WORD x = PTSIN[0]; + const WORD y = PTSIN[1]; + + /* convert x,y to start adress */ + addr = get_start_addr(x, y); + /* co-ordinates can wrap, but cannot write outside screen, + * alternatively this could check against v_bas_ad+vram_size() + */ + if (addr < (UWORD*)v_bas_ad || addr >= get_start_addr(v_hz_rez, v_vt_rez)) { + return; + } + color = INTIN[0]; /* device dependent encoded color bits */ + mask = 0x8000 >> (x&0xf); /* initial bit position in WORD */ + + for (plane = v_planes-1; plane >= 0; plane-- ) { + color = color >> 1| color << 15; /* rotate color bits */ + if (color&0x8000) + *addr++ |= mask; + else + *addr++ &= ~mask; + } +} diff --git a/video/videl.c b/video/videl.c new file mode 100644 index 0000000..5a6d69e --- /dev/null +++ b/video/videl.c @@ -0,0 +1,895 @@ +/* + * videl.c - Falcon VIDEL support + * + * Copyright (c) 2013 The EmuTOS development team + * + * Authors: + * PES Petr Stehlik + * RFB Roger Burrows + * + * This file is distributed under the GPL, version 2 or at your + * option any later version. See doc/license.txt for details. + */ + +// #define DBG_VIDEL +#ifdef DBG_VIDEL +#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0) +#else +#define dbg(format, arg...) do { ; } while (0) +#endif /* DBG_VIDEL */ + +#include +#include +#include +#include "bas_printf.h" +#include "screen.h" +#include "videl.h" + +uint16_t *colorptr; + +static const int32_t videl_dflt_palette[] = +{ + FRGB_WHITE, FRGB_RED, FRGB_GREEN, FRGB_YELLOW, + FRGB_BLUE, FRGB_MAGENTA, FRGB_CYAN, FRGB_LTGRAY, + FRGB_GRAY, FRGB_LTRED, FRGB_LTGREEN, FRGB_LTYELLOW, + FRGB_LTBLUE, FRGB_LTMAGENTA, FRGB_LTCYAN, FRGB_BLACK, + 0xffff00ff, 0xeded00ed, 0xdddd00dd, 0xcccc00cc, + 0xbaba00ba, 0xaaaa00aa, 0x99990099, 0x87870087, + 0x77770077, 0x66660066, 0x54540054, 0x44440044, + 0x33330033, 0x21210021, 0x11110011, 0x00000000, + 0xff000000, 0xff000011, 0xff000021, 0xff000033, + 0xff000044, 0xff000054, 0xff000066, 0xff000077, + 0xff000087, 0xff000099, 0xff0000aa, 0xff0000ba, + 0xff0000cc, 0xff0000dd, 0xff0000ed, 0xff0000ff, + 0xed0000ff, 0xdd0000ff, 0xcc0000ff, 0xba0000ff, + 0xaa0000ff, 0x990000ff, 0x870000ff, 0x770000ff, + 0x660000ff, 0x540000ff, 0x440000ff, 0x330000ff, + 0x210000ff, 0x110000ff, 0x000000ff, 0x001100ff, + 0x002100ff, 0x003300ff, 0x004400ff, 0x005400ff, + 0x006600ff, 0x007700ff, 0x008700ff, 0x009900ff, + 0x00aa00ff, 0x00ba00ff, 0x00cc00ff, 0x00dd00ff, + 0x00ed00ff, 0x00ff00ff, 0x00ff00ed, 0x00ff00dd, + 0x00ff00cc, 0x00ff00ba, 0x00ff00aa, 0x00ff0099, + 0x00ff0087, 0x00ff0077, 0x00ff0066, 0x00ff0054, + 0x00ff0044, 0x00ff0033, 0x00ff0021, 0x00ff0011, + 0x00ff0000, 0x11ff0000, 0x21ff0000, 0x33ff0000, + 0x44ff0000, 0x54ff0000, 0x66ff0000, 0x77ff0000, + 0x87ff0000, 0x99ff0000, 0xaaff0000, 0xbaff0000, + 0xccff0000, 0xddff0000, 0xedff0000, 0xffff0000, + 0xffed0000, 0xffdd0000, 0xffcc0000, 0xffba0000, + 0xffaa0000, 0xff990000, 0xff870000, 0xff770000, + 0xff660000, 0xff540000, 0xff440000, 0xff330000, + 0xff210000, 0xff110000, 0xba000000, 0xba000011, + 0xba000021, 0xba000033, 0xba000044, 0xba000054, + 0xba000066, 0xba000077, 0xba000087, 0xba000099, + 0xba0000aa, 0xba0000ba, 0xaa0000ba, 0x990000ba, + 0x870000ba, 0x770000ba, 0x660000ba, 0x540000ba, + 0x440000ba, 0x330000ba, 0x210000ba, 0x110000ba, + 0x000000ba, 0x001100ba, 0x002100ba, 0x003300ba, + 0x004400ba, 0x005400ba, 0x006600ba, 0x007700ba, + 0x008700ba, 0x009900ba, 0x00aa00ba, 0x00ba00ba, + 0x00ba00aa, 0x00ba0099, 0x00ba0087, 0x00ba0077, + 0x00ba0066, 0x00ba0054, 0x00ba0044, 0x00ba0033, + 0x00ba0021, 0x00ba0011, 0x00ba0000, 0x11ba0000, + 0x21ba0000, 0x33ba0000, 0x44ba0000, 0x54ba0000, + 0x66ba0000, 0x77ba0000, 0x87ba0000, 0x99ba0000, + 0xaaba0000, 0xbaba0000, 0xbaaa0000, 0xba990000, + 0xba870000, 0xba770000, 0xba660000, 0xba540000, + 0xba440000, 0xba330000, 0xba210000, 0xba110000, + 0x77000000, 0x77000011, 0x77000021, 0x77000033, + 0x77000044, 0x77000054, 0x77000066, 0x77000077, + 0x66000077, 0x54000077, 0x44000077, 0x33000077, + 0x21000077, 0x11000077, 0x00000077, 0x00110077, + 0x00210077, 0x00330077, 0x00440077, 0x00540077, + 0x00660077, 0x00770077, 0x00770066, 0x00770054, + 0x00770044, 0x00770033, 0x00770021, 0x00770011, + 0x00770000, 0x11770000, 0x21770000, 0x33770000, + 0x44770000, 0x54770000, 0x66770000, 0x77770000, + 0x77660000, 0x77540000, 0x77440000, 0x77330000, + 0x77210000, 0x77110000, 0x44000000, 0x44000011, + 0x44000021, 0x44000033, 0x44000044, 0x33000044, + 0x21000044, 0x11000044, 0x00000044, 0x00110044, + 0x00210044, 0x00330044, 0x00440044, 0x00440033, + 0x00440021, 0x00440011, 0x00440000, 0x11440000, + 0x21440000, 0x33440000, 0x44440000, 0x44330000, + 0x44210000, 0x44110000, FRGB_WHITE, FRGB_BLACK +}; + +uint32_t falcon_shadow_palette[256]; /* real Falcon does this, used by vectors.S */ +static uint16_t ste_shadow_palette[16]; + +#define MON_ALL -1 /* code used in VMODE_ENTRY for match on mode only */ + +/* + * tables that cover all(?) valid Falcon modes + * note: + * . 256-colour and Truecolor modes are not currently supported by the VDI + */ +static const VMODE_ENTRY vga_init_table[] = +{ + /* the entries in this table are for VGA/NTSC (i.e. VGA 60Hz) and VGA/PAL + * (i.e. VGA 50Hz). in *this* table, each entry applies to four video modes: + * mode, mode|VIDEL_VERTICAL, mode|VIDEL_PAL, mode|VIDEL_VERTICAL|VIDEL_PAL + */ + { 0x0011, MON_ALL, 0x0017, 0x0012, 0x0001, 0x020a, 0x0009, 0x0011, 0x0419, 0x03ff, 0x003f, 0x003f, 0x03ff, 0x0415 }, + { 0x0012, MON_ALL, 0x00c6, 0x008d, 0x0015, 0x028a, 0x006b, 0x0096, 0x0419, 0x03ff, 0x003f, 0x003f, 0x03ff, 0x0415 }, + { 0x0013, MON_ALL, 0x00c6, 0x008d, 0x0015, 0x029a, 0x007b, 0x0096, 0x0419, 0x03ff, 0x003f, 0x003f, 0x03ff, 0x0415 }, + { 0x0014, MON_ALL, 0x00c6, 0x008d, 0x0015, 0x02ac, 0x0091, 0x0096, 0x0419, 0x03ff, 0x003f, 0x003f, 0x03ff, 0x0415 }, + { 0x0018, MON_ALL, 0x00c6, 0x008d, 0x0015, 0x0273, 0x0050, 0x0096, 0x0419, 0x03ff, 0x003f, 0x003f, 0x03ff, 0x0415 }, + { 0x0019, MON_ALL, 0x0017, 0x0012, 0x0001, 0x020e, 0x000d, 0x0011, 0x0419, 0x03ff, 0x003f, 0x003f, 0x03ff, 0x0415 }, + { 0x001a, MON_ALL, 0x00c6, 0x008d, 0x0015, 0x02a3, 0x007c, 0x0096, 0x0419, 0x03ff, 0x003f, 0x003f, 0x03ff, 0x0415 }, + { 0x001b, MON_ALL, 0x00c6, 0x008d, 0x0015, 0x02ab, 0x0084, 0x0096, 0x0419, 0x03ff, 0x003f, 0x003f, 0x03ff, 0x0415 }, + { 0x0092, MON_ALL, 0x0017, 0x0012, 0x0001, 0x020e, 0x000d, 0x0011, 0x0419, 0x03af, 0x008f, 0x008f, 0x03af, 0x0415 }, + { 0x0098, MON_ALL, 0x00c6, 0x008d, 0x0015, 0x0273, 0x0050, 0x0096, 0x0419, 0x03af, 0x008f, 0x008f, 0x03af, 0x0415 }, + { 0x0099, MON_ALL, 0x0017, 0x0012, 0x0001, 0x020e, 0x000d, 0x0011, 0x0419, 0x03af, 0x008f, 0x008f, 0x03af, 0x0415 }, + { -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } +}; + +static const VMODE_ENTRY nonvga_init_table[] = +{ + /* the remaining entries are for TV+NTSC, TV+PAL, TV+NTSC+overscan, TV+PAL+overscan */ + { 0x0001, MON_ALL, 0x003e, 0x0030, 0x0008, 0x0239, 0x0012, 0x0034, 0x020d, 0x0201, 0x0016, 0x004d, 0x01dd, 0x0207 }, + { 0x0002, MON_ALL, 0x00fe, 0x00c9, 0x0027, 0x000c, 0x006d, 0x00d8, 0x020d, 0x0201, 0x0016, 0x004d, 0x01dd, 0x0207 }, + { 0x0003, MON_ALL, 0x00fe, 0x00c9, 0x0027, 0x001c, 0x007d, 0x00d8, 0x020d, 0x0201, 0x0016, 0x004d, 0x01dd, 0x0207 }, + { 0x0004, MON_ALL, 0x00fe, 0x00c9, 0x0027, 0x002e, 0x008f, 0x00d8, 0x020d, 0x0201, 0x0016, 0x004d, 0x01dd, 0x0207 }, + { 0x0008, MON_ALL, 0x01ff, 0x0197, 0x0050, 0x03f0, 0x009f, 0x01b4, 0x020d, 0x0201, 0x0016, 0x004d, 0x01dd, 0x0207 }, + { 0x0009, MON_ALL, 0x003e, 0x0030, 0x0008, 0x0002, 0x0020, 0x0034, 0x020d, 0x0201, 0x0016, 0x004d, 0x01dd, 0x0207 }, + { 0x000a, MON_ALL, 0x01ff, 0x0197, 0x0050, 0x004d, 0x00fd, 0x01b4, 0x020d, 0x0201, 0x0016, 0x004d, 0x01dd, 0x0207 }, + { 0x000b, MON_ALL, 0x01ff, 0x0197, 0x0050, 0x005d, 0x010d, 0x01b4, 0x020d, 0x0201, 0x0016, 0x004d, 0x01dd, 0x0207 }, + { 0x0021, MON_ALL, 0x003e, 0x0030, 0x0008, 0x0239, 0x0012, 0x0034, 0x0271, 0x0265, 0x002f, 0x007f, 0x020f, 0x026b }, + { 0x0022, MON_ALL, 0x00fe, 0x00cb, 0x0027, 0x000c, 0x006d, 0x00d8, 0x0271, 0x0265, 0x002f, 0x007f, 0x020f, 0x026b }, + { 0x0023, MON_ALL, 0x00fe, 0x00cb, 0x0027, 0x001c, 0x007d, 0x00d8, 0x0271, 0x0265, 0x002f, 0x007f, 0x020f, 0x026b }, + { 0x0024, MON_ALL, 0x00fe, 0x00cb, 0x0027, 0x002e, 0x008f, 0x00d8, 0x0271, 0x0265, 0x002f, 0x007f, 0x020f, 0x026b }, + { 0x0028, MON_ALL, 0x01fe, 0x0199, 0x0050, 0x03ef, 0x00a0, 0x01b2, 0x0271, 0x0265, 0x002f, 0x007f, 0x020f, 0x026b }, + { 0x0029, MON_ALL, 0x003e, 0x0030, 0x0008, 0x0002, 0x0020, 0x0034, 0x0271, 0x0265, 0x002f, 0x007f, 0x020f, 0x026b }, + { 0x002a, MON_ALL, 0x01fe, 0x0199, 0x0050, 0x004d, 0x00fe, 0x01b2, 0x0271, 0x0265, 0x002f, 0x007f, 0x020f, 0x026b }, + { 0x002b, MON_ALL, 0x01fe, 0x0199, 0x0050, 0x005d, 0x010e, 0x01b2, 0x0271, 0x0265, 0x002f, 0x007f, 0x020f, 0x026b }, + { 0x0041, MON_VGA, 0x003e, 0x0030, 0x0008, 0x0239, 0x0012, 0x0034, 0x020d, 0x0201, 0x0016, 0x0025, 0x0205, 0x0207 }, + { 0x0041, MON_ALL, 0x003e, 0x0030, 0x0008, 0x0232, 0x001b, 0x0034, 0x020d, 0x0201, 0x0016, 0x0025, 0x0205, 0x0207 }, + { 0x0042, MON_VGA, 0x00fe, 0x00c9, 0x0027, 0x000c, 0x006d, 0x00d8, 0x020d, 0x0201, 0x0016, 0x0025, 0x0205, 0x0207 }, + { 0x0042, MON_ALL, 0x00fe, 0x00c9, 0x0027, 0x02ec, 0x008d, 0x00d8, 0x020d, 0x0201, 0x0016, 0x0025, 0x0205, 0x0207 }, + { 0x0043, MON_VGA, 0x00fe, 0x00c9, 0x0027, 0x001c, 0x007d, 0x00d8, 0x020d, 0x0201, 0x0016, 0x0025, 0x0205, 0x0207 }, + { 0x0043, MON_ALL, 0x00fe, 0x00c9, 0x0027, 0x02fc, 0x009d, 0x00d8, 0x020d, 0x0201, 0x0016, 0x0025, 0x0205, 0x0207 }, + { 0x0044, MON_VGA, 0x00fe, 0x00c9, 0x0027, 0x002e, 0x008f, 0x00d8, 0x020d, 0x0201, 0x0016, 0x0025, 0x0205, 0x0207 }, + { 0x0044, MON_ALL, 0x00fe, 0x00c9, 0x0027, 0x000e, 0x00af, 0x00d8, 0x020d, 0x0201, 0x0016, 0x0025, 0x0205, 0x0207 }, + { 0x0048, MON_VGA, 0x01ff, 0x0197, 0x0050, 0x03f0, 0x009f, 0x01b4, 0x020d, 0x0201, 0x0016, 0x0025, 0x0205, 0x0207 }, + { 0x0048, MON_ALL, 0x01ff, 0x0197, 0x0050, 0x03b0, 0x00df, 0x01b4, 0x020d, 0x0201, 0x0016, 0x0025, 0x0205, 0x0207 }, + { 0x0049, MON_VGA, 0x003e, 0x0030, 0x0008, 0x023b, 0x001c, 0x0034, 0x020d, 0x0201, 0x0016, 0x0025, 0x0205, 0x0207 }, + { 0x0049, MON_ALL, 0x003e, 0x0030, 0x0008, 0x0237, 0x0020, 0x0034, 0x020d, 0x0201, 0x0016, 0x0025, 0x0205, 0x0207 }, + { 0x004a, MON_VGA, 0x01ff, 0x0197, 0x0050, 0x004d, 0x00fd, 0x01b4, 0x020d, 0x0201, 0x0016, 0x0025, 0x0205, 0x0207 }, + { 0x004a, MON_ALL, 0x01ff, 0x0197, 0x0050, 0x000d, 0x013d, 0x01b4, 0x020d, 0x0201, 0x0016, 0x0025, 0x0205, 0x0207 }, + { 0x004b, MON_VGA, 0x01ff, 0x0197, 0x0050, 0x005d, 0x010d, 0x01b4, 0x020d, 0x0201, 0x0016, 0x0025, 0x0205, 0x0207 }, + { 0x004b, MON_ALL, 0x01ff, 0x0197, 0x0050, 0x001d, 0x014d, 0x01b4, 0x020d, 0x0201, 0x0016, 0x0025, 0x0205, 0x0207 }, + { 0x0061, MON_VGA, 0x003e, 0x0030, 0x0008, 0x0239, 0x0012, 0x0034, 0x0271, 0x0265, 0x002f, 0x0057, 0x0237, 0x026b }, + { 0x0061, MON_ALL, 0x003e, 0x0030, 0x0008, 0x0232, 0x001b, 0x0034, 0x0271, 0x0265, 0x002f, 0x0057, 0x0237, 0x026b }, + { 0x0062, MON_VGA, 0x00fe, 0x00cb, 0x0027, 0x000c, 0x006d, 0x00d8, 0x0271, 0x0265, 0x002f, 0x0057, 0x0237, 0x026b }, + { 0x0062, MON_ALL, 0x00fe, 0x00cb, 0x0027, 0x02ec, 0x008d, 0x00d8, 0x0271, 0x0265, 0x002f, 0x0057, 0x0237, 0x026b }, + { 0x0063, MON_VGA, 0x00fe, 0x00cb, 0x0027, 0x001c, 0x007d, 0x00d8, 0x0271, 0x0265, 0x002f, 0x0057, 0x0237, 0x026b }, + { 0x0063, MON_ALL, 0x00fe, 0x00cb, 0x0027, 0x02fc, 0x009d, 0x00d8, 0x0271, 0x0265, 0x002f, 0x0057, 0x0237, 0x026b }, + { 0x0064, MON_VGA, 0x00fe, 0x00cb, 0x0027, 0x002e, 0x008f, 0x00d8, 0x0271, 0x0265, 0x002f, 0x0057, 0x0237, 0x026b }, + { 0x0064, MON_ALL, 0x00fe, 0x00cb, 0x0027, 0x000e, 0x00af, 0x00d8, 0x0271, 0x0265, 0x002f, 0x0057, 0x0237, 0x026b }, + { 0x0068, MON_VGA, 0x01fe, 0x0199, 0x0050, 0x03ef, 0x00a0, 0x01b2, 0x0271, 0x0265, 0x002f, 0x0057, 0x0237, 0x026b }, + { 0x0068, MON_ALL, 0x01fe, 0x0199, 0x0050, 0x03af, 0x00e0, 0x01b2, 0x0271, 0x0265, 0x002f, 0x0057, 0x0237, 0x026b }, + { 0x0069, MON_VGA, 0x003e, 0x0030, 0x0008, 0x023b, 0x001c, 0x0034, 0x0271, 0x0265, 0x002f, 0x0057, 0x0237, 0x026b }, + { 0x0069, MON_ALL, 0x003e, 0x0030, 0x0008, 0x0237, 0x0020, 0x0034, 0x0271, 0x0265, 0x002f, 0x0057, 0x0237, 0x026b }, + { 0x006a, MON_VGA, 0x01fe, 0x0199, 0x0050, 0x004d, 0x00fe, 0x01b2, 0x0271, 0x0265, 0x002f, 0x0057, 0x0237, 0x026b }, + { 0x006a, MON_ALL, 0x01fe, 0x0199, 0x0050, 0x000d, 0x013e, 0x01b2, 0x0271, 0x0265, 0x002f, 0x0057, 0x0237, 0x026b }, + { 0x006b, MON_VGA, 0x01fe, 0x0199, 0x0050, 0x005d, 0x010e, 0x01b2, 0x0271, 0x0265, 0x002f, 0x0057, 0x0237, 0x026b }, + { 0x006b, MON_ALL, 0x01fe, 0x0199, 0x0050, 0x001d, 0x014e, 0x01b2, 0x0271, 0x0265, 0x002f, 0x0057, 0x0237, 0x026b }, + { 0x0082, MON_ALL, 0x003e, 0x0032, 0x0009, 0x023f, 0x001c, 0x0034, 0x020d, 0x0201, 0x0016, 0x004d, 0x01dd, 0x0207 }, + { 0x0088, MON_MONO, 0x001a, 0x0000, 0x0000, 0x020f, 0x000c, 0x0014, 0x03e9, 0x0000, 0x0000, 0x0043, 0x0363, 0x03e7 }, + { 0x0088, MON_ALL, 0x01ff, 0x0197, 0x0050, 0x03f0, 0x009f, 0x01b4, 0x020d, 0x0201, 0x0016, 0x004d, 0x01dd, 0x0207 }, + { 0x0089, MON_ALL, 0x003e, 0x0032, 0x0009, 0x023f, 0x001c, 0x0034, 0x020d, 0x0201, 0x0016, 0x004d, 0x01dd, 0x0207 }, + { 0x00a2, MON_ALL, 0x003e, 0x0032, 0x0009, 0x023f, 0x001c, 0x0034, 0x0271, 0x0265, 0x002f, 0x006f, 0x01ff, 0x026b }, + { 0x00a8, MON_MONO, 0x001a, 0x0000, 0x0000, 0x020f, 0x000c, 0x0014, 0x03e9, 0x0000, 0x0000, 0x0043, 0x0363, 0x03e7 }, + { 0x00a8, MON_ALL, 0x01fe, 0x0199, 0x0050, 0x03ef, 0x00a0, 0x01b2, 0x0271, 0x0265, 0x002f, 0x007f, 0x020f, 0x026b }, + { 0x00a9, MON_ALL, 0x003e, 0x0032, 0x0009, 0x023f, 0x001c, 0x0034, 0x0271, 0x0265, 0x002f, 0x006f, 0x01ff, 0x026b }, + { 0x00c2, MON_ALL, 0x003e, 0x0032, 0x0009, 0x023f, 0x001c, 0x0034, 0x020d, 0x0201, 0x0016, 0x004d, 0x01dd, 0x0207 }, + { 0x00c8, MON_MONO, 0x001a, 0x0000, 0x0000, 0x020f, 0x000c, 0x0014, 0x03e9, 0x0000, 0x0000, 0x0043, 0x0363, 0x03e7 }, + { 0x00c8, MON_VGA, 0x01ff, 0x0197, 0x0050, 0x03f0, 0x009f, 0x01b4, 0x020d, 0x0201, 0x0016, 0x0025, 0x0205, 0x0207 }, + { 0x00c8, MON_ALL, 0x01ff, 0x0197, 0x0050, 0x03b0, 0x00df, 0x01b4, 0x020d, 0x0201, 0x0016, 0x0025, 0x0205, 0x0207 }, + { 0x00c9, MON_ALL, 0x003e, 0x0032, 0x0009, 0x023f, 0x001c, 0x0034, 0x020d, 0x0201, 0x0016, 0x004d, 0x01dd, 0x0207 }, + { 0x00e2, MON_ALL, 0x003e, 0x0032, 0x0009, 0x023f, 0x001c, 0x0034, 0x0271, 0x0265, 0x002f, 0x006f, 0x01ff, 0x026b }, + { 0x00e8, MON_MONO, 0x001a, 0x0000, 0x0000, 0x020f, 0x000c, 0x0014, 0x03e9, 0x0000, 0x0000, 0x0043, 0x0363, 0x03e7 }, + { 0x00e8, MON_VGA, 0x01fe, 0x0199, 0x0050, 0x03ef, 0x00a0, 0x01b2, 0x0271, 0x0265, 0x002f, 0x0057, 0x0237, 0x026b }, + { 0x00e8, MON_ALL, 0x01fe, 0x0199, 0x0050, 0x03af, 0x00e0, 0x01b2, 0x0271, 0x0265, 0x002f, 0x0057, 0x0237, 0x026b }, + { 0x00e9, MON_ALL, 0x003e, 0x0032, 0x0009, 0x023f, 0x001c, 0x0034, 0x0271, 0x0265, 0x002f, 0x006f, 0x01ff, 0x026b }, + { 0x0101, MON_ALL, 0x003e, 0x0030, 0x0008, 0x0239, 0x0012, 0x0034, 0x020c, 0x0201, 0x0016, 0x004c, 0x01dc, 0x0207 }, + { 0x0102, MON_ALL, 0x00fe, 0x00c9, 0x0027, 0x000c, 0x006d, 0x00d8, 0x020c, 0x0201, 0x0016, 0x004c, 0x01dc, 0x0207 }, + { 0x0103, MON_ALL, 0x00fe, 0x00c9, 0x0027, 0x001c, 0x007d, 0x00d8, 0x020c, 0x0201, 0x0016, 0x004c, 0x01dc, 0x0207 }, + { 0x0104, MON_ALL, 0x00fe, 0x00c9, 0x0027, 0x002e, 0x008f, 0x00d8, 0x020c, 0x0201, 0x0016, 0x004c, 0x01dc, 0x0207 }, + { 0x0108, MON_ALL, 0x01ff, 0x0197, 0x0050, 0x03f0, 0x009f, 0x01b4, 0x020c, 0x0201, 0x0016, 0x004c, 0x01dc, 0x0207 }, + { 0x0109, MON_ALL, 0x003e, 0x0030, 0x0008, 0x0002, 0x0020, 0x0034, 0x020c, 0x0201, 0x0016, 0x004c, 0x01dc, 0x0207 }, + { 0x010a, MON_ALL, 0x01ff, 0x0197, 0x0050, 0x004d, 0x00fd, 0x01b4, 0x020c, 0x0201, 0x0016, 0x004c, 0x01dc, 0x0207 }, + { 0x010b, MON_ALL, 0x01ff, 0x0197, 0x0050, 0x005d, 0x010d, 0x01b4, 0x020c, 0x0201, 0x0016, 0x004c, 0x01dc, 0x0207 }, + { 0x0121, MON_ALL, 0x003e, 0x0030, 0x0008, 0x0239, 0x0012, 0x0034, 0x0270, 0x0265, 0x002f, 0x007e, 0x020e, 0x026b }, + { 0x0122, MON_ALL, 0x00fe, 0x00cb, 0x0027, 0x000c, 0x006d, 0x00d8, 0x0270, 0x0265, 0x002f, 0x007e, 0x020e, 0x026b }, + { 0x0123, MON_ALL, 0x00fe, 0x00cb, 0x0027, 0x001c, 0x007d, 0x00d8, 0x0270, 0x0265, 0x002f, 0x007e, 0x020e, 0x026b }, + { 0x0124, MON_ALL, 0x00fe, 0x00cb, 0x0027, 0x002e, 0x008f, 0x00d8, 0x0270, 0x0265, 0x002f, 0x007e, 0x020e, 0x026b }, + { 0x0128, MON_ALL, 0x01fe, 0x0199, 0x0050, 0x03ef, 0x00a0, 0x01b2, 0x0270, 0x0265, 0x002f, 0x007e, 0x020e, 0x026b }, + { 0x0129, MON_ALL, 0x003e, 0x0030, 0x0008, 0x0002, 0x0020, 0x0034, 0x0270, 0x0265, 0x002f, 0x007e, 0x020e, 0x026b }, + { 0x012a, MON_ALL, 0x01fe, 0x0199, 0x0050, 0x004d, 0x00fe, 0x01b2, 0x0270, 0x0265, 0x002f, 0x007e, 0x020e, 0x026b }, + { 0x012b, MON_ALL, 0x01fe, 0x0199, 0x0050, 0x005d, 0x010e, 0x01b2, 0x0270, 0x0265, 0x002f, 0x007e, 0x020e, 0x026b }, + { 0x0141, MON_VGA, 0x003e, 0x0030, 0x0008, 0x0239, 0x0012, 0x0034, 0x020c, 0x0201, 0x0016, 0x0024, 0x0204, 0x0207 }, + { 0x0141, MON_ALL, 0x003e, 0x0030, 0x0008, 0x0232, 0x001b, 0x0034, 0x020c, 0x0201, 0x0016, 0x0024, 0x0204, 0x0207 }, + { 0x0142, MON_VGA, 0x00fe, 0x00c9, 0x0027, 0x000c, 0x006d, 0x00d8, 0x020c, 0x0201, 0x0016, 0x0024, 0x0204, 0x0207 }, + { 0x0142, MON_ALL, 0x00fe, 0x00c9, 0x0027, 0x02ec, 0x008d, 0x00d8, 0x020c, 0x0201, 0x0016, 0x0024, 0x0204, 0x0207 }, + { 0x0143, MON_VGA, 0x00fe, 0x00c9, 0x0027, 0x001c, 0x007d, 0x00d8, 0x020c, 0x0201, 0x0016, 0x0024, 0x0204, 0x0207 }, + { 0x0143, MON_ALL, 0x00fe, 0x00c9, 0x0027, 0x02fc, 0x009d, 0x00d8, 0x020c, 0x0201, 0x0016, 0x0024, 0x0204, 0x0207 }, + { 0x0144, MON_VGA, 0x00fe, 0x00c9, 0x0027, 0x002e, 0x008f, 0x00d8, 0x020c, 0x0201, 0x0016, 0x0024, 0x0204, 0x0207 }, + { 0x0144, MON_ALL, 0x00fe, 0x00c9, 0x0027, 0x000e, 0x00af, 0x00d8, 0x020c, 0x0201, 0x0016, 0x0024, 0x0204, 0x0207 }, + { 0x0148, MON_VGA, 0x01ff, 0x0197, 0x0050, 0x03f0, 0x009f, 0x01b4, 0x020c, 0x0201, 0x0016, 0x0024, 0x0204, 0x0207 }, + { 0x0148, MON_ALL, 0x01ff, 0x0197, 0x0050, 0x03b0, 0x00df, 0x01b4, 0x020c, 0x0201, 0x0016, 0x0024, 0x0204, 0x0207 }, + { 0x0149, MON_VGA, 0x003e, 0x0030, 0x0008, 0x023b, 0x001c, 0x0034, 0x020c, 0x0201, 0x0016, 0x0024, 0x0204, 0x0207 }, + { 0x0149, MON_ALL, 0x003e, 0x0030, 0x0008, 0x0237, 0x0020, 0x0034, 0x020c, 0x0201, 0x0016, 0x0024, 0x0204, 0x0207 }, + { 0x014a, MON_VGA, 0x01ff, 0x0197, 0x0050, 0x004d, 0x00fd, 0x01b4, 0x020c, 0x0201, 0x0016, 0x0024, 0x0204, 0x0207 }, + { 0x014a, MON_ALL, 0x01ff, 0x0197, 0x0050, 0x000d, 0x013d, 0x01b4, 0x020c, 0x0201, 0x0016, 0x0024, 0x0204, 0x0207 }, + { 0x014b, MON_VGA, 0x01ff, 0x0197, 0x0050, 0x005d, 0x010d, 0x01b4, 0x020c, 0x0201, 0x0016, 0x0024, 0x0204, 0x0207 }, + { 0x014b, MON_ALL, 0x01ff, 0x0197, 0x0050, 0x001d, 0x014d, 0x01b4, 0x020c, 0x0201, 0x0016, 0x0024, 0x0204, 0x0207 }, + { 0x0161, MON_VGA, 0x003e, 0x0030, 0x0008, 0x0239, 0x0012, 0x0034, 0x0270, 0x0265, 0x002f, 0x0056, 0x0236, 0x026b }, + { 0x0161, MON_ALL, 0x003e, 0x0030, 0x0008, 0x0232, 0x001b, 0x0034, 0x0270, 0x0265, 0x002f, 0x0056, 0x0236, 0x026b }, + { 0x0162, MON_VGA, 0x00fe, 0x00cb, 0x0027, 0x000c, 0x006d, 0x00d8, 0x0270, 0x0265, 0x002f, 0x0056, 0x0236, 0x026b }, + { 0x0162, MON_ALL, 0x00fe, 0x00cb, 0x0027, 0x02ec, 0x008d, 0x00d8, 0x0270, 0x0265, 0x002f, 0x0056, 0x0236, 0x026b }, + { 0x0163, MON_VGA, 0x00fe, 0x00cb, 0x0027, 0x001c, 0x007d, 0x00d8, 0x0270, 0x0265, 0x002f, 0x0056, 0x0236, 0x026b }, + { 0x0163, MON_ALL, 0x00fe, 0x00cb, 0x0027, 0x02fc, 0x009d, 0x00d8, 0x0270, 0x0265, 0x002f, 0x0056, 0x0236, 0x026b }, + { 0x0164, MON_VGA, 0x00fe, 0x00cb, 0x0027, 0x002e, 0x008f, 0x00d8, 0x0270, 0x0265, 0x002f, 0x0056, 0x0236, 0x026b }, + { 0x0164, MON_ALL, 0x00fe, 0x00cb, 0x0027, 0x000e, 0x00af, 0x00d8, 0x0270, 0x0265, 0x002f, 0x0056, 0x0236, 0x026b }, + { 0x0168, MON_VGA, 0x01fe, 0x0199, 0x0050, 0x03ef, 0x00a0, 0x01b2, 0x0270, 0x0265, 0x002f, 0x0056, 0x0236, 0x026b }, + { 0x0168, MON_ALL, 0x01fe, 0x0199, 0x0050, 0x03af, 0x00e0, 0x01b2, 0x0270, 0x0265, 0x002f, 0x0056, 0x0236, 0x026b }, + { 0x0169, MON_VGA, 0x003e, 0x0030, 0x0008, 0x023b, 0x001c, 0x0034, 0x0270, 0x0265, 0x002f, 0x0056, 0x0236, 0x026b }, + { 0x0169, MON_ALL, 0x003e, 0x0030, 0x0008, 0x0237, 0x0020, 0x0034, 0x0270, 0x0265, 0x002f, 0x0056, 0x0236, 0x026b }, + { 0x016a, MON_VGA, 0x01fe, 0x0199, 0x0050, 0x004d, 0x00fe, 0x01b2, 0x0270, 0x0265, 0x002f, 0x0056, 0x0236, 0x026b }, + { 0x016a, MON_ALL, 0x01fe, 0x0199, 0x0050, 0x000d, 0x013e, 0x01b2, 0x0270, 0x0265, 0x002f, 0x0056, 0x0236, 0x026b }, + { 0x016b, MON_VGA, 0x01fe, 0x0199, 0x0050, 0x005d, 0x010e, 0x01b2, 0x0270, 0x0265, 0x002f, 0x0056, 0x0236, 0x026b }, + { 0x016b, MON_ALL, 0x01fe, 0x0199, 0x0050, 0x001d, 0x014e, 0x01b2, 0x0270, 0x0265, 0x002f, 0x0056, 0x0236, 0x026b }, + { 0x0182, MON_ALL, 0x003e, 0x0032, 0x0009, 0x023f, 0x001c, 0x0034, 0x020d, 0x0201, 0x0016, 0x004d, 0x01dd, 0x0207 }, + { 0x0188, MON_MONO, 0x001a, 0x0000, 0x0000, 0x020f, 0x000c, 0x0014, 0x03e9, 0x0000, 0x0000, 0x0043, 0x0363, 0x03e7 }, + { 0x0188, MON_ALL, 0x01ff, 0x0197, 0x0050, 0x03f0, 0x009f, 0x01b4, 0x020c, 0x0201, 0x0016, 0x004c, 0x01dc, 0x0207 }, + { 0x0189, MON_ALL, 0x003e, 0x0032, 0x0009, 0x023f, 0x001c, 0x0034, 0x020d, 0x0201, 0x0016, 0x004d, 0x01dd, 0x0207 }, + { 0x01a2, MON_ALL, 0x003e, 0x0032, 0x0009, 0x023f, 0x001c, 0x0034, 0x0271, 0x0265, 0x002f, 0x006f, 0x01ff, 0x026b }, + { 0x01a8, MON_MONO, 0x001a, 0x0000, 0x0000, 0x020f, 0x000c, 0x0014, 0x03e9, 0x0000, 0x0000, 0x0043, 0x0363, 0x03e7 }, + { 0x01a8, MON_ALL, 0x01fe, 0x0199, 0x0050, 0x03ef, 0x00a0, 0x01b2, 0x0270, 0x0265, 0x002f, 0x007e, 0x020e, 0x026b }, + { 0x01a9, MON_ALL, 0x003e, 0x0032, 0x0009, 0x023f, 0x001c, 0x0034, 0x0271, 0x0265, 0x002f, 0x006f, 0x01ff, 0x026b }, + { 0x01c2, MON_ALL, 0x003e, 0x0032, 0x0009, 0x023f, 0x001c, 0x0034, 0x020d, 0x0201, 0x0016, 0x004d, 0x01dd, 0x0207 }, + { 0x01c8, MON_MONO, 0x001a, 0x0000, 0x0000, 0x020f, 0x000c, 0x0014, 0x03e9, 0x0000, 0x0000, 0x0043, 0x0363, 0x03e7 }, + { 0x01c8, MON_VGA, 0x01ff, 0x0197, 0x0050, 0x03f0, 0x009f, 0x01b4, 0x020c, 0x0201, 0x0016, 0x0024, 0x0204, 0x0207 }, + { 0x01c8, MON_ALL, 0x01ff, 0x0197, 0x0050, 0x03b0, 0x00df, 0x01b4, 0x020c, 0x0201, 0x0016, 0x0024, 0x0204, 0x0207 }, + { 0x01c9, MON_ALL, 0x003e, 0x0032, 0x0009, 0x023f, 0x001c, 0x0034, 0x020d, 0x0201, 0x0016, 0x004d, 0x01dd, 0x0207 }, + { 0x01e2, MON_ALL, 0x003e, 0x0032, 0x0009, 0x023f, 0x001c, 0x0034, 0x0271, 0x0265, 0x002f, 0x006f, 0x01ff, 0x026b }, + { 0x01e8, MON_MONO, 0x001a, 0x0000, 0x0000, 0x020f, 0x000c, 0x0014, 0x03e9, 0x0000, 0x0000, 0x0043, 0x0363, 0x03e7 }, + { 0x01e8, MON_VGA, 0x01fe, 0x0199, 0x0050, 0x03ef, 0x00a0, 0x01b2, 0x0270, 0x0265, 0x002f, 0x0056, 0x0236, 0x026b }, + { 0x01e8, MON_ALL, 0x01fe, 0x0199, 0x0050, 0x03af, 0x00e0, 0x01b2, 0x0270, 0x0265, 0x002f, 0x0056, 0x0236, 0x026b }, + { 0x01e9, MON_ALL, 0x003e, 0x0032, 0x0009, 0x023f, 0x001c, 0x0034, 0x0271, 0x0265, 0x002f, 0x006f, 0x01ff, 0x026b }, + { -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } +}; + +void set_palette(uint16_t *colorptr) +{ + uint16_t *palette_regs = (uint16_t *) 0xffff9800; + + do + { + *palette_regs++ = *colorptr++; + } while (palette_regs < (uint16_t *) 0xffff9600 + 16); +} + +/* + * functions for VIDEL programming + */ + +static uint16_t get_videl_bpp(void) +{ + uint16_t f_shift = *(volatile uint16_t *)SPSHIFT; + uint8_t st_shift = *(volatile uint8_t *)ST_SHIFTER; + /* to get bpp, we must examine f_shift and st_shift. + * f_shift is valid if any of bits no. 10, 8 or 4 + * is set. Priority in f_shift is: 10 ">" 8 ">" 4, i.e. + * if bit 10 set then bit 8 and bit 4 don't care... + * If all these bits are 0 get display depth from st_shift + * (as for ST and STe) + */ + int bits_per_pixel = 1; + if (f_shift & 0x400) /* 2 colors */ + bits_per_pixel = 1; + else if (f_shift & 0x100) /* hicolor */ + bits_per_pixel = 16; + else if (f_shift & 0x010) /* 8 bitplanes */ + bits_per_pixel = 8; + else if (st_shift == 0) + bits_per_pixel = 4; + else if (st_shift == 0x1) + bits_per_pixel = 2; + else /* if (st_shift == 0x2) */ + bits_per_pixel = 1; + + return bits_per_pixel; +} + +static uint16_t get_videl_width(void) +{ + return ( * (volatile uint16_t *) 0xffff8210) * 16 / get_videl_bpp(); +} + +static uint16_t get_videl_height(void) +{ + uint16_t vdb = * (volatile uint16_t *) 0xffff82a8; + uint16_t vde = * (volatile uint16_t *) 0xffff82aa; + uint16_t vmode = * (volatile uint16_t *) 0xffff82c2; + + /* visible y resolution: + * Graphics display starts at line VDB and ends at line + * VDE. If interlace mode off unit of VC-registers is + * half lines, else lines. + */ + uint16_t yres = vde - vdb; + if (!(vmode & 0x02)) /* interlace */ + yres >>= 1; + if (vmode & 0x01) /* double */ + yres >>= 1; + + return yres; +} + + +/* + * lookup videl initialisation data for specified mode/monitor + * returns NULL if mode/monitor combination is invalid + */ +const VMODE_ENTRY *lookup_videl_mode(int16_t mode,int16_t monitor) +{ + const VMODE_ENTRY *vmode_init_table, *p; + + if (mode&VIDEL_VGA) + { + vmode_init_table = vga_init_table; + /* ignore bits that don't affect initialisation data */ + mode &= ~(VIDEL_VERTICAL|VIDEL_PAL); + } + else + { + vmode_init_table = nonvga_init_table; + } + + for (p = vmode_init_table; p->vmode >= 0; p++) + if (p->vmode == mode) + if ((p->monitor == MON_ALL) || (p->monitor == monitor)) + return p; + + return NULL; +} + + +/* + * determine scanline width based on video mode + */ +static int16_t determine_width(int16_t mode) +{ + int16_t linewidth; + + linewidth = (mode&VIDEL_80COL) ? 40 : 20; + linewidth <<= (mode & VIDEL_BPPMASK); + if (mode&VIDEL_OVERSCAN) + linewidth = linewidth * 12 / 10; /* multiply by 1.2 */ + + return linewidth; +} + + +/* + * determine vctl based on video mode and monitor type + */ +static int16_t determine_vctl(int16_t mode, int16_t monitor) +{ + int16_t vctl; + + if (mode & VIDEL_VGA) + { + vctl = (mode & VIDEL_80COL) ? 0x08 : 0x04; + if (mode & VIDEL_VERTICAL) + vctl |= 0x01; + } + else + { + vctl = (mode & VIDEL_80COL) ? 0x04 : 0x00; + if (mode & VIDEL_VERTICAL) + vctl |= 0x02; + } + + if (!(mode & VIDEL_COMPAT)) + return vctl; + + switch (mode & VIDEL_BPPMASK) + { + case VIDEL_1BPP: + if (!(mode & VIDEL_VGA) && (monitor == MON_MONO)) + vctl = 0x08; + break; + case VIDEL_2BPP: + vctl = (mode & VIDEL_VGA)? 0x09 : 0x04; + break; + case VIDEL_4BPP: + vctl = (mode & VIDEL_VGA)? 0x05 : 0x00; + break; + } + + return vctl; +} + + +/* + * determine regc0 based on video mode & monitor type + */ +static int16_t determine_regc0(int16_t mode,int16_t monitor) +{ + if (mode & VIDEL_VGA) + return 0x0186; + + if (!(mode & VIDEL_COMPAT)) + return (monitor == MON_TV) ? 0x0183 : 0x0181; + + /* handle ST-compatible modes */ + if ((mode & (VIDEL_80COL | VIDEL_BPPMASK)) == (VIDEL_80COL | VIDEL_1BPP)) + { + /* 80-column, 2-colour */ + switch(monitor) + { + case MON_MONO: + return 0x0080; + case MON_TV: + return 0x0183; + default: + return 0x0181; + } + } + + return (monitor == MON_TV) ? 0x0083 : 0x0081; +} + + +/* + * this routine can set VIDEL to 1,2,4 or 8 bitplanes mode on VGA + */ +static int set_videl_vga(int16_t mode) +{ + volatile char *videlregs = (char *)0xffff8200; +#define videlword(n) (*(volatile uint16_t *)(videlregs+(n))) + const VMODE_ENTRY *p; + int16_t linewidth, monitor, vctl; + + monitor = vmontype(); + + p = lookup_videl_mode(mode,monitor);/* validate mode */ + if (!p) + return -1; + + videlregs[0x0a] = (mode & VIDEL_PAL) ? 2 : 0; /* video sync to 50Hz if PAL */ + + // FIXME: vsync() can't work if the screen is initially turned off + //vsync(); /* wait for vbl so we're not interrupted :-) */ + + videlword(0x82) = p->hht; /* H hold timer */ + videlword(0x84) = p->hbb; /* H border begin */ + videlword(0x86) = p->hbe; /* H border end */ + videlword(0x88) = p->hdb; /* H display begin */ + videlword(0x8a) = p->hde; /* H display end */ + videlword(0x8c) = p->hss; /* H SS */ + + videlword(0xa2) = p->vft; /* V freq timer */ + videlword(0xa4) = p->vbb; /* V border begin */ + videlword(0xa6) = p->vbe; /* V border end */ + videlword(0xa8) = p->vdb; /* V display begin */ + videlword(0xaa) = p->vde; /* V display end */ + videlword(0xac) = p->vss; /* V SS */ + + videlregs[0x60] = 0x00; /* clear ST shift for safety */ + + videlword(0x0e) = 0; /* offset */ + + linewidth = determine_width(mode); + vctl = determine_vctl(mode,monitor); + + videlword(0x10) = linewidth; /* scanline width */ + videlword(0xc2) = vctl; /* video control */ + videlword(0xc0) = determine_regc0(mode,monitor); + videlword(0x66) = 0x0000; /* clear SPSHIFT */ + + switch(mode & VIDEL_BPPMASK) + { + /* set SPSHIFT / ST shift */ + case VIDEL_1BPP: /* 2 colours (mono) */ + if (monitor == MON_MONO) + videlregs[0x60] = 0x02; + else videlword(0x66) = 0x0400; + break; + case VIDEL_2BPP: /* 4 colours */ + videlregs[0x60] = 0x01; + videlword(0x10) = linewidth; /* writing to the ST shifter has */ + videlword(0xc2) = vctl; /* just overwritten these registers */ + break; + case VIDEL_4BPP: /* 16 colours */ + /* if not ST-compatible, SPSHIFT was already set correctly above */ + if (mode & VIDEL_COMPAT) + videlregs[0x60] = 0x00; /* else set ST shifter */ + break; + case VIDEL_8BPP: /* 256 colours */ + videlword(0x66) = 0x0010; + break; + case VIDEL_TRUECOLOR: /* 65536 colours (Truecolor) */ + videlword(0x66) = 0x0100; + break; + } + + return 0; +} + +/* + * the current Falcon video mode; used by vsetmode() & vfixmode() + */ +int16_t current_video_mode; + +/* + * Set Falcon video mode + */ +int16_t vsetmode(int16_t mode) +{ + int16_t ret; + + if (mode == -1) + return current_video_mode; + +#ifdef DBG_VIDEL + xprintf("vsetmode(0x%04x)\n", mode); +#endif + + if (set_videl_vga(mode) < 0) /* invalid mode */ + return current_video_mode; + + ret = current_video_mode; + current_video_mode = mode; + + return ret; +} + +/* + * Get Videl monitor type + */ +int16_t vmontype(void) +{ + return ((*(volatile uint8_t *)0xffff8006) >> 6) & 3; +} + +/* + * Set external video sync mode + */ +int16_t vsetsync(int16_t external) +{ + uint16_t spshift; + + if (external & 0x01) /* external clock wanted? */ + *(volatile int8_t *)SYNCMODE |= 0x01; + else *(volatile int8_t *)SYNCMODE &= 0xfe; + + spshift = *(volatile uint16_t *)SPSHIFT; + + if (external&0x02) /* external vertical sync wanted? */ + spshift |= 0x0020; + else spshift &= 0xffdf; + + if (external&0x04) /* external horizontal sync wanted? */ + spshift |= 0x0040; + else spshift &= 0xffbf; + + *(volatile uint16_t *)SPSHIFT = spshift; + + return 0; /* OK */ +} + +/* + * get video ram size according to mode + */ +int32_t vgetsize(int16_t mode) +{ + const VMODE_ENTRY *p; + int height; + int16_t vctl, monitor; + + monitor = vmontype(); + + mode &= VIDEL_VALID; /* ignore invalid bits */ + if ((mode & VIDEL_BPPMASK) > VIDEL_TRUECOLOR) + { + /* fixup invalid bpp */ + mode &= ~VIDEL_BPPMASK; + mode |= VIDEL_TRUECOLOR; + } + + p = lookup_videl_mode(mode, monitor); + if (!p) + { + /* invalid mode */ + if (mode & VIDEL_COMPAT) + return ST_VRAM_SIZE; + mode &= ~(VIDEL_OVERSCAN|VIDEL_PAL);/* ignore less-important bits */ + p = lookup_videl_mode(mode, monitor);/* & try again */ + if (!p) /* "can't happen" */ + return FALCON_VRAM_SIZE; + } + + vctl = determine_vctl(mode, monitor); + height = p->vde - p->vdb; + if (!(vctl & 0x02)) + height >>= 1; + if (vctl & 0x01) + height >>= 1; + + return (int32_t)determine_width(mode) * 2 * height; +} + +/* + * convert from Falcon palette format to STe palette format + */ +#define falc2ste(a) ((((a) >> 1) & 0x08) | (((a) >> 5) & 0x07)) + +static void convert2ste(uint16_t *ste, uint32_t *falcon) +{ + union + { + int32_t l; + uint8_t b[4]; + } u; + int i; + + for (i = 0; i < 16; i++) + { + u.l = *falcon++; + *ste++ = (falc2ste(u.b[0]) << 8) | (falc2ste(u.b[1]) << 4) | falc2ste(u.b[3]); + } +} + +/* + * determine whether to update STe or Falcon h/w palette registers + * returns true if we need to update the STe h/w palette + */ +static int use_ste_palette(int16_t videomode) +{ + if (vmontype() == MON_MONO) /* always for ST mono monitor */ + return true; + + if ((videomode & VIDEL_BPPMASK) == VIDEL_2BPP) /* always for 4-colour modes */ + return true; + + if ((videomode & VIDEL_COMPAT) && ((videomode & VIDEL_BPPMASK) == VIDEL_4BPP)) + return true; /* and for ST low */ + + return false; +} + +/* + * set palette registers + * + * note that the actual update of the hardware registers is done by the + * VBL interrupt handler, according to the setting of 'colorptr'. since + * the address in colorptr must be even, we use bit 0 as a flag. + * + * colorptr contents VBL interrupt handler action + * ----------------- ---------------------------- + * 0 do nothing + * address load STe palette regs from address + * address | 0x01 load first 16 Falcon palette regs from address + * 0 | 0x01 load 256 Falcon palette regs from falcon_shadow_palette[] + */ +int16_t vsetrgb(int16_t index, int16_t count, uint32_t *rgb) +{ + uint32_t *shadow, *source; + union + { + int32_t l; + uint8_t b[4]; + } u; + int16_t limit; + + if ((index < 0) || (count <= 0)) + return -1; /* Generic error */ + + limit = (get_videl_bpp() <= 4) ? 16 : 256; + if ((index + count) > limit) + return -1; /* Generic error */ + + /* + * we always update the Falcon shadow palette, since that's + * what we'll return for VgetRGB() + */ + shadow = falcon_shadow_palette + index; + source = rgb; + while (count--) + { + u.l = *source++; + u.b[0] = u.b[1]; /* shift R & G */ + u.b[1] = u.b[2]; + u.b[2] = 0x00; + *shadow++ = u.l; + } + + /* + * for ST low or 4-colour modes, we need to convert the + * Falcon shadow registers to STe palette register format, and + * request the VBL interrupt handler to update the STe palette + * registers rather than the Falcon registers + */ + if (use_ste_palette(vsetmode(-1))) + { + convert2ste(ste_shadow_palette, falcon_shadow_palette); + colorptr = ste_shadow_palette; + + + return 0; /* OK */ + } + + colorptr = (limit == 256) ? (uint16_t *) 0x01L : (uint16_t *) ((uint32_t) falcon_shadow_palette|0x01L); + + set_palette(colorptr); + return 0; /* OK */ +} + +/* + * get palette registers + */ +int16_t vgetrgb(int16_t index, int16_t count, uint32_t *rgb) +{ + uint32_t *shadow; + union + { + int32_t l; + uint8_t b[4]; + } u; + int16_t limit; + + if ((index < 0) || (count <= 0)) + return -1; /* Generic error */ + + limit = (get_videl_bpp() <= 4) ? 16 : 256; + if ((index + count) > limit) + return -1; /* Generic error */ + + shadow = falcon_shadow_palette + index; + while (count--) + { + u.l = *shadow++; + u.b[2] = u.b[1]; /* shift R & G right*/ + u.b[1] = u.b[0]; + u.b[0] = 0x00; + *rgb++ = u.l; + } + + return 0; /* OK */ +} + +/* + * Fix Videl mode + * + * This converts an (assumed legal) input mode into the + * corresponding output mode for the current monitor type + */ +int16_t vfixmode(int16_t mode) +{ + int16_t monitor, currentmode; + + monitor = vmontype(); + if (monitor == MON_MONO) + return FALCON_ST_HIGH; + + currentmode = vsetmode(-1); + if (currentmode & VIDEL_PAL) /* set PAL bit per current value */ + mode |= VIDEL_PAL; + else mode &= ~VIDEL_PAL; + + /* handle VGA monitor */ + if (monitor == MON_VGA) + { + mode &= ~VIDEL_OVERSCAN; /* turn off overscan (not used with VGA) */ + if (!(mode & VIDEL_VGA)) /* if mode doesn't have VGA set, */ + mode ^= (VIDEL_VERTICAL | VIDEL_VGA); /* set it & flip vertical */ + if (mode & VIDEL_COMPAT) + { + if ((mode&VIDEL_BPPMASK) == VIDEL_1BPP) + mode &= ~VIDEL_VERTICAL; /* clear vertical for ST high */ + else mode |= VIDEL_VERTICAL; /* set it for ST medium, low */ + } + return mode; + } + + /* handle RGB or TV */ + if (mode & VIDEL_VGA) /* if mode has VGA set, */ + mode ^= (VIDEL_VERTICAL | VIDEL_VGA); /* clear it & flip vertical */ + if (mode & VIDEL_COMPAT) + { + if ((mode & VIDEL_BPPMASK) == VIDEL_1BPP) + mode |= VIDEL_VERTICAL; /* set vertical for ST high */ + else mode &= ~VIDEL_VERTICAL; /* clear it for ST medium, low */ + } + + return mode; +} + +int16_t videl_check_moderez(int16_t moderez) +{ + int16_t current_mode, return_mode; + + if (moderez < 0) /* ignore rez values */ + return 0; + + current_mode = get_videl_mode(); + return_mode = vfixmode(moderez);/* adjust */ + return (return_mode == current_mode) ? 0 : return_mode; +} + +uint32_t videl_vram_size(void) +{ + return get_videl_width() / 8L * get_videl_height() * get_videl_bpp(); +} + +void videl_get_current_mode_info(uint16_t *planes, uint16_t *hz_rez, uint16_t *vt_rez) +{ + *planes = get_videl_bpp(); + *hz_rez = get_videl_width(); + *vt_rez = get_videl_height(); +} + +/* + * Initialise Falcon palette + */ +void initialise_falcon_palette(int16_t mode) +{ + volatile int16_t *col_regs = (int16_t *) ST_PALETTE_REGS; + volatile int32_t *fcol_regs = (int32_t *) FALCON_PALETTE_REGS; + int i, limit; + + /* first, set up Falcon shadow palette and real registers */ + for (i = 0; i < 256; i++) + falcon_shadow_palette[i] = videl_dflt_palette[i]; + + switch(mode&VIDEL_BPPMASK) + { + case VIDEL_1BPP: /* 2-colour mode */ + falcon_shadow_palette[1] = falcon_shadow_palette[15]; + break; + + case VIDEL_2BPP: /* 4-colour mode */ + falcon_shadow_palette[3] = falcon_shadow_palette[15]; + break; + } + + /* a 'feature' of the Falcon hardware: if we're in a mode with less + * than 256 colours, and we attempt to set the Falcon hardware + * palette registers for colours 16 & above, it will screw up the + * values in the first 16 hardware palette registers, resulting in + * a messed-up display ... + * NOTE: what happens in the Truecolor case is yet to be determined, + * although it is probably not important since we don't use those + * registers. + */ + limit = ((mode & VIDEL_BPPMASK) == VIDEL_8BPP) ? 256 : 16; + for (i = 0; i < limit; i++) + fcol_regs[i] = falcon_shadow_palette[i]; + + /* + * if appropriate, set up the STe shadow & real palette registers + */ + if (use_ste_palette(mode)) + { + convert2ste(ste_shadow_palette, falcon_shadow_palette); + for (i = 0; i < 16; i++) + col_regs[i] = ste_shadow_palette[i]; + } +} + +/* + * Get videl mode + * This is the same as vsetmode(-1) except that it returns + * zero when there is no videl. Used by app_save(). + */ +int16_t get_videl_mode(void) +{ + return vsetmode(-1); +} + diff --git a/video/video.c b/video/video.c new file mode 100644 index 0000000..ab53148 --- /dev/null +++ b/video/video.c @@ -0,0 +1,419 @@ +#include "video.h" +#include "videl.h" +#include "screen.h" +#include "pci.h" +#include "pci_ids.h" +#include "mod_devicetable.h" +#include "fb.h" +#include "radeonfb.h" + +// #define DEBUG +#include "debug.h" + +#ifdef _USE_VIDEL_ +#define MON_ALL -1 /* code used in VMODE_ENTRY for match on mode only */ + +/* + * tables that cover all(?) valid Falcon modes + * note: + * . 256-colour and Truecolor modes are not currently supported by the VDI + */ +static const VMODE_ENTRY vga_init_table[] = { + /* the entries in this table are for VGA/NTSC (i.e. VGA 60Hz) and VGA/PAL + * (i.e. VGA 50Hz). in *this* table, each entry applies to four video modes: + * mode, mode|VIDEL_VERTICAL, mode|VIDEL_PAL, mode|VIDEL_VERTICAL|VIDEL_PAL + */ + { 0x0011, MON_ALL, 0x0017, 0x0012, 0x0001, 0x020a, 0x0009, 0x0011, 0x0419, 0x03ff, 0x003f, 0x003f, 0x03ff, 0x0415 }, + { 0x0012, MON_ALL, 0x00c6, 0x008d, 0x0015, 0x028a, 0x006b, 0x0096, 0x0419, 0x03ff, 0x003f, 0x003f, 0x03ff, 0x0415 }, + { 0x0013, MON_ALL, 0x00c6, 0x008d, 0x0015, 0x029a, 0x007b, 0x0096, 0x0419, 0x03ff, 0x003f, 0x003f, 0x03ff, 0x0415 }, + { 0x0014, MON_ALL, 0x00c6, 0x008d, 0x0015, 0x02ac, 0x0091, 0x0096, 0x0419, 0x03ff, 0x003f, 0x003f, 0x03ff, 0x0415 }, + { 0x0018, MON_ALL, 0x00c6, 0x008d, 0x0015, 0x0273, 0x0050, 0x0096, 0x0419, 0x03ff, 0x003f, 0x003f, 0x03ff, 0x0415 }, + { 0x0019, MON_ALL, 0x0017, 0x0012, 0x0001, 0x020e, 0x000d, 0x0011, 0x0419, 0x03ff, 0x003f, 0x003f, 0x03ff, 0x0415 }, + { 0x001a, MON_ALL, 0x00c6, 0x008d, 0x0015, 0x02a3, 0x007c, 0x0096, 0x0419, 0x03ff, 0x003f, 0x003f, 0x03ff, 0x0415 }, + { 0x001b, MON_ALL, 0x00c6, 0x008d, 0x0015, 0x02ab, 0x0084, 0x0096, 0x0419, 0x03ff, 0x003f, 0x003f, 0x03ff, 0x0415 }, + { 0x0092, MON_ALL, 0x0017, 0x0012, 0x0001, 0x020e, 0x000d, 0x0011, 0x0419, 0x03af, 0x008f, 0x008f, 0x03af, 0x0415 }, + { 0x0098, MON_ALL, 0x00c6, 0x008d, 0x0015, 0x0273, 0x0050, 0x0096, 0x0419, 0x03af, 0x008f, 0x008f, 0x03af, 0x0415 }, + { 0x0099, MON_ALL, 0x0017, 0x0012, 0x0001, 0x020e, 0x000d, 0x0011, 0x0419, 0x03af, 0x008f, 0x008f, 0x03af, 0x0415 }, + { -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } +}; + +/* + * Initialise palette registers + * This routine is also used by resolution change + */ +void initialise_palette_registers(int16_t rez,int16_t mode) +{ + initialise_falcon_palette(mode); +} + + +/* + * determine regc0 based on video mode & monitor type + */ +static int16_t determine_regc0(int16_t mode, int16_t monitor) +{ + if (mode&VIDEL_VGA) + return 0x0186; + + if (!(mode&VIDEL_COMPAT)) + return (monitor==MON_TV)?0x0183:0x0181; + + /* handle ST-compatible modes */ + if ((mode&(VIDEL_80COL|VIDEL_BPPMASK)) == (VIDEL_80COL|VIDEL_1BPP)) { /* 80-column, 2-colour */ + switch(monitor) { + case MON_MONO: + return 0x0080; + case MON_TV: + return 0x0183; + default: + return 0x0181; + } + } + + return (monitor==MON_TV)?0x0083:0x0081; +} + +/* + * determine vctl based on video mode and monitor type + */ +static int16_t determine_vctl(int16_t mode,int16_t monitor) +{ + int16_t vctl; + + if (mode&VIDEL_VGA) { + vctl = (mode&VIDEL_80COL) ? 0x08 : 0x04; + if (mode&VIDEL_VERTICAL) + vctl |= 0x01; + } else { + vctl = (mode&VIDEL_80COL) ? 0x04 : 0x00; + if (mode&VIDEL_VERTICAL) + vctl |= 0x02; + } + + if (!(mode&VIDEL_COMPAT)) + return vctl; + + switch(mode&VIDEL_BPPMASK) { + case VIDEL_1BPP: + if (!(mode&VIDEL_VGA) && (monitor == MON_MONO)) + vctl = 0x08; + break; + case VIDEL_2BPP: + vctl = (mode&VIDEL_VGA)? 0x09 : 0x04; + break; + case VIDEL_4BPP: + vctl = (mode&VIDEL_VGA)? 0x05 : 0x00; + break; + } + + return vctl; +} + + +/* + * determine scanline width based on video mode + */ +static int16_t determine_width(int16_t mode) +{ + int16_t linewidth; + + linewidth = (mode&VIDEL_80COL) ? 40 : 20; + linewidth <<= (mode & VIDEL_BPPMASK); + if (mode&VIDEL_OVERSCAN) + linewidth = linewidth * 12 / 10; /* multiply by 1.2 */ + + return linewidth; +} + +static int set_videl_vga(int16_t mode) +{ + volatile char *videlregs = (char *)0xffff8200; +#define videlword(n) (*(volatile uint16_t *)(videlregs+(n))) + const VMODE_ENTRY *p; + int16_t linewidth, monitor, vctl; + + monitor = vmontype(); + + p = lookup_videl_mode(mode,monitor);/* validate mode */ + if (!p) + return -1; + + videlregs[0x0a] = (mode&VIDEL_PAL) ? 2 : 0; /* video sync to 50Hz if PAL */ + + // FIXME: vsync() can't work if the screen is initially turned off + //vsync(); /* wait for vbl so we're not interrupted :-) */ + + videlword(0x82) = p->hht; /* H hold timer */ + videlword(0x84) = p->hbb; /* H border begin */ + videlword(0x86) = p->hbe; /* H border end */ + videlword(0x88) = p->hdb; /* H display begin */ + videlword(0x8a) = p->hde; /* H display end */ + videlword(0x8c) = p->hss; /* H SS */ + + videlword(0xa2) = p->vft; /* V freq timer */ + videlword(0xa4) = p->vbb; /* V border begin */ + videlword(0xa6) = p->vbe; /* V border end */ + videlword(0xa8) = p->vdb; /* V display begin */ + videlword(0xaa) = p->vde; /* V display end */ + videlword(0xac) = p->vss; /* V SS */ + + videlregs[0x60] = 0x00; /* clear ST shift for safety */ + + videlword(0x0e) = 0; /* offset */ + + linewidth = determine_width(mode); + vctl = determine_vctl(mode,monitor); + + videlword(0x10) = linewidth; /* scanline width */ + videlword(0xc2) = vctl; /* video control */ + videlword(0xc0) = determine_regc0(mode,monitor); + videlword(0x66) = 0x0000; /* clear SPSHIFT */ + + switch(mode&VIDEL_BPPMASK) { /* set SPSHIFT / ST shift */ + case VIDEL_1BPP: /* 2 colours (mono) */ + if (monitor == MON_MONO) + videlregs[0x60] = 0x02; + else videlword(0x66) = 0x0400; + break; + case VIDEL_2BPP: /* 4 colours */ + videlregs[0x60] = 0x01; + videlword(0x10) = linewidth; /* writing to the ST shifter has */ + videlword(0xc2) = vctl; /* just overwritten these registers */ + break; + case VIDEL_4BPP: /* 16 colours */ + /* if not ST-compatible, SPSHIFT was already set correctly above */ + if (mode&VIDEL_COMPAT) + videlregs[0x60] = 0x00; /* else set ST shifter */ + break; + case VIDEL_8BPP: /* 256 colours */ + videlword(0x66) = 0x0010; + break; + case VIDEL_TRUECOLOR: /* 65536 colours (Truecolor) */ + videlword(0x66) = 0x0100; + break; + } + + return 0; +} + +int16_t current_video_mode; + +/* Set physical screen address */ + +static void setphys(int32_t addr,int checkaddr) +{ + *(volatile uint8_t *) VIDEOBASE_ADDR_HI = ((uint32_t) addr) >> 16; + *(volatile uint8_t *) VIDEOBASE_ADDR_MID = ((uint32_t) addr) >> 8; + *(volatile uint8_t *) VIDEOBASE_ADDR_LOW = ((uint32_t) addr); +} + +/* + * In the original TOS there used to be an early screen init, + * before memory configuration. This is not used here, and all is + * done at the same time from C. + */ + +void videl_screen_init(void) +{ + uint32_t screen_start; + uint16_t boot_resolution = FALCON_DEFAULT_BOOT; + int16_t monitor_type, sync_mode; + int16_t rez = 0; /* avoid 'may be uninitialized' warning */ + + /* Initialize the interrupt handlers. + * It is important to do this first because the initialization code below + * may call vsync(), which temporarily enables the interrupts. */ + + /* TODO: VEC_HBL = int_hbl; */ + /* TODO: VEC_VBL = int_vbl; */ + + /* + * first, see what we're connected to, and set the + * resolution / video mode appropriately + */ + monitor_type = MON_COLOR; + xprintf("monitor_type = %d\r\n", monitor_type); + + /* reset VIDEL on boot-up */ + /* first set the physbase to a safe memory */ + setphys(0xd00000, 0); + + if (!lookup_videl_mode(boot_resolution, monitor_type)) /* mode isn't in table */ + { + xprintf("Invalid video mode 0x%04x changed to 0x%04x\r\n", + boot_resolution, FALCON_DEFAULT_BOOT); + boot_resolution = FALCON_DEFAULT_BOOT; /* so pick one that is */ + } + + if (!VALID_VDI_BPP(boot_resolution)) /* mustn't confuse VDI */ + { + xprintf("VDI doesn't support video mode 0x%04x, changed to 0x%04x\r\n", + boot_resolution, FALCON_DEFAULT_BOOT); + boot_resolution = FALCON_DEFAULT_BOOT; /* so use default */ + } + + vsetmode(boot_resolution); + rez = FALCON_REZ; /* fake value indicates Falcon/Videl */ + sync_mode = (boot_resolution & VIDEL_PAL) ? 0x02 : 0x00; + *(volatile uint8_t *) SYNCMODE = sync_mode; + + /* + * next, set up the palette(s) + */ + initialise_palette_registers(rez, boot_resolution); + /* FIXME: sshiftmod = rez; */ + + /* videoram is placed just below the phystop */ + screen_start = 0xd00000; + + /* correct physical address */ + setphys(screen_start, 1); +} + +#endif /* _USE_VIDEL_ */ + +static uint8_t mon1_EDID[40]; +static uint8_t mon2_EDID[40]; + +static struct radeonfb_info rfb = +{ + .mon1_EDID = mon1_EDID, + .mon2_EDID = mon2_EDID, +}; + +static struct fb_var_screeninfo default_fb = +{ + .xres = 640, + .yres = 480, + .xres_virtual = 640 * 2, + .yres_virtual = 480 * 2, /* ensure we have accel offscreen space */ + .bits_per_pixel = 8, + .grayscale = 0, + .red = { .length = 8 }, + .green = { .length = 8 }, + .blue = { .length = 8 }, + .activate = FB_ACTIVATE_NOW, + .height = -1, + .width = -1, + .pixclock = 39721, + .left_margin = 40, + .right_margin = 24, + .upper_margin = 32, + .lower_margin = 11, + .hsync_len = 96, + .vsync_len = 2, + .vmode = FB_VMODE_NONINTERLACED, + .activate = FB_ACTIVATE_ALL | FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW +}; + +static struct fb_info fb = +{ + .par = &rfb, + + .fix = + { + .id = "ATI Radeon", + .smem_start = 0x80000000, + .smem_len = 0x00800000, + .type = FB_TYPE_PLANES, + .type_aux = 0, + .visual = FB_VISUAL_PSEUDOCOLOR, + .xpanstep = 1, + .ypanstep = 1, + .ywrapstep = 1, + .line_length = 640, + .mmio_len = 0x88000000, + .accel = 0x4000, + .reserved = { 0, 0, 0 }, + }, +}; + +struct fb_info *info_fb = &fb; + +const char monitor_layout[1024] = "\0"; +int16_t ignore_edid; + +struct mode_option resolution = +{ + .used = 0, + .width = 640, + .height = 480, + .bpp = 8, + .freq = 60, + .flags = 0, +}; + +int16_t force_measure_pll = 0; + +void install_vbl_timer(void *func, int32_t remove) +{ + dbg("not implemented\r\n"); +} + +/* + * detect and initialise PCI graphics cards + */ +void video_init(void) +{ + /* + * detect PCI video card + */ + + int index = 0; + int32_t handle; + struct pci_device_id *board; + int32_t id; + bool radeon_found = false; + + do + { + /* + * scan PCI bus for graphics cards + */ + handle = pci_find_classcode(PCI_BASE_CLASS_DISPLAY | PCI_FIND_BASE_CLASS, index); + dbg("handle=%d\r\n", handle); + if (handle > 0) /* found a display device */ + { + dbg("handle = 0x%x\r\n", handle); + + id = swpl(pci_read_config_longword(handle, PCIIDR)); /* get vendor + device id */ + dbg("PCIIDR=0x%x\r\n", id); + + board = &radeonfb_pci_table[0]; + + do + { + /* check it against elements of table */ + dbg("check %x %x against %08x\r\n", board->device, board->vendor, id); + if ((board->device == (id >> 16)) && (board->vendor == (id & 0xffff))) + { + radeon_found = true; + + dbg("matched\r\n"); + + xprintf("registering RADEON card with PCI handle 0x%02x\r\n", handle); + + if (radeonfb_pci_register(handle, board) >= 0) + { + info_fb->fbops->fb_check_modes(info_fb, &resolution); + + + fb_set_var(info_fb, &default_fb); + inf("RADEON video card found and registered\r\n"); + } + else + { + err("failed to register RADEON PCI video card\r\n"); + } + return; + } + board++; + } while (board->vendor); + } + index++; + } while (handle > 0); + inf("RADEON video card %sfound and %sregistered\r\n", + (radeon_found ? "" : "not "), (radeon_found ? "" : "not ")); +} + + diff --git a/x86emu/x86biosemu.c b/x86emu/x86biosemu.c new file mode 100644 index 0000000..fd0fc87 --- /dev/null +++ b/x86emu/x86biosemu.c @@ -0,0 +1,436 @@ +#define RINFO_ONLY +#include "radeonfb.h" +#include "bas_printf.h" +#include "bas_string.h" +#include "util.h" +#include "driver_mem.h" +#include "x86emu.h" +#include "x86emu_regs.h" +#include "pci.h" +#include "pci_ids.h" +#include "x86pcibios.h" + +// #define DEBUG +#include "debug.h" + +struct rom_header +{ + uint16_t signature; + uint8_t size; + uint8_t init[3]; + uint8_t reserved[0x12]; + uint16_t data; +}; + +struct pci_data +{ + uint32_t signature; + uint16_t vendor; + uint16_t device; + uint16_t reserved_1; + uint16_t dlen; + uint8_t drevision; + uint8_t class_lo; + uint16_t class_hi; + uint16_t ilen; + uint16_t irevision; + uint8_t type; + uint8_t indicator; + uint16_t reserved_2; +}; + +static struct radeonfb_info *rinfo_biosemu; +uint16_t offset_port; +uint32_t offset_mem; +static uint32_t offset_io; +static uint32_t config_address_reg; + + +/* general software interrupt handler */ +static uint32_t getIntVect(struct X86EMU *emu, int num) +{ + return MEM_RW(num << 2) + (MEM_RW((num << 2) + 2) << 4); +} + +/* FixME: There is already a push_word() in the emulator */ +static void pushw(struct X86EMU *emu, uint16_t val) +{ + emu->x86.R_ESP -= 2; + MEM_WW(((uint32_t) emu->x86.R_SS << 4) + emu->x86.R_SP, val); +} + +static int run_bios_int(struct X86EMU *emu, int num) +{ + uint32_t eflags; + + eflags = emu->x86.R_EFLG; + pushw(emu, eflags); + pushw(emu, emu->x86.R_CS); + pushw(emu, emu->x86.R_IP); + emu->x86.R_CS = MEM_RW((num << 2) + 2); + emu->x86.R_IP = MEM_RW(num << 2); + + return 1; +} + +static uint8_t inb(struct X86EMU *emu, uint16_t port) +{ + uint8_t val = 0; + + if ((port >= offset_port) && (port <= offset_port + 0xff)) + { + val = * (volatile uint8_t *) (offset_io + (uint32_t) port); + } + else + dbg("illegal port 0x%x\r\n", port); + + return val; +} + +static uint16_t inw(struct X86EMU *emu, uint16_t port) +{ + uint16_t val = 0; + + if ((port >= offset_port) && (port <= offset_port + 0xFF)) + { + val = swpw(*(volatile uint16_t *)(offset_io + (uint32_t) port)); + } + else + dbg("illegal port 0x%x\r\n", port); + + return val; +} + +#define PC_PCI_INDEX_PORT 0xcf8 +#define PC_PCI_DATA_PORT 0xcfc + +static uint32_t inl(struct X86EMU *emu, uint16_t port) +{ + uint32_t val = 0; + + if ((port >= offset_port) && (port <= offset_port + 0xFF)) + { + val = swpl(*(volatile uint32_t *)(offset_io + (uint32_t) port)); + } + else if (port == PC_PCI_INDEX_PORT) + { + val = config_address_reg; + } + else if ((port == PC_PCI_DATA_PORT) && ((config_address_reg & 0x80000000) != 0)) + { + switch (config_address_reg & 0xFC) + { + case PCIIDR: + val = ((uint32_t) rinfo_biosemu->chipset << 16) + PCI_VENDOR_ID_ATI; + break; + + case PCIBAR1: + val = (uint32_t) offset_port + 1; + break; + + default: + val = pci_read_config_longword(rinfo_biosemu->handle, config_address_reg & 0xFC); + break; + } + } + else + dbg("illegal port 0x%x\r\n", port); + + return val; +} + +static void outb(struct X86EMU *emu, uint16_t port, uint8_t val) +{ + if ((port >= offset_port) && (port <= offset_port + 0xFF)) + { + *(volatile uint8_t *)(offset_io + (uint32_t) port) = val; + } + else + dbg("illegal port 0x%x\r\n", port); +} + +static void outw(struct X86EMU *emu, uint16_t port, uint16_t val) +{ + if ((port >= offset_port) && (port <= offset_port + 0xFF)) + { + *(volatile uint16_t *)(offset_io + (uint32_t) port) = swpw(val); + } + else + dbg("illegal port 0x%x\r\n", port); +} + +static void outl(struct X86EMU *emu, uint16_t port, uint32_t val) +{ + if ((port >= offset_port) && (port <= offset_port + 0xFF)) + { + *(volatile uint32_t *)(offset_io + (uint32_t) port) = swpl(val); + } + else if (port == PC_PCI_INDEX_PORT) + { + config_address_reg = val; + } + else if ((port == PC_PCI_DATA_PORT) && ((config_address_reg & 0x80000000) !=0)) + { + dbg("(0x%x, 0x%x) to PCI config space\r\n", port, val); + if ((config_address_reg & 0xFC) == PCIBAR1) + { + offset_port = (uint16_t) val & 0xFFFC; + } + else + { + pci_write_config_longword(rinfo_biosemu->handle, config_address_reg & 0xFC, val); + } + } + else + dbg("illegal port 0x%x\r\n", port); +} + +/* + * Interrupt multiplexer + */ + +static void do_int(struct X86EMU *emu, int num) +{ + int ret = 0; + + switch (num) + { + case 0x10: + /* video interrupt */ + /* fall through intentional */ + + case 0x42: + /* video interrupt */ + /* fall through intentional */ + + case 0x6d: + /* VGA internal interrupt */ + + dbg("int %02xh, AH=0x%02x, AL=0x%02x\r\n", num, + emu->x86.register_a.I8_reg.h_reg, + emu->x86.register_a.I8_reg.l_reg); + + if (emu->x86.register_a.I8_reg.h_reg == 0x13) /* VGA write string */ + { + int num_chars = emu->x86.register_c.I16_reg.x_reg; + int seg = emu->x86.register_es; + int off = emu->x86.register_bp.I16_reg.x_reg; + int str = (seg << 4) + off; + int i; + + dbg("string to output at 0x%04x:0x%04x length=0x%04x\r\n", seg, off, num_chars); + + /* + * output VGA BIOS version string + */ + for (i = 0; i < num_chars; i++) + xprintf("%c", * (char *)(BIOS_MEM + str + i)); + } + + if (getIntVect(emu, num) == 0x0000) + err("uninitialised int vector\r\n"); + + if (getIntVect(emu, num) == 0xFF065) + { + ret = 1; + } + break; + + case 0x15: + ret = 1; + break; + + case 0x16: + ret = 0; + break; + + case 0x1a: + ret = x86_pcibios_handler(emu); + ret = 1; + break; + + case 0xe6: + ret = 0; + break; + + default: + dbg("unhandled interrupt 0x%x\r\n", num); + break; + } + + if (!ret) + { + ret = run_bios_int(emu, num); + } +} + +static int setup_system_bios(void *base_addr) +{ + char *base = (char *) base_addr; + int i; + + /* + * we trap the "industry standard entry points" to the BIOS + * and all other locations by filling them with "hlt" + * TODO: implement hlt-handler for these + */ + + for (i = 0; i < SIZE_EMU + 4; base[i++] = 0xf4); + + return 1; +} + +void run_bios(struct radeonfb_info *rinfo) +{ + long i; + long j; + unsigned char *ptr; + struct rom_header *rom_header; + struct pci_data *rom_data; + unsigned long rom_size = 0; + unsigned long image_size = 0; + unsigned long addr; + unsigned short initialcs; + unsigned short initialip; + unsigned short devfn = (unsigned short) rinfo->handle; + + struct X86EMU emu = { 0 }; + + X86EMU_init_default(&emu); + emu.emu_inb = inb; + emu.emu_inw = inw; + emu.emu_inl = inl; + + emu.emu_outb = outb; + emu.emu_outw = outw; + emu.emu_outl = outl; + + + if ((rinfo->mmio_base == NULL) || (rinfo->io_base == NULL)) + { + dbg("rinfo->mmio_base = %p, rinfo->io_base = %p\r\n", rinfo->mmio_base, rinfo->io_base); + return; + } + + rinfo_biosemu = rinfo; + config_address_reg = 0; + offset_port = 0x300; + offset_io = (uint32_t) rinfo->io_base - (uint32_t) offset_port; + offset_mem = (uint32_t) rinfo->fb_base - 0xa0000; + + rom_header = NULL; + + do + { + rom_header = (struct rom_header *) ((uintptr_t) rom_header + image_size); // get next image + rom_data = (struct pci_data *) ((uintptr_t) rom_header + (uintptr_t) BIOS_IN16((long) &rom_header->data)); + image_size = (size_t) BIOS_IN16((long) &rom_data->ilen) * 512; + } while ((BIOS_IN8((long) &rom_data->type) != 0) && (BIOS_IN8((long) &rom_data->indicator) != 0)); // make sure we got x86 version + + if (BIOS_IN8((long) &rom_data->type) != 0) + { + dbg("unknown ROM data type = 0x%x\r\n", BIOS_IN8((long) &rom_data->type)); + return; + } + + rom_size = (size_t) BIOS_IN8((uintptr_t) &rom_header->size) * 512; + dbg("ROM size = 0x%lx\r\n", rom_size); + + if (PCI_CLASS_DISPLAY_VGA == BIOS_IN16((long) &rom_data->class_hi)) + { + memset((char *) BIOS_MEM, 0, SIZE_EMU); + setup_system_bios((char *) BIOS_MEM); + + dbg("Copy VGA ROM Image from %p to %p (0x%lx bytes)\r\n", + (uintptr_t) rinfo->bios_seg + (uintptr_t) rom_header, + BIOS_MEM + PCI_VGA_RAM_IMAGE_START, rom_size); + { + long bytes_align = (uintptr_t) rom_header & 3; + + ptr = (uint8_t *) BIOS_MEM; + i = (long) rom_header; + j = PCI_VGA_RAM_IMAGE_START; + + if (bytes_align) + { + for (; i < 4 - bytes_align; ptr[j++] = BIOS_IN8(i++)); + } + + for (; i < (long) rom_header + rom_size; i += 4, j += 4) + { + *((uintptr_t *) &ptr[j]) = swpl(BIOS_IN32(i)); + } + } + addr = PCI_VGA_RAM_IMAGE_START; + } + else + { + memset((uint8_t *) BIOS_MEM, 0, SIZE_EMU); + setup_system_bios((char *) BIOS_MEM); + + dbg("Copy non-VGA ROM Image from %p to %p (0x%lx bytes)\r\n", + (uintptr_t) rinfo->bios_seg + (uintptr_t) rom_header, + BIOS_MEM + PCI_RAM_IMAGE_START, + rom_size); + ptr = (uint8_t *) BIOS_MEM; + for (i = (long) rom_header, j = PCI_RAM_IMAGE_START; i < (long) rom_header + rom_size; ptr[j++] = BIOS_IN8(i++)); + addr = PCI_RAM_IMAGE_START; + } + + initialcs = (addr & 0xf0000) >> 4; + initialip = (addr + 3) & 0xffff; + dbg("initial CS=0x%x, initial IP=0x%x\r\n", initialcs, initialip); + + /* + * set emulator memory + */ + emu.mem_base = (void *) BIOS_MEM; + emu.mem_size = SIZE_EMU; + + for (i = 0; i < 256; i++) + { + emu._X86EMU_intrTab[i] = do_int; + } + + char *date = "01/01/99"; + + for (i = 0; date[i]; i++) + { + emu.emu_wrb(&emu, 0xffff5 + i, date[i]); + } + emu.emu_wrb(&emu, 0xffff7, '/'); + emu.emu_wrb(&emu, 0xffffa, '/'); + + /* cpu setup */ + emu.x86.R_AX = devfn ? devfn : 0xff; + emu.x86.R_DX = 0x80; + emu.x86.R_IP = initialip; + emu.x86.R_CS = initialcs; + + /* Initialize stack and data segment */ + emu.x86.R_SS = initialcs; + emu.x86.R_SP = 0xfffe; + emu.x86.R_DS = 0x0040; + emu.x86.R_ES = 0x0000; + + /* + * We need a sane way to return from bios + * execution. A hlt instruction and a pointer + * to it, both kept on the stack, will do. + */ + pushw(&emu, 0xf4f4); /* hlt; hlt */ + + pushw(&emu, emu.x86.R_SS); + pushw(&emu, emu.x86.R_SP + 2); + + dbg("X86EMU entering emulator\r\n"); + + X86EMU_exec(&emu); + + dbg("X86EMU halted\r\n"); + + /* + * clear emulator memory once we are finished + */ + memset((char *) BIOS_MEM, 0, SIZE_EMU); +} diff --git a/x86emu/x86emu.c b/x86emu/x86emu.c new file mode 100644 index 0000000..acc2cf3 --- /dev/null +++ b/x86emu/x86emu.c @@ -0,0 +1,8164 @@ +/* $NetBSD: x86emu.c,v 1.10 2014/08/04 21:41:44 joerg Exp $ */ + +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* Copyright (C) 2007 Joerg Sonnenberger +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +****************************************************************************/ + +#include +#include +#include +#include "setjmp.h" +#include "debug.h" + +static void x86emu_intr_raise (struct X86EMU *, uint8_t type); + +static void X86EMU_exec_one_byte(struct X86EMU *); +static void X86EMU_exec_two_byte(struct X86EMU *); + +static void fetch_decode_modrm (struct X86EMU *); +static uint8_t fetch_byte_imm (struct X86EMU *); +static uint16_t fetch_word_imm (struct X86EMU *); +static uint32_t fetch_long_imm (struct X86EMU *); +static uint8_t fetch_data_byte (struct X86EMU *, uint32_t offset); +static uint8_t fetch_byte (struct X86EMU *, uint32_t segment, uint32_t offset); +static uint16_t fetch_data_word (struct X86EMU *, uint32_t offset); +static uint16_t fetch_word (struct X86EMU *, uint32_t segment, uint32_t offset); +static uint32_t fetch_data_long (struct X86EMU *, uint32_t offset); +static uint32_t fetch_long (struct X86EMU *, uint32_t segment, uint32_t offset); +static void store_data_byte (struct X86EMU *, uint32_t offset, uint8_t val); +static void store_byte (struct X86EMU *, uint32_t segment, uint32_t offset, uint8_t val); +static void store_data_word (struct X86EMU *, uint32_t offset, uint16_t val); +static void store_word (struct X86EMU *, uint32_t segment, uint32_t offset, uint16_t val); +static void store_data_long (struct X86EMU *, uint32_t offset, uint32_t val); +static void store_long (struct X86EMU *, uint32_t segment, uint32_t offset, uint32_t val); +static uint8_t *decode_rl_byte_register(struct X86EMU *); +static uint16_t *decode_rl_word_register(struct X86EMU *); +static uint32_t *decode_rl_long_register(struct X86EMU *); +static uint8_t *decode_rh_byte_register(struct X86EMU *); +static uint16_t *decode_rh_word_register(struct X86EMU *); +static uint32_t *decode_rh_long_register(struct X86EMU *); +static uint16_t *decode_rh_seg_register(struct X86EMU *); +static uint32_t decode_rl_address(struct X86EMU *); + +static uint8_t decode_and_fetch_byte(struct X86EMU *); +static uint16_t decode_and_fetch_word(struct X86EMU *); +static uint32_t decode_and_fetch_long(struct X86EMU *); + +static uint8_t decode_and_fetch_byte_imm8(struct X86EMU *, uint8_t *); +static uint16_t decode_and_fetch_word_imm8(struct X86EMU *, uint8_t *); +static uint32_t decode_and_fetch_long_imm8(struct X86EMU *, uint8_t *); + +static uint16_t decode_and_fetch_word_disp(struct X86EMU *, int16_t); +static uint32_t decode_and_fetch_long_disp(struct X86EMU *, int16_t); + +static void write_back_byte(struct X86EMU *, uint8_t); +static void write_back_word(struct X86EMU *, uint16_t); +static void write_back_long(struct X86EMU *, uint32_t); + +static uint16_t aaa_word (struct X86EMU *, uint16_t d); +static uint16_t aas_word (struct X86EMU *, uint16_t d); +static uint16_t aad_word (struct X86EMU *, uint16_t d); +static uint16_t aam_word (struct X86EMU *, uint8_t d); +static uint8_t adc_byte (struct X86EMU *, uint8_t d, uint8_t s); +static uint16_t adc_word (struct X86EMU *, uint16_t d, uint16_t s); +static uint32_t adc_long (struct X86EMU *, uint32_t d, uint32_t s); +static uint8_t add_byte (struct X86EMU *, uint8_t d, uint8_t s); +static uint16_t add_word (struct X86EMU *, uint16_t d, uint16_t s); +static uint32_t add_long (struct X86EMU *, uint32_t d, uint32_t s); +static uint8_t and_byte (struct X86EMU *, uint8_t d, uint8_t s); +static uint16_t and_word (struct X86EMU *, uint16_t d, uint16_t s); +static uint32_t and_long (struct X86EMU *, uint32_t d, uint32_t s); +static uint8_t cmp_byte (struct X86EMU *, uint8_t d, uint8_t s); +static uint16_t cmp_word (struct X86EMU *, uint16_t d, uint16_t s); +static uint32_t cmp_long (struct X86EMU *, uint32_t d, uint32_t s); +static void cmp_byte_no_return (struct X86EMU *, uint8_t d, uint8_t s); +static void cmp_word_no_return (struct X86EMU *, uint16_t d, uint16_t s); +static void cmp_long_no_return (struct X86EMU *, uint32_t d, uint32_t s); +static uint8_t daa_byte (struct X86EMU *, uint8_t d); +static uint8_t das_byte (struct X86EMU *, uint8_t d); +static uint8_t dec_byte (struct X86EMU *, uint8_t d); +static uint16_t dec_word (struct X86EMU *, uint16_t d); +static uint32_t dec_long (struct X86EMU *, uint32_t d); +static uint8_t inc_byte (struct X86EMU *, uint8_t d); +static uint16_t inc_word (struct X86EMU *, uint16_t d); +static uint32_t inc_long (struct X86EMU *, uint32_t d); +static uint8_t or_byte (struct X86EMU *, uint8_t d, uint8_t s); +static uint16_t or_word (struct X86EMU *, uint16_t d, uint16_t s); +static uint32_t or_long (struct X86EMU *, uint32_t d, uint32_t s); +static uint8_t neg_byte (struct X86EMU *, uint8_t s); +static uint16_t neg_word (struct X86EMU *, uint16_t s); +static uint32_t neg_long (struct X86EMU *, uint32_t s); +static uint8_t rcl_byte (struct X86EMU *, uint8_t d, uint8_t s); +static uint16_t rcl_word (struct X86EMU *, uint16_t d, uint8_t s); +static uint32_t rcl_long (struct X86EMU *, uint32_t d, uint8_t s); +static uint8_t rcr_byte (struct X86EMU *, uint8_t d, uint8_t s); +static uint16_t rcr_word (struct X86EMU *, uint16_t d, uint8_t s); +static uint32_t rcr_long (struct X86EMU *, uint32_t d, uint8_t s); +static uint8_t rol_byte (struct X86EMU *, uint8_t d, uint8_t s); +static uint16_t rol_word (struct X86EMU *, uint16_t d, uint8_t s); +static uint32_t rol_long (struct X86EMU *, uint32_t d, uint8_t s); +static uint8_t ror_byte (struct X86EMU *, uint8_t d, uint8_t s); +static uint16_t ror_word (struct X86EMU *, uint16_t d, uint8_t s); +static uint32_t ror_long (struct X86EMU *, uint32_t d, uint8_t s); +static uint8_t shl_byte (struct X86EMU *, uint8_t d, uint8_t s); +static uint16_t shl_word (struct X86EMU *, uint16_t d, uint8_t s); +static uint32_t shl_long (struct X86EMU *, uint32_t d, uint8_t s); +static uint8_t shr_byte (struct X86EMU *, uint8_t d, uint8_t s); +static uint16_t shr_word (struct X86EMU *, uint16_t d, uint8_t s); +static uint32_t shr_long (struct X86EMU *, uint32_t d, uint8_t s); +static uint8_t sar_byte (struct X86EMU *, uint8_t d, uint8_t s); +static uint16_t sar_word (struct X86EMU *, uint16_t d, uint8_t s); +static uint32_t sar_long (struct X86EMU *, uint32_t d, uint8_t s); +static uint16_t shld_word (struct X86EMU *, uint16_t d, uint16_t fill, uint8_t s); +static uint32_t shld_long (struct X86EMU *, uint32_t d, uint32_t fill, uint8_t s); +static uint16_t shrd_word (struct X86EMU *, uint16_t d, uint16_t fill, uint8_t s); +static uint32_t shrd_long (struct X86EMU *, uint32_t d, uint32_t fill, uint8_t s); +static uint8_t sbb_byte (struct X86EMU *, uint8_t d, uint8_t s); +static uint16_t sbb_word (struct X86EMU *, uint16_t d, uint16_t s); +static uint32_t sbb_long (struct X86EMU *, uint32_t d, uint32_t s); +static uint8_t sub_byte (struct X86EMU *, uint8_t d, uint8_t s); +static uint16_t sub_word (struct X86EMU *, uint16_t d, uint16_t s); +static uint32_t sub_long (struct X86EMU *, uint32_t d, uint32_t s); +static void test_byte (struct X86EMU *, uint8_t d, uint8_t s); +static void test_word (struct X86EMU *, uint16_t d, uint16_t s); +static void test_long (struct X86EMU *, uint32_t d, uint32_t s); +static uint8_t xor_byte (struct X86EMU *, uint8_t d, uint8_t s); +static uint16_t xor_word (struct X86EMU *, uint16_t d, uint16_t s); +static uint32_t xor_long (struct X86EMU *, uint32_t d, uint32_t s); +static void imul_byte (struct X86EMU *, uint8_t s); +static void imul_word (struct X86EMU *, uint16_t s); +static void imul_long (struct X86EMU *, uint32_t s); +static void mul_byte (struct X86EMU *, uint8_t s); +static void mul_word (struct X86EMU *, uint16_t s); +static void mul_long (struct X86EMU *, uint32_t s); +static void idiv_byte (struct X86EMU *, uint8_t s); +static void idiv_word (struct X86EMU *, uint16_t s); +static void idiv_long (struct X86EMU *, uint32_t s); +static void div_byte (struct X86EMU *, uint8_t s); +static void div_word (struct X86EMU *, uint16_t s); +static void div_long (struct X86EMU *, uint32_t s); +static void ins (struct X86EMU *, int size); +static void outs (struct X86EMU *, int size); +static void push_word (struct X86EMU *, uint16_t w); +static void push_long (struct X86EMU *, uint32_t w); +static uint16_t pop_word (struct X86EMU *); +static uint32_t pop_long (struct X86EMU *); + + +/**************************************************************************** +REMARKS: +Handles any pending asychronous interrupts. +****************************************************************************/ +static void x86emu_intr_dispatch(struct X86EMU *emu, uint8_t intno) +{ + if (emu->_X86EMU_intrTab[intno]) + { + (*emu->_X86EMU_intrTab[intno]) (emu, intno); + } + else + { + push_word(emu, (uint16_t) emu->x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(emu, emu->x86.R_CS); + emu->x86.R_CS = fetch_word(emu, 0, intno * 4 + 2); + push_word(emu, emu->x86.R_IP); + emu->x86.R_IP = fetch_word(emu, 0, intno * 4); + } +} + +static void x86emu_intr_handle(struct X86EMU *emu) +{ + uint8_t intno; + + if (emu->x86.intr & INTR_SYNCH) + { + intno = emu->x86.intno; + emu->x86.intr = 0; + x86emu_intr_dispatch(emu, intno); + } +} + +/**************************************************************************** +PARAMETERS: +intrnum - Interrupt number to raise + +REMARKS: +Raise the specified interrupt to be handled before the execution of the +next instruction. +****************************************************************************/ +void x86emu_intr_raise(struct X86EMU *emu, uint8_t intrnum) +{ + emu->x86.intno = intrnum; + emu->x86.intr |= INTR_SYNCH; +} + +/**************************************************************************** +REMARKS: +Main execution loop for the emulator. We return from here when the system +halts, which is normally caused by a stack fault when we return from the +original real mode call. +****************************************************************************/ +void X86EMU_exec(struct X86EMU *emu) +{ + emu->x86.intr = 0; + + if (setjmp(emu->exec_state)) + return; + + for (;;) { + if (emu->x86.intr) { + if (((emu->x86.intr & INTR_SYNCH) && (emu->x86.intno == 0 || emu->x86.intno == 2)) || + !ACCESS_FLAG(F_IF)) { + x86emu_intr_handle(emu); + } + } + if (emu->x86.R_CS == 0 && emu->x86.R_IP == 0) + return; + X86EMU_exec_one_byte(emu); + ++emu->cur_cycles; + } +} + +void +X86EMU_exec_call(struct X86EMU *emu, uint16_t seg, uint16_t off) +{ + push_word(emu, 0); + push_word(emu, 0); + emu->x86.R_CS = seg; + emu->x86.R_IP = off; + + X86EMU_exec(emu); +} + +void +X86EMU_exec_intr(struct X86EMU *emu, uint8_t intr) +{ + push_word(emu, emu->x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(emu, 0); + push_word(emu, 0); + emu->x86.R_CS = (*emu->emu_rdw)(emu, intr * 4 + 2); + emu->x86.R_IP = (*emu->emu_rdw)(emu, intr * 4); + emu->x86.intr = 0; + + X86EMU_exec(emu); +} +/**************************************************************************** +REMARKS: +Halts the system by setting the halted system flag. +****************************************************************************/ +void +X86EMU_halt_sys(struct X86EMU *emu) +{ + dbg("\r\n"); + +#ifdef _KERNEL + longjmp(&emu->exec_state); +#else + longjmp(emu->exec_state, 1); +#endif +} +/**************************************************************************** +PARAMETERS: +mod - Mod value from decoded byte +regh - Reg h value from decoded byte +regl - Reg l value from decoded byte + +REMARKS: +Raise the specified interrupt to be handled before the execution of the +next instruction. + +NOTE: Do not inline this function, as (*emu->emu_rdb) is already inline! +****************************************************************************/ +static void +fetch_decode_modrm(struct X86EMU *emu) +{ + int fetched; + + fetched = fetch_byte_imm(emu); + emu->cur_mod = (fetched >> 6) & 0x03; + emu->cur_rh = (fetched >> 3) & 0x07; + emu->cur_rl = (fetched >> 0) & 0x07; +} +/**************************************************************************** +RETURNS: +Immediate byte value read from instruction queue + +REMARKS: +This function returns the immediate byte from the instruction queue, and +moves the instruction pointer to the next value. + +NOTE: Do not inline this function, as (*emu->emu_rdb) is already inline! +****************************************************************************/ +static uint8_t +fetch_byte_imm(struct X86EMU *emu) +{ + uint8_t fetched; + + fetched = fetch_byte(emu, emu->x86.R_CS, emu->x86.R_IP); + emu->x86.R_IP++; + return fetched; +} +/**************************************************************************** +RETURNS: +Immediate word value read from instruction queue + +REMARKS: +This function returns the immediate byte from the instruction queue, and +moves the instruction pointer to the next value. + +NOTE: Do not inline this function, as (*emu->emu_rdw) is already inline! +****************************************************************************/ +static uint16_t +fetch_word_imm(struct X86EMU *emu) +{ + uint16_t fetched; + + fetched = fetch_word(emu, emu->x86.R_CS, emu->x86.R_IP); + emu->x86.R_IP += 2; + return fetched; +} +/**************************************************************************** +RETURNS: +Immediate long value read from instruction queue + +REMARKS: +This function returns the immediate byte from the instruction queue, and +moves the instruction pointer to the next value. + +NOTE: Do not inline this function, as (*emu->emu_rdw) is already inline! +****************************************************************************/ +static uint32_t +fetch_long_imm(struct X86EMU *emu) +{ + uint32_t fetched; + + fetched = fetch_long(emu, emu->x86.R_CS, emu->x86.R_IP); + emu->x86.R_IP += 4; + return fetched; +} +/**************************************************************************** +RETURNS: +Value of the default data segment + +REMARKS: +Inline function that returns the default data segment for the current +instruction. + +On the x86 processor, the default segment is not always DS if there is +no segment override. Address modes such as -3[BP] or 10[BP+SI] all refer to +addresses relative to SS (ie: on the stack). So, at the minimum, all +decodings of addressing modes would have to set/clear a bit describing +whether the access is relative to DS or SS. That is the function of the +cpu-state-varible emu->x86.mode. There are several potential states: + + repe prefix seen (handled elsewhere) + repne prefix seen (ditto) + + cs segment override + ds segment override + es segment override + fs segment override + gs segment override + ss segment override + + ds/ss select (in absense of override) + +Each of the above 7 items are handled with a bit in the mode field. +****************************************************************************/ +static uint32_t +get_data_segment(struct X86EMU *emu) +{ + switch (emu->x86.mode & SYSMODE_SEGMASK) { + case 0: /* default case: use ds register */ + case SYSMODE_SEGOVR_DS: + case SYSMODE_SEGOVR_DS | SYSMODE_SEG_DS_SS: + return emu->x86.R_DS; + case SYSMODE_SEG_DS_SS:/* non-overridden, use ss register */ + return emu->x86.R_SS; + case SYSMODE_SEGOVR_CS: + case SYSMODE_SEGOVR_CS | SYSMODE_SEG_DS_SS: + return emu->x86.R_CS; + case SYSMODE_SEGOVR_ES: + case SYSMODE_SEGOVR_ES | SYSMODE_SEG_DS_SS: + return emu->x86.R_ES; + case SYSMODE_SEGOVR_FS: + case SYSMODE_SEGOVR_FS | SYSMODE_SEG_DS_SS: + return emu->x86.R_FS; + case SYSMODE_SEGOVR_GS: + case SYSMODE_SEGOVR_GS | SYSMODE_SEG_DS_SS: + return emu->x86.R_GS; + case SYSMODE_SEGOVR_SS: + case SYSMODE_SEGOVR_SS | SYSMODE_SEG_DS_SS: + return emu->x86.R_SS; + } + dbg("unexpected SYSMODE_SEGMASK. Halting.\r\n", emu->x86.mode & SYSMODE_SEGMASK); + X86EMU_halt_sys(emu); + return 0L; +} +/**************************************************************************** +PARAMETERS: +offset - Offset to load data from + +RETURNS: +Byte value read from the absolute memory location. + +NOTE: Do not inline this function as (*emu->emu_rdX) is already inline! +****************************************************************************/ +static uint8_t +fetch_data_byte(struct X86EMU *emu, uint32_t offset) +{ + return fetch_byte(emu, get_data_segment(emu), offset); +} +/**************************************************************************** +PARAMETERS: +offset - Offset to load data from + +RETURNS: +Word value read from the absolute memory location. + +NOTE: Do not inline this function as (*emu->emu_rdX) is already inline! +****************************************************************************/ +static uint16_t +fetch_data_word(struct X86EMU *emu, uint32_t offset) +{ + return fetch_word(emu, get_data_segment(emu), offset); +} +/**************************************************************************** +PARAMETERS: +offset - Offset to load data from + +RETURNS: +Long value read from the absolute memory location. + +NOTE: Do not inline this function as (*emu->emu_rdX) is already inline! +****************************************************************************/ +static uint32_t +fetch_data_long(struct X86EMU *emu, uint32_t offset) +{ + return fetch_long(emu, get_data_segment(emu), offset); +} +/**************************************************************************** +PARAMETERS: +segment - Segment to load data from +offset - Offset to load data from + +RETURNS: +Byte value read from the absolute memory location. + +NOTE: Do not inline this function as (*emu->emu_rdX) is already inline! +****************************************************************************/ +static uint8_t +fetch_byte(struct X86EMU *emu, uint32_t segment, uint32_t offset) +{ + return (*emu->emu_rdb) (emu, ((uint32_t) segment << 4) + offset); +} +/**************************************************************************** +PARAMETERS: +segment - Segment to load data from +offset - Offset to load data from + +RETURNS: +Word value read from the absolute memory location. + +NOTE: Do not inline this function as (*emu->emu_rdX) is already inline! +****************************************************************************/ +static uint16_t +fetch_word(struct X86EMU *emu, uint32_t segment, uint32_t offset) +{ + return (*emu->emu_rdw) (emu, ((uint32_t) segment << 4) + offset); +} +/**************************************************************************** +PARAMETERS: +segment - Segment to load data from +offset - Offset to load data from + +RETURNS: +Long value read from the absolute memory location. + +NOTE: Do not inline this function as (*emu->emu_rdX) is already inline! +****************************************************************************/ +static uint32_t +fetch_long(struct X86EMU *emu, uint32_t segment, uint32_t offset) +{ + return (*emu->emu_rdl) (emu, ((uint32_t) segment << 4) + offset); +} +/**************************************************************************** +PARAMETERS: +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a word value to an segmented memory location. The segment used is +the current 'default' segment, which may have been overridden. + +NOTE: Do not inline this function as (*emu->emu_wrX) is already inline! +****************************************************************************/ +static void +store_data_byte(struct X86EMU *emu, uint32_t offset, uint8_t val) +{ + store_byte(emu, get_data_segment(emu), offset, val); +} +/**************************************************************************** +PARAMETERS: +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a word value to an segmented memory location. The segment used is +the current 'default' segment, which may have been overridden. + +NOTE: Do not inline this function as (*emu->emu_wrX) is already inline! +****************************************************************************/ +static void +store_data_word(struct X86EMU *emu, uint32_t offset, uint16_t val) +{ + store_word(emu, get_data_segment(emu), offset, val); +} +/**************************************************************************** +PARAMETERS: +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a long value to an segmented memory location. The segment used is +the current 'default' segment, which may have been overridden. + +NOTE: Do not inline this function as (*emu->emu_wrX) is already inline! +****************************************************************************/ +static void +store_data_long(struct X86EMU *emu, uint32_t offset, uint32_t val) +{ + store_long(emu, get_data_segment(emu), offset, val); +} +/**************************************************************************** +PARAMETERS: +segment - Segment to store data at +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a byte value to an absolute memory location. + +NOTE: Do not inline this function as (*emu->emu_wrX) is already inline! +****************************************************************************/ +static void +store_byte(struct X86EMU *emu, uint32_t segment, uint32_t offset, uint8_t val) +{ + (*emu->emu_wrb) (emu, ((uint32_t) segment << 4) + offset, val); +} +/**************************************************************************** +PARAMETERS: +segment - Segment to store data at +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a word value to an absolute memory location. + +NOTE: Do not inline this function as (*emu->emu_wrX) is already inline! +****************************************************************************/ +static void +store_word(struct X86EMU *emu, uint32_t segment, uint32_t offset, uint16_t val) +{ + (*emu->emu_wrw) (emu, ((uint32_t) segment << 4) + offset, val); +} +/**************************************************************************** +PARAMETERS: +segment - Segment to store data at +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a long value to an absolute memory location. + +NOTE: Do not inline this function as (*emu->emu_wrX) is already inline! +****************************************************************************/ +static void +store_long(struct X86EMU *emu, uint32_t segment, uint32_t offset, uint32_t val) +{ + (*emu->emu_wrl) (emu, ((uint32_t) segment << 4) + offset, val); +} +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for byte operands. Also enables the decoding of instructions. +****************************************************************************/ +static uint8_t * +decode_rm_byte_register(struct X86EMU *emu, int reg) +{ + switch (reg) { + case 0: + return &emu->x86.R_AL; + case 1: + return &emu->x86.R_CL; + case 2: + return &emu->x86.R_DL; + case 3: + return &emu->x86.R_BL; + case 4: + return &emu->x86.R_AH; + case 5: + return &emu->x86.R_CH; + case 6: + return &emu->x86.R_DH; + case 7: + return &emu->x86.R_BH; + default: + dbg("unexpected register %d\r\n", reg); + X86EMU_halt_sys(emu); + } + return 0L; +} + +static uint8_t * +decode_rl_byte_register(struct X86EMU *emu) +{ + return decode_rm_byte_register(emu, emu->cur_rl); +} + +static uint8_t * +decode_rh_byte_register(struct X86EMU *emu) +{ + return decode_rm_byte_register(emu, emu->cur_rh); +} +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for word operands. Also enables the decoding of instructions. +****************************************************************************/ +static uint16_t * +decode_rm_word_register(struct X86EMU *emu, int reg) +{ + switch (reg) { + case 0: + return &emu->x86.R_AX; + case 1: + return &emu->x86.R_CX; + case 2: + return &emu->x86.R_DX; + case 3: + return &emu->x86.R_BX; + case 4: + return &emu->x86.R_SP; + case 5: + return &emu->x86.R_BP; + case 6: + return &emu->x86.R_SI; + case 7: + return &emu->x86.R_DI; + default: + dbg("unexpected register %d\r\n", reg); + X86EMU_halt_sys(emu); + } + return 0; +} + +static uint16_t * +decode_rl_word_register(struct X86EMU *emu) +{ + return decode_rm_word_register(emu, emu->cur_rl); +} + +static uint16_t * +decode_rh_word_register(struct X86EMU *emu) +{ + return decode_rm_word_register(emu, emu->cur_rh); +} +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for dword operands. Also enables the decoding of instructions. +****************************************************************************/ +static uint32_t * +decode_rm_long_register(struct X86EMU *emu, int reg) +{ + switch (reg) { + case 0: + return &emu->x86.R_EAX; + case 1: + return &emu->x86.R_ECX; + case 2: + return &emu->x86.R_EDX; + case 3: + return &emu->x86.R_EBX; + case 4: + return &emu->x86.R_ESP; + case 5: + return &emu->x86.R_EBP; + case 6: + return &emu->x86.R_ESI; + case 7: + return &emu->x86.R_EDI; + default: + dbg("unexpected register %d\r\n", reg); + X86EMU_halt_sys(emu); + } + return 0L; +} + +static uint32_t * +decode_rl_long_register(struct X86EMU *emu) +{ + return decode_rm_long_register(emu, emu->cur_rl); +} + +static uint32_t * +decode_rh_long_register(struct X86EMU *emu) +{ + return decode_rm_long_register(emu, emu->cur_rh); +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for word operands, modified from above for the weirdo +special case of segreg operands. Also enables the decoding of instructions. +****************************************************************************/ +static uint16_t * +decode_rh_seg_register(struct X86EMU *emu) +{ + switch (emu->cur_rh) { + case 0: + return &emu->x86.R_ES; + case 1: + return &emu->x86.R_CS; + case 2: + return &emu->x86.R_SS; + case 3: + return &emu->x86.R_DS; + case 4: + return &emu->x86.R_FS; + case 5: + return &emu->x86.R_GS; + default: + dbg("unexpected register %d\r\n", emu->cur_rh); + X86EMU_halt_sys(emu); + } + return 0; +} +/* + * + * return offset from the SIB Byte + */ +static uint32_t +decode_sib_address(struct X86EMU *emu, int sib, int mod) +{ + uint32_t base = 0, i = 0, scale = 1; + + switch (sib & 0x07) { + case 0: + base = emu->x86.R_EAX; + break; + case 1: + base = emu->x86.R_ECX; + break; + case 2: + base = emu->x86.R_EDX; + break; + case 3: + base = emu->x86.R_EBX; + break; + case 4: + base = emu->x86.R_ESP; + emu->x86.mode |= SYSMODE_SEG_DS_SS; + break; + case 5: + if (mod == 0) { + base = fetch_long_imm(emu); + } else { + base = emu->x86.R_EBP; + emu->x86.mode |= SYSMODE_SEG_DS_SS; + } + break; + case 6: + base = emu->x86.R_ESI; + break; + case 7: + base = emu->x86.R_EDI; + break; + } + switch ((sib >> 3) & 0x07) { + case 0: + i = emu->x86.R_EAX; + break; + case 1: + i = emu->x86.R_ECX; + break; + case 2: + i = emu->x86.R_EDX; + break; + case 3: + i = emu->x86.R_EBX; + break; + case 4: + i = 0; + break; + case 5: + i = emu->x86.R_EBP; + break; + case 6: + i = emu->x86.R_ESI; + break; + case 7: + i = emu->x86.R_EDI; + break; + } + scale = 1 << ((sib >> 6) & 0x03); + return base + (i * scale); +} +/**************************************************************************** +PARAMETERS: +rm - RM value to decode + +RETURNS: +Offset in memory for the address decoding + +REMARKS: +Return the offset given by mod=00, mod=01 or mod=10 addressing. +Also enables the decoding of instructions. +****************************************************************************/ +static uint32_t +decode_rl_address(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_ADDR) { + uint32_t offset, sib; + /* 32-bit addressing */ + switch (emu->cur_rl) { + case 0: + offset = emu->x86.R_EAX; + break; + case 1: + offset = emu->x86.R_ECX; + break; + case 2: + offset = emu->x86.R_EDX; + break; + case 3: + offset = emu->x86.R_EBX; + break; + case 4: + sib = fetch_byte_imm(emu); + offset = decode_sib_address(emu, sib, 0); + break; + case 5: + if (emu->cur_mod == 0) { + offset = fetch_long_imm(emu); + } else { + emu->x86.mode |= SYSMODE_SEG_DS_SS; + offset = emu->x86.R_EBP; + } + break; + case 6: + offset = emu->x86.R_ESI; + break; + case 7: + offset = emu->x86.R_EDI; + break; + default: + dbg("unexpected mode %d\r\n", emu->x86.mode & SYSMODE_PREFIX_ADDR); + X86EMU_halt_sys(emu); + } + if (emu->cur_mod == 1) + offset += (int8_t)fetch_byte_imm(emu); + else if (emu->cur_mod == 2) + offset += fetch_long_imm(emu); + return offset; + } else { + uint16_t offset; + + /* 16-bit addressing */ + switch (emu->cur_rl) { + case 0: + offset = emu->x86.R_BX + emu->x86.R_SI; + break; + case 1: + offset = emu->x86.R_BX + emu->x86.R_DI; + break; + case 2: + emu->x86.mode |= SYSMODE_SEG_DS_SS; + offset = emu->x86.R_BP + emu->x86.R_SI; + break; + case 3: + emu->x86.mode |= SYSMODE_SEG_DS_SS; + offset = emu->x86.R_BP + emu->x86.R_DI; + break; + case 4: + offset = emu->x86.R_SI; + break; + case 5: + offset = emu->x86.R_DI; + break; + case 6: + if (emu->cur_mod == 0) { + offset = fetch_word_imm(emu); + } else { + emu->x86.mode |= SYSMODE_SEG_DS_SS; + offset = emu->x86.R_BP; + } + break; + case 7: + offset = emu->x86.R_BX; + break; + default: + dbg("unexpected register %d\r\n", emu->cur_rl); + X86EMU_halt_sys(emu); + } + if (emu->cur_mod == 1) + offset += (int8_t)fetch_byte_imm(emu); + else if (emu->cur_mod == 2) + offset += fetch_word_imm(emu); + return offset; + } +} + +static uint8_t +decode_and_fetch_byte(struct X86EMU *emu) +{ + if (emu->cur_mod != 3) { + emu->cur_offset = decode_rl_address(emu); + return fetch_data_byte(emu, emu->cur_offset); + } else { + return *decode_rl_byte_register(emu); + } +} + +static uint16_t +decode_and_fetch_word_disp(struct X86EMU *emu, int16_t disp) +{ + if (emu->cur_mod != 3) { + /* TODO: A20 gate emulation */ + emu->cur_offset = decode_rl_address(emu) + disp; + if ((emu->x86.mode & SYSMODE_PREFIX_ADDR) == 0) + emu->cur_offset &= 0xffff; + return fetch_data_word(emu, emu->cur_offset); + } else { + return *decode_rl_word_register(emu); + } +} + +static uint32_t +decode_and_fetch_long_disp(struct X86EMU *emu, int16_t disp) +{ + if (emu->cur_mod != 3) { + /* TODO: A20 gate emulation */ + emu->cur_offset = decode_rl_address(emu) + disp; + if ((emu->x86.mode & SYSMODE_PREFIX_ADDR) == 0) + emu->cur_offset &= 0xffff; + return fetch_data_long(emu, emu->cur_offset); + } else { + return *decode_rl_long_register(emu); + } +} + +uint16_t +decode_and_fetch_word(struct X86EMU *emu) +{ + return decode_and_fetch_word_disp(emu, 0); +} + +uint32_t +decode_and_fetch_long(struct X86EMU *emu) +{ + return decode_and_fetch_long_disp(emu, 0); +} + +uint8_t +decode_and_fetch_byte_imm8(struct X86EMU *emu, uint8_t *imm) +{ + if (emu->cur_mod != 3) { + emu->cur_offset = decode_rl_address(emu); + *imm = fetch_byte_imm(emu); + return fetch_data_byte(emu, emu->cur_offset); + } else { + *imm = fetch_byte_imm(emu); + return *decode_rl_byte_register(emu); + } +} + +static uint16_t +decode_and_fetch_word_imm8(struct X86EMU *emu, uint8_t *imm) +{ + if (emu->cur_mod != 3) { + emu->cur_offset = decode_rl_address(emu); + *imm = fetch_byte_imm(emu); + return fetch_data_word(emu, emu->cur_offset); + } else { + *imm = fetch_byte_imm(emu); + return *decode_rl_word_register(emu); + } +} + +static uint32_t +decode_and_fetch_long_imm8(struct X86EMU *emu, uint8_t *imm) +{ + if (emu->cur_mod != 3) { + emu->cur_offset = decode_rl_address(emu); + *imm = fetch_byte_imm(emu); + return fetch_data_long(emu, emu->cur_offset); + } else { + *imm = fetch_byte_imm(emu); + return *decode_rl_long_register(emu); + } +} + +static void +write_back_byte(struct X86EMU *emu, uint8_t val) +{ + if (emu->cur_mod != 3) + store_data_byte(emu, emu->cur_offset, val); + else + *decode_rl_byte_register(emu) = val; +} + +static void +write_back_word(struct X86EMU *emu, uint16_t val) +{ + if (emu->cur_mod != 3) + store_data_word(emu, emu->cur_offset, val); + else + *decode_rl_word_register(emu) = val; +} + +static void +write_back_long(struct X86EMU *emu, uint32_t val) +{ + if (emu->cur_mod != 3) + store_data_long(emu, emu->cur_offset, val); + else + *decode_rl_long_register(emu) = val; +} + +static void +common_inc_word_long(struct X86EMU *emu, union X86EMU_register *reg) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + reg->I32_reg.e_reg = inc_long(emu, reg->I32_reg.e_reg); + else + reg->I16_reg.x_reg = inc_word(emu, reg->I16_reg.x_reg); +} + +static void +common_dec_word_long(struct X86EMU *emu, union X86EMU_register *reg) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + reg->I32_reg.e_reg = dec_long(emu, reg->I32_reg.e_reg); + else + reg->I16_reg.x_reg = dec_word(emu, reg->I16_reg.x_reg); +} + +static void +common_binop_byte_rm_r(struct X86EMU *emu, uint8_t (*binop)(struct X86EMU *, uint8_t, uint8_t)) +{ + uint32_t destoffset; + uint8_t *destreg, srcval; + uint8_t destval; + + fetch_decode_modrm(emu); + srcval = *decode_rh_byte_register(emu); + if (emu->cur_mod != 3) { + destoffset = decode_rl_address(emu); + destval = fetch_data_byte(emu, destoffset); + destval = (*binop)(emu, destval, srcval); + store_data_byte(emu, destoffset, destval); + } else { + destreg = decode_rl_byte_register(emu); + *destreg = (*binop)(emu, *destreg, srcval); + } +} + +static void +common_binop_ns_byte_rm_r(struct X86EMU *emu, void (*binop)(struct X86EMU *, uint8_t, uint8_t)) +{ + uint32_t destoffset; + uint8_t destval, srcval; + + fetch_decode_modrm(emu); + srcval = *decode_rh_byte_register(emu); + if (emu->cur_mod != 3) { + destoffset = decode_rl_address(emu); + destval = fetch_data_byte(emu, destoffset); + } else { + destval = *decode_rl_byte_register(emu); + } + (*binop)(emu, destval, srcval); +} + +static void +common_binop_word_rm_r(struct X86EMU *emu, uint16_t (*binop)(struct X86EMU *, uint16_t, uint16_t)) +{ + uint32_t destoffset; + uint16_t destval, *destreg, srcval; + + fetch_decode_modrm(emu); + srcval = *decode_rh_word_register(emu); + if (emu->cur_mod != 3) { + destoffset = decode_rl_address(emu); + destval = fetch_data_word(emu, destoffset); + destval = (*binop)(emu, destval, srcval); + store_data_word(emu, destoffset, destval); + } else { + destreg = decode_rl_word_register(emu); + *destreg = (*binop)(emu, *destreg, srcval); + } +} + +static void +common_binop_byte_r_rm(struct X86EMU *emu, uint8_t (*binop)(struct X86EMU *, uint8_t, uint8_t)) +{ + uint8_t *destreg, srcval; + uint32_t srcoffset; + + fetch_decode_modrm(emu); + destreg = decode_rh_byte_register(emu); + if (emu->cur_mod != 3) { + srcoffset = decode_rl_address(emu); + srcval = fetch_data_byte(emu, srcoffset); + } else { + srcval = *decode_rl_byte_register(emu); + } + *destreg = (*binop)(emu, *destreg, srcval); +} + +static void +common_binop_long_rm_r(struct X86EMU *emu, uint32_t (*binop)(struct X86EMU *, uint32_t, uint32_t)) +{ + uint32_t destoffset; + uint32_t destval, *destreg, srcval; + + fetch_decode_modrm(emu); + srcval = *decode_rh_long_register(emu); + if (emu->cur_mod != 3) { + destoffset = decode_rl_address(emu); + destval = fetch_data_long(emu, destoffset); + destval = (*binop)(emu, destval, srcval); + store_data_long(emu, destoffset, destval); + } else { + destreg = decode_rl_long_register(emu); + *destreg = (*binop)(emu, *destreg, srcval); + } +} + +static void +common_binop_word_long_rm_r(struct X86EMU *emu, + uint16_t (*binop16)(struct X86EMU *, uint16_t, uint16_t), uint32_t (*binop32)(struct X86EMU *, uint32_t, uint32_t)) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + common_binop_long_rm_r(emu, binop32); + else + common_binop_word_rm_r(emu, binop16); +} + +static void +common_binop_ns_word_rm_r(struct X86EMU *emu, void (*binop)(struct X86EMU *, uint16_t, uint16_t)) +{ + uint32_t destoffset; + uint16_t destval, srcval; + + fetch_decode_modrm(emu); + srcval = *decode_rh_word_register(emu); + if (emu->cur_mod != 3) { + destoffset = decode_rl_address(emu); + destval = fetch_data_word(emu, destoffset); + } else { + destval = *decode_rl_word_register(emu); + } + (*binop)(emu, destval, srcval); +} + + +static void +common_binop_ns_long_rm_r(struct X86EMU *emu, void (*binop)(struct X86EMU *, uint32_t, uint32_t)) +{ + uint32_t destoffset; + uint32_t destval, srcval; + + fetch_decode_modrm(emu); + srcval = *decode_rh_long_register(emu); + if (emu->cur_mod != 3) { + destoffset = decode_rl_address(emu); + destval = fetch_data_long(emu, destoffset); + } else { + destval = *decode_rl_long_register(emu); + } + (*binop)(emu, destval, srcval); +} + +static void +common_binop_ns_word_long_rm_r(struct X86EMU *emu, + void (*binop16)(struct X86EMU *, uint16_t, uint16_t), void (*binop32)(struct X86EMU *, uint32_t, uint32_t)) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + common_binop_ns_long_rm_r(emu, binop32); + else + common_binop_ns_word_rm_r(emu, binop16); +} + +static void +common_binop_long_r_rm(struct X86EMU *emu, uint32_t (*binop)(struct X86EMU *, uint32_t, uint32_t)) +{ + uint32_t srcoffset; + uint32_t *destreg, srcval; + + fetch_decode_modrm(emu); + destreg = decode_rh_long_register(emu); + if (emu->cur_mod != 3) { + srcoffset = decode_rl_address(emu); + srcval = fetch_data_long(emu, srcoffset); + } else { + srcval = *decode_rl_long_register(emu); + } + *destreg = (*binop)(emu, *destreg, srcval); +} + +static void +common_binop_word_r_rm(struct X86EMU *emu, uint16_t (*binop)(struct X86EMU *, uint16_t, uint16_t)) +{ + uint32_t srcoffset; + uint16_t *destreg, srcval; + + fetch_decode_modrm(emu); + destreg = decode_rh_word_register(emu); + if (emu->cur_mod != 3) { + srcoffset = decode_rl_address(emu); + srcval = fetch_data_word(emu, srcoffset); + } else { + srcval = *decode_rl_word_register(emu); + } + *destreg = (*binop)(emu, *destreg, srcval); +} + +static void +common_binop_word_long_r_rm(struct X86EMU *emu, + uint16_t (*binop16)(struct X86EMU *, uint16_t, uint16_t), uint32_t (*binop32)(struct X86EMU *, uint32_t, uint32_t)) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + common_binop_long_r_rm(emu, binop32); + else + common_binop_word_r_rm(emu, binop16); +} + +static void +common_binop_byte_imm(struct X86EMU *emu, uint8_t (*binop)(struct X86EMU *, uint8_t, uint8_t)) +{ + uint8_t srcval; + + srcval = fetch_byte_imm(emu); + emu->x86.R_AL = (*binop)(emu, emu->x86.R_AL, srcval); +} + +static void +common_binop_word_long_imm(struct X86EMU *emu, + uint16_t (*binop16)(struct X86EMU *, uint16_t, uint16_t), uint32_t (*binop32)(struct X86EMU *, uint32_t, uint32_t)) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + uint32_t srcval; + + srcval = fetch_long_imm(emu); + emu->x86.R_EAX = (*binop32)(emu, emu->x86.R_EAX, srcval); + } else { + uint16_t srcval; + + srcval = fetch_word_imm(emu); + emu->x86.R_AX = (*binop16)(emu, emu->x86.R_AX, srcval); + } +} + +static void +common_push_word_long(struct X86EMU *emu, union X86EMU_register *reg) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + push_long(emu, reg->I32_reg.e_reg); + else + push_word(emu, reg->I16_reg.x_reg); +} + +static void +common_pop_word_long(struct X86EMU *emu, union X86EMU_register *reg) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + reg->I32_reg.e_reg = pop_long(emu); + else + reg->I16_reg.x_reg = pop_word(emu); +} + +static void +common_imul_long_IMM(struct X86EMU *emu, bool byte_imm) +{ + uint32_t srcoffset; + uint32_t *destreg, srcval; + int32_t imm; + uint64_t res; + + fetch_decode_modrm(emu); + destreg = decode_rh_long_register(emu); + if (emu->cur_mod != 3) { + srcoffset = decode_rl_address(emu); + srcval = fetch_data_long(emu, srcoffset); + } else { + srcval = *decode_rl_long_register(emu); + } + + if (byte_imm) + imm = (int8_t)fetch_byte_imm(emu); + else + imm = fetch_long_imm(emu); + res = (int32_t)srcval * imm; + + if (res > 0xffffffff) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (uint32_t)res; +} + +static void +common_imul_word_IMM(struct X86EMU *emu, bool byte_imm) +{ + uint32_t srcoffset; + uint16_t *destreg, srcval; + int16_t imm; + uint32_t res; + + fetch_decode_modrm(emu); + destreg = decode_rh_word_register(emu); + if (emu->cur_mod != 3) { + srcoffset = decode_rl_address(emu); + srcval = fetch_data_word(emu, srcoffset); + } else { + srcval = *decode_rl_word_register(emu); + } + + if (byte_imm) + imm = (int8_t)fetch_byte_imm(emu); + else + imm = fetch_word_imm(emu); + res = (int16_t)srcval * imm; + + if (res > 0xffff) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (uint16_t) res; +} + +static void +common_imul_imm(struct X86EMU *emu, bool byte_imm) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + common_imul_long_IMM(emu, byte_imm); + else + common_imul_word_IMM(emu, byte_imm); +} + +static void +common_jmp_near(struct X86EMU *emu, bool cond) +{ + int8_t offset; + uint16_t target; + + offset = (int8_t) fetch_byte_imm(emu); + target = (uint16_t) (emu->x86.R_IP + (int16_t) offset); + if (cond) + emu->x86.R_IP = target; +} + +static void +common_load_far_pointer(struct X86EMU *emu, uint16_t *seg) +{ + uint16_t *dstreg; + uint32_t srcoffset; + + fetch_decode_modrm(emu); + if (emu->cur_mod == 3) + { + dbg("unexpected mode %d\r\n", emu->cur_mod); + X86EMU_halt_sys(emu); + } + + dstreg = decode_rh_word_register(emu); + srcoffset = decode_rl_address(emu); + *dstreg = fetch_data_word(emu, srcoffset); + *seg = fetch_data_word(emu, srcoffset + 2); +} + +/*----------------------------- Implementation ----------------------------*/ +/**************************************************************************** +REMARKS: +Handles opcode 0x3a +****************************************************************************/ +static void +x86emuOp_cmp_byte_R_RM(struct X86EMU *emu) +{ + uint8_t *destreg, srcval; + + fetch_decode_modrm(emu); + destreg = decode_rh_byte_register(emu); + srcval = decode_and_fetch_byte(emu); + cmp_byte(emu, *destreg, srcval); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x3b +****************************************************************************/ +static void +x86emuOp32_cmp_word_R_RM(struct X86EMU *emu) +{ + uint32_t srcval, *destreg; + + fetch_decode_modrm(emu); + destreg = decode_rh_long_register(emu); + srcval = decode_and_fetch_long(emu); + cmp_long(emu, *destreg, srcval); +} + +static void +x86emuOp16_cmp_word_R_RM(struct X86EMU *emu) +{ + uint16_t srcval, *destreg; + + fetch_decode_modrm(emu); + destreg = decode_rh_word_register(emu); + srcval = decode_and_fetch_word(emu); + cmp_word(emu, *destreg, srcval); +} + +static void +x86emuOp_cmp_word_R_RM(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + x86emuOp32_cmp_word_R_RM(emu); + else + x86emuOp16_cmp_word_R_RM(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x3c +****************************************************************************/ +static void +x86emuOp_cmp_byte_AL_IMM(struct X86EMU *emu) +{ + uint8_t srcval; + + srcval = fetch_byte_imm(emu); + cmp_byte(emu, emu->x86.R_AL, srcval); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x3d +****************************************************************************/ +static void +x86emuOp32_cmp_word_AX_IMM(struct X86EMU *emu) +{ + uint32_t srcval; + + srcval = fetch_long_imm(emu); + cmp_long(emu, emu->x86.R_EAX, srcval); +} + +static void +x86emuOp16_cmp_word_AX_IMM(struct X86EMU *emu) +{ + uint16_t srcval; + + srcval = fetch_word_imm(emu); + cmp_word(emu, emu->x86.R_AX, srcval); +} + +static void +x86emuOp_cmp_word_AX_IMM(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + x86emuOp32_cmp_word_AX_IMM(emu); + else + x86emuOp16_cmp_word_AX_IMM(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x60 +****************************************************************************/ +static void +x86emuOp_push_all(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + uint32_t old_sp = emu->x86.R_ESP; + + push_long(emu, emu->x86.R_EAX); + push_long(emu, emu->x86.R_ECX); + push_long(emu, emu->x86.R_EDX); + push_long(emu, emu->x86.R_EBX); + push_long(emu, old_sp); + push_long(emu, emu->x86.R_EBP); + push_long(emu, emu->x86.R_ESI); + push_long(emu, emu->x86.R_EDI); + } else { + uint16_t old_sp = emu->x86.R_SP; + + push_word(emu, emu->x86.R_AX); + push_word(emu, emu->x86.R_CX); + push_word(emu, emu->x86.R_DX); + push_word(emu, emu->x86.R_BX); + push_word(emu, old_sp); + push_word(emu, emu->x86.R_BP); + push_word(emu, emu->x86.R_SI); + push_word(emu, emu->x86.R_DI); + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0x61 +****************************************************************************/ +static void +x86emuOp_pop_all(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + emu->x86.R_EDI = pop_long(emu); + emu->x86.R_ESI = pop_long(emu); + emu->x86.R_EBP = pop_long(emu); + emu->x86.R_ESP += 4; /* skip ESP */ + emu->x86.R_EBX = pop_long(emu); + emu->x86.R_EDX = pop_long(emu); + emu->x86.R_ECX = pop_long(emu); + emu->x86.R_EAX = pop_long(emu); + } else { + emu->x86.R_DI = pop_word(emu); + emu->x86.R_SI = pop_word(emu); + emu->x86.R_BP = pop_word(emu); + emu->x86.R_SP += 2;/* skip SP */ + emu->x86.R_BX = pop_word(emu); + emu->x86.R_DX = pop_word(emu); + emu->x86.R_CX = pop_word(emu); + emu->x86.R_AX = pop_word(emu); + } +} +/*opcode 0x62 ILLEGAL OP, calls x86emuOp_illegal_op() */ +/*opcode 0x63 ILLEGAL OP, calls x86emuOp_illegal_op() */ + +/**************************************************************************** +REMARKS: +Handles opcode 0x68 +****************************************************************************/ +static void +x86emuOp_push_word_IMM(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + uint32_t imm; + + imm = fetch_long_imm(emu); + push_long(emu, imm); + } else { + uint16_t imm; + + imm = fetch_word_imm(emu); + push_word(emu, imm); + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0x6a +****************************************************************************/ +static void +x86emuOp_push_byte_IMM(struct X86EMU *emu) +{ + int16_t imm; + + imm = (int8_t) fetch_byte_imm(emu); + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + push_long(emu, (int32_t) imm); + } else { + push_word(emu, imm); + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0x6c +****************************************************************************/ +/**************************************************************************** +REMARKS: +Handles opcode 0x6d +****************************************************************************/ +static void +x86emuOp_ins_word(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + ins(emu, 4); + } else { + ins(emu, 2); + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0x6f +****************************************************************************/ +static void +x86emuOp_outs_word(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + outs(emu, 4); + } else { + outs(emu, 2); + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0x7c +****************************************************************************/ +static void +x86emuOp_jump_near_L(struct X86EMU *emu) +{ + bool sf, of; + + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + + common_jmp_near(emu, sf != of); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x7d +****************************************************************************/ +static void +x86emuOp_jump_near_NL(struct X86EMU *emu) +{ + bool sf, of; + + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + + common_jmp_near(emu, sf == of); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x7e +****************************************************************************/ +static void +x86emuOp_jump_near_LE(struct X86EMU *emu) +{ + bool sf, of; + + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + + common_jmp_near(emu, sf != of || ACCESS_FLAG(F_ZF)); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x7f +****************************************************************************/ +static void +x86emuOp_jump_near_NLE(struct X86EMU *emu) +{ + bool sf, of; + + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + + common_jmp_near(emu, sf == of && !ACCESS_FLAG(F_ZF)); +} + +static +uint8_t(*const opc80_byte_operation[]) (struct X86EMU *, uint8_t d, uint8_t s) = +{ + add_byte, /* 00 */ + or_byte, /* 01 */ + adc_byte, /* 02 */ + sbb_byte, /* 03 */ + and_byte, /* 04 */ + sub_byte, /* 05 */ + xor_byte, /* 06 */ + cmp_byte, /* 07 */ + }; +/**************************************************************************** +REMARKS: +Handles opcode 0x80 +****************************************************************************/ +static void +x86emuOp_opc80_byte_RM_IMM(struct X86EMU *emu) +{ + uint8_t imm, destval; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction + */ + fetch_decode_modrm(emu); + destval = decode_and_fetch_byte(emu); + imm = fetch_byte_imm(emu); + destval = (*opc80_byte_operation[emu->cur_rh]) (emu, destval, imm); + if (emu->cur_rh != 7) + write_back_byte(emu, destval); +} + +static +uint16_t(* const opc81_word_operation[]) (struct X86EMU *, uint16_t d, uint16_t s) = +{ + add_word, /* 00 */ + or_word, /* 01 */ + adc_word, /* 02 */ + sbb_word, /* 03 */ + and_word, /* 04 */ + sub_word, /* 05 */ + xor_word, /* 06 */ + cmp_word, /* 07 */ + }; + +static +uint32_t(* const opc81_long_operation[]) (struct X86EMU *, uint32_t d, uint32_t s) = +{ + add_long, /* 00 */ + or_long, /* 01 */ + adc_long, /* 02 */ + sbb_long, /* 03 */ + and_long, /* 04 */ + sub_long, /* 05 */ + xor_long, /* 06 */ + cmp_long, /* 07 */ + }; +/**************************************************************************** +REMARKS: +Handles opcode 0x81 +****************************************************************************/ +static void +x86emuOp32_opc81_word_RM_IMM(struct X86EMU *emu) +{ + uint32_t destval, imm; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction + */ + fetch_decode_modrm(emu); + destval = decode_and_fetch_long(emu); + imm = fetch_long_imm(emu); + destval = (*opc81_long_operation[emu->cur_rh]) (emu, destval, imm); + if (emu->cur_rh != 7) + write_back_long(emu, destval); +} + +static void +x86emuOp16_opc81_word_RM_IMM(struct X86EMU *emu) +{ + uint16_t destval, imm; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction + */ + fetch_decode_modrm(emu); + destval = decode_and_fetch_word(emu); + imm = fetch_word_imm(emu); + destval = (*opc81_word_operation[emu->cur_rh]) (emu, destval, imm); + if (emu->cur_rh != 7) + write_back_word(emu, destval); +} + +static void +x86emuOp_opc81_word_RM_IMM(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + x86emuOp32_opc81_word_RM_IMM(emu); + else + x86emuOp16_opc81_word_RM_IMM(emu); +} + +static +uint8_t(* const opc82_byte_operation[]) (struct X86EMU *, uint8_t s, uint8_t d) = +{ + add_byte, /* 00 */ + or_byte, /* 01 *//* YYY UNUSED ???? */ + adc_byte, /* 02 */ + sbb_byte, /* 03 */ + and_byte, /* 04 *//* YYY UNUSED ???? */ + sub_byte, /* 05 */ + xor_byte, /* 06 *//* YYY UNUSED ???? */ + cmp_byte, /* 07 */ + }; +/**************************************************************************** +REMARKS: +Handles opcode 0x82 +****************************************************************************/ +static void +x86emuOp_opc82_byte_RM_IMM(struct X86EMU *emu) +{ + uint8_t imm, destval; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction Similar to opcode 81, except that + * the immediate byte is sign extended to a word length. + */ + fetch_decode_modrm(emu); + destval = decode_and_fetch_byte(emu); + imm = fetch_byte_imm(emu); + destval = (*opc82_byte_operation[emu->cur_rh]) (emu, destval, imm); + if (emu->cur_rh != 7) + write_back_byte(emu, destval); +} + +static +uint16_t(* const opc83_word_operation[]) (struct X86EMU *, uint16_t s, uint16_t d) = +{ + add_word, /* 00 */ + or_word, /* 01 *//* YYY UNUSED ???? */ + adc_word, /* 02 */ + sbb_word, /* 03 */ + and_word, /* 04 *//* YYY UNUSED ???? */ + sub_word, /* 05 */ + xor_word, /* 06 *//* YYY UNUSED ???? */ + cmp_word, /* 07 */ + }; + +static +uint32_t(* const opc83_long_operation[]) (struct X86EMU *, uint32_t s, uint32_t d) = +{ + add_long, /* 00 */ + or_long, /* 01 *//* YYY UNUSED ???? */ + adc_long, /* 02 */ + sbb_long, /* 03 */ + and_long, /* 04 *//* YYY UNUSED ???? */ + sub_long, /* 05 */ + xor_long, /* 06 *//* YYY UNUSED ???? */ + cmp_long, /* 07 */ + }; +/**************************************************************************** +REMARKS: +Handles opcode 0x83 +****************************************************************************/ +static void +x86emuOp32_opc83_word_RM_IMM(struct X86EMU *emu) +{ + uint32_t destval, imm; + + fetch_decode_modrm(emu); + destval = decode_and_fetch_long(emu); + imm = (int8_t) fetch_byte_imm(emu); + destval = (*opc83_long_operation[emu->cur_rh]) (emu, destval, imm); + if (emu->cur_rh != 7) + write_back_long(emu, destval); +} + +static void +x86emuOp16_opc83_word_RM_IMM(struct X86EMU *emu) +{ + uint16_t destval, imm; + + fetch_decode_modrm(emu); + destval = decode_and_fetch_word(emu); + imm = (int8_t) fetch_byte_imm(emu); + destval = (*opc83_word_operation[emu->cur_rh]) (emu, destval, imm); + if (emu->cur_rh != 7) + write_back_word(emu, destval); +} + +static void +x86emuOp_opc83_word_RM_IMM(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + x86emuOp32_opc83_word_RM_IMM(emu); + else + x86emuOp16_opc83_word_RM_IMM(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x86 +****************************************************************************/ +static void +x86emuOp_xchg_byte_RM_R(struct X86EMU *emu) +{ + uint8_t *srcreg, destval, tmp; + + fetch_decode_modrm(emu); + destval = decode_and_fetch_byte(emu); + srcreg = decode_rh_byte_register(emu); + tmp = destval; + destval = *srcreg; + *srcreg = tmp; + write_back_byte(emu, destval); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x87 +****************************************************************************/ +static void +x86emuOp32_xchg_word_RM_R(struct X86EMU *emu) +{ + uint32_t *srcreg, destval, tmp; + + fetch_decode_modrm(emu); + destval = decode_and_fetch_long(emu); + srcreg = decode_rh_long_register(emu); + tmp = destval; + destval = *srcreg; + *srcreg = tmp; + write_back_long(emu, destval); +} + +static void +x86emuOp16_xchg_word_RM_R(struct X86EMU *emu) +{ + uint16_t *srcreg, destval, tmp; + + fetch_decode_modrm(emu); + destval = decode_and_fetch_word(emu); + srcreg = decode_rh_word_register(emu); + tmp = destval; + destval = *srcreg; + *srcreg = tmp; + write_back_word(emu, destval); +} + +static void +x86emuOp_xchg_word_RM_R(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + x86emuOp32_xchg_word_RM_R(emu); + else + x86emuOp16_xchg_word_RM_R(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x88 +****************************************************************************/ +static void +x86emuOp_mov_byte_RM_R(struct X86EMU *emu) +{ + uint8_t *destreg, *srcreg; + uint32_t destoffset; + + fetch_decode_modrm(emu); + srcreg = decode_rh_byte_register(emu); + if (emu->cur_mod != 3) { + destoffset = decode_rl_address(emu); + store_data_byte(emu, destoffset, *srcreg); + } else { + destreg = decode_rl_byte_register(emu); + *destreg = *srcreg; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0x89 +****************************************************************************/ +static void +x86emuOp32_mov_word_RM_R(struct X86EMU *emu) +{ + uint32_t destoffset; + uint32_t *destreg, srcval; + + fetch_decode_modrm(emu); + srcval = *decode_rh_long_register(emu); + if (emu->cur_mod != 3) { + destoffset = decode_rl_address(emu); + store_data_long(emu, destoffset, srcval); + } else { + destreg = decode_rl_long_register(emu); + *destreg = srcval; + } +} + +static void +x86emuOp16_mov_word_RM_R(struct X86EMU *emu) +{ + uint32_t destoffset; + uint16_t *destreg, srcval; + + fetch_decode_modrm(emu); + srcval = *decode_rh_word_register(emu); + if (emu->cur_mod != 3) { + destoffset = decode_rl_address(emu); + store_data_word(emu, destoffset, srcval); + } else { + destreg = decode_rl_word_register(emu); + *destreg = srcval; + } +} + +static void +x86emuOp_mov_word_RM_R(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + x86emuOp32_mov_word_RM_R(emu); + else + x86emuOp16_mov_word_RM_R(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x8a +****************************************************************************/ +static void +x86emuOp_mov_byte_R_RM(struct X86EMU *emu) +{ + uint8_t *destreg; + + fetch_decode_modrm(emu); + destreg = decode_rh_byte_register(emu); + *destreg = decode_and_fetch_byte(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x8b +****************************************************************************/ +static void +x86emuOp_mov_word_R_RM(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + uint32_t *destreg; + + fetch_decode_modrm(emu); + destreg = decode_rh_long_register(emu); + *destreg = decode_and_fetch_long(emu); + } else { + uint16_t *destreg; + + fetch_decode_modrm(emu); + destreg = decode_rh_word_register(emu); + *destreg = decode_and_fetch_word(emu); + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0x8c +****************************************************************************/ +static void +x86emuOp_mov_word_RM_SR(struct X86EMU *emu) +{ + uint16_t *destreg, srcval; + uint32_t destoffset; + + fetch_decode_modrm(emu); + srcval = *decode_rh_seg_register(emu); + if (emu->cur_mod != 3) { + destoffset = decode_rl_address(emu); + store_data_word(emu, destoffset, srcval); + } else { + destreg = decode_rl_word_register(emu); + *destreg = srcval; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0x8d +****************************************************************************/ +static void +x86emuOp_lea_word_R_M(struct X86EMU *emu) +{ + uint32_t destoffset; + + fetch_decode_modrm(emu); + if (emu->cur_mod == 3) + { + dbg("unexpected mode %d\r\n", emu->cur_mod); + X86EMU_halt_sys(emu); + } + + destoffset = decode_rl_address(emu); + if (emu->x86.mode & SYSMODE_PREFIX_ADDR) { + uint32_t *srcreg; + + srcreg = decode_rh_long_register(emu); + *srcreg = (uint32_t) destoffset; + } else { + uint16_t *srcreg; + + srcreg = decode_rh_word_register(emu); + *srcreg = (uint16_t) destoffset; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0x8e +****************************************************************************/ +static void +x86emuOp_mov_word_SR_RM(struct X86EMU *emu) +{ + uint16_t *destreg; + + fetch_decode_modrm(emu); + destreg = decode_rh_seg_register(emu); + *destreg = decode_and_fetch_word(emu); + /* + * Clean up, and reset all the R_xSP pointers to the correct + * locations. This is about 3x too much overhead (doing all the + * segreg ptrs when only one is needed, but this instruction + * *cannot* be that common, and this isn't too much work anyway. + */ +} +/**************************************************************************** +REMARKS: +Handles opcode 0x8f +****************************************************************************/ +static void +x86emuOp32_pop_RM(struct X86EMU *emu) +{ + uint32_t destoffset; + uint32_t destval, *destreg; + + fetch_decode_modrm(emu); + if (emu->cur_mod != 3) { + destoffset = decode_rl_address(emu); + destval = pop_long(emu); + store_data_long(emu, destoffset, destval); + } else { + destreg = decode_rl_long_register(emu); + *destreg = pop_long(emu); + } +} + +static void +x86emuOp16_pop_RM(struct X86EMU *emu) +{ + uint32_t destoffset; + uint16_t destval, *destreg; + + fetch_decode_modrm(emu); + if (emu->cur_mod != 3) { + destoffset = decode_rl_address(emu); + destval = pop_word(emu); + store_data_word(emu, destoffset, destval); + } else { + destreg = decode_rl_word_register(emu); + *destreg = pop_word(emu); + } +} + +static void +x86emuOp_pop_RM(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + x86emuOp32_pop_RM(emu); + else + x86emuOp16_pop_RM(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x91 +****************************************************************************/ +static void +x86emuOp_xchg_word_AX_CX(struct X86EMU *emu) +{ + uint32_t tmp; + + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + tmp = emu->x86.R_EAX; + emu->x86.R_EAX = emu->x86.R_ECX; + emu->x86.R_ECX = tmp; + } else { + tmp = emu->x86.R_AX; + emu->x86.R_AX = emu->x86.R_CX; + emu->x86.R_CX = (uint16_t) tmp; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0x92 +****************************************************************************/ +static void +x86emuOp_xchg_word_AX_DX(struct X86EMU *emu) +{ + uint32_t tmp; + + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + tmp = emu->x86.R_EAX; + emu->x86.R_EAX = emu->x86.R_EDX; + emu->x86.R_EDX = tmp; + } else { + tmp = emu->x86.R_AX; + emu->x86.R_AX = emu->x86.R_DX; + emu->x86.R_DX = (uint16_t) tmp; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0x93 +****************************************************************************/ +static void +x86emuOp_xchg_word_AX_BX(struct X86EMU *emu) +{ + uint32_t tmp; + + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + tmp = emu->x86.R_EAX; + emu->x86.R_EAX = emu->x86.R_EBX; + emu->x86.R_EBX = tmp; + } else { + tmp = emu->x86.R_AX; + emu->x86.R_AX = emu->x86.R_BX; + emu->x86.R_BX = (uint16_t) tmp; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0x94 +****************************************************************************/ +static void +x86emuOp_xchg_word_AX_SP(struct X86EMU *emu) +{ + uint32_t tmp; + + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + tmp = emu->x86.R_EAX; + emu->x86.R_EAX = emu->x86.R_ESP; + emu->x86.R_ESP = tmp; + } else { + tmp = emu->x86.R_AX; + emu->x86.R_AX = emu->x86.R_SP; + emu->x86.R_SP = (uint16_t) tmp; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0x95 +****************************************************************************/ +static void +x86emuOp_xchg_word_AX_BP(struct X86EMU *emu) +{ + uint32_t tmp; + + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + tmp = emu->x86.R_EAX; + emu->x86.R_EAX = emu->x86.R_EBP; + emu->x86.R_EBP = tmp; + } else { + tmp = emu->x86.R_AX; + emu->x86.R_AX = emu->x86.R_BP; + emu->x86.R_BP = (uint16_t) tmp; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0x96 +****************************************************************************/ +static void +x86emuOp_xchg_word_AX_SI(struct X86EMU *emu) +{ + uint32_t tmp; + + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + tmp = emu->x86.R_EAX; + emu->x86.R_EAX = emu->x86.R_ESI; + emu->x86.R_ESI = tmp; + } else { + tmp = emu->x86.R_AX; + emu->x86.R_AX = emu->x86.R_SI; + emu->x86.R_SI = (uint16_t) tmp; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0x97 +****************************************************************************/ +static void +x86emuOp_xchg_word_AX_DI(struct X86EMU *emu) +{ + uint32_t tmp; + + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + tmp = emu->x86.R_EAX; + emu->x86.R_EAX = emu->x86.R_EDI; + emu->x86.R_EDI = tmp; + } else { + tmp = emu->x86.R_AX; + emu->x86.R_AX = emu->x86.R_DI; + emu->x86.R_DI = (uint16_t) tmp; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0x98 +****************************************************************************/ +static void +x86emuOp_cbw(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + if (emu->x86.R_AX & 0x8000) { + emu->x86.R_EAX |= 0xffff0000; + } else { + emu->x86.R_EAX &= 0x0000ffff; + } + } else { + if (emu->x86.R_AL & 0x80) { + emu->x86.R_AH = 0xff; + } else { + emu->x86.R_AH = 0x0; + } + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0x99 +****************************************************************************/ +static void +x86emuOp_cwd(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + if (emu->x86.R_EAX & 0x80000000) { + emu->x86.R_EDX = 0xffffffff; + } else { + emu->x86.R_EDX = 0x0; + } + } else { + if (emu->x86.R_AX & 0x8000) { + emu->x86.R_DX = 0xffff; + } else { + emu->x86.R_DX = 0x0; + } + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0x9a +****************************************************************************/ +static void +x86emuOp_call_far_IMM(struct X86EMU *emu) +{ + uint16_t farseg, faroff; + + faroff = fetch_word_imm(emu); + farseg = fetch_word_imm(emu); + /* XXX + * + * Hooked interrupt vectors calling into our "BIOS" will cause problems + * unless all intersegment stuff is checked for BIOS access. Check + * needed here. For moment, let it alone. */ + push_word(emu, emu->x86.R_CS); + emu->x86.R_CS = farseg; + push_word(emu, emu->x86.R_IP); + emu->x86.R_IP = faroff; +} +/**************************************************************************** +REMARKS: +Handles opcode 0x9c +****************************************************************************/ +static void +x86emuOp_pushf_word(struct X86EMU *emu) +{ + uint32_t flags; + + /* clear out *all* bits not representing flags, and turn on real bits */ + flags = (emu->x86.R_EFLG & F_MSK) | F_ALWAYS_ON; + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + push_long(emu, flags); + } else { + push_word(emu, (uint16_t) flags); + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0x9d +****************************************************************************/ +static void +x86emuOp_popf_word(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + emu->x86.R_EFLG = pop_long(emu); + } else { + emu->x86.R_FLG = pop_word(emu); + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0x9e +****************************************************************************/ +static void +x86emuOp_sahf(struct X86EMU *emu) +{ + /* clear the lower bits of the flag register */ + emu->x86.R_FLG &= 0xffffff00; + /* or in the AH register into the flags register */ + emu->x86.R_FLG |= emu->x86.R_AH; +} +/**************************************************************************** +REMARKS: +Handles opcode 0x9f +****************************************************************************/ +static void +x86emuOp_lahf(struct X86EMU *emu) +{ + emu->x86.R_AH = (uint8_t) (emu->x86.R_FLG & 0xff); + /* undocumented TC++ behavior??? Nope. It's documented, but you have + * too look real hard to notice it. */ + emu->x86.R_AH |= 0x2; +} +/**************************************************************************** +REMARKS: +Handles opcode 0xa0 +****************************************************************************/ +static void +x86emuOp_mov_AL_M_IMM(struct X86EMU *emu) +{ + uint16_t offset; + + offset = fetch_word_imm(emu); + emu->x86.R_AL = fetch_data_byte(emu, offset); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xa1 +****************************************************************************/ +static void +x86emuOp_mov_AX_M_IMM(struct X86EMU *emu) +{ + uint16_t offset; + + offset = fetch_word_imm(emu); + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + emu->x86.R_EAX = fetch_data_long(emu, offset); + } else { + emu->x86.R_AX = fetch_data_word(emu, offset); + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xa2 +****************************************************************************/ +static void +x86emuOp_mov_M_AL_IMM(struct X86EMU *emu) +{ + uint16_t offset; + + offset = fetch_word_imm(emu); + store_data_byte(emu, offset, emu->x86.R_AL); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xa3 +****************************************************************************/ +static void +x86emuOp_mov_M_AX_IMM(struct X86EMU *emu) +{ + uint16_t offset; + + offset = fetch_word_imm(emu); + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + store_data_long(emu, offset, emu->x86.R_EAX); + } else { + store_data_word(emu, offset, emu->x86.R_AX); + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xa4 +****************************************************************************/ +static void +x86emuOp_movs_byte(struct X86EMU *emu) +{ + uint8_t val; + uint32_t count; + int inc; + + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + count = 1; + if (emu->x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = emu->x86.R_CX; + emu->x86.R_CX = 0; + emu->x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + val = fetch_data_byte(emu, emu->x86.R_SI); + store_byte(emu, emu->x86.R_ES, emu->x86.R_DI, val); + emu->x86.R_SI += inc; + emu->x86.R_DI += inc; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xa5 +****************************************************************************/ +static void +x86emuOp_movs_word(struct X86EMU *emu) +{ + uint32_t val; + int inc; + uint32_t count; + + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + inc = 4; + else + inc = 2; + + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -inc; + + count = 1; + if (emu->x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = emu->x86.R_CX; + emu->x86.R_CX = 0; + emu->x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long(emu, emu->x86.R_SI); + store_long(emu, emu->x86.R_ES, emu->x86.R_DI, val); + } else { + val = fetch_data_word(emu, emu->x86.R_SI); + store_word(emu, emu->x86.R_ES, emu->x86.R_DI, (uint16_t) val); + } + emu->x86.R_SI += inc; + emu->x86.R_DI += inc; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xa6 +****************************************************************************/ +static void +x86emuOp_cmps_byte(struct X86EMU *emu) +{ + int8_t val1, val2; + int inc; + + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + + if (emu->x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (emu->x86.R_CX != 0) { + val1 = fetch_data_byte(emu, emu->x86.R_SI); + val2 = fetch_byte(emu, emu->x86.R_ES, emu->x86.R_DI); + cmp_byte(emu, val1, val2); + emu->x86.R_CX -= 1; + emu->x86.R_SI += inc; + emu->x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + emu->x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (emu->x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (emu->x86.R_CX != 0) { + val1 = fetch_data_byte(emu, emu->x86.R_SI); + val2 = fetch_byte(emu, emu->x86.R_ES, emu->x86.R_DI); + cmp_byte(emu, val1, val2); + emu->x86.R_CX -= 1; + emu->x86.R_SI += inc; + emu->x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + emu->x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + val1 = fetch_data_byte(emu, emu->x86.R_SI); + val2 = fetch_byte(emu, emu->x86.R_ES, emu->x86.R_DI); + cmp_byte(emu, val1, val2); + emu->x86.R_SI += inc; + emu->x86.R_DI += inc; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xa7 +****************************************************************************/ +static void +x86emuOp_cmps_word(struct X86EMU *emu) +{ + uint32_t val1, val2; + int inc; + + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + if (emu->x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (emu->x86.R_CX != 0) { + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(emu, emu->x86.R_SI); + val2 = fetch_long(emu, emu->x86.R_ES, emu->x86.R_DI); + cmp_long(emu, val1, val2); + } else { + val1 = fetch_data_word(emu, emu->x86.R_SI); + val2 = fetch_word(emu, emu->x86.R_ES, emu->x86.R_DI); + cmp_word(emu, (uint16_t) val1, (uint16_t) val2); + } + emu->x86.R_CX -= 1; + emu->x86.R_SI += inc; + emu->x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + emu->x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (emu->x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (emu->x86.R_CX != 0) { + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(emu, emu->x86.R_SI); + val2 = fetch_long(emu, emu->x86.R_ES, emu->x86.R_DI); + cmp_long(emu, val1, val2); + } else { + val1 = fetch_data_word(emu, emu->x86.R_SI); + val2 = fetch_word(emu, emu->x86.R_ES, emu->x86.R_DI); + cmp_word(emu, (uint16_t) val1, (uint16_t) val2); + } + emu->x86.R_CX -= 1; + emu->x86.R_SI += inc; + emu->x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + emu->x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(emu, emu->x86.R_SI); + val2 = fetch_long(emu, emu->x86.R_ES, emu->x86.R_DI); + cmp_long(emu, val1, val2); + } else { + val1 = fetch_data_word(emu, emu->x86.R_SI); + val2 = fetch_word(emu, emu->x86.R_ES, emu->x86.R_DI); + cmp_word(emu, (uint16_t) val1, (uint16_t) val2); + } + emu->x86.R_SI += inc; + emu->x86.R_DI += inc; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xa9 +****************************************************************************/ +static void +x86emuOp_test_AX_IMM(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + test_long(emu, emu->x86.R_EAX, fetch_long_imm(emu)); + } else { + test_word(emu, emu->x86.R_AX, fetch_word_imm(emu)); + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xaa +****************************************************************************/ +static void +x86emuOp_stos_byte(struct X86EMU *emu) +{ + int inc; + + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + if (emu->x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + while (emu->x86.R_CX != 0) { + store_byte(emu, emu->x86.R_ES, emu->x86.R_DI, emu->x86.R_AL); + emu->x86.R_CX -= 1; + emu->x86.R_DI += inc; + } + emu->x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + store_byte(emu, emu->x86.R_ES, emu->x86.R_DI, emu->x86.R_AL); + emu->x86.R_DI += inc; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xab +****************************************************************************/ +static void +x86emuOp_stos_word(struct X86EMU *emu) +{ + int inc; + uint32_t count; + + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + inc = 4; + else + inc = 2; + + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -inc; + + count = 1; + if (emu->x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = emu->x86.R_CX; + emu->x86.R_CX = 0; + emu->x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + store_long(emu, emu->x86.R_ES, emu->x86.R_DI, emu->x86.R_EAX); + } else { + store_word(emu, emu->x86.R_ES, emu->x86.R_DI, emu->x86.R_AX); + } + emu->x86.R_DI += inc; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xac +****************************************************************************/ +static void +x86emuOp_lods_byte(struct X86EMU *emu) +{ + int inc; + + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + if (emu->x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + while (emu->x86.R_CX != 0) { + emu->x86.R_AL = fetch_data_byte(emu, emu->x86.R_SI); + emu->x86.R_CX -= 1; + emu->x86.R_SI += inc; + } + emu->x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + emu->x86.R_AL = fetch_data_byte(emu, emu->x86.R_SI); + emu->x86.R_SI += inc; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xad +****************************************************************************/ +static void +x86emuOp_lods_word(struct X86EMU *emu) +{ + int inc; + uint32_t count; + + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + inc = 4; + else + inc = 2; + + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -inc; + + count = 1; + if (emu->x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = emu->x86.R_CX; + emu->x86.R_CX = 0; + emu->x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + emu->x86.R_EAX = fetch_data_long(emu, emu->x86.R_SI); + } else { + emu->x86.R_AX = fetch_data_word(emu, emu->x86.R_SI); + } + emu->x86.R_SI += inc; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xae +****************************************************************************/ +static void +x86emuOp_scas_byte(struct X86EMU *emu) +{ + int8_t val2; + int inc; + + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + if (emu->x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (emu->x86.R_CX != 0) { + val2 = fetch_byte(emu, emu->x86.R_ES, emu->x86.R_DI); + cmp_byte(emu, emu->x86.R_AL, val2); + emu->x86.R_CX -= 1; + emu->x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + emu->x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (emu->x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (emu->x86.R_CX != 0) { + val2 = fetch_byte(emu, emu->x86.R_ES, emu->x86.R_DI); + cmp_byte(emu, emu->x86.R_AL, val2); + emu->x86.R_CX -= 1; + emu->x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + emu->x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + val2 = fetch_byte(emu, emu->x86.R_ES, emu->x86.R_DI); + cmp_byte(emu, emu->x86.R_AL, val2); + emu->x86.R_DI += inc; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xaf +****************************************************************************/ +static void +x86emuOp_scas_word(struct X86EMU *emu) +{ + int inc; + uint32_t val; + + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + inc = 4; + else + inc = 2; + + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -inc; + + if (emu->x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (emu->x86.R_CX != 0) { + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_long(emu, emu->x86.R_ES, emu->x86.R_DI); + cmp_long(emu, emu->x86.R_EAX, val); + } else { + val = fetch_word(emu, emu->x86.R_ES, emu->x86.R_DI); + cmp_word(emu, emu->x86.R_AX, (uint16_t) val); + } + emu->x86.R_CX -= 1; + emu->x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + emu->x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (emu->x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (emu->x86.R_CX != 0) { + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_long(emu, emu->x86.R_ES, emu->x86.R_DI); + cmp_long(emu, emu->x86.R_EAX, val); + } else { + val = fetch_word(emu, emu->x86.R_ES, emu->x86.R_DI); + cmp_word(emu, emu->x86.R_AX, (uint16_t) val); + } + emu->x86.R_CX -= 1; + emu->x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + emu->x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_long(emu, emu->x86.R_ES, emu->x86.R_DI); + cmp_long(emu, emu->x86.R_EAX, val); + } else { + val = fetch_word(emu, emu->x86.R_ES, emu->x86.R_DI); + cmp_word(emu, emu->x86.R_AX, (uint16_t) val); + } + emu->x86.R_DI += inc; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xb8 +****************************************************************************/ +static void +x86emuOp_mov_word_AX_IMM(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + emu->x86.R_EAX = fetch_long_imm(emu); + else + emu->x86.R_AX = fetch_word_imm(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xb9 +****************************************************************************/ +static void +x86emuOp_mov_word_CX_IMM(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + emu->x86.R_ECX = fetch_long_imm(emu); + else + emu->x86.R_CX = fetch_word_imm(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xba +****************************************************************************/ +static void +x86emuOp_mov_word_DX_IMM(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + emu->x86.R_EDX = fetch_long_imm(emu); + else + emu->x86.R_DX = fetch_word_imm(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xbb +****************************************************************************/ +static void +x86emuOp_mov_word_BX_IMM(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + emu->x86.R_EBX = fetch_long_imm(emu); + else + emu->x86.R_BX = fetch_word_imm(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xbc +****************************************************************************/ +static void +x86emuOp_mov_word_SP_IMM(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + emu->x86.R_ESP = fetch_long_imm(emu); + else + emu->x86.R_SP = fetch_word_imm(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xbd +****************************************************************************/ +static void +x86emuOp_mov_word_BP_IMM(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + emu->x86.R_EBP = fetch_long_imm(emu); + else + emu->x86.R_BP = fetch_word_imm(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xbe +****************************************************************************/ +static void +x86emuOp_mov_word_SI_IMM(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + emu->x86.R_ESI = fetch_long_imm(emu); + else + emu->x86.R_SI = fetch_word_imm(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xbf +****************************************************************************/ +static void +x86emuOp_mov_word_DI_IMM(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + emu->x86.R_EDI = fetch_long_imm(emu); + else + emu->x86.R_DI = fetch_word_imm(emu); +} +/* used by opcodes c0, d0, and d2. */ +static +uint8_t(* const opcD0_byte_operation[]) (struct X86EMU *, uint8_t d, uint8_t s) = +{ + rol_byte, + ror_byte, + rcl_byte, + rcr_byte, + shl_byte, + shr_byte, + shl_byte, /* sal_byte === shl_byte by definition */ + sar_byte, + }; +/**************************************************************************** +REMARKS: +Handles opcode 0xc0 +****************************************************************************/ +static void +x86emuOp_opcC0_byte_RM_MEM(struct X86EMU *emu) +{ + uint8_t destval, amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + fetch_decode_modrm(emu); + /* know operation, decode the mod byte to find the addressing mode. */ + destval = decode_and_fetch_byte_imm8(emu, &amt); + destval = (*opcD0_byte_operation[emu->cur_rh]) (emu, destval, amt); + write_back_byte(emu, destval); +} +/* used by opcodes c1, d1, and d3. */ +static +uint16_t(* const opcD1_word_operation[]) (struct X86EMU *, uint16_t s, uint8_t d) = +{ + rol_word, + ror_word, + rcl_word, + rcr_word, + shl_word, + shr_word, + shl_word, /* sal_byte === shl_byte by definition */ + sar_word, + }; +/* used by opcodes c1, d1, and d3. */ +static +uint32_t(* const opcD1_long_operation[]) (struct X86EMU *, uint32_t s, uint8_t d) = +{ + rol_long, + ror_long, + rcl_long, + rcr_long, + shl_long, + shr_long, + shl_long, /* sal_byte === shl_byte by definition */ + sar_long, + }; +/**************************************************************************** +REMARKS: +Handles opcode 0xc1 +****************************************************************************/ +static void +x86emuOp_opcC1_word_RM_MEM(struct X86EMU *emu) +{ + uint8_t amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + fetch_decode_modrm(emu); + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + uint32_t destval; + + destval = decode_and_fetch_long_imm8(emu, &amt); + destval = (*opcD1_long_operation[emu->cur_rh]) (emu, destval, amt); + write_back_long(emu, destval); + } else { + uint16_t destval; + + destval = decode_and_fetch_word_imm8(emu, &amt); + destval = (*opcD1_word_operation[emu->cur_rh]) (emu, destval, amt); + write_back_word(emu, destval); + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xc2 +****************************************************************************/ +static void +x86emuOp_ret_near_IMM(struct X86EMU *emu) +{ + uint16_t imm; + + imm = fetch_word_imm(emu); + emu->x86.R_IP = pop_word(emu); + emu->x86.R_SP += imm; +} +/**************************************************************************** +REMARKS: +Handles opcode 0xc6 +****************************************************************************/ +static void +x86emuOp_mov_byte_RM_IMM(struct X86EMU *emu) +{ + uint8_t *destreg; + uint32_t destoffset; + uint8_t imm; + + fetch_decode_modrm(emu); + if (emu->cur_rh != 0) + { + dbg("unexpected mode %d\r\n", emu->cur_rh); + X86EMU_halt_sys(emu); + } + if (emu->cur_mod != 3) { + destoffset = decode_rl_address(emu); + imm = fetch_byte_imm(emu); + store_data_byte(emu, destoffset, imm); + } else { + destreg = decode_rl_byte_register(emu); + imm = fetch_byte_imm(emu); + *destreg = imm; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xc7 +****************************************************************************/ +static void +x86emuOp32_mov_word_RM_IMM(struct X86EMU *emu) +{ + uint32_t destoffset; + uint32_t imm, *destreg; + + fetch_decode_modrm(emu); + if (emu->cur_rh != 0) + { + dbg("unexpected mode %d\r\n", emu->cur_rh); + X86EMU_halt_sys(emu); + } + + if (emu->cur_mod != 3) { + destoffset = decode_rl_address(emu); + imm = fetch_long_imm(emu); + store_data_long(emu, destoffset, imm); + } else { + destreg = decode_rl_long_register(emu); + imm = fetch_long_imm(emu); + *destreg = imm; + } +} + +static void +x86emuOp16_mov_word_RM_IMM(struct X86EMU *emu) +{ + uint32_t destoffset; + uint16_t imm, *destreg; + + fetch_decode_modrm(emu); + if (emu->cur_rh != 0) + { + dbg("unexpected mode %d\r\n", emu->cur_rh); + X86EMU_halt_sys(emu); + } + + if (emu->cur_mod != 3) { + destoffset = decode_rl_address(emu); + imm = fetch_word_imm(emu); + store_data_word(emu, destoffset, imm); + } else { + destreg = decode_rl_word_register(emu); + imm = fetch_word_imm(emu); + *destreg = imm; + } +} + +static void +x86emuOp_mov_word_RM_IMM(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + x86emuOp32_mov_word_RM_IMM(emu); + else + x86emuOp16_mov_word_RM_IMM(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xc8 +****************************************************************************/ +static void +x86emuOp_enter(struct X86EMU *emu) +{ + uint16_t local, frame_pointer; + uint8_t nesting; + int i; + + local = fetch_word_imm(emu); + nesting = fetch_byte_imm(emu); + push_word(emu, emu->x86.R_BP); + frame_pointer = emu->x86.R_SP; + if (nesting > 0) { + for (i = 1; i < nesting; i++) { + emu->x86.R_BP -= 2; + push_word(emu, fetch_word(emu, emu->x86.R_SS, emu->x86.R_BP)); + } + push_word(emu, frame_pointer); + } + emu->x86.R_BP = frame_pointer; + emu->x86.R_SP = (uint16_t) (emu->x86.R_SP - local); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xc9 +****************************************************************************/ +static void +x86emuOp_leave(struct X86EMU *emu) +{ + emu->x86.R_SP = emu->x86.R_BP; + emu->x86.R_BP = pop_word(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xca +****************************************************************************/ +static void +x86emuOp_ret_far_IMM(struct X86EMU *emu) +{ + uint16_t imm; + + imm = fetch_word_imm(emu); + emu->x86.R_IP = pop_word(emu); + emu->x86.R_CS = pop_word(emu); + emu->x86.R_SP += imm; +} +/**************************************************************************** +REMARKS: +Handles opcode 0xcb +****************************************************************************/ +static void +x86emuOp_ret_far(struct X86EMU *emu) +{ + emu->x86.R_IP = pop_word(emu); + emu->x86.R_CS = pop_word(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xcc +****************************************************************************/ +static void +x86emuOp_int3(struct X86EMU *emu) +{ + x86emu_intr_dispatch(emu, 3); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xcd +****************************************************************************/ +static void +x86emuOp_int_IMM(struct X86EMU *emu) +{ + uint8_t intnum; + + intnum = fetch_byte_imm(emu); + x86emu_intr_dispatch(emu, intnum); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xce +****************************************************************************/ +static void +x86emuOp_into(struct X86EMU *emu) +{ + if (ACCESS_FLAG(F_OF)) + x86emu_intr_dispatch(emu, 4); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xcf +****************************************************************************/ +static void +x86emuOp_iret(struct X86EMU *emu) +{ + emu->x86.R_IP = pop_word(emu); + emu->x86.R_CS = pop_word(emu); + emu->x86.R_FLG = pop_word(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xd0 +****************************************************************************/ +static void +x86emuOp_opcD0_byte_RM_1(struct X86EMU *emu) +{ + uint8_t destval; + + fetch_decode_modrm(emu); + destval = decode_and_fetch_byte(emu); + destval = (*opcD0_byte_operation[emu->cur_rh]) (emu, destval, 1); + write_back_byte(emu, destval); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xd1 +****************************************************************************/ +static void +x86emuOp_opcD1_word_RM_1(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + uint32_t destval; + + fetch_decode_modrm(emu); + destval = decode_and_fetch_long(emu); + destval = (*opcD1_long_operation[emu->cur_rh]) (emu, destval, 1); + write_back_long(emu, destval); + } else { + uint16_t destval; + + fetch_decode_modrm(emu); + destval = decode_and_fetch_word(emu); + destval = (*opcD1_word_operation[emu->cur_rh]) (emu, destval, 1); + write_back_word(emu, destval); + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xd2 +****************************************************************************/ +static void +x86emuOp_opcD2_byte_RM_CL(struct X86EMU *emu) +{ + uint8_t destval; + + fetch_decode_modrm(emu); + destval = decode_and_fetch_byte(emu); + destval = (*opcD0_byte_operation[emu->cur_rh]) (emu, destval, emu->x86.R_CL); + write_back_byte(emu, destval); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xd3 +****************************************************************************/ +static void +x86emuOp_opcD3_word_RM_CL(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + uint32_t destval; + + fetch_decode_modrm(emu); + destval = decode_and_fetch_long(emu); + destval = (*opcD1_long_operation[emu->cur_rh]) (emu, destval, emu->x86.R_CL); + write_back_long(emu, destval); + } else { + uint16_t destval; + + fetch_decode_modrm(emu); + destval = decode_and_fetch_word(emu); + destval = (*opcD1_word_operation[emu->cur_rh]) (emu, destval, emu->x86.R_CL); + write_back_word(emu, destval); + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xd4 +****************************************************************************/ +static void +x86emuOp_aam(struct X86EMU *emu) +{ + uint8_t a; + + a = fetch_byte_imm(emu); /* this is a stupid encoding. */ + if (a != 10) { + /* fix: add base decoding aam_word(uint8_t val, int base a) */ + dbg("unexpected encoding %d\r\n", a); + X86EMU_halt_sys(emu); + } + /* note the type change here --- returning AL and AH in AX. */ + emu->x86.R_AX = aam_word(emu, emu->x86.R_AL); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xd5 +****************************************************************************/ +static void +x86emuOp_aad(struct X86EMU *emu) +{ + uint8_t a; + + a = fetch_byte_imm(emu); + if (a != 10) { + /* fix: add base decoding aad_word(uint16_t val, int base a) */ + dbg("unexpected encoding %d\r\n", a); + X86EMU_halt_sys(emu); + } + emu->x86.R_AX = aad_word(emu, emu->x86.R_AX); +} +/* opcode 0xd6 ILLEGAL OPCODE */ + +/**************************************************************************** +REMARKS: +Handles opcode 0xd7 +****************************************************************************/ +static void +x86emuOp_xlat(struct X86EMU *emu) +{ + uint16_t addr; + + addr = (uint16_t) (emu->x86.R_BX + (uint8_t) emu->x86.R_AL); + emu->x86.R_AL = fetch_data_byte(emu, addr); +} + +/* opcode=0xd8 */ +static void +x86emuOp_esc_coprocess_d8(struct X86EMU *emu) +{ +} +/* opcode=0xd9 */ +static void +x86emuOp_esc_coprocess_d9(struct X86EMU *emu) +{ + fetch_decode_modrm(emu); + if (emu->cur_mod != 3) + decode_rl_address(emu); +} +/* opcode=0xda */ +static void +x86emuOp_esc_coprocess_da(struct X86EMU *emu) +{ + fetch_decode_modrm(emu); + if (emu->cur_mod != 3) + decode_rl_address(emu); +} +/* opcode=0xdb */ +static void +x86emuOp_esc_coprocess_db(struct X86EMU *emu) +{ + fetch_decode_modrm(emu); + if (emu->cur_mod != 3) + decode_rl_address(emu); +} +/* opcode=0xdc */ +static void +x86emuOp_esc_coprocess_dc(struct X86EMU *emu) +{ + fetch_decode_modrm(emu); + if (emu->cur_mod != 3) + decode_rl_address(emu); +} +/* opcode=0xdd */ +static void +x86emuOp_esc_coprocess_dd(struct X86EMU *emu) +{ + fetch_decode_modrm(emu); + if (emu->cur_mod != 3) + decode_rl_address(emu); +} +/* opcode=0xde */ +static void +x86emuOp_esc_coprocess_de(struct X86EMU *emu) +{ + fetch_decode_modrm(emu); + if (emu->cur_mod != 3) + decode_rl_address(emu); +} +/* opcode=0xdf */ +static void +x86emuOp_esc_coprocess_df(struct X86EMU *emu) +{ + fetch_decode_modrm(emu); + if (emu->cur_mod != 3) + decode_rl_address(emu); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe0 +****************************************************************************/ +static void +x86emuOp_loopne(struct X86EMU *emu) +{ + int16_t ip; + + ip = (int8_t) fetch_byte_imm(emu); + ip += (int16_t) emu->x86.R_IP; + emu->x86.R_CX -= 1; + if (emu->x86.R_CX != 0 && !ACCESS_FLAG(F_ZF)) /* CX != 0 and !ZF */ + emu->x86.R_IP = ip; +} +/**************************************************************************** +REMARKS: +Handles opcode 0xe1 +****************************************************************************/ +static void +x86emuOp_loope(struct X86EMU *emu) +{ + int16_t ip; + + ip = (int8_t) fetch_byte_imm(emu); + ip += (int16_t) emu->x86.R_IP; + emu->x86.R_CX -= 1; + if (emu->x86.R_CX != 0 && ACCESS_FLAG(F_ZF)) /* CX != 0 and ZF */ + emu->x86.R_IP = ip; +} +/**************************************************************************** +REMARKS: +Handles opcode 0xe2 +****************************************************************************/ +static void +x86emuOp_loop(struct X86EMU *emu) +{ + int16_t ip; + + ip = (int8_t) fetch_byte_imm(emu); + ip += (int16_t) emu->x86.R_IP; + emu->x86.R_CX -= 1; + if (emu->x86.R_CX != 0) + emu->x86.R_IP = ip; +} +/**************************************************************************** +REMARKS: +Handles opcode 0xe3 +****************************************************************************/ +static void +x86emuOp_jcxz(struct X86EMU *emu) +{ + uint16_t target; + int8_t offset; + + /* jump to byte offset if overflow flag is set */ + offset = (int8_t) fetch_byte_imm(emu); + target = (uint16_t) (emu->x86.R_IP + offset); + if (emu->x86.R_CX == 0) + emu->x86.R_IP = target; +} +/**************************************************************************** +REMARKS: +Handles opcode 0xe4 +****************************************************************************/ +static void +x86emuOp_in_byte_AL_IMM(struct X86EMU *emu) +{ + uint8_t port; + + port = (uint8_t) fetch_byte_imm(emu); + emu->x86.R_AL = (*emu->emu_inb) (emu, port); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xe5 +****************************************************************************/ +static void +x86emuOp_in_word_AX_IMM(struct X86EMU *emu) +{ + uint8_t port; + + port = (uint8_t) fetch_byte_imm(emu); + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + emu->x86.R_EAX = (*emu->emu_inl) (emu, port); + } else { + emu->x86.R_AX = (*emu->emu_inw) (emu, port); + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xe6 +****************************************************************************/ +static void +x86emuOp_out_byte_IMM_AL(struct X86EMU *emu) +{ + uint8_t port; + + port = (uint8_t) fetch_byte_imm(emu); + (*emu->emu_outb) (emu, port, emu->x86.R_AL); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xe7 +****************************************************************************/ +static void +x86emuOp_out_word_IMM_AX(struct X86EMU *emu) +{ + uint8_t port; + + port = (uint8_t) fetch_byte_imm(emu); + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + (*emu->emu_outl) (emu, port, emu->x86.R_EAX); + } else { + (*emu->emu_outw) (emu, port, emu->x86.R_AX); + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xe8 +****************************************************************************/ +static void +x86emuOp_call_near_IMM(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + int32_t ip; + ip = (int32_t) fetch_long_imm(emu); + ip += (int32_t) emu->x86.R_EIP; + push_long(emu, emu->x86.R_EIP); + emu->x86.R_EIP = ip; + } else { + int16_t ip; + ip = (int16_t) fetch_word_imm(emu); + ip += (int16_t) emu->x86.R_IP; /* CHECK SIGN */ + push_word(emu, emu->x86.R_IP); + emu->x86.R_IP = ip; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xe9 +****************************************************************************/ +static void +x86emuOp_jump_near_IMM(struct X86EMU *emu) +{ + int ip; + + ip = (int16_t) fetch_word_imm(emu); + ip += (int16_t) emu->x86.R_IP; + emu->x86.R_IP = (uint16_t) ip; +} +/**************************************************************************** +REMARKS: +Handles opcode 0xea +****************************************************************************/ +static void +x86emuOp_jump_far_IMM(struct X86EMU *emu) +{ + uint16_t cs, ip; + + ip = fetch_word_imm(emu); + cs = fetch_word_imm(emu); + emu->x86.R_IP = ip; + emu->x86.R_CS = cs; +} +/**************************************************************************** +REMARKS: +Handles opcode 0xeb +****************************************************************************/ +static void +x86emuOp_jump_byte_IMM(struct X86EMU *emu) +{ + uint16_t target; + int8_t offset; + + offset = (int8_t) fetch_byte_imm(emu); + target = (uint16_t) (emu->x86.R_IP + offset); + emu->x86.R_IP = target; +} +/**************************************************************************** +REMARKS: +Handles opcode 0xec +****************************************************************************/ +static void +x86emuOp_in_byte_AL_DX(struct X86EMU *emu) +{ + emu->x86.R_AL = (*emu->emu_inb) (emu, emu->x86.R_DX); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xed +****************************************************************************/ +static void +x86emuOp_in_word_AX_DX(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + emu->x86.R_EAX = (*emu->emu_inl) (emu, emu->x86.R_DX); + } else { + emu->x86.R_AX = (*emu->emu_inw) (emu, emu->x86.R_DX); + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xee +****************************************************************************/ +static void +x86emuOp_out_byte_DX_AL(struct X86EMU *emu) +{ + (*emu->emu_outb) (emu, emu->x86.R_DX, emu->x86.R_AL); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xef +****************************************************************************/ +static void +x86emuOp_out_word_DX_AX(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + (*emu->emu_outl) (emu, emu->x86.R_DX, emu->x86.R_EAX); + } else { + (*emu->emu_outw) (emu, emu->x86.R_DX, emu->x86.R_AX); + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xf0 +****************************************************************************/ +static void +x86emuOp_lock(struct X86EMU *emu) +{ +} +/*opcode 0xf1 ILLEGAL OPERATION */ + +/**************************************************************************** +REMARKS: +Handles opcode 0xf5 +****************************************************************************/ +static void +x86emuOp_cmc(struct X86EMU *emu) +{ + if (ACCESS_FLAG(F_CF)) + CLEAR_FLAG(F_CF); + else + SET_FLAG(F_CF); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xf6 +****************************************************************************/ +static void +x86emuOp_opcF6_byte_RM(struct X86EMU *emu) +{ + uint8_t destval, srcval; + + /* long, drawn out code follows. Double switch for a total of 32 + * cases. */ + fetch_decode_modrm(emu); + if (emu->cur_rh == 1) + { + dbg("unexpected mode %d\r\n", emu->cur_rh); + X86EMU_halt_sys(emu); + } + + if (emu->cur_rh == 0) { + destval = decode_and_fetch_byte_imm8(emu, &srcval); + test_byte(emu, destval, srcval); + return; + } + destval = decode_and_fetch_byte(emu); + switch (emu->cur_rh) { + case 2: + destval = ~destval; + write_back_byte(emu, destval); + break; + case 3: + destval = neg_byte(emu, destval); + write_back_byte(emu, destval); + break; + case 4: + mul_byte(emu, destval); + break; + case 5: + imul_byte(emu, destval); + break; + case 6: + div_byte(emu, destval); + break; + case 7: + idiv_byte(emu, destval); + break; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xf7 +****************************************************************************/ +static void +x86emuOp32_opcF7_word_RM(struct X86EMU *emu) +{ + uint32_t destval, srcval; + + /* long, drawn out code follows. Double switch for a total of 32 + * cases. */ + fetch_decode_modrm(emu); + if (emu->cur_rh == 1) + { + dbg("unexpected mode %d\r\n", emu->cur_rh); + X86EMU_halt_sys(emu); + } + + if (emu->cur_rh == 0) { + if (emu->cur_mod != 3) { + uint32_t destoffset; + + destoffset = decode_rl_address(emu); + srcval = fetch_long_imm(emu); + destval = fetch_data_long(emu, destoffset); + } else { + srcval = fetch_long_imm(emu); + destval = *decode_rl_long_register(emu); + } + test_long(emu, destval, srcval); + return; + } + destval = decode_and_fetch_long(emu); + switch (emu->cur_rh) { + case 2: + destval = ~destval; + write_back_long(emu, destval); + break; + case 3: + destval = neg_long(emu, destval); + write_back_long(emu, destval); + break; + case 4: + mul_long(emu, destval); + break; + case 5: + imul_long(emu, destval); + break; + case 6: + div_long(emu, destval); + break; + case 7: + idiv_long(emu, destval); + break; + } +} +static void +x86emuOp16_opcF7_word_RM(struct X86EMU *emu) +{ + uint16_t destval, srcval; + + /* long, drawn out code follows. Double switch for a total of 32 + * cases. */ + fetch_decode_modrm(emu); + if (emu->cur_rh == 1) + { + dbg("unexpected encoding %d\r\n", emu->cur_rh); + X86EMU_halt_sys(emu); + } + + if (emu->cur_rh == 0) { + if (emu->cur_mod != 3) { + uint32_t destoffset; + + destoffset = decode_rl_address(emu); + srcval = fetch_word_imm(emu); + destval = fetch_data_word(emu, destoffset); + } else { + srcval = fetch_word_imm(emu); + destval = *decode_rl_word_register(emu); + } + test_word(emu, destval, srcval); + return; + } + destval = decode_and_fetch_word(emu); + switch (emu->cur_rh) { + case 2: + destval = ~destval; + write_back_word(emu, destval); + break; + case 3: + destval = neg_word(emu, destval); + write_back_word(emu, destval); + break; + case 4: + mul_word(emu, destval); + break; + case 5: + imul_word(emu, destval); + break; + case 6: + div_word(emu, destval); + break; + case 7: + idiv_word(emu, destval); + break; + } +} +static void +x86emuOp_opcF7_word_RM(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + x86emuOp32_opcF7_word_RM(emu); + else + x86emuOp16_opcF7_word_RM(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0xfe +****************************************************************************/ +static void +x86emuOp_opcFE_byte_RM(struct X86EMU *emu) +{ + uint8_t destval; + uint32_t destoffset; + uint8_t *destreg; + + /* Yet another special case instruction. */ + fetch_decode_modrm(emu); + if (emu->cur_mod != 3) { + destoffset = decode_rl_address(emu); + switch (emu->cur_rh) { + case 0: /* inc word ptr ... */ + destval = fetch_data_byte(emu, destoffset); + destval = inc_byte(emu, destval); + store_data_byte(emu, destoffset, destval); + break; + case 1: /* dec word ptr ... */ + destval = fetch_data_byte(emu, destoffset); + destval = dec_byte(emu, destval); + store_data_byte(emu, destoffset, destval); + break; + } + } else { + destreg = decode_rl_byte_register(emu); + switch (emu->cur_rh) { + case 0: + *destreg = inc_byte(emu, *destreg); + break; + case 1: + *destreg = dec_byte(emu, *destreg); + break; + } + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0xff +****************************************************************************/ +static void +x86emuOp32_opcFF_word_RM(struct X86EMU *emu) +{ + uint32_t destoffset = 0; + uint32_t destval, *destreg; + + if (emu->cur_mod != 3) { + destoffset = decode_rl_address(emu); + destval = fetch_data_long(emu, destoffset); + switch (emu->cur_rh) { + case 0: /* inc word ptr ... */ + destval = inc_long(emu, destval); + store_data_long(emu, destoffset, destval); + break; + case 1: /* dec word ptr ... */ + destval = dec_long(emu, destval); + store_data_long(emu, destoffset, destval); + break; + case 6: /* push word ptr ... */ + push_long(emu, destval); + break; + } + } else { + destreg = decode_rl_long_register(emu); + switch (emu->cur_rh) { + case 0: + *destreg = inc_long(emu, *destreg); + break; + case 1: + *destreg = dec_long(emu, *destreg); + break; + case 6: + push_long(emu, *destreg); + break; + } + } +} + +static void +x86emuOp16_opcFF_word_RM(struct X86EMU *emu) +{ + uint32_t destoffset = 0; + uint16_t *destreg; + uint16_t destval; + + if (emu->cur_mod != 3) { + destoffset = decode_rl_address(emu); + destval = fetch_data_word(emu, destoffset); + switch (emu->cur_rh) { + case 0: + destval = inc_word(emu, destval); + store_data_word(emu, destoffset, destval); + break; + case 1: /* dec word ptr ... */ + destval = dec_word(emu, destval); + store_data_word(emu, destoffset, destval); + break; + case 6: /* push word ptr ... */ + push_word(emu, destval); + break; + } + } else { + destreg = decode_rl_word_register(emu); + switch (emu->cur_rh) { + case 0: + *destreg = inc_word(emu, *destreg); + break; + case 1: + *destreg = dec_word(emu, *destreg); + break; + case 6: + push_word(emu, *destreg); + break; + } + } +} + +static void +x86emuOp_opcFF_word_RM(struct X86EMU *emu) +{ + uint32_t destoffset = 0; + uint16_t destval, destval2; + + /* Yet another special case instruction. */ + fetch_decode_modrm(emu); + if ((emu->cur_mod == 3 && (emu->cur_rh == 3 || emu->cur_rh == 5)) || emu->cur_rh == 7) + { + dbg("unexpected mode %d, %d\r\n", emu->cur_mod, emu->cur_rh); + X86EMU_halt_sys(emu); + } + if (emu->cur_rh == 0 || emu->cur_rh == 1 || emu->cur_rh == 6) { + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + x86emuOp32_opcFF_word_RM(emu); + else + x86emuOp16_opcFF_word_RM(emu); + return; + } + + if (emu->cur_mod != 3) { + destoffset = decode_rl_address(emu); + destval = fetch_data_word(emu, destoffset); + switch (emu->cur_rh) { + case 3: /* call far ptr ... */ + destval2 = fetch_data_word(emu, destoffset + 2); + push_word(emu, emu->x86.R_CS); + emu->x86.R_CS = destval2; + push_word(emu, emu->x86.R_IP); + emu->x86.R_IP = destval; + break; + case 5: /* jmp far ptr ... */ + destval2 = fetch_data_word(emu, destoffset + 2); + emu->x86.R_IP = destval; + emu->x86.R_CS = destval2; + break; + } + } else { + destval = *decode_rl_word_register(emu); + } + + switch (emu->cur_rh) { + case 2: /* call word ptr */ + push_word(emu, emu->x86.R_IP); + emu->x86.R_IP = destval; + break; + case 4: /* jmp */ + emu->x86.R_IP = destval; + break; + } +} +/*************************************************************************** + * Single byte operation code table: + **************************************************************************/ +static void +X86EMU_exec_one_byte(struct X86EMU * emu) +{ + uint8_t op1; + + op1 = fetch_byte_imm(emu); + + switch (op1) { + case 0x00: + common_binop_byte_rm_r(emu, add_byte); + break; + case 0x01: + common_binop_word_long_rm_r(emu, add_word, add_long); + break; + case 0x02: + common_binop_byte_r_rm(emu, add_byte); + break; + case 0x03: + common_binop_word_long_r_rm(emu, add_word, add_long); + break; + case 0x04: + common_binop_byte_imm(emu, add_byte); + break; + case 0x05: + common_binop_word_long_imm(emu, add_word, add_long); + break; + case 0x06: + push_word(emu, emu->x86.R_ES); + break; + case 0x07: + emu->x86.R_ES = pop_word(emu); + break; + + case 0x08: + common_binop_byte_rm_r(emu, or_byte); + break; + case 0x09: + common_binop_word_long_rm_r(emu, or_word, or_long); + break; + case 0x0a: + common_binop_byte_r_rm(emu, or_byte); + break; + case 0x0b: + common_binop_word_long_r_rm(emu, or_word, or_long); + break; + case 0x0c: + common_binop_byte_imm(emu, or_byte); + break; + case 0x0d: + common_binop_word_long_imm(emu, or_word, or_long); + break; + case 0x0e: + push_word(emu, emu->x86.R_CS); + break; + case 0x0f: + X86EMU_exec_two_byte(emu); + break; + + case 0x10: + common_binop_byte_rm_r(emu, adc_byte); + break; + case 0x11: + common_binop_word_long_rm_r(emu, adc_word, adc_long); + break; + case 0x12: + common_binop_byte_r_rm(emu, adc_byte); + break; + case 0x13: + common_binop_word_long_r_rm(emu, adc_word, adc_long); + break; + case 0x14: + common_binop_byte_imm(emu, adc_byte); + break; + case 0x15: + common_binop_word_long_imm(emu, adc_word, adc_long); + break; + case 0x16: + push_word(emu, emu->x86.R_SS); + break; + case 0x17: + emu->x86.R_SS = pop_word(emu); + break; + + case 0x18: + common_binop_byte_rm_r(emu, sbb_byte); + break; + case 0x19: + common_binop_word_long_rm_r(emu, sbb_word, sbb_long); + break; + case 0x1a: + common_binop_byte_r_rm(emu, sbb_byte); + break; + case 0x1b: + common_binop_word_long_r_rm(emu, sbb_word, sbb_long); + break; + case 0x1c: + common_binop_byte_imm(emu, sbb_byte); + break; + case 0x1d: + common_binop_word_long_imm(emu, sbb_word, sbb_long); + break; + case 0x1e: + push_word(emu, emu->x86.R_DS); + break; + case 0x1f: + emu->x86.R_DS = pop_word(emu); + break; + + case 0x20: + common_binop_byte_rm_r(emu, and_byte); + break; + case 0x21: + common_binop_word_long_rm_r(emu, and_word, and_long); + break; + case 0x22: + common_binop_byte_r_rm(emu, and_byte); + break; + case 0x23: + common_binop_word_long_r_rm(emu, and_word, and_long); + break; + case 0x24: + common_binop_byte_imm(emu, and_byte); + break; + case 0x25: + common_binop_word_long_imm(emu, and_word, and_long); + break; + case 0x26: + emu->x86.mode |= SYSMODE_SEGOVR_ES; + break; + case 0x27: + emu->x86.R_AL = daa_byte(emu, emu->x86.R_AL); + break; + + case 0x28: + common_binop_byte_rm_r(emu, sub_byte); + break; + case 0x29: + common_binop_word_long_rm_r(emu, sub_word, sub_long); + break; + case 0x2a: + common_binop_byte_r_rm(emu, sub_byte); + break; + case 0x2b: + common_binop_word_long_r_rm(emu, sub_word, sub_long); + break; + case 0x2c: + common_binop_byte_imm(emu, sub_byte); + break; + case 0x2d: + common_binop_word_long_imm(emu, sub_word, sub_long); + break; + case 0x2e: + emu->x86.mode |= SYSMODE_SEGOVR_CS; + break; + case 0x2f: + emu->x86.R_AL = das_byte(emu, emu->x86.R_AL); + break; + + case 0x30: + common_binop_byte_rm_r(emu, xor_byte); + break; + case 0x31: + common_binop_word_long_rm_r(emu, xor_word, xor_long); + break; + case 0x32: + common_binop_byte_r_rm(emu, xor_byte); + break; + case 0x33: + common_binop_word_long_r_rm(emu, xor_word, xor_long); + break; + case 0x34: + common_binop_byte_imm(emu, xor_byte); + break; + case 0x35: + common_binop_word_long_imm(emu, xor_word, xor_long); + break; + case 0x36: + emu->x86.mode |= SYSMODE_SEGOVR_SS; + break; + case 0x37: + emu->x86.R_AX = aaa_word(emu, emu->x86.R_AX); + break; + + case 0x38: + common_binop_ns_byte_rm_r(emu, cmp_byte_no_return); + break; + case 0x39: + common_binop_ns_word_long_rm_r(emu, cmp_word_no_return, + cmp_long_no_return); + break; + case 0x3a: + x86emuOp_cmp_byte_R_RM(emu); + break; + case 0x3b: + x86emuOp_cmp_word_R_RM(emu); + break; + case 0x3c: + x86emuOp_cmp_byte_AL_IMM(emu); + break; + case 0x3d: + x86emuOp_cmp_word_AX_IMM(emu); + break; + case 0x3e: + emu->x86.mode |= SYSMODE_SEGOVR_DS; + break; + case 0x3f: + emu->x86.R_AX = aas_word(emu, emu->x86.R_AX); + break; + + case 0x40: + common_inc_word_long(emu, &emu->x86.register_a); + break; + case 0x41: + common_inc_word_long(emu, &emu->x86.register_c); + break; + case 0x42: + common_inc_word_long(emu, &emu->x86.register_d); + break; + case 0x43: + common_inc_word_long(emu, &emu->x86.register_b); + break; + case 0x44: + common_inc_word_long(emu, &emu->x86.register_sp); + break; + case 0x45: + common_inc_word_long(emu, &emu->x86.register_bp); + break; + case 0x46: + common_inc_word_long(emu, &emu->x86.register_si); + break; + case 0x47: + common_inc_word_long(emu, &emu->x86.register_di); + break; + + case 0x48: + common_dec_word_long(emu, &emu->x86.register_a); + break; + case 0x49: + common_dec_word_long(emu, &emu->x86.register_c); + break; + case 0x4a: + common_dec_word_long(emu, &emu->x86.register_d); + break; + case 0x4b: + common_dec_word_long(emu, &emu->x86.register_b); + break; + case 0x4c: + common_dec_word_long(emu, &emu->x86.register_sp); + break; + case 0x4d: + common_dec_word_long(emu, &emu->x86.register_bp); + break; + case 0x4e: + common_dec_word_long(emu, &emu->x86.register_si); + break; + case 0x4f: + common_dec_word_long(emu, &emu->x86.register_di); + break; + + case 0x50: + common_push_word_long(emu, &emu->x86.register_a); + break; + case 0x51: + common_push_word_long(emu, &emu->x86.register_c); + break; + case 0x52: + common_push_word_long(emu, &emu->x86.register_d); + break; + case 0x53: + common_push_word_long(emu, &emu->x86.register_b); + break; + case 0x54: + common_push_word_long(emu, &emu->x86.register_sp); + break; + case 0x55: + common_push_word_long(emu, &emu->x86.register_bp); + break; + case 0x56: + common_push_word_long(emu, &emu->x86.register_si); + break; + case 0x57: + common_push_word_long(emu, &emu->x86.register_di); + break; + + case 0x58: + common_pop_word_long(emu, &emu->x86.register_a); + break; + case 0x59: + common_pop_word_long(emu, &emu->x86.register_c); + break; + case 0x5a: + common_pop_word_long(emu, &emu->x86.register_d); + break; + case 0x5b: + common_pop_word_long(emu, &emu->x86.register_b); + break; + case 0x5c: + common_pop_word_long(emu, &emu->x86.register_sp); + break; + case 0x5d: + common_pop_word_long(emu, &emu->x86.register_bp); + break; + case 0x5e: + common_pop_word_long(emu, &emu->x86.register_si); + break; + case 0x5f: + common_pop_word_long(emu, &emu->x86.register_di); + break; + + case 0x60: + x86emuOp_push_all(emu); + break; + case 0x61: + x86emuOp_pop_all(emu); + break; + /* 0x62 bound */ + /* 0x63 arpl */ + case 0x64: + emu->x86.mode |= SYSMODE_SEGOVR_FS; + break; + case 0x65: + emu->x86.mode |= SYSMODE_SEGOVR_GS; + break; + case 0x66: + emu->x86.mode |= SYSMODE_PREFIX_DATA; + break; + case 0x67: + emu->x86.mode |= SYSMODE_PREFIX_ADDR; + break; + + case 0x68: + x86emuOp_push_word_IMM(emu); + break; + case 0x69: + common_imul_imm(emu, false); + break; + case 0x6a: + x86emuOp_push_byte_IMM(emu); + break; + case 0x6b: + common_imul_imm(emu, true); + break; + case 0x6c: + ins(emu, 1); + break; + case 0x6d: + x86emuOp_ins_word(emu); + break; + case 0x6e: + outs(emu, 1); + break; + case 0x6f: + x86emuOp_outs_word(emu); + break; + + case 0x70: + common_jmp_near(emu, ACCESS_FLAG(F_OF)); + break; + case 0x71: + common_jmp_near(emu, !ACCESS_FLAG(F_OF)); + break; + case 0x72: + common_jmp_near(emu, ACCESS_FLAG(F_CF)); + break; + case 0x73: + common_jmp_near(emu, !ACCESS_FLAG(F_CF)); + break; + case 0x74: + common_jmp_near(emu, ACCESS_FLAG(F_ZF)); + break; + case 0x75: + common_jmp_near(emu, !ACCESS_FLAG(F_ZF)); + break; + case 0x76: + common_jmp_near(emu, ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); + break; + case 0x77: + common_jmp_near(emu, !ACCESS_FLAG(F_CF) && !ACCESS_FLAG(F_ZF)); + break; + + case 0x78: + common_jmp_near(emu, ACCESS_FLAG(F_SF)); + break; + case 0x79: + common_jmp_near(emu, !ACCESS_FLAG(F_SF)); + break; + case 0x7a: + common_jmp_near(emu, ACCESS_FLAG(F_PF)); + break; + case 0x7b: + common_jmp_near(emu, !ACCESS_FLAG(F_PF)); + break; + case 0x7c: + x86emuOp_jump_near_L(emu); + break; + case 0x7d: + x86emuOp_jump_near_NL(emu); + break; + case 0x7e: + x86emuOp_jump_near_LE(emu); + break; + case 0x7f: + x86emuOp_jump_near_NLE(emu); + break; + + case 0x80: + x86emuOp_opc80_byte_RM_IMM(emu); + break; + case 0x81: + x86emuOp_opc81_word_RM_IMM(emu); + break; + case 0x82: + x86emuOp_opc82_byte_RM_IMM(emu); + break; + case 0x83: + x86emuOp_opc83_word_RM_IMM(emu); + break; + case 0x84: + common_binop_ns_byte_rm_r(emu, test_byte); + break; + case 0x85: + common_binop_ns_word_long_rm_r(emu, test_word, test_long); + break; + case 0x86: + x86emuOp_xchg_byte_RM_R(emu); + break; + case 0x87: + x86emuOp_xchg_word_RM_R(emu); + break; + + case 0x88: + x86emuOp_mov_byte_RM_R(emu); + break; + case 0x89: + x86emuOp_mov_word_RM_R(emu); + break; + case 0x8a: + x86emuOp_mov_byte_R_RM(emu); + break; + case 0x8b: + x86emuOp_mov_word_R_RM(emu); + break; + case 0x8c: + x86emuOp_mov_word_RM_SR(emu); + break; + case 0x8d: + x86emuOp_lea_word_R_M(emu); + break; + case 0x8e: + x86emuOp_mov_word_SR_RM(emu); + break; + case 0x8f: + x86emuOp_pop_RM(emu); + break; + + case 0x90: + /* nop */ + break; + case 0x91: + x86emuOp_xchg_word_AX_CX(emu); + break; + case 0x92: + x86emuOp_xchg_word_AX_DX(emu); + break; + case 0x93: + x86emuOp_xchg_word_AX_BX(emu); + break; + case 0x94: + x86emuOp_xchg_word_AX_SP(emu); + break; + case 0x95: + x86emuOp_xchg_word_AX_BP(emu); + break; + case 0x96: + x86emuOp_xchg_word_AX_SI(emu); + break; + case 0x97: + x86emuOp_xchg_word_AX_DI(emu); + break; + + case 0x98: + x86emuOp_cbw(emu); + break; + case 0x99: + x86emuOp_cwd(emu); + break; + case 0x9a: + x86emuOp_call_far_IMM(emu); + break; + case 0x9b: + /* wait */ + break; + case 0x9c: + x86emuOp_pushf_word(emu); + break; + case 0x9d: + x86emuOp_popf_word(emu); + break; + case 0x9e: + x86emuOp_sahf(emu); + break; + case 0x9f: + x86emuOp_lahf(emu); + break; + + case 0xa0: + x86emuOp_mov_AL_M_IMM(emu); + break; + case 0xa1: + x86emuOp_mov_AX_M_IMM(emu); + break; + case 0xa2: + x86emuOp_mov_M_AL_IMM(emu); + break; + case 0xa3: + x86emuOp_mov_M_AX_IMM(emu); + break; + case 0xa4: + x86emuOp_movs_byte(emu); + break; + case 0xa5: + x86emuOp_movs_word(emu); + break; + case 0xa6: + x86emuOp_cmps_byte(emu); + break; + case 0xa7: + x86emuOp_cmps_word(emu); + break; + + case 0xa8: + test_byte(emu, emu->x86.R_AL, fetch_byte_imm(emu)); + break; + case 0xa9: + x86emuOp_test_AX_IMM(emu); + break; + case 0xaa: + x86emuOp_stos_byte(emu); + break; + case 0xab: + x86emuOp_stos_word(emu); + break; + case 0xac: + x86emuOp_lods_byte(emu); + break; + case 0xad: + x86emuOp_lods_word(emu); + break; + case 0xae: + x86emuOp_scas_byte(emu); + break; + case 0xaf: + x86emuOp_scas_word(emu); + break; + + case 0xb0: + emu->x86.R_AL = fetch_byte_imm(emu); + break; + case 0xb1: + emu->x86.R_CL = fetch_byte_imm(emu); + break; + case 0xb2: + emu->x86.R_DL = fetch_byte_imm(emu); + break; + case 0xb3: + emu->x86.R_BL = fetch_byte_imm(emu); + break; + case 0xb4: + emu->x86.R_AH = fetch_byte_imm(emu); + break; + case 0xb5: + emu->x86.R_CH = fetch_byte_imm(emu); + break; + case 0xb6: + emu->x86.R_DH = fetch_byte_imm(emu); + break; + case 0xb7: + emu->x86.R_BH = fetch_byte_imm(emu); + break; + + case 0xb8: + x86emuOp_mov_word_AX_IMM(emu); + break; + case 0xb9: + x86emuOp_mov_word_CX_IMM(emu); + break; + case 0xba: + x86emuOp_mov_word_DX_IMM(emu); + break; + case 0xbb: + x86emuOp_mov_word_BX_IMM(emu); + break; + case 0xbc: + x86emuOp_mov_word_SP_IMM(emu); + break; + case 0xbd: + x86emuOp_mov_word_BP_IMM(emu); + break; + case 0xbe: + x86emuOp_mov_word_SI_IMM(emu); + break; + case 0xbf: + x86emuOp_mov_word_DI_IMM(emu); + break; + + case 0xc0: + x86emuOp_opcC0_byte_RM_MEM(emu); + break; + case 0xc1: + x86emuOp_opcC1_word_RM_MEM(emu); + break; + case 0xc2: + x86emuOp_ret_near_IMM(emu); + break; + case 0xc3: + emu->x86.R_IP = pop_word(emu); + break; + case 0xc4: + common_load_far_pointer(emu, &emu->x86.R_ES); + break; + case 0xc5: + common_load_far_pointer(emu, &emu->x86.R_DS); + break; + case 0xc6: + x86emuOp_mov_byte_RM_IMM(emu); + break; + case 0xc7: + x86emuOp_mov_word_RM_IMM(emu); + break; + case 0xc8: + x86emuOp_enter(emu); + break; + case 0xc9: + x86emuOp_leave(emu); + break; + case 0xca: + x86emuOp_ret_far_IMM(emu); + break; + case 0xcb: + x86emuOp_ret_far(emu); + break; + case 0xcc: + x86emuOp_int3(emu); + break; + case 0xcd: + x86emuOp_int_IMM(emu); + break; + case 0xce: + x86emuOp_into(emu); + break; + case 0xcf: + x86emuOp_iret(emu); + break; + + case 0xd0: + x86emuOp_opcD0_byte_RM_1(emu); + break; + case 0xd1: + x86emuOp_opcD1_word_RM_1(emu); + break; + case 0xd2: + x86emuOp_opcD2_byte_RM_CL(emu); + break; + case 0xd3: + x86emuOp_opcD3_word_RM_CL(emu); + break; + case 0xd4: + x86emuOp_aam(emu); + break; + case 0xd5: + x86emuOp_aad(emu); + break; + /* 0xd6 Undocumented SETALC instruction */ + case 0xd7: + x86emuOp_xlat(emu); + break; + case 0xd8: + x86emuOp_esc_coprocess_d8(emu); + break; + case 0xd9: + x86emuOp_esc_coprocess_d9(emu); + break; + case 0xda: + x86emuOp_esc_coprocess_da(emu); + break; + case 0xdb: + x86emuOp_esc_coprocess_db(emu); + break; + case 0xdc: + x86emuOp_esc_coprocess_dc(emu); + break; + case 0xdd: + x86emuOp_esc_coprocess_dd(emu); + break; + case 0xde: + x86emuOp_esc_coprocess_de(emu); + break; + case 0xdf: + x86emuOp_esc_coprocess_df(emu); + break; + + case 0xe0: + x86emuOp_loopne(emu); + break; + case 0xe1: + x86emuOp_loope(emu); + break; + case 0xe2: + x86emuOp_loop(emu); + break; + case 0xe3: + x86emuOp_jcxz(emu); + break; + case 0xe4: + x86emuOp_in_byte_AL_IMM(emu); + break; + case 0xe5: + x86emuOp_in_word_AX_IMM(emu); + break; + case 0xe6: + x86emuOp_out_byte_IMM_AL(emu); + break; + case 0xe7: + x86emuOp_out_word_IMM_AX(emu); + break; + + case 0xe8: + x86emuOp_call_near_IMM(emu); + break; + case 0xe9: + x86emuOp_jump_near_IMM(emu); + break; + case 0xea: + x86emuOp_jump_far_IMM(emu); + break; + case 0xeb: + x86emuOp_jump_byte_IMM(emu); + break; + case 0xec: + x86emuOp_in_byte_AL_DX(emu); + break; + case 0xed: + x86emuOp_in_word_AX_DX(emu); + break; + case 0xee: + x86emuOp_out_byte_DX_AL(emu); + break; + case 0xef: + x86emuOp_out_word_DX_AX(emu); + break; + + case 0xf0: + x86emuOp_lock(emu); + break; + case 0xf2: + emu->x86.mode |= SYSMODE_PREFIX_REPNE; + break; + case 0xf3: + emu->x86.mode |= SYSMODE_PREFIX_REPE; + break; + case 0xf4: + dbg("unexpected op1\r\n"); + X86EMU_halt_sys(emu); + break; + case 0xf5: + x86emuOp_cmc(emu); + break; + case 0xf6: + x86emuOp_opcF6_byte_RM(emu); + break; + case 0xf7: + x86emuOp_opcF7_word_RM(emu); + break; + + case 0xf8: + CLEAR_FLAG(F_CF); + break; + case 0xf9: + SET_FLAG(F_CF); + break; + case 0xfa: + CLEAR_FLAG(F_IF); + break; + case 0xfb: + SET_FLAG(F_IF); + break; + case 0xfc: + CLEAR_FLAG(F_DF); + break; + case 0xfd: + SET_FLAG(F_DF); + break; + case 0xfe: + x86emuOp_opcFE_byte_RM(emu); + break; + case 0xff: + x86emuOp_opcFF_word_RM(emu); + break; + default: + dbg("unexpected op1 %d\r\n", op1); + X86EMU_halt_sys(emu); + break; + } + if (op1 != 0x26 && op1 != 0x2e && op1 != 0x36 && op1 != 0x3e && + (op1 | 3) != 0x67) + emu->x86.mode &= ~SYSMODE_CLRMASK; +} + +static void +common_jmp_long(struct X86EMU *emu, bool cond) +{ + int16_t target; + + target = (int16_t) fetch_word_imm(emu); + target += (int16_t) emu->x86.R_IP; + if (cond) + emu->x86.R_IP = (uint16_t) target; +} + +static void +common_set_byte(struct X86EMU *emu, bool cond) +{ + uint32_t destoffset; + uint8_t *destreg, destval; + + fetch_decode_modrm(emu); + destval = cond ? 0x01 : 0x00; + if (emu->cur_mod != 3) { + destoffset = decode_rl_address(emu); + store_data_byte(emu, destoffset, destval); + } else { + destreg = decode_rl_byte_register(emu); + *destreg = destval; + } +} + +static void +common_bitstring32(struct X86EMU *emu, int op) +{ + int bit; + uint32_t srcval, *shiftreg, mask; + + fetch_decode_modrm(emu); + shiftreg = decode_rh_long_register(emu); + srcval = decode_and_fetch_long_disp(emu, (int16_t) *shiftreg >> 5); + bit = *shiftreg & 0x1F; + mask = 0x1 << bit; + CONDITIONAL_SET_FLAG(srcval & mask, F_CF); + + switch (op) { + case 0: + break; + case 1: + write_back_long(emu, srcval | mask); + break; + case 2: + write_back_long(emu, srcval & ~mask); + break; + case 3: + write_back_long(emu, srcval ^ mask); + break; + } +} + +static void +common_bitstring16(struct X86EMU *emu, int op) +{ + int bit; + uint16_t srcval, *shiftreg, mask; + + fetch_decode_modrm(emu); + shiftreg = decode_rh_word_register(emu); + srcval = decode_and_fetch_word_disp(emu, (int16_t) *shiftreg >> 4); + bit = *shiftreg & 0xF; + mask = 0x1 << bit; + CONDITIONAL_SET_FLAG(srcval & mask, F_CF); + + switch (op) { + case 0: + break; + case 1: + write_back_word(emu, srcval | mask); + break; + case 2: + write_back_word(emu, srcval & ~mask); + break; + case 3: + write_back_word(emu, srcval ^ mask); + break; + } +} + +static void +common_bitstring(struct X86EMU *emu, int op) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + common_bitstring32(emu, op); + else + common_bitstring16(emu, op); +} + +static void +common_bitsearch32(struct X86EMU *emu, int diff) +{ + uint32_t srcval, *dstreg; + + fetch_decode_modrm(emu); + dstreg = decode_rh_long_register(emu); + srcval = decode_and_fetch_long(emu); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for (*dstreg = 0; *dstreg < 32; *dstreg += diff) { + if ((srcval >> *dstreg) & 1) + break; + } +} + +static void +common_bitsearch16(struct X86EMU *emu, int diff) +{ + uint16_t srcval, *dstreg; + + fetch_decode_modrm(emu); + dstreg = decode_rh_word_register(emu); + srcval = decode_and_fetch_word(emu); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for (*dstreg = 0; *dstreg < 16; *dstreg += diff) { + if ((srcval >> *dstreg) & 1) + break; + } +} + +static void +common_bitsearch(struct X86EMU *emu, int diff) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + common_bitsearch32(emu, diff); + else + common_bitsearch16(emu, diff); +} + +static void +common_shift32(struct X86EMU *emu, bool shift_left, bool use_cl) +{ + uint8_t shift; + uint32_t destval, *shiftreg; + + fetch_decode_modrm(emu); + shiftreg = decode_rh_long_register(emu); + if (use_cl) { + destval = decode_and_fetch_long(emu); + shift = emu->x86.R_CL; + } else { + destval = decode_and_fetch_long_imm8(emu, &shift); + } + if (shift_left) + destval = shld_long(emu, destval, *shiftreg, shift); + else + destval = shrd_long(emu, destval, *shiftreg, shift); + write_back_long(emu, destval); +} + +static void +common_shift16(struct X86EMU *emu, bool shift_left, bool use_cl) +{ + uint8_t shift; + uint16_t destval, *shiftreg; + + fetch_decode_modrm(emu); + shiftreg = decode_rh_word_register(emu); + if (use_cl) { + destval = decode_and_fetch_word(emu); + shift = emu->x86.R_CL; + } else { + destval = decode_and_fetch_word_imm8(emu, &shift); + } + if (shift_left) + destval = shld_word(emu, destval, *shiftreg, shift); + else + destval = shrd_word(emu, destval, *shiftreg, shift); + write_back_word(emu, destval); +} + +static void +common_shift(struct X86EMU *emu, bool shift_left, bool use_cl) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + common_shift32(emu, shift_left, use_cl); + else + common_shift16(emu, shift_left, use_cl); +} + +/*----------------------------- Implementation ----------------------------*/ +#define xorl(a,b) ((a) && !(b)) || (!(a) && (b)) + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0x31 +****************************************************************************/ +static void +x86emuOp2_rdtsc(struct X86EMU *emu) +{ + emu->x86.R_EAX = emu->cur_cycles & 0xffffffff; + emu->x86.R_EDX = emu->cur_cycles >> 32; +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa0 +****************************************************************************/ +static void +x86emuOp2_push_FS(struct X86EMU *emu) +{ + push_word(emu, emu->x86.R_FS); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa1 +****************************************************************************/ +static void +x86emuOp2_pop_FS(struct X86EMU *emu) +{ + emu->x86.R_FS = pop_word(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa1 +****************************************************************************/ +#if defined(__i386__) || defined(__amd64__) +static void +hw_cpuid(uint32_t *a, uint32_t *b, uint32_t *c, uint32_t *d) +{ + __asm__ __volatile__("cpuid" + : "=a" (*a), "=b" (*b), + "=c" (*c), "=d" (*d) + : "a" (*a), "c" (*c) + : "cc"); +} +#endif +static void +x86emuOp2_cpuid(struct X86EMU *emu) +{ +#if defined(__i386__) || defined(__amd64__) + hw_cpuid(&emu->x86.R_EAX, &emu->x86.R_EBX, &emu->x86.R_ECX, + &emu->x86.R_EDX); +#endif + switch (emu->x86.R_EAX) { + case 0: + emu->x86.R_EAX = 1; +#if !defined(__i386__) && !defined(__amd64__) + /* "GenuineIntel" */ + emu->x86.R_EBX = 0x756e6547; + emu->x86.R_EDX = 0x49656e69; + emu->x86.R_ECX = 0x6c65746e; +#endif + break; + case 1: +#if !defined(__i386__) && !defined(__amd64__) + emu->x86.R_EAX = 0x00000480; + emu->x86.R_EBX = emu->x86.R_ECX = 0; + emu->x86.R_EDX = 0x00000002; +#else + emu->x86.R_EDX &= 0x00000012; +#endif + break; + default: + emu->x86.R_EAX = emu->x86.R_EBX = emu->x86.R_ECX = + emu->x86.R_EDX = 0; + break; + } +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa3 +****************************************************************************/ +static void +x86emuOp2_bt_R(struct X86EMU *emu) +{ + common_bitstring(emu, 0); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa4 +****************************************************************************/ +static void +x86emuOp2_shld_IMM(struct X86EMU *emu) +{ + common_shift(emu, true, false); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa5 +****************************************************************************/ +static void +x86emuOp2_shld_CL(struct X86EMU *emu) +{ + common_shift(emu, true, true); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa8 +****************************************************************************/ +static void +x86emuOp2_push_GS(struct X86EMU *emu) +{ + push_word(emu, emu->x86.R_GS); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa9 +****************************************************************************/ +static void +x86emuOp2_pop_GS(struct X86EMU *emu) +{ + emu->x86.R_GS = pop_word(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xab +****************************************************************************/ +static void +x86emuOp2_bts_R(struct X86EMU *emu) +{ + common_bitstring(emu, 1); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xac +****************************************************************************/ +static void +x86emuOp2_shrd_IMM(struct X86EMU *emu) +{ + common_shift(emu, false, false); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xad +****************************************************************************/ +static void +x86emuOp2_shrd_CL(struct X86EMU *emu) +{ + common_shift(emu, false, true); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xaf +****************************************************************************/ +static void +x86emuOp2_32_imul_R_RM(struct X86EMU *emu) +{ + uint32_t *destreg, srcval; + uint64_t res; + + fetch_decode_modrm(emu); + destreg = decode_rh_long_register(emu); + srcval = decode_and_fetch_long(emu); + res = (int32_t) *destreg * (int32_t)srcval; + if (res > 0xffffffff) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (uint32_t) res; +} + +static void +x86emuOp2_16_imul_R_RM(struct X86EMU *emu) +{ + uint16_t *destreg, srcval; + uint32_t res; + + fetch_decode_modrm(emu); + destreg = decode_rh_word_register(emu); + srcval = decode_and_fetch_word(emu); + res = (int16_t) * destreg * (int16_t)srcval; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (uint16_t) res; +} + +static void +x86emuOp2_imul_R_RM(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + x86emuOp2_32_imul_R_RM(emu); + else + x86emuOp2_16_imul_R_RM(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb2 +****************************************************************************/ +static void +x86emuOp2_lss_R_IMM(struct X86EMU *emu) +{ + common_load_far_pointer(emu, &emu->x86.R_SS); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb3 +****************************************************************************/ +static void +x86emuOp2_btr_R(struct X86EMU *emu) +{ + common_bitstring(emu, 2); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb4 +****************************************************************************/ +static void +x86emuOp2_lfs_R_IMM(struct X86EMU *emu) +{ + common_load_far_pointer(emu, &emu->x86.R_FS); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb5 +****************************************************************************/ +static void +x86emuOp2_lgs_R_IMM(struct X86EMU *emu) +{ + common_load_far_pointer(emu, &emu->x86.R_GS); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb6 +****************************************************************************/ +static void +x86emuOp2_32_movzx_byte_R_RM(struct X86EMU *emu) +{ + uint32_t *destreg; + + fetch_decode_modrm(emu); + destreg = decode_rh_long_register(emu); + *destreg = decode_and_fetch_byte(emu); +} + +static void +x86emuOp2_16_movzx_byte_R_RM(struct X86EMU *emu) +{ + uint16_t *destreg; + + fetch_decode_modrm(emu); + destreg = decode_rh_word_register(emu); + *destreg = decode_and_fetch_byte(emu); +} + +static void +x86emuOp2_movzx_byte_R_RM(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + x86emuOp2_32_movzx_byte_R_RM(emu); + else + x86emuOp2_16_movzx_byte_R_RM(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb7 +****************************************************************************/ +static void +x86emuOp2_movzx_word_R_RM(struct X86EMU *emu) +{ + uint32_t *destreg; + + fetch_decode_modrm(emu); + destreg = decode_rh_long_register(emu); + *destreg = decode_and_fetch_word(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xba +****************************************************************************/ +static void +x86emuOp2_32_btX_I(struct X86EMU *emu) +{ + int bit; + uint32_t srcval, mask; + uint8_t shift; + + fetch_decode_modrm(emu); + if (emu->cur_rh < 4) + { + dbg("unexpected mode %d\r\n", emu->cur_rh); + X86EMU_halt_sys(emu); + } + + srcval = decode_and_fetch_long_imm8(emu, &shift); + bit = shift & 0x1F; + mask = (0x1 << bit); + + switch (emu->cur_rh) { + case 5: + write_back_long(emu, srcval | mask); + break; + case 6: + write_back_long(emu, srcval & ~mask); + break; + case 7: + write_back_long(emu, srcval ^ mask); + break; + } + CONDITIONAL_SET_FLAG(srcval & mask, F_CF); +} + +static void +x86emuOp2_16_btX_I(struct X86EMU *emu) +{ + int bit; + + uint16_t srcval, mask; + uint8_t shift; + + fetch_decode_modrm(emu); + if (emu->cur_rh < 4) + { + dbg("unexpected mode %d\r\n", emu->cur_rh); + X86EMU_halt_sys(emu); + } + + srcval = decode_and_fetch_word_imm8(emu, &shift); + bit = shift & 0xF; + mask = (0x1 << bit); + switch (emu->cur_rh) { + case 5: + write_back_word(emu, srcval | mask); + break; + case 6: + write_back_word(emu, srcval & ~mask); + break; + case 7: + write_back_word(emu, srcval ^ mask); + break; + } + CONDITIONAL_SET_FLAG(srcval & mask, F_CF); +} + +static void +x86emuOp2_btX_I(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + x86emuOp2_32_btX_I(emu); + else + x86emuOp2_16_btX_I(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbb +****************************************************************************/ +static void +x86emuOp2_btc_R(struct X86EMU *emu) +{ + common_bitstring(emu, 3); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbc +****************************************************************************/ +static void +x86emuOp2_bsf(struct X86EMU *emu) +{ + common_bitsearch(emu, +1); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbd +****************************************************************************/ +static void +x86emuOp2_bsr(struct X86EMU *emu) +{ + common_bitsearch(emu, -1); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbe +****************************************************************************/ +static void +x86emuOp2_32_movsx_byte_R_RM(struct X86EMU *emu) +{ + uint32_t *destreg; + + fetch_decode_modrm(emu); + destreg = decode_rh_long_register(emu); + *destreg = (int32_t)(int8_t)decode_and_fetch_byte(emu); +} + +static void +x86emuOp2_16_movsx_byte_R_RM(struct X86EMU *emu) +{ + uint16_t *destreg; + + fetch_decode_modrm(emu); + destreg = decode_rh_word_register(emu); + *destreg = (int16_t)(int8_t)decode_and_fetch_byte(emu); +} + +static void +x86emuOp2_movsx_byte_R_RM(struct X86EMU *emu) +{ + if (emu->x86.mode & SYSMODE_PREFIX_DATA) + x86emuOp2_32_movsx_byte_R_RM(emu); + else + x86emuOp2_16_movsx_byte_R_RM(emu); +} +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbf +****************************************************************************/ +static void +x86emuOp2_movsx_word_R_RM(struct X86EMU *emu) +{ + uint32_t *destreg; + + fetch_decode_modrm(emu); + destreg = decode_rh_long_register(emu); + *destreg = (int32_t)(int16_t)decode_and_fetch_word(emu); +} + +static void +X86EMU_exec_two_byte(struct X86EMU * emu) +{ + uint8_t op2; + + op2 = fetch_byte_imm(emu); + + switch (op2) { + /* 0x00 Group F (ring 0 PM) */ + /* 0x01 Group G (ring 0 PM) */ + /* 0x02 lar (ring 0 PM) */ + /* 0x03 lsl (ring 0 PM) */ + /* 0x05 loadall (undocumented) */ + /* 0x06 clts (ring 0 PM) */ + /* 0x07 loadall (undocumented) */ + /* 0x08 invd (ring 0 PM) */ + /* 0x09 wbinvd (ring 0 PM) */ + + /* 0x20 mov reg32(op2); break;creg (ring 0 PM) */ + /* 0x21 mov reg32(op2); break;dreg (ring 0 PM) */ + /* 0x22 mov creg(op2); break;reg32 (ring 0 PM) */ + /* 0x23 mov dreg(op2); break;reg32 (ring 0 PM) */ + /* 0x24 mov reg32(op2); break;treg (ring 0 PM) */ + /* 0x26 mov treg(op2); break;reg32 (ring 0 PM) */ + + case 0x31: + x86emuOp2_rdtsc(emu); + break; + + case 0x80: + common_jmp_long(emu, ACCESS_FLAG(F_OF)); + break; + case 0x81: + common_jmp_long(emu, !ACCESS_FLAG(F_OF)); + break; + case 0x82: + common_jmp_long(emu, ACCESS_FLAG(F_CF)); + break; + case 0x83: + common_jmp_long(emu, !ACCESS_FLAG(F_CF)); + break; + case 0x84: + common_jmp_long(emu, ACCESS_FLAG(F_ZF)); + break; + case 0x85: + common_jmp_long(emu, !ACCESS_FLAG(F_ZF)); + break; + case 0x86: + common_jmp_long(emu, ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); + break; + case 0x87: + common_jmp_long(emu, !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF))); + break; + case 0x88: + common_jmp_long(emu, ACCESS_FLAG(F_SF)); + break; + case 0x89: + common_jmp_long(emu, !ACCESS_FLAG(F_SF)); + break; + case 0x8a: + common_jmp_long(emu, ACCESS_FLAG(F_PF)); + break; + case 0x8b: + common_jmp_long(emu, !ACCESS_FLAG(F_PF)); + break; + case 0x8c: + common_jmp_long(emu, xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF))); + break; + case 0x8d: + common_jmp_long(emu, !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)))); + break; + case 0x8e: + common_jmp_long(emu, + (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || ACCESS_FLAG(F_ZF))); + break; + case 0x8f: + common_jmp_long(emu, + !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || ACCESS_FLAG(F_ZF))); + break; + + case 0x90: + common_set_byte(emu, ACCESS_FLAG(F_OF)); + break; + case 0x91: + common_set_byte(emu, !ACCESS_FLAG(F_OF)); + break; + case 0x92: + common_set_byte(emu, ACCESS_FLAG(F_CF)); + break; + case 0x93: + common_set_byte(emu, !ACCESS_FLAG(F_CF)); + break; + case 0x94: + common_set_byte(emu, ACCESS_FLAG(F_ZF)); + break; + case 0x95: + common_set_byte(emu, !ACCESS_FLAG(F_ZF)); + break; + case 0x96: + common_set_byte(emu, ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); + break; + case 0x97: + common_set_byte(emu, !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF))); + break; + case 0x98: + common_set_byte(emu, ACCESS_FLAG(F_SF)); + break; + case 0x99: + common_set_byte(emu, !ACCESS_FLAG(F_SF)); + break; + case 0x9a: + common_set_byte(emu, ACCESS_FLAG(F_PF)); + break; + case 0x9b: + common_set_byte(emu, !ACCESS_FLAG(F_PF)); + break; + case 0x9c: + common_set_byte(emu, xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF))); + break; + case 0x9d: + common_set_byte(emu, xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF))); + break; + case 0x9e: + common_set_byte(emu, + (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF))); + break; + case 0x9f: + common_set_byte(emu, + !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF))); + break; + + case 0xa0: + x86emuOp2_push_FS(emu); + break; + case 0xa1: + x86emuOp2_pop_FS(emu); + break; + case 0xa2: + x86emuOp2_cpuid(emu); + break; + case 0xa3: + x86emuOp2_bt_R(emu); + break; + case 0xa4: + x86emuOp2_shld_IMM(emu); + break; + case 0xa5: + x86emuOp2_shld_CL(emu); + break; + case 0xa8: + x86emuOp2_push_GS(emu); + break; + case 0xa9: + x86emuOp2_pop_GS(emu); + break; + case 0xab: + x86emuOp2_bts_R(emu); + break; + case 0xac: + x86emuOp2_shrd_IMM(emu); + break; + case 0xad: + x86emuOp2_shrd_CL(emu); + break; + case 0xaf: + x86emuOp2_imul_R_RM(emu); + break; + + /* 0xb0 TODO: cmpxchg */ + /* 0xb1 TODO: cmpxchg */ + case 0xb2: + x86emuOp2_lss_R_IMM(emu); + break; + case 0xb3: + x86emuOp2_btr_R(emu); + break; + case 0xb4: + x86emuOp2_lfs_R_IMM(emu); + break; + case 0xb5: + x86emuOp2_lgs_R_IMM(emu); + break; + case 0xb6: + x86emuOp2_movzx_byte_R_RM(emu); + break; + case 0xb7: + x86emuOp2_movzx_word_R_RM(emu); + break; + case 0xba: + x86emuOp2_btX_I(emu); + break; + case 0xbb: + x86emuOp2_btc_R(emu); + break; + case 0xbc: + x86emuOp2_bsf(emu); + break; + case 0xbd: + x86emuOp2_bsr(emu); + break; + case 0xbe: + x86emuOp2_movsx_byte_R_RM(emu); + break; + case 0xbf: + x86emuOp2_movsx_word_R_RM(emu); + break; + + /* 0xc0 TODO: xadd */ + /* 0xc1 TODO: xadd */ + /* 0xc8 TODO: bswap */ + /* 0xc9 TODO: bswap */ + /* 0xca TODO: bswap */ + /* 0xcb TODO: bswap */ + /* 0xcc TODO: bswap */ + /* 0xcd TODO: bswap */ + /* 0xce TODO: bswap */ + /* 0xcf TODO: bswap */ + + default: + dbg("unexpected op2 %d\r\n", op2); + X86EMU_halt_sys(emu); + break; + } +} + +/* +* Carry Chain Calculation +* +* This represents a somewhat expensive calculation which is +* apparently required to emulate the setting of the OF and AF flag. +* The latter is not so important, but the former is. The overflow +* flag is the XOR of the top two bits of the carry chain for an +* addition (similar for subtraction). Since we do not want to +* simulate the addition in a bitwise manner, we try to calculate the +* carry chain given the two operands and the result. +* +* So, given the following table, which represents the addition of two +* bits, we can derive a formula for the carry chain. +* +* a b cin r cout +* 0 0 0 0 0 +* 0 0 1 1 0 +* 0 1 0 1 0 +* 0 1 1 0 1 +* 1 0 0 1 0 +* 1 0 1 0 1 +* 1 1 0 0 1 +* 1 1 1 1 1 +* +* Construction of table for cout: +* +* ab +* r \ 00 01 11 10 +* |------------------ +* 0 | 0 1 1 1 +* 1 | 0 0 1 0 +* +* By inspection, one gets: cc = ab + r'(a + b) +* +* That represents alot of operations, but NO CHOICE.... +* +* Borrow Chain Calculation. +* +* The following table represents the subtraction of two bits, from +* which we can derive a formula for the borrow chain. +* +* a b bin r bout +* 0 0 0 0 0 +* 0 0 1 1 1 +* 0 1 0 1 1 +* 0 1 1 0 1 +* 1 0 0 1 0 +* 1 0 1 0 0 +* 1 1 0 0 0 +* 1 1 1 1 1 +* +* Construction of table for cout: +* +* ab +* r \ 00 01 11 10 +* |------------------ +* 0 | 0 1 0 0 +* 1 | 1 1 1 0 +* +* By inspection, one gets: bc = a'b + r(a' + b) +* +****************************************************************************/ + +/*------------------------- Global Variables ------------------------------*/ + +static uint32_t x86emu_parity_tab[8] = +{ + 0x96696996, + 0x69969669, + 0x69969669, + 0x96696996, + 0x69969669, + 0x96696996, + 0x96696996, + 0x69969669, +}; +#define PARITY(x) (((x86emu_parity_tab[(x) / 32] >> ((x) % 32)) & 1) == 0) +#define XOR2(x) (((x) ^ ((x)>>1)) & 0x1) + +/**************************************************************************** +REMARKS: +Implements the AAA instruction and side effects. +****************************************************************************/ +static uint16_t +aaa_word(struct X86EMU *emu, uint16_t d) +{ + uint16_t res; + if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { + d += 0x6; + d += 0x100; + SET_FLAG(F_AF); + SET_FLAG(F_CF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + } + res = (uint16_t) (d & 0xFF0F); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} +/**************************************************************************** +REMARKS: +Implements the AAA instruction and side effects. +****************************************************************************/ +static uint16_t +aas_word(struct X86EMU *emu, uint16_t d) +{ + uint16_t res; + if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { + d -= 0x6; + d -= 0x100; + SET_FLAG(F_AF); + SET_FLAG(F_CF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + } + res = (uint16_t) (d & 0xFF0F); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} +/**************************************************************************** +REMARKS: +Implements the AAD instruction and side effects. +****************************************************************************/ +static uint16_t +aad_word(struct X86EMU *emu, uint16_t d) +{ + uint16_t l; + uint8_t hb, lb; + + hb = (uint8_t) ((d >> 8) & 0xff); + lb = (uint8_t) ((d & 0xff)); + l = (uint16_t) ((lb + 10 * hb) & 0xFF); + + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(l & 0x80, F_SF); + CONDITIONAL_SET_FLAG(l == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(l & 0xff), F_PF); + return l; +} +/**************************************************************************** +REMARKS: +Implements the AAM instruction and side effects. +****************************************************************************/ +static uint16_t +aam_word(struct X86EMU *emu, uint8_t d) +{ + uint16_t h, l; + + h = (uint16_t) (d / 10); + l = (uint16_t) (d % 10); + l |= (uint16_t) (h << 8); + + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(l & 0x80, F_SF); + CONDITIONAL_SET_FLAG(l == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(l & 0xff), F_PF); + return l; +} +/**************************************************************************** +REMARKS: +Implements the ADC instruction and side effects. +****************************************************************************/ +static uint8_t +adc_byte(struct X86EMU *emu, uint8_t d, uint8_t s) +{ + uint32_t res; /* all operands in native machine order */ + uint32_t cc; + + if (ACCESS_FLAG(F_CF)) + res = 1 + d + s; + else + res = d + s; + + CONDITIONAL_SET_FLAG(res & 0x100, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (uint8_t) res; +} +/**************************************************************************** +REMARKS: +Implements the ADC instruction and side effects. +****************************************************************************/ +static uint16_t +adc_word(struct X86EMU *emu, uint16_t d, uint16_t s) +{ + uint32_t res; /* all operands in native machine order */ + uint32_t cc; + + if (ACCESS_FLAG(F_CF)) + res = 1 + d + s; + else + res = d + s; + + CONDITIONAL_SET_FLAG(res & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (uint16_t) res; +} +/**************************************************************************** +REMARKS: +Implements the ADC instruction and side effects. +****************************************************************************/ +static uint32_t +adc_long(struct X86EMU *emu, uint32_t d, uint32_t s) +{ + uint32_t lo; /* all operands in native machine order */ + uint32_t hi; + uint32_t res; + uint32_t cc; + + if (ACCESS_FLAG(F_CF)) { + lo = 1 + (d & 0xFFFF) + (s & 0xFFFF); + res = 1 + d + s; + } else { + lo = (d & 0xFFFF) + (s & 0xFFFF); + res = d + s; + } + hi = (lo >> 16) + (d >> 16) + (s >> 16); + + CONDITIONAL_SET_FLAG(hi & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return res; +} +/**************************************************************************** +REMARKS: +Implements the ADD instruction and side effects. +****************************************************************************/ +static uint8_t +add_byte(struct X86EMU *emu, uint8_t d, uint8_t s) +{ + uint32_t res; /* all operands in native machine order */ + uint32_t cc; + + res = d + s; + CONDITIONAL_SET_FLAG(res & 0x100, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (uint8_t) res; +} +/**************************************************************************** +REMARKS: +Implements the ADD instruction and side effects. +****************************************************************************/ +static uint16_t +add_word(struct X86EMU *emu, uint16_t d, uint16_t s) +{ + uint32_t res; /* all operands in native machine order */ + uint32_t cc; + + res = d + s; + CONDITIONAL_SET_FLAG(res & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (uint16_t) res; +} +/**************************************************************************** +REMARKS: +Implements the ADD instruction and side effects. +****************************************************************************/ +static uint32_t +add_long(struct X86EMU *emu, uint32_t d, uint32_t s) +{ + uint32_t lo; /* all operands in native machine order */ + uint32_t hi; + uint32_t res; + uint32_t cc; + + lo = (d & 0xFFFF) + (s & 0xFFFF); + res = d + s; + hi = (lo >> 16) + (d >> 16) + (s >> 16); + + CONDITIONAL_SET_FLAG(hi & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + + return res; +} +/**************************************************************************** +REMARKS: +Implements the AND instruction and side effects. +****************************************************************************/ +static uint8_t +and_byte(struct X86EMU *emu, uint8_t d, uint8_t s) +{ + uint8_t res; /* all operands in native machine order */ + + res = d & s; + + /* set the flags */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + return res; +} +/**************************************************************************** +REMARKS: +Implements the AND instruction and side effects. +****************************************************************************/ +static uint16_t +and_word(struct X86EMU *emu, uint16_t d, uint16_t s) +{ + uint16_t res; /* all operands in native machine order */ + + res = d & s; + + /* set the flags */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} +/**************************************************************************** +REMARKS: +Implements the AND instruction and side effects. +****************************************************************************/ +static uint32_t +and_long(struct X86EMU *emu, uint32_t d, uint32_t s) +{ + uint32_t res; /* all operands in native machine order */ + + res = d & s; + + /* set the flags */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} +/**************************************************************************** +REMARKS: +Implements the CMP instruction and side effects. +****************************************************************************/ +static uint8_t +cmp_byte(struct X86EMU *emu, uint8_t d, uint8_t s) +{ + uint32_t res; /* all operands in native machine order */ + uint32_t bc; + + res = d - s; + CLEAR_FLAG(F_CF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return d; +} + +static void +cmp_byte_no_return(struct X86EMU *emu, uint8_t d, uint8_t s) +{ + cmp_byte(emu, d, s); +} +/**************************************************************************** +REMARKS: +Implements the CMP instruction and side effects. +****************************************************************************/ +static uint16_t +cmp_word(struct X86EMU *emu, uint16_t d, uint16_t s) +{ + uint32_t res; /* all operands in native machine order */ + uint32_t bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return d; +} + +static void +cmp_word_no_return(struct X86EMU *emu, uint16_t d, uint16_t s) +{ + cmp_word(emu, d, s); +} +/**************************************************************************** +REMARKS: +Implements the CMP instruction and side effects. +****************************************************************************/ +static uint32_t +cmp_long(struct X86EMU *emu, uint32_t d, uint32_t s) +{ + uint32_t res; /* all operands in native machine order */ + uint32_t bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return d; +} + +static void +cmp_long_no_return(struct X86EMU *emu, uint32_t d, uint32_t s) +{ + cmp_long(emu, d, s); +} +/**************************************************************************** +REMARKS: +Implements the DAA instruction and side effects. +****************************************************************************/ +static uint8_t +daa_byte(struct X86EMU *emu, uint8_t d) +{ + uint32_t res = d; + if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { + res += 6; + SET_FLAG(F_AF); + } + if (res > 0x9F || ACCESS_FLAG(F_CF)) { + res += 0x60; + SET_FLAG(F_CF); + } + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xFF) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return (uint8_t) res; +} +/**************************************************************************** +REMARKS: +Implements the DAS instruction and side effects. +****************************************************************************/ +static uint8_t +das_byte(struct X86EMU *emu, uint8_t d) +{ + if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { + d -= 6; + SET_FLAG(F_AF); + } + if (d > 0x9F || ACCESS_FLAG(F_CF)) { + d -= 0x60; + SET_FLAG(F_CF); + } + CONDITIONAL_SET_FLAG(d & 0x80, F_SF); + CONDITIONAL_SET_FLAG(d == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(d & 0xff), F_PF); + return d; +} +/**************************************************************************** +REMARKS: +Implements the DEC instruction and side effects. +****************************************************************************/ +static uint8_t +dec_byte(struct X86EMU *emu, uint8_t d) +{ + uint32_t res; /* all operands in native machine order */ + uint32_t bc; + + res = d - 1; + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + /* based on sub_byte, uses s==1. */ + bc = (res & (~d | 1)) | (~d & 1); + /* carry flag unchanged */ + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (uint8_t) res; +} +/**************************************************************************** +REMARKS: +Implements the DEC instruction and side effects. +****************************************************************************/ +static uint16_t +dec_word(struct X86EMU *emu, uint16_t d) +{ + uint32_t res; /* all operands in native machine order */ + uint32_t bc; + + res = d - 1; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + /* based on the sub_byte routine, with s==1 */ + bc = (res & (~d | 1)) | (~d & 1); + /* carry flag unchanged */ + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (uint16_t) res; +} +/**************************************************************************** +REMARKS: +Implements the DEC instruction and side effects. +****************************************************************************/ +static uint32_t +dec_long(struct X86EMU *emu, uint32_t d) +{ + uint32_t res; /* all operands in native machine order */ + uint32_t bc; + + res = d - 1; + + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | 1)) | (~d & 1); + /* carry flag unchanged */ + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} +/**************************************************************************** +REMARKS: +Implements the INC instruction and side effects. +****************************************************************************/ +static uint8_t +inc_byte(struct X86EMU *emu, uint8_t d) +{ + uint32_t res; /* all operands in native machine order */ + uint32_t cc; + + res = d + 1; + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = ((1 & d) | (~res)) & (1 | d); + CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (uint8_t) res; +} +/**************************************************************************** +REMARKS: +Implements the INC instruction and side effects. +****************************************************************************/ +static uint16_t +inc_word(struct X86EMU *emu, uint16_t d) +{ + uint32_t res; /* all operands in native machine order */ + uint32_t cc; + + res = d + 1; + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (1 & d) | ((~res) & (1 | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (uint16_t) res; +} +/**************************************************************************** +REMARKS: +Implements the INC instruction and side effects. +****************************************************************************/ +static uint32_t +inc_long(struct X86EMU *emu, uint32_t d) +{ + uint32_t res; /* all operands in native machine order */ + uint32_t cc; + + res = d + 1; + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (1 & d) | ((~res) & (1 | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return res; +} +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +static uint8_t +or_byte(struct X86EMU *emu, uint8_t d, uint8_t s) +{ + uint8_t res; /* all operands in native machine order */ + + res = d | s; + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + return res; +} +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +static uint16_t +or_word(struct X86EMU *emu, uint16_t d, uint16_t s) +{ + uint16_t res; /* all operands in native machine order */ + + res = d | s; + /* set the carry flag to be bit 8 */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +static uint32_t +or_long(struct X86EMU *emu, uint32_t d, uint32_t s) +{ + uint32_t res; /* all operands in native machine order */ + + res = d | s; + + /* set the carry flag to be bit 8 */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +static uint8_t +neg_byte(struct X86EMU *emu, uint8_t s) +{ + uint8_t res; + uint8_t bc; + + CONDITIONAL_SET_FLAG(s != 0, F_CF); + res = (uint8_t) - s; + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + /* calculate the borrow chain --- modified such that d=0. + * substitutiing d=0 into bc= res&(~d|s)|(~d&s); (the one used for + * sub) and simplifying, since ~d=0xff..., ~d|s == 0xffff..., and + * res&0xfff... == res. Similarly ~d&s == s. So the simplified + * result is: */ + bc = res | s; + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +static uint16_t +neg_word(struct X86EMU *emu, uint16_t s) +{ + uint16_t res; + uint16_t bc; + + CONDITIONAL_SET_FLAG(s != 0, F_CF); + res = (uint16_t) - s; + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain --- modified such that d=0. + * substitutiing d=0 into bc= res&(~d|s)|(~d&s); (the one used for + * sub) and simplifying, since ~d=0xff..., ~d|s == 0xffff..., and + * res&0xfff... == res. Similarly ~d&s == s. So the simplified + * result is: */ + bc = res | s; + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +static uint32_t +neg_long(struct X86EMU *emu, uint32_t s) +{ + uint32_t res; + uint32_t bc; + + CONDITIONAL_SET_FLAG(s != 0, F_CF); + res = (uint32_t) - s; + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain --- modified such that d=0. + * substitutiing d=0 into bc= res&(~d|s)|(~d&s); (the one used for + * sub) and simplifying, since ~d=0xff..., ~d|s == 0xffff..., and + * res&0xfff... == res. Similarly ~d&s == s. So the simplified + * result is: */ + bc = res | s; + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} +/**************************************************************************** +REMARKS: +Implements the RCL instruction and side effects. +****************************************************************************/ +static uint8_t +rcl_byte(struct X86EMU *emu, uint8_t d, uint8_t s) +{ + unsigned int res, cnt, mask, cf; + + /* s is the rotate distance. It varies from 0 - 8. */ + /* have + * + * CF B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 + * + * want to rotate through the carry by "s" bits. We could loop, but + * that's inefficient. So the width is 9, and we split into three + * parts: + * + * The new carry flag (was B_n) the stuff in B_n-1 .. B_0 the stuff in + * B_7 .. B_n+1 + * + * The new rotate is done mod 9, and given this, for a rotation of n bits + * (mod 9) the new carry flag is then located n bits from the MSB. + * The low part is then shifted up cnt bits, and the high part is or'd + * in. Using CAPS for new values, and lowercase for the original + * values, this can be expressed as: + * + * IF n > 0 1) CF <- b_(8-n) 2) B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 + * 3) B_(n-1) <- cf 4) B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) */ + res = d; + if ((cnt = s % 9) != 0) { + /* extract the new CARRY FLAG. */ + /* CF <- b_(8-n) */ + cf = (d >> (8 - cnt)) & 0x1; + + /* get the low stuff which rotated into the range B_7 .. B_cnt */ + /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 */ + /* note that the right hand side done by the mask */ + res = (d << cnt) & 0xff; + + /* now the high stuff which rotated around into the positions + * B_cnt-2 .. B_0 */ + /* B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) */ + /* shift it downward, 7-(n-2) = 9-n positions. and mask off + * the result before or'ing in. */ + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (9 - cnt)) & mask; + + /* if the carry flag was set, or it in. */ + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + /* B_(n-1) <- cf */ + res |= 1 << (cnt - 1); + } + /* set the new carry flag, based on the variable "cf" */ + CONDITIONAL_SET_FLAG(cf, F_CF); + /* OVERFLOW is set *IFF* cnt==1, then it is the xor of CF and + * the most significant bit. Blecck. */ + /* parenthesized this expression since it appears to be + * causing OF to be misset */ + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 6) & 0x2)), + F_OF); + + } + return (uint8_t) res; +} +/**************************************************************************** +REMARKS: +Implements the RCL instruction and side effects. +****************************************************************************/ +static uint16_t +rcl_word(struct X86EMU *emu, uint16_t d, uint8_t s) +{ + unsigned int res, cnt, mask, cf; + + res = d; + if ((cnt = s % 17) != 0) { + cf = (d >> (16 - cnt)) & 0x1; + res = (d << cnt) & 0xffff; + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (17 - cnt)) & mask; + if (ACCESS_FLAG(F_CF)) { + res |= 1 << (cnt - 1); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 14) & 0x2)), + F_OF); + } + return (uint16_t) res; +} +/**************************************************************************** +REMARKS: +Implements the RCL instruction and side effects. +****************************************************************************/ +static uint32_t +rcl_long(struct X86EMU *emu, uint32_t d, uint8_t s) +{ + uint32_t res, cnt, mask, cf; + + res = d; + if ((cnt = s % 33) != 0) { + cf = (d >> (32 - cnt)) & 0x1; + res = (d << cnt) & 0xffffffff; + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (33 - cnt)) & mask; + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + res |= 1 << (cnt - 1); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 30) & 0x2)), + F_OF); + } + return res; +} +/**************************************************************************** +REMARKS: +Implements the RCR instruction and side effects. +****************************************************************************/ +static uint8_t +rcr_byte(struct X86EMU *emu, uint8_t d, uint8_t s) +{ + uint32_t res, cnt; + uint32_t mask, cf, ocf = 0; + + /* rotate right through carry */ + /* s is the rotate distance. It varies from 0 - 8. d is the byte + * object rotated. + * + * have + * + * CF B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 + * + * The new rotate is done mod 9, and given this, for a rotation of n bits + * (mod 9) the new carry flag is then located n bits from the LSB. + * The low part is then shifted up cnt bits, and the high part is or'd + * in. Using CAPS for new values, and lowercase for the original + * values, this can be expressed as: + * + * IF n > 0 1) CF <- b_(n-1) 2) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) + * 3) B_(8-n) <- cf 4) B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) */ + res = d; + if ((cnt = s % 9) != 0) { + /* extract the new CARRY FLAG. */ + /* CF <- b_(n-1) */ + if (cnt == 1) { + cf = d & 0x1; + /* note hackery here. Access_flag(..) evaluates to + * either 0 if flag not set non-zero if flag is set. + * doing access_flag(..) != 0 casts that into either + * 0..1 in any representation of the flags register + * (i.e. packed bit array or unpacked.) */ + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + + /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_n */ + /* note that the right hand side done by the mask This is + * effectively done by shifting the object to the right. The + * result must be masked, in case the object came in and was + * treated as a negative number. Needed??? */ + + mask = (1 << (8 - cnt)) - 1; + res = (d >> cnt) & mask; + + /* now the high stuff which rotated around into the positions + * B_cnt-2 .. B_0 */ + /* B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) */ + /* shift it downward, 7-(n-2) = 9-n positions. and mask off + * the result before or'ing in. */ + res |= (d << (9 - cnt)); + + /* if the carry flag was set, or it in. */ + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + /* B_(8-n) <- cf */ + res |= 1 << (8 - cnt); + } + /* set the new carry flag, based on the variable "cf" */ + CONDITIONAL_SET_FLAG(cf, F_CF); + /* OVERFLOW is set *IFF* cnt==1, then it is the xor of CF and + * the most significant bit. Blecck. */ + /* parenthesized... */ + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 6) & 0x2)), + F_OF); + } + } + return (uint8_t) res; +} +/**************************************************************************** +REMARKS: +Implements the RCR instruction and side effects. +****************************************************************************/ +static uint16_t +rcr_word(struct X86EMU *emu, uint16_t d, uint8_t s) +{ + uint32_t res, cnt; + uint32_t mask, cf, ocf = 0; + + /* rotate right through carry */ + res = d; + if ((cnt = s % 17) != 0) { + if (cnt == 1) { + cf = d & 0x1; + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + mask = (1 << (16 - cnt)) - 1; + res = (d >> cnt) & mask; + res |= (d << (17 - cnt)); + if (ACCESS_FLAG(F_CF)) { + res |= 1 << (16 - cnt); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 14) & 0x2)), + F_OF); + } + } + return (uint16_t) res; +} +/**************************************************************************** +REMARKS: +Implements the RCR instruction and side effects. +****************************************************************************/ +static uint32_t +rcr_long(struct X86EMU *emu, uint32_t d, uint8_t s) +{ + uint32_t res, cnt; + uint32_t mask, cf, ocf = 0; + + /* rotate right through carry */ + res = d; + if ((cnt = s % 33) != 0) { + if (cnt == 1) { + cf = d & 0x1; + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + mask = (1 << (32 - cnt)) - 1; + res = (d >> cnt) & mask; + if (cnt != 1) + res |= (d << (33 - cnt)); + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + res |= 1 << (32 - cnt); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 30) & 0x2)), + F_OF); + } + } + return res; +} +/**************************************************************************** +REMARKS: +Implements the ROL instruction and side effects. +****************************************************************************/ +static uint8_t +rol_byte(struct X86EMU *emu, uint8_t d, uint8_t s) +{ + unsigned int res, cnt, mask; + + /* rotate left */ + /* s is the rotate distance. It varies from 0 - 8. d is the byte + * object rotated. + * + * have + * + * CF B_7 ... B_0 + * + * The new rotate is done mod 8. Much simpler than the "rcl" or "rcr" + * operations. + * + * IF n > 0 1) B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) 2) B_(n-1) .. + * B_(0) <- b_(7) .. b_(8-n) */ + res = d; + if ((cnt = s % 8) != 0) { + /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) */ + res = (d << cnt); + + /* B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) */ + mask = (1 << cnt) - 1; + res |= (d >> (8 - cnt)) & mask; + + /* set the new carry flag, Note that it is the low order bit + * of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + /* OVERFLOW is set *IFF* s==1, then it is the xor of CF and + * the most significant bit. Blecck. */ + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 6) & 0x2)), + F_OF); + } if (s != 0) { + /* set the new carry flag, Note that it is the low order bit + * of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + } + return (uint8_t) res; +} +/**************************************************************************** +REMARKS: +Implements the ROL instruction and side effects. +****************************************************************************/ +static uint16_t +rol_word(struct X86EMU *emu, uint16_t d, uint8_t s) +{ + unsigned int res, cnt, mask; + + res = d; + if ((cnt = s % 16) != 0) { + res = (d << cnt); + mask = (1 << cnt) - 1; + res |= (d >> (16 - cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 14) & 0x2)), + F_OF); + } if (s != 0) { + /* set the new carry flag, Note that it is the low order bit + * of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + } + return (uint16_t) res; +} +/**************************************************************************** +REMARKS: +Implements the ROL instruction and side effects. +****************************************************************************/ +static uint32_t +rol_long(struct X86EMU *emu, uint32_t d, uint8_t s) +{ + uint32_t res, cnt, mask; + + res = d; + if ((cnt = s % 32) != 0) { + res = (d << cnt); + mask = (1 << cnt) - 1; + res |= (d >> (32 - cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 30) & 0x2)), + F_OF); + } if (s != 0) { + /* set the new carry flag, Note that it is the low order bit + * of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + } + return res; +} +/**************************************************************************** +REMARKS: +Implements the ROR instruction and side effects. +****************************************************************************/ +static uint8_t +ror_byte(struct X86EMU *emu, uint8_t d, uint8_t s) +{ + unsigned int res, cnt, mask; + + /* rotate right */ + /* s is the rotate distance. It varies from 0 - 8. d is the byte + * object rotated. + * + * have + * + * B_7 ... B_0 + * + * The rotate is done mod 8. + * + * IF n > 0 1) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) 2) B_(7) .. + * B_(8-n) <- b_(n-1) .. b_(0) */ + res = d; + if ((cnt = s % 8) != 0) { /* not a typo, do nada if cnt==0 */ + /* B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) */ + res = (d << (8 - cnt)); + + /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) */ + mask = (1 << (8 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + + /* set the new carry flag, Note that it is the low order bit + * of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80, F_CF); + /* OVERFLOW is set *IFF* s==1, then it is the xor of the two + * most significant bits. Blecck. */ + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 6), F_OF); + } else if (s != 0) { + /* set the new carry flag, Note that it is the low order bit + * of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80, F_CF); + } + return (uint8_t) res; +} +/**************************************************************************** +REMARKS: +Implements the ROR instruction and side effects. +****************************************************************************/ +static uint16_t +ror_word(struct X86EMU *emu, uint16_t d, uint8_t s) +{ + unsigned int res, cnt, mask; + + res = d; + if ((cnt = s % 16) != 0) { + res = (d << (16 - cnt)); + mask = (1 << (16 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 14), F_OF); + } else if (s != 0) { + /* set the new carry flag, Note that it is the low order bit + * of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); + } + return (uint16_t) res; +} +/**************************************************************************** +REMARKS: +Implements the ROR instruction and side effects. +****************************************************************************/ +static uint32_t +ror_long(struct X86EMU *emu, uint32_t d, uint8_t s) +{ + uint32_t res, cnt, mask; + + res = d; + if ((cnt = s % 32) != 0) { + res = (d << (32 - cnt)); + mask = (1 << (32 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 30), F_OF); + } else if (s != 0) { + /* set the new carry flag, Note that it is the low order bit + * of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); + } + return res; +} +/**************************************************************************** +REMARKS: +Implements the SHL instruction and side effects. +****************************************************************************/ +static uint8_t +shl_byte(struct X86EMU *emu, uint8_t d, uint8_t s) +{ + unsigned int cnt, res, cf; + + if (s < 8) { + cnt = s % 8; + + /* last bit shifted out goes into carry flag */ + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (8 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = (uint8_t) d; + } + + if (cnt == 1) { + /* Needs simplification. */ + CONDITIONAL_SET_FLAG( + (((res & 0x80) == 0x80) ^ + (ACCESS_FLAG(F_CF) != 0)), + /* was (emu->x86.R_FLG&F_CF)==F_CF)), */ + F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s - 1)) & 0x80, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (uint8_t) res; +} +/**************************************************************************** +REMARKS: +Implements the SHL instruction and side effects. +****************************************************************************/ +static uint16_t +shl_word(struct X86EMU *emu, uint16_t d, uint8_t s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = (uint16_t) d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG( + (((res & 0x8000) == 0x8000) ^ + (ACCESS_FLAG(F_CF) != 0)), + F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s - 1)) & 0x8000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (uint16_t) res; +} +/**************************************************************************** +REMARKS: +Implements the SHL instruction and side effects. +****************************************************************************/ +static uint32_t +shl_long(struct X86EMU *emu, uint32_t d, uint8_t s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s - 1)) & 0x80000000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return res; +} +/**************************************************************************** +REMARKS: +Implements the SHR instruction and side effects. +****************************************************************************/ +static uint8_t +shr_byte(struct X86EMU *emu, uint8_t d, uint8_t s) +{ + unsigned int cnt, res, cf; + + if (s < 8) { + cnt = s % 8; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = (uint8_t) d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 6), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d >> (s - 1)) & 0x1, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (uint8_t) res; +} +/**************************************************************************** +REMARKS: +Implements the SHR instruction and side effects. +****************************************************************************/ +static uint16_t +shr_word(struct X86EMU *emu, uint16_t d, uint8_t s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return (uint16_t) res; +} +/**************************************************************************** +REMARKS: +Implements the SHR instruction and side effects. +****************************************************************************/ +static uint32_t +shr_long(struct X86EMU *emu, uint32_t d, uint8_t s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return res; +} +/**************************************************************************** +REMARKS: +Implements the SAR instruction and side effects. +****************************************************************************/ +static uint8_t +sar_byte(struct X86EMU *emu, uint8_t d, uint8_t s) +{ + unsigned int cnt, res, cf, mask, sf; + + res = d; + sf = d & 0x80; + cnt = s % 8; + if (cnt > 0 && cnt < 8) { + mask = (1 << (8 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + } else if (cnt >= 8) { + if (sf) { + res = 0xff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + } + return (uint8_t) res; +} +/**************************************************************************** +REMARKS: +Implements the SAR instruction and side effects. +****************************************************************************/ +static uint16_t +sar_word(struct X86EMU *emu, uint16_t d, uint8_t s) +{ + unsigned int cnt, res, cf, mask, sf; + + sf = d & 0x8000; + cnt = s % 16; + res = d; + if (cnt > 0 && cnt < 16) { + mask = (1 << (16 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else if (cnt >= 16) { + if (sf) { + res = 0xffff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + } + return (uint16_t) res; +} +/**************************************************************************** +REMARKS: +Implements the SAR instruction and side effects. +****************************************************************************/ +static uint32_t +sar_long(struct X86EMU *emu, uint32_t d, uint8_t s) +{ + uint32_t cnt, res, cf, mask, sf; + + sf = d & 0x80000000; + cnt = s % 32; + res = d; + if (cnt > 0 && cnt < 32) { + mask = (1 << (32 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else if (cnt >= 32) { + if (sf) { + res = 0xffffffff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + } + return res; +} +/**************************************************************************** +REMARKS: +Implements the SHLD instruction and side effects. +****************************************************************************/ +static uint16_t +shld_word(struct X86EMU *emu, uint16_t d, uint16_t fill, uint8_t s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + res = (d << cnt) | (fill >> (16 - cnt)); + cf = d & (1 << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x8000) == 0x8000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s - 1)) & 0x8000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (uint16_t) res; +} +/**************************************************************************** +REMARKS: +Implements the SHLD instruction and side effects. +****************************************************************************/ +static uint32_t +shld_long(struct X86EMU *emu, uint32_t d, uint32_t fill, uint8_t s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + res = (d << cnt) | (fill >> (32 - cnt)); + cf = d & (1 << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s - 1)) & 0x80000000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return res; +} +/**************************************************************************** +REMARKS: +Implements the SHRD instruction and side effects. +****************************************************************************/ +static uint16_t +shrd_word(struct X86EMU *emu, uint16_t d, uint16_t fill, uint8_t s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) | (fill << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return (uint16_t) res; +} +/**************************************************************************** +REMARKS: +Implements the SHRD instruction and side effects. +****************************************************************************/ +static uint32_t +shrd_long(struct X86EMU *emu, uint32_t d, uint32_t fill, uint8_t s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) | (fill << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return res; +} +/**************************************************************************** +REMARKS: +Implements the SBB instruction and side effects. +****************************************************************************/ +static uint8_t +sbb_byte(struct X86EMU *emu, uint8_t d, uint8_t s) +{ + uint32_t res; /* all operands in native machine order */ + uint32_t bc; + + if (ACCESS_FLAG(F_CF)) + res = d - s - 1; + else + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (uint8_t) res; +} +/**************************************************************************** +REMARKS: +Implements the SBB instruction and side effects. +****************************************************************************/ +static uint16_t +sbb_word(struct X86EMU *emu, uint16_t d, uint16_t s) +{ + uint32_t res; /* all operands in native machine order */ + uint32_t bc; + + if (ACCESS_FLAG(F_CF)) + res = d - s - 1; + else + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (uint16_t) res; +} +/**************************************************************************** +REMARKS: +Implements the SBB instruction and side effects. +****************************************************************************/ +static uint32_t +sbb_long(struct X86EMU *emu, uint32_t d, uint32_t s) +{ + uint32_t res; /* all operands in native machine order */ + uint32_t bc; + + if (ACCESS_FLAG(F_CF)) + res = d - s - 1; + else + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} +/**************************************************************************** +REMARKS: +Implements the SUB instruction and side effects. +****************************************************************************/ +static uint8_t +sub_byte(struct X86EMU *emu, uint8_t d, uint8_t s) +{ + uint32_t res; /* all operands in native machine order */ + uint32_t bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (uint8_t) res; +} +/**************************************************************************** +REMARKS: +Implements the SUB instruction and side effects. +****************************************************************************/ +static uint16_t +sub_word(struct X86EMU *emu, uint16_t d, uint16_t s) +{ + uint32_t res; /* all operands in native machine order */ + uint32_t bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (uint16_t) res; +} +/**************************************************************************** +REMARKS: +Implements the SUB instruction and side effects. +****************************************************************************/ +static uint32_t +sub_long(struct X86EMU *emu, uint32_t d, uint32_t s) +{ + uint32_t res; /* all operands in native machine order */ + uint32_t bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} +/**************************************************************************** +REMARKS: +Implements the TEST instruction and side effects. +****************************************************************************/ +static void +test_byte(struct X86EMU *emu, uint8_t d, uint8_t s) +{ + uint32_t res; /* all operands in native machine order */ + + res = d & s; + + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + /* AF == dont care */ + CLEAR_FLAG(F_CF); +} +/**************************************************************************** +REMARKS: +Implements the TEST instruction and side effects. +****************************************************************************/ +static void +test_word(struct X86EMU *emu, uint16_t d, uint16_t s) +{ + uint32_t res; /* all operands in native machine order */ + + res = d & s; + + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + /* AF == dont care */ + CLEAR_FLAG(F_CF); +} +/**************************************************************************** +REMARKS: +Implements the TEST instruction and side effects. +****************************************************************************/ +static void +test_long(struct X86EMU *emu, uint32_t d, uint32_t s) +{ + uint32_t res; /* all operands in native machine order */ + + res = d & s; + + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + /* AF == dont care */ + CLEAR_FLAG(F_CF); +} +/**************************************************************************** +REMARKS: +Implements the XOR instruction and side effects. +****************************************************************************/ +static uint8_t +xor_byte(struct X86EMU *emu, uint8_t d, uint8_t s) +{ + uint8_t res; /* all operands in native machine order */ + + res = d ^ s; + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + return res; +} +/**************************************************************************** +REMARKS: +Implements the XOR instruction and side effects. +****************************************************************************/ +static uint16_t +xor_word(struct X86EMU *emu, uint16_t d, uint16_t s) +{ + uint16_t res; /* all operands in native machine order */ + + res = d ^ s; + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + return res; +} +/**************************************************************************** +REMARKS: +Implements the XOR instruction and side effects. +****************************************************************************/ +static uint32_t +xor_long(struct X86EMU *emu, uint32_t d, uint32_t s) +{ + uint32_t res; /* all operands in native machine order */ + + res = d ^ s; + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + return res; +} +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +static void +imul_byte(struct X86EMU *emu, uint8_t s) +{ + int16_t res = (int16_t) ((int8_t) emu->x86.R_AL * (int8_t) s); + + emu->x86.R_AX = res; + if (((emu->x86.R_AL & 0x80) == 0 && emu->x86.R_AH == 0x00) || + ((emu->x86.R_AL & 0x80) != 0 && emu->x86.R_AH == 0xFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +static void +imul_word(struct X86EMU *emu, uint16_t s) +{ + int32_t res = (int16_t) emu->x86.R_AX * (int16_t) s; + + emu->x86.R_AX = (uint16_t) res; + emu->x86.R_DX = (uint16_t) (res >> 16); + if (((emu->x86.R_AX & 0x8000) == 0 && emu->x86.R_DX == 0x00) || + ((emu->x86.R_AX & 0x8000) != 0 && emu->x86.R_DX == 0xFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +static void +imul_long(struct X86EMU *emu, uint32_t s) +{ + int64_t res; + + res = (int64_t)(int32_t)emu->x86.R_EAX * (int32_t)s; + emu->x86.R_EAX = (uint32_t)res; + emu->x86.R_EDX = ((uint64_t)res) >> 32; + if (((emu->x86.R_EAX & 0x80000000) == 0 && emu->x86.R_EDX == 0x00) || + ((emu->x86.R_EAX & 0x80000000) != 0 && emu->x86.R_EDX == 0xFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} +/**************************************************************************** +REMARKS: +Implements the MUL instruction and side effects. +****************************************************************************/ +static void +mul_byte(struct X86EMU *emu, uint8_t s) +{ + uint16_t res = (uint16_t) (emu->x86.R_AL * s); + + emu->x86.R_AX = res; + if (emu->x86.R_AH == 0) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} +/**************************************************************************** +REMARKS: +Implements the MUL instruction and side effects. +****************************************************************************/ +static void +mul_word(struct X86EMU *emu, uint16_t s) +{ + uint32_t res = emu->x86.R_AX * s; + + emu->x86.R_AX = (uint16_t) res; + emu->x86.R_DX = (uint16_t) (res >> 16); + if (emu->x86.R_DX == 0) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} +/**************************************************************************** +REMARKS: +Implements the MUL instruction and side effects. +****************************************************************************/ +static void +mul_long(struct X86EMU *emu, uint32_t s) +{ + uint64_t res = (uint64_t) emu->x86.R_EAX * s; + + emu->x86.R_EAX = (uint32_t) res; + emu->x86.R_EDX = (uint32_t) (res >> 32); + + if (emu->x86.R_EDX == 0) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} +/**************************************************************************** +REMARKS: +Implements the IDIV instruction and side effects. +****************************************************************************/ +static void +idiv_byte(struct X86EMU *emu, uint8_t s) +{ + int32_t dvd, div, mod; + + dvd = (int16_t) emu->x86.R_AX; + if (s == 0) { + x86emu_intr_raise(emu, 8); + return; + } + div = dvd / (int8_t) s; + mod = dvd % (int8_t) s; + if (div > 0x7f || div < -0x7f) { + x86emu_intr_raise(emu, 8); + return; + } + emu->x86.R_AL = (int8_t) div; + emu->x86.R_AH = (int8_t) mod; +} +/**************************************************************************** +REMARKS: +Implements the IDIV instruction and side effects. +****************************************************************************/ +static void +idiv_word(struct X86EMU *emu, uint16_t s) +{ + int32_t dvd, div, mod; + + dvd = (((int32_t) emu->x86.R_DX) << 16) | emu->x86.R_AX; + if (s == 0) { + x86emu_intr_raise(emu, 8); + return; + } + div = dvd / (int16_t) s; + mod = dvd % (int16_t) s; + if (div > 0x7fff || div < -0x7fff) { + x86emu_intr_raise(emu, 8); + return; + } + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(div == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + emu->x86.R_AX = (uint16_t) div; + emu->x86.R_DX = (uint16_t) mod; +} + + +/**************************************************************************** +REMARKS: +Implements the IDIV instruction and side effects. +****************************************************************************/ +static void +idiv_long(struct X86EMU *emu, uint32_t s) +{ + int64_t dvd, div, mod; + + dvd = (((int64_t) emu->x86.R_EDX) << 32) | emu->x86.R_EAX; + if (s == 0) { + x86emu_intr_raise(emu, 8); + return; + } + div = dvd / (int32_t) s; + mod = dvd % (int32_t) s; + if (div > 0x7fffffff || div < -0x7fffffff) { + x86emu_intr_raise(emu, 8); + return; + } + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + emu->x86.R_EAX = (uint32_t) div; + emu->x86.R_EDX = (uint32_t) mod; +} +/**************************************************************************** +REMARKS: +Implements the DIV instruction and side effects. +****************************************************************************/ +static void +div_byte(struct X86EMU *emu, uint8_t s) +{ + uint32_t dvd, div, mod; + + dvd = emu->x86.R_AX; + if (s == 0) { + x86emu_intr_raise(emu, 8); + return; + } + div = dvd / (uint8_t) s; + mod = dvd % (uint8_t) s; + if (div > 0xff) { + x86emu_intr_raise(emu, 8); + return; + } + emu->x86.R_AL = (uint8_t) div; + emu->x86.R_AH = (uint8_t) mod; +} +/**************************************************************************** +REMARKS: +Implements the DIV instruction and side effects. +****************************************************************************/ +static void +div_word(struct X86EMU *emu, uint16_t s) +{ + uint32_t dvd, div, mod; + + dvd = (((uint32_t) emu->x86.R_DX) << 16) | emu->x86.R_AX; + if (s == 0) { + x86emu_intr_raise(emu, 8); + return; + } + div = dvd / (uint16_t) s; + mod = dvd % (uint16_t) s; + if (div > 0xffff) { + x86emu_intr_raise(emu, 8); + return; + } + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(div == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + emu->x86.R_AX = (uint16_t) div; + emu->x86.R_DX = (uint16_t) mod; +} +/**************************************************************************** +REMARKS: +Implements the DIV instruction and side effects. +****************************************************************************/ +static void +div_long(struct X86EMU *emu, uint32_t s) +{ + uint64_t dvd, div, mod; + + dvd = (((uint64_t) emu->x86.R_EDX) << 32) | emu->x86.R_EAX; + if (s == 0) { + x86emu_intr_raise(emu, 8); + return; + } + div = dvd / (uint32_t) s; + mod = dvd % (uint32_t) s; + if (div > 0xffffffff) { + x86emu_intr_raise(emu, 8); + return; + } + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + emu->x86.R_EAX = (uint32_t) div; + emu->x86.R_EDX = (uint32_t) mod; +} +/**************************************************************************** +REMARKS: +Implements the IN string instruction and side effects. +****************************************************************************/ +static void +ins(struct X86EMU *emu, int size) +{ + int inc = size; + + if (ACCESS_FLAG(F_DF)) { + inc = -size; + } + if (emu->x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* in until CX is ZERO. */ + uint32_t count = ((emu->x86.mode & SYSMODE_PREFIX_DATA) ? + emu->x86.R_ECX : emu->x86.R_CX); + switch (size) { + case 1: + while (count--) { + store_byte(emu, emu->x86.R_ES, emu->x86.R_DI, + (*emu->emu_inb) (emu, emu->x86.R_DX)); + emu->x86.R_DI += inc; + } + break; + + case 2: + while (count--) { + store_word(emu, emu->x86.R_ES, emu->x86.R_DI, + (*emu->emu_inw) (emu, emu->x86.R_DX)); + emu->x86.R_DI += inc; + } + break; + case 4: + while (count--) { + store_long(emu, emu->x86.R_ES, emu->x86.R_DI, + (*emu->emu_inl) (emu, emu->x86.R_DX)); + emu->x86.R_DI += inc; + break; + } + } + emu->x86.R_CX = 0; + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + emu->x86.R_ECX = 0; + } + emu->x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + switch (size) { + case 1: + store_byte(emu, emu->x86.R_ES, emu->x86.R_DI, + (*emu->emu_inb) (emu, emu->x86.R_DX)); + break; + case 2: + store_word(emu, emu->x86.R_ES, emu->x86.R_DI, + (*emu->emu_inw) (emu, emu->x86.R_DX)); + break; + case 4: + store_long(emu, emu->x86.R_ES, emu->x86.R_DI, + (*emu->emu_inl) (emu, emu->x86.R_DX)); + break; + } + emu->x86.R_DI += inc; + } +} +/**************************************************************************** +REMARKS: +Implements the OUT string instruction and side effects. +****************************************************************************/ +static void +outs(struct X86EMU *emu, int size) +{ + int inc = size; + + if (ACCESS_FLAG(F_DF)) { + inc = -size; + } + if (emu->x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* out until CX is ZERO. */ + uint32_t count = ((emu->x86.mode & SYSMODE_PREFIX_DATA) ? + emu->x86.R_ECX : emu->x86.R_CX); + switch (size) { + case 1: + while (count--) { + (*emu->emu_outb) (emu, emu->x86.R_DX, + fetch_byte(emu, emu->x86.R_ES, emu->x86.R_SI)); + emu->x86.R_SI += inc; + } + break; + + case 2: + while (count--) { + (*emu->emu_outw) (emu, emu->x86.R_DX, + fetch_word(emu, emu->x86.R_ES, emu->x86.R_SI)); + emu->x86.R_SI += inc; + } + break; + case 4: + while (count--) { + (*emu->emu_outl) (emu, emu->x86.R_DX, + fetch_long(emu, emu->x86.R_ES, emu->x86.R_SI)); + emu->x86.R_SI += inc; + break; + } + } + emu->x86.R_CX = 0; + if (emu->x86.mode & SYSMODE_PREFIX_DATA) { + emu->x86.R_ECX = 0; + } + emu->x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + switch (size) { + case 1: + (*emu->emu_outb) (emu, emu->x86.R_DX, + fetch_byte(emu, emu->x86.R_ES, emu->x86.R_SI)); + break; + case 2: + (*emu->emu_outw) (emu, emu->x86.R_DX, + fetch_word(emu, emu->x86.R_ES, emu->x86.R_SI)); + break; + case 4: + (*emu->emu_outl) (emu, emu->x86.R_DX, + fetch_long(emu, emu->x86.R_ES, emu->x86.R_SI)); + break; + } + emu->x86.R_SI += inc; + } +} +/**************************************************************************** +REMARKS: +Pushes a word onto the stack. + +NOTE: Do not inline this, as (*emu->emu_wrX) is already inline! +****************************************************************************/ +static void +push_word(struct X86EMU *emu, uint16_t w) +{ + emu->x86.R_SP -= 2; + store_word(emu, emu->x86.R_SS, emu->x86.R_SP, w); +} +/**************************************************************************** +REMARKS: +Pushes a long onto the stack. + +NOTE: Do not inline this, as (*emu->emu_wrX) is already inline! +****************************************************************************/ +static void +push_long(struct X86EMU *emu, uint32_t w) +{ + emu->x86.R_SP -= 4; + store_long(emu, emu->x86.R_SS, emu->x86.R_SP, w); +} +/**************************************************************************** +REMARKS: +Pops a word from the stack. + +NOTE: Do not inline this, as (*emu->emu_rdX) is already inline! +****************************************************************************/ +static uint16_t +pop_word(struct X86EMU *emu) +{ + uint16_t res; + + res = fetch_word(emu, emu->x86.R_SS, emu->x86.R_SP); + emu->x86.R_SP += 2; + return res; +} +/**************************************************************************** +REMARKS: +Pops a long from the stack. + +NOTE: Do not inline this, as (*emu->emu_rdX) is already inline! +****************************************************************************/ +static uint32_t +pop_long(struct X86EMU *emu) +{ + uint32_t res; + + res = fetch_long(emu, emu->x86.R_SS, emu->x86.R_SP); + emu->x86.R_SP += 4; + return res; +} diff --git a/x86emu/x86emu_util.c b/x86emu/x86emu_util.c new file mode 100644 index 0000000..a0e5f86 --- /dev/null +++ b/x86emu/x86emu_util.c @@ -0,0 +1,201 @@ +/* $NetBSD: x86emu_util.c,v 1.1 2007/11/30 20:02:50 joerg Exp $ */ + +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* Copyright (C) 2007 Joerg Sonnenberger +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +****************************************************************************/ + +#include "x86emu.h" +#include "x86emu_regs.h" + +// #define DEBUG +#include "debug.h" + +static __inline uint16_t le16dec(const void *buf) +{ + const uint8_t *p = (uint8_t *) buf; + + return ((p[1] << 8) | p[0]); +} + +static __inline uint32_t le32dec(const void *buf) +{ + const uint8_t *p = (uint8_t *) buf; + + return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]); +} + +static __inline void le16enc(void *buf, uint16_t u) +{ + uint8_t *p = buf; + + p[0] = u & 0xff; + p[1] = ((unsigned) u >> 8) & 0xff; +} + +static __inline void le32enc(void *buf, uint32_t u) +{ + uint8_t *p = buf; + + p[0] = u & 0xff; + p[1] = (u >> 8) & 0xff; + p[2] = (u >> 16) & 0xff; + p[3] = (u >> 24) & 0xff; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Byte value read from emulator memory. + +REMARKS: +Reads a byte value from the emulator memory. +****************************************************************************/ +static uint8_t rdb(struct X86EMU *emu, uint32_t addr) +{ + if (addr > emu->mem_size - 1) + { + dbg("attempted read outside system memory: 0x%lx. Halt emulator.\r\n", addr); + X86EMU_halt_sys(emu); + } + return emu->mem_base[addr]; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Word value read from emulator memory. + +REMARKS: +Reads a word value from the emulator memory. +****************************************************************************/ +static uint16_t rdw(struct X86EMU *emu, uint32_t addr) +{ + if (addr > emu->mem_size - 2) + { + dbg("attempted read outside system memory: 0x%lx. Halt emulator.\r\n", addr); + X86EMU_halt_sys(emu); + } + return le16dec(emu->mem_base + addr); +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Long value read from emulator memory. +REMARKS: +Reads a long value from the emulator memory. +****************************************************************************/ +static uint32_t rdl(struct X86EMU *emu, uint32_t addr) +{ + if (addr > emu->mem_size - 4) + { + dbg("attempted read outside system memory: 0x%lx. Halt emulator.\r\n", addr); + X86EMU_halt_sys(emu); + } + return le32dec(emu->mem_base + addr); +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a byte value to emulator memory. +****************************************************************************/ +static void wrb(struct X86EMU *emu, uint32_t addr, uint8_t val) +{ + if (addr > emu->mem_size - 1) + { + dbg("attempted write outside system memory: 0x%lx (0x%02x). Halt emulator.\r\n", addr, val); + X86EMU_halt_sys(emu); + } + emu->mem_base[addr] = val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a word value to emulator memory. +****************************************************************************/ +static void wrw(struct X86EMU *emu, uint32_t addr, uint16_t val) +{ + if (addr > emu->mem_size - 2) + { + dbg("attempted write outside system memory: 0x%lx (0x%04x). Halt emulator\r\n", addr, val); + X86EMU_halt_sys(emu); + } + le16enc(emu->mem_base + addr, val); +} +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to write +val - Value to store + +REMARKS: +Writes a long value to emulator memory. +****************************************************************************/ +static void wrl(struct X86EMU *emu, uint32_t addr, uint32_t val) +{ + if (addr > emu->mem_size - 4) + { + dbg("attempted write outside system memory: 0x%lx (0x%08x)\r\n", addr, val); + X86EMU_halt_sys(emu); + } + le32enc(emu->mem_base + addr, val); +} + +/*----------------------------- Setup -------------------------------------*/ + +void X86EMU_init_default(struct X86EMU *emu) +{ + int i; + + emu->emu_rdb = rdb; + emu->emu_rdw = rdw; + emu->emu_rdl = rdl; + emu->emu_wrb = wrb; + emu->emu_wrw = wrw; + emu->emu_wrl = wrl; + + for (i = 0; i < 256; i++) + { + emu->_X86EMU_intrTab[i] = NULL; + } +} diff --git a/x86emu/x86pcibios.c b/x86emu/x86pcibios.c new file mode 100644 index 0000000..6042fdf --- /dev/null +++ b/x86emu/x86pcibios.c @@ -0,0 +1,171 @@ +#include "radeonfb.h" +#include "pci.h" +#include "x86emu.h" +#include "x86pcibios.h" +#include "x86emu_regs.h" +#include "bas_printf.h" + +extern unsigned short offset_port; + +// #define DEBUG +#include "debug.h" + +int x86_pcibios_handler(struct X86EMU *emu) +{ + int ret = 0; + unsigned long dev; + + switch (emu->x86.R_AX) + { + case PCI_BIOS_PRESENT: + dbg("PCI_BIOS_PRESENT\r\n"); + emu->x86.R_AH = 0x00; /* no config space/special cycle support */ + emu->x86.R_AL = 0x01; /* config mechanism 1 */ + emu->x86.R_EDX = 'P' | 'C' << 8 | 'I' << 16 | ' ' << 24; + emu->x86.R_EBX = 0x0210; /* Version 2.10 */ + emu->x86.R_ECX = 0xFF00; /* FixME: Max bus number */ + emu->x86.R_EFLG &= ~FB_CF; /* clear carry flag */ + ret = 1; + break; + + case FIND_PCI_DEVICE: + dbg("FIND_PCI_DEVICE vendor = %04x, device = %04x\r\n", emu->x86.R_DX, emu->x86.R_CX); + dev = pci_find_device((uintptr_t) emu->x86.R_DX, ((unsigned long) emu->x86.R_CX), 0); + + if (dev != 0) + { + dbg("dev = %d\r\n", dev); + emu->x86.R_BH = PCI_BUS_FROM_HANDLE(dev); + //X86_BH = (char)(dev >> 16) / PCI_MAX_FUNCTION); // dev->bus->secondary; + emu->x86.R_BL = PCI_DEVICE_FROM_HANDLE(dev) << 3 | PCI_FUNCTION_FROM_HANDLE(dev); + //X86_BL = (char)dev; // dev->path.u.pci.devfn; + emu->x86.R_AH = SUCCESSFUL; + emu->x86.R_EFLG &= ~FB_CF; /* clear carry flag */ + ret = 1; + } + else + { + dbg("device not found\r\n"); + emu->x86.R_AH = DEVICE_NOT_FOUND; + emu->x86.R_EFLG |= FB_CF; /* set carry flag */ + ret = 0; + } + break; + + case FIND_PCI_CLASS_CODE: + /* FixME: support SI != 0 */ + dbg("FIND_PCI_CLASS_CODE %x", emu->x86.R_ECX); + dev = pci_find_classcode(emu->x86.R_ECX, 0); + if (dev != 0) { + dbg(" ...OK\r\n"); + emu->x86.R_BH = PCI_BUS_FROM_HANDLE(dev); + emu->x86.R_BL = PCI_DEVICE_FROM_HANDLE(dev) << 3 | PCI_FUNCTION_FROM_HANDLE(dev); + emu->x86.R_AH = SUCCESSFUL; + emu->x86.R_EFLG &= ~FB_CF; /* clear carry flag */ + ret = 1; + } + else + { + dbg(" ... error\r\n"); + emu->x86.R_AH = DEVICE_NOT_FOUND; + emu->x86.R_EFLG |= FB_CF; /* set carry flag */ + ret = 0; + } + break; + + case READ_CONFIG_BYTE: + // bus, devfn + dbg("READ_CONFIG_BYTE bus = %x, devfn = %x, reg = %x\r\n", emu->x86.R_BH, emu->x86.R_BL, emu->x86.R_DI); + dev = PCI_HANDLE(emu->x86.R_BH, emu->x86.R_BL >> 3, emu->x86.R_BL & 7); + emu->x86.R_CL = pci_read_config_byte(dev, emu->x86.R_DI); + dbg("dev=0x%04x value = 0x%04x\r\n", emu->x86.R_CL); + emu->x86.R_AH = SUCCESSFUL; + emu->x86.R_EFLG &= ~FB_CF; /* clear carry flag */ + ret = 1; + break; + + case READ_CONFIG_WORD: + // bus, devfn + dbg("READ_CONFIG_WORD bus = %x, devfn = %x, reg = %x\r\n", emu->x86.R_BH, emu->x86.R_BL, emu->x86.R_DI); + dev = PCI_HANDLE(emu->x86.R_BH, emu->x86.R_BL >> 3, emu->x86.R_BL & 7); + if (emu->x86.R_DI == PCIBAR1) + emu->x86.R_CX = offset_port + 1; + else + emu->x86.R_CX = pci_read_config_word(dev, emu->x86.R_DI); + dbg("offset_port=0x%04x dev=0x%04x, value = %x\r\n", offset_port, dev, emu->x86.R_CX); + emu->x86.R_AH = SUCCESSFUL; + emu->x86.R_EFLG &= ~FB_CF; /* clear carry flag */ + ret = 1; + break; + + case READ_CONFIG_DWORD: + // bus, devfn + dbg("READ_CONFIG_DWORD bus = %x, devfn = %x, reg = %x\r\n", emu->x86.R_BH, emu->x86.R_BL, emu->x86.R_DI); + dev = PCI_HANDLE(emu->x86.R_BH, emu->x86.R_BL >> 3, emu->x86.R_BL & 7); + if (emu->x86.R_DI == PCIBAR1) + emu->x86.R_CX = (unsigned long) offset_port + 1; + else + emu->x86.R_ECX = pci_read_config_longword(dev, emu->x86.R_DI); + dbg("value = %x\r\n", emu->x86.R_ECX); + emu->x86.R_AH = SUCCESSFUL; + emu->x86.R_EFLG &= ~FB_CF; /* clear carry flag */ + ret = 1; + break; + + case WRITE_CONFIG_BYTE: + // bus, devfn + dbg("READ_CONFIG_BYTE bus = %x, devfn = %x, reg = %x, value = %x\r\n", + emu->x86.R_BH, emu->x86.R_BL, emu->x86.R_DI, emu->x86.R_CL); + dev = PCI_HANDLE(emu->x86.R_BH, emu->x86.R_BL >> 3, emu->x86.R_BL & 7); + pci_write_config_byte(dev, emu->x86.R_DI, emu->x86.R_CL); + emu->x86.R_AH = SUCCESSFUL; + emu->x86.R_EFLG &= ~FB_CF; /* clear carry flag */ + ret = 1; + break; + + case WRITE_CONFIG_WORD: + // bus, devfn + dev = PCI_HANDLE(emu->x86.R_BH, emu->x86.R_BL >> 3, emu->x86.R_BL & 7); + dbg("WRITE_CONFIG_WORD bus = %x, devfn = %x, reg = %x, value = %x\r\n", emu->x86.R_BH, emu->x86.R_BL, emu->x86.R_DI, emu->x86.R_CX); + if (emu->x86.R_DI == PCIBAR1) + { + offset_port = emu->x86.R_CX; + emu->x86.R_AH = SUCCESSFUL; + emu->x86.R_EFLG &= ~FB_CF; /* clear carry flag */ + ret = 1; + break; + } + pci_write_config_word(dev, emu->x86.R_DI, emu->x86.R_CX); + emu->x86.R_AH = SUCCESSFUL; + emu->x86.R_EFLG &= ~FB_CF; /* clear carry flag */ + ret = 1; + break; + + case WRITE_CONFIG_DWORD: + // bus, devfn + dev = PCI_HANDLE(emu->x86.R_BH, emu->x86.R_BL >> 3, emu->x86.R_BL & 7); + dbg("WRITE_CONFIG_DWORD bus = %x, devfn = %x, value = %x\r\n", + emu->x86.R_BH, emu->x86.R_BL, emu->x86.R_DI, emu->x86.R_ECX); + if (emu->x86.R_DI == PCIBAR1) + { + offset_port = (unsigned short) emu->x86.R_ECX & 0xFFFC; + emu->x86.R_AH = SUCCESSFUL; + emu->x86.R_EFLG &= ~FB_CF; /* clear carry flag */ + ret = 1; + break; + } + pci_write_config_longword(dev, emu->x86.R_DI, emu->x86.R_ECX); + emu->x86.R_AH = SUCCESSFUL; + emu->x86.R_EFLG &= ~FB_CF; /* clear carry flag */ + ret = 1; + break; + + default: + dbg("PCI_BIOS FUNC_NOT_SUPPORTED\r\n"); + emu->x86.R_AH = FUNC_NOT_SUPPORTED; + emu->x86.R_EFLG |= FB_CF; + break; + } + + return ret; +} diff --git a/xhdi/xhdi_interface.c b/xhdi/xhdi_interface.c new file mode 100644 index 0000000..3b41f8e --- /dev/null +++ b/xhdi/xhdi_interface.c @@ -0,0 +1,314 @@ +/* + * xhdi_sd.c + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 01.05.2013 + * Copyright 2012: M. Fröschle + */ + +#include +#include + +#include "xhdi_sd.h" +#include "bas_printf.h" + + +uint32_t xhdi_call(uint16_t *stack) +{ + uint16_t opcode = *stack; + + switch (opcode) + { + case XHDI_VERSION: + return xhdi_version(); + break; + + case XHDI_INQUIRE_TARGET: + { + struct XHINQTARGET_args + { + uint16_t opcode; + uint16_t major; + uint16_t minor; + uint32_t *blocksize; + uint32_t *deviceflags; + char *productname; + } *args = (struct XHINQTARGET_args *) stack; + + return xhdi_inquire_target(args->major, args->minor, args->blocksize, + args->deviceflags, args->productname); + } + break; + + case XHDI_RESERVE: + { + struct XHRESERVE_args + { + uint16_t opcode; + uint16_t major; + uint16_t minor; + uint16_t do_reserve; + uint16_t key; + } *args = (struct XHRESERVE_args *) stack; + + return xhdi_reserve(args->major, args->minor, args->do_reserve, args->key); + } + + case XHDI_LOCK: + { + struct XHLOCK_args + { + uint16_t opcode; + uint16_t major; + uint16_t minor; + uint16_t do_lock; + uint16_t key; + } *args = (struct XHLOCK_args *) stack; + + return xhdi_lock(args->major, args->minor, args->do_lock, args->key); + } + + case XHDI_STOP: + { + struct XHSTOP_args + { + uint16_t opcode; + uint16_t major; + uint16_t minor; + uint16_t do_stop; + uint16_t key; + } *args = (struct XHSTOP_args *) stack; + + return xhdi_stop(args->major, args->minor, args->do_stop, args->key); + } + + case XHDI_EJECT: + { + struct XHEJECT_args + { + uint16_t opcode; + uint16_t major; + uint16_t minor; + uint16_t do_eject; + uint16_t key; + } *args = (struct XHEJECT_args *) stack; + + return xhdi_eject(args->major, args->minor, args->do_eject, args->key); + } + + case XHDI_DRIVEMAP: + { + return xhdi_drivemap(); + } + + case XHDI_INQUIRE_DEVICE: + { + struct XHINQDEV_args + { + uint16_t opcode; + uint16_t drv; + uint16_t *major; + uint16_t *minor; + uint32_t *start; + BPB *bpb; + } *args = (struct XHINQDEV_args *) stack; + + return xhdi_inquire_device(args->drv, args->major, args->minor, args->start, + args->bpb); + } + + case XHDI_INQUIRE_DRIVER: + { + struct XHINQDRIVER_args + { + uint16_t opcode; + uint16_t dev; + char *name; + char *version; + char *company; + uint16_t *ahdi_version; + uint16_t *maxIPL; + } *args = (struct XHINQDRIVER_args *) stack; + + return xhdi_inquire_driver(args->dev, args->name, args->version, args->company, + args->ahdi_version, args->maxIPL); + } + + case XHDI_NEW_COOKIE: + { + struct XHNEWCOOKIE_args + { + uint16_t opcode; + uint32_t newcookie; + } *args = (struct XHNEWCOOKIE_args *) stack; + + return xhdi_new_cookie(args->newcookie); + } + + case XHDI_READ_WRITE: + { + struct XHREADWRITE_args + { + uint16_t opcode; + uint16_t major; + uint16_t minor; + uint16_t rw; + uint32_t sector; + uint16_t count; + void *buf; + } *args = (struct XHREADWRITE_args *) stack; + + return xhdi_read_write(args->major, args->minor, + args->rw, args->sector, + args->count, args->buf); + } + + case XHDI_INQUIRE_TARGET2: + { + struct XHINQTARGET2_args + { + uint16_t opcode; + uint16_t major; + uint16_t minor; + uint32_t *blocksize; + uint32_t *deviceflags; + char *productname; + uint16_t stringlen; + } *args = (struct XHINQTARGET2_args *) stack; + + return xhdi_inquire_target2(args->major, args->minor, args->blocksize, + args->deviceflags, args->productname, args->stringlen); + } + + case XHDI_INQUIRE_DEVICE2: + { + struct XHINQDEV2_args + { + uint16_t opcode; + uint16_t drv; + uint16_t *major; + uint16_t *minor; + uint32_t *start; + BPB *bpb; + uint32_t *blocks; + char *partid; + } *args = (struct XHINQDEV2_args *) stack; + + return xhdi_inquire_device2(args->drv, args->major, args->minor, args->start, + args->bpb, args->blocks, args->partid); + } + + case XHDI_DRIVER_SPECIAL: + { + struct XHDRIVERSPECIAL_args + { + uint16_t opcode; + uint32_t key1; + uint32_t key2; + uint16_t subopcode; + void *data; + } *args = (struct XHDRIVERSPECIAL_args *) stack; + + return xhdi_driver_special(args->key1, args->key2, args->subopcode, + args->data); + } + + case XHDI_GET_CAPACITY: + { + struct XHGETCAPACITY_args + { + uint16_t opcode; + uint16_t major; + uint16_t minor; + uint32_t *blocks; + uint32_t *blocksize; + } *args = (struct XHGETCAPACITY_args *) stack; + + return xhdi_get_capacity(args->major, args->minor, args->blocks, + args->blocksize); + } + + case XHDI_MEDIUM_CHANGED: + { + struct XHMEDIUMCHANGED_args + { + uint16_t opcode; + uint16_t major; + uint16_t minor; + } *args = (struct XHMEDIUMCHANGED_args *) stack; + + return xhdi_medium_changed(args->major, args->minor); + } + + case XHDI_MINT_INFO: + { + struct XHMINTINFO_args + { + uint16_t opcode; + uint16_t subopcode; + void *data; + } *args = (struct XHMINTINFO_args *) stack; + + return xhdi_mint_info(args->subopcode, args->data); + } + + case XHDI_DOS_LIMITS: + { + struct XHDOSLIMITS_args + { + uint16_t opcode; + uint16_t which; + uint32_t limit; + } *args = (struct XHDOSLIMITS_args *) stack; + + return xhdi_dos_limits(args->which, args->limit); + } + + case XHDI_LAST_ACCESS: + { + struct XHLASTACCESS_args + { + uint16_t opcode; + uint16_t major; + uint16_t minor; + uint32_t *ms; + } *args = (struct XHLASTACCESS_args *) stack; + + return xhdi_last_access(args->major, args->minor, args->ms); + } + + case XHDI_REACCESS: + { + struct XHREACCESS_args + { + uint16_t opcode; + uint16_t major; + uint16_t minor; + } *args = (struct XHREACCESS_args *) stack; + + return xhdi_reaccess(args->major, args->minor); + } + + default: + { + xprintf("unknown XHDI function 0x%x\r\n", opcode); + return EINVFN; + break; + } + } +} + diff --git a/xhdi/xhdi_sd.c b/xhdi/xhdi_sd.c new file mode 100644 index 0000000..a16567f --- /dev/null +++ b/xhdi/xhdi_sd.c @@ -0,0 +1,242 @@ +/* + * xhdi_sd.c + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 01.05.2013 + * Copyright 2012 M. Fröschle + */ + +#include +#include + +#include "xhdi_sd.h" +#include "bas_printf.h" +#include "bas_string.h" +#include "diskio.h" + +#define DRIVER_VERSION 0x130 + +#define MY_MAJOR 7 +#define MY_MINOR 0 + +uint16_t xhdi_version(void) +{ + return DRIVER_VERSION; +} + +uint32_t xhdi_inquire_target(uint16_t major, uint16_t minor, uint32_t *block_size, uint32_t *flags, + char *product_name) +{ + return xhdi_inquire_target2(major, minor, block_size, flags, product_name, 33); +} + +uint32_t xhdi_reserve(uint16_t major, uint16_t minor, uint16_t do_reserve, uint16_t key) +{ + if (major == MY_MAJOR) + return ERROR; /* device cannot be reserved */ + + return EUNDEV; +} + +uint32_t xhdi_lock(uint16_t major, uint16_t minor, uint16_t do_lock, uint16_t key) +{ + if (major == MY_MAJOR) + return ERROR; /* device cannot be locked */ + + return EUNDEV; +} + +uint32_t xhdi_stop(uint16_t major, uint16_t minor, uint16_t do_stop, uint16_t key) +{ + if (major == MY_MAJOR) + return ERROR; /* device cannot be locked */ + + return EUNDEV; +} + +uint32_t xhdi_eject(uint16_t major, uint16_t minor, uint16_t do_eject, uint16_t key) +{ + if (major == MY_MAJOR) + return ERROR; /* device cannot be ejected */ + + return EUNDEV; +} + +uint32_t xhdi_drivemap(void) +{ + long map = (1 << ('S' - 'A')); + + return map; +} + +uint32_t xhdi_inquire_device(uint16_t bios_device, uint16_t *major, uint16_t *minor, + uint32_t *start_sector, /* BPB */ void *bpb) +{ + if (major != NULL) *major = MY_MAJOR; + if (minor != NULL) *minor = MY_MINOR; + if (start_sector != NULL) *start_sector = 0; + + return E_OK; +} + +uint32_t xhdi_inquire_driver(uint16_t bios_device, char *name, char *version, + char *company, uint16_t *ahdi_version, uint16_t *maxIPL) +{ + if (bios_device == 'S' - 'A') + { + if (name != NULL) strcpy(name, "BaS SD-card driver"); + if (version != NULL) strcpy(version, "0.1"); + if (company != NULL) strcpy(company, "Markus Fröschle"); + if (ahdi_version != NULL) *ahdi_version = 300; + if (maxIPL != NULL) *maxIPL = 7; + + return E_OK; + } + return EUNDEV; +} + +uint32_t xhdi_new_cookie(uint32_t newcookie) +{ + return EUNDEV; +} + +uint32_t xhdi_read_write(uint16_t major, uint16_t minor, uint16_t rwflag, + uint32_t recno, uint16_t count, void *buf) +{ + int ret; + uint16_t num_sectors; + int16_t s_count = count; + uint16_t retries; + const uint16_t max_retries = 3; + + if (major == MY_MAJOR) + { + do { + num_sectors = ((s_count > 63) ? 63 : s_count); + + retries = 0; + do { + ret = ((rwflag & 1) ? disk_write(0, buf, recno, num_sectors) : disk_read(0, buf, recno, num_sectors)); + if (ret != RES_OK) + { + disk_reset(0); + retries++; + if (retries < max_retries) continue; + + xprintf("SD card %s error at sector %lx: %d\r\n", (rwflag & 1) ? "write" : "read", recno, ret); + return ERROR; + } + } while (retries < max_retries && ret != RES_OK); + + buf += num_sectors * 512; + recno += num_sectors; + s_count -= num_sectors; + } while (s_count > 0); + + return E_OK; + } + return EUNDEV; +} + +uint32_t xhdi_inquire_target2(uint16_t major, uint16_t minor, uint32_t *block_size, + uint32_t *device_flags, char *product_name, uint16_t stringlen) +{ + if (major == MY_MAJOR) + { + if (block_size != NULL) *block_size = 512; + if (device_flags != NULL) *device_flags = XH_TARGET_REMOVABLE; + if (product_name != NULL) strncpy(product_name, "BaS SD driver", stringlen); + + return E_OK; + + } + return EUNDEV; +} + +uint32_t xhdi_inquire_device2(uint16_t bios_device, uint16_t *major, uint16_t *minor, + uint32_t *start_sector, BPB *bpb, uint32_t *blocks, char *partid) +{ + + if (bios_device == 'S' - 'A') + { + return E_OK; + } + return EUNDEV; +} + +uint32_t xhdi_driver_special(uint32_t key1, uint32_t key2, uint16_t subopcode, void *data) +{ + return EUNDEV; +} + +uint32_t xhdi_get_capacity(uint16_t major, uint16_t minor, uint32_t *blocks, uint32_t *bs) +{ + if (major == MY_MAJOR) + { + if (blocks != 0) + { + if (disk_ioctl(0, GET_SECTOR_COUNT, blocks) != RES_OK) + { + xprintf("disk_ioctl(0, GET_SECTOR_COUNT, %p) failed at %s:%d\r\n", blocks, __FILE__, __LINE__); + + return ERROR; + } + //xprintf("%s:%d: determined sector count to %ld\r\n", __FILE__, __LINE__, *blocks); + } + + if (bs != 0) + { + if (disk_ioctl(0, GET_SECTOR_SIZE, bs) != RES_OK) + { + xprintf("disk_ioctl(0, GET_SECTOR_SIZE, %p) failed at %s:%dr\n", bs, __FILE__, __LINE__); + + return ERROR; + } + //xprintf("%s:%d: determined sector size to %ld\r\n", __FILE__, __LINE__, *bs); + } + return E_OK; + } + return EUNDEV; +} + +uint32_t xhdi_medium_changed(uint16_t major, uint16_t minor) +{ + if (major == MY_MAJOR) + return 1; /* may have changed */ + + return EUNDEV; +} + +uint32_t xhdi_mint_info(uint16_t opcode, void *data) +{ + return EUNDEV; +} + +uint32_t xhdi_dos_limits(uint16_t which, uint32_t limit) +{ + return EUNDEV; +} + +uint32_t xhdi_last_access(uint16_t major, uint16_t minor, uint32_t *ms) +{ + return EUNDEV; +} + +uint32_t xhdi_reaccess(uint16_t major, uint16_t minor) +{ + return EUNDEV; +} diff --git a/xhdi/xhdi_vec.S b/xhdi/xhdi_vec.S new file mode 100644 index 0000000..e04c437 --- /dev/null +++ b/xhdi/xhdi_vec.S @@ -0,0 +1,65 @@ +/* + * xhdi_vec.S + * + * XHDI entry point for EmuTOS into BaS' SD-card driver + * + * This file is part of BaS_gcc. + * + * BaS_gcc is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * BaS_gcc is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with BaS_gcc. If not, see . + * + * Created on: 26.02.2013 + * Author: Markus Fröschle + */ + +// +// XHDI entry point +// + .extern _xhdi_call + + .globl _xhdi_vec + .globl _xhdi_sd_install + +// +// this is where the XHDI cookie points to: +// + + .text + .byte 'B','A','S','_' +_xhdi_vec: + lea -12(sp),sp // save all used registers according to XHDI spec + movem.l d1/a0-a1,(sp) + + pea 16(sp) // forward address of parameters on stack + jsr _xhdi_call // to internal routine + addq.l #4,sp // correct stack + + movem.l (sp),d1/a0-a1 // restore registers + lea 12(sp),sp + rts + + .bss +_old_vector: + .long 1 + + .text + +// +// trap #0 handler to bring the address of the disk routines into TOS +// +_xhdi_sd_install: + move.l 4(sp),d0 // address of the old XHDI vector + move.l d0,_old_vector // save it - just in case we need it later + move.l #_xhdi_vec,d0 // return our BaS vector to TOS + move.l d0,a0 // + rte