add missing files not taken with github import
This commit is contained in:
Markus Fröschle
491
tos/fpga_test/sources/fpga_test.c
Normal file
491
tos/fpga_test/sources/fpga_test.c
Normal file
@@ -0,0 +1,491 @@
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#include <stdio.h>
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#include <mint/osbind.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "bas_printf.h"
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#include "MCF5475.h"
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#include "driver_vec.h"
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#define FPGA_CONFIG (1 << 2)
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#define FPGA_CONF_DONE (1 << 5)
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#define SRAM1_START 0xff101000
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#define SRAM1_END SRAM1_START + 0x1000
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#define SAFE_STACK SRAM1_END - 4
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#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory")
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#define SYSCLK 132000
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long bas_start = 0xe0000000;
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volatile uint16_t *FB_CS1 = (volatile uint16_t *) 0xfff00000; /* "classic" ATARI I/O registers */
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volatile uint32_t *FB_CS2 = (volatile uint32_t *) 0xf0000000; /* FireBee 32 bit I/O registers */
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volatile uint16_t *FB_CS3 = (volatile uint16_t *) 0xf8000000; /* FireBee SRAM */
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volatile uint32_t *FB_CS4 = (uint32_t *) 0x40000000; /* FireBee SD RAM */
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const long sdram_size = 128 * 1024L * 1024L;
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static void init_ddr_ram(void)
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{
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xprintf("init video RAM: ");
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FB_CS2[0x100] = 0xb; /* set cke = 1, cs=1, config = 1 */
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NOP();
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FB_CS4[0] = 0x00050400; /* IPALL */
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NOP();
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FB_CS4[0] = 0x00072000; /* load EMR pll on */
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NOP();
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FB_CS4[0] = 0x00070122; /* load MR: reset pll, cl=2, burst=4lw */
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NOP();
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FB_CS4[0] = 0x00050400; /* IPALL */
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NOP();
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FB_CS4[0] = 0x00060000; /* auto refresh */
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NOP();
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FB_CS4[0] = 0x00060000; /* auto refresh */
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NOP();
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/* FIXME: what's this? */
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FB_CS4[0] = 0000070022; /* load MR dll on */
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NOP();
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FB_CS2[0x100] = 0x01070082; /* fifo on, refresh on, ddrcs und cke on, video dac on, Falcon shift mode on */
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xprintf("finished\r\n");
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}
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bool verify_ddr_ram(uint32_t value)
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{
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volatile uint32_t *lp;
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volatile uint16_t *wp;
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uint32_t rl;
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uint16_t rw;
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lp = FB_CS4;
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/*
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* write/read longs
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*/
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lp = FB_CS4;
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do
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{
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*lp = value;
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xprintf("W: 0x%08x R: 0x%08x\r", value, rl = *lp);
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if (rl != value)
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{
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xprintf("\nvalidation error at %p: written = 0x%08x, read = 0x%08x\r\n", lp, value, rl);
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return false;
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}
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} while (lp++ <= FB_CS4 + sdram_size - 1);
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wp = (uint16_t *) FB_CS4;
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/*
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* write/read words
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*/
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wp = (uint16_t *) FB_CS4;
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do
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{
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*wp = (uint16_t) value;
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xprintf("W: 0x%04x R: 0x%04x\r", value, rw = *wp);
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if (rw != value)
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{
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xprintf("\nvalidation error at %p: written = 0x%04x, read = 0x%04x\r\n", wp, value, rw);
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return false;
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}
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} while (wp++ <= (uint16_t *) FB_CS4 + sdram_size - 1);
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return true;
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}
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bool verify_longaddr(volatile uint32_t * const addr, uint32_t value)
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{
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*addr = value;
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xprintf("W: 0x%08x R: 0x%08x\r", value, *addr);
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if (value != *addr)
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{
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xprintf("validation error at %p: written = 0x%08x, read = 0x%08x\r\n", addr, value, *addr);
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xprintf("\r\n");
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return false;
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}
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return true;
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}
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bool verify_long(volatile uint32_t * const addr, uint32_t low_value, uint32_t high_value)
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{
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uint32_t i;
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for (i = low_value; i <= high_value; i++)
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if (verify_longaddr(addr, i) == false)
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{
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xprintf("verify of %p failed: 0x%08x written, 0x%08x read\r\n",
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addr, i, *addr);
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return false;
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}
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return true;
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}
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void firebee_io_test(void)
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{
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volatile uint32_t *ACP_VCTR = &FB_CS2[0x100]; /* 0xf000400 */
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volatile uint32_t *CCR = &FB_CS2[0x101]; /* 0xf000401 - FireBee mode border color */
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volatile uint32_t *ATARI_HH = &FB_CS2[0x104]; /* 0xf000410 */
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volatile uint32_t *ATARI_VH = &FB_CS2[0x105]; /* 0xf000414 */
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volatile uint32_t *ATARI_HL = &FB_CS2[0x106]; /* 0xf000418 */
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volatile uint32_t *ATARI_VL = &FB_CS2[0x107]; /* 0xf00041c */
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volatile uint32_t *VIDEO_PLL_CONFIG = &FB_CS2[0x180]; /* 0xf000600 */
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volatile uint32_t *VIDEO_PLL_RECONFIG = &FB_CS2[0x200]; /* 0xf000800 */
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xprintf("verify ACP_VCTR register\r\n");
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verify_long(ACP_VCTR, 0, 0x1ff);
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xprintf("verify CCR register\r\n");
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verify_long(CCR, 0, 0x1ff);
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xprintf("verify ATARI_HH register\r\n");
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verify_long(ATARI_HH, 0, 0x1ff);
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xprintf("verify ATARI_VH register\r\n");
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verify_long(ATARI_VH, 0, 0x1ff);
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xprintf("verify ATARI_HL register\r\n");
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verify_long(ATARI_HL, 0, 0x1ff);
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xprintf("verify ATARI_VL register\r\n");
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verify_long(ATARI_VL, 0, 0x1ff);
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xprintf("verify VIDEO_PLL_CONFIG register\r\n");
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verify_long(VIDEO_PLL_CONFIG, 0, 0x1ff);
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xprintf("verify VIDEO_PLL_RECONFIG register\r\n");
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verify_long(VIDEO_PLL_RECONFIG, 0, 0x1ff);
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}
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bool verify_wordaddr(volatile uint16_t * const addr, uint16_t value)
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{
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long rvalue;
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*addr = value;
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if (value != (rvalue = *addr))
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{
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xprintf("validation error at %p, wrote 0x%04x, read 0x%04x\r\n", addr, value, rvalue);
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xprintf("\r\n");
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return false;
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}
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return true;
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}
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bool verify_word(volatile uint16_t * const addr, uint16_t low_value, uint16_t high_value)
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{
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uint16_t i;
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for (i = low_value; i <= high_value; i++)
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if (verify_wordaddr(addr, i) == false)
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{
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xprintf("verify of %p failed: 0x%04x written, 0x%04x read\r\n",
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addr, i, *addr);
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return false;
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}
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return true;
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}
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bool verify_byteaddr(volatile uint8_t * const addr, uint8_t value)
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{
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uint8_t rvalue;
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*addr = value;
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if (value != (rvalue = *addr))
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{
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xprintf("validation error at %p, wrote 0x%02x, read 0x%02x\r\n", addr, value, rvalue);
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xprintf("\r\n");
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return false;
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}
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return true;
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}
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bool verify_byte(volatile uint8_t * const addr, uint8_t low_value, uint8_t high_value)
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{
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int8_t i;
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for (i = low_value; i <= high_value; i++)
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if (verify_byteaddr(addr, i) == false)
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{
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xprintf("verify of %p failed: 0x%02x written, 0x%02x read\r\n",
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addr, i, *addr);
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return false;
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}
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return true;
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}
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void falcon_io_test(void)
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{
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int i;
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volatile uint16_t *SYS_CTR = &FB_CS1[0x7c003]; /* 0xffff8006 */
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volatile uint8_t *VIDEO_ADR_HI = ((volatile uint8_t *) &FB_CS1[0x7c100]) + 1; /* 0xffff8201 */
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volatile uint8_t *VIDEO_ADR_MI = ((volatile uint8_t *) &FB_CS1[0x7c101]) + 1; /* 0xffff8203 */
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volatile uint8_t *VIDEO_ADR_LO = ((volatile uint8_t *) &FB_CS1[0x7c106]) + 1; /* 0xffff820d */
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volatile uint8_t *VIDEO_CNT_HI = ((volatile uint8_t *) &FB_CS1[0x7c102]) + 1; /* 0xffff8205 */
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volatile uint8_t *VIDEO_CNT_MI = ((volatile uint8_t *) &FB_CS1[0x7c103]) + 1; /* 0xffff8207 */
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volatile uint8_t *VIDEO_CNT_LO = ((volatile uint8_t *) &FB_CS1[0x7c104]) + 1; /* 0xffff8209 */
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volatile uint8_t *SYNC_MODE = ((volatile uint8_t *) &FB_CS1[0x7c105]) + 1; /* 0xffff8006 */
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volatile uint16_t *VDL_LOF = &FB_CS1[0x7c107]; /* 0xffff820e */
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volatile uint16_t *VDL_LWD = &FB_CS1[0x7c108]; /* 0xffff8210 */
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volatile uint16_t *VDL_HHT = &FB_CS1[0x7c141]; /* 0xffff8282 */
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volatile uint16_t *VDL_HBB = &FB_CS1[0x7c142]; /* 0xffff8284 */
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volatile uint16_t *VDL_HBE = &FB_CS1[0x7c143]; /* 0xffff8286 */
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volatile uint16_t *VDL_HDB = &FB_CS1[0x7c144]; /* 0xffff8288 */
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volatile uint16_t *VDL_HDE = &FB_CS1[0x7c145]; /* 0xffff828a */
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volatile uint16_t *VDL_HSS = &FB_CS1[0x7c146]; /* 0xffff828c */
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volatile uint16_t *VDL_VFT = &FB_CS1[0x7c151]; /* 0xffff82a2 */
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volatile uint16_t *VDL_VBB = &FB_CS1[0x7c152]; /* 0xffff82a4 */
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volatile uint16_t *VDL_VBE = &FB_CS1[0x7c153]; /* 0xffff82a6 */
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volatile uint16_t *VDL_VDB = &FB_CS1[0x7c154]; /* 0xffff82a8 */
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volatile uint16_t *VDL_VDE = &FB_CS1[0x7c155]; /* 0xffff82aa */
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volatile uint16_t *VDL_VSS = &FB_CS1[0x7c156]; /* 0xffff82ac */
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volatile uint16_t *VDL_VCT = &FB_CS1[0x7c160]; /* 0xffff82c0 */
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volatile uint16_t *VDL_VMD = &FB_CS1[0x7c161]; /* 0xffff82c2 */
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/* ST palette registers */
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volatile uint8_t *st_palette = (volatile uint8_t *) &FB_CS1[0x7c120]; /* 0xffff8240 */
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/* Falcon palette registers */
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volatile uint8_t *falcon_palette = (volatile uint8_t *) &FB_CS1[0x7cc00]; /* 0xffff9800 */
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xprintf("verify VIDEO_ADR_XX registers\r\n");
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verify_byte(VIDEO_ADR_HI, 0x00, 0xff);
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verify_byte(VIDEO_ADR_MI, 0x00, 0xff);
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verify_byte(VIDEO_ADR_LO, 0x00, 0xff);
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xprintf("verify VIDEO_CNT_XX registers\r\n");
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verify_byte(VIDEO_CNT_HI, 0x00, 0xff);
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verify_byte(VIDEO_CNT_MI, 0x00, 0xff);
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verify_byte(VIDEO_CNT_LO, 0x00, 0xff);
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xprintf("verify SYNC_MODE register\r\n");
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verify_byte(SYNC_MODE, 0x00, 0xff);
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xprintf("verify SYS_CTR register\r\n");
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verify_word(SYS_CTR, 0, 0x1ff);
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for (i = 0; i < 16 * 2; i += 2)
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{
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xprintf("verify ST palette register %d\r\n", i / 2);
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verify_byte(&st_palette[i], i / 2, i / 2);
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verify_byte(&st_palette[i], i / 2, i / 2); /* do two consecutive tests here because of RAM latency */
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}
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for (i = 0; i < 255 * 2; i += 2)
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{
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xprintf("verify Falcon palette register %d\r\n", i / 2);
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verify_byte(&falcon_palette[i], i / 2, i / 2);
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verify_byte(&falcon_palette[i], i / 2, i / 2); /* do two consecutive tests here because of FPGA RAM latency */
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}
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xprintf("verify LOF register\r\n");
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verify_word(VDL_LOF, 0, 0x1ff);
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xprintf("verify LWD register \r\n");
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verify_word(VDL_LWD, 0, 0x1ff);
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xprintf("verify HHT register\r\n");
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verify_word(VDL_HHT, 0, 0x1ff);
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xprintf("verify HBB register\r\n");
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verify_word(VDL_HBB, 0, 0x1ff);
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xprintf("verify HBE register\r\n");
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verify_word(VDL_HBE, 0, 0x1ff);
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xprintf("verify HDB register\r\n");
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verify_word(VDL_HDB, 0, 0x1ff);
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xprintf("verify HDE register\r\n");
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verify_word(VDL_HDE, 0, 0x1ff);
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xprintf("verify HSS register\r\n");
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verify_word(VDL_HSS, 0, 0x1ff);
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xprintf("verify VFT register\r\n");
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verify_word(VDL_VFT, 0, 0x1ff);
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xprintf("verify VBB register\r\n");
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verify_word(VDL_VBB, 0, 0x1ff);
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xprintf("verify VBE register\r\n");
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verify_word(VDL_VBE, 0, 0x1ff);
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xprintf("verify VDB register\r\n");
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verify_word(VDL_VDB, 0, 0x1ff);
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xprintf("verify VDE register\r\n");
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verify_word(VDL_VDE, 0, 0x1ff);
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xprintf("verify VSS register\r\n");
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verify_word(VDL_VSS, 0, 0x1ff);
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xprintf("verify VCT register\r\n");
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verify_word(VDL_VCT, 0, 0x1ff);
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xprintf("verify VMD register\r\n");
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verify_word(VDL_VMD, 0, 0x1ff);
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}
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void do_tests(void)
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{
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xprintf("start tests:\r\n");
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xprintf("Falcon I/O test\r\n");
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falcon_io_test();
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xprintf("FireBee I/O test\r\n");
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firebee_io_test();
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init_ddr_ram();
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verify_ddr_ram(0xaaaaaaaa);
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verify_ddr_ram(0x55555555);
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}
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void wait_for_jtag(void)
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{
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long i;
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/* set supervisor stack to end of SRAM1 */
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__asm__ __volatile__ (
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" move #0x2700,sr\n\t" /* disable interrupts */
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" move.l %[stack],d0\n\t" /* 4KB on-chip core SRAM1 */
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" move.l d0,sp\n\t" /* set stack pointer */
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:
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: [stack] "i" (SAFE_STACK)
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: "d0", "cc" /* clobber */
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);
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MCF_EPORT_EPIER = 0x0; /* disable EPORT interrupts */
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MCF_INTC_IMRL = 0xffffffff;
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MCF_INTC_IMRH = 0xffffffff; /* disable interrupt controller */
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MCF_MMU_MMUCR &= ~MCF_MMU_MMUCR_EN; /* disable MMU */
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xprintf("relocated supervisor stack, disabled interrupts and disabled MMU\r\n");
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/*
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* configure FEC1L port directions to enable external JTAG configuration download to FPGA
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*/
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MCF_GPIO_PDDR_FEC1L = 0 |
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MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4; /* bit 4 = LED => output */
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/* all other bits = input */
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/*
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* configure DSPI_CS3 as GPIO input to avoid the MCU driving against the FPGA blink
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*/
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MCF_PAD_PAR_DSPI &= ~MCF_PAD_PAR_DSPI_PAR_CS3(MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3);
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/*
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* now that GPIO ports have been switched to input, we can poll for FPGA config
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* started from the JTAG interface (CONF_DONE goes low) and finish (CONF_DONE goes high)
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*/
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xprintf("waiting for JTAG configuration start\r\n");
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while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load started */
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xprintf("waiting for JTAG configuration to finish\r\n");
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while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load finished */
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xprintf("JTAG configuration finished.\r\n");
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/* wait */
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xprintf("wait a little to let things settle...\r\n");
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for (i = 0; i < 100000L; i++);
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||||
|
||||
xprintf("disable caches\r\n");
|
||||
__asm__ __volatile(
|
||||
"move.l #0x01000000,d0 \r\n"
|
||||
"movec d0,CACR \r\n"
|
||||
: /* no output */
|
||||
: /* no input */
|
||||
: "d0", "memory");
|
||||
|
||||
/* begin of tests */
|
||||
|
||||
do_tests();
|
||||
|
||||
xprintf("wait a little to let things settle...\r\n");
|
||||
for (i = 0; i < 100000L; i++);
|
||||
|
||||
xprintf("INFO: endless loop now. Press reset to reboot\r\n");
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
printf("FPGA JTAG configuration support\r\n");
|
||||
printf("test FPGA DDR RAM controller\r\n");
|
||||
printf("\xbd 2014 M. Fr\x94schle\r\n");
|
||||
|
||||
printf("You may now savely load a new FPGA configuration through the JTAG interface\r\n"
|
||||
"and your FireBee will reboot once finished using that new configuration.\r\n");
|
||||
if (argc == 2)
|
||||
{
|
||||
/*
|
||||
* we got an argument. This is supposed to be the address that we need to jump to after JTAG
|
||||
* configuration has been finished. Meant to support BaS in RAM testing
|
||||
*/
|
||||
char *addr_str = argv[1];
|
||||
char *addr = NULL;
|
||||
char *end = NULL;
|
||||
|
||||
addr = (char *) strtol(addr_str, &end, 16);
|
||||
if (addr != NULL && addr <= (char *) 0xe0000000 && addr >= (char *) 0x10000000)
|
||||
{
|
||||
/*
|
||||
* seems to be a valid address
|
||||
*/
|
||||
bas_start = (long) addr;
|
||||
|
||||
printf("BaS start address set to %p\r\n", (void *) bas_start);
|
||||
}
|
||||
else
|
||||
{
|
||||
printf("\r\nNote: BaS start address %p not valid. Stick to %p.\r\n", addr, (void *) bas_start);
|
||||
}
|
||||
}
|
||||
Supexec(wait_for_jtag);
|
||||
|
||||
return 0; /* just to make the compiler happy, we will never return */
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user