add missing files not taken with github import
This commit is contained in:
Markus Fröschle
1174
pci/ehci-hcd.c
Normal file
1174
pci/ehci-hcd.c
Normal file
File diff suppressed because it is too large
Load Diff
2380
pci/ohci-hcd.c
Normal file
2380
pci/ohci-hcd.c
Normal file
File diff suppressed because it is too large
Load Diff
66
pci/pci_errata.c
Executable file
66
pci/pci_errata.c
Executable file
@@ -0,0 +1,66 @@
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#include "pci_errata.h"
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#include "pci.h"
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#include <MCF5475.h>
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#include "debug.h"
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__attribute__((aligned(16))) void chip_errata_135(void)
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{
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/*
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* Errata type: Silicon
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* Affected component: PCI
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* Description: When core PCI transactions that involve writes to configuration or I/O space
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* are followed by a core line access to line addresses 0x4 and 0xC, core access
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* to the XL bus can hang.
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* Workaround: Prevent PCI configuration and I/O writes from being followed by the described
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* line access by the core by generating a known good XL bus transaction after
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* the PCI transaction.
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* Create a dummy function which is called immediately after each of the affected
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* transactions. There are three requirements for this dummy function.
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* 1. The function must be aligned to a 16-byte boundary.
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* 2. The function must contain a dummy write to a location on the XL bus,
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* preferably one with no side effects.
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* 3. The function must be longer than 32 bytes. If it is not, the function should
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* be padded with 16- or 48-bit TPF instructions placed after the end of
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* the function (after the RTS instruction) such that the length is longer
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* than 32 bytes.
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*/
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__asm__ __volatile(
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" .extern __MBAR \n\t"
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" clr.l d0 \n\t"
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" move.l d0,__MBAR+0xF0C \n\t" /* Must use direct addressing. write to EPORT module */
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/* xlbus -> slavebus -> eport, writing '0' to register */
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/* has no effect */
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" rts \n\t"
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" tpf.l #0x0 \n\t"
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" tpf.l #0x0 \n\t"
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" tpf.l #0x0 \n\t"
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" tpf.l #0x0 \n\t"
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" tpf.l #0x0 \n\t"
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::: "d0", "memory");
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}
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void chip_errata_055(int32_t handle)
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{
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uint32_t dummy;
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return; /* test */
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/* initiate PCI configuration access to device */
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MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */
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MCF_PCI_PCICAR_BUSNUM(3) | /* note: invalid bus number */
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MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | /* device number, devices 0 - 9 are reserved */
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MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | /* function number */
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MCF_PCI_PCICAR_DWORD(0);
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/* issue a dummy read to an unsupported bus number (will fail) */
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dummy = * (volatile uint32_t *) PCI_IO_OFFSET; /* access device */
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/* silently clear the PCI errors we produced just now */
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MCF_PCI_PCIISR = 0xffffffff; /* clear all errors */
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MCF_PCI_PCIGSCR = MCF_PCI_PCIGSCR_PE | MCF_PCI_PCIGSCR_SE;
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(void) dummy;
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}
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469
pci/pci_wrappers.S
Normal file
469
pci/pci_wrappers.S
Normal file
@@ -0,0 +1,469 @@
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/*
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* pci.S
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*
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* Purpose: PCI configuration for the Coldfire builtin PCI bridge.
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*
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* Notes:
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*
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* This file is part of BaS_gcc.
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*
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* BaS_gcc is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* BaS_gcc is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
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*
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* Created on: 08.05.2014
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* Author: David Galvez
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*/
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.global _wrapper_find_pci_device
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.global _wrapper_find_pci_classcode
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.global _wrapper_read_config_longword
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.global _wrapper_read_config_word
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.global _wrapper_read_config_byte
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.global _wrapper_fast_read_config_byte
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.global _wrapper_fast_read_config_word
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.global _wrapper_fast_read_config_longword
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.global _wrapper_write_config_longword
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.global _wrapper_write_config_word
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.global _wrapper_write_config_byte
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.global _wrapper_get_resource
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.global _wrapper_hook_interrupt
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.global _wrapper_unhook_interrupt
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.global _wrapper_special_cycle
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.global _wrapper_get_routing
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.global _wrapper_set_interrupt
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.global _wrapper_get_resource
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.global _wrapper_get_card_used
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.global _wrapper_set_card_used
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.global _wrapper_read_mem_byte
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.global _wrapper_read_mem_word
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.global _wrapper_read_mem_longword
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.global _wrapper_fast_read_mem_byte
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.global _wrapper_fast_read_mem_word
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.global _wrapper_fast_read_mem_longword
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.global _wrapper_write_mem_byte
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.global _wrapper_write_mem_word
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.global _wrapper_write_mem_longword
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.global _wrapper_read_io_byte
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.global _wrapper_read_io_word
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.global _wrapper_read_io_longword
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.global _wrapper_fast_read_io_byte
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.global _wrapper_fast_read_io_word
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.global _wrapper_fast_read_io_longword
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.global _wrapper_write_io_byte
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.global _wrapper_write_io_word
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.global _wrapper_write_io_longword
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.global _wrapper_get_machine_id
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.global _wrapper_get_pagesize
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.global _wrapper_virt_to_bus
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.global _wrapper_bus_to_virt
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.global _wrapper_virt_to_phys
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.global _wrapper_phys_to_virt
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_wrapper_find_pci_device:
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move.l D1,-(SP) // index
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move.l D0,-(SP) // Vendor ID
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move.l #16,D1
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lsr.l D1,D0
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move.l D0,-(SP) // Device ID
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jsr _pci_find_device
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add.l #12,SP
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rts
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_wrapper_find_pci_classcode:
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move.l D1,-(SP) // index
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move.l D0,-(SP) // ID
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jsr _pci_find_classcode
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addq.l #8,SP
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rts
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_wrapper_read_config_byte:
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move.l A0,-(SP) // pointer to space for read data
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move.l D1,-(SP) // PCI register
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move.l D0,-(SP) // handle
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jsr _pci_read_config_byte
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move.l 8(SP),A0 // PCI_BIOS expects value in memory
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move.l D0,(A0)
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add.l #12,SP
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move.l #0,D0
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rts
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_wrapper_read_config_word:
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move.l A0,-(SP) // pointer to space for read data
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move.l D1,-(SP) // PCI register
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move.l D0,-(SP) // handle
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jsr _pci_read_config_word
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move.l 8(SP),A0 // little to big endian
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move.l D0,(A0)
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mvz.b 1(A0),D0
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lsl.l #8,D0
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move.b (A0),D0
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move.l D0,(A0) // PCI_BIOS expects value in memory, not in D0
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add.l #12,SP
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move.l #0,D0
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rts
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_wrapper_read_config_longword:
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move.l A0,-(SP) // pointer to space for read data
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move.l D1,-(SP) // PCI register
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move.l D0,-(SP) // handle
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jsr _pci_read_config_longword
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move.l 8(SP),A0 // little to big endian
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move.l D0,(A0)
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mvz.b 3(A0),D0
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lsl.l #8,D0
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move.b 2(A0),D0
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lsl.l #8,D0
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move.b 1(A0),D0
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lsl.l #8,D0
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move.b (A0),D0
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move.l D0,(A0) // PCI_BIOS expects value in memory, not in D0
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add.l #12,SP
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move.l #0,D0
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rts
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/* Not implemented */
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_wrapper_fast_read_config_byte:
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move.l D1,-(SP) // PCI register
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move.l D0,-(SP) // handle
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jsr _pci_fast_read_config_byte
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addq.l #8,SP
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rts
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/* Not implemented */
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_wrapper_fast_read_config_word:
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move.l D1,-(SP) // PCI register
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move.l D0,-(SP) // handle
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jsr _pci_fast_read_config_word
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addq.l #8,SP
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rts
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/* Not implemented */
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_wrapper_fast_read_config_longword:
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move.l D1,-(SP) // PCI register
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move.l D0,-(SP) // handle
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jsr _pci_fast_read_config_longword
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addq.l #8,SP
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rts
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_wrapper_write_config_byte:
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move.l D2,-(SP) // data to write
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move.l D1,-(SP) // PCI register
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move.l D0,-(SP) // handle
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jsr _pci_write_config_byte
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add.l #12,SP
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rts
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_wrapper_write_config_word:
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move.l D0,-(SP) // make data little endian
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moveq #0,D1
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move.w D2,D1
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lsr.l #8,D1
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asl.l #8,D2
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or.l D1,D2
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move.l (SP)+,D0
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move.l D2,-(SP) // data to write
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move.l D1,-(SP) // PCI register
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move.l D0,-(SP) // handle
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jsr _pci_write_config_word
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add.l #12,SP
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rts
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_wrapper_write_config_longword:
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move.l D0,-(SP)
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move.l D2,D0 // make data little endian
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lsr.l #8,D0
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asl.l #8,D2
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and.l #0x00FF00FF,D0
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and.l #0xFF00FF00,D2
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or.l D0,D2
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swap D2
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move.l (SP)+,D0
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move.l D2,-(SP) // data to write
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move.l D1,-(SP) // PCI register
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move.l D0,-(SP) // handle
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jsr _pci_write_config_longword
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add.l #12,SP
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rts
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_wrapper_hook_interrupt:
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move.l A1,-(SP) // parameter for interrupt handler
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move.l A0,-(SP) // pointer to interrupt handler
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move.l D0,-(SP) // handle
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jsr _pci_hook_interrupt
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add.l #12,SP
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rts
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_wrapper_unhook_interrupt:
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move.l D0,-(SP) // handle
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jsr _pci_unhook_interrupt
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addq.l #4,SP
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rts
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||||
|
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/* Not implemented */
|
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_wrapper_special_cycle:
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move.l D1,-(SP) // special cycle data
|
||||
move.l D0,-(SP) // bus number
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jsr _pci_special_cycle
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addq.l #8,SP
|
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rts
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/* Not implemented */
|
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_wrapper_get_routing:
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move.l D0,-(SP) // handle
|
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jsr _pci_get_routing
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addq.l #4,SP
|
||||
rts
|
||||
|
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/* Not implemented */
|
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_wrapper_set_interrupt:
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move.l D1,-(SP) // mode
|
||||
move.l D0,-(SP) // handle
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jsr _pci_set_interrupt
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addq.l #8,SP
|
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rts
|
||||
|
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_wrapper_get_resource:
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move.l D0,-(SP) // handle
|
||||
jsr _pci_get_resource
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addq.l #4,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_get_card_used:
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move.l D1,-(SP) // address
|
||||
move.l D0,-(SP) // handle
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jsr _pci_get_card_used
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addq.l #8,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_set_card_used:
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move.l A0,-(SP) // callback
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_set_card_used
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addq.l #8,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_read_mem_byte:
|
||||
move.l A0,-(SP) // pointer to data in memory
|
||||
move.l D1,-(SP) // address to access (in PCI memory address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_mem_byte
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_read_mem_word:
|
||||
move.l A0,-(SP) // pointer to data in memory
|
||||
move.l D1,-(SP) // address to access (in PCI memory address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_mem_word
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_read_mem_longword:
|
||||
move.l A0,-(SP) // pointer to data in memory
|
||||
move.l D1,-(SP) // address to access (in PCI memory address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_mem_longword
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_fast_read_mem_byte:
|
||||
move.l D1,-(SP) // address to access (in PCI memory address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_mem_byte
|
||||
addq.l #8,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_fast_read_mem_word:
|
||||
move.l D1,-(SP) // address to access (in PCI memory address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_mem_word
|
||||
addq.l #8,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_fast_read_mem_longword:
|
||||
move.l D1,-(SP) // address to access (in PCI memory address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_mem_longword
|
||||
addq.l #8,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_write_mem_byte:
|
||||
move.l D2,-(SP) // data to write
|
||||
move.l D1,-(SP) // address to access (in PCI memory address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_write_mem_byte
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_write_mem_word:
|
||||
move.l D2,-(SP) // data to write
|
||||
move.l D1,-(SP) // address to access (in PCI memory address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_write_mem_word
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_write_mem_longword:
|
||||
move.l D2,-(SP) // data to write
|
||||
move.l D1,-(SP) // address to access (in PCI memory address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_write_mem_longword
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_read_io_byte:
|
||||
move.l A0,-(SP) // pointer to data in memory
|
||||
move.l D1,-(SP) // address to access (in PCI I/O address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_io_byte
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_read_io_word:
|
||||
move.l A0,-(SP) // pointer to data in memory
|
||||
move.l D1,-(SP) // address to access (in PCI I/O address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_io_word
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_read_io_longword:
|
||||
move.l A0,-(SP) // pointer to data in memory
|
||||
move.l D1,-(SP) // address to access (in PCI I/O address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_io_longword
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_fast_read_io_byte:
|
||||
move.l D1,-(SP) // address to access (in PCI I/O address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_io_byte
|
||||
addq.l #8,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_fast_read_io_word:
|
||||
move.l D1,-(SP) // address to access (in PCI I/O address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_io_word
|
||||
addq.l #8,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_fast_read_io_longword:
|
||||
move.l D1,-(SP) // address to access (in PCI I/O address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_read_io_longword
|
||||
addq.l #8,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_write_io_byte:
|
||||
move.l D2,-(SP) // data to write
|
||||
move.l D1,-(SP) // address to access (in PCI I/O address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_write_io_byte
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_write_io_word:
|
||||
move.l D2,-(SP) // data to write
|
||||
move.l D1,-(SP) // address to access (in PCI I/O address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_write_io_word
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_write_io_longword:
|
||||
move.l D2,-(SP) // data to write
|
||||
move.l D1,-(SP) // address to access (in PCI I/O address space)
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_write_io_longword
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_get_machine_id:
|
||||
jsr _pci_get_machine_id
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_get_pagesize:
|
||||
jsr _pci_get_pagesize
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_virt_to_bus:
|
||||
move.l A0,-(SP) // ptr
|
||||
move.l D1,-(SP) // address in virtual CPU space
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_virt_to_bus
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_bus_to_virt:
|
||||
move.l A0,-(SP) // ptr
|
||||
move.l D1,-(SP) // PCI bus address
|
||||
move.l D0,-(SP) // handle
|
||||
jsr _pci_bus_to_virt
|
||||
add.l #12,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_virt_to_phys:
|
||||
move.l A0,-(SP) // ptr
|
||||
move.l D0,-(SP) // address in virtual CPU space
|
||||
jsr _pci_virt_to_phys
|
||||
addq.l #8,SP
|
||||
rts
|
||||
|
||||
/* Not implemented */
|
||||
_wrapper_phys_to_virt:
|
||||
move.l A0,-(SP) // ptr
|
||||
move.l D0,-(SP) // physical CPU address
|
||||
jsr _pci_phys_to_virt
|
||||
addq.l #8,SP
|
||||
rts
|
||||
Reference in New Issue
Block a user