Markus Fröschle bb0f702a45 reformatted, forced tighter timing ...

Config works, but screen is still scrambled

2015-09-20 17:13:10 +00:00

FPGA_Quartus_13.1

reformatted, forced tighter timing

2015-09-20 17:13:10 +00:00

Description

No description provided

10 MiB

Languages

VHDL 83.4%

Verilog 13.1%

PHP 2.1%

Tcl 0.6%

Assembly 0.4%

Other 0.4%