forked from Firebee/FPGA_Config
7e2181fbc9
Design compiles and runs, but still has issues with different screen resolutions and video clocks
241 lines
9.9 KiB
Tcl
241 lines
9.9 KiB
Tcl
## Generated SDC file "firebee1.sdc"
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## Copyright (C) 1991-2014 Altera Corporation
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## Your use of Altera Corporation's design tools, logic functions
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## and other software and tools, and its AMPP partner logic
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## functions, and any output files from any of the foregoing
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## (including device programming or simulation files), and any
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## associated documentation or information are expressly subject
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## to the terms and conditions of the Altera Program License
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## Subscription Agreement, Altera MegaCore Function License
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## Agreement, or other applicable license agreement, including,
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## without limitation, that your use is for the sole purpose of
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## programming logic devices manufactured by Altera and sold by
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## Altera or its authorized distributors. Please refer to the
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## applicable agreement for further details.
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## VENDOR "Altera"
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## PROGRAM "Quartus II"
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## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
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## DATE "Mon Sep 21 20:39:03 2015"
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##
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## DEVICE "EP3C40F484C6"
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##
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#**************************************************************
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# Time Information
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#**************************************************************
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set_time_format -unit ns -decimal_places 3
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#**************************************************************
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# Create Clock
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#**************************************************************
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create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_ports {MAIN_CLK}]
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# Clocks used:
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# MAIN_CLK 33MHz
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#
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# PLL1: i_mfp_acia_clk_pll
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# input: MAIN_CLK
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# c0: 500 kHz
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# c1: 2.4576 MHz
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# c2: 24.576 MHz
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#
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# PLL2: i_ddr_clock_pll
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# input: MAIN_CLK
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# c0: 132 MHz
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# c1: 132 MHz
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# c2: 132 MHz
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# c3: 132 MHz
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# c4: 66 MHz
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#
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# PLL3: i_atari_clk_pll
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# input: MAIN_CLK
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# c0: 2 MHz
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# c1: 16 MHz
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# c2: 25 MHz
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# c3: 48 MHz
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#
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# PLL4_ i_video_clk_pll
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# input: USB_CLK (48 MHz, PLL3 c3)
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# c0: 96 MHz, programmable in 1MHz steps
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#
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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derive_pll_clocks
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# PIXEL_CLK is either
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# CLK13M, CLK17M, CLK25M, CLK33M or CLK_VIDEO
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# where CLK13M is half of CLK25M,
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# CLK17M is half of CLK33M and CLK_VIDEO is the freely programmable
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# clock of i_video_clk_pll
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#
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 2.00
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set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 2.00
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derive_clock_uncertainty
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] 1.000 [get_ports {FB_AD[0]}]
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] 1.000 [get_ports {FB_AD[0]}]
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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#**************************************************************
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# Set False Path
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#**************************************************************
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#
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# i_videl_clk is freely programmable
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#
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set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
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# MAIN_CLK to 16 MHz clk -> false_path
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set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
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set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]
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# MAIN_CLK to DDR clk and v.v.
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set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
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set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
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set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}]
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set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}]
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set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
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set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
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set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
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set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}]
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# 2 MHz to 33 MHz
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set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
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# 16 MHz to 33 MHz
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set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}]
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set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
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# 25 MHz to 33 MHz
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set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {MAIN_CLK}]
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set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]
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set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
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set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
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set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]
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set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
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set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
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set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
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set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}]
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set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}]
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set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}]
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set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*}]
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set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe19|dffe20a*}]
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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# Clocks used:
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# MAIN_CLK 33MHz
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#
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# PLL1: i_mfp_acia_clk_pll
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# input: MAIN_CLK
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# c0: 500 kHz
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# c1: 2.4576 MHz
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# c2: 24.576 MHz
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#
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# PLL2: i_ddr_clock_pll
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# input: MAIN_CLK
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# c0: 132 MHz
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# c1: 132 MHz
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# c2: 132 MHz
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# c3: 132 MHz
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# c4: 66 MHz
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#
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# PLL3: i_atari_clk_pll
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# input: MAIN_CLK
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# c0: 2 MHz
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# c1: 16 MHz
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# c2: 25 MHz
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# c3: 48 MHz
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#
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# PLL4_ i_video_clk_pll
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# input: USB_CLK (48 MHz, PLL3 c3)
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# c0: 96 MHz, programmable in 1MHz steps
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# 66 MHz to 33 MHz
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set_multicycle_path -setup -start -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 2
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set_multicycle_path -hold -start -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 2
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# 33 MHz to 66 MHz
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set_multicycle_path -setup -end -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2
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set_multicycle_path -hold -end -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2
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# 132 MHz to 33 MHz
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set_multicycle_path -setup -end -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 4
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set_multicycle_path -hold -end -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 4
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# 33 MHz to 132 MHz
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set_multicycle_path -setup -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 4
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set_multicycle_path -hold -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 4
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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# from here to the end of the file statements are just an experiment
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#set_max_delay 25 -from [get_ports {*}]
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#set_min_delay 0.5 -from [get_ports {*}]
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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#set_input_delay -max -clock [get_clocks {MAIN_CLK}] [get_pins {*}] 25
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#set_input_delay -min -clock [get_clocks {MAIN_CLK}] [get_pins {*}] .5
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#set_output_delay -max -clock [get_clocks {MAIN_CLK}] [get_pins {*}] 25
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#set_output_delay -min -clock [get_clocks {MAIN_CLK}] [get_pins {*}] .5
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